diff --git a/Common/sim/compile_unisim.do b/Common/sim/compile_unisim.do index 4aec199..303a370 100644 --- a/Common/sim/compile_unisim.do +++ b/Common/sim/compile_unisim.do @@ -1,8 +1,6 @@ vlib unisim -set XILINX $env(XILINX) - -vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_vpkg.vhd -vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_vcomp.vhd -vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_smodel.vhd -vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_vital.vhd +vcom -93 -work unisim xilinx/libsrc/unisims/unisim_vpkg.vhd +vcom -93 -work unisim xilinx/libsrc/unisims/unisim_vcomp.vhd +vcom -93 -work unisim xilinx/libsrc/unisims/unisim_smodel.vhd +vcom -93 -work unisim xilinx/libsrc/unisims/unisim_vital.vhd diff --git a/Common/sim/xilinx/libsrc/unisims/unisim_SECUREIP.vhd b/Common/sim/xilinx/libsrc/unisims/unisim_SECUREIP.vhd new file mode 100644 index 0000000..3457b60 --- /dev/null +++ b/Common/sim/xilinx/libsrc/unisims/unisim_SECUREIP.vhd @@ -0,0 +1,66369 @@ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2006 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Multi-Gigabit Transceiver +-- /___/ /\ Filename : gtp_dual.vhd +-- \ \ / \ Timestamp : Thu Dec 8 2005 +-- \___\/\___\ +-- +-- Revision: +-- 12/08/05 - Initial version. +-- 01/09/06 - Added architecture +-- 01/27/06 - Updated ONE_UI[10:0] to ONE_UI[31:0] +-- CR#22431 - Remove GSR pin +-- 02/23/06 - Updated Header +-- 03/29/06 - CR#226744 - Fixed output connectivity. +-- 03/29/06 - CR#225541 - Updated GTP_DUAL smartmodel version to 0.006 for following updates +-- - GTP_DUAL smartmodel not generating DO output on the DRP port properly +-- - Renamed some of the ports. +-- - Removed some of the attributes. +-- - Renamed some of the attributes. +-- 04/24/06 - CR#230306 - CLKIN => REFCLKOUT delay added +-- 04/27/06 - CR#230648 - REFCLKOUT removed from wait on +-- - CR#230642 - Spreadsheet updates for I.31 +-- 05/22/06 - CR#231412 - SIM_RECEIVER_DETECT_PASS0/1 attributes added +-- 05/23/06 - CR#231962 - Add buffers for connectivity +-- 10/26/06 - - replaced ZERO_DELAY with CLK_DELAY to be consistent with writers (PPC440 update) +-- - PBS_ERR_THRESHOLD_0 default value X"11111111" to X"00000001 +-- 05/23/07 - CR#439780 - Default attribute value change - PMA_CDR_SCAN0/1, PMA_RX_CFG_0/1, TX_DIFF_BOOST_0/1 +-- - PCS_COM_CFG is a user visible attribute +-- 05/23/07 - CR#440008 - Specify block timing update - RXCHBONDO0/1 synchronous to RXUSRCLK0, RXCHBONDI0/1 synchronous to RXUSRCLK1 +-- 02/21/08 - CR#467686 - Add SIM_MODE attribute with values LEGACY & FAST model +-- 06/24/08 - CR472608, CR472665 - Update SIM_MODE default to FAST +-- End Revision + +----- CELL GTP_DUAL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +library secureip; +use secureip.all; + +entity GTP_DUAL is +generic ( + AC_CAP_DIS_0 : boolean := TRUE; + AC_CAP_DIS_1 : boolean := TRUE; + ALIGN_COMMA_WORD_0 : integer := 1; + ALIGN_COMMA_WORD_1 : integer := 1; + CHAN_BOND_1_MAX_SKEW_0 : integer := 7; + CHAN_BOND_1_MAX_SKEW_1 : integer := 7; + CHAN_BOND_2_MAX_SKEW_0 : integer := 1; + CHAN_BOND_2_MAX_SKEW_1 : integer := 1; + CHAN_BOND_LEVEL_0 : integer := 0; + CHAN_BOND_LEVEL_1 : integer := 0; + CHAN_BOND_MODE_0 : string := "OFF"; + CHAN_BOND_MODE_1 : string := "OFF"; + CHAN_BOND_SEQ_1_1_0 : bit_vector := "0001001010"; + CHAN_BOND_SEQ_1_1_1 : bit_vector := "0001001010"; + CHAN_BOND_SEQ_1_2_0 : bit_vector := "0001001010"; + CHAN_BOND_SEQ_1_2_1 : bit_vector := "0001001010"; + CHAN_BOND_SEQ_1_3_0 : bit_vector := "0001001010"; + CHAN_BOND_SEQ_1_3_1 : bit_vector := "0001001010"; + CHAN_BOND_SEQ_1_4_0 : bit_vector := "0110111100"; + CHAN_BOND_SEQ_1_4_1 : bit_vector := "0110111100"; + CHAN_BOND_SEQ_1_ENABLE_0 : bit_vector := "1111"; + CHAN_BOND_SEQ_1_ENABLE_1 : bit_vector := "1111"; + CHAN_BOND_SEQ_2_1_0 : bit_vector := "0110111100"; + CHAN_BOND_SEQ_2_1_1 : bit_vector := "0110111100"; + CHAN_BOND_SEQ_2_2_0 : bit_vector := "0100111100"; + CHAN_BOND_SEQ_2_2_1 : bit_vector := "0100111100"; + CHAN_BOND_SEQ_2_3_0 : bit_vector := "0100111100"; + CHAN_BOND_SEQ_2_3_1 : bit_vector := "0100111100"; + CHAN_BOND_SEQ_2_4_0 : bit_vector := "0100111100"; + CHAN_BOND_SEQ_2_4_1 : bit_vector := "0100111100"; + CHAN_BOND_SEQ_2_ENABLE_0 : bit_vector := "1111"; + CHAN_BOND_SEQ_2_ENABLE_1 : bit_vector := "1111"; + CHAN_BOND_SEQ_2_USE_0 : boolean := TRUE; + CHAN_BOND_SEQ_2_USE_1 : boolean := TRUE; + CHAN_BOND_SEQ_LEN_0 : integer := 4; + CHAN_BOND_SEQ_LEN_1 : integer := 4; + CLK25_DIVIDER : integer := 4; + CLKINDC_B : boolean := TRUE; + CLK_CORRECT_USE_0 : boolean := TRUE; + CLK_CORRECT_USE_1 : boolean := TRUE; + CLK_COR_ADJ_LEN_0 : integer := 1; + CLK_COR_ADJ_LEN_1 : integer := 1; + CLK_COR_DET_LEN_0 : integer := 1; + CLK_COR_DET_LEN_1 : integer := 1; + CLK_COR_INSERT_IDLE_FLAG_0 : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG_1 : boolean := FALSE; + CLK_COR_KEEP_IDLE_0 : boolean := FALSE; + CLK_COR_KEEP_IDLE_1 : boolean := FALSE; + CLK_COR_MAX_LAT_0 : integer := 18; + CLK_COR_MAX_LAT_1 : integer := 18; + CLK_COR_MIN_LAT_0 : integer := 16; + CLK_COR_MIN_LAT_1 : integer := 16; + CLK_COR_PRECEDENCE_0 : boolean := TRUE; + CLK_COR_PRECEDENCE_1 : boolean := TRUE; + CLK_COR_REPEAT_WAIT_0 : integer := 5; + CLK_COR_REPEAT_WAIT_1 : integer := 5; + CLK_COR_SEQ_1_1_0 : bit_vector := "0100011100"; + CLK_COR_SEQ_1_1_1 : bit_vector := "0100011100"; + CLK_COR_SEQ_1_2_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_2_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_3_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_3_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_4_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_4_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_ENABLE_0 : bit_vector := "1111"; + CLK_COR_SEQ_1_ENABLE_1 : bit_vector := "1111"; + CLK_COR_SEQ_2_1_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_1_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_2_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_2_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_3_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_3_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_4_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_4_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_ENABLE_0 : bit_vector := "1111"; + CLK_COR_SEQ_2_ENABLE_1 : bit_vector := "1111"; + CLK_COR_SEQ_2_USE_0 : boolean := FALSE; + CLK_COR_SEQ_2_USE_1 : boolean := FALSE; + COMMA_10B_ENABLE_0 : bit_vector := "1111111111"; + COMMA_10B_ENABLE_1 : bit_vector := "1111111111"; + COMMA_DOUBLE_0 : boolean := FALSE; + COMMA_DOUBLE_1 : boolean := FALSE; + COM_BURST_VAL_0 : bit_vector := "1111"; + COM_BURST_VAL_1 : bit_vector := "1111"; + DEC_MCOMMA_DETECT_0 : boolean := TRUE; + DEC_MCOMMA_DETECT_1 : boolean := TRUE; + DEC_PCOMMA_DETECT_0 : boolean := TRUE; + DEC_PCOMMA_DETECT_1 : boolean := TRUE; + DEC_VALID_COMMA_ONLY_0 : boolean := TRUE; + DEC_VALID_COMMA_ONLY_1 : boolean := TRUE; + MCOMMA_10B_VALUE_0 : bit_vector := "1010000011"; + MCOMMA_10B_VALUE_1 : bit_vector := "1010000011"; + MCOMMA_DETECT_0 : boolean := TRUE; + MCOMMA_DETECT_1 : boolean := TRUE; + OOBDETECT_THRESHOLD_0 : bit_vector := "001"; + OOBDETECT_THRESHOLD_1 : bit_vector := "001"; + OOB_CLK_DIVIDER : integer := 4; + OVERSAMPLE_MODE : boolean := FALSE; + PCI_EXPRESS_MODE_0 : boolean := TRUE; + PCI_EXPRESS_MODE_1 : boolean := TRUE; + PCOMMA_10B_VALUE_0 : bit_vector := "0101111100"; + PCOMMA_10B_VALUE_1 : bit_vector := "0101111100"; + PCOMMA_DETECT_0 : boolean := TRUE; + PCOMMA_DETECT_1 : boolean := TRUE; + PCS_COM_CFG : bit_vector := X"1680a0e"; + PLL_DIVSEL_FB : integer := 5; + PLL_DIVSEL_REF : integer := 2; + PLL_RXDIVSEL_OUT_0 : integer := 1; + PLL_RXDIVSEL_OUT_1 : integer := 1; + PLL_SATA_0 : boolean := FALSE; + PLL_SATA_1 : boolean := FALSE; + PLL_TXDIVSEL_COMM_OUT : integer := 1; + PLL_TXDIVSEL_OUT_0 : integer := 1; + PLL_TXDIVSEL_OUT_1 : integer := 1; + PMA_CDR_SCAN_0 : bit_vector := X"6c07640"; + PMA_CDR_SCAN_1 : bit_vector := X"6c07640"; + PMA_RX_CFG_0 : bit_vector := X"09f0089"; + PMA_RX_CFG_1 : bit_vector := X"09f0089"; + PRBS_ERR_THRESHOLD_0 : bit_vector := X"00000001"; + PRBS_ERR_THRESHOLD_1 : bit_vector := X"00000001"; + RCV_TERM_GND_0 : boolean := TRUE; + RCV_TERM_GND_1 : boolean := TRUE; + RCV_TERM_MID_0 : boolean := FALSE; + RCV_TERM_MID_1 : boolean := FALSE; + RCV_TERM_VTTRX_0 : boolean := FALSE; + RCV_TERM_VTTRX_1 : boolean := FALSE; + RX_BUFFER_USE_0 : boolean := TRUE; + RX_BUFFER_USE_1 : boolean := TRUE; + RX_DECODE_SEQ_MATCH_0 : boolean := TRUE; + RX_DECODE_SEQ_MATCH_1 : boolean := TRUE; + RX_LOSS_OF_SYNC_FSM_0 : boolean := FALSE; + RX_LOSS_OF_SYNC_FSM_1 : boolean := FALSE; + RX_LOS_INVALID_INCR_0 : integer := 8; + RX_LOS_INVALID_INCR_1 : integer := 8; + RX_LOS_THRESHOLD_0 : integer := 128; + RX_LOS_THRESHOLD_1 : integer := 128; + RX_SLIDE_MODE_0 : string := "PCS"; + RX_SLIDE_MODE_1 : string := "PCS"; + RX_STATUS_FMT_0 : string := "PCIE"; + RX_STATUS_FMT_1 : string := "PCIE"; + RX_XCLK_SEL_0 : string := "RXREC"; + RX_XCLK_SEL_1 : string := "RXREC"; + SATA_BURST_VAL_0 : bit_vector := "100"; + SATA_BURST_VAL_1 : bit_vector := "100"; + SATA_IDLE_VAL_0 : bit_vector := "011"; + SATA_IDLE_VAL_1 : bit_vector := "011"; + SATA_MAX_BURST_0 : integer := 7; + SATA_MAX_BURST_1 : integer := 7; + SATA_MAX_INIT_0 : integer := 22; + SATA_MAX_INIT_1 : integer := 22; + SATA_MAX_WAKE_0 : integer := 7; + SATA_MAX_WAKE_1 : integer := 7; + SATA_MIN_BURST_0 : integer := 4; + SATA_MIN_BURST_1 : integer := 4; + SATA_MIN_INIT_0 : integer := 12; + SATA_MIN_INIT_1 : integer := 12; + SATA_MIN_WAKE_0 : integer := 4; + SATA_MIN_WAKE_1 : integer := 4; + SIM_GTPRESET_SPEEDUP : integer := 0; + SIM_MODE : string := "FAST"; + SIM_PLL_PERDIV2 : bit_vector := X"190"; + SIM_RECEIVER_DETECT_PASS0 : boolean := FALSE; + SIM_RECEIVER_DETECT_PASS1 : boolean := FALSE; + TERMINATION_CTRL : bit_vector := "10100"; + TERMINATION_IMP_0 : integer := 50; + TERMINATION_IMP_1 : integer := 50; + TERMINATION_OVRD : boolean := FALSE; + TRANS_TIME_FROM_P2_0 : bit_vector := X"003c"; + TRANS_TIME_FROM_P2_1 : bit_vector := X"003c"; + TRANS_TIME_NON_P2_0 : bit_vector := X"0019"; + TRANS_TIME_NON_P2_1 : bit_vector := X"0019"; + TRANS_TIME_TO_P2_0 : bit_vector := X"0064"; + TRANS_TIME_TO_P2_1 : bit_vector := X"0064"; + TXRX_INVERT_0 : bit_vector := "00000"; + TXRX_INVERT_1 : bit_vector := "00000"; + TX_BUFFER_USE_0 : boolean := TRUE; + TX_BUFFER_USE_1 : boolean := TRUE; + TX_DIFF_BOOST_0 : boolean := TRUE; + TX_DIFF_BOOST_1 : boolean := TRUE; + TX_SYNC_FILTERB : integer := 1; + TX_XCLK_SEL_0 : string := "TXUSR"; + TX_XCLK_SEL_1 : string := "TXUSR" + ); + +port ( + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + PHYSTATUS0 : out std_ulogic; + PHYSTATUS1 : out std_ulogic; + PLLLKDET : out std_ulogic; + REFCLKOUT : out std_ulogic; + RESETDONE0 : out std_ulogic; + RESETDONE1 : out std_ulogic; + RXBUFSTATUS0 : out std_logic_vector(2 downto 0); + RXBUFSTATUS1 : out std_logic_vector(2 downto 0); + RXBYTEISALIGNED0 : out std_ulogic; + RXBYTEISALIGNED1 : out std_ulogic; + RXBYTEREALIGN0 : out std_ulogic; + RXBYTEREALIGN1 : out std_ulogic; + RXCHANBONDSEQ0 : out std_ulogic; + RXCHANBONDSEQ1 : out std_ulogic; + RXCHANISALIGNED0 : out std_ulogic; + RXCHANISALIGNED1 : out std_ulogic; + RXCHANREALIGN0 : out std_ulogic; + RXCHANREALIGN1 : out std_ulogic; + RXCHARISCOMMA0 : out std_logic_vector(1 downto 0); + RXCHARISCOMMA1 : out std_logic_vector(1 downto 0); + RXCHARISK0 : out std_logic_vector(1 downto 0); + RXCHARISK1 : out std_logic_vector(1 downto 0); + RXCHBONDO0 : out std_logic_vector(2 downto 0); + RXCHBONDO1 : out std_logic_vector(2 downto 0); + RXCLKCORCNT0 : out std_logic_vector(2 downto 0); + RXCLKCORCNT1 : out std_logic_vector(2 downto 0); + RXCOMMADET0 : out std_ulogic; + RXCOMMADET1 : out std_ulogic; + RXDATA0 : out std_logic_vector(15 downto 0); + RXDATA1 : out std_logic_vector(15 downto 0); + RXDISPERR0 : out std_logic_vector(1 downto 0); + RXDISPERR1 : out std_logic_vector(1 downto 0); + RXELECIDLE0 : out std_ulogic; + RXELECIDLE1 : out std_ulogic; + RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); + RXNOTINTABLE0 : out std_logic_vector(1 downto 0); + RXNOTINTABLE1 : out std_logic_vector(1 downto 0); + RXOVERSAMPLEERR0 : out std_ulogic; + RXOVERSAMPLEERR1 : out std_ulogic; + RXPRBSERR0 : out std_ulogic; + RXPRBSERR1 : out std_ulogic; + RXRECCLK0 : out std_ulogic; + RXRECCLK1 : out std_ulogic; + RXRUNDISP0 : out std_logic_vector(1 downto 0); + RXRUNDISP1 : out std_logic_vector(1 downto 0); + RXSTATUS0 : out std_logic_vector(2 downto 0); + RXSTATUS1 : out std_logic_vector(2 downto 0); + RXVALID0 : out std_ulogic; + RXVALID1 : out std_ulogic; + TXBUFSTATUS0 : out std_logic_vector(1 downto 0); + TXBUFSTATUS1 : out std_logic_vector(1 downto 0); + TXKERR0 : out std_logic_vector(1 downto 0); + TXKERR1 : out std_logic_vector(1 downto 0); + TXN0 : out std_ulogic; + TXN1 : out std_ulogic; + TXOUTCLK0 : out std_ulogic; + TXOUTCLK1 : out std_ulogic; + TXP0 : out std_ulogic; + TXP1 : out std_ulogic; + TXRUNDISP0 : out std_logic_vector(1 downto 0); + TXRUNDISP1 : out std_logic_vector(1 downto 0); + + CLKIN : in std_ulogic; + DADDR : in std_logic_vector(6 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + GTPRESET : in std_ulogic; + GTPTEST : in std_logic_vector(3 downto 0); + INTDATAWIDTH : in std_ulogic; + LOOPBACK0 : in std_logic_vector(2 downto 0); + LOOPBACK1 : in std_logic_vector(2 downto 0); + PLLLKDETEN : in std_ulogic; + PLLPOWERDOWN : in std_ulogic; + PRBSCNTRESET0 : in std_ulogic; + PRBSCNTRESET1 : in std_ulogic; + REFCLKPWRDNB : in std_ulogic; + RXBUFRESET0 : in std_ulogic; + RXBUFRESET1 : in std_ulogic; + RXCDRRESET0 : in std_ulogic; + RXCDRRESET1 : in std_ulogic; + RXCHBONDI0 : in std_logic_vector(2 downto 0); + RXCHBONDI1 : in std_logic_vector(2 downto 0); + RXCOMMADETUSE0 : in std_ulogic; + RXCOMMADETUSE1 : in std_ulogic; + RXDATAWIDTH0 : in std_ulogic; + RXDATAWIDTH1 : in std_ulogic; + RXDEC8B10BUSE0 : in std_ulogic; + RXDEC8B10BUSE1 : in std_ulogic; + RXELECIDLERESET0 : in std_ulogic; + RXELECIDLERESET1 : in std_ulogic; + RXENCHANSYNC0 : in std_ulogic; + RXENCHANSYNC1 : in std_ulogic; + RXENELECIDLERESETB : in std_ulogic; + RXENEQB0 : in std_ulogic; + RXENEQB1 : in std_ulogic; + RXENMCOMMAALIGN0 : in std_ulogic; + RXENMCOMMAALIGN1 : in std_ulogic; + RXENPCOMMAALIGN0 : in std_ulogic; + RXENPCOMMAALIGN1 : in std_ulogic; + RXENPRBSTST0 : in std_logic_vector(1 downto 0); + RXENPRBSTST1 : in std_logic_vector(1 downto 0); + RXENSAMPLEALIGN0 : in std_ulogic; + RXENSAMPLEALIGN1 : in std_ulogic; + RXEQMIX0 : in std_logic_vector(1 downto 0); + RXEQMIX1 : in std_logic_vector(1 downto 0); + RXEQPOLE0 : in std_logic_vector(3 downto 0); + RXEQPOLE1 : in std_logic_vector(3 downto 0); + RXN0 : in std_ulogic; + RXN1 : in std_ulogic; + RXP0 : in std_ulogic; + RXP1 : in std_ulogic; + RXPMASETPHASE0 : in std_ulogic; + RXPMASETPHASE1 : in std_ulogic; + RXPOLARITY0 : in std_ulogic; + RXPOLARITY1 : in std_ulogic; + RXPOWERDOWN0 : in std_logic_vector(1 downto 0); + RXPOWERDOWN1 : in std_logic_vector(1 downto 0); + RXRESET0 : in std_ulogic; + RXRESET1 : in std_ulogic; + RXSLIDE0 : in std_ulogic; + RXSLIDE1 : in std_ulogic; + RXUSRCLK0 : in std_ulogic; + RXUSRCLK1 : in std_ulogic; + RXUSRCLK20 : in std_ulogic; + RXUSRCLK21 : in std_ulogic; + TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXBYPASS8B10B0 : in std_logic_vector(1 downto 0); + TXBYPASS8B10B1 : in std_logic_vector(1 downto 0); + TXCHARDISPMODE0 : in std_logic_vector(1 downto 0); + TXCHARDISPMODE1 : in std_logic_vector(1 downto 0); + TXCHARDISPVAL0 : in std_logic_vector(1 downto 0); + TXCHARDISPVAL1 : in std_logic_vector(1 downto 0); + TXCHARISK0 : in std_logic_vector(1 downto 0); + TXCHARISK1 : in std_logic_vector(1 downto 0); + TXCOMSTART0 : in std_ulogic; + TXCOMSTART1 : in std_ulogic; + TXCOMTYPE0 : in std_ulogic; + TXCOMTYPE1 : in std_ulogic; + TXDATA0 : in std_logic_vector(15 downto 0); + TXDATA1 : in std_logic_vector(15 downto 0); + TXDATAWIDTH0 : in std_ulogic; + TXDATAWIDTH1 : in std_ulogic; + TXDETECTRX0 : in std_ulogic; + TXDETECTRX1 : in std_ulogic; + TXDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXELECIDLE0 : in std_ulogic; + TXELECIDLE1 : in std_ulogic; + TXENC8B10BUSE0 : in std_ulogic; + TXENC8B10BUSE1 : in std_ulogic; + TXENPMAPHASEALIGN : in std_ulogic; + TXENPRBSTST0 : in std_logic_vector(1 downto 0); + TXENPRBSTST1 : in std_logic_vector(1 downto 0); + TXINHIBIT0 : in std_ulogic; + TXINHIBIT1 : in std_ulogic; + TXPMASETPHASE : in std_ulogic; + TXPOLARITY0 : in std_ulogic; + TXPOLARITY1 : in std_ulogic; + TXPOWERDOWN0 : in std_logic_vector(1 downto 0); + TXPOWERDOWN1 : in std_logic_vector(1 downto 0); + TXPREEMPHASIS0 : in std_logic_vector(2 downto 0); + TXPREEMPHASIS1 : in std_logic_vector(2 downto 0); + TXRESET0 : in std_ulogic; + TXRESET1 : in std_ulogic; + TXUSRCLK0 : in std_ulogic; + TXUSRCLK1 : in std_ulogic; + TXUSRCLK20 : in std_ulogic; + TXUSRCLK21 : in std_ulogic + ); +end GTP_DUAL; + +architecture GTP_DUAL_V of GTP_DUAL is + + component GTP_DUAL_SWIFT + port ( + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + PHYSTATUS0 : out std_ulogic; + PHYSTATUS1 : out std_ulogic; + PLLLKDET : out std_ulogic; + REFCLKOUT : out std_ulogic; + RESETDONE0 : out std_ulogic; + RESETDONE1 : out std_ulogic; + RXBUFSTATUS0 : out std_logic_vector(2 downto 0); + RXBUFSTATUS1 : out std_logic_vector(2 downto 0); + RXBYTEISALIGNED0 : out std_ulogic; + RXBYTEISALIGNED1 : out std_ulogic; + RXBYTEREALIGN0 : out std_ulogic; + RXBYTEREALIGN1 : out std_ulogic; + RXCHANBONDSEQ0 : out std_ulogic; + RXCHANBONDSEQ1 : out std_ulogic; + RXCHANISALIGNED0 : out std_ulogic; + RXCHANISALIGNED1 : out std_ulogic; + RXCHANREALIGN0 : out std_ulogic; + RXCHANREALIGN1 : out std_ulogic; + RXCHARISCOMMA0 : out std_logic_vector(1 downto 0); + RXCHARISCOMMA1 : out std_logic_vector(1 downto 0); + RXCHARISK0 : out std_logic_vector(1 downto 0); + RXCHARISK1 : out std_logic_vector(1 downto 0); + RXCHBONDO0 : out std_logic_vector(2 downto 0); + RXCHBONDO1 : out std_logic_vector(2 downto 0); + RXCLKCORCNT0 : out std_logic_vector(2 downto 0); + RXCLKCORCNT1 : out std_logic_vector(2 downto 0); + RXCOMMADET0 : out std_ulogic; + RXCOMMADET1 : out std_ulogic; + RXDATA0 : out std_logic_vector(15 downto 0); + RXDATA1 : out std_logic_vector(15 downto 0); + RXDISPERR0 : out std_logic_vector(1 downto 0); + RXDISPERR1 : out std_logic_vector(1 downto 0); + RXELECIDLE0 : out std_ulogic; + RXELECIDLE1 : out std_ulogic; + RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); + RXNOTINTABLE0 : out std_logic_vector(1 downto 0); + RXNOTINTABLE1 : out std_logic_vector(1 downto 0); + RXOVERSAMPLEERR0 : out std_ulogic; + RXOVERSAMPLEERR1 : out std_ulogic; + RXPRBSERR0 : out std_ulogic; + RXPRBSERR1 : out std_ulogic; + RXRECCLK0 : out std_ulogic; + RXRECCLK1 : out std_ulogic; + RXRUNDISP0 : out std_logic_vector(1 downto 0); + RXRUNDISP1 : out std_logic_vector(1 downto 0); + RXSTATUS0 : out std_logic_vector(2 downto 0); + RXSTATUS1 : out std_logic_vector(2 downto 0); + RXVALID0 : out std_ulogic; + RXVALID1 : out std_ulogic; + TXBUFSTATUS0 : out std_logic_vector(1 downto 0); + TXBUFSTATUS1 : out std_logic_vector(1 downto 0); + TXKERR0 : out std_logic_vector(1 downto 0); + TXKERR1 : out std_logic_vector(1 downto 0); + TXN0 : out std_ulogic; + TXN1 : out std_ulogic; + TXOUTCLK0 : out std_ulogic; + TXOUTCLK1 : out std_ulogic; + TXP0 : out std_ulogic; + TXP1 : out std_ulogic; + TXRUNDISP0 : out std_logic_vector(1 downto 0); + TXRUNDISP1 : out std_logic_vector(1 downto 0); + + CLKIN : in std_ulogic; + DADDR : in std_logic_vector(6 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + GSR : in std_ulogic; + GTPRESET : in std_ulogic; + GTPTEST : in std_logic_vector(3 downto 0); + INTDATAWIDTH : in std_ulogic; + LOOPBACK0 : in std_logic_vector(2 downto 0); + LOOPBACK1 : in std_logic_vector(2 downto 0); + PLLLKDETEN : in std_ulogic; + PLLPOWERDOWN : in std_ulogic; + PRBSCNTRESET0 : in std_ulogic; + PRBSCNTRESET1 : in std_ulogic; + REFCLKPWRDNB : in std_ulogic; + RXBUFRESET0 : in std_ulogic; + RXBUFRESET1 : in std_ulogic; + RXCDRRESET0 : in std_ulogic; + RXCDRRESET1 : in std_ulogic; + RXCHBONDI0 : in std_logic_vector(2 downto 0); + RXCHBONDI1 : in std_logic_vector(2 downto 0); + RXCOMMADETUSE0 : in std_ulogic; + RXCOMMADETUSE1 : in std_ulogic; + RXDATAWIDTH0 : in std_ulogic; + RXDATAWIDTH1 : in std_ulogic; + RXDEC8B10BUSE0 : in std_ulogic; + RXDEC8B10BUSE1 : in std_ulogic; + RXELECIDLERESET0 : in std_ulogic; + RXELECIDLERESET1 : in std_ulogic; + RXENCHANSYNC0 : in std_ulogic; + RXENCHANSYNC1 : in std_ulogic; + RXENELECIDLERESETB : in std_ulogic; + RXENEQB0 : in std_ulogic; + RXENEQB1 : in std_ulogic; + RXENMCOMMAALIGN0 : in std_ulogic; + RXENMCOMMAALIGN1 : in std_ulogic; + RXENPCOMMAALIGN0 : in std_ulogic; + RXENPCOMMAALIGN1 : in std_ulogic; + RXENPRBSTST0 : in std_logic_vector(1 downto 0); + RXENPRBSTST1 : in std_logic_vector(1 downto 0); + RXENSAMPLEALIGN0 : in std_ulogic; + RXENSAMPLEALIGN1 : in std_ulogic; + RXEQMIX0 : in std_logic_vector(1 downto 0); + RXEQMIX1 : in std_logic_vector(1 downto 0); + RXEQPOLE0 : in std_logic_vector(3 downto 0); + RXEQPOLE1 : in std_logic_vector(3 downto 0); + RXN0 : in std_ulogic; + RXN1 : in std_ulogic; + RXP0 : in std_ulogic; + RXP1 : in std_ulogic; + RXPMASETPHASE0 : in std_ulogic; + RXPMASETPHASE1 : in std_ulogic; + RXPOLARITY0 : in std_ulogic; + RXPOLARITY1 : in std_ulogic; + RXPOWERDOWN0 : in std_logic_vector(1 downto 0); + RXPOWERDOWN1 : in std_logic_vector(1 downto 0); + RXRESET0 : in std_ulogic; + RXRESET1 : in std_ulogic; + RXSLIDE0 : in std_ulogic; + RXSLIDE1 : in std_ulogic; + RXUSRCLK0 : in std_ulogic; + RXUSRCLK1 : in std_ulogic; + RXUSRCLK20 : in std_ulogic; + RXUSRCLK21 : in std_ulogic; + TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXBYPASS8B10B0 : in std_logic_vector(1 downto 0); + TXBYPASS8B10B1 : in std_logic_vector(1 downto 0); + TXCHARDISPMODE0 : in std_logic_vector(1 downto 0); + TXCHARDISPMODE1 : in std_logic_vector(1 downto 0); + TXCHARDISPVAL0 : in std_logic_vector(1 downto 0); + TXCHARDISPVAL1 : in std_logic_vector(1 downto 0); + TXCHARISK0 : in std_logic_vector(1 downto 0); + TXCHARISK1 : in std_logic_vector(1 downto 0); + TXCOMSTART0 : in std_ulogic; + TXCOMSTART1 : in std_ulogic; + TXCOMTYPE0 : in std_ulogic; + TXCOMTYPE1 : in std_ulogic; + TXDATA0 : in std_logic_vector(15 downto 0); + TXDATA1 : in std_logic_vector(15 downto 0); + TXDATAWIDTH0 : in std_ulogic; + TXDATAWIDTH1 : in std_ulogic; + TXDETECTRX0 : in std_ulogic; + TXDETECTRX1 : in std_ulogic; + TXDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXELECIDLE0 : in std_ulogic; + TXELECIDLE1 : in std_ulogic; + TXENC8B10BUSE0 : in std_ulogic; + TXENC8B10BUSE1 : in std_ulogic; + TXENPMAPHASEALIGN : in std_ulogic; + TXENPRBSTST0 : in std_logic_vector(1 downto 0); + TXENPRBSTST1 : in std_logic_vector(1 downto 0); + TXINHIBIT0 : in std_ulogic; + TXINHIBIT1 : in std_ulogic; + TXPMASETPHASE : in std_ulogic; + TXPOLARITY0 : in std_ulogic; + TXPOLARITY1 : in std_ulogic; + TXPOWERDOWN0 : in std_logic_vector(1 downto 0); + TXPOWERDOWN1 : in std_logic_vector(1 downto 0); + TXPREEMPHASIS0 : in std_logic_vector(2 downto 0); + TXPREEMPHASIS1 : in std_logic_vector(2 downto 0); + TXRESET0 : in std_ulogic; + TXRESET1 : in std_ulogic; + TXUSRCLK0 : in std_ulogic; + TXUSRCLK1 : in std_ulogic; + TXUSRCLK20 : in std_ulogic; + TXUSRCLK21 : in std_ulogic; + + AC_CAP_DIS_0 : in std_ulogic; + AC_CAP_DIS_1 : in std_ulogic; + ALIGN_COMMA_WORD_0 : in std_ulogic; + ALIGN_COMMA_WORD_1 : in std_ulogic; + CHAN_BOND_1_MAX_SKEW_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_1_MAX_SKEW_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_2_MAX_SKEW_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_2_MAX_SKEW_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_LEVEL_0 : in std_logic_vector(2 downto 0); + CHAN_BOND_LEVEL_1 : in std_logic_vector(2 downto 0); + CHAN_BOND_MODE_0 : in std_logic_vector(1 downto 0); + CHAN_BOND_MODE_1 : in std_logic_vector(1 downto 0); + CHAN_BOND_SEQ_1_1_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_1_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_2_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_2_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_3_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_3_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_4_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_4_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_1_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_1_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_2_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_2_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_3_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_3_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_4_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_4_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_USE_0 : in std_ulogic; + CHAN_BOND_SEQ_2_USE_1 : in std_ulogic; + CHAN_BOND_SEQ_LEN_0 : in std_logic_vector(1 downto 0); + CHAN_BOND_SEQ_LEN_1 : in std_logic_vector(1 downto 0); + CLK25_DIVIDER : in std_logic_vector(2 downto 0); + CLKINDC_B : in std_ulogic; + CLK_CORRECT_USE_0 : in std_ulogic; + CLK_CORRECT_USE_1 : in std_ulogic; + CLK_COR_ADJ_LEN_0 : in std_logic_vector(1 downto 0); + CLK_COR_ADJ_LEN_1 : in std_logic_vector(1 downto 0); + CLK_COR_DET_LEN_0 : in std_logic_vector(1 downto 0); + CLK_COR_DET_LEN_1 : in std_logic_vector(1 downto 0); + CLK_COR_INSERT_IDLE_FLAG_0 : in std_ulogic; + CLK_COR_INSERT_IDLE_FLAG_1 : in std_ulogic; + CLK_COR_KEEP_IDLE_0 : in std_ulogic; + CLK_COR_KEEP_IDLE_1 : in std_ulogic; + CLK_COR_MAX_LAT_0 : in std_logic_vector(5 downto 0); + CLK_COR_MAX_LAT_1 : in std_logic_vector(5 downto 0); + CLK_COR_MIN_LAT_0 : in std_logic_vector(5 downto 0); + CLK_COR_MIN_LAT_1 : in std_logic_vector(5 downto 0); + CLK_COR_PRECEDENCE_0 : in std_ulogic; + CLK_COR_PRECEDENCE_1 : in std_ulogic; + CLK_COR_REPEAT_WAIT_0 : in std_logic_vector(4 downto 0); + CLK_COR_REPEAT_WAIT_1 : in std_logic_vector(4 downto 0); + CLK_COR_SEQ_1_1_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_1_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_2_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_2_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_3_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_3_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_4_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_4_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_1_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_1_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_2_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_2_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_3_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_3_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_4_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_4_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_USE_0 : in std_ulogic; + CLK_COR_SEQ_2_USE_1 : in std_ulogic; + COMMA_10B_ENABLE_0 : in std_logic_vector(9 downto 0); + COMMA_10B_ENABLE_1 : in std_logic_vector(9 downto 0); + COMMA_DOUBLE_0 : in std_ulogic; + COMMA_DOUBLE_1 : in std_ulogic; + COM_BURST_VAL_0 : in std_logic_vector(3 downto 0); + COM_BURST_VAL_1 : in std_logic_vector(3 downto 0); + DEC_MCOMMA_DETECT_0 : in std_ulogic; + DEC_MCOMMA_DETECT_1 : in std_ulogic; + DEC_PCOMMA_DETECT_0 : in std_ulogic; + DEC_PCOMMA_DETECT_1 : in std_ulogic; + DEC_VALID_COMMA_ONLY_0 : in std_ulogic; + DEC_VALID_COMMA_ONLY_1 : in std_ulogic; + MCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); + MCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); + MCOMMA_DETECT_0 : in std_ulogic; + MCOMMA_DETECT_1 : in std_ulogic; + OOBDETECT_THRESHOLD_0 : in std_logic_vector(2 downto 0); + OOBDETECT_THRESHOLD_1 : in std_logic_vector(2 downto 0); + OOB_CLK_DIVIDER : in std_logic_vector(2 downto 0); + OVERSAMPLE_MODE : in std_ulogic; + PCI_EXPRESS_MODE_0 : in std_ulogic; + PCI_EXPRESS_MODE_1 : in std_ulogic; + PCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); + PCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); + PCOMMA_DETECT_0 : in std_ulogic; + PCOMMA_DETECT_1 : in std_ulogic; + PCS_COM_CFG : in std_logic_vector(27 downto 0); + PLL_DIVSEL_FB : in std_logic_vector(4 downto 0); + PLL_DIVSEL_REF : in std_logic_vector(5 downto 0); + PLL_RXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); + PLL_RXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); + PLL_SATA_0 : in std_ulogic; + PLL_SATA_1 : in std_ulogic; + PLL_TXDIVSEL_COMM_OUT : in std_logic_vector(1 downto 0); + PLL_TXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); + PLL_TXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); + PMA_CDR_SCAN_0 : in std_logic_vector(26 downto 0); + PMA_CDR_SCAN_1 : in std_logic_vector(26 downto 0); + PMA_RX_CFG_0 : in std_logic_vector(24 downto 0); + PMA_RX_CFG_1 : in std_logic_vector(24 downto 0); + PRBS_ERR_THRESHOLD_0 : in std_logic_vector(31 downto 0); + PRBS_ERR_THRESHOLD_1 : in std_logic_vector(31 downto 0); + RCV_TERM_GND_0 : in std_ulogic; + RCV_TERM_GND_1 : in std_ulogic; + RCV_TERM_MID_0 : in std_ulogic; + RCV_TERM_MID_1 : in std_ulogic; + RCV_TERM_VTTRX_0 : in std_ulogic; + RCV_TERM_VTTRX_1 : in std_ulogic; + RX_BUFFER_USE_0 : in std_ulogic; + RX_BUFFER_USE_1 : in std_ulogic; + RX_DECODE_SEQ_MATCH_0 : in std_ulogic; + RX_DECODE_SEQ_MATCH_1 : in std_ulogic; + RX_LOSS_OF_SYNC_FSM_0 : in std_ulogic; + RX_LOSS_OF_SYNC_FSM_1 : in std_ulogic; + RX_LOS_INVALID_INCR_0 : in std_logic_vector(2 downto 0); + RX_LOS_INVALID_INCR_1 : in std_logic_vector(2 downto 0); + RX_LOS_THRESHOLD_0 : in std_logic_vector(2 downto 0); + RX_LOS_THRESHOLD_1 : in std_logic_vector(2 downto 0); + RX_SLIDE_MODE_0 : in std_ulogic; + RX_SLIDE_MODE_1 : in std_ulogic; + RX_STATUS_FMT_0 : in std_ulogic; + RX_STATUS_FMT_1 : in std_ulogic; + RX_XCLK_SEL_0 : in std_ulogic; + RX_XCLK_SEL_1 : in std_ulogic; + SATA_BURST_VAL_0 : in std_logic_vector(2 downto 0); + SATA_BURST_VAL_1 : in std_logic_vector(2 downto 0); + SATA_IDLE_VAL_0 : in std_logic_vector(2 downto 0); + SATA_IDLE_VAL_1 : in std_logic_vector(2 downto 0); + SATA_MAX_BURST_0 : in std_logic_vector(5 downto 0); + SATA_MAX_BURST_1 : in std_logic_vector(5 downto 0); + SATA_MAX_INIT_0 : in std_logic_vector(5 downto 0); + SATA_MAX_INIT_1 : in std_logic_vector(5 downto 0); + SATA_MAX_WAKE_0 : in std_logic_vector(5 downto 0); + SATA_MAX_WAKE_1 : in std_logic_vector(5 downto 0); + SATA_MIN_BURST_0 : in std_logic_vector(5 downto 0); + SATA_MIN_BURST_1 : in std_logic_vector(5 downto 0); + SATA_MIN_INIT_0 : in std_logic_vector(5 downto 0); + SATA_MIN_INIT_1 : in std_logic_vector(5 downto 0); + SATA_MIN_WAKE_0 : in std_logic_vector(5 downto 0); + SATA_MIN_WAKE_1 : in std_logic_vector(5 downto 0); + SIM_GTPRESET_SPEEDUP : in std_ulogic; + SIM_PLL_PERDIV2 : in std_logic_vector(8 downto 0); + SIM_RECEIVER_DETECT_PASS0 : in std_ulogic; + SIM_RECEIVER_DETECT_PASS1 : in std_ulogic; + TERMINATION_CTRL : in std_logic_vector(4 downto 0); + TERMINATION_IMP_0 : in std_ulogic; + TERMINATION_IMP_1 : in std_ulogic; + TERMINATION_OVRD : in std_ulogic; + TRANS_TIME_FROM_P2_0 : in std_logic_vector(15 downto 0); + TRANS_TIME_FROM_P2_1 : in std_logic_vector(15 downto 0); + TRANS_TIME_NON_P2_0 : in std_logic_vector(15 downto 0); + TRANS_TIME_NON_P2_1 : in std_logic_vector(15 downto 0); + TRANS_TIME_TO_P2_0 : in std_logic_vector(15 downto 0); + TRANS_TIME_TO_P2_1 : in std_logic_vector(15 downto 0); + TXRX_INVERT_0 : in std_logic_vector(4 downto 0); + TXRX_INVERT_1 : in std_logic_vector(4 downto 0); + TX_BUFFER_USE_0 : in std_ulogic; + TX_BUFFER_USE_1 : in std_ulogic; + TX_DIFF_BOOST_0 : in std_ulogic; + TX_DIFF_BOOST_1 : in std_ulogic; + TX_SYNC_FILTERB : in std_ulogic; + TX_XCLK_SEL_0 : in std_ulogic; + TX_XCLK_SEL_1 : in std_ulogic + ); + end component; + + component GTP_DUAL_FAST + port ( + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + PHYSTATUS0 : out std_ulogic; + PHYSTATUS1 : out std_ulogic; + PLLLKDET : out std_ulogic; + REFCLKOUT : out std_ulogic; + RESETDONE0 : out std_ulogic; + RESETDONE1 : out std_ulogic; + RXBUFSTATUS0 : out std_logic_vector(2 downto 0); + RXBUFSTATUS1 : out std_logic_vector(2 downto 0); + RXBYTEISALIGNED0 : out std_ulogic; + RXBYTEISALIGNED1 : out std_ulogic; + RXBYTEREALIGN0 : out std_ulogic; + RXBYTEREALIGN1 : out std_ulogic; + RXCHANBONDSEQ0 : out std_ulogic; + RXCHANBONDSEQ1 : out std_ulogic; + RXCHANISALIGNED0 : out std_ulogic; + RXCHANISALIGNED1 : out std_ulogic; + RXCHANREALIGN0 : out std_ulogic; + RXCHANREALIGN1 : out std_ulogic; + RXCHARISCOMMA0 : out std_logic_vector(1 downto 0); + RXCHARISCOMMA1 : out std_logic_vector(1 downto 0); + RXCHARISK0 : out std_logic_vector(1 downto 0); + RXCHARISK1 : out std_logic_vector(1 downto 0); + RXCHBONDO0 : out std_logic_vector(2 downto 0); + RXCHBONDO1 : out std_logic_vector(2 downto 0); + RXCLKCORCNT0 : out std_logic_vector(2 downto 0); + RXCLKCORCNT1 : out std_logic_vector(2 downto 0); + RXCOMMADET0 : out std_ulogic; + RXCOMMADET1 : out std_ulogic; + RXDATA0 : out std_logic_vector(15 downto 0); + RXDATA1 : out std_logic_vector(15 downto 0); + RXDISPERR0 : out std_logic_vector(1 downto 0); + RXDISPERR1 : out std_logic_vector(1 downto 0); + RXELECIDLE0 : out std_ulogic; + RXELECIDLE1 : out std_ulogic; + RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); + RXNOTINTABLE0 : out std_logic_vector(1 downto 0); + RXNOTINTABLE1 : out std_logic_vector(1 downto 0); + RXOVERSAMPLEERR0 : out std_ulogic; + RXOVERSAMPLEERR1 : out std_ulogic; + RXPRBSERR0 : out std_ulogic; + RXPRBSERR1 : out std_ulogic; + RXRECCLK0 : out std_ulogic; + RXRECCLK1 : out std_ulogic; + RXRUNDISP0 : out std_logic_vector(1 downto 0); + RXRUNDISP1 : out std_logic_vector(1 downto 0); + RXSTATUS0 : out std_logic_vector(2 downto 0); + RXSTATUS1 : out std_logic_vector(2 downto 0); + RXVALID0 : out std_ulogic; + RXVALID1 : out std_ulogic; + TXBUFSTATUS0 : out std_logic_vector(1 downto 0); + TXBUFSTATUS1 : out std_logic_vector(1 downto 0); + TXKERR0 : out std_logic_vector(1 downto 0); + TXKERR1 : out std_logic_vector(1 downto 0); + TXN0 : out std_ulogic; + TXN1 : out std_ulogic; + TXOUTCLK0 : out std_ulogic; + TXOUTCLK1 : out std_ulogic; + TXP0 : out std_ulogic; + TXP1 : out std_ulogic; + TXRUNDISP0 : out std_logic_vector(1 downto 0); + TXRUNDISP1 : out std_logic_vector(1 downto 0); + + CLKIN : in std_ulogic; + DADDR : in std_logic_vector(6 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + GSR : in std_ulogic; + GTPRESET : in std_ulogic; + GTPTEST : in std_logic_vector(3 downto 0); + INTDATAWIDTH : in std_ulogic; + LOOPBACK0 : in std_logic_vector(2 downto 0); + LOOPBACK1 : in std_logic_vector(2 downto 0); + PLLLKDETEN : in std_ulogic; + PLLPOWERDOWN : in std_ulogic; + PRBSCNTRESET0 : in std_ulogic; + PRBSCNTRESET1 : in std_ulogic; + REFCLKPWRDNB : in std_ulogic; + RXBUFRESET0 : in std_ulogic; + RXBUFRESET1 : in std_ulogic; + RXCDRRESET0 : in std_ulogic; + RXCDRRESET1 : in std_ulogic; + RXCHBONDI0 : in std_logic_vector(2 downto 0); + RXCHBONDI1 : in std_logic_vector(2 downto 0); + RXCOMMADETUSE0 : in std_ulogic; + RXCOMMADETUSE1 : in std_ulogic; + RXDATAWIDTH0 : in std_ulogic; + RXDATAWIDTH1 : in std_ulogic; + RXDEC8B10BUSE0 : in std_ulogic; + RXDEC8B10BUSE1 : in std_ulogic; + RXELECIDLERESET0 : in std_ulogic; + RXELECIDLERESET1 : in std_ulogic; + RXENCHANSYNC0 : in std_ulogic; + RXENCHANSYNC1 : in std_ulogic; + RXENELECIDLERESETB : in std_ulogic; + RXENEQB0 : in std_ulogic; + RXENEQB1 : in std_ulogic; + RXENMCOMMAALIGN0 : in std_ulogic; + RXENMCOMMAALIGN1 : in std_ulogic; + RXENPCOMMAALIGN0 : in std_ulogic; + RXENPCOMMAALIGN1 : in std_ulogic; + RXENPRBSTST0 : in std_logic_vector(1 downto 0); + RXENPRBSTST1 : in std_logic_vector(1 downto 0); + RXENSAMPLEALIGN0 : in std_ulogic; + RXENSAMPLEALIGN1 : in std_ulogic; + RXEQMIX0 : in std_logic_vector(1 downto 0); + RXEQMIX1 : in std_logic_vector(1 downto 0); + RXEQPOLE0 : in std_logic_vector(3 downto 0); + RXEQPOLE1 : in std_logic_vector(3 downto 0); + RXN0 : in std_ulogic; + RXN1 : in std_ulogic; + RXP0 : in std_ulogic; + RXP1 : in std_ulogic; + RXPMASETPHASE0 : in std_ulogic; + RXPMASETPHASE1 : in std_ulogic; + RXPOLARITY0 : in std_ulogic; + RXPOLARITY1 : in std_ulogic; + RXPOWERDOWN0 : in std_logic_vector(1 downto 0); + RXPOWERDOWN1 : in std_logic_vector(1 downto 0); + RXRESET0 : in std_ulogic; + RXRESET1 : in std_ulogic; + RXSLIDE0 : in std_ulogic; + RXSLIDE1 : in std_ulogic; + RXUSRCLK0 : in std_ulogic; + RXUSRCLK1 : in std_ulogic; + RXUSRCLK20 : in std_ulogic; + RXUSRCLK21 : in std_ulogic; + TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXBYPASS8B10B0 : in std_logic_vector(1 downto 0); + TXBYPASS8B10B1 : in std_logic_vector(1 downto 0); + TXCHARDISPMODE0 : in std_logic_vector(1 downto 0); + TXCHARDISPMODE1 : in std_logic_vector(1 downto 0); + TXCHARDISPVAL0 : in std_logic_vector(1 downto 0); + TXCHARDISPVAL1 : in std_logic_vector(1 downto 0); + TXCHARISK0 : in std_logic_vector(1 downto 0); + TXCHARISK1 : in std_logic_vector(1 downto 0); + TXCOMSTART0 : in std_ulogic; + TXCOMSTART1 : in std_ulogic; + TXCOMTYPE0 : in std_ulogic; + TXCOMTYPE1 : in std_ulogic; + TXDATA0 : in std_logic_vector(15 downto 0); + TXDATA1 : in std_logic_vector(15 downto 0); + TXDATAWIDTH0 : in std_ulogic; + TXDATAWIDTH1 : in std_ulogic; + TXDETECTRX0 : in std_ulogic; + TXDETECTRX1 : in std_ulogic; + TXDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXELECIDLE0 : in std_ulogic; + TXELECIDLE1 : in std_ulogic; + TXENC8B10BUSE0 : in std_ulogic; + TXENC8B10BUSE1 : in std_ulogic; + TXENPMAPHASEALIGN : in std_ulogic; + TXENPRBSTST0 : in std_logic_vector(1 downto 0); + TXENPRBSTST1 : in std_logic_vector(1 downto 0); + TXINHIBIT0 : in std_ulogic; + TXINHIBIT1 : in std_ulogic; + TXPMASETPHASE : in std_ulogic; + TXPOLARITY0 : in std_ulogic; + TXPOLARITY1 : in std_ulogic; + TXPOWERDOWN0 : in std_logic_vector(1 downto 0); + TXPOWERDOWN1 : in std_logic_vector(1 downto 0); + TXPREEMPHASIS0 : in std_logic_vector(2 downto 0); + TXPREEMPHASIS1 : in std_logic_vector(2 downto 0); + TXRESET0 : in std_ulogic; + TXRESET1 : in std_ulogic; + TXUSRCLK0 : in std_ulogic; + TXUSRCLK1 : in std_ulogic; + TXUSRCLK20 : in std_ulogic; + TXUSRCLK21 : in std_ulogic; + + AC_CAP_DIS_0 : in std_ulogic; + AC_CAP_DIS_1 : in std_ulogic; + ALIGN_COMMA_WORD_0 : in std_ulogic; + ALIGN_COMMA_WORD_1 : in std_ulogic; + CHAN_BOND_1_MAX_SKEW_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_1_MAX_SKEW_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_2_MAX_SKEW_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_2_MAX_SKEW_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_LEVEL_0 : in std_logic_vector(2 downto 0); + CHAN_BOND_LEVEL_1 : in std_logic_vector(2 downto 0); + CHAN_BOND_MODE_0 : in std_logic_vector(1 downto 0); + CHAN_BOND_MODE_1 : in std_logic_vector(1 downto 0); + CHAN_BOND_SEQ_1_1_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_1_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_2_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_2_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_3_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_3_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_4_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_4_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_1_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_1_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_2_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_2_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_3_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_3_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_4_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_4_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_USE_0 : in std_ulogic; + CHAN_BOND_SEQ_2_USE_1 : in std_ulogic; + CHAN_BOND_SEQ_LEN_0 : in std_logic_vector(1 downto 0); + CHAN_BOND_SEQ_LEN_1 : in std_logic_vector(1 downto 0); + CLK25_DIVIDER : in std_logic_vector(2 downto 0); + CLKINDC_B : in std_ulogic; + CLK_CORRECT_USE_0 : in std_ulogic; + CLK_CORRECT_USE_1 : in std_ulogic; + CLK_COR_ADJ_LEN_0 : in std_logic_vector(1 downto 0); + CLK_COR_ADJ_LEN_1 : in std_logic_vector(1 downto 0); + CLK_COR_DET_LEN_0 : in std_logic_vector(1 downto 0); + CLK_COR_DET_LEN_1 : in std_logic_vector(1 downto 0); + CLK_COR_INSERT_IDLE_FLAG_0 : in std_ulogic; + CLK_COR_INSERT_IDLE_FLAG_1 : in std_ulogic; + CLK_COR_KEEP_IDLE_0 : in std_ulogic; + CLK_COR_KEEP_IDLE_1 : in std_ulogic; + CLK_COR_MAX_LAT_0 : in std_logic_vector(5 downto 0); + CLK_COR_MAX_LAT_1 : in std_logic_vector(5 downto 0); + CLK_COR_MIN_LAT_0 : in std_logic_vector(5 downto 0); + CLK_COR_MIN_LAT_1 : in std_logic_vector(5 downto 0); + CLK_COR_PRECEDENCE_0 : in std_ulogic; + CLK_COR_PRECEDENCE_1 : in std_ulogic; + CLK_COR_REPEAT_WAIT_0 : in std_logic_vector(4 downto 0); + CLK_COR_REPEAT_WAIT_1 : in std_logic_vector(4 downto 0); + CLK_COR_SEQ_1_1_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_1_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_2_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_2_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_3_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_3_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_4_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_4_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_1_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_1_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_2_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_2_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_3_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_3_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_4_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_4_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_USE_0 : in std_ulogic; + CLK_COR_SEQ_2_USE_1 : in std_ulogic; + COMMA_10B_ENABLE_0 : in std_logic_vector(9 downto 0); + COMMA_10B_ENABLE_1 : in std_logic_vector(9 downto 0); + COMMA_DOUBLE_0 : in std_ulogic; + COMMA_DOUBLE_1 : in std_ulogic; + COM_BURST_VAL_0 : in std_logic_vector(3 downto 0); + COM_BURST_VAL_1 : in std_logic_vector(3 downto 0); + DEC_MCOMMA_DETECT_0 : in std_ulogic; + DEC_MCOMMA_DETECT_1 : in std_ulogic; + DEC_PCOMMA_DETECT_0 : in std_ulogic; + DEC_PCOMMA_DETECT_1 : in std_ulogic; + DEC_VALID_COMMA_ONLY_0 : in std_ulogic; + DEC_VALID_COMMA_ONLY_1 : in std_ulogic; + MCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); + MCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); + MCOMMA_DETECT_0 : in std_ulogic; + MCOMMA_DETECT_1 : in std_ulogic; + OOBDETECT_THRESHOLD_0 : in std_logic_vector(2 downto 0); + OOBDETECT_THRESHOLD_1 : in std_logic_vector(2 downto 0); + OOB_CLK_DIVIDER : in std_logic_vector(2 downto 0); + OVERSAMPLE_MODE : in std_ulogic; + PCI_EXPRESS_MODE_0 : in std_ulogic; + PCI_EXPRESS_MODE_1 : in std_ulogic; + PCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); + PCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); + PCOMMA_DETECT_0 : in std_ulogic; + PCOMMA_DETECT_1 : in std_ulogic; + PCS_COM_CFG : in std_logic_vector(27 downto 0); + PLL_DIVSEL_FB : in std_logic_vector(4 downto 0); + PLL_DIVSEL_REF : in std_logic_vector(5 downto 0); + PLL_RXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); + PLL_RXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); + PLL_SATA_0 : in std_ulogic; + PLL_SATA_1 : in std_ulogic; + PLL_TXDIVSEL_COMM_OUT : in std_logic_vector(1 downto 0); + PLL_TXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); + PLL_TXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); + PMA_CDR_SCAN_0 : in std_logic_vector(26 downto 0); + PMA_CDR_SCAN_1 : in std_logic_vector(26 downto 0); + PMA_RX_CFG_0 : in std_logic_vector(24 downto 0); + PMA_RX_CFG_1 : in std_logic_vector(24 downto 0); + PRBS_ERR_THRESHOLD_0 : in std_logic_vector(31 downto 0); + PRBS_ERR_THRESHOLD_1 : in std_logic_vector(31 downto 0); + RCV_TERM_GND_0 : in std_ulogic; + RCV_TERM_GND_1 : in std_ulogic; + RCV_TERM_MID_0 : in std_ulogic; + RCV_TERM_MID_1 : in std_ulogic; + RCV_TERM_VTTRX_0 : in std_ulogic; + RCV_TERM_VTTRX_1 : in std_ulogic; + RX_BUFFER_USE_0 : in std_ulogic; + RX_BUFFER_USE_1 : in std_ulogic; + RX_DECODE_SEQ_MATCH_0 : in std_ulogic; + RX_DECODE_SEQ_MATCH_1 : in std_ulogic; + RX_LOSS_OF_SYNC_FSM_0 : in std_ulogic; + RX_LOSS_OF_SYNC_FSM_1 : in std_ulogic; + RX_LOS_INVALID_INCR_0 : in std_logic_vector(2 downto 0); + RX_LOS_INVALID_INCR_1 : in std_logic_vector(2 downto 0); + RX_LOS_THRESHOLD_0 : in std_logic_vector(2 downto 0); + RX_LOS_THRESHOLD_1 : in std_logic_vector(2 downto 0); + RX_SLIDE_MODE_0 : in std_ulogic; + RX_SLIDE_MODE_1 : in std_ulogic; + RX_STATUS_FMT_0 : in std_ulogic; + RX_STATUS_FMT_1 : in std_ulogic; + RX_XCLK_SEL_0 : in std_ulogic; + RX_XCLK_SEL_1 : in std_ulogic; + SATA_BURST_VAL_0 : in std_logic_vector(2 downto 0); + SATA_BURST_VAL_1 : in std_logic_vector(2 downto 0); + SATA_IDLE_VAL_0 : in std_logic_vector(2 downto 0); + SATA_IDLE_VAL_1 : in std_logic_vector(2 downto 0); + SATA_MAX_BURST_0 : in std_logic_vector(5 downto 0); + SATA_MAX_BURST_1 : in std_logic_vector(5 downto 0); + SATA_MAX_INIT_0 : in std_logic_vector(5 downto 0); + SATA_MAX_INIT_1 : in std_logic_vector(5 downto 0); + SATA_MAX_WAKE_0 : in std_logic_vector(5 downto 0); + SATA_MAX_WAKE_1 : in std_logic_vector(5 downto 0); + SATA_MIN_BURST_0 : in std_logic_vector(5 downto 0); + SATA_MIN_BURST_1 : in std_logic_vector(5 downto 0); + SATA_MIN_INIT_0 : in std_logic_vector(5 downto 0); + SATA_MIN_INIT_1 : in std_logic_vector(5 downto 0); + SATA_MIN_WAKE_0 : in std_logic_vector(5 downto 0); + SATA_MIN_WAKE_1 : in std_logic_vector(5 downto 0); + SIM_GTPRESET_SPEEDUP : in std_ulogic; + SIM_PLL_PERDIV2 : in std_logic_vector(8 downto 0); + SIM_RECEIVER_DETECT_PASS0 : in std_ulogic; + SIM_RECEIVER_DETECT_PASS1 : in std_ulogic; + TERMINATION_CTRL : in std_logic_vector(4 downto 0); + TERMINATION_IMP_0 : in std_ulogic; + TERMINATION_IMP_1 : in std_ulogic; + TERMINATION_OVRD : in std_ulogic; + TRANS_TIME_FROM_P2_0 : in std_logic_vector(15 downto 0); + TRANS_TIME_FROM_P2_1 : in std_logic_vector(15 downto 0); + TRANS_TIME_NON_P2_0 : in std_logic_vector(15 downto 0); + TRANS_TIME_NON_P2_1 : in std_logic_vector(15 downto 0); + TRANS_TIME_TO_P2_0 : in std_logic_vector(15 downto 0); + TRANS_TIME_TO_P2_1 : in std_logic_vector(15 downto 0); + TXRX_INVERT_0 : in std_logic_vector(4 downto 0); + TXRX_INVERT_1 : in std_logic_vector(4 downto 0); + TX_BUFFER_USE_0 : in std_ulogic; + TX_BUFFER_USE_1 : in std_ulogic; + TX_DIFF_BOOST_0 : in std_ulogic; + TX_DIFF_BOOST_1 : in std_ulogic; + TX_SYNC_FILTERB : in std_ulogic; + TX_XCLK_SEL_0 : in std_ulogic; + TX_XCLK_SEL_1 : in std_ulogic + ); + end component; + + constant IN_DELAY : time := 0 ps; + constant OUT_DELAY : time := 0 ps; + constant CLK_DELAY : time := 0 ps; + + constant PATH_DELAY : VitalDelayType01 := (100 ps, 100 ps); + + signal PLL_TXDIVSEL_OUT_0_BINARY : std_logic_vector(1 downto 0); + signal PLL_RXDIVSEL_OUT_0_BINARY : std_logic_vector(1 downto 0); + signal PLL_TXDIVSEL_OUT_1_BINARY : std_logic_vector(1 downto 0); + signal PLL_RXDIVSEL_OUT_1_BINARY : std_logic_vector(1 downto 0); + signal PLL_DIVSEL_FB_BINARY : std_logic_vector(4 downto 0); + signal PLL_DIVSEL_REF_BINARY : std_logic_vector(5 downto 0); + signal PLL_TXDIVSEL_COMM_OUT_BINARY : std_logic_vector(1 downto 0); + signal PLL_SATA_0_BINARY : std_ulogic; + signal PLL_SATA_1_BINARY : std_ulogic; + signal TX_DIFF_BOOST_0_BINARY : std_ulogic; + signal OOBDETECT_THRESHOLD_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(OOBDETECT_THRESHOLD_0); + signal TX_DIFF_BOOST_1_BINARY : std_ulogic; + signal OOBDETECT_THRESHOLD_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(OOBDETECT_THRESHOLD_1); + signal PMA_CDR_SCAN_0_BINARY : std_logic_vector(26 downto 0) := To_StdLogicVector(PMA_CDR_SCAN_0)(26 downto 0); + signal PMA_CDR_SCAN_1_BINARY : std_logic_vector(26 downto 0) := To_StdLogicVector(PMA_CDR_SCAN_1)(26 downto 0); + signal PMA_RX_CFG_0_BINARY : std_logic_vector(24 downto 0) := To_StdLogicVector(PMA_RX_CFG_0)(24 downto 0); + signal PMA_RX_CFG_1_BINARY : std_logic_vector(24 downto 0) := To_StdLogicVector(PMA_RX_CFG_1)(24 downto 0); + signal OOB_CLK_DIVIDER_BINARY : std_logic_vector(2 downto 0); + signal TX_SYNC_FILTERB_BINARY : std_ulogic; + signal AC_CAP_DIS_0_BINARY : std_ulogic; + signal AC_CAP_DIS_1_BINARY : std_ulogic; + signal RCV_TERM_GND_0_BINARY : std_ulogic; + signal RCV_TERM_GND_1_BINARY : std_ulogic; + signal RCV_TERM_MID_0_BINARY : std_ulogic; + signal RCV_TERM_MID_1_BINARY : std_ulogic; + signal TERMINATION_IMP_0_BINARY : std_ulogic; + signal TERMINATION_IMP_1_BINARY : std_ulogic; + signal TERMINATION_OVRD_BINARY : std_ulogic; + signal TERMINATION_CTRL_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TERMINATION_CTRL); + signal RCV_TERM_VTTRX_0_BINARY : std_ulogic; + signal RCV_TERM_VTTRX_1_BINARY : std_ulogic; + signal TXRX_INVERT_0_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TXRX_INVERT_0); + signal TXRX_INVERT_1_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TXRX_INVERT_1); + signal CLKINDC_B_BINARY : std_ulogic; + signal PCOMMA_DETECT_0_BINARY : std_ulogic; + signal MCOMMA_DETECT_0_BINARY : std_ulogic; + signal PCOMMA_10B_VALUE_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(PCOMMA_10B_VALUE_0); + signal MCOMMA_10B_VALUE_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(MCOMMA_10B_VALUE_0); + signal COMMA_10B_ENABLE_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(COMMA_10B_ENABLE_0); + signal COMMA_DOUBLE_0_BINARY : std_ulogic; + signal ALIGN_COMMA_WORD_0_BINARY : std_ulogic; + signal DEC_PCOMMA_DETECT_0_BINARY : std_ulogic; + signal DEC_MCOMMA_DETECT_0_BINARY : std_ulogic; + signal DEC_VALID_COMMA_ONLY_0_BINARY : std_ulogic; + signal PCOMMA_DETECT_1_BINARY : std_ulogic; + signal MCOMMA_DETECT_1_BINARY : std_ulogic; + signal PCOMMA_10B_VALUE_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(PCOMMA_10B_VALUE_1); + signal MCOMMA_10B_VALUE_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(MCOMMA_10B_VALUE_1); + signal COMMA_10B_ENABLE_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(COMMA_10B_ENABLE_1); + signal COMMA_DOUBLE_1_BINARY : std_ulogic; + signal ALIGN_COMMA_WORD_1_BINARY : std_ulogic; + signal DEC_PCOMMA_DETECT_1_BINARY : std_ulogic; + signal DEC_MCOMMA_DETECT_1_BINARY : std_ulogic; + signal DEC_VALID_COMMA_ONLY_1_BINARY : std_ulogic; + signal RX_LOSS_OF_SYNC_FSM_0_BINARY : std_ulogic; + signal RX_LOS_INVALID_INCR_0_BINARY : std_logic_vector(2 downto 0); + signal RX_LOS_THRESHOLD_0_BINARY : std_logic_vector(2 downto 0); + signal RX_LOSS_OF_SYNC_FSM_1_BINARY : std_ulogic; + signal RX_LOS_INVALID_INCR_1_BINARY : std_logic_vector(2 downto 0); + signal RX_LOS_THRESHOLD_1_BINARY : std_logic_vector(2 downto 0); + signal RX_BUFFER_USE_0_BINARY : std_ulogic; + signal RX_DECODE_SEQ_MATCH_0_BINARY : std_ulogic; + signal RX_BUFFER_USE_1_BINARY : std_ulogic; + signal RX_DECODE_SEQ_MATCH_1_BINARY : std_ulogic; + signal CLK_COR_MIN_LAT_0_BINARY : std_logic_vector(5 downto 0); + signal CLK_COR_MAX_LAT_0_BINARY : std_logic_vector(5 downto 0); + signal CLK_CORRECT_USE_0_BINARY : std_ulogic; + signal CLK_COR_PRECEDENCE_0_BINARY : std_ulogic; + signal CLK_COR_DET_LEN_0_BINARY : std_logic_vector(1 downto 0); + signal CLK_COR_ADJ_LEN_0_BINARY : std_logic_vector(1 downto 0); + signal CLK_COR_KEEP_IDLE_0_BINARY : std_ulogic; + signal CLK_COR_INSERT_IDLE_FLAG_0_BINARY : std_ulogic; + signal CLK_COR_REPEAT_WAIT_0_BINARY : std_logic_vector(4 downto 0); + signal CLK_COR_SEQ_2_USE_0_BINARY : std_ulogic; + signal CLK_COR_SEQ_1_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1_0); + signal CLK_COR_SEQ_1_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2_0); + signal CLK_COR_SEQ_1_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3_0); + signal CLK_COR_SEQ_1_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4_0); + signal CLK_COR_SEQ_2_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1_0); + signal CLK_COR_SEQ_2_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2_0); + signal CLK_COR_SEQ_2_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3_0); + signal CLK_COR_SEQ_2_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4_0); + signal CLK_COR_SEQ_1_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_ENABLE_0); + signal CLK_COR_SEQ_2_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_ENABLE_0); + signal CLK_COR_MIN_LAT_1_BINARY : std_logic_vector(5 downto 0); + signal CLK_COR_MAX_LAT_1_BINARY : std_logic_vector(5 downto 0); + signal CLK_CORRECT_USE_1_BINARY : std_ulogic; + signal CLK_COR_PRECEDENCE_1_BINARY : std_ulogic; + signal CLK_COR_DET_LEN_1_BINARY : std_logic_vector(1 downto 0); + signal CLK_COR_ADJ_LEN_1_BINARY : std_logic_vector(1 downto 0); + signal CLK_COR_KEEP_IDLE_1_BINARY : std_ulogic; + signal CLK_COR_INSERT_IDLE_FLAG_1_BINARY : std_ulogic; + signal CLK_COR_REPEAT_WAIT_1_BINARY : std_logic_vector(4 downto 0); + signal CLK_COR_SEQ_2_USE_1_BINARY : std_ulogic; + signal CLK_COR_SEQ_1_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1_1); + signal CLK_COR_SEQ_1_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2_1); + signal CLK_COR_SEQ_1_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3_1); + signal CLK_COR_SEQ_1_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4_1); + signal CLK_COR_SEQ_2_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1_1); + signal CLK_COR_SEQ_2_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2_1); + signal CLK_COR_SEQ_2_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3_1); + signal CLK_COR_SEQ_2_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4_1); + signal CLK_COR_SEQ_1_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_ENABLE_1); + signal CLK_COR_SEQ_2_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_ENABLE_1); + signal CHAN_BOND_MODE_0_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_LEVEL_0_BINARY : std_logic_vector(2 downto 0); + signal CHAN_BOND_SEQ_LEN_0_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_SEQ_2_USE_0_BINARY : std_ulogic; + signal CHAN_BOND_SEQ_1_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1_0); + signal CHAN_BOND_SEQ_1_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2_0); + signal CHAN_BOND_SEQ_1_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3_0); + signal CHAN_BOND_SEQ_1_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4_0); + signal CHAN_BOND_SEQ_2_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1_0); + signal CHAN_BOND_SEQ_2_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2_0); + signal CHAN_BOND_SEQ_2_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3_0); + signal CHAN_BOND_SEQ_2_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4_0); + signal CHAN_BOND_SEQ_1_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_ENABLE_0); + signal CHAN_BOND_SEQ_2_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_ENABLE_0); + signal CHAN_BOND_1_MAX_SKEW_0_BINARY : std_logic_vector(3 downto 0); + signal CHAN_BOND_2_MAX_SKEW_0_BINARY : std_logic_vector(3 downto 0); + signal CHAN_BOND_MODE_1_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_LEVEL_1_BINARY : std_logic_vector(2 downto 0); + signal CHAN_BOND_SEQ_LEN_1_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_SEQ_2_USE_1_BINARY : std_ulogic; + signal CHAN_BOND_SEQ_1_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1_1); + signal CHAN_BOND_SEQ_1_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2_1); + signal CHAN_BOND_SEQ_1_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3_1); + signal CHAN_BOND_SEQ_1_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4_1); + signal CHAN_BOND_SEQ_2_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1_1); + signal CHAN_BOND_SEQ_2_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2_1); + signal CHAN_BOND_SEQ_2_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3_1); + signal CHAN_BOND_SEQ_2_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4_1); + signal CHAN_BOND_SEQ_1_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_ENABLE_1); + signal CHAN_BOND_SEQ_2_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_ENABLE_1); + signal CHAN_BOND_1_MAX_SKEW_1_BINARY : std_logic_vector(3 downto 0); + signal CHAN_BOND_2_MAX_SKEW_1_BINARY : std_logic_vector(3 downto 0); + signal PCI_EXPRESS_MODE_0_BINARY : std_ulogic; + signal TRANS_TIME_FROM_P2_0_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TRANS_TIME_FROM_P2_0); + signal TRANS_TIME_NON_P2_0_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TRANS_TIME_NON_P2_0); + signal TRANS_TIME_TO_P2_0_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TRANS_TIME_TO_P2_0); + signal PCI_EXPRESS_MODE_1_BINARY : std_ulogic; + signal TRANS_TIME_FROM_P2_1_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TRANS_TIME_FROM_P2_1); + signal TRANS_TIME_NON_P2_1_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TRANS_TIME_NON_P2_1); + signal TRANS_TIME_TO_P2_1_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TRANS_TIME_TO_P2_1); + signal RX_STATUS_FMT_0_BINARY : std_ulogic; + signal TX_BUFFER_USE_0_BINARY : std_ulogic; + signal TX_XCLK_SEL_0_BINARY : std_ulogic; + signal RX_XCLK_SEL_0_BINARY : std_ulogic; + signal RX_STATUS_FMT_1_BINARY : std_ulogic; + signal TX_BUFFER_USE_1_BINARY : std_ulogic; + signal TX_XCLK_SEL_1_BINARY : std_ulogic; + signal RX_XCLK_SEL_1_BINARY : std_ulogic; + signal PRBS_ERR_THRESHOLD_0_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(PRBS_ERR_THRESHOLD_0); + signal RX_SLIDE_MODE_0_BINARY : std_ulogic; + signal PRBS_ERR_THRESHOLD_1_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(PRBS_ERR_THRESHOLD_1); + signal RX_SLIDE_MODE_1_BINARY : std_ulogic; + signal SATA_MIN_BURST_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_BURST_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_INIT_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_INIT_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_WAKE_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_WAKE_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_BURST_VAL_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_BURST_VAL_0); + signal SATA_IDLE_VAL_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_IDLE_VAL_0); + signal COM_BURST_VAL_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(COM_BURST_VAL_0); + signal SATA_MIN_BURST_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_BURST_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_INIT_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_INIT_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_WAKE_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_WAKE_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_BURST_VAL_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_BURST_VAL_1); + signal SATA_IDLE_VAL_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_IDLE_VAL_1); + signal COM_BURST_VAL_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(COM_BURST_VAL_1); + signal CLK25_DIVIDER_BINARY : std_logic_vector(2 downto 0); + signal PCS_COM_CFG_BINARY : std_logic_vector(27 downto 0) := To_StdLogicVector(PCS_COM_CFG); + signal OVERSAMPLE_MODE_BINARY : std_ulogic; + signal SIM_GTPRESET_SPEEDUP_BINARY : std_ulogic; + signal SIM_MODE_BINARY : std_ulogic; + signal SIM_PLL_PERDIV2_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(SIM_PLL_PERDIV2)(8 downto 0); + signal SIM_RECEIVER_DETECT_PASS0_BINARY : std_ulogic; + signal SIM_RECEIVER_DETECT_PASS1_BINARY : std_ulogic; + + signal REFCLKOUT_out : std_ulogic; + signal RXRECCLK0_out : std_ulogic; + signal TXOUTCLK0_out : std_ulogic; + signal RXRECCLK1_out : std_ulogic; + signal TXOUTCLK1_out : std_ulogic; + signal TXP0_out : std_ulogic; + signal TXN0_out : std_ulogic; + signal TXP1_out : std_ulogic; + signal TXN1_out : std_ulogic; + signal RXDATA0_out : std_logic_vector(15 downto 0); + signal RXNOTINTABLE0_out : std_logic_vector(1 downto 0); + signal RXDISPERR0_out : std_logic_vector(1 downto 0); + signal RXCHARISK0_out : std_logic_vector(1 downto 0); + signal RXRUNDISP0_out : std_logic_vector(1 downto 0); + signal RXCHARISCOMMA0_out : std_logic_vector(1 downto 0); + signal RXVALID0_out : std_ulogic; + signal RXDATA1_out : std_logic_vector(15 downto 0); + signal RXNOTINTABLE1_out : std_logic_vector(1 downto 0); + signal RXDISPERR1_out : std_logic_vector(1 downto 0); + signal RXCHARISK1_out : std_logic_vector(1 downto 0); + signal RXRUNDISP1_out : std_logic_vector(1 downto 0); + signal RXCHARISCOMMA1_out : std_logic_vector(1 downto 0); + signal RXVALID1_out : std_ulogic; + signal RESETDONE0_out : std_ulogic; + signal RESETDONE1_out : std_ulogic; + signal TXKERR0_out : std_logic_vector(1 downto 0); + signal TXRUNDISP0_out : std_logic_vector(1 downto 0); + signal TXBUFSTATUS0_out : std_logic_vector(1 downto 0); + signal TXKERR1_out : std_logic_vector(1 downto 0); + signal TXRUNDISP1_out : std_logic_vector(1 downto 0); + signal TXBUFSTATUS1_out : std_logic_vector(1 downto 0); + signal RXCOMMADET0_out : std_ulogic; + signal RXBYTEREALIGN0_out : std_ulogic; + signal RXBYTEISALIGNED0_out : std_ulogic; + signal RXLOSSOFSYNC0_out : std_logic_vector(1 downto 0); + signal RXCHBONDO0_out : std_logic_vector(2 downto 0); + signal RXCHANBONDSEQ0_out : std_ulogic; + signal RXCHANREALIGN0_out : std_ulogic; + signal RXCHANISALIGNED0_out : std_ulogic; + signal RXBUFSTATUS0_out : std_logic_vector(2 downto 0); + signal RXCOMMADET1_out : std_ulogic; + signal RXBYTEREALIGN1_out : std_ulogic; + signal RXBYTEISALIGNED1_out : std_ulogic; + signal RXLOSSOFSYNC1_out : std_logic_vector(1 downto 0); + signal RXCHBONDO1_out : std_logic_vector(2 downto 0); + signal RXCHANBONDSEQ1_out : std_ulogic; + signal RXCHANREALIGN1_out : std_ulogic; + signal RXCHANISALIGNED1_out : std_ulogic; + signal RXBUFSTATUS1_out : std_logic_vector(2 downto 0); + signal PHYSTATUS0_out : std_ulogic; + signal PHYSTATUS1_out : std_ulogic; + signal RXELECIDLE0_out : std_ulogic; + signal RXSTATUS0_out : std_logic_vector(2 downto 0); + signal RXCLKCORCNT0_out : std_logic_vector(2 downto 0); + signal RXELECIDLE1_out : std_ulogic; + signal RXSTATUS1_out : std_logic_vector(2 downto 0); + signal RXCLKCORCNT1_out : std_logic_vector(2 downto 0); + signal PLLLKDET_out : std_ulogic; + signal RXPRBSERR0_out : std_ulogic; + signal RXPRBSERR1_out : std_ulogic; + signal DO_out : std_logic_vector(15 downto 0); + signal DRDY_out : std_ulogic; + signal RXOVERSAMPLEERR0_out : std_ulogic; + signal RXOVERSAMPLEERR1_out : std_ulogic; + signal REFCLKOUT_outdelay : std_logic; + signal RXRECCLK0_outdelay : std_logic; + signal TXOUTCLK0_outdelay : std_logic; + signal RXRECCLK1_outdelay : std_logic; + signal TXOUTCLK1_outdelay : std_logic; + signal RXCLKCORCNT0_outdelay : std_logic_vector(2 downto 0); + signal RXCLKCORCNT1_outdelay : std_logic_vector(2 downto 0); + signal TXP0_outdelay : std_logic; + signal TXN0_outdelay : std_logic; + signal TXP1_outdelay : std_logic; + signal TXN1_outdelay : std_logic; + signal RXDATA0_outdelay : std_logic_vector(15 downto 0); + signal RXNOTINTABLE0_outdelay : std_logic_vector(1 downto 0); + signal RXDISPERR0_outdelay : std_logic_vector(1 downto 0); + signal RXCHARISK0_outdelay : std_logic_vector(1 downto 0); + signal RXRUNDISP0_outdelay : std_logic_vector(1 downto 0); + signal RXCHARISCOMMA0_outdelay : std_logic_vector(1 downto 0); + signal RXVALID0_outdelay : std_logic; + signal RXDATA1_outdelay : std_logic_vector(15 downto 0); + signal RXNOTINTABLE1_outdelay : std_logic_vector(1 downto 0); + signal RXDISPERR1_outdelay : std_logic_vector(1 downto 0); + signal RXCHARISK1_outdelay : std_logic_vector(1 downto 0); + signal RXRUNDISP1_outdelay : std_logic_vector(1 downto 0); + signal RXCHARISCOMMA1_outdelay : std_logic_vector(1 downto 0); + signal RXVALID1_outdelay : std_logic; + signal RESETDONE0_outdelay : std_logic; + signal RESETDONE1_outdelay : std_logic; + signal TXKERR0_outdelay : std_logic_vector(1 downto 0); + signal TXRUNDISP0_outdelay : std_logic_vector(1 downto 0); + signal TXBUFSTATUS0_outdelay : std_logic_vector(1 downto 0); + signal TXKERR1_outdelay : std_logic_vector(1 downto 0); + signal TXRUNDISP1_outdelay : std_logic_vector(1 downto 0); + signal TXBUFSTATUS1_outdelay : std_logic_vector(1 downto 0); + signal RXCOMMADET0_outdelay : std_logic; + signal RXBYTEREALIGN0_outdelay : std_logic; + signal RXBYTEISALIGNED0_outdelay : std_logic; + signal RXLOSSOFSYNC0_outdelay : std_logic_vector(1 downto 0); + signal RXCHBONDO0_outdelay : std_logic_vector(2 downto 0); + signal RXCHANBONDSEQ0_outdelay : std_logic; + signal RXCHANREALIGN0_outdelay : std_logic; + signal RXCHANISALIGNED0_outdelay : std_logic; + signal RXBUFSTATUS0_outdelay : std_logic_vector(2 downto 0); + signal RXCOMMADET1_outdelay : std_logic; + signal RXBYTEREALIGN1_outdelay : std_logic; + signal RXBYTEISALIGNED1_outdelay : std_logic; + signal RXLOSSOFSYNC1_outdelay : std_logic_vector(1 downto 0); + signal RXCHBONDO1_outdelay : std_logic_vector(2 downto 0); + signal RXCHANBONDSEQ1_outdelay : std_logic; + signal RXCHANREALIGN1_outdelay : std_logic; + signal RXCHANISALIGNED1_outdelay : std_logic; + signal RXBUFSTATUS1_outdelay : std_logic_vector(2 downto 0); + signal PHYSTATUS0_outdelay : std_logic; + signal PHYSTATUS1_outdelay : std_logic; + signal RXELECIDLE0_outdelay : std_logic; + signal RXSTATUS0_outdelay : std_logic_vector(2 downto 0); + signal RXELECIDLE1_outdelay : std_logic; + signal RXSTATUS1_outdelay : std_logic_vector(2 downto 0); + signal PLLLKDET_outdelay : std_logic; + signal RXPRBSERR0_outdelay : std_logic; + signal RXPRBSERR1_outdelay : std_logic; + signal DO_outdelay : std_logic_vector(15 downto 0); + signal DRDY_outdelay : std_logic; + signal RXOVERSAMPLEERR0_outdelay : std_logic; + signal RXOVERSAMPLEERR1_outdelay : std_logic; + + signal CLKIN_ipd : std_ulogic; + signal TXUSRCLK0_ipd : std_ulogic; + signal TXUSRCLK20_ipd : std_ulogic; + signal RXUSRCLK0_ipd : std_ulogic; + signal RXUSRCLK20_ipd : std_ulogic; + signal TXUSRCLK1_ipd : std_ulogic; + signal TXUSRCLK21_ipd : std_ulogic; + signal RXUSRCLK1_ipd : std_ulogic; + signal RXUSRCLK21_ipd : std_ulogic; + signal RXP0_ipd : std_ulogic; + signal RXN0_ipd : std_ulogic; + signal TXDATA0_ipd : std_logic_vector(15 downto 0); + signal TXBYPASS8B10B0_ipd : std_logic_vector(1 downto 0); + signal TXCHARISK0_ipd : std_logic_vector(1 downto 0); + signal TXCHARDISPMODE0_ipd : std_logic_vector(1 downto 0); + signal TXCHARDISPVAL0_ipd : std_logic_vector(1 downto 0); + signal RXP1_ipd : std_ulogic; + signal RXN1_ipd : std_ulogic; + signal TXDATA1_ipd : std_logic_vector(15 downto 0); + signal TXBYPASS8B10B1_ipd : std_logic_vector(1 downto 0); + signal TXCHARISK1_ipd : std_logic_vector(1 downto 0); + signal TXCHARDISPMODE1_ipd : std_logic_vector(1 downto 0); + signal TXCHARDISPVAL1_ipd : std_logic_vector(1 downto 0); + signal GTPRESET_ipd : std_ulogic; + signal RXCDRRESET0_ipd : std_ulogic; + signal TXRESET0_ipd : std_ulogic; + signal RXRESET0_ipd : std_ulogic; + signal RXBUFRESET0_ipd : std_ulogic; + signal RXCDRRESET1_ipd : std_ulogic; + signal TXRESET1_ipd : std_ulogic; + signal RXRESET1_ipd : std_ulogic; + signal RXBUFRESET1_ipd : std_ulogic; + signal TXPOWERDOWN0_ipd : std_logic_vector(1 downto 0); + signal RXPOWERDOWN0_ipd : std_logic_vector(1 downto 0); + signal TXPOWERDOWN1_ipd : std_logic_vector(1 downto 0); + signal RXPOWERDOWN1_ipd : std_logic_vector(1 downto 0); + signal PLLPOWERDOWN_ipd : std_ulogic; + signal REFCLKPWRDNB_ipd : std_ulogic; + signal LOOPBACK0_ipd : std_logic_vector(2 downto 0); + signal LOOPBACK1_ipd : std_logic_vector(2 downto 0); + signal TXDIFFCTRL0_ipd : std_logic_vector(2 downto 0); + signal TXBUFDIFFCTRL0_ipd : std_logic_vector(2 downto 0); + signal TXPREEMPHASIS0_ipd : std_logic_vector(2 downto 0); + signal TXDIFFCTRL1_ipd : std_logic_vector(2 downto 0); + signal TXBUFDIFFCTRL1_ipd : std_logic_vector(2 downto 0); + signal TXPREEMPHASIS1_ipd : std_logic_vector(2 downto 0); + signal RXENEQB0_ipd : std_ulogic; + signal RXEQMIX0_ipd : std_logic_vector(1 downto 0); + signal RXEQPOLE0_ipd : std_logic_vector(3 downto 0); + signal RXENEQB1_ipd : std_ulogic; + signal RXEQMIX1_ipd : std_logic_vector(1 downto 0); + signal RXEQPOLE1_ipd : std_logic_vector(3 downto 0); + signal INTDATAWIDTH_ipd : std_ulogic; + signal TXDATAWIDTH0_ipd : std_ulogic; + signal TXDATAWIDTH1_ipd : std_ulogic; + signal TXENPMAPHASEALIGN_ipd : std_ulogic; + signal TXPMASETPHASE_ipd : std_ulogic; + signal RXPMASETPHASE0_ipd : std_ulogic; + signal RXPMASETPHASE1_ipd : std_ulogic; + signal TXENC8B10BUSE0_ipd : std_ulogic; + signal TXPOLARITY0_ipd : std_ulogic; + signal TXINHIBIT0_ipd : std_ulogic; + signal TXENC8B10BUSE1_ipd : std_ulogic; + signal TXPOLARITY1_ipd : std_ulogic; + signal TXINHIBIT1_ipd : std_ulogic; + signal RXPOLARITY0_ipd : std_ulogic; + signal RXENPCOMMAALIGN0_ipd : std_ulogic; + signal RXENMCOMMAALIGN0_ipd : std_ulogic; + signal RXSLIDE0_ipd : std_ulogic; + signal RXCOMMADETUSE0_ipd : std_ulogic; + signal RXDEC8B10BUSE0_ipd : std_ulogic; + signal RXENCHANSYNC0_ipd : std_ulogic; + signal RXCHBONDI0_ipd : std_logic_vector(2 downto 0); + signal RXDATAWIDTH0_ipd : std_ulogic; + signal RXPOLARITY1_ipd : std_ulogic; + signal RXENPCOMMAALIGN1_ipd : std_ulogic; + signal RXENMCOMMAALIGN1_ipd : std_ulogic; + signal RXSLIDE1_ipd : std_ulogic; + signal RXCOMMADETUSE1_ipd : std_ulogic; + signal RXDEC8B10BUSE1_ipd : std_ulogic; + signal RXENCHANSYNC1_ipd : std_ulogic; + signal RXCHBONDI1_ipd : std_logic_vector(2 downto 0); + signal RXDATAWIDTH1_ipd : std_ulogic; + signal TXELECIDLE0_ipd : std_ulogic; + signal TXDETECTRX0_ipd : std_ulogic; + signal TXELECIDLE1_ipd : std_ulogic; + signal TXDETECTRX1_ipd : std_ulogic; + signal TXCOMSTART0_ipd : std_ulogic; + signal TXCOMTYPE0_ipd : std_ulogic; + signal TXCOMSTART1_ipd : std_ulogic; + signal TXCOMTYPE1_ipd : std_ulogic; + signal PLLLKDETEN_ipd : std_ulogic; + signal TXENPRBSTST0_ipd : std_logic_vector(1 downto 0); + signal RXENPRBSTST0_ipd : std_logic_vector(1 downto 0); + signal PRBSCNTRESET0_ipd : std_ulogic; + signal TXENPRBSTST1_ipd : std_logic_vector(1 downto 0); + signal RXENPRBSTST1_ipd : std_logic_vector(1 downto 0); + signal PRBSCNTRESET1_ipd : std_ulogic; + signal DCLK_ipd : std_ulogic; + signal DADDR_ipd : std_logic_vector(6 downto 0); + signal DI_ipd : std_logic_vector(15 downto 0); + signal DEN_ipd : std_ulogic; + signal DWE_ipd : std_ulogic; + signal RXENSAMPLEALIGN0_ipd : std_ulogic; + signal RXENSAMPLEALIGN1_ipd : std_ulogic; + signal RXELECIDLERESET0_ipd : std_ulogic; + signal RXELECIDLERESET1_ipd : std_ulogic; + signal RXENELECIDLERESETB_ipd : std_ulogic; + signal GTPTEST_ipd : std_logic_vector(3 downto 0); + + signal CLKIN_indelay : std_ulogic; + signal TXUSRCLK0_indelay : std_ulogic; + signal TXUSRCLK20_indelay : std_ulogic; + signal RXUSRCLK0_indelay : std_ulogic; + signal RXUSRCLK20_indelay : std_ulogic; + signal TXUSRCLK1_indelay : std_ulogic; + signal TXUSRCLK21_indelay : std_ulogic; + signal RXUSRCLK1_indelay : std_ulogic; + signal RXUSRCLK21_indelay : std_ulogic; + signal RXP0_indelay : std_ulogic; + signal RXN0_indelay : std_ulogic; + signal TXDATA0_indelay : std_logic_vector(15 downto 0); + signal TXBYPASS8B10B0_indelay : std_logic_vector(1 downto 0); + signal TXCHARISK0_indelay : std_logic_vector(1 downto 0); + signal TXCHARDISPMODE0_indelay : std_logic_vector(1 downto 0); + signal TXCHARDISPVAL0_indelay : std_logic_vector(1 downto 0); + signal RXP1_indelay : std_ulogic; + signal RXN1_indelay : std_ulogic; + signal TXDATA1_indelay : std_logic_vector(15 downto 0); + signal TXBYPASS8B10B1_indelay : std_logic_vector(1 downto 0); + signal TXCHARISK1_indelay : std_logic_vector(1 downto 0); + signal TXCHARDISPMODE1_indelay : std_logic_vector(1 downto 0); + signal TXCHARDISPVAL1_indelay : std_logic_vector(1 downto 0); + signal GTPRESET_indelay : std_ulogic; + signal RXCDRRESET0_indelay : std_ulogic; + signal TXRESET0_indelay : std_ulogic; + signal RXRESET0_indelay : std_ulogic; + signal RXBUFRESET0_indelay : std_ulogic; + signal RXCDRRESET1_indelay : std_ulogic; + signal TXRESET1_indelay : std_ulogic; + signal RXRESET1_indelay : std_ulogic; + signal RXBUFRESET1_indelay : std_ulogic; + signal TXPOWERDOWN0_indelay : std_logic_vector(1 downto 0); + signal RXPOWERDOWN0_indelay : std_logic_vector(1 downto 0); + signal TXPOWERDOWN1_indelay : std_logic_vector(1 downto 0); + signal RXPOWERDOWN1_indelay : std_logic_vector(1 downto 0); + signal PLLPOWERDOWN_indelay : std_ulogic; + signal REFCLKPWRDNB_indelay : std_ulogic; + signal LOOPBACK0_indelay : std_logic_vector(2 downto 0); + signal LOOPBACK1_indelay : std_logic_vector(2 downto 0); + signal TXDIFFCTRL0_indelay : std_logic_vector(2 downto 0); + signal TXBUFDIFFCTRL0_indelay : std_logic_vector(2 downto 0); + signal TXPREEMPHASIS0_indelay : std_logic_vector(2 downto 0); + signal TXDIFFCTRL1_indelay : std_logic_vector(2 downto 0); + signal TXBUFDIFFCTRL1_indelay : std_logic_vector(2 downto 0); + signal TXPREEMPHASIS1_indelay : std_logic_vector(2 downto 0); + signal RXENEQB0_indelay : std_ulogic; + signal RXEQMIX0_indelay : std_logic_vector(1 downto 0); + signal RXEQPOLE0_indelay : std_logic_vector(3 downto 0); + signal RXENEQB1_indelay : std_ulogic; + signal RXEQMIX1_indelay : std_logic_vector(1 downto 0); + signal RXEQPOLE1_indelay : std_logic_vector(3 downto 0); + signal INTDATAWIDTH_indelay : std_ulogic; + signal TXDATAWIDTH0_indelay : std_ulogic; + signal TXDATAWIDTH1_indelay : std_ulogic; + signal TXENPMAPHASEALIGN_indelay : std_ulogic; + signal TXPMASETPHASE_indelay : std_ulogic; + signal RXPMASETPHASE0_indelay : std_ulogic; + signal RXPMASETPHASE1_indelay : std_ulogic; + signal TXENC8B10BUSE0_indelay : std_ulogic; + signal TXPOLARITY0_indelay : std_ulogic; + signal TXINHIBIT0_indelay : std_ulogic; + signal TXENC8B10BUSE1_indelay : std_ulogic; + signal TXPOLARITY1_indelay : std_ulogic; + signal TXINHIBIT1_indelay : std_ulogic; + signal RXPOLARITY0_indelay : std_ulogic; + signal RXENPCOMMAALIGN0_indelay : std_ulogic; + signal RXENMCOMMAALIGN0_indelay : std_ulogic; + signal RXSLIDE0_indelay : std_ulogic; + signal RXCOMMADETUSE0_indelay : std_ulogic; + signal RXDEC8B10BUSE0_indelay : std_ulogic; + signal RXENCHANSYNC0_indelay : std_ulogic; + signal RXCHBONDI0_indelay : std_logic_vector(2 downto 0); + signal RXDATAWIDTH0_indelay : std_ulogic; + signal RXPOLARITY1_indelay : std_ulogic; + signal RXENPCOMMAALIGN1_indelay : std_ulogic; + signal RXENMCOMMAALIGN1_indelay : std_ulogic; + signal RXSLIDE1_indelay : std_ulogic; + signal RXCOMMADETUSE1_indelay : std_ulogic; + signal RXDEC8B10BUSE1_indelay : std_ulogic; + signal RXENCHANSYNC1_indelay : std_ulogic; + signal RXCHBONDI1_indelay : std_logic_vector(2 downto 0); + signal RXDATAWIDTH1_indelay : std_ulogic; + signal TXELECIDLE0_indelay : std_ulogic; + signal TXDETECTRX0_indelay : std_ulogic; + signal TXELECIDLE1_indelay : std_ulogic; + signal TXDETECTRX1_indelay : std_ulogic; + signal TXCOMSTART0_indelay : std_ulogic; + signal TXCOMTYPE0_indelay : std_ulogic; + signal TXCOMSTART1_indelay : std_ulogic; + signal TXCOMTYPE1_indelay : std_ulogic; + signal PLLLKDETEN_indelay : std_ulogic; + signal TXENPRBSTST0_indelay : std_logic_vector(1 downto 0); + signal RXENPRBSTST0_indelay : std_logic_vector(1 downto 0); + signal PRBSCNTRESET0_indelay : std_ulogic; + signal TXENPRBSTST1_indelay : std_logic_vector(1 downto 0); + signal RXENPRBSTST1_indelay : std_logic_vector(1 downto 0); + signal PRBSCNTRESET1_indelay : std_ulogic; + signal DCLK_indelay : std_ulogic; + signal DADDR_indelay : std_logic_vector(6 downto 0); + signal DI_indelay : std_logic_vector(15 downto 0); + signal DEN_indelay : std_ulogic; + signal DWE_indelay : std_ulogic; + signal RXENSAMPLEALIGN0_indelay : std_ulogic; + signal RXENSAMPLEALIGN1_indelay : std_ulogic; + signal RXELECIDLERESET0_indelay : std_ulogic; + signal RXELECIDLERESET1_indelay : std_ulogic; + signal RXENELECIDLERESETB_indelay : std_ulogic; + signal GTPTEST_indelay : std_logic_vector(3 downto 0); + +begin + + REFCLKOUT_out <= REFCLKOUT_outdelay after CLK_DELAY; + RXCLKCORCNT0_out <= RXCLKCORCNT0_outdelay after CLK_DELAY; + RXCLKCORCNT1_out <= RXCLKCORCNT1_outdelay after CLK_DELAY; + RXRECCLK0_out <= RXRECCLK0_outdelay after CLK_DELAY; + RXRECCLK1_out <= RXRECCLK1_outdelay after CLK_DELAY; + TXOUTCLK0_out <= TXOUTCLK0_outdelay after CLK_DELAY; + TXOUTCLK1_out <= TXOUTCLK1_outdelay after CLK_DELAY; + + DO_out <= DO_outdelay after OUT_DELAY; + DRDY_out <= DRDY_outdelay after OUT_DELAY; + PHYSTATUS0_out <= PHYSTATUS0_outdelay after OUT_DELAY; + PHYSTATUS1_out <= PHYSTATUS1_outdelay after OUT_DELAY; + PLLLKDET_out <= PLLLKDET_outdelay after OUT_DELAY; + RESETDONE0_out <= RESETDONE0_outdelay after OUT_DELAY; + RESETDONE1_out <= RESETDONE1_outdelay after OUT_DELAY; + RXBUFSTATUS0_out <= RXBUFSTATUS0_outdelay after OUT_DELAY; + RXBUFSTATUS1_out <= RXBUFSTATUS1_outdelay after OUT_DELAY; + RXBYTEISALIGNED0_out <= RXBYTEISALIGNED0_outdelay after OUT_DELAY; + RXBYTEISALIGNED1_out <= RXBYTEISALIGNED1_outdelay after OUT_DELAY; + RXBYTEREALIGN0_out <= RXBYTEREALIGN0_outdelay after OUT_DELAY; + RXBYTEREALIGN1_out <= RXBYTEREALIGN1_outdelay after OUT_DELAY; + RXCHANBONDSEQ0_out <= RXCHANBONDSEQ0_outdelay after OUT_DELAY; + RXCHANBONDSEQ1_out <= RXCHANBONDSEQ1_outdelay after OUT_DELAY; + RXCHANISALIGNED0_out <= RXCHANISALIGNED0_outdelay after OUT_DELAY; + RXCHANISALIGNED1_out <= RXCHANISALIGNED1_outdelay after OUT_DELAY; + RXCHANREALIGN0_out <= RXCHANREALIGN0_outdelay after OUT_DELAY; + RXCHANREALIGN1_out <= RXCHANREALIGN1_outdelay after OUT_DELAY; + RXCHARISCOMMA0_out <= RXCHARISCOMMA0_outdelay after OUT_DELAY; + RXCHARISCOMMA1_out <= RXCHARISCOMMA1_outdelay after OUT_DELAY; + RXCHARISK0_out <= RXCHARISK0_outdelay after OUT_DELAY; + RXCHARISK1_out <= RXCHARISK1_outdelay after OUT_DELAY; + RXCHBONDO0_out <= RXCHBONDO0_outdelay after OUT_DELAY; + RXCHBONDO1_out <= RXCHBONDO1_outdelay after OUT_DELAY; + RXCOMMADET0_out <= RXCOMMADET0_outdelay after OUT_DELAY; + RXCOMMADET1_out <= RXCOMMADET1_outdelay after OUT_DELAY; + RXDATA0_out <= RXDATA0_outdelay after OUT_DELAY; + RXDATA1_out <= RXDATA1_outdelay after OUT_DELAY; + RXDISPERR0_out <= RXDISPERR0_outdelay after OUT_DELAY; + RXDISPERR1_out <= RXDISPERR1_outdelay after OUT_DELAY; + RXELECIDLE0_out <= RXELECIDLE0_outdelay after OUT_DELAY; + RXELECIDLE1_out <= RXELECIDLE1_outdelay after OUT_DELAY; + RXLOSSOFSYNC0_out <= RXLOSSOFSYNC0_outdelay after OUT_DELAY; + RXLOSSOFSYNC1_out <= RXLOSSOFSYNC1_outdelay after OUT_DELAY; + RXNOTINTABLE0_out <= RXNOTINTABLE0_outdelay after OUT_DELAY; + RXNOTINTABLE1_out <= RXNOTINTABLE1_outdelay after OUT_DELAY; + RXOVERSAMPLEERR0_out <= RXOVERSAMPLEERR0_outdelay after OUT_DELAY; + RXOVERSAMPLEERR1_out <= RXOVERSAMPLEERR1_outdelay after OUT_DELAY; + RXPRBSERR0_out <= RXPRBSERR0_outdelay after OUT_DELAY; + RXPRBSERR1_out <= RXPRBSERR1_outdelay after OUT_DELAY; + RXRUNDISP0_out <= RXRUNDISP0_outdelay after OUT_DELAY; + RXRUNDISP1_out <= RXRUNDISP1_outdelay after OUT_DELAY; + RXSTATUS0_out <= RXSTATUS0_outdelay after OUT_DELAY; + RXSTATUS1_out <= RXSTATUS1_outdelay after OUT_DELAY; + RXVALID0_out <= RXVALID0_outdelay after OUT_DELAY; + RXVALID1_out <= RXVALID1_outdelay after OUT_DELAY; + TXBUFSTATUS0_out <= TXBUFSTATUS0_outdelay after OUT_DELAY; + TXBUFSTATUS1_out <= TXBUFSTATUS1_outdelay after OUT_DELAY; + TXKERR0_out <= TXKERR0_outdelay after OUT_DELAY; + TXKERR1_out <= TXKERR1_outdelay after OUT_DELAY; + TXN0_out <= TXN0_outdelay after OUT_DELAY; + TXN1_out <= TXN1_outdelay after OUT_DELAY; + TXP0_out <= TXP0_outdelay after OUT_DELAY; + TXP1_out <= TXP1_outdelay after OUT_DELAY; + TXRUNDISP0_out <= TXRUNDISP0_outdelay after OUT_DELAY; + TXRUNDISP1_out <= TXRUNDISP1_outdelay after OUT_DELAY; + + CLKIN_ipd <= CLKIN after CLK_DELAY; + DCLK_ipd <= DCLK after CLK_DELAY; + RXUSRCLK0_ipd <= RXUSRCLK0 after CLK_DELAY; + RXUSRCLK1_ipd <= RXUSRCLK1 after CLK_DELAY; + RXUSRCLK20_ipd <= RXUSRCLK20 after CLK_DELAY; + RXUSRCLK21_ipd <= RXUSRCLK21 after CLK_DELAY; + TXUSRCLK0_ipd <= TXUSRCLK0 after CLK_DELAY; + TXUSRCLK1_ipd <= TXUSRCLK1 after CLK_DELAY; + TXUSRCLK20_ipd <= TXUSRCLK20 after CLK_DELAY; + TXUSRCLK21_ipd <= TXUSRCLK21 after CLK_DELAY; + + DADDR_ipd <= DADDR after CLK_DELAY; + DEN_ipd <= DEN after CLK_DELAY; + DI_ipd <= DI after CLK_DELAY; + DWE_ipd <= DWE after CLK_DELAY; + GTPRESET_ipd <= GTPRESET after CLK_DELAY; + GTPTEST_ipd <= GTPTEST after CLK_DELAY; + INTDATAWIDTH_ipd <= INTDATAWIDTH after CLK_DELAY; + LOOPBACK0_ipd <= LOOPBACK0 after CLK_DELAY; + LOOPBACK1_ipd <= LOOPBACK1 after CLK_DELAY; + PLLLKDETEN_ipd <= PLLLKDETEN after CLK_DELAY; + PLLPOWERDOWN_ipd <= PLLPOWERDOWN after CLK_DELAY; + PRBSCNTRESET0_ipd <= PRBSCNTRESET0 after CLK_DELAY; + PRBSCNTRESET1_ipd <= PRBSCNTRESET1 after CLK_DELAY; + REFCLKPWRDNB_ipd <= REFCLKPWRDNB after CLK_DELAY; + RXBUFRESET0_ipd <= RXBUFRESET0 after CLK_DELAY; + RXBUFRESET1_ipd <= RXBUFRESET1 after CLK_DELAY; + RXCDRRESET0_ipd <= RXCDRRESET0 after CLK_DELAY; + RXCDRRESET1_ipd <= RXCDRRESET1 after CLK_DELAY; + RXCHBONDI0_ipd <= RXCHBONDI0 after CLK_DELAY; + RXCHBONDI1_ipd <= RXCHBONDI1 after CLK_DELAY; + RXCOMMADETUSE0_ipd <= RXCOMMADETUSE0 after CLK_DELAY; + RXCOMMADETUSE1_ipd <= RXCOMMADETUSE1 after CLK_DELAY; + RXDATAWIDTH0_ipd <= RXDATAWIDTH0 after CLK_DELAY; + RXDATAWIDTH1_ipd <= RXDATAWIDTH1 after CLK_DELAY; + RXDEC8B10BUSE0_ipd <= RXDEC8B10BUSE0 after CLK_DELAY; + RXDEC8B10BUSE1_ipd <= RXDEC8B10BUSE1 after CLK_DELAY; + RXELECIDLERESET0_ipd <= RXELECIDLERESET0 after CLK_DELAY; + RXELECIDLERESET1_ipd <= RXELECIDLERESET1 after CLK_DELAY; + RXENCHANSYNC0_ipd <= RXENCHANSYNC0 after CLK_DELAY; + RXENCHANSYNC1_ipd <= RXENCHANSYNC1 after CLK_DELAY; + RXENELECIDLERESETB_ipd <= RXENELECIDLERESETB after CLK_DELAY; + RXENEQB0_ipd <= RXENEQB0 after CLK_DELAY; + RXENEQB1_ipd <= RXENEQB1 after CLK_DELAY; + RXENMCOMMAALIGN0_ipd <= RXENMCOMMAALIGN0 after CLK_DELAY; + RXENMCOMMAALIGN1_ipd <= RXENMCOMMAALIGN1 after CLK_DELAY; + RXENPCOMMAALIGN0_ipd <= RXENPCOMMAALIGN0 after CLK_DELAY; + RXENPCOMMAALIGN1_ipd <= RXENPCOMMAALIGN1 after CLK_DELAY; + RXENPRBSTST0_ipd <= RXENPRBSTST0 after CLK_DELAY; + RXENPRBSTST1_ipd <= RXENPRBSTST1 after CLK_DELAY; + RXENSAMPLEALIGN0_ipd <= RXENSAMPLEALIGN0 after CLK_DELAY; + RXENSAMPLEALIGN1_ipd <= RXENSAMPLEALIGN1 after CLK_DELAY; + RXEQMIX0_ipd <= RXEQMIX0 after CLK_DELAY; + RXEQMIX1_ipd <= RXEQMIX1 after CLK_DELAY; + RXEQPOLE0_ipd <= RXEQPOLE0 after CLK_DELAY; + RXEQPOLE1_ipd <= RXEQPOLE1 after CLK_DELAY; + RXN0_ipd <= RXN0 after CLK_DELAY; + RXN1_ipd <= RXN1 after CLK_DELAY; + RXP0_ipd <= RXP0 after CLK_DELAY; + RXP1_ipd <= RXP1 after CLK_DELAY; + RXPMASETPHASE0_ipd <= RXPMASETPHASE0 after CLK_DELAY; + RXPMASETPHASE1_ipd <= RXPMASETPHASE1 after CLK_DELAY; + RXPOLARITY0_ipd <= RXPOLARITY0 after CLK_DELAY; + RXPOLARITY1_ipd <= RXPOLARITY1 after CLK_DELAY; + RXPOWERDOWN0_ipd <= RXPOWERDOWN0 after CLK_DELAY; + RXPOWERDOWN1_ipd <= RXPOWERDOWN1 after CLK_DELAY; + RXRESET0_ipd <= RXRESET0 after CLK_DELAY; + RXRESET1_ipd <= RXRESET1 after CLK_DELAY; + RXSLIDE0_ipd <= RXSLIDE0 after CLK_DELAY; + RXSLIDE1_ipd <= RXSLIDE1 after CLK_DELAY; + TXBUFDIFFCTRL0_ipd <= TXBUFDIFFCTRL0 after CLK_DELAY; + TXBUFDIFFCTRL1_ipd <= TXBUFDIFFCTRL1 after CLK_DELAY; + TXBYPASS8B10B0_ipd <= TXBYPASS8B10B0 after CLK_DELAY; + TXBYPASS8B10B1_ipd <= TXBYPASS8B10B1 after CLK_DELAY; + TXCHARDISPMODE0_ipd <= TXCHARDISPMODE0 after CLK_DELAY; + TXCHARDISPMODE1_ipd <= TXCHARDISPMODE1 after CLK_DELAY; + TXCHARDISPVAL0_ipd <= TXCHARDISPVAL0 after CLK_DELAY; + TXCHARDISPVAL1_ipd <= TXCHARDISPVAL1 after CLK_DELAY; + TXCHARISK0_ipd <= TXCHARISK0 after CLK_DELAY; + TXCHARISK1_ipd <= TXCHARISK1 after CLK_DELAY; + TXCOMSTART0_ipd <= TXCOMSTART0 after CLK_DELAY; + TXCOMSTART1_ipd <= TXCOMSTART1 after CLK_DELAY; + TXCOMTYPE0_ipd <= TXCOMTYPE0 after CLK_DELAY; + TXCOMTYPE1_ipd <= TXCOMTYPE1 after CLK_DELAY; + TXDATA0_ipd <= TXDATA0 after CLK_DELAY; + TXDATA1_ipd <= TXDATA1 after CLK_DELAY; + TXDATAWIDTH0_ipd <= TXDATAWIDTH0 after CLK_DELAY; + TXDATAWIDTH1_ipd <= TXDATAWIDTH1 after CLK_DELAY; + TXDETECTRX0_ipd <= TXDETECTRX0 after CLK_DELAY; + TXDETECTRX1_ipd <= TXDETECTRX1 after CLK_DELAY; + TXDIFFCTRL0_ipd <= TXDIFFCTRL0 after CLK_DELAY; + TXDIFFCTRL1_ipd <= TXDIFFCTRL1 after CLK_DELAY; + TXELECIDLE0_ipd <= TXELECIDLE0 after CLK_DELAY; + TXELECIDLE1_ipd <= TXELECIDLE1 after CLK_DELAY; + TXENC8B10BUSE0_ipd <= TXENC8B10BUSE0 after CLK_DELAY; + TXENC8B10BUSE1_ipd <= TXENC8B10BUSE1 after CLK_DELAY; + TXENPMAPHASEALIGN_ipd <= TXENPMAPHASEALIGN after CLK_DELAY; + TXENPRBSTST0_ipd <= TXENPRBSTST0 after CLK_DELAY; + TXENPRBSTST1_ipd <= TXENPRBSTST1 after CLK_DELAY; + TXINHIBIT0_ipd <= TXINHIBIT0 after CLK_DELAY; + TXINHIBIT1_ipd <= TXINHIBIT1 after CLK_DELAY; + TXPMASETPHASE_ipd <= TXPMASETPHASE after CLK_DELAY; + TXPOLARITY0_ipd <= TXPOLARITY0 after CLK_DELAY; + TXPOLARITY1_ipd <= TXPOLARITY1 after CLK_DELAY; + TXPOWERDOWN0_ipd <= TXPOWERDOWN0 after CLK_DELAY; + TXPOWERDOWN1_ipd <= TXPOWERDOWN1 after CLK_DELAY; + TXPREEMPHASIS0_ipd <= TXPREEMPHASIS0 after CLK_DELAY; + TXPREEMPHASIS1_ipd <= TXPREEMPHASIS1 after CLK_DELAY; + TXRESET0_ipd <= TXRESET0 after CLK_DELAY; + TXRESET1_ipd <= TXRESET1 after CLK_DELAY; + + CLKIN_indelay <= CLKIN_ipd after CLK_DELAY; + DCLK_indelay <= DCLK_ipd after CLK_DELAY; + RXUSRCLK0_indelay <= RXUSRCLK0_ipd after CLK_DELAY; + RXUSRCLK1_indelay <= RXUSRCLK1_ipd after CLK_DELAY; + RXUSRCLK20_indelay <= RXUSRCLK20_ipd after CLK_DELAY; + RXUSRCLK21_indelay <= RXUSRCLK21_ipd after CLK_DELAY; + TXUSRCLK0_indelay <= TXUSRCLK0_ipd after CLK_DELAY; + TXUSRCLK1_indelay <= TXUSRCLK1_ipd after CLK_DELAY; + TXUSRCLK20_indelay <= TXUSRCLK20_ipd after CLK_DELAY; + TXUSRCLK21_indelay <= TXUSRCLK21_ipd after CLK_DELAY; + + DADDR_indelay <= DADDR_ipd after IN_DELAY; + DEN_indelay <= DEN_ipd after IN_DELAY; + DI_indelay <= DI_ipd after IN_DELAY; + DWE_indelay <= DWE_ipd after IN_DELAY; + GTPRESET_indelay <= GTPRESET_ipd after IN_DELAY; + GTPTEST_indelay <= GTPTEST_ipd after IN_DELAY; + INTDATAWIDTH_indelay <= INTDATAWIDTH_ipd after IN_DELAY; + LOOPBACK0_indelay <= LOOPBACK0_ipd after IN_DELAY; + LOOPBACK1_indelay <= LOOPBACK1_ipd after IN_DELAY; + PLLLKDETEN_indelay <= PLLLKDETEN_ipd after IN_DELAY; + PLLPOWERDOWN_indelay <= PLLPOWERDOWN_ipd after IN_DELAY; + PRBSCNTRESET0_indelay <= PRBSCNTRESET0_ipd after IN_DELAY; + PRBSCNTRESET1_indelay <= PRBSCNTRESET1_ipd after IN_DELAY; + REFCLKPWRDNB_indelay <= REFCLKPWRDNB_ipd after IN_DELAY; + RXBUFRESET0_indelay <= RXBUFRESET0_ipd after IN_DELAY; + RXBUFRESET1_indelay <= RXBUFRESET1_ipd after IN_DELAY; + RXCDRRESET0_indelay <= RXCDRRESET0_ipd after IN_DELAY; + RXCDRRESET1_indelay <= RXCDRRESET1_ipd after IN_DELAY; + RXCHBONDI0_indelay <= RXCHBONDI0_ipd after IN_DELAY; + RXCHBONDI1_indelay <= RXCHBONDI1_ipd after IN_DELAY; + RXCOMMADETUSE0_indelay <= RXCOMMADETUSE0_ipd after IN_DELAY; + RXCOMMADETUSE1_indelay <= RXCOMMADETUSE1_ipd after IN_DELAY; + RXDATAWIDTH0_indelay <= RXDATAWIDTH0_ipd after IN_DELAY; + RXDATAWIDTH1_indelay <= RXDATAWIDTH1_ipd after IN_DELAY; + RXDEC8B10BUSE0_indelay <= RXDEC8B10BUSE0_ipd after IN_DELAY; + RXDEC8B10BUSE1_indelay <= RXDEC8B10BUSE1_ipd after IN_DELAY; + RXELECIDLERESET0_indelay <= RXELECIDLERESET0_ipd after IN_DELAY; + RXELECIDLERESET1_indelay <= RXELECIDLERESET1_ipd after IN_DELAY; + RXENCHANSYNC0_indelay <= RXENCHANSYNC0_ipd after IN_DELAY; + RXENCHANSYNC1_indelay <= RXENCHANSYNC1_ipd after IN_DELAY; + RXENELECIDLERESETB_indelay <= RXENELECIDLERESETB_ipd after IN_DELAY; + RXENEQB0_indelay <= RXENEQB0_ipd after IN_DELAY; + RXENEQB1_indelay <= RXENEQB1_ipd after IN_DELAY; + RXENMCOMMAALIGN0_indelay <= RXENMCOMMAALIGN0_ipd after IN_DELAY; + RXENMCOMMAALIGN1_indelay <= RXENMCOMMAALIGN1_ipd after IN_DELAY; + RXENPCOMMAALIGN0_indelay <= RXENPCOMMAALIGN0_ipd after IN_DELAY; + RXENPCOMMAALIGN1_indelay <= RXENPCOMMAALIGN1_ipd after IN_DELAY; + RXENPRBSTST0_indelay <= RXENPRBSTST0_ipd after IN_DELAY; + RXENPRBSTST1_indelay <= RXENPRBSTST1_ipd after IN_DELAY; + RXENSAMPLEALIGN0_indelay <= RXENSAMPLEALIGN0_ipd after IN_DELAY; + RXENSAMPLEALIGN1_indelay <= RXENSAMPLEALIGN1_ipd after IN_DELAY; + RXEQMIX0_indelay <= RXEQMIX0_ipd after IN_DELAY; + RXEQMIX1_indelay <= RXEQMIX1_ipd after IN_DELAY; + RXEQPOLE0_indelay <= RXEQPOLE0_ipd after IN_DELAY; + RXEQPOLE1_indelay <= RXEQPOLE1_ipd after IN_DELAY; + RXN0_indelay <= RXN0_ipd after IN_DELAY; + RXN1_indelay <= RXN1_ipd after IN_DELAY; + RXP0_indelay <= RXP0_ipd after IN_DELAY; + RXP1_indelay <= RXP1_ipd after IN_DELAY; + RXPMASETPHASE0_indelay <= RXPMASETPHASE0_ipd after IN_DELAY; + RXPMASETPHASE1_indelay <= RXPMASETPHASE1_ipd after IN_DELAY; + RXPOLARITY0_indelay <= RXPOLARITY0_ipd after IN_DELAY; + RXPOLARITY1_indelay <= RXPOLARITY1_ipd after IN_DELAY; + RXPOWERDOWN0_indelay <= RXPOWERDOWN0_ipd after IN_DELAY; + RXPOWERDOWN1_indelay <= RXPOWERDOWN1_ipd after IN_DELAY; + RXRESET0_indelay <= RXRESET0_ipd after IN_DELAY; + RXRESET1_indelay <= RXRESET1_ipd after IN_DELAY; + RXSLIDE0_indelay <= RXSLIDE0_ipd after IN_DELAY; + RXSLIDE1_indelay <= RXSLIDE1_ipd after IN_DELAY; + TXBUFDIFFCTRL0_indelay <= TXBUFDIFFCTRL0_ipd after IN_DELAY; + TXBUFDIFFCTRL1_indelay <= TXBUFDIFFCTRL1_ipd after IN_DELAY; + TXBYPASS8B10B0_indelay <= TXBYPASS8B10B0_ipd after IN_DELAY; + TXBYPASS8B10B1_indelay <= TXBYPASS8B10B1_ipd after IN_DELAY; + TXCHARDISPMODE0_indelay <= TXCHARDISPMODE0_ipd after IN_DELAY; + TXCHARDISPMODE1_indelay <= TXCHARDISPMODE1_ipd after IN_DELAY; + TXCHARDISPVAL0_indelay <= TXCHARDISPVAL0_ipd after IN_DELAY; + TXCHARDISPVAL1_indelay <= TXCHARDISPVAL1_ipd after IN_DELAY; + TXCHARISK0_indelay <= TXCHARISK0_ipd after IN_DELAY; + TXCHARISK1_indelay <= TXCHARISK1_ipd after IN_DELAY; + TXCOMSTART0_indelay <= TXCOMSTART0_ipd after IN_DELAY; + TXCOMSTART1_indelay <= TXCOMSTART1_ipd after IN_DELAY; + TXCOMTYPE0_indelay <= TXCOMTYPE0_ipd after IN_DELAY; + TXCOMTYPE1_indelay <= TXCOMTYPE1_ipd after IN_DELAY; + TXDATA0_indelay <= TXDATA0_ipd after IN_DELAY; + TXDATA1_indelay <= TXDATA1_ipd after IN_DELAY; + TXDATAWIDTH0_indelay <= TXDATAWIDTH0_ipd after IN_DELAY; + TXDATAWIDTH1_indelay <= TXDATAWIDTH1_ipd after IN_DELAY; + TXDETECTRX0_indelay <= TXDETECTRX0_ipd after IN_DELAY; + TXDETECTRX1_indelay <= TXDETECTRX1_ipd after IN_DELAY; + TXDIFFCTRL0_indelay <= TXDIFFCTRL0_ipd after IN_DELAY; + TXDIFFCTRL1_indelay <= TXDIFFCTRL1_ipd after IN_DELAY; + TXELECIDLE0_indelay <= TXELECIDLE0_ipd after IN_DELAY; + TXELECIDLE1_indelay <= TXELECIDLE1_ipd after IN_DELAY; + TXENC8B10BUSE0_indelay <= TXENC8B10BUSE0_ipd after IN_DELAY; + TXENC8B10BUSE1_indelay <= TXENC8B10BUSE1_ipd after IN_DELAY; + TXENPMAPHASEALIGN_indelay <= TXENPMAPHASEALIGN_ipd after IN_DELAY; + TXENPRBSTST0_indelay <= TXENPRBSTST0_ipd after IN_DELAY; + TXENPRBSTST1_indelay <= TXENPRBSTST1_ipd after IN_DELAY; + TXINHIBIT0_indelay <= TXINHIBIT0_ipd after IN_DELAY; + TXINHIBIT1_indelay <= TXINHIBIT1_ipd after IN_DELAY; + TXPMASETPHASE_indelay <= TXPMASETPHASE_ipd after IN_DELAY; + TXPOLARITY0_indelay <= TXPOLARITY0_ipd after IN_DELAY; + TXPOLARITY1_indelay <= TXPOLARITY1_ipd after IN_DELAY; + TXPOWERDOWN0_indelay <= TXPOWERDOWN0_ipd after IN_DELAY; + TXPOWERDOWN1_indelay <= TXPOWERDOWN1_ipd after IN_DELAY; + TXPREEMPHASIS0_indelay <= TXPREEMPHASIS0_ipd after IN_DELAY; + TXPREEMPHASIS1_indelay <= TXPREEMPHASIS1_ipd after IN_DELAY; + TXRESET0_indelay <= TXRESET0_ipd after IN_DELAY; + TXRESET1_indelay <= TXRESET1_ipd after IN_DELAY; + + legacy_model: if SIM_MODE = "LEGACY" generate + gtp_dual_swift_bw_1 : GTP_DUAL_SWIFT + port map ( + AC_CAP_DIS_0 => AC_CAP_DIS_0_BINARY, + AC_CAP_DIS_1 => AC_CAP_DIS_1_BINARY, + ALIGN_COMMA_WORD_0 => ALIGN_COMMA_WORD_0_BINARY, + ALIGN_COMMA_WORD_1 => ALIGN_COMMA_WORD_1_BINARY, + CHAN_BOND_1_MAX_SKEW_0 => CHAN_BOND_1_MAX_SKEW_0_BINARY, + CHAN_BOND_1_MAX_SKEW_1 => CHAN_BOND_1_MAX_SKEW_1_BINARY, + CHAN_BOND_2_MAX_SKEW_0 => CHAN_BOND_2_MAX_SKEW_0_BINARY, + CHAN_BOND_2_MAX_SKEW_1 => CHAN_BOND_2_MAX_SKEW_1_BINARY, + CHAN_BOND_LEVEL_0 => CHAN_BOND_LEVEL_0_BINARY, + CHAN_BOND_LEVEL_1 => CHAN_BOND_LEVEL_1_BINARY, + CHAN_BOND_MODE_0 => CHAN_BOND_MODE_0_BINARY, + CHAN_BOND_MODE_1 => CHAN_BOND_MODE_1_BINARY, + CHAN_BOND_SEQ_1_1_0 => CHAN_BOND_SEQ_1_1_0_BINARY, + CHAN_BOND_SEQ_1_1_1 => CHAN_BOND_SEQ_1_1_1_BINARY, + CHAN_BOND_SEQ_1_2_0 => CHAN_BOND_SEQ_1_2_0_BINARY, + CHAN_BOND_SEQ_1_2_1 => CHAN_BOND_SEQ_1_2_1_BINARY, + CHAN_BOND_SEQ_1_3_0 => CHAN_BOND_SEQ_1_3_0_BINARY, + CHAN_BOND_SEQ_1_3_1 => CHAN_BOND_SEQ_1_3_1_BINARY, + CHAN_BOND_SEQ_1_4_0 => CHAN_BOND_SEQ_1_4_0_BINARY, + CHAN_BOND_SEQ_1_4_1 => CHAN_BOND_SEQ_1_4_1_BINARY, + CHAN_BOND_SEQ_1_ENABLE_0 => CHAN_BOND_SEQ_1_ENABLE_0_BINARY, + CHAN_BOND_SEQ_1_ENABLE_1 => CHAN_BOND_SEQ_1_ENABLE_1_BINARY, + CHAN_BOND_SEQ_2_1_0 => CHAN_BOND_SEQ_2_1_0_BINARY, + CHAN_BOND_SEQ_2_1_1 => CHAN_BOND_SEQ_2_1_1_BINARY, + CHAN_BOND_SEQ_2_2_0 => CHAN_BOND_SEQ_2_2_0_BINARY, + CHAN_BOND_SEQ_2_2_1 => CHAN_BOND_SEQ_2_2_1_BINARY, + CHAN_BOND_SEQ_2_3_0 => CHAN_BOND_SEQ_2_3_0_BINARY, + CHAN_BOND_SEQ_2_3_1 => CHAN_BOND_SEQ_2_3_1_BINARY, + CHAN_BOND_SEQ_2_4_0 => CHAN_BOND_SEQ_2_4_0_BINARY, + CHAN_BOND_SEQ_2_4_1 => CHAN_BOND_SEQ_2_4_1_BINARY, + CHAN_BOND_SEQ_2_ENABLE_0 => CHAN_BOND_SEQ_2_ENABLE_0_BINARY, + CHAN_BOND_SEQ_2_ENABLE_1 => CHAN_BOND_SEQ_2_ENABLE_1_BINARY, + CHAN_BOND_SEQ_2_USE_0 => CHAN_BOND_SEQ_2_USE_0_BINARY, + CHAN_BOND_SEQ_2_USE_1 => CHAN_BOND_SEQ_2_USE_1_BINARY, + CHAN_BOND_SEQ_LEN_0 => CHAN_BOND_SEQ_LEN_0_BINARY, + CHAN_BOND_SEQ_LEN_1 => CHAN_BOND_SEQ_LEN_1_BINARY, + CLK25_DIVIDER => CLK25_DIVIDER_BINARY, + CLKINDC_B => CLKINDC_B_BINARY, + CLK_CORRECT_USE_0 => CLK_CORRECT_USE_0_BINARY, + CLK_CORRECT_USE_1 => CLK_CORRECT_USE_1_BINARY, + CLK_COR_ADJ_LEN_0 => CLK_COR_ADJ_LEN_0_BINARY, + CLK_COR_ADJ_LEN_1 => CLK_COR_ADJ_LEN_1_BINARY, + CLK_COR_DET_LEN_0 => CLK_COR_DET_LEN_0_BINARY, + CLK_COR_DET_LEN_1 => CLK_COR_DET_LEN_1_BINARY, + CLK_COR_INSERT_IDLE_FLAG_0 => CLK_COR_INSERT_IDLE_FLAG_0_BINARY, + CLK_COR_INSERT_IDLE_FLAG_1 => CLK_COR_INSERT_IDLE_FLAG_1_BINARY, + CLK_COR_KEEP_IDLE_0 => CLK_COR_KEEP_IDLE_0_BINARY, + CLK_COR_KEEP_IDLE_1 => CLK_COR_KEEP_IDLE_1_BINARY, + CLK_COR_MAX_LAT_0 => CLK_COR_MAX_LAT_0_BINARY, + CLK_COR_MAX_LAT_1 => CLK_COR_MAX_LAT_1_BINARY, + CLK_COR_MIN_LAT_0 => CLK_COR_MIN_LAT_0_BINARY, + CLK_COR_MIN_LAT_1 => CLK_COR_MIN_LAT_1_BINARY, + CLK_COR_PRECEDENCE_0 => CLK_COR_PRECEDENCE_0_BINARY, + CLK_COR_PRECEDENCE_1 => CLK_COR_PRECEDENCE_1_BINARY, + CLK_COR_REPEAT_WAIT_0 => CLK_COR_REPEAT_WAIT_0_BINARY, + CLK_COR_REPEAT_WAIT_1 => CLK_COR_REPEAT_WAIT_1_BINARY, + CLK_COR_SEQ_1_1_0 => CLK_COR_SEQ_1_1_0_BINARY, + CLK_COR_SEQ_1_1_1 => CLK_COR_SEQ_1_1_1_BINARY, + CLK_COR_SEQ_1_2_0 => CLK_COR_SEQ_1_2_0_BINARY, + CLK_COR_SEQ_1_2_1 => CLK_COR_SEQ_1_2_1_BINARY, + CLK_COR_SEQ_1_3_0 => CLK_COR_SEQ_1_3_0_BINARY, + CLK_COR_SEQ_1_3_1 => CLK_COR_SEQ_1_3_1_BINARY, + CLK_COR_SEQ_1_4_0 => CLK_COR_SEQ_1_4_0_BINARY, + CLK_COR_SEQ_1_4_1 => CLK_COR_SEQ_1_4_1_BINARY, + CLK_COR_SEQ_1_ENABLE_0 => CLK_COR_SEQ_1_ENABLE_0_BINARY, + CLK_COR_SEQ_1_ENABLE_1 => CLK_COR_SEQ_1_ENABLE_1_BINARY, + CLK_COR_SEQ_2_1_0 => CLK_COR_SEQ_2_1_0_BINARY, + CLK_COR_SEQ_2_1_1 => CLK_COR_SEQ_2_1_1_BINARY, + CLK_COR_SEQ_2_2_0 => CLK_COR_SEQ_2_2_0_BINARY, + CLK_COR_SEQ_2_2_1 => CLK_COR_SEQ_2_2_1_BINARY, + CLK_COR_SEQ_2_3_0 => CLK_COR_SEQ_2_3_0_BINARY, + CLK_COR_SEQ_2_3_1 => CLK_COR_SEQ_2_3_1_BINARY, + CLK_COR_SEQ_2_4_0 => CLK_COR_SEQ_2_4_0_BINARY, + CLK_COR_SEQ_2_4_1 => CLK_COR_SEQ_2_4_1_BINARY, + CLK_COR_SEQ_2_ENABLE_0 => CLK_COR_SEQ_2_ENABLE_0_BINARY, + CLK_COR_SEQ_2_ENABLE_1 => CLK_COR_SEQ_2_ENABLE_1_BINARY, + CLK_COR_SEQ_2_USE_0 => CLK_COR_SEQ_2_USE_0_BINARY, + CLK_COR_SEQ_2_USE_1 => CLK_COR_SEQ_2_USE_1_BINARY, + COMMA_10B_ENABLE_0 => COMMA_10B_ENABLE_0_BINARY, + COMMA_10B_ENABLE_1 => COMMA_10B_ENABLE_1_BINARY, + COMMA_DOUBLE_0 => COMMA_DOUBLE_0_BINARY, + COMMA_DOUBLE_1 => COMMA_DOUBLE_1_BINARY, + COM_BURST_VAL_0 => COM_BURST_VAL_0_BINARY, + COM_BURST_VAL_1 => COM_BURST_VAL_1_BINARY, + DEC_MCOMMA_DETECT_0 => DEC_MCOMMA_DETECT_0_BINARY, + DEC_MCOMMA_DETECT_1 => DEC_MCOMMA_DETECT_1_BINARY, + DEC_PCOMMA_DETECT_0 => DEC_PCOMMA_DETECT_0_BINARY, + DEC_PCOMMA_DETECT_1 => DEC_PCOMMA_DETECT_1_BINARY, + DEC_VALID_COMMA_ONLY_0 => DEC_VALID_COMMA_ONLY_0_BINARY, + DEC_VALID_COMMA_ONLY_1 => DEC_VALID_COMMA_ONLY_1_BINARY, + MCOMMA_10B_VALUE_0 => MCOMMA_10B_VALUE_0_BINARY, + MCOMMA_10B_VALUE_1 => MCOMMA_10B_VALUE_1_BINARY, + MCOMMA_DETECT_0 => MCOMMA_DETECT_0_BINARY, + MCOMMA_DETECT_1 => MCOMMA_DETECT_1_BINARY, + OOBDETECT_THRESHOLD_0 => OOBDETECT_THRESHOLD_0_BINARY, + OOBDETECT_THRESHOLD_1 => OOBDETECT_THRESHOLD_1_BINARY, + OOB_CLK_DIVIDER => OOB_CLK_DIVIDER_BINARY, + OVERSAMPLE_MODE => OVERSAMPLE_MODE_BINARY, + PCI_EXPRESS_MODE_0 => PCI_EXPRESS_MODE_0_BINARY, + PCI_EXPRESS_MODE_1 => PCI_EXPRESS_MODE_1_BINARY, + PCOMMA_10B_VALUE_0 => PCOMMA_10B_VALUE_0_BINARY, + PCOMMA_10B_VALUE_1 => PCOMMA_10B_VALUE_1_BINARY, + PCOMMA_DETECT_0 => PCOMMA_DETECT_0_BINARY, + PCOMMA_DETECT_1 => PCOMMA_DETECT_1_BINARY, + PCS_COM_CFG => PCS_COM_CFG_BINARY, + PLL_DIVSEL_FB => PLL_DIVSEL_FB_BINARY, + PLL_DIVSEL_REF => PLL_DIVSEL_REF_BINARY, + PLL_RXDIVSEL_OUT_0 => PLL_RXDIVSEL_OUT_0_BINARY, + PLL_RXDIVSEL_OUT_1 => PLL_RXDIVSEL_OUT_1_BINARY, + PLL_SATA_0 => PLL_SATA_0_BINARY, + PLL_SATA_1 => PLL_SATA_1_BINARY, + PLL_TXDIVSEL_COMM_OUT => PLL_TXDIVSEL_COMM_OUT_BINARY, + PLL_TXDIVSEL_OUT_0 => PLL_TXDIVSEL_OUT_0_BINARY, + PLL_TXDIVSEL_OUT_1 => PLL_TXDIVSEL_OUT_1_BINARY, + PMA_CDR_SCAN_0 => PMA_CDR_SCAN_0_BINARY, + PMA_CDR_SCAN_1 => PMA_CDR_SCAN_1_BINARY, + PMA_RX_CFG_0 => PMA_RX_CFG_0_BINARY, + PMA_RX_CFG_1 => PMA_RX_CFG_1_BINARY, + PRBS_ERR_THRESHOLD_0 => PRBS_ERR_THRESHOLD_0_BINARY, + PRBS_ERR_THRESHOLD_1 => PRBS_ERR_THRESHOLD_1_BINARY, + RCV_TERM_GND_0 => RCV_TERM_GND_0_BINARY, + RCV_TERM_GND_1 => RCV_TERM_GND_1_BINARY, + RCV_TERM_MID_0 => RCV_TERM_MID_0_BINARY, + RCV_TERM_MID_1 => RCV_TERM_MID_1_BINARY, + RCV_TERM_VTTRX_0 => RCV_TERM_VTTRX_0_BINARY, + RCV_TERM_VTTRX_1 => RCV_TERM_VTTRX_1_BINARY, + RX_BUFFER_USE_0 => RX_BUFFER_USE_0_BINARY, + RX_BUFFER_USE_1 => RX_BUFFER_USE_1_BINARY, + RX_DECODE_SEQ_MATCH_0 => RX_DECODE_SEQ_MATCH_0_BINARY, + RX_DECODE_SEQ_MATCH_1 => RX_DECODE_SEQ_MATCH_1_BINARY, + RX_LOSS_OF_SYNC_FSM_0 => RX_LOSS_OF_SYNC_FSM_0_BINARY, + RX_LOSS_OF_SYNC_FSM_1 => RX_LOSS_OF_SYNC_FSM_1_BINARY, + RX_LOS_INVALID_INCR_0 => RX_LOS_INVALID_INCR_0_BINARY, + RX_LOS_INVALID_INCR_1 => RX_LOS_INVALID_INCR_1_BINARY, + RX_LOS_THRESHOLD_0 => RX_LOS_THRESHOLD_0_BINARY, + RX_LOS_THRESHOLD_1 => RX_LOS_THRESHOLD_1_BINARY, + RX_SLIDE_MODE_0 => RX_SLIDE_MODE_0_BINARY, + RX_SLIDE_MODE_1 => RX_SLIDE_MODE_1_BINARY, + RX_STATUS_FMT_0 => RX_STATUS_FMT_0_BINARY, + RX_STATUS_FMT_1 => RX_STATUS_FMT_1_BINARY, + RX_XCLK_SEL_0 => RX_XCLK_SEL_0_BINARY, + RX_XCLK_SEL_1 => RX_XCLK_SEL_1_BINARY, + SATA_BURST_VAL_0 => SATA_BURST_VAL_0_BINARY, + SATA_BURST_VAL_1 => SATA_BURST_VAL_1_BINARY, + SATA_IDLE_VAL_0 => SATA_IDLE_VAL_0_BINARY, + SATA_IDLE_VAL_1 => SATA_IDLE_VAL_1_BINARY, + SATA_MAX_BURST_0 => SATA_MAX_BURST_0_BINARY, + SATA_MAX_BURST_1 => SATA_MAX_BURST_1_BINARY, + SATA_MAX_INIT_0 => SATA_MAX_INIT_0_BINARY, + SATA_MAX_INIT_1 => SATA_MAX_INIT_1_BINARY, + SATA_MAX_WAKE_0 => SATA_MAX_WAKE_0_BINARY, + SATA_MAX_WAKE_1 => SATA_MAX_WAKE_1_BINARY, + SATA_MIN_BURST_0 => SATA_MIN_BURST_0_BINARY, + SATA_MIN_BURST_1 => SATA_MIN_BURST_1_BINARY, + SATA_MIN_INIT_0 => SATA_MIN_INIT_0_BINARY, + SATA_MIN_INIT_1 => SATA_MIN_INIT_1_BINARY, + SATA_MIN_WAKE_0 => SATA_MIN_WAKE_0_BINARY, + SATA_MIN_WAKE_1 => SATA_MIN_WAKE_1_BINARY, + SIM_GTPRESET_SPEEDUP => SIM_GTPRESET_SPEEDUP_BINARY, + SIM_PLL_PERDIV2 => SIM_PLL_PERDIV2_BINARY, + SIM_RECEIVER_DETECT_PASS0 => SIM_RECEIVER_DETECT_PASS0_BINARY, + SIM_RECEIVER_DETECT_PASS1 => SIM_RECEIVER_DETECT_PASS1_BINARY, + TERMINATION_CTRL => TERMINATION_CTRL_BINARY, + TERMINATION_IMP_0 => TERMINATION_IMP_0_BINARY, + TERMINATION_IMP_1 => TERMINATION_IMP_1_BINARY, + TERMINATION_OVRD => TERMINATION_OVRD_BINARY, + TRANS_TIME_FROM_P2_0 => TRANS_TIME_FROM_P2_0_BINARY, + TRANS_TIME_FROM_P2_1 => TRANS_TIME_FROM_P2_1_BINARY, + TRANS_TIME_NON_P2_0 => TRANS_TIME_NON_P2_0_BINARY, + TRANS_TIME_NON_P2_1 => TRANS_TIME_NON_P2_1_BINARY, + TRANS_TIME_TO_P2_0 => TRANS_TIME_TO_P2_0_BINARY, + TRANS_TIME_TO_P2_1 => TRANS_TIME_TO_P2_1_BINARY, + TXRX_INVERT_0 => TXRX_INVERT_0_BINARY, + TXRX_INVERT_1 => TXRX_INVERT_1_BINARY, + TX_BUFFER_USE_0 => TX_BUFFER_USE_0_BINARY, + TX_BUFFER_USE_1 => TX_BUFFER_USE_1_BINARY, + TX_DIFF_BOOST_0 => TX_DIFF_BOOST_0_BINARY, + TX_DIFF_BOOST_1 => TX_DIFF_BOOST_1_BINARY, + TX_SYNC_FILTERB => TX_SYNC_FILTERB_BINARY, + TX_XCLK_SEL_0 => TX_XCLK_SEL_0_BINARY, + TX_XCLK_SEL_1 => TX_XCLK_SEL_1_BINARY, + DO => DO_outdelay, + DRDY => DRDY_outdelay, + PHYSTATUS0 => PHYSTATUS0_outdelay, + PHYSTATUS1 => PHYSTATUS1_outdelay, + PLLLKDET => PLLLKDET_outdelay, + REFCLKOUT => REFCLKOUT_outdelay, + RESETDONE0 => RESETDONE0_outdelay, + RESETDONE1 => RESETDONE1_outdelay, + RXBUFSTATUS0 => RXBUFSTATUS0_outdelay, + RXBUFSTATUS1 => RXBUFSTATUS1_outdelay, + RXBYTEISALIGNED0 => RXBYTEISALIGNED0_outdelay, + RXBYTEISALIGNED1 => RXBYTEISALIGNED1_outdelay, + RXBYTEREALIGN0 => RXBYTEREALIGN0_outdelay, + RXBYTEREALIGN1 => RXBYTEREALIGN1_outdelay, + RXCHANBONDSEQ0 => RXCHANBONDSEQ0_outdelay, + RXCHANBONDSEQ1 => RXCHANBONDSEQ1_outdelay, + RXCHANISALIGNED0 => RXCHANISALIGNED0_outdelay, + RXCHANISALIGNED1 => RXCHANISALIGNED1_outdelay, + RXCHANREALIGN0 => RXCHANREALIGN0_outdelay, + RXCHANREALIGN1 => RXCHANREALIGN1_outdelay, + RXCHARISCOMMA0 => RXCHARISCOMMA0_outdelay, + RXCHARISCOMMA1 => RXCHARISCOMMA1_outdelay, + RXCHARISK0 => RXCHARISK0_outdelay, + RXCHARISK1 => RXCHARISK1_outdelay, + RXCHBONDO0 => RXCHBONDO0_outdelay, + RXCHBONDO1 => RXCHBONDO1_outdelay, + RXCLKCORCNT0 => RXCLKCORCNT0_outdelay, + RXCLKCORCNT1 => RXCLKCORCNT1_outdelay, + RXCOMMADET0 => RXCOMMADET0_outdelay, + RXCOMMADET1 => RXCOMMADET1_outdelay, + RXDATA0 => RXDATA0_outdelay, + RXDATA1 => RXDATA1_outdelay, + RXDISPERR0 => RXDISPERR0_outdelay, + RXDISPERR1 => RXDISPERR1_outdelay, + RXELECIDLE0 => RXELECIDLE0_outdelay, + RXELECIDLE1 => RXELECIDLE1_outdelay, + RXLOSSOFSYNC0 => RXLOSSOFSYNC0_outdelay, + RXLOSSOFSYNC1 => RXLOSSOFSYNC1_outdelay, + RXNOTINTABLE0 => RXNOTINTABLE0_outdelay, + RXNOTINTABLE1 => RXNOTINTABLE1_outdelay, + RXOVERSAMPLEERR0 => RXOVERSAMPLEERR0_outdelay, + RXOVERSAMPLEERR1 => RXOVERSAMPLEERR1_outdelay, + RXPRBSERR0 => RXPRBSERR0_outdelay, + RXPRBSERR1 => RXPRBSERR1_outdelay, + RXRECCLK0 => RXRECCLK0_outdelay, + RXRECCLK1 => RXRECCLK1_outdelay, + RXRUNDISP0 => RXRUNDISP0_outdelay, + RXRUNDISP1 => RXRUNDISP1_outdelay, + RXSTATUS0 => RXSTATUS0_outdelay, + RXSTATUS1 => RXSTATUS1_outdelay, + RXVALID0 => RXVALID0_outdelay, + RXVALID1 => RXVALID1_outdelay, + TXBUFSTATUS0 => TXBUFSTATUS0_outdelay, + TXBUFSTATUS1 => TXBUFSTATUS1_outdelay, + TXKERR0 => TXKERR0_outdelay, + TXKERR1 => TXKERR1_outdelay, + TXN0 => TXN0_outdelay, + TXN1 => TXN1_outdelay, + TXOUTCLK0 => TXOUTCLK0_outdelay, + TXOUTCLK1 => TXOUTCLK1_outdelay, + TXP0 => TXP0_outdelay, + TXP1 => TXP1_outdelay, + TXRUNDISP0 => TXRUNDISP0_outdelay, + TXRUNDISP1 => TXRUNDISP1_outdelay, + CLKIN => CLKIN_indelay, + DADDR => DADDR_indelay, + DCLK => DCLK_indelay, + DEN => DEN_indelay, + DI => DI_indelay, + DWE => DWE_indelay, + GSR => GSR, + GTPRESET => GTPRESET_indelay, + GTPTEST => GTPTEST_indelay, + INTDATAWIDTH => INTDATAWIDTH_indelay, + LOOPBACK0 => LOOPBACK0_indelay, + LOOPBACK1 => LOOPBACK1_indelay, + PLLLKDETEN => PLLLKDETEN_indelay, + PLLPOWERDOWN => PLLPOWERDOWN_indelay, + PRBSCNTRESET0 => PRBSCNTRESET0_indelay, + PRBSCNTRESET1 => PRBSCNTRESET1_indelay, + REFCLKPWRDNB => REFCLKPWRDNB_indelay, + RXBUFRESET0 => RXBUFRESET0_indelay, + RXBUFRESET1 => RXBUFRESET1_indelay, + RXCDRRESET0 => RXCDRRESET0_indelay, + RXCDRRESET1 => RXCDRRESET1_indelay, + RXCHBONDI0 => RXCHBONDI0_indelay, + RXCHBONDI1 => RXCHBONDI1_indelay, + RXCOMMADETUSE0 => RXCOMMADETUSE0_indelay, + RXCOMMADETUSE1 => RXCOMMADETUSE1_indelay, + RXDATAWIDTH0 => RXDATAWIDTH0_indelay, + RXDATAWIDTH1 => RXDATAWIDTH1_indelay, + RXDEC8B10BUSE0 => RXDEC8B10BUSE0_indelay, + RXDEC8B10BUSE1 => RXDEC8B10BUSE1_indelay, + RXELECIDLERESET0 => RXELECIDLERESET0_indelay, + RXELECIDLERESET1 => RXELECIDLERESET1_indelay, + RXENCHANSYNC0 => RXENCHANSYNC0_indelay, + RXENCHANSYNC1 => RXENCHANSYNC1_indelay, + RXENELECIDLERESETB => RXENELECIDLERESETB_indelay, + RXENEQB0 => RXENEQB0_indelay, + RXENEQB1 => RXENEQB1_indelay, + RXENMCOMMAALIGN0 => RXENMCOMMAALIGN0_indelay, + RXENMCOMMAALIGN1 => RXENMCOMMAALIGN1_indelay, + RXENPCOMMAALIGN0 => RXENPCOMMAALIGN0_indelay, + RXENPCOMMAALIGN1 => RXENPCOMMAALIGN1_indelay, + RXENPRBSTST0 => RXENPRBSTST0_indelay, + RXENPRBSTST1 => RXENPRBSTST1_indelay, + RXENSAMPLEALIGN0 => RXENSAMPLEALIGN0_indelay, + RXENSAMPLEALIGN1 => RXENSAMPLEALIGN1_indelay, + RXEQMIX0 => RXEQMIX0_indelay, + RXEQMIX1 => RXEQMIX1_indelay, + RXEQPOLE0 => RXEQPOLE0_indelay, + RXEQPOLE1 => RXEQPOLE1_indelay, + RXN0 => RXN0_indelay, + RXN1 => RXN1_indelay, + RXP0 => RXP0_indelay, + RXP1 => RXP1_indelay, + RXPMASETPHASE0 => RXPMASETPHASE0_indelay, + RXPMASETPHASE1 => RXPMASETPHASE1_indelay, + RXPOLARITY0 => RXPOLARITY0_indelay, + RXPOLARITY1 => RXPOLARITY1_indelay, + RXPOWERDOWN0 => RXPOWERDOWN0_indelay, + RXPOWERDOWN1 => RXPOWERDOWN1_indelay, + RXRESET0 => RXRESET0_indelay, + RXRESET1 => RXRESET1_indelay, + RXSLIDE0 => RXSLIDE0_indelay, + RXSLIDE1 => RXSLIDE1_indelay, + RXUSRCLK0 => RXUSRCLK0_indelay, + RXUSRCLK1 => RXUSRCLK1_indelay, + RXUSRCLK20 => RXUSRCLK20_indelay, + RXUSRCLK21 => RXUSRCLK21_indelay, + TXBUFDIFFCTRL0 => TXBUFDIFFCTRL0_indelay, + TXBUFDIFFCTRL1 => TXBUFDIFFCTRL1_indelay, + TXBYPASS8B10B0 => TXBYPASS8B10B0_indelay, + TXBYPASS8B10B1 => TXBYPASS8B10B1_indelay, + TXCHARDISPMODE0 => TXCHARDISPMODE0_indelay, + TXCHARDISPMODE1 => TXCHARDISPMODE1_indelay, + TXCHARDISPVAL0 => TXCHARDISPVAL0_indelay, + TXCHARDISPVAL1 => TXCHARDISPVAL1_indelay, + TXCHARISK0 => TXCHARISK0_indelay, + TXCHARISK1 => TXCHARISK1_indelay, + TXCOMSTART0 => TXCOMSTART0_indelay, + TXCOMSTART1 => TXCOMSTART1_indelay, + TXCOMTYPE0 => TXCOMTYPE0_indelay, + TXCOMTYPE1 => TXCOMTYPE1_indelay, + TXDATA0 => TXDATA0_indelay, + TXDATA1 => TXDATA1_indelay, + TXDATAWIDTH0 => TXDATAWIDTH0_indelay, + TXDATAWIDTH1 => TXDATAWIDTH1_indelay, + TXDETECTRX0 => TXDETECTRX0_indelay, + TXDETECTRX1 => TXDETECTRX1_indelay, + TXDIFFCTRL0 => TXDIFFCTRL0_indelay, + TXDIFFCTRL1 => TXDIFFCTRL1_indelay, + TXELECIDLE0 => TXELECIDLE0_indelay, + TXELECIDLE1 => TXELECIDLE1_indelay, + TXENC8B10BUSE0 => TXENC8B10BUSE0_indelay, + TXENC8B10BUSE1 => TXENC8B10BUSE1_indelay, + TXENPMAPHASEALIGN => TXENPMAPHASEALIGN_indelay, + TXENPRBSTST0 => TXENPRBSTST0_indelay, + TXENPRBSTST1 => TXENPRBSTST1_indelay, + TXINHIBIT0 => TXINHIBIT0_indelay, + TXINHIBIT1 => TXINHIBIT1_indelay, + TXPMASETPHASE => TXPMASETPHASE_indelay, + TXPOLARITY0 => TXPOLARITY0_indelay, + TXPOLARITY1 => TXPOLARITY1_indelay, + TXPOWERDOWN0 => TXPOWERDOWN0_indelay, + TXPOWERDOWN1 => TXPOWERDOWN1_indelay, + TXPREEMPHASIS0 => TXPREEMPHASIS0_indelay, + TXPREEMPHASIS1 => TXPREEMPHASIS1_indelay, + TXRESET0 => TXRESET0_indelay, + TXRESET1 => TXRESET1_indelay, + TXUSRCLK0 => TXUSRCLK0_indelay, + TXUSRCLK1 => TXUSRCLK1_indelay, + TXUSRCLK20 => TXUSRCLK20_indelay, + TXUSRCLK21 => TXUSRCLK21_indelay + ); + end generate legacy_model; + + fast_model: if SIM_MODE = "FAST" generate + gtp_dual_fast_bw_1 : GTP_DUAL_FAST + port map ( + AC_CAP_DIS_0 => AC_CAP_DIS_0_BINARY, + AC_CAP_DIS_1 => AC_CAP_DIS_1_BINARY, + ALIGN_COMMA_WORD_0 => ALIGN_COMMA_WORD_0_BINARY, + ALIGN_COMMA_WORD_1 => ALIGN_COMMA_WORD_1_BINARY, + CHAN_BOND_1_MAX_SKEW_0 => CHAN_BOND_1_MAX_SKEW_0_BINARY, + CHAN_BOND_1_MAX_SKEW_1 => CHAN_BOND_1_MAX_SKEW_1_BINARY, + CHAN_BOND_2_MAX_SKEW_0 => CHAN_BOND_2_MAX_SKEW_0_BINARY, + CHAN_BOND_2_MAX_SKEW_1 => CHAN_BOND_2_MAX_SKEW_1_BINARY, + CHAN_BOND_LEVEL_0 => CHAN_BOND_LEVEL_0_BINARY, + CHAN_BOND_LEVEL_1 => CHAN_BOND_LEVEL_1_BINARY, + CHAN_BOND_MODE_0 => CHAN_BOND_MODE_0_BINARY, + CHAN_BOND_MODE_1 => CHAN_BOND_MODE_1_BINARY, + CHAN_BOND_SEQ_1_1_0 => CHAN_BOND_SEQ_1_1_0_BINARY, + CHAN_BOND_SEQ_1_1_1 => CHAN_BOND_SEQ_1_1_1_BINARY, + CHAN_BOND_SEQ_1_2_0 => CHAN_BOND_SEQ_1_2_0_BINARY, + CHAN_BOND_SEQ_1_2_1 => CHAN_BOND_SEQ_1_2_1_BINARY, + CHAN_BOND_SEQ_1_3_0 => CHAN_BOND_SEQ_1_3_0_BINARY, + CHAN_BOND_SEQ_1_3_1 => CHAN_BOND_SEQ_1_3_1_BINARY, + CHAN_BOND_SEQ_1_4_0 => CHAN_BOND_SEQ_1_4_0_BINARY, + CHAN_BOND_SEQ_1_4_1 => CHAN_BOND_SEQ_1_4_1_BINARY, + CHAN_BOND_SEQ_1_ENABLE_0 => CHAN_BOND_SEQ_1_ENABLE_0_BINARY, + CHAN_BOND_SEQ_1_ENABLE_1 => CHAN_BOND_SEQ_1_ENABLE_1_BINARY, + CHAN_BOND_SEQ_2_1_0 => CHAN_BOND_SEQ_2_1_0_BINARY, + CHAN_BOND_SEQ_2_1_1 => CHAN_BOND_SEQ_2_1_1_BINARY, + CHAN_BOND_SEQ_2_2_0 => CHAN_BOND_SEQ_2_2_0_BINARY, + CHAN_BOND_SEQ_2_2_1 => CHAN_BOND_SEQ_2_2_1_BINARY, + CHAN_BOND_SEQ_2_3_0 => CHAN_BOND_SEQ_2_3_0_BINARY, + CHAN_BOND_SEQ_2_3_1 => CHAN_BOND_SEQ_2_3_1_BINARY, + CHAN_BOND_SEQ_2_4_0 => CHAN_BOND_SEQ_2_4_0_BINARY, + CHAN_BOND_SEQ_2_4_1 => CHAN_BOND_SEQ_2_4_1_BINARY, + CHAN_BOND_SEQ_2_ENABLE_0 => CHAN_BOND_SEQ_2_ENABLE_0_BINARY, + CHAN_BOND_SEQ_2_ENABLE_1 => CHAN_BOND_SEQ_2_ENABLE_1_BINARY, + CHAN_BOND_SEQ_2_USE_0 => CHAN_BOND_SEQ_2_USE_0_BINARY, + CHAN_BOND_SEQ_2_USE_1 => CHAN_BOND_SEQ_2_USE_1_BINARY, + CHAN_BOND_SEQ_LEN_0 => CHAN_BOND_SEQ_LEN_0_BINARY, + CHAN_BOND_SEQ_LEN_1 => CHAN_BOND_SEQ_LEN_1_BINARY, + CLK25_DIVIDER => CLK25_DIVIDER_BINARY, + CLKINDC_B => CLKINDC_B_BINARY, + CLK_CORRECT_USE_0 => CLK_CORRECT_USE_0_BINARY, + CLK_CORRECT_USE_1 => CLK_CORRECT_USE_1_BINARY, + CLK_COR_ADJ_LEN_0 => CLK_COR_ADJ_LEN_0_BINARY, + CLK_COR_ADJ_LEN_1 => CLK_COR_ADJ_LEN_1_BINARY, + CLK_COR_DET_LEN_0 => CLK_COR_DET_LEN_0_BINARY, + CLK_COR_DET_LEN_1 => CLK_COR_DET_LEN_1_BINARY, + CLK_COR_INSERT_IDLE_FLAG_0 => CLK_COR_INSERT_IDLE_FLAG_0_BINARY, + CLK_COR_INSERT_IDLE_FLAG_1 => CLK_COR_INSERT_IDLE_FLAG_1_BINARY, + CLK_COR_KEEP_IDLE_0 => CLK_COR_KEEP_IDLE_0_BINARY, + CLK_COR_KEEP_IDLE_1 => CLK_COR_KEEP_IDLE_1_BINARY, + CLK_COR_MAX_LAT_0 => CLK_COR_MAX_LAT_0_BINARY, + CLK_COR_MAX_LAT_1 => CLK_COR_MAX_LAT_1_BINARY, + CLK_COR_MIN_LAT_0 => CLK_COR_MIN_LAT_0_BINARY, + CLK_COR_MIN_LAT_1 => CLK_COR_MIN_LAT_1_BINARY, + CLK_COR_PRECEDENCE_0 => CLK_COR_PRECEDENCE_0_BINARY, + CLK_COR_PRECEDENCE_1 => CLK_COR_PRECEDENCE_1_BINARY, + CLK_COR_REPEAT_WAIT_0 => CLK_COR_REPEAT_WAIT_0_BINARY, + CLK_COR_REPEAT_WAIT_1 => CLK_COR_REPEAT_WAIT_1_BINARY, + CLK_COR_SEQ_1_1_0 => CLK_COR_SEQ_1_1_0_BINARY, + CLK_COR_SEQ_1_1_1 => CLK_COR_SEQ_1_1_1_BINARY, + CLK_COR_SEQ_1_2_0 => CLK_COR_SEQ_1_2_0_BINARY, + CLK_COR_SEQ_1_2_1 => CLK_COR_SEQ_1_2_1_BINARY, + CLK_COR_SEQ_1_3_0 => CLK_COR_SEQ_1_3_0_BINARY, + CLK_COR_SEQ_1_3_1 => CLK_COR_SEQ_1_3_1_BINARY, + CLK_COR_SEQ_1_4_0 => CLK_COR_SEQ_1_4_0_BINARY, + CLK_COR_SEQ_1_4_1 => CLK_COR_SEQ_1_4_1_BINARY, + CLK_COR_SEQ_1_ENABLE_0 => CLK_COR_SEQ_1_ENABLE_0_BINARY, + CLK_COR_SEQ_1_ENABLE_1 => CLK_COR_SEQ_1_ENABLE_1_BINARY, + CLK_COR_SEQ_2_1_0 => CLK_COR_SEQ_2_1_0_BINARY, + CLK_COR_SEQ_2_1_1 => CLK_COR_SEQ_2_1_1_BINARY, + CLK_COR_SEQ_2_2_0 => CLK_COR_SEQ_2_2_0_BINARY, + CLK_COR_SEQ_2_2_1 => CLK_COR_SEQ_2_2_1_BINARY, + CLK_COR_SEQ_2_3_0 => CLK_COR_SEQ_2_3_0_BINARY, + CLK_COR_SEQ_2_3_1 => CLK_COR_SEQ_2_3_1_BINARY, + CLK_COR_SEQ_2_4_0 => CLK_COR_SEQ_2_4_0_BINARY, + CLK_COR_SEQ_2_4_1 => CLK_COR_SEQ_2_4_1_BINARY, + CLK_COR_SEQ_2_ENABLE_0 => CLK_COR_SEQ_2_ENABLE_0_BINARY, + CLK_COR_SEQ_2_ENABLE_1 => CLK_COR_SEQ_2_ENABLE_1_BINARY, + CLK_COR_SEQ_2_USE_0 => CLK_COR_SEQ_2_USE_0_BINARY, + CLK_COR_SEQ_2_USE_1 => CLK_COR_SEQ_2_USE_1_BINARY, + COMMA_10B_ENABLE_0 => COMMA_10B_ENABLE_0_BINARY, + COMMA_10B_ENABLE_1 => COMMA_10B_ENABLE_1_BINARY, + COMMA_DOUBLE_0 => COMMA_DOUBLE_0_BINARY, + COMMA_DOUBLE_1 => COMMA_DOUBLE_1_BINARY, + COM_BURST_VAL_0 => COM_BURST_VAL_0_BINARY, + COM_BURST_VAL_1 => COM_BURST_VAL_1_BINARY, + DEC_MCOMMA_DETECT_0 => DEC_MCOMMA_DETECT_0_BINARY, + DEC_MCOMMA_DETECT_1 => DEC_MCOMMA_DETECT_1_BINARY, + DEC_PCOMMA_DETECT_0 => DEC_PCOMMA_DETECT_0_BINARY, + DEC_PCOMMA_DETECT_1 => DEC_PCOMMA_DETECT_1_BINARY, + DEC_VALID_COMMA_ONLY_0 => DEC_VALID_COMMA_ONLY_0_BINARY, + DEC_VALID_COMMA_ONLY_1 => DEC_VALID_COMMA_ONLY_1_BINARY, + MCOMMA_10B_VALUE_0 => MCOMMA_10B_VALUE_0_BINARY, + MCOMMA_10B_VALUE_1 => MCOMMA_10B_VALUE_1_BINARY, + MCOMMA_DETECT_0 => MCOMMA_DETECT_0_BINARY, + MCOMMA_DETECT_1 => MCOMMA_DETECT_1_BINARY, + OOBDETECT_THRESHOLD_0 => OOBDETECT_THRESHOLD_0_BINARY, + OOBDETECT_THRESHOLD_1 => OOBDETECT_THRESHOLD_1_BINARY, + OOB_CLK_DIVIDER => OOB_CLK_DIVIDER_BINARY, + OVERSAMPLE_MODE => OVERSAMPLE_MODE_BINARY, + PCI_EXPRESS_MODE_0 => PCI_EXPRESS_MODE_0_BINARY, + PCI_EXPRESS_MODE_1 => PCI_EXPRESS_MODE_1_BINARY, + PCOMMA_10B_VALUE_0 => PCOMMA_10B_VALUE_0_BINARY, + PCOMMA_10B_VALUE_1 => PCOMMA_10B_VALUE_1_BINARY, + PCOMMA_DETECT_0 => PCOMMA_DETECT_0_BINARY, + PCOMMA_DETECT_1 => PCOMMA_DETECT_1_BINARY, + PCS_COM_CFG => PCS_COM_CFG_BINARY, + PLL_DIVSEL_FB => PLL_DIVSEL_FB_BINARY, + PLL_DIVSEL_REF => PLL_DIVSEL_REF_BINARY, + PLL_RXDIVSEL_OUT_0 => PLL_RXDIVSEL_OUT_0_BINARY, + PLL_RXDIVSEL_OUT_1 => PLL_RXDIVSEL_OUT_1_BINARY, + PLL_SATA_0 => PLL_SATA_0_BINARY, + PLL_SATA_1 => PLL_SATA_1_BINARY, + PLL_TXDIVSEL_COMM_OUT => PLL_TXDIVSEL_COMM_OUT_BINARY, + PLL_TXDIVSEL_OUT_0 => PLL_TXDIVSEL_OUT_0_BINARY, + PLL_TXDIVSEL_OUT_1 => PLL_TXDIVSEL_OUT_1_BINARY, + PMA_CDR_SCAN_0 => PMA_CDR_SCAN_0_BINARY, + PMA_CDR_SCAN_1 => PMA_CDR_SCAN_1_BINARY, + PMA_RX_CFG_0 => PMA_RX_CFG_0_BINARY, + PMA_RX_CFG_1 => PMA_RX_CFG_1_BINARY, + PRBS_ERR_THRESHOLD_0 => PRBS_ERR_THRESHOLD_0_BINARY, + PRBS_ERR_THRESHOLD_1 => PRBS_ERR_THRESHOLD_1_BINARY, + RCV_TERM_GND_0 => RCV_TERM_GND_0_BINARY, + RCV_TERM_GND_1 => RCV_TERM_GND_1_BINARY, + RCV_TERM_MID_0 => RCV_TERM_MID_0_BINARY, + RCV_TERM_MID_1 => RCV_TERM_MID_1_BINARY, + RCV_TERM_VTTRX_0 => RCV_TERM_VTTRX_0_BINARY, + RCV_TERM_VTTRX_1 => RCV_TERM_VTTRX_1_BINARY, + RX_BUFFER_USE_0 => RX_BUFFER_USE_0_BINARY, + RX_BUFFER_USE_1 => RX_BUFFER_USE_1_BINARY, + RX_DECODE_SEQ_MATCH_0 => RX_DECODE_SEQ_MATCH_0_BINARY, + RX_DECODE_SEQ_MATCH_1 => RX_DECODE_SEQ_MATCH_1_BINARY, + RX_LOSS_OF_SYNC_FSM_0 => RX_LOSS_OF_SYNC_FSM_0_BINARY, + RX_LOSS_OF_SYNC_FSM_1 => RX_LOSS_OF_SYNC_FSM_1_BINARY, + RX_LOS_INVALID_INCR_0 => RX_LOS_INVALID_INCR_0_BINARY, + RX_LOS_INVALID_INCR_1 => RX_LOS_INVALID_INCR_1_BINARY, + RX_LOS_THRESHOLD_0 => RX_LOS_THRESHOLD_0_BINARY, + RX_LOS_THRESHOLD_1 => RX_LOS_THRESHOLD_1_BINARY, + RX_SLIDE_MODE_0 => RX_SLIDE_MODE_0_BINARY, + RX_SLIDE_MODE_1 => RX_SLIDE_MODE_1_BINARY, + RX_STATUS_FMT_0 => RX_STATUS_FMT_0_BINARY, + RX_STATUS_FMT_1 => RX_STATUS_FMT_1_BINARY, + RX_XCLK_SEL_0 => RX_XCLK_SEL_0_BINARY, + RX_XCLK_SEL_1 => RX_XCLK_SEL_1_BINARY, + SATA_BURST_VAL_0 => SATA_BURST_VAL_0_BINARY, + SATA_BURST_VAL_1 => SATA_BURST_VAL_1_BINARY, + SATA_IDLE_VAL_0 => SATA_IDLE_VAL_0_BINARY, + SATA_IDLE_VAL_1 => SATA_IDLE_VAL_1_BINARY, + SATA_MAX_BURST_0 => SATA_MAX_BURST_0_BINARY, + SATA_MAX_BURST_1 => SATA_MAX_BURST_1_BINARY, + SATA_MAX_INIT_0 => SATA_MAX_INIT_0_BINARY, + SATA_MAX_INIT_1 => SATA_MAX_INIT_1_BINARY, + SATA_MAX_WAKE_0 => SATA_MAX_WAKE_0_BINARY, + SATA_MAX_WAKE_1 => SATA_MAX_WAKE_1_BINARY, + SATA_MIN_BURST_0 => SATA_MIN_BURST_0_BINARY, + SATA_MIN_BURST_1 => SATA_MIN_BURST_1_BINARY, + SATA_MIN_INIT_0 => SATA_MIN_INIT_0_BINARY, + SATA_MIN_INIT_1 => SATA_MIN_INIT_1_BINARY, + SATA_MIN_WAKE_0 => SATA_MIN_WAKE_0_BINARY, + SATA_MIN_WAKE_1 => SATA_MIN_WAKE_1_BINARY, + SIM_GTPRESET_SPEEDUP => SIM_GTPRESET_SPEEDUP_BINARY, + SIM_PLL_PERDIV2 => SIM_PLL_PERDIV2_BINARY, + SIM_RECEIVER_DETECT_PASS0 => SIM_RECEIVER_DETECT_PASS0_BINARY, + SIM_RECEIVER_DETECT_PASS1 => SIM_RECEIVER_DETECT_PASS1_BINARY, + TERMINATION_CTRL => TERMINATION_CTRL_BINARY, + TERMINATION_IMP_0 => TERMINATION_IMP_0_BINARY, + TERMINATION_IMP_1 => TERMINATION_IMP_1_BINARY, + TERMINATION_OVRD => TERMINATION_OVRD_BINARY, + TRANS_TIME_FROM_P2_0 => TRANS_TIME_FROM_P2_0_BINARY, + TRANS_TIME_FROM_P2_1 => TRANS_TIME_FROM_P2_1_BINARY, + TRANS_TIME_NON_P2_0 => TRANS_TIME_NON_P2_0_BINARY, + TRANS_TIME_NON_P2_1 => TRANS_TIME_NON_P2_1_BINARY, + TRANS_TIME_TO_P2_0 => TRANS_TIME_TO_P2_0_BINARY, + TRANS_TIME_TO_P2_1 => TRANS_TIME_TO_P2_1_BINARY, + TXRX_INVERT_0 => TXRX_INVERT_0_BINARY, + TXRX_INVERT_1 => TXRX_INVERT_1_BINARY, + TX_BUFFER_USE_0 => TX_BUFFER_USE_0_BINARY, + TX_BUFFER_USE_1 => TX_BUFFER_USE_1_BINARY, + TX_DIFF_BOOST_0 => TX_DIFF_BOOST_0_BINARY, + TX_DIFF_BOOST_1 => TX_DIFF_BOOST_1_BINARY, + TX_SYNC_FILTERB => TX_SYNC_FILTERB_BINARY, + TX_XCLK_SEL_0 => TX_XCLK_SEL_0_BINARY, + TX_XCLK_SEL_1 => TX_XCLK_SEL_1_BINARY, + DO => DO_outdelay, + DRDY => DRDY_outdelay, + PHYSTATUS0 => PHYSTATUS0_outdelay, + PHYSTATUS1 => PHYSTATUS1_outdelay, + PLLLKDET => PLLLKDET_outdelay, + REFCLKOUT => REFCLKOUT_outdelay, + RESETDONE0 => RESETDONE0_outdelay, + RESETDONE1 => RESETDONE1_outdelay, + RXBUFSTATUS0 => RXBUFSTATUS0_outdelay, + RXBUFSTATUS1 => RXBUFSTATUS1_outdelay, + RXBYTEISALIGNED0 => RXBYTEISALIGNED0_outdelay, + RXBYTEISALIGNED1 => RXBYTEISALIGNED1_outdelay, + RXBYTEREALIGN0 => RXBYTEREALIGN0_outdelay, + RXBYTEREALIGN1 => RXBYTEREALIGN1_outdelay, + RXCHANBONDSEQ0 => RXCHANBONDSEQ0_outdelay, + RXCHANBONDSEQ1 => RXCHANBONDSEQ1_outdelay, + RXCHANISALIGNED0 => RXCHANISALIGNED0_outdelay, + RXCHANISALIGNED1 => RXCHANISALIGNED1_outdelay, + RXCHANREALIGN0 => RXCHANREALIGN0_outdelay, + RXCHANREALIGN1 => RXCHANREALIGN1_outdelay, + RXCHARISCOMMA0 => RXCHARISCOMMA0_outdelay, + RXCHARISCOMMA1 => RXCHARISCOMMA1_outdelay, + RXCHARISK0 => RXCHARISK0_outdelay, + RXCHARISK1 => RXCHARISK1_outdelay, + RXCHBONDO0 => RXCHBONDO0_outdelay, + RXCHBONDO1 => RXCHBONDO1_outdelay, + RXCLKCORCNT0 => RXCLKCORCNT0_outdelay, + RXCLKCORCNT1 => RXCLKCORCNT1_outdelay, + RXCOMMADET0 => RXCOMMADET0_outdelay, + RXCOMMADET1 => RXCOMMADET1_outdelay, + RXDATA0 => RXDATA0_outdelay, + RXDATA1 => RXDATA1_outdelay, + RXDISPERR0 => RXDISPERR0_outdelay, + RXDISPERR1 => RXDISPERR1_outdelay, + RXELECIDLE0 => RXELECIDLE0_outdelay, + RXELECIDLE1 => RXELECIDLE1_outdelay, + RXLOSSOFSYNC0 => RXLOSSOFSYNC0_outdelay, + RXLOSSOFSYNC1 => RXLOSSOFSYNC1_outdelay, + RXNOTINTABLE0 => RXNOTINTABLE0_outdelay, + RXNOTINTABLE1 => RXNOTINTABLE1_outdelay, + RXOVERSAMPLEERR0 => RXOVERSAMPLEERR0_outdelay, + RXOVERSAMPLEERR1 => RXOVERSAMPLEERR1_outdelay, + RXPRBSERR0 => RXPRBSERR0_outdelay, + RXPRBSERR1 => RXPRBSERR1_outdelay, + RXRECCLK0 => RXRECCLK0_outdelay, + RXRECCLK1 => RXRECCLK1_outdelay, + RXRUNDISP0 => RXRUNDISP0_outdelay, + RXRUNDISP1 => RXRUNDISP1_outdelay, + RXSTATUS0 => RXSTATUS0_outdelay, + RXSTATUS1 => RXSTATUS1_outdelay, + RXVALID0 => RXVALID0_outdelay, + RXVALID1 => RXVALID1_outdelay, + TXBUFSTATUS0 => TXBUFSTATUS0_outdelay, + TXBUFSTATUS1 => TXBUFSTATUS1_outdelay, + TXKERR0 => TXKERR0_outdelay, + TXKERR1 => TXKERR1_outdelay, + TXN0 => TXN0_outdelay, + TXN1 => TXN1_outdelay, + TXOUTCLK0 => TXOUTCLK0_outdelay, + TXOUTCLK1 => TXOUTCLK1_outdelay, + TXP0 => TXP0_outdelay, + TXP1 => TXP1_outdelay, + TXRUNDISP0 => TXRUNDISP0_outdelay, + TXRUNDISP1 => TXRUNDISP1_outdelay, + CLKIN => CLKIN_indelay, + DADDR => DADDR_indelay, + DCLK => DCLK_indelay, + DEN => DEN_indelay, + DI => DI_indelay, + DWE => DWE_indelay, + GSR => GSR, + GTPRESET => GTPRESET_indelay, + GTPTEST => GTPTEST_indelay, + INTDATAWIDTH => INTDATAWIDTH_indelay, + LOOPBACK0 => LOOPBACK0_indelay, + LOOPBACK1 => LOOPBACK1_indelay, + PLLLKDETEN => PLLLKDETEN_indelay, + PLLPOWERDOWN => PLLPOWERDOWN_indelay, + PRBSCNTRESET0 => PRBSCNTRESET0_indelay, + PRBSCNTRESET1 => PRBSCNTRESET1_indelay, + REFCLKPWRDNB => REFCLKPWRDNB_indelay, + RXBUFRESET0 => RXBUFRESET0_indelay, + RXBUFRESET1 => RXBUFRESET1_indelay, + RXCDRRESET0 => RXCDRRESET0_indelay, + RXCDRRESET1 => RXCDRRESET1_indelay, + RXCHBONDI0 => RXCHBONDI0_indelay, + RXCHBONDI1 => RXCHBONDI1_indelay, + RXCOMMADETUSE0 => RXCOMMADETUSE0_indelay, + RXCOMMADETUSE1 => RXCOMMADETUSE1_indelay, + RXDATAWIDTH0 => RXDATAWIDTH0_indelay, + RXDATAWIDTH1 => RXDATAWIDTH1_indelay, + RXDEC8B10BUSE0 => RXDEC8B10BUSE0_indelay, + RXDEC8B10BUSE1 => RXDEC8B10BUSE1_indelay, + RXELECIDLERESET0 => RXELECIDLERESET0_indelay, + RXELECIDLERESET1 => RXELECIDLERESET1_indelay, + RXENCHANSYNC0 => RXENCHANSYNC0_indelay, + RXENCHANSYNC1 => RXENCHANSYNC1_indelay, + RXENELECIDLERESETB => RXENELECIDLERESETB_indelay, + RXENEQB0 => RXENEQB0_indelay, + RXENEQB1 => RXENEQB1_indelay, + RXENMCOMMAALIGN0 => RXENMCOMMAALIGN0_indelay, + RXENMCOMMAALIGN1 => RXENMCOMMAALIGN1_indelay, + RXENPCOMMAALIGN0 => RXENPCOMMAALIGN0_indelay, + RXENPCOMMAALIGN1 => RXENPCOMMAALIGN1_indelay, + RXENPRBSTST0 => RXENPRBSTST0_indelay, + RXENPRBSTST1 => RXENPRBSTST1_indelay, + RXENSAMPLEALIGN0 => RXENSAMPLEALIGN0_indelay, + RXENSAMPLEALIGN1 => RXENSAMPLEALIGN1_indelay, + RXEQMIX0 => RXEQMIX0_indelay, + RXEQMIX1 => RXEQMIX1_indelay, + RXEQPOLE0 => RXEQPOLE0_indelay, + RXEQPOLE1 => RXEQPOLE1_indelay, + RXN0 => RXN0_indelay, + RXN1 => RXN1_indelay, + RXP0 => RXP0_indelay, + RXP1 => RXP1_indelay, + RXPMASETPHASE0 => RXPMASETPHASE0_indelay, + RXPMASETPHASE1 => RXPMASETPHASE1_indelay, + RXPOLARITY0 => RXPOLARITY0_indelay, + RXPOLARITY1 => RXPOLARITY1_indelay, + RXPOWERDOWN0 => RXPOWERDOWN0_indelay, + RXPOWERDOWN1 => RXPOWERDOWN1_indelay, + RXRESET0 => RXRESET0_indelay, + RXRESET1 => RXRESET1_indelay, + RXSLIDE0 => RXSLIDE0_indelay, + RXSLIDE1 => RXSLIDE1_indelay, + RXUSRCLK0 => RXUSRCLK0_indelay, + RXUSRCLK1 => RXUSRCLK1_indelay, + RXUSRCLK20 => RXUSRCLK20_indelay, + RXUSRCLK21 => RXUSRCLK21_indelay, + TXBUFDIFFCTRL0 => TXBUFDIFFCTRL0_indelay, + TXBUFDIFFCTRL1 => TXBUFDIFFCTRL1_indelay, + TXBYPASS8B10B0 => TXBYPASS8B10B0_indelay, + TXBYPASS8B10B1 => TXBYPASS8B10B1_indelay, + TXCHARDISPMODE0 => TXCHARDISPMODE0_indelay, + TXCHARDISPMODE1 => TXCHARDISPMODE1_indelay, + TXCHARDISPVAL0 => TXCHARDISPVAL0_indelay, + TXCHARDISPVAL1 => TXCHARDISPVAL1_indelay, + TXCHARISK0 => TXCHARISK0_indelay, + TXCHARISK1 => TXCHARISK1_indelay, + TXCOMSTART0 => TXCOMSTART0_indelay, + TXCOMSTART1 => TXCOMSTART1_indelay, + TXCOMTYPE0 => TXCOMTYPE0_indelay, + TXCOMTYPE1 => TXCOMTYPE1_indelay, + TXDATA0 => TXDATA0_indelay, + TXDATA1 => TXDATA1_indelay, + TXDATAWIDTH0 => TXDATAWIDTH0_indelay, + TXDATAWIDTH1 => TXDATAWIDTH1_indelay, + TXDETECTRX0 => TXDETECTRX0_indelay, + TXDETECTRX1 => TXDETECTRX1_indelay, + TXDIFFCTRL0 => TXDIFFCTRL0_indelay, + TXDIFFCTRL1 => TXDIFFCTRL1_indelay, + TXELECIDLE0 => TXELECIDLE0_indelay, + TXELECIDLE1 => TXELECIDLE1_indelay, + TXENC8B10BUSE0 => TXENC8B10BUSE0_indelay, + TXENC8B10BUSE1 => TXENC8B10BUSE1_indelay, + TXENPMAPHASEALIGN => TXENPMAPHASEALIGN_indelay, + TXENPRBSTST0 => TXENPRBSTST0_indelay, + TXENPRBSTST1 => TXENPRBSTST1_indelay, + TXINHIBIT0 => TXINHIBIT0_indelay, + TXINHIBIT1 => TXINHIBIT1_indelay, + TXPMASETPHASE => TXPMASETPHASE_indelay, + TXPOLARITY0 => TXPOLARITY0_indelay, + TXPOLARITY1 => TXPOLARITY1_indelay, + TXPOWERDOWN0 => TXPOWERDOWN0_indelay, + TXPOWERDOWN1 => TXPOWERDOWN1_indelay, + TXPREEMPHASIS0 => TXPREEMPHASIS0_indelay, + TXPREEMPHASIS1 => TXPREEMPHASIS1_indelay, + TXRESET0 => TXRESET0_indelay, + TXRESET1 => TXRESET1_indelay, + TXUSRCLK0 => TXUSRCLK0_indelay, + TXUSRCLK1 => TXUSRCLK1_indelay, + TXUSRCLK20 => TXUSRCLK20_indelay, + TXUSRCLK21 => TXUSRCLK21_indelay + ); + end generate fast_model; + + INIPROC : process + begin + case PLL_TXDIVSEL_OUT_0 is + when 1 => PLL_TXDIVSEL_OUT_0_BINARY <= "00"; + when 2 => PLL_TXDIVSEL_OUT_0_BINARY <= "01"; + when 4 => PLL_TXDIVSEL_OUT_0_BINARY <= "10"; + when others => assert FALSE report "Error : PLL_TXDIVSEL_OUT_0 is not in 1, 2, 4." severity error; + end case; + case PLL_RXDIVSEL_OUT_0 is + when 1 => PLL_RXDIVSEL_OUT_0_BINARY <= "00"; + when 2 => PLL_RXDIVSEL_OUT_0_BINARY <= "01"; + when 4 => PLL_RXDIVSEL_OUT_0_BINARY <= "10"; + when others => assert FALSE report "Error : PLL_RXDIVSEL_OUT_0 is not in 1, 2, 4." severity error; + end case; + case PLL_TXDIVSEL_OUT_1 is + when 1 => PLL_TXDIVSEL_OUT_1_BINARY <= "00"; + when 2 => PLL_TXDIVSEL_OUT_1_BINARY <= "01"; + when 4 => PLL_TXDIVSEL_OUT_1_BINARY <= "10"; + when others => assert FALSE report "Error : PLL_TXDIVSEL_OUT_1 is not in 1, 2, 4." severity error; + end case; + case PLL_RXDIVSEL_OUT_1 is + when 1 => PLL_RXDIVSEL_OUT_1_BINARY <= "00"; + when 2 => PLL_RXDIVSEL_OUT_1_BINARY <= "01"; + when 4 => PLL_RXDIVSEL_OUT_1_BINARY <= "10"; + when others => assert FALSE report "Error : PLL_RXDIVSEL_OUT_1 is not in 1, 2, 4." severity error; + end case; + case PLL_DIVSEL_FB is + when 1 => PLL_DIVSEL_FB_BINARY <= "10000"; + when 2 => PLL_DIVSEL_FB_BINARY <= "00000"; + when 3 => PLL_DIVSEL_FB_BINARY <= "00001"; + when 4 => PLL_DIVSEL_FB_BINARY <= "00010"; + when 5 => PLL_DIVSEL_FB_BINARY <= "00011"; + when 8 => PLL_DIVSEL_FB_BINARY <= "00110"; + when 10 => PLL_DIVSEL_FB_BINARY <= "00111"; + when others => assert FALSE report "Error : PLL_DIVSEL_FB is not in 1, 2, 3, 4, 5, 8, 10." severity error; + end case; + case PLL_DIVSEL_REF is + when 1 => PLL_DIVSEL_REF_BINARY <= "010000"; + when 2 => PLL_DIVSEL_REF_BINARY <= "000000"; + when 3 => PLL_DIVSEL_REF_BINARY <= "000001"; + when 4 => PLL_DIVSEL_REF_BINARY <= "000010"; + when 5 => PLL_DIVSEL_REF_BINARY <= "000011"; + when 6 => PLL_DIVSEL_REF_BINARY <= "000101"; + when 8 => PLL_DIVSEL_REF_BINARY <= "000110"; + when 10 => PLL_DIVSEL_REF_BINARY <= "000111"; + when 12 => PLL_DIVSEL_REF_BINARY <= "001101"; + when 16 => PLL_DIVSEL_REF_BINARY <= "001110"; + when 20 => PLL_DIVSEL_REF_BINARY <= "001111"; + when others => assert FALSE report "Error : PLL_DIVSEL_REF is not in 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20." severity error; + end case; + case PLL_TXDIVSEL_COMM_OUT is + when 1 => PLL_TXDIVSEL_COMM_OUT_BINARY <= "00"; + when 2 => PLL_TXDIVSEL_COMM_OUT_BINARY <= "01"; + when 4 => PLL_TXDIVSEL_COMM_OUT_BINARY <= "10"; + when others => assert FALSE report "Error : PLL_TXDIVSEL_COMM_OUT is not in 1, 2, 4." severity error; + end case; + case PLL_SATA_0 is + when FALSE => PLL_SATA_0_BINARY <= '0'; + when TRUE => PLL_SATA_0_BINARY <= '1'; + when others => assert FALSE report "Error : PLL_SATA_0 is neither TRUE nor FALSE." severity error; + end case; + case PLL_SATA_1 is + when FALSE => PLL_SATA_1_BINARY <= '0'; + when TRUE => PLL_SATA_1_BINARY <= '1'; + when others => assert FALSE report "Error : PLL_SATA_1 is neither TRUE nor FALSE." severity error; + end case; + case TX_DIFF_BOOST_0 is + when FALSE => TX_DIFF_BOOST_0_BINARY <= '0'; + when TRUE => TX_DIFF_BOOST_0_BINARY <= '1'; + when others => assert FALSE report "Error : TX_DIFF_BOOST_0 is neither TRUE nor FALSE." severity error; + end case; + case TX_DIFF_BOOST_1 is + when FALSE => TX_DIFF_BOOST_1_BINARY <= '0'; + when TRUE => TX_DIFF_BOOST_1_BINARY <= '1'; + when others => assert FALSE report "Error : TX_DIFF_BOOST_1 is neither TRUE nor FALSE." severity error; + end case; + case OOB_CLK_DIVIDER is + when 1 => OOB_CLK_DIVIDER_BINARY <= "000"; + when 2 => OOB_CLK_DIVIDER_BINARY <= "001"; + when 4 => OOB_CLK_DIVIDER_BINARY <= "010"; + when 6 => OOB_CLK_DIVIDER_BINARY <= "011"; + when 8 => OOB_CLK_DIVIDER_BINARY <= "100"; + when 10 => OOB_CLK_DIVIDER_BINARY <= "101"; + when 12 => OOB_CLK_DIVIDER_BINARY <= "110"; + when 14 => OOB_CLK_DIVIDER_BINARY <= "111"; + when others => assert FALSE report "Error : OOB_CLK_DIVIDER is not in 1, 2, 4, 6, 8, 10, 12, 14." severity error; + end case; + case TX_SYNC_FILTERB is + when 0 => TX_SYNC_FILTERB_BINARY <= '0'; + when 1 => TX_SYNC_FILTERB_BINARY <= '1'; + when others => assert FALSE report "Error : TX_SYNC_FILTERB is not in 0, 1." severity error; + end case; + case AC_CAP_DIS_0 is + when FALSE => AC_CAP_DIS_0_BINARY <= '0'; + when TRUE => AC_CAP_DIS_0_BINARY <= '1'; + when others => assert FALSE report "Error : AC_CAP_DIS_0 is neither TRUE nor FALSE." severity error; + end case; + case AC_CAP_DIS_1 is + when FALSE => AC_CAP_DIS_1_BINARY <= '0'; + when TRUE => AC_CAP_DIS_1_BINARY <= '1'; + when others => assert FALSE report "Error : AC_CAP_DIS_1 is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_GND_0 is + when FALSE => RCV_TERM_GND_0_BINARY <= '0'; + when TRUE => RCV_TERM_GND_0_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_GND_0 is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_GND_1 is + when FALSE => RCV_TERM_GND_1_BINARY <= '0'; + when TRUE => RCV_TERM_GND_1_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_GND_1 is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_MID_0 is + when FALSE => RCV_TERM_MID_0_BINARY <= '0'; + when TRUE => RCV_TERM_MID_0_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_MID_0 is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_MID_1 is + when FALSE => RCV_TERM_MID_1_BINARY <= '0'; + when TRUE => RCV_TERM_MID_1_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_MID_1 is neither TRUE nor FALSE." severity error; + end case; + case TERMINATION_IMP_0 is + when 50 => TERMINATION_IMP_0_BINARY <= '0'; + when 75 => TERMINATION_IMP_0_BINARY <= '1'; + when others => assert FALSE report "Error : TERMINATION_IMP_0 is not in 50, 75." severity error; + end case; + case TERMINATION_IMP_1 is + when 50 => TERMINATION_IMP_1_BINARY <= '0'; + when 75 => TERMINATION_IMP_1_BINARY <= '1'; + when others => assert FALSE report "Error : TERMINATION_IMP_1 is not in 50, 75." severity error; + end case; + case TERMINATION_OVRD is + when FALSE => TERMINATION_OVRD_BINARY <= '0'; + when TRUE => TERMINATION_OVRD_BINARY <= '1'; + when others => assert FALSE report "Error : TERMINATION_OVRD is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_VTTRX_0 is + when FALSE => RCV_TERM_VTTRX_0_BINARY <= '0'; + when TRUE => RCV_TERM_VTTRX_0_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_VTTRX_0 is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_VTTRX_1 is + when FALSE => RCV_TERM_VTTRX_1_BINARY <= '0'; + when TRUE => RCV_TERM_VTTRX_1_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_VTTRX_1 is neither TRUE nor FALSE." severity error; + end case; + case CLKINDC_B is + when FALSE => CLKINDC_B_BINARY <= '0'; + when TRUE => CLKINDC_B_BINARY <= '1'; + when others => assert FALSE report "Error : CLKINDC_B is neither TRUE nor FALSE." severity error; + end case; + case PCOMMA_DETECT_0 is + when FALSE => PCOMMA_DETECT_0_BINARY <= '0'; + when TRUE => PCOMMA_DETECT_0_BINARY <= '1'; + when others => assert FALSE report "Error : PCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; + end case; + case MCOMMA_DETECT_0 is + when FALSE => MCOMMA_DETECT_0_BINARY <= '0'; + when TRUE => MCOMMA_DETECT_0_BINARY <= '1'; + when others => assert FALSE report "Error : MCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; + end case; + case COMMA_DOUBLE_0 is + when FALSE => COMMA_DOUBLE_0_BINARY <= '0'; + when TRUE => COMMA_DOUBLE_0_BINARY <= '1'; + when others => assert FALSE report "Error : COMMA_DOUBLE_0 is neither TRUE nor FALSE." severity error; + end case; + case ALIGN_COMMA_WORD_0 is + when 1 => ALIGN_COMMA_WORD_0_BINARY <= '0'; + when 2 => ALIGN_COMMA_WORD_0_BINARY <= '1'; + when others => assert FALSE report "Error : ALIGN_COMMA_WORD_0 is not in 1, 2." severity error; + end case; + case DEC_PCOMMA_DETECT_0 is + when FALSE => DEC_PCOMMA_DETECT_0_BINARY <= '0'; + when TRUE => DEC_PCOMMA_DETECT_0_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_PCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; + end case; + case DEC_MCOMMA_DETECT_0 is + when FALSE => DEC_MCOMMA_DETECT_0_BINARY <= '0'; + when TRUE => DEC_MCOMMA_DETECT_0_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_MCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; + end case; + case DEC_VALID_COMMA_ONLY_0 is + when FALSE => DEC_VALID_COMMA_ONLY_0_BINARY <= '0'; + when TRUE => DEC_VALID_COMMA_ONLY_0_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_VALID_COMMA_ONLY_0 is neither TRUE nor FALSE." severity error; + end case; + case PCOMMA_DETECT_1 is + when FALSE => PCOMMA_DETECT_1_BINARY <= '0'; + when TRUE => PCOMMA_DETECT_1_BINARY <= '1'; + when others => assert FALSE report "Error : PCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; + end case; + case MCOMMA_DETECT_1 is + when FALSE => MCOMMA_DETECT_1_BINARY <= '0'; + when TRUE => MCOMMA_DETECT_1_BINARY <= '1'; + when others => assert FALSE report "Error : MCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; + end case; + case COMMA_DOUBLE_1 is + when FALSE => COMMA_DOUBLE_1_BINARY <= '0'; + when TRUE => COMMA_DOUBLE_1_BINARY <= '1'; + when others => assert FALSE report "Error : COMMA_DOUBLE_1 is neither TRUE nor FALSE." severity error; + end case; + case ALIGN_COMMA_WORD_1 is + when 1 => ALIGN_COMMA_WORD_1_BINARY <= '0'; + when 2 => ALIGN_COMMA_WORD_1_BINARY <= '1'; + when others => assert FALSE report "Error : ALIGN_COMMA_WORD_1 is not in 1, 2." severity error; + end case; + case DEC_PCOMMA_DETECT_1 is + when FALSE => DEC_PCOMMA_DETECT_1_BINARY <= '0'; + when TRUE => DEC_PCOMMA_DETECT_1_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_PCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; + end case; + case DEC_MCOMMA_DETECT_1 is + when FALSE => DEC_MCOMMA_DETECT_1_BINARY <= '0'; + when TRUE => DEC_MCOMMA_DETECT_1_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_MCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; + end case; + case DEC_VALID_COMMA_ONLY_1 is + when FALSE => DEC_VALID_COMMA_ONLY_1_BINARY <= '0'; + when TRUE => DEC_VALID_COMMA_ONLY_1_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_VALID_COMMA_ONLY_1 is neither TRUE nor FALSE." severity error; + end case; + case RX_LOSS_OF_SYNC_FSM_0 is + when FALSE => RX_LOSS_OF_SYNC_FSM_0_BINARY <= '0'; + when TRUE => RX_LOSS_OF_SYNC_FSM_0_BINARY <= '1'; + when others => assert FALSE report "Error : RX_LOSS_OF_SYNC_FSM_0 is neither TRUE nor FALSE." severity error; + end case; + case RX_LOS_INVALID_INCR_0 is + when 1 => RX_LOS_INVALID_INCR_0_BINARY <= "000"; + when 2 => RX_LOS_INVALID_INCR_0_BINARY <= "001"; + when 4 => RX_LOS_INVALID_INCR_0_BINARY <= "010"; + when 8 => RX_LOS_INVALID_INCR_0_BINARY <= "011"; + when 16 => RX_LOS_INVALID_INCR_0_BINARY <= "100"; + when 32 => RX_LOS_INVALID_INCR_0_BINARY <= "101"; + when 64 => RX_LOS_INVALID_INCR_0_BINARY <= "110"; + when 128 => RX_LOS_INVALID_INCR_0_BINARY <= "111"; + when others => assert FALSE report "Error : RX_LOS_INVALID_INCR_0 is not in 1, 2, 4, 8, 16, 32, 64, 128." severity error; + end case; + case RX_LOS_THRESHOLD_0 is + when 4 => RX_LOS_THRESHOLD_0_BINARY <= "000"; + when 8 => RX_LOS_THRESHOLD_0_BINARY <= "001"; + when 16 => RX_LOS_THRESHOLD_0_BINARY <= "010"; + when 32 => RX_LOS_THRESHOLD_0_BINARY <= "011"; + when 64 => RX_LOS_THRESHOLD_0_BINARY <= "100"; + when 128 => RX_LOS_THRESHOLD_0_BINARY <= "101"; + when 256 => RX_LOS_THRESHOLD_0_BINARY <= "110"; + when 512 => RX_LOS_THRESHOLD_0_BINARY <= "111"; + when others => assert FALSE report "Error : RX_LOS_THRESHOLD_0 is not in 4, 8, 16, 32, 64, 128, 256, 512." severity error; + end case; + case RX_LOSS_OF_SYNC_FSM_1 is + when FALSE => RX_LOSS_OF_SYNC_FSM_1_BINARY <= '0'; + when TRUE => RX_LOSS_OF_SYNC_FSM_1_BINARY <= '1'; + when others => assert FALSE report "Error : RX_LOSS_OF_SYNC_FSM_1 is neither TRUE nor FALSE." severity error; + end case; + case RX_LOS_INVALID_INCR_1 is + when 1 => RX_LOS_INVALID_INCR_1_BINARY <= "000"; + when 2 => RX_LOS_INVALID_INCR_1_BINARY <= "001"; + when 4 => RX_LOS_INVALID_INCR_1_BINARY <= "010"; + when 8 => RX_LOS_INVALID_INCR_1_BINARY <= "011"; + when 16 => RX_LOS_INVALID_INCR_1_BINARY <= "100"; + when 32 => RX_LOS_INVALID_INCR_1_BINARY <= "101"; + when 64 => RX_LOS_INVALID_INCR_1_BINARY <= "110"; + when 128 => RX_LOS_INVALID_INCR_1_BINARY <= "111"; + when others => assert FALSE report "Error : RX_LOS_INVALID_INCR_1 is not in 1, 2, 4, 8, 16, 32, 64, 128." severity error; + end case; + case RX_LOS_THRESHOLD_1 is + when 4 => RX_LOS_THRESHOLD_1_BINARY <= "000"; + when 8 => RX_LOS_THRESHOLD_1_BINARY <= "001"; + when 16 => RX_LOS_THRESHOLD_1_BINARY <= "010"; + when 32 => RX_LOS_THRESHOLD_1_BINARY <= "011"; + when 64 => RX_LOS_THRESHOLD_1_BINARY <= "100"; + when 128 => RX_LOS_THRESHOLD_1_BINARY <= "101"; + when 256 => RX_LOS_THRESHOLD_1_BINARY <= "110"; + when 512 => RX_LOS_THRESHOLD_1_BINARY <= "111"; + when others => assert FALSE report "Error : RX_LOS_THRESHOLD_1 is not in 4, 8, 16, 32, 64, 128, 256, 512." severity error; + end case; + case RX_BUFFER_USE_0 is + when FALSE => RX_BUFFER_USE_0_BINARY <= '0'; + when TRUE => RX_BUFFER_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : RX_BUFFER_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case RX_DECODE_SEQ_MATCH_0 is + when FALSE => RX_DECODE_SEQ_MATCH_0_BINARY <= '0'; + when TRUE => RX_DECODE_SEQ_MATCH_0_BINARY <= '1'; + when others => assert FALSE report "Error : RX_DECODE_SEQ_MATCH_0 is neither TRUE nor FALSE." severity error; + end case; + case RX_BUFFER_USE_1 is + when FALSE => RX_BUFFER_USE_1_BINARY <= '0'; + when TRUE => RX_BUFFER_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : RX_BUFFER_USE_1 is neither TRUE nor FALSE." severity error; + end case; + case RX_DECODE_SEQ_MATCH_1 is + when FALSE => RX_DECODE_SEQ_MATCH_1_BINARY <= '0'; + when TRUE => RX_DECODE_SEQ_MATCH_1_BINARY <= '1'; + when others => assert FALSE report "Error : RX_DECODE_SEQ_MATCH_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_MIN_LAT_0 is + when 3 => CLK_COR_MIN_LAT_0_BINARY <= "000011"; + when 4 => CLK_COR_MIN_LAT_0_BINARY <= "000100"; + when 5 => CLK_COR_MIN_LAT_0_BINARY <= "000101"; + when 6 => CLK_COR_MIN_LAT_0_BINARY <= "000110"; + when 7 => CLK_COR_MIN_LAT_0_BINARY <= "000111"; + when 8 => CLK_COR_MIN_LAT_0_BINARY <= "001000"; + when 9 => CLK_COR_MIN_LAT_0_BINARY <= "001001"; + when 10 => CLK_COR_MIN_LAT_0_BINARY <= "001010"; + when 11 => CLK_COR_MIN_LAT_0_BINARY <= "001011"; + when 12 => CLK_COR_MIN_LAT_0_BINARY <= "001100"; + when 13 => CLK_COR_MIN_LAT_0_BINARY <= "001101"; + when 14 => CLK_COR_MIN_LAT_0_BINARY <= "001110"; + when 15 => CLK_COR_MIN_LAT_0_BINARY <= "001111"; + when 16 => CLK_COR_MIN_LAT_0_BINARY <= "010000"; + when 17 => CLK_COR_MIN_LAT_0_BINARY <= "010001"; + when 18 => CLK_COR_MIN_LAT_0_BINARY <= "010010"; + when 19 => CLK_COR_MIN_LAT_0_BINARY <= "010011"; + when 20 => CLK_COR_MIN_LAT_0_BINARY <= "010100"; + when 21 => CLK_COR_MIN_LAT_0_BINARY <= "010101"; + when 22 => CLK_COR_MIN_LAT_0_BINARY <= "010110"; + when 23 => CLK_COR_MIN_LAT_0_BINARY <= "010111"; + when 24 => CLK_COR_MIN_LAT_0_BINARY <= "011000"; + when 25 => CLK_COR_MIN_LAT_0_BINARY <= "011001"; + when 26 => CLK_COR_MIN_LAT_0_BINARY <= "011010"; + when 27 => CLK_COR_MIN_LAT_0_BINARY <= "011011"; + when 28 => CLK_COR_MIN_LAT_0_BINARY <= "011100"; + when 29 => CLK_COR_MIN_LAT_0_BINARY <= "011101"; + when 30 => CLK_COR_MIN_LAT_0_BINARY <= "011110"; + when 31 => CLK_COR_MIN_LAT_0_BINARY <= "011111"; + when 32 => CLK_COR_MIN_LAT_0_BINARY <= "100000"; + when 33 => CLK_COR_MIN_LAT_0_BINARY <= "100001"; + when 34 => CLK_COR_MIN_LAT_0_BINARY <= "100010"; + when 35 => CLK_COR_MIN_LAT_0_BINARY <= "100011"; + when 36 => CLK_COR_MIN_LAT_0_BINARY <= "100100"; + when 37 => CLK_COR_MIN_LAT_0_BINARY <= "100101"; + when 38 => CLK_COR_MIN_LAT_0_BINARY <= "100110"; + when 39 => CLK_COR_MIN_LAT_0_BINARY <= "100111"; + when 40 => CLK_COR_MIN_LAT_0_BINARY <= "101000"; + when 41 => CLK_COR_MIN_LAT_0_BINARY <= "101001"; + when 42 => CLK_COR_MIN_LAT_0_BINARY <= "101010"; + when 43 => CLK_COR_MIN_LAT_0_BINARY <= "101011"; + when 44 => CLK_COR_MIN_LAT_0_BINARY <= "101100"; + when 45 => CLK_COR_MIN_LAT_0_BINARY <= "101101"; + when 46 => CLK_COR_MIN_LAT_0_BINARY <= "101110"; + when 47 => CLK_COR_MIN_LAT_0_BINARY <= "101111"; + when 48 => CLK_COR_MIN_LAT_0_BINARY <= "110000"; + when others => assert FALSE report "Error : CLK_COR_MIN_LAT_0 is not in range 3...48." severity error; + end case; + case CLK_COR_MAX_LAT_0 is + when 3 => CLK_COR_MAX_LAT_0_BINARY <= "000011"; + when 4 => CLK_COR_MAX_LAT_0_BINARY <= "000100"; + when 5 => CLK_COR_MAX_LAT_0_BINARY <= "000101"; + when 6 => CLK_COR_MAX_LAT_0_BINARY <= "000110"; + when 7 => CLK_COR_MAX_LAT_0_BINARY <= "000111"; + when 8 => CLK_COR_MAX_LAT_0_BINARY <= "001000"; + when 9 => CLK_COR_MAX_LAT_0_BINARY <= "001001"; + when 10 => CLK_COR_MAX_LAT_0_BINARY <= "001010"; + when 11 => CLK_COR_MAX_LAT_0_BINARY <= "001011"; + when 12 => CLK_COR_MAX_LAT_0_BINARY <= "001100"; + when 13 => CLK_COR_MAX_LAT_0_BINARY <= "001101"; + when 14 => CLK_COR_MAX_LAT_0_BINARY <= "001110"; + when 15 => CLK_COR_MAX_LAT_0_BINARY <= "001111"; + when 16 => CLK_COR_MAX_LAT_0_BINARY <= "010000"; + when 17 => CLK_COR_MAX_LAT_0_BINARY <= "010001"; + when 18 => CLK_COR_MAX_LAT_0_BINARY <= "010010"; + when 19 => CLK_COR_MAX_LAT_0_BINARY <= "010011"; + when 20 => CLK_COR_MAX_LAT_0_BINARY <= "010100"; + when 21 => CLK_COR_MAX_LAT_0_BINARY <= "010101"; + when 22 => CLK_COR_MAX_LAT_0_BINARY <= "010110"; + when 23 => CLK_COR_MAX_LAT_0_BINARY <= "010111"; + when 24 => CLK_COR_MAX_LAT_0_BINARY <= "011000"; + when 25 => CLK_COR_MAX_LAT_0_BINARY <= "011001"; + when 26 => CLK_COR_MAX_LAT_0_BINARY <= "011010"; + when 27 => CLK_COR_MAX_LAT_0_BINARY <= "011011"; + when 28 => CLK_COR_MAX_LAT_0_BINARY <= "011100"; + when 29 => CLK_COR_MAX_LAT_0_BINARY <= "011101"; + when 30 => CLK_COR_MAX_LAT_0_BINARY <= "011110"; + when 31 => CLK_COR_MAX_LAT_0_BINARY <= "011111"; + when 32 => CLK_COR_MAX_LAT_0_BINARY <= "100000"; + when 33 => CLK_COR_MAX_LAT_0_BINARY <= "100001"; + when 34 => CLK_COR_MAX_LAT_0_BINARY <= "100010"; + when 35 => CLK_COR_MAX_LAT_0_BINARY <= "100011"; + when 36 => CLK_COR_MAX_LAT_0_BINARY <= "100100"; + when 37 => CLK_COR_MAX_LAT_0_BINARY <= "100101"; + when 38 => CLK_COR_MAX_LAT_0_BINARY <= "100110"; + when 39 => CLK_COR_MAX_LAT_0_BINARY <= "100111"; + when 40 => CLK_COR_MAX_LAT_0_BINARY <= "101000"; + when 41 => CLK_COR_MAX_LAT_0_BINARY <= "101001"; + when 42 => CLK_COR_MAX_LAT_0_BINARY <= "101010"; + when 43 => CLK_COR_MAX_LAT_0_BINARY <= "101011"; + when 44 => CLK_COR_MAX_LAT_0_BINARY <= "101100"; + when 45 => CLK_COR_MAX_LAT_0_BINARY <= "101101"; + when 46 => CLK_COR_MAX_LAT_0_BINARY <= "101110"; + when 47 => CLK_COR_MAX_LAT_0_BINARY <= "101111"; + when 48 => CLK_COR_MAX_LAT_0_BINARY <= "110000"; + when others => assert FALSE report "Error : CLK_COR_MAX_LAT_0 is not in range 3...48." severity error; + end case; + case CLK_CORRECT_USE_0 is + when FALSE => CLK_CORRECT_USE_0_BINARY <= '0'; + when TRUE => CLK_CORRECT_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_CORRECT_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_PRECEDENCE_0 is + when FALSE => CLK_COR_PRECEDENCE_0_BINARY <= '0'; + when TRUE => CLK_COR_PRECEDENCE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_PRECEDENCE_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_DET_LEN_0 is + when 1 => CLK_COR_DET_LEN_0_BINARY <= "00"; + when 2 => CLK_COR_DET_LEN_0_BINARY <= "01"; + when 3 => CLK_COR_DET_LEN_0_BINARY <= "10"; + when 4 => CLK_COR_DET_LEN_0_BINARY <= "11"; + when others => assert FALSE report "Error : CLK_COR_DET_LEN_0 is not in 1, 2, 3, 4." severity error; + end case; + case CLK_COR_ADJ_LEN_0 is + when 1 => CLK_COR_ADJ_LEN_0_BINARY <= "00"; + when 2 => CLK_COR_ADJ_LEN_0_BINARY <= "01"; + when 3 => CLK_COR_ADJ_LEN_0_BINARY <= "10"; + when 4 => CLK_COR_ADJ_LEN_0_BINARY <= "11"; + when others => assert FALSE report "Error : CLK_COR_ADJ_LEN_0 is not in 1, 2, 3, 4." severity error; + end case; + case CLK_COR_KEEP_IDLE_0 is + when FALSE => CLK_COR_KEEP_IDLE_0_BINARY <= '0'; + when TRUE => CLK_COR_KEEP_IDLE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_KEEP_IDLE_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_INSERT_IDLE_FLAG_0 is + when FALSE => CLK_COR_INSERT_IDLE_FLAG_0_BINARY <= '0'; + when TRUE => CLK_COR_INSERT_IDLE_FLAG_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_INSERT_IDLE_FLAG_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_REPEAT_WAIT_0 is + when 0 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00000"; + when 1 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00001"; + when 2 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00010"; + when 3 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00011"; + when 4 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00100"; + when 5 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00101"; + when 6 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00110"; + when 7 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00111"; + when 8 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01000"; + when 9 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01001"; + when 10 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01010"; + when 11 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01011"; + when 12 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01100"; + when 13 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01101"; + when 14 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01110"; + when 15 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01111"; + when 16 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10000"; + when 17 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10001"; + when 18 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10010"; + when 19 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10011"; + when 20 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10100"; + when 21 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10101"; + when 22 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10110"; + when 23 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10111"; + when 24 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11000"; + when 25 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11001"; + when 26 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11010"; + when 27 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11011"; + when 28 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11100"; + when 29 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11101"; + when 30 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11110"; + when 31 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11111"; + when others => assert FALSE report "Error : CLK_COR_REPEAT_WAIT_0 is not in range 0...31." severity error; + end case; + case CLK_COR_SEQ_2_USE_0 is + when FALSE => CLK_COR_SEQ_2_USE_0_BINARY <= '0'; + when TRUE => CLK_COR_SEQ_2_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_SEQ_2_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_MIN_LAT_1 is + when 3 => CLK_COR_MIN_LAT_1_BINARY <= "000011"; + when 4 => CLK_COR_MIN_LAT_1_BINARY <= "000100"; + when 5 => CLK_COR_MIN_LAT_1_BINARY <= "000101"; + when 6 => CLK_COR_MIN_LAT_1_BINARY <= "000110"; + when 7 => CLK_COR_MIN_LAT_1_BINARY <= "000111"; + when 8 => CLK_COR_MIN_LAT_1_BINARY <= "001000"; + when 9 => CLK_COR_MIN_LAT_1_BINARY <= "001001"; + when 10 => CLK_COR_MIN_LAT_1_BINARY <= "001010"; + when 11 => CLK_COR_MIN_LAT_1_BINARY <= "001011"; + when 12 => CLK_COR_MIN_LAT_1_BINARY <= "001100"; + when 13 => CLK_COR_MIN_LAT_1_BINARY <= "001101"; + when 14 => CLK_COR_MIN_LAT_1_BINARY <= "001110"; + when 15 => CLK_COR_MIN_LAT_1_BINARY <= "001111"; + when 16 => CLK_COR_MIN_LAT_1_BINARY <= "010000"; + when 17 => CLK_COR_MIN_LAT_1_BINARY <= "010001"; + when 18 => CLK_COR_MIN_LAT_1_BINARY <= "010010"; + when 19 => CLK_COR_MIN_LAT_1_BINARY <= "010011"; + when 20 => CLK_COR_MIN_LAT_1_BINARY <= "010100"; + when 21 => CLK_COR_MIN_LAT_1_BINARY <= "010101"; + when 22 => CLK_COR_MIN_LAT_1_BINARY <= "010110"; + when 23 => CLK_COR_MIN_LAT_1_BINARY <= "010111"; + when 24 => CLK_COR_MIN_LAT_1_BINARY <= "011000"; + when 25 => CLK_COR_MIN_LAT_1_BINARY <= "011001"; + when 26 => CLK_COR_MIN_LAT_1_BINARY <= "011010"; + when 27 => CLK_COR_MIN_LAT_1_BINARY <= "011011"; + when 28 => CLK_COR_MIN_LAT_1_BINARY <= "011100"; + when 29 => CLK_COR_MIN_LAT_1_BINARY <= "011101"; + when 30 => CLK_COR_MIN_LAT_1_BINARY <= "011110"; + when 31 => CLK_COR_MIN_LAT_1_BINARY <= "011111"; + when 32 => CLK_COR_MIN_LAT_1_BINARY <= "100000"; + when 33 => CLK_COR_MIN_LAT_1_BINARY <= "100001"; + when 34 => CLK_COR_MIN_LAT_1_BINARY <= "100010"; + when 35 => CLK_COR_MIN_LAT_1_BINARY <= "100011"; + when 36 => CLK_COR_MIN_LAT_1_BINARY <= "100100"; + when 37 => CLK_COR_MIN_LAT_1_BINARY <= "100101"; + when 38 => CLK_COR_MIN_LAT_1_BINARY <= "100110"; + when 39 => CLK_COR_MIN_LAT_1_BINARY <= "100111"; + when 40 => CLK_COR_MIN_LAT_1_BINARY <= "101000"; + when 41 => CLK_COR_MIN_LAT_1_BINARY <= "101001"; + when 42 => CLK_COR_MIN_LAT_1_BINARY <= "101010"; + when 43 => CLK_COR_MIN_LAT_1_BINARY <= "101011"; + when 44 => CLK_COR_MIN_LAT_1_BINARY <= "101100"; + when 45 => CLK_COR_MIN_LAT_1_BINARY <= "101101"; + when 46 => CLK_COR_MIN_LAT_1_BINARY <= "101110"; + when 47 => CLK_COR_MIN_LAT_1_BINARY <= "101111"; + when 48 => CLK_COR_MIN_LAT_1_BINARY <= "110000"; + when others => assert FALSE report "Error : CLK_COR_MIN_LAT_1 is not in range 3...48." severity error; + end case; + case CLK_COR_MAX_LAT_1 is + when 3 => CLK_COR_MAX_LAT_1_BINARY <= "000011"; + when 4 => CLK_COR_MAX_LAT_1_BINARY <= "000100"; + when 5 => CLK_COR_MAX_LAT_1_BINARY <= "000101"; + when 6 => CLK_COR_MAX_LAT_1_BINARY <= "000110"; + when 7 => CLK_COR_MAX_LAT_1_BINARY <= "000111"; + when 8 => CLK_COR_MAX_LAT_1_BINARY <= "001000"; + when 9 => CLK_COR_MAX_LAT_1_BINARY <= "001001"; + when 10 => CLK_COR_MAX_LAT_1_BINARY <= "001010"; + when 11 => CLK_COR_MAX_LAT_1_BINARY <= "001011"; + when 12 => CLK_COR_MAX_LAT_1_BINARY <= "001100"; + when 13 => CLK_COR_MAX_LAT_1_BINARY <= "001101"; + when 14 => CLK_COR_MAX_LAT_1_BINARY <= "001110"; + when 15 => CLK_COR_MAX_LAT_1_BINARY <= "001111"; + when 16 => CLK_COR_MAX_LAT_1_BINARY <= "010000"; + when 17 => CLK_COR_MAX_LAT_1_BINARY <= "010001"; + when 18 => CLK_COR_MAX_LAT_1_BINARY <= "010010"; + when 19 => CLK_COR_MAX_LAT_1_BINARY <= "010011"; + when 20 => CLK_COR_MAX_LAT_1_BINARY <= "010100"; + when 21 => CLK_COR_MAX_LAT_1_BINARY <= "010101"; + when 22 => CLK_COR_MAX_LAT_1_BINARY <= "010110"; + when 23 => CLK_COR_MAX_LAT_1_BINARY <= "010111"; + when 24 => CLK_COR_MAX_LAT_1_BINARY <= "011000"; + when 25 => CLK_COR_MAX_LAT_1_BINARY <= "011001"; + when 26 => CLK_COR_MAX_LAT_1_BINARY <= "011010"; + when 27 => CLK_COR_MAX_LAT_1_BINARY <= "011011"; + when 28 => CLK_COR_MAX_LAT_1_BINARY <= "011100"; + when 29 => CLK_COR_MAX_LAT_1_BINARY <= "011101"; + when 30 => CLK_COR_MAX_LAT_1_BINARY <= "011110"; + when 31 => CLK_COR_MAX_LAT_1_BINARY <= "011111"; + when 32 => CLK_COR_MAX_LAT_1_BINARY <= "100000"; + when 33 => CLK_COR_MAX_LAT_1_BINARY <= "100001"; + when 34 => CLK_COR_MAX_LAT_1_BINARY <= "100010"; + when 35 => CLK_COR_MAX_LAT_1_BINARY <= "100011"; + when 36 => CLK_COR_MAX_LAT_1_BINARY <= "100100"; + when 37 => CLK_COR_MAX_LAT_1_BINARY <= "100101"; + when 38 => CLK_COR_MAX_LAT_1_BINARY <= "100110"; + when 39 => CLK_COR_MAX_LAT_1_BINARY <= "100111"; + when 40 => CLK_COR_MAX_LAT_1_BINARY <= "101000"; + when 41 => CLK_COR_MAX_LAT_1_BINARY <= "101001"; + when 42 => CLK_COR_MAX_LAT_1_BINARY <= "101010"; + when 43 => CLK_COR_MAX_LAT_1_BINARY <= "101011"; + when 44 => CLK_COR_MAX_LAT_1_BINARY <= "101100"; + when 45 => CLK_COR_MAX_LAT_1_BINARY <= "101101"; + when 46 => CLK_COR_MAX_LAT_1_BINARY <= "101110"; + when 47 => CLK_COR_MAX_LAT_1_BINARY <= "101111"; + when 48 => CLK_COR_MAX_LAT_1_BINARY <= "110000"; + when others => assert FALSE report "Error : CLK_COR_MAX_LAT_1 is not in range 3...48." severity error; + end case; + case CLK_CORRECT_USE_1 is + when FALSE => CLK_CORRECT_USE_1_BINARY <= '0'; + when TRUE => CLK_CORRECT_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_CORRECT_USE_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_PRECEDENCE_1 is + when FALSE => CLK_COR_PRECEDENCE_1_BINARY <= '0'; + when TRUE => CLK_COR_PRECEDENCE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_PRECEDENCE_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_DET_LEN_1 is + when 1 => CLK_COR_DET_LEN_1_BINARY <= "00"; + when 2 => CLK_COR_DET_LEN_1_BINARY <= "01"; + when 3 => CLK_COR_DET_LEN_1_BINARY <= "10"; + when 4 => CLK_COR_DET_LEN_1_BINARY <= "11"; + when others => assert FALSE report "Error : CLK_COR_DET_LEN_1 is not in 1, 2, 3, 4." severity error; + end case; + case CLK_COR_ADJ_LEN_1 is + when 1 => CLK_COR_ADJ_LEN_1_BINARY <= "00"; + when 2 => CLK_COR_ADJ_LEN_1_BINARY <= "01"; + when 3 => CLK_COR_ADJ_LEN_1_BINARY <= "10"; + when 4 => CLK_COR_ADJ_LEN_1_BINARY <= "11"; + when others => assert FALSE report "Error : CLK_COR_ADJ_LEN_1 is not in 1, 2, 3, 4." severity error; + end case; + case CLK_COR_KEEP_IDLE_1 is + when FALSE => CLK_COR_KEEP_IDLE_1_BINARY <= '0'; + when TRUE => CLK_COR_KEEP_IDLE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_KEEP_IDLE_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_INSERT_IDLE_FLAG_1 is + when FALSE => CLK_COR_INSERT_IDLE_FLAG_1_BINARY <= '0'; + when TRUE => CLK_COR_INSERT_IDLE_FLAG_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_INSERT_IDLE_FLAG_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_REPEAT_WAIT_1 is + when 0 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00000"; + when 1 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00001"; + when 2 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00010"; + when 3 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00011"; + when 4 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00100"; + when 5 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00101"; + when 6 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00110"; + when 7 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00111"; + when 8 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01000"; + when 9 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01001"; + when 10 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01010"; + when 11 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01011"; + when 12 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01100"; + when 13 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01101"; + when 14 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01110"; + when 15 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01111"; + when 16 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10000"; + when 17 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10001"; + when 18 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10010"; + when 19 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10011"; + when 20 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10100"; + when 21 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10101"; + when 22 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10110"; + when 23 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10111"; + when 24 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11000"; + when 25 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11001"; + when 26 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11010"; + when 27 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11011"; + when 28 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11100"; + when 29 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11101"; + when 30 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11110"; + when 31 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11111"; + when others => assert FALSE report "Error : CLK_COR_REPEAT_WAIT_1 is not in range 0...31." severity error; + end case; + case CLK_COR_SEQ_2_USE_1 is + when FALSE => CLK_COR_SEQ_2_USE_1_BINARY <= '0'; + when TRUE => CLK_COR_SEQ_2_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_SEQ_2_USE_1 is neither TRUE nor FALSE." severity error; + end case; +-- case CHAN_BOND_MODE_0 is + if((CHAN_BOND_MODE_0 = "OFF") or (CHAN_BOND_MODE_0 = "off")) then + CHAN_BOND_MODE_0_BINARY <= "00"; + elsif((CHAN_BOND_MODE_0 = "MASTER") or (CHAN_BOND_MODE_0 = "master")) then + CHAN_BOND_MODE_0_BINARY <= "01"; + elsif((CHAN_BOND_MODE_0 = "SLAVE") or (CHAN_BOND_MODE_0 = "slave")) then + CHAN_BOND_MODE_0_BINARY <= "10"; + else + assert FALSE report "Error : CHAN_BOND_MODE_0 = is not OFF, MASTER, SLAVE." severity error; + end if; +-- end case; + case CHAN_BOND_LEVEL_0 is + when 0 => CHAN_BOND_LEVEL_0_BINARY <= "000"; + when 1 => CHAN_BOND_LEVEL_0_BINARY <= "001"; + when 2 => CHAN_BOND_LEVEL_0_BINARY <= "010"; + when 3 => CHAN_BOND_LEVEL_0_BINARY <= "011"; + when 4 => CHAN_BOND_LEVEL_0_BINARY <= "100"; + when 5 => CHAN_BOND_LEVEL_0_BINARY <= "101"; + when 6 => CHAN_BOND_LEVEL_0_BINARY <= "110"; + when 7 => CHAN_BOND_LEVEL_0_BINARY <= "111"; + when others => assert FALSE report "Error : CHAN_BOND_LEVEL_0 is not in range 0...7." severity error; + end case; + case CHAN_BOND_SEQ_LEN_0 is + when 1 => CHAN_BOND_SEQ_LEN_0_BINARY <= "00"; + when 2 => CHAN_BOND_SEQ_LEN_0_BINARY <= "01"; + when 3 => CHAN_BOND_SEQ_LEN_0_BINARY <= "10"; + when 4 => CHAN_BOND_SEQ_LEN_0_BINARY <= "11"; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_LEN_0 is not in 1, 2, 3, 4." severity error; + end case; + case CHAN_BOND_SEQ_2_USE_0 is + when FALSE => CHAN_BOND_SEQ_2_USE_0_BINARY <= '0'; + when TRUE => CHAN_BOND_SEQ_2_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_2_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case CHAN_BOND_1_MAX_SKEW_0 is + when 1 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0001"; + when 2 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0010"; + when 3 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0011"; + when 4 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0100"; + when 5 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0101"; + when 6 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0110"; + when 7 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0111"; + when 8 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1000"; + when 9 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1001"; + when 10 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1010"; + when 11 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1011"; + when 12 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1100"; + when 13 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1101"; + when 14 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1110"; + when others => assert FALSE report "Error : CHAN_BOND_1_MAX_SKEW_0 is not in range 1...14." severity error; + end case; + case CHAN_BOND_2_MAX_SKEW_0 is + when 1 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0001"; + when 2 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0010"; + when 3 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0011"; + when 4 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0100"; + when 5 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0101"; + when 6 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0110"; + when 7 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0111"; + when 8 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1000"; + when 9 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1001"; + when 10 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1010"; + when 11 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1011"; + when 12 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1100"; + when 13 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1101"; + when 14 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1110"; + when others => assert FALSE report "Error : CHAN_BOND_2_MAX_SKEW_0 is not in range 1...14." severity error; + end case; +-- case CHAN_BOND_MODE_1 is + if((CHAN_BOND_MODE_1 = "OFF") or (CHAN_BOND_MODE_1 = "off")) then + CHAN_BOND_MODE_1_BINARY <= "00"; + elsif((CHAN_BOND_MODE_1 = "MASTER") or (CHAN_BOND_MODE_1 = "master")) then + CHAN_BOND_MODE_1_BINARY <= "01"; + elsif((CHAN_BOND_MODE_1 = "SLAVE") or (CHAN_BOND_MODE_1 = "slave")) then + CHAN_BOND_MODE_1_BINARY <= "10"; + else + assert FALSE report "Error : CHAN_BOND_MODE_1 = is not OFF, MASTER, SLAVE." severity error; + end if; +-- end case; + case CHAN_BOND_LEVEL_1 is + when 0 => CHAN_BOND_LEVEL_1_BINARY <= "000"; + when 1 => CHAN_BOND_LEVEL_1_BINARY <= "001"; + when 2 => CHAN_BOND_LEVEL_1_BINARY <= "010"; + when 3 => CHAN_BOND_LEVEL_1_BINARY <= "011"; + when 4 => CHAN_BOND_LEVEL_1_BINARY <= "100"; + when 5 => CHAN_BOND_LEVEL_1_BINARY <= "101"; + when 6 => CHAN_BOND_LEVEL_1_BINARY <= "110"; + when 7 => CHAN_BOND_LEVEL_1_BINARY <= "111"; + when others => assert FALSE report "Error : CHAN_BOND_LEVEL_1 is not in range 0...7." severity error; + end case; + case CHAN_BOND_SEQ_LEN_1 is + when 1 => CHAN_BOND_SEQ_LEN_1_BINARY <= "00"; + when 2 => CHAN_BOND_SEQ_LEN_1_BINARY <= "01"; + when 3 => CHAN_BOND_SEQ_LEN_1_BINARY <= "10"; + when 4 => CHAN_BOND_SEQ_LEN_1_BINARY <= "11"; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_LEN_1 is not in 1, 2, 3, 4." severity error; + end case; + case CHAN_BOND_SEQ_2_USE_1 is + when FALSE => CHAN_BOND_SEQ_2_USE_1_BINARY <= '0'; + when TRUE => CHAN_BOND_SEQ_2_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_2_USE_1 is neither TRUE nor FALSE." severity error; + end case; + case CHAN_BOND_1_MAX_SKEW_1 is + when 1 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0001"; + when 2 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0010"; + when 3 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0011"; + when 4 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0100"; + when 5 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0101"; + when 6 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0110"; + when 7 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0111"; + when 8 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1000"; + when 9 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1001"; + when 10 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1010"; + when 11 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1011"; + when 12 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1100"; + when 13 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1101"; + when 14 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1110"; + when others => assert FALSE report "Error : CHAN_BOND_1_MAX_SKEW_1 is not in range 1...14." severity error; + end case; + case CHAN_BOND_2_MAX_SKEW_1 is + when 1 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0001"; + when 2 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0010"; + when 3 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0011"; + when 4 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0100"; + when 5 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0101"; + when 6 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0110"; + when 7 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0111"; + when 8 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1000"; + when 9 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1001"; + when 10 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1010"; + when 11 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1011"; + when 12 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1100"; + when 13 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1101"; + when 14 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1110"; + when others => assert FALSE report "Error : CHAN_BOND_2_MAX_SKEW_1 is not in range 1...14." severity error; + end case; + case PCI_EXPRESS_MODE_0 is + when FALSE => PCI_EXPRESS_MODE_0_BINARY <= '0'; + when TRUE => PCI_EXPRESS_MODE_0_BINARY <= '1'; + when others => assert FALSE report "Error : PCI_EXPRESS_MODE_0 is neither TRUE nor FALSE." severity error; + end case; + case PCI_EXPRESS_MODE_1 is + when FALSE => PCI_EXPRESS_MODE_1_BINARY <= '0'; + when TRUE => PCI_EXPRESS_MODE_1_BINARY <= '1'; + when others => assert FALSE report "Error : PCI_EXPRESS_MODE_1 is neither TRUE nor FALSE." severity error; + end case; +-- case RX_STATUS_FMT_0 is + if((RX_STATUS_FMT_0 = "PCIE") or (RX_STATUS_FMT_0 = "pcie")) then + RX_STATUS_FMT_0_BINARY <= '0'; + elsif((RX_STATUS_FMT_0 = "SATA") or (RX_STATUS_FMT_0 = "sata")) then + RX_STATUS_FMT_0_BINARY <= '1'; + else + assert FALSE report "Error : RX_STATUS_FMT_0 = is not PCIE, SATA." severity error; + end if; +-- end case; + case TX_BUFFER_USE_0 is + when FALSE => TX_BUFFER_USE_0_BINARY <= '0'; + when TRUE => TX_BUFFER_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : TX_BUFFER_USE_0 is neither TRUE nor FALSE." severity error; + end case; +-- case TX_XCLK_SEL_0 is + if((TX_XCLK_SEL_0 = "TXUSR") or (TX_XCLK_SEL_0 = "txusr")) then + TX_XCLK_SEL_0_BINARY <= '1'; + elsif((TX_XCLK_SEL_0 = "TXOUT") or (TX_XCLK_SEL_0 = "txout")) then + TX_XCLK_SEL_0_BINARY <= '0'; + else + assert FALSE report "Error : TX_XCLK_SEL_0 = is not TXUSR, TXOUT." severity error; + end if; +-- end case; +-- case RX_XCLK_SEL_0 is + if((RX_XCLK_SEL_0 = "RXREC") or (RX_XCLK_SEL_0 = "rxrec")) then + RX_XCLK_SEL_0_BINARY <= '0'; + elsif((RX_XCLK_SEL_0 = "RXUSR") or (RX_XCLK_SEL_0 = "rxusr")) then + RX_XCLK_SEL_0_BINARY <= '1'; + else + assert FALSE report "Error : RX_XCLK_SEL_0 = is not RXREC, RXUSR." severity error; + end if; +-- end case; +-- case RX_STATUS_FMT_1 is + if((RX_STATUS_FMT_1 = "PCIE") or (RX_STATUS_FMT_1 = "pcie")) then + RX_STATUS_FMT_1_BINARY <= '0'; + elsif((RX_STATUS_FMT_1 = "SATA") or (RX_STATUS_FMT_1 = "sata")) then + RX_STATUS_FMT_1_BINARY <= '1'; + else + assert FALSE report "Error : RX_STATUS_FMT_1 = is not PCIE, SATA." severity error; + end if; +-- end case; + case TX_BUFFER_USE_1 is + when FALSE => TX_BUFFER_USE_1_BINARY <= '0'; + when TRUE => TX_BUFFER_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : TX_BUFFER_USE_1 is neither TRUE nor FALSE." severity error; + end case; +-- case TX_XCLK_SEL_1 is + if((TX_XCLK_SEL_1 = "TXUSR") or (TX_XCLK_SEL_1 = "txusr")) then + TX_XCLK_SEL_1_BINARY <= '1'; + elsif((TX_XCLK_SEL_1 = "TXOUT") or (TX_XCLK_SEL_1 = "txout")) then + TX_XCLK_SEL_1_BINARY <= '0'; + else + assert FALSE report "Error : TX_XCLK_SEL_1 = is not TXUSR, TXOUT." severity error; + end if; +-- end case; +-- case RX_XCLK_SEL_1 is + if((RX_XCLK_SEL_1 = "RXREC") or (RX_XCLK_SEL_1 = "rxrec")) then + RX_XCLK_SEL_1_BINARY <= '0'; + elsif((RX_XCLK_SEL_1 = "RXUSR") or (RX_XCLK_SEL_1 = "rxusr")) then + RX_XCLK_SEL_1_BINARY <= '1'; + else + assert FALSE report "Error : RX_XCLK_SEL_1 = is not RXREC, RXUSR." severity error; + end if; +-- end case; +-- case RX_SLIDE_MODE_0 is + if((RX_SLIDE_MODE_0 = "PCS") or (RX_SLIDE_MODE_0 = "pcs")) then + RX_SLIDE_MODE_0_BINARY <= '0'; + elsif((RX_SLIDE_MODE_0 = "PMA") or (RX_SLIDE_MODE_0 = "pma")) then + RX_SLIDE_MODE_0_BINARY <= '1'; + else + assert FALSE report "Error : RX_SLIDE_MODE_0 = is not PCS, PMA." severity error; + end if; +-- end case; +-- case RX_SLIDE_MODE_1 is + if((RX_SLIDE_MODE_1 = "PCS") or (RX_SLIDE_MODE_1 = "pcs")) then + RX_SLIDE_MODE_1_BINARY <= '0'; + elsif((RX_SLIDE_MODE_1 = "PMA") or (RX_SLIDE_MODE_1 = "pma")) then + RX_SLIDE_MODE_1_BINARY <= '1'; + else + assert FALSE report "Error : RX_SLIDE_MODE_1 = is not PCS, PMA." severity error; + end if; +-- end case; + case SATA_MIN_BURST_0 is + when 1 => SATA_MIN_BURST_0_BINARY <= "000001"; + when 2 => SATA_MIN_BURST_0_BINARY <= "000010"; + when 3 => SATA_MIN_BURST_0_BINARY <= "000011"; + when 4 => SATA_MIN_BURST_0_BINARY <= "000100"; + when 5 => SATA_MIN_BURST_0_BINARY <= "000101"; + when 6 => SATA_MIN_BURST_0_BINARY <= "000110"; + when 7 => SATA_MIN_BURST_0_BINARY <= "000111"; + when 8 => SATA_MIN_BURST_0_BINARY <= "001000"; + when 9 => SATA_MIN_BURST_0_BINARY <= "001001"; + when 10 => SATA_MIN_BURST_0_BINARY <= "001010"; + when 11 => SATA_MIN_BURST_0_BINARY <= "001011"; + when 12 => SATA_MIN_BURST_0_BINARY <= "001100"; + when 13 => SATA_MIN_BURST_0_BINARY <= "001101"; + when 14 => SATA_MIN_BURST_0_BINARY <= "001110"; + when 15 => SATA_MIN_BURST_0_BINARY <= "001111"; + when 16 => SATA_MIN_BURST_0_BINARY <= "010000"; + when 17 => SATA_MIN_BURST_0_BINARY <= "010001"; + when 18 => SATA_MIN_BURST_0_BINARY <= "010010"; + when 19 => SATA_MIN_BURST_0_BINARY <= "010011"; + when 20 => SATA_MIN_BURST_0_BINARY <= "010100"; + when 21 => SATA_MIN_BURST_0_BINARY <= "010101"; + when 22 => SATA_MIN_BURST_0_BINARY <= "010110"; + when 23 => SATA_MIN_BURST_0_BINARY <= "010111"; + when 24 => SATA_MIN_BURST_0_BINARY <= "011000"; + when 25 => SATA_MIN_BURST_0_BINARY <= "011001"; + when 26 => SATA_MIN_BURST_0_BINARY <= "011010"; + when 27 => SATA_MIN_BURST_0_BINARY <= "011011"; + when 28 => SATA_MIN_BURST_0_BINARY <= "011100"; + when 29 => SATA_MIN_BURST_0_BINARY <= "011101"; + when 30 => SATA_MIN_BURST_0_BINARY <= "011110"; + when 31 => SATA_MIN_BURST_0_BINARY <= "011111"; + when 32 => SATA_MIN_BURST_0_BINARY <= "100000"; + when 33 => SATA_MIN_BURST_0_BINARY <= "100001"; + when 34 => SATA_MIN_BURST_0_BINARY <= "100010"; + when 35 => SATA_MIN_BURST_0_BINARY <= "100011"; + when 36 => SATA_MIN_BURST_0_BINARY <= "100100"; + when 37 => SATA_MIN_BURST_0_BINARY <= "100101"; + when 38 => SATA_MIN_BURST_0_BINARY <= "100110"; + when 39 => SATA_MIN_BURST_0_BINARY <= "100111"; + when 40 => SATA_MIN_BURST_0_BINARY <= "101000"; + when 41 => SATA_MIN_BURST_0_BINARY <= "101001"; + when 42 => SATA_MIN_BURST_0_BINARY <= "101010"; + when 43 => SATA_MIN_BURST_0_BINARY <= "101011"; + when 44 => SATA_MIN_BURST_0_BINARY <= "101100"; + when 45 => SATA_MIN_BURST_0_BINARY <= "101101"; + when 46 => SATA_MIN_BURST_0_BINARY <= "101110"; + when 47 => SATA_MIN_BURST_0_BINARY <= "101111"; + when 48 => SATA_MIN_BURST_0_BINARY <= "110000"; + when 49 => SATA_MIN_BURST_0_BINARY <= "110001"; + when 50 => SATA_MIN_BURST_0_BINARY <= "110010"; + when 51 => SATA_MIN_BURST_0_BINARY <= "110011"; + when 52 => SATA_MIN_BURST_0_BINARY <= "110100"; + when 53 => SATA_MIN_BURST_0_BINARY <= "110101"; + when 54 => SATA_MIN_BURST_0_BINARY <= "110110"; + when 55 => SATA_MIN_BURST_0_BINARY <= "110111"; + when 56 => SATA_MIN_BURST_0_BINARY <= "111000"; + when 57 => SATA_MIN_BURST_0_BINARY <= "111001"; + when 58 => SATA_MIN_BURST_0_BINARY <= "111010"; + when 59 => SATA_MIN_BURST_0_BINARY <= "111011"; + when 60 => SATA_MIN_BURST_0_BINARY <= "111100"; + when 61 => SATA_MIN_BURST_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_BURST_0 is not in range 1...61." severity error; + end case; + case SATA_MAX_BURST_0 is + when 1 => SATA_MAX_BURST_0_BINARY <= "000001"; + when 2 => SATA_MAX_BURST_0_BINARY <= "000010"; + when 3 => SATA_MAX_BURST_0_BINARY <= "000011"; + when 4 => SATA_MAX_BURST_0_BINARY <= "000100"; + when 5 => SATA_MAX_BURST_0_BINARY <= "000101"; + when 6 => SATA_MAX_BURST_0_BINARY <= "000110"; + when 7 => SATA_MAX_BURST_0_BINARY <= "000111"; + when 8 => SATA_MAX_BURST_0_BINARY <= "001000"; + when 9 => SATA_MAX_BURST_0_BINARY <= "001001"; + when 10 => SATA_MAX_BURST_0_BINARY <= "001010"; + when 11 => SATA_MAX_BURST_0_BINARY <= "001011"; + when 12 => SATA_MAX_BURST_0_BINARY <= "001100"; + when 13 => SATA_MAX_BURST_0_BINARY <= "001101"; + when 14 => SATA_MAX_BURST_0_BINARY <= "001110"; + when 15 => SATA_MAX_BURST_0_BINARY <= "001111"; + when 16 => SATA_MAX_BURST_0_BINARY <= "010000"; + when 17 => SATA_MAX_BURST_0_BINARY <= "010001"; + when 18 => SATA_MAX_BURST_0_BINARY <= "010010"; + when 19 => SATA_MAX_BURST_0_BINARY <= "010011"; + when 20 => SATA_MAX_BURST_0_BINARY <= "010100"; + when 21 => SATA_MAX_BURST_0_BINARY <= "010101"; + when 22 => SATA_MAX_BURST_0_BINARY <= "010110"; + when 23 => SATA_MAX_BURST_0_BINARY <= "010111"; + when 24 => SATA_MAX_BURST_0_BINARY <= "011000"; + when 25 => SATA_MAX_BURST_0_BINARY <= "011001"; + when 26 => SATA_MAX_BURST_0_BINARY <= "011010"; + when 27 => SATA_MAX_BURST_0_BINARY <= "011011"; + when 28 => SATA_MAX_BURST_0_BINARY <= "011100"; + when 29 => SATA_MAX_BURST_0_BINARY <= "011101"; + when 30 => SATA_MAX_BURST_0_BINARY <= "011110"; + when 31 => SATA_MAX_BURST_0_BINARY <= "011111"; + when 32 => SATA_MAX_BURST_0_BINARY <= "100000"; + when 33 => SATA_MAX_BURST_0_BINARY <= "100001"; + when 34 => SATA_MAX_BURST_0_BINARY <= "100010"; + when 35 => SATA_MAX_BURST_0_BINARY <= "100011"; + when 36 => SATA_MAX_BURST_0_BINARY <= "100100"; + when 37 => SATA_MAX_BURST_0_BINARY <= "100101"; + when 38 => SATA_MAX_BURST_0_BINARY <= "100110"; + when 39 => SATA_MAX_BURST_0_BINARY <= "100111"; + when 40 => SATA_MAX_BURST_0_BINARY <= "101000"; + when 41 => SATA_MAX_BURST_0_BINARY <= "101001"; + when 42 => SATA_MAX_BURST_0_BINARY <= "101010"; + when 43 => SATA_MAX_BURST_0_BINARY <= "101011"; + when 44 => SATA_MAX_BURST_0_BINARY <= "101100"; + when 45 => SATA_MAX_BURST_0_BINARY <= "101101"; + when 46 => SATA_MAX_BURST_0_BINARY <= "101110"; + when 47 => SATA_MAX_BURST_0_BINARY <= "101111"; + when 48 => SATA_MAX_BURST_0_BINARY <= "110000"; + when 49 => SATA_MAX_BURST_0_BINARY <= "110001"; + when 50 => SATA_MAX_BURST_0_BINARY <= "110010"; + when 51 => SATA_MAX_BURST_0_BINARY <= "110011"; + when 52 => SATA_MAX_BURST_0_BINARY <= "110100"; + when 53 => SATA_MAX_BURST_0_BINARY <= "110101"; + when 54 => SATA_MAX_BURST_0_BINARY <= "110110"; + when 55 => SATA_MAX_BURST_0_BINARY <= "110111"; + when 56 => SATA_MAX_BURST_0_BINARY <= "111000"; + when 57 => SATA_MAX_BURST_0_BINARY <= "111001"; + when 58 => SATA_MAX_BURST_0_BINARY <= "111010"; + when 59 => SATA_MAX_BURST_0_BINARY <= "111011"; + when 60 => SATA_MAX_BURST_0_BINARY <= "111100"; + when 61 => SATA_MAX_BURST_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_BURST_0 is not in range 1...61." severity error; + end case; + case SATA_MIN_INIT_0 is + when 1 => SATA_MIN_INIT_0_BINARY <= "000001"; + when 2 => SATA_MIN_INIT_0_BINARY <= "000010"; + when 3 => SATA_MIN_INIT_0_BINARY <= "000011"; + when 4 => SATA_MIN_INIT_0_BINARY <= "000100"; + when 5 => SATA_MIN_INIT_0_BINARY <= "000101"; + when 6 => SATA_MIN_INIT_0_BINARY <= "000110"; + when 7 => SATA_MIN_INIT_0_BINARY <= "000111"; + when 8 => SATA_MIN_INIT_0_BINARY <= "001000"; + when 9 => SATA_MIN_INIT_0_BINARY <= "001001"; + when 10 => SATA_MIN_INIT_0_BINARY <= "001010"; + when 11 => SATA_MIN_INIT_0_BINARY <= "001011"; + when 12 => SATA_MIN_INIT_0_BINARY <= "001100"; + when 13 => SATA_MIN_INIT_0_BINARY <= "001101"; + when 14 => SATA_MIN_INIT_0_BINARY <= "001110"; + when 15 => SATA_MIN_INIT_0_BINARY <= "001111"; + when 16 => SATA_MIN_INIT_0_BINARY <= "010000"; + when 17 => SATA_MIN_INIT_0_BINARY <= "010001"; + when 18 => SATA_MIN_INIT_0_BINARY <= "010010"; + when 19 => SATA_MIN_INIT_0_BINARY <= "010011"; + when 20 => SATA_MIN_INIT_0_BINARY <= "010100"; + when 21 => SATA_MIN_INIT_0_BINARY <= "010101"; + when 22 => SATA_MIN_INIT_0_BINARY <= "010110"; + when 23 => SATA_MIN_INIT_0_BINARY <= "010111"; + when 24 => SATA_MIN_INIT_0_BINARY <= "011000"; + when 25 => SATA_MIN_INIT_0_BINARY <= "011001"; + when 26 => SATA_MIN_INIT_0_BINARY <= "011010"; + when 27 => SATA_MIN_INIT_0_BINARY <= "011011"; + when 28 => SATA_MIN_INIT_0_BINARY <= "011100"; + when 29 => SATA_MIN_INIT_0_BINARY <= "011101"; + when 30 => SATA_MIN_INIT_0_BINARY <= "011110"; + when 31 => SATA_MIN_INIT_0_BINARY <= "011111"; + when 32 => SATA_MIN_INIT_0_BINARY <= "100000"; + when 33 => SATA_MIN_INIT_0_BINARY <= "100001"; + when 34 => SATA_MIN_INIT_0_BINARY <= "100010"; + when 35 => SATA_MIN_INIT_0_BINARY <= "100011"; + when 36 => SATA_MIN_INIT_0_BINARY <= "100100"; + when 37 => SATA_MIN_INIT_0_BINARY <= "100101"; + when 38 => SATA_MIN_INIT_0_BINARY <= "100110"; + when 39 => SATA_MIN_INIT_0_BINARY <= "100111"; + when 40 => SATA_MIN_INIT_0_BINARY <= "101000"; + when 41 => SATA_MIN_INIT_0_BINARY <= "101001"; + when 42 => SATA_MIN_INIT_0_BINARY <= "101010"; + when 43 => SATA_MIN_INIT_0_BINARY <= "101011"; + when 44 => SATA_MIN_INIT_0_BINARY <= "101100"; + when 45 => SATA_MIN_INIT_0_BINARY <= "101101"; + when 46 => SATA_MIN_INIT_0_BINARY <= "101110"; + when 47 => SATA_MIN_INIT_0_BINARY <= "101111"; + when 48 => SATA_MIN_INIT_0_BINARY <= "110000"; + when 49 => SATA_MIN_INIT_0_BINARY <= "110001"; + when 50 => SATA_MIN_INIT_0_BINARY <= "110010"; + when 51 => SATA_MIN_INIT_0_BINARY <= "110011"; + when 52 => SATA_MIN_INIT_0_BINARY <= "110100"; + when 53 => SATA_MIN_INIT_0_BINARY <= "110101"; + when 54 => SATA_MIN_INIT_0_BINARY <= "110110"; + when 55 => SATA_MIN_INIT_0_BINARY <= "110111"; + when 56 => SATA_MIN_INIT_0_BINARY <= "111000"; + when 57 => SATA_MIN_INIT_0_BINARY <= "111001"; + when 58 => SATA_MIN_INIT_0_BINARY <= "111010"; + when 59 => SATA_MIN_INIT_0_BINARY <= "111011"; + when 60 => SATA_MIN_INIT_0_BINARY <= "111100"; + when 61 => SATA_MIN_INIT_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_INIT_0 is not in range 1...61." severity error; + end case; + case SATA_MAX_INIT_0 is + when 1 => SATA_MAX_INIT_0_BINARY <= "000001"; + when 2 => SATA_MAX_INIT_0_BINARY <= "000010"; + when 3 => SATA_MAX_INIT_0_BINARY <= "000011"; + when 4 => SATA_MAX_INIT_0_BINARY <= "000100"; + when 5 => SATA_MAX_INIT_0_BINARY <= "000101"; + when 6 => SATA_MAX_INIT_0_BINARY <= "000110"; + when 7 => SATA_MAX_INIT_0_BINARY <= "000111"; + when 8 => SATA_MAX_INIT_0_BINARY <= "001000"; + when 9 => SATA_MAX_INIT_0_BINARY <= "001001"; + when 10 => SATA_MAX_INIT_0_BINARY <= "001010"; + when 11 => SATA_MAX_INIT_0_BINARY <= "001011"; + when 12 => SATA_MAX_INIT_0_BINARY <= "001100"; + when 13 => SATA_MAX_INIT_0_BINARY <= "001101"; + when 14 => SATA_MAX_INIT_0_BINARY <= "001110"; + when 15 => SATA_MAX_INIT_0_BINARY <= "001111"; + when 16 => SATA_MAX_INIT_0_BINARY <= "010000"; + when 17 => SATA_MAX_INIT_0_BINARY <= "010001"; + when 18 => SATA_MAX_INIT_0_BINARY <= "010010"; + when 19 => SATA_MAX_INIT_0_BINARY <= "010011"; + when 20 => SATA_MAX_INIT_0_BINARY <= "010100"; + when 21 => SATA_MAX_INIT_0_BINARY <= "010101"; + when 22 => SATA_MAX_INIT_0_BINARY <= "010110"; + when 23 => SATA_MAX_INIT_0_BINARY <= "010111"; + when 24 => SATA_MAX_INIT_0_BINARY <= "011000"; + when 25 => SATA_MAX_INIT_0_BINARY <= "011001"; + when 26 => SATA_MAX_INIT_0_BINARY <= "011010"; + when 27 => SATA_MAX_INIT_0_BINARY <= "011011"; + when 28 => SATA_MAX_INIT_0_BINARY <= "011100"; + when 29 => SATA_MAX_INIT_0_BINARY <= "011101"; + when 30 => SATA_MAX_INIT_0_BINARY <= "011110"; + when 31 => SATA_MAX_INIT_0_BINARY <= "011111"; + when 32 => SATA_MAX_INIT_0_BINARY <= "100000"; + when 33 => SATA_MAX_INIT_0_BINARY <= "100001"; + when 34 => SATA_MAX_INIT_0_BINARY <= "100010"; + when 35 => SATA_MAX_INIT_0_BINARY <= "100011"; + when 36 => SATA_MAX_INIT_0_BINARY <= "100100"; + when 37 => SATA_MAX_INIT_0_BINARY <= "100101"; + when 38 => SATA_MAX_INIT_0_BINARY <= "100110"; + when 39 => SATA_MAX_INIT_0_BINARY <= "100111"; + when 40 => SATA_MAX_INIT_0_BINARY <= "101000"; + when 41 => SATA_MAX_INIT_0_BINARY <= "101001"; + when 42 => SATA_MAX_INIT_0_BINARY <= "101010"; + when 43 => SATA_MAX_INIT_0_BINARY <= "101011"; + when 44 => SATA_MAX_INIT_0_BINARY <= "101100"; + when 45 => SATA_MAX_INIT_0_BINARY <= "101101"; + when 46 => SATA_MAX_INIT_0_BINARY <= "101110"; + when 47 => SATA_MAX_INIT_0_BINARY <= "101111"; + when 48 => SATA_MAX_INIT_0_BINARY <= "110000"; + when 49 => SATA_MAX_INIT_0_BINARY <= "110001"; + when 50 => SATA_MAX_INIT_0_BINARY <= "110010"; + when 51 => SATA_MAX_INIT_0_BINARY <= "110011"; + when 52 => SATA_MAX_INIT_0_BINARY <= "110100"; + when 53 => SATA_MAX_INIT_0_BINARY <= "110101"; + when 54 => SATA_MAX_INIT_0_BINARY <= "110110"; + when 55 => SATA_MAX_INIT_0_BINARY <= "110111"; + when 56 => SATA_MAX_INIT_0_BINARY <= "111000"; + when 57 => SATA_MAX_INIT_0_BINARY <= "111001"; + when 58 => SATA_MAX_INIT_0_BINARY <= "111010"; + when 59 => SATA_MAX_INIT_0_BINARY <= "111011"; + when 60 => SATA_MAX_INIT_0_BINARY <= "111100"; + when 61 => SATA_MAX_INIT_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_INIT_0 is not in range 1...61." severity error; + end case; + case SATA_MIN_WAKE_0 is + when 1 => SATA_MIN_WAKE_0_BINARY <= "000001"; + when 2 => SATA_MIN_WAKE_0_BINARY <= "000010"; + when 3 => SATA_MIN_WAKE_0_BINARY <= "000011"; + when 4 => SATA_MIN_WAKE_0_BINARY <= "000100"; + when 5 => SATA_MIN_WAKE_0_BINARY <= "000101"; + when 6 => SATA_MIN_WAKE_0_BINARY <= "000110"; + when 7 => SATA_MIN_WAKE_0_BINARY <= "000111"; + when 8 => SATA_MIN_WAKE_0_BINARY <= "001000"; + when 9 => SATA_MIN_WAKE_0_BINARY <= "001001"; + when 10 => SATA_MIN_WAKE_0_BINARY <= "001010"; + when 11 => SATA_MIN_WAKE_0_BINARY <= "001011"; + when 12 => SATA_MIN_WAKE_0_BINARY <= "001100"; + when 13 => SATA_MIN_WAKE_0_BINARY <= "001101"; + when 14 => SATA_MIN_WAKE_0_BINARY <= "001110"; + when 15 => SATA_MIN_WAKE_0_BINARY <= "001111"; + when 16 => SATA_MIN_WAKE_0_BINARY <= "010000"; + when 17 => SATA_MIN_WAKE_0_BINARY <= "010001"; + when 18 => SATA_MIN_WAKE_0_BINARY <= "010010"; + when 19 => SATA_MIN_WAKE_0_BINARY <= "010011"; + when 20 => SATA_MIN_WAKE_0_BINARY <= "010100"; + when 21 => SATA_MIN_WAKE_0_BINARY <= "010101"; + when 22 => SATA_MIN_WAKE_0_BINARY <= "010110"; + when 23 => SATA_MIN_WAKE_0_BINARY <= "010111"; + when 24 => SATA_MIN_WAKE_0_BINARY <= "011000"; + when 25 => SATA_MIN_WAKE_0_BINARY <= "011001"; + when 26 => SATA_MIN_WAKE_0_BINARY <= "011010"; + when 27 => SATA_MIN_WAKE_0_BINARY <= "011011"; + when 28 => SATA_MIN_WAKE_0_BINARY <= "011100"; + when 29 => SATA_MIN_WAKE_0_BINARY <= "011101"; + when 30 => SATA_MIN_WAKE_0_BINARY <= "011110"; + when 31 => SATA_MIN_WAKE_0_BINARY <= "011111"; + when 32 => SATA_MIN_WAKE_0_BINARY <= "100000"; + when 33 => SATA_MIN_WAKE_0_BINARY <= "100001"; + when 34 => SATA_MIN_WAKE_0_BINARY <= "100010"; + when 35 => SATA_MIN_WAKE_0_BINARY <= "100011"; + when 36 => SATA_MIN_WAKE_0_BINARY <= "100100"; + when 37 => SATA_MIN_WAKE_0_BINARY <= "100101"; + when 38 => SATA_MIN_WAKE_0_BINARY <= "100110"; + when 39 => SATA_MIN_WAKE_0_BINARY <= "100111"; + when 40 => SATA_MIN_WAKE_0_BINARY <= "101000"; + when 41 => SATA_MIN_WAKE_0_BINARY <= "101001"; + when 42 => SATA_MIN_WAKE_0_BINARY <= "101010"; + when 43 => SATA_MIN_WAKE_0_BINARY <= "101011"; + when 44 => SATA_MIN_WAKE_0_BINARY <= "101100"; + when 45 => SATA_MIN_WAKE_0_BINARY <= "101101"; + when 46 => SATA_MIN_WAKE_0_BINARY <= "101110"; + when 47 => SATA_MIN_WAKE_0_BINARY <= "101111"; + when 48 => SATA_MIN_WAKE_0_BINARY <= "110000"; + when 49 => SATA_MIN_WAKE_0_BINARY <= "110001"; + when 50 => SATA_MIN_WAKE_0_BINARY <= "110010"; + when 51 => SATA_MIN_WAKE_0_BINARY <= "110011"; + when 52 => SATA_MIN_WAKE_0_BINARY <= "110100"; + when 53 => SATA_MIN_WAKE_0_BINARY <= "110101"; + when 54 => SATA_MIN_WAKE_0_BINARY <= "110110"; + when 55 => SATA_MIN_WAKE_0_BINARY <= "110111"; + when 56 => SATA_MIN_WAKE_0_BINARY <= "111000"; + when 57 => SATA_MIN_WAKE_0_BINARY <= "111001"; + when 58 => SATA_MIN_WAKE_0_BINARY <= "111010"; + when 59 => SATA_MIN_WAKE_0_BINARY <= "111011"; + when 60 => SATA_MIN_WAKE_0_BINARY <= "111100"; + when 61 => SATA_MIN_WAKE_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_WAKE_0 is not in range 1...61." severity error; + end case; + case SATA_MAX_WAKE_0 is + when 1 => SATA_MAX_WAKE_0_BINARY <= "000001"; + when 2 => SATA_MAX_WAKE_0_BINARY <= "000010"; + when 3 => SATA_MAX_WAKE_0_BINARY <= "000011"; + when 4 => SATA_MAX_WAKE_0_BINARY <= "000100"; + when 5 => SATA_MAX_WAKE_0_BINARY <= "000101"; + when 6 => SATA_MAX_WAKE_0_BINARY <= "000110"; + when 7 => SATA_MAX_WAKE_0_BINARY <= "000111"; + when 8 => SATA_MAX_WAKE_0_BINARY <= "001000"; + when 9 => SATA_MAX_WAKE_0_BINARY <= "001001"; + when 10 => SATA_MAX_WAKE_0_BINARY <= "001010"; + when 11 => SATA_MAX_WAKE_0_BINARY <= "001011"; + when 12 => SATA_MAX_WAKE_0_BINARY <= "001100"; + when 13 => SATA_MAX_WAKE_0_BINARY <= "001101"; + when 14 => SATA_MAX_WAKE_0_BINARY <= "001110"; + when 15 => SATA_MAX_WAKE_0_BINARY <= "001111"; + when 16 => SATA_MAX_WAKE_0_BINARY <= "010000"; + when 17 => SATA_MAX_WAKE_0_BINARY <= "010001"; + when 18 => SATA_MAX_WAKE_0_BINARY <= "010010"; + when 19 => SATA_MAX_WAKE_0_BINARY <= "010011"; + when 20 => SATA_MAX_WAKE_0_BINARY <= "010100"; + when 21 => SATA_MAX_WAKE_0_BINARY <= "010101"; + when 22 => SATA_MAX_WAKE_0_BINARY <= "010110"; + when 23 => SATA_MAX_WAKE_0_BINARY <= "010111"; + when 24 => SATA_MAX_WAKE_0_BINARY <= "011000"; + when 25 => SATA_MAX_WAKE_0_BINARY <= "011001"; + when 26 => SATA_MAX_WAKE_0_BINARY <= "011010"; + when 27 => SATA_MAX_WAKE_0_BINARY <= "011011"; + when 28 => SATA_MAX_WAKE_0_BINARY <= "011100"; + when 29 => SATA_MAX_WAKE_0_BINARY <= "011101"; + when 30 => SATA_MAX_WAKE_0_BINARY <= "011110"; + when 31 => SATA_MAX_WAKE_0_BINARY <= "011111"; + when 32 => SATA_MAX_WAKE_0_BINARY <= "100000"; + when 33 => SATA_MAX_WAKE_0_BINARY <= "100001"; + when 34 => SATA_MAX_WAKE_0_BINARY <= "100010"; + when 35 => SATA_MAX_WAKE_0_BINARY <= "100011"; + when 36 => SATA_MAX_WAKE_0_BINARY <= "100100"; + when 37 => SATA_MAX_WAKE_0_BINARY <= "100101"; + when 38 => SATA_MAX_WAKE_0_BINARY <= "100110"; + when 39 => SATA_MAX_WAKE_0_BINARY <= "100111"; + when 40 => SATA_MAX_WAKE_0_BINARY <= "101000"; + when 41 => SATA_MAX_WAKE_0_BINARY <= "101001"; + when 42 => SATA_MAX_WAKE_0_BINARY <= "101010"; + when 43 => SATA_MAX_WAKE_0_BINARY <= "101011"; + when 44 => SATA_MAX_WAKE_0_BINARY <= "101100"; + when 45 => SATA_MAX_WAKE_0_BINARY <= "101101"; + when 46 => SATA_MAX_WAKE_0_BINARY <= "101110"; + when 47 => SATA_MAX_WAKE_0_BINARY <= "101111"; + when 48 => SATA_MAX_WAKE_0_BINARY <= "110000"; + when 49 => SATA_MAX_WAKE_0_BINARY <= "110001"; + when 50 => SATA_MAX_WAKE_0_BINARY <= "110010"; + when 51 => SATA_MAX_WAKE_0_BINARY <= "110011"; + when 52 => SATA_MAX_WAKE_0_BINARY <= "110100"; + when 53 => SATA_MAX_WAKE_0_BINARY <= "110101"; + when 54 => SATA_MAX_WAKE_0_BINARY <= "110110"; + when 55 => SATA_MAX_WAKE_0_BINARY <= "110111"; + when 56 => SATA_MAX_WAKE_0_BINARY <= "111000"; + when 57 => SATA_MAX_WAKE_0_BINARY <= "111001"; + when 58 => SATA_MAX_WAKE_0_BINARY <= "111010"; + when 59 => SATA_MAX_WAKE_0_BINARY <= "111011"; + when 60 => SATA_MAX_WAKE_0_BINARY <= "111100"; + when 61 => SATA_MAX_WAKE_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_WAKE_0 is not in range 1...61." severity error; + end case; + case SATA_MIN_BURST_1 is + when 1 => SATA_MIN_BURST_1_BINARY <= "000001"; + when 2 => SATA_MIN_BURST_1_BINARY <= "000010"; + when 3 => SATA_MIN_BURST_1_BINARY <= "000011"; + when 4 => SATA_MIN_BURST_1_BINARY <= "000100"; + when 5 => SATA_MIN_BURST_1_BINARY <= "000101"; + when 6 => SATA_MIN_BURST_1_BINARY <= "000110"; + when 7 => SATA_MIN_BURST_1_BINARY <= "000111"; + when 8 => SATA_MIN_BURST_1_BINARY <= "001000"; + when 9 => SATA_MIN_BURST_1_BINARY <= "001001"; + when 10 => SATA_MIN_BURST_1_BINARY <= "001010"; + when 11 => SATA_MIN_BURST_1_BINARY <= "001011"; + when 12 => SATA_MIN_BURST_1_BINARY <= "001100"; + when 13 => SATA_MIN_BURST_1_BINARY <= "001101"; + when 14 => SATA_MIN_BURST_1_BINARY <= "001110"; + when 15 => SATA_MIN_BURST_1_BINARY <= "001111"; + when 16 => SATA_MIN_BURST_1_BINARY <= "010000"; + when 17 => SATA_MIN_BURST_1_BINARY <= "010001"; + when 18 => SATA_MIN_BURST_1_BINARY <= "010010"; + when 19 => SATA_MIN_BURST_1_BINARY <= "010011"; + when 20 => SATA_MIN_BURST_1_BINARY <= "010100"; + when 21 => SATA_MIN_BURST_1_BINARY <= "010101"; + when 22 => SATA_MIN_BURST_1_BINARY <= "010110"; + when 23 => SATA_MIN_BURST_1_BINARY <= "010111"; + when 24 => SATA_MIN_BURST_1_BINARY <= "011000"; + when 25 => SATA_MIN_BURST_1_BINARY <= "011001"; + when 26 => SATA_MIN_BURST_1_BINARY <= "011010"; + when 27 => SATA_MIN_BURST_1_BINARY <= "011011"; + when 28 => SATA_MIN_BURST_1_BINARY <= "011100"; + when 29 => SATA_MIN_BURST_1_BINARY <= "011101"; + when 30 => SATA_MIN_BURST_1_BINARY <= "011110"; + when 31 => SATA_MIN_BURST_1_BINARY <= "011111"; + when 32 => SATA_MIN_BURST_1_BINARY <= "100000"; + when 33 => SATA_MIN_BURST_1_BINARY <= "100001"; + when 34 => SATA_MIN_BURST_1_BINARY <= "100010"; + when 35 => SATA_MIN_BURST_1_BINARY <= "100011"; + when 36 => SATA_MIN_BURST_1_BINARY <= "100100"; + when 37 => SATA_MIN_BURST_1_BINARY <= "100101"; + when 38 => SATA_MIN_BURST_1_BINARY <= "100110"; + when 39 => SATA_MIN_BURST_1_BINARY <= "100111"; + when 40 => SATA_MIN_BURST_1_BINARY <= "101000"; + when 41 => SATA_MIN_BURST_1_BINARY <= "101001"; + when 42 => SATA_MIN_BURST_1_BINARY <= "101010"; + when 43 => SATA_MIN_BURST_1_BINARY <= "101011"; + when 44 => SATA_MIN_BURST_1_BINARY <= "101100"; + when 45 => SATA_MIN_BURST_1_BINARY <= "101101"; + when 46 => SATA_MIN_BURST_1_BINARY <= "101110"; + when 47 => SATA_MIN_BURST_1_BINARY <= "101111"; + when 48 => SATA_MIN_BURST_1_BINARY <= "110000"; + when 49 => SATA_MIN_BURST_1_BINARY <= "110001"; + when 50 => SATA_MIN_BURST_1_BINARY <= "110010"; + when 51 => SATA_MIN_BURST_1_BINARY <= "110011"; + when 52 => SATA_MIN_BURST_1_BINARY <= "110100"; + when 53 => SATA_MIN_BURST_1_BINARY <= "110101"; + when 54 => SATA_MIN_BURST_1_BINARY <= "110110"; + when 55 => SATA_MIN_BURST_1_BINARY <= "110111"; + when 56 => SATA_MIN_BURST_1_BINARY <= "111000"; + when 57 => SATA_MIN_BURST_1_BINARY <= "111001"; + when 58 => SATA_MIN_BURST_1_BINARY <= "111010"; + when 59 => SATA_MIN_BURST_1_BINARY <= "111011"; + when 60 => SATA_MIN_BURST_1_BINARY <= "111100"; + when 61 => SATA_MIN_BURST_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_BURST_1 is not in range 1...61." severity error; + end case; + case SATA_MAX_BURST_1 is + when 1 => SATA_MAX_BURST_1_BINARY <= "000001"; + when 2 => SATA_MAX_BURST_1_BINARY <= "000010"; + when 3 => SATA_MAX_BURST_1_BINARY <= "000011"; + when 4 => SATA_MAX_BURST_1_BINARY <= "000100"; + when 5 => SATA_MAX_BURST_1_BINARY <= "000101"; + when 6 => SATA_MAX_BURST_1_BINARY <= "000110"; + when 7 => SATA_MAX_BURST_1_BINARY <= "000111"; + when 8 => SATA_MAX_BURST_1_BINARY <= "001000"; + when 9 => SATA_MAX_BURST_1_BINARY <= "001001"; + when 10 => SATA_MAX_BURST_1_BINARY <= "001010"; + when 11 => SATA_MAX_BURST_1_BINARY <= "001011"; + when 12 => SATA_MAX_BURST_1_BINARY <= "001100"; + when 13 => SATA_MAX_BURST_1_BINARY <= "001101"; + when 14 => SATA_MAX_BURST_1_BINARY <= "001110"; + when 15 => SATA_MAX_BURST_1_BINARY <= "001111"; + when 16 => SATA_MAX_BURST_1_BINARY <= "010000"; + when 17 => SATA_MAX_BURST_1_BINARY <= "010001"; + when 18 => SATA_MAX_BURST_1_BINARY <= "010010"; + when 19 => SATA_MAX_BURST_1_BINARY <= "010011"; + when 20 => SATA_MAX_BURST_1_BINARY <= "010100"; + when 21 => SATA_MAX_BURST_1_BINARY <= "010101"; + when 22 => SATA_MAX_BURST_1_BINARY <= "010110"; + when 23 => SATA_MAX_BURST_1_BINARY <= "010111"; + when 24 => SATA_MAX_BURST_1_BINARY <= "011000"; + when 25 => SATA_MAX_BURST_1_BINARY <= "011001"; + when 26 => SATA_MAX_BURST_1_BINARY <= "011010"; + when 27 => SATA_MAX_BURST_1_BINARY <= "011011"; + when 28 => SATA_MAX_BURST_1_BINARY <= "011100"; + when 29 => SATA_MAX_BURST_1_BINARY <= "011101"; + when 30 => SATA_MAX_BURST_1_BINARY <= "011110"; + when 31 => SATA_MAX_BURST_1_BINARY <= "011111"; + when 32 => SATA_MAX_BURST_1_BINARY <= "100000"; + when 33 => SATA_MAX_BURST_1_BINARY <= "100001"; + when 34 => SATA_MAX_BURST_1_BINARY <= "100010"; + when 35 => SATA_MAX_BURST_1_BINARY <= "100011"; + when 36 => SATA_MAX_BURST_1_BINARY <= "100100"; + when 37 => SATA_MAX_BURST_1_BINARY <= "100101"; + when 38 => SATA_MAX_BURST_1_BINARY <= "100110"; + when 39 => SATA_MAX_BURST_1_BINARY <= "100111"; + when 40 => SATA_MAX_BURST_1_BINARY <= "101000"; + when 41 => SATA_MAX_BURST_1_BINARY <= "101001"; + when 42 => SATA_MAX_BURST_1_BINARY <= "101010"; + when 43 => SATA_MAX_BURST_1_BINARY <= "101011"; + when 44 => SATA_MAX_BURST_1_BINARY <= "101100"; + when 45 => SATA_MAX_BURST_1_BINARY <= "101101"; + when 46 => SATA_MAX_BURST_1_BINARY <= "101110"; + when 47 => SATA_MAX_BURST_1_BINARY <= "101111"; + when 48 => SATA_MAX_BURST_1_BINARY <= "110000"; + when 49 => SATA_MAX_BURST_1_BINARY <= "110001"; + when 50 => SATA_MAX_BURST_1_BINARY <= "110010"; + when 51 => SATA_MAX_BURST_1_BINARY <= "110011"; + when 52 => SATA_MAX_BURST_1_BINARY <= "110100"; + when 53 => SATA_MAX_BURST_1_BINARY <= "110101"; + when 54 => SATA_MAX_BURST_1_BINARY <= "110110"; + when 55 => SATA_MAX_BURST_1_BINARY <= "110111"; + when 56 => SATA_MAX_BURST_1_BINARY <= "111000"; + when 57 => SATA_MAX_BURST_1_BINARY <= "111001"; + when 58 => SATA_MAX_BURST_1_BINARY <= "111010"; + when 59 => SATA_MAX_BURST_1_BINARY <= "111011"; + when 60 => SATA_MAX_BURST_1_BINARY <= "111100"; + when 61 => SATA_MAX_BURST_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_BURST_1 is not in range 1...61." severity error; + end case; + case SATA_MIN_INIT_1 is + when 1 => SATA_MIN_INIT_1_BINARY <= "000001"; + when 2 => SATA_MIN_INIT_1_BINARY <= "000010"; + when 3 => SATA_MIN_INIT_1_BINARY <= "000011"; + when 4 => SATA_MIN_INIT_1_BINARY <= "000100"; + when 5 => SATA_MIN_INIT_1_BINARY <= "000101"; + when 6 => SATA_MIN_INIT_1_BINARY <= "000110"; + when 7 => SATA_MIN_INIT_1_BINARY <= "000111"; + when 8 => SATA_MIN_INIT_1_BINARY <= "001000"; + when 9 => SATA_MIN_INIT_1_BINARY <= "001001"; + when 10 => SATA_MIN_INIT_1_BINARY <= "001010"; + when 11 => SATA_MIN_INIT_1_BINARY <= "001011"; + when 12 => SATA_MIN_INIT_1_BINARY <= "001100"; + when 13 => SATA_MIN_INIT_1_BINARY <= "001101"; + when 14 => SATA_MIN_INIT_1_BINARY <= "001110"; + when 15 => SATA_MIN_INIT_1_BINARY <= "001111"; + when 16 => SATA_MIN_INIT_1_BINARY <= "010000"; + when 17 => SATA_MIN_INIT_1_BINARY <= "010001"; + when 18 => SATA_MIN_INIT_1_BINARY <= "010010"; + when 19 => SATA_MIN_INIT_1_BINARY <= "010011"; + when 20 => SATA_MIN_INIT_1_BINARY <= "010100"; + when 21 => SATA_MIN_INIT_1_BINARY <= "010101"; + when 22 => SATA_MIN_INIT_1_BINARY <= "010110"; + when 23 => SATA_MIN_INIT_1_BINARY <= "010111"; + when 24 => SATA_MIN_INIT_1_BINARY <= "011000"; + when 25 => SATA_MIN_INIT_1_BINARY <= "011001"; + when 26 => SATA_MIN_INIT_1_BINARY <= "011010"; + when 27 => SATA_MIN_INIT_1_BINARY <= "011011"; + when 28 => SATA_MIN_INIT_1_BINARY <= "011100"; + when 29 => SATA_MIN_INIT_1_BINARY <= "011101"; + when 30 => SATA_MIN_INIT_1_BINARY <= "011110"; + when 31 => SATA_MIN_INIT_1_BINARY <= "011111"; + when 32 => SATA_MIN_INIT_1_BINARY <= "100000"; + when 33 => SATA_MIN_INIT_1_BINARY <= "100001"; + when 34 => SATA_MIN_INIT_1_BINARY <= "100010"; + when 35 => SATA_MIN_INIT_1_BINARY <= "100011"; + when 36 => SATA_MIN_INIT_1_BINARY <= "100100"; + when 37 => SATA_MIN_INIT_1_BINARY <= "100101"; + when 38 => SATA_MIN_INIT_1_BINARY <= "100110"; + when 39 => SATA_MIN_INIT_1_BINARY <= "100111"; + when 40 => SATA_MIN_INIT_1_BINARY <= "101000"; + when 41 => SATA_MIN_INIT_1_BINARY <= "101001"; + when 42 => SATA_MIN_INIT_1_BINARY <= "101010"; + when 43 => SATA_MIN_INIT_1_BINARY <= "101011"; + when 44 => SATA_MIN_INIT_1_BINARY <= "101100"; + when 45 => SATA_MIN_INIT_1_BINARY <= "101101"; + when 46 => SATA_MIN_INIT_1_BINARY <= "101110"; + when 47 => SATA_MIN_INIT_1_BINARY <= "101111"; + when 48 => SATA_MIN_INIT_1_BINARY <= "110000"; + when 49 => SATA_MIN_INIT_1_BINARY <= "110001"; + when 50 => SATA_MIN_INIT_1_BINARY <= "110010"; + when 51 => SATA_MIN_INIT_1_BINARY <= "110011"; + when 52 => SATA_MIN_INIT_1_BINARY <= "110100"; + when 53 => SATA_MIN_INIT_1_BINARY <= "110101"; + when 54 => SATA_MIN_INIT_1_BINARY <= "110110"; + when 55 => SATA_MIN_INIT_1_BINARY <= "110111"; + when 56 => SATA_MIN_INIT_1_BINARY <= "111000"; + when 57 => SATA_MIN_INIT_1_BINARY <= "111001"; + when 58 => SATA_MIN_INIT_1_BINARY <= "111010"; + when 59 => SATA_MIN_INIT_1_BINARY <= "111011"; + when 60 => SATA_MIN_INIT_1_BINARY <= "111100"; + when 61 => SATA_MIN_INIT_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_INIT_1 is not in range 1...61." severity error; + end case; + case SATA_MAX_INIT_1 is + when 1 => SATA_MAX_INIT_1_BINARY <= "000001"; + when 2 => SATA_MAX_INIT_1_BINARY <= "000010"; + when 3 => SATA_MAX_INIT_1_BINARY <= "000011"; + when 4 => SATA_MAX_INIT_1_BINARY <= "000100"; + when 5 => SATA_MAX_INIT_1_BINARY <= "000101"; + when 6 => SATA_MAX_INIT_1_BINARY <= "000110"; + when 7 => SATA_MAX_INIT_1_BINARY <= "000111"; + when 8 => SATA_MAX_INIT_1_BINARY <= "001000"; + when 9 => SATA_MAX_INIT_1_BINARY <= "001001"; + when 10 => SATA_MAX_INIT_1_BINARY <= "001010"; + when 11 => SATA_MAX_INIT_1_BINARY <= "001011"; + when 12 => SATA_MAX_INIT_1_BINARY <= "001100"; + when 13 => SATA_MAX_INIT_1_BINARY <= "001101"; + when 14 => SATA_MAX_INIT_1_BINARY <= "001110"; + when 15 => SATA_MAX_INIT_1_BINARY <= "001111"; + when 16 => SATA_MAX_INIT_1_BINARY <= "010000"; + when 17 => SATA_MAX_INIT_1_BINARY <= "010001"; + when 18 => SATA_MAX_INIT_1_BINARY <= "010010"; + when 19 => SATA_MAX_INIT_1_BINARY <= "010011"; + when 20 => SATA_MAX_INIT_1_BINARY <= "010100"; + when 21 => SATA_MAX_INIT_1_BINARY <= "010101"; + when 22 => SATA_MAX_INIT_1_BINARY <= "010110"; + when 23 => SATA_MAX_INIT_1_BINARY <= "010111"; + when 24 => SATA_MAX_INIT_1_BINARY <= "011000"; + when 25 => SATA_MAX_INIT_1_BINARY <= "011001"; + when 26 => SATA_MAX_INIT_1_BINARY <= "011010"; + when 27 => SATA_MAX_INIT_1_BINARY <= "011011"; + when 28 => SATA_MAX_INIT_1_BINARY <= "011100"; + when 29 => SATA_MAX_INIT_1_BINARY <= "011101"; + when 30 => SATA_MAX_INIT_1_BINARY <= "011110"; + when 31 => SATA_MAX_INIT_1_BINARY <= "011111"; + when 32 => SATA_MAX_INIT_1_BINARY <= "100000"; + when 33 => SATA_MAX_INIT_1_BINARY <= "100001"; + when 34 => SATA_MAX_INIT_1_BINARY <= "100010"; + when 35 => SATA_MAX_INIT_1_BINARY <= "100011"; + when 36 => SATA_MAX_INIT_1_BINARY <= "100100"; + when 37 => SATA_MAX_INIT_1_BINARY <= "100101"; + when 38 => SATA_MAX_INIT_1_BINARY <= "100110"; + when 39 => SATA_MAX_INIT_1_BINARY <= "100111"; + when 40 => SATA_MAX_INIT_1_BINARY <= "101000"; + when 41 => SATA_MAX_INIT_1_BINARY <= "101001"; + when 42 => SATA_MAX_INIT_1_BINARY <= "101010"; + when 43 => SATA_MAX_INIT_1_BINARY <= "101011"; + when 44 => SATA_MAX_INIT_1_BINARY <= "101100"; + when 45 => SATA_MAX_INIT_1_BINARY <= "101101"; + when 46 => SATA_MAX_INIT_1_BINARY <= "101110"; + when 47 => SATA_MAX_INIT_1_BINARY <= "101111"; + when 48 => SATA_MAX_INIT_1_BINARY <= "110000"; + when 49 => SATA_MAX_INIT_1_BINARY <= "110001"; + when 50 => SATA_MAX_INIT_1_BINARY <= "110010"; + when 51 => SATA_MAX_INIT_1_BINARY <= "110011"; + when 52 => SATA_MAX_INIT_1_BINARY <= "110100"; + when 53 => SATA_MAX_INIT_1_BINARY <= "110101"; + when 54 => SATA_MAX_INIT_1_BINARY <= "110110"; + when 55 => SATA_MAX_INIT_1_BINARY <= "110111"; + when 56 => SATA_MAX_INIT_1_BINARY <= "111000"; + when 57 => SATA_MAX_INIT_1_BINARY <= "111001"; + when 58 => SATA_MAX_INIT_1_BINARY <= "111010"; + when 59 => SATA_MAX_INIT_1_BINARY <= "111011"; + when 60 => SATA_MAX_INIT_1_BINARY <= "111100"; + when 61 => SATA_MAX_INIT_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_INIT_1 is not in range 1...61." severity error; + end case; + case SATA_MIN_WAKE_1 is + when 1 => SATA_MIN_WAKE_1_BINARY <= "000001"; + when 2 => SATA_MIN_WAKE_1_BINARY <= "000010"; + when 3 => SATA_MIN_WAKE_1_BINARY <= "000011"; + when 4 => SATA_MIN_WAKE_1_BINARY <= "000100"; + when 5 => SATA_MIN_WAKE_1_BINARY <= "000101"; + when 6 => SATA_MIN_WAKE_1_BINARY <= "000110"; + when 7 => SATA_MIN_WAKE_1_BINARY <= "000111"; + when 8 => SATA_MIN_WAKE_1_BINARY <= "001000"; + when 9 => SATA_MIN_WAKE_1_BINARY <= "001001"; + when 10 => SATA_MIN_WAKE_1_BINARY <= "001010"; + when 11 => SATA_MIN_WAKE_1_BINARY <= "001011"; + when 12 => SATA_MIN_WAKE_1_BINARY <= "001100"; + when 13 => SATA_MIN_WAKE_1_BINARY <= "001101"; + when 14 => SATA_MIN_WAKE_1_BINARY <= "001110"; + when 15 => SATA_MIN_WAKE_1_BINARY <= "001111"; + when 16 => SATA_MIN_WAKE_1_BINARY <= "010000"; + when 17 => SATA_MIN_WAKE_1_BINARY <= "010001"; + when 18 => SATA_MIN_WAKE_1_BINARY <= "010010"; + when 19 => SATA_MIN_WAKE_1_BINARY <= "010011"; + when 20 => SATA_MIN_WAKE_1_BINARY <= "010100"; + when 21 => SATA_MIN_WAKE_1_BINARY <= "010101"; + when 22 => SATA_MIN_WAKE_1_BINARY <= "010110"; + when 23 => SATA_MIN_WAKE_1_BINARY <= "010111"; + when 24 => SATA_MIN_WAKE_1_BINARY <= "011000"; + when 25 => SATA_MIN_WAKE_1_BINARY <= "011001"; + when 26 => SATA_MIN_WAKE_1_BINARY <= "011010"; + when 27 => SATA_MIN_WAKE_1_BINARY <= "011011"; + when 28 => SATA_MIN_WAKE_1_BINARY <= "011100"; + when 29 => SATA_MIN_WAKE_1_BINARY <= "011101"; + when 30 => SATA_MIN_WAKE_1_BINARY <= "011110"; + when 31 => SATA_MIN_WAKE_1_BINARY <= "011111"; + when 32 => SATA_MIN_WAKE_1_BINARY <= "100000"; + when 33 => SATA_MIN_WAKE_1_BINARY <= "100001"; + when 34 => SATA_MIN_WAKE_1_BINARY <= "100010"; + when 35 => SATA_MIN_WAKE_1_BINARY <= "100011"; + when 36 => SATA_MIN_WAKE_1_BINARY <= "100100"; + when 37 => SATA_MIN_WAKE_1_BINARY <= "100101"; + when 38 => SATA_MIN_WAKE_1_BINARY <= "100110"; + when 39 => SATA_MIN_WAKE_1_BINARY <= "100111"; + when 40 => SATA_MIN_WAKE_1_BINARY <= "101000"; + when 41 => SATA_MIN_WAKE_1_BINARY <= "101001"; + when 42 => SATA_MIN_WAKE_1_BINARY <= "101010"; + when 43 => SATA_MIN_WAKE_1_BINARY <= "101011"; + when 44 => SATA_MIN_WAKE_1_BINARY <= "101100"; + when 45 => SATA_MIN_WAKE_1_BINARY <= "101101"; + when 46 => SATA_MIN_WAKE_1_BINARY <= "101110"; + when 47 => SATA_MIN_WAKE_1_BINARY <= "101111"; + when 48 => SATA_MIN_WAKE_1_BINARY <= "110000"; + when 49 => SATA_MIN_WAKE_1_BINARY <= "110001"; + when 50 => SATA_MIN_WAKE_1_BINARY <= "110010"; + when 51 => SATA_MIN_WAKE_1_BINARY <= "110011"; + when 52 => SATA_MIN_WAKE_1_BINARY <= "110100"; + when 53 => SATA_MIN_WAKE_1_BINARY <= "110101"; + when 54 => SATA_MIN_WAKE_1_BINARY <= "110110"; + when 55 => SATA_MIN_WAKE_1_BINARY <= "110111"; + when 56 => SATA_MIN_WAKE_1_BINARY <= "111000"; + when 57 => SATA_MIN_WAKE_1_BINARY <= "111001"; + when 58 => SATA_MIN_WAKE_1_BINARY <= "111010"; + when 59 => SATA_MIN_WAKE_1_BINARY <= "111011"; + when 60 => SATA_MIN_WAKE_1_BINARY <= "111100"; + when 61 => SATA_MIN_WAKE_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_WAKE_1 is not in range 1...61." severity error; + end case; + case SATA_MAX_WAKE_1 is + when 1 => SATA_MAX_WAKE_1_BINARY <= "000001"; + when 2 => SATA_MAX_WAKE_1_BINARY <= "000010"; + when 3 => SATA_MAX_WAKE_1_BINARY <= "000011"; + when 4 => SATA_MAX_WAKE_1_BINARY <= "000100"; + when 5 => SATA_MAX_WAKE_1_BINARY <= "000101"; + when 6 => SATA_MAX_WAKE_1_BINARY <= "000110"; + when 7 => SATA_MAX_WAKE_1_BINARY <= "000111"; + when 8 => SATA_MAX_WAKE_1_BINARY <= "001000"; + when 9 => SATA_MAX_WAKE_1_BINARY <= "001001"; + when 10 => SATA_MAX_WAKE_1_BINARY <= "001010"; + when 11 => SATA_MAX_WAKE_1_BINARY <= "001011"; + when 12 => SATA_MAX_WAKE_1_BINARY <= "001100"; + when 13 => SATA_MAX_WAKE_1_BINARY <= "001101"; + when 14 => SATA_MAX_WAKE_1_BINARY <= "001110"; + when 15 => SATA_MAX_WAKE_1_BINARY <= "001111"; + when 16 => SATA_MAX_WAKE_1_BINARY <= "010000"; + when 17 => SATA_MAX_WAKE_1_BINARY <= "010001"; + when 18 => SATA_MAX_WAKE_1_BINARY <= "010010"; + when 19 => SATA_MAX_WAKE_1_BINARY <= "010011"; + when 20 => SATA_MAX_WAKE_1_BINARY <= "010100"; + when 21 => SATA_MAX_WAKE_1_BINARY <= "010101"; + when 22 => SATA_MAX_WAKE_1_BINARY <= "010110"; + when 23 => SATA_MAX_WAKE_1_BINARY <= "010111"; + when 24 => SATA_MAX_WAKE_1_BINARY <= "011000"; + when 25 => SATA_MAX_WAKE_1_BINARY <= "011001"; + when 26 => SATA_MAX_WAKE_1_BINARY <= "011010"; + when 27 => SATA_MAX_WAKE_1_BINARY <= "011011"; + when 28 => SATA_MAX_WAKE_1_BINARY <= "011100"; + when 29 => SATA_MAX_WAKE_1_BINARY <= "011101"; + when 30 => SATA_MAX_WAKE_1_BINARY <= "011110"; + when 31 => SATA_MAX_WAKE_1_BINARY <= "011111"; + when 32 => SATA_MAX_WAKE_1_BINARY <= "100000"; + when 33 => SATA_MAX_WAKE_1_BINARY <= "100001"; + when 34 => SATA_MAX_WAKE_1_BINARY <= "100010"; + when 35 => SATA_MAX_WAKE_1_BINARY <= "100011"; + when 36 => SATA_MAX_WAKE_1_BINARY <= "100100"; + when 37 => SATA_MAX_WAKE_1_BINARY <= "100101"; + when 38 => SATA_MAX_WAKE_1_BINARY <= "100110"; + when 39 => SATA_MAX_WAKE_1_BINARY <= "100111"; + when 40 => SATA_MAX_WAKE_1_BINARY <= "101000"; + when 41 => SATA_MAX_WAKE_1_BINARY <= "101001"; + when 42 => SATA_MAX_WAKE_1_BINARY <= "101010"; + when 43 => SATA_MAX_WAKE_1_BINARY <= "101011"; + when 44 => SATA_MAX_WAKE_1_BINARY <= "101100"; + when 45 => SATA_MAX_WAKE_1_BINARY <= "101101"; + when 46 => SATA_MAX_WAKE_1_BINARY <= "101110"; + when 47 => SATA_MAX_WAKE_1_BINARY <= "101111"; + when 48 => SATA_MAX_WAKE_1_BINARY <= "110000"; + when 49 => SATA_MAX_WAKE_1_BINARY <= "110001"; + when 50 => SATA_MAX_WAKE_1_BINARY <= "110010"; + when 51 => SATA_MAX_WAKE_1_BINARY <= "110011"; + when 52 => SATA_MAX_WAKE_1_BINARY <= "110100"; + when 53 => SATA_MAX_WAKE_1_BINARY <= "110101"; + when 54 => SATA_MAX_WAKE_1_BINARY <= "110110"; + when 55 => SATA_MAX_WAKE_1_BINARY <= "110111"; + when 56 => SATA_MAX_WAKE_1_BINARY <= "111000"; + when 57 => SATA_MAX_WAKE_1_BINARY <= "111001"; + when 58 => SATA_MAX_WAKE_1_BINARY <= "111010"; + when 59 => SATA_MAX_WAKE_1_BINARY <= "111011"; + when 60 => SATA_MAX_WAKE_1_BINARY <= "111100"; + when 61 => SATA_MAX_WAKE_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_WAKE_1 is not in range 1...61." severity error; + end case; + case CLK25_DIVIDER is + when 1 => CLK25_DIVIDER_BINARY <= "000"; + when 2 => CLK25_DIVIDER_BINARY <= "001"; + when 3 => CLK25_DIVIDER_BINARY <= "010"; + when 4 => CLK25_DIVIDER_BINARY <= "011"; + when 5 => CLK25_DIVIDER_BINARY <= "100"; + when 6 => CLK25_DIVIDER_BINARY <= "101"; + when 10 => CLK25_DIVIDER_BINARY <= "110"; + when 12 => CLK25_DIVIDER_BINARY <= "111"; + when others => assert FALSE report "Error : CLK25_DIVIDER is not in 1, 2, 3, 4, 5, 6, 10, 12." severity error; + end case; + case OVERSAMPLE_MODE is + when FALSE => OVERSAMPLE_MODE_BINARY <= '0'; + when TRUE => OVERSAMPLE_MODE_BINARY <= '1'; + when others => assert FALSE report "Error : OVERSAMPLE_MODE is neither TRUE nor FALSE." severity error; + end case; + case SIM_GTPRESET_SPEEDUP is + when 0 => SIM_GTPRESET_SPEEDUP_BINARY <= '0'; + when 1 => SIM_GTPRESET_SPEEDUP_BINARY <= '1'; + when others => assert FALSE report "Error : SIM_GTPRESET_SPEEDUP is not in 0, 1." severity error; + end case; +-- case SIM_MODE is + if((SIM_MODE = "LEGACY") or (SIM_MODE = "legacy")) then + SIM_MODE_BINARY <= '1'; + elsif((SIM_MODE = "FAST") or (SIM_MODE = "fast")) then + SIM_MODE_BINARY <= '0'; + else + assert FALSE report "Error : SIM_MODE = is not LEGACY, FAST." severity error; + end if; +-- end case; + case SIM_RECEIVER_DETECT_PASS0 is + when FALSE => SIM_RECEIVER_DETECT_PASS0_BINARY <= '0'; + when TRUE => SIM_RECEIVER_DETECT_PASS0_BINARY <= '1'; + when others => assert FALSE report "Error : SIM_RECEIVER_DETECT_PASS0 is neither TRUE nor FALSE." severity error; + end case; + case SIM_RECEIVER_DETECT_PASS1 is + when FALSE => SIM_RECEIVER_DETECT_PASS1_BINARY <= '0'; + when TRUE => SIM_RECEIVER_DETECT_PASS1_BINARY <= '1'; + when others => assert FALSE report "Error : SIM_RECEIVER_DETECT_PASS1 is neither TRUE nor FALSE." severity error; + end case; + wait; + end process INIPROC; + + TIMING : process + +-- Pin timing violations (clock input pins) + +-- Pin Timing Violations (all input pins) + +-- Output Pin glitch declaration + variable REFCLKOUT_GlitchData : VitalGlitchDataType; + variable RXRECCLK0_GlitchData : VitalGlitchDataType; + variable TXOUTCLK0_GlitchData : VitalGlitchDataType; + variable RXRECCLK1_GlitchData : VitalGlitchDataType; + variable TXOUTCLK1_GlitchData : VitalGlitchDataType; + variable TXP0_GlitchData : VitalGlitchDataType; + variable TXN0_GlitchData : VitalGlitchDataType; + variable TXP1_GlitchData : VitalGlitchDataType; + variable TXN1_GlitchData : VitalGlitchDataType; + variable RXDATA00_GlitchData : VitalGlitchDataType; + variable RXDATA01_GlitchData : VitalGlitchDataType; + variable RXDATA02_GlitchData : VitalGlitchDataType; + variable RXDATA03_GlitchData : VitalGlitchDataType; + variable RXDATA04_GlitchData : VitalGlitchDataType; + variable RXDATA05_GlitchData : VitalGlitchDataType; + variable RXDATA06_GlitchData : VitalGlitchDataType; + variable RXDATA07_GlitchData : VitalGlitchDataType; + variable RXDATA08_GlitchData : VitalGlitchDataType; + variable RXDATA09_GlitchData : VitalGlitchDataType; + variable RXDATA010_GlitchData : VitalGlitchDataType; + variable RXDATA011_GlitchData : VitalGlitchDataType; + variable RXDATA012_GlitchData : VitalGlitchDataType; + variable RXDATA013_GlitchData : VitalGlitchDataType; + variable RXDATA014_GlitchData : VitalGlitchDataType; + variable RXDATA015_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE00_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE01_GlitchData : VitalGlitchDataType; + variable RXDISPERR00_GlitchData : VitalGlitchDataType; + variable RXDISPERR01_GlitchData : VitalGlitchDataType; + variable RXCHARISK00_GlitchData : VitalGlitchDataType; + variable RXCHARISK01_GlitchData : VitalGlitchDataType; + variable RXRUNDISP00_GlitchData : VitalGlitchDataType; + variable RXRUNDISP01_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA00_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA01_GlitchData : VitalGlitchDataType; + variable RXVALID0_GlitchData : VitalGlitchDataType; + variable RXDATA10_GlitchData : VitalGlitchDataType; + variable RXDATA11_GlitchData : VitalGlitchDataType; + variable RXDATA12_GlitchData : VitalGlitchDataType; + variable RXDATA13_GlitchData : VitalGlitchDataType; + variable RXDATA14_GlitchData : VitalGlitchDataType; + variable RXDATA15_GlitchData : VitalGlitchDataType; + variable RXDATA16_GlitchData : VitalGlitchDataType; + variable RXDATA17_GlitchData : VitalGlitchDataType; + variable RXDATA18_GlitchData : VitalGlitchDataType; + variable RXDATA19_GlitchData : VitalGlitchDataType; + variable RXDATA110_GlitchData : VitalGlitchDataType; + variable RXDATA111_GlitchData : VitalGlitchDataType; + variable RXDATA112_GlitchData : VitalGlitchDataType; + variable RXDATA113_GlitchData : VitalGlitchDataType; + variable RXDATA114_GlitchData : VitalGlitchDataType; + variable RXDATA115_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE10_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE11_GlitchData : VitalGlitchDataType; + variable RXDISPERR10_GlitchData : VitalGlitchDataType; + variable RXDISPERR11_GlitchData : VitalGlitchDataType; + variable RXCHARISK10_GlitchData : VitalGlitchDataType; + variable RXCHARISK11_GlitchData : VitalGlitchDataType; + variable RXRUNDISP10_GlitchData : VitalGlitchDataType; + variable RXRUNDISP11_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA10_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA11_GlitchData : VitalGlitchDataType; + variable RXVALID1_GlitchData : VitalGlitchDataType; + variable RESETDONE0_GlitchData : VitalGlitchDataType; + variable RESETDONE1_GlitchData : VitalGlitchDataType; + variable TXKERR00_GlitchData : VitalGlitchDataType; + variable TXKERR01_GlitchData : VitalGlitchDataType; + variable TXRUNDISP00_GlitchData : VitalGlitchDataType; + variable TXRUNDISP01_GlitchData : VitalGlitchDataType; + variable TXBUFSTATUS00_GlitchData : VitalGlitchDataType; + variable TXBUFSTATUS01_GlitchData : VitalGlitchDataType; + variable TXKERR10_GlitchData : VitalGlitchDataType; + variable TXKERR11_GlitchData : VitalGlitchDataType; + variable TXRUNDISP10_GlitchData : VitalGlitchDataType; + variable TXRUNDISP11_GlitchData : VitalGlitchDataType; + variable TXBUFSTATUS10_GlitchData : VitalGlitchDataType; + variable TXBUFSTATUS11_GlitchData : VitalGlitchDataType; + variable RXCOMMADET0_GlitchData : VitalGlitchDataType; + variable RXBYTEREALIGN0_GlitchData : VitalGlitchDataType; + variable RXBYTEISALIGNED0_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC00_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC01_GlitchData : VitalGlitchDataType; + variable RXCHBONDO00_GlitchData : VitalGlitchDataType; + variable RXCHBONDO01_GlitchData : VitalGlitchDataType; + variable RXCHBONDO02_GlitchData : VitalGlitchDataType; + variable RXCHANBONDSEQ0_GlitchData : VitalGlitchDataType; + variable RXCHANREALIGN0_GlitchData : VitalGlitchDataType; + variable RXCHANISALIGNED0_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS00_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS01_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS02_GlitchData : VitalGlitchDataType; + variable RXCOMMADET1_GlitchData : VitalGlitchDataType; + variable RXBYTEREALIGN1_GlitchData : VitalGlitchDataType; + variable RXBYTEISALIGNED1_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC10_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC11_GlitchData : VitalGlitchDataType; + variable RXCHBONDO10_GlitchData : VitalGlitchDataType; + variable RXCHBONDO11_GlitchData : VitalGlitchDataType; + variable RXCHBONDO12_GlitchData : VitalGlitchDataType; + variable RXCHANBONDSEQ1_GlitchData : VitalGlitchDataType; + variable RXCHANREALIGN1_GlitchData : VitalGlitchDataType; + variable RXCHANISALIGNED1_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS10_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS11_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS12_GlitchData : VitalGlitchDataType; + variable PHYSTATUS0_GlitchData : VitalGlitchDataType; + variable PHYSTATUS1_GlitchData : VitalGlitchDataType; + variable RXELECIDLE0_GlitchData : VitalGlitchDataType; + variable RXSTATUS00_GlitchData : VitalGlitchDataType; + variable RXSTATUS01_GlitchData : VitalGlitchDataType; + variable RXSTATUS02_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT00_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT01_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT02_GlitchData : VitalGlitchDataType; + variable RXELECIDLE1_GlitchData : VitalGlitchDataType; + variable RXSTATUS10_GlitchData : VitalGlitchDataType; + variable RXSTATUS11_GlitchData : VitalGlitchDataType; + variable RXSTATUS12_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT10_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT11_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT12_GlitchData : VitalGlitchDataType; + variable PLLLKDET_GlitchData : VitalGlitchDataType; + variable RXPRBSERR0_GlitchData : VitalGlitchDataType; + variable RXPRBSERR1_GlitchData : VitalGlitchDataType; + variable DO0_GlitchData : VitalGlitchDataType; + variable DO1_GlitchData : VitalGlitchDataType; + variable DO2_GlitchData : VitalGlitchDataType; + variable DO3_GlitchData : VitalGlitchDataType; + variable DO4_GlitchData : VitalGlitchDataType; + variable DO5_GlitchData : VitalGlitchDataType; + variable DO6_GlitchData : VitalGlitchDataType; + variable DO7_GlitchData : VitalGlitchDataType; + variable DO8_GlitchData : VitalGlitchDataType; + variable DO9_GlitchData : VitalGlitchDataType; + variable DO10_GlitchData : VitalGlitchDataType; + variable DO11_GlitchData : VitalGlitchDataType; + variable DO12_GlitchData : VitalGlitchDataType; + variable DO13_GlitchData : VitalGlitchDataType; + variable DO14_GlitchData : VitalGlitchDataType; + variable DO15_GlitchData : VitalGlitchDataType; + variable DRDY_GlitchData : VitalGlitchDataType; + variable RXOVERSAMPLEERR0_GlitchData : VitalGlitchDataType; + variable RXOVERSAMPLEERR1_GlitchData : VitalGlitchDataType; +begin + +-- Output-to-Clock path delay + VitalPathDelay01 + ( + OutSignal => REFCLKOUT, + GlitchData => REFCLKOUT_GlitchData, + OutSignalName => "REFCLKOUT", + OutTemp => REFCLKOUT_OUT, + Paths => (0 => (CLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(0), + GlitchData => RXDATA00_GlitchData, + OutSignalName => "RXDATA0(0)", + OutTemp => RXDATA0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(1), + GlitchData => RXDATA01_GlitchData, + OutSignalName => "RXDATA0(1)", + OutTemp => RXDATA0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(2), + GlitchData => RXDATA02_GlitchData, + OutSignalName => "RXDATA0(2)", + OutTemp => RXDATA0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(3), + GlitchData => RXDATA03_GlitchData, + OutSignalName => "RXDATA0(3)", + OutTemp => RXDATA0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(4), + GlitchData => RXDATA04_GlitchData, + OutSignalName => "RXDATA0(4)", + OutTemp => RXDATA0_OUT(4), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(5), + GlitchData => RXDATA05_GlitchData, + OutSignalName => "RXDATA0(5)", + OutTemp => RXDATA0_OUT(5), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(6), + GlitchData => RXDATA06_GlitchData, + OutSignalName => "RXDATA0(6)", + OutTemp => RXDATA0_OUT(6), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(7), + GlitchData => RXDATA07_GlitchData, + OutSignalName => "RXDATA0(7)", + OutTemp => RXDATA0_OUT(7), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(8), + GlitchData => RXDATA08_GlitchData, + OutSignalName => "RXDATA0(8)", + OutTemp => RXDATA0_OUT(8), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(9), + GlitchData => RXDATA09_GlitchData, + OutSignalName => "RXDATA0(9)", + OutTemp => RXDATA0_OUT(9), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(10), + GlitchData => RXDATA010_GlitchData, + OutSignalName => "RXDATA0(10)", + OutTemp => RXDATA0_OUT(10), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(11), + GlitchData => RXDATA011_GlitchData, + OutSignalName => "RXDATA0(11)", + OutTemp => RXDATA0_OUT(11), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(12), + GlitchData => RXDATA012_GlitchData, + OutSignalName => "RXDATA0(12)", + OutTemp => RXDATA0_OUT(12), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(13), + GlitchData => RXDATA013_GlitchData, + OutSignalName => "RXDATA0(13)", + OutTemp => RXDATA0_OUT(13), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(14), + GlitchData => RXDATA014_GlitchData, + OutSignalName => "RXDATA0(14)", + OutTemp => RXDATA0_OUT(14), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(15), + GlitchData => RXDATA015_GlitchData, + OutSignalName => "RXDATA0(15)", + OutTemp => RXDATA0_OUT(15), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE0(0), + GlitchData => RXNOTINTABLE00_GlitchData, + OutSignalName => "RXNOTINTABLE0(0)", + OutTemp => RXNOTINTABLE0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE0(1), + GlitchData => RXNOTINTABLE01_GlitchData, + OutSignalName => "RXNOTINTABLE0(1)", + OutTemp => RXNOTINTABLE0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR0(0), + GlitchData => RXDISPERR00_GlitchData, + OutSignalName => "RXDISPERR0(0)", + OutTemp => RXDISPERR0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR0(1), + GlitchData => RXDISPERR01_GlitchData, + OutSignalName => "RXDISPERR0(1)", + OutTemp => RXDISPERR0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK0(0), + GlitchData => RXCHARISK00_GlitchData, + OutSignalName => "RXCHARISK0(0)", + OutTemp => RXCHARISK0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK0(1), + GlitchData => RXCHARISK01_GlitchData, + OutSignalName => "RXCHARISK0(1)", + OutTemp => RXCHARISK0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP0(0), + GlitchData => RXRUNDISP00_GlitchData, + OutSignalName => "RXRUNDISP0(0)", + OutTemp => RXRUNDISP0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP0(1), + GlitchData => RXRUNDISP01_GlitchData, + OutSignalName => "RXRUNDISP0(1)", + OutTemp => RXRUNDISP0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA0(0), + GlitchData => RXCHARISCOMMA00_GlitchData, + OutSignalName => "RXCHARISCOMMA0(0)", + OutTemp => RXCHARISCOMMA0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA0(1), + GlitchData => RXCHARISCOMMA01_GlitchData, + OutSignalName => "RXCHARISCOMMA0(1)", + OutTemp => RXCHARISCOMMA0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXVALID0, + GlitchData => RXVALID0_GlitchData, + OutSignalName => "RXVALID0", + OutTemp => RXVALID0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(0), + GlitchData => RXDATA10_GlitchData, + OutSignalName => "RXDATA1(0)", + OutTemp => RXDATA1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(1), + GlitchData => RXDATA11_GlitchData, + OutSignalName => "RXDATA1(1)", + OutTemp => RXDATA1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(2), + GlitchData => RXDATA12_GlitchData, + OutSignalName => "RXDATA1(2)", + OutTemp => RXDATA1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(3), + GlitchData => RXDATA13_GlitchData, + OutSignalName => "RXDATA1(3)", + OutTemp => RXDATA1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(4), + GlitchData => RXDATA14_GlitchData, + OutSignalName => "RXDATA1(4)", + OutTemp => RXDATA1_OUT(4), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(5), + GlitchData => RXDATA15_GlitchData, + OutSignalName => "RXDATA1(5)", + OutTemp => RXDATA1_OUT(5), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(6), + GlitchData => RXDATA16_GlitchData, + OutSignalName => "RXDATA1(6)", + OutTemp => RXDATA1_OUT(6), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(7), + GlitchData => RXDATA17_GlitchData, + OutSignalName => "RXDATA1(7)", + OutTemp => RXDATA1_OUT(7), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(8), + GlitchData => RXDATA18_GlitchData, + OutSignalName => "RXDATA1(8)", + OutTemp => RXDATA1_OUT(8), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(9), + GlitchData => RXDATA19_GlitchData, + OutSignalName => "RXDATA1(9)", + OutTemp => RXDATA1_OUT(9), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(10), + GlitchData => RXDATA110_GlitchData, + OutSignalName => "RXDATA1(10)", + OutTemp => RXDATA1_OUT(10), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(11), + GlitchData => RXDATA111_GlitchData, + OutSignalName => "RXDATA1(11)", + OutTemp => RXDATA1_OUT(11), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(12), + GlitchData => RXDATA112_GlitchData, + OutSignalName => "RXDATA1(12)", + OutTemp => RXDATA1_OUT(12), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(13), + GlitchData => RXDATA113_GlitchData, + OutSignalName => "RXDATA1(13)", + OutTemp => RXDATA1_OUT(13), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(14), + GlitchData => RXDATA114_GlitchData, + OutSignalName => "RXDATA1(14)", + OutTemp => RXDATA1_OUT(14), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(15), + GlitchData => RXDATA115_GlitchData, + OutSignalName => "RXDATA1(15)", + OutTemp => RXDATA1_OUT(15), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE1(0), + GlitchData => RXNOTINTABLE10_GlitchData, + OutSignalName => "RXNOTINTABLE1(0)", + OutTemp => RXNOTINTABLE1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE1(1), + GlitchData => RXNOTINTABLE11_GlitchData, + OutSignalName => "RXNOTINTABLE1(1)", + OutTemp => RXNOTINTABLE1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR1(0), + GlitchData => RXDISPERR10_GlitchData, + OutSignalName => "RXDISPERR1(0)", + OutTemp => RXDISPERR1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR1(1), + GlitchData => RXDISPERR11_GlitchData, + OutSignalName => "RXDISPERR1(1)", + OutTemp => RXDISPERR1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK1(0), + GlitchData => RXCHARISK10_GlitchData, + OutSignalName => "RXCHARISK1(0)", + OutTemp => RXCHARISK1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK1(1), + GlitchData => RXCHARISK11_GlitchData, + OutSignalName => "RXCHARISK1(1)", + OutTemp => RXCHARISK1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP1(0), + GlitchData => RXRUNDISP10_GlitchData, + OutSignalName => "RXRUNDISP1(0)", + OutTemp => RXRUNDISP1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP1(1), + GlitchData => RXRUNDISP11_GlitchData, + OutSignalName => "RXRUNDISP1(1)", + OutTemp => RXRUNDISP1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA1(0), + GlitchData => RXCHARISCOMMA10_GlitchData, + OutSignalName => "RXCHARISCOMMA1(0)", + OutTemp => RXCHARISCOMMA1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA1(1), + GlitchData => RXCHARISCOMMA11_GlitchData, + OutSignalName => "RXCHARISCOMMA1(1)", + OutTemp => RXCHARISCOMMA1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXVALID1, + GlitchData => RXVALID1_GlitchData, + OutSignalName => "RXVALID1", + OutTemp => RXVALID1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR0(0), + GlitchData => TXKERR00_GlitchData, + OutSignalName => "TXKERR0(0)", + OutTemp => TXKERR0_OUT(0), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR0(1), + GlitchData => TXKERR01_GlitchData, + OutSignalName => "TXKERR0(1)", + OutTemp => TXKERR0_OUT(1), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP0(0), + GlitchData => TXRUNDISP00_GlitchData, + OutSignalName => "TXRUNDISP0(0)", + OutTemp => TXRUNDISP0_OUT(0), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP0(1), + GlitchData => TXRUNDISP01_GlitchData, + OutSignalName => "TXRUNDISP0(1)", + OutTemp => TXRUNDISP0_OUT(1), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXBUFSTATUS0(0), + GlitchData => TXBUFSTATUS00_GlitchData, + OutSignalName => "TXBUFSTATUS0(0)", + OutTemp => TXBUFSTATUS0_OUT(0), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXBUFSTATUS0(1), + GlitchData => TXBUFSTATUS01_GlitchData, + OutSignalName => "TXBUFSTATUS0(1)", + OutTemp => TXBUFSTATUS0_OUT(1), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR1(0), + GlitchData => TXKERR10_GlitchData, + OutSignalName => "TXKERR1(0)", + OutTemp => TXKERR1_OUT(0), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR1(1), + GlitchData => TXKERR11_GlitchData, + OutSignalName => "TXKERR1(1)", + OutTemp => TXKERR1_OUT(1), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP1(0), + GlitchData => TXRUNDISP10_GlitchData, + OutSignalName => "TXRUNDISP1(0)", + OutTemp => TXRUNDISP1_OUT(0), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP1(1), + GlitchData => TXRUNDISP11_GlitchData, + OutSignalName => "TXRUNDISP1(1)", + OutTemp => TXRUNDISP1_OUT(1), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXBUFSTATUS1(0), + GlitchData => TXBUFSTATUS10_GlitchData, + OutSignalName => "TXBUFSTATUS1(0)", + OutTemp => TXBUFSTATUS1_OUT(0), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXBUFSTATUS1(1), + GlitchData => TXBUFSTATUS11_GlitchData, + OutSignalName => "TXBUFSTATUS1(1)", + OutTemp => TXBUFSTATUS1_OUT(1), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCOMMADET0, + GlitchData => RXCOMMADET0_GlitchData, + OutSignalName => "RXCOMMADET0", + OutTemp => RXCOMMADET0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBYTEREALIGN0, + GlitchData => RXBYTEREALIGN0_GlitchData, + OutSignalName => "RXBYTEREALIGN0", + OutTemp => RXBYTEREALIGN0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBYTEISALIGNED0, + GlitchData => RXBYTEISALIGNED0_GlitchData, + OutSignalName => "RXBYTEISALIGNED0", + OutTemp => RXBYTEISALIGNED0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC0(0), + GlitchData => RXLOSSOFSYNC00_GlitchData, + OutSignalName => "RXLOSSOFSYNC0(0)", + OutTemp => RXLOSSOFSYNC0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC0(1), + GlitchData => RXLOSSOFSYNC01_GlitchData, + OutSignalName => "RXLOSSOFSYNC0(1)", + OutTemp => RXLOSSOFSYNC0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO0(0), + GlitchData => RXCHBONDO00_GlitchData, + OutSignalName => "RXCHBONDO0(0)", + OutTemp => RXCHBONDO0_OUT(0), + Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO0(1), + GlitchData => RXCHBONDO01_GlitchData, + OutSignalName => "RXCHBONDO0(1)", + OutTemp => RXCHBONDO0_OUT(1), + Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO0(2), + GlitchData => RXCHBONDO02_GlitchData, + OutSignalName => "RXCHBONDO0(2)", + OutTemp => RXCHBONDO0_OUT(2), + Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANBONDSEQ0, + GlitchData => RXCHANBONDSEQ0_GlitchData, + OutSignalName => "RXCHANBONDSEQ0", + OutTemp => RXCHANBONDSEQ0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANREALIGN0, + GlitchData => RXCHANREALIGN0_GlitchData, + OutSignalName => "RXCHANREALIGN0", + OutTemp => RXCHANREALIGN0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANISALIGNED0, + GlitchData => RXCHANISALIGNED0_GlitchData, + OutSignalName => "RXCHANISALIGNED0", + OutTemp => RXCHANISALIGNED0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS0(0), + GlitchData => RXBUFSTATUS00_GlitchData, + OutSignalName => "RXBUFSTATUS0(0)", + OutTemp => RXBUFSTATUS0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS0(1), + GlitchData => RXBUFSTATUS01_GlitchData, + OutSignalName => "RXBUFSTATUS0(1)", + OutTemp => RXBUFSTATUS0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS0(2), + GlitchData => RXBUFSTATUS02_GlitchData, + OutSignalName => "RXBUFSTATUS0(2)", + OutTemp => RXBUFSTATUS0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCOMMADET1, + GlitchData => RXCOMMADET1_GlitchData, + OutSignalName => "RXCOMMADET1", + OutTemp => RXCOMMADET1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBYTEREALIGN1, + GlitchData => RXBYTEREALIGN1_GlitchData, + OutSignalName => "RXBYTEREALIGN1", + OutTemp => RXBYTEREALIGN1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBYTEISALIGNED1, + GlitchData => RXBYTEISALIGNED1_GlitchData, + OutSignalName => "RXBYTEISALIGNED1", + OutTemp => RXBYTEISALIGNED1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC1(0), + GlitchData => RXLOSSOFSYNC10_GlitchData, + OutSignalName => "RXLOSSOFSYNC1(0)", + OutTemp => RXLOSSOFSYNC1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC1(1), + GlitchData => RXLOSSOFSYNC11_GlitchData, + OutSignalName => "RXLOSSOFSYNC1(1)", + OutTemp => RXLOSSOFSYNC1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO1(0), + GlitchData => RXCHBONDO10_GlitchData, + OutSignalName => "RXCHBONDO1(0)", + OutTemp => RXCHBONDO1_OUT(0), + Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO1(1), + GlitchData => RXCHBONDO11_GlitchData, + OutSignalName => "RXCHBONDO1(1)", + OutTemp => RXCHBONDO1_OUT(1), + Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO1(2), + GlitchData => RXCHBONDO12_GlitchData, + OutSignalName => "RXCHBONDO1(2)", + OutTemp => RXCHBONDO1_OUT(2), + Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANBONDSEQ1, + GlitchData => RXCHANBONDSEQ1_GlitchData, + OutSignalName => "RXCHANBONDSEQ1", + OutTemp => RXCHANBONDSEQ1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANREALIGN1, + GlitchData => RXCHANREALIGN1_GlitchData, + OutSignalName => "RXCHANREALIGN1", + OutTemp => RXCHANREALIGN1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANISALIGNED1, + GlitchData => RXCHANISALIGNED1_GlitchData, + OutSignalName => "RXCHANISALIGNED1", + OutTemp => RXCHANISALIGNED1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS1(0), + GlitchData => RXBUFSTATUS10_GlitchData, + OutSignalName => "RXBUFSTATUS1(0)", + OutTemp => RXBUFSTATUS1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS1(1), + GlitchData => RXBUFSTATUS11_GlitchData, + OutSignalName => "RXBUFSTATUS1(1)", + OutTemp => RXBUFSTATUS1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS1(2), + GlitchData => RXBUFSTATUS12_GlitchData, + OutSignalName => "RXBUFSTATUS1(2)", + OutTemp => RXBUFSTATUS1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS0(0), + GlitchData => RXSTATUS00_GlitchData, + OutSignalName => "RXSTATUS0(0)", + OutTemp => RXSTATUS0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS0(1), + GlitchData => RXSTATUS01_GlitchData, + OutSignalName => "RXSTATUS0(1)", + OutTemp => RXSTATUS0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS0(2), + GlitchData => RXSTATUS02_GlitchData, + OutSignalName => "RXSTATUS0(2)", + OutTemp => RXSTATUS0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT0(0), + GlitchData => RXCLKCORCNT00_GlitchData, + OutSignalName => "RXCLKCORCNT0(0)", + OutTemp => RXCLKCORCNT0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT0(1), + GlitchData => RXCLKCORCNT01_GlitchData, + OutSignalName => "RXCLKCORCNT0(1)", + OutTemp => RXCLKCORCNT0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT0(2), + GlitchData => RXCLKCORCNT02_GlitchData, + OutSignalName => "RXCLKCORCNT0(2)", + OutTemp => RXCLKCORCNT0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS1(0), + GlitchData => RXSTATUS10_GlitchData, + OutSignalName => "RXSTATUS1(0)", + OutTemp => RXSTATUS1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS1(1), + GlitchData => RXSTATUS11_GlitchData, + OutSignalName => "RXSTATUS1(1)", + OutTemp => RXSTATUS1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS1(2), + GlitchData => RXSTATUS12_GlitchData, + OutSignalName => "RXSTATUS1(2)", + OutTemp => RXSTATUS1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT1(0), + GlitchData => RXCLKCORCNT10_GlitchData, + OutSignalName => "RXCLKCORCNT1(0)", + OutTemp => RXCLKCORCNT1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT1(1), + GlitchData => RXCLKCORCNT11_GlitchData, + OutSignalName => "RXCLKCORCNT1(1)", + OutTemp => RXCLKCORCNT1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT1(2), + GlitchData => RXCLKCORCNT12_GlitchData, + OutSignalName => "RXCLKCORCNT1(2)", + OutTemp => RXCLKCORCNT1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXPRBSERR0, + GlitchData => RXPRBSERR0_GlitchData, + OutSignalName => "RXPRBSERR0", + OutTemp => RXPRBSERR0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXPRBSERR1, + GlitchData => RXPRBSERR1_GlitchData, + OutSignalName => "RXPRBSERR1", + OutTemp => RXPRBSERR1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(0), + GlitchData => DO0_GlitchData, + OutSignalName => "DO(0)", + OutTemp => DO_OUT(0), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(1), + GlitchData => DO1_GlitchData, + OutSignalName => "DO(1)", + OutTemp => DO_OUT(1), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(2), + GlitchData => DO2_GlitchData, + OutSignalName => "DO(2)", + OutTemp => DO_OUT(2), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(3), + GlitchData => DO3_GlitchData, + OutSignalName => "DO(3)", + OutTemp => DO_OUT(3), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(4), + GlitchData => DO4_GlitchData, + OutSignalName => "DO(4)", + OutTemp => DO_OUT(4), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(5), + GlitchData => DO5_GlitchData, + OutSignalName => "DO(5)", + OutTemp => DO_OUT(5), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(6), + GlitchData => DO6_GlitchData, + OutSignalName => "DO(6)", + OutTemp => DO_OUT(6), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(7), + GlitchData => DO7_GlitchData, + OutSignalName => "DO(7)", + OutTemp => DO_OUT(7), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(8), + GlitchData => DO8_GlitchData, + OutSignalName => "DO(8)", + OutTemp => DO_OUT(8), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(9), + GlitchData => DO9_GlitchData, + OutSignalName => "DO(9)", + OutTemp => DO_OUT(9), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(10), + GlitchData => DO10_GlitchData, + OutSignalName => "DO(10)", + OutTemp => DO_OUT(10), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(11), + GlitchData => DO11_GlitchData, + OutSignalName => "DO(11)", + OutTemp => DO_OUT(11), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(12), + GlitchData => DO12_GlitchData, + OutSignalName => "DO(12)", + OutTemp => DO_OUT(12), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(13), + GlitchData => DO13_GlitchData, + OutSignalName => "DO(13)", + OutTemp => DO_OUT(13), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(14), + GlitchData => DO14_GlitchData, + OutSignalName => "DO(14)", + OutTemp => DO_OUT(14), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(15), + GlitchData => DO15_GlitchData, + OutSignalName => "DO(15)", + OutTemp => DO_OUT(15), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DRDY, + GlitchData => DRDY_GlitchData, + OutSignalName => "DRDY", + OutTemp => DRDY_OUT, + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXOVERSAMPLEERR0, + GlitchData => RXOVERSAMPLEERR0_GlitchData, + OutSignalName => "RXOVERSAMPLEERR0", + OutTemp => RXOVERSAMPLEERR0_OUT, + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXOVERSAMPLEERR1, + GlitchData => RXOVERSAMPLEERR1_GlitchData, + OutSignalName => "RXOVERSAMPLEERR1", + OutTemp => RXOVERSAMPLEERR1_OUT, + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + + +-- Wait signal (input/output pins) + wait on + DO_out, + DRDY_out, + REFCLKOUT_out, + RXBUFSTATUS0_out, + RXBUFSTATUS1_out, + RXBYTEISALIGNED0_out, + RXBYTEISALIGNED1_out, + RXBYTEREALIGN0_out, + RXBYTEREALIGN1_out, + RXCHANBONDSEQ0_out, + RXCHANBONDSEQ1_out, + RXCHANISALIGNED0_out, + RXCHANISALIGNED1_out, + RXCHANREALIGN0_out, + RXCHANREALIGN1_out, + RXCHARISCOMMA0_out, + RXCHARISCOMMA1_out, + RXCHARISK0_out, + RXCHARISK1_out, + RXCHBONDO0_out, + RXCHBONDO1_out, + RXCLKCORCNT0_out, + RXCLKCORCNT1_out, + RXCOMMADET0_out, + RXCOMMADET1_out, + RXDATA0_out, + RXDATA1_out, + RXDISPERR0_out, + RXDISPERR1_out, + RXLOSSOFSYNC0_out, + RXLOSSOFSYNC1_out, + RXNOTINTABLE0_out, + RXNOTINTABLE1_out, + RXOVERSAMPLEERR0_out, + RXOVERSAMPLEERR1_out, + RXPRBSERR0_out, + RXPRBSERR1_out, + RXRUNDISP0_out, + RXRUNDISP1_out, + RXSTATUS0_out, + RXSTATUS1_out, + RXVALID0_out, + RXVALID1_out, + TXBUFSTATUS0_out, + TXBUFSTATUS1_out, + TXKERR0_out, + TXKERR1_out, + TXRUNDISP0_out, + TXRUNDISP1_out, + + CLKIN_ipd, + DADDR_ipd, + DCLK_ipd, + DEN_ipd, + DI_ipd, + DWE_ipd, + GTPRESET_ipd, + GTPTEST_ipd, + INTDATAWIDTH_ipd, + LOOPBACK0_ipd, + LOOPBACK1_ipd, + PLLLKDETEN_ipd, + PLLPOWERDOWN_ipd, + PRBSCNTRESET0_ipd, + PRBSCNTRESET1_ipd, + REFCLKPWRDNB_ipd, + RXBUFRESET0_ipd, + RXBUFRESET1_ipd, + RXCDRRESET0_ipd, + RXCDRRESET1_ipd, + RXCHBONDI0_ipd, + RXCHBONDI1_ipd, + RXCOMMADETUSE0_ipd, + RXCOMMADETUSE1_ipd, + RXDATAWIDTH0_ipd, + RXDATAWIDTH1_ipd, + RXDEC8B10BUSE0_ipd, + RXDEC8B10BUSE1_ipd, + RXELECIDLERESET0_ipd, + RXELECIDLERESET1_ipd, + RXENCHANSYNC0_ipd, + RXENCHANSYNC1_ipd, + RXENELECIDLERESETB_ipd, + RXENEQB0_ipd, + RXENEQB1_ipd, + RXENMCOMMAALIGN0_ipd, + RXENMCOMMAALIGN1_ipd, + RXENPCOMMAALIGN0_ipd, + RXENPCOMMAALIGN1_ipd, + RXENPRBSTST0_ipd, + RXENPRBSTST1_ipd, + RXENSAMPLEALIGN0_ipd, + RXENSAMPLEALIGN1_ipd, + RXEQMIX0_ipd, + RXEQMIX1_ipd, + RXEQPOLE0_ipd, + RXEQPOLE1_ipd, + RXN0_ipd, + RXN1_ipd, + RXP0_ipd, + RXP1_ipd, + RXPMASETPHASE0_ipd, + RXPMASETPHASE1_ipd, + RXPOLARITY0_ipd, + RXPOLARITY1_ipd, + RXPOWERDOWN0_ipd, + RXPOWERDOWN1_ipd, + RXRESET0_ipd, + RXRESET1_ipd, + RXSLIDE0_ipd, + RXSLIDE1_ipd, + RXUSRCLK0_ipd, + RXUSRCLK1_ipd, + RXUSRCLK20_ipd, + RXUSRCLK21_ipd, + TXBUFDIFFCTRL0_ipd, + TXBUFDIFFCTRL1_ipd, + TXBYPASS8B10B0_ipd, + TXBYPASS8B10B1_ipd, + TXCHARDISPMODE0_ipd, + TXCHARDISPMODE1_ipd, + TXCHARDISPVAL0_ipd, + TXCHARDISPVAL1_ipd, + TXCHARISK0_ipd, + TXCHARISK1_ipd, + TXCOMSTART0_ipd, + TXCOMSTART1_ipd, + TXCOMTYPE0_ipd, + TXCOMTYPE1_ipd, + TXDATA0_ipd, + TXDATA1_ipd, + TXDATAWIDTH0_ipd, + TXDATAWIDTH1_ipd, + TXDETECTRX0_ipd, + TXDETECTRX1_ipd, + TXDIFFCTRL0_ipd, + TXDIFFCTRL1_ipd, + TXELECIDLE0_ipd, + TXELECIDLE1_ipd, + TXENC8B10BUSE0_ipd, + TXENC8B10BUSE1_ipd, + TXENPMAPHASEALIGN_ipd, + TXENPRBSTST0_ipd, + TXENPRBSTST1_ipd, + TXINHIBIT0_ipd, + TXINHIBIT1_ipd, + TXPMASETPHASE_ipd, + TXPOLARITY0_ipd, + TXPOLARITY1_ipd, + TXPOWERDOWN0_ipd, + TXPOWERDOWN1_ipd, + TXPREEMPHASIS0_ipd, + TXPREEMPHASIS1_ipd, + TXRESET0_ipd, + TXRESET1_ipd, + TXUSRCLK0_ipd, + TXUSRCLK1_ipd, + TXUSRCLK20_ipd, + TXUSRCLK21_ipd; + +end process TIMING; + + PHYSTATUS0 <= PHYSTATUS0_out; + PHYSTATUS1 <= PHYSTATUS1_out; + PLLLKDET <= PLLLKDET_out; + RESETDONE0 <= RESETDONE0_out; + RESETDONE1 <= RESETDONE1_out; + RXELECIDLE0 <= RXELECIDLE0_out; + RXELECIDLE1 <= RXELECIDLE1_out; + RXRECCLK0 <= RXRECCLK0_out; + RXRECCLK1 <= RXRECCLK1_out; + TXN0 <= TXN0_out; + TXN1 <= TXN1_out; + TXOUTCLK0 <= TXOUTCLK0_out; + TXOUTCLK1 <= TXOUTCLK1_out; + TXP0 <= TXP0_out; + TXP1 <= TXP1_out; + +end GTP_DUAL_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2006 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / PCI Express +-- /___/ /\ Filename : pcie_ep.vhd +-- \ \ / \ Timestamp : Thu Dec 8 2005 +-- \___\/\___\ +-- +-- Revision: +-- 08/14/06 - CR#421379 - Initial version. +-- 08/31/06 - BVT#1001 - Added PCIE_INTERNAL_1_1 component +-- 08/13/06 - CR#423912 - Added zero vectors (std_logic_vector) +-- 10/16/06 - CR#427095 - Modified generic map SWIFT instantiation to match spreadsheets +-- 12/05/06 - CR#420518 - Added input pin LLKRXDSTCONTREQN +-- 12/05/06 - CR#420518 - Added input pin LLKRXDSTCONTREQN +-- 03/13/07 - CR#435993 - Add LLKTXCONFIGREADYN +-- End Revision + +----- CELL PCIE_EP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +library secureip; +use secureip.all; + +entity PCIE_EP is +generic ( + ACTIVELANESIN : bit_vector := X"01"; + AERBASEPTR : bit_vector := X"110"; + AERCAPABILITYNEXTPTR : bit_vector := X"138"; + BAR0ADDRWIDTH : integer := 0; + BAR0EXIST : boolean := TRUE; + BAR0IOMEMN : integer := 0; + BAR0MASKWIDTH : bit_vector := X"14"; + BAR0PREFETCHABLE : boolean := TRUE; + BAR1ADDRWIDTH : integer := 0; + BAR1EXIST : boolean := FALSE; + BAR1IOMEMN : integer := 0; + BAR1MASKWIDTH : bit_vector := X"00"; + BAR1PREFETCHABLE : boolean := FALSE; + BAR2ADDRWIDTH : integer := 0; + BAR2EXIST : boolean := FALSE; + BAR2IOMEMN : integer := 0; + BAR2MASKWIDTH : bit_vector := X"00"; + BAR2PREFETCHABLE : boolean := FALSE; + BAR3ADDRWIDTH : integer := 0; + BAR3EXIST : boolean := FALSE; + BAR3IOMEMN : integer := 0; + BAR3MASKWIDTH : bit_vector := X"00"; + BAR3PREFETCHABLE : boolean := FALSE; + BAR4ADDRWIDTH : integer := 0; + BAR4EXIST : boolean := FALSE; + BAR4IOMEMN : integer := 0; + BAR4MASKWIDTH : bit_vector := X"00"; + BAR4PREFETCHABLE : boolean := FALSE; + BAR5EXIST : boolean := FALSE; + BAR5IOMEMN : integer := 0; + BAR5MASKWIDTH : bit_vector := X"00"; + BAR5PREFETCHABLE : boolean := FALSE; + CAPABILITIESPOINTER : bit_vector := X"40"; + CARDBUSCISPOINTER : bit_vector := X"00000000"; + CLASSCODE : bit_vector := X"058000"; + CLKDIVIDED : boolean := FALSE; + DEVICECAPABILITYENDPOINTL0SLATENCY : bit_vector := X"0"; + DEVICECAPABILITYENDPOINTL1LATENCY : bit_vector := X"0"; + DEVICEID : bit_vector := X"5050"; + DEVICESERIALNUMBER : bit_vector := X"E000000001000A35"; + DSNBASEPTR : bit_vector := X"148"; + DSNCAPABILITYNEXTPTR : bit_vector := X"154"; + INFINITECOMPLETIONS : boolean := TRUE; + INTERRUPTPIN : bit_vector := X"00"; + L0SEXITLATENCY : integer := 7; + L0SEXITLATENCYCOMCLK : integer := 7; + L1EXITLATENCY : integer := 7; + L1EXITLATENCYCOMCLK : integer := 7; + LINKCAPABILITYASPMSUPPORT : bit_vector := X"1"; + LINKCAPABILITYMAXLINKWIDTH : bit_vector := X"01"; + LINKSTATUSSLOTCLOCKCONFIG : boolean := FALSE; + LOWPRIORITYVCCOUNT : integer := 0; + MSIBASEPTR : bit_vector := X"048"; + MSICAPABILITYMULTIMSGCAP : bit_vector := X"0"; + MSICAPABILITYNEXTPTR : bit_vector := X"60"; + PBBASEPTR : bit_vector := X"138"; + PBCAPABILITYDW0BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW0DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW0PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW0PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW0POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW0TYPE : bit_vector := X"0"; + PBCAPABILITYDW1BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW1DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW1PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW1PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW1POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW1TYPE : bit_vector := X"0"; + PBCAPABILITYDW2BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW2DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW2PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW2PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW2POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW2TYPE : bit_vector := X"0"; + PBCAPABILITYDW3BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW3DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW3PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW3PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW3POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW3TYPE : bit_vector := X"0"; + PBCAPABILITYNEXTPTR : bit_vector := X"148"; + PBCAPABILITYSYSTEMALLOCATED : boolean := FALSE; + PCIECAPABILITYNEXTPTR : bit_vector := X"00"; + PMBASEPTR : bit_vector := X"040"; + PMCAPABILITYAUXCURRENT : bit_vector := X"0"; + PMCAPABILITYD1SUPPORT : boolean := FALSE; + PMCAPABILITYD2SUPPORT : boolean := FALSE; + PMCAPABILITYDSI : boolean := TRUE; + PMCAPABILITYNEXTPTR : bit_vector := X"60"; + PMCAPABILITYPMESUPPORT : bit_vector := X"00"; + PMDATA0 : bit_vector := X"00"; + PMDATA1 : bit_vector := X"00"; + PMDATA2 : bit_vector := X"00"; + PMDATA3 : bit_vector := X"00"; + PMDATA4 : bit_vector := X"00"; + PMDATA5 : bit_vector := X"00"; + PMDATA6 : bit_vector := X"00"; + PMDATA7 : bit_vector := X"00"; + PMDATASCALE0 : integer := 0; + PMDATASCALE1 : integer := 0; + PMDATASCALE2 : integer := 0; + PMDATASCALE3 : integer := 0; + PMDATASCALE4 : integer := 0; + PMDATASCALE5 : integer := 0; + PMDATASCALE6 : integer := 0; + PMDATASCALE7 : integer := 0; + PORTVCCAPABILITYEXTENDEDVCCOUNT : bit_vector := X"0"; + PORTVCCAPABILITYVCARBCAP : bit_vector := X"00"; + PORTVCCAPABILITYVCARBTABLEOFFSET : bit_vector := X"00"; + RESETMODE : boolean := FALSE; + RETRYRAMREADLATENCY : integer := 3; + RETRYRAMSIZE : bit_vector := X"009"; + RETRYRAMWRITELATENCY : integer := 1; + REVISIONID : bit_vector := X"00"; + SUBSYSTEMID : bit_vector := X"5050"; + SUBSYSTEMVENDORID : bit_vector := X"10EE"; + TLRAMREADLATENCY : integer := 3; + TLRAMWRITELATENCY : integer := 1; + TXTSNFTS : integer := 255; + TXTSNFTSCOMCLK : integer := 255; + VC0RXFIFOBASEC : bit_vector := X"0098"; + VC0RXFIFOBASENP : bit_vector := X"0080"; + VC0RXFIFOBASEP : bit_vector := X"0000"; + VC0RXFIFOLIMITC : bit_vector := X"0117"; + VC0RXFIFOLIMITNP : bit_vector := X"0097"; + VC0RXFIFOLIMITP : bit_vector := X"007f"; + VC0TOTALCREDITSCD : bit_vector := X"000"; + VC0TOTALCREDITSCH : bit_vector := X"00"; + VC0TOTALCREDITSNPH : bit_vector := X"08"; + VC0TOTALCREDITSPD : bit_vector := X"034"; + VC0TOTALCREDITSPH : bit_vector := X"08"; + VC0TXFIFOBASEC : bit_vector := X"0098"; + VC0TXFIFOBASENP : bit_vector := X"0080"; + VC0TXFIFOBASEP : bit_vector := X"0000"; + VC0TXFIFOLIMITC : bit_vector := X"0117"; + VC0TXFIFOLIMITNP : bit_vector := X"0097"; + VC0TXFIFOLIMITP : bit_vector := X"007f"; + VC1RXFIFOBASEC : bit_vector := X"0118"; + VC1RXFIFOBASENP : bit_vector := X"0118"; + VC1RXFIFOBASEP : bit_vector := X"0118"; + VC1RXFIFOLIMITC : bit_vector := X"0118"; + VC1RXFIFOLIMITNP : bit_vector := X"0118"; + VC1RXFIFOLIMITP : bit_vector := X"0118"; + VC1TOTALCREDITSCD : bit_vector := X"000"; + VC1TOTALCREDITSCH : bit_vector := X"00"; + VC1TOTALCREDITSNPH : bit_vector := X"00"; + VC1TOTALCREDITSPD : bit_vector := X"000"; + VC1TOTALCREDITSPH : bit_vector := X"00"; + VC1TXFIFOBASEC : bit_vector := X"0118"; + VC1TXFIFOBASENP : bit_vector := X"0118"; + VC1TXFIFOBASEP : bit_vector := X"0118"; + VC1TXFIFOLIMITC : bit_vector := X"0118"; + VC1TXFIFOLIMITNP : bit_vector := X"0118"; + VC1TXFIFOLIMITP : bit_vector := X"0118"; + VCBASEPTR : bit_vector := X"154"; + VCCAPABILITYNEXTPTR : bit_vector := X"000"; + VENDORID : bit_vector := X"10EE"; + XPBASEPTR : bit_vector := X"60"; + XPDEVICEPORTTYPE : bit_vector := X"0"; + XPMAXPAYLOAD : integer := 0 + ); + +port ( + BUSMASTERENABLE : out std_ulogic; + CRMDOHOTRESETN : out std_ulogic; + CRMPWRSOFTRESETN : out std_ulogic; + DLLTXPMDLLPOUTSTANDING : out std_ulogic; + INTERRUPTDISABLE : out std_ulogic; + IOSPACEENABLE : out std_ulogic; + L0CFGLOOPBACKACK : out std_ulogic; + L0COMPLETERID : out std_logic_vector(12 downto 0); + L0DLLERRORVECTOR : out std_logic_vector(6 downto 0); + L0DLLRXACKOUTSTANDING : out std_ulogic; + L0DLLTXNONFCOUTSTANDING : out std_ulogic; + L0DLLTXOUTSTANDING : out std_ulogic; + L0DLLVCSTATUS : out std_logic_vector(7 downto 0); + L0DLUPDOWN : out std_logic_vector(7 downto 0); + L0FIRSTCFGWRITEOCCURRED : out std_ulogic; + L0LTSSMSTATE : out std_logic_vector(3 downto 0); + L0MACENTEREDL0 : out std_ulogic; + L0MACLINKTRAINING : out std_ulogic; + L0MACLINKUP : out std_ulogic; + L0MACNEGOTIATEDLINKWIDTH : out std_logic_vector(3 downto 0); + L0MACNEWSTATEACK : out std_ulogic; + L0MACRXL0SSTATE : out std_ulogic; + L0MSIENABLE0 : out std_ulogic; + L0MULTIMSGEN0 : out std_logic_vector(2 downto 0); + L0PMEACK : out std_ulogic; + L0PMEEN : out std_ulogic; + L0PMEREQOUT : out std_ulogic; + L0PWRL1STATE : out std_ulogic; + L0PWRL23READYSTATE : out std_ulogic; + L0PWRSTATE0 : out std_logic_vector(1 downto 0); + L0PWRTURNOFFREQ : out std_ulogic; + L0PWRTXL0SSTATE : out std_ulogic; + L0RXDLLPM : out std_ulogic; + L0RXDLLPMTYPE : out std_logic_vector(2 downto 0); + L0RXMACLINKERROR : out std_logic_vector(1 downto 0); + L0STATSCFGOTHERRECEIVED : out std_ulogic; + L0STATSCFGOTHERTRANSMITTED : out std_ulogic; + L0STATSCFGRECEIVED : out std_ulogic; + L0STATSCFGTRANSMITTED : out std_ulogic; + L0STATSDLLPRECEIVED : out std_ulogic; + L0STATSDLLPTRANSMITTED : out std_ulogic; + L0STATSOSRECEIVED : out std_ulogic; + L0STATSOSTRANSMITTED : out std_ulogic; + L0STATSTLPRECEIVED : out std_ulogic; + L0STATSTLPTRANSMITTED : out std_ulogic; + L0UNLOCKRECEIVED : out std_ulogic; + LLKRXCHCOMPLETIONAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHNONPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXDATA : out std_logic_vector(63 downto 0); + LLKRXEOFN : out std_ulogic; + LLKRXEOPN : out std_ulogic; + LLKRXPREFERREDTYPE : out std_logic_vector(15 downto 0); + LLKRXSOFN : out std_ulogic; + LLKRXSOPN : out std_ulogic; + LLKRXSRCLASTREQN : out std_ulogic; + LLKRXSRCRDYN : out std_ulogic; + LLKRXVALIDN : out std_logic_vector(1 downto 0); + LLKTCSTATUS : out std_logic_vector(7 downto 0); + LLKTXCHANSPACE : out std_logic_vector(9 downto 0); + LLKTXCHCOMPLETIONREADYN : out std_logic_vector(7 downto 0); + LLKTXCHNONPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCHPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCONFIGREADYN : out std_ulogic; + LLKTXDSTRDYN : out std_ulogic; + MAXPAYLOADSIZE : out std_logic_vector(2 downto 0); + MAXREADREQUESTSIZE : out std_logic_vector(2 downto 0); + MEMSPACEENABLE : out std_ulogic; + MGMTPSO : out std_logic_vector(16 downto 0); + MGMTRDATA : out std_logic_vector(31 downto 0); + MGMTSTATSCREDIT : out std_logic_vector(11 downto 0); + MIMDLLBRADD : out std_logic_vector(11 downto 0); + MIMDLLBREN : out std_ulogic; + MIMDLLBWADD : out std_logic_vector(11 downto 0); + MIMDLLBWDATA : out std_logic_vector(63 downto 0); + MIMDLLBWEN : out std_ulogic; + MIMRXBRADD : out std_logic_vector(12 downto 0); + MIMRXBREN : out std_ulogic; + MIMRXBWADD : out std_logic_vector(12 downto 0); + MIMRXBWDATA : out std_logic_vector(63 downto 0); + MIMRXBWEN : out std_ulogic; + MIMTXBRADD : out std_logic_vector(12 downto 0); + MIMTXBREN : out std_ulogic; + MIMTXBWADD : out std_logic_vector(12 downto 0); + MIMTXBWDATA : out std_logic_vector(63 downto 0); + MIMTXBWEN : out std_ulogic; + PARITYERRORRESPONSE : out std_ulogic; + PIPEDESKEWLANESL0 : out std_ulogic; + PIPEDESKEWLANESL1 : out std_ulogic; + PIPEDESKEWLANESL2 : out std_ulogic; + PIPEDESKEWLANESL3 : out std_ulogic; + PIPEDESKEWLANESL4 : out std_ulogic; + PIPEDESKEWLANESL5 : out std_ulogic; + PIPEDESKEWLANESL6 : out std_ulogic; + PIPEDESKEWLANESL7 : out std_ulogic; + PIPEPOWERDOWNL0 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL1 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL2 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL3 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL4 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL5 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL6 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL7 : out std_logic_vector(1 downto 0); + PIPERESETL0 : out std_ulogic; + PIPERESETL1 : out std_ulogic; + PIPERESETL2 : out std_ulogic; + PIPERESETL3 : out std_ulogic; + PIPERESETL4 : out std_ulogic; + PIPERESETL5 : out std_ulogic; + PIPERESETL6 : out std_ulogic; + PIPERESETL7 : out std_ulogic; + PIPERXPOLARITYL0 : out std_ulogic; + PIPERXPOLARITYL1 : out std_ulogic; + PIPERXPOLARITYL2 : out std_ulogic; + PIPERXPOLARITYL3 : out std_ulogic; + PIPERXPOLARITYL4 : out std_ulogic; + PIPERXPOLARITYL5 : out std_ulogic; + PIPERXPOLARITYL6 : out std_ulogic; + PIPERXPOLARITYL7 : out std_ulogic; + PIPETXCOMPLIANCEL0 : out std_ulogic; + PIPETXCOMPLIANCEL1 : out std_ulogic; + PIPETXCOMPLIANCEL2 : out std_ulogic; + PIPETXCOMPLIANCEL3 : out std_ulogic; + PIPETXCOMPLIANCEL4 : out std_ulogic; + PIPETXCOMPLIANCEL5 : out std_ulogic; + PIPETXCOMPLIANCEL6 : out std_ulogic; + PIPETXCOMPLIANCEL7 : out std_ulogic; + PIPETXDATAKL0 : out std_ulogic; + PIPETXDATAKL1 : out std_ulogic; + PIPETXDATAKL2 : out std_ulogic; + PIPETXDATAKL3 : out std_ulogic; + PIPETXDATAKL4 : out std_ulogic; + PIPETXDATAKL5 : out std_ulogic; + PIPETXDATAKL6 : out std_ulogic; + PIPETXDATAKL7 : out std_ulogic; + PIPETXDATAL0 : out std_logic_vector(7 downto 0); + PIPETXDATAL1 : out std_logic_vector(7 downto 0); + PIPETXDATAL2 : out std_logic_vector(7 downto 0); + PIPETXDATAL3 : out std_logic_vector(7 downto 0); + PIPETXDATAL4 : out std_logic_vector(7 downto 0); + PIPETXDATAL5 : out std_logic_vector(7 downto 0); + PIPETXDATAL6 : out std_logic_vector(7 downto 0); + PIPETXDATAL7 : out std_logic_vector(7 downto 0); + PIPETXDETECTRXLOOPBACKL0 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL1 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL2 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL3 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL4 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL5 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL6 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL7 : out std_ulogic; + PIPETXELECIDLEL0 : out std_ulogic; + PIPETXELECIDLEL1 : out std_ulogic; + PIPETXELECIDLEL2 : out std_ulogic; + PIPETXELECIDLEL3 : out std_ulogic; + PIPETXELECIDLEL4 : out std_ulogic; + PIPETXELECIDLEL5 : out std_ulogic; + PIPETXELECIDLEL6 : out std_ulogic; + PIPETXELECIDLEL7 : out std_ulogic; + SERRENABLE : out std_ulogic; + URREPORTINGENABLE : out std_ulogic; + + AUXPOWER : in std_ulogic; + COMPLIANCEAVOID : in std_ulogic; + CRMCORECLK : in std_ulogic; + CRMCORECLKDLO : in std_ulogic; + CRMCORECLKRXO : in std_ulogic; + CRMCORECLKTXO : in std_ulogic; + CRMLINKRSTN : in std_ulogic; + CRMMACRSTN : in std_ulogic; + CRMMGMTRSTN : in std_ulogic; + CRMNVRSTN : in std_ulogic; + CRMURSTN : in std_ulogic; + CRMUSERCFGRSTN : in std_ulogic; + CRMUSERCLK : in std_ulogic; + CRMUSERCLKRXO : in std_ulogic; + CRMUSERCLKTXO : in std_ulogic; + L0CFGDISABLESCRAMBLE : in std_ulogic; + L0CFGLOOPBACKMASTER : in std_ulogic; + L0LEGACYINTFUNCT0 : in std_ulogic; + L0MSIREQUEST0 : in std_logic_vector(3 downto 0); + L0PACKETHEADERFROMUSER : in std_logic_vector(127 downto 0); + L0PMEREQIN : in std_ulogic; + L0SETCOMPLETERABORTERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTCORRERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTUNCORRERROR : in std_ulogic; + L0SETDETECTEDCORRERROR : in std_ulogic; + L0SETDETECTEDFATALERROR : in std_ulogic; + L0SETDETECTEDNONFATALERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONCORRERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTOTHERERROR : in std_ulogic; + L0SETUSERDETECTEDPARITYERROR : in std_ulogic; + L0SETUSERMASTERDATAPARITY : in std_ulogic; + L0SETUSERRECEIVEDMASTERABORT : in std_ulogic; + L0SETUSERRECEIVEDTARGETABORT : in std_ulogic; + L0SETUSERSIGNALLEDTARGETABORT : in std_ulogic; + L0SETUSERSYSTEMERROR : in std_ulogic; + L0TRANSACTIONSPENDING : in std_ulogic; + LLKRXCHFIFO : in std_logic_vector(1 downto 0); + LLKRXCHTC : in std_logic_vector(2 downto 0); + LLKRXDSTCONTREQN : in std_ulogic; + LLKRXDSTREQN : in std_ulogic; + LLKTXCHFIFO : in std_logic_vector(1 downto 0); + LLKTXCHTC : in std_logic_vector(2 downto 0); + LLKTXDATA : in std_logic_vector(63 downto 0); + LLKTXENABLEN : in std_logic_vector(1 downto 0); + LLKTXEOFN : in std_ulogic; + LLKTXEOPN : in std_ulogic; + LLKTXSOFN : in std_ulogic; + LLKTXSOPN : in std_ulogic; + LLKTXSRCDSCN : in std_ulogic; + LLKTXSRCRDYN : in std_ulogic; + MGMTADDR : in std_logic_vector(10 downto 0); + MGMTBWREN : in std_logic_vector(3 downto 0); + MGMTRDEN : in std_ulogic; + MGMTSTATSCREDITSEL : in std_logic_vector(6 downto 0); + MGMTWDATA : in std_logic_vector(31 downto 0); + MGMTWREN : in std_ulogic; + MIMDLLBRDATA : in std_logic_vector(63 downto 0); + MIMRXBRDATA : in std_logic_vector(63 downto 0); + MIMTXBRDATA : in std_logic_vector(63 downto 0); + PIPEPHYSTATUSL0 : in std_ulogic; + PIPEPHYSTATUSL1 : in std_ulogic; + PIPEPHYSTATUSL2 : in std_ulogic; + PIPEPHYSTATUSL3 : in std_ulogic; + PIPEPHYSTATUSL4 : in std_ulogic; + PIPEPHYSTATUSL5 : in std_ulogic; + PIPEPHYSTATUSL6 : in std_ulogic; + PIPEPHYSTATUSL7 : in std_ulogic; + PIPERXCHANISALIGNEDL0 : in std_ulogic; + PIPERXCHANISALIGNEDL1 : in std_ulogic; + PIPERXCHANISALIGNEDL2 : in std_ulogic; + PIPERXCHANISALIGNEDL3 : in std_ulogic; + PIPERXCHANISALIGNEDL4 : in std_ulogic; + PIPERXCHANISALIGNEDL5 : in std_ulogic; + PIPERXCHANISALIGNEDL6 : in std_ulogic; + PIPERXCHANISALIGNEDL7 : in std_ulogic; + PIPERXDATAKL0 : in std_ulogic; + PIPERXDATAKL1 : in std_ulogic; + PIPERXDATAKL2 : in std_ulogic; + PIPERXDATAKL3 : in std_ulogic; + PIPERXDATAKL4 : in std_ulogic; + PIPERXDATAKL5 : in std_ulogic; + PIPERXDATAKL6 : in std_ulogic; + PIPERXDATAKL7 : in std_ulogic; + PIPERXDATAL0 : in std_logic_vector(7 downto 0); + PIPERXDATAL1 : in std_logic_vector(7 downto 0); + PIPERXDATAL2 : in std_logic_vector(7 downto 0); + PIPERXDATAL3 : in std_logic_vector(7 downto 0); + PIPERXDATAL4 : in std_logic_vector(7 downto 0); + PIPERXDATAL5 : in std_logic_vector(7 downto 0); + PIPERXDATAL6 : in std_logic_vector(7 downto 0); + PIPERXDATAL7 : in std_logic_vector(7 downto 0); + PIPERXELECIDLEL0 : in std_ulogic; + PIPERXELECIDLEL1 : in std_ulogic; + PIPERXELECIDLEL2 : in std_ulogic; + PIPERXELECIDLEL3 : in std_ulogic; + PIPERXELECIDLEL4 : in std_ulogic; + PIPERXELECIDLEL5 : in std_ulogic; + PIPERXELECIDLEL6 : in std_ulogic; + PIPERXELECIDLEL7 : in std_ulogic; + PIPERXSTATUSL0 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL1 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL2 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL3 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL4 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL5 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL6 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL7 : in std_logic_vector(2 downto 0); + PIPERXVALIDL0 : in std_ulogic; + PIPERXVALIDL1 : in std_ulogic; + PIPERXVALIDL2 : in std_ulogic; + PIPERXVALIDL3 : in std_ulogic; + PIPERXVALIDL4 : in std_ulogic; + PIPERXVALIDL5 : in std_ulogic; + PIPERXVALIDL6 : in std_ulogic; + PIPERXVALIDL7 : in std_ulogic + ); +end PCIE_EP; + +architecture PCIE_EP_V of PCIE_EP is + + component PCIE_INTERNAL_1_1 + generic ( + ACTIVELANESIN : bit_vector := X"01"; + AERBASEPTR : bit_vector := X"110"; + AERCAPABILITYECRCCHECKCAPABLE : boolean := FALSE; + AERCAPABILITYECRCGENCAPABLE : boolean := FALSE; + AERCAPABILITYNEXTPTR : bit_vector := X"138"; + BAR0ADDRWIDTH : integer := 0; + BAR0EXIST : boolean := TRUE; + BAR0IOMEMN : integer := 0; + BAR0MASKWIDTH : bit_vector := X"14"; + BAR0PREFETCHABLE : boolean := TRUE; + BAR1ADDRWIDTH : integer := 0; + BAR1EXIST : boolean := FALSE; + BAR1IOMEMN : integer := 0; + BAR1MASKWIDTH : bit_vector := X"00"; + BAR1PREFETCHABLE : boolean := FALSE; + BAR2ADDRWIDTH : integer := 0; + BAR2EXIST : boolean := FALSE; + BAR2IOMEMN : integer := 0; + BAR2MASKWIDTH : bit_vector := X"00"; + BAR2PREFETCHABLE : boolean := FALSE; + BAR3ADDRWIDTH : integer := 0; + BAR3EXIST : boolean := FALSE; + BAR3IOMEMN : integer := 0; + BAR3MASKWIDTH : bit_vector := X"00"; + BAR3PREFETCHABLE : boolean := FALSE; + BAR4ADDRWIDTH : integer := 0; + BAR4EXIST : boolean := FALSE; + BAR4IOMEMN : integer := 0; + BAR4MASKWIDTH : bit_vector := X"00"; + BAR4PREFETCHABLE : boolean := FALSE; + BAR5EXIST : boolean := FALSE; + BAR5IOMEMN : integer := 0; + BAR5MASKWIDTH : bit_vector := X"00"; + BAR5PREFETCHABLE : boolean := FALSE; + CAPABILITIESPOINTER : bit_vector := X"40"; + CARDBUSCISPOINTER : bit_vector := X"00000000"; + CLASSCODE : bit_vector := X"058000"; + CLKDIVIDED : boolean := FALSE; + CONFIGROUTING : bit_vector := X"1"; + DEVICECAPABILITYENDPOINTL0SLATENCY : bit_vector := X"0"; + DEVICECAPABILITYENDPOINTL1LATENCY : bit_vector := X"0"; + DEVICEID : bit_vector := X"5050"; + DEVICESERIALNUMBER : bit_vector := X"E000000001000A35"; + DSNBASEPTR : bit_vector := X"148"; + DSNCAPABILITYNEXTPTR : bit_vector := X"154"; + DUALCOREENABLE : boolean := FALSE; + DUALCORESLAVE : boolean := FALSE; + DUALROLECFGCNTRLROOTEPN : integer := 0; + EXTCFGCAPPTR : bit_vector := X"00"; + EXTCFGXPCAPPTR : bit_vector := X"000"; + HEADERTYPE : bit_vector := X"00"; + INFINITECOMPLETIONS : boolean := TRUE; + INTERRUPTPIN : bit_vector := X"00"; + ISSWITCH : boolean := FALSE; + L0SEXITLATENCY : integer := 7; + L0SEXITLATENCYCOMCLK : integer := 7; + L1EXITLATENCY : integer := 7; + L1EXITLATENCYCOMCLK : integer := 7; + LINKCAPABILITYASPMSUPPORT : bit_vector := X"1"; + LINKCAPABILITYMAXLINKWIDTH : bit_vector := X"01"; + LINKSTATUSSLOTCLOCKCONFIG : boolean := FALSE; + LLKBYPASS : boolean := FALSE; + LOWPRIORITYVCCOUNT : integer := 0; + MSIBASEPTR : bit_vector := X"048"; + MSICAPABILITYMULTIMSGCAP : bit_vector := X"0"; + MSICAPABILITYNEXTPTR : bit_vector := X"60"; + PBBASEPTR : bit_vector := X"138"; + PBCAPABILITYDW0BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW0DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW0PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW0PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW0POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW0TYPE : bit_vector := X"0"; + PBCAPABILITYDW1BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW1DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW1PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW1PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW1POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW1TYPE : bit_vector := X"0"; + PBCAPABILITYDW2BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW2DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW2PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW2PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW2POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW2TYPE : bit_vector := X"0"; + PBCAPABILITYDW3BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW3DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW3PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW3PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW3POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW3TYPE : bit_vector := X"0"; + PBCAPABILITYNEXTPTR : bit_vector := X"148"; + PBCAPABILITYSYSTEMALLOCATED : boolean := FALSE; + PCIECAPABILITYINTMSGNUM : bit_vector := X"00"; + PCIECAPABILITYNEXTPTR : bit_vector := X"00"; + PCIECAPABILITYSLOTIMPL : boolean := FALSE; + PCIEREVISION : integer := 1; + PMBASEPTR : bit_vector := X"040"; + PMCAPABILITYAUXCURRENT : bit_vector := X"0"; + PMCAPABILITYD1SUPPORT : boolean := FALSE; + PMCAPABILITYD2SUPPORT : boolean := FALSE; + PMCAPABILITYDSI : boolean := TRUE; + PMCAPABILITYNEXTPTR : bit_vector := X"60"; + PMCAPABILITYPMESUPPORT : bit_vector := X"00"; + PMDATA0 : bit_vector := X"00"; + PMDATA1 : bit_vector := X"00"; + PMDATA2 : bit_vector := X"00"; + PMDATA3 : bit_vector := X"00"; + PMDATA4 : bit_vector := X"00"; + PMDATA5 : bit_vector := X"00"; + PMDATA6 : bit_vector := X"00"; + PMDATA7 : bit_vector := X"00"; + PMDATA8 : bit_vector := X"00"; + PMDATASCALE0 : integer := 0; + PMDATASCALE1 : integer := 0; + PMDATASCALE2 : integer := 0; + PMDATASCALE3 : integer := 0; + PMDATASCALE4 : integer := 0; + PMDATASCALE5 : integer := 0; + PMDATASCALE6 : integer := 0; + PMDATASCALE7 : integer := 0; + PMDATASCALE8 : integer := 0; + PMSTATUSCONTROLDATASCALE : bit_vector := X"0"; + PORTVCCAPABILITYEXTENDEDVCCOUNT : bit_vector := X"0"; + PORTVCCAPABILITYVCARBCAP : bit_vector := X"00"; + PORTVCCAPABILITYVCARBTABLEOFFSET : bit_vector := X"00"; + RAMSHARETXRX : boolean := FALSE; + RESETMODE : boolean := FALSE; + RETRYRAMREADLATENCY : integer := 3; + RETRYRAMSIZE : bit_vector := X"009"; + RETRYRAMWIDTH : integer := 0; + RETRYRAMWRITELATENCY : integer := 1; + RETRYREADADDRPIPE : boolean := FALSE; + RETRYREADDATAPIPE : boolean := FALSE; + RETRYWRITEPIPE : boolean := FALSE; + REVISIONID : bit_vector := X"00"; + RXREADADDRPIPE : boolean := FALSE; + RXREADDATAPIPE : boolean := FALSE; + RXWRITEPIPE : boolean := FALSE; + SELECTASMODE : boolean := FALSE; + SELECTDLLIF : boolean := FALSE; + SLOTCAPABILITYATTBUTTONPRESENT : boolean := FALSE; + SLOTCAPABILITYATTINDICATORPRESENT : boolean := FALSE; + SLOTCAPABILITYHOTPLUGCAPABLE : boolean := FALSE; + SLOTCAPABILITYHOTPLUGSURPRISE : boolean := FALSE; + SLOTCAPABILITYMSLSENSORPRESENT : boolean := FALSE; + SLOTCAPABILITYPHYSICALSLOTNUM : bit_vector := X"0000"; + SLOTCAPABILITYPOWERCONTROLLERPRESENT : boolean := FALSE; + SLOTCAPABILITYPOWERINDICATORPRESENT : boolean := FALSE; + SLOTCAPABILITYSLOTPOWERLIMITSCALE : bit_vector := X"0"; + SLOTCAPABILITYSLOTPOWERLIMITVALUE : bit_vector := X"00"; + SLOTIMPLEMENTED : boolean := FALSE; + SUBSYSTEMID : bit_vector := X"5050"; + SUBSYSTEMVENDORID : bit_vector := X"10EE"; + TLRAMREADLATENCY : integer := 3; + TLRAMWIDTH : integer := 0; + TLRAMWRITELATENCY : integer := 1; + TXREADADDRPIPE : boolean := FALSE; + TXREADDATAPIPE : boolean := FALSE; + TXTSNFTS : integer := 255; + TXTSNFTSCOMCLK : integer := 255; + TXWRITEPIPE : boolean := FALSE; + UPSTREAMFACING : boolean := TRUE; + VC0RXFIFOBASEC : bit_vector := X"0098"; + VC0RXFIFOBASENP : bit_vector := X"0080"; + VC0RXFIFOBASEP : bit_vector := X"0000"; + VC0RXFIFOLIMITC : bit_vector := X"0117"; + VC0RXFIFOLIMITNP : bit_vector := X"0097"; + VC0RXFIFOLIMITP : bit_vector := X"007f"; + VC0TOTALCREDITSCD : bit_vector := X"000"; + VC0TOTALCREDITSCH : bit_vector := X"00"; + VC0TOTALCREDITSNPH : bit_vector := X"08"; + VC0TOTALCREDITSPD : bit_vector := X"034"; + VC0TOTALCREDITSPH : bit_vector := X"08"; + VC0TXFIFOBASEC : bit_vector := X"0098"; + VC0TXFIFOBASENP : bit_vector := X"0080"; + VC0TXFIFOBASEP : bit_vector := X"0000"; + VC0TXFIFOLIMITC : bit_vector := X"0117"; + VC0TXFIFOLIMITNP : bit_vector := X"0097"; + VC0TXFIFOLIMITP : bit_vector := X"007f"; + VC1RXFIFOBASEC : bit_vector := X"0118"; + VC1RXFIFOBASENP : bit_vector := X"0118"; + VC1RXFIFOBASEP : bit_vector := X"0118"; + VC1RXFIFOLIMITC : bit_vector := X"0118"; + VC1RXFIFOLIMITNP : bit_vector := X"0118"; + VC1RXFIFOLIMITP : bit_vector := X"0118"; + VC1TOTALCREDITSCD : bit_vector := X"000"; + VC1TOTALCREDITSCH : bit_vector := X"00"; + VC1TOTALCREDITSNPH : bit_vector := X"00"; + VC1TOTALCREDITSPD : bit_vector := X"000"; + VC1TOTALCREDITSPH : bit_vector := X"00"; + VC1TXFIFOBASEC : bit_vector := X"0118"; + VC1TXFIFOBASENP : bit_vector := X"0118"; + VC1TXFIFOBASEP : bit_vector := X"0118"; + VC1TXFIFOLIMITC : bit_vector := X"0118"; + VC1TXFIFOLIMITNP : bit_vector := X"0118"; + VC1TXFIFOLIMITP : bit_vector := X"0118"; + VCBASEPTR : bit_vector := X"154"; + VCCAPABILITYNEXTPTR : bit_vector := X"000"; + VENDORID : bit_vector := X"10EE"; + XLINKSUPPORTED : boolean := FALSE; + XPBASEPTR : bit_vector := X"60"; + XPDEVICEPORTTYPE : bit_vector := X"0"; + XPMAXPAYLOAD : integer := 0; + XPRCBCONTROL : integer := 0 + + ); + port ( + BUSMASTERENABLE : out std_ulogic; + CRMDOHOTRESETN : out std_ulogic; + CRMPWRSOFTRESETN : out std_ulogic; + CRMRXHOTRESETN : out std_ulogic; + DLLTXPMDLLPOUTSTANDING : out std_ulogic; + INTERRUPTDISABLE : out std_ulogic; + IOSPACEENABLE : out std_ulogic; + L0ASAUTONOMOUSINITCOMPLETED : out std_ulogic; + L0ATTENTIONINDICATORCONTROL : out std_logic_vector(1 downto 0); + L0CFGLOOPBACKACK : out std_ulogic; + L0COMPLETERID : out std_logic_vector(12 downto 0); + L0CORRERRMSGRCVD : out std_ulogic; + L0DLLASRXSTATE : out std_logic_vector(1 downto 0); + L0DLLASTXSTATE : out std_ulogic; + L0DLLERRORVECTOR : out std_logic_vector(6 downto 0); + L0DLLRXACKOUTSTANDING : out std_ulogic; + L0DLLTXNONFCOUTSTANDING : out std_ulogic; + L0DLLTXOUTSTANDING : out std_ulogic; + L0DLLVCSTATUS : out std_logic_vector(7 downto 0); + L0DLUPDOWN : out std_logic_vector(7 downto 0); + L0ERRMSGREQID : out std_logic_vector(15 downto 0); + L0FATALERRMSGRCVD : out std_ulogic; + L0FIRSTCFGWRITEOCCURRED : out std_ulogic; + L0FWDCORRERROUT : out std_ulogic; + L0FWDFATALERROUT : out std_ulogic; + L0FWDNONFATALERROUT : out std_ulogic; + L0LTSSMSTATE : out std_logic_vector(3 downto 0); + L0MACENTEREDL0 : out std_ulogic; + L0MACLINKTRAINING : out std_ulogic; + L0MACLINKUP : out std_ulogic; + L0MACNEGOTIATEDLINKWIDTH : out std_logic_vector(3 downto 0); + L0MACNEWSTATEACK : out std_ulogic; + L0MACRXL0SSTATE : out std_ulogic; + L0MACUPSTREAMDOWNSTREAM : out std_ulogic; + L0MCFOUND : out std_logic_vector(2 downto 0); + L0MSIENABLE0 : out std_ulogic; + L0MULTIMSGEN0 : out std_logic_vector(2 downto 0); + L0NONFATALERRMSGRCVD : out std_ulogic; + L0PMEACK : out std_ulogic; + L0PMEEN : out std_ulogic; + L0PMEREQOUT : out std_ulogic; + L0POWERCONTROLLERCONTROL : out std_ulogic; + L0POWERINDICATORCONTROL : out std_logic_vector(1 downto 0); + L0PWRINHIBITTRANSFERS : out std_ulogic; + L0PWRL1STATE : out std_ulogic; + L0PWRL23READYDEVICE : out std_ulogic; + L0PWRL23READYSTATE : out std_ulogic; + L0PWRSTATE0 : out std_logic_vector(1 downto 0); + L0PWRTURNOFFREQ : out std_ulogic; + L0PWRTXL0SSTATE : out std_ulogic; + L0RECEIVEDASSERTINTALEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTBLEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTCLEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTDLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTALEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTBLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTCLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTDLEGACYINT : out std_ulogic; + L0RXBEACON : out std_ulogic; + L0RXDLLFCCMPLMCCRED : out std_logic_vector(23 downto 0); + L0RXDLLFCCMPLMCUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLFCNPOSTBYPCRED : out std_logic_vector(19 downto 0); + L0RXDLLFCNPOSTBYPUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLFCPOSTORDCRED : out std_logic_vector(23 downto 0); + L0RXDLLFCPOSTORDUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLPM : out std_ulogic; + L0RXDLLPMTYPE : out std_logic_vector(2 downto 0); + L0RXDLLSBFCDATA : out std_logic_vector(18 downto 0); + L0RXDLLSBFCUPDATE : out std_ulogic; + L0RXDLLTLPECRCOK : out std_ulogic; + L0RXDLLTLPEND : out std_logic_vector(1 downto 0); + L0RXMACLINKERROR : out std_logic_vector(1 downto 0); + L0STATSCFGOTHERRECEIVED : out std_ulogic; + L0STATSCFGOTHERTRANSMITTED : out std_ulogic; + L0STATSCFGRECEIVED : out std_ulogic; + L0STATSCFGTRANSMITTED : out std_ulogic; + L0STATSDLLPRECEIVED : out std_ulogic; + L0STATSDLLPTRANSMITTED : out std_ulogic; + L0STATSOSRECEIVED : out std_ulogic; + L0STATSOSTRANSMITTED : out std_ulogic; + L0STATSTLPRECEIVED : out std_ulogic; + L0STATSTLPTRANSMITTED : out std_ulogic; + L0TOGGLEELECTROMECHANICALINTERLOCK : out std_ulogic; + L0TRANSFORMEDVC : out std_logic_vector(2 downto 0); + L0TXDLLFCCMPLMCUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLFCNPOSTBYPUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLFCPOSTORDUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLPMUPDATED : out std_ulogic; + L0TXDLLSBFCUPDATED : out std_ulogic; + L0UCBYPFOUND : out std_logic_vector(3 downto 0); + L0UCORDFOUND : out std_logic_vector(3 downto 0); + L0UNLOCKRECEIVED : out std_ulogic; + LLKRX4DWHEADERN : out std_ulogic; + LLKRXCHCOMPLETIONAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHCOMPLETIONPARTIALN : out std_logic_vector(7 downto 0); + LLKRXCHCONFIGAVAILABLEN : out std_ulogic; + LLKRXCHCONFIGPARTIALN : out std_ulogic; + LLKRXCHNONPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHNONPOSTEDPARTIALN : out std_logic_vector(7 downto 0); + LLKRXCHPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHPOSTEDPARTIALN : out std_logic_vector(7 downto 0); + LLKRXDATA : out std_logic_vector(63 downto 0); + LLKRXECRCBADN : out std_ulogic; + LLKRXEOFN : out std_ulogic; + LLKRXEOPN : out std_ulogic; + LLKRXPREFERREDTYPE : out std_logic_vector(15 downto 0); + LLKRXSOFN : out std_ulogic; + LLKRXSOPN : out std_ulogic; + LLKRXSRCDSCN : out std_ulogic; + LLKRXSRCLASTREQN : out std_ulogic; + LLKRXSRCRDYN : out std_ulogic; + LLKRXVALIDN : out std_logic_vector(1 downto 0); + LLKTCSTATUS : out std_logic_vector(7 downto 0); + LLKTXCHANSPACE : out std_logic_vector(9 downto 0); + LLKTXCHCOMPLETIONREADYN : out std_logic_vector(7 downto 0); + LLKTXCHNONPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCHPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCONFIGREADYN : out std_ulogic; + LLKTXDSTRDYN : out std_ulogic; + MAXPAYLOADSIZE : out std_logic_vector(2 downto 0); + MAXREADREQUESTSIZE : out std_logic_vector(2 downto 0); + MEMSPACEENABLE : out std_ulogic; + MGMTPSO : out std_logic_vector(16 downto 0); + MGMTRDATA : out std_logic_vector(31 downto 0); + MGMTSTATSCREDIT : out std_logic_vector(11 downto 0); + MIMDLLBRADD : out std_logic_vector(11 downto 0); + MIMDLLBREN : out std_ulogic; + MIMDLLBWADD : out std_logic_vector(11 downto 0); + MIMDLLBWDATA : out std_logic_vector(63 downto 0); + MIMDLLBWEN : out std_ulogic; + MIMRXBRADD : out std_logic_vector(12 downto 0); + MIMRXBREN : out std_ulogic; + MIMRXBWADD : out std_logic_vector(12 downto 0); + MIMRXBWDATA : out std_logic_vector(63 downto 0); + MIMRXBWEN : out std_ulogic; + MIMTXBRADD : out std_logic_vector(12 downto 0); + MIMTXBREN : out std_ulogic; + MIMTXBWADD : out std_logic_vector(12 downto 0); + MIMTXBWDATA : out std_logic_vector(63 downto 0); + MIMTXBWEN : out std_ulogic; + PARITYERRORRESPONSE : out std_ulogic; + PIPEDESKEWLANESL0 : out std_ulogic; + PIPEDESKEWLANESL1 : out std_ulogic; + PIPEDESKEWLANESL2 : out std_ulogic; + PIPEDESKEWLANESL3 : out std_ulogic; + PIPEDESKEWLANESL4 : out std_ulogic; + PIPEDESKEWLANESL5 : out std_ulogic; + PIPEDESKEWLANESL6 : out std_ulogic; + PIPEDESKEWLANESL7 : out std_ulogic; + PIPEPOWERDOWNL0 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL1 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL2 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL3 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL4 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL5 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL6 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL7 : out std_logic_vector(1 downto 0); + PIPERESETL0 : out std_ulogic; + PIPERESETL1 : out std_ulogic; + PIPERESETL2 : out std_ulogic; + PIPERESETL3 : out std_ulogic; + PIPERESETL4 : out std_ulogic; + PIPERESETL5 : out std_ulogic; + PIPERESETL6 : out std_ulogic; + PIPERESETL7 : out std_ulogic; + PIPERXPOLARITYL0 : out std_ulogic; + PIPERXPOLARITYL1 : out std_ulogic; + PIPERXPOLARITYL2 : out std_ulogic; + PIPERXPOLARITYL3 : out std_ulogic; + PIPERXPOLARITYL4 : out std_ulogic; + PIPERXPOLARITYL5 : out std_ulogic; + PIPERXPOLARITYL6 : out std_ulogic; + PIPERXPOLARITYL7 : out std_ulogic; + PIPETXCOMPLIANCEL0 : out std_ulogic; + PIPETXCOMPLIANCEL1 : out std_ulogic; + PIPETXCOMPLIANCEL2 : out std_ulogic; + PIPETXCOMPLIANCEL3 : out std_ulogic; + PIPETXCOMPLIANCEL4 : out std_ulogic; + PIPETXCOMPLIANCEL5 : out std_ulogic; + PIPETXCOMPLIANCEL6 : out std_ulogic; + PIPETXCOMPLIANCEL7 : out std_ulogic; + PIPETXDATAKL0 : out std_ulogic; + PIPETXDATAKL1 : out std_ulogic; + PIPETXDATAKL2 : out std_ulogic; + PIPETXDATAKL3 : out std_ulogic; + PIPETXDATAKL4 : out std_ulogic; + PIPETXDATAKL5 : out std_ulogic; + PIPETXDATAKL6 : out std_ulogic; + PIPETXDATAKL7 : out std_ulogic; + PIPETXDATAL0 : out std_logic_vector(7 downto 0); + PIPETXDATAL1 : out std_logic_vector(7 downto 0); + PIPETXDATAL2 : out std_logic_vector(7 downto 0); + PIPETXDATAL3 : out std_logic_vector(7 downto 0); + PIPETXDATAL4 : out std_logic_vector(7 downto 0); + PIPETXDATAL5 : out std_logic_vector(7 downto 0); + PIPETXDATAL6 : out std_logic_vector(7 downto 0); + PIPETXDATAL7 : out std_logic_vector(7 downto 0); + PIPETXDETECTRXLOOPBACKL0 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL1 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL2 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL3 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL4 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL5 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL6 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL7 : out std_ulogic; + PIPETXELECIDLEL0 : out std_ulogic; + PIPETXELECIDLEL1 : out std_ulogic; + PIPETXELECIDLEL2 : out std_ulogic; + PIPETXELECIDLEL3 : out std_ulogic; + PIPETXELECIDLEL4 : out std_ulogic; + PIPETXELECIDLEL5 : out std_ulogic; + PIPETXELECIDLEL6 : out std_ulogic; + PIPETXELECIDLEL7 : out std_ulogic; + SERRENABLE : out std_ulogic; + URREPORTINGENABLE : out std_ulogic; + + AUXPOWER : in std_ulogic; + CFGNEGOTIATEDLINKWIDTH : in std_logic_vector(5 downto 0); + COMPLIANCEAVOID : in std_ulogic; + CRMCFGBRIDGEHOTRESET : in std_ulogic; + CRMCORECLK : in std_ulogic; + CRMCORECLKDLO : in std_ulogic; + CRMCORECLKRXO : in std_ulogic; + CRMCORECLKTXO : in std_ulogic; + CRMLINKRSTN : in std_ulogic; + CRMMACRSTN : in std_ulogic; + CRMMGMTRSTN : in std_ulogic; + CRMNVRSTN : in std_ulogic; + CRMTXHOTRESETN : in std_ulogic; + CRMURSTN : in std_ulogic; + CRMUSERCFGRSTN : in std_ulogic; + CRMUSERCLK : in std_ulogic; + CRMUSERCLKRXO : in std_ulogic; + CRMUSERCLKTXO : in std_ulogic; + CROSSLINKSEED : in std_ulogic; + L0ACKNAKTIMERADJUSTMENT : in std_logic_vector(11 downto 0); + L0ALLDOWNPORTSINL1 : in std_ulogic; + L0ALLDOWNRXPORTSINL0S : in std_ulogic; + L0ASE : in std_ulogic; + L0ASPORTCOUNT : in std_logic_vector(7 downto 0); + L0ASTURNPOOLBITSCONSUMED : in std_logic_vector(2 downto 0); + L0ATTENTIONBUTTONPRESSED : in std_ulogic; + L0CFGASSPANTREEOWNEDSTATE : in std_ulogic; + L0CFGASSTATECHANGECMD : in std_logic_vector(3 downto 0); + L0CFGDISABLESCRAMBLE : in std_ulogic; + L0CFGEXTENDEDSYNC : in std_ulogic; + L0CFGL0SENTRYENABLE : in std_ulogic; + L0CFGL0SENTRYSUP : in std_ulogic; + L0CFGL0SEXITLAT : in std_logic_vector(2 downto 0); + L0CFGLINKDISABLE : in std_ulogic; + L0CFGLOOPBACKMASTER : in std_ulogic; + L0CFGNEGOTIATEDMAXP : in std_logic_vector(2 downto 0); + L0CFGVCENABLE : in std_logic_vector(7 downto 0); + L0CFGVCID : in std_logic_vector(23 downto 0); + L0DLLHOLDLINKUP : in std_ulogic; + L0ELECTROMECHANICALINTERLOCKENGAGED : in std_ulogic; + L0FWDASSERTINTALEGACYINT : in std_ulogic; + L0FWDASSERTINTBLEGACYINT : in std_ulogic; + L0FWDASSERTINTCLEGACYINT : in std_ulogic; + L0FWDASSERTINTDLEGACYINT : in std_ulogic; + L0FWDCORRERRIN : in std_ulogic; + L0FWDDEASSERTINTALEGACYINT : in std_ulogic; + L0FWDDEASSERTINTBLEGACYINT : in std_ulogic; + L0FWDDEASSERTINTCLEGACYINT : in std_ulogic; + L0FWDDEASSERTINTDLEGACYINT : in std_ulogic; + L0FWDFATALERRIN : in std_ulogic; + L0FWDNONFATALERRIN : in std_ulogic; + L0LEGACYINTFUNCT0 : in std_ulogic; + L0MRLSENSORCLOSEDN : in std_ulogic; + L0MSIREQUEST0 : in std_logic_vector(3 downto 0); + L0PACKETHEADERFROMUSER : in std_logic_vector(127 downto 0); + L0PMEREQIN : in std_ulogic; + L0PORTNUMBER : in std_logic_vector(7 downto 0); + L0POWERFAULTDETECTED : in std_ulogic; + L0PRESENCEDETECTSLOTEMPTYN : in std_ulogic; + L0PWRNEWSTATEREQ : in std_ulogic; + L0PWRNEXTLINKSTATE : in std_logic_vector(1 downto 0); + L0REPLAYTIMERADJUSTMENT : in std_logic_vector(11 downto 0); + L0ROOTTURNOFFREQ : in std_ulogic; + L0RXTLTLPNONINITIALIZEDVC : in std_logic_vector(7 downto 0); + L0SENDUNLOCKMESSAGE : in std_ulogic; + L0SETCOMPLETERABORTERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTCORRERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTUNCORRERROR : in std_ulogic; + L0SETDETECTEDCORRERROR : in std_ulogic; + L0SETDETECTEDFATALERROR : in std_ulogic; + L0SETDETECTEDNONFATALERROR : in std_ulogic; + L0SETLINKDETECTEDPARITYERROR : in std_ulogic; + L0SETLINKMASTERDATAPARITY : in std_ulogic; + L0SETLINKRECEIVEDMASTERABORT : in std_ulogic; + L0SETLINKRECEIVEDTARGETABORT : in std_ulogic; + L0SETLINKSIGNALLEDTARGETABORT : in std_ulogic; + L0SETLINKSYSTEMERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONCORRERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTOTHERERROR : in std_ulogic; + L0SETUSERDETECTEDPARITYERROR : in std_ulogic; + L0SETUSERMASTERDATAPARITY : in std_ulogic; + L0SETUSERRECEIVEDMASTERABORT : in std_ulogic; + L0SETUSERRECEIVEDTARGETABORT : in std_ulogic; + L0SETUSERSIGNALLEDTARGETABORT : in std_ulogic; + L0SETUSERSYSTEMERROR : in std_ulogic; + L0TLASFCCREDSTARVATION : in std_ulogic; + L0TLLINKRETRAIN : in std_ulogic; + L0TRANSACTIONSPENDING : in std_ulogic; + L0TXBEACON : in std_ulogic; + L0TXCFGPM : in std_ulogic; + L0TXCFGPMTYPE : in std_logic_vector(2 downto 0); + L0TXTLFCCMPLMCCRED : in std_logic_vector(159 downto 0); + L0TXTLFCCMPLMCUPDATE : in std_logic_vector(15 downto 0); + L0TXTLFCNPOSTBYPCRED : in std_logic_vector(191 downto 0); + L0TXTLFCNPOSTBYPUPDATE : in std_logic_vector(15 downto 0); + L0TXTLFCPOSTORDCRED : in std_logic_vector(159 downto 0); + L0TXTLFCPOSTORDUPDATE : in std_logic_vector(15 downto 0); + L0TXTLSBFCDATA : in std_logic_vector(18 downto 0); + L0TXTLSBFCUPDATE : in std_ulogic; + L0TXTLTLPDATA : in std_logic_vector(63 downto 0); + L0TXTLTLPEDB : in std_ulogic; + L0TXTLTLPENABLE : in std_logic_vector(1 downto 0); + L0TXTLTLPEND : in std_logic_vector(1 downto 0); + L0TXTLTLPLATENCY : in std_logic_vector(3 downto 0); + L0TXTLTLPREQ : in std_ulogic; + L0TXTLTLPREQEND : in std_ulogic; + L0TXTLTLPWIDTH : in std_ulogic; + L0UPSTREAMRXPORTINL0S : in std_ulogic; + L0VC0PREVIEWEXPAND : in std_ulogic; + L0WAKEN : in std_ulogic; + LLKRXCHFIFO : in std_logic_vector(1 downto 0); + LLKRXCHTC : in std_logic_vector(2 downto 0); + LLKRXDSTCONTREQN : in std_ulogic; + LLKRXDSTREQN : in std_ulogic; + LLKTX4DWHEADERN : in std_ulogic; + LLKTXCHFIFO : in std_logic_vector(1 downto 0); + LLKTXCHTC : in std_logic_vector(2 downto 0); + LLKTXCOMPLETEN : in std_ulogic; + LLKTXCREATEECRCN : in std_ulogic; + LLKTXDATA : in std_logic_vector(63 downto 0); + LLKTXENABLEN : in std_logic_vector(1 downto 0); + LLKTXEOFN : in std_ulogic; + LLKTXEOPN : in std_ulogic; + LLKTXSOFN : in std_ulogic; + LLKTXSOPN : in std_ulogic; + LLKTXSRCDSCN : in std_ulogic; + LLKTXSRCRDYN : in std_ulogic; + MAINPOWER : in std_ulogic; + MGMTADDR : in std_logic_vector(10 downto 0); + MGMTBWREN : in std_logic_vector(3 downto 0); + MGMTRDEN : in std_ulogic; + MGMTSTATSCREDITSEL : in std_logic_vector(6 downto 0); + MGMTWDATA : in std_logic_vector(31 downto 0); + MGMTWREN : in std_ulogic; + MIMDLLBRDATA : in std_logic_vector(63 downto 0); + MIMRXBRDATA : in std_logic_vector(63 downto 0); + MIMTXBRDATA : in std_logic_vector(63 downto 0); + PIPEPHYSTATUSL0 : in std_ulogic; + PIPEPHYSTATUSL1 : in std_ulogic; + PIPEPHYSTATUSL2 : in std_ulogic; + PIPEPHYSTATUSL3 : in std_ulogic; + PIPEPHYSTATUSL4 : in std_ulogic; + PIPEPHYSTATUSL5 : in std_ulogic; + PIPEPHYSTATUSL6 : in std_ulogic; + PIPEPHYSTATUSL7 : in std_ulogic; + PIPERXCHANISALIGNEDL0 : in std_ulogic; + PIPERXCHANISALIGNEDL1 : in std_ulogic; + PIPERXCHANISALIGNEDL2 : in std_ulogic; + PIPERXCHANISALIGNEDL3 : in std_ulogic; + PIPERXCHANISALIGNEDL4 : in std_ulogic; + PIPERXCHANISALIGNEDL5 : in std_ulogic; + PIPERXCHANISALIGNEDL6 : in std_ulogic; + PIPERXCHANISALIGNEDL7 : in std_ulogic; + PIPERXDATAKL0 : in std_ulogic; + PIPERXDATAKL1 : in std_ulogic; + PIPERXDATAKL2 : in std_ulogic; + PIPERXDATAKL3 : in std_ulogic; + PIPERXDATAKL4 : in std_ulogic; + PIPERXDATAKL5 : in std_ulogic; + PIPERXDATAKL6 : in std_ulogic; + PIPERXDATAKL7 : in std_ulogic; + PIPERXDATAL0 : in std_logic_vector(7 downto 0); + PIPERXDATAL1 : in std_logic_vector(7 downto 0); + PIPERXDATAL2 : in std_logic_vector(7 downto 0); + PIPERXDATAL3 : in std_logic_vector(7 downto 0); + PIPERXDATAL4 : in std_logic_vector(7 downto 0); + PIPERXDATAL5 : in std_logic_vector(7 downto 0); + PIPERXDATAL6 : in std_logic_vector(7 downto 0); + PIPERXDATAL7 : in std_logic_vector(7 downto 0); + PIPERXELECIDLEL0 : in std_ulogic; + PIPERXELECIDLEL1 : in std_ulogic; + PIPERXELECIDLEL2 : in std_ulogic; + PIPERXELECIDLEL3 : in std_ulogic; + PIPERXELECIDLEL4 : in std_ulogic; + PIPERXELECIDLEL5 : in std_ulogic; + PIPERXELECIDLEL6 : in std_ulogic; + PIPERXELECIDLEL7 : in std_ulogic; + PIPERXSTATUSL0 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL1 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL2 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL3 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL4 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL5 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL6 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL7 : in std_logic_vector(2 downto 0); + PIPERXVALIDL0 : in std_ulogic; + PIPERXVALIDL1 : in std_ulogic; + PIPERXVALIDL2 : in std_ulogic; + PIPERXVALIDL3 : in std_ulogic; + PIPERXVALIDL4 : in std_ulogic; + PIPERXVALIDL5 : in std_ulogic; + PIPERXVALIDL6 : in std_ulogic; + PIPERXVALIDL7 : in std_ulogic + ); + end component; + +signal OPEN1 : std_logic; +signal OPEN8 : std_logic_vector(7 downto 0); +signal OPEN2 : std_logic_vector(1 downto 0); +signal OPEN16 : std_logic_vector(15 downto 0); +signal OPEN19 : std_logic_vector(18 downto 0); +signal OPEN20 : std_logic_vector(19 downto 0); +signal OPEN24 : std_logic_vector(23 downto 0); +signal OPEN4 : std_logic_vector(3 downto 0); +signal OPEN3 : std_logic_vector(2 downto 0); + +signal z1_0 : std_logic := '0'; +signal z1_1 : std_logic := '1'; +signal z2 : std_logic_vector(1 downto 0) := "00"; +signal z3 : std_logic_vector(2 downto 0) := "000"; +signal z4 : std_logic_vector(3 downto 0) := "0000"; +signal z6 : std_logic_vector(5 downto 0) := "000000"; +signal z8 : std_logic_vector(7 downto 0) := "00000000"; + +signal z12 : std_logic_vector(11 downto 0) := "000000000000"; +signal z16 : std_logic_vector(15 downto 0) := "0000000000000000"; +signal z19 : std_logic_vector(18 downto 0) := "0000000000000000000"; +signal z24 : std_logic_vector(23 downto 0) := "000000000000000000000000"; +signal z64 : std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; +signal z160 : std_logic_vector(159 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; +signal z192 : std_logic_vector(191 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + +begin +PCIE_INTERNAL_1_1_inst : PCIE_INTERNAL_1_1 + generic map ( + ACTIVELANESIN => ACTIVELANESIN, + AERBASEPTR => AERBASEPTR, + AERCAPABILITYECRCCHECKCAPABLE => FALSE, + AERCAPABILITYECRCGENCAPABLE => FALSE, + AERCAPABILITYNEXTPTR => AERCAPABILITYNEXTPTR, + BAR0ADDRWIDTH => BAR0ADDRWIDTH, + BAR0EXIST => BAR0EXIST, + BAR0IOMEMN => BAR0IOMEMN, + BAR0MASKWIDTH => BAR0MASKWIDTH, + BAR0PREFETCHABLE => BAR0PREFETCHABLE, + BAR1ADDRWIDTH => BAR1ADDRWIDTH, + BAR1EXIST => BAR1EXIST, + BAR1IOMEMN => BAR1IOMEMN, + BAR1MASKWIDTH => BAR1MASKWIDTH, + BAR1PREFETCHABLE => BAR1PREFETCHABLE, + BAR2ADDRWIDTH => BAR2ADDRWIDTH, + BAR2EXIST => BAR2EXIST, + BAR2IOMEMN => BAR2IOMEMN, + BAR2MASKWIDTH => BAR2MASKWIDTH, + BAR2PREFETCHABLE => BAR2PREFETCHABLE, + BAR3ADDRWIDTH => BAR3ADDRWIDTH, + BAR3EXIST => BAR3EXIST, + BAR3IOMEMN => BAR3IOMEMN, + BAR3MASKWIDTH => BAR3MASKWIDTH, + BAR3PREFETCHABLE => BAR3PREFETCHABLE, + BAR4ADDRWIDTH => BAR4ADDRWIDTH, + BAR4EXIST => BAR4EXIST, + BAR4IOMEMN => BAR4IOMEMN, + BAR4MASKWIDTH => BAR4MASKWIDTH, + BAR4PREFETCHABLE => BAR4PREFETCHABLE, + BAR5EXIST => BAR5EXIST, + BAR5IOMEMN => BAR5IOMEMN, + BAR5MASKWIDTH => BAR5MASKWIDTH, + BAR5PREFETCHABLE => BAR5PREFETCHABLE, + CAPABILITIESPOINTER => CAPABILITIESPOINTER, + CARDBUSCISPOINTER => CARDBUSCISPOINTER, + CLASSCODE => CLASSCODE, + CLKDIVIDED => CLKDIVIDED, + CONFIGROUTING => "001", + DEVICECAPABILITYENDPOINTL0SLATENCY => DEVICECAPABILITYENDPOINTL0SLATENCY, + DEVICECAPABILITYENDPOINTL1LATENCY => DEVICECAPABILITYENDPOINTL1LATENCY, + DEVICEID => DEVICEID, + DEVICESERIALNUMBER => DEVICESERIALNUMBER, + DSNBASEPTR => DSNBASEPTR, + DSNCAPABILITYNEXTPTR => DSNCAPABILITYNEXTPTR, + DUALCOREENABLE => FALSE, + DUALCORESLAVE => FALSE, + DUALROLECFGCNTRLROOTEPN => 0, + EXTCFGCAPPTR => X"00", + EXTCFGXPCAPPTR => X"000", + HEADERTYPE => X"00", + INFINITECOMPLETIONS => INFINITECOMPLETIONS, + INTERRUPTPIN => INTERRUPTPIN, + ISSWITCH => FALSE, + L0SEXITLATENCY => L0SEXITLATENCY, + L0SEXITLATENCYCOMCLK => L0SEXITLATENCYCOMCLK, + L1EXITLATENCY => L1EXITLATENCY, + L1EXITLATENCYCOMCLK => L1EXITLATENCYCOMCLK, + LINKCAPABILITYASPMSUPPORT => LINKCAPABILITYASPMSUPPORT, + LINKCAPABILITYMAXLINKWIDTH => LINKCAPABILITYMAXLINKWIDTH, + LINKSTATUSSLOTCLOCKCONFIG => LINKSTATUSSLOTCLOCKCONFIG, + LLKBYPASS => FALSE, + LOWPRIORITYVCCOUNT => LOWPRIORITYVCCOUNT, + MSIBASEPTR => MSIBASEPTR, + MSICAPABILITYMULTIMSGCAP => MSICAPABILITYMULTIMSGCAP, + MSICAPABILITYNEXTPTR => MSICAPABILITYNEXTPTR, + PBBASEPTR => PBBASEPTR, + PBCAPABILITYDW0BASEPOWER => PBCAPABILITYDW0BASEPOWER, + PBCAPABILITYDW0DATASCALE => PBCAPABILITYDW0DATASCALE, + PBCAPABILITYDW0PMSTATE => PBCAPABILITYDW0PMSTATE, + PBCAPABILITYDW0PMSUBSTATE => PBCAPABILITYDW0PMSUBSTATE, + PBCAPABILITYDW0POWERRAIL => PBCAPABILITYDW0POWERRAIL, + PBCAPABILITYDW0TYPE => PBCAPABILITYDW0TYPE, + PBCAPABILITYDW1BASEPOWER => PBCAPABILITYDW1BASEPOWER, + PBCAPABILITYDW1DATASCALE => PBCAPABILITYDW1DATASCALE, + PBCAPABILITYDW1PMSTATE => PBCAPABILITYDW1PMSTATE, + PBCAPABILITYDW1PMSUBSTATE => PBCAPABILITYDW1PMSUBSTATE, + PBCAPABILITYDW1POWERRAIL => PBCAPABILITYDW1POWERRAIL, + PBCAPABILITYDW1TYPE => PBCAPABILITYDW1TYPE, + PBCAPABILITYDW2BASEPOWER => PBCAPABILITYDW2BASEPOWER, + PBCAPABILITYDW2DATASCALE => PBCAPABILITYDW2DATASCALE, + PBCAPABILITYDW2PMSTATE => PBCAPABILITYDW2PMSTATE, + PBCAPABILITYDW2PMSUBSTATE => PBCAPABILITYDW2PMSUBSTATE, + PBCAPABILITYDW2POWERRAIL => PBCAPABILITYDW2POWERRAIL, + PBCAPABILITYDW2TYPE => PBCAPABILITYDW2TYPE, + PBCAPABILITYDW3BASEPOWER => PBCAPABILITYDW3BASEPOWER, + PBCAPABILITYDW3DATASCALE => PBCAPABILITYDW3DATASCALE, + PBCAPABILITYDW3PMSTATE => PBCAPABILITYDW3PMSTATE, + PBCAPABILITYDW3PMSUBSTATE => PBCAPABILITYDW3PMSUBSTATE, + PBCAPABILITYDW3POWERRAIL => PBCAPABILITYDW3POWERRAIL, + PBCAPABILITYDW3TYPE => PBCAPABILITYDW3TYPE, + PBCAPABILITYNEXTPTR => PBCAPABILITYNEXTPTR, + PBCAPABILITYSYSTEMALLOCATED => PBCAPABILITYSYSTEMALLOCATED, + PCIECAPABILITYINTMSGNUM => "00000", + PCIECAPABILITYNEXTPTR => PCIECAPABILITYNEXTPTR, + PCIECAPABILITYSLOTIMPL => FALSE, + PCIEREVISION => 1, + PMBASEPTR => PMBASEPTR, + PMCAPABILITYAUXCURRENT => PMCAPABILITYAUXCURRENT, + PMCAPABILITYD1SUPPORT => PMCAPABILITYD1SUPPORT, + PMCAPABILITYD2SUPPORT => PMCAPABILITYD2SUPPORT, + PMCAPABILITYDSI => PMCAPABILITYDSI, + PMCAPABILITYNEXTPTR => PMCAPABILITYNEXTPTR, + PMCAPABILITYPMESUPPORT => PMCAPABILITYPMESUPPORT, + PMDATA0 => PMDATA0, + PMDATA1 => PMDATA1, + PMDATA2 => PMDATA2, + PMDATA3 => PMDATA3, + PMDATA4 => PMDATA4, + PMDATA5 => PMDATA5, + PMDATA6 => PMDATA6, + PMDATA7 => PMDATA7, + PMDATA8 => X"00", + PMDATASCALE0 => PMDATASCALE0, + PMDATASCALE1 => PMDATASCALE1, + PMDATASCALE2 => PMDATASCALE2, + PMDATASCALE3 => PMDATASCALE3, + PMDATASCALE4 => PMDATASCALE4, + PMDATASCALE5 => PMDATASCALE5, + PMDATASCALE6 => PMDATASCALE6, + PMDATASCALE7 => PMDATASCALE7, + PMDATASCALE8 => 0, + PMSTATUSCONTROLDATASCALE => "00", + PORTVCCAPABILITYEXTENDEDVCCOUNT => PORTVCCAPABILITYEXTENDEDVCCOUNT, + PORTVCCAPABILITYVCARBCAP => PORTVCCAPABILITYVCARBCAP, + PORTVCCAPABILITYVCARBTABLEOFFSET => PORTVCCAPABILITYVCARBTABLEOFFSET, + RAMSHARETXRX => FALSE, + RESETMODE => RESETMODE, + RETRYRAMREADLATENCY => RETRYRAMREADLATENCY, + RETRYRAMSIZE => RETRYRAMSIZE, + RETRYRAMWIDTH => 0, + RETRYRAMWRITELATENCY => RETRYRAMWRITELATENCY, + RETRYREADADDRPIPE => FALSE, + RETRYREADDATAPIPE => FALSE, + RETRYWRITEPIPE => FALSE, + REVISIONID => REVISIONID, + RXREADADDRPIPE => FALSE, + RXREADDATAPIPE => FALSE, + RXWRITEPIPE => FALSE, + SELECTASMODE => FALSE, + SELECTDLLIF => FALSE, + SLOTCAPABILITYATTBUTTONPRESENT => FALSE, + SLOTCAPABILITYATTINDICATORPRESENT => FALSE, + SLOTCAPABILITYHOTPLUGCAPABLE => FALSE, + SLOTCAPABILITYHOTPLUGSURPRISE => FALSE, + SLOTCAPABILITYMSLSENSORPRESENT => FALSE, + SLOTCAPABILITYPHYSICALSLOTNUM => "0000000000000", + SLOTCAPABILITYPOWERCONTROLLERPRESENT => FALSE, + SLOTCAPABILITYPOWERINDICATORPRESENT => FALSE, + SLOTCAPABILITYSLOTPOWERLIMITSCALE => "00", + SLOTCAPABILITYSLOTPOWERLIMITVALUE => X"00", + SLOTIMPLEMENTED => FALSE, + SUBSYSTEMID => SUBSYSTEMID, + SUBSYSTEMVENDORID => SUBSYSTEMVENDORID, + TLRAMREADLATENCY => TLRAMREADLATENCY, + TLRAMWIDTH => 0, + TLRAMWRITELATENCY => TLRAMWRITELATENCY, + TXREADADDRPIPE => FALSE, + TXREADDATAPIPE => FALSE, + TXTSNFTS => TXTSNFTS, + TXTSNFTSCOMCLK => TXTSNFTSCOMCLK, + TXWRITEPIPE => FALSE, + UPSTREAMFACING => TRUE, + VC0RXFIFOBASEC => VC0RXFIFOBASEC, + VC0RXFIFOBASENP => VC0RXFIFOBASENP, + VC0RXFIFOBASEP => VC0RXFIFOBASEP, + VC0RXFIFOLIMITC => VC0RXFIFOLIMITC, + VC0RXFIFOLIMITNP => VC0RXFIFOLIMITNP, + VC0RXFIFOLIMITP => VC0RXFIFOLIMITP, + VC0TOTALCREDITSCD => VC0TOTALCREDITSCD, + VC0TOTALCREDITSCH => VC0TOTALCREDITSCH, + VC0TOTALCREDITSNPH => VC0TOTALCREDITSNPH, + VC0TOTALCREDITSPD => VC0TOTALCREDITSPD, + VC0TOTALCREDITSPH => VC0TOTALCREDITSPH, + VC0TXFIFOBASEC => VC0TXFIFOBASEC, + VC0TXFIFOBASENP => VC0TXFIFOBASENP, + VC0TXFIFOBASEP => VC0TXFIFOBASEP, + VC0TXFIFOLIMITC => VC0TXFIFOLIMITC, + VC0TXFIFOLIMITNP => VC0TXFIFOLIMITNP, + VC0TXFIFOLIMITP => VC0TXFIFOLIMITP, + VC1RXFIFOBASEC => VC1RXFIFOBASEC, + VC1RXFIFOBASENP => VC1RXFIFOBASENP, + VC1RXFIFOBASEP => VC1RXFIFOBASEP, + VC1RXFIFOLIMITC => VC1RXFIFOLIMITC, + VC1RXFIFOLIMITNP => VC1RXFIFOLIMITNP, + VC1RXFIFOLIMITP => VC1RXFIFOLIMITP, + VC1TOTALCREDITSCD => VC1TOTALCREDITSCD, + VC1TOTALCREDITSCH => VC1TOTALCREDITSCH, + VC1TOTALCREDITSNPH => VC1TOTALCREDITSNPH, + VC1TOTALCREDITSPD => VC1TOTALCREDITSPD, + VC1TOTALCREDITSPH => VC1TOTALCREDITSPH, + VC1TXFIFOBASEC => VC1TXFIFOBASEC, + VC1TXFIFOBASENP => VC1TXFIFOBASENP, + VC1TXFIFOBASEP => VC1TXFIFOBASEP, + VC1TXFIFOLIMITC => VC1TXFIFOLIMITC, + VC1TXFIFOLIMITNP => VC1TXFIFOLIMITNP, + VC1TXFIFOLIMITP => VC1TXFIFOLIMITP, + VCBASEPTR => VCBASEPTR, + VCCAPABILITYNEXTPTR => VCCAPABILITYNEXTPTR, + VENDORID => VENDORID, + XLINKSUPPORTED => FALSE, + XPBASEPTR => XPBASEPTR, + XPDEVICEPORTTYPE => XPDEVICEPORTTYPE, + XPMAXPAYLOAD => XPMAXPAYLOAD, + XPRCBCONTROL => 0 +) + +port map ( + AUXPOWER => AUXPOWER, + BUSMASTERENABLE => BUSMASTERENABLE, + CFGNEGOTIATEDLINKWIDTH => z6, + COMPLIANCEAVOID => COMPLIANCEAVOID, + CRMCFGBRIDGEHOTRESET => z1_0, + CRMCORECLK => CRMCORECLK, + CRMCORECLKDLO => CRMCORECLKDLO, + CRMCORECLKRXO => CRMCORECLKRXO, + CRMCORECLKTXO => CRMCORECLKTXO, + CRMDOHOTRESETN => CRMDOHOTRESETN, + CRMLINKRSTN => CRMLINKRSTN, + CRMMACRSTN => CRMMACRSTN, + CRMMGMTRSTN => CRMMGMTRSTN, + CRMNVRSTN => CRMNVRSTN, + CRMPWRSOFTRESETN => CRMPWRSOFTRESETN, + CRMRXHOTRESETN => OPEN1, + CRMTXHOTRESETN => z1_1, + CRMURSTN => CRMURSTN, + CRMUSERCFGRSTN => CRMUSERCFGRSTN, + CRMUSERCLK => CRMUSERCLK, + CRMUSERCLKRXO => CRMUSERCLKRXO, + CRMUSERCLKTXO => CRMUSERCLKTXO, + CROSSLINKSEED => z1_1, + DLLTXPMDLLPOUTSTANDING => DLLTXPMDLLPOUTSTANDING, + INTERRUPTDISABLE => INTERRUPTDISABLE, + IOSPACEENABLE => IOSPACEENABLE, + L0ACKNAKTIMERADJUSTMENT => z12, + L0ALLDOWNPORTSINL1 => z1_0, + L0ALLDOWNRXPORTSINL0S => z1_0, + L0ASAUTONOMOUSINITCOMPLETED => OPEN1, + L0ASE => z1_0, + L0ASPORTCOUNT => z8, + L0ASTURNPOOLBITSCONSUMED => z3, + L0ATTENTIONBUTTONPRESSED => z1_0, + L0ATTENTIONINDICATORCONTROL => OPEN2, + L0CFGASSPANTREEOWNEDSTATE => z1_0, + L0CFGASSTATECHANGECMD => z4, + L0CFGDISABLESCRAMBLE => L0CFGDISABLESCRAMBLE, + L0CFGEXTENDEDSYNC => z1_0, + L0CFGL0SENTRYENABLE => z1_0, + L0CFGL0SENTRYSUP => z1_0, + L0CFGL0SEXITLAT => z3, + L0CFGLINKDISABLE => z1_0, + L0CFGLOOPBACKACK => L0CFGLOOPBACKACK, + L0CFGLOOPBACKMASTER => L0CFGLOOPBACKMASTER, + L0CFGNEGOTIATEDMAXP => z3, + L0CFGVCENABLE => z8, + L0CFGVCID => z24, + L0COMPLETERID => L0COMPLETERID, + L0CORRERRMSGRCVD => OPEN1, + L0DLLASRXSTATE => OPEN2, + L0DLLASTXSTATE => OPEN1, + L0DLLERRORVECTOR => L0DLLERRORVECTOR, + L0DLLHOLDLINKUP => z1_0, + L0DLLRXACKOUTSTANDING => L0DLLRXACKOUTSTANDING, + L0DLLTXNONFCOUTSTANDING => L0DLLTXNONFCOUTSTANDING, + L0DLLTXOUTSTANDING => L0DLLTXOUTSTANDING, + L0DLLVCSTATUS => L0DLLVCSTATUS, + L0DLUPDOWN => L0DLUPDOWN, + L0ELECTROMECHANICALINTERLOCKENGAGED => z1_0, + L0ERRMSGREQID => OPEN16, + L0FATALERRMSGRCVD => OPEN1, + L0FIRSTCFGWRITEOCCURRED => L0FIRSTCFGWRITEOCCURRED, + L0FWDASSERTINTALEGACYINT => z1_0, + L0FWDASSERTINTBLEGACYINT => z1_0, + L0FWDASSERTINTCLEGACYINT => z1_0, + L0FWDASSERTINTDLEGACYINT => z1_0, + L0FWDCORRERRIN => z1_0, + L0FWDCORRERROUT => OPEN1, + L0FWDDEASSERTINTALEGACYINT => z1_0, + L0FWDDEASSERTINTBLEGACYINT => z1_0, + L0FWDDEASSERTINTCLEGACYINT => z1_0, + L0FWDDEASSERTINTDLEGACYINT => z1_0, + L0FWDFATALERRIN => z1_0, + L0FWDFATALERROUT => OPEN1, + L0FWDNONFATALERRIN => z1_0, + L0FWDNONFATALERROUT => OPEN1, + L0LEGACYINTFUNCT0 => L0LEGACYINTFUNCT0, + L0LTSSMSTATE => L0LTSSMSTATE, + L0MACENTEREDL0 => L0MACENTEREDL0, + L0MACLINKTRAINING => L0MACLINKTRAINING, + L0MACLINKUP => L0MACLINKUP, + L0MACNEGOTIATEDLINKWIDTH => L0MACNEGOTIATEDLINKWIDTH, + L0MACNEWSTATEACK => L0MACNEWSTATEACK, + L0MACRXL0SSTATE => L0MACRXL0SSTATE, + L0MACUPSTREAMDOWNSTREAM => OPEN1, + L0MCFOUND => OPEN3, + L0MRLSENSORCLOSEDN => z1_0, + L0MSIENABLE0 => L0MSIENABLE0, + L0MSIREQUEST0 => L0MSIREQUEST0, + L0MULTIMSGEN0 => L0MULTIMSGEN0, + L0NONFATALERRMSGRCVD => OPEN1, + L0PACKETHEADERFROMUSER => L0PACKETHEADERFROMUSER, + L0PMEACK => L0PMEACK, + L0PMEEN => L0PMEEN, + L0PMEREQIN => L0PMEREQIN, + L0PMEREQOUT => L0PMEREQOUT, + L0PORTNUMBER => z8, + L0POWERCONTROLLERCONTROL => OPEN1, + L0POWERFAULTDETECTED => z1_0, + L0POWERINDICATORCONTROL => OPEN2, + L0PRESENCEDETECTSLOTEMPTYN => z1_0, + L0PWRINHIBITTRANSFERS => OPEN1, + L0PWRL1STATE => L0PWRL1STATE, + L0PWRL23READYDEVICE => OPEN1, + L0PWRL23READYSTATE => L0PWRL23READYSTATE, + L0PWRNEWSTATEREQ => z1_0, + L0PWRNEXTLINKSTATE => z2, + L0PWRSTATE0 => L0PWRSTATE0, + L0PWRTURNOFFREQ => L0PWRTURNOFFREQ, + L0PWRTXL0SSTATE => L0PWRTXL0SSTATE, + L0RECEIVEDASSERTINTALEGACYINT => OPEN1, + L0RECEIVEDASSERTINTBLEGACYINT => OPEN1, + L0RECEIVEDASSERTINTCLEGACYINT => OPEN1, + L0RECEIVEDASSERTINTDLEGACYINT => OPEN1, + L0RECEIVEDDEASSERTINTALEGACYINT => OPEN1, + L0RECEIVEDDEASSERTINTBLEGACYINT => OPEN1, + L0RECEIVEDDEASSERTINTCLEGACYINT => OPEN1, + L0RECEIVEDDEASSERTINTDLEGACYINT => OPEN1, + L0REPLAYTIMERADJUSTMENT => z12, + L0ROOTTURNOFFREQ => z1_0, + L0RXBEACON => OPEN1, + L0RXDLLFCCMPLMCCRED => OPEN24, + L0RXDLLFCCMPLMCUPDATE => OPEN8, + L0RXDLLFCNPOSTBYPCRED => OPEN20, + L0RXDLLFCNPOSTBYPUPDATE => OPEN8, + L0RXDLLFCPOSTORDCRED => OPEN24, + L0RXDLLFCPOSTORDUPDATE => OPEN8, + L0RXDLLPM => L0RXDLLPM, + L0RXDLLPMTYPE => L0RXDLLPMTYPE, + L0RXDLLSBFCDATA => OPEN19, + L0RXDLLSBFCUPDATE => OPEN1, + L0RXDLLTLPECRCOK => OPEN1, + L0RXDLLTLPEND => OPEN2, + L0RXMACLINKERROR => L0RXMACLINKERROR, + L0RXTLTLPNONINITIALIZEDVC => z8, + L0SENDUNLOCKMESSAGE => z1_0, + L0SETCOMPLETERABORTERROR => L0SETCOMPLETERABORTERROR, + L0SETCOMPLETIONTIMEOUTCORRERROR => L0SETCOMPLETIONTIMEOUTCORRERROR, + L0SETCOMPLETIONTIMEOUTUNCORRERROR => L0SETCOMPLETIONTIMEOUTUNCORRERROR, + L0SETDETECTEDCORRERROR => L0SETDETECTEDCORRERROR, + L0SETDETECTEDFATALERROR => L0SETDETECTEDFATALERROR, + L0SETDETECTEDNONFATALERROR => L0SETDETECTEDNONFATALERROR, + L0SETLINKDETECTEDPARITYERROR => z1_0, + L0SETLINKMASTERDATAPARITY => z1_0, + L0SETLINKRECEIVEDMASTERABORT => z1_0, + L0SETLINKRECEIVEDTARGETABORT => z1_0, + L0SETLINKSIGNALLEDTARGETABORT => z1_0, + L0SETLINKSYSTEMERROR => z1_0, + L0SETUNEXPECTEDCOMPLETIONCORRERROR => L0SETUNEXPECTEDCOMPLETIONCORRERROR, + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR => L0SETUNEXPECTEDCOMPLETIONUNCORRERROR, + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR => L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR, + L0SETUNSUPPORTEDREQUESTOTHERERROR => L0SETUNSUPPORTEDREQUESTOTHERERROR, + L0SETUSERDETECTEDPARITYERROR => L0SETUSERDETECTEDPARITYERROR, + L0SETUSERMASTERDATAPARITY => L0SETUSERMASTERDATAPARITY, + L0SETUSERRECEIVEDMASTERABORT => L0SETUSERRECEIVEDMASTERABORT, + L0SETUSERRECEIVEDTARGETABORT => L0SETUSERRECEIVEDTARGETABORT, + L0SETUSERSIGNALLEDTARGETABORT => L0SETUSERSIGNALLEDTARGETABORT, + L0SETUSERSYSTEMERROR => L0SETUSERSYSTEMERROR, + L0STATSCFGOTHERRECEIVED => L0STATSCFGOTHERRECEIVED, + L0STATSCFGOTHERTRANSMITTED => L0STATSCFGOTHERTRANSMITTED, + L0STATSCFGRECEIVED => L0STATSCFGRECEIVED, + L0STATSCFGTRANSMITTED => L0STATSCFGTRANSMITTED, + L0STATSDLLPRECEIVED => L0STATSDLLPRECEIVED, + L0STATSDLLPTRANSMITTED => L0STATSDLLPTRANSMITTED, + L0STATSOSRECEIVED => L0STATSOSRECEIVED, + L0STATSOSTRANSMITTED => L0STATSOSTRANSMITTED, + L0STATSTLPRECEIVED => L0STATSTLPRECEIVED, + L0STATSTLPTRANSMITTED => L0STATSTLPTRANSMITTED, + L0TLASFCCREDSTARVATION => z1_0, + L0TLLINKRETRAIN => z1_0, + L0TOGGLEELECTROMECHANICALINTERLOCK => OPEN1, + L0TRANSACTIONSPENDING => L0TRANSACTIONSPENDING, + L0TRANSFORMEDVC => OPEN3, + L0TXBEACON => z1_0, + L0TXCFGPM => z1_0, + L0TXCFGPMTYPE => z3, + L0TXDLLFCCMPLMCUPDATED => OPEN8, + L0TXDLLFCNPOSTBYPUPDATED => OPEN8, + L0TXDLLFCPOSTORDUPDATED => OPEN8, + L0TXDLLPMUPDATED => OPEN1, + L0TXDLLSBFCUPDATED => OPEN1, + L0TXTLFCCMPLMCCRED => z160, + L0TXTLFCCMPLMCUPDATE => z16, + L0TXTLFCNPOSTBYPCRED => z192, + L0TXTLFCNPOSTBYPUPDATE => z16, + L0TXTLFCPOSTORDCRED => z160, + L0TXTLFCPOSTORDUPDATE => z16, + L0TXTLSBFCDATA => z19, + L0TXTLSBFCUPDATE => z1_0, + L0TXTLTLPDATA => z64, + L0TXTLTLPEDB => z1_0, + L0TXTLTLPENABLE => z2, + L0TXTLTLPEND => z2, + L0TXTLTLPLATENCY => z4, + L0TXTLTLPREQ => z1_0, + L0TXTLTLPREQEND => z1_0, + L0TXTLTLPWIDTH => z1_0, + L0UCBYPFOUND => OPEN4, + L0UCORDFOUND => OPEN4, + L0UNLOCKRECEIVED => L0UNLOCKRECEIVED, + L0UPSTREAMRXPORTINL0S => z1_0, + L0VC0PREVIEWEXPAND => z1_0, + L0WAKEN => z1_1, + LLKRX4DWHEADERN => OPEN1, + LLKRXCHCOMPLETIONAVAILABLEN => LLKRXCHCOMPLETIONAVAILABLEN, + LLKRXCHCOMPLETIONPARTIALN => OPEN8, + LLKRXCHCONFIGAVAILABLEN => OPEN1, + LLKRXCHCONFIGPARTIALN => OPEN1, + LLKRXCHFIFO => LLKRXCHFIFO, + LLKRXCHNONPOSTEDAVAILABLEN => LLKRXCHNONPOSTEDAVAILABLEN, + LLKRXCHNONPOSTEDPARTIALN => OPEN8, + LLKRXCHPOSTEDAVAILABLEN => LLKRXCHPOSTEDAVAILABLEN, + LLKRXCHPOSTEDPARTIALN => OPEN8, + LLKRXCHTC => LLKRXCHTC, + LLKRXDATA => LLKRXDATA, + LLKRXDSTCONTREQN => LLKRXDSTCONTREQN, + LLKRXDSTREQN => LLKRXDSTREQN, + LLKRXECRCBADN => OPEN1, + LLKRXEOFN => LLKRXEOFN, + LLKRXEOPN => LLKRXEOPN, + LLKRXPREFERREDTYPE => LLKRXPREFERREDTYPE, + LLKRXSOFN => LLKRXSOFN, + LLKRXSOPN => LLKRXSOPN, + LLKRXSRCDSCN => OPEN1, + LLKRXSRCLASTREQN => LLKRXSRCLASTREQN, + LLKRXSRCRDYN => LLKRXSRCRDYN, + LLKRXVALIDN => LLKRXVALIDN, + LLKTCSTATUS => LLKTCSTATUS, + LLKTX4DWHEADERN => z1_1, + LLKTXCHANSPACE => LLKTXCHANSPACE, + LLKTXCHCOMPLETIONREADYN => LLKTXCHCOMPLETIONREADYN, + LLKTXCHFIFO => LLKTXCHFIFO, + LLKTXCHNONPOSTEDREADYN => LLKTXCHNONPOSTEDREADYN, + LLKTXCHPOSTEDREADYN => LLKTXCHPOSTEDREADYN, + LLKTXCHTC => LLKTXCHTC, + LLKTXCOMPLETEN => z1_1, + LLKTXCONFIGREADYN => LLKTXCONFIGREADYN, + LLKTXCREATEECRCN => z1_1, + LLKTXDATA => LLKTXDATA, + LLKTXDSTRDYN => LLKTXDSTRDYN, + LLKTXENABLEN => LLKTXENABLEN, + LLKTXEOFN => LLKTXEOFN, + LLKTXEOPN => LLKTXEOPN, + LLKTXSOFN => LLKTXSOFN, + LLKTXSOPN => LLKTXSOPN, + LLKTXSRCDSCN => LLKTXSRCDSCN, + LLKTXSRCRDYN => LLKTXSRCRDYN, + MAINPOWER => z1_1, + MAXPAYLOADSIZE => MAXPAYLOADSIZE, + MAXREADREQUESTSIZE => MAXREADREQUESTSIZE, + MEMSPACEENABLE => MEMSPACEENABLE, + MGMTADDR => MGMTADDR, + MGMTBWREN => MGMTBWREN, + MGMTPSO => MGMTPSO, + MGMTRDATA => MGMTRDATA, + MGMTRDEN => MGMTRDEN, + MGMTSTATSCREDIT => MGMTSTATSCREDIT, + MGMTSTATSCREDITSEL => MGMTSTATSCREDITSEL, + MGMTWDATA => MGMTWDATA, + MGMTWREN => MGMTWREN, + MIMDLLBRADD => MIMDLLBRADD, + MIMDLLBRDATA => MIMDLLBRDATA, + MIMDLLBREN => MIMDLLBREN, + MIMDLLBWADD => MIMDLLBWADD, + MIMDLLBWDATA => MIMDLLBWDATA, + MIMDLLBWEN => MIMDLLBWEN, + MIMRXBRADD => MIMRXBRADD, + MIMRXBRDATA => MIMRXBRDATA, + MIMRXBREN => MIMRXBREN, + MIMRXBWADD => MIMRXBWADD, + MIMRXBWDATA => MIMRXBWDATA, + MIMRXBWEN => MIMRXBWEN, + MIMTXBRADD => MIMTXBRADD, + MIMTXBRDATA => MIMTXBRDATA, + MIMTXBREN => MIMTXBREN, + MIMTXBWADD => MIMTXBWADD, + MIMTXBWDATA => MIMTXBWDATA, + MIMTXBWEN => MIMTXBWEN, + PARITYERRORRESPONSE => PARITYERRORRESPONSE, + PIPEDESKEWLANESL0 => PIPEDESKEWLANESL0, + PIPEDESKEWLANESL1 => PIPEDESKEWLANESL1, + PIPEDESKEWLANESL2 => PIPEDESKEWLANESL2, + PIPEDESKEWLANESL3 => PIPEDESKEWLANESL3, + PIPEDESKEWLANESL4 => PIPEDESKEWLANESL4, + PIPEDESKEWLANESL5 => PIPEDESKEWLANESL5, + PIPEDESKEWLANESL6 => PIPEDESKEWLANESL6, + PIPEDESKEWLANESL7 => PIPEDESKEWLANESL7, + PIPEPHYSTATUSL0 => PIPEPHYSTATUSL0, + PIPEPHYSTATUSL1 => PIPEPHYSTATUSL1, + PIPEPHYSTATUSL2 => PIPEPHYSTATUSL2, + PIPEPHYSTATUSL3 => PIPEPHYSTATUSL3, + PIPEPHYSTATUSL4 => PIPEPHYSTATUSL4, + PIPEPHYSTATUSL5 => PIPEPHYSTATUSL5, + PIPEPHYSTATUSL6 => PIPEPHYSTATUSL6, + PIPEPHYSTATUSL7 => PIPEPHYSTATUSL7, + PIPEPOWERDOWNL0 => PIPEPOWERDOWNL0, + PIPEPOWERDOWNL1 => PIPEPOWERDOWNL1, + PIPEPOWERDOWNL2 => PIPEPOWERDOWNL2, + PIPEPOWERDOWNL3 => PIPEPOWERDOWNL3, + PIPEPOWERDOWNL4 => PIPEPOWERDOWNL4, + PIPEPOWERDOWNL5 => PIPEPOWERDOWNL5, + PIPEPOWERDOWNL6 => PIPEPOWERDOWNL6, + PIPEPOWERDOWNL7 => PIPEPOWERDOWNL7, + PIPERESETL0 => PIPERESETL0, + PIPERESETL1 => PIPERESETL1, + PIPERESETL2 => PIPERESETL2, + PIPERESETL3 => PIPERESETL3, + PIPERESETL4 => PIPERESETL4, + PIPERESETL5 => PIPERESETL5, + PIPERESETL6 => PIPERESETL6, + PIPERESETL7 => PIPERESETL7, + PIPERXCHANISALIGNEDL0 => PIPERXCHANISALIGNEDL0, + PIPERXCHANISALIGNEDL1 => PIPERXCHANISALIGNEDL1, + PIPERXCHANISALIGNEDL2 => PIPERXCHANISALIGNEDL2, + PIPERXCHANISALIGNEDL3 => PIPERXCHANISALIGNEDL3, + PIPERXCHANISALIGNEDL4 => PIPERXCHANISALIGNEDL4, + PIPERXCHANISALIGNEDL5 => PIPERXCHANISALIGNEDL5, + PIPERXCHANISALIGNEDL6 => PIPERXCHANISALIGNEDL6, + PIPERXCHANISALIGNEDL7 => PIPERXCHANISALIGNEDL7, + PIPERXDATAKL0 => PIPERXDATAKL0, + PIPERXDATAKL1 => PIPERXDATAKL1, + PIPERXDATAKL2 => PIPERXDATAKL2, + PIPERXDATAKL3 => PIPERXDATAKL3, + PIPERXDATAKL4 => PIPERXDATAKL4, + PIPERXDATAKL5 => PIPERXDATAKL5, + PIPERXDATAKL6 => PIPERXDATAKL6, + PIPERXDATAKL7 => PIPERXDATAKL7, + PIPERXDATAL0 => PIPERXDATAL0, + PIPERXDATAL1 => PIPERXDATAL1, + PIPERXDATAL2 => PIPERXDATAL2, + PIPERXDATAL3 => PIPERXDATAL3, + PIPERXDATAL4 => PIPERXDATAL4, + PIPERXDATAL5 => PIPERXDATAL5, + PIPERXDATAL6 => PIPERXDATAL6, + PIPERXDATAL7 => PIPERXDATAL7, + PIPERXELECIDLEL0 => PIPERXELECIDLEL0, + PIPERXELECIDLEL1 => PIPERXELECIDLEL1, + PIPERXELECIDLEL2 => PIPERXELECIDLEL2, + PIPERXELECIDLEL3 => PIPERXELECIDLEL3, + PIPERXELECIDLEL4 => PIPERXELECIDLEL4, + PIPERXELECIDLEL5 => PIPERXELECIDLEL5, + PIPERXELECIDLEL6 => PIPERXELECIDLEL6, + PIPERXELECIDLEL7 => PIPERXELECIDLEL7, + PIPERXPOLARITYL0 => PIPERXPOLARITYL0, + PIPERXPOLARITYL1 => PIPERXPOLARITYL1, + PIPERXPOLARITYL2 => PIPERXPOLARITYL2, + PIPERXPOLARITYL3 => PIPERXPOLARITYL3, + PIPERXPOLARITYL4 => PIPERXPOLARITYL4, + PIPERXPOLARITYL5 => PIPERXPOLARITYL5, + PIPERXPOLARITYL6 => PIPERXPOLARITYL6, + PIPERXPOLARITYL7 => PIPERXPOLARITYL7, + PIPERXSTATUSL0 => PIPERXSTATUSL0, + PIPERXSTATUSL1 => PIPERXSTATUSL1, + PIPERXSTATUSL2 => PIPERXSTATUSL2, + PIPERXSTATUSL3 => PIPERXSTATUSL3, + PIPERXSTATUSL4 => PIPERXSTATUSL4, + PIPERXSTATUSL5 => PIPERXSTATUSL5, + PIPERXSTATUSL6 => PIPERXSTATUSL6, + PIPERXSTATUSL7 => PIPERXSTATUSL7, + PIPERXVALIDL0 => PIPERXVALIDL0, + PIPERXVALIDL1 => PIPERXVALIDL1, + PIPERXVALIDL2 => PIPERXVALIDL2, + PIPERXVALIDL3 => PIPERXVALIDL3, + PIPERXVALIDL4 => PIPERXVALIDL4, + PIPERXVALIDL5 => PIPERXVALIDL5, + PIPERXVALIDL6 => PIPERXVALIDL6, + PIPERXVALIDL7 => PIPERXVALIDL7, + PIPETXCOMPLIANCEL0 => PIPETXCOMPLIANCEL0, + PIPETXCOMPLIANCEL1 => PIPETXCOMPLIANCEL1, + PIPETXCOMPLIANCEL2 => PIPETXCOMPLIANCEL2, + PIPETXCOMPLIANCEL3 => PIPETXCOMPLIANCEL3, + PIPETXCOMPLIANCEL4 => PIPETXCOMPLIANCEL4, + PIPETXCOMPLIANCEL5 => PIPETXCOMPLIANCEL5, + PIPETXCOMPLIANCEL6 => PIPETXCOMPLIANCEL6, + PIPETXCOMPLIANCEL7 => PIPETXCOMPLIANCEL7, + PIPETXDATAKL0 => PIPETXDATAKL0, + PIPETXDATAKL1 => PIPETXDATAKL1, + PIPETXDATAKL2 => PIPETXDATAKL2, + PIPETXDATAKL3 => PIPETXDATAKL3, + PIPETXDATAKL4 => PIPETXDATAKL4, + PIPETXDATAKL5 => PIPETXDATAKL5, + PIPETXDATAKL6 => PIPETXDATAKL6, + PIPETXDATAKL7 => PIPETXDATAKL7, + PIPETXDATAL0 => PIPETXDATAL0, + PIPETXDATAL1 => PIPETXDATAL1, + PIPETXDATAL2 => PIPETXDATAL2, + PIPETXDATAL3 => PIPETXDATAL3, + PIPETXDATAL4 => PIPETXDATAL4, + PIPETXDATAL5 => PIPETXDATAL5, + PIPETXDATAL6 => PIPETXDATAL6, + PIPETXDATAL7 => PIPETXDATAL7, + PIPETXDETECTRXLOOPBACKL0 => PIPETXDETECTRXLOOPBACKL0, + PIPETXDETECTRXLOOPBACKL1 => PIPETXDETECTRXLOOPBACKL1, + PIPETXDETECTRXLOOPBACKL2 => PIPETXDETECTRXLOOPBACKL2, + PIPETXDETECTRXLOOPBACKL3 => PIPETXDETECTRXLOOPBACKL3, + PIPETXDETECTRXLOOPBACKL4 => PIPETXDETECTRXLOOPBACKL4, + PIPETXDETECTRXLOOPBACKL5 => PIPETXDETECTRXLOOPBACKL5, + PIPETXDETECTRXLOOPBACKL6 => PIPETXDETECTRXLOOPBACKL6, + PIPETXDETECTRXLOOPBACKL7 => PIPETXDETECTRXLOOPBACKL7, + PIPETXELECIDLEL0 => PIPETXELECIDLEL0, + PIPETXELECIDLEL1 => PIPETXELECIDLEL1, + PIPETXELECIDLEL2 => PIPETXELECIDLEL2, + PIPETXELECIDLEL3 => PIPETXELECIDLEL3, + PIPETXELECIDLEL4 => PIPETXELECIDLEL4, + PIPETXELECIDLEL5 => PIPETXELECIDLEL5, + PIPETXELECIDLEL6 => PIPETXELECIDLEL6, + PIPETXELECIDLEL7 => PIPETXELECIDLEL7, + SERRENABLE => SERRENABLE, + URREPORTINGENABLE => URREPORTINGENABLE + +); + +end PCIE_EP_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2006 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / PCI Express +-- /___/ /\ Filename : pcie_internal_1_1.vhd +-- \ \ / \ Timestamp : Thu Dec 8 2005 +-- \___\/\___\ +-- +-- Revision: +-- 12/08/05 - Initial version. +-- 01/09/06 - Added architecture +-- 01/23/06 - Parameter MC updates CR#224562 +-- 01/27/06 - CR#224810 Remove GSR pins +-- 02/23/06 - Updated Header +-- 04/24/06 - CR#230393 - Updated timing according to the spreadsheets +-- 04/28/06 - CR#230712 - Spreadsheet update +-- 05/23/06 - CR#231962 - Add buffers for connectivity +-- 08/14/06 - CR#421379 - PCIE updated to PCIE_INTERNAL_1_1 +-- - spreadsheet updates on parameter default values +-- 10/26/06 - - replaced ZERO_DELAY with CLK_DELAY to be consistent with writers (PPC440 update) +-- End Revision + +----- CELL PCIE_INTERNAL_1_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +library secureip; +use secureip.all; + +entity PCIE_INTERNAL_1_1 is +generic ( + ACTIVELANESIN : bit_vector := X"01"; + AERBASEPTR : bit_vector := X"110"; + AERCAPABILITYECRCCHECKCAPABLE : boolean := FALSE; + AERCAPABILITYECRCGENCAPABLE : boolean := FALSE; + AERCAPABILITYNEXTPTR : bit_vector := X"138"; + BAR0ADDRWIDTH : integer := 0; + BAR0EXIST : boolean := TRUE; + BAR0IOMEMN : integer := 0; + BAR0MASKWIDTH : bit_vector := X"14"; + BAR0PREFETCHABLE : boolean := TRUE; + BAR1ADDRWIDTH : integer := 0; + BAR1EXIST : boolean := FALSE; + BAR1IOMEMN : integer := 0; + BAR1MASKWIDTH : bit_vector := X"00"; + BAR1PREFETCHABLE : boolean := FALSE; + BAR2ADDRWIDTH : integer := 0; + BAR2EXIST : boolean := FALSE; + BAR2IOMEMN : integer := 0; + BAR2MASKWIDTH : bit_vector := X"00"; + BAR2PREFETCHABLE : boolean := FALSE; + BAR3ADDRWIDTH : integer := 0; + BAR3EXIST : boolean := FALSE; + BAR3IOMEMN : integer := 0; + BAR3MASKWIDTH : bit_vector := X"00"; + BAR3PREFETCHABLE : boolean := FALSE; + BAR4ADDRWIDTH : integer := 0; + BAR4EXIST : boolean := FALSE; + BAR4IOMEMN : integer := 0; + BAR4MASKWIDTH : bit_vector := X"00"; + BAR4PREFETCHABLE : boolean := FALSE; + BAR5EXIST : boolean := FALSE; + BAR5IOMEMN : integer := 0; + BAR5MASKWIDTH : bit_vector := X"00"; + BAR5PREFETCHABLE : boolean := FALSE; + CAPABILITIESPOINTER : bit_vector := X"40"; + CARDBUSCISPOINTER : bit_vector := X"00000000"; + CLASSCODE : bit_vector := X"058000"; + CLKDIVIDED : boolean := FALSE; + CONFIGROUTING : bit_vector := X"1"; + DEVICECAPABILITYENDPOINTL0SLATENCY : bit_vector := X"0"; + DEVICECAPABILITYENDPOINTL1LATENCY : bit_vector := X"0"; + DEVICEID : bit_vector := X"5050"; + DEVICESERIALNUMBER : bit_vector := X"E000000001000A35"; + DSNBASEPTR : bit_vector := X"148"; + DSNCAPABILITYNEXTPTR : bit_vector := X"154"; + DUALCOREENABLE : boolean := FALSE; + DUALCORESLAVE : boolean := FALSE; + DUALROLECFGCNTRLROOTEPN : integer := 0; + EXTCFGCAPPTR : bit_vector := X"00"; + EXTCFGXPCAPPTR : bit_vector := X"000"; + HEADERTYPE : bit_vector := X"00"; + INFINITECOMPLETIONS : boolean := TRUE; + INTERRUPTPIN : bit_vector := X"00"; + ISSWITCH : boolean := FALSE; + L0SEXITLATENCY : integer := 7; + L0SEXITLATENCYCOMCLK : integer := 7; + L1EXITLATENCY : integer := 7; + L1EXITLATENCYCOMCLK : integer := 7; + LINKCAPABILITYASPMSUPPORT : bit_vector := X"1"; + LINKCAPABILITYMAXLINKWIDTH : bit_vector := X"01"; + LINKSTATUSSLOTCLOCKCONFIG : boolean := FALSE; + LLKBYPASS : boolean := FALSE; + LOWPRIORITYVCCOUNT : integer := 0; + MSIBASEPTR : bit_vector := X"048"; + MSICAPABILITYMULTIMSGCAP : bit_vector := X"0"; + MSICAPABILITYNEXTPTR : bit_vector := X"60"; + PBBASEPTR : bit_vector := X"138"; + PBCAPABILITYDW0BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW0DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW0PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW0PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW0POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW0TYPE : bit_vector := X"0"; + PBCAPABILITYDW1BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW1DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW1PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW1PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW1POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW1TYPE : bit_vector := X"0"; + PBCAPABILITYDW2BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW2DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW2PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW2PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW2POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW2TYPE : bit_vector := X"0"; + PBCAPABILITYDW3BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW3DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW3PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW3PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW3POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW3TYPE : bit_vector := X"0"; + PBCAPABILITYNEXTPTR : bit_vector := X"148"; + PBCAPABILITYSYSTEMALLOCATED : boolean := FALSE; + PCIECAPABILITYINTMSGNUM : bit_vector := X"00"; + PCIECAPABILITYNEXTPTR : bit_vector := X"00"; + PCIECAPABILITYSLOTIMPL : boolean := FALSE; + PCIEREVISION : integer := 1; + PMBASEPTR : bit_vector := X"040"; + PMCAPABILITYAUXCURRENT : bit_vector := X"0"; + PMCAPABILITYD1SUPPORT : boolean := FALSE; + PMCAPABILITYD2SUPPORT : boolean := FALSE; + PMCAPABILITYDSI : boolean := TRUE; + PMCAPABILITYNEXTPTR : bit_vector := X"60"; + PMCAPABILITYPMESUPPORT : bit_vector := X"00"; + PMDATA0 : bit_vector := X"00"; + PMDATA1 : bit_vector := X"00"; + PMDATA2 : bit_vector := X"00"; + PMDATA3 : bit_vector := X"00"; + PMDATA4 : bit_vector := X"00"; + PMDATA5 : bit_vector := X"00"; + PMDATA6 : bit_vector := X"00"; + PMDATA7 : bit_vector := X"00"; + PMDATA8 : bit_vector := X"00"; + PMDATASCALE0 : integer := 0; + PMDATASCALE1 : integer := 0; + PMDATASCALE2 : integer := 0; + PMDATASCALE3 : integer := 0; + PMDATASCALE4 : integer := 0; + PMDATASCALE5 : integer := 0; + PMDATASCALE6 : integer := 0; + PMDATASCALE7 : integer := 0; + PMDATASCALE8 : integer := 0; + PMSTATUSCONTROLDATASCALE : bit_vector := X"0"; + PORTVCCAPABILITYEXTENDEDVCCOUNT : bit_vector := X"0"; + PORTVCCAPABILITYVCARBCAP : bit_vector := X"00"; + PORTVCCAPABILITYVCARBTABLEOFFSET : bit_vector := X"00"; + RAMSHARETXRX : boolean := FALSE; + RESETMODE : boolean := FALSE; + RETRYRAMREADLATENCY : integer := 3; + RETRYRAMSIZE : bit_vector := X"009"; + RETRYRAMWIDTH : integer := 0; + RETRYRAMWRITELATENCY : integer := 1; + RETRYREADADDRPIPE : boolean := FALSE; + RETRYREADDATAPIPE : boolean := FALSE; + RETRYWRITEPIPE : boolean := FALSE; + REVISIONID : bit_vector := X"00"; + RXREADADDRPIPE : boolean := FALSE; + RXREADDATAPIPE : boolean := FALSE; + RXWRITEPIPE : boolean := FALSE; + SELECTASMODE : boolean := FALSE; + SELECTDLLIF : boolean := FALSE; + SLOTCAPABILITYATTBUTTONPRESENT : boolean := FALSE; + SLOTCAPABILITYATTINDICATORPRESENT : boolean := FALSE; + SLOTCAPABILITYHOTPLUGCAPABLE : boolean := FALSE; + SLOTCAPABILITYHOTPLUGSURPRISE : boolean := FALSE; + SLOTCAPABILITYMSLSENSORPRESENT : boolean := FALSE; + SLOTCAPABILITYPHYSICALSLOTNUM : bit_vector := X"0000"; + SLOTCAPABILITYPOWERCONTROLLERPRESENT : boolean := FALSE; + SLOTCAPABILITYPOWERINDICATORPRESENT : boolean := FALSE; + SLOTCAPABILITYSLOTPOWERLIMITSCALE : bit_vector := X"0"; + SLOTCAPABILITYSLOTPOWERLIMITVALUE : bit_vector := X"00"; + SLOTIMPLEMENTED : boolean := FALSE; + SUBSYSTEMID : bit_vector := X"5050"; + SUBSYSTEMVENDORID : bit_vector := X"10EE"; + TLRAMREADLATENCY : integer := 3; + TLRAMWIDTH : integer := 0; + TLRAMWRITELATENCY : integer := 1; + TXREADADDRPIPE : boolean := FALSE; + TXREADDATAPIPE : boolean := FALSE; + TXTSNFTS : integer := 255; + TXTSNFTSCOMCLK : integer := 255; + TXWRITEPIPE : boolean := FALSE; + UPSTREAMFACING : boolean := TRUE; + VC0RXFIFOBASEC : bit_vector := X"0098"; + VC0RXFIFOBASENP : bit_vector := X"0080"; + VC0RXFIFOBASEP : bit_vector := X"0000"; + VC0RXFIFOLIMITC : bit_vector := X"0117"; + VC0RXFIFOLIMITNP : bit_vector := X"0097"; + VC0RXFIFOLIMITP : bit_vector := X"007f"; + VC0TOTALCREDITSCD : bit_vector := X"000"; + VC0TOTALCREDITSCH : bit_vector := X"00"; + VC0TOTALCREDITSNPH : bit_vector := X"08"; + VC0TOTALCREDITSPD : bit_vector := X"034"; + VC0TOTALCREDITSPH : bit_vector := X"08"; + VC0TXFIFOBASEC : bit_vector := X"0098"; + VC0TXFIFOBASENP : bit_vector := X"0080"; + VC0TXFIFOBASEP : bit_vector := X"0000"; + VC0TXFIFOLIMITC : bit_vector := X"0117"; + VC0TXFIFOLIMITNP : bit_vector := X"0097"; + VC0TXFIFOLIMITP : bit_vector := X"007f"; + VC1RXFIFOBASEC : bit_vector := X"0118"; + VC1RXFIFOBASENP : bit_vector := X"0118"; + VC1RXFIFOBASEP : bit_vector := X"0118"; + VC1RXFIFOLIMITC : bit_vector := X"0118"; + VC1RXFIFOLIMITNP : bit_vector := X"0118"; + VC1RXFIFOLIMITP : bit_vector := X"0118"; + VC1TOTALCREDITSCD : bit_vector := X"000"; + VC1TOTALCREDITSCH : bit_vector := X"00"; + VC1TOTALCREDITSNPH : bit_vector := X"00"; + VC1TOTALCREDITSPD : bit_vector := X"000"; + VC1TOTALCREDITSPH : bit_vector := X"00"; + VC1TXFIFOBASEC : bit_vector := X"0118"; + VC1TXFIFOBASENP : bit_vector := X"0118"; + VC1TXFIFOBASEP : bit_vector := X"0118"; + VC1TXFIFOLIMITC : bit_vector := X"0118"; + VC1TXFIFOLIMITNP : bit_vector := X"0118"; + VC1TXFIFOLIMITP : bit_vector := X"0118"; + VCBASEPTR : bit_vector := X"154"; + VCCAPABILITYNEXTPTR : bit_vector := X"000"; + VENDORID : bit_vector := X"10EE"; + XLINKSUPPORTED : boolean := FALSE; + XPBASEPTR : bit_vector := X"60"; + XPDEVICEPORTTYPE : bit_vector := X"0"; + XPMAXPAYLOAD : integer := 0; + XPRCBCONTROL : integer := 0 + + + + + ); + +port ( + BUSMASTERENABLE : out std_ulogic; + CRMDOHOTRESETN : out std_ulogic; + CRMPWRSOFTRESETN : out std_ulogic; + CRMRXHOTRESETN : out std_ulogic; + DLLTXPMDLLPOUTSTANDING : out std_ulogic; + INTERRUPTDISABLE : out std_ulogic; + IOSPACEENABLE : out std_ulogic; + L0ASAUTONOMOUSINITCOMPLETED : out std_ulogic; + L0ATTENTIONINDICATORCONTROL : out std_logic_vector(1 downto 0); + L0CFGLOOPBACKACK : out std_ulogic; + L0COMPLETERID : out std_logic_vector(12 downto 0); + L0CORRERRMSGRCVD : out std_ulogic; + L0DLLASRXSTATE : out std_logic_vector(1 downto 0); + L0DLLASTXSTATE : out std_ulogic; + L0DLLERRORVECTOR : out std_logic_vector(6 downto 0); + L0DLLRXACKOUTSTANDING : out std_ulogic; + L0DLLTXNONFCOUTSTANDING : out std_ulogic; + L0DLLTXOUTSTANDING : out std_ulogic; + L0DLLVCSTATUS : out std_logic_vector(7 downto 0); + L0DLUPDOWN : out std_logic_vector(7 downto 0); + L0ERRMSGREQID : out std_logic_vector(15 downto 0); + L0FATALERRMSGRCVD : out std_ulogic; + L0FIRSTCFGWRITEOCCURRED : out std_ulogic; + L0FWDCORRERROUT : out std_ulogic; + L0FWDFATALERROUT : out std_ulogic; + L0FWDNONFATALERROUT : out std_ulogic; + L0LTSSMSTATE : out std_logic_vector(3 downto 0); + L0MACENTEREDL0 : out std_ulogic; + L0MACLINKTRAINING : out std_ulogic; + L0MACLINKUP : out std_ulogic; + L0MACNEGOTIATEDLINKWIDTH : out std_logic_vector(3 downto 0); + L0MACNEWSTATEACK : out std_ulogic; + L0MACRXL0SSTATE : out std_ulogic; + L0MACUPSTREAMDOWNSTREAM : out std_ulogic; + L0MCFOUND : out std_logic_vector(2 downto 0); + L0MSIENABLE0 : out std_ulogic; + L0MULTIMSGEN0 : out std_logic_vector(2 downto 0); + L0NONFATALERRMSGRCVD : out std_ulogic; + L0PMEACK : out std_ulogic; + L0PMEEN : out std_ulogic; + L0PMEREQOUT : out std_ulogic; + L0POWERCONTROLLERCONTROL : out std_ulogic; + L0POWERINDICATORCONTROL : out std_logic_vector(1 downto 0); + L0PWRINHIBITTRANSFERS : out std_ulogic; + L0PWRL1STATE : out std_ulogic; + L0PWRL23READYDEVICE : out std_ulogic; + L0PWRL23READYSTATE : out std_ulogic; + L0PWRSTATE0 : out std_logic_vector(1 downto 0); + L0PWRTURNOFFREQ : out std_ulogic; + L0PWRTXL0SSTATE : out std_ulogic; + L0RECEIVEDASSERTINTALEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTBLEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTCLEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTDLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTALEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTBLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTCLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTDLEGACYINT : out std_ulogic; + L0RXBEACON : out std_ulogic; + L0RXDLLFCCMPLMCCRED : out std_logic_vector(23 downto 0); + L0RXDLLFCCMPLMCUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLFCNPOSTBYPCRED : out std_logic_vector(19 downto 0); + L0RXDLLFCNPOSTBYPUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLFCPOSTORDCRED : out std_logic_vector(23 downto 0); + L0RXDLLFCPOSTORDUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLPM : out std_ulogic; + L0RXDLLPMTYPE : out std_logic_vector(2 downto 0); + L0RXDLLSBFCDATA : out std_logic_vector(18 downto 0); + L0RXDLLSBFCUPDATE : out std_ulogic; + L0RXDLLTLPECRCOK : out std_ulogic; + L0RXDLLTLPEND : out std_logic_vector(1 downto 0); + L0RXMACLINKERROR : out std_logic_vector(1 downto 0); + L0STATSCFGOTHERRECEIVED : out std_ulogic; + L0STATSCFGOTHERTRANSMITTED : out std_ulogic; + L0STATSCFGRECEIVED : out std_ulogic; + L0STATSCFGTRANSMITTED : out std_ulogic; + L0STATSDLLPRECEIVED : out std_ulogic; + L0STATSDLLPTRANSMITTED : out std_ulogic; + L0STATSOSRECEIVED : out std_ulogic; + L0STATSOSTRANSMITTED : out std_ulogic; + L0STATSTLPRECEIVED : out std_ulogic; + L0STATSTLPTRANSMITTED : out std_ulogic; + L0TOGGLEELECTROMECHANICALINTERLOCK : out std_ulogic; + L0TRANSFORMEDVC : out std_logic_vector(2 downto 0); + L0TXDLLFCCMPLMCUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLFCNPOSTBYPUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLFCPOSTORDUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLPMUPDATED : out std_ulogic; + L0TXDLLSBFCUPDATED : out std_ulogic; + L0UCBYPFOUND : out std_logic_vector(3 downto 0); + L0UCORDFOUND : out std_logic_vector(3 downto 0); + L0UNLOCKRECEIVED : out std_ulogic; + LLKRX4DWHEADERN : out std_ulogic; + LLKRXCHCOMPLETIONAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHCOMPLETIONPARTIALN : out std_logic_vector(7 downto 0); + LLKRXCHCONFIGAVAILABLEN : out std_ulogic; + LLKRXCHCONFIGPARTIALN : out std_ulogic; + LLKRXCHNONPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHNONPOSTEDPARTIALN : out std_logic_vector(7 downto 0); + LLKRXCHPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHPOSTEDPARTIALN : out std_logic_vector(7 downto 0); + LLKRXDATA : out std_logic_vector(63 downto 0); + LLKRXECRCBADN : out std_ulogic; + LLKRXEOFN : out std_ulogic; + LLKRXEOPN : out std_ulogic; + LLKRXPREFERREDTYPE : out std_logic_vector(15 downto 0); + LLKRXSOFN : out std_ulogic; + LLKRXSOPN : out std_ulogic; + LLKRXSRCDSCN : out std_ulogic; + LLKRXSRCLASTREQN : out std_ulogic; + LLKRXSRCRDYN : out std_ulogic; + LLKRXVALIDN : out std_logic_vector(1 downto 0); + LLKTCSTATUS : out std_logic_vector(7 downto 0); + LLKTXCHANSPACE : out std_logic_vector(9 downto 0); + LLKTXCHCOMPLETIONREADYN : out std_logic_vector(7 downto 0); + LLKTXCHNONPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCHPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCONFIGREADYN : out std_ulogic; + LLKTXDSTRDYN : out std_ulogic; + MAXPAYLOADSIZE : out std_logic_vector(2 downto 0); + MAXREADREQUESTSIZE : out std_logic_vector(2 downto 0); + MEMSPACEENABLE : out std_ulogic; + MGMTPSO : out std_logic_vector(16 downto 0); + MGMTRDATA : out std_logic_vector(31 downto 0); + MGMTSTATSCREDIT : out std_logic_vector(11 downto 0); + MIMDLLBRADD : out std_logic_vector(11 downto 0); + MIMDLLBREN : out std_ulogic; + MIMDLLBWADD : out std_logic_vector(11 downto 0); + MIMDLLBWDATA : out std_logic_vector(63 downto 0); + MIMDLLBWEN : out std_ulogic; + MIMRXBRADD : out std_logic_vector(12 downto 0); + MIMRXBREN : out std_ulogic; + MIMRXBWADD : out std_logic_vector(12 downto 0); + MIMRXBWDATA : out std_logic_vector(63 downto 0); + MIMRXBWEN : out std_ulogic; + MIMTXBRADD : out std_logic_vector(12 downto 0); + MIMTXBREN : out std_ulogic; + MIMTXBWADD : out std_logic_vector(12 downto 0); + MIMTXBWDATA : out std_logic_vector(63 downto 0); + MIMTXBWEN : out std_ulogic; + PARITYERRORRESPONSE : out std_ulogic; + PIPEDESKEWLANESL0 : out std_ulogic; + PIPEDESKEWLANESL1 : out std_ulogic; + PIPEDESKEWLANESL2 : out std_ulogic; + PIPEDESKEWLANESL3 : out std_ulogic; + PIPEDESKEWLANESL4 : out std_ulogic; + PIPEDESKEWLANESL5 : out std_ulogic; + PIPEDESKEWLANESL6 : out std_ulogic; + PIPEDESKEWLANESL7 : out std_ulogic; + PIPEPOWERDOWNL0 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL1 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL2 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL3 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL4 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL5 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL6 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL7 : out std_logic_vector(1 downto 0); + PIPERESETL0 : out std_ulogic; + PIPERESETL1 : out std_ulogic; + PIPERESETL2 : out std_ulogic; + PIPERESETL3 : out std_ulogic; + PIPERESETL4 : out std_ulogic; + PIPERESETL5 : out std_ulogic; + PIPERESETL6 : out std_ulogic; + PIPERESETL7 : out std_ulogic; + PIPERXPOLARITYL0 : out std_ulogic; + PIPERXPOLARITYL1 : out std_ulogic; + PIPERXPOLARITYL2 : out std_ulogic; + PIPERXPOLARITYL3 : out std_ulogic; + PIPERXPOLARITYL4 : out std_ulogic; + PIPERXPOLARITYL5 : out std_ulogic; + PIPERXPOLARITYL6 : out std_ulogic; + PIPERXPOLARITYL7 : out std_ulogic; + PIPETXCOMPLIANCEL0 : out std_ulogic; + PIPETXCOMPLIANCEL1 : out std_ulogic; + PIPETXCOMPLIANCEL2 : out std_ulogic; + PIPETXCOMPLIANCEL3 : out std_ulogic; + PIPETXCOMPLIANCEL4 : out std_ulogic; + PIPETXCOMPLIANCEL5 : out std_ulogic; + PIPETXCOMPLIANCEL6 : out std_ulogic; + PIPETXCOMPLIANCEL7 : out std_ulogic; + PIPETXDATAKL0 : out std_ulogic; + PIPETXDATAKL1 : out std_ulogic; + PIPETXDATAKL2 : out std_ulogic; + PIPETXDATAKL3 : out std_ulogic; + PIPETXDATAKL4 : out std_ulogic; + PIPETXDATAKL5 : out std_ulogic; + PIPETXDATAKL6 : out std_ulogic; + PIPETXDATAKL7 : out std_ulogic; + PIPETXDATAL0 : out std_logic_vector(7 downto 0); + PIPETXDATAL1 : out std_logic_vector(7 downto 0); + PIPETXDATAL2 : out std_logic_vector(7 downto 0); + PIPETXDATAL3 : out std_logic_vector(7 downto 0); + PIPETXDATAL4 : out std_logic_vector(7 downto 0); + PIPETXDATAL5 : out std_logic_vector(7 downto 0); + PIPETXDATAL6 : out std_logic_vector(7 downto 0); + PIPETXDATAL7 : out std_logic_vector(7 downto 0); + PIPETXDETECTRXLOOPBACKL0 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL1 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL2 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL3 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL4 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL5 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL6 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL7 : out std_ulogic; + PIPETXELECIDLEL0 : out std_ulogic; + PIPETXELECIDLEL1 : out std_ulogic; + PIPETXELECIDLEL2 : out std_ulogic; + PIPETXELECIDLEL3 : out std_ulogic; + PIPETXELECIDLEL4 : out std_ulogic; + PIPETXELECIDLEL5 : out std_ulogic; + PIPETXELECIDLEL6 : out std_ulogic; + PIPETXELECIDLEL7 : out std_ulogic; + SERRENABLE : out std_ulogic; + URREPORTINGENABLE : out std_ulogic; + + AUXPOWER : in std_ulogic; + CFGNEGOTIATEDLINKWIDTH : in std_logic_vector(5 downto 0); + COMPLIANCEAVOID : in std_ulogic; + CRMCFGBRIDGEHOTRESET : in std_ulogic; + CRMCORECLK : in std_ulogic; + CRMCORECLKDLO : in std_ulogic; + CRMCORECLKRXO : in std_ulogic; + CRMCORECLKTXO : in std_ulogic; + CRMLINKRSTN : in std_ulogic; + CRMMACRSTN : in std_ulogic; + CRMMGMTRSTN : in std_ulogic; + CRMNVRSTN : in std_ulogic; + CRMTXHOTRESETN : in std_ulogic; + CRMURSTN : in std_ulogic; + CRMUSERCFGRSTN : in std_ulogic; + CRMUSERCLK : in std_ulogic; + CRMUSERCLKRXO : in std_ulogic; + CRMUSERCLKTXO : in std_ulogic; + CROSSLINKSEED : in std_ulogic; + L0ACKNAKTIMERADJUSTMENT : in std_logic_vector(11 downto 0); + L0ALLDOWNPORTSINL1 : in std_ulogic; + L0ALLDOWNRXPORTSINL0S : in std_ulogic; + L0ASE : in std_ulogic; + L0ASPORTCOUNT : in std_logic_vector(7 downto 0); + L0ASTURNPOOLBITSCONSUMED : in std_logic_vector(2 downto 0); + L0ATTENTIONBUTTONPRESSED : in std_ulogic; + L0CFGASSPANTREEOWNEDSTATE : in std_ulogic; + L0CFGASSTATECHANGECMD : in std_logic_vector(3 downto 0); + L0CFGDISABLESCRAMBLE : in std_ulogic; + L0CFGEXTENDEDSYNC : in std_ulogic; + L0CFGL0SENTRYENABLE : in std_ulogic; + L0CFGL0SENTRYSUP : in std_ulogic; + L0CFGL0SEXITLAT : in std_logic_vector(2 downto 0); + L0CFGLINKDISABLE : in std_ulogic; + L0CFGLOOPBACKMASTER : in std_ulogic; + L0CFGNEGOTIATEDMAXP : in std_logic_vector(2 downto 0); + L0CFGVCENABLE : in std_logic_vector(7 downto 0); + L0CFGVCID : in std_logic_vector(23 downto 0); + L0DLLHOLDLINKUP : in std_ulogic; + L0ELECTROMECHANICALINTERLOCKENGAGED : in std_ulogic; + L0FWDASSERTINTALEGACYINT : in std_ulogic; + L0FWDASSERTINTBLEGACYINT : in std_ulogic; + L0FWDASSERTINTCLEGACYINT : in std_ulogic; + L0FWDASSERTINTDLEGACYINT : in std_ulogic; + L0FWDCORRERRIN : in std_ulogic; + L0FWDDEASSERTINTALEGACYINT : in std_ulogic; + L0FWDDEASSERTINTBLEGACYINT : in std_ulogic; + L0FWDDEASSERTINTCLEGACYINT : in std_ulogic; + L0FWDDEASSERTINTDLEGACYINT : in std_ulogic; + L0FWDFATALERRIN : in std_ulogic; + L0FWDNONFATALERRIN : in std_ulogic; + L0LEGACYINTFUNCT0 : in std_ulogic; + L0MRLSENSORCLOSEDN : in std_ulogic; + L0MSIREQUEST0 : in std_logic_vector(3 downto 0); + L0PACKETHEADERFROMUSER : in std_logic_vector(127 downto 0); + L0PMEREQIN : in std_ulogic; + L0PORTNUMBER : in std_logic_vector(7 downto 0); + L0POWERFAULTDETECTED : in std_ulogic; + L0PRESENCEDETECTSLOTEMPTYN : in std_ulogic; + L0PWRNEWSTATEREQ : in std_ulogic; + L0PWRNEXTLINKSTATE : in std_logic_vector(1 downto 0); + L0REPLAYTIMERADJUSTMENT : in std_logic_vector(11 downto 0); + L0ROOTTURNOFFREQ : in std_ulogic; + L0RXTLTLPNONINITIALIZEDVC : in std_logic_vector(7 downto 0); + L0SENDUNLOCKMESSAGE : in std_ulogic; + L0SETCOMPLETERABORTERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTCORRERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTUNCORRERROR : in std_ulogic; + L0SETDETECTEDCORRERROR : in std_ulogic; + L0SETDETECTEDFATALERROR : in std_ulogic; + L0SETDETECTEDNONFATALERROR : in std_ulogic; + L0SETLINKDETECTEDPARITYERROR : in std_ulogic; + L0SETLINKMASTERDATAPARITY : in std_ulogic; + L0SETLINKRECEIVEDMASTERABORT : in std_ulogic; + L0SETLINKRECEIVEDTARGETABORT : in std_ulogic; + L0SETLINKSIGNALLEDTARGETABORT : in std_ulogic; + L0SETLINKSYSTEMERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONCORRERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTOTHERERROR : in std_ulogic; + L0SETUSERDETECTEDPARITYERROR : in std_ulogic; + L0SETUSERMASTERDATAPARITY : in std_ulogic; + L0SETUSERRECEIVEDMASTERABORT : in std_ulogic; + L0SETUSERRECEIVEDTARGETABORT : in std_ulogic; + L0SETUSERSIGNALLEDTARGETABORT : in std_ulogic; + L0SETUSERSYSTEMERROR : in std_ulogic; + L0TLASFCCREDSTARVATION : in std_ulogic; + L0TLLINKRETRAIN : in std_ulogic; + L0TRANSACTIONSPENDING : in std_ulogic; + L0TXBEACON : in std_ulogic; + L0TXCFGPM : in std_ulogic; + L0TXCFGPMTYPE : in std_logic_vector(2 downto 0); + L0TXTLFCCMPLMCCRED : in std_logic_vector(159 downto 0); + L0TXTLFCCMPLMCUPDATE : in std_logic_vector(15 downto 0); + L0TXTLFCNPOSTBYPCRED : in std_logic_vector(191 downto 0); + L0TXTLFCNPOSTBYPUPDATE : in std_logic_vector(15 downto 0); + L0TXTLFCPOSTORDCRED : in std_logic_vector(159 downto 0); + L0TXTLFCPOSTORDUPDATE : in std_logic_vector(15 downto 0); + L0TXTLSBFCDATA : in std_logic_vector(18 downto 0); + L0TXTLSBFCUPDATE : in std_ulogic; + L0TXTLTLPDATA : in std_logic_vector(63 downto 0); + L0TXTLTLPEDB : in std_ulogic; + L0TXTLTLPENABLE : in std_logic_vector(1 downto 0); + L0TXTLTLPEND : in std_logic_vector(1 downto 0); + L0TXTLTLPLATENCY : in std_logic_vector(3 downto 0); + L0TXTLTLPREQ : in std_ulogic; + L0TXTLTLPREQEND : in std_ulogic; + L0TXTLTLPWIDTH : in std_ulogic; + L0UPSTREAMRXPORTINL0S : in std_ulogic; + L0VC0PREVIEWEXPAND : in std_ulogic; + L0WAKEN : in std_ulogic; + LLKRXCHFIFO : in std_logic_vector(1 downto 0); + LLKRXCHTC : in std_logic_vector(2 downto 0); + LLKRXDSTCONTREQN : in std_ulogic; + LLKRXDSTREQN : in std_ulogic; + LLKTX4DWHEADERN : in std_ulogic; + LLKTXCHFIFO : in std_logic_vector(1 downto 0); + LLKTXCHTC : in std_logic_vector(2 downto 0); + LLKTXCOMPLETEN : in std_ulogic; + LLKTXCREATEECRCN : in std_ulogic; + LLKTXDATA : in std_logic_vector(63 downto 0); + LLKTXENABLEN : in std_logic_vector(1 downto 0); + LLKTXEOFN : in std_ulogic; + LLKTXEOPN : in std_ulogic; + LLKTXSOFN : in std_ulogic; + LLKTXSOPN : in std_ulogic; + LLKTXSRCDSCN : in std_ulogic; + LLKTXSRCRDYN : in std_ulogic; + MAINPOWER : in std_ulogic; + MGMTADDR : in std_logic_vector(10 downto 0); + MGMTBWREN : in std_logic_vector(3 downto 0); + MGMTRDEN : in std_ulogic; + MGMTSTATSCREDITSEL : in std_logic_vector(6 downto 0); + MGMTWDATA : in std_logic_vector(31 downto 0); + MGMTWREN : in std_ulogic; + MIMDLLBRDATA : in std_logic_vector(63 downto 0); + MIMRXBRDATA : in std_logic_vector(63 downto 0); + MIMTXBRDATA : in std_logic_vector(63 downto 0); + PIPEPHYSTATUSL0 : in std_ulogic; + PIPEPHYSTATUSL1 : in std_ulogic; + PIPEPHYSTATUSL2 : in std_ulogic; + PIPEPHYSTATUSL3 : in std_ulogic; + PIPEPHYSTATUSL4 : in std_ulogic; + PIPEPHYSTATUSL5 : in std_ulogic; + PIPEPHYSTATUSL6 : in std_ulogic; + PIPEPHYSTATUSL7 : in std_ulogic; + PIPERXCHANISALIGNEDL0 : in std_ulogic; + PIPERXCHANISALIGNEDL1 : in std_ulogic; + PIPERXCHANISALIGNEDL2 : in std_ulogic; + PIPERXCHANISALIGNEDL3 : in std_ulogic; + PIPERXCHANISALIGNEDL4 : in std_ulogic; + PIPERXCHANISALIGNEDL5 : in std_ulogic; + PIPERXCHANISALIGNEDL6 : in std_ulogic; + PIPERXCHANISALIGNEDL7 : in std_ulogic; + PIPERXDATAKL0 : in std_ulogic; + PIPERXDATAKL1 : in std_ulogic; + PIPERXDATAKL2 : in std_ulogic; + PIPERXDATAKL3 : in std_ulogic; + PIPERXDATAKL4 : in std_ulogic; + PIPERXDATAKL5 : in std_ulogic; + PIPERXDATAKL6 : in std_ulogic; + PIPERXDATAKL7 : in std_ulogic; + PIPERXDATAL0 : in std_logic_vector(7 downto 0); + PIPERXDATAL1 : in std_logic_vector(7 downto 0); + PIPERXDATAL2 : in std_logic_vector(7 downto 0); + PIPERXDATAL3 : in std_logic_vector(7 downto 0); + PIPERXDATAL4 : in std_logic_vector(7 downto 0); + PIPERXDATAL5 : in std_logic_vector(7 downto 0); + PIPERXDATAL6 : in std_logic_vector(7 downto 0); + PIPERXDATAL7 : in std_logic_vector(7 downto 0); + PIPERXELECIDLEL0 : in std_ulogic; + PIPERXELECIDLEL1 : in std_ulogic; + PIPERXELECIDLEL2 : in std_ulogic; + PIPERXELECIDLEL3 : in std_ulogic; + PIPERXELECIDLEL4 : in std_ulogic; + PIPERXELECIDLEL5 : in std_ulogic; + PIPERXELECIDLEL6 : in std_ulogic; + PIPERXELECIDLEL7 : in std_ulogic; + PIPERXSTATUSL0 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL1 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL2 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL3 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL4 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL5 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL6 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL7 : in std_logic_vector(2 downto 0); + PIPERXVALIDL0 : in std_ulogic; + PIPERXVALIDL1 : in std_ulogic; + PIPERXVALIDL2 : in std_ulogic; + PIPERXVALIDL3 : in std_ulogic; + PIPERXVALIDL4 : in std_ulogic; + PIPERXVALIDL5 : in std_ulogic; + PIPERXVALIDL6 : in std_ulogic; + PIPERXVALIDL7 : in std_ulogic + ); +end PCIE_INTERNAL_1_1; + +architecture PCIE_INTERNAL_1_1_V of PCIE_INTERNAL_1_1 is + + component PCIE_INTERNAL_1_1_SWIFT + port ( + BUSMASTERENABLE : out std_ulogic; + CRMDOHOTRESETN : out std_ulogic; + CRMPWRSOFTRESETN : out std_ulogic; + CRMRXHOTRESETN : out std_ulogic; + DLLTXPMDLLPOUTSTANDING : out std_ulogic; + INTERRUPTDISABLE : out std_ulogic; + IOSPACEENABLE : out std_ulogic; + L0ASAUTONOMOUSINITCOMPLETED : out std_ulogic; + L0ATTENTIONINDICATORCONTROL : out std_logic_vector(1 downto 0); + L0CFGLOOPBACKACK : out std_ulogic; + L0COMPLETERID : out std_logic_vector(12 downto 0); + L0CORRERRMSGRCVD : out std_ulogic; + L0DLLASRXSTATE : out std_logic_vector(1 downto 0); + L0DLLASTXSTATE : out std_ulogic; + L0DLLERRORVECTOR : out std_logic_vector(6 downto 0); + L0DLLRXACKOUTSTANDING : out std_ulogic; + L0DLLTXNONFCOUTSTANDING : out std_ulogic; + L0DLLTXOUTSTANDING : out std_ulogic; + L0DLLVCSTATUS : out std_logic_vector(7 downto 0); + L0DLUPDOWN : out std_logic_vector(7 downto 0); + L0ERRMSGREQID : out std_logic_vector(15 downto 0); + L0FATALERRMSGRCVD : out std_ulogic; + L0FIRSTCFGWRITEOCCURRED : out std_ulogic; + L0FWDCORRERROUT : out std_ulogic; + L0FWDFATALERROUT : out std_ulogic; + L0FWDNONFATALERROUT : out std_ulogic; + L0LTSSMSTATE : out std_logic_vector(3 downto 0); + L0MACENTEREDL0 : out std_ulogic; + L0MACLINKTRAINING : out std_ulogic; + L0MACLINKUP : out std_ulogic; + L0MACNEGOTIATEDLINKWIDTH : out std_logic_vector(3 downto 0); + L0MACNEWSTATEACK : out std_ulogic; + L0MACRXL0SSTATE : out std_ulogic; + L0MACUPSTREAMDOWNSTREAM : out std_ulogic; + L0MCFOUND : out std_logic_vector(2 downto 0); + L0MSIENABLE0 : out std_ulogic; + L0MULTIMSGEN0 : out std_logic_vector(2 downto 0); + L0NONFATALERRMSGRCVD : out std_ulogic; + L0PMEACK : out std_ulogic; + L0PMEEN : out std_ulogic; + L0PMEREQOUT : out std_ulogic; + L0POWERCONTROLLERCONTROL : out std_ulogic; + L0POWERINDICATORCONTROL : out std_logic_vector(1 downto 0); + L0PWRINHIBITTRANSFERS : out std_ulogic; + L0PWRL1STATE : out std_ulogic; + L0PWRL23READYDEVICE : out std_ulogic; + L0PWRL23READYSTATE : out std_ulogic; + L0PWRSTATE0 : out std_logic_vector(1 downto 0); + L0PWRTURNOFFREQ : out std_ulogic; + L0PWRTXL0SSTATE : out std_ulogic; + L0RECEIVEDASSERTINTALEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTBLEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTCLEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTDLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTALEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTBLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTCLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTDLEGACYINT : out std_ulogic; + L0RXBEACON : out std_ulogic; + L0RXDLLFCCMPLMCCRED : out std_logic_vector(23 downto 0); + L0RXDLLFCCMPLMCUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLFCNPOSTBYPCRED : out std_logic_vector(19 downto 0); + L0RXDLLFCNPOSTBYPUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLFCPOSTORDCRED : out std_logic_vector(23 downto 0); + L0RXDLLFCPOSTORDUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLPM : out std_ulogic; + L0RXDLLPMTYPE : out std_logic_vector(2 downto 0); + L0RXDLLSBFCDATA : out std_logic_vector(18 downto 0); + L0RXDLLSBFCUPDATE : out std_ulogic; + L0RXDLLTLPECRCOK : out std_ulogic; + L0RXDLLTLPEND : out std_logic_vector(1 downto 0); + L0RXMACLINKERROR : out std_logic_vector(1 downto 0); + L0STATSCFGOTHERRECEIVED : out std_ulogic; + L0STATSCFGOTHERTRANSMITTED : out std_ulogic; + L0STATSCFGRECEIVED : out std_ulogic; + L0STATSCFGTRANSMITTED : out std_ulogic; + L0STATSDLLPRECEIVED : out std_ulogic; + L0STATSDLLPTRANSMITTED : out std_ulogic; + L0STATSOSRECEIVED : out std_ulogic; + L0STATSOSTRANSMITTED : out std_ulogic; + L0STATSTLPRECEIVED : out std_ulogic; + L0STATSTLPTRANSMITTED : out std_ulogic; + L0TOGGLEELECTROMECHANICALINTERLOCK : out std_ulogic; + L0TRANSFORMEDVC : out std_logic_vector(2 downto 0); + L0TXDLLFCCMPLMCUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLFCNPOSTBYPUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLFCPOSTORDUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLPMUPDATED : out std_ulogic; + L0TXDLLSBFCUPDATED : out std_ulogic; + L0UCBYPFOUND : out std_logic_vector(3 downto 0); + L0UCORDFOUND : out std_logic_vector(3 downto 0); + L0UNLOCKRECEIVED : out std_ulogic; + LLKRX4DWHEADERN : out std_ulogic; + LLKRXCHCOMPLETIONAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHCOMPLETIONPARTIALN : out std_logic_vector(7 downto 0); + LLKRXCHCONFIGAVAILABLEN : out std_ulogic; + LLKRXCHCONFIGPARTIALN : out std_ulogic; + LLKRXCHNONPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHNONPOSTEDPARTIALN : out std_logic_vector(7 downto 0); + LLKRXCHPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHPOSTEDPARTIALN : out std_logic_vector(7 downto 0); + LLKRXDATA : out std_logic_vector(63 downto 0); + LLKRXECRCBADN : out std_ulogic; + LLKRXEOFN : out std_ulogic; + LLKRXEOPN : out std_ulogic; + LLKRXPREFERREDTYPE : out std_logic_vector(15 downto 0); + LLKRXSOFN : out std_ulogic; + LLKRXSOPN : out std_ulogic; + LLKRXSRCDSCN : out std_ulogic; + LLKRXSRCLASTREQN : out std_ulogic; + LLKRXSRCRDYN : out std_ulogic; + LLKRXVALIDN : out std_logic_vector(1 downto 0); + LLKTCSTATUS : out std_logic_vector(7 downto 0); + LLKTXCHANSPACE : out std_logic_vector(9 downto 0); + LLKTXCHCOMPLETIONREADYN : out std_logic_vector(7 downto 0); + LLKTXCHNONPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCHPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCONFIGREADYN : out std_ulogic; + LLKTXDSTRDYN : out std_ulogic; + MAXPAYLOADSIZE : out std_logic_vector(2 downto 0); + MAXREADREQUESTSIZE : out std_logic_vector(2 downto 0); + MEMSPACEENABLE : out std_ulogic; + MGMTPSO : out std_logic_vector(16 downto 0); + MGMTRDATA : out std_logic_vector(31 downto 0); + MGMTSTATSCREDIT : out std_logic_vector(11 downto 0); + MIMDLLBRADD : out std_logic_vector(11 downto 0); + MIMDLLBREN : out std_ulogic; + MIMDLLBWADD : out std_logic_vector(11 downto 0); + MIMDLLBWDATA : out std_logic_vector(63 downto 0); + MIMDLLBWEN : out std_ulogic; + MIMRXBRADD : out std_logic_vector(12 downto 0); + MIMRXBREN : out std_ulogic; + MIMRXBWADD : out std_logic_vector(12 downto 0); + MIMRXBWDATA : out std_logic_vector(63 downto 0); + MIMRXBWEN : out std_ulogic; + MIMTXBRADD : out std_logic_vector(12 downto 0); + MIMTXBREN : out std_ulogic; + MIMTXBWADD : out std_logic_vector(12 downto 0); + MIMTXBWDATA : out std_logic_vector(63 downto 0); + MIMTXBWEN : out std_ulogic; + PARITYERRORRESPONSE : out std_ulogic; + PIPEDESKEWLANESL0 : out std_ulogic; + PIPEDESKEWLANESL1 : out std_ulogic; + PIPEDESKEWLANESL2 : out std_ulogic; + PIPEDESKEWLANESL3 : out std_ulogic; + PIPEDESKEWLANESL4 : out std_ulogic; + PIPEDESKEWLANESL5 : out std_ulogic; + PIPEDESKEWLANESL6 : out std_ulogic; + PIPEDESKEWLANESL7 : out std_ulogic; + PIPEPOWERDOWNL0 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL1 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL2 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL3 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL4 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL5 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL6 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL7 : out std_logic_vector(1 downto 0); + PIPERESETL0 : out std_ulogic; + PIPERESETL1 : out std_ulogic; + PIPERESETL2 : out std_ulogic; + PIPERESETL3 : out std_ulogic; + PIPERESETL4 : out std_ulogic; + PIPERESETL5 : out std_ulogic; + PIPERESETL6 : out std_ulogic; + PIPERESETL7 : out std_ulogic; + PIPERXPOLARITYL0 : out std_ulogic; + PIPERXPOLARITYL1 : out std_ulogic; + PIPERXPOLARITYL2 : out std_ulogic; + PIPERXPOLARITYL3 : out std_ulogic; + PIPERXPOLARITYL4 : out std_ulogic; + PIPERXPOLARITYL5 : out std_ulogic; + PIPERXPOLARITYL6 : out std_ulogic; + PIPERXPOLARITYL7 : out std_ulogic; + PIPETXCOMPLIANCEL0 : out std_ulogic; + PIPETXCOMPLIANCEL1 : out std_ulogic; + PIPETXCOMPLIANCEL2 : out std_ulogic; + PIPETXCOMPLIANCEL3 : out std_ulogic; + PIPETXCOMPLIANCEL4 : out std_ulogic; + PIPETXCOMPLIANCEL5 : out std_ulogic; + PIPETXCOMPLIANCEL6 : out std_ulogic; + PIPETXCOMPLIANCEL7 : out std_ulogic; + PIPETXDATAKL0 : out std_ulogic; + PIPETXDATAKL1 : out std_ulogic; + PIPETXDATAKL2 : out std_ulogic; + PIPETXDATAKL3 : out std_ulogic; + PIPETXDATAKL4 : out std_ulogic; + PIPETXDATAKL5 : out std_ulogic; + PIPETXDATAKL6 : out std_ulogic; + PIPETXDATAKL7 : out std_ulogic; + PIPETXDATAL0 : out std_logic_vector(7 downto 0); + PIPETXDATAL1 : out std_logic_vector(7 downto 0); + PIPETXDATAL2 : out std_logic_vector(7 downto 0); + PIPETXDATAL3 : out std_logic_vector(7 downto 0); + PIPETXDATAL4 : out std_logic_vector(7 downto 0); + PIPETXDATAL5 : out std_logic_vector(7 downto 0); + PIPETXDATAL6 : out std_logic_vector(7 downto 0); + PIPETXDATAL7 : out std_logic_vector(7 downto 0); + PIPETXDETECTRXLOOPBACKL0 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL1 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL2 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL3 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL4 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL5 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL6 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL7 : out std_ulogic; + PIPETXELECIDLEL0 : out std_ulogic; + PIPETXELECIDLEL1 : out std_ulogic; + PIPETXELECIDLEL2 : out std_ulogic; + PIPETXELECIDLEL3 : out std_ulogic; + PIPETXELECIDLEL4 : out std_ulogic; + PIPETXELECIDLEL5 : out std_ulogic; + PIPETXELECIDLEL6 : out std_ulogic; + PIPETXELECIDLEL7 : out std_ulogic; + SERRENABLE : out std_ulogic; + URREPORTINGENABLE : out std_ulogic; + + AUXPOWER : in std_ulogic; + CFGNEGOTIATEDLINKWIDTH : in std_logic_vector(5 downto 0); + COMPLIANCEAVOID : in std_ulogic; + CRMCFGBRIDGEHOTRESET : in std_ulogic; + CRMCORECLK : in std_ulogic; + CRMCORECLKDLO : in std_ulogic; + CRMCORECLKRXO : in std_ulogic; + CRMCORECLKTXO : in std_ulogic; + CRMLINKRSTN : in std_ulogic; + CRMMACRSTN : in std_ulogic; + CRMMGMTRSTN : in std_ulogic; + CRMNVRSTN : in std_ulogic; + CRMTXHOTRESETN : in std_ulogic; + CRMURSTN : in std_ulogic; + CRMUSERCFGRSTN : in std_ulogic; + CRMUSERCLK : in std_ulogic; + CRMUSERCLKRXO : in std_ulogic; + CRMUSERCLKTXO : in std_ulogic; + CROSSLINKSEED : in std_ulogic; + GSR : in std_ulogic; + L0ACKNAKTIMERADJUSTMENT : in std_logic_vector(11 downto 0); + L0ALLDOWNPORTSINL1 : in std_ulogic; + L0ALLDOWNRXPORTSINL0S : in std_ulogic; + L0ASE : in std_ulogic; + L0ASPORTCOUNT : in std_logic_vector(7 downto 0); + L0ASTURNPOOLBITSCONSUMED : in std_logic_vector(2 downto 0); + L0ATTENTIONBUTTONPRESSED : in std_ulogic; + L0CFGASSPANTREEOWNEDSTATE : in std_ulogic; + L0CFGASSTATECHANGECMD : in std_logic_vector(3 downto 0); + L0CFGDISABLESCRAMBLE : in std_ulogic; + L0CFGEXTENDEDSYNC : in std_ulogic; + L0CFGL0SENTRYENABLE : in std_ulogic; + L0CFGL0SENTRYSUP : in std_ulogic; + L0CFGL0SEXITLAT : in std_logic_vector(2 downto 0); + L0CFGLINKDISABLE : in std_ulogic; + L0CFGLOOPBACKMASTER : in std_ulogic; + L0CFGNEGOTIATEDMAXP : in std_logic_vector(2 downto 0); + L0CFGVCENABLE : in std_logic_vector(7 downto 0); + L0CFGVCID : in std_logic_vector(23 downto 0); + L0DLLHOLDLINKUP : in std_ulogic; + L0ELECTROMECHANICALINTERLOCKENGAGED : in std_ulogic; + L0FWDASSERTINTALEGACYINT : in std_ulogic; + L0FWDASSERTINTBLEGACYINT : in std_ulogic; + L0FWDASSERTINTCLEGACYINT : in std_ulogic; + L0FWDASSERTINTDLEGACYINT : in std_ulogic; + L0FWDCORRERRIN : in std_ulogic; + L0FWDDEASSERTINTALEGACYINT : in std_ulogic; + L0FWDDEASSERTINTBLEGACYINT : in std_ulogic; + L0FWDDEASSERTINTCLEGACYINT : in std_ulogic; + L0FWDDEASSERTINTDLEGACYINT : in std_ulogic; + L0FWDFATALERRIN : in std_ulogic; + L0FWDNONFATALERRIN : in std_ulogic; + L0LEGACYINTFUNCT0 : in std_ulogic; + L0MRLSENSORCLOSEDN : in std_ulogic; + L0MSIREQUEST0 : in std_logic_vector(3 downto 0); + L0PACKETHEADERFROMUSER : in std_logic_vector(127 downto 0); + L0PMEREQIN : in std_ulogic; + L0PORTNUMBER : in std_logic_vector(7 downto 0); + L0POWERFAULTDETECTED : in std_ulogic; + L0PRESENCEDETECTSLOTEMPTYN : in std_ulogic; + L0PWRNEWSTATEREQ : in std_ulogic; + L0PWRNEXTLINKSTATE : in std_logic_vector(1 downto 0); + L0REPLAYTIMERADJUSTMENT : in std_logic_vector(11 downto 0); + L0ROOTTURNOFFREQ : in std_ulogic; + L0RXTLTLPNONINITIALIZEDVC : in std_logic_vector(7 downto 0); + L0SENDUNLOCKMESSAGE : in std_ulogic; + L0SETCOMPLETERABORTERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTCORRERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTUNCORRERROR : in std_ulogic; + L0SETDETECTEDCORRERROR : in std_ulogic; + L0SETDETECTEDFATALERROR : in std_ulogic; + L0SETDETECTEDNONFATALERROR : in std_ulogic; + L0SETLINKDETECTEDPARITYERROR : in std_ulogic; + L0SETLINKMASTERDATAPARITY : in std_ulogic; + L0SETLINKRECEIVEDMASTERABORT : in std_ulogic; + L0SETLINKRECEIVEDTARGETABORT : in std_ulogic; + L0SETLINKSIGNALLEDTARGETABORT : in std_ulogic; + L0SETLINKSYSTEMERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONCORRERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTOTHERERROR : in std_ulogic; + L0SETUSERDETECTEDPARITYERROR : in std_ulogic; + L0SETUSERMASTERDATAPARITY : in std_ulogic; + L0SETUSERRECEIVEDMASTERABORT : in std_ulogic; + L0SETUSERRECEIVEDTARGETABORT : in std_ulogic; + L0SETUSERSIGNALLEDTARGETABORT : in std_ulogic; + L0SETUSERSYSTEMERROR : in std_ulogic; + L0TLASFCCREDSTARVATION : in std_ulogic; + L0TLLINKRETRAIN : in std_ulogic; + L0TRANSACTIONSPENDING : in std_ulogic; + L0TXBEACON : in std_ulogic; + L0TXCFGPM : in std_ulogic; + L0TXCFGPMTYPE : in std_logic_vector(2 downto 0); + L0TXTLFCCMPLMCCRED : in std_logic_vector(159 downto 0); + L0TXTLFCCMPLMCUPDATE : in std_logic_vector(15 downto 0); + L0TXTLFCNPOSTBYPCRED : in std_logic_vector(191 downto 0); + L0TXTLFCNPOSTBYPUPDATE : in std_logic_vector(15 downto 0); + L0TXTLFCPOSTORDCRED : in std_logic_vector(159 downto 0); + L0TXTLFCPOSTORDUPDATE : in std_logic_vector(15 downto 0); + L0TXTLSBFCDATA : in std_logic_vector(18 downto 0); + L0TXTLSBFCUPDATE : in std_ulogic; + L0TXTLTLPDATA : in std_logic_vector(63 downto 0); + L0TXTLTLPEDB : in std_ulogic; + L0TXTLTLPENABLE : in std_logic_vector(1 downto 0); + L0TXTLTLPEND : in std_logic_vector(1 downto 0); + L0TXTLTLPLATENCY : in std_logic_vector(3 downto 0); + L0TXTLTLPREQ : in std_ulogic; + L0TXTLTLPREQEND : in std_ulogic; + L0TXTLTLPWIDTH : in std_ulogic; + L0UPSTREAMRXPORTINL0S : in std_ulogic; + L0VC0PREVIEWEXPAND : in std_ulogic; + L0WAKEN : in std_ulogic; + LLKRXCHFIFO : in std_logic_vector(1 downto 0); + LLKRXCHTC : in std_logic_vector(2 downto 0); + LLKRXDSTCONTREQN : in std_ulogic; + LLKRXDSTREQN : in std_ulogic; + LLKTX4DWHEADERN : in std_ulogic; + LLKTXCHFIFO : in std_logic_vector(1 downto 0); + LLKTXCHTC : in std_logic_vector(2 downto 0); + LLKTXCOMPLETEN : in std_ulogic; + LLKTXCREATEECRCN : in std_ulogic; + LLKTXDATA : in std_logic_vector(63 downto 0); + LLKTXENABLEN : in std_logic_vector(1 downto 0); + LLKTXEOFN : in std_ulogic; + LLKTXEOPN : in std_ulogic; + LLKTXSOFN : in std_ulogic; + LLKTXSOPN : in std_ulogic; + LLKTXSRCDSCN : in std_ulogic; + LLKTXSRCRDYN : in std_ulogic; + MAINPOWER : in std_ulogic; + MGMTADDR : in std_logic_vector(10 downto 0); + MGMTBWREN : in std_logic_vector(3 downto 0); + MGMTRDEN : in std_ulogic; + MGMTSTATSCREDITSEL : in std_logic_vector(6 downto 0); + MGMTWDATA : in std_logic_vector(31 downto 0); + MGMTWREN : in std_ulogic; + MIMDLLBRDATA : in std_logic_vector(63 downto 0); + MIMRXBRDATA : in std_logic_vector(63 downto 0); + MIMTXBRDATA : in std_logic_vector(63 downto 0); + PIPEPHYSTATUSL0 : in std_ulogic; + PIPEPHYSTATUSL1 : in std_ulogic; + PIPEPHYSTATUSL2 : in std_ulogic; + PIPEPHYSTATUSL3 : in std_ulogic; + PIPEPHYSTATUSL4 : in std_ulogic; + PIPEPHYSTATUSL5 : in std_ulogic; + PIPEPHYSTATUSL6 : in std_ulogic; + PIPEPHYSTATUSL7 : in std_ulogic; + PIPERXCHANISALIGNEDL0 : in std_ulogic; + PIPERXCHANISALIGNEDL1 : in std_ulogic; + PIPERXCHANISALIGNEDL2 : in std_ulogic; + PIPERXCHANISALIGNEDL3 : in std_ulogic; + PIPERXCHANISALIGNEDL4 : in std_ulogic; + PIPERXCHANISALIGNEDL5 : in std_ulogic; + PIPERXCHANISALIGNEDL6 : in std_ulogic; + PIPERXCHANISALIGNEDL7 : in std_ulogic; + PIPERXDATAKL0 : in std_ulogic; + PIPERXDATAKL1 : in std_ulogic; + PIPERXDATAKL2 : in std_ulogic; + PIPERXDATAKL3 : in std_ulogic; + PIPERXDATAKL4 : in std_ulogic; + PIPERXDATAKL5 : in std_ulogic; + PIPERXDATAKL6 : in std_ulogic; + PIPERXDATAKL7 : in std_ulogic; + PIPERXDATAL0 : in std_logic_vector(7 downto 0); + PIPERXDATAL1 : in std_logic_vector(7 downto 0); + PIPERXDATAL2 : in std_logic_vector(7 downto 0); + PIPERXDATAL3 : in std_logic_vector(7 downto 0); + PIPERXDATAL4 : in std_logic_vector(7 downto 0); + PIPERXDATAL5 : in std_logic_vector(7 downto 0); + PIPERXDATAL6 : in std_logic_vector(7 downto 0); + PIPERXDATAL7 : in std_logic_vector(7 downto 0); + PIPERXELECIDLEL0 : in std_ulogic; + PIPERXELECIDLEL1 : in std_ulogic; + PIPERXELECIDLEL2 : in std_ulogic; + PIPERXELECIDLEL3 : in std_ulogic; + PIPERXELECIDLEL4 : in std_ulogic; + PIPERXELECIDLEL5 : in std_ulogic; + PIPERXELECIDLEL6 : in std_ulogic; + PIPERXELECIDLEL7 : in std_ulogic; + PIPERXSTATUSL0 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL1 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL2 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL3 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL4 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL5 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL6 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL7 : in std_logic_vector(2 downto 0); + PIPERXVALIDL0 : in std_ulogic; + PIPERXVALIDL1 : in std_ulogic; + PIPERXVALIDL2 : in std_ulogic; + PIPERXVALIDL3 : in std_ulogic; + PIPERXVALIDL4 : in std_ulogic; + PIPERXVALIDL5 : in std_ulogic; + PIPERXVALIDL6 : in std_ulogic; + PIPERXVALIDL7 : in std_ulogic; + + MCACTIVELANESIN : in std_logic_vector(7 downto 0); + MCAERBASEPTR : in std_logic_vector(11 downto 0); + MCAERCAPABILITYECRCCHECKCAPABLE : in std_ulogic; + MCAERCAPABILITYECRCGENCAPABLE : in std_ulogic; + MCAERCAPABILITYNEXTPTR : in std_logic_vector(11 downto 0); + MCBAR0ADDRWIDTH : in std_ulogic; + MCBAR0EXIST : in std_ulogic; + MCBAR0IOMEMN : in std_ulogic; + MCBAR0MASKWIDTH : in std_logic_vector(5 downto 0); + MCBAR0PREFETCHABLE : in std_ulogic; + MCBAR1ADDRWIDTH : in std_ulogic; + MCBAR1EXIST : in std_ulogic; + MCBAR1IOMEMN : in std_ulogic; + MCBAR1MASKWIDTH : in std_logic_vector(5 downto 0); + MCBAR1PREFETCHABLE : in std_ulogic; + MCBAR2ADDRWIDTH : in std_ulogic; + MCBAR2EXIST : in std_ulogic; + MCBAR2IOMEMN : in std_ulogic; + MCBAR2MASKWIDTH : in std_logic_vector(5 downto 0); + MCBAR2PREFETCHABLE : in std_ulogic; + MCBAR3ADDRWIDTH : in std_ulogic; + MCBAR3EXIST : in std_ulogic; + MCBAR3IOMEMN : in std_ulogic; + MCBAR3MASKWIDTH : in std_logic_vector(5 downto 0); + MCBAR3PREFETCHABLE : in std_ulogic; + MCBAR4ADDRWIDTH : in std_ulogic; + MCBAR4EXIST : in std_ulogic; + MCBAR4IOMEMN : in std_ulogic; + MCBAR4MASKWIDTH : in std_logic_vector(5 downto 0); + MCBAR4PREFETCHABLE : in std_ulogic; + MCBAR5ADDRWIDTH : in std_ulogic; + MCBAR5EXIST : in std_ulogic; + MCBAR5IOMEMN : in std_ulogic; + MCBAR5MASKWIDTH : in std_logic_vector(5 downto 0); + MCBAR5PREFETCHABLE : in std_ulogic; + MCCAPABILITIESPOINTER : in std_logic_vector(7 downto 0); + MCCARDBUSCISPOINTER : in std_logic_vector(31 downto 0); + MCCLASSCODE : in std_logic_vector(23 downto 0); +-- MCCLKDIVIDED : in std_ulogic; + MCCONFIGROUTING : in std_logic_vector(2 downto 0); + MCDEVICECAPABILITYENDPOINTL0SLATENCY : in std_logic_vector(2 downto 0); + MCDEVICECAPABILITYENDPOINTL1LATENCY : in std_logic_vector(2 downto 0); + MCDEVICEID : in std_logic_vector(15 downto 0); + MCDEVICESERIALNUMBER : in std_logic_vector(63 downto 0); + MCDSNBASEPTR : in std_logic_vector(11 downto 0); + MCDSNCAPABILITYNEXTPTR : in std_logic_vector(11 downto 0); + MCDUALCOREENABLE : in std_ulogic; + MCDUALCORESLAVE : in std_ulogic; + MCDUALROLECFGCNTRLROOTEPN : in std_ulogic; + MCEXTCFGCAPPTR : in std_logic_vector(7 downto 0); + MCEXTCFGXPCAPPTR : in std_logic_vector(11 downto 0); + MCHEADERTYPE : in std_logic_vector(7 downto 0); + MCINFINITECOMPLETIONS : in std_ulogic; + MCINTERRUPTPIN : in std_logic_vector(7 downto 0); + MCISSWITCH : in std_ulogic; + MCL0SEXITLATENCY : in std_logic_vector(2 downto 0); + MCL0SEXITLATENCYCOMCLK : in std_logic_vector(2 downto 0); + MCL1EXITLATENCY : in std_logic_vector(2 downto 0); + MCL1EXITLATENCYCOMCLK : in std_logic_vector(2 downto 0); + MCLINKCAPABILITYASPMSUPPORT : in std_logic_vector(1 downto 0); + MCLINKCAPABILITYMAXLINKWIDTH : in std_logic_vector(5 downto 0); + MCLINKSTATUSSLOTCLOCKCONFIG : in std_ulogic; + MCLLKBYPASS : in std_ulogic; + MCLOWPRIORITYVCCOUNT : in std_logic_vector(2 downto 0); + MCMSIBASEPTR : in std_logic_vector(11 downto 0); + MCMSICAPABILITYMULTIMSGCAP : in std_logic_vector(2 downto 0); + MCMSICAPABILITYNEXTPTR : in std_logic_vector(7 downto 0); + MCPBBASEPTR : in std_logic_vector(11 downto 0); + MCPBCAPABILITYDW0BASEPOWER : in std_logic_vector(7 downto 0); + MCPBCAPABILITYDW0DATASCALE : in std_logic_vector(1 downto 0); + MCPBCAPABILITYDW0PMSTATE : in std_logic_vector(1 downto 0); + MCPBCAPABILITYDW0PMSUBSTATE : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW0POWERRAIL : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW0TYPE : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW1BASEPOWER : in std_logic_vector(7 downto 0); + MCPBCAPABILITYDW1DATASCALE : in std_logic_vector(1 downto 0); + MCPBCAPABILITYDW1PMSTATE : in std_logic_vector(1 downto 0); + MCPBCAPABILITYDW1PMSUBSTATE : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW1POWERRAIL : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW1TYPE : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW2BASEPOWER : in std_logic_vector(7 downto 0); + MCPBCAPABILITYDW2DATASCALE : in std_logic_vector(1 downto 0); + MCPBCAPABILITYDW2PMSTATE : in std_logic_vector(1 downto 0); + MCPBCAPABILITYDW2PMSUBSTATE : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW2POWERRAIL : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW2TYPE : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW3BASEPOWER : in std_logic_vector(7 downto 0); + MCPBCAPABILITYDW3DATASCALE : in std_logic_vector(1 downto 0); + MCPBCAPABILITYDW3PMSTATE : in std_logic_vector(1 downto 0); + MCPBCAPABILITYDW3PMSUBSTATE : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW3POWERRAIL : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW3TYPE : in std_logic_vector(2 downto 0); + MCPBCAPABILITYNEXTPTR : in std_logic_vector(11 downto 0); + MCPBCAPABILITYSYSTEMALLOCATED : in std_ulogic; + MCPCIECAPABILITYINTMSGNUM : in std_logic_vector(4 downto 0); + MCPCIECAPABILITYNEXTPTR : in std_logic_vector(7 downto 0); + MCPCIECAPABILITYSLOTIMPL : in std_ulogic; + MCPCIEREVISION : in std_ulogic; + MCPMBASEPTR : in std_logic_vector(11 downto 0); + MCPMCAPABILITYAUXCURRENT : in std_logic_vector(2 downto 0); + MCPMCAPABILITYD1SUPPORT : in std_ulogic; + MCPMCAPABILITYD2SUPPORT : in std_ulogic; + MCPMCAPABILITYDSI : in std_ulogic; + MCPMCAPABILITYNEXTPTR : in std_logic_vector(7 downto 0); + MCPMCAPABILITYPMESUPPORT : in std_logic_vector(4 downto 0); + MCPMDATA0 : in std_logic_vector(7 downto 0); + MCPMDATA1 : in std_logic_vector(7 downto 0); + MCPMDATA2 : in std_logic_vector(7 downto 0); + MCPMDATA3 : in std_logic_vector(7 downto 0); + MCPMDATA4 : in std_logic_vector(7 downto 0); + MCPMDATA5 : in std_logic_vector(7 downto 0); + MCPMDATA6 : in std_logic_vector(7 downto 0); + MCPMDATA7 : in std_logic_vector(7 downto 0); + MCPMDATA8 : in std_logic_vector(7 downto 0); + MCPMDATASCALE0 : in std_logic_vector(1 downto 0); + MCPMDATASCALE1 : in std_logic_vector(1 downto 0); + MCPMDATASCALE2 : in std_logic_vector(1 downto 0); + MCPMDATASCALE3 : in std_logic_vector(1 downto 0); + MCPMDATASCALE4 : in std_logic_vector(1 downto 0); + MCPMDATASCALE5 : in std_logic_vector(1 downto 0); + MCPMDATASCALE6 : in std_logic_vector(1 downto 0); + MCPMDATASCALE7 : in std_logic_vector(1 downto 0); + MCPMDATASCALE8 : in std_logic_vector(1 downto 0); + MCPMSTATUSCONTROLDATASCALE : in std_logic_vector(1 downto 0); + MCPORTVCCAPABILITYEXTENDEDVCCOUNT : in std_logic_vector(2 downto 0); + MCPORTVCCAPABILITYVCARBCAP : in std_logic_vector(7 downto 0); + MCPORTVCCAPABILITYVCARBTABLEOFFSET : in std_logic_vector(7 downto 0); + MCRAMSHARETXRX : in std_ulogic; + MCRESETMODE : in std_ulogic; + MCRETRYRAMREADLATENCY : in std_logic_vector(2 downto 0); + MCRETRYRAMSIZE : in std_logic_vector(11 downto 0); + MCRETRYRAMWIDTH : in std_ulogic; + MCRETRYRAMWRITELATENCY : in std_logic_vector(2 downto 0); + MCRETRYREADADDRPIPE : in std_ulogic; + MCRETRYREADDATAPIPE : in std_ulogic; + MCRETRYWRITEPIPE : in std_ulogic; + MCREVISIONID : in std_logic_vector(7 downto 0); + MCRXREADADDRPIPE : in std_ulogic; + MCRXREADDATAPIPE : in std_ulogic; + MCRXWRITEPIPE : in std_ulogic; + MCSELECTASMODE : in std_ulogic; + MCSELECTDLLIF : in std_ulogic; + MCSLOTCAPABILITYATTBUTTONPRESENT : in std_ulogic; + MCSLOTCAPABILITYATTINDICATORPRESENT : in std_ulogic; + MCSLOTCAPABILITYHOTPLUGCAPABLE : in std_ulogic; + MCSLOTCAPABILITYHOTPLUGSURPRISE : in std_ulogic; + MCSLOTCAPABILITYMSLSENSORPRESENT : in std_ulogic; + MCSLOTCAPABILITYPHYSICALSLOTNUM : in std_logic_vector(12 downto 0); + MCSLOTCAPABILITYPOWERCONTROLLERPRESENT : in std_ulogic; + MCSLOTCAPABILITYPOWERINDICATORPRESENT : in std_ulogic; + MCSLOTCAPABILITYSLOTPOWERLIMITSCALE : in std_logic_vector(1 downto 0); + MCSLOTCAPABILITYSLOTPOWERLIMITVALUE : in std_logic_vector(7 downto 0); + MCSLOTIMPLEMENTED : in std_ulogic; + MCSUBSYSTEMID : in std_logic_vector(15 downto 0); + MCSUBSYSTEMVENDORID : in std_logic_vector(15 downto 0); + MCTLRAMREADLATENCY : in std_logic_vector(2 downto 0); + MCTLRAMWIDTH : in std_ulogic; + MCTLRAMWRITELATENCY : in std_logic_vector(2 downto 0); + MCTXREADADDRPIPE : in std_ulogic; + MCTXREADDATAPIPE : in std_ulogic; + MCTXTSNFTS : in std_logic_vector(7 downto 0); + MCTXTSNFTSCOMCLK : in std_logic_vector(7 downto 0); + MCTXWRITEPIPE : in std_ulogic; + MCUPSTREAMFACING : in std_ulogic; + MCVC0RXFIFOBASEC : in std_logic_vector(12 downto 0); + MCVC0RXFIFOBASENP : in std_logic_vector(12 downto 0); + MCVC0RXFIFOBASEP : in std_logic_vector(12 downto 0); + MCVC0RXFIFOLIMITC : in std_logic_vector(12 downto 0); + MCVC0RXFIFOLIMITNP : in std_logic_vector(12 downto 0); + MCVC0RXFIFOLIMITP : in std_logic_vector(12 downto 0); + MCVC0TOTALCREDITSCD : in std_logic_vector(10 downto 0); + MCVC0TOTALCREDITSCH : in std_logic_vector(6 downto 0); + MCVC0TOTALCREDITSNPH : in std_logic_vector(6 downto 0); + MCVC0TOTALCREDITSPD : in std_logic_vector(10 downto 0); + MCVC0TOTALCREDITSPH : in std_logic_vector(6 downto 0); + MCVC0TXFIFOBASEC : in std_logic_vector(12 downto 0); + MCVC0TXFIFOBASENP : in std_logic_vector(12 downto 0); + MCVC0TXFIFOBASEP : in std_logic_vector(12 downto 0); + MCVC0TXFIFOLIMITC : in std_logic_vector(12 downto 0); + MCVC0TXFIFOLIMITNP : in std_logic_vector(12 downto 0); + MCVC0TXFIFOLIMITP : in std_logic_vector(12 downto 0); + MCVC1RXFIFOBASEC : in std_logic_vector(12 downto 0); + MCVC1RXFIFOBASENP : in std_logic_vector(12 downto 0); + MCVC1RXFIFOBASEP : in std_logic_vector(12 downto 0); + MCVC1RXFIFOLIMITC : in std_logic_vector(12 downto 0); + MCVC1RXFIFOLIMITNP : in std_logic_vector(12 downto 0); + MCVC1RXFIFOLIMITP : in std_logic_vector(12 downto 0); + MCVC1TOTALCREDITSCD : in std_logic_vector(10 downto 0); + MCVC1TOTALCREDITSCH : in std_logic_vector(6 downto 0); + MCVC1TOTALCREDITSNPH : in std_logic_vector(6 downto 0); + MCVC1TOTALCREDITSPD : in std_logic_vector(10 downto 0); + MCVC1TOTALCREDITSPH : in std_logic_vector(6 downto 0); + MCVC1TXFIFOBASEC : in std_logic_vector(12 downto 0); + MCVC1TXFIFOBASENP : in std_logic_vector(12 downto 0); + MCVC1TXFIFOBASEP : in std_logic_vector(12 downto 0); + MCVC1TXFIFOLIMITC : in std_logic_vector(12 downto 0); + MCVC1TXFIFOLIMITNP : in std_logic_vector(12 downto 0); + MCVC1TXFIFOLIMITP : in std_logic_vector(12 downto 0); + MCVCBASEPTR : in std_logic_vector(11 downto 0); + MCVCCAPABILITYNEXTPTR : in std_logic_vector(11 downto 0); + MCVENDORID : in std_logic_vector(15 downto 0); + MCXLINKSUPPORTED : in std_ulogic; + MCXPBASEPTR : in std_logic_vector(7 downto 0); + MCXPDEVICEPORTTYPE : in std_logic_vector(3 downto 0); + MCXPMAXPAYLOAD : in std_logic_vector(2 downto 0); + MCXPRCBCONTROL : in std_ulogic + ); + end component; + + constant IN_DELAY : time := 0 ps; + constant OUT_DELAY : time := 0 ps; + constant CLK_DELAY : time := 0 ps; + + constant PATH_DELAY : VitalDelayType01 := (100 ps, 100 ps); + + + signal VC0TXFIFOBASEP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0TXFIFOBASEP)(12 downto 0); + signal VC0TXFIFOBASENP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0TXFIFOBASENP)(12 downto 0); + signal VC0TXFIFOBASEC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0TXFIFOBASEC)(12 downto 0); + signal VC0TXFIFOLIMITP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0TXFIFOLIMITP)(12 downto 0); + signal VC0TXFIFOLIMITNP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0TXFIFOLIMITNP)(12 downto 0); + signal VC0TXFIFOLIMITC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0TXFIFOLIMITC)(12 downto 0); + signal VC0TOTALCREDITSPH_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(VC0TOTALCREDITSPH)(6 downto 0); + signal VC0TOTALCREDITSNPH_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(VC0TOTALCREDITSNPH)(6 downto 0); + signal VC0TOTALCREDITSCH_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(VC0TOTALCREDITSCH)(6 downto 0); + signal VC0TOTALCREDITSPD_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(VC0TOTALCREDITSPD)(10 downto 0); + signal VC0TOTALCREDITSCD_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(VC0TOTALCREDITSCD)(10 downto 0); + signal VC0RXFIFOBASEP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0RXFIFOBASEP)(12 downto 0); + signal VC0RXFIFOBASENP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0RXFIFOBASENP)(12 downto 0); + signal VC0RXFIFOBASEC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0RXFIFOBASEC)(12 downto 0); + signal VC0RXFIFOLIMITP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0RXFIFOLIMITP)(12 downto 0); + signal VC0RXFIFOLIMITNP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0RXFIFOLIMITNP)(12 downto 0); + signal VC0RXFIFOLIMITC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0RXFIFOLIMITC)(12 downto 0); + signal VC1TXFIFOBASEP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1TXFIFOBASEP)(12 downto 0); + signal VC1TXFIFOBASENP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1TXFIFOBASENP)(12 downto 0); + signal VC1TXFIFOBASEC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1TXFIFOBASEC)(12 downto 0); + signal VC1TXFIFOLIMITP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1TXFIFOLIMITP)(12 downto 0); + signal VC1TXFIFOLIMITNP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1TXFIFOLIMITNP)(12 downto 0); + signal VC1TXFIFOLIMITC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1TXFIFOLIMITC)(12 downto 0); + signal VC1TOTALCREDITSPH_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(VC1TOTALCREDITSPH)(6 downto 0); + signal VC1TOTALCREDITSNPH_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(VC1TOTALCREDITSNPH)(6 downto 0); + signal VC1TOTALCREDITSCH_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(VC1TOTALCREDITSCH)(6 downto 0); + signal VC1TOTALCREDITSPD_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(VC1TOTALCREDITSPD)(10 downto 0); + signal VC1TOTALCREDITSCD_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(VC1TOTALCREDITSCD)(10 downto 0); + signal VC1RXFIFOBASEP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1RXFIFOBASEP)(12 downto 0); + signal VC1RXFIFOBASENP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1RXFIFOBASENP)(12 downto 0); + signal VC1RXFIFOBASEC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1RXFIFOBASEC)(12 downto 0); + signal VC1RXFIFOLIMITP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1RXFIFOLIMITP)(12 downto 0); + signal VC1RXFIFOLIMITNP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1RXFIFOLIMITNP)(12 downto 0); + signal VC1RXFIFOLIMITC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1RXFIFOLIMITC)(12 downto 0); + signal ACTIVELANESIN_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(ACTIVELANESIN); + signal TXTSNFTS_BINARY : std_logic_vector(7 downto 0); + signal TXTSNFTSCOMCLK_BINARY : std_logic_vector(7 downto 0); + signal RETRYRAMREADLATENCY_BINARY : std_logic_vector(2 downto 0); + signal RETRYRAMWRITELATENCY_BINARY : std_logic_vector(2 downto 0); + signal RETRYRAMWIDTH_BINARY : std_ulogic; + signal RETRYRAMSIZE_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(RETRYRAMSIZE); + signal RETRYWRITEPIPE_BINARY : std_ulogic; + signal RETRYREADADDRPIPE_BINARY : std_ulogic; + signal RETRYREADDATAPIPE_BINARY : std_ulogic; + signal XLINKSUPPORTED_BINARY : std_ulogic; + signal INFINITECOMPLETIONS_BINARY : std_ulogic; + signal TLRAMREADLATENCY_BINARY : std_logic_vector(2 downto 0); + signal TLRAMWRITELATENCY_BINARY : std_logic_vector(2 downto 0); + signal TLRAMWIDTH_BINARY : std_ulogic; + signal RAMSHARETXRX_BINARY : std_ulogic; + signal L0SEXITLATENCY_BINARY : std_logic_vector(2 downto 0); + signal L0SEXITLATENCYCOMCLK_BINARY : std_logic_vector(2 downto 0); + signal L1EXITLATENCY_BINARY : std_logic_vector(2 downto 0); + signal L1EXITLATENCYCOMCLK_BINARY : std_logic_vector(2 downto 0); + signal DUALCORESLAVE_BINARY : std_ulogic; + signal DUALCOREENABLE_BINARY : std_ulogic; + signal DUALROLECFGCNTRLROOTEPN_BINARY : std_ulogic; + signal RXREADADDRPIPE_BINARY : std_ulogic; + signal RXREADDATAPIPE_BINARY : std_ulogic; + signal TXWRITEPIPE_BINARY : std_ulogic; + signal TXREADADDRPIPE_BINARY : std_ulogic; + signal TXREADDATAPIPE_BINARY : std_ulogic; + signal RXWRITEPIPE_BINARY : std_ulogic; + signal LLKBYPASS_BINARY : std_ulogic; + signal PCIEREVISION_BINARY : std_ulogic; + signal SELECTDLLIF_BINARY : std_ulogic; + signal SELECTASMODE_BINARY : std_ulogic; + signal ISSWITCH_BINARY : std_ulogic; + signal UPSTREAMFACING_BINARY : std_ulogic; + signal SLOTIMPLEMENTED_BINARY : std_ulogic; + signal EXTCFGCAPPTR_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(EXTCFGCAPPTR); + signal EXTCFGXPCAPPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(EXTCFGXPCAPPTR); + signal BAR0EXIST_BINARY : std_ulogic; + signal BAR1EXIST_BINARY : std_ulogic; + signal BAR2EXIST_BINARY : std_ulogic; + signal BAR3EXIST_BINARY : std_ulogic; + signal BAR4EXIST_BINARY : std_ulogic; + signal BAR5EXIST_BINARY : std_ulogic; + signal BAR0ADDRWIDTH_BINARY : std_ulogic; + signal BAR1ADDRWIDTH_BINARY : std_ulogic; + signal BAR2ADDRWIDTH_BINARY : std_ulogic; + signal BAR3ADDRWIDTH_BINARY : std_ulogic; + signal BAR4ADDRWIDTH_BINARY : std_ulogic; + signal BAR5ADDRWIDTH_BINARY : std_ulogic := '0'; + signal BAR0PREFETCHABLE_BINARY : std_ulogic; + signal BAR1PREFETCHABLE_BINARY : std_ulogic; + signal BAR2PREFETCHABLE_BINARY : std_ulogic; + signal BAR3PREFETCHABLE_BINARY : std_ulogic; + signal BAR4PREFETCHABLE_BINARY : std_ulogic; + signal BAR5PREFETCHABLE_BINARY : std_ulogic; + signal BAR0IOMEMN_BINARY : std_ulogic; + signal BAR1IOMEMN_BINARY : std_ulogic; + signal BAR2IOMEMN_BINARY : std_ulogic; + signal BAR3IOMEMN_BINARY : std_ulogic; + signal BAR4IOMEMN_BINARY : std_ulogic; + signal BAR5IOMEMN_BINARY : std_ulogic; + signal BAR0MASKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(BAR0MASKWIDTH)(5 downto 0); + signal BAR1MASKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(BAR1MASKWIDTH)(5 downto 0); + signal BAR2MASKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(BAR2MASKWIDTH)(5 downto 0); + signal BAR3MASKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(BAR3MASKWIDTH)(5 downto 0); + signal BAR4MASKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(BAR4MASKWIDTH)(5 downto 0); + signal BAR5MASKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(BAR5MASKWIDTH)(5 downto 0); + signal CONFIGROUTING_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(CONFIGROUTING)(2 downto 0); + signal XPDEVICEPORTTYPE_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(XPDEVICEPORTTYPE); + signal HEADERTYPE_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(HEADERTYPE); + signal XPMAXPAYLOAD_BINARY : std_logic_vector(2 downto 0); + signal XPRCBCONTROL_BINARY : std_ulogic; + signal LOWPRIORITYVCCOUNT_BINARY : std_logic_vector(2 downto 0); + signal VENDORID_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(VENDORID); + signal DEVICEID_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(DEVICEID); + signal REVISIONID_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(REVISIONID); + signal CLASSCODE_BINARY : std_logic_vector(23 downto 0) := To_StdLogicVector(CLASSCODE); + signal CARDBUSCISPOINTER_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(CARDBUSCISPOINTER); + signal SUBSYSTEMVENDORID_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(SUBSYSTEMVENDORID); + signal SUBSYSTEMID_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(SUBSYSTEMID); + signal CAPABILITIESPOINTER_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(CAPABILITIESPOINTER); + signal INTERRUPTPIN_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(INTERRUPTPIN); + signal PMCAPABILITYNEXTPTR_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMCAPABILITYNEXTPTR); + signal PMCAPABILITYDSI_BINARY : std_ulogic; + signal PMCAPABILITYAUXCURRENT_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PMCAPABILITYAUXCURRENT)(2 downto 0); + signal PMCAPABILITYD1SUPPORT_BINARY : std_ulogic; + signal PMCAPABILITYD2SUPPORT_BINARY : std_ulogic; + signal PMCAPABILITYPMESUPPORT_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(PMCAPABILITYPMESUPPORT)(4 downto 0); + signal PMSTATUSCONTROLDATASCALE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PMSTATUSCONTROLDATASCALE)(1 downto 0); + signal PMDATA0_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA0); + signal PMDATA1_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA1); + signal PMDATA2_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA2); + signal PMDATA3_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA3); + signal PMDATA4_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA4); + signal PMDATA5_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA5); + signal PMDATA6_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA6); + signal PMDATA7_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA7); + signal PMDATA8_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA8); + signal PMDATASCALE0_BINARY : std_logic_vector(1 downto 0); + signal PMDATASCALE1_BINARY : std_logic_vector(1 downto 0); + signal PMDATASCALE2_BINARY : std_logic_vector(1 downto 0); + signal PMDATASCALE3_BINARY : std_logic_vector(1 downto 0); + signal PMDATASCALE4_BINARY : std_logic_vector(1 downto 0); + signal PMDATASCALE5_BINARY : std_logic_vector(1 downto 0); + signal PMDATASCALE6_BINARY : std_logic_vector(1 downto 0); + signal PMDATASCALE7_BINARY : std_logic_vector(1 downto 0); + signal PMDATASCALE8_BINARY : std_logic_vector(1 downto 0); + signal MSICAPABILITYNEXTPTR_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(MSICAPABILITYNEXTPTR); + signal MSICAPABILITYMULTIMSGCAP_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(MSICAPABILITYMULTIMSGCAP)(2 downto 0); + signal PCIECAPABILITYNEXTPTR_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PCIECAPABILITYNEXTPTR); + signal PCIECAPABILITYSLOTIMPL_BINARY : std_ulogic; + signal PCIECAPABILITYINTMSGNUM_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(PCIECAPABILITYINTMSGNUM)(4 downto 0); + signal DEVICECAPABILITYENDPOINTL0SLATENCY_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(DEVICECAPABILITYENDPOINTL0SLATENCY)(2 downto 0); + signal DEVICECAPABILITYENDPOINTL1LATENCY_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(DEVICECAPABILITYENDPOINTL1LATENCY)(2 downto 0); + signal LINKCAPABILITYMAXLINKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(LINKCAPABILITYMAXLINKWIDTH)(5 downto 0); + signal LINKCAPABILITYASPMSUPPORT_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(LINKCAPABILITYASPMSUPPORT)(1 downto 0); + signal LINKSTATUSSLOTCLOCKCONFIG_BINARY : std_ulogic; + signal SLOTCAPABILITYATTBUTTONPRESENT_BINARY : std_ulogic; + signal SLOTCAPABILITYPOWERCONTROLLERPRESENT_BINARY : std_ulogic; + signal SLOTCAPABILITYMSLSENSORPRESENT_BINARY : std_ulogic; + signal SLOTCAPABILITYATTINDICATORPRESENT_BINARY : std_ulogic; + signal SLOTCAPABILITYPOWERINDICATORPRESENT_BINARY : std_ulogic; + signal SLOTCAPABILITYHOTPLUGSURPRISE_BINARY : std_ulogic; + signal SLOTCAPABILITYHOTPLUGCAPABLE_BINARY : std_ulogic; + signal SLOTCAPABILITYSLOTPOWERLIMITVALUE_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(SLOTCAPABILITYSLOTPOWERLIMITVALUE); + signal SLOTCAPABILITYSLOTPOWERLIMITSCALE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(SLOTCAPABILITYSLOTPOWERLIMITSCALE)(1 downto 0); + signal SLOTCAPABILITYPHYSICALSLOTNUM_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(SLOTCAPABILITYPHYSICALSLOTNUM)(12 downto 0); + signal AERCAPABILITYNEXTPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(AERCAPABILITYNEXTPTR); + signal AERCAPABILITYECRCGENCAPABLE_BINARY : std_ulogic; + signal AERCAPABILITYECRCCHECKCAPABLE_BINARY : std_ulogic; + signal VCCAPABILITYNEXTPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(VCCAPABILITYNEXTPTR); + signal PORTVCCAPABILITYEXTENDEDVCCOUNT_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PORTVCCAPABILITYEXTENDEDVCCOUNT)(2 downto 0); + signal PORTVCCAPABILITYVCARBCAP_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PORTVCCAPABILITYVCARBCAP); + signal PORTVCCAPABILITYVCARBTABLEOFFSET_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PORTVCCAPABILITYVCARBTABLEOFFSET); + signal DSNCAPABILITYNEXTPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(DSNCAPABILITYNEXTPTR); + signal DEVICESERIALNUMBER_BINARY : std_logic_vector(63 downto 0) := To_StdLogicVector(DEVICESERIALNUMBER); + signal PBCAPABILITYNEXTPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(PBCAPABILITYNEXTPTR); + signal PBCAPABILITYDW0BASEPOWER_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PBCAPABILITYDW0BASEPOWER); + signal PBCAPABILITYDW0DATASCALE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW0DATASCALE)(1 downto 0); + signal PBCAPABILITYDW0PMSUBSTATE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW0PMSUBSTATE)(2 downto 0); + signal PBCAPABILITYDW0PMSTATE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW0PMSTATE)(1 downto 0); + signal PBCAPABILITYDW0TYPE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW0TYPE)(2 downto 0); + signal PBCAPABILITYDW0POWERRAIL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW0POWERRAIL)(2 downto 0); + signal PBCAPABILITYDW1BASEPOWER_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PBCAPABILITYDW1BASEPOWER); + signal PBCAPABILITYDW1DATASCALE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW1DATASCALE)(1 downto 0); + signal PBCAPABILITYDW1PMSUBSTATE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW1PMSUBSTATE)(2 downto 0); + signal PBCAPABILITYDW1PMSTATE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW1PMSTATE)(1 downto 0); + signal PBCAPABILITYDW1TYPE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW1TYPE)(2 downto 0); + signal PBCAPABILITYDW1POWERRAIL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW1POWERRAIL)(2 downto 0); + signal PBCAPABILITYDW2BASEPOWER_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PBCAPABILITYDW2BASEPOWER); + signal PBCAPABILITYDW2DATASCALE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW2DATASCALE)(1 downto 0); + signal PBCAPABILITYDW2PMSUBSTATE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW2PMSUBSTATE)(2 downto 0); + signal PBCAPABILITYDW2PMSTATE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW2PMSTATE)(1 downto 0); + signal PBCAPABILITYDW2TYPE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW2TYPE)(2 downto 0); + signal PBCAPABILITYDW2POWERRAIL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW2POWERRAIL)(2 downto 0); + signal PBCAPABILITYDW3BASEPOWER_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PBCAPABILITYDW3BASEPOWER); + signal PBCAPABILITYDW3DATASCALE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW3DATASCALE)(1 downto 0); + signal PBCAPABILITYDW3PMSUBSTATE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW3PMSUBSTATE)(2 downto 0); + signal PBCAPABILITYDW3PMSTATE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW3PMSTATE)(1 downto 0); + signal PBCAPABILITYDW3TYPE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW3TYPE)(2 downto 0); + signal PBCAPABILITYDW3POWERRAIL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW3POWERRAIL)(2 downto 0); + signal PBCAPABILITYSYSTEMALLOCATED_BINARY : std_ulogic; + signal RESETMODE_BINARY : std_ulogic; + signal AERBASEPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(AERBASEPTR); + signal DSNBASEPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(DSNBASEPTR); + signal MSIBASEPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(MSIBASEPTR); + signal PBBASEPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(PBBASEPTR); + signal PMBASEPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(PMBASEPTR); + signal VCBASEPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(VCBASEPTR); + signal XPBASEPTR_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(XPBASEPTR); + signal CLKDIVIDED_BINARY : std_ulogic; + + + signal PIPETXDATAL0_out : std_logic_vector(7 downto 0); + signal PIPETXDATAKL0_out : std_ulogic; + signal PIPETXELECIDLEL0_out : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL0_out : std_ulogic; + signal PIPETXCOMPLIANCEL0_out : std_ulogic; + signal PIPERXPOLARITYL0_out : std_ulogic; + signal PIPEPOWERDOWNL0_out : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL0_out : std_ulogic; + signal PIPERESETL0_out : std_ulogic; + signal PIPETXDATAL1_out : std_logic_vector(7 downto 0); + signal PIPETXDATAKL1_out : std_ulogic; + signal PIPETXELECIDLEL1_out : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL1_out : std_ulogic; + signal PIPETXCOMPLIANCEL1_out : std_ulogic; + signal PIPERXPOLARITYL1_out : std_ulogic; + signal PIPEPOWERDOWNL1_out : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL1_out : std_ulogic; + signal PIPERESETL1_out : std_ulogic; + signal PIPETXDATAL2_out : std_logic_vector(7 downto 0); + signal PIPETXDATAKL2_out : std_ulogic; + signal PIPETXELECIDLEL2_out : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL2_out : std_ulogic; + signal PIPETXCOMPLIANCEL2_out : std_ulogic; + signal PIPERXPOLARITYL2_out : std_ulogic; + signal PIPEPOWERDOWNL2_out : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL2_out : std_ulogic; + signal PIPERESETL2_out : std_ulogic; + signal PIPETXDATAL3_out : std_logic_vector(7 downto 0); + signal PIPETXDATAKL3_out : std_ulogic; + signal PIPETXELECIDLEL3_out : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL3_out : std_ulogic; + signal PIPETXCOMPLIANCEL3_out : std_ulogic; + signal PIPERXPOLARITYL3_out : std_ulogic; + signal PIPEPOWERDOWNL3_out : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL3_out : std_ulogic; + signal PIPERESETL3_out : std_ulogic; + signal PIPETXDATAL4_out : std_logic_vector(7 downto 0); + signal PIPETXDATAKL4_out : std_ulogic; + signal PIPETXELECIDLEL4_out : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL4_out : std_ulogic; + signal PIPETXCOMPLIANCEL4_out : std_ulogic; + signal PIPERXPOLARITYL4_out : std_ulogic; + signal PIPEPOWERDOWNL4_out : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL4_out : std_ulogic; + signal PIPERESETL4_out : std_ulogic; + signal PIPETXDATAL5_out : std_logic_vector(7 downto 0); + signal PIPETXDATAKL5_out : std_ulogic; + signal PIPETXELECIDLEL5_out : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL5_out : std_ulogic; + signal PIPETXCOMPLIANCEL5_out : std_ulogic; + signal PIPERXPOLARITYL5_out : std_ulogic; + signal PIPEPOWERDOWNL5_out : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL5_out : std_ulogic; + signal PIPERESETL5_out : std_ulogic; + signal PIPETXDATAL6_out : std_logic_vector(7 downto 0); + signal PIPETXDATAKL6_out : std_ulogic; + signal PIPETXELECIDLEL6_out : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL6_out : std_ulogic; + signal PIPETXCOMPLIANCEL6_out : std_ulogic; + signal PIPERXPOLARITYL6_out : std_ulogic; + signal PIPEPOWERDOWNL6_out : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL6_out : std_ulogic; + signal PIPERESETL6_out : std_ulogic; + signal PIPETXDATAL7_out : std_logic_vector(7 downto 0); + signal PIPETXDATAKL7_out : std_ulogic; + signal PIPETXELECIDLEL7_out : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL7_out : std_ulogic; + signal PIPETXCOMPLIANCEL7_out : std_ulogic; + signal PIPERXPOLARITYL7_out : std_ulogic; + signal PIPEPOWERDOWNL7_out : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL7_out : std_ulogic; + signal PIPERESETL7_out : std_ulogic; + signal MIMRXBWDATA_out : std_logic_vector(63 downto 0); + signal MIMRXBWADD_out : std_logic_vector(12 downto 0); + signal MIMRXBRADD_out : std_logic_vector(12 downto 0); + signal MIMRXBWEN_out : std_ulogic; + signal MIMRXBREN_out : std_ulogic; + signal MIMTXBWDATA_out : std_logic_vector(63 downto 0); + signal MIMTXBWADD_out : std_logic_vector(12 downto 0); + signal MIMTXBRADD_out : std_logic_vector(12 downto 0); + signal MIMTXBWEN_out : std_ulogic; + signal MIMTXBREN_out : std_ulogic; + signal MIMDLLBWDATA_out : std_logic_vector(63 downto 0); + signal MIMDLLBWADD_out : std_logic_vector(11 downto 0); + signal MIMDLLBRADD_out : std_logic_vector(11 downto 0); + signal MIMDLLBWEN_out : std_ulogic; + signal MIMDLLBREN_out : std_ulogic; + signal CRMRXHOTRESETN_out : std_ulogic; + signal CRMDOHOTRESETN_out : std_ulogic; + signal CRMPWRSOFTRESETN_out : std_ulogic; + signal LLKTCSTATUS_out : std_logic_vector(7 downto 0); + signal LLKTXDSTRDYN_out : std_ulogic; + signal LLKTXCHANSPACE_out : std_logic_vector(9 downto 0); + signal LLKTXCHPOSTEDREADYN_out : std_logic_vector(7 downto 0); + signal LLKTXCHNONPOSTEDREADYN_out : std_logic_vector(7 downto 0); + signal LLKTXCHCOMPLETIONREADYN_out : std_logic_vector(7 downto 0); + signal LLKTXCONFIGREADYN_out : std_ulogic; + signal LLKRXDATA_out : std_logic_vector(63 downto 0); + signal LLKRXSRCRDYN_out : std_ulogic; + signal LLKRXSRCLASTREQN_out : std_ulogic; + signal LLKRXSRCDSCN_out : std_ulogic; + signal LLKRXSOFN_out : std_ulogic; + signal LLKRXEOFN_out : std_ulogic; + signal LLKRXSOPN_out : std_ulogic; + signal LLKRXEOPN_out : std_ulogic; + signal LLKRXVALIDN_out : std_logic_vector(1 downto 0); + signal LLKRXPREFERREDTYPE_out : std_logic_vector(15 downto 0); + signal LLKRXCHPOSTEDAVAILABLEN_out : std_logic_vector(7 downto 0); + signal LLKRXCHNONPOSTEDAVAILABLEN_out : std_logic_vector(7 downto 0); + signal LLKRXCHCOMPLETIONAVAILABLEN_out : std_logic_vector(7 downto 0); + signal LLKRXCHCONFIGAVAILABLEN_out : std_ulogic; + signal LLKRXCHPOSTEDPARTIALN_out : std_logic_vector(7 downto 0); + signal LLKRXCHNONPOSTEDPARTIALN_out : std_logic_vector(7 downto 0); + signal LLKRXCHCOMPLETIONPARTIALN_out : std_logic_vector(7 downto 0); + signal LLKRXCHCONFIGPARTIALN_out : std_ulogic; + signal LLKRX4DWHEADERN_out : std_ulogic; + signal LLKRXECRCBADN_out : std_ulogic; + signal MGMTRDATA_out : std_logic_vector(31 downto 0); + signal MGMTPSO_out : std_logic_vector(16 downto 0); + signal MGMTSTATSCREDIT_out : std_logic_vector(11 downto 0); + signal L0RXDLLTLPECRCOK_out : std_ulogic; + signal DLLTXPMDLLPOUTSTANDING_out : std_ulogic; + signal L0FIRSTCFGWRITEOCCURRED_out : std_ulogic; + signal L0CFGLOOPBACKACK_out : std_ulogic; + signal L0MACUPSTREAMDOWNSTREAM_out : std_ulogic; + signal L0RXMACLINKERROR_out : std_logic_vector(1 downto 0); + signal L0MACLINKUP_out : std_ulogic; + signal L0MACNEGOTIATEDLINKWIDTH_out : std_logic_vector(3 downto 0); + signal L0MACLINKTRAINING_out : std_ulogic; + signal L0LTSSMSTATE_out : std_logic_vector(3 downto 0); + signal L0DLLVCSTATUS_out : std_logic_vector(7 downto 0); + signal L0DLUPDOWN_out : std_logic_vector(7 downto 0); + signal L0DLLERRORVECTOR_out : std_logic_vector(6 downto 0); + signal L0DLLASRXSTATE_out : std_logic_vector(1 downto 0); + signal L0DLLASTXSTATE_out : std_ulogic; + signal L0ASAUTONOMOUSINITCOMPLETED_out : std_ulogic; + signal L0COMPLETERID_out : std_logic_vector(12 downto 0); + signal L0UNLOCKRECEIVED_out : std_ulogic; + signal L0CORRERRMSGRCVD_out : std_ulogic; + signal L0FATALERRMSGRCVD_out : std_ulogic; + signal L0NONFATALERRMSGRCVD_out : std_ulogic; + signal L0ERRMSGREQID_out : std_logic_vector(15 downto 0); + signal L0FWDCORRERROUT_out : std_ulogic; + signal L0FWDFATALERROUT_out : std_ulogic; + signal L0FWDNONFATALERROUT_out : std_ulogic; + signal L0RECEIVEDASSERTINTALEGACYINT_out : std_ulogic; + signal L0RECEIVEDASSERTINTBLEGACYINT_out : std_ulogic; + signal L0RECEIVEDASSERTINTCLEGACYINT_out : std_ulogic; + signal L0RECEIVEDASSERTINTDLEGACYINT_out : std_ulogic; + signal L0RECEIVEDDEASSERTINTALEGACYINT_out : std_ulogic; + signal L0RECEIVEDDEASSERTINTBLEGACYINT_out : std_ulogic; + signal L0RECEIVEDDEASSERTINTCLEGACYINT_out : std_ulogic; + signal L0RECEIVEDDEASSERTINTDLEGACYINT_out : std_ulogic; + signal L0MSIENABLE0_out : std_ulogic; + signal L0MULTIMSGEN0_out : std_logic_vector(2 downto 0); + signal L0STATSDLLPRECEIVED_out : std_ulogic; + signal L0STATSDLLPTRANSMITTED_out : std_ulogic; + signal L0STATSOSRECEIVED_out : std_ulogic; + signal L0STATSOSTRANSMITTED_out : std_ulogic; + signal L0STATSTLPRECEIVED_out : std_ulogic; + signal L0STATSTLPTRANSMITTED_out : std_ulogic; + signal L0STATSCFGRECEIVED_out : std_ulogic; + signal L0STATSCFGTRANSMITTED_out : std_ulogic; + signal L0STATSCFGOTHERRECEIVED_out : std_ulogic; + signal L0STATSCFGOTHERTRANSMITTED_out : std_ulogic; + signal MAXPAYLOADSIZE_out : std_logic_vector(2 downto 0); + signal MAXREADREQUESTSIZE_out : std_logic_vector(2 downto 0); + signal IOSPACEENABLE_out : std_ulogic; + signal MEMSPACEENABLE_out : std_ulogic; + signal L0ATTENTIONINDICATORCONTROL_out : std_logic_vector(1 downto 0); + signal L0POWERINDICATORCONTROL_out : std_logic_vector(1 downto 0); + signal L0POWERCONTROLLERCONTROL_out : std_ulogic; + signal L0TOGGLEELECTROMECHANICALINTERLOCK_out : std_ulogic; + signal L0RXBEACON_out : std_ulogic; + signal L0PWRSTATE0_out : std_logic_vector(1 downto 0); + signal L0PMEACK_out : std_ulogic; + signal L0PMEREQOUT_out : std_ulogic; + signal L0PMEEN_out : std_ulogic; + signal L0PWRINHIBITTRANSFERS_out : std_ulogic; + signal L0PWRL1STATE_out : std_ulogic; + signal L0PWRL23READYDEVICE_out : std_ulogic; + signal L0PWRL23READYSTATE_out : std_ulogic; + signal L0PWRTXL0SSTATE_out : std_ulogic; + signal L0PWRTURNOFFREQ_out : std_ulogic; + signal L0RXDLLPM_out : std_ulogic; + signal L0RXDLLPMTYPE_out : std_logic_vector(2 downto 0); + signal L0TXDLLPMUPDATED_out : std_ulogic; + signal L0MACNEWSTATEACK_out : std_ulogic; + signal L0MACRXL0SSTATE_out : std_ulogic; + signal L0MACENTEREDL0_out : std_ulogic; + signal L0DLLRXACKOUTSTANDING_out : std_ulogic; + signal L0DLLTXOUTSTANDING_out : std_ulogic; + signal L0DLLTXNONFCOUTSTANDING_out : std_ulogic; + signal L0RXDLLTLPEND_out : std_logic_vector(1 downto 0); + signal L0TXDLLSBFCUPDATED_out : std_ulogic; + signal L0RXDLLSBFCDATA_out : std_logic_vector(18 downto 0); + signal L0RXDLLSBFCUPDATE_out : std_ulogic; + signal L0TXDLLFCNPOSTBYPUPDATED_out : std_logic_vector(7 downto 0); + signal L0TXDLLFCPOSTORDUPDATED_out : std_logic_vector(7 downto 0); + signal L0TXDLLFCCMPLMCUPDATED_out : std_logic_vector(7 downto 0); + signal L0RXDLLFCNPOSTBYPCRED_out : std_logic_vector(19 downto 0); + signal L0RXDLLFCNPOSTBYPUPDATE_out : std_logic_vector(7 downto 0); + signal L0RXDLLFCPOSTORDCRED_out : std_logic_vector(23 downto 0); + signal L0RXDLLFCPOSTORDUPDATE_out : std_logic_vector(7 downto 0); + signal L0RXDLLFCCMPLMCCRED_out : std_logic_vector(23 downto 0); + signal L0RXDLLFCCMPLMCUPDATE_out : std_logic_vector(7 downto 0); + signal L0UCBYPFOUND_out : std_logic_vector(3 downto 0); + signal L0UCORDFOUND_out : std_logic_vector(3 downto 0); + signal L0MCFOUND_out : std_logic_vector(2 downto 0); + signal L0TRANSFORMEDVC_out : std_logic_vector(2 downto 0); + signal BUSMASTERENABLE_out : std_ulogic; + signal PARITYERRORRESPONSE_out : std_ulogic; + signal SERRENABLE_out : std_ulogic; + signal INTERRUPTDISABLE_out : std_ulogic; + signal URREPORTINGENABLE_out : std_ulogic; + + + signal PIPETXDATAL0_outdelay : std_logic_vector(7 downto 0); + signal PIPETXDATAKL0_outdelay : std_ulogic; + signal PIPETXELECIDLEL0_outdelay : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL0_outdelay : std_ulogic; + signal PIPETXCOMPLIANCEL0_outdelay : std_ulogic; + signal PIPERXPOLARITYL0_outdelay : std_ulogic; + signal PIPEPOWERDOWNL0_outdelay : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL0_outdelay : std_ulogic; + signal PIPERESETL0_outdelay : std_ulogic; + signal PIPETXDATAL1_outdelay : std_logic_vector(7 downto 0); + signal PIPETXDATAKL1_outdelay : std_ulogic; + signal PIPETXELECIDLEL1_outdelay : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL1_outdelay : std_ulogic; + signal PIPETXCOMPLIANCEL1_outdelay : std_ulogic; + signal PIPERXPOLARITYL1_outdelay : std_ulogic; + signal PIPEPOWERDOWNL1_outdelay : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL1_outdelay : std_ulogic; + signal PIPERESETL1_outdelay : std_ulogic; + signal PIPETXDATAL2_outdelay : std_logic_vector(7 downto 0); + signal PIPETXDATAKL2_outdelay : std_ulogic; + signal PIPETXELECIDLEL2_outdelay : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL2_outdelay : std_ulogic; + signal PIPETXCOMPLIANCEL2_outdelay : std_ulogic; + signal PIPERXPOLARITYL2_outdelay : std_ulogic; + signal PIPEPOWERDOWNL2_outdelay : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL2_outdelay : std_ulogic; + signal PIPERESETL2_outdelay : std_ulogic; + signal PIPETXDATAL3_outdelay : std_logic_vector(7 downto 0); + signal PIPETXDATAKL3_outdelay : std_ulogic; + signal PIPETXELECIDLEL3_outdelay : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL3_outdelay : std_ulogic; + signal PIPETXCOMPLIANCEL3_outdelay : std_ulogic; + signal PIPERXPOLARITYL3_outdelay : std_ulogic; + signal PIPEPOWERDOWNL3_outdelay : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL3_outdelay : std_ulogic; + signal PIPERESETL3_outdelay : std_ulogic; + signal PIPETXDATAL4_outdelay : std_logic_vector(7 downto 0); + signal PIPETXDATAKL4_outdelay : std_ulogic; + signal PIPETXELECIDLEL4_outdelay : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL4_outdelay : std_ulogic; + signal PIPETXCOMPLIANCEL4_outdelay : std_ulogic; + signal PIPERXPOLARITYL4_outdelay : std_ulogic; + signal PIPEPOWERDOWNL4_outdelay : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL4_outdelay : std_ulogic; + signal PIPERESETL4_outdelay : std_ulogic; + signal PIPETXDATAL5_outdelay : std_logic_vector(7 downto 0); + signal PIPETXDATAKL5_outdelay : std_ulogic; + signal PIPETXELECIDLEL5_outdelay : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL5_outdelay : std_ulogic; + signal PIPETXCOMPLIANCEL5_outdelay : std_ulogic; + signal PIPERXPOLARITYL5_outdelay : std_ulogic; + signal PIPEPOWERDOWNL5_outdelay : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL5_outdelay : std_ulogic; + signal PIPERESETL5_outdelay : std_ulogic; + signal PIPETXDATAL6_outdelay : std_logic_vector(7 downto 0); + signal PIPETXDATAKL6_outdelay : std_ulogic; + signal PIPETXELECIDLEL6_outdelay : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL6_outdelay : std_ulogic; + signal PIPETXCOMPLIANCEL6_outdelay : std_ulogic; + signal PIPERXPOLARITYL6_outdelay : std_ulogic; + signal PIPEPOWERDOWNL6_outdelay : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL6_outdelay : std_ulogic; + signal PIPERESETL6_outdelay : std_ulogic; + signal PIPETXDATAL7_outdelay : std_logic_vector(7 downto 0); + signal PIPETXDATAKL7_outdelay : std_ulogic; + signal PIPETXELECIDLEL7_outdelay : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL7_outdelay : std_ulogic; + signal PIPETXCOMPLIANCEL7_outdelay : std_ulogic; + signal PIPERXPOLARITYL7_outdelay : std_ulogic; + signal PIPEPOWERDOWNL7_outdelay : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL7_outdelay : std_ulogic; + signal PIPERESETL7_outdelay : std_ulogic; + signal MIMRXBWDATA_outdelay : std_logic_vector(63 downto 0); + signal MIMRXBWADD_outdelay : std_logic_vector(12 downto 0); + signal MIMRXBRADD_outdelay : std_logic_vector(12 downto 0); + signal MIMRXBWEN_outdelay : std_ulogic; + signal MIMRXBREN_outdelay : std_ulogic; + signal MIMTXBWDATA_outdelay : std_logic_vector(63 downto 0); + signal MIMTXBWADD_outdelay : std_logic_vector(12 downto 0); + signal MIMTXBRADD_outdelay : std_logic_vector(12 downto 0); + signal MIMTXBWEN_outdelay : std_ulogic; + signal MIMTXBREN_outdelay : std_ulogic; + signal MIMDLLBWDATA_outdelay : std_logic_vector(63 downto 0); + signal MIMDLLBWADD_outdelay : std_logic_vector(11 downto 0); + signal MIMDLLBRADD_outdelay : std_logic_vector(11 downto 0); + signal MIMDLLBWEN_outdelay : std_ulogic; + signal MIMDLLBREN_outdelay : std_ulogic; + signal CRMRXHOTRESETN_outdelay : std_ulogic; + signal CRMDOHOTRESETN_outdelay : std_ulogic; + signal CRMPWRSOFTRESETN_outdelay : std_ulogic; + signal LLKTCSTATUS_outdelay : std_logic_vector(7 downto 0); + signal LLKTXDSTRDYN_outdelay : std_ulogic; + signal LLKTXCHANSPACE_outdelay : std_logic_vector(9 downto 0); + signal LLKTXCHPOSTEDREADYN_outdelay : std_logic_vector(7 downto 0); + signal LLKTXCHNONPOSTEDREADYN_outdelay : std_logic_vector(7 downto 0); + signal LLKTXCHCOMPLETIONREADYN_outdelay : std_logic_vector(7 downto 0); + signal LLKTXCONFIGREADYN_outdelay : std_ulogic; + signal LLKRXDATA_outdelay : std_logic_vector(63 downto 0); + signal LLKRXSRCRDYN_outdelay : std_ulogic; + signal LLKRXSRCLASTREQN_outdelay : std_ulogic; + signal LLKRXSRCDSCN_outdelay : std_ulogic; + signal LLKRXSOFN_outdelay : std_ulogic; + signal LLKRXEOFN_outdelay : std_ulogic; + signal LLKRXSOPN_outdelay : std_ulogic; + signal LLKRXEOPN_outdelay : std_ulogic; + signal LLKRXVALIDN_outdelay : std_logic_vector(1 downto 0); + signal LLKRXPREFERREDTYPE_outdelay : std_logic_vector(15 downto 0); + signal LLKRXCHPOSTEDAVAILABLEN_outdelay : std_logic_vector(7 downto 0); + signal LLKRXCHNONPOSTEDAVAILABLEN_outdelay : std_logic_vector(7 downto 0); + signal LLKRXCHCOMPLETIONAVAILABLEN_outdelay : std_logic_vector(7 downto 0); + signal LLKRXCHCONFIGAVAILABLEN_outdelay : std_ulogic; + signal LLKRXCHPOSTEDPARTIALN_outdelay : std_logic_vector(7 downto 0); + signal LLKRXCHNONPOSTEDPARTIALN_outdelay : std_logic_vector(7 downto 0); + signal LLKRXCHCOMPLETIONPARTIALN_outdelay : std_logic_vector(7 downto 0); + signal LLKRXCHCONFIGPARTIALN_outdelay : std_ulogic; + signal LLKRX4DWHEADERN_outdelay : std_ulogic; + signal LLKRXECRCBADN_outdelay : std_ulogic; + signal MGMTRDATA_outdelay : std_logic_vector(31 downto 0); + signal MGMTPSO_outdelay : std_logic_vector(16 downto 0); + signal MGMTSTATSCREDIT_outdelay : std_logic_vector(11 downto 0); + signal L0RXDLLTLPECRCOK_outdelay : std_ulogic; + signal DLLTXPMDLLPOUTSTANDING_outdelay : std_ulogic; + signal L0FIRSTCFGWRITEOCCURRED_outdelay : std_ulogic; + signal L0CFGLOOPBACKACK_outdelay : std_ulogic; + signal L0MACUPSTREAMDOWNSTREAM_outdelay : std_ulogic; + signal L0RXMACLINKERROR_outdelay : std_logic_vector(1 downto 0); + signal L0MACLINKUP_outdelay : std_ulogic; + signal L0MACNEGOTIATEDLINKWIDTH_outdelay : std_logic_vector(3 downto 0); + signal L0MACLINKTRAINING_outdelay : std_ulogic; + signal L0LTSSMSTATE_outdelay : std_logic_vector(3 downto 0); + signal L0DLLVCSTATUS_outdelay : std_logic_vector(7 downto 0); + signal L0DLUPDOWN_outdelay : std_logic_vector(7 downto 0); + signal L0DLLERRORVECTOR_outdelay : std_logic_vector(6 downto 0); + signal L0DLLASRXSTATE_outdelay : std_logic_vector(1 downto 0); + signal L0DLLASTXSTATE_outdelay : std_ulogic; + signal L0ASAUTONOMOUSINITCOMPLETED_outdelay : std_ulogic; + signal L0COMPLETERID_outdelay : std_logic_vector(12 downto 0); + signal L0UNLOCKRECEIVED_outdelay : std_ulogic; + signal L0CORRERRMSGRCVD_outdelay : std_ulogic; + signal L0FATALERRMSGRCVD_outdelay : std_ulogic; + signal L0NONFATALERRMSGRCVD_outdelay : std_ulogic; + signal L0ERRMSGREQID_outdelay : std_logic_vector(15 downto 0); + signal L0FWDCORRERROUT_outdelay : std_ulogic; + signal L0FWDFATALERROUT_outdelay : std_ulogic; + signal L0FWDNONFATALERROUT_outdelay : std_ulogic; + signal L0RECEIVEDASSERTINTALEGACYINT_outdelay : std_ulogic; + signal L0RECEIVEDASSERTINTBLEGACYINT_outdelay : std_ulogic; + signal L0RECEIVEDASSERTINTCLEGACYINT_outdelay : std_ulogic; + signal L0RECEIVEDASSERTINTDLEGACYINT_outdelay : std_ulogic; + signal L0RECEIVEDDEASSERTINTALEGACYINT_outdelay : std_ulogic; + signal L0RECEIVEDDEASSERTINTBLEGACYINT_outdelay : std_ulogic; + signal L0RECEIVEDDEASSERTINTCLEGACYINT_outdelay : std_ulogic; + signal L0RECEIVEDDEASSERTINTDLEGACYINT_outdelay : std_ulogic; + signal L0MSIENABLE0_outdelay : std_ulogic; + signal L0MULTIMSGEN0_outdelay : std_logic_vector(2 downto 0); + signal L0STATSDLLPRECEIVED_outdelay : std_ulogic; + signal L0STATSDLLPTRANSMITTED_outdelay : std_ulogic; + signal L0STATSOSRECEIVED_outdelay : std_ulogic; + signal L0STATSOSTRANSMITTED_outdelay : std_ulogic; + signal L0STATSTLPRECEIVED_outdelay : std_ulogic; + signal L0STATSTLPTRANSMITTED_outdelay : std_ulogic; + signal L0STATSCFGRECEIVED_outdelay : std_ulogic; + signal L0STATSCFGTRANSMITTED_outdelay : std_ulogic; + signal L0STATSCFGOTHERRECEIVED_outdelay : std_ulogic; + signal L0STATSCFGOTHERTRANSMITTED_outdelay : std_ulogic; + signal MAXPAYLOADSIZE_outdelay : std_logic_vector(2 downto 0); + signal MAXREADREQUESTSIZE_outdelay : std_logic_vector(2 downto 0); + signal IOSPACEENABLE_outdelay : std_ulogic; + signal MEMSPACEENABLE_outdelay : std_ulogic; + signal L0ATTENTIONINDICATORCONTROL_outdelay : std_logic_vector(1 downto 0); + signal L0POWERINDICATORCONTROL_outdelay : std_logic_vector(1 downto 0); + signal L0POWERCONTROLLERCONTROL_outdelay : std_ulogic; + signal L0TOGGLEELECTROMECHANICALINTERLOCK_outdelay : std_ulogic; + signal L0RXBEACON_outdelay : std_ulogic; + signal L0PWRSTATE0_outdelay : std_logic_vector(1 downto 0); + signal L0PMEACK_outdelay : std_ulogic; + signal L0PMEREQOUT_outdelay : std_ulogic; + signal L0PMEEN_outdelay : std_ulogic; + signal L0PWRINHIBITTRANSFERS_outdelay : std_ulogic; + signal L0PWRL1STATE_outdelay : std_ulogic; + signal L0PWRL23READYDEVICE_outdelay : std_ulogic; + signal L0PWRL23READYSTATE_outdelay : std_ulogic; + signal L0PWRTXL0SSTATE_outdelay : std_ulogic; + signal L0PWRTURNOFFREQ_outdelay : std_ulogic; + signal L0RXDLLPM_outdelay : std_ulogic; + signal L0RXDLLPMTYPE_outdelay : std_logic_vector(2 downto 0); + signal L0TXDLLPMUPDATED_outdelay : std_ulogic; + signal L0MACNEWSTATEACK_outdelay : std_ulogic; + signal L0MACRXL0SSTATE_outdelay : std_ulogic; + signal L0MACENTEREDL0_outdelay : std_ulogic; + signal L0DLLRXACKOUTSTANDING_outdelay : std_ulogic; + signal L0DLLTXOUTSTANDING_outdelay : std_ulogic; + signal L0DLLTXNONFCOUTSTANDING_outdelay : std_ulogic; + signal L0RXDLLTLPEND_outdelay : std_logic_vector(1 downto 0); + signal L0TXDLLSBFCUPDATED_outdelay : std_ulogic; + signal L0RXDLLSBFCDATA_outdelay : std_logic_vector(18 downto 0); + signal L0RXDLLSBFCUPDATE_outdelay : std_ulogic; + signal L0TXDLLFCNPOSTBYPUPDATED_outdelay : std_logic_vector(7 downto 0); + signal L0TXDLLFCPOSTORDUPDATED_outdelay : std_logic_vector(7 downto 0); + signal L0TXDLLFCCMPLMCUPDATED_outdelay : std_logic_vector(7 downto 0); + signal L0RXDLLFCNPOSTBYPCRED_outdelay : std_logic_vector(19 downto 0); + signal L0RXDLLFCNPOSTBYPUPDATE_outdelay : std_logic_vector(7 downto 0); + signal L0RXDLLFCPOSTORDCRED_outdelay : std_logic_vector(23 downto 0); + signal L0RXDLLFCPOSTORDUPDATE_outdelay : std_logic_vector(7 downto 0); + signal L0RXDLLFCCMPLMCCRED_outdelay : std_logic_vector(23 downto 0); + signal L0RXDLLFCCMPLMCUPDATE_outdelay : std_logic_vector(7 downto 0); + signal L0UCBYPFOUND_outdelay : std_logic_vector(3 downto 0); + signal L0UCORDFOUND_outdelay : std_logic_vector(3 downto 0); + signal L0MCFOUND_outdelay : std_logic_vector(2 downto 0); + signal L0TRANSFORMEDVC_outdelay : std_logic_vector(2 downto 0); + signal BUSMASTERENABLE_outdelay : std_ulogic; + signal PARITYERRORRESPONSE_outdelay : std_ulogic; + signal SERRENABLE_outdelay : std_ulogic; + signal INTERRUPTDISABLE_outdelay : std_ulogic; + signal URREPORTINGENABLE_outdelay : std_ulogic; + + signal PIPERXELECIDLEL0_ipd : std_ulogic; + signal PIPERXSTATUSL0_ipd : std_logic_vector(2 downto 0); + signal PIPERXDATAL0_ipd : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL0_ipd : std_ulogic; + signal PIPERXDATAKL0_ipd : std_ulogic; + signal PIPERXVALIDL0_ipd : std_ulogic; + signal PIPERXCHANISALIGNEDL0_ipd : std_ulogic; + signal PIPERXELECIDLEL1_ipd : std_ulogic; + signal PIPERXSTATUSL1_ipd : std_logic_vector(2 downto 0); + signal PIPERXDATAL1_ipd : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL1_ipd : std_ulogic; + signal PIPERXDATAKL1_ipd : std_ulogic; + signal PIPERXVALIDL1_ipd : std_ulogic; + signal PIPERXCHANISALIGNEDL1_ipd : std_ulogic; + signal PIPERXELECIDLEL2_ipd : std_ulogic; + signal PIPERXSTATUSL2_ipd : std_logic_vector(2 downto 0); + signal PIPERXDATAL2_ipd : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL2_ipd : std_ulogic; + signal PIPERXDATAKL2_ipd : std_ulogic; + signal PIPERXVALIDL2_ipd : std_ulogic; + signal PIPERXCHANISALIGNEDL2_ipd : std_ulogic; + signal PIPERXELECIDLEL3_ipd : std_ulogic; + signal PIPERXSTATUSL3_ipd : std_logic_vector(2 downto 0); + signal PIPERXDATAL3_ipd : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL3_ipd : std_ulogic; + signal PIPERXDATAKL3_ipd : std_ulogic; + signal PIPERXVALIDL3_ipd : std_ulogic; + signal PIPERXCHANISALIGNEDL3_ipd : std_ulogic; + signal PIPERXELECIDLEL4_ipd : std_ulogic; + signal PIPERXSTATUSL4_ipd : std_logic_vector(2 downto 0); + signal PIPERXDATAL4_ipd : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL4_ipd : std_ulogic; + signal PIPERXDATAKL4_ipd : std_ulogic; + signal PIPERXVALIDL4_ipd : std_ulogic; + signal PIPERXCHANISALIGNEDL4_ipd : std_ulogic; + signal PIPERXELECIDLEL5_ipd : std_ulogic; + signal PIPERXSTATUSL5_ipd : std_logic_vector(2 downto 0); + signal PIPERXDATAL5_ipd : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL5_ipd : std_ulogic; + signal PIPERXDATAKL5_ipd : std_ulogic; + signal PIPERXVALIDL5_ipd : std_ulogic; + signal PIPERXCHANISALIGNEDL5_ipd : std_ulogic; + signal PIPERXELECIDLEL6_ipd : std_ulogic; + signal PIPERXSTATUSL6_ipd : std_logic_vector(2 downto 0); + signal PIPERXDATAL6_ipd : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL6_ipd : std_ulogic; + signal PIPERXDATAKL6_ipd : std_ulogic; + signal PIPERXVALIDL6_ipd : std_ulogic; + signal PIPERXCHANISALIGNEDL6_ipd : std_ulogic; + signal PIPERXELECIDLEL7_ipd : std_ulogic; + signal PIPERXSTATUSL7_ipd : std_logic_vector(2 downto 0); + signal PIPERXDATAL7_ipd : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL7_ipd : std_ulogic; + signal PIPERXDATAKL7_ipd : std_ulogic; + signal PIPERXVALIDL7_ipd : std_ulogic; + signal PIPERXCHANISALIGNEDL7_ipd : std_ulogic; + signal MIMRXBRDATA_ipd : std_logic_vector(63 downto 0); + signal CRMCORECLKRXO_ipd : std_ulogic; + signal CRMUSERCLKRXO_ipd : std_ulogic; + signal MIMTXBRDATA_ipd : std_logic_vector(63 downto 0); + signal CRMCORECLKTXO_ipd : std_ulogic; + signal CRMUSERCLKTXO_ipd : std_ulogic; + signal MIMDLLBRDATA_ipd : std_logic_vector(63 downto 0); + signal CRMCORECLKDLO_ipd : std_ulogic; + signal CRMCORECLK_ipd : std_ulogic; + signal CRMUSERCLK_ipd : std_ulogic; + signal CRMURSTN_ipd : std_ulogic; + signal CRMNVRSTN_ipd : std_ulogic; + signal CRMMGMTRSTN_ipd : std_ulogic; + signal CRMUSERCFGRSTN_ipd : std_ulogic; + signal CRMMACRSTN_ipd : std_ulogic; + signal CRMLINKRSTN_ipd : std_ulogic; + signal CRMTXHOTRESETN_ipd : std_ulogic; + signal CRMCFGBRIDGEHOTRESET_ipd : std_ulogic; + signal LLKTXDATA_ipd : std_logic_vector(63 downto 0); + signal LLKTXSRCRDYN_ipd : std_ulogic; + signal LLKTXSRCDSCN_ipd : std_ulogic; + signal LLKTXCOMPLETEN_ipd : std_ulogic; + signal LLKTXSOFN_ipd : std_ulogic; + signal LLKTXEOFN_ipd : std_ulogic; + signal LLKTXSOPN_ipd : std_ulogic; + signal LLKTXEOPN_ipd : std_ulogic; + signal LLKTXENABLEN_ipd : std_logic_vector(1 downto 0); + signal LLKTXCHTC_ipd : std_logic_vector(2 downto 0); + signal LLKTXCHFIFO_ipd : std_logic_vector(1 downto 0); + signal LLKTXCREATEECRCN_ipd : std_ulogic; + signal LLKTX4DWHEADERN_ipd : std_ulogic; + signal LLKRXDSTREQN_ipd : std_ulogic; + signal LLKRXCHTC_ipd : std_logic_vector(2 downto 0); + signal LLKRXCHFIFO_ipd : std_logic_vector(1 downto 0); + signal LLKRXDSTCONTREQN_ipd : std_ulogic; + signal MGMTWDATA_ipd : std_logic_vector(31 downto 0); + signal MGMTBWREN_ipd : std_logic_vector(3 downto 0); + signal MGMTWREN_ipd : std_ulogic; + signal MGMTADDR_ipd : std_logic_vector(10 downto 0); + signal MGMTRDEN_ipd : std_ulogic; + signal MGMTSTATSCREDITSEL_ipd : std_logic_vector(6 downto 0); + signal MAINPOWER_ipd : std_ulogic; + signal AUXPOWER_ipd : std_ulogic; + signal L0TLLINKRETRAIN_ipd : std_ulogic; + signal CFGNEGOTIATEDLINKWIDTH_ipd : std_logic_vector(5 downto 0); + signal CROSSLINKSEED_ipd : std_ulogic; + signal COMPLIANCEAVOID_ipd : std_ulogic; + signal L0VC0PREVIEWEXPAND_ipd : std_ulogic; + signal L0CFGVCID_ipd : std_logic_vector(23 downto 0); + signal L0CFGLOOPBACKMASTER_ipd : std_ulogic; + signal L0REPLAYTIMERADJUSTMENT_ipd : std_logic_vector(11 downto 0); + signal L0ACKNAKTIMERADJUSTMENT_ipd : std_logic_vector(11 downto 0); + signal L0DLLHOLDLINKUP_ipd : std_ulogic; + signal L0CFGASSTATECHANGECMD_ipd : std_logic_vector(3 downto 0); + signal L0CFGASSPANTREEOWNEDSTATE_ipd : std_ulogic; + signal L0ASE_ipd : std_ulogic; + signal L0ASTURNPOOLBITSCONSUMED_ipd : std_logic_vector(2 downto 0); + signal L0ASPORTCOUNT_ipd : std_logic_vector(7 downto 0); + signal L0CFGVCENABLE_ipd : std_logic_vector(7 downto 0); + signal L0CFGNEGOTIATEDMAXP_ipd : std_logic_vector(2 downto 0); + signal L0CFGDISABLESCRAMBLE_ipd : std_ulogic; + signal L0CFGEXTENDEDSYNC_ipd : std_ulogic; + signal L0CFGLINKDISABLE_ipd : std_ulogic; + signal L0PORTNUMBER_ipd : std_logic_vector(7 downto 0); + signal L0SENDUNLOCKMESSAGE_ipd : std_ulogic; + signal L0ALLDOWNRXPORTSINL0S_ipd : std_ulogic; + signal L0UPSTREAMRXPORTINL0S_ipd : std_ulogic; + signal L0TRANSACTIONSPENDING_ipd : std_ulogic; + signal L0ALLDOWNPORTSINL1_ipd : std_ulogic; + signal L0FWDCORRERRIN_ipd : std_ulogic; + signal L0FWDFATALERRIN_ipd : std_ulogic; + signal L0FWDNONFATALERRIN_ipd : std_ulogic; + signal L0SETCOMPLETERABORTERROR_ipd : std_ulogic; + signal L0SETDETECTEDCORRERROR_ipd : std_ulogic; + signal L0SETDETECTEDFATALERROR_ipd : std_ulogic; + signal L0SETDETECTEDNONFATALERROR_ipd : std_ulogic; + signal L0SETLINKDETECTEDPARITYERROR_ipd : std_ulogic; + signal L0SETLINKMASTERDATAPARITY_ipd : std_ulogic; + signal L0SETLINKRECEIVEDMASTERABORT_ipd : std_ulogic; + signal L0SETLINKRECEIVEDTARGETABORT_ipd : std_ulogic; + signal L0SETLINKSYSTEMERROR_ipd : std_ulogic; + signal L0SETLINKSIGNALLEDTARGETABORT_ipd : std_ulogic; + signal L0SETUSERDETECTEDPARITYERROR_ipd : std_ulogic; + signal L0SETUSERMASTERDATAPARITY_ipd : std_ulogic; + signal L0SETUSERRECEIVEDMASTERABORT_ipd : std_ulogic; + signal L0SETUSERRECEIVEDTARGETABORT_ipd : std_ulogic; + signal L0SETUSERSYSTEMERROR_ipd : std_ulogic; + signal L0SETUSERSIGNALLEDTARGETABORT_ipd : std_ulogic; + signal L0SETCOMPLETIONTIMEOUTUNCORRERROR_ipd : std_ulogic; + signal L0SETCOMPLETIONTIMEOUTCORRERROR_ipd : std_ulogic; + signal L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_ipd : std_ulogic; + signal L0SETUNEXPECTEDCOMPLETIONCORRERROR_ipd : std_ulogic; + signal L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_ipd : std_ulogic; + signal L0SETUNSUPPORTEDREQUESTOTHERERROR_ipd : std_ulogic; + signal L0PACKETHEADERFROMUSER_ipd : std_logic_vector(127 downto 0); + signal L0LEGACYINTFUNCT0_ipd : std_ulogic; + signal L0FWDASSERTINTALEGACYINT_ipd : std_ulogic; + signal L0FWDASSERTINTBLEGACYINT_ipd : std_ulogic; + signal L0FWDASSERTINTCLEGACYINT_ipd : std_ulogic; + signal L0FWDASSERTINTDLEGACYINT_ipd : std_ulogic; + signal L0FWDDEASSERTINTALEGACYINT_ipd : std_ulogic; + signal L0FWDDEASSERTINTBLEGACYINT_ipd : std_ulogic; + signal L0FWDDEASSERTINTCLEGACYINT_ipd : std_ulogic; + signal L0FWDDEASSERTINTDLEGACYINT_ipd : std_ulogic; + signal L0MSIREQUEST0_ipd : std_logic_vector(3 downto 0); + signal L0ELECTROMECHANICALINTERLOCKENGAGED_ipd : std_ulogic; + signal L0MRLSENSORCLOSEDN_ipd : std_ulogic; + signal L0POWERFAULTDETECTED_ipd : std_ulogic; + signal L0PRESENCEDETECTSLOTEMPTYN_ipd : std_ulogic; + signal L0ATTENTIONBUTTONPRESSED_ipd : std_ulogic; + signal L0TXBEACON_ipd : std_ulogic; + signal L0WAKEN_ipd : std_ulogic; + signal L0PMEREQIN_ipd : std_ulogic; + signal L0ROOTTURNOFFREQ_ipd : std_ulogic; + signal L0TXCFGPM_ipd : std_ulogic; + signal L0TXCFGPMTYPE_ipd : std_logic_vector(2 downto 0); + signal L0PWRNEWSTATEREQ_ipd : std_ulogic; + signal L0PWRNEXTLINKSTATE_ipd : std_logic_vector(1 downto 0); + signal L0CFGL0SENTRYSUP_ipd : std_ulogic; + signal L0CFGL0SENTRYENABLE_ipd : std_ulogic; + signal L0CFGL0SEXITLAT_ipd : std_logic_vector(2 downto 0); + signal L0TXTLTLPDATA_ipd : std_logic_vector(63 downto 0); + signal L0TXTLTLPEND_ipd : std_logic_vector(1 downto 0); + signal L0TXTLTLPENABLE_ipd : std_logic_vector(1 downto 0); + signal L0TXTLTLPEDB_ipd : std_ulogic; + signal L0TXTLTLPREQ_ipd : std_ulogic; + signal L0TXTLTLPREQEND_ipd : std_ulogic; + signal L0TXTLTLPWIDTH_ipd : std_ulogic; + signal L0TXTLTLPLATENCY_ipd : std_logic_vector(3 downto 0); + signal L0TLASFCCREDSTARVATION_ipd : std_ulogic; + signal L0TXTLSBFCDATA_ipd : std_logic_vector(18 downto 0); + signal L0TXTLSBFCUPDATE_ipd : std_ulogic; + signal L0TXTLFCNPOSTBYPCRED_ipd : std_logic_vector(191 downto 0); + signal L0TXTLFCNPOSTBYPUPDATE_ipd : std_logic_vector(15 downto 0); + signal L0TXTLFCPOSTORDCRED_ipd : std_logic_vector(159 downto 0); + signal L0TXTLFCPOSTORDUPDATE_ipd : std_logic_vector(15 downto 0); + signal L0TXTLFCCMPLMCCRED_ipd : std_logic_vector(159 downto 0); + signal L0TXTLFCCMPLMCUPDATE_ipd : std_logic_vector(15 downto 0); + signal L0RXTLTLPNONINITIALIZEDVC_ipd : std_logic_vector(7 downto 0); + + + signal PIPERXELECIDLEL0_indelay : std_ulogic; + signal PIPERXSTATUSL0_indelay : std_logic_vector(2 downto 0); + signal PIPERXDATAL0_indelay : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL0_indelay : std_ulogic; + signal PIPERXDATAKL0_indelay : std_ulogic; + signal PIPERXVALIDL0_indelay : std_ulogic; + signal PIPERXCHANISALIGNEDL0_indelay : std_ulogic; + signal PIPERXELECIDLEL1_indelay : std_ulogic; + signal PIPERXSTATUSL1_indelay : std_logic_vector(2 downto 0); + signal PIPERXDATAL1_indelay : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL1_indelay : std_ulogic; + signal PIPERXDATAKL1_indelay : std_ulogic; + signal PIPERXVALIDL1_indelay : std_ulogic; + signal PIPERXCHANISALIGNEDL1_indelay : std_ulogic; + signal PIPERXELECIDLEL2_indelay : std_ulogic; + signal PIPERXSTATUSL2_indelay : std_logic_vector(2 downto 0); + signal PIPERXDATAL2_indelay : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL2_indelay : std_ulogic; + signal PIPERXDATAKL2_indelay : std_ulogic; + signal PIPERXVALIDL2_indelay : std_ulogic; + signal PIPERXCHANISALIGNEDL2_indelay : std_ulogic; + signal PIPERXELECIDLEL3_indelay : std_ulogic; + signal PIPERXSTATUSL3_indelay : std_logic_vector(2 downto 0); + signal PIPERXDATAL3_indelay : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL3_indelay : std_ulogic; + signal PIPERXDATAKL3_indelay : std_ulogic; + signal PIPERXVALIDL3_indelay : std_ulogic; + signal PIPERXCHANISALIGNEDL3_indelay : std_ulogic; + signal PIPERXELECIDLEL4_indelay : std_ulogic; + signal PIPERXSTATUSL4_indelay : std_logic_vector(2 downto 0); + signal PIPERXDATAL4_indelay : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL4_indelay : std_ulogic; + signal PIPERXDATAKL4_indelay : std_ulogic; + signal PIPERXVALIDL4_indelay : std_ulogic; + signal PIPERXCHANISALIGNEDL4_indelay : std_ulogic; + signal PIPERXELECIDLEL5_indelay : std_ulogic; + signal PIPERXSTATUSL5_indelay : std_logic_vector(2 downto 0); + signal PIPERXDATAL5_indelay : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL5_indelay : std_ulogic; + signal PIPERXDATAKL5_indelay : std_ulogic; + signal PIPERXVALIDL5_indelay : std_ulogic; + signal PIPERXCHANISALIGNEDL5_indelay : std_ulogic; + signal PIPERXELECIDLEL6_indelay : std_ulogic; + signal PIPERXSTATUSL6_indelay : std_logic_vector(2 downto 0); + signal PIPERXDATAL6_indelay : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL6_indelay : std_ulogic; + signal PIPERXDATAKL6_indelay : std_ulogic; + signal PIPERXVALIDL6_indelay : std_ulogic; + signal PIPERXCHANISALIGNEDL6_indelay : std_ulogic; + signal PIPERXELECIDLEL7_indelay : std_ulogic; + signal PIPERXSTATUSL7_indelay : std_logic_vector(2 downto 0); + signal PIPERXDATAL7_indelay : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL7_indelay : std_ulogic; + signal PIPERXDATAKL7_indelay : std_ulogic; + signal PIPERXVALIDL7_indelay : std_ulogic; + signal PIPERXCHANISALIGNEDL7_indelay : std_ulogic; + signal MIMRXBRDATA_indelay : std_logic_vector(63 downto 0); + signal CRMCORECLKRXO_indelay : std_ulogic; + signal CRMUSERCLKRXO_indelay : std_ulogic; + signal MIMTXBRDATA_indelay : std_logic_vector(63 downto 0); + signal CRMCORECLKTXO_indelay : std_ulogic; + signal CRMUSERCLKTXO_indelay : std_ulogic; + signal MIMDLLBRDATA_indelay : std_logic_vector(63 downto 0); + signal CRMCORECLKDLO_indelay : std_ulogic; + signal CRMCORECLK_indelay : std_ulogic; + signal CRMUSERCLK_indelay : std_ulogic; + signal CRMURSTN_indelay : std_ulogic; + signal CRMNVRSTN_indelay : std_ulogic; + signal CRMMGMTRSTN_indelay : std_ulogic; + signal CRMUSERCFGRSTN_indelay : std_ulogic; + signal CRMMACRSTN_indelay : std_ulogic; + signal CRMLINKRSTN_indelay : std_ulogic; + signal CRMTXHOTRESETN_indelay : std_ulogic; + signal CRMCFGBRIDGEHOTRESET_indelay : std_ulogic; + signal LLKTXDATA_indelay : std_logic_vector(63 downto 0); + signal LLKTXSRCRDYN_indelay : std_ulogic; + signal LLKTXSRCDSCN_indelay : std_ulogic; + signal LLKTXCOMPLETEN_indelay : std_ulogic; + signal LLKTXSOFN_indelay : std_ulogic; + signal LLKTXEOFN_indelay : std_ulogic; + signal LLKTXSOPN_indelay : std_ulogic; + signal LLKTXEOPN_indelay : std_ulogic; + signal LLKTXENABLEN_indelay : std_logic_vector(1 downto 0); + signal LLKTXCHTC_indelay : std_logic_vector(2 downto 0); + signal LLKTXCHFIFO_indelay : std_logic_vector(1 downto 0); + signal LLKTXCREATEECRCN_indelay : std_ulogic; + signal LLKTX4DWHEADERN_indelay : std_ulogic; + signal LLKRXDSTREQN_indelay : std_ulogic; + signal LLKRXCHTC_indelay : std_logic_vector(2 downto 0); + signal LLKRXCHFIFO_indelay : std_logic_vector(1 downto 0); + signal LLKRXDSTCONTREQN_indelay : std_ulogic; + signal MGMTWDATA_indelay : std_logic_vector(31 downto 0); + signal MGMTBWREN_indelay : std_logic_vector(3 downto 0); + signal MGMTWREN_indelay : std_ulogic; + signal MGMTADDR_indelay : std_logic_vector(10 downto 0); + signal MGMTRDEN_indelay : std_ulogic; + signal MGMTSTATSCREDITSEL_indelay : std_logic_vector(6 downto 0); + signal MAINPOWER_indelay : std_ulogic; + signal AUXPOWER_indelay : std_ulogic; + signal L0TLLINKRETRAIN_indelay : std_ulogic; + signal CFGNEGOTIATEDLINKWIDTH_indelay : std_logic_vector(5 downto 0); + signal CROSSLINKSEED_indelay : std_ulogic; + signal COMPLIANCEAVOID_indelay : std_ulogic; + signal L0VC0PREVIEWEXPAND_indelay : std_ulogic; + signal L0CFGVCID_indelay : std_logic_vector(23 downto 0); + signal L0CFGLOOPBACKMASTER_indelay : std_ulogic; + signal L0REPLAYTIMERADJUSTMENT_indelay : std_logic_vector(11 downto 0); + signal L0ACKNAKTIMERADJUSTMENT_indelay : std_logic_vector(11 downto 0); + signal L0DLLHOLDLINKUP_indelay : std_ulogic; + signal L0CFGASSTATECHANGECMD_indelay : std_logic_vector(3 downto 0); + signal L0CFGASSPANTREEOWNEDSTATE_indelay : std_ulogic; + signal L0ASE_indelay : std_ulogic; + signal L0ASTURNPOOLBITSCONSUMED_indelay : std_logic_vector(2 downto 0); + signal L0ASPORTCOUNT_indelay : std_logic_vector(7 downto 0); + signal L0CFGVCENABLE_indelay : std_logic_vector(7 downto 0); + signal L0CFGNEGOTIATEDMAXP_indelay : std_logic_vector(2 downto 0); + signal L0CFGDISABLESCRAMBLE_indelay : std_ulogic; + signal L0CFGEXTENDEDSYNC_indelay : std_ulogic; + signal L0CFGLINKDISABLE_indelay : std_ulogic; + signal L0PORTNUMBER_indelay : std_logic_vector(7 downto 0); + signal L0SENDUNLOCKMESSAGE_indelay : std_ulogic; + signal L0ALLDOWNRXPORTSINL0S_indelay : std_ulogic; + signal L0UPSTREAMRXPORTINL0S_indelay : std_ulogic; + signal L0TRANSACTIONSPENDING_indelay : std_ulogic; + signal L0ALLDOWNPORTSINL1_indelay : std_ulogic; + signal L0FWDCORRERRIN_indelay : std_ulogic; + signal L0FWDFATALERRIN_indelay : std_ulogic; + signal L0FWDNONFATALERRIN_indelay : std_ulogic; + signal L0SETCOMPLETERABORTERROR_indelay : std_ulogic; + signal L0SETDETECTEDCORRERROR_indelay : std_ulogic; + signal L0SETDETECTEDFATALERROR_indelay : std_ulogic; + signal L0SETDETECTEDNONFATALERROR_indelay : std_ulogic; + signal L0SETLINKDETECTEDPARITYERROR_indelay : std_ulogic; + signal L0SETLINKMASTERDATAPARITY_indelay : std_ulogic; + signal L0SETLINKRECEIVEDMASTERABORT_indelay : std_ulogic; + signal L0SETLINKRECEIVEDTARGETABORT_indelay : std_ulogic; + signal L0SETLINKSYSTEMERROR_indelay : std_ulogic; + signal L0SETLINKSIGNALLEDTARGETABORT_indelay : std_ulogic; + signal L0SETUSERDETECTEDPARITYERROR_indelay : std_ulogic; + signal L0SETUSERMASTERDATAPARITY_indelay : std_ulogic; + signal L0SETUSERRECEIVEDMASTERABORT_indelay : std_ulogic; + signal L0SETUSERRECEIVEDTARGETABORT_indelay : std_ulogic; + signal L0SETUSERSYSTEMERROR_indelay : std_ulogic; + signal L0SETUSERSIGNALLEDTARGETABORT_indelay : std_ulogic; + signal L0SETCOMPLETIONTIMEOUTUNCORRERROR_indelay : std_ulogic; + signal L0SETCOMPLETIONTIMEOUTCORRERROR_indelay : std_ulogic; + signal L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_indelay : std_ulogic; + signal L0SETUNEXPECTEDCOMPLETIONCORRERROR_indelay : std_ulogic; + signal L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_indelay : std_ulogic; + signal L0SETUNSUPPORTEDREQUESTOTHERERROR_indelay : std_ulogic; + signal L0PACKETHEADERFROMUSER_indelay : std_logic_vector(127 downto 0); + signal L0LEGACYINTFUNCT0_indelay : std_ulogic; + signal L0FWDASSERTINTALEGACYINT_indelay : std_ulogic; + signal L0FWDASSERTINTBLEGACYINT_indelay : std_ulogic; + signal L0FWDASSERTINTCLEGACYINT_indelay : std_ulogic; + signal L0FWDASSERTINTDLEGACYINT_indelay : std_ulogic; + signal L0FWDDEASSERTINTALEGACYINT_indelay : std_ulogic; + signal L0FWDDEASSERTINTBLEGACYINT_indelay : std_ulogic; + signal L0FWDDEASSERTINTCLEGACYINT_indelay : std_ulogic; + signal L0FWDDEASSERTINTDLEGACYINT_indelay : std_ulogic; + signal L0MSIREQUEST0_indelay : std_logic_vector(3 downto 0); + signal L0ELECTROMECHANICALINTERLOCKENGAGED_indelay : std_ulogic; + signal L0MRLSENSORCLOSEDN_indelay : std_ulogic; + signal L0POWERFAULTDETECTED_indelay : std_ulogic; + signal L0PRESENCEDETECTSLOTEMPTYN_indelay : std_ulogic; + signal L0ATTENTIONBUTTONPRESSED_indelay : std_ulogic; + signal L0TXBEACON_indelay : std_ulogic; + signal L0WAKEN_indelay : std_ulogic; + signal L0PMEREQIN_indelay : std_ulogic; + signal L0ROOTTURNOFFREQ_indelay : std_ulogic; + signal L0TXCFGPM_indelay : std_ulogic; + signal L0TXCFGPMTYPE_indelay : std_logic_vector(2 downto 0); + signal L0PWRNEWSTATEREQ_indelay : std_ulogic; + signal L0PWRNEXTLINKSTATE_indelay : std_logic_vector(1 downto 0); + signal L0CFGL0SENTRYSUP_indelay : std_ulogic; + signal L0CFGL0SENTRYENABLE_indelay : std_ulogic; + signal L0CFGL0SEXITLAT_indelay : std_logic_vector(2 downto 0); + signal L0TXTLTLPDATA_indelay : std_logic_vector(63 downto 0); + signal L0TXTLTLPEND_indelay : std_logic_vector(1 downto 0); + signal L0TXTLTLPENABLE_indelay : std_logic_vector(1 downto 0); + signal L0TXTLTLPEDB_indelay : std_ulogic; + signal L0TXTLTLPREQ_indelay : std_ulogic; + signal L0TXTLTLPREQEND_indelay : std_ulogic; + signal L0TXTLTLPWIDTH_indelay : std_ulogic; + signal L0TXTLTLPLATENCY_indelay : std_logic_vector(3 downto 0); + signal L0TLASFCCREDSTARVATION_indelay : std_ulogic; + signal L0TXTLSBFCDATA_indelay : std_logic_vector(18 downto 0); + signal L0TXTLSBFCUPDATE_indelay : std_ulogic; + signal L0TXTLFCNPOSTBYPCRED_indelay : std_logic_vector(191 downto 0); + signal L0TXTLFCNPOSTBYPUPDATE_indelay : std_logic_vector(15 downto 0); + signal L0TXTLFCPOSTORDCRED_indelay : std_logic_vector(159 downto 0); + signal L0TXTLFCPOSTORDUPDATE_indelay : std_logic_vector(15 downto 0); + signal L0TXTLFCCMPLMCCRED_indelay : std_logic_vector(159 downto 0); + signal L0TXTLFCCMPLMCUPDATE_indelay : std_logic_vector(15 downto 0); + signal L0RXTLTLPNONINITIALIZEDVC_indelay : std_logic_vector(7 downto 0); + +begin + + + BUSMASTERENABLE_out <= BUSMASTERENABLE_outdelay after OUT_DELAY; + CRMDOHOTRESETN_out <= CRMDOHOTRESETN_outdelay after OUT_DELAY; + CRMPWRSOFTRESETN_out <= CRMPWRSOFTRESETN_outdelay after OUT_DELAY; + CRMRXHOTRESETN_out <= CRMRXHOTRESETN_outdelay after OUT_DELAY; + DLLTXPMDLLPOUTSTANDING_out <= DLLTXPMDLLPOUTSTANDING_outdelay after OUT_DELAY; + INTERRUPTDISABLE_out <= INTERRUPTDISABLE_outdelay after OUT_DELAY; + IOSPACEENABLE_out <= IOSPACEENABLE_outdelay after OUT_DELAY; + L0ASAUTONOMOUSINITCOMPLETED_out <= L0ASAUTONOMOUSINITCOMPLETED_outdelay after OUT_DELAY; + L0ATTENTIONINDICATORCONTROL_out <= L0ATTENTIONINDICATORCONTROL_outdelay after OUT_DELAY; + L0CFGLOOPBACKACK_out <= L0CFGLOOPBACKACK_outdelay after OUT_DELAY; + L0COMPLETERID_out <= L0COMPLETERID_outdelay after OUT_DELAY; + L0CORRERRMSGRCVD_out <= L0CORRERRMSGRCVD_outdelay after OUT_DELAY; + L0DLLASRXSTATE_out <= L0DLLASRXSTATE_outdelay after OUT_DELAY; + L0DLLASTXSTATE_out <= L0DLLASTXSTATE_outdelay after OUT_DELAY; + L0DLLERRORVECTOR_out <= L0DLLERRORVECTOR_outdelay after OUT_DELAY; + L0DLLRXACKOUTSTANDING_out <= L0DLLRXACKOUTSTANDING_outdelay after OUT_DELAY; + L0DLLTXNONFCOUTSTANDING_out <= L0DLLTXNONFCOUTSTANDING_outdelay after OUT_DELAY; + L0DLLTXOUTSTANDING_out <= L0DLLTXOUTSTANDING_outdelay after OUT_DELAY; + L0DLLVCSTATUS_out <= L0DLLVCSTATUS_outdelay after OUT_DELAY; + L0DLUPDOWN_out <= L0DLUPDOWN_outdelay after OUT_DELAY; + L0ERRMSGREQID_out <= L0ERRMSGREQID_outdelay after OUT_DELAY; + L0FATALERRMSGRCVD_out <= L0FATALERRMSGRCVD_outdelay after OUT_DELAY; + L0FIRSTCFGWRITEOCCURRED_out <= L0FIRSTCFGWRITEOCCURRED_outdelay after OUT_DELAY; + L0FWDCORRERROUT_out <= L0FWDCORRERROUT_outdelay after OUT_DELAY; + L0FWDFATALERROUT_out <= L0FWDFATALERROUT_outdelay after OUT_DELAY; + L0FWDNONFATALERROUT_out <= L0FWDNONFATALERROUT_outdelay after OUT_DELAY; + L0LTSSMSTATE_out <= L0LTSSMSTATE_outdelay after OUT_DELAY; + L0MACENTEREDL0_out <= L0MACENTEREDL0_outdelay after OUT_DELAY; + L0MACLINKTRAINING_out <= L0MACLINKTRAINING_outdelay after OUT_DELAY; + L0MACLINKUP_out <= L0MACLINKUP_outdelay after OUT_DELAY; + L0MACNEGOTIATEDLINKWIDTH_out <= L0MACNEGOTIATEDLINKWIDTH_outdelay after OUT_DELAY; + L0MACNEWSTATEACK_out <= L0MACNEWSTATEACK_outdelay after OUT_DELAY; + L0MACRXL0SSTATE_out <= L0MACRXL0SSTATE_outdelay after OUT_DELAY; + L0MACUPSTREAMDOWNSTREAM_out <= L0MACUPSTREAMDOWNSTREAM_outdelay after OUT_DELAY; + L0MCFOUND_out <= L0MCFOUND_outdelay after OUT_DELAY; + L0MSIENABLE0_out <= L0MSIENABLE0_outdelay after OUT_DELAY; + L0MULTIMSGEN0_out <= L0MULTIMSGEN0_outdelay after OUT_DELAY; + L0NONFATALERRMSGRCVD_out <= L0NONFATALERRMSGRCVD_outdelay after OUT_DELAY; + L0PMEACK_out <= L0PMEACK_outdelay after OUT_DELAY; + L0PMEEN_out <= L0PMEEN_outdelay after OUT_DELAY; + L0PMEREQOUT_out <= L0PMEREQOUT_outdelay after OUT_DELAY; + L0POWERCONTROLLERCONTROL_out <= L0POWERCONTROLLERCONTROL_outdelay after OUT_DELAY; + L0POWERINDICATORCONTROL_out <= L0POWERINDICATORCONTROL_outdelay after OUT_DELAY; + L0PWRINHIBITTRANSFERS_out <= L0PWRINHIBITTRANSFERS_outdelay after OUT_DELAY; + L0PWRL1STATE_out <= L0PWRL1STATE_outdelay after OUT_DELAY; + L0PWRL23READYDEVICE_out <= L0PWRL23READYDEVICE_outdelay after OUT_DELAY; + L0PWRL23READYSTATE_out <= L0PWRL23READYSTATE_outdelay after OUT_DELAY; + L0PWRSTATE0_out <= L0PWRSTATE0_outdelay after OUT_DELAY; + L0PWRTURNOFFREQ_out <= L0PWRTURNOFFREQ_outdelay after OUT_DELAY; + L0PWRTXL0SSTATE_out <= L0PWRTXL0SSTATE_outdelay after OUT_DELAY; + L0RECEIVEDASSERTINTALEGACYINT_out <= L0RECEIVEDASSERTINTALEGACYINT_outdelay after OUT_DELAY; + L0RECEIVEDASSERTINTBLEGACYINT_out <= L0RECEIVEDASSERTINTBLEGACYINT_outdelay after OUT_DELAY; + L0RECEIVEDASSERTINTCLEGACYINT_out <= L0RECEIVEDASSERTINTCLEGACYINT_outdelay after OUT_DELAY; + L0RECEIVEDASSERTINTDLEGACYINT_out <= L0RECEIVEDASSERTINTDLEGACYINT_outdelay after OUT_DELAY; + L0RECEIVEDDEASSERTINTALEGACYINT_out <= L0RECEIVEDDEASSERTINTALEGACYINT_outdelay after OUT_DELAY; + L0RECEIVEDDEASSERTINTBLEGACYINT_out <= L0RECEIVEDDEASSERTINTBLEGACYINT_outdelay after OUT_DELAY; + L0RECEIVEDDEASSERTINTCLEGACYINT_out <= L0RECEIVEDDEASSERTINTCLEGACYINT_outdelay after OUT_DELAY; + L0RECEIVEDDEASSERTINTDLEGACYINT_out <= L0RECEIVEDDEASSERTINTDLEGACYINT_outdelay after OUT_DELAY; + L0RXBEACON_out <= L0RXBEACON_outdelay after OUT_DELAY; + L0RXDLLFCCMPLMCCRED_out <= L0RXDLLFCCMPLMCCRED_outdelay after OUT_DELAY; + L0RXDLLFCCMPLMCUPDATE_out <= L0RXDLLFCCMPLMCUPDATE_outdelay after OUT_DELAY; + L0RXDLLFCNPOSTBYPCRED_out <= L0RXDLLFCNPOSTBYPCRED_outdelay after OUT_DELAY; + L0RXDLLFCNPOSTBYPUPDATE_out <= L0RXDLLFCNPOSTBYPUPDATE_outdelay after OUT_DELAY; + L0RXDLLFCPOSTORDCRED_out <= L0RXDLLFCPOSTORDCRED_outdelay after OUT_DELAY; + L0RXDLLFCPOSTORDUPDATE_out <= L0RXDLLFCPOSTORDUPDATE_outdelay after OUT_DELAY; + L0RXDLLPMTYPE_out <= L0RXDLLPMTYPE_outdelay after OUT_DELAY; + L0RXDLLPM_out <= L0RXDLLPM_outdelay after OUT_DELAY; + L0RXDLLSBFCDATA_out <= L0RXDLLSBFCDATA_outdelay after OUT_DELAY; + L0RXDLLSBFCUPDATE_out <= L0RXDLLSBFCUPDATE_outdelay after OUT_DELAY; + L0RXDLLTLPECRCOK_out <= L0RXDLLTLPECRCOK_outdelay after OUT_DELAY; + L0RXDLLTLPEND_out <= L0RXDLLTLPEND_outdelay after OUT_DELAY; + L0RXMACLINKERROR_out <= L0RXMACLINKERROR_outdelay after OUT_DELAY; + L0STATSCFGOTHERRECEIVED_out <= L0STATSCFGOTHERRECEIVED_outdelay after OUT_DELAY; + L0STATSCFGOTHERTRANSMITTED_out <= L0STATSCFGOTHERTRANSMITTED_outdelay after OUT_DELAY; + L0STATSCFGRECEIVED_out <= L0STATSCFGRECEIVED_outdelay after OUT_DELAY; + L0STATSCFGTRANSMITTED_out <= L0STATSCFGTRANSMITTED_outdelay after OUT_DELAY; + L0STATSDLLPRECEIVED_out <= L0STATSDLLPRECEIVED_outdelay after OUT_DELAY; + L0STATSDLLPTRANSMITTED_out <= L0STATSDLLPTRANSMITTED_outdelay after OUT_DELAY; + L0STATSOSRECEIVED_out <= L0STATSOSRECEIVED_outdelay after OUT_DELAY; + L0STATSOSTRANSMITTED_out <= L0STATSOSTRANSMITTED_outdelay after OUT_DELAY; + L0STATSTLPRECEIVED_out <= L0STATSTLPRECEIVED_outdelay after OUT_DELAY; + L0STATSTLPTRANSMITTED_out <= L0STATSTLPTRANSMITTED_outdelay after OUT_DELAY; + L0TOGGLEELECTROMECHANICALINTERLOCK_out <= L0TOGGLEELECTROMECHANICALINTERLOCK_outdelay after OUT_DELAY; + L0TRANSFORMEDVC_out <= L0TRANSFORMEDVC_outdelay after OUT_DELAY; + L0TXDLLFCCMPLMCUPDATED_out <= L0TXDLLFCCMPLMCUPDATED_outdelay after OUT_DELAY; + L0TXDLLFCNPOSTBYPUPDATED_out <= L0TXDLLFCNPOSTBYPUPDATED_outdelay after OUT_DELAY; + L0TXDLLFCPOSTORDUPDATED_out <= L0TXDLLFCPOSTORDUPDATED_outdelay after OUT_DELAY; + L0TXDLLPMUPDATED_out <= L0TXDLLPMUPDATED_outdelay after OUT_DELAY; + L0TXDLLSBFCUPDATED_out <= L0TXDLLSBFCUPDATED_outdelay after OUT_DELAY; + L0UCBYPFOUND_out <= L0UCBYPFOUND_outdelay after OUT_DELAY; + L0UCORDFOUND_out <= L0UCORDFOUND_outdelay after OUT_DELAY; + L0UNLOCKRECEIVED_out <= L0UNLOCKRECEIVED_outdelay after OUT_DELAY; + LLKRX4DWHEADERN_out <= LLKRX4DWHEADERN_outdelay after OUT_DELAY; + LLKRXCHCOMPLETIONAVAILABLEN_out <= LLKRXCHCOMPLETIONAVAILABLEN_outdelay after OUT_DELAY; + LLKRXCHCOMPLETIONPARTIALN_out <= LLKRXCHCOMPLETIONPARTIALN_outdelay after OUT_DELAY; + LLKRXCHCONFIGAVAILABLEN_out <= LLKRXCHCONFIGAVAILABLEN_outdelay after OUT_DELAY; + LLKRXCHCONFIGPARTIALN_out <= LLKRXCHCONFIGPARTIALN_outdelay after OUT_DELAY; + LLKRXCHNONPOSTEDAVAILABLEN_out <= LLKRXCHNONPOSTEDAVAILABLEN_outdelay after OUT_DELAY; + LLKRXCHNONPOSTEDPARTIALN_out <= LLKRXCHNONPOSTEDPARTIALN_outdelay after OUT_DELAY; + LLKRXCHPOSTEDAVAILABLEN_out <= LLKRXCHPOSTEDAVAILABLEN_outdelay after OUT_DELAY; + LLKRXCHPOSTEDPARTIALN_out <= LLKRXCHPOSTEDPARTIALN_outdelay after OUT_DELAY; + LLKRXDATA_out <= LLKRXDATA_outdelay after OUT_DELAY; + LLKRXECRCBADN_out <= LLKRXECRCBADN_outdelay after OUT_DELAY; + LLKRXEOFN_out <= LLKRXEOFN_outdelay after OUT_DELAY; + LLKRXEOPN_out <= LLKRXEOPN_outdelay after OUT_DELAY; + LLKRXPREFERREDTYPE_out <= LLKRXPREFERREDTYPE_outdelay after OUT_DELAY; + LLKRXSOFN_out <= LLKRXSOFN_outdelay after OUT_DELAY; + LLKRXSOPN_out <= LLKRXSOPN_outdelay after OUT_DELAY; + LLKRXSRCDSCN_out <= LLKRXSRCDSCN_outdelay after OUT_DELAY; + LLKRXSRCLASTREQN_out <= LLKRXSRCLASTREQN_outdelay after OUT_DELAY; + LLKRXSRCRDYN_out <= LLKRXSRCRDYN_outdelay after OUT_DELAY; + LLKRXVALIDN_out <= LLKRXVALIDN_outdelay after OUT_DELAY; + LLKTCSTATUS_out <= LLKTCSTATUS_outdelay after OUT_DELAY; + LLKTXCHANSPACE_out <= LLKTXCHANSPACE_outdelay after OUT_DELAY; + LLKTXCHCOMPLETIONREADYN_out <= LLKTXCHCOMPLETIONREADYN_outdelay after OUT_DELAY; + LLKTXCHNONPOSTEDREADYN_out <= LLKTXCHNONPOSTEDREADYN_outdelay after OUT_DELAY; + LLKTXCHPOSTEDREADYN_out <= LLKTXCHPOSTEDREADYN_outdelay after OUT_DELAY; + LLKTXCONFIGREADYN_out <= LLKTXCONFIGREADYN_outdelay after OUT_DELAY; + LLKTXDSTRDYN_out <= LLKTXDSTRDYN_outdelay after OUT_DELAY; + MAXPAYLOADSIZE_out <= MAXPAYLOADSIZE_outdelay after OUT_DELAY; + MAXREADREQUESTSIZE_out <= MAXREADREQUESTSIZE_outdelay after OUT_DELAY; + MEMSPACEENABLE_out <= MEMSPACEENABLE_outdelay after OUT_DELAY; + MGMTPSO_out <= MGMTPSO_outdelay after OUT_DELAY; + MGMTRDATA_out <= MGMTRDATA_outdelay after OUT_DELAY; + MGMTSTATSCREDIT_out <= MGMTSTATSCREDIT_outdelay after OUT_DELAY; + MIMDLLBRADD_out <= MIMDLLBRADD_outdelay after OUT_DELAY; + MIMDLLBREN_out <= MIMDLLBREN_outdelay after OUT_DELAY; + MIMDLLBWADD_out <= MIMDLLBWADD_outdelay after OUT_DELAY; + MIMDLLBWDATA_out <= MIMDLLBWDATA_outdelay after OUT_DELAY; + MIMDLLBWEN_out <= MIMDLLBWEN_outdelay after OUT_DELAY; + MIMRXBRADD_out <= MIMRXBRADD_outdelay after OUT_DELAY; + MIMRXBREN_out <= MIMRXBREN_outdelay after OUT_DELAY; + MIMRXBWADD_out <= MIMRXBWADD_outdelay after OUT_DELAY; + MIMRXBWDATA_out <= MIMRXBWDATA_outdelay after OUT_DELAY; + MIMRXBWEN_out <= MIMRXBWEN_outdelay after OUT_DELAY; + MIMTXBRADD_out <= MIMTXBRADD_outdelay after OUT_DELAY; + MIMTXBREN_out <= MIMTXBREN_outdelay after OUT_DELAY; + MIMTXBWADD_out <= MIMTXBWADD_outdelay after OUT_DELAY; + MIMTXBWDATA_out <= MIMTXBWDATA_outdelay after OUT_DELAY; + MIMTXBWEN_out <= MIMTXBWEN_outdelay after OUT_DELAY; + PARITYERRORRESPONSE_out <= PARITYERRORRESPONSE_outdelay after OUT_DELAY; + PIPEDESKEWLANESL0_out <= PIPEDESKEWLANESL0_outdelay after OUT_DELAY; + PIPEDESKEWLANESL1_out <= PIPEDESKEWLANESL1_outdelay after OUT_DELAY; + PIPEDESKEWLANESL2_out <= PIPEDESKEWLANESL2_outdelay after OUT_DELAY; + PIPEDESKEWLANESL3_out <= PIPEDESKEWLANESL3_outdelay after OUT_DELAY; + PIPEDESKEWLANESL4_out <= PIPEDESKEWLANESL4_outdelay after OUT_DELAY; + PIPEDESKEWLANESL5_out <= PIPEDESKEWLANESL5_outdelay after OUT_DELAY; + PIPEDESKEWLANESL6_out <= PIPEDESKEWLANESL6_outdelay after OUT_DELAY; + PIPEDESKEWLANESL7_out <= PIPEDESKEWLANESL7_outdelay after OUT_DELAY; + PIPEPOWERDOWNL0_out <= PIPEPOWERDOWNL0_outdelay after OUT_DELAY; + PIPEPOWERDOWNL1_out <= PIPEPOWERDOWNL1_outdelay after OUT_DELAY; + PIPEPOWERDOWNL2_out <= PIPEPOWERDOWNL2_outdelay after OUT_DELAY; + PIPEPOWERDOWNL3_out <= PIPEPOWERDOWNL3_outdelay after OUT_DELAY; + PIPEPOWERDOWNL4_out <= PIPEPOWERDOWNL4_outdelay after OUT_DELAY; + PIPEPOWERDOWNL5_out <= PIPEPOWERDOWNL5_outdelay after OUT_DELAY; + PIPEPOWERDOWNL6_out <= PIPEPOWERDOWNL6_outdelay after OUT_DELAY; + PIPEPOWERDOWNL7_out <= PIPEPOWERDOWNL7_outdelay after OUT_DELAY; + PIPERESETL0_out <= PIPERESETL0_outdelay after OUT_DELAY; + PIPERESETL1_out <= PIPERESETL1_outdelay after OUT_DELAY; + PIPERESETL2_out <= PIPERESETL2_outdelay after OUT_DELAY; + PIPERESETL3_out <= PIPERESETL3_outdelay after OUT_DELAY; + PIPERESETL4_out <= PIPERESETL4_outdelay after OUT_DELAY; + PIPERESETL5_out <= PIPERESETL5_outdelay after OUT_DELAY; + PIPERESETL6_out <= PIPERESETL6_outdelay after OUT_DELAY; + PIPERESETL7_out <= PIPERESETL7_outdelay after OUT_DELAY; + PIPERXPOLARITYL0_out <= PIPERXPOLARITYL0_outdelay after OUT_DELAY; + PIPERXPOLARITYL1_out <= PIPERXPOLARITYL1_outdelay after OUT_DELAY; + PIPERXPOLARITYL2_out <= PIPERXPOLARITYL2_outdelay after OUT_DELAY; + PIPERXPOLARITYL3_out <= PIPERXPOLARITYL3_outdelay after OUT_DELAY; + PIPERXPOLARITYL4_out <= PIPERXPOLARITYL4_outdelay after OUT_DELAY; + PIPERXPOLARITYL5_out <= PIPERXPOLARITYL5_outdelay after OUT_DELAY; + PIPERXPOLARITYL6_out <= PIPERXPOLARITYL6_outdelay after OUT_DELAY; + PIPERXPOLARITYL7_out <= PIPERXPOLARITYL7_outdelay after OUT_DELAY; + PIPETXCOMPLIANCEL0_out <= PIPETXCOMPLIANCEL0_outdelay after OUT_DELAY; + PIPETXCOMPLIANCEL1_out <= PIPETXCOMPLIANCEL1_outdelay after OUT_DELAY; + PIPETXCOMPLIANCEL2_out <= PIPETXCOMPLIANCEL2_outdelay after OUT_DELAY; + PIPETXCOMPLIANCEL3_out <= PIPETXCOMPLIANCEL3_outdelay after OUT_DELAY; + PIPETXCOMPLIANCEL4_out <= PIPETXCOMPLIANCEL4_outdelay after OUT_DELAY; + PIPETXCOMPLIANCEL5_out <= PIPETXCOMPLIANCEL5_outdelay after OUT_DELAY; + PIPETXCOMPLIANCEL6_out <= PIPETXCOMPLIANCEL6_outdelay after OUT_DELAY; + PIPETXCOMPLIANCEL7_out <= PIPETXCOMPLIANCEL7_outdelay after OUT_DELAY; + PIPETXDATAKL0_out <= PIPETXDATAKL0_outdelay after OUT_DELAY; + PIPETXDATAKL1_out <= PIPETXDATAKL1_outdelay after OUT_DELAY; + PIPETXDATAKL2_out <= PIPETXDATAKL2_outdelay after OUT_DELAY; + PIPETXDATAKL3_out <= PIPETXDATAKL3_outdelay after OUT_DELAY; + PIPETXDATAKL4_out <= PIPETXDATAKL4_outdelay after OUT_DELAY; + PIPETXDATAKL5_out <= PIPETXDATAKL5_outdelay after OUT_DELAY; + PIPETXDATAKL6_out <= PIPETXDATAKL6_outdelay after OUT_DELAY; + PIPETXDATAKL7_out <= PIPETXDATAKL7_outdelay after OUT_DELAY; + PIPETXDATAL0_out <= PIPETXDATAL0_outdelay after OUT_DELAY; + PIPETXDATAL1_out <= PIPETXDATAL1_outdelay after OUT_DELAY; + PIPETXDATAL2_out <= PIPETXDATAL2_outdelay after OUT_DELAY; + PIPETXDATAL3_out <= PIPETXDATAL3_outdelay after OUT_DELAY; + PIPETXDATAL4_out <= PIPETXDATAL4_outdelay after OUT_DELAY; + PIPETXDATAL5_out <= PIPETXDATAL5_outdelay after OUT_DELAY; + PIPETXDATAL6_out <= PIPETXDATAL6_outdelay after OUT_DELAY; + PIPETXDATAL7_out <= PIPETXDATAL7_outdelay after OUT_DELAY; + PIPETXDETECTRXLOOPBACKL0_out <= PIPETXDETECTRXLOOPBACKL0_outdelay after OUT_DELAY; + PIPETXDETECTRXLOOPBACKL1_out <= PIPETXDETECTRXLOOPBACKL1_outdelay after OUT_DELAY; + PIPETXDETECTRXLOOPBACKL2_out <= PIPETXDETECTRXLOOPBACKL2_outdelay after OUT_DELAY; + PIPETXDETECTRXLOOPBACKL3_out <= PIPETXDETECTRXLOOPBACKL3_outdelay after OUT_DELAY; + PIPETXDETECTRXLOOPBACKL4_out <= PIPETXDETECTRXLOOPBACKL4_outdelay after OUT_DELAY; + PIPETXDETECTRXLOOPBACKL5_out <= PIPETXDETECTRXLOOPBACKL5_outdelay after OUT_DELAY; + PIPETXDETECTRXLOOPBACKL6_out <= PIPETXDETECTRXLOOPBACKL6_outdelay after OUT_DELAY; + PIPETXDETECTRXLOOPBACKL7_out <= PIPETXDETECTRXLOOPBACKL7_outdelay after OUT_DELAY; + PIPETXELECIDLEL0_out <= PIPETXELECIDLEL0_outdelay after OUT_DELAY; + PIPETXELECIDLEL1_out <= PIPETXELECIDLEL1_outdelay after OUT_DELAY; + PIPETXELECIDLEL2_out <= PIPETXELECIDLEL2_outdelay after OUT_DELAY; + PIPETXELECIDLEL3_out <= PIPETXELECIDLEL3_outdelay after OUT_DELAY; + PIPETXELECIDLEL4_out <= PIPETXELECIDLEL4_outdelay after OUT_DELAY; + PIPETXELECIDLEL5_out <= PIPETXELECIDLEL5_outdelay after OUT_DELAY; + PIPETXELECIDLEL6_out <= PIPETXELECIDLEL6_outdelay after OUT_DELAY; + PIPETXELECIDLEL7_out <= PIPETXELECIDLEL7_outdelay after OUT_DELAY; + SERRENABLE_out <= SERRENABLE_outdelay after OUT_DELAY; + URREPORTINGENABLE_out <= URREPORTINGENABLE_outdelay after OUT_DELAY; + + CRMCORECLKDLO_ipd <= CRMCORECLKDLO after CLK_DELAY; + CRMCORECLKRXO_ipd <= CRMCORECLKRXO after CLK_DELAY; + CRMCORECLKTXO_ipd <= CRMCORECLKTXO after CLK_DELAY; + CRMCORECLK_ipd <= CRMCORECLK after CLK_DELAY; + CRMUSERCLKRXO_ipd <= CRMUSERCLKRXO after CLK_DELAY; + CRMUSERCLKTXO_ipd <= CRMUSERCLKTXO after CLK_DELAY; + CRMUSERCLK_ipd <= CRMUSERCLK after CLK_DELAY; + + AUXPOWER_ipd <= AUXPOWER after CLK_DELAY; + CFGNEGOTIATEDLINKWIDTH_ipd <= CFGNEGOTIATEDLINKWIDTH after CLK_DELAY; + COMPLIANCEAVOID_ipd <= COMPLIANCEAVOID after CLK_DELAY; + CRMCFGBRIDGEHOTRESET_ipd <= CRMCFGBRIDGEHOTRESET after CLK_DELAY; + CRMLINKRSTN_ipd <= CRMLINKRSTN after CLK_DELAY; + CRMMACRSTN_ipd <= CRMMACRSTN after CLK_DELAY; + CRMMGMTRSTN_ipd <= CRMMGMTRSTN after CLK_DELAY; + CRMNVRSTN_ipd <= CRMNVRSTN after CLK_DELAY; + CRMTXHOTRESETN_ipd <= CRMTXHOTRESETN after CLK_DELAY; + CRMURSTN_ipd <= CRMURSTN after CLK_DELAY; + CRMUSERCFGRSTN_ipd <= CRMUSERCFGRSTN after CLK_DELAY; + CROSSLINKSEED_ipd <= CROSSLINKSEED after CLK_DELAY; + L0ACKNAKTIMERADJUSTMENT_ipd <= L0ACKNAKTIMERADJUSTMENT after CLK_DELAY; + L0ALLDOWNPORTSINL1_ipd <= L0ALLDOWNPORTSINL1 after CLK_DELAY; + L0ALLDOWNRXPORTSINL0S_ipd <= L0ALLDOWNRXPORTSINL0S after CLK_DELAY; + L0ASE_ipd <= L0ASE after CLK_DELAY; + L0ASPORTCOUNT_ipd <= L0ASPORTCOUNT after CLK_DELAY; + L0ASTURNPOOLBITSCONSUMED_ipd <= L0ASTURNPOOLBITSCONSUMED after CLK_DELAY; + L0ATTENTIONBUTTONPRESSED_ipd <= L0ATTENTIONBUTTONPRESSED after CLK_DELAY; + L0CFGASSPANTREEOWNEDSTATE_ipd <= L0CFGASSPANTREEOWNEDSTATE after CLK_DELAY; + L0CFGASSTATECHANGECMD_ipd <= L0CFGASSTATECHANGECMD after CLK_DELAY; + L0CFGDISABLESCRAMBLE_ipd <= L0CFGDISABLESCRAMBLE after CLK_DELAY; + L0CFGEXTENDEDSYNC_ipd <= L0CFGEXTENDEDSYNC after CLK_DELAY; + L0CFGL0SENTRYENABLE_ipd <= L0CFGL0SENTRYENABLE after CLK_DELAY; + L0CFGL0SENTRYSUP_ipd <= L0CFGL0SENTRYSUP after CLK_DELAY; + L0CFGL0SEXITLAT_ipd <= L0CFGL0SEXITLAT after CLK_DELAY; + L0CFGLINKDISABLE_ipd <= L0CFGLINKDISABLE after CLK_DELAY; + L0CFGLOOPBACKMASTER_ipd <= L0CFGLOOPBACKMASTER after CLK_DELAY; + L0CFGNEGOTIATEDMAXP_ipd <= L0CFGNEGOTIATEDMAXP after CLK_DELAY; + L0CFGVCENABLE_ipd <= L0CFGVCENABLE after CLK_DELAY; + L0CFGVCID_ipd <= L0CFGVCID after CLK_DELAY; + L0DLLHOLDLINKUP_ipd <= L0DLLHOLDLINKUP after CLK_DELAY; + L0ELECTROMECHANICALINTERLOCKENGAGED_ipd <= L0ELECTROMECHANICALINTERLOCKENGAGED after CLK_DELAY; + L0FWDASSERTINTALEGACYINT_ipd <= L0FWDASSERTINTALEGACYINT after CLK_DELAY; + L0FWDASSERTINTBLEGACYINT_ipd <= L0FWDASSERTINTBLEGACYINT after CLK_DELAY; + L0FWDASSERTINTCLEGACYINT_ipd <= L0FWDASSERTINTCLEGACYINT after CLK_DELAY; + L0FWDASSERTINTDLEGACYINT_ipd <= L0FWDASSERTINTDLEGACYINT after CLK_DELAY; + L0FWDCORRERRIN_ipd <= L0FWDCORRERRIN after CLK_DELAY; + L0FWDDEASSERTINTALEGACYINT_ipd <= L0FWDDEASSERTINTALEGACYINT after CLK_DELAY; + L0FWDDEASSERTINTBLEGACYINT_ipd <= L0FWDDEASSERTINTBLEGACYINT after CLK_DELAY; + L0FWDDEASSERTINTCLEGACYINT_ipd <= L0FWDDEASSERTINTCLEGACYINT after CLK_DELAY; + L0FWDDEASSERTINTDLEGACYINT_ipd <= L0FWDDEASSERTINTDLEGACYINT after CLK_DELAY; + L0FWDFATALERRIN_ipd <= L0FWDFATALERRIN after CLK_DELAY; + L0FWDNONFATALERRIN_ipd <= L0FWDNONFATALERRIN after CLK_DELAY; + L0LEGACYINTFUNCT0_ipd <= L0LEGACYINTFUNCT0 after CLK_DELAY; + L0MRLSENSORCLOSEDN_ipd <= L0MRLSENSORCLOSEDN after CLK_DELAY; + L0MSIREQUEST0_ipd <= L0MSIREQUEST0 after CLK_DELAY; + L0PACKETHEADERFROMUSER_ipd <= L0PACKETHEADERFROMUSER after CLK_DELAY; + L0PMEREQIN_ipd <= L0PMEREQIN after CLK_DELAY; + L0PORTNUMBER_ipd <= L0PORTNUMBER after CLK_DELAY; + L0POWERFAULTDETECTED_ipd <= L0POWERFAULTDETECTED after CLK_DELAY; + L0PRESENCEDETECTSLOTEMPTYN_ipd <= L0PRESENCEDETECTSLOTEMPTYN after CLK_DELAY; + L0PWRNEWSTATEREQ_ipd <= L0PWRNEWSTATEREQ after CLK_DELAY; + L0PWRNEXTLINKSTATE_ipd <= L0PWRNEXTLINKSTATE after CLK_DELAY; + L0REPLAYTIMERADJUSTMENT_ipd <= L0REPLAYTIMERADJUSTMENT after CLK_DELAY; + L0ROOTTURNOFFREQ_ipd <= L0ROOTTURNOFFREQ after CLK_DELAY; + L0RXTLTLPNONINITIALIZEDVC_ipd <= L0RXTLTLPNONINITIALIZEDVC after CLK_DELAY; + L0SENDUNLOCKMESSAGE_ipd <= L0SENDUNLOCKMESSAGE after CLK_DELAY; + L0SETCOMPLETERABORTERROR_ipd <= L0SETCOMPLETERABORTERROR after CLK_DELAY; + L0SETCOMPLETIONTIMEOUTCORRERROR_ipd <= L0SETCOMPLETIONTIMEOUTCORRERROR after CLK_DELAY; + L0SETCOMPLETIONTIMEOUTUNCORRERROR_ipd <= L0SETCOMPLETIONTIMEOUTUNCORRERROR after CLK_DELAY; + L0SETDETECTEDCORRERROR_ipd <= L0SETDETECTEDCORRERROR after CLK_DELAY; + L0SETDETECTEDFATALERROR_ipd <= L0SETDETECTEDFATALERROR after CLK_DELAY; + L0SETDETECTEDNONFATALERROR_ipd <= L0SETDETECTEDNONFATALERROR after CLK_DELAY; + L0SETLINKDETECTEDPARITYERROR_ipd <= L0SETLINKDETECTEDPARITYERROR after CLK_DELAY; + L0SETLINKMASTERDATAPARITY_ipd <= L0SETLINKMASTERDATAPARITY after CLK_DELAY; + L0SETLINKRECEIVEDMASTERABORT_ipd <= L0SETLINKRECEIVEDMASTERABORT after CLK_DELAY; + L0SETLINKRECEIVEDTARGETABORT_ipd <= L0SETLINKRECEIVEDTARGETABORT after CLK_DELAY; + L0SETLINKSIGNALLEDTARGETABORT_ipd <= L0SETLINKSIGNALLEDTARGETABORT after CLK_DELAY; + L0SETLINKSYSTEMERROR_ipd <= L0SETLINKSYSTEMERROR after CLK_DELAY; + L0SETUNEXPECTEDCOMPLETIONCORRERROR_ipd <= L0SETUNEXPECTEDCOMPLETIONCORRERROR after CLK_DELAY; + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_ipd <= L0SETUNEXPECTEDCOMPLETIONUNCORRERROR after CLK_DELAY; + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_ipd <= L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR after CLK_DELAY; + L0SETUNSUPPORTEDREQUESTOTHERERROR_ipd <= L0SETUNSUPPORTEDREQUESTOTHERERROR after CLK_DELAY; + L0SETUSERDETECTEDPARITYERROR_ipd <= L0SETUSERDETECTEDPARITYERROR after CLK_DELAY; + L0SETUSERMASTERDATAPARITY_ipd <= L0SETUSERMASTERDATAPARITY after CLK_DELAY; + L0SETUSERRECEIVEDMASTERABORT_ipd <= L0SETUSERRECEIVEDMASTERABORT after CLK_DELAY; + L0SETUSERRECEIVEDTARGETABORT_ipd <= L0SETUSERRECEIVEDTARGETABORT after CLK_DELAY; + L0SETUSERSIGNALLEDTARGETABORT_ipd <= L0SETUSERSIGNALLEDTARGETABORT after CLK_DELAY; + L0SETUSERSYSTEMERROR_ipd <= L0SETUSERSYSTEMERROR after CLK_DELAY; + L0TLASFCCREDSTARVATION_ipd <= L0TLASFCCREDSTARVATION after CLK_DELAY; + L0TLLINKRETRAIN_ipd <= L0TLLINKRETRAIN after CLK_DELAY; + L0TRANSACTIONSPENDING_ipd <= L0TRANSACTIONSPENDING after CLK_DELAY; + L0TXBEACON_ipd <= L0TXBEACON after CLK_DELAY; + L0TXCFGPMTYPE_ipd <= L0TXCFGPMTYPE after CLK_DELAY; + L0TXCFGPM_ipd <= L0TXCFGPM after CLK_DELAY; + L0TXTLFCCMPLMCCRED_ipd <= L0TXTLFCCMPLMCCRED after CLK_DELAY; + L0TXTLFCCMPLMCUPDATE_ipd <= L0TXTLFCCMPLMCUPDATE after CLK_DELAY; + L0TXTLFCNPOSTBYPCRED_ipd <= L0TXTLFCNPOSTBYPCRED after CLK_DELAY; + L0TXTLFCNPOSTBYPUPDATE_ipd <= L0TXTLFCNPOSTBYPUPDATE after CLK_DELAY; + L0TXTLFCPOSTORDCRED_ipd <= L0TXTLFCPOSTORDCRED after CLK_DELAY; + L0TXTLFCPOSTORDUPDATE_ipd <= L0TXTLFCPOSTORDUPDATE after CLK_DELAY; + L0TXTLSBFCDATA_ipd <= L0TXTLSBFCDATA after CLK_DELAY; + L0TXTLSBFCUPDATE_ipd <= L0TXTLSBFCUPDATE after CLK_DELAY; + L0TXTLTLPDATA_ipd <= L0TXTLTLPDATA after CLK_DELAY; + L0TXTLTLPEDB_ipd <= L0TXTLTLPEDB after CLK_DELAY; + L0TXTLTLPENABLE_ipd <= L0TXTLTLPENABLE after CLK_DELAY; + L0TXTLTLPEND_ipd <= L0TXTLTLPEND after CLK_DELAY; + L0TXTLTLPLATENCY_ipd <= L0TXTLTLPLATENCY after CLK_DELAY; + L0TXTLTLPREQEND_ipd <= L0TXTLTLPREQEND after CLK_DELAY; + L0TXTLTLPREQ_ipd <= L0TXTLTLPREQ after CLK_DELAY; + L0TXTLTLPWIDTH_ipd <= L0TXTLTLPWIDTH after CLK_DELAY; + L0UPSTREAMRXPORTINL0S_ipd <= L0UPSTREAMRXPORTINL0S after CLK_DELAY; + L0VC0PREVIEWEXPAND_ipd <= L0VC0PREVIEWEXPAND after CLK_DELAY; + L0WAKEN_ipd <= L0WAKEN after CLK_DELAY; + LLKRXCHFIFO_ipd <= LLKRXCHFIFO after CLK_DELAY; + LLKRXCHTC_ipd <= LLKRXCHTC after CLK_DELAY; + LLKRXDSTCONTREQN_ipd <= LLKRXDSTCONTREQN after CLK_DELAY; + LLKRXDSTREQN_ipd <= LLKRXDSTREQN after CLK_DELAY; + LLKTX4DWHEADERN_ipd <= LLKTX4DWHEADERN after CLK_DELAY; + LLKTXCHFIFO_ipd <= LLKTXCHFIFO after CLK_DELAY; + LLKTXCHTC_ipd <= LLKTXCHTC after CLK_DELAY; + LLKTXCOMPLETEN_ipd <= LLKTXCOMPLETEN after CLK_DELAY; + LLKTXCREATEECRCN_ipd <= LLKTXCREATEECRCN after CLK_DELAY; + LLKTXDATA_ipd <= LLKTXDATA after CLK_DELAY; + LLKTXENABLEN_ipd <= LLKTXENABLEN after CLK_DELAY; + LLKTXEOFN_ipd <= LLKTXEOFN after CLK_DELAY; + LLKTXEOPN_ipd <= LLKTXEOPN after CLK_DELAY; + LLKTXSOFN_ipd <= LLKTXSOFN after CLK_DELAY; + LLKTXSOPN_ipd <= LLKTXSOPN after CLK_DELAY; + LLKTXSRCDSCN_ipd <= LLKTXSRCDSCN after CLK_DELAY; + LLKTXSRCRDYN_ipd <= LLKTXSRCRDYN after CLK_DELAY; + MAINPOWER_ipd <= MAINPOWER after CLK_DELAY; + MGMTADDR_ipd <= MGMTADDR after CLK_DELAY; + MGMTBWREN_ipd <= MGMTBWREN after CLK_DELAY; + MGMTRDEN_ipd <= MGMTRDEN after CLK_DELAY; + MGMTSTATSCREDITSEL_ipd <= MGMTSTATSCREDITSEL after CLK_DELAY; + MGMTWDATA_ipd <= MGMTWDATA after CLK_DELAY; + MGMTWREN_ipd <= MGMTWREN after CLK_DELAY; + MIMDLLBRDATA_ipd <= MIMDLLBRDATA after CLK_DELAY; + MIMRXBRDATA_ipd <= MIMRXBRDATA after CLK_DELAY; + MIMTXBRDATA_ipd <= MIMTXBRDATA after CLK_DELAY; + PIPEPHYSTATUSL0_ipd <= PIPEPHYSTATUSL0 after CLK_DELAY; + PIPEPHYSTATUSL1_ipd <= PIPEPHYSTATUSL1 after CLK_DELAY; + PIPEPHYSTATUSL2_ipd <= PIPEPHYSTATUSL2 after CLK_DELAY; + PIPEPHYSTATUSL3_ipd <= PIPEPHYSTATUSL3 after CLK_DELAY; + PIPEPHYSTATUSL4_ipd <= PIPEPHYSTATUSL4 after CLK_DELAY; + PIPEPHYSTATUSL5_ipd <= PIPEPHYSTATUSL5 after CLK_DELAY; + PIPEPHYSTATUSL6_ipd <= PIPEPHYSTATUSL6 after CLK_DELAY; + PIPEPHYSTATUSL7_ipd <= PIPEPHYSTATUSL7 after CLK_DELAY; + PIPERXCHANISALIGNEDL0_ipd <= PIPERXCHANISALIGNEDL0 after CLK_DELAY; + PIPERXCHANISALIGNEDL1_ipd <= PIPERXCHANISALIGNEDL1 after CLK_DELAY; + PIPERXCHANISALIGNEDL2_ipd <= PIPERXCHANISALIGNEDL2 after CLK_DELAY; + PIPERXCHANISALIGNEDL3_ipd <= PIPERXCHANISALIGNEDL3 after CLK_DELAY; + PIPERXCHANISALIGNEDL4_ipd <= PIPERXCHANISALIGNEDL4 after CLK_DELAY; + PIPERXCHANISALIGNEDL5_ipd <= PIPERXCHANISALIGNEDL5 after CLK_DELAY; + PIPERXCHANISALIGNEDL6_ipd <= PIPERXCHANISALIGNEDL6 after CLK_DELAY; + PIPERXCHANISALIGNEDL7_ipd <= PIPERXCHANISALIGNEDL7 after CLK_DELAY; + PIPERXDATAKL0_ipd <= PIPERXDATAKL0 after CLK_DELAY; + PIPERXDATAKL1_ipd <= PIPERXDATAKL1 after CLK_DELAY; + PIPERXDATAKL2_ipd <= PIPERXDATAKL2 after CLK_DELAY; + PIPERXDATAKL3_ipd <= PIPERXDATAKL3 after CLK_DELAY; + PIPERXDATAKL4_ipd <= PIPERXDATAKL4 after CLK_DELAY; + PIPERXDATAKL5_ipd <= PIPERXDATAKL5 after CLK_DELAY; + PIPERXDATAKL6_ipd <= PIPERXDATAKL6 after CLK_DELAY; + PIPERXDATAKL7_ipd <= PIPERXDATAKL7 after CLK_DELAY; + PIPERXDATAL0_ipd <= PIPERXDATAL0 after CLK_DELAY; + PIPERXDATAL1_ipd <= PIPERXDATAL1 after CLK_DELAY; + PIPERXDATAL2_ipd <= PIPERXDATAL2 after CLK_DELAY; + PIPERXDATAL3_ipd <= PIPERXDATAL3 after CLK_DELAY; + PIPERXDATAL4_ipd <= PIPERXDATAL4 after CLK_DELAY; + PIPERXDATAL5_ipd <= PIPERXDATAL5 after CLK_DELAY; + PIPERXDATAL6_ipd <= PIPERXDATAL6 after CLK_DELAY; + PIPERXDATAL7_ipd <= PIPERXDATAL7 after CLK_DELAY; + PIPERXELECIDLEL0_ipd <= PIPERXELECIDLEL0 after CLK_DELAY; + PIPERXELECIDLEL1_ipd <= PIPERXELECIDLEL1 after CLK_DELAY; + PIPERXELECIDLEL2_ipd <= PIPERXELECIDLEL2 after CLK_DELAY; + PIPERXELECIDLEL3_ipd <= PIPERXELECIDLEL3 after CLK_DELAY; + PIPERXELECIDLEL4_ipd <= PIPERXELECIDLEL4 after CLK_DELAY; + PIPERXELECIDLEL5_ipd <= PIPERXELECIDLEL5 after CLK_DELAY; + PIPERXELECIDLEL6_ipd <= PIPERXELECIDLEL6 after CLK_DELAY; + PIPERXELECIDLEL7_ipd <= PIPERXELECIDLEL7 after CLK_DELAY; + PIPERXSTATUSL0_ipd <= PIPERXSTATUSL0 after CLK_DELAY; + PIPERXSTATUSL1_ipd <= PIPERXSTATUSL1 after CLK_DELAY; + PIPERXSTATUSL2_ipd <= PIPERXSTATUSL2 after CLK_DELAY; + PIPERXSTATUSL3_ipd <= PIPERXSTATUSL3 after CLK_DELAY; + PIPERXSTATUSL4_ipd <= PIPERXSTATUSL4 after CLK_DELAY; + PIPERXSTATUSL5_ipd <= PIPERXSTATUSL5 after CLK_DELAY; + PIPERXSTATUSL6_ipd <= PIPERXSTATUSL6 after CLK_DELAY; + PIPERXSTATUSL7_ipd <= PIPERXSTATUSL7 after CLK_DELAY; + PIPERXVALIDL0_ipd <= PIPERXVALIDL0 after CLK_DELAY; + PIPERXVALIDL1_ipd <= PIPERXVALIDL1 after CLK_DELAY; + PIPERXVALIDL2_ipd <= PIPERXVALIDL2 after CLK_DELAY; + PIPERXVALIDL3_ipd <= PIPERXVALIDL3 after CLK_DELAY; + PIPERXVALIDL4_ipd <= PIPERXVALIDL4 after CLK_DELAY; + PIPERXVALIDL5_ipd <= PIPERXVALIDL5 after CLK_DELAY; + PIPERXVALIDL6_ipd <= PIPERXVALIDL6 after CLK_DELAY; + PIPERXVALIDL7_ipd <= PIPERXVALIDL7 after CLK_DELAY; + + CRMCORECLKDLO_indelay <= CRMCORECLKDLO_ipd after CLK_DELAY; + CRMCORECLKRXO_indelay <= CRMCORECLKRXO_ipd after CLK_DELAY; + CRMCORECLKTXO_indelay <= CRMCORECLKTXO_ipd after CLK_DELAY; + CRMCORECLK_indelay <= CRMCORECLK_ipd after CLK_DELAY; + CRMUSERCLKRXO_indelay <= CRMUSERCLKRXO_ipd after CLK_DELAY; + CRMUSERCLKTXO_indelay <= CRMUSERCLKTXO_ipd after CLK_DELAY; + CRMUSERCLK_indelay <= CRMUSERCLK_ipd after CLK_DELAY; + + AUXPOWER_indelay <= AUXPOWER_ipd after IN_DELAY; + CFGNEGOTIATEDLINKWIDTH_indelay <= CFGNEGOTIATEDLINKWIDTH_ipd after IN_DELAY; + COMPLIANCEAVOID_indelay <= COMPLIANCEAVOID_ipd after IN_DELAY; + CRMCFGBRIDGEHOTRESET_indelay <= CRMCFGBRIDGEHOTRESET_ipd after IN_DELAY; + CRMLINKRSTN_indelay <= CRMLINKRSTN_ipd after IN_DELAY; + CRMMACRSTN_indelay <= CRMMACRSTN_ipd after IN_DELAY; + CRMMGMTRSTN_indelay <= CRMMGMTRSTN_ipd after IN_DELAY; + CRMNVRSTN_indelay <= CRMNVRSTN_ipd after IN_DELAY; + CRMTXHOTRESETN_indelay <= CRMTXHOTRESETN_ipd after IN_DELAY; + CRMURSTN_indelay <= CRMURSTN_ipd after IN_DELAY; + CRMUSERCFGRSTN_indelay <= CRMUSERCFGRSTN_ipd after IN_DELAY; + CROSSLINKSEED_indelay <= CROSSLINKSEED_ipd after IN_DELAY; + L0ACKNAKTIMERADJUSTMENT_indelay <= L0ACKNAKTIMERADJUSTMENT_ipd after IN_DELAY; + L0ALLDOWNPORTSINL1_indelay <= L0ALLDOWNPORTSINL1_ipd after IN_DELAY; + L0ALLDOWNRXPORTSINL0S_indelay <= L0ALLDOWNRXPORTSINL0S_ipd after IN_DELAY; + L0ASE_indelay <= L0ASE_ipd after IN_DELAY; + L0ASPORTCOUNT_indelay <= L0ASPORTCOUNT_ipd after IN_DELAY; + L0ASTURNPOOLBITSCONSUMED_indelay <= L0ASTURNPOOLBITSCONSUMED_ipd after IN_DELAY; + L0ATTENTIONBUTTONPRESSED_indelay <= L0ATTENTIONBUTTONPRESSED_ipd after IN_DELAY; + L0CFGASSPANTREEOWNEDSTATE_indelay <= L0CFGASSPANTREEOWNEDSTATE_ipd after IN_DELAY; + L0CFGASSTATECHANGECMD_indelay <= L0CFGASSTATECHANGECMD_ipd after IN_DELAY; + L0CFGDISABLESCRAMBLE_indelay <= L0CFGDISABLESCRAMBLE_ipd after IN_DELAY; + L0CFGEXTENDEDSYNC_indelay <= L0CFGEXTENDEDSYNC_ipd after IN_DELAY; + L0CFGL0SENTRYENABLE_indelay <= L0CFGL0SENTRYENABLE_ipd after IN_DELAY; + L0CFGL0SENTRYSUP_indelay <= L0CFGL0SENTRYSUP_ipd after IN_DELAY; + L0CFGL0SEXITLAT_indelay <= L0CFGL0SEXITLAT_ipd after IN_DELAY; + L0CFGLINKDISABLE_indelay <= L0CFGLINKDISABLE_ipd after IN_DELAY; + L0CFGLOOPBACKMASTER_indelay <= L0CFGLOOPBACKMASTER_ipd after IN_DELAY; + L0CFGNEGOTIATEDMAXP_indelay <= L0CFGNEGOTIATEDMAXP_ipd after IN_DELAY; + L0CFGVCENABLE_indelay <= L0CFGVCENABLE_ipd after IN_DELAY; + L0CFGVCID_indelay <= L0CFGVCID_ipd after IN_DELAY; + L0DLLHOLDLINKUP_indelay <= L0DLLHOLDLINKUP_ipd after IN_DELAY; + L0ELECTROMECHANICALINTERLOCKENGAGED_indelay <= L0ELECTROMECHANICALINTERLOCKENGAGED_ipd after IN_DELAY; + L0FWDASSERTINTALEGACYINT_indelay <= L0FWDASSERTINTALEGACYINT_ipd after IN_DELAY; + L0FWDASSERTINTBLEGACYINT_indelay <= L0FWDASSERTINTBLEGACYINT_ipd after IN_DELAY; + L0FWDASSERTINTCLEGACYINT_indelay <= L0FWDASSERTINTCLEGACYINT_ipd after IN_DELAY; + L0FWDASSERTINTDLEGACYINT_indelay <= L0FWDASSERTINTDLEGACYINT_ipd after IN_DELAY; + L0FWDCORRERRIN_indelay <= L0FWDCORRERRIN_ipd after IN_DELAY; + L0FWDDEASSERTINTALEGACYINT_indelay <= L0FWDDEASSERTINTALEGACYINT_ipd after IN_DELAY; + L0FWDDEASSERTINTBLEGACYINT_indelay <= L0FWDDEASSERTINTBLEGACYINT_ipd after IN_DELAY; + L0FWDDEASSERTINTCLEGACYINT_indelay <= L0FWDDEASSERTINTCLEGACYINT_ipd after IN_DELAY; + L0FWDDEASSERTINTDLEGACYINT_indelay <= L0FWDDEASSERTINTDLEGACYINT_ipd after IN_DELAY; + L0FWDFATALERRIN_indelay <= L0FWDFATALERRIN_ipd after IN_DELAY; + L0FWDNONFATALERRIN_indelay <= L0FWDNONFATALERRIN_ipd after IN_DELAY; + L0LEGACYINTFUNCT0_indelay <= L0LEGACYINTFUNCT0_ipd after IN_DELAY; + L0MRLSENSORCLOSEDN_indelay <= L0MRLSENSORCLOSEDN_ipd after IN_DELAY; + L0MSIREQUEST0_indelay <= L0MSIREQUEST0_ipd after IN_DELAY; + L0PACKETHEADERFROMUSER_indelay <= L0PACKETHEADERFROMUSER_ipd after IN_DELAY; + L0PMEREQIN_indelay <= L0PMEREQIN_ipd after IN_DELAY; + L0PORTNUMBER_indelay <= L0PORTNUMBER_ipd after IN_DELAY; + L0POWERFAULTDETECTED_indelay <= L0POWERFAULTDETECTED_ipd after IN_DELAY; + L0PRESENCEDETECTSLOTEMPTYN_indelay <= L0PRESENCEDETECTSLOTEMPTYN_ipd after IN_DELAY; + L0PWRNEWSTATEREQ_indelay <= L0PWRNEWSTATEREQ_ipd after IN_DELAY; + L0PWRNEXTLINKSTATE_indelay <= L0PWRNEXTLINKSTATE_ipd after IN_DELAY; + L0REPLAYTIMERADJUSTMENT_indelay <= L0REPLAYTIMERADJUSTMENT_ipd after IN_DELAY; + L0ROOTTURNOFFREQ_indelay <= L0ROOTTURNOFFREQ_ipd after IN_DELAY; + L0RXTLTLPNONINITIALIZEDVC_indelay <= L0RXTLTLPNONINITIALIZEDVC_ipd after IN_DELAY; + L0SENDUNLOCKMESSAGE_indelay <= L0SENDUNLOCKMESSAGE_ipd after IN_DELAY; + L0SETCOMPLETERABORTERROR_indelay <= L0SETCOMPLETERABORTERROR_ipd after IN_DELAY; + L0SETCOMPLETIONTIMEOUTCORRERROR_indelay <= L0SETCOMPLETIONTIMEOUTCORRERROR_ipd after IN_DELAY; + L0SETCOMPLETIONTIMEOUTUNCORRERROR_indelay <= L0SETCOMPLETIONTIMEOUTUNCORRERROR_ipd after IN_DELAY; + L0SETDETECTEDCORRERROR_indelay <= L0SETDETECTEDCORRERROR_ipd after IN_DELAY; + L0SETDETECTEDFATALERROR_indelay <= L0SETDETECTEDFATALERROR_ipd after IN_DELAY; + L0SETDETECTEDNONFATALERROR_indelay <= L0SETDETECTEDNONFATALERROR_ipd after IN_DELAY; + L0SETLINKDETECTEDPARITYERROR_indelay <= L0SETLINKDETECTEDPARITYERROR_ipd after IN_DELAY; + L0SETLINKMASTERDATAPARITY_indelay <= L0SETLINKMASTERDATAPARITY_ipd after IN_DELAY; + L0SETLINKRECEIVEDMASTERABORT_indelay <= L0SETLINKRECEIVEDMASTERABORT_ipd after IN_DELAY; + L0SETLINKRECEIVEDTARGETABORT_indelay <= L0SETLINKRECEIVEDTARGETABORT_ipd after IN_DELAY; + L0SETLINKSIGNALLEDTARGETABORT_indelay <= L0SETLINKSIGNALLEDTARGETABORT_ipd after IN_DELAY; + L0SETLINKSYSTEMERROR_indelay <= L0SETLINKSYSTEMERROR_ipd after IN_DELAY; + L0SETUNEXPECTEDCOMPLETIONCORRERROR_indelay <= L0SETUNEXPECTEDCOMPLETIONCORRERROR_ipd after IN_DELAY; + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_indelay <= L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_ipd after IN_DELAY; + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_indelay <= L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_ipd after IN_DELAY; + L0SETUNSUPPORTEDREQUESTOTHERERROR_indelay <= L0SETUNSUPPORTEDREQUESTOTHERERROR_ipd after IN_DELAY; + L0SETUSERDETECTEDPARITYERROR_indelay <= L0SETUSERDETECTEDPARITYERROR_ipd after IN_DELAY; + L0SETUSERMASTERDATAPARITY_indelay <= L0SETUSERMASTERDATAPARITY_ipd after IN_DELAY; + L0SETUSERRECEIVEDMASTERABORT_indelay <= L0SETUSERRECEIVEDMASTERABORT_ipd after IN_DELAY; + L0SETUSERRECEIVEDTARGETABORT_indelay <= L0SETUSERRECEIVEDTARGETABORT_ipd after IN_DELAY; + L0SETUSERSIGNALLEDTARGETABORT_indelay <= L0SETUSERSIGNALLEDTARGETABORT_ipd after IN_DELAY; + L0SETUSERSYSTEMERROR_indelay <= L0SETUSERSYSTEMERROR_ipd after IN_DELAY; + L0TLASFCCREDSTARVATION_indelay <= L0TLASFCCREDSTARVATION_ipd after IN_DELAY; + L0TLLINKRETRAIN_indelay <= L0TLLINKRETRAIN_ipd after IN_DELAY; + L0TRANSACTIONSPENDING_indelay <= L0TRANSACTIONSPENDING_ipd after IN_DELAY; + L0TXBEACON_indelay <= L0TXBEACON_ipd after IN_DELAY; + L0TXCFGPMTYPE_indelay <= L0TXCFGPMTYPE_ipd after IN_DELAY; + L0TXCFGPM_indelay <= L0TXCFGPM_ipd after IN_DELAY; + L0TXTLFCCMPLMCCRED_indelay <= L0TXTLFCCMPLMCCRED_ipd after IN_DELAY; + L0TXTLFCCMPLMCUPDATE_indelay <= L0TXTLFCCMPLMCUPDATE_ipd after IN_DELAY; + L0TXTLFCNPOSTBYPCRED_indelay <= L0TXTLFCNPOSTBYPCRED_ipd after IN_DELAY; + L0TXTLFCNPOSTBYPUPDATE_indelay <= L0TXTLFCNPOSTBYPUPDATE_ipd after IN_DELAY; + L0TXTLFCPOSTORDCRED_indelay <= L0TXTLFCPOSTORDCRED_ipd after IN_DELAY; + L0TXTLFCPOSTORDUPDATE_indelay <= L0TXTLFCPOSTORDUPDATE_ipd after IN_DELAY; + L0TXTLSBFCDATA_indelay <= L0TXTLSBFCDATA_ipd after IN_DELAY; + L0TXTLSBFCUPDATE_indelay <= L0TXTLSBFCUPDATE_ipd after IN_DELAY; + L0TXTLTLPDATA_indelay <= L0TXTLTLPDATA_ipd after IN_DELAY; + L0TXTLTLPEDB_indelay <= L0TXTLTLPEDB_ipd after IN_DELAY; + L0TXTLTLPENABLE_indelay <= L0TXTLTLPENABLE_ipd after IN_DELAY; + L0TXTLTLPEND_indelay <= L0TXTLTLPEND_ipd after IN_DELAY; + L0TXTLTLPLATENCY_indelay <= L0TXTLTLPLATENCY_ipd after IN_DELAY; + L0TXTLTLPREQEND_indelay <= L0TXTLTLPREQEND_ipd after IN_DELAY; + L0TXTLTLPREQ_indelay <= L0TXTLTLPREQ_ipd after IN_DELAY; + L0TXTLTLPWIDTH_indelay <= L0TXTLTLPWIDTH_ipd after IN_DELAY; + L0UPSTREAMRXPORTINL0S_indelay <= L0UPSTREAMRXPORTINL0S_ipd after IN_DELAY; + L0VC0PREVIEWEXPAND_indelay <= L0VC0PREVIEWEXPAND_ipd after IN_DELAY; + L0WAKEN_indelay <= L0WAKEN_ipd after IN_DELAY; + LLKRXCHFIFO_indelay <= LLKRXCHFIFO_ipd after IN_DELAY; + LLKRXCHTC_indelay <= LLKRXCHTC_ipd after IN_DELAY; + LLKRXDSTCONTREQN_indelay <= LLKRXDSTCONTREQN_ipd after IN_DELAY; + LLKRXDSTREQN_indelay <= LLKRXDSTREQN_ipd after IN_DELAY; + LLKTX4DWHEADERN_indelay <= LLKTX4DWHEADERN_ipd after IN_DELAY; + LLKTXCHFIFO_indelay <= LLKTXCHFIFO_ipd after IN_DELAY; + LLKTXCHTC_indelay <= LLKTXCHTC_ipd after IN_DELAY; + LLKTXCOMPLETEN_indelay <= LLKTXCOMPLETEN_ipd after IN_DELAY; + LLKTXCREATEECRCN_indelay <= LLKTXCREATEECRCN_ipd after IN_DELAY; + LLKTXDATA_indelay <= LLKTXDATA_ipd after IN_DELAY; + LLKTXENABLEN_indelay <= LLKTXENABLEN_ipd after IN_DELAY; + LLKTXEOFN_indelay <= LLKTXEOFN_ipd after IN_DELAY; + LLKTXEOPN_indelay <= LLKTXEOPN_ipd after IN_DELAY; + LLKTXSOFN_indelay <= LLKTXSOFN_ipd after IN_DELAY; + LLKTXSOPN_indelay <= LLKTXSOPN_ipd after IN_DELAY; + LLKTXSRCDSCN_indelay <= LLKTXSRCDSCN_ipd after IN_DELAY; + LLKTXSRCRDYN_indelay <= LLKTXSRCRDYN_ipd after IN_DELAY; + MAINPOWER_indelay <= MAINPOWER_ipd after IN_DELAY; + MGMTADDR_indelay <= MGMTADDR_ipd after IN_DELAY; + MGMTBWREN_indelay <= MGMTBWREN_ipd after IN_DELAY; + MGMTRDEN_indelay <= MGMTRDEN_ipd after IN_DELAY; + MGMTSTATSCREDITSEL_indelay <= MGMTSTATSCREDITSEL_ipd after IN_DELAY; + MGMTWDATA_indelay <= MGMTWDATA_ipd after IN_DELAY; + MGMTWREN_indelay <= MGMTWREN_ipd after IN_DELAY; + MIMDLLBRDATA_indelay <= MIMDLLBRDATA_ipd after IN_DELAY; + MIMRXBRDATA_indelay <= MIMRXBRDATA_ipd after IN_DELAY; + MIMTXBRDATA_indelay <= MIMTXBRDATA_ipd after IN_DELAY; + PIPEPHYSTATUSL0_indelay <= PIPEPHYSTATUSL0_ipd after IN_DELAY; + PIPEPHYSTATUSL1_indelay <= PIPEPHYSTATUSL1_ipd after IN_DELAY; + PIPEPHYSTATUSL2_indelay <= PIPEPHYSTATUSL2_ipd after IN_DELAY; + PIPEPHYSTATUSL3_indelay <= PIPEPHYSTATUSL3_ipd after IN_DELAY; + PIPEPHYSTATUSL4_indelay <= PIPEPHYSTATUSL4_ipd after IN_DELAY; + PIPEPHYSTATUSL5_indelay <= PIPEPHYSTATUSL5_ipd after IN_DELAY; + PIPEPHYSTATUSL6_indelay <= PIPEPHYSTATUSL6_ipd after IN_DELAY; + PIPEPHYSTATUSL7_indelay <= PIPEPHYSTATUSL7_ipd after IN_DELAY; + PIPERXCHANISALIGNEDL0_indelay <= PIPERXCHANISALIGNEDL0_ipd after IN_DELAY; + PIPERXCHANISALIGNEDL1_indelay <= PIPERXCHANISALIGNEDL1_ipd after IN_DELAY; + PIPERXCHANISALIGNEDL2_indelay <= PIPERXCHANISALIGNEDL2_ipd after IN_DELAY; + PIPERXCHANISALIGNEDL3_indelay <= PIPERXCHANISALIGNEDL3_ipd after IN_DELAY; + PIPERXCHANISALIGNEDL4_indelay <= PIPERXCHANISALIGNEDL4_ipd after IN_DELAY; + PIPERXCHANISALIGNEDL5_indelay <= PIPERXCHANISALIGNEDL5_ipd after IN_DELAY; + PIPERXCHANISALIGNEDL6_indelay <= PIPERXCHANISALIGNEDL6_ipd after IN_DELAY; + PIPERXCHANISALIGNEDL7_indelay <= PIPERXCHANISALIGNEDL7_ipd after IN_DELAY; + PIPERXDATAKL0_indelay <= PIPERXDATAKL0_ipd after IN_DELAY; + PIPERXDATAKL1_indelay <= PIPERXDATAKL1_ipd after IN_DELAY; + PIPERXDATAKL2_indelay <= PIPERXDATAKL2_ipd after IN_DELAY; + PIPERXDATAKL3_indelay <= PIPERXDATAKL3_ipd after IN_DELAY; + PIPERXDATAKL4_indelay <= PIPERXDATAKL4_ipd after IN_DELAY; + PIPERXDATAKL5_indelay <= PIPERXDATAKL5_ipd after IN_DELAY; + PIPERXDATAKL6_indelay <= PIPERXDATAKL6_ipd after IN_DELAY; + PIPERXDATAKL7_indelay <= PIPERXDATAKL7_ipd after IN_DELAY; + PIPERXDATAL0_indelay <= PIPERXDATAL0_ipd after IN_DELAY; + PIPERXDATAL1_indelay <= PIPERXDATAL1_ipd after IN_DELAY; + PIPERXDATAL2_indelay <= PIPERXDATAL2_ipd after IN_DELAY; + PIPERXDATAL3_indelay <= PIPERXDATAL3_ipd after IN_DELAY; + PIPERXDATAL4_indelay <= PIPERXDATAL4_ipd after IN_DELAY; + PIPERXDATAL5_indelay <= PIPERXDATAL5_ipd after IN_DELAY; + PIPERXDATAL6_indelay <= PIPERXDATAL6_ipd after IN_DELAY; + PIPERXDATAL7_indelay <= PIPERXDATAL7_ipd after IN_DELAY; + PIPERXELECIDLEL0_indelay <= PIPERXELECIDLEL0_ipd after IN_DELAY; + PIPERXELECIDLEL1_indelay <= PIPERXELECIDLEL1_ipd after IN_DELAY; + PIPERXELECIDLEL2_indelay <= PIPERXELECIDLEL2_ipd after IN_DELAY; + PIPERXELECIDLEL3_indelay <= PIPERXELECIDLEL3_ipd after IN_DELAY; + PIPERXELECIDLEL4_indelay <= PIPERXELECIDLEL4_ipd after IN_DELAY; + PIPERXELECIDLEL5_indelay <= PIPERXELECIDLEL5_ipd after IN_DELAY; + PIPERXELECIDLEL6_indelay <= PIPERXELECIDLEL6_ipd after IN_DELAY; + PIPERXELECIDLEL7_indelay <= PIPERXELECIDLEL7_ipd after IN_DELAY; + PIPERXSTATUSL0_indelay <= PIPERXSTATUSL0_ipd after IN_DELAY; + PIPERXSTATUSL1_indelay <= PIPERXSTATUSL1_ipd after IN_DELAY; + PIPERXSTATUSL2_indelay <= PIPERXSTATUSL2_ipd after IN_DELAY; + PIPERXSTATUSL3_indelay <= PIPERXSTATUSL3_ipd after IN_DELAY; + PIPERXSTATUSL4_indelay <= PIPERXSTATUSL4_ipd after IN_DELAY; + PIPERXSTATUSL5_indelay <= PIPERXSTATUSL5_ipd after IN_DELAY; + PIPERXSTATUSL6_indelay <= PIPERXSTATUSL6_ipd after IN_DELAY; + PIPERXSTATUSL7_indelay <= PIPERXSTATUSL7_ipd after IN_DELAY; + PIPERXVALIDL0_indelay <= PIPERXVALIDL0_ipd after IN_DELAY; + PIPERXVALIDL1_indelay <= PIPERXVALIDL1_ipd after IN_DELAY; + PIPERXVALIDL2_indelay <= PIPERXVALIDL2_ipd after IN_DELAY; + PIPERXVALIDL3_indelay <= PIPERXVALIDL3_ipd after IN_DELAY; + PIPERXVALIDL4_indelay <= PIPERXVALIDL4_ipd after IN_DELAY; + PIPERXVALIDL5_indelay <= PIPERXVALIDL5_ipd after IN_DELAY; + PIPERXVALIDL6_indelay <= PIPERXVALIDL6_ipd after IN_DELAY; + PIPERXVALIDL7_indelay <= PIPERXVALIDL7_ipd after IN_DELAY; + + + pcie_internal_1_1_swift_bw_1 : PCIE_INTERNAL_1_1_SWIFT + port map ( + MCACTIVELANESIN => ACTIVELANESIN_BINARY, + MCAERBASEPTR => AERBASEPTR_BINARY, + MCAERCAPABILITYECRCCHECKCAPABLE => AERCAPABILITYECRCCHECKCAPABLE_BINARY, + MCAERCAPABILITYECRCGENCAPABLE => AERCAPABILITYECRCGENCAPABLE_BINARY, + MCAERCAPABILITYNEXTPTR => AERCAPABILITYNEXTPTR_BINARY, + MCBAR0ADDRWIDTH => BAR0ADDRWIDTH_BINARY, + MCBAR0EXIST => BAR0EXIST_BINARY, + MCBAR0IOMEMN => BAR0IOMEMN_BINARY, + MCBAR0MASKWIDTH => BAR0MASKWIDTH_BINARY, + MCBAR0PREFETCHABLE => BAR0PREFETCHABLE_BINARY, + MCBAR1ADDRWIDTH => BAR1ADDRWIDTH_BINARY, + MCBAR1EXIST => BAR1EXIST_BINARY, + MCBAR1IOMEMN => BAR1IOMEMN_BINARY, + MCBAR1MASKWIDTH => BAR1MASKWIDTH_BINARY, + MCBAR1PREFETCHABLE => BAR1PREFETCHABLE_BINARY, + MCBAR2ADDRWIDTH => BAR2ADDRWIDTH_BINARY, + MCBAR2EXIST => BAR2EXIST_BINARY, + MCBAR2IOMEMN => BAR2IOMEMN_BINARY, + MCBAR2MASKWIDTH => BAR2MASKWIDTH_BINARY, + MCBAR2PREFETCHABLE => BAR2PREFETCHABLE_BINARY, + MCBAR3ADDRWIDTH => BAR3ADDRWIDTH_BINARY, + MCBAR3EXIST => BAR3EXIST_BINARY, + MCBAR3IOMEMN => BAR3IOMEMN_BINARY, + MCBAR3MASKWIDTH => BAR3MASKWIDTH_BINARY, + MCBAR3PREFETCHABLE => BAR3PREFETCHABLE_BINARY, + MCBAR4ADDRWIDTH => BAR4ADDRWIDTH_BINARY, + MCBAR4EXIST => BAR4EXIST_BINARY, + MCBAR4IOMEMN => BAR4IOMEMN_BINARY, + MCBAR4MASKWIDTH => BAR4MASKWIDTH_BINARY, + MCBAR4PREFETCHABLE => BAR4PREFETCHABLE_BINARY, + MCBAR5ADDRWIDTH => BAR5ADDRWIDTH_BINARY, + MCBAR5EXIST => BAR5EXIST_BINARY, + MCBAR5IOMEMN => BAR5IOMEMN_BINARY, + MCBAR5MASKWIDTH => BAR5MASKWIDTH_BINARY, + MCBAR5PREFETCHABLE => BAR5PREFETCHABLE_BINARY, + MCCAPABILITIESPOINTER => CAPABILITIESPOINTER_BINARY, + MCCARDBUSCISPOINTER => CARDBUSCISPOINTER_BINARY, + MCCLASSCODE => CLASSCODE_BINARY, +-- MCCLKDIVIDED => CLKDIVIDED_BINARY, + MCCONFIGROUTING => CONFIGROUTING_BINARY, + MCDEVICECAPABILITYENDPOINTL0SLATENCY => DEVICECAPABILITYENDPOINTL0SLATENCY_BINARY, + MCDEVICECAPABILITYENDPOINTL1LATENCY => DEVICECAPABILITYENDPOINTL1LATENCY_BINARY, + MCDEVICEID => DEVICEID_BINARY, + MCDEVICESERIALNUMBER => DEVICESERIALNUMBER_BINARY, + MCDSNBASEPTR => DSNBASEPTR_BINARY, + MCDSNCAPABILITYNEXTPTR => DSNCAPABILITYNEXTPTR_BINARY, + MCDUALCOREENABLE => DUALCOREENABLE_BINARY, + MCDUALCORESLAVE => DUALCORESLAVE_BINARY, + MCDUALROLECFGCNTRLROOTEPN => DUALROLECFGCNTRLROOTEPN_BINARY, + MCEXTCFGCAPPTR => EXTCFGCAPPTR_BINARY, + MCEXTCFGXPCAPPTR => EXTCFGXPCAPPTR_BINARY, + MCHEADERTYPE => HEADERTYPE_BINARY, + MCINFINITECOMPLETIONS => INFINITECOMPLETIONS_BINARY, + MCINTERRUPTPIN => INTERRUPTPIN_BINARY, + MCISSWITCH => ISSWITCH_BINARY, + MCL0SEXITLATENCY => L0SEXITLATENCY_BINARY, + MCL0SEXITLATENCYCOMCLK => L0SEXITLATENCYCOMCLK_BINARY, + MCL1EXITLATENCY => L1EXITLATENCY_BINARY, + MCL1EXITLATENCYCOMCLK => L1EXITLATENCYCOMCLK_BINARY, + MCLINKCAPABILITYASPMSUPPORT => LINKCAPABILITYASPMSUPPORT_BINARY, + MCLINKCAPABILITYMAXLINKWIDTH => LINKCAPABILITYMAXLINKWIDTH_BINARY, + MCLINKSTATUSSLOTCLOCKCONFIG => LINKSTATUSSLOTCLOCKCONFIG_BINARY, + MCLLKBYPASS => LLKBYPASS_BINARY, + MCLOWPRIORITYVCCOUNT => LOWPRIORITYVCCOUNT_BINARY, + MCMSIBASEPTR => MSIBASEPTR_BINARY, + MCMSICAPABILITYMULTIMSGCAP => MSICAPABILITYMULTIMSGCAP_BINARY, + MCMSICAPABILITYNEXTPTR => MSICAPABILITYNEXTPTR_BINARY, + MCPBBASEPTR => PBBASEPTR_BINARY, + MCPBCAPABILITYDW0BASEPOWER => PBCAPABILITYDW0BASEPOWER_BINARY, + MCPBCAPABILITYDW0DATASCALE => PBCAPABILITYDW0DATASCALE_BINARY, + MCPBCAPABILITYDW0PMSTATE => PBCAPABILITYDW0PMSTATE_BINARY, + MCPBCAPABILITYDW0PMSUBSTATE => PBCAPABILITYDW0PMSUBSTATE_BINARY, + MCPBCAPABILITYDW0POWERRAIL => PBCAPABILITYDW0POWERRAIL_BINARY, + MCPBCAPABILITYDW0TYPE => PBCAPABILITYDW0TYPE_BINARY, + MCPBCAPABILITYDW1BASEPOWER => PBCAPABILITYDW1BASEPOWER_BINARY, + MCPBCAPABILITYDW1DATASCALE => PBCAPABILITYDW1DATASCALE_BINARY, + MCPBCAPABILITYDW1PMSTATE => PBCAPABILITYDW1PMSTATE_BINARY, + MCPBCAPABILITYDW1PMSUBSTATE => PBCAPABILITYDW1PMSUBSTATE_BINARY, + MCPBCAPABILITYDW1POWERRAIL => PBCAPABILITYDW1POWERRAIL_BINARY, + MCPBCAPABILITYDW1TYPE => PBCAPABILITYDW1TYPE_BINARY, + MCPBCAPABILITYDW2BASEPOWER => PBCAPABILITYDW2BASEPOWER_BINARY, + MCPBCAPABILITYDW2DATASCALE => PBCAPABILITYDW2DATASCALE_BINARY, + MCPBCAPABILITYDW2PMSTATE => PBCAPABILITYDW2PMSTATE_BINARY, + MCPBCAPABILITYDW2PMSUBSTATE => PBCAPABILITYDW2PMSUBSTATE_BINARY, + MCPBCAPABILITYDW2POWERRAIL => PBCAPABILITYDW2POWERRAIL_BINARY, + MCPBCAPABILITYDW2TYPE => PBCAPABILITYDW2TYPE_BINARY, + MCPBCAPABILITYDW3BASEPOWER => PBCAPABILITYDW3BASEPOWER_BINARY, + MCPBCAPABILITYDW3DATASCALE => PBCAPABILITYDW3DATASCALE_BINARY, + MCPBCAPABILITYDW3PMSTATE => PBCAPABILITYDW3PMSTATE_BINARY, + MCPBCAPABILITYDW3PMSUBSTATE => PBCAPABILITYDW3PMSUBSTATE_BINARY, + MCPBCAPABILITYDW3POWERRAIL => PBCAPABILITYDW3POWERRAIL_BINARY, + MCPBCAPABILITYDW3TYPE => PBCAPABILITYDW3TYPE_BINARY, + MCPBCAPABILITYNEXTPTR => PBCAPABILITYNEXTPTR_BINARY, + MCPBCAPABILITYSYSTEMALLOCATED => PBCAPABILITYSYSTEMALLOCATED_BINARY, + MCPCIECAPABILITYINTMSGNUM => PCIECAPABILITYINTMSGNUM_BINARY, + MCPCIECAPABILITYNEXTPTR => PCIECAPABILITYNEXTPTR_BINARY, + MCPCIECAPABILITYSLOTIMPL => PCIECAPABILITYSLOTIMPL_BINARY, + MCPCIEREVISION => PCIEREVISION_BINARY, + MCPMBASEPTR => PMBASEPTR_BINARY, + MCPMCAPABILITYAUXCURRENT => PMCAPABILITYAUXCURRENT_BINARY, + MCPMCAPABILITYD1SUPPORT => PMCAPABILITYD1SUPPORT_BINARY, + MCPMCAPABILITYD2SUPPORT => PMCAPABILITYD2SUPPORT_BINARY, + MCPMCAPABILITYDSI => PMCAPABILITYDSI_BINARY, + MCPMCAPABILITYNEXTPTR => PMCAPABILITYNEXTPTR_BINARY, + MCPMCAPABILITYPMESUPPORT => PMCAPABILITYPMESUPPORT_BINARY, + MCPMDATA0 => PMDATA0_BINARY, + MCPMDATA1 => PMDATA1_BINARY, + MCPMDATA2 => PMDATA2_BINARY, + MCPMDATA3 => PMDATA3_BINARY, + MCPMDATA4 => PMDATA4_BINARY, + MCPMDATA5 => PMDATA5_BINARY, + MCPMDATA6 => PMDATA6_BINARY, + MCPMDATA7 => PMDATA7_BINARY, + MCPMDATA8 => PMDATA8_BINARY, + MCPMDATASCALE0 => PMDATASCALE0_BINARY, + MCPMDATASCALE1 => PMDATASCALE1_BINARY, + MCPMDATASCALE2 => PMDATASCALE2_BINARY, + MCPMDATASCALE3 => PMDATASCALE3_BINARY, + MCPMDATASCALE4 => PMDATASCALE4_BINARY, + MCPMDATASCALE5 => PMDATASCALE5_BINARY, + MCPMDATASCALE6 => PMDATASCALE6_BINARY, + MCPMDATASCALE7 => PMDATASCALE7_BINARY, + MCPMDATASCALE8 => PMDATASCALE8_BINARY, + MCPMSTATUSCONTROLDATASCALE => PMSTATUSCONTROLDATASCALE_BINARY, + MCPORTVCCAPABILITYEXTENDEDVCCOUNT => PORTVCCAPABILITYEXTENDEDVCCOUNT_BINARY, + MCPORTVCCAPABILITYVCARBCAP => PORTVCCAPABILITYVCARBCAP_BINARY, + MCPORTVCCAPABILITYVCARBTABLEOFFSET => PORTVCCAPABILITYVCARBTABLEOFFSET_BINARY, + MCRAMSHARETXRX => RAMSHARETXRX_BINARY, + MCRESETMODE => RESETMODE_BINARY, + MCRETRYRAMREADLATENCY => RETRYRAMREADLATENCY_BINARY, + MCRETRYRAMSIZE => RETRYRAMSIZE_BINARY, + MCRETRYRAMWIDTH => RETRYRAMWIDTH_BINARY, + MCRETRYRAMWRITELATENCY => RETRYRAMWRITELATENCY_BINARY, + MCRETRYREADADDRPIPE => RETRYREADADDRPIPE_BINARY, + MCRETRYREADDATAPIPE => RETRYREADDATAPIPE_BINARY, + MCRETRYWRITEPIPE => RETRYWRITEPIPE_BINARY, + MCREVISIONID => REVISIONID_BINARY, + MCRXREADADDRPIPE => RXREADADDRPIPE_BINARY, + MCRXREADDATAPIPE => RXREADDATAPIPE_BINARY, + MCRXWRITEPIPE => RXWRITEPIPE_BINARY, + MCSELECTASMODE => SELECTASMODE_BINARY, + MCSELECTDLLIF => SELECTDLLIF_BINARY, + MCSLOTCAPABILITYATTBUTTONPRESENT => SLOTCAPABILITYATTBUTTONPRESENT_BINARY, + MCSLOTCAPABILITYATTINDICATORPRESENT => SLOTCAPABILITYATTINDICATORPRESENT_BINARY, + MCSLOTCAPABILITYHOTPLUGCAPABLE => SLOTCAPABILITYHOTPLUGCAPABLE_BINARY, + MCSLOTCAPABILITYHOTPLUGSURPRISE => SLOTCAPABILITYHOTPLUGSURPRISE_BINARY, + MCSLOTCAPABILITYMSLSENSORPRESENT => SLOTCAPABILITYMSLSENSORPRESENT_BINARY, + MCSLOTCAPABILITYPHYSICALSLOTNUM => SLOTCAPABILITYPHYSICALSLOTNUM_BINARY, + MCSLOTCAPABILITYPOWERCONTROLLERPRESENT => SLOTCAPABILITYPOWERCONTROLLERPRESENT_BINARY, + MCSLOTCAPABILITYPOWERINDICATORPRESENT => SLOTCAPABILITYPOWERINDICATORPRESENT_BINARY, + MCSLOTCAPABILITYSLOTPOWERLIMITSCALE => SLOTCAPABILITYSLOTPOWERLIMITSCALE_BINARY, + MCSLOTCAPABILITYSLOTPOWERLIMITVALUE => SLOTCAPABILITYSLOTPOWERLIMITVALUE_BINARY, + MCSLOTIMPLEMENTED => SLOTIMPLEMENTED_BINARY, + MCSUBSYSTEMID => SUBSYSTEMID_BINARY, + MCSUBSYSTEMVENDORID => SUBSYSTEMVENDORID_BINARY, + MCTLRAMREADLATENCY => TLRAMREADLATENCY_BINARY, + MCTLRAMWIDTH => TLRAMWIDTH_BINARY, + MCTLRAMWRITELATENCY => TLRAMWRITELATENCY_BINARY, + MCTXREADADDRPIPE => TXREADADDRPIPE_BINARY, + MCTXREADDATAPIPE => TXREADDATAPIPE_BINARY, + MCTXTSNFTS => TXTSNFTS_BINARY, + MCTXTSNFTSCOMCLK => TXTSNFTSCOMCLK_BINARY, + MCTXWRITEPIPE => TXWRITEPIPE_BINARY, + MCUPSTREAMFACING => UPSTREAMFACING_BINARY, + MCVC0RXFIFOBASEC => VC0RXFIFOBASEC_BINARY, + MCVC0RXFIFOBASENP => VC0RXFIFOBASENP_BINARY, + MCVC0RXFIFOBASEP => VC0RXFIFOBASEP_BINARY, + MCVC0RXFIFOLIMITC => VC0RXFIFOLIMITC_BINARY, + MCVC0RXFIFOLIMITNP => VC0RXFIFOLIMITNP_BINARY, + MCVC0RXFIFOLIMITP => VC0RXFIFOLIMITP_BINARY, + MCVC0TOTALCREDITSCD => VC0TOTALCREDITSCD_BINARY, + MCVC0TOTALCREDITSCH => VC0TOTALCREDITSCH_BINARY, + MCVC0TOTALCREDITSNPH => VC0TOTALCREDITSNPH_BINARY, + MCVC0TOTALCREDITSPD => VC0TOTALCREDITSPD_BINARY, + MCVC0TOTALCREDITSPH => VC0TOTALCREDITSPH_BINARY, + MCVC0TXFIFOBASEC => VC0TXFIFOBASEC_BINARY, + MCVC0TXFIFOBASENP => VC0TXFIFOBASENP_BINARY, + MCVC0TXFIFOBASEP => VC0TXFIFOBASEP_BINARY, + MCVC0TXFIFOLIMITC => VC0TXFIFOLIMITC_BINARY, + MCVC0TXFIFOLIMITNP => VC0TXFIFOLIMITNP_BINARY, + MCVC0TXFIFOLIMITP => VC0TXFIFOLIMITP_BINARY, + MCVC1RXFIFOBASEC => VC1RXFIFOBASEC_BINARY, + MCVC1RXFIFOBASENP => VC1RXFIFOBASENP_BINARY, + MCVC1RXFIFOBASEP => VC1RXFIFOBASEP_BINARY, + MCVC1RXFIFOLIMITC => VC1RXFIFOLIMITC_BINARY, + MCVC1RXFIFOLIMITNP => VC1RXFIFOLIMITNP_BINARY, + MCVC1RXFIFOLIMITP => VC1RXFIFOLIMITP_BINARY, + MCVC1TOTALCREDITSCD => VC1TOTALCREDITSCD_BINARY, + MCVC1TOTALCREDITSCH => VC1TOTALCREDITSCH_BINARY, + MCVC1TOTALCREDITSNPH => VC1TOTALCREDITSNPH_BINARY, + MCVC1TOTALCREDITSPD => VC1TOTALCREDITSPD_BINARY, + MCVC1TOTALCREDITSPH => VC1TOTALCREDITSPH_BINARY, + MCVC1TXFIFOBASEC => VC1TXFIFOBASEC_BINARY, + MCVC1TXFIFOBASENP => VC1TXFIFOBASENP_BINARY, + MCVC1TXFIFOBASEP => VC1TXFIFOBASEP_BINARY, + MCVC1TXFIFOLIMITC => VC1TXFIFOLIMITC_BINARY, + MCVC1TXFIFOLIMITNP => VC1TXFIFOLIMITNP_BINARY, + MCVC1TXFIFOLIMITP => VC1TXFIFOLIMITP_BINARY, + MCVCBASEPTR => VCBASEPTR_BINARY, + MCVCCAPABILITYNEXTPTR => VCCAPABILITYNEXTPTR_BINARY, + MCVENDORID => VENDORID_BINARY, + MCXLINKSUPPORTED => XLINKSUPPORTED_BINARY, + MCXPBASEPTR => XPBASEPTR_BINARY, + MCXPDEVICEPORTTYPE => XPDEVICEPORTTYPE_BINARY, + MCXPMAXPAYLOAD => XPMAXPAYLOAD_BINARY, + MCXPRCBCONTROL => XPRCBCONTROL_BINARY, + + BUSMASTERENABLE => BUSMASTERENABLE_outdelay, + CRMDOHOTRESETN => CRMDOHOTRESETN_outdelay, + CRMPWRSOFTRESETN => CRMPWRSOFTRESETN_outdelay, + CRMRXHOTRESETN => CRMRXHOTRESETN_outdelay, + DLLTXPMDLLPOUTSTANDING => DLLTXPMDLLPOUTSTANDING_outdelay, + INTERRUPTDISABLE => INTERRUPTDISABLE_outdelay, + IOSPACEENABLE => IOSPACEENABLE_outdelay, + L0ASAUTONOMOUSINITCOMPLETED => L0ASAUTONOMOUSINITCOMPLETED_outdelay, + L0ATTENTIONINDICATORCONTROL => L0ATTENTIONINDICATORCONTROL_outdelay, + L0CFGLOOPBACKACK => L0CFGLOOPBACKACK_outdelay, + L0COMPLETERID => L0COMPLETERID_outdelay, + L0CORRERRMSGRCVD => L0CORRERRMSGRCVD_outdelay, + L0DLLASRXSTATE => L0DLLASRXSTATE_outdelay, + L0DLLASTXSTATE => L0DLLASTXSTATE_outdelay, + L0DLLERRORVECTOR => L0DLLERRORVECTOR_outdelay, + L0DLLRXACKOUTSTANDING => L0DLLRXACKOUTSTANDING_outdelay, + L0DLLTXNONFCOUTSTANDING => L0DLLTXNONFCOUTSTANDING_outdelay, + L0DLLTXOUTSTANDING => L0DLLTXOUTSTANDING_outdelay, + L0DLLVCSTATUS => L0DLLVCSTATUS_outdelay, + L0DLUPDOWN => L0DLUPDOWN_outdelay, + L0ERRMSGREQID => L0ERRMSGREQID_outdelay, + L0FATALERRMSGRCVD => L0FATALERRMSGRCVD_outdelay, + L0FIRSTCFGWRITEOCCURRED => L0FIRSTCFGWRITEOCCURRED_outdelay, + L0FWDCORRERROUT => L0FWDCORRERROUT_outdelay, + L0FWDFATALERROUT => L0FWDFATALERROUT_outdelay, + L0FWDNONFATALERROUT => L0FWDNONFATALERROUT_outdelay, + L0LTSSMSTATE => L0LTSSMSTATE_outdelay, + L0MACENTEREDL0 => L0MACENTEREDL0_outdelay, + L0MACLINKTRAINING => L0MACLINKTRAINING_outdelay, + L0MACLINKUP => L0MACLINKUP_outdelay, + L0MACNEGOTIATEDLINKWIDTH => L0MACNEGOTIATEDLINKWIDTH_outdelay, + L0MACNEWSTATEACK => L0MACNEWSTATEACK_outdelay, + L0MACRXL0SSTATE => L0MACRXL0SSTATE_outdelay, + L0MACUPSTREAMDOWNSTREAM => L0MACUPSTREAMDOWNSTREAM_outdelay, + L0MCFOUND => L0MCFOUND_outdelay, + L0MSIENABLE0 => L0MSIENABLE0_outdelay, + L0MULTIMSGEN0 => L0MULTIMSGEN0_outdelay, + L0NONFATALERRMSGRCVD => L0NONFATALERRMSGRCVD_outdelay, + L0PMEACK => L0PMEACK_outdelay, + L0PMEEN => L0PMEEN_outdelay, + L0PMEREQOUT => L0PMEREQOUT_outdelay, + L0POWERCONTROLLERCONTROL => L0POWERCONTROLLERCONTROL_outdelay, + L0POWERINDICATORCONTROL => L0POWERINDICATORCONTROL_outdelay, + L0PWRINHIBITTRANSFERS => L0PWRINHIBITTRANSFERS_outdelay, + L0PWRL1STATE => L0PWRL1STATE_outdelay, + L0PWRL23READYDEVICE => L0PWRL23READYDEVICE_outdelay, + L0PWRL23READYSTATE => L0PWRL23READYSTATE_outdelay, + L0PWRSTATE0 => L0PWRSTATE0_outdelay, + L0PWRTURNOFFREQ => L0PWRTURNOFFREQ_outdelay, + L0PWRTXL0SSTATE => L0PWRTXL0SSTATE_outdelay, + L0RECEIVEDASSERTINTALEGACYINT => L0RECEIVEDASSERTINTALEGACYINT_outdelay, + L0RECEIVEDASSERTINTBLEGACYINT => L0RECEIVEDASSERTINTBLEGACYINT_outdelay, + L0RECEIVEDASSERTINTCLEGACYINT => L0RECEIVEDASSERTINTCLEGACYINT_outdelay, + L0RECEIVEDASSERTINTDLEGACYINT => L0RECEIVEDASSERTINTDLEGACYINT_outdelay, + L0RECEIVEDDEASSERTINTALEGACYINT => L0RECEIVEDDEASSERTINTALEGACYINT_outdelay, + L0RECEIVEDDEASSERTINTBLEGACYINT => L0RECEIVEDDEASSERTINTBLEGACYINT_outdelay, + L0RECEIVEDDEASSERTINTCLEGACYINT => L0RECEIVEDDEASSERTINTCLEGACYINT_outdelay, + L0RECEIVEDDEASSERTINTDLEGACYINT => L0RECEIVEDDEASSERTINTDLEGACYINT_outdelay, + L0RXBEACON => L0RXBEACON_outdelay, + L0RXDLLFCCMPLMCCRED => L0RXDLLFCCMPLMCCRED_outdelay, + L0RXDLLFCCMPLMCUPDATE => L0RXDLLFCCMPLMCUPDATE_outdelay, + L0RXDLLFCNPOSTBYPCRED => L0RXDLLFCNPOSTBYPCRED_outdelay, + L0RXDLLFCNPOSTBYPUPDATE => L0RXDLLFCNPOSTBYPUPDATE_outdelay, + L0RXDLLFCPOSTORDCRED => L0RXDLLFCPOSTORDCRED_outdelay, + L0RXDLLFCPOSTORDUPDATE => L0RXDLLFCPOSTORDUPDATE_outdelay, + L0RXDLLPM => L0RXDLLPM_outdelay, + L0RXDLLPMTYPE => L0RXDLLPMTYPE_outdelay, + L0RXDLLSBFCDATA => L0RXDLLSBFCDATA_outdelay, + L0RXDLLSBFCUPDATE => L0RXDLLSBFCUPDATE_outdelay, + L0RXDLLTLPECRCOK => L0RXDLLTLPECRCOK_outdelay, + L0RXDLLTLPEND => L0RXDLLTLPEND_outdelay, + L0RXMACLINKERROR => L0RXMACLINKERROR_outdelay, + L0STATSCFGOTHERRECEIVED => L0STATSCFGOTHERRECEIVED_outdelay, + L0STATSCFGOTHERTRANSMITTED => L0STATSCFGOTHERTRANSMITTED_outdelay, + L0STATSCFGRECEIVED => L0STATSCFGRECEIVED_outdelay, + L0STATSCFGTRANSMITTED => L0STATSCFGTRANSMITTED_outdelay, + L0STATSDLLPRECEIVED => L0STATSDLLPRECEIVED_outdelay, + L0STATSDLLPTRANSMITTED => L0STATSDLLPTRANSMITTED_outdelay, + L0STATSOSRECEIVED => L0STATSOSRECEIVED_outdelay, + L0STATSOSTRANSMITTED => L0STATSOSTRANSMITTED_outdelay, + L0STATSTLPRECEIVED => L0STATSTLPRECEIVED_outdelay, + L0STATSTLPTRANSMITTED => L0STATSTLPTRANSMITTED_outdelay, + L0TOGGLEELECTROMECHANICALINTERLOCK => L0TOGGLEELECTROMECHANICALINTERLOCK_outdelay, + L0TRANSFORMEDVC => L0TRANSFORMEDVC_outdelay, + L0TXDLLFCCMPLMCUPDATED => L0TXDLLFCCMPLMCUPDATED_outdelay, + L0TXDLLFCNPOSTBYPUPDATED => L0TXDLLFCNPOSTBYPUPDATED_outdelay, + L0TXDLLFCPOSTORDUPDATED => L0TXDLLFCPOSTORDUPDATED_outdelay, + L0TXDLLPMUPDATED => L0TXDLLPMUPDATED_outdelay, + L0TXDLLSBFCUPDATED => L0TXDLLSBFCUPDATED_outdelay, + L0UCBYPFOUND => L0UCBYPFOUND_outdelay, + L0UCORDFOUND => L0UCORDFOUND_outdelay, + L0UNLOCKRECEIVED => L0UNLOCKRECEIVED_outdelay, + LLKRX4DWHEADERN => LLKRX4DWHEADERN_outdelay, + LLKRXCHCOMPLETIONAVAILABLEN => LLKRXCHCOMPLETIONAVAILABLEN_outdelay, + LLKRXCHCOMPLETIONPARTIALN => LLKRXCHCOMPLETIONPARTIALN_outdelay, + LLKRXCHCONFIGAVAILABLEN => LLKRXCHCONFIGAVAILABLEN_outdelay, + LLKRXCHCONFIGPARTIALN => LLKRXCHCONFIGPARTIALN_outdelay, + LLKRXCHNONPOSTEDAVAILABLEN => LLKRXCHNONPOSTEDAVAILABLEN_outdelay, + LLKRXCHNONPOSTEDPARTIALN => LLKRXCHNONPOSTEDPARTIALN_outdelay, + LLKRXCHPOSTEDAVAILABLEN => LLKRXCHPOSTEDAVAILABLEN_outdelay, + LLKRXCHPOSTEDPARTIALN => LLKRXCHPOSTEDPARTIALN_outdelay, + LLKRXDATA => LLKRXDATA_outdelay, + LLKRXECRCBADN => LLKRXECRCBADN_outdelay, + LLKRXEOFN => LLKRXEOFN_outdelay, + LLKRXEOPN => LLKRXEOPN_outdelay, + LLKRXPREFERREDTYPE => LLKRXPREFERREDTYPE_outdelay, + LLKRXSOFN => LLKRXSOFN_outdelay, + LLKRXSOPN => LLKRXSOPN_outdelay, + LLKRXSRCDSCN => LLKRXSRCDSCN_outdelay, + LLKRXSRCLASTREQN => LLKRXSRCLASTREQN_outdelay, + LLKRXSRCRDYN => LLKRXSRCRDYN_outdelay, + LLKRXVALIDN => LLKRXVALIDN_outdelay, + LLKTCSTATUS => LLKTCSTATUS_outdelay, + LLKTXCHANSPACE => LLKTXCHANSPACE_outdelay, + LLKTXCHCOMPLETIONREADYN => LLKTXCHCOMPLETIONREADYN_outdelay, + LLKTXCHNONPOSTEDREADYN => LLKTXCHNONPOSTEDREADYN_outdelay, + LLKTXCHPOSTEDREADYN => LLKTXCHPOSTEDREADYN_outdelay, + LLKTXCONFIGREADYN => LLKTXCONFIGREADYN_outdelay, + LLKTXDSTRDYN => LLKTXDSTRDYN_outdelay, + MAXPAYLOADSIZE => MAXPAYLOADSIZE_outdelay, + MAXREADREQUESTSIZE => MAXREADREQUESTSIZE_outdelay, + MEMSPACEENABLE => MEMSPACEENABLE_outdelay, + MGMTPSO => MGMTPSO_outdelay, + MGMTRDATA => MGMTRDATA_outdelay, + MGMTSTATSCREDIT => MGMTSTATSCREDIT_outdelay, + MIMDLLBRADD => MIMDLLBRADD_outdelay, + MIMDLLBREN => MIMDLLBREN_outdelay, + MIMDLLBWADD => MIMDLLBWADD_outdelay, + MIMDLLBWDATA => MIMDLLBWDATA_outdelay, + MIMDLLBWEN => MIMDLLBWEN_outdelay, + MIMRXBRADD => MIMRXBRADD_outdelay, + MIMRXBREN => MIMRXBREN_outdelay, + MIMRXBWADD => MIMRXBWADD_outdelay, + MIMRXBWDATA => MIMRXBWDATA_outdelay, + MIMRXBWEN => MIMRXBWEN_outdelay, + MIMTXBRADD => MIMTXBRADD_outdelay, + MIMTXBREN => MIMTXBREN_outdelay, + MIMTXBWADD => MIMTXBWADD_outdelay, + MIMTXBWDATA => MIMTXBWDATA_outdelay, + MIMTXBWEN => MIMTXBWEN_outdelay, + PARITYERRORRESPONSE => PARITYERRORRESPONSE_outdelay, + PIPEDESKEWLANESL0 => PIPEDESKEWLANESL0_outdelay, + PIPEDESKEWLANESL1 => PIPEDESKEWLANESL1_outdelay, + PIPEDESKEWLANESL2 => PIPEDESKEWLANESL2_outdelay, + PIPEDESKEWLANESL3 => PIPEDESKEWLANESL3_outdelay, + PIPEDESKEWLANESL4 => PIPEDESKEWLANESL4_outdelay, + PIPEDESKEWLANESL5 => PIPEDESKEWLANESL5_outdelay, + PIPEDESKEWLANESL6 => PIPEDESKEWLANESL6_outdelay, + PIPEDESKEWLANESL7 => PIPEDESKEWLANESL7_outdelay, + PIPEPOWERDOWNL0 => PIPEPOWERDOWNL0_outdelay, + PIPEPOWERDOWNL1 => PIPEPOWERDOWNL1_outdelay, + PIPEPOWERDOWNL2 => PIPEPOWERDOWNL2_outdelay, + PIPEPOWERDOWNL3 => PIPEPOWERDOWNL3_outdelay, + PIPEPOWERDOWNL4 => PIPEPOWERDOWNL4_outdelay, + PIPEPOWERDOWNL5 => PIPEPOWERDOWNL5_outdelay, + PIPEPOWERDOWNL6 => PIPEPOWERDOWNL6_outdelay, + PIPEPOWERDOWNL7 => PIPEPOWERDOWNL7_outdelay, + PIPERESETL0 => PIPERESETL0_outdelay, + PIPERESETL1 => PIPERESETL1_outdelay, + PIPERESETL2 => PIPERESETL2_outdelay, + PIPERESETL3 => PIPERESETL3_outdelay, + PIPERESETL4 => PIPERESETL4_outdelay, + PIPERESETL5 => PIPERESETL5_outdelay, + PIPERESETL6 => PIPERESETL6_outdelay, + PIPERESETL7 => PIPERESETL7_outdelay, + PIPERXPOLARITYL0 => PIPERXPOLARITYL0_outdelay, + PIPERXPOLARITYL1 => PIPERXPOLARITYL1_outdelay, + PIPERXPOLARITYL2 => PIPERXPOLARITYL2_outdelay, + PIPERXPOLARITYL3 => PIPERXPOLARITYL3_outdelay, + PIPERXPOLARITYL4 => PIPERXPOLARITYL4_outdelay, + PIPERXPOLARITYL5 => PIPERXPOLARITYL5_outdelay, + PIPERXPOLARITYL6 => PIPERXPOLARITYL6_outdelay, + PIPERXPOLARITYL7 => PIPERXPOLARITYL7_outdelay, + PIPETXCOMPLIANCEL0 => PIPETXCOMPLIANCEL0_outdelay, + PIPETXCOMPLIANCEL1 => PIPETXCOMPLIANCEL1_outdelay, + PIPETXCOMPLIANCEL2 => PIPETXCOMPLIANCEL2_outdelay, + PIPETXCOMPLIANCEL3 => PIPETXCOMPLIANCEL3_outdelay, + PIPETXCOMPLIANCEL4 => PIPETXCOMPLIANCEL4_outdelay, + PIPETXCOMPLIANCEL5 => PIPETXCOMPLIANCEL5_outdelay, + PIPETXCOMPLIANCEL6 => PIPETXCOMPLIANCEL6_outdelay, + PIPETXCOMPLIANCEL7 => PIPETXCOMPLIANCEL7_outdelay, + PIPETXDATAKL0 => PIPETXDATAKL0_outdelay, + PIPETXDATAKL1 => PIPETXDATAKL1_outdelay, + PIPETXDATAKL2 => PIPETXDATAKL2_outdelay, + PIPETXDATAKL3 => PIPETXDATAKL3_outdelay, + PIPETXDATAKL4 => PIPETXDATAKL4_outdelay, + PIPETXDATAKL5 => PIPETXDATAKL5_outdelay, + PIPETXDATAKL6 => PIPETXDATAKL6_outdelay, + PIPETXDATAKL7 => PIPETXDATAKL7_outdelay, + PIPETXDATAL0 => PIPETXDATAL0_outdelay, + PIPETXDATAL1 => PIPETXDATAL1_outdelay, + PIPETXDATAL2 => PIPETXDATAL2_outdelay, + PIPETXDATAL3 => PIPETXDATAL3_outdelay, + PIPETXDATAL4 => PIPETXDATAL4_outdelay, + PIPETXDATAL5 => PIPETXDATAL5_outdelay, + PIPETXDATAL6 => PIPETXDATAL6_outdelay, + PIPETXDATAL7 => PIPETXDATAL7_outdelay, + PIPETXDETECTRXLOOPBACKL0 => PIPETXDETECTRXLOOPBACKL0_outdelay, + PIPETXDETECTRXLOOPBACKL1 => PIPETXDETECTRXLOOPBACKL1_outdelay, + PIPETXDETECTRXLOOPBACKL2 => PIPETXDETECTRXLOOPBACKL2_outdelay, + PIPETXDETECTRXLOOPBACKL3 => PIPETXDETECTRXLOOPBACKL3_outdelay, + PIPETXDETECTRXLOOPBACKL4 => PIPETXDETECTRXLOOPBACKL4_outdelay, + PIPETXDETECTRXLOOPBACKL5 => PIPETXDETECTRXLOOPBACKL5_outdelay, + PIPETXDETECTRXLOOPBACKL6 => PIPETXDETECTRXLOOPBACKL6_outdelay, + PIPETXDETECTRXLOOPBACKL7 => PIPETXDETECTRXLOOPBACKL7_outdelay, + PIPETXELECIDLEL0 => PIPETXELECIDLEL0_outdelay, + PIPETXELECIDLEL1 => PIPETXELECIDLEL1_outdelay, + PIPETXELECIDLEL2 => PIPETXELECIDLEL2_outdelay, + PIPETXELECIDLEL3 => PIPETXELECIDLEL3_outdelay, + PIPETXELECIDLEL4 => PIPETXELECIDLEL4_outdelay, + PIPETXELECIDLEL5 => PIPETXELECIDLEL5_outdelay, + PIPETXELECIDLEL6 => PIPETXELECIDLEL6_outdelay, + PIPETXELECIDLEL7 => PIPETXELECIDLEL7_outdelay, + SERRENABLE => SERRENABLE_outdelay, + URREPORTINGENABLE => URREPORTINGENABLE_outdelay, + + AUXPOWER => AUXPOWER_indelay, + CFGNEGOTIATEDLINKWIDTH => CFGNEGOTIATEDLINKWIDTH_indelay, + COMPLIANCEAVOID => COMPLIANCEAVOID_indelay, + CRMCFGBRIDGEHOTRESET => CRMCFGBRIDGEHOTRESET_indelay, + CRMCORECLK => CRMCORECLK_indelay, + CRMCORECLKDLO => CRMCORECLKDLO_indelay, + CRMCORECLKRXO => CRMCORECLKRXO_indelay, + CRMCORECLKTXO => CRMCORECLKTXO_indelay, + CRMLINKRSTN => CRMLINKRSTN_indelay, + CRMMACRSTN => CRMMACRSTN_indelay, + CRMMGMTRSTN => CRMMGMTRSTN_indelay, + CRMNVRSTN => CRMNVRSTN_indelay, + CRMTXHOTRESETN => CRMTXHOTRESETN_indelay, + CRMURSTN => CRMURSTN_indelay, + CRMUSERCFGRSTN => CRMUSERCFGRSTN_indelay, + CRMUSERCLK => CRMUSERCLK_indelay, + CRMUSERCLKRXO => CRMUSERCLKRXO_indelay, + CRMUSERCLKTXO => CRMUSERCLKTXO_indelay, + CROSSLINKSEED => CROSSLINKSEED_indelay, + GSR => GSR, + L0ACKNAKTIMERADJUSTMENT => L0ACKNAKTIMERADJUSTMENT_indelay, + L0ALLDOWNPORTSINL1 => L0ALLDOWNPORTSINL1_indelay, + L0ALLDOWNRXPORTSINL0S => L0ALLDOWNRXPORTSINL0S_indelay, + L0ASE => L0ASE_indelay, + L0ASPORTCOUNT => L0ASPORTCOUNT_indelay, + L0ASTURNPOOLBITSCONSUMED => L0ASTURNPOOLBITSCONSUMED_indelay, + L0ATTENTIONBUTTONPRESSED => L0ATTENTIONBUTTONPRESSED_indelay, + L0CFGASSPANTREEOWNEDSTATE => L0CFGASSPANTREEOWNEDSTATE_indelay, + L0CFGASSTATECHANGECMD => L0CFGASSTATECHANGECMD_indelay, + L0CFGDISABLESCRAMBLE => L0CFGDISABLESCRAMBLE_indelay, + L0CFGEXTENDEDSYNC => L0CFGEXTENDEDSYNC_indelay, + L0CFGL0SENTRYENABLE => L0CFGL0SENTRYENABLE_indelay, + L0CFGL0SENTRYSUP => L0CFGL0SENTRYSUP_indelay, + L0CFGL0SEXITLAT => L0CFGL0SEXITLAT_indelay, + L0CFGLINKDISABLE => L0CFGLINKDISABLE_indelay, + L0CFGLOOPBACKMASTER => L0CFGLOOPBACKMASTER_indelay, + L0CFGNEGOTIATEDMAXP => L0CFGNEGOTIATEDMAXP_indelay, + L0CFGVCENABLE => L0CFGVCENABLE_indelay, + L0CFGVCID => L0CFGVCID_indelay, + L0DLLHOLDLINKUP => L0DLLHOLDLINKUP_indelay, + L0ELECTROMECHANICALINTERLOCKENGAGED => L0ELECTROMECHANICALINTERLOCKENGAGED_indelay, + L0FWDASSERTINTALEGACYINT => L0FWDASSERTINTALEGACYINT_indelay, + L0FWDASSERTINTBLEGACYINT => L0FWDASSERTINTBLEGACYINT_indelay, + L0FWDASSERTINTCLEGACYINT => L0FWDASSERTINTCLEGACYINT_indelay, + L0FWDASSERTINTDLEGACYINT => L0FWDASSERTINTDLEGACYINT_indelay, + L0FWDCORRERRIN => L0FWDCORRERRIN_indelay, + L0FWDDEASSERTINTALEGACYINT => L0FWDDEASSERTINTALEGACYINT_indelay, + L0FWDDEASSERTINTBLEGACYINT => L0FWDDEASSERTINTBLEGACYINT_indelay, + L0FWDDEASSERTINTCLEGACYINT => L0FWDDEASSERTINTCLEGACYINT_indelay, + L0FWDDEASSERTINTDLEGACYINT => L0FWDDEASSERTINTDLEGACYINT_indelay, + L0FWDFATALERRIN => L0FWDFATALERRIN_indelay, + L0FWDNONFATALERRIN => L0FWDNONFATALERRIN_indelay, + L0LEGACYINTFUNCT0 => L0LEGACYINTFUNCT0_indelay, + L0MRLSENSORCLOSEDN => L0MRLSENSORCLOSEDN_indelay, + L0MSIREQUEST0 => L0MSIREQUEST0_indelay, + L0PACKETHEADERFROMUSER => L0PACKETHEADERFROMUSER_indelay, + L0PMEREQIN => L0PMEREQIN_indelay, + L0PORTNUMBER => L0PORTNUMBER_indelay, + L0POWERFAULTDETECTED => L0POWERFAULTDETECTED_indelay, + L0PRESENCEDETECTSLOTEMPTYN => L0PRESENCEDETECTSLOTEMPTYN_indelay, + L0PWRNEWSTATEREQ => L0PWRNEWSTATEREQ_indelay, + L0PWRNEXTLINKSTATE => L0PWRNEXTLINKSTATE_indelay, + L0REPLAYTIMERADJUSTMENT => L0REPLAYTIMERADJUSTMENT_indelay, + L0ROOTTURNOFFREQ => L0ROOTTURNOFFREQ_indelay, + L0RXTLTLPNONINITIALIZEDVC => L0RXTLTLPNONINITIALIZEDVC_indelay, + L0SENDUNLOCKMESSAGE => L0SENDUNLOCKMESSAGE_indelay, + L0SETCOMPLETERABORTERROR => L0SETCOMPLETERABORTERROR_indelay, + L0SETCOMPLETIONTIMEOUTCORRERROR => L0SETCOMPLETIONTIMEOUTCORRERROR_indelay, + L0SETCOMPLETIONTIMEOUTUNCORRERROR => L0SETCOMPLETIONTIMEOUTUNCORRERROR_indelay, + L0SETDETECTEDCORRERROR => L0SETDETECTEDCORRERROR_indelay, + L0SETDETECTEDFATALERROR => L0SETDETECTEDFATALERROR_indelay, + L0SETDETECTEDNONFATALERROR => L0SETDETECTEDNONFATALERROR_indelay, + L0SETLINKDETECTEDPARITYERROR => L0SETLINKDETECTEDPARITYERROR_indelay, + L0SETLINKMASTERDATAPARITY => L0SETLINKMASTERDATAPARITY_indelay, + L0SETLINKRECEIVEDMASTERABORT => L0SETLINKRECEIVEDMASTERABORT_indelay, + L0SETLINKRECEIVEDTARGETABORT => L0SETLINKRECEIVEDTARGETABORT_indelay, + L0SETLINKSIGNALLEDTARGETABORT => L0SETLINKSIGNALLEDTARGETABORT_indelay, + L0SETLINKSYSTEMERROR => L0SETLINKSYSTEMERROR_indelay, + L0SETUNEXPECTEDCOMPLETIONCORRERROR => L0SETUNEXPECTEDCOMPLETIONCORRERROR_indelay, + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR => L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_indelay, + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR => L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_indelay, + L0SETUNSUPPORTEDREQUESTOTHERERROR => L0SETUNSUPPORTEDREQUESTOTHERERROR_indelay, + L0SETUSERDETECTEDPARITYERROR => L0SETUSERDETECTEDPARITYERROR_indelay, + L0SETUSERMASTERDATAPARITY => L0SETUSERMASTERDATAPARITY_indelay, + L0SETUSERRECEIVEDMASTERABORT => L0SETUSERRECEIVEDMASTERABORT_indelay, + L0SETUSERRECEIVEDTARGETABORT => L0SETUSERRECEIVEDTARGETABORT_indelay, + L0SETUSERSIGNALLEDTARGETABORT => L0SETUSERSIGNALLEDTARGETABORT_indelay, + L0SETUSERSYSTEMERROR => L0SETUSERSYSTEMERROR_indelay, + L0TLASFCCREDSTARVATION => L0TLASFCCREDSTARVATION_indelay, + L0TLLINKRETRAIN => L0TLLINKRETRAIN_indelay, + L0TRANSACTIONSPENDING => L0TRANSACTIONSPENDING_indelay, + L0TXBEACON => L0TXBEACON_indelay, + L0TXCFGPM => L0TXCFGPM_indelay, + L0TXCFGPMTYPE => L0TXCFGPMTYPE_indelay, + L0TXTLFCCMPLMCCRED => L0TXTLFCCMPLMCCRED_indelay, + L0TXTLFCCMPLMCUPDATE => L0TXTLFCCMPLMCUPDATE_indelay, + L0TXTLFCNPOSTBYPCRED => L0TXTLFCNPOSTBYPCRED_indelay, + L0TXTLFCNPOSTBYPUPDATE => L0TXTLFCNPOSTBYPUPDATE_indelay, + L0TXTLFCPOSTORDCRED => L0TXTLFCPOSTORDCRED_indelay, + L0TXTLFCPOSTORDUPDATE => L0TXTLFCPOSTORDUPDATE_indelay, + L0TXTLSBFCDATA => L0TXTLSBFCDATA_indelay, + L0TXTLSBFCUPDATE => L0TXTLSBFCUPDATE_indelay, + L0TXTLTLPDATA => L0TXTLTLPDATA_indelay, + L0TXTLTLPEDB => L0TXTLTLPEDB_indelay, + L0TXTLTLPENABLE => L0TXTLTLPENABLE_indelay, + L0TXTLTLPEND => L0TXTLTLPEND_indelay, + L0TXTLTLPLATENCY => L0TXTLTLPLATENCY_indelay, + L0TXTLTLPREQ => L0TXTLTLPREQ_indelay, + L0TXTLTLPREQEND => L0TXTLTLPREQEND_indelay, + L0TXTLTLPWIDTH => L0TXTLTLPWIDTH_indelay, + L0UPSTREAMRXPORTINL0S => L0UPSTREAMRXPORTINL0S_indelay, + L0VC0PREVIEWEXPAND => L0VC0PREVIEWEXPAND_indelay, + L0WAKEN => L0WAKEN_indelay, + LLKRXCHFIFO => LLKRXCHFIFO_indelay, + LLKRXCHTC => LLKRXCHTC_indelay, + LLKRXDSTCONTREQN => LLKRXDSTCONTREQN_indelay, + LLKRXDSTREQN => LLKRXDSTREQN_indelay, + LLKTX4DWHEADERN => LLKTX4DWHEADERN_indelay, + LLKTXCHFIFO => LLKTXCHFIFO_indelay, + LLKTXCHTC => LLKTXCHTC_indelay, + LLKTXCOMPLETEN => LLKTXCOMPLETEN_indelay, + LLKTXCREATEECRCN => LLKTXCREATEECRCN_indelay, + LLKTXDATA => LLKTXDATA_indelay, + LLKTXENABLEN => LLKTXENABLEN_indelay, + LLKTXEOFN => LLKTXEOFN_indelay, + LLKTXEOPN => LLKTXEOPN_indelay, + LLKTXSOFN => LLKTXSOFN_indelay, + LLKTXSOPN => LLKTXSOPN_indelay, + LLKTXSRCDSCN => LLKTXSRCDSCN_indelay, + LLKTXSRCRDYN => LLKTXSRCRDYN_indelay, + MAINPOWER => MAINPOWER_indelay, + MGMTADDR => MGMTADDR_indelay, + MGMTBWREN => MGMTBWREN_indelay, + MGMTRDEN => MGMTRDEN_indelay, + MGMTSTATSCREDITSEL => MGMTSTATSCREDITSEL_indelay, + MGMTWDATA => MGMTWDATA_indelay, + MGMTWREN => MGMTWREN_indelay, + MIMDLLBRDATA => MIMDLLBRDATA_indelay, + MIMRXBRDATA => MIMRXBRDATA_indelay, + MIMTXBRDATA => MIMTXBRDATA_indelay, + PIPEPHYSTATUSL0 => PIPEPHYSTATUSL0_indelay, + PIPEPHYSTATUSL1 => PIPEPHYSTATUSL1_indelay, + PIPEPHYSTATUSL2 => PIPEPHYSTATUSL2_indelay, + PIPEPHYSTATUSL3 => PIPEPHYSTATUSL3_indelay, + PIPEPHYSTATUSL4 => PIPEPHYSTATUSL4_indelay, + PIPEPHYSTATUSL5 => PIPEPHYSTATUSL5_indelay, + PIPEPHYSTATUSL6 => PIPEPHYSTATUSL6_indelay, + PIPEPHYSTATUSL7 => PIPEPHYSTATUSL7_indelay, + PIPERXCHANISALIGNEDL0 => PIPERXCHANISALIGNEDL0_indelay, + PIPERXCHANISALIGNEDL1 => PIPERXCHANISALIGNEDL1_indelay, + PIPERXCHANISALIGNEDL2 => PIPERXCHANISALIGNEDL2_indelay, + PIPERXCHANISALIGNEDL3 => PIPERXCHANISALIGNEDL3_indelay, + PIPERXCHANISALIGNEDL4 => PIPERXCHANISALIGNEDL4_indelay, + PIPERXCHANISALIGNEDL5 => PIPERXCHANISALIGNEDL5_indelay, + PIPERXCHANISALIGNEDL6 => PIPERXCHANISALIGNEDL6_indelay, + PIPERXCHANISALIGNEDL7 => PIPERXCHANISALIGNEDL7_indelay, + PIPERXDATAKL0 => PIPERXDATAKL0_indelay, + PIPERXDATAKL1 => PIPERXDATAKL1_indelay, + PIPERXDATAKL2 => PIPERXDATAKL2_indelay, + PIPERXDATAKL3 => PIPERXDATAKL3_indelay, + PIPERXDATAKL4 => PIPERXDATAKL4_indelay, + PIPERXDATAKL5 => PIPERXDATAKL5_indelay, + PIPERXDATAKL6 => PIPERXDATAKL6_indelay, + PIPERXDATAKL7 => PIPERXDATAKL7_indelay, + PIPERXDATAL0 => PIPERXDATAL0_indelay, + PIPERXDATAL1 => PIPERXDATAL1_indelay, + PIPERXDATAL2 => PIPERXDATAL2_indelay, + PIPERXDATAL3 => PIPERXDATAL3_indelay, + PIPERXDATAL4 => PIPERXDATAL4_indelay, + PIPERXDATAL5 => PIPERXDATAL5_indelay, + PIPERXDATAL6 => PIPERXDATAL6_indelay, + PIPERXDATAL7 => PIPERXDATAL7_indelay, + PIPERXELECIDLEL0 => PIPERXELECIDLEL0_indelay, + PIPERXELECIDLEL1 => PIPERXELECIDLEL1_indelay, + PIPERXELECIDLEL2 => PIPERXELECIDLEL2_indelay, + PIPERXELECIDLEL3 => PIPERXELECIDLEL3_indelay, + PIPERXELECIDLEL4 => PIPERXELECIDLEL4_indelay, + PIPERXELECIDLEL5 => PIPERXELECIDLEL5_indelay, + PIPERXELECIDLEL6 => PIPERXELECIDLEL6_indelay, + PIPERXELECIDLEL7 => PIPERXELECIDLEL7_indelay, + PIPERXSTATUSL0 => PIPERXSTATUSL0_indelay, + PIPERXSTATUSL1 => PIPERXSTATUSL1_indelay, + PIPERXSTATUSL2 => PIPERXSTATUSL2_indelay, + PIPERXSTATUSL3 => PIPERXSTATUSL3_indelay, + PIPERXSTATUSL4 => PIPERXSTATUSL4_indelay, + PIPERXSTATUSL5 => PIPERXSTATUSL5_indelay, + PIPERXSTATUSL6 => PIPERXSTATUSL6_indelay, + PIPERXSTATUSL7 => PIPERXSTATUSL7_indelay, + PIPERXVALIDL0 => PIPERXVALIDL0_indelay, + PIPERXVALIDL1 => PIPERXVALIDL1_indelay, + PIPERXVALIDL2 => PIPERXVALIDL2_indelay, + PIPERXVALIDL3 => PIPERXVALIDL3_indelay, + PIPERXVALIDL4 => PIPERXVALIDL4_indelay, + PIPERXVALIDL5 => PIPERXVALIDL5_indelay, + PIPERXVALIDL6 => PIPERXVALIDL6_indelay, + PIPERXVALIDL7 => PIPERXVALIDL7_indelay + ); + + INIPROC : process + begin + case TXTSNFTS is + when 0 => TXTSNFTS_BINARY <= "00000000"; + when 1 => TXTSNFTS_BINARY <= "00000001"; + when 2 => TXTSNFTS_BINARY <= "00000010"; + when 3 => TXTSNFTS_BINARY <= "00000011"; + when 4 => TXTSNFTS_BINARY <= "00000100"; + when 5 => TXTSNFTS_BINARY <= "00000101"; + when 6 => TXTSNFTS_BINARY <= "00000110"; + when 7 => TXTSNFTS_BINARY <= "00000111"; + when 8 => TXTSNFTS_BINARY <= "00001000"; + when 9 => TXTSNFTS_BINARY <= "00001001"; + when 10 => TXTSNFTS_BINARY <= "00001010"; + when 11 => TXTSNFTS_BINARY <= "00001011"; + when 12 => TXTSNFTS_BINARY <= "00001100"; + when 13 => TXTSNFTS_BINARY <= "00001101"; + when 14 => TXTSNFTS_BINARY <= "00001110"; + when 15 => TXTSNFTS_BINARY <= "00001111"; + when 16 => TXTSNFTS_BINARY <= "00010000"; + when 17 => TXTSNFTS_BINARY <= "00010001"; + when 18 => TXTSNFTS_BINARY <= "00010010"; + when 19 => TXTSNFTS_BINARY <= "00010011"; + when 20 => TXTSNFTS_BINARY <= "00010100"; + when 21 => TXTSNFTS_BINARY <= "00010101"; + when 22 => TXTSNFTS_BINARY <= "00010110"; + when 23 => TXTSNFTS_BINARY <= "00010111"; + when 24 => TXTSNFTS_BINARY <= "00011000"; + when 25 => TXTSNFTS_BINARY <= "00011001"; + when 26 => TXTSNFTS_BINARY <= "00011010"; + when 27 => TXTSNFTS_BINARY <= "00011011"; + when 28 => TXTSNFTS_BINARY <= "00011100"; + when 29 => TXTSNFTS_BINARY <= "00011101"; + when 30 => TXTSNFTS_BINARY <= "00011110"; + when 31 => TXTSNFTS_BINARY <= "00011111"; + when 32 => TXTSNFTS_BINARY <= "00100000"; + when 33 => TXTSNFTS_BINARY <= "00100001"; + when 34 => TXTSNFTS_BINARY <= "00100010"; + when 35 => TXTSNFTS_BINARY <= "00100011"; + when 36 => TXTSNFTS_BINARY <= "00100100"; + when 37 => TXTSNFTS_BINARY <= "00100101"; + when 38 => TXTSNFTS_BINARY <= "00100110"; + when 39 => TXTSNFTS_BINARY <= "00100111"; + when 40 => TXTSNFTS_BINARY <= "00101000"; + when 41 => TXTSNFTS_BINARY <= "00101001"; + when 42 => TXTSNFTS_BINARY <= "00101010"; + when 43 => TXTSNFTS_BINARY <= "00101011"; + when 44 => TXTSNFTS_BINARY <= "00101100"; + when 45 => TXTSNFTS_BINARY <= "00101101"; + when 46 => TXTSNFTS_BINARY <= "00101110"; + when 47 => TXTSNFTS_BINARY <= "00101111"; + when 48 => TXTSNFTS_BINARY <= "00110000"; + when 49 => TXTSNFTS_BINARY <= "00110001"; + when 50 => TXTSNFTS_BINARY <= "00110010"; + when 51 => TXTSNFTS_BINARY <= "00110011"; + when 52 => TXTSNFTS_BINARY <= "00110100"; + when 53 => TXTSNFTS_BINARY <= "00110101"; + when 54 => TXTSNFTS_BINARY <= "00110110"; + when 55 => TXTSNFTS_BINARY <= "00110111"; + when 56 => TXTSNFTS_BINARY <= "00111000"; + when 57 => TXTSNFTS_BINARY <= "00111001"; + when 58 => TXTSNFTS_BINARY <= "00111010"; + when 59 => TXTSNFTS_BINARY <= "00111011"; + when 60 => TXTSNFTS_BINARY <= "00111100"; + when 61 => TXTSNFTS_BINARY <= "00111101"; + when 62 => TXTSNFTS_BINARY <= "00111110"; + when 63 => TXTSNFTS_BINARY <= "00111111"; + when 64 => TXTSNFTS_BINARY <= "01000000"; + when 65 => TXTSNFTS_BINARY <= "01000001"; + when 66 => TXTSNFTS_BINARY <= "01000010"; + when 67 => TXTSNFTS_BINARY <= "01000011"; + when 68 => TXTSNFTS_BINARY <= "01000100"; + when 69 => TXTSNFTS_BINARY <= "01000101"; + when 70 => TXTSNFTS_BINARY <= "01000110"; + when 71 => TXTSNFTS_BINARY <= "01000111"; + when 72 => TXTSNFTS_BINARY <= "01001000"; + when 73 => TXTSNFTS_BINARY <= "01001001"; + when 74 => TXTSNFTS_BINARY <= "01001010"; + when 75 => TXTSNFTS_BINARY <= "01001011"; + when 76 => TXTSNFTS_BINARY <= "01001100"; + when 77 => TXTSNFTS_BINARY <= "01001101"; + when 78 => TXTSNFTS_BINARY <= "01001110"; + when 79 => TXTSNFTS_BINARY <= "01001111"; + when 80 => TXTSNFTS_BINARY <= "01010000"; + when 81 => TXTSNFTS_BINARY <= "01010001"; + when 82 => TXTSNFTS_BINARY <= "01010010"; + when 83 => TXTSNFTS_BINARY <= "01010011"; + when 84 => TXTSNFTS_BINARY <= "01010100"; + when 85 => TXTSNFTS_BINARY <= "01010101"; + when 86 => TXTSNFTS_BINARY <= "01010110"; + when 87 => TXTSNFTS_BINARY <= "01010111"; + when 88 => TXTSNFTS_BINARY <= "01011000"; + when 89 => TXTSNFTS_BINARY <= "01011001"; + when 90 => TXTSNFTS_BINARY <= "01011010"; + when 91 => TXTSNFTS_BINARY <= "01011011"; + when 92 => TXTSNFTS_BINARY <= "01011100"; + when 93 => TXTSNFTS_BINARY <= "01011101"; + when 94 => TXTSNFTS_BINARY <= "01011110"; + when 95 => TXTSNFTS_BINARY <= "01011111"; + when 96 => TXTSNFTS_BINARY <= "01100000"; + when 97 => TXTSNFTS_BINARY <= "01100001"; + when 98 => TXTSNFTS_BINARY <= "01100010"; + when 99 => TXTSNFTS_BINARY <= "01100011"; + when 100 => TXTSNFTS_BINARY <= "01100100"; + when 101 => TXTSNFTS_BINARY <= "01100101"; + when 102 => TXTSNFTS_BINARY <= "01100110"; + when 103 => TXTSNFTS_BINARY <= "01100111"; + when 104 => TXTSNFTS_BINARY <= "01101000"; + when 105 => TXTSNFTS_BINARY <= "01101001"; + when 106 => TXTSNFTS_BINARY <= "01101010"; + when 107 => TXTSNFTS_BINARY <= "01101011"; + when 108 => TXTSNFTS_BINARY <= "01101100"; + when 109 => TXTSNFTS_BINARY <= "01101101"; + when 110 => TXTSNFTS_BINARY <= "01101110"; + when 111 => TXTSNFTS_BINARY <= "01101111"; + when 112 => TXTSNFTS_BINARY <= "01110000"; + when 113 => TXTSNFTS_BINARY <= "01110001"; + when 114 => TXTSNFTS_BINARY <= "01110010"; + when 115 => TXTSNFTS_BINARY <= "01110011"; + when 116 => TXTSNFTS_BINARY <= "01110100"; + when 117 => TXTSNFTS_BINARY <= "01110101"; + when 118 => TXTSNFTS_BINARY <= "01110110"; + when 119 => TXTSNFTS_BINARY <= "01110111"; + when 120 => TXTSNFTS_BINARY <= "01111000"; + when 121 => TXTSNFTS_BINARY <= "01111001"; + when 122 => TXTSNFTS_BINARY <= "01111010"; + when 123 => TXTSNFTS_BINARY <= "01111011"; + when 124 => TXTSNFTS_BINARY <= "01111100"; + when 125 => TXTSNFTS_BINARY <= "01111101"; + when 126 => TXTSNFTS_BINARY <= "01111110"; + when 127 => TXTSNFTS_BINARY <= "01111111"; + when 128 => TXTSNFTS_BINARY <= "10000000"; + when 129 => TXTSNFTS_BINARY <= "10000001"; + when 130 => TXTSNFTS_BINARY <= "10000010"; + when 131 => TXTSNFTS_BINARY <= "10000011"; + when 132 => TXTSNFTS_BINARY <= "10000100"; + when 133 => TXTSNFTS_BINARY <= "10000101"; + when 134 => TXTSNFTS_BINARY <= "10000110"; + when 135 => TXTSNFTS_BINARY <= "10000111"; + when 136 => TXTSNFTS_BINARY <= "10001000"; + when 137 => TXTSNFTS_BINARY <= "10001001"; + when 138 => TXTSNFTS_BINARY <= "10001010"; + when 139 => TXTSNFTS_BINARY <= "10001011"; + when 140 => TXTSNFTS_BINARY <= "10001100"; + when 141 => TXTSNFTS_BINARY <= "10001101"; + when 142 => TXTSNFTS_BINARY <= "10001110"; + when 143 => TXTSNFTS_BINARY <= "10001111"; + when 144 => TXTSNFTS_BINARY <= "10010000"; + when 145 => TXTSNFTS_BINARY <= "10010001"; + when 146 => TXTSNFTS_BINARY <= "10010010"; + when 147 => TXTSNFTS_BINARY <= "10010011"; + when 148 => TXTSNFTS_BINARY <= "10010100"; + when 149 => TXTSNFTS_BINARY <= "10010101"; + when 150 => TXTSNFTS_BINARY <= "10010110"; + when 151 => TXTSNFTS_BINARY <= "10010111"; + when 152 => TXTSNFTS_BINARY <= "10011000"; + when 153 => TXTSNFTS_BINARY <= "10011001"; + when 154 => TXTSNFTS_BINARY <= "10011010"; + when 155 => TXTSNFTS_BINARY <= "10011011"; + when 156 => TXTSNFTS_BINARY <= "10011100"; + when 157 => TXTSNFTS_BINARY <= "10011101"; + when 158 => TXTSNFTS_BINARY <= "10011110"; + when 159 => TXTSNFTS_BINARY <= "10011111"; + when 160 => TXTSNFTS_BINARY <= "10100000"; + when 161 => TXTSNFTS_BINARY <= "10100001"; + when 162 => TXTSNFTS_BINARY <= "10100010"; + when 163 => TXTSNFTS_BINARY <= "10100011"; + when 164 => TXTSNFTS_BINARY <= "10100100"; + when 165 => TXTSNFTS_BINARY <= "10100101"; + when 166 => TXTSNFTS_BINARY <= "10100110"; + when 167 => TXTSNFTS_BINARY <= "10100111"; + when 168 => TXTSNFTS_BINARY <= "10101000"; + when 169 => TXTSNFTS_BINARY <= "10101001"; + when 170 => TXTSNFTS_BINARY <= "10101010"; + when 171 => TXTSNFTS_BINARY <= "10101011"; + when 172 => TXTSNFTS_BINARY <= "10101100"; + when 173 => TXTSNFTS_BINARY <= "10101101"; + when 174 => TXTSNFTS_BINARY <= "10101110"; + when 175 => TXTSNFTS_BINARY <= "10101111"; + when 176 => TXTSNFTS_BINARY <= "10110000"; + when 177 => TXTSNFTS_BINARY <= "10110001"; + when 178 => TXTSNFTS_BINARY <= "10110010"; + when 179 => TXTSNFTS_BINARY <= "10110011"; + when 180 => TXTSNFTS_BINARY <= "10110100"; + when 181 => TXTSNFTS_BINARY <= "10110101"; + when 182 => TXTSNFTS_BINARY <= "10110110"; + when 183 => TXTSNFTS_BINARY <= "10110111"; + when 184 => TXTSNFTS_BINARY <= "10111000"; + when 185 => TXTSNFTS_BINARY <= "10111001"; + when 186 => TXTSNFTS_BINARY <= "10111010"; + when 187 => TXTSNFTS_BINARY <= "10111011"; + when 188 => TXTSNFTS_BINARY <= "10111100"; + when 189 => TXTSNFTS_BINARY <= "10111101"; + when 190 => TXTSNFTS_BINARY <= "10111110"; + when 191 => TXTSNFTS_BINARY <= "10111111"; + when 192 => TXTSNFTS_BINARY <= "11000000"; + when 193 => TXTSNFTS_BINARY <= "11000001"; + when 194 => TXTSNFTS_BINARY <= "11000010"; + when 195 => TXTSNFTS_BINARY <= "11000011"; + when 196 => TXTSNFTS_BINARY <= "11000100"; + when 197 => TXTSNFTS_BINARY <= "11000101"; + when 198 => TXTSNFTS_BINARY <= "11000110"; + when 199 => TXTSNFTS_BINARY <= "11000111"; + when 200 => TXTSNFTS_BINARY <= "11001000"; + when 201 => TXTSNFTS_BINARY <= "11001001"; + when 202 => TXTSNFTS_BINARY <= "11001010"; + when 203 => TXTSNFTS_BINARY <= "11001011"; + when 204 => TXTSNFTS_BINARY <= "11001100"; + when 205 => TXTSNFTS_BINARY <= "11001101"; + when 206 => TXTSNFTS_BINARY <= "11001110"; + when 207 => TXTSNFTS_BINARY <= "11001111"; + when 208 => TXTSNFTS_BINARY <= "11010000"; + when 209 => TXTSNFTS_BINARY <= "11010001"; + when 210 => TXTSNFTS_BINARY <= "11010010"; + when 211 => TXTSNFTS_BINARY <= "11010011"; + when 212 => TXTSNFTS_BINARY <= "11010100"; + when 213 => TXTSNFTS_BINARY <= "11010101"; + when 214 => TXTSNFTS_BINARY <= "11010110"; + when 215 => TXTSNFTS_BINARY <= "11010111"; + when 216 => TXTSNFTS_BINARY <= "11011000"; + when 217 => TXTSNFTS_BINARY <= "11011001"; + when 218 => TXTSNFTS_BINARY <= "11011010"; + when 219 => TXTSNFTS_BINARY <= "11011011"; + when 220 => TXTSNFTS_BINARY <= "11011100"; + when 221 => TXTSNFTS_BINARY <= "11011101"; + when 222 => TXTSNFTS_BINARY <= "11011110"; + when 223 => TXTSNFTS_BINARY <= "11011111"; + when 224 => TXTSNFTS_BINARY <= "11100000"; + when 225 => TXTSNFTS_BINARY <= "11100001"; + when 226 => TXTSNFTS_BINARY <= "11100010"; + when 227 => TXTSNFTS_BINARY <= "11100011"; + when 228 => TXTSNFTS_BINARY <= "11100100"; + when 229 => TXTSNFTS_BINARY <= "11100101"; + when 230 => TXTSNFTS_BINARY <= "11100110"; + when 231 => TXTSNFTS_BINARY <= "11100111"; + when 232 => TXTSNFTS_BINARY <= "11101000"; + when 233 => TXTSNFTS_BINARY <= "11101001"; + when 234 => TXTSNFTS_BINARY <= "11101010"; + when 235 => TXTSNFTS_BINARY <= "11101011"; + when 236 => TXTSNFTS_BINARY <= "11101100"; + when 237 => TXTSNFTS_BINARY <= "11101101"; + when 238 => TXTSNFTS_BINARY <= "11101110"; + when 239 => TXTSNFTS_BINARY <= "11101111"; + when 240 => TXTSNFTS_BINARY <= "11110000"; + when 241 => TXTSNFTS_BINARY <= "11110001"; + when 242 => TXTSNFTS_BINARY <= "11110010"; + when 243 => TXTSNFTS_BINARY <= "11110011"; + when 244 => TXTSNFTS_BINARY <= "11110100"; + when 245 => TXTSNFTS_BINARY <= "11110101"; + when 246 => TXTSNFTS_BINARY <= "11110110"; + when 247 => TXTSNFTS_BINARY <= "11110111"; + when 248 => TXTSNFTS_BINARY <= "11111000"; + when 249 => TXTSNFTS_BINARY <= "11111001"; + when 250 => TXTSNFTS_BINARY <= "11111010"; + when 251 => TXTSNFTS_BINARY <= "11111011"; + when 252 => TXTSNFTS_BINARY <= "11111100"; + when 253 => TXTSNFTS_BINARY <= "11111101"; + when 254 => TXTSNFTS_BINARY <= "11111110"; + when 255 => TXTSNFTS_BINARY <= "11111111"; + when others => assert FALSE report "Error : TXTSNFTS is not in range 0...255." severity error; + end case; + case TXTSNFTSCOMCLK is + when 0 => TXTSNFTSCOMCLK_BINARY <= "00000000"; + when 1 => TXTSNFTSCOMCLK_BINARY <= "00000001"; + when 2 => TXTSNFTSCOMCLK_BINARY <= "00000010"; + when 3 => TXTSNFTSCOMCLK_BINARY <= "00000011"; + when 4 => TXTSNFTSCOMCLK_BINARY <= "00000100"; + when 5 => TXTSNFTSCOMCLK_BINARY <= "00000101"; + when 6 => TXTSNFTSCOMCLK_BINARY <= "00000110"; + when 7 => TXTSNFTSCOMCLK_BINARY <= "00000111"; + when 8 => TXTSNFTSCOMCLK_BINARY <= "00001000"; + when 9 => TXTSNFTSCOMCLK_BINARY <= "00001001"; + when 10 => TXTSNFTSCOMCLK_BINARY <= "00001010"; + when 11 => TXTSNFTSCOMCLK_BINARY <= "00001011"; + when 12 => TXTSNFTSCOMCLK_BINARY <= "00001100"; + when 13 => TXTSNFTSCOMCLK_BINARY <= "00001101"; + when 14 => TXTSNFTSCOMCLK_BINARY <= "00001110"; + when 15 => TXTSNFTSCOMCLK_BINARY <= "00001111"; + when 16 => TXTSNFTSCOMCLK_BINARY <= "00010000"; + when 17 => TXTSNFTSCOMCLK_BINARY <= "00010001"; + when 18 => TXTSNFTSCOMCLK_BINARY <= "00010010"; + when 19 => TXTSNFTSCOMCLK_BINARY <= "00010011"; + when 20 => TXTSNFTSCOMCLK_BINARY <= "00010100"; + when 21 => TXTSNFTSCOMCLK_BINARY <= "00010101"; + when 22 => TXTSNFTSCOMCLK_BINARY <= "00010110"; + when 23 => TXTSNFTSCOMCLK_BINARY <= "00010111"; + when 24 => TXTSNFTSCOMCLK_BINARY <= "00011000"; + when 25 => TXTSNFTSCOMCLK_BINARY <= "00011001"; + when 26 => TXTSNFTSCOMCLK_BINARY <= "00011010"; + when 27 => TXTSNFTSCOMCLK_BINARY <= "00011011"; + when 28 => TXTSNFTSCOMCLK_BINARY <= "00011100"; + when 29 => TXTSNFTSCOMCLK_BINARY <= "00011101"; + when 30 => TXTSNFTSCOMCLK_BINARY <= "00011110"; + when 31 => TXTSNFTSCOMCLK_BINARY <= "00011111"; + when 32 => TXTSNFTSCOMCLK_BINARY <= "00100000"; + when 33 => TXTSNFTSCOMCLK_BINARY <= "00100001"; + when 34 => TXTSNFTSCOMCLK_BINARY <= "00100010"; + when 35 => TXTSNFTSCOMCLK_BINARY <= "00100011"; + when 36 => TXTSNFTSCOMCLK_BINARY <= "00100100"; + when 37 => TXTSNFTSCOMCLK_BINARY <= "00100101"; + when 38 => TXTSNFTSCOMCLK_BINARY <= "00100110"; + when 39 => TXTSNFTSCOMCLK_BINARY <= "00100111"; + when 40 => TXTSNFTSCOMCLK_BINARY <= "00101000"; + when 41 => TXTSNFTSCOMCLK_BINARY <= "00101001"; + when 42 => TXTSNFTSCOMCLK_BINARY <= "00101010"; + when 43 => TXTSNFTSCOMCLK_BINARY <= "00101011"; + when 44 => TXTSNFTSCOMCLK_BINARY <= "00101100"; + when 45 => TXTSNFTSCOMCLK_BINARY <= "00101101"; + when 46 => TXTSNFTSCOMCLK_BINARY <= "00101110"; + when 47 => TXTSNFTSCOMCLK_BINARY <= "00101111"; + when 48 => TXTSNFTSCOMCLK_BINARY <= "00110000"; + when 49 => TXTSNFTSCOMCLK_BINARY <= "00110001"; + when 50 => TXTSNFTSCOMCLK_BINARY <= "00110010"; + when 51 => TXTSNFTSCOMCLK_BINARY <= "00110011"; + when 52 => TXTSNFTSCOMCLK_BINARY <= "00110100"; + when 53 => TXTSNFTSCOMCLK_BINARY <= "00110101"; + when 54 => TXTSNFTSCOMCLK_BINARY <= "00110110"; + when 55 => TXTSNFTSCOMCLK_BINARY <= "00110111"; + when 56 => TXTSNFTSCOMCLK_BINARY <= "00111000"; + when 57 => TXTSNFTSCOMCLK_BINARY <= "00111001"; + when 58 => TXTSNFTSCOMCLK_BINARY <= "00111010"; + when 59 => TXTSNFTSCOMCLK_BINARY <= "00111011"; + when 60 => TXTSNFTSCOMCLK_BINARY <= "00111100"; + when 61 => TXTSNFTSCOMCLK_BINARY <= "00111101"; + when 62 => TXTSNFTSCOMCLK_BINARY <= "00111110"; + when 63 => TXTSNFTSCOMCLK_BINARY <= "00111111"; + when 64 => TXTSNFTSCOMCLK_BINARY <= "01000000"; + when 65 => TXTSNFTSCOMCLK_BINARY <= "01000001"; + when 66 => TXTSNFTSCOMCLK_BINARY <= "01000010"; + when 67 => TXTSNFTSCOMCLK_BINARY <= "01000011"; + when 68 => TXTSNFTSCOMCLK_BINARY <= "01000100"; + when 69 => TXTSNFTSCOMCLK_BINARY <= "01000101"; + when 70 => TXTSNFTSCOMCLK_BINARY <= "01000110"; + when 71 => TXTSNFTSCOMCLK_BINARY <= "01000111"; + when 72 => TXTSNFTSCOMCLK_BINARY <= "01001000"; + when 73 => TXTSNFTSCOMCLK_BINARY <= "01001001"; + when 74 => TXTSNFTSCOMCLK_BINARY <= "01001010"; + when 75 => TXTSNFTSCOMCLK_BINARY <= "01001011"; + when 76 => TXTSNFTSCOMCLK_BINARY <= "01001100"; + when 77 => TXTSNFTSCOMCLK_BINARY <= "01001101"; + when 78 => TXTSNFTSCOMCLK_BINARY <= "01001110"; + when 79 => TXTSNFTSCOMCLK_BINARY <= "01001111"; + when 80 => TXTSNFTSCOMCLK_BINARY <= "01010000"; + when 81 => TXTSNFTSCOMCLK_BINARY <= "01010001"; + when 82 => TXTSNFTSCOMCLK_BINARY <= "01010010"; + when 83 => TXTSNFTSCOMCLK_BINARY <= "01010011"; + when 84 => TXTSNFTSCOMCLK_BINARY <= "01010100"; + when 85 => TXTSNFTSCOMCLK_BINARY <= "01010101"; + when 86 => TXTSNFTSCOMCLK_BINARY <= "01010110"; + when 87 => TXTSNFTSCOMCLK_BINARY <= "01010111"; + when 88 => TXTSNFTSCOMCLK_BINARY <= "01011000"; + when 89 => TXTSNFTSCOMCLK_BINARY <= "01011001"; + when 90 => TXTSNFTSCOMCLK_BINARY <= "01011010"; + when 91 => TXTSNFTSCOMCLK_BINARY <= "01011011"; + when 92 => TXTSNFTSCOMCLK_BINARY <= "01011100"; + when 93 => TXTSNFTSCOMCLK_BINARY <= "01011101"; + when 94 => TXTSNFTSCOMCLK_BINARY <= "01011110"; + when 95 => TXTSNFTSCOMCLK_BINARY <= "01011111"; + when 96 => TXTSNFTSCOMCLK_BINARY <= "01100000"; + when 97 => TXTSNFTSCOMCLK_BINARY <= "01100001"; + when 98 => TXTSNFTSCOMCLK_BINARY <= "01100010"; + when 99 => TXTSNFTSCOMCLK_BINARY <= "01100011"; + when 100 => TXTSNFTSCOMCLK_BINARY <= "01100100"; + when 101 => TXTSNFTSCOMCLK_BINARY <= "01100101"; + when 102 => TXTSNFTSCOMCLK_BINARY <= "01100110"; + when 103 => TXTSNFTSCOMCLK_BINARY <= "01100111"; + when 104 => TXTSNFTSCOMCLK_BINARY <= "01101000"; + when 105 => TXTSNFTSCOMCLK_BINARY <= "01101001"; + when 106 => TXTSNFTSCOMCLK_BINARY <= "01101010"; + when 107 => TXTSNFTSCOMCLK_BINARY <= "01101011"; + when 108 => TXTSNFTSCOMCLK_BINARY <= "01101100"; + when 109 => TXTSNFTSCOMCLK_BINARY <= "01101101"; + when 110 => TXTSNFTSCOMCLK_BINARY <= "01101110"; + when 111 => TXTSNFTSCOMCLK_BINARY <= "01101111"; + when 112 => TXTSNFTSCOMCLK_BINARY <= "01110000"; + when 113 => TXTSNFTSCOMCLK_BINARY <= "01110001"; + when 114 => TXTSNFTSCOMCLK_BINARY <= "01110010"; + when 115 => TXTSNFTSCOMCLK_BINARY <= "01110011"; + when 116 => TXTSNFTSCOMCLK_BINARY <= "01110100"; + when 117 => TXTSNFTSCOMCLK_BINARY <= "01110101"; + when 118 => TXTSNFTSCOMCLK_BINARY <= "01110110"; + when 119 => TXTSNFTSCOMCLK_BINARY <= "01110111"; + when 120 => TXTSNFTSCOMCLK_BINARY <= "01111000"; + when 121 => TXTSNFTSCOMCLK_BINARY <= "01111001"; + when 122 => TXTSNFTSCOMCLK_BINARY <= "01111010"; + when 123 => TXTSNFTSCOMCLK_BINARY <= "01111011"; + when 124 => TXTSNFTSCOMCLK_BINARY <= "01111100"; + when 125 => TXTSNFTSCOMCLK_BINARY <= "01111101"; + when 126 => TXTSNFTSCOMCLK_BINARY <= "01111110"; + when 127 => TXTSNFTSCOMCLK_BINARY <= "01111111"; + when 128 => TXTSNFTSCOMCLK_BINARY <= "10000000"; + when 129 => TXTSNFTSCOMCLK_BINARY <= "10000001"; + when 130 => TXTSNFTSCOMCLK_BINARY <= "10000010"; + when 131 => TXTSNFTSCOMCLK_BINARY <= "10000011"; + when 132 => TXTSNFTSCOMCLK_BINARY <= "10000100"; + when 133 => TXTSNFTSCOMCLK_BINARY <= "10000101"; + when 134 => TXTSNFTSCOMCLK_BINARY <= "10000110"; + when 135 => TXTSNFTSCOMCLK_BINARY <= "10000111"; + when 136 => TXTSNFTSCOMCLK_BINARY <= "10001000"; + when 137 => TXTSNFTSCOMCLK_BINARY <= "10001001"; + when 138 => TXTSNFTSCOMCLK_BINARY <= "10001010"; + when 139 => TXTSNFTSCOMCLK_BINARY <= "10001011"; + when 140 => TXTSNFTSCOMCLK_BINARY <= "10001100"; + when 141 => TXTSNFTSCOMCLK_BINARY <= "10001101"; + when 142 => TXTSNFTSCOMCLK_BINARY <= "10001110"; + when 143 => TXTSNFTSCOMCLK_BINARY <= "10001111"; + when 144 => TXTSNFTSCOMCLK_BINARY <= "10010000"; + when 145 => TXTSNFTSCOMCLK_BINARY <= "10010001"; + when 146 => TXTSNFTSCOMCLK_BINARY <= "10010010"; + when 147 => TXTSNFTSCOMCLK_BINARY <= "10010011"; + when 148 => TXTSNFTSCOMCLK_BINARY <= "10010100"; + when 149 => TXTSNFTSCOMCLK_BINARY <= "10010101"; + when 150 => TXTSNFTSCOMCLK_BINARY <= "10010110"; + when 151 => TXTSNFTSCOMCLK_BINARY <= "10010111"; + when 152 => TXTSNFTSCOMCLK_BINARY <= "10011000"; + when 153 => TXTSNFTSCOMCLK_BINARY <= "10011001"; + when 154 => TXTSNFTSCOMCLK_BINARY <= "10011010"; + when 155 => TXTSNFTSCOMCLK_BINARY <= "10011011"; + when 156 => TXTSNFTSCOMCLK_BINARY <= "10011100"; + when 157 => TXTSNFTSCOMCLK_BINARY <= "10011101"; + when 158 => TXTSNFTSCOMCLK_BINARY <= "10011110"; + when 159 => TXTSNFTSCOMCLK_BINARY <= "10011111"; + when 160 => TXTSNFTSCOMCLK_BINARY <= "10100000"; + when 161 => TXTSNFTSCOMCLK_BINARY <= "10100001"; + when 162 => TXTSNFTSCOMCLK_BINARY <= "10100010"; + when 163 => TXTSNFTSCOMCLK_BINARY <= "10100011"; + when 164 => TXTSNFTSCOMCLK_BINARY <= "10100100"; + when 165 => TXTSNFTSCOMCLK_BINARY <= "10100101"; + when 166 => TXTSNFTSCOMCLK_BINARY <= "10100110"; + when 167 => TXTSNFTSCOMCLK_BINARY <= "10100111"; + when 168 => TXTSNFTSCOMCLK_BINARY <= "10101000"; + when 169 => TXTSNFTSCOMCLK_BINARY <= "10101001"; + when 170 => TXTSNFTSCOMCLK_BINARY <= "10101010"; + when 171 => TXTSNFTSCOMCLK_BINARY <= "10101011"; + when 172 => TXTSNFTSCOMCLK_BINARY <= "10101100"; + when 173 => TXTSNFTSCOMCLK_BINARY <= "10101101"; + when 174 => TXTSNFTSCOMCLK_BINARY <= "10101110"; + when 175 => TXTSNFTSCOMCLK_BINARY <= "10101111"; + when 176 => TXTSNFTSCOMCLK_BINARY <= "10110000"; + when 177 => TXTSNFTSCOMCLK_BINARY <= "10110001"; + when 178 => TXTSNFTSCOMCLK_BINARY <= "10110010"; + when 179 => TXTSNFTSCOMCLK_BINARY <= "10110011"; + when 180 => TXTSNFTSCOMCLK_BINARY <= "10110100"; + when 181 => TXTSNFTSCOMCLK_BINARY <= "10110101"; + when 182 => TXTSNFTSCOMCLK_BINARY <= "10110110"; + when 183 => TXTSNFTSCOMCLK_BINARY <= "10110111"; + when 184 => TXTSNFTSCOMCLK_BINARY <= "10111000"; + when 185 => TXTSNFTSCOMCLK_BINARY <= "10111001"; + when 186 => TXTSNFTSCOMCLK_BINARY <= "10111010"; + when 187 => TXTSNFTSCOMCLK_BINARY <= "10111011"; + when 188 => TXTSNFTSCOMCLK_BINARY <= "10111100"; + when 189 => TXTSNFTSCOMCLK_BINARY <= "10111101"; + when 190 => TXTSNFTSCOMCLK_BINARY <= "10111110"; + when 191 => TXTSNFTSCOMCLK_BINARY <= "10111111"; + when 192 => TXTSNFTSCOMCLK_BINARY <= "11000000"; + when 193 => TXTSNFTSCOMCLK_BINARY <= "11000001"; + when 194 => TXTSNFTSCOMCLK_BINARY <= "11000010"; + when 195 => TXTSNFTSCOMCLK_BINARY <= "11000011"; + when 196 => TXTSNFTSCOMCLK_BINARY <= "11000100"; + when 197 => TXTSNFTSCOMCLK_BINARY <= "11000101"; + when 198 => TXTSNFTSCOMCLK_BINARY <= "11000110"; + when 199 => TXTSNFTSCOMCLK_BINARY <= "11000111"; + when 200 => TXTSNFTSCOMCLK_BINARY <= "11001000"; + when 201 => TXTSNFTSCOMCLK_BINARY <= "11001001"; + when 202 => TXTSNFTSCOMCLK_BINARY <= "11001010"; + when 203 => TXTSNFTSCOMCLK_BINARY <= "11001011"; + when 204 => TXTSNFTSCOMCLK_BINARY <= "11001100"; + when 205 => TXTSNFTSCOMCLK_BINARY <= "11001101"; + when 206 => TXTSNFTSCOMCLK_BINARY <= "11001110"; + when 207 => TXTSNFTSCOMCLK_BINARY <= "11001111"; + when 208 => TXTSNFTSCOMCLK_BINARY <= "11010000"; + when 209 => TXTSNFTSCOMCLK_BINARY <= "11010001"; + when 210 => TXTSNFTSCOMCLK_BINARY <= "11010010"; + when 211 => TXTSNFTSCOMCLK_BINARY <= "11010011"; + when 212 => TXTSNFTSCOMCLK_BINARY <= "11010100"; + when 213 => TXTSNFTSCOMCLK_BINARY <= "11010101"; + when 214 => TXTSNFTSCOMCLK_BINARY <= "11010110"; + when 215 => TXTSNFTSCOMCLK_BINARY <= "11010111"; + when 216 => TXTSNFTSCOMCLK_BINARY <= "11011000"; + when 217 => TXTSNFTSCOMCLK_BINARY <= "11011001"; + when 218 => TXTSNFTSCOMCLK_BINARY <= "11011010"; + when 219 => TXTSNFTSCOMCLK_BINARY <= "11011011"; + when 220 => TXTSNFTSCOMCLK_BINARY <= "11011100"; + when 221 => TXTSNFTSCOMCLK_BINARY <= "11011101"; + when 222 => TXTSNFTSCOMCLK_BINARY <= "11011110"; + when 223 => TXTSNFTSCOMCLK_BINARY <= "11011111"; + when 224 => TXTSNFTSCOMCLK_BINARY <= "11100000"; + when 225 => TXTSNFTSCOMCLK_BINARY <= "11100001"; + when 226 => TXTSNFTSCOMCLK_BINARY <= "11100010"; + when 227 => TXTSNFTSCOMCLK_BINARY <= "11100011"; + when 228 => TXTSNFTSCOMCLK_BINARY <= "11100100"; + when 229 => TXTSNFTSCOMCLK_BINARY <= "11100101"; + when 230 => TXTSNFTSCOMCLK_BINARY <= "11100110"; + when 231 => TXTSNFTSCOMCLK_BINARY <= "11100111"; + when 232 => TXTSNFTSCOMCLK_BINARY <= "11101000"; + when 233 => TXTSNFTSCOMCLK_BINARY <= "11101001"; + when 234 => TXTSNFTSCOMCLK_BINARY <= "11101010"; + when 235 => TXTSNFTSCOMCLK_BINARY <= "11101011"; + when 236 => TXTSNFTSCOMCLK_BINARY <= "11101100"; + when 237 => TXTSNFTSCOMCLK_BINARY <= "11101101"; + when 238 => TXTSNFTSCOMCLK_BINARY <= "11101110"; + when 239 => TXTSNFTSCOMCLK_BINARY <= "11101111"; + when 240 => TXTSNFTSCOMCLK_BINARY <= "11110000"; + when 241 => TXTSNFTSCOMCLK_BINARY <= "11110001"; + when 242 => TXTSNFTSCOMCLK_BINARY <= "11110010"; + when 243 => TXTSNFTSCOMCLK_BINARY <= "11110011"; + when 244 => TXTSNFTSCOMCLK_BINARY <= "11110100"; + when 245 => TXTSNFTSCOMCLK_BINARY <= "11110101"; + when 246 => TXTSNFTSCOMCLK_BINARY <= "11110110"; + when 247 => TXTSNFTSCOMCLK_BINARY <= "11110111"; + when 248 => TXTSNFTSCOMCLK_BINARY <= "11111000"; + when 249 => TXTSNFTSCOMCLK_BINARY <= "11111001"; + when 250 => TXTSNFTSCOMCLK_BINARY <= "11111010"; + when 251 => TXTSNFTSCOMCLK_BINARY <= "11111011"; + when 252 => TXTSNFTSCOMCLK_BINARY <= "11111100"; + when 253 => TXTSNFTSCOMCLK_BINARY <= "11111101"; + when 254 => TXTSNFTSCOMCLK_BINARY <= "11111110"; + when 255 => TXTSNFTSCOMCLK_BINARY <= "11111111"; + when others => assert FALSE report "Error : TXTSNFTSCOMCLK is not in range 0...255." severity error; + end case; + case RETRYRAMREADLATENCY is + when 0 => RETRYRAMREADLATENCY_BINARY <= "000"; + when 1 => RETRYRAMREADLATENCY_BINARY <= "001"; + when 2 => RETRYRAMREADLATENCY_BINARY <= "010"; + when 3 => RETRYRAMREADLATENCY_BINARY <= "011"; + when 4 => RETRYRAMREADLATENCY_BINARY <= "100"; + when 5 => RETRYRAMREADLATENCY_BINARY <= "101"; + when 6 => RETRYRAMREADLATENCY_BINARY <= "110"; + when 7 => RETRYRAMREADLATENCY_BINARY <= "111"; + when others => assert FALSE report "Error : RETRYRAMREADLATENCY is not in range 0...7." severity error; + end case; + case RETRYRAMWRITELATENCY is + when 0 => RETRYRAMWRITELATENCY_BINARY <= "000"; + when 1 => RETRYRAMWRITELATENCY_BINARY <= "001"; + when 2 => RETRYRAMWRITELATENCY_BINARY <= "010"; + when 3 => RETRYRAMWRITELATENCY_BINARY <= "011"; + when 4 => RETRYRAMWRITELATENCY_BINARY <= "100"; + when 5 => RETRYRAMWRITELATENCY_BINARY <= "101"; + when 6 => RETRYRAMWRITELATENCY_BINARY <= "110"; + when 7 => RETRYRAMWRITELATENCY_BINARY <= "111"; + when others => assert FALSE report "Error : RETRYRAMWRITELATENCY is not in range 0...7." severity error; + end case; + case RETRYRAMWIDTH is + when 0 => RETRYRAMWIDTH_BINARY <= '0'; + when 1 => RETRYRAMWIDTH_BINARY <= '1'; + when others => assert FALSE report "Error : RETRYRAMWIDTH is not in range 0...1." severity error; + end case; + case RETRYWRITEPIPE is + when FALSE => RETRYWRITEPIPE_BINARY <= '0'; + when TRUE => RETRYWRITEPIPE_BINARY <= '1'; + when others => assert FALSE report "Error : RETRYWRITEPIPE is neither TRUE nor FALSE." severity error; + end case; + case RETRYREADADDRPIPE is + when FALSE => RETRYREADADDRPIPE_BINARY <= '0'; + when TRUE => RETRYREADADDRPIPE_BINARY <= '1'; + when others => assert FALSE report "Error : RETRYREADADDRPIPE is neither TRUE nor FALSE." severity error; + end case; + case RETRYREADDATAPIPE is + when FALSE => RETRYREADDATAPIPE_BINARY <= '0'; + when TRUE => RETRYREADDATAPIPE_BINARY <= '1'; + when others => assert FALSE report "Error : RETRYREADDATAPIPE is neither TRUE nor FALSE." severity error; + end case; + case XLINKSUPPORTED is + when FALSE => XLINKSUPPORTED_BINARY <= '0'; + when TRUE => XLINKSUPPORTED_BINARY <= '1'; + when others => assert FALSE report "Error : XLINKSUPPORTED is neither TRUE nor FALSE." severity error; + end case; + case INFINITECOMPLETIONS is + when FALSE => INFINITECOMPLETIONS_BINARY <= '0'; + when TRUE => INFINITECOMPLETIONS_BINARY <= '1'; + when others => assert FALSE report "Error : INFINITECOMPLETIONS is neither TRUE nor FALSE." severity error; + end case; + case TLRAMREADLATENCY is + when 0 => TLRAMREADLATENCY_BINARY <= "000"; + when 1 => TLRAMREADLATENCY_BINARY <= "001"; + when 2 => TLRAMREADLATENCY_BINARY <= "010"; + when 3 => TLRAMREADLATENCY_BINARY <= "011"; + when 4 => TLRAMREADLATENCY_BINARY <= "100"; + when 5 => TLRAMREADLATENCY_BINARY <= "101"; + when 6 => TLRAMREADLATENCY_BINARY <= "110"; + when 7 => TLRAMREADLATENCY_BINARY <= "111"; + when others => assert FALSE report "Error : TLRAMREADLATENCY is not in range 0...7." severity error; + end case; + case TLRAMWRITELATENCY is + when 0 => TLRAMWRITELATENCY_BINARY <= "000"; + when 1 => TLRAMWRITELATENCY_BINARY <= "001"; + when 2 => TLRAMWRITELATENCY_BINARY <= "010"; + when 3 => TLRAMWRITELATENCY_BINARY <= "011"; + when 4 => TLRAMWRITELATENCY_BINARY <= "100"; + when 5 => TLRAMWRITELATENCY_BINARY <= "101"; + when 6 => TLRAMWRITELATENCY_BINARY <= "110"; + when 7 => TLRAMWRITELATENCY_BINARY <= "111"; + when others => assert FALSE report "Error : TLRAMWRITELATENCY is not in range 0...7." severity error; + end case; + case TLRAMWIDTH is + when 0 => TLRAMWIDTH_BINARY <= '0'; + when 1 => TLRAMWIDTH_BINARY <= '1'; + when others => assert FALSE report "Error : TLRAMWIDTH is not in range 0...1." severity error; + end case; + case RAMSHARETXRX is + when FALSE => RAMSHARETXRX_BINARY <= '0'; + when TRUE => RAMSHARETXRX_BINARY <= '1'; + when others => assert FALSE report "Error : RAMSHARETXRX is neither TRUE nor FALSE." severity error; + end case; + case L0SEXITLATENCY is + when 0 => L0SEXITLATENCY_BINARY <= "000"; + when 1 => L0SEXITLATENCY_BINARY <= "001"; + when 2 => L0SEXITLATENCY_BINARY <= "010"; + when 3 => L0SEXITLATENCY_BINARY <= "011"; + when 4 => L0SEXITLATENCY_BINARY <= "100"; + when 5 => L0SEXITLATENCY_BINARY <= "101"; + when 6 => L0SEXITLATENCY_BINARY <= "110"; + when 7 => L0SEXITLATENCY_BINARY <= "111"; + when others => assert FALSE report "Error : L0SEXITLATENCY is not in range 0...7." severity error; + end case; + case L0SEXITLATENCYCOMCLK is + when 0 => L0SEXITLATENCYCOMCLK_BINARY <= "000"; + when 1 => L0SEXITLATENCYCOMCLK_BINARY <= "001"; + when 2 => L0SEXITLATENCYCOMCLK_BINARY <= "010"; + when 3 => L0SEXITLATENCYCOMCLK_BINARY <= "011"; + when 4 => L0SEXITLATENCYCOMCLK_BINARY <= "100"; + when 5 => L0SEXITLATENCYCOMCLK_BINARY <= "101"; + when 6 => L0SEXITLATENCYCOMCLK_BINARY <= "110"; + when 7 => L0SEXITLATENCYCOMCLK_BINARY <= "111"; + when others => assert FALSE report "Error : L0SEXITLATENCYCOMCLK is not in range 0...7." severity error; + end case; + case L1EXITLATENCY is + when 0 => L1EXITLATENCY_BINARY <= "000"; + when 1 => L1EXITLATENCY_BINARY <= "001"; + when 2 => L1EXITLATENCY_BINARY <= "010"; + when 3 => L1EXITLATENCY_BINARY <= "011"; + when 4 => L1EXITLATENCY_BINARY <= "100"; + when 5 => L1EXITLATENCY_BINARY <= "101"; + when 6 => L1EXITLATENCY_BINARY <= "110"; + when 7 => L1EXITLATENCY_BINARY <= "111"; + when others => assert FALSE report "Error : L1EXITLATENCY is not in range 0...7." severity error; + end case; + case L1EXITLATENCYCOMCLK is + when 0 => L1EXITLATENCYCOMCLK_BINARY <= "000"; + when 1 => L1EXITLATENCYCOMCLK_BINARY <= "001"; + when 2 => L1EXITLATENCYCOMCLK_BINARY <= "010"; + when 3 => L1EXITLATENCYCOMCLK_BINARY <= "011"; + when 4 => L1EXITLATENCYCOMCLK_BINARY <= "100"; + when 5 => L1EXITLATENCYCOMCLK_BINARY <= "101"; + when 6 => L1EXITLATENCYCOMCLK_BINARY <= "110"; + when 7 => L1EXITLATENCYCOMCLK_BINARY <= "111"; + when others => assert FALSE report "Error : L1EXITLATENCYCOMCLK is not in range 0...7." severity error; + end case; + case DUALCORESLAVE is + when FALSE => DUALCORESLAVE_BINARY <= '0'; + when TRUE => DUALCORESLAVE_BINARY <= '1'; + when others => assert FALSE report "Error : DUALCORESLAVE is neither TRUE nor FALSE." severity error; + end case; + case DUALCOREENABLE is + when FALSE => DUALCOREENABLE_BINARY <= '0'; + when TRUE => DUALCOREENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : DUALCOREENABLE is neither TRUE nor FALSE." severity error; + end case; + case DUALROLECFGCNTRLROOTEPN is + when 0 => DUALROLECFGCNTRLROOTEPN_BINARY <= '0'; + when 1 => DUALROLECFGCNTRLROOTEPN_BINARY <= '1'; + when others => assert FALSE report "Error : DUALROLECFGCNTRLROOTEPN is not in range 0...1." severity error; + end case; + case RXREADADDRPIPE is + when FALSE => RXREADADDRPIPE_BINARY <= '0'; + when TRUE => RXREADADDRPIPE_BINARY <= '1'; + when others => assert FALSE report "Error : RXREADADDRPIPE is neither TRUE nor FALSE." severity error; + end case; + case RXREADDATAPIPE is + when FALSE => RXREADDATAPIPE_BINARY <= '0'; + when TRUE => RXREADDATAPIPE_BINARY <= '1'; + when others => assert FALSE report "Error : RXREADDATAPIPE is neither TRUE nor FALSE." severity error; + end case; + case TXWRITEPIPE is + when FALSE => TXWRITEPIPE_BINARY <= '0'; + when TRUE => TXWRITEPIPE_BINARY <= '1'; + when others => assert FALSE report "Error : TXWRITEPIPE is neither TRUE nor FALSE." severity error; + end case; + case TXREADADDRPIPE is + when FALSE => TXREADADDRPIPE_BINARY <= '0'; + when TRUE => TXREADADDRPIPE_BINARY <= '1'; + when others => assert FALSE report "Error : TXREADADDRPIPE is neither TRUE nor FALSE." severity error; + end case; + case TXREADDATAPIPE is + when FALSE => TXREADDATAPIPE_BINARY <= '0'; + when TRUE => TXREADDATAPIPE_BINARY <= '1'; + when others => assert FALSE report "Error : TXREADDATAPIPE is neither TRUE nor FALSE." severity error; + end case; + case RXWRITEPIPE is + when FALSE => RXWRITEPIPE_BINARY <= '0'; + when TRUE => RXWRITEPIPE_BINARY <= '1'; + when others => assert FALSE report "Error : RXWRITEPIPE is neither TRUE nor FALSE." severity error; + end case; + case LLKBYPASS is + when FALSE => LLKBYPASS_BINARY <= '0'; + when TRUE => LLKBYPASS_BINARY <= '1'; + when others => assert FALSE report "Error : LLKBYPASS is neither TRUE nor FALSE." severity error; + end case; + case PCIEREVISION is + when 0 => PCIEREVISION_BINARY <= '0'; + when 1 => PCIEREVISION_BINARY <= '1'; + when others => assert FALSE report "Error : PCIEREVISION is not in range 0...1." severity error; + end case; + case SELECTDLLIF is + when FALSE => SELECTDLLIF_BINARY <= '0'; + when TRUE => SELECTDLLIF_BINARY <= '1'; + when others => assert FALSE report "Error : SELECTDLLIF is neither TRUE nor FALSE." severity error; + end case; + case SELECTASMODE is + when FALSE => SELECTASMODE_BINARY <= '0'; + when TRUE => SELECTASMODE_BINARY <= '1'; + when others => assert FALSE report "Error : SELECTASMODE is neither TRUE nor FALSE." severity error; + end case; + case ISSWITCH is + when FALSE => ISSWITCH_BINARY <= '0'; + when TRUE => ISSWITCH_BINARY <= '1'; + when others => assert FALSE report "Error : ISSWITCH is neither TRUE nor FALSE." severity error; + end case; + case UPSTREAMFACING is + when FALSE => UPSTREAMFACING_BINARY <= '0'; + when TRUE => UPSTREAMFACING_BINARY <= '1'; + when others => assert FALSE report "Error : UPSTREAMFACING is neither TRUE nor FALSE." severity error; + end case; + case SLOTIMPLEMENTED is + when FALSE => SLOTIMPLEMENTED_BINARY <= '0'; + when TRUE => SLOTIMPLEMENTED_BINARY <= '1'; + when others => assert FALSE report "Error : SLOTIMPLEMENTED is neither TRUE nor FALSE." severity error; + end case; + case BAR0EXIST is + when FALSE => BAR0EXIST_BINARY <= '0'; + when TRUE => BAR0EXIST_BINARY <= '1'; + when others => assert FALSE report "Error : BAR0EXIST is neither TRUE nor FALSE." severity error; + end case; + case BAR1EXIST is + when FALSE => BAR1EXIST_BINARY <= '0'; + when TRUE => BAR1EXIST_BINARY <= '1'; + when others => assert FALSE report "Error : BAR1EXIST is neither TRUE nor FALSE." severity error; + end case; + case BAR2EXIST is + when FALSE => BAR2EXIST_BINARY <= '0'; + when TRUE => BAR2EXIST_BINARY <= '1'; + when others => assert FALSE report "Error : BAR2EXIST is neither TRUE nor FALSE." severity error; + end case; + case BAR3EXIST is + when FALSE => BAR3EXIST_BINARY <= '0'; + when TRUE => BAR3EXIST_BINARY <= '1'; + when others => assert FALSE report "Error : BAR3EXIST is neither TRUE nor FALSE." severity error; + end case; + case BAR4EXIST is + when FALSE => BAR4EXIST_BINARY <= '0'; + when TRUE => BAR4EXIST_BINARY <= '1'; + when others => assert FALSE report "Error : BAR4EXIST is neither TRUE nor FALSE." severity error; + end case; + case BAR5EXIST is + when FALSE => BAR5EXIST_BINARY <= '0'; + when TRUE => BAR5EXIST_BINARY <= '1'; + when others => assert FALSE report "Error : BAR5EXIST is neither TRUE nor FALSE." severity error; + end case; + case BAR0ADDRWIDTH is + when 0 => BAR0ADDRWIDTH_BINARY <= '0'; + when 1 => BAR0ADDRWIDTH_BINARY <= '1'; + when others => assert FALSE report "Error : BAR0ADDRWIDTH is not in range 0...1." severity error; + end case; + case BAR1ADDRWIDTH is + when 0 => BAR1ADDRWIDTH_BINARY <= '0'; + when 1 => BAR1ADDRWIDTH_BINARY <= '1'; + when others => assert FALSE report "Error : BAR1ADDRWIDTH is not in range 0...1." severity error; + end case; + case BAR2ADDRWIDTH is + when 0 => BAR2ADDRWIDTH_BINARY <= '0'; + when 1 => BAR2ADDRWIDTH_BINARY <= '1'; + when others => assert FALSE report "Error : BAR2ADDRWIDTH is not in range 0...1." severity error; + end case; + case BAR3ADDRWIDTH is + when 0 => BAR3ADDRWIDTH_BINARY <= '0'; + when 1 => BAR3ADDRWIDTH_BINARY <= '1'; + when others => assert FALSE report "Error : BAR3ADDRWIDTH is not in range 0...1." severity error; + end case; + case BAR4ADDRWIDTH is + when 0 => BAR4ADDRWIDTH_BINARY <= '0'; + when 1 => BAR4ADDRWIDTH_BINARY <= '1'; + when others => assert FALSE report "Error : BAR4ADDRWIDTH is not in range 0...1." severity error; + end case; + case BAR0PREFETCHABLE is + when FALSE => BAR0PREFETCHABLE_BINARY <= '0'; + when TRUE => BAR0PREFETCHABLE_BINARY <= '1'; + when others => assert FALSE report "Error : BAR0PREFETCHABLE is neither TRUE nor FALSE." severity error; + end case; + case BAR1PREFETCHABLE is + when FALSE => BAR1PREFETCHABLE_BINARY <= '0'; + when TRUE => BAR1PREFETCHABLE_BINARY <= '1'; + when others => assert FALSE report "Error : BAR1PREFETCHABLE is neither TRUE nor FALSE." severity error; + end case; + case BAR2PREFETCHABLE is + when FALSE => BAR2PREFETCHABLE_BINARY <= '0'; + when TRUE => BAR2PREFETCHABLE_BINARY <= '1'; + when others => assert FALSE report "Error : BAR2PREFETCHABLE is neither TRUE nor FALSE." severity error; + end case; + case BAR3PREFETCHABLE is + when FALSE => BAR3PREFETCHABLE_BINARY <= '0'; + when TRUE => BAR3PREFETCHABLE_BINARY <= '1'; + when others => assert FALSE report "Error : BAR3PREFETCHABLE is neither TRUE nor FALSE." severity error; + end case; + case BAR4PREFETCHABLE is + when FALSE => BAR4PREFETCHABLE_BINARY <= '0'; + when TRUE => BAR4PREFETCHABLE_BINARY <= '1'; + when others => assert FALSE report "Error : BAR4PREFETCHABLE is neither TRUE nor FALSE." severity error; + end case; + case BAR5PREFETCHABLE is + when FALSE => BAR5PREFETCHABLE_BINARY <= '0'; + when TRUE => BAR5PREFETCHABLE_BINARY <= '1'; + when others => assert FALSE report "Error : BAR5PREFETCHABLE is neither TRUE nor FALSE." severity error; + end case; + case BAR0IOMEMN is + when 0 => BAR0IOMEMN_BINARY <= '0'; + when 1 => BAR0IOMEMN_BINARY <= '1'; + when others => assert FALSE report "Error : BAR0IOMEMN is not in range 0...1." severity error; + end case; + case BAR1IOMEMN is + when 0 => BAR1IOMEMN_BINARY <= '0'; + when 1 => BAR1IOMEMN_BINARY <= '1'; + when others => assert FALSE report "Error : BAR1IOMEMN is not in range 0...1." severity error; + end case; + case BAR2IOMEMN is + when 0 => BAR2IOMEMN_BINARY <= '0'; + when 1 => BAR2IOMEMN_BINARY <= '1'; + when others => assert FALSE report "Error : BAR2IOMEMN is not in range 0...1." severity error; + end case; + case BAR3IOMEMN is + when 0 => BAR3IOMEMN_BINARY <= '0'; + when 1 => BAR3IOMEMN_BINARY <= '1'; + when others => assert FALSE report "Error : BAR3IOMEMN is not in range 0...1." severity error; + end case; + case BAR4IOMEMN is + when 0 => BAR4IOMEMN_BINARY <= '0'; + when 1 => BAR4IOMEMN_BINARY <= '1'; + when others => assert FALSE report "Error : BAR4IOMEMN is not in range 0...1." severity error; + end case; + case BAR5IOMEMN is + when 0 => BAR5IOMEMN_BINARY <= '0'; + when 1 => BAR5IOMEMN_BINARY <= '1'; + when others => assert FALSE report "Error : BAR5IOMEMN is not in range 0...1." severity error; + end case; + case XPMAXPAYLOAD is + when 0 => XPMAXPAYLOAD_BINARY <= "000"; + when 1 => XPMAXPAYLOAD_BINARY <= "001"; + when 2 => XPMAXPAYLOAD_BINARY <= "010"; + when 3 => XPMAXPAYLOAD_BINARY <= "011"; + when 4 => XPMAXPAYLOAD_BINARY <= "100"; + when 5 => XPMAXPAYLOAD_BINARY <= "101"; + when 6 => XPMAXPAYLOAD_BINARY <= "110"; + when 7 => XPMAXPAYLOAD_BINARY <= "111"; + when others => assert FALSE report "Error : XPMAXPAYLOAD is not in range 0...7." severity error; + end case; + case XPRCBCONTROL is + when 0 => XPRCBCONTROL_BINARY <= '0'; + when 1 => XPRCBCONTROL_BINARY <= '1'; + when others => assert FALSE report "Error : XPRCBCONTROL is not in range 0...1." severity error; + end case; + case LOWPRIORITYVCCOUNT is + when 0 => LOWPRIORITYVCCOUNT_BINARY <= "000"; + when 1 => LOWPRIORITYVCCOUNT_BINARY <= "001"; + when 2 => LOWPRIORITYVCCOUNT_BINARY <= "010"; + when 3 => LOWPRIORITYVCCOUNT_BINARY <= "011"; + when 4 => LOWPRIORITYVCCOUNT_BINARY <= "100"; + when 5 => LOWPRIORITYVCCOUNT_BINARY <= "101"; + when 6 => LOWPRIORITYVCCOUNT_BINARY <= "110"; + when 7 => LOWPRIORITYVCCOUNT_BINARY <= "111"; + when others => assert FALSE report "Error : LOWPRIORITYVCCOUNT is not in range 0...7." severity error; + end case; + case PMCAPABILITYDSI is + when FALSE => PMCAPABILITYDSI_BINARY <= '0'; + when TRUE => PMCAPABILITYDSI_BINARY <= '1'; + when others => assert FALSE report "Error : PMCAPABILITYDSI is neither TRUE nor FALSE." severity error; + end case; + case PMCAPABILITYD1SUPPORT is + when FALSE => PMCAPABILITYD1SUPPORT_BINARY <= '0'; + when TRUE => PMCAPABILITYD1SUPPORT_BINARY <= '1'; + when others => assert FALSE report "Error : PMCAPABILITYD1SUPPORT is neither TRUE nor FALSE." severity error; + end case; + case PMCAPABILITYD2SUPPORT is + when FALSE => PMCAPABILITYD2SUPPORT_BINARY <= '0'; + when TRUE => PMCAPABILITYD2SUPPORT_BINARY <= '1'; + when others => assert FALSE report "Error : PMCAPABILITYD2SUPPORT is neither TRUE nor FALSE." severity error; + end case; + case PMDATASCALE0 is + when 0 => PMDATASCALE0_BINARY <= "00"; + when 1 => PMDATASCALE0_BINARY <= "01"; + when 2 => PMDATASCALE0_BINARY <= "10"; + when 3 => PMDATASCALE0_BINARY <= "11"; + when others => assert FALSE report "Error : PMDATASCALE0 is not in range 0...3." severity error; + end case; + case PMDATASCALE1 is + when 0 => PMDATASCALE1_BINARY <= "00"; + when 1 => PMDATASCALE1_BINARY <= "01"; + when 2 => PMDATASCALE1_BINARY <= "10"; + when 3 => PMDATASCALE1_BINARY <= "11"; + when others => assert FALSE report "Error : PMDATASCALE1 is not in range 0...3." severity error; + end case; + case PMDATASCALE2 is + when 0 => PMDATASCALE2_BINARY <= "00"; + when 1 => PMDATASCALE2_BINARY <= "01"; + when 2 => PMDATASCALE2_BINARY <= "10"; + when 3 => PMDATASCALE2_BINARY <= "11"; + when others => assert FALSE report "Error : PMDATASCALE2 is not in range 0...3." severity error; + end case; + case PMDATASCALE3 is + when 0 => PMDATASCALE3_BINARY <= "00"; + when 1 => PMDATASCALE3_BINARY <= "01"; + when 2 => PMDATASCALE3_BINARY <= "10"; + when 3 => PMDATASCALE3_BINARY <= "11"; + when others => assert FALSE report "Error : PMDATASCALE3 is not in range 0...3." severity error; + end case; + case PMDATASCALE4 is + when 0 => PMDATASCALE4_BINARY <= "00"; + when 1 => PMDATASCALE4_BINARY <= "01"; + when 2 => PMDATASCALE4_BINARY <= "10"; + when 3 => PMDATASCALE4_BINARY <= "11"; + when others => assert FALSE report "Error : PMDATASCALE4 is not in range 0...3." severity error; + end case; + case PMDATASCALE5 is + when 0 => PMDATASCALE5_BINARY <= "00"; + when 1 => PMDATASCALE5_BINARY <= "01"; + when 2 => PMDATASCALE5_BINARY <= "10"; + when 3 => PMDATASCALE5_BINARY <= "11"; + when others => assert FALSE report "Error : PMDATASCALE5 is not in range 0...3." severity error; + end case; + case PMDATASCALE6 is + when 0 => PMDATASCALE6_BINARY <= "00"; + when 1 => PMDATASCALE6_BINARY <= "01"; + when 2 => PMDATASCALE6_BINARY <= "10"; + when 3 => PMDATASCALE6_BINARY <= "11"; + when others => assert FALSE report "Error : PMDATASCALE6 is not in range 0...3." severity error; + end case; + case PMDATASCALE7 is + when 0 => PMDATASCALE7_BINARY <= "00"; + when 1 => PMDATASCALE7_BINARY <= "01"; + when 2 => PMDATASCALE7_BINARY <= "10"; + when 3 => PMDATASCALE7_BINARY <= "11"; + when others => assert FALSE report "Error : PMDATASCALE7 is not in range 0...3." severity error; + end case; + case PMDATASCALE8 is + when 0 => PMDATASCALE8_BINARY <= "00"; + when 1 => PMDATASCALE8_BINARY <= "01"; + when 2 => PMDATASCALE8_BINARY <= "10"; + when 3 => PMDATASCALE8_BINARY <= "11"; + when others => assert FALSE report "Error : PMDATASCALE8 is not in range 0...3." severity error; + end case; + case PCIECAPABILITYSLOTIMPL is + when FALSE => PCIECAPABILITYSLOTIMPL_BINARY <= '0'; + when TRUE => PCIECAPABILITYSLOTIMPL_BINARY <= '1'; + when others => assert FALSE report "Error : PCIECAPABILITYSLOTIMPL is neither TRUE nor FALSE." severity error; + end case; + case LINKSTATUSSLOTCLOCKCONFIG is + when FALSE => LINKSTATUSSLOTCLOCKCONFIG_BINARY <= '0'; + when TRUE => LINKSTATUSSLOTCLOCKCONFIG_BINARY <= '1'; + when others => assert FALSE report "Error : LINKSTATUSSLOTCLOCKCONFIG is neither TRUE nor FALSE." severity error; + end case; + case SLOTCAPABILITYATTBUTTONPRESENT is + when FALSE => SLOTCAPABILITYATTBUTTONPRESENT_BINARY <= '0'; + when TRUE => SLOTCAPABILITYATTBUTTONPRESENT_BINARY <= '1'; + when others => assert FALSE report "Error : SLOTCAPABILITYATTBUTTONPRESENT is neither TRUE nor FALSE." severity error; + end case; + case SLOTCAPABILITYPOWERCONTROLLERPRESENT is + when FALSE => SLOTCAPABILITYPOWERCONTROLLERPRESENT_BINARY <= '0'; + when TRUE => SLOTCAPABILITYPOWERCONTROLLERPRESENT_BINARY <= '1'; + when others => assert FALSE report "Error : SLOTCAPABILITYPOWERCONTROLLERPRESENT is neither TRUE nor FALSE." severity error; + end case; + case SLOTCAPABILITYMSLSENSORPRESENT is + when FALSE => SLOTCAPABILITYMSLSENSORPRESENT_BINARY <= '0'; + when TRUE => SLOTCAPABILITYMSLSENSORPRESENT_BINARY <= '1'; + when others => assert FALSE report "Error : SLOTCAPABILITYMSLSENSORPRESENT is neither TRUE nor FALSE." severity error; + end case; + case SLOTCAPABILITYATTINDICATORPRESENT is + when FALSE => SLOTCAPABILITYATTINDICATORPRESENT_BINARY <= '0'; + when TRUE => SLOTCAPABILITYATTINDICATORPRESENT_BINARY <= '1'; + when others => assert FALSE report "Error : SLOTCAPABILITYATTINDICATORPRESENT is neither TRUE nor FALSE." severity error; + end case; + case SLOTCAPABILITYPOWERINDICATORPRESENT is + when FALSE => SLOTCAPABILITYPOWERINDICATORPRESENT_BINARY <= '0'; + when TRUE => SLOTCAPABILITYPOWERINDICATORPRESENT_BINARY <= '1'; + when others => assert FALSE report "Error : SLOTCAPABILITYPOWERINDICATORPRESENT is neither TRUE nor FALSE." severity error; + end case; + case SLOTCAPABILITYHOTPLUGSURPRISE is + when FALSE => SLOTCAPABILITYHOTPLUGSURPRISE_BINARY <= '0'; + when TRUE => SLOTCAPABILITYHOTPLUGSURPRISE_BINARY <= '1'; + when others => assert FALSE report "Error : SLOTCAPABILITYHOTPLUGSURPRISE is neither TRUE nor FALSE." severity error; + end case; + case SLOTCAPABILITYHOTPLUGCAPABLE is + when FALSE => SLOTCAPABILITYHOTPLUGCAPABLE_BINARY <= '0'; + when TRUE => SLOTCAPABILITYHOTPLUGCAPABLE_BINARY <= '1'; + when others => assert FALSE report "Error : SLOTCAPABILITYHOTPLUGCAPABLE is neither TRUE nor FALSE." severity error; + end case; + case AERCAPABILITYECRCGENCAPABLE is + when FALSE => AERCAPABILITYECRCGENCAPABLE_BINARY <= '0'; + when TRUE => AERCAPABILITYECRCGENCAPABLE_BINARY <= '1'; + when others => assert FALSE report "Error : AERCAPABILITYECRCGENCAPABLE is neither TRUE nor FALSE." severity error; + end case; + case AERCAPABILITYECRCCHECKCAPABLE is + when FALSE => AERCAPABILITYECRCCHECKCAPABLE_BINARY <= '0'; + when TRUE => AERCAPABILITYECRCCHECKCAPABLE_BINARY <= '1'; + when others => assert FALSE report "Error : AERCAPABILITYECRCCHECKCAPABLE is neither TRUE nor FALSE." severity error; + end case; + case PBCAPABILITYSYSTEMALLOCATED is + when FALSE => PBCAPABILITYSYSTEMALLOCATED_BINARY <= '0'; + when TRUE => PBCAPABILITYSYSTEMALLOCATED_BINARY <= '1'; + when others => assert FALSE report "Error : PBCAPABILITYSYSTEMALLOCATED is neither TRUE nor FALSE." severity error; + end case; + case RESETMODE is + when FALSE => RESETMODE_BINARY <= '0'; + when TRUE => RESETMODE_BINARY <= '1'; + when others => assert FALSE report "Error : RESETMODE is neither TRUE nor FALSE." severity error; + end case; + case CLKDIVIDED is + when FALSE => CLKDIVIDED_BINARY <= '0'; + when TRUE => CLKDIVIDED_BINARY <= '1'; + when others => assert FALSE report "Error : CLKDIVIDED is neither TRUE nor FALSE." severity error; + end case; + wait; + end process INIPROC; + + TIMING : process + + + + variable PIPETXDATAL00_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL01_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL02_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL03_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL04_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL05_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL06_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL07_GlitchData : VitalGlitchDataType; + variable PIPETXDATAKL0_GlitchData : VitalGlitchDataType; + variable PIPETXELECIDLEL0_GlitchData : VitalGlitchDataType; + variable PIPETXDETECTRXLOOPBACKL0_GlitchData : VitalGlitchDataType; + variable PIPETXCOMPLIANCEL0_GlitchData : VitalGlitchDataType; + variable PIPERXPOLARITYL0_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL00_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL01_GlitchData : VitalGlitchDataType; + variable PIPEDESKEWLANESL0_GlitchData : VitalGlitchDataType; + variable PIPERESETL0_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL10_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL11_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL12_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL13_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL14_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL15_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL16_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL17_GlitchData : VitalGlitchDataType; + variable PIPETXDATAKL1_GlitchData : VitalGlitchDataType; + variable PIPETXELECIDLEL1_GlitchData : VitalGlitchDataType; + variable PIPETXDETECTRXLOOPBACKL1_GlitchData : VitalGlitchDataType; + variable PIPETXCOMPLIANCEL1_GlitchData : VitalGlitchDataType; + variable PIPERXPOLARITYL1_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL10_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL11_GlitchData : VitalGlitchDataType; + variable PIPEDESKEWLANESL1_GlitchData : VitalGlitchDataType; + variable PIPERESETL1_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL20_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL21_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL22_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL23_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL24_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL25_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL26_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL27_GlitchData : VitalGlitchDataType; + variable PIPETXDATAKL2_GlitchData : VitalGlitchDataType; + variable PIPETXELECIDLEL2_GlitchData : VitalGlitchDataType; + variable PIPETXDETECTRXLOOPBACKL2_GlitchData : VitalGlitchDataType; + variable PIPETXCOMPLIANCEL2_GlitchData : VitalGlitchDataType; + variable PIPERXPOLARITYL2_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL20_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL21_GlitchData : VitalGlitchDataType; + variable PIPEDESKEWLANESL2_GlitchData : VitalGlitchDataType; + variable PIPERESETL2_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL30_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL31_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL32_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL33_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL34_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL35_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL36_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL37_GlitchData : VitalGlitchDataType; + variable PIPETXDATAKL3_GlitchData : VitalGlitchDataType; + variable PIPETXELECIDLEL3_GlitchData : VitalGlitchDataType; + variable PIPETXDETECTRXLOOPBACKL3_GlitchData : VitalGlitchDataType; + variable PIPETXCOMPLIANCEL3_GlitchData : VitalGlitchDataType; + variable PIPERXPOLARITYL3_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL30_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL31_GlitchData : VitalGlitchDataType; + variable PIPEDESKEWLANESL3_GlitchData : VitalGlitchDataType; + variable PIPERESETL3_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL40_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL41_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL42_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL43_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL44_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL45_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL46_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL47_GlitchData : VitalGlitchDataType; + variable PIPETXDATAKL4_GlitchData : VitalGlitchDataType; + variable PIPETXELECIDLEL4_GlitchData : VitalGlitchDataType; + variable PIPETXDETECTRXLOOPBACKL4_GlitchData : VitalGlitchDataType; + variable PIPETXCOMPLIANCEL4_GlitchData : VitalGlitchDataType; + variable PIPERXPOLARITYL4_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL40_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL41_GlitchData : VitalGlitchDataType; + variable PIPEDESKEWLANESL4_GlitchData : VitalGlitchDataType; + variable PIPERESETL4_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL50_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL51_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL52_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL53_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL54_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL55_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL56_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL57_GlitchData : VitalGlitchDataType; + variable PIPETXDATAKL5_GlitchData : VitalGlitchDataType; + variable PIPETXELECIDLEL5_GlitchData : VitalGlitchDataType; + variable PIPETXDETECTRXLOOPBACKL5_GlitchData : VitalGlitchDataType; + variable PIPETXCOMPLIANCEL5_GlitchData : VitalGlitchDataType; + variable PIPERXPOLARITYL5_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL50_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL51_GlitchData : VitalGlitchDataType; + variable PIPEDESKEWLANESL5_GlitchData : VitalGlitchDataType; + variable PIPERESETL5_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL60_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL61_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL62_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL63_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL64_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL65_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL66_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL67_GlitchData : VitalGlitchDataType; + variable PIPETXDATAKL6_GlitchData : VitalGlitchDataType; + variable PIPETXELECIDLEL6_GlitchData : VitalGlitchDataType; + variable PIPETXDETECTRXLOOPBACKL6_GlitchData : VitalGlitchDataType; + variable PIPETXCOMPLIANCEL6_GlitchData : VitalGlitchDataType; + variable PIPERXPOLARITYL6_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL60_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL61_GlitchData : VitalGlitchDataType; + variable PIPEDESKEWLANESL6_GlitchData : VitalGlitchDataType; + variable PIPERESETL6_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL70_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL71_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL72_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL73_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL74_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL75_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL76_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL77_GlitchData : VitalGlitchDataType; + variable PIPETXDATAKL7_GlitchData : VitalGlitchDataType; + variable PIPETXELECIDLEL7_GlitchData : VitalGlitchDataType; + variable PIPETXDETECTRXLOOPBACKL7_GlitchData : VitalGlitchDataType; + variable PIPETXCOMPLIANCEL7_GlitchData : VitalGlitchDataType; + variable PIPERXPOLARITYL7_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL70_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL71_GlitchData : VitalGlitchDataType; + variable PIPEDESKEWLANESL7_GlitchData : VitalGlitchDataType; + variable PIPERESETL7_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA0_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA1_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA2_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA3_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA4_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA5_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA6_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA7_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA8_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA9_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA10_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA11_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA12_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA13_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA14_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA15_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA16_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA17_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA18_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA19_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA20_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA21_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA22_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA23_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA24_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA25_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA26_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA27_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA28_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA29_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA30_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA31_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA32_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA33_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA34_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA35_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA36_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA37_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA38_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA39_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA40_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA41_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA42_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA43_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA44_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA45_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA46_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA47_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA48_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA49_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA50_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA51_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA52_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA53_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA54_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA55_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA56_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA57_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA58_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA59_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA60_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA61_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA62_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA63_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD0_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD1_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD2_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD3_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD4_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD5_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD6_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD7_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD8_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD9_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD10_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD11_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD12_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD0_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD1_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD2_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD3_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD4_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD5_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD6_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD7_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD8_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD9_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD10_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD11_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD12_GlitchData : VitalGlitchDataType; + variable MIMRXBWEN_GlitchData : VitalGlitchDataType; + variable MIMRXBREN_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA0_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA1_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA2_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA3_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA4_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA5_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA6_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA7_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA8_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA9_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA10_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA11_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA12_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA13_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA14_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA15_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA16_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA17_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA18_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA19_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA20_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA21_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA22_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA23_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA24_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA25_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA26_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA27_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA28_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA29_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA30_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA31_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA32_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA33_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA34_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA35_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA36_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA37_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA38_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA39_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA40_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA41_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA42_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA43_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA44_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA45_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA46_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA47_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA48_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA49_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA50_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA51_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA52_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA53_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA54_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA55_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA56_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA57_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA58_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA59_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA60_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA61_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA62_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA63_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD0_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD1_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD2_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD3_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD4_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD5_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD6_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD7_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD8_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD9_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD10_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD11_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD12_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD0_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD1_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD2_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD3_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD4_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD5_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD6_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD7_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD8_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD9_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD10_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD11_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD12_GlitchData : VitalGlitchDataType; + variable MIMTXBWEN_GlitchData : VitalGlitchDataType; + variable MIMTXBREN_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA0_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA1_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA2_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA3_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA4_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA5_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA6_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA7_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA8_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA9_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA10_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA11_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA12_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA13_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA14_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA15_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA16_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA17_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA18_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA19_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA20_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA21_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA22_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA23_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA24_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA25_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA26_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA27_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA28_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA29_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA30_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA31_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA32_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA33_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA34_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA35_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA36_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA37_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA38_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA39_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA40_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA41_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA42_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA43_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA44_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA45_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA46_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA47_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA48_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA49_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA50_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA51_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA52_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA53_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA54_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA55_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA56_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA57_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA58_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA59_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA60_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA61_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA62_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA63_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD0_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD1_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD2_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD3_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD4_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD5_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD6_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD7_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD8_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD9_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD10_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD11_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD0_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD1_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD2_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD3_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD4_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD5_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD6_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD7_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD8_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD9_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD10_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD11_GlitchData : VitalGlitchDataType; + variable MIMDLLBWEN_GlitchData : VitalGlitchDataType; + variable MIMDLLBREN_GlitchData : VitalGlitchDataType; + variable CRMRXHOTRESETN_GlitchData : VitalGlitchDataType; + variable CRMDOHOTRESETN_GlitchData : VitalGlitchDataType; + variable CRMPWRSOFTRESETN_GlitchData : VitalGlitchDataType; + variable LLKTCSTATUS0_GlitchData : VitalGlitchDataType; + variable LLKTCSTATUS1_GlitchData : VitalGlitchDataType; + variable LLKTCSTATUS2_GlitchData : VitalGlitchDataType; + variable LLKTCSTATUS3_GlitchData : VitalGlitchDataType; + variable LLKTCSTATUS4_GlitchData : VitalGlitchDataType; + variable LLKTCSTATUS5_GlitchData : VitalGlitchDataType; + variable LLKTCSTATUS6_GlitchData : VitalGlitchDataType; + variable LLKTCSTATUS7_GlitchData : VitalGlitchDataType; + variable LLKTXDSTRDYN_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE0_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE1_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE2_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE3_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE4_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE5_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE6_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE7_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE8_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE9_GlitchData : VitalGlitchDataType; + variable LLKTXCHPOSTEDREADYN0_GlitchData : VitalGlitchDataType; + variable LLKTXCHPOSTEDREADYN1_GlitchData : VitalGlitchDataType; + variable LLKTXCHPOSTEDREADYN2_GlitchData : VitalGlitchDataType; + variable LLKTXCHPOSTEDREADYN3_GlitchData : VitalGlitchDataType; + variable LLKTXCHPOSTEDREADYN4_GlitchData : VitalGlitchDataType; + variable LLKTXCHPOSTEDREADYN5_GlitchData : VitalGlitchDataType; + variable LLKTXCHPOSTEDREADYN6_GlitchData : VitalGlitchDataType; + variable LLKTXCHPOSTEDREADYN7_GlitchData : VitalGlitchDataType; + variable LLKTXCHNONPOSTEDREADYN0_GlitchData : VitalGlitchDataType; + variable LLKTXCHNONPOSTEDREADYN1_GlitchData : VitalGlitchDataType; + variable LLKTXCHNONPOSTEDREADYN2_GlitchData : VitalGlitchDataType; + variable LLKTXCHNONPOSTEDREADYN3_GlitchData : VitalGlitchDataType; + variable LLKTXCHNONPOSTEDREADYN4_GlitchData : VitalGlitchDataType; + variable LLKTXCHNONPOSTEDREADYN5_GlitchData : VitalGlitchDataType; + variable LLKTXCHNONPOSTEDREADYN6_GlitchData : VitalGlitchDataType; + variable LLKTXCHNONPOSTEDREADYN7_GlitchData : VitalGlitchDataType; + variable LLKTXCHCOMPLETIONREADYN0_GlitchData : VitalGlitchDataType; + variable LLKTXCHCOMPLETIONREADYN1_GlitchData : VitalGlitchDataType; + variable LLKTXCHCOMPLETIONREADYN2_GlitchData : VitalGlitchDataType; + variable LLKTXCHCOMPLETIONREADYN3_GlitchData : VitalGlitchDataType; + variable LLKTXCHCOMPLETIONREADYN4_GlitchData : VitalGlitchDataType; + variable LLKTXCHCOMPLETIONREADYN5_GlitchData : VitalGlitchDataType; + variable LLKTXCHCOMPLETIONREADYN6_GlitchData : VitalGlitchDataType; + variable LLKTXCHCOMPLETIONREADYN7_GlitchData : VitalGlitchDataType; + variable LLKTXCONFIGREADYN_GlitchData : VitalGlitchDataType; + variable LLKRXDATA0_GlitchData : VitalGlitchDataType; + variable LLKRXDATA1_GlitchData : VitalGlitchDataType; + variable LLKRXDATA2_GlitchData : VitalGlitchDataType; + variable LLKRXDATA3_GlitchData : VitalGlitchDataType; + variable LLKRXDATA4_GlitchData : VitalGlitchDataType; + variable LLKRXDATA5_GlitchData : VitalGlitchDataType; + variable LLKRXDATA6_GlitchData : VitalGlitchDataType; + variable LLKRXDATA7_GlitchData : VitalGlitchDataType; + variable LLKRXDATA8_GlitchData : VitalGlitchDataType; + variable LLKRXDATA9_GlitchData : VitalGlitchDataType; + variable LLKRXDATA10_GlitchData : VitalGlitchDataType; + variable LLKRXDATA11_GlitchData : VitalGlitchDataType; + variable LLKRXDATA12_GlitchData : VitalGlitchDataType; + variable LLKRXDATA13_GlitchData : VitalGlitchDataType; + variable LLKRXDATA14_GlitchData : VitalGlitchDataType; + variable LLKRXDATA15_GlitchData : VitalGlitchDataType; + variable LLKRXDATA16_GlitchData : VitalGlitchDataType; + variable LLKRXDATA17_GlitchData : VitalGlitchDataType; + variable LLKRXDATA18_GlitchData : VitalGlitchDataType; + variable LLKRXDATA19_GlitchData : VitalGlitchDataType; + variable LLKRXDATA20_GlitchData : VitalGlitchDataType; + variable LLKRXDATA21_GlitchData : VitalGlitchDataType; + variable LLKRXDATA22_GlitchData : VitalGlitchDataType; + variable LLKRXDATA23_GlitchData : VitalGlitchDataType; + variable LLKRXDATA24_GlitchData : VitalGlitchDataType; + variable LLKRXDATA25_GlitchData : VitalGlitchDataType; + variable LLKRXDATA26_GlitchData : VitalGlitchDataType; + variable LLKRXDATA27_GlitchData : VitalGlitchDataType; + variable LLKRXDATA28_GlitchData : VitalGlitchDataType; + variable LLKRXDATA29_GlitchData : VitalGlitchDataType; + variable LLKRXDATA30_GlitchData : VitalGlitchDataType; + variable LLKRXDATA31_GlitchData : VitalGlitchDataType; + variable LLKRXDATA32_GlitchData : VitalGlitchDataType; + variable LLKRXDATA33_GlitchData : VitalGlitchDataType; + variable LLKRXDATA34_GlitchData : VitalGlitchDataType; + variable LLKRXDATA35_GlitchData : VitalGlitchDataType; + variable LLKRXDATA36_GlitchData : VitalGlitchDataType; + variable LLKRXDATA37_GlitchData : VitalGlitchDataType; + variable LLKRXDATA38_GlitchData : VitalGlitchDataType; + variable LLKRXDATA39_GlitchData : VitalGlitchDataType; + variable LLKRXDATA40_GlitchData : VitalGlitchDataType; + variable LLKRXDATA41_GlitchData : VitalGlitchDataType; + variable LLKRXDATA42_GlitchData : VitalGlitchDataType; + variable LLKRXDATA43_GlitchData : VitalGlitchDataType; + variable LLKRXDATA44_GlitchData : VitalGlitchDataType; + variable LLKRXDATA45_GlitchData : VitalGlitchDataType; + variable LLKRXDATA46_GlitchData : VitalGlitchDataType; + variable LLKRXDATA47_GlitchData : VitalGlitchDataType; + variable LLKRXDATA48_GlitchData : VitalGlitchDataType; + variable LLKRXDATA49_GlitchData : VitalGlitchDataType; + variable LLKRXDATA50_GlitchData : VitalGlitchDataType; + variable LLKRXDATA51_GlitchData : VitalGlitchDataType; + variable LLKRXDATA52_GlitchData : VitalGlitchDataType; + variable LLKRXDATA53_GlitchData : VitalGlitchDataType; + variable LLKRXDATA54_GlitchData : VitalGlitchDataType; + variable LLKRXDATA55_GlitchData : VitalGlitchDataType; + variable LLKRXDATA56_GlitchData : VitalGlitchDataType; + variable LLKRXDATA57_GlitchData : VitalGlitchDataType; + variable LLKRXDATA58_GlitchData : VitalGlitchDataType; + variable LLKRXDATA59_GlitchData : VitalGlitchDataType; + variable LLKRXDATA60_GlitchData : VitalGlitchDataType; + variable LLKRXDATA61_GlitchData : VitalGlitchDataType; + variable LLKRXDATA62_GlitchData : VitalGlitchDataType; + variable LLKRXDATA63_GlitchData : VitalGlitchDataType; + variable LLKRXSRCRDYN_GlitchData : VitalGlitchDataType; + variable LLKRXSRCLASTREQN_GlitchData : VitalGlitchDataType; + variable LLKRXSRCDSCN_GlitchData : VitalGlitchDataType; + variable LLKRXSOFN_GlitchData : VitalGlitchDataType; + variable LLKRXEOFN_GlitchData : VitalGlitchDataType; + variable LLKRXSOPN_GlitchData : VitalGlitchDataType; + variable LLKRXEOPN_GlitchData : VitalGlitchDataType; + variable LLKRXVALIDN0_GlitchData : VitalGlitchDataType; + variable LLKRXVALIDN1_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE0_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE1_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE2_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE3_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE4_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE5_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE6_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE7_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE8_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE9_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE10_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE11_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE12_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE13_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE14_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE15_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDAVAILABLEN0_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDAVAILABLEN1_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDAVAILABLEN2_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDAVAILABLEN3_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDAVAILABLEN4_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDAVAILABLEN5_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDAVAILABLEN6_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDAVAILABLEN7_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDAVAILABLEN0_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDAVAILABLEN1_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDAVAILABLEN2_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDAVAILABLEN3_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDAVAILABLEN4_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDAVAILABLEN5_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDAVAILABLEN6_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDAVAILABLEN7_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONAVAILABLEN0_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONAVAILABLEN1_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONAVAILABLEN2_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONAVAILABLEN3_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONAVAILABLEN4_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONAVAILABLEN5_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONAVAILABLEN6_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONAVAILABLEN7_GlitchData : VitalGlitchDataType; + variable LLKRXCHCONFIGAVAILABLEN_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDPARTIALN0_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDPARTIALN1_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDPARTIALN2_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDPARTIALN3_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDPARTIALN4_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDPARTIALN5_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDPARTIALN6_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDPARTIALN7_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDPARTIALN0_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDPARTIALN1_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDPARTIALN2_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDPARTIALN3_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDPARTIALN4_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDPARTIALN5_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDPARTIALN6_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDPARTIALN7_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONPARTIALN0_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONPARTIALN1_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONPARTIALN2_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONPARTIALN3_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONPARTIALN4_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONPARTIALN5_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONPARTIALN6_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONPARTIALN7_GlitchData : VitalGlitchDataType; + variable LLKRXCHCONFIGPARTIALN_GlitchData : VitalGlitchDataType; + variable LLKRX4DWHEADERN_GlitchData : VitalGlitchDataType; + variable LLKRXECRCBADN_GlitchData : VitalGlitchDataType; + variable MGMTRDATA0_GlitchData : VitalGlitchDataType; + variable MGMTRDATA1_GlitchData : VitalGlitchDataType; + variable MGMTRDATA2_GlitchData : VitalGlitchDataType; + variable MGMTRDATA3_GlitchData : VitalGlitchDataType; + variable MGMTRDATA4_GlitchData : VitalGlitchDataType; + variable MGMTRDATA5_GlitchData : VitalGlitchDataType; + variable MGMTRDATA6_GlitchData : VitalGlitchDataType; + variable MGMTRDATA7_GlitchData : VitalGlitchDataType; + variable MGMTRDATA8_GlitchData : VitalGlitchDataType; + variable MGMTRDATA9_GlitchData : VitalGlitchDataType; + variable MGMTRDATA10_GlitchData : VitalGlitchDataType; + variable MGMTRDATA11_GlitchData : VitalGlitchDataType; + variable MGMTRDATA12_GlitchData : VitalGlitchDataType; + variable MGMTRDATA13_GlitchData : VitalGlitchDataType; + variable MGMTRDATA14_GlitchData : VitalGlitchDataType; + variable MGMTRDATA15_GlitchData : VitalGlitchDataType; + variable MGMTRDATA16_GlitchData : VitalGlitchDataType; + variable MGMTRDATA17_GlitchData : VitalGlitchDataType; + variable MGMTRDATA18_GlitchData : VitalGlitchDataType; + variable MGMTRDATA19_GlitchData : VitalGlitchDataType; + variable MGMTRDATA20_GlitchData : VitalGlitchDataType; + variable MGMTRDATA21_GlitchData : VitalGlitchDataType; + variable MGMTRDATA22_GlitchData : VitalGlitchDataType; + variable MGMTRDATA23_GlitchData : VitalGlitchDataType; + variable MGMTRDATA24_GlitchData : VitalGlitchDataType; + variable MGMTRDATA25_GlitchData : VitalGlitchDataType; + variable MGMTRDATA26_GlitchData : VitalGlitchDataType; + variable MGMTRDATA27_GlitchData : VitalGlitchDataType; + variable MGMTRDATA28_GlitchData : VitalGlitchDataType; + variable MGMTRDATA29_GlitchData : VitalGlitchDataType; + variable MGMTRDATA30_GlitchData : VitalGlitchDataType; + variable MGMTRDATA31_GlitchData : VitalGlitchDataType; + variable MGMTPSO0_GlitchData : VitalGlitchDataType; + variable MGMTPSO1_GlitchData : VitalGlitchDataType; + variable MGMTPSO2_GlitchData : VitalGlitchDataType; + variable MGMTPSO3_GlitchData : VitalGlitchDataType; + variable MGMTPSO4_GlitchData : VitalGlitchDataType; + variable MGMTPSO5_GlitchData : VitalGlitchDataType; + variable MGMTPSO6_GlitchData : VitalGlitchDataType; + variable MGMTPSO7_GlitchData : VitalGlitchDataType; + variable MGMTPSO8_GlitchData : VitalGlitchDataType; + variable MGMTPSO9_GlitchData : VitalGlitchDataType; + variable MGMTPSO10_GlitchData : VitalGlitchDataType; + variable MGMTPSO11_GlitchData : VitalGlitchDataType; + variable MGMTPSO12_GlitchData : VitalGlitchDataType; + variable MGMTPSO13_GlitchData : VitalGlitchDataType; + variable MGMTPSO14_GlitchData : VitalGlitchDataType; + variable MGMTPSO15_GlitchData : VitalGlitchDataType; + variable MGMTPSO16_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT0_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT1_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT2_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT3_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT4_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT5_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT6_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT7_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT8_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT9_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT10_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT11_GlitchData : VitalGlitchDataType; + variable L0RXDLLTLPECRCOK_GlitchData : VitalGlitchDataType; + variable DLLTXPMDLLPOUTSTANDING_GlitchData : VitalGlitchDataType; + variable L0FIRSTCFGWRITEOCCURRED_GlitchData : VitalGlitchDataType; + variable L0CFGLOOPBACKACK_GlitchData : VitalGlitchDataType; + variable L0MACUPSTREAMDOWNSTREAM_GlitchData : VitalGlitchDataType; + variable L0RXMACLINKERROR0_GlitchData : VitalGlitchDataType; + variable L0RXMACLINKERROR1_GlitchData : VitalGlitchDataType; + variable L0MACLINKUP_GlitchData : VitalGlitchDataType; + variable L0MACNEGOTIATEDLINKWIDTH0_GlitchData : VitalGlitchDataType; + variable L0MACNEGOTIATEDLINKWIDTH1_GlitchData : VitalGlitchDataType; + variable L0MACNEGOTIATEDLINKWIDTH2_GlitchData : VitalGlitchDataType; + variable L0MACNEGOTIATEDLINKWIDTH3_GlitchData : VitalGlitchDataType; + variable L0MACLINKTRAINING_GlitchData : VitalGlitchDataType; + variable L0LTSSMSTATE0_GlitchData : VitalGlitchDataType; + variable L0LTSSMSTATE1_GlitchData : VitalGlitchDataType; + variable L0LTSSMSTATE2_GlitchData : VitalGlitchDataType; + variable L0LTSSMSTATE3_GlitchData : VitalGlitchDataType; + variable L0DLLVCSTATUS0_GlitchData : VitalGlitchDataType; + variable L0DLLVCSTATUS1_GlitchData : VitalGlitchDataType; + variable L0DLLVCSTATUS2_GlitchData : VitalGlitchDataType; + variable L0DLLVCSTATUS3_GlitchData : VitalGlitchDataType; + variable L0DLLVCSTATUS4_GlitchData : VitalGlitchDataType; + variable L0DLLVCSTATUS5_GlitchData : VitalGlitchDataType; + variable L0DLLVCSTATUS6_GlitchData : VitalGlitchDataType; + variable L0DLLVCSTATUS7_GlitchData : VitalGlitchDataType; + variable L0DLUPDOWN0_GlitchData : VitalGlitchDataType; + variable L0DLUPDOWN1_GlitchData : VitalGlitchDataType; + variable L0DLUPDOWN2_GlitchData : VitalGlitchDataType; + variable L0DLUPDOWN3_GlitchData : VitalGlitchDataType; + variable L0DLUPDOWN4_GlitchData : VitalGlitchDataType; + variable L0DLUPDOWN5_GlitchData : VitalGlitchDataType; + variable L0DLUPDOWN6_GlitchData : VitalGlitchDataType; + variable L0DLUPDOWN7_GlitchData : VitalGlitchDataType; + variable L0DLLERRORVECTOR0_GlitchData : VitalGlitchDataType; + variable L0DLLERRORVECTOR1_GlitchData : VitalGlitchDataType; + variable L0DLLERRORVECTOR2_GlitchData : VitalGlitchDataType; + variable L0DLLERRORVECTOR3_GlitchData : VitalGlitchDataType; + variable L0DLLERRORVECTOR4_GlitchData : VitalGlitchDataType; + variable L0DLLERRORVECTOR5_GlitchData : VitalGlitchDataType; + variable L0DLLERRORVECTOR6_GlitchData : VitalGlitchDataType; + variable L0DLLASRXSTATE0_GlitchData : VitalGlitchDataType; + variable L0DLLASRXSTATE1_GlitchData : VitalGlitchDataType; + variable L0DLLASTXSTATE_GlitchData : VitalGlitchDataType; + variable L0ASAUTONOMOUSINITCOMPLETED_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID0_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID1_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID2_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID3_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID4_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID5_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID6_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID7_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID8_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID9_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID10_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID11_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID12_GlitchData : VitalGlitchDataType; + variable L0UNLOCKRECEIVED_GlitchData : VitalGlitchDataType; + variable L0CORRERRMSGRCVD_GlitchData : VitalGlitchDataType; + variable L0FATALERRMSGRCVD_GlitchData : VitalGlitchDataType; + variable L0NONFATALERRMSGRCVD_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID0_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID1_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID2_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID3_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID4_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID5_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID6_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID7_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID8_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID9_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID10_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID11_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID12_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID13_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID14_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID15_GlitchData : VitalGlitchDataType; + variable L0FWDCORRERROUT_GlitchData : VitalGlitchDataType; + variable L0FWDFATALERROUT_GlitchData : VitalGlitchDataType; + variable L0FWDNONFATALERROUT_GlitchData : VitalGlitchDataType; + variable L0RECEIVEDASSERTINTALEGACYINT_GlitchData : VitalGlitchDataType; + variable L0RECEIVEDASSERTINTBLEGACYINT_GlitchData : VitalGlitchDataType; + variable L0RECEIVEDASSERTINTCLEGACYINT_GlitchData : VitalGlitchDataType; + variable L0RECEIVEDASSERTINTDLEGACYINT_GlitchData : VitalGlitchDataType; + variable L0RECEIVEDDEASSERTINTALEGACYINT_GlitchData : VitalGlitchDataType; + variable L0RECEIVEDDEASSERTINTBLEGACYINT_GlitchData : VitalGlitchDataType; + variable L0RECEIVEDDEASSERTINTCLEGACYINT_GlitchData : VitalGlitchDataType; + variable L0RECEIVEDDEASSERTINTDLEGACYINT_GlitchData : VitalGlitchDataType; + variable L0MSIENABLE0_GlitchData : VitalGlitchDataType; + variable L0MULTIMSGEN00_GlitchData : VitalGlitchDataType; + variable L0MULTIMSGEN01_GlitchData : VitalGlitchDataType; + variable L0MULTIMSGEN02_GlitchData : VitalGlitchDataType; + variable L0STATSDLLPRECEIVED_GlitchData : VitalGlitchDataType; + variable L0STATSDLLPTRANSMITTED_GlitchData : VitalGlitchDataType; + variable L0STATSOSRECEIVED_GlitchData : VitalGlitchDataType; + variable L0STATSOSTRANSMITTED_GlitchData : VitalGlitchDataType; + variable L0STATSTLPRECEIVED_GlitchData : VitalGlitchDataType; + variable L0STATSTLPTRANSMITTED_GlitchData : VitalGlitchDataType; + variable L0STATSCFGRECEIVED_GlitchData : VitalGlitchDataType; + variable L0STATSCFGTRANSMITTED_GlitchData : VitalGlitchDataType; + variable L0STATSCFGOTHERRECEIVED_GlitchData : VitalGlitchDataType; + variable L0STATSCFGOTHERTRANSMITTED_GlitchData : VitalGlitchDataType; + variable MAXPAYLOADSIZE0_GlitchData : VitalGlitchDataType; + variable MAXPAYLOADSIZE1_GlitchData : VitalGlitchDataType; + variable MAXPAYLOADSIZE2_GlitchData : VitalGlitchDataType; + variable MAXREADREQUESTSIZE0_GlitchData : VitalGlitchDataType; + variable MAXREADREQUESTSIZE1_GlitchData : VitalGlitchDataType; + variable MAXREADREQUESTSIZE2_GlitchData : VitalGlitchDataType; + variable IOSPACEENABLE_GlitchData : VitalGlitchDataType; + variable MEMSPACEENABLE_GlitchData : VitalGlitchDataType; + variable L0ATTENTIONINDICATORCONTROL0_GlitchData : VitalGlitchDataType; + variable L0ATTENTIONINDICATORCONTROL1_GlitchData : VitalGlitchDataType; + variable L0POWERINDICATORCONTROL0_GlitchData : VitalGlitchDataType; + variable L0POWERINDICATORCONTROL1_GlitchData : VitalGlitchDataType; + variable L0POWERCONTROLLERCONTROL_GlitchData : VitalGlitchDataType; + variable L0TOGGLEELECTROMECHANICALINTERLOCK_GlitchData : VitalGlitchDataType; + variable L0RXBEACON_GlitchData : VitalGlitchDataType; + variable L0PWRSTATE00_GlitchData : VitalGlitchDataType; + variable L0PWRSTATE01_GlitchData : VitalGlitchDataType; + variable L0PMEACK_GlitchData : VitalGlitchDataType; + variable L0PMEREQOUT_GlitchData : VitalGlitchDataType; + variable L0PMEEN_GlitchData : VitalGlitchDataType; + variable L0PWRINHIBITTRANSFERS_GlitchData : VitalGlitchDataType; + variable L0PWRL1STATE_GlitchData : VitalGlitchDataType; + variable L0PWRL23READYDEVICE_GlitchData : VitalGlitchDataType; + variable L0PWRL23READYSTATE_GlitchData : VitalGlitchDataType; + variable L0PWRTXL0SSTATE_GlitchData : VitalGlitchDataType; + variable L0PWRTURNOFFREQ_GlitchData : VitalGlitchDataType; + variable L0RXDLLPM_GlitchData : VitalGlitchDataType; + variable L0RXDLLPMTYPE0_GlitchData : VitalGlitchDataType; + variable L0RXDLLPMTYPE1_GlitchData : VitalGlitchDataType; + variable L0RXDLLPMTYPE2_GlitchData : VitalGlitchDataType; + variable L0TXDLLPMUPDATED_GlitchData : VitalGlitchDataType; + variable L0MACNEWSTATEACK_GlitchData : VitalGlitchDataType; + variable L0MACRXL0SSTATE_GlitchData : VitalGlitchDataType; + variable L0MACENTEREDL0_GlitchData : VitalGlitchDataType; + variable L0DLLRXACKOUTSTANDING_GlitchData : VitalGlitchDataType; + variable L0DLLTXOUTSTANDING_GlitchData : VitalGlitchDataType; + variable L0DLLTXNONFCOUTSTANDING_GlitchData : VitalGlitchDataType; + variable L0RXDLLTLPEND0_GlitchData : VitalGlitchDataType; + variable L0RXDLLTLPEND1_GlitchData : VitalGlitchDataType; + variable L0TXDLLSBFCUPDATED_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA0_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA1_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA2_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA3_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA4_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA5_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA6_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA7_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA8_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA9_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA10_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA11_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA12_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA13_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA14_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA15_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA16_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA17_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA18_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCUPDATE_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCNPOSTBYPUPDATED0_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCNPOSTBYPUPDATED1_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCNPOSTBYPUPDATED2_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCNPOSTBYPUPDATED3_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCNPOSTBYPUPDATED4_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCNPOSTBYPUPDATED5_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCNPOSTBYPUPDATED6_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCNPOSTBYPUPDATED7_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCPOSTORDUPDATED0_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCPOSTORDUPDATED1_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCPOSTORDUPDATED2_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCPOSTORDUPDATED3_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCPOSTORDUPDATED4_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCPOSTORDUPDATED5_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCPOSTORDUPDATED6_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCPOSTORDUPDATED7_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCCMPLMCUPDATED0_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCCMPLMCUPDATED1_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCCMPLMCUPDATED2_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCCMPLMCUPDATED3_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCCMPLMCUPDATED4_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCCMPLMCUPDATED5_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCCMPLMCUPDATED6_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCCMPLMCUPDATED7_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED0_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED1_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED2_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED3_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED4_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED5_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED6_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED7_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED8_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED9_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED10_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED11_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED12_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED13_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED14_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED15_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED16_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED17_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED18_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED19_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPUPDATE0_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPUPDATE1_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPUPDATE2_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPUPDATE3_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPUPDATE4_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPUPDATE5_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPUPDATE6_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPUPDATE7_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED0_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED1_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED2_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED3_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED4_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED5_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED6_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED7_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED8_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED9_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED10_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED11_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED12_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED13_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED14_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED15_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED16_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED17_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED18_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED19_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED20_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED21_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED22_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED23_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDUPDATE0_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDUPDATE1_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDUPDATE2_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDUPDATE3_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDUPDATE4_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDUPDATE5_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDUPDATE6_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDUPDATE7_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED0_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED1_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED2_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED3_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED4_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED5_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED6_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED7_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED8_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED9_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED10_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED11_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED12_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED13_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED14_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED15_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED16_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED17_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED18_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED19_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED20_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED21_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED22_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED23_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCUPDATE0_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCUPDATE1_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCUPDATE2_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCUPDATE3_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCUPDATE4_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCUPDATE5_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCUPDATE6_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCUPDATE7_GlitchData : VitalGlitchDataType; + variable L0UCBYPFOUND0_GlitchData : VitalGlitchDataType; + variable L0UCBYPFOUND1_GlitchData : VitalGlitchDataType; + variable L0UCBYPFOUND2_GlitchData : VitalGlitchDataType; + variable L0UCBYPFOUND3_GlitchData : VitalGlitchDataType; + variable L0UCORDFOUND0_GlitchData : VitalGlitchDataType; + variable L0UCORDFOUND1_GlitchData : VitalGlitchDataType; + variable L0UCORDFOUND2_GlitchData : VitalGlitchDataType; + variable L0UCORDFOUND3_GlitchData : VitalGlitchDataType; + variable L0MCFOUND0_GlitchData : VitalGlitchDataType; + variable L0MCFOUND1_GlitchData : VitalGlitchDataType; + variable L0MCFOUND2_GlitchData : VitalGlitchDataType; + variable L0TRANSFORMEDVC0_GlitchData : VitalGlitchDataType; + variable L0TRANSFORMEDVC1_GlitchData : VitalGlitchDataType; + variable L0TRANSFORMEDVC2_GlitchData : VitalGlitchDataType; + variable BUSMASTERENABLE_GlitchData : VitalGlitchDataType; + variable PARITYERRORRESPONSE_GlitchData : VitalGlitchDataType; + variable SERRENABLE_GlitchData : VitalGlitchDataType; + variable INTERRUPTDISABLE_GlitchData : VitalGlitchDataType; + variable URREPORTINGENABLE_GlitchData : VitalGlitchDataType; +begin + + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL0(0), + GlitchData => PIPETXDATAL00_GlitchData, + OutSignalName => "PIPETXDATAL0(0)", + OutTemp => PIPETXDATAL0_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL0(1), + GlitchData => PIPETXDATAL01_GlitchData, + OutSignalName => "PIPETXDATAL0(1)", + OutTemp => PIPETXDATAL0_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL0(2), + GlitchData => PIPETXDATAL02_GlitchData, + OutSignalName => "PIPETXDATAL0(2)", + OutTemp => PIPETXDATAL0_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL0(3), + GlitchData => PIPETXDATAL03_GlitchData, + OutSignalName => "PIPETXDATAL0(3)", + OutTemp => PIPETXDATAL0_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL0(4), + GlitchData => PIPETXDATAL04_GlitchData, + OutSignalName => "PIPETXDATAL0(4)", + OutTemp => PIPETXDATAL0_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL0(5), + GlitchData => PIPETXDATAL05_GlitchData, + OutSignalName => "PIPETXDATAL0(5)", + OutTemp => PIPETXDATAL0_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL0(6), + GlitchData => PIPETXDATAL06_GlitchData, + OutSignalName => "PIPETXDATAL0(6)", + OutTemp => PIPETXDATAL0_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL0(7), + GlitchData => PIPETXDATAL07_GlitchData, + OutSignalName => "PIPETXDATAL0(7)", + OutTemp => PIPETXDATAL0_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAKL0, + GlitchData => PIPETXDATAKL0_GlitchData, + OutSignalName => "PIPETXDATAKL0", + OutTemp => PIPETXDATAKL0_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXELECIDLEL0, + GlitchData => PIPETXELECIDLEL0_GlitchData, + OutSignalName => "PIPETXELECIDLEL0", + OutTemp => PIPETXELECIDLEL0_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDETECTRXLOOPBACKL0, + GlitchData => PIPETXDETECTRXLOOPBACKL0_GlitchData, + OutSignalName => "PIPETXDETECTRXLOOPBACKL0", + OutTemp => PIPETXDETECTRXLOOPBACKL0_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXCOMPLIANCEL0, + GlitchData => PIPETXCOMPLIANCEL0_GlitchData, + OutSignalName => "PIPETXCOMPLIANCEL0", + OutTemp => PIPETXCOMPLIANCEL0_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERXPOLARITYL0, + GlitchData => PIPERXPOLARITYL0_GlitchData, + OutSignalName => "PIPERXPOLARITYL0", + OutTemp => PIPERXPOLARITYL0_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL0(0), + GlitchData => PIPEPOWERDOWNL00_GlitchData, + OutSignalName => "PIPEPOWERDOWNL0(0)", + OutTemp => PIPEPOWERDOWNL0_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL0(0), + GlitchData => PIPEPOWERDOWNL00_GlitchData, + OutSignalName => "PIPEPOWERDOWNL0(0)", + OutTemp => PIPEPOWERDOWNL0_OUT(0), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL0(1), + GlitchData => PIPEPOWERDOWNL01_GlitchData, + OutSignalName => "PIPEPOWERDOWNL0(1)", + OutTemp => PIPEPOWERDOWNL0_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL0(1), + GlitchData => PIPEPOWERDOWNL01_GlitchData, + OutSignalName => "PIPEPOWERDOWNL0(1)", + OutTemp => PIPEPOWERDOWNL0_OUT(1), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEDESKEWLANESL0, + GlitchData => PIPEDESKEWLANESL0_GlitchData, + OutSignalName => "PIPEDESKEWLANESL0", + OutTemp => PIPEDESKEWLANESL0_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERESETL0, + GlitchData => PIPERESETL0_GlitchData, + OutSignalName => "PIPERESETL0", + OutTemp => PIPERESETL0_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL1(0), + GlitchData => PIPETXDATAL10_GlitchData, + OutSignalName => "PIPETXDATAL1(0)", + OutTemp => PIPETXDATAL1_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL1(1), + GlitchData => PIPETXDATAL11_GlitchData, + OutSignalName => "PIPETXDATAL1(1)", + OutTemp => PIPETXDATAL1_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL1(2), + GlitchData => PIPETXDATAL12_GlitchData, + OutSignalName => "PIPETXDATAL1(2)", + OutTemp => PIPETXDATAL1_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL1(3), + GlitchData => PIPETXDATAL13_GlitchData, + OutSignalName => "PIPETXDATAL1(3)", + OutTemp => PIPETXDATAL1_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL1(4), + GlitchData => PIPETXDATAL14_GlitchData, + OutSignalName => "PIPETXDATAL1(4)", + OutTemp => PIPETXDATAL1_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL1(5), + GlitchData => PIPETXDATAL15_GlitchData, + OutSignalName => "PIPETXDATAL1(5)", + OutTemp => PIPETXDATAL1_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL1(6), + GlitchData => PIPETXDATAL16_GlitchData, + OutSignalName => "PIPETXDATAL1(6)", + OutTemp => PIPETXDATAL1_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL1(7), + GlitchData => PIPETXDATAL17_GlitchData, + OutSignalName => "PIPETXDATAL1(7)", + OutTemp => PIPETXDATAL1_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAKL1, + GlitchData => PIPETXDATAKL1_GlitchData, + OutSignalName => "PIPETXDATAKL1", + OutTemp => PIPETXDATAKL1_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXELECIDLEL1, + GlitchData => PIPETXELECIDLEL1_GlitchData, + OutSignalName => "PIPETXELECIDLEL1", + OutTemp => PIPETXELECIDLEL1_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDETECTRXLOOPBACKL1, + GlitchData => PIPETXDETECTRXLOOPBACKL1_GlitchData, + OutSignalName => "PIPETXDETECTRXLOOPBACKL1", + OutTemp => PIPETXDETECTRXLOOPBACKL1_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXCOMPLIANCEL1, + GlitchData => PIPETXCOMPLIANCEL1_GlitchData, + OutSignalName => "PIPETXCOMPLIANCEL1", + OutTemp => PIPETXCOMPLIANCEL1_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERXPOLARITYL1, + GlitchData => PIPERXPOLARITYL1_GlitchData, + OutSignalName => "PIPERXPOLARITYL1", + OutTemp => PIPERXPOLARITYL1_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL1(0), + GlitchData => PIPEPOWERDOWNL10_GlitchData, + OutSignalName => "PIPEPOWERDOWNL1(0)", + OutTemp => PIPEPOWERDOWNL1_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL1(0), + GlitchData => PIPEPOWERDOWNL10_GlitchData, + OutSignalName => "PIPEPOWERDOWNL1(0)", + OutTemp => PIPEPOWERDOWNL1_OUT(0), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL1(1), + GlitchData => PIPEPOWERDOWNL11_GlitchData, + OutSignalName => "PIPEPOWERDOWNL1(1)", + OutTemp => PIPEPOWERDOWNL1_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL1(1), + GlitchData => PIPEPOWERDOWNL11_GlitchData, + OutSignalName => "PIPEPOWERDOWNL1(1)", + OutTemp => PIPEPOWERDOWNL1_OUT(1), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEDESKEWLANESL1, + GlitchData => PIPEDESKEWLANESL1_GlitchData, + OutSignalName => "PIPEDESKEWLANESL1", + OutTemp => PIPEDESKEWLANESL1_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERESETL1, + GlitchData => PIPERESETL1_GlitchData, + OutSignalName => "PIPERESETL1", + OutTemp => PIPERESETL1_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL2(0), + GlitchData => PIPETXDATAL20_GlitchData, + OutSignalName => "PIPETXDATAL2(0)", + OutTemp => PIPETXDATAL2_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL2(1), + GlitchData => PIPETXDATAL21_GlitchData, + OutSignalName => "PIPETXDATAL2(1)", + OutTemp => PIPETXDATAL2_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL2(2), + GlitchData => PIPETXDATAL22_GlitchData, + OutSignalName => "PIPETXDATAL2(2)", + OutTemp => PIPETXDATAL2_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL2(3), + GlitchData => PIPETXDATAL23_GlitchData, + OutSignalName => "PIPETXDATAL2(3)", + OutTemp => PIPETXDATAL2_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL2(4), + GlitchData => PIPETXDATAL24_GlitchData, + OutSignalName => "PIPETXDATAL2(4)", + OutTemp => PIPETXDATAL2_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL2(5), + GlitchData => PIPETXDATAL25_GlitchData, + OutSignalName => "PIPETXDATAL2(5)", + OutTemp => PIPETXDATAL2_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL2(6), + GlitchData => PIPETXDATAL26_GlitchData, + OutSignalName => "PIPETXDATAL2(6)", + OutTemp => PIPETXDATAL2_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL2(7), + GlitchData => PIPETXDATAL27_GlitchData, + OutSignalName => "PIPETXDATAL2(7)", + OutTemp => PIPETXDATAL2_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAKL2, + GlitchData => PIPETXDATAKL2_GlitchData, + OutSignalName => "PIPETXDATAKL2", + OutTemp => PIPETXDATAKL2_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXELECIDLEL2, + GlitchData => PIPETXELECIDLEL2_GlitchData, + OutSignalName => "PIPETXELECIDLEL2", + OutTemp => PIPETXELECIDLEL2_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDETECTRXLOOPBACKL2, + GlitchData => PIPETXDETECTRXLOOPBACKL2_GlitchData, + OutSignalName => "PIPETXDETECTRXLOOPBACKL2", + OutTemp => PIPETXDETECTRXLOOPBACKL2_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXCOMPLIANCEL2, + GlitchData => PIPETXCOMPLIANCEL2_GlitchData, + OutSignalName => "PIPETXCOMPLIANCEL2", + OutTemp => PIPETXCOMPLIANCEL2_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERXPOLARITYL2, + GlitchData => PIPERXPOLARITYL2_GlitchData, + OutSignalName => "PIPERXPOLARITYL2", + OutTemp => PIPERXPOLARITYL2_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL2(0), + GlitchData => PIPEPOWERDOWNL20_GlitchData, + OutSignalName => "PIPEPOWERDOWNL2(0)", + OutTemp => PIPEPOWERDOWNL2_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL2(0), + GlitchData => PIPEPOWERDOWNL20_GlitchData, + OutSignalName => "PIPEPOWERDOWNL2(0)", + OutTemp => PIPEPOWERDOWNL2_OUT(0), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL2(1), + GlitchData => PIPEPOWERDOWNL21_GlitchData, + OutSignalName => "PIPEPOWERDOWNL2(1)", + OutTemp => PIPEPOWERDOWNL2_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL2(1), + GlitchData => PIPEPOWERDOWNL21_GlitchData, + OutSignalName => "PIPEPOWERDOWNL2(1)", + OutTemp => PIPEPOWERDOWNL2_OUT(1), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEDESKEWLANESL2, + GlitchData => PIPEDESKEWLANESL2_GlitchData, + OutSignalName => "PIPEDESKEWLANESL2", + OutTemp => PIPEDESKEWLANESL2_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERESETL2, + GlitchData => PIPERESETL2_GlitchData, + OutSignalName => "PIPERESETL2", + OutTemp => PIPERESETL2_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL3(0), + GlitchData => PIPETXDATAL30_GlitchData, + OutSignalName => "PIPETXDATAL3(0)", + OutTemp => PIPETXDATAL3_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL3(1), + GlitchData => PIPETXDATAL31_GlitchData, + OutSignalName => "PIPETXDATAL3(1)", + OutTemp => PIPETXDATAL3_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL3(2), + GlitchData => PIPETXDATAL32_GlitchData, + OutSignalName => "PIPETXDATAL3(2)", + OutTemp => PIPETXDATAL3_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL3(3), + GlitchData => PIPETXDATAL33_GlitchData, + OutSignalName => "PIPETXDATAL3(3)", + OutTemp => PIPETXDATAL3_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL3(4), + GlitchData => PIPETXDATAL34_GlitchData, + OutSignalName => "PIPETXDATAL3(4)", + OutTemp => PIPETXDATAL3_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL3(5), + GlitchData => PIPETXDATAL35_GlitchData, + OutSignalName => "PIPETXDATAL3(5)", + OutTemp => PIPETXDATAL3_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL3(6), + GlitchData => PIPETXDATAL36_GlitchData, + OutSignalName => "PIPETXDATAL3(6)", + OutTemp => PIPETXDATAL3_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL3(7), + GlitchData => PIPETXDATAL37_GlitchData, + OutSignalName => "PIPETXDATAL3(7)", + OutTemp => PIPETXDATAL3_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAKL3, + GlitchData => PIPETXDATAKL3_GlitchData, + OutSignalName => "PIPETXDATAKL3", + OutTemp => PIPETXDATAKL3_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXELECIDLEL3, + GlitchData => PIPETXELECIDLEL3_GlitchData, + OutSignalName => "PIPETXELECIDLEL3", + OutTemp => PIPETXELECIDLEL3_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDETECTRXLOOPBACKL3, + GlitchData => PIPETXDETECTRXLOOPBACKL3_GlitchData, + OutSignalName => "PIPETXDETECTRXLOOPBACKL3", + OutTemp => PIPETXDETECTRXLOOPBACKL3_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXCOMPLIANCEL3, + GlitchData => PIPETXCOMPLIANCEL3_GlitchData, + OutSignalName => "PIPETXCOMPLIANCEL3", + OutTemp => PIPETXCOMPLIANCEL3_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERXPOLARITYL3, + GlitchData => PIPERXPOLARITYL3_GlitchData, + OutSignalName => "PIPERXPOLARITYL3", + OutTemp => PIPERXPOLARITYL3_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL3(0), + GlitchData => PIPEPOWERDOWNL30_GlitchData, + OutSignalName => "PIPEPOWERDOWNL3(0)", + OutTemp => PIPEPOWERDOWNL3_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL3(0), + GlitchData => PIPEPOWERDOWNL30_GlitchData, + OutSignalName => "PIPEPOWERDOWNL3(0)", + OutTemp => PIPEPOWERDOWNL3_OUT(0), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL3(1), + GlitchData => PIPEPOWERDOWNL31_GlitchData, + OutSignalName => "PIPEPOWERDOWNL3(1)", + OutTemp => PIPEPOWERDOWNL3_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL3(1), + GlitchData => PIPEPOWERDOWNL31_GlitchData, + OutSignalName => "PIPEPOWERDOWNL3(1)", + OutTemp => PIPEPOWERDOWNL3_OUT(1), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEDESKEWLANESL3, + GlitchData => PIPEDESKEWLANESL3_GlitchData, + OutSignalName => "PIPEDESKEWLANESL3", + OutTemp => PIPEDESKEWLANESL3_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERESETL3, + GlitchData => PIPERESETL3_GlitchData, + OutSignalName => "PIPERESETL3", + OutTemp => PIPERESETL3_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL4(0), + GlitchData => PIPETXDATAL40_GlitchData, + OutSignalName => "PIPETXDATAL4(0)", + OutTemp => PIPETXDATAL4_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL4(1), + GlitchData => PIPETXDATAL41_GlitchData, + OutSignalName => "PIPETXDATAL4(1)", + OutTemp => PIPETXDATAL4_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL4(2), + GlitchData => PIPETXDATAL42_GlitchData, + OutSignalName => "PIPETXDATAL4(2)", + OutTemp => PIPETXDATAL4_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL4(3), + GlitchData => PIPETXDATAL43_GlitchData, + OutSignalName => "PIPETXDATAL4(3)", + OutTemp => PIPETXDATAL4_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL4(4), + GlitchData => PIPETXDATAL44_GlitchData, + OutSignalName => "PIPETXDATAL4(4)", + OutTemp => PIPETXDATAL4_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL4(5), + GlitchData => PIPETXDATAL45_GlitchData, + OutSignalName => "PIPETXDATAL4(5)", + OutTemp => PIPETXDATAL4_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL4(6), + GlitchData => PIPETXDATAL46_GlitchData, + OutSignalName => "PIPETXDATAL4(6)", + OutTemp => PIPETXDATAL4_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL4(7), + GlitchData => PIPETXDATAL47_GlitchData, + OutSignalName => "PIPETXDATAL4(7)", + OutTemp => PIPETXDATAL4_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAKL4, + GlitchData => PIPETXDATAKL4_GlitchData, + OutSignalName => "PIPETXDATAKL4", + OutTemp => PIPETXDATAKL4_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXELECIDLEL4, + GlitchData => PIPETXELECIDLEL4_GlitchData, + OutSignalName => "PIPETXELECIDLEL4", + OutTemp => PIPETXELECIDLEL4_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDETECTRXLOOPBACKL4, + GlitchData => PIPETXDETECTRXLOOPBACKL4_GlitchData, + OutSignalName => "PIPETXDETECTRXLOOPBACKL4", + OutTemp => PIPETXDETECTRXLOOPBACKL4_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXCOMPLIANCEL4, + GlitchData => PIPETXCOMPLIANCEL4_GlitchData, + OutSignalName => "PIPETXCOMPLIANCEL4", + OutTemp => PIPETXCOMPLIANCEL4_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERXPOLARITYL4, + GlitchData => PIPERXPOLARITYL4_GlitchData, + OutSignalName => "PIPERXPOLARITYL4", + OutTemp => PIPERXPOLARITYL4_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL4(0), + GlitchData => PIPEPOWERDOWNL40_GlitchData, + OutSignalName => "PIPEPOWERDOWNL4(0)", + OutTemp => PIPEPOWERDOWNL4_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL4(0), + GlitchData => PIPEPOWERDOWNL40_GlitchData, + OutSignalName => "PIPEPOWERDOWNL4(0)", + OutTemp => PIPEPOWERDOWNL4_OUT(0), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL4(1), + GlitchData => PIPEPOWERDOWNL41_GlitchData, + OutSignalName => "PIPEPOWERDOWNL4(1)", + OutTemp => PIPEPOWERDOWNL4_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL4(1), + GlitchData => PIPEPOWERDOWNL41_GlitchData, + OutSignalName => "PIPEPOWERDOWNL4(1)", + OutTemp => PIPEPOWERDOWNL4_OUT(1), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEDESKEWLANESL4, + GlitchData => PIPEDESKEWLANESL4_GlitchData, + OutSignalName => "PIPEDESKEWLANESL4", + OutTemp => PIPEDESKEWLANESL4_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERESETL4, + GlitchData => PIPERESETL4_GlitchData, + OutSignalName => "PIPERESETL4", + OutTemp => PIPERESETL4_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL5(0), + GlitchData => PIPETXDATAL50_GlitchData, + OutSignalName => "PIPETXDATAL5(0)", + OutTemp => PIPETXDATAL5_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL5(1), + GlitchData => PIPETXDATAL51_GlitchData, + OutSignalName => "PIPETXDATAL5(1)", + OutTemp => PIPETXDATAL5_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL5(2), + GlitchData => PIPETXDATAL52_GlitchData, + OutSignalName => "PIPETXDATAL5(2)", + OutTemp => PIPETXDATAL5_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL5(3), + GlitchData => PIPETXDATAL53_GlitchData, + OutSignalName => "PIPETXDATAL5(3)", + OutTemp => PIPETXDATAL5_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL5(4), + GlitchData => PIPETXDATAL54_GlitchData, + OutSignalName => "PIPETXDATAL5(4)", + OutTemp => PIPETXDATAL5_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL5(5), + GlitchData => PIPETXDATAL55_GlitchData, + OutSignalName => "PIPETXDATAL5(5)", + OutTemp => PIPETXDATAL5_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL5(6), + GlitchData => PIPETXDATAL56_GlitchData, + OutSignalName => "PIPETXDATAL5(6)", + OutTemp => PIPETXDATAL5_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL5(7), + GlitchData => PIPETXDATAL57_GlitchData, + OutSignalName => "PIPETXDATAL5(7)", + OutTemp => PIPETXDATAL5_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAKL5, + GlitchData => PIPETXDATAKL5_GlitchData, + OutSignalName => "PIPETXDATAKL5", + OutTemp => PIPETXDATAKL5_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXELECIDLEL5, + GlitchData => PIPETXELECIDLEL5_GlitchData, + OutSignalName => "PIPETXELECIDLEL5", + OutTemp => PIPETXELECIDLEL5_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDETECTRXLOOPBACKL5, + GlitchData => PIPETXDETECTRXLOOPBACKL5_GlitchData, + OutSignalName => "PIPETXDETECTRXLOOPBACKL5", + OutTemp => PIPETXDETECTRXLOOPBACKL5_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXCOMPLIANCEL5, + GlitchData => PIPETXCOMPLIANCEL5_GlitchData, + OutSignalName => "PIPETXCOMPLIANCEL5", + OutTemp => PIPETXCOMPLIANCEL5_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERXPOLARITYL5, + GlitchData => PIPERXPOLARITYL5_GlitchData, + OutSignalName => "PIPERXPOLARITYL5", + OutTemp => PIPERXPOLARITYL5_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL5(0), + GlitchData => PIPEPOWERDOWNL50_GlitchData, + OutSignalName => "PIPEPOWERDOWNL5(0)", + OutTemp => PIPEPOWERDOWNL5_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL5(0), + GlitchData => PIPEPOWERDOWNL50_GlitchData, + OutSignalName => "PIPEPOWERDOWNL5(0)", + OutTemp => PIPEPOWERDOWNL5_OUT(0), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL5(1), + GlitchData => PIPEPOWERDOWNL51_GlitchData, + OutSignalName => "PIPEPOWERDOWNL5(1)", + OutTemp => PIPEPOWERDOWNL5_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL5(1), + GlitchData => PIPEPOWERDOWNL51_GlitchData, + OutSignalName => "PIPEPOWERDOWNL5(1)", + OutTemp => PIPEPOWERDOWNL5_OUT(1), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEDESKEWLANESL5, + GlitchData => PIPEDESKEWLANESL5_GlitchData, + OutSignalName => "PIPEDESKEWLANESL5", + OutTemp => PIPEDESKEWLANESL5_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERESETL5, + GlitchData => PIPERESETL5_GlitchData, + OutSignalName => "PIPERESETL5", + OutTemp => PIPERESETL5_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL6(0), + GlitchData => PIPETXDATAL60_GlitchData, + OutSignalName => "PIPETXDATAL6(0)", + OutTemp => PIPETXDATAL6_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL6(1), + GlitchData => PIPETXDATAL61_GlitchData, + OutSignalName => "PIPETXDATAL6(1)", + OutTemp => PIPETXDATAL6_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL6(2), + GlitchData => PIPETXDATAL62_GlitchData, + OutSignalName => "PIPETXDATAL6(2)", + OutTemp => PIPETXDATAL6_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL6(3), + GlitchData => PIPETXDATAL63_GlitchData, + OutSignalName => "PIPETXDATAL6(3)", + OutTemp => PIPETXDATAL6_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL6(4), + GlitchData => PIPETXDATAL64_GlitchData, + OutSignalName => "PIPETXDATAL6(4)", + OutTemp => PIPETXDATAL6_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL6(5), + GlitchData => PIPETXDATAL65_GlitchData, + OutSignalName => "PIPETXDATAL6(5)", + OutTemp => PIPETXDATAL6_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL6(6), + GlitchData => PIPETXDATAL66_GlitchData, + OutSignalName => "PIPETXDATAL6(6)", + OutTemp => PIPETXDATAL6_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL6(7), + GlitchData => PIPETXDATAL67_GlitchData, + OutSignalName => "PIPETXDATAL6(7)", + OutTemp => PIPETXDATAL6_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAKL6, + GlitchData => PIPETXDATAKL6_GlitchData, + OutSignalName => "PIPETXDATAKL6", + OutTemp => PIPETXDATAKL6_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXELECIDLEL6, + GlitchData => PIPETXELECIDLEL6_GlitchData, + OutSignalName => "PIPETXELECIDLEL6", + OutTemp => PIPETXELECIDLEL6_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDETECTRXLOOPBACKL6, + GlitchData => PIPETXDETECTRXLOOPBACKL6_GlitchData, + OutSignalName => "PIPETXDETECTRXLOOPBACKL6", + OutTemp => PIPETXDETECTRXLOOPBACKL6_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXCOMPLIANCEL6, + GlitchData => PIPETXCOMPLIANCEL6_GlitchData, + OutSignalName => "PIPETXCOMPLIANCEL6", + OutTemp => PIPETXCOMPLIANCEL6_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERXPOLARITYL6, + GlitchData => PIPERXPOLARITYL6_GlitchData, + OutSignalName => "PIPERXPOLARITYL6", + OutTemp => PIPERXPOLARITYL6_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL6(0), + GlitchData => PIPEPOWERDOWNL60_GlitchData, + OutSignalName => "PIPEPOWERDOWNL6(0)", + OutTemp => PIPEPOWERDOWNL6_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL6(0), + GlitchData => PIPEPOWERDOWNL60_GlitchData, + OutSignalName => "PIPEPOWERDOWNL6(0)", + OutTemp => PIPEPOWERDOWNL6_OUT(0), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL6(1), + GlitchData => PIPEPOWERDOWNL61_GlitchData, + OutSignalName => "PIPEPOWERDOWNL6(1)", + OutTemp => PIPEPOWERDOWNL6_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL6(1), + GlitchData => PIPEPOWERDOWNL61_GlitchData, + OutSignalName => "PIPEPOWERDOWNL6(1)", + OutTemp => PIPEPOWERDOWNL6_OUT(1), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEDESKEWLANESL6, + GlitchData => PIPEDESKEWLANESL6_GlitchData, + OutSignalName => "PIPEDESKEWLANESL6", + OutTemp => PIPEDESKEWLANESL6_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERESETL6, + GlitchData => PIPERESETL6_GlitchData, + OutSignalName => "PIPERESETL6", + OutTemp => PIPERESETL6_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL7(0), + GlitchData => PIPETXDATAL70_GlitchData, + OutSignalName => "PIPETXDATAL7(0)", + OutTemp => PIPETXDATAL7_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL7(1), + GlitchData => PIPETXDATAL71_GlitchData, + OutSignalName => "PIPETXDATAL7(1)", + OutTemp => PIPETXDATAL7_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL7(2), + GlitchData => PIPETXDATAL72_GlitchData, + OutSignalName => "PIPETXDATAL7(2)", + OutTemp => PIPETXDATAL7_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL7(3), + GlitchData => PIPETXDATAL73_GlitchData, + OutSignalName => "PIPETXDATAL7(3)", + OutTemp => PIPETXDATAL7_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL7(4), + GlitchData => PIPETXDATAL74_GlitchData, + OutSignalName => "PIPETXDATAL7(4)", + OutTemp => PIPETXDATAL7_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL7(5), + GlitchData => PIPETXDATAL75_GlitchData, + OutSignalName => "PIPETXDATAL7(5)", + OutTemp => PIPETXDATAL7_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL7(6), + GlitchData => PIPETXDATAL76_GlitchData, + OutSignalName => "PIPETXDATAL7(6)", + OutTemp => PIPETXDATAL7_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL7(7), + GlitchData => PIPETXDATAL77_GlitchData, + OutSignalName => "PIPETXDATAL7(7)", + OutTemp => PIPETXDATAL7_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAKL7, + GlitchData => PIPETXDATAKL7_GlitchData, + OutSignalName => "PIPETXDATAKL7", + OutTemp => PIPETXDATAKL7_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXELECIDLEL7, + GlitchData => PIPETXELECIDLEL7_GlitchData, + OutSignalName => "PIPETXELECIDLEL7", + OutTemp => PIPETXELECIDLEL7_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDETECTRXLOOPBACKL7, + GlitchData => PIPETXDETECTRXLOOPBACKL7_GlitchData, + OutSignalName => "PIPETXDETECTRXLOOPBACKL7", + OutTemp => PIPETXDETECTRXLOOPBACKL7_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXCOMPLIANCEL7, + GlitchData => PIPETXCOMPLIANCEL7_GlitchData, + OutSignalName => "PIPETXCOMPLIANCEL7", + OutTemp => PIPETXCOMPLIANCEL7_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERXPOLARITYL7, + GlitchData => PIPERXPOLARITYL7_GlitchData, + OutSignalName => "PIPERXPOLARITYL7", + OutTemp => PIPERXPOLARITYL7_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL7(0), + GlitchData => PIPEPOWERDOWNL70_GlitchData, + OutSignalName => "PIPEPOWERDOWNL7(0)", + OutTemp => PIPEPOWERDOWNL7_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL7(0), + GlitchData => PIPEPOWERDOWNL70_GlitchData, + OutSignalName => "PIPEPOWERDOWNL7(0)", + OutTemp => PIPEPOWERDOWNL7_OUT(0), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL7(1), + GlitchData => PIPEPOWERDOWNL71_GlitchData, + OutSignalName => "PIPEPOWERDOWNL7(1)", + OutTemp => PIPEPOWERDOWNL7_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL7(1), + GlitchData => PIPEPOWERDOWNL71_GlitchData, + OutSignalName => "PIPEPOWERDOWNL7(1)", + OutTemp => PIPEPOWERDOWNL7_OUT(1), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEDESKEWLANESL7, + GlitchData => PIPEDESKEWLANESL7_GlitchData, + OutSignalName => "PIPEDESKEWLANESL7", + OutTemp => PIPEDESKEWLANESL7_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERESETL7, + GlitchData => PIPERESETL7_GlitchData, + OutSignalName => "PIPERESETL7", + OutTemp => PIPERESETL7_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(0), + GlitchData => MIMRXBWDATA0_GlitchData, + OutSignalName => "MIMRXBWDATA(0)", + OutTemp => MIMRXBWDATA_OUT(0), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(1), + GlitchData => MIMRXBWDATA1_GlitchData, + OutSignalName => "MIMRXBWDATA(1)", + OutTemp => MIMRXBWDATA_OUT(1), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(2), + GlitchData => MIMRXBWDATA2_GlitchData, + OutSignalName => "MIMRXBWDATA(2)", + OutTemp => MIMRXBWDATA_OUT(2), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(3), + GlitchData => MIMRXBWDATA3_GlitchData, + OutSignalName => "MIMRXBWDATA(3)", + OutTemp => MIMRXBWDATA_OUT(3), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(4), + GlitchData => MIMRXBWDATA4_GlitchData, + OutSignalName => "MIMRXBWDATA(4)", + OutTemp => MIMRXBWDATA_OUT(4), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(5), + GlitchData => MIMRXBWDATA5_GlitchData, + OutSignalName => "MIMRXBWDATA(5)", + OutTemp => MIMRXBWDATA_OUT(5), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(6), + GlitchData => MIMRXBWDATA6_GlitchData, + OutSignalName => "MIMRXBWDATA(6)", + OutTemp => MIMRXBWDATA_OUT(6), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(7), + GlitchData => MIMRXBWDATA7_GlitchData, + OutSignalName => "MIMRXBWDATA(7)", + OutTemp => MIMRXBWDATA_OUT(7), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(8), + GlitchData => MIMRXBWDATA8_GlitchData, + OutSignalName => "MIMRXBWDATA(8)", + OutTemp => MIMRXBWDATA_OUT(8), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(9), + GlitchData => MIMRXBWDATA9_GlitchData, + OutSignalName => "MIMRXBWDATA(9)", + OutTemp => MIMRXBWDATA_OUT(9), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(10), + GlitchData => MIMRXBWDATA10_GlitchData, + OutSignalName => "MIMRXBWDATA(10)", + OutTemp => MIMRXBWDATA_OUT(10), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(11), + GlitchData => MIMRXBWDATA11_GlitchData, + OutSignalName => "MIMRXBWDATA(11)", + OutTemp => MIMRXBWDATA_OUT(11), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(12), + GlitchData => MIMRXBWDATA12_GlitchData, + OutSignalName => "MIMRXBWDATA(12)", + OutTemp => MIMRXBWDATA_OUT(12), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(13), + GlitchData => MIMRXBWDATA13_GlitchData, + OutSignalName => "MIMRXBWDATA(13)", + OutTemp => MIMRXBWDATA_OUT(13), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(14), + GlitchData => MIMRXBWDATA14_GlitchData, + OutSignalName => "MIMRXBWDATA(14)", + OutTemp => MIMRXBWDATA_OUT(14), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(15), + GlitchData => MIMRXBWDATA15_GlitchData, + OutSignalName => "MIMRXBWDATA(15)", + OutTemp => MIMRXBWDATA_OUT(15), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(16), + GlitchData => MIMRXBWDATA16_GlitchData, + OutSignalName => "MIMRXBWDATA(16)", + OutTemp => MIMRXBWDATA_OUT(16), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(17), + GlitchData => MIMRXBWDATA17_GlitchData, + OutSignalName => "MIMRXBWDATA(17)", + OutTemp => MIMRXBWDATA_OUT(17), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(18), + GlitchData => MIMRXBWDATA18_GlitchData, + OutSignalName => "MIMRXBWDATA(18)", + OutTemp => MIMRXBWDATA_OUT(18), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(19), + GlitchData => MIMRXBWDATA19_GlitchData, + OutSignalName => "MIMRXBWDATA(19)", + OutTemp => MIMRXBWDATA_OUT(19), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(20), + GlitchData => MIMRXBWDATA20_GlitchData, + OutSignalName => "MIMRXBWDATA(20)", + OutTemp => MIMRXBWDATA_OUT(20), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(21), + GlitchData => MIMRXBWDATA21_GlitchData, + OutSignalName => "MIMRXBWDATA(21)", + OutTemp => MIMRXBWDATA_OUT(21), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(22), + GlitchData => MIMRXBWDATA22_GlitchData, + OutSignalName => "MIMRXBWDATA(22)", + OutTemp => MIMRXBWDATA_OUT(22), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(23), + GlitchData => MIMRXBWDATA23_GlitchData, + OutSignalName => "MIMRXBWDATA(23)", + OutTemp => MIMRXBWDATA_OUT(23), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(24), + GlitchData => MIMRXBWDATA24_GlitchData, + OutSignalName => "MIMRXBWDATA(24)", + OutTemp => MIMRXBWDATA_OUT(24), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(25), + GlitchData => MIMRXBWDATA25_GlitchData, + OutSignalName => "MIMRXBWDATA(25)", + OutTemp => MIMRXBWDATA_OUT(25), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(26), + GlitchData => MIMRXBWDATA26_GlitchData, + OutSignalName => "MIMRXBWDATA(26)", + OutTemp => MIMRXBWDATA_OUT(26), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(27), + GlitchData => MIMRXBWDATA27_GlitchData, + OutSignalName => "MIMRXBWDATA(27)", + OutTemp => MIMRXBWDATA_OUT(27), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(28), + GlitchData => MIMRXBWDATA28_GlitchData, + OutSignalName => "MIMRXBWDATA(28)", + OutTemp => MIMRXBWDATA_OUT(28), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(29), + GlitchData => MIMRXBWDATA29_GlitchData, + OutSignalName => "MIMRXBWDATA(29)", + OutTemp => MIMRXBWDATA_OUT(29), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(30), + GlitchData => MIMRXBWDATA30_GlitchData, + OutSignalName => "MIMRXBWDATA(30)", + OutTemp => MIMRXBWDATA_OUT(30), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(31), + GlitchData => MIMRXBWDATA31_GlitchData, + OutSignalName => "MIMRXBWDATA(31)", + OutTemp => MIMRXBWDATA_OUT(31), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(32), + GlitchData => MIMRXBWDATA32_GlitchData, + OutSignalName => "MIMRXBWDATA(32)", + OutTemp => MIMRXBWDATA_OUT(32), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(33), + GlitchData => MIMRXBWDATA33_GlitchData, + OutSignalName => "MIMRXBWDATA(33)", + OutTemp => MIMRXBWDATA_OUT(33), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(34), + GlitchData => MIMRXBWDATA34_GlitchData, + OutSignalName => "MIMRXBWDATA(34)", + OutTemp => MIMRXBWDATA_OUT(34), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(35), + GlitchData => MIMRXBWDATA35_GlitchData, + OutSignalName => "MIMRXBWDATA(35)", + OutTemp => MIMRXBWDATA_OUT(35), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(36), + GlitchData => MIMRXBWDATA36_GlitchData, + OutSignalName => "MIMRXBWDATA(36)", + OutTemp => MIMRXBWDATA_OUT(36), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(37), + GlitchData => MIMRXBWDATA37_GlitchData, + OutSignalName => "MIMRXBWDATA(37)", + OutTemp => MIMRXBWDATA_OUT(37), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(38), + GlitchData => MIMRXBWDATA38_GlitchData, + OutSignalName => "MIMRXBWDATA(38)", + OutTemp => MIMRXBWDATA_OUT(38), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(39), + GlitchData => MIMRXBWDATA39_GlitchData, + OutSignalName => "MIMRXBWDATA(39)", + OutTemp => MIMRXBWDATA_OUT(39), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(40), + GlitchData => MIMRXBWDATA40_GlitchData, + OutSignalName => "MIMRXBWDATA(40)", + OutTemp => MIMRXBWDATA_OUT(40), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(41), + GlitchData => MIMRXBWDATA41_GlitchData, + OutSignalName => "MIMRXBWDATA(41)", + OutTemp => MIMRXBWDATA_OUT(41), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(42), + GlitchData => MIMRXBWDATA42_GlitchData, + OutSignalName => "MIMRXBWDATA(42)", + OutTemp => MIMRXBWDATA_OUT(42), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(43), + GlitchData => MIMRXBWDATA43_GlitchData, + OutSignalName => "MIMRXBWDATA(43)", + OutTemp => MIMRXBWDATA_OUT(43), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(44), + GlitchData => MIMRXBWDATA44_GlitchData, + OutSignalName => "MIMRXBWDATA(44)", + OutTemp => MIMRXBWDATA_OUT(44), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(45), + GlitchData => MIMRXBWDATA45_GlitchData, + OutSignalName => "MIMRXBWDATA(45)", + OutTemp => MIMRXBWDATA_OUT(45), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(46), + GlitchData => MIMRXBWDATA46_GlitchData, + OutSignalName => "MIMRXBWDATA(46)", + OutTemp => MIMRXBWDATA_OUT(46), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(47), + GlitchData => MIMRXBWDATA47_GlitchData, + OutSignalName => "MIMRXBWDATA(47)", + OutTemp => MIMRXBWDATA_OUT(47), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(48), + GlitchData => MIMRXBWDATA48_GlitchData, + OutSignalName => "MIMRXBWDATA(48)", + OutTemp => MIMRXBWDATA_OUT(48), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(49), + GlitchData => MIMRXBWDATA49_GlitchData, + OutSignalName => "MIMRXBWDATA(49)", + OutTemp => MIMRXBWDATA_OUT(49), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(50), + GlitchData => MIMRXBWDATA50_GlitchData, + OutSignalName => "MIMRXBWDATA(50)", + OutTemp => MIMRXBWDATA_OUT(50), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(51), + GlitchData => MIMRXBWDATA51_GlitchData, + OutSignalName => "MIMRXBWDATA(51)", + OutTemp => MIMRXBWDATA_OUT(51), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(52), + GlitchData => MIMRXBWDATA52_GlitchData, + OutSignalName => "MIMRXBWDATA(52)", + OutTemp => MIMRXBWDATA_OUT(52), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(53), + GlitchData => MIMRXBWDATA53_GlitchData, + OutSignalName => "MIMRXBWDATA(53)", + OutTemp => MIMRXBWDATA_OUT(53), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(54), + GlitchData => MIMRXBWDATA54_GlitchData, + OutSignalName => "MIMRXBWDATA(54)", + OutTemp => MIMRXBWDATA_OUT(54), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(55), + GlitchData => MIMRXBWDATA55_GlitchData, + OutSignalName => "MIMRXBWDATA(55)", + OutTemp => MIMRXBWDATA_OUT(55), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(56), + GlitchData => MIMRXBWDATA56_GlitchData, + OutSignalName => "MIMRXBWDATA(56)", + OutTemp => MIMRXBWDATA_OUT(56), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(57), + GlitchData => MIMRXBWDATA57_GlitchData, + OutSignalName => "MIMRXBWDATA(57)", + OutTemp => MIMRXBWDATA_OUT(57), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(58), + GlitchData => MIMRXBWDATA58_GlitchData, + OutSignalName => "MIMRXBWDATA(58)", + OutTemp => MIMRXBWDATA_OUT(58), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(59), + GlitchData => MIMRXBWDATA59_GlitchData, + OutSignalName => "MIMRXBWDATA(59)", + OutTemp => MIMRXBWDATA_OUT(59), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(60), + GlitchData => MIMRXBWDATA60_GlitchData, + OutSignalName => "MIMRXBWDATA(60)", + OutTemp => MIMRXBWDATA_OUT(60), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(61), + GlitchData => MIMRXBWDATA61_GlitchData, + OutSignalName => "MIMRXBWDATA(61)", + OutTemp => MIMRXBWDATA_OUT(61), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(62), + GlitchData => MIMRXBWDATA62_GlitchData, + OutSignalName => "MIMRXBWDATA(62)", + OutTemp => MIMRXBWDATA_OUT(62), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(63), + GlitchData => MIMRXBWDATA63_GlitchData, + OutSignalName => "MIMRXBWDATA(63)", + OutTemp => MIMRXBWDATA_OUT(63), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(0), + GlitchData => MIMRXBWADD0_GlitchData, + OutSignalName => "MIMRXBWADD(0)", + OutTemp => MIMRXBWADD_OUT(0), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(1), + GlitchData => MIMRXBWADD1_GlitchData, + OutSignalName => "MIMRXBWADD(1)", + OutTemp => MIMRXBWADD_OUT(1), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(2), + GlitchData => MIMRXBWADD2_GlitchData, + OutSignalName => "MIMRXBWADD(2)", + OutTemp => MIMRXBWADD_OUT(2), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(3), + GlitchData => MIMRXBWADD3_GlitchData, + OutSignalName => "MIMRXBWADD(3)", + OutTemp => MIMRXBWADD_OUT(3), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(4), + GlitchData => MIMRXBWADD4_GlitchData, + OutSignalName => "MIMRXBWADD(4)", + OutTemp => MIMRXBWADD_OUT(4), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(5), + GlitchData => MIMRXBWADD5_GlitchData, + OutSignalName => "MIMRXBWADD(5)", + OutTemp => MIMRXBWADD_OUT(5), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(6), + GlitchData => MIMRXBWADD6_GlitchData, + OutSignalName => "MIMRXBWADD(6)", + OutTemp => MIMRXBWADD_OUT(6), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(7), + GlitchData => MIMRXBWADD7_GlitchData, + OutSignalName => "MIMRXBWADD(7)", + OutTemp => MIMRXBWADD_OUT(7), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(8), + GlitchData => MIMRXBWADD8_GlitchData, + OutSignalName => "MIMRXBWADD(8)", + OutTemp => MIMRXBWADD_OUT(8), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(9), + GlitchData => MIMRXBWADD9_GlitchData, + OutSignalName => "MIMRXBWADD(9)", + OutTemp => MIMRXBWADD_OUT(9), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(10), + GlitchData => MIMRXBWADD10_GlitchData, + OutSignalName => "MIMRXBWADD(10)", + OutTemp => MIMRXBWADD_OUT(10), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(11), + GlitchData => MIMRXBWADD11_GlitchData, + OutSignalName => "MIMRXBWADD(11)", + OutTemp => MIMRXBWADD_OUT(11), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(12), + GlitchData => MIMRXBWADD12_GlitchData, + OutSignalName => "MIMRXBWADD(12)", + OutTemp => MIMRXBWADD_OUT(12), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(0), + GlitchData => MIMRXBRADD0_GlitchData, + OutSignalName => "MIMRXBRADD(0)", + OutTemp => MIMRXBRADD_OUT(0), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(0), + GlitchData => MIMRXBRADD0_GlitchData, + OutSignalName => "MIMRXBRADD(0)", + OutTemp => MIMRXBRADD_OUT(0), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(1), + GlitchData => MIMRXBRADD1_GlitchData, + OutSignalName => "MIMRXBRADD(1)", + OutTemp => MIMRXBRADD_OUT(1), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(1), + GlitchData => MIMRXBRADD1_GlitchData, + OutSignalName => "MIMRXBRADD(1)", + OutTemp => MIMRXBRADD_OUT(1), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(2), + GlitchData => MIMRXBRADD2_GlitchData, + OutSignalName => "MIMRXBRADD(2)", + OutTemp => MIMRXBRADD_OUT(2), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(2), + GlitchData => MIMRXBRADD2_GlitchData, + OutSignalName => "MIMRXBRADD(2)", + OutTemp => MIMRXBRADD_OUT(2), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(3), + GlitchData => MIMRXBRADD3_GlitchData, + OutSignalName => "MIMRXBRADD(3)", + OutTemp => MIMRXBRADD_OUT(3), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(3), + GlitchData => MIMRXBRADD3_GlitchData, + OutSignalName => "MIMRXBRADD(3)", + OutTemp => MIMRXBRADD_OUT(3), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(4), + GlitchData => MIMRXBRADD4_GlitchData, + OutSignalName => "MIMRXBRADD(4)", + OutTemp => MIMRXBRADD_OUT(4), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(4), + GlitchData => MIMRXBRADD4_GlitchData, + OutSignalName => "MIMRXBRADD(4)", + OutTemp => MIMRXBRADD_OUT(4), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(5), + GlitchData => MIMRXBRADD5_GlitchData, + OutSignalName => "MIMRXBRADD(5)", + OutTemp => MIMRXBRADD_OUT(5), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(5), + GlitchData => MIMRXBRADD5_GlitchData, + OutSignalName => "MIMRXBRADD(5)", + OutTemp => MIMRXBRADD_OUT(5), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(6), + GlitchData => MIMRXBRADD6_GlitchData, + OutSignalName => "MIMRXBRADD(6)", + OutTemp => MIMRXBRADD_OUT(6), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(6), + GlitchData => MIMRXBRADD6_GlitchData, + OutSignalName => "MIMRXBRADD(6)", + OutTemp => MIMRXBRADD_OUT(6), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(7), + GlitchData => MIMRXBRADD7_GlitchData, + OutSignalName => "MIMRXBRADD(7)", + OutTemp => MIMRXBRADD_OUT(7), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(7), + GlitchData => MIMRXBRADD7_GlitchData, + OutSignalName => "MIMRXBRADD(7)", + OutTemp => MIMRXBRADD_OUT(7), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(8), + GlitchData => MIMRXBRADD8_GlitchData, + OutSignalName => "MIMRXBRADD(8)", + OutTemp => MIMRXBRADD_OUT(8), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(8), + GlitchData => MIMRXBRADD8_GlitchData, + OutSignalName => "MIMRXBRADD(8)", + OutTemp => MIMRXBRADD_OUT(8), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(9), + GlitchData => MIMRXBRADD9_GlitchData, + OutSignalName => "MIMRXBRADD(9)", + OutTemp => MIMRXBRADD_OUT(9), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(9), + GlitchData => MIMRXBRADD9_GlitchData, + OutSignalName => "MIMRXBRADD(9)", + OutTemp => MIMRXBRADD_OUT(9), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(10), + GlitchData => MIMRXBRADD10_GlitchData, + OutSignalName => "MIMRXBRADD(10)", + OutTemp => MIMRXBRADD_OUT(10), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(10), + GlitchData => MIMRXBRADD10_GlitchData, + OutSignalName => "MIMRXBRADD(10)", + OutTemp => MIMRXBRADD_OUT(10), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(11), + GlitchData => MIMRXBRADD11_GlitchData, + OutSignalName => "MIMRXBRADD(11)", + OutTemp => MIMRXBRADD_OUT(11), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(11), + GlitchData => MIMRXBRADD11_GlitchData, + OutSignalName => "MIMRXBRADD(11)", + OutTemp => MIMRXBRADD_OUT(11), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(12), + GlitchData => MIMRXBRADD12_GlitchData, + OutSignalName => "MIMRXBRADD(12)", + OutTemp => MIMRXBRADD_OUT(12), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(12), + GlitchData => MIMRXBRADD12_GlitchData, + OutSignalName => "MIMRXBRADD(12)", + OutTemp => MIMRXBRADD_OUT(12), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWEN, + GlitchData => MIMRXBWEN_GlitchData, + OutSignalName => "MIMRXBWEN", + OutTemp => MIMRXBWEN_OUT, + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBREN, + GlitchData => MIMRXBREN_GlitchData, + OutSignalName => "MIMRXBREN", + OutTemp => MIMRXBREN_OUT, + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBREN, + GlitchData => MIMRXBREN_GlitchData, + OutSignalName => "MIMRXBREN", + OutTemp => MIMRXBREN_OUT, + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(0), + GlitchData => MIMTXBWDATA0_GlitchData, + OutSignalName => "MIMTXBWDATA(0)", + OutTemp => MIMTXBWDATA_OUT(0), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(0), + GlitchData => MIMTXBWDATA0_GlitchData, + OutSignalName => "MIMTXBWDATA(0)", + OutTemp => MIMTXBWDATA_OUT(0), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(1), + GlitchData => MIMTXBWDATA1_GlitchData, + OutSignalName => "MIMTXBWDATA(1)", + OutTemp => MIMTXBWDATA_OUT(1), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(1), + GlitchData => MIMTXBWDATA1_GlitchData, + OutSignalName => "MIMTXBWDATA(1)", + OutTemp => MIMTXBWDATA_OUT(1), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(2), + GlitchData => MIMTXBWDATA2_GlitchData, + OutSignalName => "MIMTXBWDATA(2)", + OutTemp => MIMTXBWDATA_OUT(2), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(2), + GlitchData => MIMTXBWDATA2_GlitchData, + OutSignalName => "MIMTXBWDATA(2)", + OutTemp => MIMTXBWDATA_OUT(2), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(3), + GlitchData => MIMTXBWDATA3_GlitchData, + OutSignalName => "MIMTXBWDATA(3)", + OutTemp => MIMTXBWDATA_OUT(3), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(3), + GlitchData => MIMTXBWDATA3_GlitchData, + OutSignalName => "MIMTXBWDATA(3)", + OutTemp => MIMTXBWDATA_OUT(3), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(4), + GlitchData => MIMTXBWDATA4_GlitchData, + OutSignalName => "MIMTXBWDATA(4)", + OutTemp => MIMTXBWDATA_OUT(4), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(4), + GlitchData => MIMTXBWDATA4_GlitchData, + OutSignalName => "MIMTXBWDATA(4)", + OutTemp => MIMTXBWDATA_OUT(4), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(5), + GlitchData => MIMTXBWDATA5_GlitchData, + OutSignalName => "MIMTXBWDATA(5)", + OutTemp => MIMTXBWDATA_OUT(5), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(5), + GlitchData => MIMTXBWDATA5_GlitchData, + OutSignalName => "MIMTXBWDATA(5)", + OutTemp => MIMTXBWDATA_OUT(5), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(6), + GlitchData => MIMTXBWDATA6_GlitchData, + OutSignalName => "MIMTXBWDATA(6)", + OutTemp => MIMTXBWDATA_OUT(6), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(6), + GlitchData => MIMTXBWDATA6_GlitchData, + OutSignalName => "MIMTXBWDATA(6)", + OutTemp => MIMTXBWDATA_OUT(6), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(7), + GlitchData => MIMTXBWDATA7_GlitchData, + OutSignalName => "MIMTXBWDATA(7)", + OutTemp => MIMTXBWDATA_OUT(7), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(7), + GlitchData => MIMTXBWDATA7_GlitchData, + OutSignalName => "MIMTXBWDATA(7)", + OutTemp => MIMTXBWDATA_OUT(7), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(8), + GlitchData => MIMTXBWDATA8_GlitchData, + OutSignalName => "MIMTXBWDATA(8)", + OutTemp => MIMTXBWDATA_OUT(8), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(8), + GlitchData => MIMTXBWDATA8_GlitchData, + OutSignalName => "MIMTXBWDATA(8)", + OutTemp => MIMTXBWDATA_OUT(8), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(9), + GlitchData => MIMTXBWDATA9_GlitchData, + OutSignalName => "MIMTXBWDATA(9)", + OutTemp => MIMTXBWDATA_OUT(9), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(9), + GlitchData => MIMTXBWDATA9_GlitchData, + OutSignalName => "MIMTXBWDATA(9)", + OutTemp => MIMTXBWDATA_OUT(9), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(10), + GlitchData => MIMTXBWDATA10_GlitchData, + OutSignalName => "MIMTXBWDATA(10)", + OutTemp => MIMTXBWDATA_OUT(10), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(10), + GlitchData => MIMTXBWDATA10_GlitchData, + OutSignalName => "MIMTXBWDATA(10)", + OutTemp => MIMTXBWDATA_OUT(10), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(11), + GlitchData => MIMTXBWDATA11_GlitchData, + OutSignalName => "MIMTXBWDATA(11)", + OutTemp => MIMTXBWDATA_OUT(11), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(11), + GlitchData => MIMTXBWDATA11_GlitchData, + OutSignalName => "MIMTXBWDATA(11)", + OutTemp => MIMTXBWDATA_OUT(11), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(12), + GlitchData => MIMTXBWDATA12_GlitchData, + OutSignalName => "MIMTXBWDATA(12)", + OutTemp => MIMTXBWDATA_OUT(12), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(12), + GlitchData => MIMTXBWDATA12_GlitchData, + OutSignalName => "MIMTXBWDATA(12)", + OutTemp => MIMTXBWDATA_OUT(12), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(13), + GlitchData => MIMTXBWDATA13_GlitchData, + OutSignalName => "MIMTXBWDATA(13)", + OutTemp => MIMTXBWDATA_OUT(13), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(13), + GlitchData => MIMTXBWDATA13_GlitchData, + OutSignalName => "MIMTXBWDATA(13)", + OutTemp => MIMTXBWDATA_OUT(13), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(14), + GlitchData => MIMTXBWDATA14_GlitchData, + OutSignalName => "MIMTXBWDATA(14)", + OutTemp => MIMTXBWDATA_OUT(14), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(14), + GlitchData => MIMTXBWDATA14_GlitchData, + OutSignalName => "MIMTXBWDATA(14)", + OutTemp => MIMTXBWDATA_OUT(14), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(15), + GlitchData => MIMTXBWDATA15_GlitchData, + OutSignalName => "MIMTXBWDATA(15)", + OutTemp => MIMTXBWDATA_OUT(15), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(15), + GlitchData => MIMTXBWDATA15_GlitchData, + OutSignalName => "MIMTXBWDATA(15)", + OutTemp => MIMTXBWDATA_OUT(15), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(16), + GlitchData => MIMTXBWDATA16_GlitchData, + OutSignalName => "MIMTXBWDATA(16)", + OutTemp => MIMTXBWDATA_OUT(16), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(16), + GlitchData => MIMTXBWDATA16_GlitchData, + OutSignalName => "MIMTXBWDATA(16)", + OutTemp => MIMTXBWDATA_OUT(16), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(17), + GlitchData => MIMTXBWDATA17_GlitchData, + OutSignalName => "MIMTXBWDATA(17)", + OutTemp => MIMTXBWDATA_OUT(17), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(17), + GlitchData => MIMTXBWDATA17_GlitchData, + OutSignalName => "MIMTXBWDATA(17)", + OutTemp => MIMTXBWDATA_OUT(17), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(18), + GlitchData => MIMTXBWDATA18_GlitchData, + OutSignalName => "MIMTXBWDATA(18)", + OutTemp => MIMTXBWDATA_OUT(18), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(18), + GlitchData => MIMTXBWDATA18_GlitchData, + OutSignalName => "MIMTXBWDATA(18)", + OutTemp => MIMTXBWDATA_OUT(18), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(19), + GlitchData => MIMTXBWDATA19_GlitchData, + OutSignalName => "MIMTXBWDATA(19)", + OutTemp => MIMTXBWDATA_OUT(19), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(19), + GlitchData => MIMTXBWDATA19_GlitchData, + OutSignalName => "MIMTXBWDATA(19)", + OutTemp => MIMTXBWDATA_OUT(19), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(20), + GlitchData => MIMTXBWDATA20_GlitchData, + OutSignalName => "MIMTXBWDATA(20)", + OutTemp => MIMTXBWDATA_OUT(20), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(20), + GlitchData => MIMTXBWDATA20_GlitchData, + OutSignalName => "MIMTXBWDATA(20)", + OutTemp => MIMTXBWDATA_OUT(20), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(21), + GlitchData => MIMTXBWDATA21_GlitchData, + OutSignalName => "MIMTXBWDATA(21)", + OutTemp => MIMTXBWDATA_OUT(21), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(21), + GlitchData => MIMTXBWDATA21_GlitchData, + OutSignalName => "MIMTXBWDATA(21)", + OutTemp => MIMTXBWDATA_OUT(21), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(22), + GlitchData => MIMTXBWDATA22_GlitchData, + OutSignalName => "MIMTXBWDATA(22)", + OutTemp => MIMTXBWDATA_OUT(22), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(22), + GlitchData => MIMTXBWDATA22_GlitchData, + OutSignalName => "MIMTXBWDATA(22)", + OutTemp => MIMTXBWDATA_OUT(22), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(23), + GlitchData => MIMTXBWDATA23_GlitchData, + OutSignalName => "MIMTXBWDATA(23)", + OutTemp => MIMTXBWDATA_OUT(23), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(23), + GlitchData => MIMTXBWDATA23_GlitchData, + OutSignalName => "MIMTXBWDATA(23)", + OutTemp => MIMTXBWDATA_OUT(23), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(24), + GlitchData => MIMTXBWDATA24_GlitchData, + OutSignalName => "MIMTXBWDATA(24)", + OutTemp => MIMTXBWDATA_OUT(24), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(24), + GlitchData => MIMTXBWDATA24_GlitchData, + OutSignalName => "MIMTXBWDATA(24)", + OutTemp => MIMTXBWDATA_OUT(24), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(25), + GlitchData => MIMTXBWDATA25_GlitchData, + OutSignalName => "MIMTXBWDATA(25)", + OutTemp => MIMTXBWDATA_OUT(25), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(25), + GlitchData => MIMTXBWDATA25_GlitchData, + OutSignalName => "MIMTXBWDATA(25)", + OutTemp => MIMTXBWDATA_OUT(25), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(26), + GlitchData => MIMTXBWDATA26_GlitchData, + OutSignalName => "MIMTXBWDATA(26)", + OutTemp => MIMTXBWDATA_OUT(26), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(26), + GlitchData => MIMTXBWDATA26_GlitchData, + OutSignalName => "MIMTXBWDATA(26)", + OutTemp => MIMTXBWDATA_OUT(26), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(27), + GlitchData => MIMTXBWDATA27_GlitchData, + OutSignalName => "MIMTXBWDATA(27)", + OutTemp => MIMTXBWDATA_OUT(27), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(27), + GlitchData => MIMTXBWDATA27_GlitchData, + OutSignalName => "MIMTXBWDATA(27)", + OutTemp => MIMTXBWDATA_OUT(27), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(28), + GlitchData => MIMTXBWDATA28_GlitchData, + OutSignalName => "MIMTXBWDATA(28)", + OutTemp => MIMTXBWDATA_OUT(28), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(28), + GlitchData => MIMTXBWDATA28_GlitchData, + OutSignalName => "MIMTXBWDATA(28)", + OutTemp => MIMTXBWDATA_OUT(28), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(29), + GlitchData => MIMTXBWDATA29_GlitchData, + OutSignalName => "MIMTXBWDATA(29)", + OutTemp => MIMTXBWDATA_OUT(29), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(29), + GlitchData => MIMTXBWDATA29_GlitchData, + OutSignalName => "MIMTXBWDATA(29)", + OutTemp => MIMTXBWDATA_OUT(29), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(30), + GlitchData => MIMTXBWDATA30_GlitchData, + OutSignalName => "MIMTXBWDATA(30)", + OutTemp => MIMTXBWDATA_OUT(30), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(30), + GlitchData => MIMTXBWDATA30_GlitchData, + OutSignalName => "MIMTXBWDATA(30)", + OutTemp => MIMTXBWDATA_OUT(30), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(31), + GlitchData => MIMTXBWDATA31_GlitchData, + OutSignalName => "MIMTXBWDATA(31)", + OutTemp => MIMTXBWDATA_OUT(31), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(31), + GlitchData => MIMTXBWDATA31_GlitchData, + OutSignalName => "MIMTXBWDATA(31)", + OutTemp => MIMTXBWDATA_OUT(31), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(32), + GlitchData => MIMTXBWDATA32_GlitchData, + OutSignalName => "MIMTXBWDATA(32)", + OutTemp => MIMTXBWDATA_OUT(32), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(32), + GlitchData => MIMTXBWDATA32_GlitchData, + OutSignalName => "MIMTXBWDATA(32)", + OutTemp => MIMTXBWDATA_OUT(32), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(33), + GlitchData => MIMTXBWDATA33_GlitchData, + OutSignalName => "MIMTXBWDATA(33)", + OutTemp => MIMTXBWDATA_OUT(33), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(33), + GlitchData => MIMTXBWDATA33_GlitchData, + OutSignalName => "MIMTXBWDATA(33)", + OutTemp => MIMTXBWDATA_OUT(33), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(34), + GlitchData => MIMTXBWDATA34_GlitchData, + OutSignalName => "MIMTXBWDATA(34)", + OutTemp => MIMTXBWDATA_OUT(34), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(34), + GlitchData => MIMTXBWDATA34_GlitchData, + OutSignalName => "MIMTXBWDATA(34)", + OutTemp => MIMTXBWDATA_OUT(34), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(35), + GlitchData => MIMTXBWDATA35_GlitchData, + OutSignalName => "MIMTXBWDATA(35)", + OutTemp => MIMTXBWDATA_OUT(35), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(35), + GlitchData => MIMTXBWDATA35_GlitchData, + OutSignalName => "MIMTXBWDATA(35)", + OutTemp => MIMTXBWDATA_OUT(35), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(36), + GlitchData => MIMTXBWDATA36_GlitchData, + OutSignalName => "MIMTXBWDATA(36)", + OutTemp => MIMTXBWDATA_OUT(36), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(36), + GlitchData => MIMTXBWDATA36_GlitchData, + OutSignalName => "MIMTXBWDATA(36)", + OutTemp => MIMTXBWDATA_OUT(36), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(37), + GlitchData => MIMTXBWDATA37_GlitchData, + OutSignalName => "MIMTXBWDATA(37)", + OutTemp => MIMTXBWDATA_OUT(37), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(37), + GlitchData => MIMTXBWDATA37_GlitchData, + OutSignalName => "MIMTXBWDATA(37)", + OutTemp => MIMTXBWDATA_OUT(37), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(38), + GlitchData => MIMTXBWDATA38_GlitchData, + OutSignalName => "MIMTXBWDATA(38)", + OutTemp => MIMTXBWDATA_OUT(38), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(38), + GlitchData => MIMTXBWDATA38_GlitchData, + OutSignalName => "MIMTXBWDATA(38)", + OutTemp => MIMTXBWDATA_OUT(38), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(39), + GlitchData => MIMTXBWDATA39_GlitchData, + OutSignalName => "MIMTXBWDATA(39)", + OutTemp => MIMTXBWDATA_OUT(39), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(39), + GlitchData => MIMTXBWDATA39_GlitchData, + OutSignalName => "MIMTXBWDATA(39)", + OutTemp => MIMTXBWDATA_OUT(39), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(40), + GlitchData => MIMTXBWDATA40_GlitchData, + OutSignalName => "MIMTXBWDATA(40)", + OutTemp => MIMTXBWDATA_OUT(40), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(40), + GlitchData => MIMTXBWDATA40_GlitchData, + OutSignalName => "MIMTXBWDATA(40)", + OutTemp => MIMTXBWDATA_OUT(40), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(41), + GlitchData => MIMTXBWDATA41_GlitchData, + OutSignalName => "MIMTXBWDATA(41)", + OutTemp => MIMTXBWDATA_OUT(41), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(41), + GlitchData => MIMTXBWDATA41_GlitchData, + OutSignalName => "MIMTXBWDATA(41)", + OutTemp => MIMTXBWDATA_OUT(41), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(42), + GlitchData => MIMTXBWDATA42_GlitchData, + OutSignalName => "MIMTXBWDATA(42)", + OutTemp => MIMTXBWDATA_OUT(42), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(42), + GlitchData => MIMTXBWDATA42_GlitchData, + OutSignalName => "MIMTXBWDATA(42)", + OutTemp => MIMTXBWDATA_OUT(42), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(43), + GlitchData => MIMTXBWDATA43_GlitchData, + OutSignalName => "MIMTXBWDATA(43)", + OutTemp => MIMTXBWDATA_OUT(43), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(43), + GlitchData => MIMTXBWDATA43_GlitchData, + OutSignalName => "MIMTXBWDATA(43)", + OutTemp => MIMTXBWDATA_OUT(43), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(44), + GlitchData => MIMTXBWDATA44_GlitchData, + OutSignalName => "MIMTXBWDATA(44)", + OutTemp => MIMTXBWDATA_OUT(44), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(44), + GlitchData => MIMTXBWDATA44_GlitchData, + OutSignalName => "MIMTXBWDATA(44)", + OutTemp => MIMTXBWDATA_OUT(44), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(45), + GlitchData => MIMTXBWDATA45_GlitchData, + OutSignalName => "MIMTXBWDATA(45)", + OutTemp => MIMTXBWDATA_OUT(45), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(45), + GlitchData => MIMTXBWDATA45_GlitchData, + OutSignalName => "MIMTXBWDATA(45)", + OutTemp => MIMTXBWDATA_OUT(45), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(46), + GlitchData => MIMTXBWDATA46_GlitchData, + OutSignalName => "MIMTXBWDATA(46)", + OutTemp => MIMTXBWDATA_OUT(46), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(46), + GlitchData => MIMTXBWDATA46_GlitchData, + OutSignalName => "MIMTXBWDATA(46)", + OutTemp => MIMTXBWDATA_OUT(46), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(47), + GlitchData => MIMTXBWDATA47_GlitchData, + OutSignalName => "MIMTXBWDATA(47)", + OutTemp => MIMTXBWDATA_OUT(47), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(47), + GlitchData => MIMTXBWDATA47_GlitchData, + OutSignalName => "MIMTXBWDATA(47)", + OutTemp => MIMTXBWDATA_OUT(47), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(48), + GlitchData => MIMTXBWDATA48_GlitchData, + OutSignalName => "MIMTXBWDATA(48)", + OutTemp => MIMTXBWDATA_OUT(48), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(48), + GlitchData => MIMTXBWDATA48_GlitchData, + OutSignalName => "MIMTXBWDATA(48)", + OutTemp => MIMTXBWDATA_OUT(48), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(49), + GlitchData => MIMTXBWDATA49_GlitchData, + OutSignalName => "MIMTXBWDATA(49)", + OutTemp => MIMTXBWDATA_OUT(49), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(49), + GlitchData => MIMTXBWDATA49_GlitchData, + OutSignalName => "MIMTXBWDATA(49)", + OutTemp => MIMTXBWDATA_OUT(49), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(50), + GlitchData => MIMTXBWDATA50_GlitchData, + OutSignalName => "MIMTXBWDATA(50)", + OutTemp => MIMTXBWDATA_OUT(50), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(50), + GlitchData => MIMTXBWDATA50_GlitchData, + OutSignalName => "MIMTXBWDATA(50)", + OutTemp => MIMTXBWDATA_OUT(50), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(51), + GlitchData => MIMTXBWDATA51_GlitchData, + OutSignalName => "MIMTXBWDATA(51)", + OutTemp => MIMTXBWDATA_OUT(51), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(51), + GlitchData => MIMTXBWDATA51_GlitchData, + OutSignalName => "MIMTXBWDATA(51)", + OutTemp => MIMTXBWDATA_OUT(51), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(52), + GlitchData => MIMTXBWDATA52_GlitchData, + OutSignalName => "MIMTXBWDATA(52)", + OutTemp => MIMTXBWDATA_OUT(52), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(52), + GlitchData => MIMTXBWDATA52_GlitchData, + OutSignalName => "MIMTXBWDATA(52)", + OutTemp => MIMTXBWDATA_OUT(52), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(53), + GlitchData => MIMTXBWDATA53_GlitchData, + OutSignalName => "MIMTXBWDATA(53)", + OutTemp => MIMTXBWDATA_OUT(53), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(53), + GlitchData => MIMTXBWDATA53_GlitchData, + OutSignalName => "MIMTXBWDATA(53)", + OutTemp => MIMTXBWDATA_OUT(53), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(54), + GlitchData => MIMTXBWDATA54_GlitchData, + OutSignalName => "MIMTXBWDATA(54)", + OutTemp => MIMTXBWDATA_OUT(54), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(54), + GlitchData => MIMTXBWDATA54_GlitchData, + OutSignalName => "MIMTXBWDATA(54)", + OutTemp => MIMTXBWDATA_OUT(54), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(55), + GlitchData => MIMTXBWDATA55_GlitchData, + OutSignalName => "MIMTXBWDATA(55)", + OutTemp => MIMTXBWDATA_OUT(55), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(55), + GlitchData => MIMTXBWDATA55_GlitchData, + OutSignalName => "MIMTXBWDATA(55)", + OutTemp => MIMTXBWDATA_OUT(55), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(56), + GlitchData => MIMTXBWDATA56_GlitchData, + OutSignalName => "MIMTXBWDATA(56)", + OutTemp => MIMTXBWDATA_OUT(56), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(56), + GlitchData => MIMTXBWDATA56_GlitchData, + OutSignalName => "MIMTXBWDATA(56)", + OutTemp => MIMTXBWDATA_OUT(56), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(57), + GlitchData => MIMTXBWDATA57_GlitchData, + OutSignalName => "MIMTXBWDATA(57)", + OutTemp => MIMTXBWDATA_OUT(57), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(57), + GlitchData => MIMTXBWDATA57_GlitchData, + OutSignalName => "MIMTXBWDATA(57)", + OutTemp => MIMTXBWDATA_OUT(57), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(58), + GlitchData => MIMTXBWDATA58_GlitchData, + OutSignalName => "MIMTXBWDATA(58)", + OutTemp => MIMTXBWDATA_OUT(58), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(58), + GlitchData => MIMTXBWDATA58_GlitchData, + OutSignalName => "MIMTXBWDATA(58)", + OutTemp => MIMTXBWDATA_OUT(58), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(59), + GlitchData => MIMTXBWDATA59_GlitchData, + OutSignalName => "MIMTXBWDATA(59)", + OutTemp => MIMTXBWDATA_OUT(59), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(59), + GlitchData => MIMTXBWDATA59_GlitchData, + OutSignalName => "MIMTXBWDATA(59)", + OutTemp => MIMTXBWDATA_OUT(59), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(60), + GlitchData => MIMTXBWDATA60_GlitchData, + OutSignalName => "MIMTXBWDATA(60)", + OutTemp => MIMTXBWDATA_OUT(60), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(60), + GlitchData => MIMTXBWDATA60_GlitchData, + OutSignalName => "MIMTXBWDATA(60)", + OutTemp => MIMTXBWDATA_OUT(60), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(61), + GlitchData => MIMTXBWDATA61_GlitchData, + OutSignalName => "MIMTXBWDATA(61)", + OutTemp => MIMTXBWDATA_OUT(61), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(61), + GlitchData => MIMTXBWDATA61_GlitchData, + OutSignalName => "MIMTXBWDATA(61)", + OutTemp => MIMTXBWDATA_OUT(61), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(62), + GlitchData => MIMTXBWDATA62_GlitchData, + OutSignalName => "MIMTXBWDATA(62)", + OutTemp => MIMTXBWDATA_OUT(62), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(62), + GlitchData => MIMTXBWDATA62_GlitchData, + OutSignalName => "MIMTXBWDATA(62)", + OutTemp => MIMTXBWDATA_OUT(62), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(63), + GlitchData => MIMTXBWDATA63_GlitchData, + OutSignalName => "MIMTXBWDATA(63)", + OutTemp => MIMTXBWDATA_OUT(63), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(63), + GlitchData => MIMTXBWDATA63_GlitchData, + OutSignalName => "MIMTXBWDATA(63)", + OutTemp => MIMTXBWDATA_OUT(63), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(0), + GlitchData => MIMTXBWADD0_GlitchData, + OutSignalName => "MIMTXBWADD(0)", + OutTemp => MIMTXBWADD_OUT(0), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(0), + GlitchData => MIMTXBWADD0_GlitchData, + OutSignalName => "MIMTXBWADD(0)", + OutTemp => MIMTXBWADD_OUT(0), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(1), + GlitchData => MIMTXBWADD1_GlitchData, + OutSignalName => "MIMTXBWADD(1)", + OutTemp => MIMTXBWADD_OUT(1), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(1), + GlitchData => MIMTXBWADD1_GlitchData, + OutSignalName => "MIMTXBWADD(1)", + OutTemp => MIMTXBWADD_OUT(1), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(2), + GlitchData => MIMTXBWADD2_GlitchData, + OutSignalName => "MIMTXBWADD(2)", + OutTemp => MIMTXBWADD_OUT(2), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(2), + GlitchData => MIMTXBWADD2_GlitchData, + OutSignalName => "MIMTXBWADD(2)", + OutTemp => MIMTXBWADD_OUT(2), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(3), + GlitchData => MIMTXBWADD3_GlitchData, + OutSignalName => "MIMTXBWADD(3)", + OutTemp => MIMTXBWADD_OUT(3), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(3), + GlitchData => MIMTXBWADD3_GlitchData, + OutSignalName => "MIMTXBWADD(3)", + OutTemp => MIMTXBWADD_OUT(3), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(4), + GlitchData => MIMTXBWADD4_GlitchData, + OutSignalName => "MIMTXBWADD(4)", + OutTemp => MIMTXBWADD_OUT(4), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(4), + GlitchData => MIMTXBWADD4_GlitchData, + OutSignalName => "MIMTXBWADD(4)", + OutTemp => MIMTXBWADD_OUT(4), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(5), + GlitchData => MIMTXBWADD5_GlitchData, + OutSignalName => "MIMTXBWADD(5)", + OutTemp => MIMTXBWADD_OUT(5), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(5), + GlitchData => MIMTXBWADD5_GlitchData, + OutSignalName => "MIMTXBWADD(5)", + OutTemp => MIMTXBWADD_OUT(5), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(6), + GlitchData => MIMTXBWADD6_GlitchData, + OutSignalName => "MIMTXBWADD(6)", + OutTemp => MIMTXBWADD_OUT(6), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(6), + GlitchData => MIMTXBWADD6_GlitchData, + OutSignalName => "MIMTXBWADD(6)", + OutTemp => MIMTXBWADD_OUT(6), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(7), + GlitchData => MIMTXBWADD7_GlitchData, + OutSignalName => "MIMTXBWADD(7)", + OutTemp => MIMTXBWADD_OUT(7), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(7), + GlitchData => MIMTXBWADD7_GlitchData, + OutSignalName => "MIMTXBWADD(7)", + OutTemp => MIMTXBWADD_OUT(7), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(8), + GlitchData => MIMTXBWADD8_GlitchData, + OutSignalName => "MIMTXBWADD(8)", + OutTemp => MIMTXBWADD_OUT(8), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(8), + GlitchData => MIMTXBWADD8_GlitchData, + OutSignalName => "MIMTXBWADD(8)", + OutTemp => MIMTXBWADD_OUT(8), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(9), + GlitchData => MIMTXBWADD9_GlitchData, + OutSignalName => "MIMTXBWADD(9)", + OutTemp => MIMTXBWADD_OUT(9), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(9), + GlitchData => MIMTXBWADD9_GlitchData, + OutSignalName => "MIMTXBWADD(9)", + OutTemp => MIMTXBWADD_OUT(9), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(10), + GlitchData => MIMTXBWADD10_GlitchData, + OutSignalName => "MIMTXBWADD(10)", + OutTemp => MIMTXBWADD_OUT(10), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(10), + GlitchData => MIMTXBWADD10_GlitchData, + OutSignalName => "MIMTXBWADD(10)", + OutTemp => MIMTXBWADD_OUT(10), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(11), + GlitchData => MIMTXBWADD11_GlitchData, + OutSignalName => "MIMTXBWADD(11)", + OutTemp => MIMTXBWADD_OUT(11), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(11), + GlitchData => MIMTXBWADD11_GlitchData, + OutSignalName => "MIMTXBWADD(11)", + OutTemp => MIMTXBWADD_OUT(11), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(12), + GlitchData => MIMTXBWADD12_GlitchData, + OutSignalName => "MIMTXBWADD(12)", + OutTemp => MIMTXBWADD_OUT(12), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(12), + GlitchData => MIMTXBWADD12_GlitchData, + OutSignalName => "MIMTXBWADD(12)", + OutTemp => MIMTXBWADD_OUT(12), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(0), + GlitchData => MIMTXBRADD0_GlitchData, + OutSignalName => "MIMTXBRADD(0)", + OutTemp => MIMTXBRADD_OUT(0), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(1), + GlitchData => MIMTXBRADD1_GlitchData, + OutSignalName => "MIMTXBRADD(1)", + OutTemp => MIMTXBRADD_OUT(1), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(2), + GlitchData => MIMTXBRADD2_GlitchData, + OutSignalName => "MIMTXBRADD(2)", + OutTemp => MIMTXBRADD_OUT(2), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(3), + GlitchData => MIMTXBRADD3_GlitchData, + OutSignalName => "MIMTXBRADD(3)", + OutTemp => MIMTXBRADD_OUT(3), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(4), + GlitchData => MIMTXBRADD4_GlitchData, + OutSignalName => "MIMTXBRADD(4)", + OutTemp => MIMTXBRADD_OUT(4), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(5), + GlitchData => MIMTXBRADD5_GlitchData, + OutSignalName => "MIMTXBRADD(5)", + OutTemp => MIMTXBRADD_OUT(5), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(6), + GlitchData => MIMTXBRADD6_GlitchData, + OutSignalName => "MIMTXBRADD(6)", + OutTemp => MIMTXBRADD_OUT(6), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(7), + GlitchData => MIMTXBRADD7_GlitchData, + OutSignalName => "MIMTXBRADD(7)", + OutTemp => MIMTXBRADD_OUT(7), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(8), + GlitchData => MIMTXBRADD8_GlitchData, + OutSignalName => "MIMTXBRADD(8)", + OutTemp => MIMTXBRADD_OUT(8), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(9), + GlitchData => MIMTXBRADD9_GlitchData, + OutSignalName => "MIMTXBRADD(9)", + OutTemp => MIMTXBRADD_OUT(9), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(10), + GlitchData => MIMTXBRADD10_GlitchData, + OutSignalName => "MIMTXBRADD(10)", + OutTemp => MIMTXBRADD_OUT(10), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(11), + GlitchData => MIMTXBRADD11_GlitchData, + OutSignalName => "MIMTXBRADD(11)", + OutTemp => MIMTXBRADD_OUT(11), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(12), + GlitchData => MIMTXBRADD12_GlitchData, + OutSignalName => "MIMTXBRADD(12)", + OutTemp => MIMTXBRADD_OUT(12), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWEN, + GlitchData => MIMTXBWEN_GlitchData, + OutSignalName => "MIMTXBWEN", + OutTemp => MIMTXBWEN_OUT, + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWEN, + GlitchData => MIMTXBWEN_GlitchData, + OutSignalName => "MIMTXBWEN", + OutTemp => MIMTXBWEN_OUT, + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBREN, + GlitchData => MIMTXBREN_GlitchData, + OutSignalName => "MIMTXBREN", + OutTemp => MIMTXBREN_OUT, + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(0), + GlitchData => MIMDLLBWDATA0_GlitchData, + OutSignalName => "MIMDLLBWDATA(0)", + OutTemp => MIMDLLBWDATA_OUT(0), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(1), + GlitchData => MIMDLLBWDATA1_GlitchData, + OutSignalName => "MIMDLLBWDATA(1)", + OutTemp => MIMDLLBWDATA_OUT(1), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(2), + GlitchData => MIMDLLBWDATA2_GlitchData, + OutSignalName => "MIMDLLBWDATA(2)", + OutTemp => MIMDLLBWDATA_OUT(2), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(3), + GlitchData => MIMDLLBWDATA3_GlitchData, + OutSignalName => "MIMDLLBWDATA(3)", + OutTemp => MIMDLLBWDATA_OUT(3), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(4), + GlitchData => MIMDLLBWDATA4_GlitchData, + OutSignalName => "MIMDLLBWDATA(4)", + OutTemp => MIMDLLBWDATA_OUT(4), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(5), + GlitchData => MIMDLLBWDATA5_GlitchData, + OutSignalName => "MIMDLLBWDATA(5)", + OutTemp => MIMDLLBWDATA_OUT(5), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(6), + GlitchData => MIMDLLBWDATA6_GlitchData, + OutSignalName => "MIMDLLBWDATA(6)", + OutTemp => MIMDLLBWDATA_OUT(6), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(7), + GlitchData => MIMDLLBWDATA7_GlitchData, + OutSignalName => "MIMDLLBWDATA(7)", + OutTemp => MIMDLLBWDATA_OUT(7), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(8), + GlitchData => MIMDLLBWDATA8_GlitchData, + OutSignalName => "MIMDLLBWDATA(8)", + OutTemp => MIMDLLBWDATA_OUT(8), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(9), + GlitchData => MIMDLLBWDATA9_GlitchData, + OutSignalName => "MIMDLLBWDATA(9)", + OutTemp => MIMDLLBWDATA_OUT(9), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(10), + GlitchData => MIMDLLBWDATA10_GlitchData, + OutSignalName => "MIMDLLBWDATA(10)", + OutTemp => MIMDLLBWDATA_OUT(10), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(11), + GlitchData => MIMDLLBWDATA11_GlitchData, + OutSignalName => "MIMDLLBWDATA(11)", + OutTemp => MIMDLLBWDATA_OUT(11), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(12), + GlitchData => MIMDLLBWDATA12_GlitchData, + OutSignalName => "MIMDLLBWDATA(12)", + OutTemp => MIMDLLBWDATA_OUT(12), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(13), + GlitchData => MIMDLLBWDATA13_GlitchData, + OutSignalName => "MIMDLLBWDATA(13)", + OutTemp => MIMDLLBWDATA_OUT(13), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(14), + GlitchData => MIMDLLBWDATA14_GlitchData, + OutSignalName => "MIMDLLBWDATA(14)", + OutTemp => MIMDLLBWDATA_OUT(14), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(15), + GlitchData => MIMDLLBWDATA15_GlitchData, + OutSignalName => "MIMDLLBWDATA(15)", + OutTemp => MIMDLLBWDATA_OUT(15), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(16), + GlitchData => MIMDLLBWDATA16_GlitchData, + OutSignalName => "MIMDLLBWDATA(16)", + OutTemp => MIMDLLBWDATA_OUT(16), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(17), + GlitchData => MIMDLLBWDATA17_GlitchData, + OutSignalName => "MIMDLLBWDATA(17)", + OutTemp => MIMDLLBWDATA_OUT(17), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(18), + GlitchData => MIMDLLBWDATA18_GlitchData, + OutSignalName => "MIMDLLBWDATA(18)", + OutTemp => MIMDLLBWDATA_OUT(18), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(19), + GlitchData => MIMDLLBWDATA19_GlitchData, + OutSignalName => "MIMDLLBWDATA(19)", + OutTemp => MIMDLLBWDATA_OUT(19), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(20), + GlitchData => MIMDLLBWDATA20_GlitchData, + OutSignalName => "MIMDLLBWDATA(20)", + OutTemp => MIMDLLBWDATA_OUT(20), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(21), + GlitchData => MIMDLLBWDATA21_GlitchData, + OutSignalName => "MIMDLLBWDATA(21)", + OutTemp => MIMDLLBWDATA_OUT(21), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(22), + GlitchData => MIMDLLBWDATA22_GlitchData, + OutSignalName => "MIMDLLBWDATA(22)", + OutTemp => MIMDLLBWDATA_OUT(22), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(23), + GlitchData => MIMDLLBWDATA23_GlitchData, + OutSignalName => "MIMDLLBWDATA(23)", + OutTemp => MIMDLLBWDATA_OUT(23), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(24), + GlitchData => MIMDLLBWDATA24_GlitchData, + OutSignalName => "MIMDLLBWDATA(24)", + OutTemp => MIMDLLBWDATA_OUT(24), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(25), + GlitchData => MIMDLLBWDATA25_GlitchData, + OutSignalName => "MIMDLLBWDATA(25)", + OutTemp => MIMDLLBWDATA_OUT(25), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(26), + GlitchData => MIMDLLBWDATA26_GlitchData, + OutSignalName => "MIMDLLBWDATA(26)", + OutTemp => MIMDLLBWDATA_OUT(26), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(27), + GlitchData => MIMDLLBWDATA27_GlitchData, + OutSignalName => "MIMDLLBWDATA(27)", + OutTemp => MIMDLLBWDATA_OUT(27), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(28), + GlitchData => MIMDLLBWDATA28_GlitchData, + OutSignalName => "MIMDLLBWDATA(28)", + OutTemp => MIMDLLBWDATA_OUT(28), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(29), + GlitchData => MIMDLLBWDATA29_GlitchData, + OutSignalName => "MIMDLLBWDATA(29)", + OutTemp => MIMDLLBWDATA_OUT(29), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(30), + GlitchData => MIMDLLBWDATA30_GlitchData, + OutSignalName => "MIMDLLBWDATA(30)", + OutTemp => MIMDLLBWDATA_OUT(30), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(31), + GlitchData => MIMDLLBWDATA31_GlitchData, + OutSignalName => "MIMDLLBWDATA(31)", + OutTemp => MIMDLLBWDATA_OUT(31), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(32), + GlitchData => MIMDLLBWDATA32_GlitchData, + OutSignalName => "MIMDLLBWDATA(32)", + OutTemp => MIMDLLBWDATA_OUT(32), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(33), + GlitchData => MIMDLLBWDATA33_GlitchData, + OutSignalName => "MIMDLLBWDATA(33)", + OutTemp => MIMDLLBWDATA_OUT(33), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(34), + GlitchData => MIMDLLBWDATA34_GlitchData, + OutSignalName => "MIMDLLBWDATA(34)", + OutTemp => MIMDLLBWDATA_OUT(34), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(35), + GlitchData => MIMDLLBWDATA35_GlitchData, + OutSignalName => "MIMDLLBWDATA(35)", + OutTemp => MIMDLLBWDATA_OUT(35), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(36), + GlitchData => MIMDLLBWDATA36_GlitchData, + OutSignalName => "MIMDLLBWDATA(36)", + OutTemp => MIMDLLBWDATA_OUT(36), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(37), + GlitchData => MIMDLLBWDATA37_GlitchData, + OutSignalName => "MIMDLLBWDATA(37)", + OutTemp => MIMDLLBWDATA_OUT(37), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(38), + GlitchData => MIMDLLBWDATA38_GlitchData, + OutSignalName => "MIMDLLBWDATA(38)", + OutTemp => MIMDLLBWDATA_OUT(38), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(39), + GlitchData => MIMDLLBWDATA39_GlitchData, + OutSignalName => "MIMDLLBWDATA(39)", + OutTemp => MIMDLLBWDATA_OUT(39), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(40), + GlitchData => MIMDLLBWDATA40_GlitchData, + OutSignalName => "MIMDLLBWDATA(40)", + OutTemp => MIMDLLBWDATA_OUT(40), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(41), + GlitchData => MIMDLLBWDATA41_GlitchData, + OutSignalName => "MIMDLLBWDATA(41)", + OutTemp => MIMDLLBWDATA_OUT(41), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(42), + GlitchData => MIMDLLBWDATA42_GlitchData, + OutSignalName => "MIMDLLBWDATA(42)", + OutTemp => MIMDLLBWDATA_OUT(42), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(43), + GlitchData => MIMDLLBWDATA43_GlitchData, + OutSignalName => "MIMDLLBWDATA(43)", + OutTemp => MIMDLLBWDATA_OUT(43), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(44), + GlitchData => MIMDLLBWDATA44_GlitchData, + OutSignalName => "MIMDLLBWDATA(44)", + OutTemp => MIMDLLBWDATA_OUT(44), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(45), + GlitchData => MIMDLLBWDATA45_GlitchData, + OutSignalName => "MIMDLLBWDATA(45)", + OutTemp => MIMDLLBWDATA_OUT(45), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(46), + GlitchData => MIMDLLBWDATA46_GlitchData, + OutSignalName => "MIMDLLBWDATA(46)", + OutTemp => MIMDLLBWDATA_OUT(46), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(47), + GlitchData => MIMDLLBWDATA47_GlitchData, + OutSignalName => "MIMDLLBWDATA(47)", + OutTemp => MIMDLLBWDATA_OUT(47), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(48), + GlitchData => MIMDLLBWDATA48_GlitchData, + OutSignalName => "MIMDLLBWDATA(48)", + OutTemp => MIMDLLBWDATA_OUT(48), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(49), + GlitchData => MIMDLLBWDATA49_GlitchData, + OutSignalName => "MIMDLLBWDATA(49)", + OutTemp => MIMDLLBWDATA_OUT(49), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(50), + GlitchData => MIMDLLBWDATA50_GlitchData, + OutSignalName => "MIMDLLBWDATA(50)", + OutTemp => MIMDLLBWDATA_OUT(50), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(51), + GlitchData => MIMDLLBWDATA51_GlitchData, + OutSignalName => "MIMDLLBWDATA(51)", + OutTemp => MIMDLLBWDATA_OUT(51), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(52), + GlitchData => MIMDLLBWDATA52_GlitchData, + OutSignalName => "MIMDLLBWDATA(52)", + OutTemp => MIMDLLBWDATA_OUT(52), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(53), + GlitchData => MIMDLLBWDATA53_GlitchData, + OutSignalName => "MIMDLLBWDATA(53)", + OutTemp => MIMDLLBWDATA_OUT(53), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(54), + GlitchData => MIMDLLBWDATA54_GlitchData, + OutSignalName => "MIMDLLBWDATA(54)", + OutTemp => MIMDLLBWDATA_OUT(54), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(55), + GlitchData => MIMDLLBWDATA55_GlitchData, + OutSignalName => "MIMDLLBWDATA(55)", + OutTemp => MIMDLLBWDATA_OUT(55), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(56), + GlitchData => MIMDLLBWDATA56_GlitchData, + OutSignalName => "MIMDLLBWDATA(56)", + OutTemp => MIMDLLBWDATA_OUT(56), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(57), + GlitchData => MIMDLLBWDATA57_GlitchData, + OutSignalName => "MIMDLLBWDATA(57)", + OutTemp => MIMDLLBWDATA_OUT(57), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(58), + GlitchData => MIMDLLBWDATA58_GlitchData, + OutSignalName => "MIMDLLBWDATA(58)", + OutTemp => MIMDLLBWDATA_OUT(58), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(59), + GlitchData => MIMDLLBWDATA59_GlitchData, + OutSignalName => "MIMDLLBWDATA(59)", + OutTemp => MIMDLLBWDATA_OUT(59), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(60), + GlitchData => MIMDLLBWDATA60_GlitchData, + OutSignalName => "MIMDLLBWDATA(60)", + OutTemp => MIMDLLBWDATA_OUT(60), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(61), + GlitchData => MIMDLLBWDATA61_GlitchData, + OutSignalName => "MIMDLLBWDATA(61)", + OutTemp => MIMDLLBWDATA_OUT(61), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(62), + GlitchData => MIMDLLBWDATA62_GlitchData, + OutSignalName => "MIMDLLBWDATA(62)", + OutTemp => MIMDLLBWDATA_OUT(62), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(63), + GlitchData => MIMDLLBWDATA63_GlitchData, + OutSignalName => "MIMDLLBWDATA(63)", + OutTemp => MIMDLLBWDATA_OUT(63), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(0), + GlitchData => MIMDLLBWADD0_GlitchData, + OutSignalName => "MIMDLLBWADD(0)", + OutTemp => MIMDLLBWADD_OUT(0), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(1), + GlitchData => MIMDLLBWADD1_GlitchData, + OutSignalName => "MIMDLLBWADD(1)", + OutTemp => MIMDLLBWADD_OUT(1), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(2), + GlitchData => MIMDLLBWADD2_GlitchData, + OutSignalName => "MIMDLLBWADD(2)", + OutTemp => MIMDLLBWADD_OUT(2), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(3), + GlitchData => MIMDLLBWADD3_GlitchData, + OutSignalName => "MIMDLLBWADD(3)", + OutTemp => MIMDLLBWADD_OUT(3), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(4), + GlitchData => MIMDLLBWADD4_GlitchData, + OutSignalName => "MIMDLLBWADD(4)", + OutTemp => MIMDLLBWADD_OUT(4), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(5), + GlitchData => MIMDLLBWADD5_GlitchData, + OutSignalName => "MIMDLLBWADD(5)", + OutTemp => MIMDLLBWADD_OUT(5), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(6), + GlitchData => MIMDLLBWADD6_GlitchData, + OutSignalName => "MIMDLLBWADD(6)", + OutTemp => MIMDLLBWADD_OUT(6), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(7), + GlitchData => MIMDLLBWADD7_GlitchData, + OutSignalName => "MIMDLLBWADD(7)", + OutTemp => MIMDLLBWADD_OUT(7), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(8), + GlitchData => MIMDLLBWADD8_GlitchData, + OutSignalName => "MIMDLLBWADD(8)", + OutTemp => MIMDLLBWADD_OUT(8), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(9), + GlitchData => MIMDLLBWADD9_GlitchData, + OutSignalName => "MIMDLLBWADD(9)", + OutTemp => MIMDLLBWADD_OUT(9), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(10), + GlitchData => MIMDLLBWADD10_GlitchData, + OutSignalName => "MIMDLLBWADD(10)", + OutTemp => MIMDLLBWADD_OUT(10), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(11), + GlitchData => MIMDLLBWADD11_GlitchData, + OutSignalName => "MIMDLLBWADD(11)", + OutTemp => MIMDLLBWADD_OUT(11), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(0), + GlitchData => MIMDLLBRADD0_GlitchData, + OutSignalName => "MIMDLLBRADD(0)", + OutTemp => MIMDLLBRADD_OUT(0), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(1), + GlitchData => MIMDLLBRADD1_GlitchData, + OutSignalName => "MIMDLLBRADD(1)", + OutTemp => MIMDLLBRADD_OUT(1), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(2), + GlitchData => MIMDLLBRADD2_GlitchData, + OutSignalName => "MIMDLLBRADD(2)", + OutTemp => MIMDLLBRADD_OUT(2), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(3), + GlitchData => MIMDLLBRADD3_GlitchData, + OutSignalName => "MIMDLLBRADD(3)", + OutTemp => MIMDLLBRADD_OUT(3), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(4), + GlitchData => MIMDLLBRADD4_GlitchData, + OutSignalName => "MIMDLLBRADD(4)", + OutTemp => MIMDLLBRADD_OUT(4), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(5), + GlitchData => MIMDLLBRADD5_GlitchData, + OutSignalName => "MIMDLLBRADD(5)", + OutTemp => MIMDLLBRADD_OUT(5), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(6), + GlitchData => MIMDLLBRADD6_GlitchData, + OutSignalName => "MIMDLLBRADD(6)", + OutTemp => MIMDLLBRADD_OUT(6), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(7), + GlitchData => MIMDLLBRADD7_GlitchData, + OutSignalName => "MIMDLLBRADD(7)", + OutTemp => MIMDLLBRADD_OUT(7), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(8), + GlitchData => MIMDLLBRADD8_GlitchData, + OutSignalName => "MIMDLLBRADD(8)", + OutTemp => MIMDLLBRADD_OUT(8), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(9), + GlitchData => MIMDLLBRADD9_GlitchData, + OutSignalName => "MIMDLLBRADD(9)", + OutTemp => MIMDLLBRADD_OUT(9), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(10), + GlitchData => MIMDLLBRADD10_GlitchData, + OutSignalName => "MIMDLLBRADD(10)", + OutTemp => MIMDLLBRADD_OUT(10), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(11), + GlitchData => MIMDLLBRADD11_GlitchData, + OutSignalName => "MIMDLLBRADD(11)", + OutTemp => MIMDLLBRADD_OUT(11), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWEN, + GlitchData => MIMDLLBWEN_GlitchData, + OutSignalName => "MIMDLLBWEN", + OutTemp => MIMDLLBWEN_OUT, + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBREN, + GlitchData => MIMDLLBREN_GlitchData, + OutSignalName => "MIMDLLBREN", + OutTemp => MIMDLLBREN_OUT, + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CRMRXHOTRESETN, + GlitchData => CRMRXHOTRESETN_GlitchData, + OutSignalName => "CRMRXHOTRESETN", + OutTemp => CRMRXHOTRESETN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CRMDOHOTRESETN, + GlitchData => CRMDOHOTRESETN_GlitchData, + OutSignalName => "CRMDOHOTRESETN", + OutTemp => CRMDOHOTRESETN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CRMPWRSOFTRESETN, + GlitchData => CRMPWRSOFTRESETN_GlitchData, + OutSignalName => "CRMPWRSOFTRESETN", + OutTemp => CRMPWRSOFTRESETN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(0), + GlitchData => LLKTCSTATUS0_GlitchData, + OutSignalName => "LLKTCSTATUS(0)", + OutTemp => LLKTCSTATUS_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(0), + GlitchData => LLKTCSTATUS0_GlitchData, + OutSignalName => "LLKTCSTATUS(0)", + OutTemp => LLKTCSTATUS_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(1), + GlitchData => LLKTCSTATUS1_GlitchData, + OutSignalName => "LLKTCSTATUS(1)", + OutTemp => LLKTCSTATUS_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(1), + GlitchData => LLKTCSTATUS1_GlitchData, + OutSignalName => "LLKTCSTATUS(1)", + OutTemp => LLKTCSTATUS_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(2), + GlitchData => LLKTCSTATUS2_GlitchData, + OutSignalName => "LLKTCSTATUS(2)", + OutTemp => LLKTCSTATUS_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(2), + GlitchData => LLKTCSTATUS2_GlitchData, + OutSignalName => "LLKTCSTATUS(2)", + OutTemp => LLKTCSTATUS_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(3), + GlitchData => LLKTCSTATUS3_GlitchData, + OutSignalName => "LLKTCSTATUS(3)", + OutTemp => LLKTCSTATUS_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(3), + GlitchData => LLKTCSTATUS3_GlitchData, + OutSignalName => "LLKTCSTATUS(3)", + OutTemp => LLKTCSTATUS_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(4), + GlitchData => LLKTCSTATUS4_GlitchData, + OutSignalName => "LLKTCSTATUS(4)", + OutTemp => LLKTCSTATUS_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(4), + GlitchData => LLKTCSTATUS4_GlitchData, + OutSignalName => "LLKTCSTATUS(4)", + OutTemp => LLKTCSTATUS_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(5), + GlitchData => LLKTCSTATUS5_GlitchData, + OutSignalName => "LLKTCSTATUS(5)", + OutTemp => LLKTCSTATUS_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(5), + GlitchData => LLKTCSTATUS5_GlitchData, + OutSignalName => "LLKTCSTATUS(5)", + OutTemp => LLKTCSTATUS_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(6), + GlitchData => LLKTCSTATUS6_GlitchData, + OutSignalName => "LLKTCSTATUS(6)", + OutTemp => LLKTCSTATUS_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(6), + GlitchData => LLKTCSTATUS6_GlitchData, + OutSignalName => "LLKTCSTATUS(6)", + OutTemp => LLKTCSTATUS_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(7), + GlitchData => LLKTCSTATUS7_GlitchData, + OutSignalName => "LLKTCSTATUS(7)", + OutTemp => LLKTCSTATUS_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(7), + GlitchData => LLKTCSTATUS7_GlitchData, + OutSignalName => "LLKTCSTATUS(7)", + OutTemp => LLKTCSTATUS_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXDSTRDYN, + GlitchData => LLKTXDSTRDYN_GlitchData, + OutSignalName => "LLKTXDSTRDYN", + OutTemp => LLKTXDSTRDYN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXDSTRDYN, + GlitchData => LLKTXDSTRDYN_GlitchData, + OutSignalName => "LLKTXDSTRDYN", + OutTemp => LLKTXDSTRDYN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(0), + GlitchData => LLKTXCHANSPACE0_GlitchData, + OutSignalName => "LLKTXCHANSPACE(0)", + OutTemp => LLKTXCHANSPACE_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(0), + GlitchData => LLKTXCHANSPACE0_GlitchData, + OutSignalName => "LLKTXCHANSPACE(0)", + OutTemp => LLKTXCHANSPACE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(1), + GlitchData => LLKTXCHANSPACE1_GlitchData, + OutSignalName => "LLKTXCHANSPACE(1)", + OutTemp => LLKTXCHANSPACE_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(1), + GlitchData => LLKTXCHANSPACE1_GlitchData, + OutSignalName => "LLKTXCHANSPACE(1)", + OutTemp => LLKTXCHANSPACE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(2), + GlitchData => LLKTXCHANSPACE2_GlitchData, + OutSignalName => "LLKTXCHANSPACE(2)", + OutTemp => LLKTXCHANSPACE_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(2), + GlitchData => LLKTXCHANSPACE2_GlitchData, + OutSignalName => "LLKTXCHANSPACE(2)", + OutTemp => LLKTXCHANSPACE_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(3), + GlitchData => LLKTXCHANSPACE3_GlitchData, + OutSignalName => "LLKTXCHANSPACE(3)", + OutTemp => LLKTXCHANSPACE_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(3), + GlitchData => LLKTXCHANSPACE3_GlitchData, + OutSignalName => "LLKTXCHANSPACE(3)", + OutTemp => LLKTXCHANSPACE_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(4), + GlitchData => LLKTXCHANSPACE4_GlitchData, + OutSignalName => "LLKTXCHANSPACE(4)", + OutTemp => LLKTXCHANSPACE_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(4), + GlitchData => LLKTXCHANSPACE4_GlitchData, + OutSignalName => "LLKTXCHANSPACE(4)", + OutTemp => LLKTXCHANSPACE_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(5), + GlitchData => LLKTXCHANSPACE5_GlitchData, + OutSignalName => "LLKTXCHANSPACE(5)", + OutTemp => LLKTXCHANSPACE_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(5), + GlitchData => LLKTXCHANSPACE5_GlitchData, + OutSignalName => "LLKTXCHANSPACE(5)", + OutTemp => LLKTXCHANSPACE_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(6), + GlitchData => LLKTXCHANSPACE6_GlitchData, + OutSignalName => "LLKTXCHANSPACE(6)", + OutTemp => LLKTXCHANSPACE_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(6), + GlitchData => LLKTXCHANSPACE6_GlitchData, + OutSignalName => "LLKTXCHANSPACE(6)", + OutTemp => LLKTXCHANSPACE_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(7), + GlitchData => LLKTXCHANSPACE7_GlitchData, + OutSignalName => "LLKTXCHANSPACE(7)", + OutTemp => LLKTXCHANSPACE_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(7), + GlitchData => LLKTXCHANSPACE7_GlitchData, + OutSignalName => "LLKTXCHANSPACE(7)", + OutTemp => LLKTXCHANSPACE_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(8), + GlitchData => LLKTXCHANSPACE8_GlitchData, + OutSignalName => "LLKTXCHANSPACE(8)", + OutTemp => LLKTXCHANSPACE_OUT(8), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(8), + GlitchData => LLKTXCHANSPACE8_GlitchData, + OutSignalName => "LLKTXCHANSPACE(8)", + OutTemp => LLKTXCHANSPACE_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(9), + GlitchData => LLKTXCHANSPACE9_GlitchData, + OutSignalName => "LLKTXCHANSPACE(9)", + OutTemp => LLKTXCHANSPACE_OUT(9), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(9), + GlitchData => LLKTXCHANSPACE9_GlitchData, + OutSignalName => "LLKTXCHANSPACE(9)", + OutTemp => LLKTXCHANSPACE_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(0), + GlitchData => LLKTXCHPOSTEDREADYN0_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(0)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(0), + GlitchData => LLKTXCHPOSTEDREADYN0_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(0)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(1), + GlitchData => LLKTXCHPOSTEDREADYN1_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(1)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(1), + GlitchData => LLKTXCHPOSTEDREADYN1_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(1)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(2), + GlitchData => LLKTXCHPOSTEDREADYN2_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(2)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(2), + GlitchData => LLKTXCHPOSTEDREADYN2_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(2)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(3), + GlitchData => LLKTXCHPOSTEDREADYN3_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(3)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(3), + GlitchData => LLKTXCHPOSTEDREADYN3_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(3)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(4), + GlitchData => LLKTXCHPOSTEDREADYN4_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(4)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(4), + GlitchData => LLKTXCHPOSTEDREADYN4_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(4)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(5), + GlitchData => LLKTXCHPOSTEDREADYN5_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(5)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(5), + GlitchData => LLKTXCHPOSTEDREADYN5_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(5)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(6), + GlitchData => LLKTXCHPOSTEDREADYN6_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(6)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(6), + GlitchData => LLKTXCHPOSTEDREADYN6_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(6)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(7), + GlitchData => LLKTXCHPOSTEDREADYN7_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(7)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(7), + GlitchData => LLKTXCHPOSTEDREADYN7_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(7)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(0), + GlitchData => LLKTXCHNONPOSTEDREADYN0_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(0)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(0), + GlitchData => LLKTXCHNONPOSTEDREADYN0_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(0)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(1), + GlitchData => LLKTXCHNONPOSTEDREADYN1_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(1)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(1), + GlitchData => LLKTXCHNONPOSTEDREADYN1_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(1)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(2), + GlitchData => LLKTXCHNONPOSTEDREADYN2_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(2)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(2), + GlitchData => LLKTXCHNONPOSTEDREADYN2_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(2)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(3), + GlitchData => LLKTXCHNONPOSTEDREADYN3_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(3)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(3), + GlitchData => LLKTXCHNONPOSTEDREADYN3_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(3)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(4), + GlitchData => LLKTXCHNONPOSTEDREADYN4_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(4)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(4), + GlitchData => LLKTXCHNONPOSTEDREADYN4_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(4)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(5), + GlitchData => LLKTXCHNONPOSTEDREADYN5_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(5)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(5), + GlitchData => LLKTXCHNONPOSTEDREADYN5_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(5)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(6), + GlitchData => LLKTXCHNONPOSTEDREADYN6_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(6)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(6), + GlitchData => LLKTXCHNONPOSTEDREADYN6_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(6)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(7), + GlitchData => LLKTXCHNONPOSTEDREADYN7_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(7)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(7), + GlitchData => LLKTXCHNONPOSTEDREADYN7_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(7)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(0), + GlitchData => LLKTXCHCOMPLETIONREADYN0_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(0)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(0), + GlitchData => LLKTXCHCOMPLETIONREADYN0_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(0)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(1), + GlitchData => LLKTXCHCOMPLETIONREADYN1_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(1)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(1), + GlitchData => LLKTXCHCOMPLETIONREADYN1_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(1)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(2), + GlitchData => LLKTXCHCOMPLETIONREADYN2_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(2)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(2), + GlitchData => LLKTXCHCOMPLETIONREADYN2_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(2)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(3), + GlitchData => LLKTXCHCOMPLETIONREADYN3_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(3)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(3), + GlitchData => LLKTXCHCOMPLETIONREADYN3_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(3)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(4), + GlitchData => LLKTXCHCOMPLETIONREADYN4_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(4)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(4), + GlitchData => LLKTXCHCOMPLETIONREADYN4_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(4)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(5), + GlitchData => LLKTXCHCOMPLETIONREADYN5_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(5)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(5), + GlitchData => LLKTXCHCOMPLETIONREADYN5_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(5)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(6), + GlitchData => LLKTXCHCOMPLETIONREADYN6_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(6)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(6), + GlitchData => LLKTXCHCOMPLETIONREADYN6_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(6)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(7), + GlitchData => LLKTXCHCOMPLETIONREADYN7_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(7)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(7), + GlitchData => LLKTXCHCOMPLETIONREADYN7_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(7)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCONFIGREADYN, + GlitchData => LLKTXCONFIGREADYN_GlitchData, + OutSignalName => "LLKTXCONFIGREADYN", + OutTemp => LLKTXCONFIGREADYN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCONFIGREADYN, + GlitchData => LLKTXCONFIGREADYN_GlitchData, + OutSignalName => "LLKTXCONFIGREADYN", + OutTemp => LLKTXCONFIGREADYN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(0), + GlitchData => LLKRXDATA0_GlitchData, + OutSignalName => "LLKRXDATA(0)", + OutTemp => LLKRXDATA_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(0), + GlitchData => LLKRXDATA0_GlitchData, + OutSignalName => "LLKRXDATA(0)", + OutTemp => LLKRXDATA_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(1), + GlitchData => LLKRXDATA1_GlitchData, + OutSignalName => "LLKRXDATA(1)", + OutTemp => LLKRXDATA_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(1), + GlitchData => LLKRXDATA1_GlitchData, + OutSignalName => "LLKRXDATA(1)", + OutTemp => LLKRXDATA_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(2), + GlitchData => LLKRXDATA2_GlitchData, + OutSignalName => "LLKRXDATA(2)", + OutTemp => LLKRXDATA_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(2), + GlitchData => LLKRXDATA2_GlitchData, + OutSignalName => "LLKRXDATA(2)", + OutTemp => LLKRXDATA_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(3), + GlitchData => LLKRXDATA3_GlitchData, + OutSignalName => "LLKRXDATA(3)", + OutTemp => LLKRXDATA_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(3), + GlitchData => LLKRXDATA3_GlitchData, + OutSignalName => "LLKRXDATA(3)", + OutTemp => LLKRXDATA_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(4), + GlitchData => LLKRXDATA4_GlitchData, + OutSignalName => "LLKRXDATA(4)", + OutTemp => LLKRXDATA_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(4), + GlitchData => LLKRXDATA4_GlitchData, + OutSignalName => "LLKRXDATA(4)", + OutTemp => LLKRXDATA_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(5), + GlitchData => LLKRXDATA5_GlitchData, + OutSignalName => "LLKRXDATA(5)", + OutTemp => LLKRXDATA_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(5), + GlitchData => LLKRXDATA5_GlitchData, + OutSignalName => "LLKRXDATA(5)", + OutTemp => LLKRXDATA_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(6), + GlitchData => LLKRXDATA6_GlitchData, + OutSignalName => "LLKRXDATA(6)", + OutTemp => LLKRXDATA_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(6), + GlitchData => LLKRXDATA6_GlitchData, + OutSignalName => "LLKRXDATA(6)", + OutTemp => LLKRXDATA_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(7), + GlitchData => LLKRXDATA7_GlitchData, + OutSignalName => "LLKRXDATA(7)", + OutTemp => LLKRXDATA_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(7), + GlitchData => LLKRXDATA7_GlitchData, + OutSignalName => "LLKRXDATA(7)", + OutTemp => LLKRXDATA_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(8), + GlitchData => LLKRXDATA8_GlitchData, + OutSignalName => "LLKRXDATA(8)", + OutTemp => LLKRXDATA_OUT(8), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(8), + GlitchData => LLKRXDATA8_GlitchData, + OutSignalName => "LLKRXDATA(8)", + OutTemp => LLKRXDATA_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(9), + GlitchData => LLKRXDATA9_GlitchData, + OutSignalName => "LLKRXDATA(9)", + OutTemp => LLKRXDATA_OUT(9), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(9), + GlitchData => LLKRXDATA9_GlitchData, + OutSignalName => "LLKRXDATA(9)", + OutTemp => LLKRXDATA_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(10), + GlitchData => LLKRXDATA10_GlitchData, + OutSignalName => "LLKRXDATA(10)", + OutTemp => LLKRXDATA_OUT(10), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(10), + GlitchData => LLKRXDATA10_GlitchData, + OutSignalName => "LLKRXDATA(10)", + OutTemp => LLKRXDATA_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(11), + GlitchData => LLKRXDATA11_GlitchData, + OutSignalName => "LLKRXDATA(11)", + OutTemp => LLKRXDATA_OUT(11), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(11), + GlitchData => LLKRXDATA11_GlitchData, + OutSignalName => "LLKRXDATA(11)", + OutTemp => LLKRXDATA_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(12), + GlitchData => LLKRXDATA12_GlitchData, + OutSignalName => "LLKRXDATA(12)", + OutTemp => LLKRXDATA_OUT(12), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(12), + GlitchData => LLKRXDATA12_GlitchData, + OutSignalName => "LLKRXDATA(12)", + OutTemp => LLKRXDATA_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(13), + GlitchData => LLKRXDATA13_GlitchData, + OutSignalName => "LLKRXDATA(13)", + OutTemp => LLKRXDATA_OUT(13), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(13), + GlitchData => LLKRXDATA13_GlitchData, + OutSignalName => "LLKRXDATA(13)", + OutTemp => LLKRXDATA_OUT(13), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(14), + GlitchData => LLKRXDATA14_GlitchData, + OutSignalName => "LLKRXDATA(14)", + OutTemp => LLKRXDATA_OUT(14), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(14), + GlitchData => LLKRXDATA14_GlitchData, + OutSignalName => "LLKRXDATA(14)", + OutTemp => LLKRXDATA_OUT(14), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(15), + GlitchData => LLKRXDATA15_GlitchData, + OutSignalName => "LLKRXDATA(15)", + OutTemp => LLKRXDATA_OUT(15), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(15), + GlitchData => LLKRXDATA15_GlitchData, + OutSignalName => "LLKRXDATA(15)", + OutTemp => LLKRXDATA_OUT(15), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(16), + GlitchData => LLKRXDATA16_GlitchData, + OutSignalName => "LLKRXDATA(16)", + OutTemp => LLKRXDATA_OUT(16), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(16), + GlitchData => LLKRXDATA16_GlitchData, + OutSignalName => "LLKRXDATA(16)", + OutTemp => LLKRXDATA_OUT(16), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(17), + GlitchData => LLKRXDATA17_GlitchData, + OutSignalName => "LLKRXDATA(17)", + OutTemp => LLKRXDATA_OUT(17), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(17), + GlitchData => LLKRXDATA17_GlitchData, + OutSignalName => "LLKRXDATA(17)", + OutTemp => LLKRXDATA_OUT(17), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(18), + GlitchData => LLKRXDATA18_GlitchData, + OutSignalName => "LLKRXDATA(18)", + OutTemp => LLKRXDATA_OUT(18), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(18), + GlitchData => LLKRXDATA18_GlitchData, + OutSignalName => "LLKRXDATA(18)", + OutTemp => LLKRXDATA_OUT(18), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(19), + GlitchData => LLKRXDATA19_GlitchData, + OutSignalName => "LLKRXDATA(19)", + OutTemp => LLKRXDATA_OUT(19), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(19), + GlitchData => LLKRXDATA19_GlitchData, + OutSignalName => "LLKRXDATA(19)", + OutTemp => LLKRXDATA_OUT(19), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(20), + GlitchData => LLKRXDATA20_GlitchData, + OutSignalName => "LLKRXDATA(20)", + OutTemp => LLKRXDATA_OUT(20), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(20), + GlitchData => LLKRXDATA20_GlitchData, + OutSignalName => "LLKRXDATA(20)", + OutTemp => LLKRXDATA_OUT(20), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(21), + GlitchData => LLKRXDATA21_GlitchData, + OutSignalName => "LLKRXDATA(21)", + OutTemp => LLKRXDATA_OUT(21), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(21), + GlitchData => LLKRXDATA21_GlitchData, + OutSignalName => "LLKRXDATA(21)", + OutTemp => LLKRXDATA_OUT(21), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(22), + GlitchData => LLKRXDATA22_GlitchData, + OutSignalName => "LLKRXDATA(22)", + OutTemp => LLKRXDATA_OUT(22), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(22), + GlitchData => LLKRXDATA22_GlitchData, + OutSignalName => "LLKRXDATA(22)", + OutTemp => LLKRXDATA_OUT(22), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(23), + GlitchData => LLKRXDATA23_GlitchData, + OutSignalName => "LLKRXDATA(23)", + OutTemp => LLKRXDATA_OUT(23), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(23), + GlitchData => LLKRXDATA23_GlitchData, + OutSignalName => "LLKRXDATA(23)", + OutTemp => LLKRXDATA_OUT(23), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(24), + GlitchData => LLKRXDATA24_GlitchData, + OutSignalName => "LLKRXDATA(24)", + OutTemp => LLKRXDATA_OUT(24), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(24), + GlitchData => LLKRXDATA24_GlitchData, + OutSignalName => "LLKRXDATA(24)", + OutTemp => LLKRXDATA_OUT(24), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(25), + GlitchData => LLKRXDATA25_GlitchData, + OutSignalName => "LLKRXDATA(25)", + OutTemp => LLKRXDATA_OUT(25), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(25), + GlitchData => LLKRXDATA25_GlitchData, + OutSignalName => "LLKRXDATA(25)", + OutTemp => LLKRXDATA_OUT(25), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(26), + GlitchData => LLKRXDATA26_GlitchData, + OutSignalName => "LLKRXDATA(26)", + OutTemp => LLKRXDATA_OUT(26), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(26), + GlitchData => LLKRXDATA26_GlitchData, + OutSignalName => "LLKRXDATA(26)", + OutTemp => LLKRXDATA_OUT(26), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(27), + GlitchData => LLKRXDATA27_GlitchData, + OutSignalName => "LLKRXDATA(27)", + OutTemp => LLKRXDATA_OUT(27), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(27), + GlitchData => LLKRXDATA27_GlitchData, + OutSignalName => "LLKRXDATA(27)", + OutTemp => LLKRXDATA_OUT(27), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(28), + GlitchData => LLKRXDATA28_GlitchData, + OutSignalName => "LLKRXDATA(28)", + OutTemp => LLKRXDATA_OUT(28), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(28), + GlitchData => LLKRXDATA28_GlitchData, + OutSignalName => "LLKRXDATA(28)", + OutTemp => LLKRXDATA_OUT(28), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(29), + GlitchData => LLKRXDATA29_GlitchData, + OutSignalName => "LLKRXDATA(29)", + OutTemp => LLKRXDATA_OUT(29), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(29), + GlitchData => LLKRXDATA29_GlitchData, + OutSignalName => "LLKRXDATA(29)", + OutTemp => LLKRXDATA_OUT(29), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(30), + GlitchData => LLKRXDATA30_GlitchData, + OutSignalName => "LLKRXDATA(30)", + OutTemp => LLKRXDATA_OUT(30), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(30), + GlitchData => LLKRXDATA30_GlitchData, + OutSignalName => "LLKRXDATA(30)", + OutTemp => LLKRXDATA_OUT(30), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(31), + GlitchData => LLKRXDATA31_GlitchData, + OutSignalName => "LLKRXDATA(31)", + OutTemp => LLKRXDATA_OUT(31), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(31), + GlitchData => LLKRXDATA31_GlitchData, + OutSignalName => "LLKRXDATA(31)", + OutTemp => LLKRXDATA_OUT(31), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(32), + GlitchData => LLKRXDATA32_GlitchData, + OutSignalName => "LLKRXDATA(32)", + OutTemp => LLKRXDATA_OUT(32), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(32), + GlitchData => LLKRXDATA32_GlitchData, + OutSignalName => "LLKRXDATA(32)", + OutTemp => LLKRXDATA_OUT(32), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(33), + GlitchData => LLKRXDATA33_GlitchData, + OutSignalName => "LLKRXDATA(33)", + OutTemp => LLKRXDATA_OUT(33), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(33), + GlitchData => LLKRXDATA33_GlitchData, + OutSignalName => "LLKRXDATA(33)", + OutTemp => LLKRXDATA_OUT(33), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(34), + GlitchData => LLKRXDATA34_GlitchData, + OutSignalName => "LLKRXDATA(34)", + OutTemp => LLKRXDATA_OUT(34), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(34), + GlitchData => LLKRXDATA34_GlitchData, + OutSignalName => "LLKRXDATA(34)", + OutTemp => LLKRXDATA_OUT(34), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(35), + GlitchData => LLKRXDATA35_GlitchData, + OutSignalName => "LLKRXDATA(35)", + OutTemp => LLKRXDATA_OUT(35), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(35), + GlitchData => LLKRXDATA35_GlitchData, + OutSignalName => "LLKRXDATA(35)", + OutTemp => LLKRXDATA_OUT(35), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(36), + GlitchData => LLKRXDATA36_GlitchData, + OutSignalName => "LLKRXDATA(36)", + OutTemp => LLKRXDATA_OUT(36), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(36), + GlitchData => LLKRXDATA36_GlitchData, + OutSignalName => "LLKRXDATA(36)", + OutTemp => LLKRXDATA_OUT(36), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(37), + GlitchData => LLKRXDATA37_GlitchData, + OutSignalName => "LLKRXDATA(37)", + OutTemp => LLKRXDATA_OUT(37), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(37), + GlitchData => LLKRXDATA37_GlitchData, + OutSignalName => "LLKRXDATA(37)", + OutTemp => LLKRXDATA_OUT(37), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(38), + GlitchData => LLKRXDATA38_GlitchData, + OutSignalName => "LLKRXDATA(38)", + OutTemp => LLKRXDATA_OUT(38), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(38), + GlitchData => LLKRXDATA38_GlitchData, + OutSignalName => "LLKRXDATA(38)", + OutTemp => LLKRXDATA_OUT(38), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(39), + GlitchData => LLKRXDATA39_GlitchData, + OutSignalName => "LLKRXDATA(39)", + OutTemp => LLKRXDATA_OUT(39), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(39), + GlitchData => LLKRXDATA39_GlitchData, + OutSignalName => "LLKRXDATA(39)", + OutTemp => LLKRXDATA_OUT(39), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(40), + GlitchData => LLKRXDATA40_GlitchData, + OutSignalName => "LLKRXDATA(40)", + OutTemp => LLKRXDATA_OUT(40), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(40), + GlitchData => LLKRXDATA40_GlitchData, + OutSignalName => "LLKRXDATA(40)", + OutTemp => LLKRXDATA_OUT(40), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(41), + GlitchData => LLKRXDATA41_GlitchData, + OutSignalName => "LLKRXDATA(41)", + OutTemp => LLKRXDATA_OUT(41), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(41), + GlitchData => LLKRXDATA41_GlitchData, + OutSignalName => "LLKRXDATA(41)", + OutTemp => LLKRXDATA_OUT(41), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(42), + GlitchData => LLKRXDATA42_GlitchData, + OutSignalName => "LLKRXDATA(42)", + OutTemp => LLKRXDATA_OUT(42), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(42), + GlitchData => LLKRXDATA42_GlitchData, + OutSignalName => "LLKRXDATA(42)", + OutTemp => LLKRXDATA_OUT(42), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(43), + GlitchData => LLKRXDATA43_GlitchData, + OutSignalName => "LLKRXDATA(43)", + OutTemp => LLKRXDATA_OUT(43), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(43), + GlitchData => LLKRXDATA43_GlitchData, + OutSignalName => "LLKRXDATA(43)", + OutTemp => LLKRXDATA_OUT(43), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(44), + GlitchData => LLKRXDATA44_GlitchData, + OutSignalName => "LLKRXDATA(44)", + OutTemp => LLKRXDATA_OUT(44), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(44), + GlitchData => LLKRXDATA44_GlitchData, + OutSignalName => "LLKRXDATA(44)", + OutTemp => LLKRXDATA_OUT(44), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(45), + GlitchData => LLKRXDATA45_GlitchData, + OutSignalName => "LLKRXDATA(45)", + OutTemp => LLKRXDATA_OUT(45), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(45), + GlitchData => LLKRXDATA45_GlitchData, + OutSignalName => "LLKRXDATA(45)", + OutTemp => LLKRXDATA_OUT(45), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(46), + GlitchData => LLKRXDATA46_GlitchData, + OutSignalName => "LLKRXDATA(46)", + OutTemp => LLKRXDATA_OUT(46), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(46), + GlitchData => LLKRXDATA46_GlitchData, + OutSignalName => "LLKRXDATA(46)", + OutTemp => LLKRXDATA_OUT(46), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(47), + GlitchData => LLKRXDATA47_GlitchData, + OutSignalName => "LLKRXDATA(47)", + OutTemp => LLKRXDATA_OUT(47), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(47), + GlitchData => LLKRXDATA47_GlitchData, + OutSignalName => "LLKRXDATA(47)", + OutTemp => LLKRXDATA_OUT(47), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(48), + GlitchData => LLKRXDATA48_GlitchData, + OutSignalName => "LLKRXDATA(48)", + OutTemp => LLKRXDATA_OUT(48), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(48), + GlitchData => LLKRXDATA48_GlitchData, + OutSignalName => "LLKRXDATA(48)", + OutTemp => LLKRXDATA_OUT(48), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(49), + GlitchData => LLKRXDATA49_GlitchData, + OutSignalName => "LLKRXDATA(49)", + OutTemp => LLKRXDATA_OUT(49), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(49), + GlitchData => LLKRXDATA49_GlitchData, + OutSignalName => "LLKRXDATA(49)", + OutTemp => LLKRXDATA_OUT(49), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(50), + GlitchData => LLKRXDATA50_GlitchData, + OutSignalName => "LLKRXDATA(50)", + OutTemp => LLKRXDATA_OUT(50), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(50), + GlitchData => LLKRXDATA50_GlitchData, + OutSignalName => "LLKRXDATA(50)", + OutTemp => LLKRXDATA_OUT(50), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(51), + GlitchData => LLKRXDATA51_GlitchData, + OutSignalName => "LLKRXDATA(51)", + OutTemp => LLKRXDATA_OUT(51), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(51), + GlitchData => LLKRXDATA51_GlitchData, + OutSignalName => "LLKRXDATA(51)", + OutTemp => LLKRXDATA_OUT(51), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(52), + GlitchData => LLKRXDATA52_GlitchData, + OutSignalName => "LLKRXDATA(52)", + OutTemp => LLKRXDATA_OUT(52), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(52), + GlitchData => LLKRXDATA52_GlitchData, + OutSignalName => "LLKRXDATA(52)", + OutTemp => LLKRXDATA_OUT(52), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(53), + GlitchData => LLKRXDATA53_GlitchData, + OutSignalName => "LLKRXDATA(53)", + OutTemp => LLKRXDATA_OUT(53), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(53), + GlitchData => LLKRXDATA53_GlitchData, + OutSignalName => "LLKRXDATA(53)", + OutTemp => LLKRXDATA_OUT(53), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(54), + GlitchData => LLKRXDATA54_GlitchData, + OutSignalName => "LLKRXDATA(54)", + OutTemp => LLKRXDATA_OUT(54), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(54), + GlitchData => LLKRXDATA54_GlitchData, + OutSignalName => "LLKRXDATA(54)", + OutTemp => LLKRXDATA_OUT(54), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(55), + GlitchData => LLKRXDATA55_GlitchData, + OutSignalName => "LLKRXDATA(55)", + OutTemp => LLKRXDATA_OUT(55), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(55), + GlitchData => LLKRXDATA55_GlitchData, + OutSignalName => "LLKRXDATA(55)", + OutTemp => LLKRXDATA_OUT(55), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(56), + GlitchData => LLKRXDATA56_GlitchData, + OutSignalName => "LLKRXDATA(56)", + OutTemp => LLKRXDATA_OUT(56), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(56), + GlitchData => LLKRXDATA56_GlitchData, + OutSignalName => "LLKRXDATA(56)", + OutTemp => LLKRXDATA_OUT(56), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(57), + GlitchData => LLKRXDATA57_GlitchData, + OutSignalName => "LLKRXDATA(57)", + OutTemp => LLKRXDATA_OUT(57), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(57), + GlitchData => LLKRXDATA57_GlitchData, + OutSignalName => "LLKRXDATA(57)", + OutTemp => LLKRXDATA_OUT(57), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(58), + GlitchData => LLKRXDATA58_GlitchData, + OutSignalName => "LLKRXDATA(58)", + OutTemp => LLKRXDATA_OUT(58), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(58), + GlitchData => LLKRXDATA58_GlitchData, + OutSignalName => "LLKRXDATA(58)", + OutTemp => LLKRXDATA_OUT(58), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(59), + GlitchData => LLKRXDATA59_GlitchData, + OutSignalName => "LLKRXDATA(59)", + OutTemp => LLKRXDATA_OUT(59), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(59), + GlitchData => LLKRXDATA59_GlitchData, + OutSignalName => "LLKRXDATA(59)", + OutTemp => LLKRXDATA_OUT(59), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(60), + GlitchData => LLKRXDATA60_GlitchData, + OutSignalName => "LLKRXDATA(60)", + OutTemp => LLKRXDATA_OUT(60), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(60), + GlitchData => LLKRXDATA60_GlitchData, + OutSignalName => "LLKRXDATA(60)", + OutTemp => LLKRXDATA_OUT(60), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(61), + GlitchData => LLKRXDATA61_GlitchData, + OutSignalName => "LLKRXDATA(61)", + OutTemp => LLKRXDATA_OUT(61), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(61), + GlitchData => LLKRXDATA61_GlitchData, + OutSignalName => "LLKRXDATA(61)", + OutTemp => LLKRXDATA_OUT(61), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(62), + GlitchData => LLKRXDATA62_GlitchData, + OutSignalName => "LLKRXDATA(62)", + OutTemp => LLKRXDATA_OUT(62), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(62), + GlitchData => LLKRXDATA62_GlitchData, + OutSignalName => "LLKRXDATA(62)", + OutTemp => LLKRXDATA_OUT(62), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(63), + GlitchData => LLKRXDATA63_GlitchData, + OutSignalName => "LLKRXDATA(63)", + OutTemp => LLKRXDATA_OUT(63), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(63), + GlitchData => LLKRXDATA63_GlitchData, + OutSignalName => "LLKRXDATA(63)", + OutTemp => LLKRXDATA_OUT(63), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSRCRDYN, + GlitchData => LLKRXSRCRDYN_GlitchData, + OutSignalName => "LLKRXSRCRDYN", + OutTemp => LLKRXSRCRDYN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSRCRDYN, + GlitchData => LLKRXSRCRDYN_GlitchData, + OutSignalName => "LLKRXSRCRDYN", + OutTemp => LLKRXSRCRDYN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSRCLASTREQN, + GlitchData => LLKRXSRCLASTREQN_GlitchData, + OutSignalName => "LLKRXSRCLASTREQN", + OutTemp => LLKRXSRCLASTREQN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSRCLASTREQN, + GlitchData => LLKRXSRCLASTREQN_GlitchData, + OutSignalName => "LLKRXSRCLASTREQN", + OutTemp => LLKRXSRCLASTREQN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSRCDSCN, + GlitchData => LLKRXSRCDSCN_GlitchData, + OutSignalName => "LLKRXSRCDSCN", + OutTemp => LLKRXSRCDSCN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSRCDSCN, + GlitchData => LLKRXSRCDSCN_GlitchData, + OutSignalName => "LLKRXSRCDSCN", + OutTemp => LLKRXSRCDSCN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSOFN, + GlitchData => LLKRXSOFN_GlitchData, + OutSignalName => "LLKRXSOFN", + OutTemp => LLKRXSOFN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSOFN, + GlitchData => LLKRXSOFN_GlitchData, + OutSignalName => "LLKRXSOFN", + OutTemp => LLKRXSOFN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXEOFN, + GlitchData => LLKRXEOFN_GlitchData, + OutSignalName => "LLKRXEOFN", + OutTemp => LLKRXEOFN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXEOFN, + GlitchData => LLKRXEOFN_GlitchData, + OutSignalName => "LLKRXEOFN", + OutTemp => LLKRXEOFN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSOPN, + GlitchData => LLKRXSOPN_GlitchData, + OutSignalName => "LLKRXSOPN", + OutTemp => LLKRXSOPN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSOPN, + GlitchData => LLKRXSOPN_GlitchData, + OutSignalName => "LLKRXSOPN", + OutTemp => LLKRXSOPN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXEOPN, + GlitchData => LLKRXEOPN_GlitchData, + OutSignalName => "LLKRXEOPN", + OutTemp => LLKRXEOPN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXEOPN, + GlitchData => LLKRXEOPN_GlitchData, + OutSignalName => "LLKRXEOPN", + OutTemp => LLKRXEOPN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXVALIDN(0), + GlitchData => LLKRXVALIDN0_GlitchData, + OutSignalName => "LLKRXVALIDN(0)", + OutTemp => LLKRXVALIDN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXVALIDN(0), + GlitchData => LLKRXVALIDN0_GlitchData, + OutSignalName => "LLKRXVALIDN(0)", + OutTemp => LLKRXVALIDN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXVALIDN(1), + GlitchData => LLKRXVALIDN1_GlitchData, + OutSignalName => "LLKRXVALIDN(1)", + OutTemp => LLKRXVALIDN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXVALIDN(1), + GlitchData => LLKRXVALIDN1_GlitchData, + OutSignalName => "LLKRXVALIDN(1)", + OutTemp => LLKRXVALIDN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(0), + GlitchData => LLKRXPREFERREDTYPE0_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(0)", + OutTemp => LLKRXPREFERREDTYPE_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(0), + GlitchData => LLKRXPREFERREDTYPE0_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(0)", + OutTemp => LLKRXPREFERREDTYPE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(1), + GlitchData => LLKRXPREFERREDTYPE1_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(1)", + OutTemp => LLKRXPREFERREDTYPE_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(1), + GlitchData => LLKRXPREFERREDTYPE1_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(1)", + OutTemp => LLKRXPREFERREDTYPE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(2), + GlitchData => LLKRXPREFERREDTYPE2_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(2)", + OutTemp => LLKRXPREFERREDTYPE_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(2), + GlitchData => LLKRXPREFERREDTYPE2_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(2)", + OutTemp => LLKRXPREFERREDTYPE_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(3), + GlitchData => LLKRXPREFERREDTYPE3_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(3)", + OutTemp => LLKRXPREFERREDTYPE_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(3), + GlitchData => LLKRXPREFERREDTYPE3_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(3)", + OutTemp => LLKRXPREFERREDTYPE_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(4), + GlitchData => LLKRXPREFERREDTYPE4_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(4)", + OutTemp => LLKRXPREFERREDTYPE_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(4), + GlitchData => LLKRXPREFERREDTYPE4_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(4)", + OutTemp => LLKRXPREFERREDTYPE_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(5), + GlitchData => LLKRXPREFERREDTYPE5_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(5)", + OutTemp => LLKRXPREFERREDTYPE_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(5), + GlitchData => LLKRXPREFERREDTYPE5_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(5)", + OutTemp => LLKRXPREFERREDTYPE_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(6), + GlitchData => LLKRXPREFERREDTYPE6_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(6)", + OutTemp => LLKRXPREFERREDTYPE_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(6), + GlitchData => LLKRXPREFERREDTYPE6_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(6)", + OutTemp => LLKRXPREFERREDTYPE_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(7), + GlitchData => LLKRXPREFERREDTYPE7_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(7)", + OutTemp => LLKRXPREFERREDTYPE_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(7), + GlitchData => LLKRXPREFERREDTYPE7_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(7)", + OutTemp => LLKRXPREFERREDTYPE_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(8), + GlitchData => LLKRXPREFERREDTYPE8_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(8)", + OutTemp => LLKRXPREFERREDTYPE_OUT(8), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(8), + GlitchData => LLKRXPREFERREDTYPE8_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(8)", + OutTemp => LLKRXPREFERREDTYPE_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(9), + GlitchData => LLKRXPREFERREDTYPE9_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(9)", + OutTemp => LLKRXPREFERREDTYPE_OUT(9), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(9), + GlitchData => LLKRXPREFERREDTYPE9_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(9)", + OutTemp => LLKRXPREFERREDTYPE_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(10), + GlitchData => LLKRXPREFERREDTYPE10_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(10)", + OutTemp => LLKRXPREFERREDTYPE_OUT(10), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(10), + GlitchData => LLKRXPREFERREDTYPE10_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(10)", + OutTemp => LLKRXPREFERREDTYPE_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(11), + GlitchData => LLKRXPREFERREDTYPE11_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(11)", + OutTemp => LLKRXPREFERREDTYPE_OUT(11), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(11), + GlitchData => LLKRXPREFERREDTYPE11_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(11)", + OutTemp => LLKRXPREFERREDTYPE_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(12), + GlitchData => LLKRXPREFERREDTYPE12_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(12)", + OutTemp => LLKRXPREFERREDTYPE_OUT(12), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(12), + GlitchData => LLKRXPREFERREDTYPE12_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(12)", + OutTemp => LLKRXPREFERREDTYPE_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(13), + GlitchData => LLKRXPREFERREDTYPE13_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(13)", + OutTemp => LLKRXPREFERREDTYPE_OUT(13), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(13), + GlitchData => LLKRXPREFERREDTYPE13_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(13)", + OutTemp => LLKRXPREFERREDTYPE_OUT(13), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(14), + GlitchData => LLKRXPREFERREDTYPE14_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(14)", + OutTemp => LLKRXPREFERREDTYPE_OUT(14), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(14), + GlitchData => LLKRXPREFERREDTYPE14_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(14)", + OutTemp => LLKRXPREFERREDTYPE_OUT(14), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(15), + GlitchData => LLKRXPREFERREDTYPE15_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(15)", + OutTemp => LLKRXPREFERREDTYPE_OUT(15), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(15), + GlitchData => LLKRXPREFERREDTYPE15_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(15)", + OutTemp => LLKRXPREFERREDTYPE_OUT(15), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(0), + GlitchData => LLKRXCHPOSTEDAVAILABLEN0_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(0)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(0), + GlitchData => LLKRXCHPOSTEDAVAILABLEN0_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(0)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(1), + GlitchData => LLKRXCHPOSTEDAVAILABLEN1_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(1)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(1), + GlitchData => LLKRXCHPOSTEDAVAILABLEN1_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(1)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(2), + GlitchData => LLKRXCHPOSTEDAVAILABLEN2_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(2)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(2), + GlitchData => LLKRXCHPOSTEDAVAILABLEN2_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(2)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(3), + GlitchData => LLKRXCHPOSTEDAVAILABLEN3_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(3)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(3), + GlitchData => LLKRXCHPOSTEDAVAILABLEN3_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(3)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(4), + GlitchData => LLKRXCHPOSTEDAVAILABLEN4_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(4)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(4), + GlitchData => LLKRXCHPOSTEDAVAILABLEN4_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(4)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(5), + GlitchData => LLKRXCHPOSTEDAVAILABLEN5_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(5)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(5), + GlitchData => LLKRXCHPOSTEDAVAILABLEN5_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(5)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(6), + GlitchData => LLKRXCHPOSTEDAVAILABLEN6_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(6)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(6), + GlitchData => LLKRXCHPOSTEDAVAILABLEN6_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(6)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(7), + GlitchData => LLKRXCHPOSTEDAVAILABLEN7_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(7)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(7), + GlitchData => LLKRXCHPOSTEDAVAILABLEN7_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(7)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(0), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN0_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(0)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(0), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN0_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(0)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(1), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN1_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(1)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(1), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN1_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(1)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(2), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN2_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(2)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(2), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN2_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(2)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(3), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN3_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(3)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(3), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN3_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(3)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(4), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN4_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(4)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(4), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN4_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(4)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(5), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN5_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(5)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(5), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN5_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(5)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(6), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN6_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(6)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(6), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN6_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(6)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(7), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN7_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(7)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(7), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN7_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(7)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(0), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN0_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(0)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(0), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN0_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(0)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(1), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN1_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(1)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(1), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN1_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(1)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(2), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN2_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(2)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(2), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN2_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(2)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(3), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN3_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(3)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(3), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN3_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(3)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(4), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN4_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(4)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(4), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN4_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(4)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(5), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN5_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(5)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(5), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN5_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(5)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(6), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN6_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(6)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(6), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN6_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(6)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(7), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN7_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(7)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(7), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN7_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(7)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCONFIGAVAILABLEN, + GlitchData => LLKRXCHCONFIGAVAILABLEN_GlitchData, + OutSignalName => "LLKRXCHCONFIGAVAILABLEN", + OutTemp => LLKRXCHCONFIGAVAILABLEN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCONFIGAVAILABLEN, + GlitchData => LLKRXCHCONFIGAVAILABLEN_GlitchData, + OutSignalName => "LLKRXCHCONFIGAVAILABLEN", + OutTemp => LLKRXCHCONFIGAVAILABLEN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(0), + GlitchData => LLKRXCHPOSTEDPARTIALN0_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(0)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(0), + GlitchData => LLKRXCHPOSTEDPARTIALN0_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(0)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(1), + GlitchData => LLKRXCHPOSTEDPARTIALN1_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(1)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(1), + GlitchData => LLKRXCHPOSTEDPARTIALN1_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(1)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(2), + GlitchData => LLKRXCHPOSTEDPARTIALN2_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(2)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(2), + GlitchData => LLKRXCHPOSTEDPARTIALN2_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(2)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(3), + GlitchData => LLKRXCHPOSTEDPARTIALN3_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(3)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(3), + GlitchData => LLKRXCHPOSTEDPARTIALN3_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(3)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(4), + GlitchData => LLKRXCHPOSTEDPARTIALN4_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(4)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(4), + GlitchData => LLKRXCHPOSTEDPARTIALN4_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(4)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(5), + GlitchData => LLKRXCHPOSTEDPARTIALN5_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(5)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(5), + GlitchData => LLKRXCHPOSTEDPARTIALN5_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(5)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(6), + GlitchData => LLKRXCHPOSTEDPARTIALN6_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(6)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(6), + GlitchData => LLKRXCHPOSTEDPARTIALN6_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(6)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(7), + GlitchData => LLKRXCHPOSTEDPARTIALN7_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(7)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(7), + GlitchData => LLKRXCHPOSTEDPARTIALN7_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(7)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(0), + GlitchData => LLKRXCHNONPOSTEDPARTIALN0_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(0)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(0), + GlitchData => LLKRXCHNONPOSTEDPARTIALN0_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(0)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(1), + GlitchData => LLKRXCHNONPOSTEDPARTIALN1_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(1)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(1), + GlitchData => LLKRXCHNONPOSTEDPARTIALN1_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(1)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(2), + GlitchData => LLKRXCHNONPOSTEDPARTIALN2_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(2)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(2), + GlitchData => LLKRXCHNONPOSTEDPARTIALN2_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(2)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(3), + GlitchData => LLKRXCHNONPOSTEDPARTIALN3_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(3)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(3), + GlitchData => LLKRXCHNONPOSTEDPARTIALN3_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(3)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(4), + GlitchData => LLKRXCHNONPOSTEDPARTIALN4_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(4)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(4), + GlitchData => LLKRXCHNONPOSTEDPARTIALN4_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(4)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(5), + GlitchData => LLKRXCHNONPOSTEDPARTIALN5_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(5)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(5), + GlitchData => LLKRXCHNONPOSTEDPARTIALN5_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(5)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(6), + GlitchData => LLKRXCHNONPOSTEDPARTIALN6_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(6)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(6), + GlitchData => LLKRXCHNONPOSTEDPARTIALN6_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(6)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(7), + GlitchData => LLKRXCHNONPOSTEDPARTIALN7_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(7)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(7), + GlitchData => LLKRXCHNONPOSTEDPARTIALN7_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(7)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(0), + GlitchData => LLKRXCHCOMPLETIONPARTIALN0_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(0)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(0), + GlitchData => LLKRXCHCOMPLETIONPARTIALN0_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(0)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(1), + GlitchData => LLKRXCHCOMPLETIONPARTIALN1_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(1)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(1), + GlitchData => LLKRXCHCOMPLETIONPARTIALN1_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(1)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(2), + GlitchData => LLKRXCHCOMPLETIONPARTIALN2_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(2)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(2), + GlitchData => LLKRXCHCOMPLETIONPARTIALN2_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(2)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(3), + GlitchData => LLKRXCHCOMPLETIONPARTIALN3_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(3)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(3), + GlitchData => LLKRXCHCOMPLETIONPARTIALN3_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(3)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(4), + GlitchData => LLKRXCHCOMPLETIONPARTIALN4_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(4)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(4), + GlitchData => LLKRXCHCOMPLETIONPARTIALN4_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(4)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(5), + GlitchData => LLKRXCHCOMPLETIONPARTIALN5_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(5)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(5), + GlitchData => LLKRXCHCOMPLETIONPARTIALN5_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(5)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(6), + GlitchData => LLKRXCHCOMPLETIONPARTIALN6_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(6)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(6), + GlitchData => LLKRXCHCOMPLETIONPARTIALN6_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(6)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(7), + GlitchData => LLKRXCHCOMPLETIONPARTIALN7_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(7)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(7), + GlitchData => LLKRXCHCOMPLETIONPARTIALN7_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(7)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCONFIGPARTIALN, + GlitchData => LLKRXCHCONFIGPARTIALN_GlitchData, + OutSignalName => "LLKRXCHCONFIGPARTIALN", + OutTemp => LLKRXCHCONFIGPARTIALN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCONFIGPARTIALN, + GlitchData => LLKRXCHCONFIGPARTIALN_GlitchData, + OutSignalName => "LLKRXCHCONFIGPARTIALN", + OutTemp => LLKRXCHCONFIGPARTIALN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRX4DWHEADERN, + GlitchData => LLKRX4DWHEADERN_GlitchData, + OutSignalName => "LLKRX4DWHEADERN", + OutTemp => LLKRX4DWHEADERN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRX4DWHEADERN, + GlitchData => LLKRX4DWHEADERN_GlitchData, + OutSignalName => "LLKRX4DWHEADERN", + OutTemp => LLKRX4DWHEADERN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXECRCBADN, + GlitchData => LLKRXECRCBADN_GlitchData, + OutSignalName => "LLKRXECRCBADN", + OutTemp => LLKRXECRCBADN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXECRCBADN, + GlitchData => LLKRXECRCBADN_GlitchData, + OutSignalName => "LLKRXECRCBADN", + OutTemp => LLKRXECRCBADN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(0), + GlitchData => MGMTRDATA0_GlitchData, + OutSignalName => "MGMTRDATA(0)", + OutTemp => MGMTRDATA_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(0), + GlitchData => MGMTRDATA0_GlitchData, + OutSignalName => "MGMTRDATA(0)", + OutTemp => MGMTRDATA_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(1), + GlitchData => MGMTRDATA1_GlitchData, + OutSignalName => "MGMTRDATA(1)", + OutTemp => MGMTRDATA_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(1), + GlitchData => MGMTRDATA1_GlitchData, + OutSignalName => "MGMTRDATA(1)", + OutTemp => MGMTRDATA_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(2), + GlitchData => MGMTRDATA2_GlitchData, + OutSignalName => "MGMTRDATA(2)", + OutTemp => MGMTRDATA_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(2), + GlitchData => MGMTRDATA2_GlitchData, + OutSignalName => "MGMTRDATA(2)", + OutTemp => MGMTRDATA_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(3), + GlitchData => MGMTRDATA3_GlitchData, + OutSignalName => "MGMTRDATA(3)", + OutTemp => MGMTRDATA_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(3), + GlitchData => MGMTRDATA3_GlitchData, + OutSignalName => "MGMTRDATA(3)", + OutTemp => MGMTRDATA_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(4), + GlitchData => MGMTRDATA4_GlitchData, + OutSignalName => "MGMTRDATA(4)", + OutTemp => MGMTRDATA_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(4), + GlitchData => MGMTRDATA4_GlitchData, + OutSignalName => "MGMTRDATA(4)", + OutTemp => MGMTRDATA_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(5), + GlitchData => MGMTRDATA5_GlitchData, + OutSignalName => "MGMTRDATA(5)", + OutTemp => MGMTRDATA_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(5), + GlitchData => MGMTRDATA5_GlitchData, + OutSignalName => "MGMTRDATA(5)", + OutTemp => MGMTRDATA_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(6), + GlitchData => MGMTRDATA6_GlitchData, + OutSignalName => "MGMTRDATA(6)", + OutTemp => MGMTRDATA_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(6), + GlitchData => MGMTRDATA6_GlitchData, + OutSignalName => "MGMTRDATA(6)", + OutTemp => MGMTRDATA_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(7), + GlitchData => MGMTRDATA7_GlitchData, + OutSignalName => "MGMTRDATA(7)", + OutTemp => MGMTRDATA_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(7), + GlitchData => MGMTRDATA7_GlitchData, + OutSignalName => "MGMTRDATA(7)", + OutTemp => MGMTRDATA_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(8), + GlitchData => MGMTRDATA8_GlitchData, + OutSignalName => "MGMTRDATA(8)", + OutTemp => MGMTRDATA_OUT(8), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(8), + GlitchData => MGMTRDATA8_GlitchData, + OutSignalName => "MGMTRDATA(8)", + OutTemp => MGMTRDATA_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(9), + GlitchData => MGMTRDATA9_GlitchData, + OutSignalName => "MGMTRDATA(9)", + OutTemp => MGMTRDATA_OUT(9), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(9), + GlitchData => MGMTRDATA9_GlitchData, + OutSignalName => "MGMTRDATA(9)", + OutTemp => MGMTRDATA_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(10), + GlitchData => MGMTRDATA10_GlitchData, + OutSignalName => "MGMTRDATA(10)", + OutTemp => MGMTRDATA_OUT(10), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(10), + GlitchData => MGMTRDATA10_GlitchData, + OutSignalName => "MGMTRDATA(10)", + OutTemp => MGMTRDATA_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(11), + GlitchData => MGMTRDATA11_GlitchData, + OutSignalName => "MGMTRDATA(11)", + OutTemp => MGMTRDATA_OUT(11), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(11), + GlitchData => MGMTRDATA11_GlitchData, + OutSignalName => "MGMTRDATA(11)", + OutTemp => MGMTRDATA_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(12), + GlitchData => MGMTRDATA12_GlitchData, + OutSignalName => "MGMTRDATA(12)", + OutTemp => MGMTRDATA_OUT(12), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(12), + GlitchData => MGMTRDATA12_GlitchData, + OutSignalName => "MGMTRDATA(12)", + OutTemp => MGMTRDATA_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(13), + GlitchData => MGMTRDATA13_GlitchData, + OutSignalName => "MGMTRDATA(13)", + OutTemp => MGMTRDATA_OUT(13), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(13), + GlitchData => MGMTRDATA13_GlitchData, + OutSignalName => "MGMTRDATA(13)", + OutTemp => MGMTRDATA_OUT(13), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(14), + GlitchData => MGMTRDATA14_GlitchData, + OutSignalName => "MGMTRDATA(14)", + OutTemp => MGMTRDATA_OUT(14), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(14), + GlitchData => MGMTRDATA14_GlitchData, + OutSignalName => "MGMTRDATA(14)", + OutTemp => MGMTRDATA_OUT(14), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(15), + GlitchData => MGMTRDATA15_GlitchData, + OutSignalName => "MGMTRDATA(15)", + OutTemp => MGMTRDATA_OUT(15), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(15), + GlitchData => MGMTRDATA15_GlitchData, + OutSignalName => "MGMTRDATA(15)", + OutTemp => MGMTRDATA_OUT(15), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(16), + GlitchData => MGMTRDATA16_GlitchData, + OutSignalName => "MGMTRDATA(16)", + OutTemp => MGMTRDATA_OUT(16), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(16), + GlitchData => MGMTRDATA16_GlitchData, + OutSignalName => "MGMTRDATA(16)", + OutTemp => MGMTRDATA_OUT(16), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(17), + GlitchData => MGMTRDATA17_GlitchData, + OutSignalName => "MGMTRDATA(17)", + OutTemp => MGMTRDATA_OUT(17), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(17), + GlitchData => MGMTRDATA17_GlitchData, + OutSignalName => "MGMTRDATA(17)", + OutTemp => MGMTRDATA_OUT(17), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(18), + GlitchData => MGMTRDATA18_GlitchData, + OutSignalName => "MGMTRDATA(18)", + OutTemp => MGMTRDATA_OUT(18), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(18), + GlitchData => MGMTRDATA18_GlitchData, + OutSignalName => "MGMTRDATA(18)", + OutTemp => MGMTRDATA_OUT(18), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(19), + GlitchData => MGMTRDATA19_GlitchData, + OutSignalName => "MGMTRDATA(19)", + OutTemp => MGMTRDATA_OUT(19), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(19), + GlitchData => MGMTRDATA19_GlitchData, + OutSignalName => "MGMTRDATA(19)", + OutTemp => MGMTRDATA_OUT(19), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(20), + GlitchData => MGMTRDATA20_GlitchData, + OutSignalName => "MGMTRDATA(20)", + OutTemp => MGMTRDATA_OUT(20), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(20), + GlitchData => MGMTRDATA20_GlitchData, + OutSignalName => "MGMTRDATA(20)", + OutTemp => MGMTRDATA_OUT(20), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(21), + GlitchData => MGMTRDATA21_GlitchData, + OutSignalName => "MGMTRDATA(21)", + OutTemp => MGMTRDATA_OUT(21), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(21), + GlitchData => MGMTRDATA21_GlitchData, + OutSignalName => "MGMTRDATA(21)", + OutTemp => MGMTRDATA_OUT(21), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(22), + GlitchData => MGMTRDATA22_GlitchData, + OutSignalName => "MGMTRDATA(22)", + OutTemp => MGMTRDATA_OUT(22), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(22), + GlitchData => MGMTRDATA22_GlitchData, + OutSignalName => "MGMTRDATA(22)", + OutTemp => MGMTRDATA_OUT(22), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(23), + GlitchData => MGMTRDATA23_GlitchData, + OutSignalName => "MGMTRDATA(23)", + OutTemp => MGMTRDATA_OUT(23), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(23), + GlitchData => MGMTRDATA23_GlitchData, + OutSignalName => "MGMTRDATA(23)", + OutTemp => MGMTRDATA_OUT(23), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(24), + GlitchData => MGMTRDATA24_GlitchData, + OutSignalName => "MGMTRDATA(24)", + OutTemp => MGMTRDATA_OUT(24), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(24), + GlitchData => MGMTRDATA24_GlitchData, + OutSignalName => "MGMTRDATA(24)", + OutTemp => MGMTRDATA_OUT(24), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(25), + GlitchData => MGMTRDATA25_GlitchData, + OutSignalName => "MGMTRDATA(25)", + OutTemp => MGMTRDATA_OUT(25), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(25), + GlitchData => MGMTRDATA25_GlitchData, + OutSignalName => "MGMTRDATA(25)", + OutTemp => MGMTRDATA_OUT(25), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(26), + GlitchData => MGMTRDATA26_GlitchData, + OutSignalName => "MGMTRDATA(26)", + OutTemp => MGMTRDATA_OUT(26), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(26), + GlitchData => MGMTRDATA26_GlitchData, + OutSignalName => "MGMTRDATA(26)", + OutTemp => MGMTRDATA_OUT(26), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(27), + GlitchData => MGMTRDATA27_GlitchData, + OutSignalName => "MGMTRDATA(27)", + OutTemp => MGMTRDATA_OUT(27), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(27), + GlitchData => MGMTRDATA27_GlitchData, + OutSignalName => "MGMTRDATA(27)", + OutTemp => MGMTRDATA_OUT(27), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(28), + GlitchData => MGMTRDATA28_GlitchData, + OutSignalName => "MGMTRDATA(28)", + OutTemp => MGMTRDATA_OUT(28), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(28), + GlitchData => MGMTRDATA28_GlitchData, + OutSignalName => "MGMTRDATA(28)", + OutTemp => MGMTRDATA_OUT(28), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(29), + GlitchData => MGMTRDATA29_GlitchData, + OutSignalName => "MGMTRDATA(29)", + OutTemp => MGMTRDATA_OUT(29), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(29), + GlitchData => MGMTRDATA29_GlitchData, + OutSignalName => "MGMTRDATA(29)", + OutTemp => MGMTRDATA_OUT(29), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(30), + GlitchData => MGMTRDATA30_GlitchData, + OutSignalName => "MGMTRDATA(30)", + OutTemp => MGMTRDATA_OUT(30), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(30), + GlitchData => MGMTRDATA30_GlitchData, + OutSignalName => "MGMTRDATA(30)", + OutTemp => MGMTRDATA_OUT(30), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(31), + GlitchData => MGMTRDATA31_GlitchData, + OutSignalName => "MGMTRDATA(31)", + OutTemp => MGMTRDATA_OUT(31), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(31), + GlitchData => MGMTRDATA31_GlitchData, + OutSignalName => "MGMTRDATA(31)", + OutTemp => MGMTRDATA_OUT(31), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(0), + GlitchData => MGMTPSO0_GlitchData, + OutSignalName => "MGMTPSO(0)", + OutTemp => MGMTPSO_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(0), + GlitchData => MGMTPSO0_GlitchData, + OutSignalName => "MGMTPSO(0)", + OutTemp => MGMTPSO_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(1), + GlitchData => MGMTPSO1_GlitchData, + OutSignalName => "MGMTPSO(1)", + OutTemp => MGMTPSO_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(1), + GlitchData => MGMTPSO1_GlitchData, + OutSignalName => "MGMTPSO(1)", + OutTemp => MGMTPSO_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(2), + GlitchData => MGMTPSO2_GlitchData, + OutSignalName => "MGMTPSO(2)", + OutTemp => MGMTPSO_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(2), + GlitchData => MGMTPSO2_GlitchData, + OutSignalName => "MGMTPSO(2)", + OutTemp => MGMTPSO_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(3), + GlitchData => MGMTPSO3_GlitchData, + OutSignalName => "MGMTPSO(3)", + OutTemp => MGMTPSO_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(3), + GlitchData => MGMTPSO3_GlitchData, + OutSignalName => "MGMTPSO(3)", + OutTemp => MGMTPSO_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(4), + GlitchData => MGMTPSO4_GlitchData, + OutSignalName => "MGMTPSO(4)", + OutTemp => MGMTPSO_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(4), + GlitchData => MGMTPSO4_GlitchData, + OutSignalName => "MGMTPSO(4)", + OutTemp => MGMTPSO_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(5), + GlitchData => MGMTPSO5_GlitchData, + OutSignalName => "MGMTPSO(5)", + OutTemp => MGMTPSO_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(5), + GlitchData => MGMTPSO5_GlitchData, + OutSignalName => "MGMTPSO(5)", + OutTemp => MGMTPSO_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(6), + GlitchData => MGMTPSO6_GlitchData, + OutSignalName => "MGMTPSO(6)", + OutTemp => MGMTPSO_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(6), + GlitchData => MGMTPSO6_GlitchData, + OutSignalName => "MGMTPSO(6)", + OutTemp => MGMTPSO_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(7), + GlitchData => MGMTPSO7_GlitchData, + OutSignalName => "MGMTPSO(7)", + OutTemp => MGMTPSO_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(7), + GlitchData => MGMTPSO7_GlitchData, + OutSignalName => "MGMTPSO(7)", + OutTemp => MGMTPSO_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(8), + GlitchData => MGMTPSO8_GlitchData, + OutSignalName => "MGMTPSO(8)", + OutTemp => MGMTPSO_OUT(8), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(8), + GlitchData => MGMTPSO8_GlitchData, + OutSignalName => "MGMTPSO(8)", + OutTemp => MGMTPSO_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(9), + GlitchData => MGMTPSO9_GlitchData, + OutSignalName => "MGMTPSO(9)", + OutTemp => MGMTPSO_OUT(9), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(9), + GlitchData => MGMTPSO9_GlitchData, + OutSignalName => "MGMTPSO(9)", + OutTemp => MGMTPSO_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(10), + GlitchData => MGMTPSO10_GlitchData, + OutSignalName => "MGMTPSO(10)", + OutTemp => MGMTPSO_OUT(10), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(10), + GlitchData => MGMTPSO10_GlitchData, + OutSignalName => "MGMTPSO(10)", + OutTemp => MGMTPSO_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(11), + GlitchData => MGMTPSO11_GlitchData, + OutSignalName => "MGMTPSO(11)", + OutTemp => MGMTPSO_OUT(11), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(11), + GlitchData => MGMTPSO11_GlitchData, + OutSignalName => "MGMTPSO(11)", + OutTemp => MGMTPSO_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(12), + GlitchData => MGMTPSO12_GlitchData, + OutSignalName => "MGMTPSO(12)", + OutTemp => MGMTPSO_OUT(12), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(12), + GlitchData => MGMTPSO12_GlitchData, + OutSignalName => "MGMTPSO(12)", + OutTemp => MGMTPSO_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(13), + GlitchData => MGMTPSO13_GlitchData, + OutSignalName => "MGMTPSO(13)", + OutTemp => MGMTPSO_OUT(13), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(13), + GlitchData => MGMTPSO13_GlitchData, + OutSignalName => "MGMTPSO(13)", + OutTemp => MGMTPSO_OUT(13), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(14), + GlitchData => MGMTPSO14_GlitchData, + OutSignalName => "MGMTPSO(14)", + OutTemp => MGMTPSO_OUT(14), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(14), + GlitchData => MGMTPSO14_GlitchData, + OutSignalName => "MGMTPSO(14)", + OutTemp => MGMTPSO_OUT(14), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(15), + GlitchData => MGMTPSO15_GlitchData, + OutSignalName => "MGMTPSO(15)", + OutTemp => MGMTPSO_OUT(15), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(15), + GlitchData => MGMTPSO15_GlitchData, + OutSignalName => "MGMTPSO(15)", + OutTemp => MGMTPSO_OUT(15), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(16), + GlitchData => MGMTPSO16_GlitchData, + OutSignalName => "MGMTPSO(16)", + OutTemp => MGMTPSO_OUT(16), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(16), + GlitchData => MGMTPSO16_GlitchData, + OutSignalName => "MGMTPSO(16)", + OutTemp => MGMTPSO_OUT(16), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(0), + GlitchData => MGMTSTATSCREDIT0_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(0)", + OutTemp => MGMTSTATSCREDIT_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(0), + GlitchData => MGMTSTATSCREDIT0_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(0)", + OutTemp => MGMTSTATSCREDIT_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(1), + GlitchData => MGMTSTATSCREDIT1_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(1)", + OutTemp => MGMTSTATSCREDIT_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(1), + GlitchData => MGMTSTATSCREDIT1_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(1)", + OutTemp => MGMTSTATSCREDIT_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(2), + GlitchData => MGMTSTATSCREDIT2_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(2)", + OutTemp => MGMTSTATSCREDIT_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(2), + GlitchData => MGMTSTATSCREDIT2_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(2)", + OutTemp => MGMTSTATSCREDIT_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(3), + GlitchData => MGMTSTATSCREDIT3_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(3)", + OutTemp => MGMTSTATSCREDIT_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(3), + GlitchData => MGMTSTATSCREDIT3_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(3)", + OutTemp => MGMTSTATSCREDIT_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(4), + GlitchData => MGMTSTATSCREDIT4_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(4)", + OutTemp => MGMTSTATSCREDIT_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(4), + GlitchData => MGMTSTATSCREDIT4_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(4)", + OutTemp => MGMTSTATSCREDIT_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(5), + GlitchData => MGMTSTATSCREDIT5_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(5)", + OutTemp => MGMTSTATSCREDIT_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(5), + GlitchData => MGMTSTATSCREDIT5_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(5)", + OutTemp => MGMTSTATSCREDIT_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(6), + GlitchData => MGMTSTATSCREDIT6_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(6)", + OutTemp => MGMTSTATSCREDIT_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(6), + GlitchData => MGMTSTATSCREDIT6_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(6)", + OutTemp => MGMTSTATSCREDIT_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(7), + GlitchData => MGMTSTATSCREDIT7_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(7)", + OutTemp => MGMTSTATSCREDIT_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(7), + GlitchData => MGMTSTATSCREDIT7_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(7)", + OutTemp => MGMTSTATSCREDIT_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(8), + GlitchData => MGMTSTATSCREDIT8_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(8)", + OutTemp => MGMTSTATSCREDIT_OUT(8), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(8), + GlitchData => MGMTSTATSCREDIT8_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(8)", + OutTemp => MGMTSTATSCREDIT_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(9), + GlitchData => MGMTSTATSCREDIT9_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(9)", + OutTemp => MGMTSTATSCREDIT_OUT(9), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(9), + GlitchData => MGMTSTATSCREDIT9_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(9)", + OutTemp => MGMTSTATSCREDIT_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(10), + GlitchData => MGMTSTATSCREDIT10_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(10)", + OutTemp => MGMTSTATSCREDIT_OUT(10), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(10), + GlitchData => MGMTSTATSCREDIT10_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(10)", + OutTemp => MGMTSTATSCREDIT_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(11), + GlitchData => MGMTSTATSCREDIT11_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(11)", + OutTemp => MGMTSTATSCREDIT_OUT(11), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(11), + GlitchData => MGMTSTATSCREDIT11_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(11)", + OutTemp => MGMTSTATSCREDIT_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLTLPECRCOK, + GlitchData => L0RXDLLTLPECRCOK_GlitchData, + OutSignalName => "L0RXDLLTLPECRCOK", + OutTemp => L0RXDLLTLPECRCOK_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DLLTXPMDLLPOUTSTANDING, + GlitchData => DLLTXPMDLLPOUTSTANDING_GlitchData, + OutSignalName => "DLLTXPMDLLPOUTSTANDING", + OutTemp => DLLTXPMDLLPOUTSTANDING_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FIRSTCFGWRITEOCCURRED, + GlitchData => L0FIRSTCFGWRITEOCCURRED_GlitchData, + OutSignalName => "L0FIRSTCFGWRITEOCCURRED", + OutTemp => L0FIRSTCFGWRITEOCCURRED_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FIRSTCFGWRITEOCCURRED, + GlitchData => L0FIRSTCFGWRITEOCCURRED_GlitchData, + OutSignalName => "L0FIRSTCFGWRITEOCCURRED", + OutTemp => L0FIRSTCFGWRITEOCCURRED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0CFGLOOPBACKACK, + GlitchData => L0CFGLOOPBACKACK_GlitchData, + OutSignalName => "L0CFGLOOPBACKACK", + OutTemp => L0CFGLOOPBACKACK_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACUPSTREAMDOWNSTREAM, + GlitchData => L0MACUPSTREAMDOWNSTREAM_GlitchData, + OutSignalName => "L0MACUPSTREAMDOWNSTREAM", + OutTemp => L0MACUPSTREAMDOWNSTREAM_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXMACLINKERROR(0), + GlitchData => L0RXMACLINKERROR0_GlitchData, + OutSignalName => "L0RXMACLINKERROR(0)", + OutTemp => L0RXMACLINKERROR_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXMACLINKERROR(1), + GlitchData => L0RXMACLINKERROR1_GlitchData, + OutSignalName => "L0RXMACLINKERROR(1)", + OutTemp => L0RXMACLINKERROR_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACLINKUP, + GlitchData => L0MACLINKUP_GlitchData, + OutSignalName => "L0MACLINKUP", + OutTemp => L0MACLINKUP_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACNEGOTIATEDLINKWIDTH(0), + GlitchData => L0MACNEGOTIATEDLINKWIDTH0_GlitchData, + OutSignalName => "L0MACNEGOTIATEDLINKWIDTH(0)", + OutTemp => L0MACNEGOTIATEDLINKWIDTH_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACNEGOTIATEDLINKWIDTH(1), + GlitchData => L0MACNEGOTIATEDLINKWIDTH1_GlitchData, + OutSignalName => "L0MACNEGOTIATEDLINKWIDTH(1)", + OutTemp => L0MACNEGOTIATEDLINKWIDTH_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACNEGOTIATEDLINKWIDTH(2), + GlitchData => L0MACNEGOTIATEDLINKWIDTH2_GlitchData, + OutSignalName => "L0MACNEGOTIATEDLINKWIDTH(2)", + OutTemp => L0MACNEGOTIATEDLINKWIDTH_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACNEGOTIATEDLINKWIDTH(3), + GlitchData => L0MACNEGOTIATEDLINKWIDTH3_GlitchData, + OutSignalName => "L0MACNEGOTIATEDLINKWIDTH(3)", + OutTemp => L0MACNEGOTIATEDLINKWIDTH_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACLINKTRAINING, + GlitchData => L0MACLINKTRAINING_GlitchData, + OutSignalName => "L0MACLINKTRAINING", + OutTemp => L0MACLINKTRAINING_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0LTSSMSTATE(0), + GlitchData => L0LTSSMSTATE0_GlitchData, + OutSignalName => "L0LTSSMSTATE(0)", + OutTemp => L0LTSSMSTATE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0LTSSMSTATE(1), + GlitchData => L0LTSSMSTATE1_GlitchData, + OutSignalName => "L0LTSSMSTATE(1)", + OutTemp => L0LTSSMSTATE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0LTSSMSTATE(2), + GlitchData => L0LTSSMSTATE2_GlitchData, + OutSignalName => "L0LTSSMSTATE(2)", + OutTemp => L0LTSSMSTATE_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0LTSSMSTATE(3), + GlitchData => L0LTSSMSTATE3_GlitchData, + OutSignalName => "L0LTSSMSTATE(3)", + OutTemp => L0LTSSMSTATE_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLVCSTATUS(0), + GlitchData => L0DLLVCSTATUS0_GlitchData, + OutSignalName => "L0DLLVCSTATUS(0)", + OutTemp => L0DLLVCSTATUS_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLVCSTATUS(1), + GlitchData => L0DLLVCSTATUS1_GlitchData, + OutSignalName => "L0DLLVCSTATUS(1)", + OutTemp => L0DLLVCSTATUS_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLVCSTATUS(2), + GlitchData => L0DLLVCSTATUS2_GlitchData, + OutSignalName => "L0DLLVCSTATUS(2)", + OutTemp => L0DLLVCSTATUS_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLVCSTATUS(3), + GlitchData => L0DLLVCSTATUS3_GlitchData, + OutSignalName => "L0DLLVCSTATUS(3)", + OutTemp => L0DLLVCSTATUS_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLVCSTATUS(4), + GlitchData => L0DLLVCSTATUS4_GlitchData, + OutSignalName => "L0DLLVCSTATUS(4)", + OutTemp => L0DLLVCSTATUS_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLVCSTATUS(5), + GlitchData => L0DLLVCSTATUS5_GlitchData, + OutSignalName => "L0DLLVCSTATUS(5)", + OutTemp => L0DLLVCSTATUS_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLVCSTATUS(6), + GlitchData => L0DLLVCSTATUS6_GlitchData, + OutSignalName => "L0DLLVCSTATUS(6)", + OutTemp => L0DLLVCSTATUS_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLVCSTATUS(7), + GlitchData => L0DLLVCSTATUS7_GlitchData, + OutSignalName => "L0DLLVCSTATUS(7)", + OutTemp => L0DLLVCSTATUS_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLUPDOWN(0), + GlitchData => L0DLUPDOWN0_GlitchData, + OutSignalName => "L0DLUPDOWN(0)", + OutTemp => L0DLUPDOWN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLUPDOWN(1), + GlitchData => L0DLUPDOWN1_GlitchData, + OutSignalName => "L0DLUPDOWN(1)", + OutTemp => L0DLUPDOWN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLUPDOWN(2), + GlitchData => L0DLUPDOWN2_GlitchData, + OutSignalName => "L0DLUPDOWN(2)", + OutTemp => L0DLUPDOWN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLUPDOWN(3), + GlitchData => L0DLUPDOWN3_GlitchData, + OutSignalName => "L0DLUPDOWN(3)", + OutTemp => L0DLUPDOWN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLUPDOWN(4), + GlitchData => L0DLUPDOWN4_GlitchData, + OutSignalName => "L0DLUPDOWN(4)", + OutTemp => L0DLUPDOWN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLUPDOWN(5), + GlitchData => L0DLUPDOWN5_GlitchData, + OutSignalName => "L0DLUPDOWN(5)", + OutTemp => L0DLUPDOWN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLUPDOWN(6), + GlitchData => L0DLUPDOWN6_GlitchData, + OutSignalName => "L0DLUPDOWN(6)", + OutTemp => L0DLUPDOWN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLUPDOWN(7), + GlitchData => L0DLUPDOWN7_GlitchData, + OutSignalName => "L0DLUPDOWN(7)", + OutTemp => L0DLUPDOWN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLERRORVECTOR(0), + GlitchData => L0DLLERRORVECTOR0_GlitchData, + OutSignalName => "L0DLLERRORVECTOR(0)", + OutTemp => L0DLLERRORVECTOR_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLERRORVECTOR(1), + GlitchData => L0DLLERRORVECTOR1_GlitchData, + OutSignalName => "L0DLLERRORVECTOR(1)", + OutTemp => L0DLLERRORVECTOR_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLERRORVECTOR(2), + GlitchData => L0DLLERRORVECTOR2_GlitchData, + OutSignalName => "L0DLLERRORVECTOR(2)", + OutTemp => L0DLLERRORVECTOR_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLERRORVECTOR(3), + GlitchData => L0DLLERRORVECTOR3_GlitchData, + OutSignalName => "L0DLLERRORVECTOR(3)", + OutTemp => L0DLLERRORVECTOR_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLERRORVECTOR(4), + GlitchData => L0DLLERRORVECTOR4_GlitchData, + OutSignalName => "L0DLLERRORVECTOR(4)", + OutTemp => L0DLLERRORVECTOR_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLERRORVECTOR(5), + GlitchData => L0DLLERRORVECTOR5_GlitchData, + OutSignalName => "L0DLLERRORVECTOR(5)", + OutTemp => L0DLLERRORVECTOR_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLERRORVECTOR(6), + GlitchData => L0DLLERRORVECTOR6_GlitchData, + OutSignalName => "L0DLLERRORVECTOR(6)", + OutTemp => L0DLLERRORVECTOR_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLASRXSTATE(0), + GlitchData => L0DLLASRXSTATE0_GlitchData, + OutSignalName => "L0DLLASRXSTATE(0)", + OutTemp => L0DLLASRXSTATE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLASRXSTATE(1), + GlitchData => L0DLLASRXSTATE1_GlitchData, + OutSignalName => "L0DLLASRXSTATE(1)", + OutTemp => L0DLLASRXSTATE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLASTXSTATE, + GlitchData => L0DLLASTXSTATE_GlitchData, + OutSignalName => "L0DLLASTXSTATE", + OutTemp => L0DLLASTXSTATE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ASAUTONOMOUSINITCOMPLETED, + GlitchData => L0ASAUTONOMOUSINITCOMPLETED_GlitchData, + OutSignalName => "L0ASAUTONOMOUSINITCOMPLETED", + OutTemp => L0ASAUTONOMOUSINITCOMPLETED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(0), + GlitchData => L0COMPLETERID0_GlitchData, + OutSignalName => "L0COMPLETERID(0)", + OutTemp => L0COMPLETERID_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(0), + GlitchData => L0COMPLETERID0_GlitchData, + OutSignalName => "L0COMPLETERID(0)", + OutTemp => L0COMPLETERID_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(1), + GlitchData => L0COMPLETERID1_GlitchData, + OutSignalName => "L0COMPLETERID(1)", + OutTemp => L0COMPLETERID_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(1), + GlitchData => L0COMPLETERID1_GlitchData, + OutSignalName => "L0COMPLETERID(1)", + OutTemp => L0COMPLETERID_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(2), + GlitchData => L0COMPLETERID2_GlitchData, + OutSignalName => "L0COMPLETERID(2)", + OutTemp => L0COMPLETERID_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(2), + GlitchData => L0COMPLETERID2_GlitchData, + OutSignalName => "L0COMPLETERID(2)", + OutTemp => L0COMPLETERID_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(3), + GlitchData => L0COMPLETERID3_GlitchData, + OutSignalName => "L0COMPLETERID(3)", + OutTemp => L0COMPLETERID_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(3), + GlitchData => L0COMPLETERID3_GlitchData, + OutSignalName => "L0COMPLETERID(3)", + OutTemp => L0COMPLETERID_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(4), + GlitchData => L0COMPLETERID4_GlitchData, + OutSignalName => "L0COMPLETERID(4)", + OutTemp => L0COMPLETERID_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(4), + GlitchData => L0COMPLETERID4_GlitchData, + OutSignalName => "L0COMPLETERID(4)", + OutTemp => L0COMPLETERID_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(5), + GlitchData => L0COMPLETERID5_GlitchData, + OutSignalName => "L0COMPLETERID(5)", + OutTemp => L0COMPLETERID_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(5), + GlitchData => L0COMPLETERID5_GlitchData, + OutSignalName => "L0COMPLETERID(5)", + OutTemp => L0COMPLETERID_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(6), + GlitchData => L0COMPLETERID6_GlitchData, + OutSignalName => "L0COMPLETERID(6)", + OutTemp => L0COMPLETERID_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(6), + GlitchData => L0COMPLETERID6_GlitchData, + OutSignalName => "L0COMPLETERID(6)", + OutTemp => L0COMPLETERID_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(7), + GlitchData => L0COMPLETERID7_GlitchData, + OutSignalName => "L0COMPLETERID(7)", + OutTemp => L0COMPLETERID_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(7), + GlitchData => L0COMPLETERID7_GlitchData, + OutSignalName => "L0COMPLETERID(7)", + OutTemp => L0COMPLETERID_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(8), + GlitchData => L0COMPLETERID8_GlitchData, + OutSignalName => "L0COMPLETERID(8)", + OutTemp => L0COMPLETERID_OUT(8), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(8), + GlitchData => L0COMPLETERID8_GlitchData, + OutSignalName => "L0COMPLETERID(8)", + OutTemp => L0COMPLETERID_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(9), + GlitchData => L0COMPLETERID9_GlitchData, + OutSignalName => "L0COMPLETERID(9)", + OutTemp => L0COMPLETERID_OUT(9), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(9), + GlitchData => L0COMPLETERID9_GlitchData, + OutSignalName => "L0COMPLETERID(9)", + OutTemp => L0COMPLETERID_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(10), + GlitchData => L0COMPLETERID10_GlitchData, + OutSignalName => "L0COMPLETERID(10)", + OutTemp => L0COMPLETERID_OUT(10), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(10), + GlitchData => L0COMPLETERID10_GlitchData, + OutSignalName => "L0COMPLETERID(10)", + OutTemp => L0COMPLETERID_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(11), + GlitchData => L0COMPLETERID11_GlitchData, + OutSignalName => "L0COMPLETERID(11)", + OutTemp => L0COMPLETERID_OUT(11), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(11), + GlitchData => L0COMPLETERID11_GlitchData, + OutSignalName => "L0COMPLETERID(11)", + OutTemp => L0COMPLETERID_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(12), + GlitchData => L0COMPLETERID12_GlitchData, + OutSignalName => "L0COMPLETERID(12)", + OutTemp => L0COMPLETERID_OUT(12), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(12), + GlitchData => L0COMPLETERID12_GlitchData, + OutSignalName => "L0COMPLETERID(12)", + OutTemp => L0COMPLETERID_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UNLOCKRECEIVED, + GlitchData => L0UNLOCKRECEIVED_GlitchData, + OutSignalName => "L0UNLOCKRECEIVED", + OutTemp => L0UNLOCKRECEIVED_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UNLOCKRECEIVED, + GlitchData => L0UNLOCKRECEIVED_GlitchData, + OutSignalName => "L0UNLOCKRECEIVED", + OutTemp => L0UNLOCKRECEIVED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0CORRERRMSGRCVD, + GlitchData => L0CORRERRMSGRCVD_GlitchData, + OutSignalName => "L0CORRERRMSGRCVD", + OutTemp => L0CORRERRMSGRCVD_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0CORRERRMSGRCVD, + GlitchData => L0CORRERRMSGRCVD_GlitchData, + OutSignalName => "L0CORRERRMSGRCVD", + OutTemp => L0CORRERRMSGRCVD_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FATALERRMSGRCVD, + GlitchData => L0FATALERRMSGRCVD_GlitchData, + OutSignalName => "L0FATALERRMSGRCVD", + OutTemp => L0FATALERRMSGRCVD_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FATALERRMSGRCVD, + GlitchData => L0FATALERRMSGRCVD_GlitchData, + OutSignalName => "L0FATALERRMSGRCVD", + OutTemp => L0FATALERRMSGRCVD_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0NONFATALERRMSGRCVD, + GlitchData => L0NONFATALERRMSGRCVD_GlitchData, + OutSignalName => "L0NONFATALERRMSGRCVD", + OutTemp => L0NONFATALERRMSGRCVD_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0NONFATALERRMSGRCVD, + GlitchData => L0NONFATALERRMSGRCVD_GlitchData, + OutSignalName => "L0NONFATALERRMSGRCVD", + OutTemp => L0NONFATALERRMSGRCVD_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(0), + GlitchData => L0ERRMSGREQID0_GlitchData, + OutSignalName => "L0ERRMSGREQID(0)", + OutTemp => L0ERRMSGREQID_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(0), + GlitchData => L0ERRMSGREQID0_GlitchData, + OutSignalName => "L0ERRMSGREQID(0)", + OutTemp => L0ERRMSGREQID_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(1), + GlitchData => L0ERRMSGREQID1_GlitchData, + OutSignalName => "L0ERRMSGREQID(1)", + OutTemp => L0ERRMSGREQID_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(1), + GlitchData => L0ERRMSGREQID1_GlitchData, + OutSignalName => "L0ERRMSGREQID(1)", + OutTemp => L0ERRMSGREQID_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(2), + GlitchData => L0ERRMSGREQID2_GlitchData, + OutSignalName => "L0ERRMSGREQID(2)", + OutTemp => L0ERRMSGREQID_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(2), + GlitchData => L0ERRMSGREQID2_GlitchData, + OutSignalName => "L0ERRMSGREQID(2)", + OutTemp => L0ERRMSGREQID_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(3), + GlitchData => L0ERRMSGREQID3_GlitchData, + OutSignalName => "L0ERRMSGREQID(3)", + OutTemp => L0ERRMSGREQID_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(3), + GlitchData => L0ERRMSGREQID3_GlitchData, + OutSignalName => "L0ERRMSGREQID(3)", + OutTemp => L0ERRMSGREQID_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(4), + GlitchData => L0ERRMSGREQID4_GlitchData, + OutSignalName => "L0ERRMSGREQID(4)", + OutTemp => L0ERRMSGREQID_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(4), + GlitchData => L0ERRMSGREQID4_GlitchData, + OutSignalName => "L0ERRMSGREQID(4)", + OutTemp => L0ERRMSGREQID_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(5), + GlitchData => L0ERRMSGREQID5_GlitchData, + OutSignalName => "L0ERRMSGREQID(5)", + OutTemp => L0ERRMSGREQID_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(5), + GlitchData => L0ERRMSGREQID5_GlitchData, + OutSignalName => "L0ERRMSGREQID(5)", + OutTemp => L0ERRMSGREQID_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(6), + GlitchData => L0ERRMSGREQID6_GlitchData, + OutSignalName => "L0ERRMSGREQID(6)", + OutTemp => L0ERRMSGREQID_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(6), + GlitchData => L0ERRMSGREQID6_GlitchData, + OutSignalName => "L0ERRMSGREQID(6)", + OutTemp => L0ERRMSGREQID_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(7), + GlitchData => L0ERRMSGREQID7_GlitchData, + OutSignalName => "L0ERRMSGREQID(7)", + OutTemp => L0ERRMSGREQID_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(7), + GlitchData => L0ERRMSGREQID7_GlitchData, + OutSignalName => "L0ERRMSGREQID(7)", + OutTemp => L0ERRMSGREQID_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(8), + GlitchData => L0ERRMSGREQID8_GlitchData, + OutSignalName => "L0ERRMSGREQID(8)", + OutTemp => L0ERRMSGREQID_OUT(8), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(8), + GlitchData => L0ERRMSGREQID8_GlitchData, + OutSignalName => "L0ERRMSGREQID(8)", + OutTemp => L0ERRMSGREQID_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(9), + GlitchData => L0ERRMSGREQID9_GlitchData, + OutSignalName => "L0ERRMSGREQID(9)", + OutTemp => L0ERRMSGREQID_OUT(9), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(9), + GlitchData => L0ERRMSGREQID9_GlitchData, + OutSignalName => "L0ERRMSGREQID(9)", + OutTemp => L0ERRMSGREQID_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(10), + GlitchData => L0ERRMSGREQID10_GlitchData, + OutSignalName => "L0ERRMSGREQID(10)", + OutTemp => L0ERRMSGREQID_OUT(10), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(10), + GlitchData => L0ERRMSGREQID10_GlitchData, + OutSignalName => "L0ERRMSGREQID(10)", + OutTemp => L0ERRMSGREQID_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(11), + GlitchData => L0ERRMSGREQID11_GlitchData, + OutSignalName => "L0ERRMSGREQID(11)", + OutTemp => L0ERRMSGREQID_OUT(11), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(11), + GlitchData => L0ERRMSGREQID11_GlitchData, + OutSignalName => "L0ERRMSGREQID(11)", + OutTemp => L0ERRMSGREQID_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(12), + GlitchData => L0ERRMSGREQID12_GlitchData, + OutSignalName => "L0ERRMSGREQID(12)", + OutTemp => L0ERRMSGREQID_OUT(12), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(12), + GlitchData => L0ERRMSGREQID12_GlitchData, + OutSignalName => "L0ERRMSGREQID(12)", + OutTemp => L0ERRMSGREQID_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(13), + GlitchData => L0ERRMSGREQID13_GlitchData, + OutSignalName => "L0ERRMSGREQID(13)", + OutTemp => L0ERRMSGREQID_OUT(13), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(13), + GlitchData => L0ERRMSGREQID13_GlitchData, + OutSignalName => "L0ERRMSGREQID(13)", + OutTemp => L0ERRMSGREQID_OUT(13), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(14), + GlitchData => L0ERRMSGREQID14_GlitchData, + OutSignalName => "L0ERRMSGREQID(14)", + OutTemp => L0ERRMSGREQID_OUT(14), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(14), + GlitchData => L0ERRMSGREQID14_GlitchData, + OutSignalName => "L0ERRMSGREQID(14)", + OutTemp => L0ERRMSGREQID_OUT(14), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(15), + GlitchData => L0ERRMSGREQID15_GlitchData, + OutSignalName => "L0ERRMSGREQID(15)", + OutTemp => L0ERRMSGREQID_OUT(15), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(15), + GlitchData => L0ERRMSGREQID15_GlitchData, + OutSignalName => "L0ERRMSGREQID(15)", + OutTemp => L0ERRMSGREQID_OUT(15), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FWDCORRERROUT, + GlitchData => L0FWDCORRERROUT_GlitchData, + OutSignalName => "L0FWDCORRERROUT", + OutTemp => L0FWDCORRERROUT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FWDCORRERROUT, + GlitchData => L0FWDCORRERROUT_GlitchData, + OutSignalName => "L0FWDCORRERROUT", + OutTemp => L0FWDCORRERROUT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FWDFATALERROUT, + GlitchData => L0FWDFATALERROUT_GlitchData, + OutSignalName => "L0FWDFATALERROUT", + OutTemp => L0FWDFATALERROUT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FWDFATALERROUT, + GlitchData => L0FWDFATALERROUT_GlitchData, + OutSignalName => "L0FWDFATALERROUT", + OutTemp => L0FWDFATALERROUT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FWDNONFATALERROUT, + GlitchData => L0FWDNONFATALERROUT_GlitchData, + OutSignalName => "L0FWDNONFATALERROUT", + OutTemp => L0FWDNONFATALERROUT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FWDNONFATALERROUT, + GlitchData => L0FWDNONFATALERROUT_GlitchData, + OutSignalName => "L0FWDNONFATALERROUT", + OutTemp => L0FWDNONFATALERROUT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDASSERTINTALEGACYINT, + GlitchData => L0RECEIVEDASSERTINTALEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDASSERTINTALEGACYINT", + OutTemp => L0RECEIVEDASSERTINTALEGACYINT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDASSERTINTALEGACYINT, + GlitchData => L0RECEIVEDASSERTINTALEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDASSERTINTALEGACYINT", + OutTemp => L0RECEIVEDASSERTINTALEGACYINT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDASSERTINTBLEGACYINT, + GlitchData => L0RECEIVEDASSERTINTBLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDASSERTINTBLEGACYINT", + OutTemp => L0RECEIVEDASSERTINTBLEGACYINT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDASSERTINTBLEGACYINT, + GlitchData => L0RECEIVEDASSERTINTBLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDASSERTINTBLEGACYINT", + OutTemp => L0RECEIVEDASSERTINTBLEGACYINT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDASSERTINTCLEGACYINT, + GlitchData => L0RECEIVEDASSERTINTCLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDASSERTINTCLEGACYINT", + OutTemp => L0RECEIVEDASSERTINTCLEGACYINT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDASSERTINTCLEGACYINT, + GlitchData => L0RECEIVEDASSERTINTCLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDASSERTINTCLEGACYINT", + OutTemp => L0RECEIVEDASSERTINTCLEGACYINT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDASSERTINTDLEGACYINT, + GlitchData => L0RECEIVEDASSERTINTDLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDASSERTINTDLEGACYINT", + OutTemp => L0RECEIVEDASSERTINTDLEGACYINT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDASSERTINTDLEGACYINT, + GlitchData => L0RECEIVEDASSERTINTDLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDASSERTINTDLEGACYINT", + OutTemp => L0RECEIVEDASSERTINTDLEGACYINT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDDEASSERTINTALEGACYINT, + GlitchData => L0RECEIVEDDEASSERTINTALEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDDEASSERTINTALEGACYINT", + OutTemp => L0RECEIVEDDEASSERTINTALEGACYINT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDDEASSERTINTALEGACYINT, + GlitchData => L0RECEIVEDDEASSERTINTALEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDDEASSERTINTALEGACYINT", + OutTemp => L0RECEIVEDDEASSERTINTALEGACYINT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDDEASSERTINTBLEGACYINT, + GlitchData => L0RECEIVEDDEASSERTINTBLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDDEASSERTINTBLEGACYINT", + OutTemp => L0RECEIVEDDEASSERTINTBLEGACYINT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDDEASSERTINTBLEGACYINT, + GlitchData => L0RECEIVEDDEASSERTINTBLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDDEASSERTINTBLEGACYINT", + OutTemp => L0RECEIVEDDEASSERTINTBLEGACYINT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDDEASSERTINTCLEGACYINT, + GlitchData => L0RECEIVEDDEASSERTINTCLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDDEASSERTINTCLEGACYINT", + OutTemp => L0RECEIVEDDEASSERTINTCLEGACYINT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDDEASSERTINTCLEGACYINT, + GlitchData => L0RECEIVEDDEASSERTINTCLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDDEASSERTINTCLEGACYINT", + OutTemp => L0RECEIVEDDEASSERTINTCLEGACYINT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDDEASSERTINTDLEGACYINT, + GlitchData => L0RECEIVEDDEASSERTINTDLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDDEASSERTINTDLEGACYINT", + OutTemp => L0RECEIVEDDEASSERTINTDLEGACYINT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDDEASSERTINTDLEGACYINT, + GlitchData => L0RECEIVEDDEASSERTINTDLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDDEASSERTINTDLEGACYINT", + OutTemp => L0RECEIVEDDEASSERTINTDLEGACYINT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MSIENABLE0, + GlitchData => L0MSIENABLE0_GlitchData, + OutSignalName => "L0MSIENABLE0", + OutTemp => L0MSIENABLE0_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MSIENABLE0, + GlitchData => L0MSIENABLE0_GlitchData, + OutSignalName => "L0MSIENABLE0", + OutTemp => L0MSIENABLE0_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MULTIMSGEN0(0), + GlitchData => L0MULTIMSGEN00_GlitchData, + OutSignalName => "L0MULTIMSGEN0(0)", + OutTemp => L0MULTIMSGEN0_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MULTIMSGEN0(0), + GlitchData => L0MULTIMSGEN00_GlitchData, + OutSignalName => "L0MULTIMSGEN0(0)", + OutTemp => L0MULTIMSGEN0_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MULTIMSGEN0(1), + GlitchData => L0MULTIMSGEN01_GlitchData, + OutSignalName => "L0MULTIMSGEN0(1)", + OutTemp => L0MULTIMSGEN0_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MULTIMSGEN0(1), + GlitchData => L0MULTIMSGEN01_GlitchData, + OutSignalName => "L0MULTIMSGEN0(1)", + OutTemp => L0MULTIMSGEN0_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MULTIMSGEN0(2), + GlitchData => L0MULTIMSGEN02_GlitchData, + OutSignalName => "L0MULTIMSGEN0(2)", + OutTemp => L0MULTIMSGEN0_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MULTIMSGEN0(2), + GlitchData => L0MULTIMSGEN02_GlitchData, + OutSignalName => "L0MULTIMSGEN0(2)", + OutTemp => L0MULTIMSGEN0_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSDLLPRECEIVED, + GlitchData => L0STATSDLLPRECEIVED_GlitchData, + OutSignalName => "L0STATSDLLPRECEIVED", + OutTemp => L0STATSDLLPRECEIVED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSDLLPTRANSMITTED, + GlitchData => L0STATSDLLPTRANSMITTED_GlitchData, + OutSignalName => "L0STATSDLLPTRANSMITTED", + OutTemp => L0STATSDLLPTRANSMITTED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSOSRECEIVED, + GlitchData => L0STATSOSRECEIVED_GlitchData, + OutSignalName => "L0STATSOSRECEIVED", + OutTemp => L0STATSOSRECEIVED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSOSTRANSMITTED, + GlitchData => L0STATSOSTRANSMITTED_GlitchData, + OutSignalName => "L0STATSOSTRANSMITTED", + OutTemp => L0STATSOSTRANSMITTED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSTLPRECEIVED, + GlitchData => L0STATSTLPRECEIVED_GlitchData, + OutSignalName => "L0STATSTLPRECEIVED", + OutTemp => L0STATSTLPRECEIVED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSTLPTRANSMITTED, + GlitchData => L0STATSTLPTRANSMITTED_GlitchData, + OutSignalName => "L0STATSTLPTRANSMITTED", + OutTemp => L0STATSTLPTRANSMITTED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSCFGRECEIVED, + GlitchData => L0STATSCFGRECEIVED_GlitchData, + OutSignalName => "L0STATSCFGRECEIVED", + OutTemp => L0STATSCFGRECEIVED_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSCFGRECEIVED, + GlitchData => L0STATSCFGRECEIVED_GlitchData, + OutSignalName => "L0STATSCFGRECEIVED", + OutTemp => L0STATSCFGRECEIVED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSCFGTRANSMITTED, + GlitchData => L0STATSCFGTRANSMITTED_GlitchData, + OutSignalName => "L0STATSCFGTRANSMITTED", + OutTemp => L0STATSCFGTRANSMITTED_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSCFGTRANSMITTED, + GlitchData => L0STATSCFGTRANSMITTED_GlitchData, + OutSignalName => "L0STATSCFGTRANSMITTED", + OutTemp => L0STATSCFGTRANSMITTED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSCFGOTHERRECEIVED, + GlitchData => L0STATSCFGOTHERRECEIVED_GlitchData, + OutSignalName => "L0STATSCFGOTHERRECEIVED", + OutTemp => L0STATSCFGOTHERRECEIVED_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSCFGOTHERRECEIVED, + GlitchData => L0STATSCFGOTHERRECEIVED_GlitchData, + OutSignalName => "L0STATSCFGOTHERRECEIVED", + OutTemp => L0STATSCFGOTHERRECEIVED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSCFGOTHERTRANSMITTED, + GlitchData => L0STATSCFGOTHERTRANSMITTED_GlitchData, + OutSignalName => "L0STATSCFGOTHERTRANSMITTED", + OutTemp => L0STATSCFGOTHERTRANSMITTED_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSCFGOTHERTRANSMITTED, + GlitchData => L0STATSCFGOTHERTRANSMITTED_GlitchData, + OutSignalName => "L0STATSCFGOTHERTRANSMITTED", + OutTemp => L0STATSCFGOTHERTRANSMITTED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXPAYLOADSIZE(0), + GlitchData => MAXPAYLOADSIZE0_GlitchData, + OutSignalName => "MAXPAYLOADSIZE(0)", + OutTemp => MAXPAYLOADSIZE_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXPAYLOADSIZE(0), + GlitchData => MAXPAYLOADSIZE0_GlitchData, + OutSignalName => "MAXPAYLOADSIZE(0)", + OutTemp => MAXPAYLOADSIZE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXPAYLOADSIZE(1), + GlitchData => MAXPAYLOADSIZE1_GlitchData, + OutSignalName => "MAXPAYLOADSIZE(1)", + OutTemp => MAXPAYLOADSIZE_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXPAYLOADSIZE(1), + GlitchData => MAXPAYLOADSIZE1_GlitchData, + OutSignalName => "MAXPAYLOADSIZE(1)", + OutTemp => MAXPAYLOADSIZE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXPAYLOADSIZE(2), + GlitchData => MAXPAYLOADSIZE2_GlitchData, + OutSignalName => "MAXPAYLOADSIZE(2)", + OutTemp => MAXPAYLOADSIZE_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXPAYLOADSIZE(2), + GlitchData => MAXPAYLOADSIZE2_GlitchData, + OutSignalName => "MAXPAYLOADSIZE(2)", + OutTemp => MAXPAYLOADSIZE_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXREADREQUESTSIZE(0), + GlitchData => MAXREADREQUESTSIZE0_GlitchData, + OutSignalName => "MAXREADREQUESTSIZE(0)", + OutTemp => MAXREADREQUESTSIZE_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXREADREQUESTSIZE(0), + GlitchData => MAXREADREQUESTSIZE0_GlitchData, + OutSignalName => "MAXREADREQUESTSIZE(0)", + OutTemp => MAXREADREQUESTSIZE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXREADREQUESTSIZE(1), + GlitchData => MAXREADREQUESTSIZE1_GlitchData, + OutSignalName => "MAXREADREQUESTSIZE(1)", + OutTemp => MAXREADREQUESTSIZE_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXREADREQUESTSIZE(1), + GlitchData => MAXREADREQUESTSIZE1_GlitchData, + OutSignalName => "MAXREADREQUESTSIZE(1)", + OutTemp => MAXREADREQUESTSIZE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXREADREQUESTSIZE(2), + GlitchData => MAXREADREQUESTSIZE2_GlitchData, + OutSignalName => "MAXREADREQUESTSIZE(2)", + OutTemp => MAXREADREQUESTSIZE_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXREADREQUESTSIZE(2), + GlitchData => MAXREADREQUESTSIZE2_GlitchData, + OutSignalName => "MAXREADREQUESTSIZE(2)", + OutTemp => MAXREADREQUESTSIZE_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => IOSPACEENABLE, + GlitchData => IOSPACEENABLE_GlitchData, + OutSignalName => "IOSPACEENABLE", + OutTemp => IOSPACEENABLE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => IOSPACEENABLE, + GlitchData => IOSPACEENABLE_GlitchData, + OutSignalName => "IOSPACEENABLE", + OutTemp => IOSPACEENABLE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MEMSPACEENABLE, + GlitchData => MEMSPACEENABLE_GlitchData, + OutSignalName => "MEMSPACEENABLE", + OutTemp => MEMSPACEENABLE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MEMSPACEENABLE, + GlitchData => MEMSPACEENABLE_GlitchData, + OutSignalName => "MEMSPACEENABLE", + OutTemp => MEMSPACEENABLE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ATTENTIONINDICATORCONTROL(0), + GlitchData => L0ATTENTIONINDICATORCONTROL0_GlitchData, + OutSignalName => "L0ATTENTIONINDICATORCONTROL(0)", + OutTemp => L0ATTENTIONINDICATORCONTROL_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ATTENTIONINDICATORCONTROL(0), + GlitchData => L0ATTENTIONINDICATORCONTROL0_GlitchData, + OutSignalName => "L0ATTENTIONINDICATORCONTROL(0)", + OutTemp => L0ATTENTIONINDICATORCONTROL_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ATTENTIONINDICATORCONTROL(1), + GlitchData => L0ATTENTIONINDICATORCONTROL1_GlitchData, + OutSignalName => "L0ATTENTIONINDICATORCONTROL(1)", + OutTemp => L0ATTENTIONINDICATORCONTROL_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ATTENTIONINDICATORCONTROL(1), + GlitchData => L0ATTENTIONINDICATORCONTROL1_GlitchData, + OutSignalName => "L0ATTENTIONINDICATORCONTROL(1)", + OutTemp => L0ATTENTIONINDICATORCONTROL_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0POWERINDICATORCONTROL(0), + GlitchData => L0POWERINDICATORCONTROL0_GlitchData, + OutSignalName => "L0POWERINDICATORCONTROL(0)", + OutTemp => L0POWERINDICATORCONTROL_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0POWERINDICATORCONTROL(0), + GlitchData => L0POWERINDICATORCONTROL0_GlitchData, + OutSignalName => "L0POWERINDICATORCONTROL(0)", + OutTemp => L0POWERINDICATORCONTROL_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0POWERINDICATORCONTROL(1), + GlitchData => L0POWERINDICATORCONTROL1_GlitchData, + OutSignalName => "L0POWERINDICATORCONTROL(1)", + OutTemp => L0POWERINDICATORCONTROL_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0POWERINDICATORCONTROL(1), + GlitchData => L0POWERINDICATORCONTROL1_GlitchData, + OutSignalName => "L0POWERINDICATORCONTROL(1)", + OutTemp => L0POWERINDICATORCONTROL_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0POWERCONTROLLERCONTROL, + GlitchData => L0POWERCONTROLLERCONTROL_GlitchData, + OutSignalName => "L0POWERCONTROLLERCONTROL", + OutTemp => L0POWERCONTROLLERCONTROL_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0POWERCONTROLLERCONTROL, + GlitchData => L0POWERCONTROLLERCONTROL_GlitchData, + OutSignalName => "L0POWERCONTROLLERCONTROL", + OutTemp => L0POWERCONTROLLERCONTROL_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TOGGLEELECTROMECHANICALINTERLOCK, + GlitchData => L0TOGGLEELECTROMECHANICALINTERLOCK_GlitchData, + OutSignalName => "L0TOGGLEELECTROMECHANICALINTERLOCK", + OutTemp => L0TOGGLEELECTROMECHANICALINTERLOCK_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TOGGLEELECTROMECHANICALINTERLOCK, + GlitchData => L0TOGGLEELECTROMECHANICALINTERLOCK_GlitchData, + OutSignalName => "L0TOGGLEELECTROMECHANICALINTERLOCK", + OutTemp => L0TOGGLEELECTROMECHANICALINTERLOCK_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXBEACON, + GlitchData => L0RXBEACON_GlitchData, + OutSignalName => "L0RXBEACON", + OutTemp => L0RXBEACON_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXBEACON, + GlitchData => L0RXBEACON_GlitchData, + OutSignalName => "L0RXBEACON", + OutTemp => L0RXBEACON_OUT, + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXBEACON, + GlitchData => L0RXBEACON_GlitchData, + OutSignalName => "L0RXBEACON", + OutTemp => L0RXBEACON_OUT, + Paths => (0 => (L0WAKEN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRSTATE0(0), + GlitchData => L0PWRSTATE00_GlitchData, + OutSignalName => "L0PWRSTATE0(0)", + OutTemp => L0PWRSTATE0_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRSTATE0(0), + GlitchData => L0PWRSTATE00_GlitchData, + OutSignalName => "L0PWRSTATE0(0)", + OutTemp => L0PWRSTATE0_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRSTATE0(1), + GlitchData => L0PWRSTATE01_GlitchData, + OutSignalName => "L0PWRSTATE0(1)", + OutTemp => L0PWRSTATE0_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRSTATE0(1), + GlitchData => L0PWRSTATE01_GlitchData, + OutSignalName => "L0PWRSTATE0(1)", + OutTemp => L0PWRSTATE0_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PMEACK, + GlitchData => L0PMEACK_GlitchData, + OutSignalName => "L0PMEACK", + OutTemp => L0PMEACK_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PMEACK, + GlitchData => L0PMEACK_GlitchData, + OutSignalName => "L0PMEACK", + OutTemp => L0PMEACK_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PMEREQOUT, + GlitchData => L0PMEREQOUT_GlitchData, + OutSignalName => "L0PMEREQOUT", + OutTemp => L0PMEREQOUT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PMEREQOUT, + GlitchData => L0PMEREQOUT_GlitchData, + OutSignalName => "L0PMEREQOUT", + OutTemp => L0PMEREQOUT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PMEREQOUT, + GlitchData => L0PMEREQOUT_GlitchData, + OutSignalName => "L0PMEREQOUT", + OutTemp => L0PMEREQOUT_OUT, + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PMEEN, + GlitchData => L0PMEEN_GlitchData, + OutSignalName => "L0PMEEN", + OutTemp => L0PMEEN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PMEEN, + GlitchData => L0PMEEN_GlitchData, + OutSignalName => "L0PMEEN", + OutTemp => L0PMEEN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PMEEN, + GlitchData => L0PMEEN_GlitchData, + OutSignalName => "L0PMEEN", + OutTemp => L0PMEEN_OUT, + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRINHIBITTRANSFERS, + GlitchData => L0PWRINHIBITTRANSFERS_GlitchData, + OutSignalName => "L0PWRINHIBITTRANSFERS", + OutTemp => L0PWRINHIBITTRANSFERS_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRL1STATE, + GlitchData => L0PWRL1STATE_GlitchData, + OutSignalName => "L0PWRL1STATE", + OutTemp => L0PWRL1STATE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRL1STATE, + GlitchData => L0PWRL1STATE_GlitchData, + OutSignalName => "L0PWRL1STATE", + OutTemp => L0PWRL1STATE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRL23READYDEVICE, + GlitchData => L0PWRL23READYDEVICE_GlitchData, + OutSignalName => "L0PWRL23READYDEVICE", + OutTemp => L0PWRL23READYDEVICE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRL23READYDEVICE, + GlitchData => L0PWRL23READYDEVICE_GlitchData, + OutSignalName => "L0PWRL23READYDEVICE", + OutTemp => L0PWRL23READYDEVICE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRL23READYSTATE, + GlitchData => L0PWRL23READYSTATE_GlitchData, + OutSignalName => "L0PWRL23READYSTATE", + OutTemp => L0PWRL23READYSTATE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRL23READYSTATE, + GlitchData => L0PWRL23READYSTATE_GlitchData, + OutSignalName => "L0PWRL23READYSTATE", + OutTemp => L0PWRL23READYSTATE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRTXL0SSTATE, + GlitchData => L0PWRTXL0SSTATE_GlitchData, + OutSignalName => "L0PWRTXL0SSTATE", + OutTemp => L0PWRTXL0SSTATE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRTXL0SSTATE, + GlitchData => L0PWRTXL0SSTATE_GlitchData, + OutSignalName => "L0PWRTXL0SSTATE", + OutTemp => L0PWRTXL0SSTATE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRTURNOFFREQ, + GlitchData => L0PWRTURNOFFREQ_GlitchData, + OutSignalName => "L0PWRTURNOFFREQ", + OutTemp => L0PWRTURNOFFREQ_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRTURNOFFREQ, + GlitchData => L0PWRTURNOFFREQ_GlitchData, + OutSignalName => "L0PWRTURNOFFREQ", + OutTemp => L0PWRTURNOFFREQ_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLPM, + GlitchData => L0RXDLLPM_GlitchData, + OutSignalName => "L0RXDLLPM", + OutTemp => L0RXDLLPM_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLPMTYPE(0), + GlitchData => L0RXDLLPMTYPE0_GlitchData, + OutSignalName => "L0RXDLLPMTYPE(0)", + OutTemp => L0RXDLLPMTYPE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLPMTYPE(1), + GlitchData => L0RXDLLPMTYPE1_GlitchData, + OutSignalName => "L0RXDLLPMTYPE(1)", + OutTemp => L0RXDLLPMTYPE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLPMTYPE(2), + GlitchData => L0RXDLLPMTYPE2_GlitchData, + OutSignalName => "L0RXDLLPMTYPE(2)", + OutTemp => L0RXDLLPMTYPE_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLPMUPDATED, + GlitchData => L0TXDLLPMUPDATED_GlitchData, + OutSignalName => "L0TXDLLPMUPDATED", + OutTemp => L0TXDLLPMUPDATED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACNEWSTATEACK, + GlitchData => L0MACNEWSTATEACK_GlitchData, + OutSignalName => "L0MACNEWSTATEACK", + OutTemp => L0MACNEWSTATEACK_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACRXL0SSTATE, + GlitchData => L0MACRXL0SSTATE_GlitchData, + OutSignalName => "L0MACRXL0SSTATE", + OutTemp => L0MACRXL0SSTATE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACENTEREDL0, + GlitchData => L0MACENTEREDL0_GlitchData, + OutSignalName => "L0MACENTEREDL0", + OutTemp => L0MACENTEREDL0_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLRXACKOUTSTANDING, + GlitchData => L0DLLRXACKOUTSTANDING_GlitchData, + OutSignalName => "L0DLLRXACKOUTSTANDING", + OutTemp => L0DLLRXACKOUTSTANDING_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLTXOUTSTANDING, + GlitchData => L0DLLTXOUTSTANDING_GlitchData, + OutSignalName => "L0DLLTXOUTSTANDING", + OutTemp => L0DLLTXOUTSTANDING_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLTXNONFCOUTSTANDING, + GlitchData => L0DLLTXNONFCOUTSTANDING_GlitchData, + OutSignalName => "L0DLLTXNONFCOUTSTANDING", + OutTemp => L0DLLTXNONFCOUTSTANDING_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLTLPEND(0), + GlitchData => L0RXDLLTLPEND0_GlitchData, + OutSignalName => "L0RXDLLTLPEND(0)", + OutTemp => L0RXDLLTLPEND_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLTLPEND(1), + GlitchData => L0RXDLLTLPEND1_GlitchData, + OutSignalName => "L0RXDLLTLPEND(1)", + OutTemp => L0RXDLLTLPEND_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLSBFCUPDATED, + GlitchData => L0TXDLLSBFCUPDATED_GlitchData, + OutSignalName => "L0TXDLLSBFCUPDATED", + OutTemp => L0TXDLLSBFCUPDATED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(0), + GlitchData => L0RXDLLSBFCDATA0_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(0)", + OutTemp => L0RXDLLSBFCDATA_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(1), + GlitchData => L0RXDLLSBFCDATA1_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(1)", + OutTemp => L0RXDLLSBFCDATA_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(2), + GlitchData => L0RXDLLSBFCDATA2_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(2)", + OutTemp => L0RXDLLSBFCDATA_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(3), + GlitchData => L0RXDLLSBFCDATA3_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(3)", + OutTemp => L0RXDLLSBFCDATA_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(4), + GlitchData => L0RXDLLSBFCDATA4_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(4)", + OutTemp => L0RXDLLSBFCDATA_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(5), + GlitchData => L0RXDLLSBFCDATA5_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(5)", + OutTemp => L0RXDLLSBFCDATA_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(6), + GlitchData => L0RXDLLSBFCDATA6_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(6)", + OutTemp => L0RXDLLSBFCDATA_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(7), + GlitchData => L0RXDLLSBFCDATA7_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(7)", + OutTemp => L0RXDLLSBFCDATA_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(8), + GlitchData => L0RXDLLSBFCDATA8_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(8)", + OutTemp => L0RXDLLSBFCDATA_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(9), + GlitchData => L0RXDLLSBFCDATA9_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(9)", + OutTemp => L0RXDLLSBFCDATA_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(10), + GlitchData => L0RXDLLSBFCDATA10_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(10)", + OutTemp => L0RXDLLSBFCDATA_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(11), + GlitchData => L0RXDLLSBFCDATA11_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(11)", + OutTemp => L0RXDLLSBFCDATA_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(12), + GlitchData => L0RXDLLSBFCDATA12_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(12)", + OutTemp => L0RXDLLSBFCDATA_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(13), + GlitchData => L0RXDLLSBFCDATA13_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(13)", + OutTemp => L0RXDLLSBFCDATA_OUT(13), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(14), + GlitchData => L0RXDLLSBFCDATA14_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(14)", + OutTemp => L0RXDLLSBFCDATA_OUT(14), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(15), + GlitchData => L0RXDLLSBFCDATA15_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(15)", + OutTemp => L0RXDLLSBFCDATA_OUT(15), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(16), + GlitchData => L0RXDLLSBFCDATA16_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(16)", + OutTemp => L0RXDLLSBFCDATA_OUT(16), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(17), + GlitchData => L0RXDLLSBFCDATA17_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(17)", + OutTemp => L0RXDLLSBFCDATA_OUT(17), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(18), + GlitchData => L0RXDLLSBFCDATA18_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(18)", + OutTemp => L0RXDLLSBFCDATA_OUT(18), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCUPDATE, + GlitchData => L0RXDLLSBFCUPDATE_GlitchData, + OutSignalName => "L0RXDLLSBFCUPDATE", + OutTemp => L0RXDLLSBFCUPDATE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCNPOSTBYPUPDATED(0), + GlitchData => L0TXDLLFCNPOSTBYPUPDATED0_GlitchData, + OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(0)", + OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCNPOSTBYPUPDATED(1), + GlitchData => L0TXDLLFCNPOSTBYPUPDATED1_GlitchData, + OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(1)", + OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCNPOSTBYPUPDATED(2), + GlitchData => L0TXDLLFCNPOSTBYPUPDATED2_GlitchData, + OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(2)", + OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCNPOSTBYPUPDATED(3), + GlitchData => L0TXDLLFCNPOSTBYPUPDATED3_GlitchData, + OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(3)", + OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCNPOSTBYPUPDATED(4), + GlitchData => L0TXDLLFCNPOSTBYPUPDATED4_GlitchData, + OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(4)", + OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCNPOSTBYPUPDATED(5), + GlitchData => L0TXDLLFCNPOSTBYPUPDATED5_GlitchData, + OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(5)", + OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCNPOSTBYPUPDATED(6), + GlitchData => L0TXDLLFCNPOSTBYPUPDATED6_GlitchData, + OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(6)", + OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCNPOSTBYPUPDATED(7), + GlitchData => L0TXDLLFCNPOSTBYPUPDATED7_GlitchData, + OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(7)", + OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCPOSTORDUPDATED(0), + GlitchData => L0TXDLLFCPOSTORDUPDATED0_GlitchData, + OutSignalName => "L0TXDLLFCPOSTORDUPDATED(0)", + OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCPOSTORDUPDATED(1), + GlitchData => L0TXDLLFCPOSTORDUPDATED1_GlitchData, + OutSignalName => "L0TXDLLFCPOSTORDUPDATED(1)", + OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCPOSTORDUPDATED(2), + GlitchData => L0TXDLLFCPOSTORDUPDATED2_GlitchData, + OutSignalName => "L0TXDLLFCPOSTORDUPDATED(2)", + OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCPOSTORDUPDATED(3), + GlitchData => L0TXDLLFCPOSTORDUPDATED3_GlitchData, + OutSignalName => "L0TXDLLFCPOSTORDUPDATED(3)", + OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCPOSTORDUPDATED(4), + GlitchData => L0TXDLLFCPOSTORDUPDATED4_GlitchData, + OutSignalName => "L0TXDLLFCPOSTORDUPDATED(4)", + OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCPOSTORDUPDATED(5), + GlitchData => L0TXDLLFCPOSTORDUPDATED5_GlitchData, + OutSignalName => "L0TXDLLFCPOSTORDUPDATED(5)", + OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCPOSTORDUPDATED(6), + GlitchData => L0TXDLLFCPOSTORDUPDATED6_GlitchData, + OutSignalName => "L0TXDLLFCPOSTORDUPDATED(6)", + OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCPOSTORDUPDATED(7), + GlitchData => L0TXDLLFCPOSTORDUPDATED7_GlitchData, + OutSignalName => "L0TXDLLFCPOSTORDUPDATED(7)", + OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCCMPLMCUPDATED(0), + GlitchData => L0TXDLLFCCMPLMCUPDATED0_GlitchData, + OutSignalName => "L0TXDLLFCCMPLMCUPDATED(0)", + OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCCMPLMCUPDATED(1), + GlitchData => L0TXDLLFCCMPLMCUPDATED1_GlitchData, + OutSignalName => "L0TXDLLFCCMPLMCUPDATED(1)", + OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCCMPLMCUPDATED(2), + GlitchData => L0TXDLLFCCMPLMCUPDATED2_GlitchData, + OutSignalName => "L0TXDLLFCCMPLMCUPDATED(2)", + OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCCMPLMCUPDATED(3), + GlitchData => L0TXDLLFCCMPLMCUPDATED3_GlitchData, + OutSignalName => "L0TXDLLFCCMPLMCUPDATED(3)", + OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCCMPLMCUPDATED(4), + GlitchData => L0TXDLLFCCMPLMCUPDATED4_GlitchData, + OutSignalName => "L0TXDLLFCCMPLMCUPDATED(4)", + OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCCMPLMCUPDATED(5), + GlitchData => L0TXDLLFCCMPLMCUPDATED5_GlitchData, + OutSignalName => "L0TXDLLFCCMPLMCUPDATED(5)", + OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCCMPLMCUPDATED(6), + GlitchData => L0TXDLLFCCMPLMCUPDATED6_GlitchData, + OutSignalName => "L0TXDLLFCCMPLMCUPDATED(6)", + OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCCMPLMCUPDATED(7), + GlitchData => L0TXDLLFCCMPLMCUPDATED7_GlitchData, + OutSignalName => "L0TXDLLFCCMPLMCUPDATED(7)", + OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(0), + GlitchData => L0RXDLLFCNPOSTBYPCRED0_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(0)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(1), + GlitchData => L0RXDLLFCNPOSTBYPCRED1_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(1)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(2), + GlitchData => L0RXDLLFCNPOSTBYPCRED2_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(2)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(3), + GlitchData => L0RXDLLFCNPOSTBYPCRED3_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(3)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(4), + GlitchData => L0RXDLLFCNPOSTBYPCRED4_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(4)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(5), + GlitchData => L0RXDLLFCNPOSTBYPCRED5_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(5)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(6), + GlitchData => L0RXDLLFCNPOSTBYPCRED6_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(6)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(7), + GlitchData => L0RXDLLFCNPOSTBYPCRED7_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(7)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(8), + GlitchData => L0RXDLLFCNPOSTBYPCRED8_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(8)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(9), + GlitchData => L0RXDLLFCNPOSTBYPCRED9_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(9)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(10), + GlitchData => L0RXDLLFCNPOSTBYPCRED10_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(10)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(11), + GlitchData => L0RXDLLFCNPOSTBYPCRED11_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(11)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(12), + GlitchData => L0RXDLLFCNPOSTBYPCRED12_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(12)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(13), + GlitchData => L0RXDLLFCNPOSTBYPCRED13_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(13)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(13), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(14), + GlitchData => L0RXDLLFCNPOSTBYPCRED14_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(14)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(14), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(15), + GlitchData => L0RXDLLFCNPOSTBYPCRED15_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(15)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(15), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(16), + GlitchData => L0RXDLLFCNPOSTBYPCRED16_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(16)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(16), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(17), + GlitchData => L0RXDLLFCNPOSTBYPCRED17_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(17)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(17), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(18), + GlitchData => L0RXDLLFCNPOSTBYPCRED18_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(18)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(18), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(19), + GlitchData => L0RXDLLFCNPOSTBYPCRED19_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(19)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(19), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPUPDATE(0), + GlitchData => L0RXDLLFCNPOSTBYPUPDATE0_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(0)", + OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPUPDATE(1), + GlitchData => L0RXDLLFCNPOSTBYPUPDATE1_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(1)", + OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPUPDATE(2), + GlitchData => L0RXDLLFCNPOSTBYPUPDATE2_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(2)", + OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPUPDATE(3), + GlitchData => L0RXDLLFCNPOSTBYPUPDATE3_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(3)", + OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPUPDATE(4), + GlitchData => L0RXDLLFCNPOSTBYPUPDATE4_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(4)", + OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPUPDATE(5), + GlitchData => L0RXDLLFCNPOSTBYPUPDATE5_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(5)", + OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPUPDATE(6), + GlitchData => L0RXDLLFCNPOSTBYPUPDATE6_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(6)", + OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPUPDATE(7), + GlitchData => L0RXDLLFCNPOSTBYPUPDATE7_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(7)", + OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(0), + GlitchData => L0RXDLLFCPOSTORDCRED0_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(0)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(1), + GlitchData => L0RXDLLFCPOSTORDCRED1_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(1)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(2), + GlitchData => L0RXDLLFCPOSTORDCRED2_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(2)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(3), + GlitchData => L0RXDLLFCPOSTORDCRED3_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(3)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(4), + GlitchData => L0RXDLLFCPOSTORDCRED4_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(4)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(5), + GlitchData => L0RXDLLFCPOSTORDCRED5_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(5)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(6), + GlitchData => L0RXDLLFCPOSTORDCRED6_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(6)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(7), + GlitchData => L0RXDLLFCPOSTORDCRED7_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(7)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(8), + GlitchData => L0RXDLLFCPOSTORDCRED8_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(8)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(9), + GlitchData => L0RXDLLFCPOSTORDCRED9_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(9)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(10), + GlitchData => L0RXDLLFCPOSTORDCRED10_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(10)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(11), + GlitchData => L0RXDLLFCPOSTORDCRED11_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(11)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(12), + GlitchData => L0RXDLLFCPOSTORDCRED12_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(12)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(13), + GlitchData => L0RXDLLFCPOSTORDCRED13_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(13)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(13), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(14), + GlitchData => L0RXDLLFCPOSTORDCRED14_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(14)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(14), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(15), + GlitchData => L0RXDLLFCPOSTORDCRED15_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(15)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(15), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(16), + GlitchData => L0RXDLLFCPOSTORDCRED16_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(16)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(16), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(17), + GlitchData => L0RXDLLFCPOSTORDCRED17_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(17)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(17), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(18), + GlitchData => L0RXDLLFCPOSTORDCRED18_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(18)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(18), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(19), + GlitchData => L0RXDLLFCPOSTORDCRED19_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(19)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(19), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(20), + GlitchData => L0RXDLLFCPOSTORDCRED20_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(20)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(20), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(21), + GlitchData => L0RXDLLFCPOSTORDCRED21_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(21)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(21), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(22), + GlitchData => L0RXDLLFCPOSTORDCRED22_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(22)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(22), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(23), + GlitchData => L0RXDLLFCPOSTORDCRED23_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(23)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(23), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDUPDATE(0), + GlitchData => L0RXDLLFCPOSTORDUPDATE0_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDUPDATE(0)", + OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDUPDATE(1), + GlitchData => L0RXDLLFCPOSTORDUPDATE1_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDUPDATE(1)", + OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDUPDATE(2), + GlitchData => L0RXDLLFCPOSTORDUPDATE2_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDUPDATE(2)", + OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDUPDATE(3), + GlitchData => L0RXDLLFCPOSTORDUPDATE3_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDUPDATE(3)", + OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDUPDATE(4), + GlitchData => L0RXDLLFCPOSTORDUPDATE4_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDUPDATE(4)", + OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDUPDATE(5), + GlitchData => L0RXDLLFCPOSTORDUPDATE5_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDUPDATE(5)", + OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDUPDATE(6), + GlitchData => L0RXDLLFCPOSTORDUPDATE6_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDUPDATE(6)", + OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDUPDATE(7), + GlitchData => L0RXDLLFCPOSTORDUPDATE7_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDUPDATE(7)", + OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(0), + GlitchData => L0RXDLLFCCMPLMCCRED0_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(0)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(1), + GlitchData => L0RXDLLFCCMPLMCCRED1_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(1)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(2), + GlitchData => L0RXDLLFCCMPLMCCRED2_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(2)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(3), + GlitchData => L0RXDLLFCCMPLMCCRED3_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(3)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(4), + GlitchData => L0RXDLLFCCMPLMCCRED4_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(4)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(5), + GlitchData => L0RXDLLFCCMPLMCCRED5_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(5)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(6), + GlitchData => L0RXDLLFCCMPLMCCRED6_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(6)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(7), + GlitchData => L0RXDLLFCCMPLMCCRED7_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(7)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(8), + GlitchData => L0RXDLLFCCMPLMCCRED8_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(8)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(9), + GlitchData => L0RXDLLFCCMPLMCCRED9_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(9)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(10), + GlitchData => L0RXDLLFCCMPLMCCRED10_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(10)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(11), + GlitchData => L0RXDLLFCCMPLMCCRED11_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(11)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(12), + GlitchData => L0RXDLLFCCMPLMCCRED12_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(12)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(13), + GlitchData => L0RXDLLFCCMPLMCCRED13_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(13)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(13), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(14), + GlitchData => L0RXDLLFCCMPLMCCRED14_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(14)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(14), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(15), + GlitchData => L0RXDLLFCCMPLMCCRED15_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(15)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(15), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(16), + GlitchData => L0RXDLLFCCMPLMCCRED16_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(16)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(16), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(17), + GlitchData => L0RXDLLFCCMPLMCCRED17_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(17)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(17), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(18), + GlitchData => L0RXDLLFCCMPLMCCRED18_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(18)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(18), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(19), + GlitchData => L0RXDLLFCCMPLMCCRED19_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(19)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(19), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(20), + GlitchData => L0RXDLLFCCMPLMCCRED20_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(20)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(20), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(21), + GlitchData => L0RXDLLFCCMPLMCCRED21_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(21)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(21), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(22), + GlitchData => L0RXDLLFCCMPLMCCRED22_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(22)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(22), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(23), + GlitchData => L0RXDLLFCCMPLMCCRED23_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(23)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(23), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCUPDATE(0), + GlitchData => L0RXDLLFCCMPLMCUPDATE0_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCUPDATE(0)", + OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCUPDATE(1), + GlitchData => L0RXDLLFCCMPLMCUPDATE1_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCUPDATE(1)", + OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCUPDATE(2), + GlitchData => L0RXDLLFCCMPLMCUPDATE2_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCUPDATE(2)", + OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCUPDATE(3), + GlitchData => L0RXDLLFCCMPLMCUPDATE3_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCUPDATE(3)", + OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCUPDATE(4), + GlitchData => L0RXDLLFCCMPLMCUPDATE4_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCUPDATE(4)", + OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCUPDATE(5), + GlitchData => L0RXDLLFCCMPLMCUPDATE5_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCUPDATE(5)", + OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCUPDATE(6), + GlitchData => L0RXDLLFCCMPLMCUPDATE6_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCUPDATE(6)", + OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCUPDATE(7), + GlitchData => L0RXDLLFCCMPLMCUPDATE7_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCUPDATE(7)", + OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UCBYPFOUND(0), + GlitchData => L0UCBYPFOUND0_GlitchData, + OutSignalName => "L0UCBYPFOUND(0)", + OutTemp => L0UCBYPFOUND_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UCBYPFOUND(1), + GlitchData => L0UCBYPFOUND1_GlitchData, + OutSignalName => "L0UCBYPFOUND(1)", + OutTemp => L0UCBYPFOUND_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UCBYPFOUND(2), + GlitchData => L0UCBYPFOUND2_GlitchData, + OutSignalName => "L0UCBYPFOUND(2)", + OutTemp => L0UCBYPFOUND_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UCBYPFOUND(3), + GlitchData => L0UCBYPFOUND3_GlitchData, + OutSignalName => "L0UCBYPFOUND(3)", + OutTemp => L0UCBYPFOUND_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UCORDFOUND(0), + GlitchData => L0UCORDFOUND0_GlitchData, + OutSignalName => "L0UCORDFOUND(0)", + OutTemp => L0UCORDFOUND_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UCORDFOUND(1), + GlitchData => L0UCORDFOUND1_GlitchData, + OutSignalName => "L0UCORDFOUND(1)", + OutTemp => L0UCORDFOUND_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UCORDFOUND(2), + GlitchData => L0UCORDFOUND2_GlitchData, + OutSignalName => "L0UCORDFOUND(2)", + OutTemp => L0UCORDFOUND_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UCORDFOUND(3), + GlitchData => L0UCORDFOUND3_GlitchData, + OutSignalName => "L0UCORDFOUND(3)", + OutTemp => L0UCORDFOUND_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MCFOUND(0), + GlitchData => L0MCFOUND0_GlitchData, + OutSignalName => "L0MCFOUND(0)", + OutTemp => L0MCFOUND_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MCFOUND(1), + GlitchData => L0MCFOUND1_GlitchData, + OutSignalName => "L0MCFOUND(1)", + OutTemp => L0MCFOUND_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MCFOUND(2), + GlitchData => L0MCFOUND2_GlitchData, + OutSignalName => "L0MCFOUND(2)", + OutTemp => L0MCFOUND_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TRANSFORMEDVC(0), + GlitchData => L0TRANSFORMEDVC0_GlitchData, + OutSignalName => "L0TRANSFORMEDVC(0)", + OutTemp => L0TRANSFORMEDVC_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TRANSFORMEDVC(1), + GlitchData => L0TRANSFORMEDVC1_GlitchData, + OutSignalName => "L0TRANSFORMEDVC(1)", + OutTemp => L0TRANSFORMEDVC_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TRANSFORMEDVC(2), + GlitchData => L0TRANSFORMEDVC2_GlitchData, + OutSignalName => "L0TRANSFORMEDVC(2)", + OutTemp => L0TRANSFORMEDVC_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => BUSMASTERENABLE, + GlitchData => BUSMASTERENABLE_GlitchData, + OutSignalName => "BUSMASTERENABLE", + OutTemp => BUSMASTERENABLE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => BUSMASTERENABLE, + GlitchData => BUSMASTERENABLE_GlitchData, + OutSignalName => "BUSMASTERENABLE", + OutTemp => BUSMASTERENABLE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PARITYERRORRESPONSE, + GlitchData => PARITYERRORRESPONSE_GlitchData, + OutSignalName => "PARITYERRORRESPONSE", + OutTemp => PARITYERRORRESPONSE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PARITYERRORRESPONSE, + GlitchData => PARITYERRORRESPONSE_GlitchData, + OutSignalName => "PARITYERRORRESPONSE", + OutTemp => PARITYERRORRESPONSE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => SERRENABLE, + GlitchData => SERRENABLE_GlitchData, + OutSignalName => "SERRENABLE", + OutTemp => SERRENABLE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => SERRENABLE, + GlitchData => SERRENABLE_GlitchData, + OutSignalName => "SERRENABLE", + OutTemp => SERRENABLE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => INTERRUPTDISABLE, + GlitchData => INTERRUPTDISABLE_GlitchData, + OutSignalName => "INTERRUPTDISABLE", + OutTemp => INTERRUPTDISABLE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => INTERRUPTDISABLE, + GlitchData => INTERRUPTDISABLE_GlitchData, + OutSignalName => "INTERRUPTDISABLE", + OutTemp => INTERRUPTDISABLE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => URREPORTINGENABLE, + GlitchData => URREPORTINGENABLE_GlitchData, + OutSignalName => "URREPORTINGENABLE", + OutTemp => URREPORTINGENABLE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => URREPORTINGENABLE, + GlitchData => URREPORTINGENABLE_GlitchData, + OutSignalName => "URREPORTINGENABLE", + OutTemp => URREPORTINGENABLE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + + wait on + BUSMASTERENABLE_out, + CRMDOHOTRESETN_out, + CRMPWRSOFTRESETN_out, + CRMRXHOTRESETN_out, + DLLTXPMDLLPOUTSTANDING_out, + INTERRUPTDISABLE_out, + IOSPACEENABLE_out, + L0ASAUTONOMOUSINITCOMPLETED_out, + L0ATTENTIONINDICATORCONTROL_out, + L0CFGLOOPBACKACK_out, + L0COMPLETERID_out, + L0CORRERRMSGRCVD_out, + L0DLLASRXSTATE_out, + L0DLLASTXSTATE_out, + L0DLLERRORVECTOR_out, + L0DLLRXACKOUTSTANDING_out, + L0DLLTXNONFCOUTSTANDING_out, + L0DLLTXOUTSTANDING_out, + L0DLLVCSTATUS_out, + L0DLUPDOWN_out, + L0ERRMSGREQID_out, + L0FATALERRMSGRCVD_out, + L0FIRSTCFGWRITEOCCURRED_out, + L0FWDCORRERROUT_out, + L0FWDFATALERROUT_out, + L0FWDNONFATALERROUT_out, + L0LTSSMSTATE_out, + L0MACENTEREDL0_out, + L0MACLINKTRAINING_out, + L0MACLINKUP_out, + L0MACNEGOTIATEDLINKWIDTH_out, + L0MACNEWSTATEACK_out, + L0MACRXL0SSTATE_out, + L0MACUPSTREAMDOWNSTREAM_out, + L0MCFOUND_out, + L0MSIENABLE0_out, + L0MULTIMSGEN0_out, + L0NONFATALERRMSGRCVD_out, + L0PMEACK_out, + L0PMEEN_out, + L0PMEREQOUT_out, + L0POWERCONTROLLERCONTROL_out, + L0POWERINDICATORCONTROL_out, + L0PWRINHIBITTRANSFERS_out, + L0PWRL1STATE_out, + L0PWRL23READYDEVICE_out, + L0PWRL23READYSTATE_out, + L0PWRSTATE0_out, + L0PWRTURNOFFREQ_out, + L0PWRTXL0SSTATE_out, + L0RECEIVEDASSERTINTALEGACYINT_out, + L0RECEIVEDASSERTINTBLEGACYINT_out, + L0RECEIVEDASSERTINTCLEGACYINT_out, + L0RECEIVEDASSERTINTDLEGACYINT_out, + L0RECEIVEDDEASSERTINTALEGACYINT_out, + L0RECEIVEDDEASSERTINTBLEGACYINT_out, + L0RECEIVEDDEASSERTINTCLEGACYINT_out, + L0RECEIVEDDEASSERTINTDLEGACYINT_out, + L0RXBEACON_out, + L0RXDLLFCCMPLMCCRED_out, + L0RXDLLFCCMPLMCUPDATE_out, + L0RXDLLFCNPOSTBYPCRED_out, + L0RXDLLFCNPOSTBYPUPDATE_out, + L0RXDLLFCPOSTORDCRED_out, + L0RXDLLFCPOSTORDUPDATE_out, + L0RXDLLPMTYPE_out, + L0RXDLLPM_out, + L0RXDLLSBFCDATA_out, + L0RXDLLSBFCUPDATE_out, + L0RXDLLTLPECRCOK_out, + L0RXDLLTLPEND_out, + L0RXMACLINKERROR_out, + L0STATSCFGOTHERRECEIVED_out, + L0STATSCFGOTHERTRANSMITTED_out, + L0STATSCFGRECEIVED_out, + L0STATSCFGTRANSMITTED_out, + L0STATSDLLPRECEIVED_out, + L0STATSDLLPTRANSMITTED_out, + L0STATSOSRECEIVED_out, + L0STATSOSTRANSMITTED_out, + L0STATSTLPRECEIVED_out, + L0STATSTLPTRANSMITTED_out, + L0TOGGLEELECTROMECHANICALINTERLOCK_out, + L0TRANSFORMEDVC_out, + L0TXDLLFCCMPLMCUPDATED_out, + L0TXDLLFCNPOSTBYPUPDATED_out, + L0TXDLLFCPOSTORDUPDATED_out, + L0TXDLLPMUPDATED_out, + L0TXDLLSBFCUPDATED_out, + L0UCBYPFOUND_out, + L0UCORDFOUND_out, + L0UNLOCKRECEIVED_out, + LLKRX4DWHEADERN_out, + LLKRXCHCOMPLETIONAVAILABLEN_out, + LLKRXCHCOMPLETIONPARTIALN_out, + LLKRXCHCONFIGAVAILABLEN_out, + LLKRXCHCONFIGPARTIALN_out, + LLKRXCHNONPOSTEDAVAILABLEN_out, + LLKRXCHNONPOSTEDPARTIALN_out, + LLKRXCHPOSTEDAVAILABLEN_out, + LLKRXCHPOSTEDPARTIALN_out, + LLKRXDATA_out, + LLKRXECRCBADN_out, + LLKRXEOFN_out, + LLKRXEOPN_out, + LLKRXPREFERREDTYPE_out, + LLKRXSOFN_out, + LLKRXSOPN_out, + LLKRXSRCDSCN_out, + LLKRXSRCLASTREQN_out, + LLKRXSRCRDYN_out, + LLKRXVALIDN_out, + LLKTCSTATUS_out, + LLKTXCHANSPACE_out, + LLKTXCHCOMPLETIONREADYN_out, + LLKTXCHNONPOSTEDREADYN_out, + LLKTXCHPOSTEDREADYN_out, + LLKTXCONFIGREADYN_out, + LLKTXDSTRDYN_out, + MAXPAYLOADSIZE_out, + MAXREADREQUESTSIZE_out, + MEMSPACEENABLE_out, + MGMTPSO_out, + MGMTRDATA_out, + MGMTSTATSCREDIT_out, + MIMDLLBRADD_out, + MIMDLLBREN_out, + MIMDLLBWADD_out, + MIMDLLBWDATA_out, + MIMDLLBWEN_out, + MIMRXBRADD_out, + MIMRXBREN_out, + MIMRXBWADD_out, + MIMRXBWDATA_out, + MIMRXBWEN_out, + MIMTXBRADD_out, + MIMTXBREN_out, + MIMTXBWADD_out, + MIMTXBWDATA_out, + MIMTXBWEN_out, + PARITYERRORRESPONSE_out, + PIPEDESKEWLANESL0_out, + PIPEDESKEWLANESL1_out, + PIPEDESKEWLANESL2_out, + PIPEDESKEWLANESL3_out, + PIPEDESKEWLANESL4_out, + PIPEDESKEWLANESL5_out, + PIPEDESKEWLANESL6_out, + PIPEDESKEWLANESL7_out, + PIPEPOWERDOWNL0_out, + PIPEPOWERDOWNL1_out, + PIPEPOWERDOWNL2_out, + PIPEPOWERDOWNL3_out, + PIPEPOWERDOWNL4_out, + PIPEPOWERDOWNL5_out, + PIPEPOWERDOWNL6_out, + PIPEPOWERDOWNL7_out, + PIPERESETL0_out, + PIPERESETL1_out, + PIPERESETL2_out, + PIPERESETL3_out, + PIPERESETL4_out, + PIPERESETL5_out, + PIPERESETL6_out, + PIPERESETL7_out, + PIPERXPOLARITYL0_out, + PIPERXPOLARITYL1_out, + PIPERXPOLARITYL2_out, + PIPERXPOLARITYL3_out, + PIPERXPOLARITYL4_out, + PIPERXPOLARITYL5_out, + PIPERXPOLARITYL6_out, + PIPERXPOLARITYL7_out, + PIPETXCOMPLIANCEL0_out, + PIPETXCOMPLIANCEL1_out, + PIPETXCOMPLIANCEL2_out, + PIPETXCOMPLIANCEL3_out, + PIPETXCOMPLIANCEL4_out, + PIPETXCOMPLIANCEL5_out, + PIPETXCOMPLIANCEL6_out, + PIPETXCOMPLIANCEL7_out, + PIPETXDATAKL0_out, + PIPETXDATAKL1_out, + PIPETXDATAKL2_out, + PIPETXDATAKL3_out, + PIPETXDATAKL4_out, + PIPETXDATAKL5_out, + PIPETXDATAKL6_out, + PIPETXDATAKL7_out, + PIPETXDATAL0_out, + PIPETXDATAL1_out, + PIPETXDATAL2_out, + PIPETXDATAL3_out, + PIPETXDATAL4_out, + PIPETXDATAL5_out, + PIPETXDATAL6_out, + PIPETXDATAL7_out, + PIPETXDETECTRXLOOPBACKL0_out, + PIPETXDETECTRXLOOPBACKL1_out, + PIPETXDETECTRXLOOPBACKL2_out, + PIPETXDETECTRXLOOPBACKL3_out, + PIPETXDETECTRXLOOPBACKL4_out, + PIPETXDETECTRXLOOPBACKL5_out, + PIPETXDETECTRXLOOPBACKL6_out, + PIPETXDETECTRXLOOPBACKL7_out, + PIPETXELECIDLEL0_out, + PIPETXELECIDLEL1_out, + PIPETXELECIDLEL2_out, + PIPETXELECIDLEL3_out, + PIPETXELECIDLEL4_out, + PIPETXELECIDLEL5_out, + PIPETXELECIDLEL6_out, + PIPETXELECIDLEL7_out, + SERRENABLE_out, + URREPORTINGENABLE_out, + + AUXPOWER_ipd, + CFGNEGOTIATEDLINKWIDTH_ipd, + COMPLIANCEAVOID_ipd, + CRMCFGBRIDGEHOTRESET_ipd, + CRMCORECLKDLO_ipd, + CRMCORECLKRXO_ipd, + CRMCORECLKTXO_ipd, + CRMCORECLK_ipd, + CRMLINKRSTN_ipd, + CRMMACRSTN_ipd, + CRMMGMTRSTN_ipd, + CRMNVRSTN_ipd, + CRMTXHOTRESETN_ipd, + CRMURSTN_ipd, + CRMUSERCFGRSTN_ipd, + CRMUSERCLKRXO_ipd, + CRMUSERCLKTXO_ipd, + CRMUSERCLK_ipd, + CROSSLINKSEED_ipd, + L0ACKNAKTIMERADJUSTMENT_ipd, + L0ALLDOWNPORTSINL1_ipd, + L0ALLDOWNRXPORTSINL0S_ipd, + L0ASE_ipd, + L0ASPORTCOUNT_ipd, + L0ASTURNPOOLBITSCONSUMED_ipd, + L0ATTENTIONBUTTONPRESSED_ipd, + L0CFGASSPANTREEOWNEDSTATE_ipd, + L0CFGASSTATECHANGECMD_ipd, + L0CFGDISABLESCRAMBLE_ipd, + L0CFGEXTENDEDSYNC_ipd, + L0CFGL0SENTRYENABLE_ipd, + L0CFGL0SENTRYSUP_ipd, + L0CFGL0SEXITLAT_ipd, + L0CFGLINKDISABLE_ipd, + L0CFGLOOPBACKMASTER_ipd, + L0CFGNEGOTIATEDMAXP_ipd, + L0CFGVCENABLE_ipd, + L0CFGVCID_ipd, + L0DLLHOLDLINKUP_ipd, + L0ELECTROMECHANICALINTERLOCKENGAGED_ipd, + L0FWDASSERTINTALEGACYINT_ipd, + L0FWDASSERTINTBLEGACYINT_ipd, + L0FWDASSERTINTCLEGACYINT_ipd, + L0FWDASSERTINTDLEGACYINT_ipd, + L0FWDCORRERRIN_ipd, + L0FWDDEASSERTINTALEGACYINT_ipd, + L0FWDDEASSERTINTBLEGACYINT_ipd, + L0FWDDEASSERTINTCLEGACYINT_ipd, + L0FWDDEASSERTINTDLEGACYINT_ipd, + L0FWDFATALERRIN_ipd, + L0FWDNONFATALERRIN_ipd, + L0LEGACYINTFUNCT0_ipd, + L0MRLSENSORCLOSEDN_ipd, + L0MSIREQUEST0_ipd, + L0PACKETHEADERFROMUSER_ipd, + L0PMEREQIN_ipd, + L0PORTNUMBER_ipd, + L0POWERFAULTDETECTED_ipd, + L0PRESENCEDETECTSLOTEMPTYN_ipd, + L0PWRNEWSTATEREQ_ipd, + L0PWRNEXTLINKSTATE_ipd, + L0REPLAYTIMERADJUSTMENT_ipd, + L0ROOTTURNOFFREQ_ipd, + L0RXTLTLPNONINITIALIZEDVC_ipd, + L0SENDUNLOCKMESSAGE_ipd, + L0SETCOMPLETERABORTERROR_ipd, + L0SETCOMPLETIONTIMEOUTCORRERROR_ipd, + L0SETCOMPLETIONTIMEOUTUNCORRERROR_ipd, + L0SETDETECTEDCORRERROR_ipd, + L0SETDETECTEDFATALERROR_ipd, + L0SETDETECTEDNONFATALERROR_ipd, + L0SETLINKDETECTEDPARITYERROR_ipd, + L0SETLINKMASTERDATAPARITY_ipd, + L0SETLINKRECEIVEDMASTERABORT_ipd, + L0SETLINKRECEIVEDTARGETABORT_ipd, + L0SETLINKSIGNALLEDTARGETABORT_ipd, + L0SETLINKSYSTEMERROR_ipd, + L0SETUNEXPECTEDCOMPLETIONCORRERROR_ipd, + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_ipd, + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_ipd, + L0SETUNSUPPORTEDREQUESTOTHERERROR_ipd, + L0SETUSERDETECTEDPARITYERROR_ipd, + L0SETUSERMASTERDATAPARITY_ipd, + L0SETUSERRECEIVEDMASTERABORT_ipd, + L0SETUSERRECEIVEDTARGETABORT_ipd, + L0SETUSERSIGNALLEDTARGETABORT_ipd, + L0SETUSERSYSTEMERROR_ipd, + L0TLASFCCREDSTARVATION_ipd, + L0TLLINKRETRAIN_ipd, + L0TRANSACTIONSPENDING_ipd, + L0TXBEACON_ipd, + L0TXCFGPMTYPE_ipd, + L0TXCFGPM_ipd, + L0TXTLFCCMPLMCCRED_ipd, + L0TXTLFCCMPLMCUPDATE_ipd, + L0TXTLFCNPOSTBYPCRED_ipd, + L0TXTLFCNPOSTBYPUPDATE_ipd, + L0TXTLFCPOSTORDCRED_ipd, + L0TXTLFCPOSTORDUPDATE_ipd, + L0TXTLSBFCDATA_ipd, + L0TXTLSBFCUPDATE_ipd, + L0TXTLTLPDATA_ipd, + L0TXTLTLPEDB_ipd, + L0TXTLTLPENABLE_ipd, + L0TXTLTLPEND_ipd, + L0TXTLTLPLATENCY_ipd, + L0TXTLTLPREQEND_ipd, + L0TXTLTLPREQ_ipd, + L0TXTLTLPWIDTH_ipd, + L0UPSTREAMRXPORTINL0S_ipd, + L0VC0PREVIEWEXPAND_ipd, + L0WAKEN_ipd, + LLKRXCHFIFO_ipd, + LLKRXCHTC_ipd, + LLKRXDSTCONTREQN_ipd, + LLKRXDSTREQN_ipd, + LLKTX4DWHEADERN_ipd, + LLKTXCHFIFO_ipd, + LLKTXCHTC_ipd, + LLKTXCOMPLETEN_ipd, + LLKTXCREATEECRCN_ipd, + LLKTXDATA_ipd, + LLKTXENABLEN_ipd, + LLKTXEOFN_ipd, + LLKTXEOPN_ipd, + LLKTXSOFN_ipd, + LLKTXSOPN_ipd, + LLKTXSRCDSCN_ipd, + LLKTXSRCRDYN_ipd, + MAINPOWER_ipd, + MGMTADDR_ipd, + MGMTBWREN_ipd, + MGMTRDEN_ipd, + MGMTSTATSCREDITSEL_ipd, + MGMTWDATA_ipd, + MGMTWREN_ipd, + MIMDLLBRDATA_ipd, + MIMRXBRDATA_ipd, + MIMTXBRDATA_ipd, + PIPEPHYSTATUSL0_ipd, + PIPEPHYSTATUSL1_ipd, + PIPEPHYSTATUSL2_ipd, + PIPEPHYSTATUSL3_ipd, + PIPEPHYSTATUSL4_ipd, + PIPEPHYSTATUSL5_ipd, + PIPEPHYSTATUSL6_ipd, + PIPEPHYSTATUSL7_ipd, + PIPERXCHANISALIGNEDL0_ipd, + PIPERXCHANISALIGNEDL1_ipd, + PIPERXCHANISALIGNEDL2_ipd, + PIPERXCHANISALIGNEDL3_ipd, + PIPERXCHANISALIGNEDL4_ipd, + PIPERXCHANISALIGNEDL5_ipd, + PIPERXCHANISALIGNEDL6_ipd, + PIPERXCHANISALIGNEDL7_ipd, + PIPERXDATAKL0_ipd, + PIPERXDATAKL1_ipd, + PIPERXDATAKL2_ipd, + PIPERXDATAKL3_ipd, + PIPERXDATAKL4_ipd, + PIPERXDATAKL5_ipd, + PIPERXDATAKL6_ipd, + PIPERXDATAKL7_ipd, + PIPERXDATAL0_ipd, + PIPERXDATAL1_ipd, + PIPERXDATAL2_ipd, + PIPERXDATAL3_ipd, + PIPERXDATAL4_ipd, + PIPERXDATAL5_ipd, + PIPERXDATAL6_ipd, + PIPERXDATAL7_ipd, + PIPERXELECIDLEL0_ipd, + PIPERXELECIDLEL1_ipd, + PIPERXELECIDLEL2_ipd, + PIPERXELECIDLEL3_ipd, + PIPERXELECIDLEL4_ipd, + PIPERXELECIDLEL5_ipd, + PIPERXELECIDLEL6_ipd, + PIPERXELECIDLEL7_ipd, + PIPERXSTATUSL0_ipd, + PIPERXSTATUSL1_ipd, + PIPERXSTATUSL2_ipd, + PIPERXSTATUSL3_ipd, + PIPERXSTATUSL4_ipd, + PIPERXSTATUSL5_ipd, + PIPERXSTATUSL6_ipd, + PIPERXSTATUSL7_ipd, + PIPERXVALIDL0_ipd, + PIPERXVALIDL1_ipd, + PIPERXVALIDL2_ipd, + PIPERXVALIDL3_ipd, + PIPERXVALIDL4_ipd, + PIPERXVALIDL5_ipd, + PIPERXVALIDL6_ipd, + PIPERXVALIDL7_ipd; + + end process TIMING; + + +end PCIE_INTERNAL_1_1_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2006 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Tri-Mode Ethernet MAC +-- /___/ /\ Filename : temac.vhd +-- \ \ / \ Timestamp : Thu Dec 8 2005 +-- \___\/\___\ +-- +-- Revision: +-- 12/08/05 - Initial version. +-- 01/09/06 - Added architecture +-- 02/06/06 - pinTime updates +-- 02/23/06 - Updated Header +-- 03/10/06 - CR#226740. Changed generic type of some of the generics from +-- string to boolean +-- 03/27/06 - Updated TEMAC smartmodel to version number 00.002 for following changes +-- CR#224695 - +-- 1. TEMAC smartmodel 16 bit client interface problem. +-- 2. Compiled smartmodel with `delay_mode_zero directive +-- CR#226083 - +-- 1. Loopback attributes don't work in Verilog TEMAC smartmodel. +-- CR#224695 - +-- 1 . Added 50 ps input delay to all inputs(except clocks) going into temac swift model +-- 04/11/06 - CR#228762 - Added some missing path delays to timing block. +-- 04/27/06 - CR#230105 - Fixed connectivity for CLK +-- 05/23/06 - CR#231962 - Add buffers for connectivity +-- 09/15/06 - CR#423162 - Timing updates +-- 10/26/06 - - replaced ZERO_DELAY with CLK_DELAY to be consistent with writers (PPC440 update) +-- 06/08/07 - CR#440717 - Add constant EMAC0MIITXCLK_DELAY & EMAC1MIITXCLK_DELAY +-- 08/28/07 - CR#447575 - Path Delay updates due to pinDev/pinTime updates +-- End Revision + + +----- CELL TEMAC ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +library secureip; +use secureip.all; + +entity TEMAC is +generic ( + EMAC0_1000BASEX_ENABLE : boolean := FALSE; + EMAC0_ADDRFILTER_ENABLE : boolean := FALSE; + EMAC0_BYTEPHY : boolean := FALSE; + EMAC0_CONFIGVEC_79 : boolean := FALSE; + EMAC0_DCRBASEADDR : bit_vector := X"00"; + EMAC0_GTLOOPBACK : boolean := FALSE; + EMAC0_HOST_ENABLE : boolean := FALSE; + EMAC0_LINKTIMERVAL : bit_vector := X"000"; + EMAC0_LTCHECK_DISABLE : boolean := FALSE; + EMAC0_MDIO_ENABLE : boolean := FALSE; + EMAC0_PAUSEADDR : bit_vector := X"000000000000"; + EMAC0_PHYINITAUTONEG_ENABLE : boolean := FALSE; + EMAC0_PHYISOLATE : boolean := FALSE; + EMAC0_PHYLOOPBACKMSB : boolean := FALSE; + EMAC0_PHYPOWERDOWN : boolean := FALSE; + EMAC0_PHYRESET : boolean := FALSE; + EMAC0_RGMII_ENABLE : boolean := FALSE; + EMAC0_RX16BITCLIENT_ENABLE : boolean := FALSE; + EMAC0_RXFLOWCTRL_ENABLE : boolean := FALSE; + EMAC0_RXHALFDUPLEX : boolean := FALSE; + EMAC0_RXINBANDFCS_ENABLE : boolean := FALSE; + EMAC0_RXJUMBOFRAME_ENABLE : boolean := FALSE; + EMAC0_RXRESET : boolean := FALSE; + EMAC0_RXVLAN_ENABLE : boolean := FALSE; + EMAC0_RX_ENABLE : boolean := FALSE; + EMAC0_SGMII_ENABLE : boolean := FALSE; + EMAC0_SPEED_LSB : boolean := FALSE; + EMAC0_SPEED_MSB : boolean := FALSE; + EMAC0_TX16BITCLIENT_ENABLE : boolean := FALSE; + EMAC0_TXFLOWCTRL_ENABLE : boolean := FALSE; + EMAC0_TXHALFDUPLEX : boolean := FALSE; + EMAC0_TXIFGADJUST_ENABLE : boolean := FALSE; + EMAC0_TXINBANDFCS_ENABLE : boolean := FALSE; + EMAC0_TXJUMBOFRAME_ENABLE : boolean := FALSE; + EMAC0_TXRESET : boolean := FALSE; + EMAC0_TXVLAN_ENABLE : boolean := FALSE; + EMAC0_TX_ENABLE : boolean := FALSE; + EMAC0_UNICASTADDR : bit_vector := X"000000000000"; + EMAC0_UNIDIRECTION_ENABLE : boolean := FALSE; + EMAC0_USECLKEN : boolean := FALSE; + EMAC1_1000BASEX_ENABLE : boolean := FALSE; + EMAC1_ADDRFILTER_ENABLE : boolean := FALSE; + EMAC1_BYTEPHY : boolean := FALSE; + EMAC1_CONFIGVEC_79 : boolean := FALSE; + EMAC1_DCRBASEADDR : bit_vector := X"00"; + EMAC1_GTLOOPBACK : boolean := FALSE; + EMAC1_HOST_ENABLE : boolean := FALSE; + EMAC1_LINKTIMERVAL : bit_vector := X"000"; + EMAC1_LTCHECK_DISABLE : boolean := FALSE; + EMAC1_MDIO_ENABLE : boolean := FALSE; + EMAC1_PAUSEADDR : bit_vector := X"000000000000"; + EMAC1_PHYINITAUTONEG_ENABLE : boolean := FALSE; + EMAC1_PHYISOLATE : boolean := FALSE; + EMAC1_PHYLOOPBACKMSB : boolean := FALSE; + EMAC1_PHYPOWERDOWN : boolean := FALSE; + EMAC1_PHYRESET : boolean := FALSE; + EMAC1_RGMII_ENABLE : boolean := FALSE; + EMAC1_RX16BITCLIENT_ENABLE : boolean := FALSE; + EMAC1_RXFLOWCTRL_ENABLE : boolean := FALSE; + EMAC1_RXHALFDUPLEX : boolean := FALSE; + EMAC1_RXINBANDFCS_ENABLE : boolean := FALSE; + EMAC1_RXJUMBOFRAME_ENABLE : boolean := FALSE; + EMAC1_RXRESET : boolean := FALSE; + EMAC1_RXVLAN_ENABLE : boolean := FALSE; + EMAC1_RX_ENABLE : boolean := FALSE; + EMAC1_SGMII_ENABLE : boolean := FALSE; + EMAC1_SPEED_LSB : boolean := FALSE; + EMAC1_SPEED_MSB : boolean := FALSE; + EMAC1_TX16BITCLIENT_ENABLE : boolean := FALSE; + EMAC1_TXFLOWCTRL_ENABLE : boolean := FALSE; + EMAC1_TXHALFDUPLEX : boolean := FALSE; + EMAC1_TXIFGADJUST_ENABLE : boolean := FALSE; + EMAC1_TXINBANDFCS_ENABLE : boolean := FALSE; + EMAC1_TXJUMBOFRAME_ENABLE : boolean := FALSE; + EMAC1_TXRESET : boolean := FALSE; + EMAC1_TXVLAN_ENABLE : boolean := FALSE; + EMAC1_TX_ENABLE : boolean := FALSE; + EMAC1_UNICASTADDR : bit_vector := X"000000000000"; + EMAC1_UNIDIRECTION_ENABLE : boolean := FALSE; + EMAC1_USECLKEN : boolean := FALSE + ); + +port ( + DCRHOSTDONEIR : out std_ulogic; + EMAC0CLIENTANINTERRUPT : out std_ulogic; + EMAC0CLIENTRXBADFRAME : out std_ulogic; + EMAC0CLIENTRXCLIENTCLKOUT : out std_ulogic; + EMAC0CLIENTRXD : out std_logic_vector(15 downto 0); + EMAC0CLIENTRXDVLD : out std_ulogic; + EMAC0CLIENTRXDVLDMSW : out std_ulogic; + EMAC0CLIENTRXFRAMEDROP : out std_ulogic; + EMAC0CLIENTRXGOODFRAME : out std_ulogic; + EMAC0CLIENTRXSTATS : out std_logic_vector(6 downto 0); + EMAC0CLIENTRXSTATSBYTEVLD : out std_ulogic; + EMAC0CLIENTRXSTATSVLD : out std_ulogic; + EMAC0CLIENTTXACK : out std_ulogic; + EMAC0CLIENTTXCLIENTCLKOUT : out std_ulogic; + EMAC0CLIENTTXCOLLISION : out std_ulogic; + EMAC0CLIENTTXRETRANSMIT : out std_ulogic; + EMAC0CLIENTTXSTATS : out std_ulogic; + EMAC0CLIENTTXSTATSBYTEVLD : out std_ulogic; + EMAC0CLIENTTXSTATSVLD : out std_ulogic; + EMAC0PHYENCOMMAALIGN : out std_ulogic; + EMAC0PHYLOOPBACKMSB : out std_ulogic; + EMAC0PHYMCLKOUT : out std_ulogic; + EMAC0PHYMDOUT : out std_ulogic; + EMAC0PHYMDTRI : out std_ulogic; + EMAC0PHYMGTRXRESET : out std_ulogic; + EMAC0PHYMGTTXRESET : out std_ulogic; + EMAC0PHYPOWERDOWN : out std_ulogic; + EMAC0PHYSYNCACQSTATUS : out std_ulogic; + EMAC0PHYTXCHARDISPMODE : out std_ulogic; + EMAC0PHYTXCHARDISPVAL : out std_ulogic; + EMAC0PHYTXCHARISK : out std_ulogic; + EMAC0PHYTXCLK : out std_ulogic; + EMAC0PHYTXD : out std_logic_vector(7 downto 0); + EMAC0PHYTXEN : out std_ulogic; + EMAC0PHYTXER : out std_ulogic; + EMAC0PHYTXGMIIMIICLKOUT : out std_ulogic; + EMAC0SPEEDIS10100 : out std_ulogic; + EMAC1CLIENTANINTERRUPT : out std_ulogic; + EMAC1CLIENTRXBADFRAME : out std_ulogic; + EMAC1CLIENTRXCLIENTCLKOUT : out std_ulogic; + EMAC1CLIENTRXD : out std_logic_vector(15 downto 0); + EMAC1CLIENTRXDVLD : out std_ulogic; + EMAC1CLIENTRXDVLDMSW : out std_ulogic; + EMAC1CLIENTRXFRAMEDROP : out std_ulogic; + EMAC1CLIENTRXGOODFRAME : out std_ulogic; + EMAC1CLIENTRXSTATS : out std_logic_vector(6 downto 0); + EMAC1CLIENTRXSTATSBYTEVLD : out std_ulogic; + EMAC1CLIENTRXSTATSVLD : out std_ulogic; + EMAC1CLIENTTXACK : out std_ulogic; + EMAC1CLIENTTXCLIENTCLKOUT : out std_ulogic; + EMAC1CLIENTTXCOLLISION : out std_ulogic; + EMAC1CLIENTTXRETRANSMIT : out std_ulogic; + EMAC1CLIENTTXSTATS : out std_ulogic; + EMAC1CLIENTTXSTATSBYTEVLD : out std_ulogic; + EMAC1CLIENTTXSTATSVLD : out std_ulogic; + EMAC1PHYENCOMMAALIGN : out std_ulogic; + EMAC1PHYLOOPBACKMSB : out std_ulogic; + EMAC1PHYMCLKOUT : out std_ulogic; + EMAC1PHYMDOUT : out std_ulogic; + EMAC1PHYMDTRI : out std_ulogic; + EMAC1PHYMGTRXRESET : out std_ulogic; + EMAC1PHYMGTTXRESET : out std_ulogic; + EMAC1PHYPOWERDOWN : out std_ulogic; + EMAC1PHYSYNCACQSTATUS : out std_ulogic; + EMAC1PHYTXCHARDISPMODE : out std_ulogic; + EMAC1PHYTXCHARDISPVAL : out std_ulogic; + EMAC1PHYTXCHARISK : out std_ulogic; + EMAC1PHYTXCLK : out std_ulogic; + EMAC1PHYTXD : out std_logic_vector(7 downto 0); + EMAC1PHYTXEN : out std_ulogic; + EMAC1PHYTXER : out std_ulogic; + EMAC1PHYTXGMIIMIICLKOUT : out std_ulogic; + EMAC1SPEEDIS10100 : out std_ulogic; + EMACDCRACK : out std_ulogic; + EMACDCRDBUS : out std_logic_vector(0 to 31); + HOSTMIIMRDY : out std_ulogic; + HOSTRDDATA : out std_logic_vector(31 downto 0); + + CLIENTEMAC0DCMLOCKED : in std_ulogic; + CLIENTEMAC0PAUSEREQ : in std_ulogic; + CLIENTEMAC0PAUSEVAL : in std_logic_vector(15 downto 0); + CLIENTEMAC0RXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC0TXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC0TXD : in std_logic_vector(15 downto 0); + CLIENTEMAC0TXDVLD : in std_ulogic; + CLIENTEMAC0TXDVLDMSW : in std_ulogic; + CLIENTEMAC0TXFIRSTBYTE : in std_ulogic; + CLIENTEMAC0TXIFGDELAY : in std_logic_vector(7 downto 0); + CLIENTEMAC0TXUNDERRUN : in std_ulogic; + CLIENTEMAC1DCMLOCKED : in std_ulogic; + CLIENTEMAC1PAUSEREQ : in std_ulogic; + CLIENTEMAC1PAUSEVAL : in std_logic_vector(15 downto 0); + CLIENTEMAC1RXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC1TXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC1TXD : in std_logic_vector(15 downto 0); + CLIENTEMAC1TXDVLD : in std_ulogic; + CLIENTEMAC1TXDVLDMSW : in std_ulogic; + CLIENTEMAC1TXFIRSTBYTE : in std_ulogic; + CLIENTEMAC1TXIFGDELAY : in std_logic_vector(7 downto 0); + CLIENTEMAC1TXUNDERRUN : in std_ulogic; + DCREMACABUS : in std_logic_vector(0 to 9); + DCREMACCLK : in std_ulogic; + DCREMACDBUS : in std_logic_vector(0 to 31); + DCREMACENABLE : in std_ulogic; + DCREMACREAD : in std_ulogic; + DCREMACWRITE : in std_ulogic; + HOSTADDR : in std_logic_vector(9 downto 0); + HOSTCLK : in std_ulogic; + HOSTEMAC1SEL : in std_ulogic; + HOSTMIIMSEL : in std_ulogic; + HOSTOPCODE : in std_logic_vector(1 downto 0); + HOSTREQ : in std_ulogic; + HOSTWRDATA : in std_logic_vector(31 downto 0); + PHYEMAC0COL : in std_ulogic; + PHYEMAC0CRS : in std_ulogic; + PHYEMAC0GTXCLK : in std_ulogic; + PHYEMAC0MCLKIN : in std_ulogic; + PHYEMAC0MDIN : in std_ulogic; + PHYEMAC0MIITXCLK : in std_ulogic; + PHYEMAC0PHYAD : in std_logic_vector(4 downto 0); + PHYEMAC0RXBUFERR : in std_ulogic; + PHYEMAC0RXBUFSTATUS : in std_logic_vector(1 downto 0); + PHYEMAC0RXCHARISCOMMA : in std_ulogic; + PHYEMAC0RXCHARISK : in std_ulogic; + PHYEMAC0RXCHECKINGCRC : in std_ulogic; + PHYEMAC0RXCLK : in std_ulogic; + PHYEMAC0RXCLKCORCNT : in std_logic_vector(2 downto 0); + PHYEMAC0RXCOMMADET : in std_ulogic; + PHYEMAC0RXD : in std_logic_vector(7 downto 0); + PHYEMAC0RXDISPERR : in std_ulogic; + PHYEMAC0RXDV : in std_ulogic; + PHYEMAC0RXER : in std_ulogic; + PHYEMAC0RXLOSSOFSYNC : in std_logic_vector(1 downto 0); + PHYEMAC0RXNOTINTABLE : in std_ulogic; + PHYEMAC0RXRUNDISP : in std_ulogic; + PHYEMAC0SIGNALDET : in std_ulogic; + PHYEMAC0TXBUFERR : in std_ulogic; + PHYEMAC0TXGMIIMIICLKIN : in std_ulogic; + PHYEMAC1COL : in std_ulogic; + PHYEMAC1CRS : in std_ulogic; + PHYEMAC1GTXCLK : in std_ulogic; + PHYEMAC1MCLKIN : in std_ulogic; + PHYEMAC1MDIN : in std_ulogic; + PHYEMAC1MIITXCLK : in std_ulogic; + PHYEMAC1PHYAD : in std_logic_vector(4 downto 0); + PHYEMAC1RXBUFERR : in std_ulogic; + PHYEMAC1RXBUFSTATUS : in std_logic_vector(1 downto 0); + PHYEMAC1RXCHARISCOMMA : in std_ulogic; + PHYEMAC1RXCHARISK : in std_ulogic; + PHYEMAC1RXCHECKINGCRC : in std_ulogic; + PHYEMAC1RXCLK : in std_ulogic; + PHYEMAC1RXCLKCORCNT : in std_logic_vector(2 downto 0); + PHYEMAC1RXCOMMADET : in std_ulogic; + PHYEMAC1RXD : in std_logic_vector(7 downto 0); + PHYEMAC1RXDISPERR : in std_ulogic; + PHYEMAC1RXDV : in std_ulogic; + PHYEMAC1RXER : in std_ulogic; + PHYEMAC1RXLOSSOFSYNC : in std_logic_vector(1 downto 0); + PHYEMAC1RXNOTINTABLE : in std_ulogic; + PHYEMAC1RXRUNDISP : in std_ulogic; + PHYEMAC1SIGNALDET : in std_ulogic; + PHYEMAC1TXBUFERR : in std_ulogic; + PHYEMAC1TXGMIIMIICLKIN : in std_ulogic; + RESET : in std_ulogic + ); +end TEMAC; + +architecture TEMAC_V of TEMAC is + + + + component TEMAC_SWIFT + port ( + DCRHOSTDONEIR : out std_ulogic; + EMAC0CLIENTANINTERRUPT : out std_ulogic; + EMAC0CLIENTRXBADFRAME : out std_ulogic; + EMAC0CLIENTRXCLIENTCLKOUT : out std_ulogic; + EMAC0CLIENTRXD : out std_logic_vector(15 downto 0); + EMAC0CLIENTRXDVLD : out std_ulogic; + EMAC0CLIENTRXDVLDMSW : out std_ulogic; + EMAC0CLIENTRXFRAMEDROP : out std_ulogic; + EMAC0CLIENTRXGOODFRAME : out std_ulogic; + EMAC0CLIENTRXSTATS : out std_logic_vector(6 downto 0); + EMAC0CLIENTRXSTATSBYTEVLD : out std_ulogic; + EMAC0CLIENTRXSTATSVLD : out std_ulogic; + EMAC0CLIENTTXACK : out std_ulogic; + EMAC0CLIENTTXCLIENTCLKOUT : out std_ulogic; + EMAC0CLIENTTXCOLLISION : out std_ulogic; + EMAC0CLIENTTXRETRANSMIT : out std_ulogic; + EMAC0CLIENTTXSTATS : out std_ulogic; + EMAC0CLIENTTXSTATSBYTEVLD : out std_ulogic; + EMAC0CLIENTTXSTATSVLD : out std_ulogic; + EMAC0PHYENCOMMAALIGN : out std_ulogic; + EMAC0PHYLOOPBACKMSB : out std_ulogic; + EMAC0PHYMCLKOUT : out std_ulogic; + EMAC0PHYMDOUT : out std_ulogic; + EMAC0PHYMDTRI : out std_ulogic; + EMAC0PHYMGTRXRESET : out std_ulogic; + EMAC0PHYMGTTXRESET : out std_ulogic; + EMAC0PHYPOWERDOWN : out std_ulogic; + EMAC0PHYSYNCACQSTATUS : out std_ulogic; + EMAC0PHYTXCHARDISPMODE : out std_ulogic; + EMAC0PHYTXCHARDISPVAL : out std_ulogic; + EMAC0PHYTXCHARISK : out std_ulogic; + EMAC0PHYTXCLK : out std_ulogic; + EMAC0PHYTXD : out std_logic_vector(7 downto 0); + EMAC0PHYTXEN : out std_ulogic; + EMAC0PHYTXER : out std_ulogic; + EMAC0PHYTXGMIIMIICLKOUT : out std_ulogic; + EMAC0SPEEDIS10100 : out std_ulogic; + EMAC1CLIENTANINTERRUPT : out std_ulogic; + EMAC1CLIENTRXBADFRAME : out std_ulogic; + EMAC1CLIENTRXCLIENTCLKOUT : out std_ulogic; + EMAC1CLIENTRXD : out std_logic_vector(15 downto 0); + EMAC1CLIENTRXDVLD : out std_ulogic; + EMAC1CLIENTRXDVLDMSW : out std_ulogic; + EMAC1CLIENTRXFRAMEDROP : out std_ulogic; + EMAC1CLIENTRXGOODFRAME : out std_ulogic; + EMAC1CLIENTRXSTATS : out std_logic_vector(6 downto 0); + EMAC1CLIENTRXSTATSBYTEVLD : out std_ulogic; + EMAC1CLIENTRXSTATSVLD : out std_ulogic; + EMAC1CLIENTTXACK : out std_ulogic; + EMAC1CLIENTTXCLIENTCLKOUT : out std_ulogic; + EMAC1CLIENTTXCOLLISION : out std_ulogic; + EMAC1CLIENTTXRETRANSMIT : out std_ulogic; + EMAC1CLIENTTXSTATS : out std_ulogic; + EMAC1CLIENTTXSTATSBYTEVLD : out std_ulogic; + EMAC1CLIENTTXSTATSVLD : out std_ulogic; + EMAC1PHYENCOMMAALIGN : out std_ulogic; + EMAC1PHYLOOPBACKMSB : out std_ulogic; + EMAC1PHYMCLKOUT : out std_ulogic; + EMAC1PHYMDOUT : out std_ulogic; + EMAC1PHYMDTRI : out std_ulogic; + EMAC1PHYMGTRXRESET : out std_ulogic; + EMAC1PHYMGTTXRESET : out std_ulogic; + EMAC1PHYPOWERDOWN : out std_ulogic; + EMAC1PHYSYNCACQSTATUS : out std_ulogic; + EMAC1PHYTXCHARDISPMODE : out std_ulogic; + EMAC1PHYTXCHARDISPVAL : out std_ulogic; + EMAC1PHYTXCHARISK : out std_ulogic; + EMAC1PHYTXCLK : out std_ulogic; + EMAC1PHYTXD : out std_logic_vector(7 downto 0); + EMAC1PHYTXEN : out std_ulogic; + EMAC1PHYTXER : out std_ulogic; + EMAC1PHYTXGMIIMIICLKOUT : out std_ulogic; + EMAC1SPEEDIS10100 : out std_ulogic; + EMACDCRACK : out std_ulogic; + EMACDCRDBUS : out std_logic_vector(0 to 31); + HOSTMIIMRDY : out std_ulogic; + HOSTRDDATA : out std_logic_vector(31 downto 0); + + CLIENTEMAC0DCMLOCKED : in std_ulogic; + CLIENTEMAC0PAUSEREQ : in std_ulogic; + CLIENTEMAC0PAUSEVAL : in std_logic_vector(15 downto 0); + CLIENTEMAC0RXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC0TXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC0TXD : in std_logic_vector(15 downto 0); + CLIENTEMAC0TXDVLD : in std_ulogic; + CLIENTEMAC0TXDVLDMSW : in std_ulogic; + CLIENTEMAC0TXFIRSTBYTE : in std_ulogic; + CLIENTEMAC0TXIFGDELAY : in std_logic_vector(7 downto 0); + CLIENTEMAC0TXUNDERRUN : in std_ulogic; + CLIENTEMAC1DCMLOCKED : in std_ulogic; + CLIENTEMAC1PAUSEREQ : in std_ulogic; + CLIENTEMAC1PAUSEVAL : in std_logic_vector(15 downto 0); + CLIENTEMAC1RXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC1TXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC1TXD : in std_logic_vector(15 downto 0); + CLIENTEMAC1TXDVLD : in std_ulogic; + CLIENTEMAC1TXDVLDMSW : in std_ulogic; + CLIENTEMAC1TXFIRSTBYTE : in std_ulogic; + CLIENTEMAC1TXIFGDELAY : in std_logic_vector(7 downto 0); + CLIENTEMAC1TXUNDERRUN : in std_ulogic; + DCREMACABUS : in std_logic_vector(0 to 9); + DCREMACCLK : in std_ulogic; + DCREMACDBUS : in std_logic_vector(0 to 31); + DCREMACENABLE : in std_ulogic; + DCREMACREAD : in std_ulogic; + DCREMACWRITE : in std_ulogic; + HOSTADDR : in std_logic_vector(9 downto 0); + HOSTCLK : in std_ulogic; + HOSTEMAC1SEL : in std_ulogic; + HOSTMIIMSEL : in std_ulogic; + HOSTOPCODE : in std_logic_vector(1 downto 0); + HOSTREQ : in std_ulogic; + HOSTWRDATA : in std_logic_vector(31 downto 0); + PHYEMAC0COL : in std_ulogic; + PHYEMAC0CRS : in std_ulogic; + PHYEMAC0GTXCLK : in std_ulogic; + PHYEMAC0MCLKIN : in std_ulogic; + PHYEMAC0MDIN : in std_ulogic; + PHYEMAC0MIITXCLK : in std_ulogic; + PHYEMAC0PHYAD : in std_logic_vector(4 downto 0); + PHYEMAC0RXBUFERR : in std_ulogic; + PHYEMAC0RXBUFSTATUS : in std_logic_vector(1 downto 0); + PHYEMAC0RXCHARISCOMMA : in std_ulogic; + PHYEMAC0RXCHARISK : in std_ulogic; + PHYEMAC0RXCHECKINGCRC : in std_ulogic; + PHYEMAC0RXCLK : in std_ulogic; + PHYEMAC0RXCLKCORCNT : in std_logic_vector(2 downto 0); + PHYEMAC0RXCOMMADET : in std_ulogic; + PHYEMAC0RXD : in std_logic_vector(7 downto 0); + PHYEMAC0RXDISPERR : in std_ulogic; + PHYEMAC0RXDV : in std_ulogic; + PHYEMAC0RXER : in std_ulogic; + PHYEMAC0RXLOSSOFSYNC : in std_logic_vector(1 downto 0); + PHYEMAC0RXNOTINTABLE : in std_ulogic; + PHYEMAC0RXRUNDISP : in std_ulogic; + PHYEMAC0SIGNALDET : in std_ulogic; + PHYEMAC0TXBUFERR : in std_ulogic; + PHYEMAC0TXGMIIMIICLKIN : in std_ulogic; + PHYEMAC1COL : in std_ulogic; + PHYEMAC1CRS : in std_ulogic; + PHYEMAC1GTXCLK : in std_ulogic; + PHYEMAC1MCLKIN : in std_ulogic; + PHYEMAC1MDIN : in std_ulogic; + PHYEMAC1MIITXCLK : in std_ulogic; + PHYEMAC1PHYAD : in std_logic_vector(4 downto 0); + PHYEMAC1RXBUFERR : in std_ulogic; + PHYEMAC1RXBUFSTATUS : in std_logic_vector(1 downto 0); + PHYEMAC1RXCHARISCOMMA : in std_ulogic; + PHYEMAC1RXCHARISK : in std_ulogic; + PHYEMAC1RXCHECKINGCRC : in std_ulogic; + PHYEMAC1RXCLK : in std_ulogic; + PHYEMAC1RXCLKCORCNT : in std_logic_vector(2 downto 0); + PHYEMAC1RXCOMMADET : in std_ulogic; + PHYEMAC1RXD : in std_logic_vector(7 downto 0); + PHYEMAC1RXDISPERR : in std_ulogic; + PHYEMAC1RXDV : in std_ulogic; + PHYEMAC1RXER : in std_ulogic; + PHYEMAC1RXLOSSOFSYNC : in std_logic_vector(1 downto 0); + PHYEMAC1RXNOTINTABLE : in std_ulogic; + PHYEMAC1RXRUNDISP : in std_ulogic; + PHYEMAC1SIGNALDET : in std_ulogic; + PHYEMAC1TXBUFERR : in std_ulogic; + PHYEMAC1TXGMIIMIICLKIN : in std_ulogic; + RESET : in std_ulogic; + + EMAC0_1000BASEX_ENABLE : in std_ulogic; + EMAC0_ADDRFILTER_ENABLE : in std_ulogic; + EMAC0_BYTEPHY : in std_ulogic; + EMAC0_CONFIGVEC_79 : in std_ulogic; + EMAC0_DCRBASEADDR : in std_logic_vector(0 to 7); + EMAC0_GTLOOPBACK : in std_ulogic; + EMAC0_HOST_ENABLE : in std_ulogic; + EMAC0_LINKTIMERVAL : in std_logic_vector(8 downto 0); + EMAC0_LTCHECK_DISABLE : in std_ulogic; + EMAC0_MDIO_ENABLE : in std_ulogic; + EMAC0_PAUSEADDR : in std_logic_vector(47 downto 0); + EMAC0_PHYINITAUTONEG_ENABLE : in std_ulogic; + EMAC0_PHYISOLATE : in std_ulogic; + EMAC0_PHYLOOPBACKMSB : in std_ulogic; + EMAC0_PHYPOWERDOWN : in std_ulogic; + EMAC0_PHYRESET : in std_ulogic; + EMAC0_RGMII_ENABLE : in std_ulogic; + EMAC0_RX16BITCLIENT_ENABLE : in std_ulogic; + EMAC0_RXFLOWCTRL_ENABLE : in std_ulogic; + EMAC0_RXHALFDUPLEX : in std_ulogic; + EMAC0_RXINBANDFCS_ENABLE : in std_ulogic; + EMAC0_RXJUMBOFRAME_ENABLE : in std_ulogic; + EMAC0_RXRESET : in std_ulogic; + EMAC0_RXVLAN_ENABLE : in std_ulogic; + EMAC0_RX_ENABLE : in std_ulogic; + EMAC0_SGMII_ENABLE : in std_ulogic; + EMAC0_SPEED_LSB : in std_ulogic; + EMAC0_SPEED_MSB : in std_ulogic; + EMAC0_TX16BITCLIENT_ENABLE : in std_ulogic; + EMAC0_TXFLOWCTRL_ENABLE : in std_ulogic; + EMAC0_TXHALFDUPLEX : in std_ulogic; + EMAC0_TXIFGADJUST_ENABLE : in std_ulogic; + EMAC0_TXINBANDFCS_ENABLE : in std_ulogic; + EMAC0_TXJUMBOFRAME_ENABLE : in std_ulogic; + EMAC0_TXRESET : in std_ulogic; + EMAC0_TXVLAN_ENABLE : in std_ulogic; + EMAC0_TX_ENABLE : in std_ulogic; + EMAC0_UNICASTADDR : in std_logic_vector(47 downto 0); + EMAC0_UNIDIRECTION_ENABLE : in std_ulogic; + EMAC0_USECLKEN : in std_ulogic; + EMAC1_1000BASEX_ENABLE : in std_ulogic; + EMAC1_ADDRFILTER_ENABLE : in std_ulogic; + EMAC1_BYTEPHY : in std_ulogic; + EMAC1_CONFIGVEC_79 : in std_ulogic; + EMAC1_DCRBASEADDR : in std_logic_vector(0 to 7); + EMAC1_GTLOOPBACK : in std_ulogic; + EMAC1_HOST_ENABLE : in std_ulogic; + EMAC1_LINKTIMERVAL : in std_logic_vector(8 downto 0); + EMAC1_LTCHECK_DISABLE : in std_ulogic; + EMAC1_MDIO_ENABLE : in std_ulogic; + EMAC1_PAUSEADDR : in std_logic_vector(47 downto 0); + EMAC1_PHYINITAUTONEG_ENABLE : in std_ulogic; + EMAC1_PHYISOLATE : in std_ulogic; + EMAC1_PHYLOOPBACKMSB : in std_ulogic; + EMAC1_PHYPOWERDOWN : in std_ulogic; + EMAC1_PHYRESET : in std_ulogic; + EMAC1_RGMII_ENABLE : in std_ulogic; + EMAC1_RX16BITCLIENT_ENABLE : in std_ulogic; + EMAC1_RXFLOWCTRL_ENABLE : in std_ulogic; + EMAC1_RXHALFDUPLEX : in std_ulogic; + EMAC1_RXINBANDFCS_ENABLE : in std_ulogic; + EMAC1_RXJUMBOFRAME_ENABLE : in std_ulogic; + EMAC1_RXRESET : in std_ulogic; + EMAC1_RXVLAN_ENABLE : in std_ulogic; + EMAC1_RX_ENABLE : in std_ulogic; + EMAC1_SGMII_ENABLE : in std_ulogic; + EMAC1_SPEED_LSB : in std_ulogic; + EMAC1_SPEED_MSB : in std_ulogic; + EMAC1_TX16BITCLIENT_ENABLE : in std_ulogic; + EMAC1_TXFLOWCTRL_ENABLE : in std_ulogic; + EMAC1_TXHALFDUPLEX : in std_ulogic; + EMAC1_TXIFGADJUST_ENABLE : in std_ulogic; + EMAC1_TXINBANDFCS_ENABLE : in std_ulogic; + EMAC1_TXJUMBOFRAME_ENABLE : in std_ulogic; + EMAC1_TXRESET : in std_ulogic; + EMAC1_TXVLAN_ENABLE : in std_ulogic; + EMAC1_TX_ENABLE : in std_ulogic; + EMAC1_UNICASTADDR : in std_logic_vector(47 downto 0); + EMAC1_UNIDIRECTION_ENABLE : in std_ulogic; + EMAC1_USECLKEN : in std_ulogic + ); + end component; + + + function GetValue_EMAC0 ( + EMAC0_TX16BITCLIENT_ENABLE : in boolean + ) return time is + variable delay_time : time; + begin + case EMAC0_TX16BITCLIENT_ENABLE is + when TRUE => delay_time := 25 ps; + when FALSE => delay_time := 0 ps; + end case; + return delay_time; + end; + + function GetValue_EMAC1 ( + EMAC1_TX16BITCLIENT_ENABLE : in boolean + ) return time is + variable delay_time : time; + begin + case EMAC1_TX16BITCLIENT_ENABLE is + when TRUE => delay_time := 25 ps; + when FALSE => delay_time := 0 ps; + end case; + return delay_time; + end; + constant IN_DELAY : time := 50 ps; + constant OUT_DELAY : time := 0 ps; + constant CLK_DELAY : time := 0 ps; + constant EMAC0MIITXCLK_DELAY : time := GetValue_EMAC0(EMAC0_TX16BITCLIENT_ENABLE); + constant EMAC1MIITXCLK_DELAY : time := GetValue_EMAC1(EMAC1_TX16BITCLIENT_ENABLE); + + constant PATH_DELAY : VitalDelayType01 := (100 ps, 100 ps); + + signal EMAC0_PAUSEADDR_BINARY : std_logic_vector(47 downto 0) := To_StdLogicVector(EMAC0_PAUSEADDR); + signal EMAC0_RXHALFDUPLEX_BINARY : std_ulogic; + signal EMAC0_RXVLAN_ENABLE_BINARY : std_ulogic; + signal EMAC0_RX_ENABLE_BINARY : std_ulogic; + signal EMAC0_RXINBANDFCS_ENABLE_BINARY : std_ulogic; + signal EMAC0_RXJUMBOFRAME_ENABLE_BINARY : std_ulogic; + signal EMAC0_RXRESET_BINARY : std_ulogic; + signal EMAC0_TXIFGADJUST_ENABLE_BINARY : std_ulogic; + signal EMAC0_TXHALFDUPLEX_BINARY : std_ulogic; + signal EMAC0_TXVLAN_ENABLE_BINARY : std_ulogic; + signal EMAC0_TX_ENABLE_BINARY : std_ulogic; + signal EMAC0_TXINBANDFCS_ENABLE_BINARY : std_ulogic; + signal EMAC0_TXJUMBOFRAME_ENABLE_BINARY : std_ulogic; + signal EMAC0_TXRESET_BINARY : std_ulogic; + signal EMAC0_TXFLOWCTRL_ENABLE_BINARY : std_ulogic; + signal EMAC0_RXFLOWCTRL_ENABLE_BINARY : std_ulogic; + signal EMAC0_LTCHECK_DISABLE_BINARY : std_ulogic; + signal EMAC0_ADDRFILTER_ENABLE_BINARY : std_ulogic; + signal EMAC0_RX16BITCLIENT_ENABLE_BINARY : std_ulogic; + signal EMAC0_TX16BITCLIENT_ENABLE_BINARY : std_ulogic; + signal EMAC0_HOST_ENABLE_BINARY : std_ulogic; + signal EMAC0_1000BASEX_ENABLE_BINARY : std_ulogic; + signal EMAC0_SGMII_ENABLE_BINARY : std_ulogic; + signal EMAC0_RGMII_ENABLE_BINARY : std_ulogic; + signal EMAC0_SPEED_LSB_BINARY : std_ulogic; + signal EMAC0_SPEED_MSB_BINARY : std_ulogic; + signal EMAC0_MDIO_ENABLE_BINARY : std_ulogic; + signal EMAC0_PHYLOOPBACKMSB_BINARY : std_ulogic; + signal EMAC0_PHYPOWERDOWN_BINARY : std_ulogic; + signal EMAC0_PHYISOLATE_BINARY : std_ulogic; + signal EMAC0_PHYINITAUTONEG_ENABLE_BINARY : std_ulogic; + signal EMAC0_PHYRESET_BINARY : std_ulogic; + signal EMAC0_CONFIGVEC_79_BINARY : std_ulogic; + signal EMAC0_UNIDIRECTION_ENABLE_BINARY : std_ulogic; + signal EMAC0_GTLOOPBACK_BINARY : std_ulogic; + signal EMAC0_UNICASTADDR_BINARY : std_logic_vector(47 downto 0) := To_StdLogicVector(EMAC0_UNICASTADDR); + signal EMAC0_LINKTIMERVAL_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(EMAC0_LINKTIMERVAL)(8 downto 0); + signal EMAC0_BYTEPHY_BINARY : std_ulogic; + signal EMAC0_USECLKEN_BINARY : std_ulogic; + signal EMAC0_DCRBASEADDR_BINARY : std_logic_vector(0 to 7) := To_StdLogicVector(EMAC0_DCRBASEADDR); + signal EMAC1_PAUSEADDR_BINARY : std_logic_vector(47 downto 0) := To_StdLogicVector(EMAC1_PAUSEADDR); + signal EMAC1_RXHALFDUPLEX_BINARY : std_ulogic; + signal EMAC1_RXVLAN_ENABLE_BINARY : std_ulogic; + signal EMAC1_RX_ENABLE_BINARY : std_ulogic; + signal EMAC1_RXINBANDFCS_ENABLE_BINARY : std_ulogic; + signal EMAC1_RXJUMBOFRAME_ENABLE_BINARY : std_ulogic; + signal EMAC1_RXRESET_BINARY : std_ulogic; + signal EMAC1_TXIFGADJUST_ENABLE_BINARY : std_ulogic; + signal EMAC1_TXHALFDUPLEX_BINARY : std_ulogic; + signal EMAC1_TXVLAN_ENABLE_BINARY : std_ulogic; + signal EMAC1_TX_ENABLE_BINARY : std_ulogic; + signal EMAC1_TXINBANDFCS_ENABLE_BINARY : std_ulogic; + signal EMAC1_TXJUMBOFRAME_ENABLE_BINARY : std_ulogic; + signal EMAC1_TXRESET_BINARY : std_ulogic; + signal EMAC1_TXFLOWCTRL_ENABLE_BINARY : std_ulogic; + signal EMAC1_RXFLOWCTRL_ENABLE_BINARY : std_ulogic; + signal EMAC1_LTCHECK_DISABLE_BINARY : std_ulogic; + signal EMAC1_ADDRFILTER_ENABLE_BINARY : std_ulogic; + signal EMAC1_RX16BITCLIENT_ENABLE_BINARY : std_ulogic; + signal EMAC1_TX16BITCLIENT_ENABLE_BINARY : std_ulogic; + signal EMAC1_HOST_ENABLE_BINARY : std_ulogic; + signal EMAC1_1000BASEX_ENABLE_BINARY : std_ulogic; + signal EMAC1_SGMII_ENABLE_BINARY : std_ulogic; + signal EMAC1_RGMII_ENABLE_BINARY : std_ulogic; + signal EMAC1_SPEED_LSB_BINARY : std_ulogic; + signal EMAC1_SPEED_MSB_BINARY : std_ulogic; + signal EMAC1_MDIO_ENABLE_BINARY : std_ulogic; + signal EMAC1_PHYLOOPBACKMSB_BINARY : std_ulogic; + signal EMAC1_PHYPOWERDOWN_BINARY : std_ulogic; + signal EMAC1_PHYISOLATE_BINARY : std_ulogic; + signal EMAC1_PHYINITAUTONEG_ENABLE_BINARY : std_ulogic; + signal EMAC1_PHYRESET_BINARY : std_ulogic; + signal EMAC1_CONFIGVEC_79_BINARY : std_ulogic; + signal EMAC1_UNIDIRECTION_ENABLE_BINARY : std_ulogic; + signal EMAC1_GTLOOPBACK_BINARY : std_ulogic; + signal EMAC1_UNICASTADDR_BINARY : std_logic_vector(47 downto 0) := To_StdLogicVector(EMAC1_UNICASTADDR); + signal EMAC1_LINKTIMERVAL_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(EMAC1_LINKTIMERVAL)(8 downto 0); + signal EMAC1_BYTEPHY_BINARY : std_ulogic; + signal EMAC1_USECLKEN_BINARY : std_ulogic; + signal EMAC1_DCRBASEADDR_BINARY : std_logic_vector(0 to 7) := To_StdLogicVector(EMAC1_DCRBASEADDR); + + signal DCRHOSTDONEIR_out : std_ulogic; + signal EMAC0CLIENTANINTERRUPT_out : std_ulogic; + signal EMAC0CLIENTRXBADFRAME_out : std_ulogic; + signal EMAC0CLIENTRXCLIENTCLKOUT_out : std_ulogic; + signal EMAC0CLIENTRXD_out : std_logic_vector(15 downto 0); + signal EMAC0CLIENTRXDVLD_out : std_ulogic; + signal EMAC0CLIENTRXDVLDMSW_out : std_ulogic; + signal EMAC0CLIENTRXFRAMEDROP_out : std_ulogic; + signal EMAC0CLIENTRXGOODFRAME_out : std_ulogic; + signal EMAC0CLIENTRXSTATS_out : std_logic_vector(6 downto 0); + signal EMAC0CLIENTRXSTATSBYTEVLD_out : std_ulogic; + signal EMAC0CLIENTRXSTATSVLD_out : std_ulogic; + signal EMAC0CLIENTTXACK_out : std_ulogic; + signal EMAC0CLIENTTXCLIENTCLKOUT_out : std_ulogic; + signal EMAC0CLIENTTXCOLLISION_out : std_ulogic; + signal EMAC0PHYTXGMIIMIICLKOUT_out : std_ulogic; + signal EMAC0CLIENTTXRETRANSMIT_out : std_ulogic; + signal EMAC0CLIENTTXSTATS_out : std_ulogic; + signal EMAC0CLIENTTXSTATSBYTEVLD_out : std_ulogic; + signal EMAC0CLIENTTXSTATSVLD_out : std_ulogic; + signal EMAC0PHYENCOMMAALIGN_out : std_ulogic; + signal EMAC0PHYLOOPBACKMSB_out : std_ulogic; + signal EMAC0PHYMCLKOUT_out : std_ulogic; + signal EMAC0PHYMDOUT_out : std_ulogic; + signal EMAC0PHYMDTRI_out : std_ulogic; + signal EMAC0PHYMGTRXRESET_out : std_ulogic; + signal EMAC0PHYMGTTXRESET_out : std_ulogic; + signal EMAC0PHYPOWERDOWN_out : std_ulogic; + signal EMAC0PHYSYNCACQSTATUS_out : std_ulogic; + signal EMAC0PHYTXCHARDISPMODE_out : std_ulogic; + signal EMAC0PHYTXCHARDISPVAL_out : std_ulogic; + signal EMAC0PHYTXCHARISK_out : std_ulogic; + signal EMAC0PHYTXCLK_out : std_ulogic; + signal EMAC0PHYTXD_out : std_logic_vector(7 downto 0); + signal EMAC0PHYTXEN_out : std_ulogic; + signal EMAC0PHYTXER_out : std_ulogic; + signal EMAC0SPEEDIS10100_out : std_ulogic; + signal EMAC1CLIENTANINTERRUPT_out : std_ulogic; + signal EMAC1CLIENTRXBADFRAME_out : std_ulogic; + signal EMAC1CLIENTRXCLIENTCLKOUT_out : std_ulogic; + signal EMAC1CLIENTRXD_out : std_logic_vector(15 downto 0); + signal EMAC1CLIENTRXDVLD_out : std_ulogic; + signal EMAC1CLIENTRXDVLDMSW_out : std_ulogic; + signal EMAC1CLIENTRXFRAMEDROP_out : std_ulogic; + signal EMAC1CLIENTRXGOODFRAME_out : std_ulogic; + signal EMAC1CLIENTRXSTATS_out : std_logic_vector(6 downto 0); + signal EMAC1CLIENTRXSTATSBYTEVLD_out : std_ulogic; + signal EMAC1CLIENTRXSTATSVLD_out : std_ulogic; + signal EMAC1CLIENTTXACK_out : std_ulogic; + signal EMAC1CLIENTTXCLIENTCLKOUT_out : std_ulogic; + signal EMAC1CLIENTTXCOLLISION_out : std_ulogic; + signal EMAC1PHYTXGMIIMIICLKOUT_out : std_ulogic; + signal EMAC1CLIENTTXRETRANSMIT_out : std_ulogic; + signal EMAC1CLIENTTXSTATS_out : std_ulogic; + signal EMAC1CLIENTTXSTATSBYTEVLD_out : std_ulogic; + signal EMAC1CLIENTTXSTATSVLD_out : std_ulogic; + signal EMAC1PHYENCOMMAALIGN_out : std_ulogic; + signal EMAC1PHYLOOPBACKMSB_out : std_ulogic; + signal EMAC1PHYMCLKOUT_out : std_ulogic; + signal EMAC1PHYMDOUT_out : std_ulogic; + signal EMAC1PHYMDTRI_out : std_ulogic; + signal EMAC1PHYMGTRXRESET_out : std_ulogic; + signal EMAC1PHYMGTTXRESET_out : std_ulogic; + signal EMAC1PHYPOWERDOWN_out : std_ulogic; + signal EMAC1PHYSYNCACQSTATUS_out : std_ulogic; + signal EMAC1PHYTXCHARDISPMODE_out : std_ulogic; + signal EMAC1PHYTXCHARDISPVAL_out : std_ulogic; + signal EMAC1PHYTXCHARISK_out : std_ulogic; + signal EMAC1PHYTXCLK_out : std_ulogic; + signal EMAC1PHYTXD_out : std_logic_vector(7 downto 0); + signal EMAC1PHYTXEN_out : std_ulogic; + signal EMAC1PHYTXER_out : std_ulogic; + signal EMAC1SPEEDIS10100_out : std_ulogic; + signal EMACDCRACK_out : std_ulogic; + signal EMACDCRDBUS_out : std_logic_vector(0 to 31); + signal HOSTMIIMRDY_out : std_ulogic; + signal HOSTRDDATA_out : std_logic_vector(31 downto 0); + + signal EMAC0CLIENTRXCLIENTCLKOUT_outdelay : std_ulogic; + signal EMAC0CLIENTTXCLIENTCLKOUT_outdelay : std_ulogic; + signal EMAC0PHYTXGMIIMIICLKOUT_outdelay : std_ulogic; + signal EMAC0PHYMCLKOUT_outdelay : std_ulogic; + signal EMAC0PHYTXCLK_outdelay : std_ulogic; + signal EMAC1CLIENTRXCLIENTCLKOUT_outdelay : std_ulogic; + signal EMAC1CLIENTTXCLIENTCLKOUT_outdelay : std_ulogic; + signal EMAC1PHYTXGMIIMIICLKOUT_outdelay : std_ulogic; + signal EMAC1PHYMCLKOUT_outdelay : std_ulogic; + signal EMAC1PHYTXCLK_outdelay : std_ulogic; + + signal DCRHOSTDONEIR_outdelay : std_ulogic; + signal EMAC0CLIENTANINTERRUPT_outdelay : std_ulogic; + signal EMAC0CLIENTRXBADFRAME_outdelay : std_ulogic; + signal EMAC0CLIENTRXD_outdelay : std_logic_vector(15 downto 0); + signal EMAC0CLIENTRXDVLD_outdelay : std_ulogic; + signal EMAC0CLIENTRXDVLDMSW_outdelay : std_ulogic; + signal EMAC0CLIENTRXFRAMEDROP_outdelay : std_ulogic; + signal EMAC0CLIENTRXGOODFRAME_outdelay : std_ulogic; + signal EMAC0CLIENTRXSTATS_outdelay : std_logic_vector(6 downto 0); + signal EMAC0CLIENTRXSTATSBYTEVLD_outdelay : std_ulogic; + signal EMAC0CLIENTRXSTATSVLD_outdelay : std_ulogic; + signal EMAC0CLIENTTXACK_outdelay : std_ulogic; + signal EMAC0CLIENTTXCOLLISION_outdelay : std_ulogic; + signal EMAC0CLIENTTXRETRANSMIT_outdelay : std_ulogic; + signal EMAC0CLIENTTXSTATS_outdelay : std_ulogic; + signal EMAC0CLIENTTXSTATSBYTEVLD_outdelay : std_ulogic; + signal EMAC0CLIENTTXSTATSVLD_outdelay : std_ulogic; + signal EMAC0PHYENCOMMAALIGN_outdelay : std_ulogic; + signal EMAC0PHYLOOPBACKMSB_outdelay : std_ulogic; + signal EMAC0PHYMDOUT_outdelay : std_ulogic; + signal EMAC0PHYMDTRI_outdelay : std_ulogic; + signal EMAC0PHYMGTRXRESET_outdelay : std_ulogic; + signal EMAC0PHYMGTTXRESET_outdelay : std_ulogic; + signal EMAC0PHYPOWERDOWN_outdelay : std_ulogic; + signal EMAC0PHYSYNCACQSTATUS_outdelay : std_ulogic; + signal EMAC0PHYTXCHARDISPMODE_outdelay : std_ulogic; + signal EMAC0PHYTXCHARDISPVAL_outdelay : std_ulogic; + signal EMAC0PHYTXCHARISK_outdelay : std_ulogic; + signal EMAC0PHYTXD_outdelay : std_logic_vector(7 downto 0); + signal EMAC0PHYTXEN_outdelay : std_ulogic; + signal EMAC0PHYTXER_outdelay : std_ulogic; + signal EMAC0SPEEDIS10100_outdelay : std_ulogic; + signal EMAC1CLIENTANINTERRUPT_outdelay : std_ulogic; + signal EMAC1CLIENTRXBADFRAME_outdelay : std_ulogic; + signal EMAC1CLIENTRXD_outdelay : std_logic_vector(15 downto 0); + signal EMAC1CLIENTRXDVLD_outdelay : std_ulogic; + signal EMAC1CLIENTRXDVLDMSW_outdelay : std_ulogic; + signal EMAC1CLIENTRXFRAMEDROP_outdelay : std_ulogic; + signal EMAC1CLIENTRXGOODFRAME_outdelay : std_ulogic; + signal EMAC1CLIENTRXSTATS_outdelay : std_logic_vector(6 downto 0); + signal EMAC1CLIENTRXSTATSBYTEVLD_outdelay : std_ulogic; + signal EMAC1CLIENTRXSTATSVLD_outdelay : std_ulogic; + signal EMAC1CLIENTTXACK_outdelay : std_ulogic; + signal EMAC1CLIENTTXCOLLISION_outdelay : std_ulogic; + signal EMAC1CLIENTTXRETRANSMIT_outdelay : std_ulogic; + signal EMAC1CLIENTTXSTATS_outdelay : std_ulogic; + signal EMAC1CLIENTTXSTATSBYTEVLD_outdelay : std_ulogic; + signal EMAC1CLIENTTXSTATSVLD_outdelay : std_ulogic; + signal EMAC1PHYENCOMMAALIGN_outdelay : std_ulogic; + signal EMAC1PHYLOOPBACKMSB_outdelay : std_ulogic; + signal EMAC1PHYMDOUT_outdelay : std_ulogic; + signal EMAC1PHYMDTRI_outdelay : std_ulogic; + signal EMAC1PHYMGTRXRESET_outdelay : std_ulogic; + signal EMAC1PHYMGTTXRESET_outdelay : std_ulogic; + signal EMAC1PHYPOWERDOWN_outdelay : std_ulogic; + signal EMAC1PHYSYNCACQSTATUS_outdelay : std_ulogic; + signal EMAC1PHYTXCHARDISPMODE_outdelay : std_ulogic; + signal EMAC1PHYTXCHARDISPVAL_outdelay : std_ulogic; + signal EMAC1PHYTXCHARISK_outdelay : std_ulogic; + signal EMAC1PHYTXD_outdelay : std_logic_vector(7 downto 0); + signal EMAC1PHYTXEN_outdelay : std_ulogic; + signal EMAC1PHYTXER_outdelay : std_ulogic; + signal EMAC1SPEEDIS10100_outdelay : std_ulogic; + signal EMACDCRACK_outdelay : std_ulogic; + signal EMACDCRDBUS_outdelay : std_logic_vector(0 to 31); + signal HOSTMIIMRDY_outdelay : std_ulogic; + signal HOSTRDDATA_outdelay : std_logic_vector(31 downto 0); + + signal CLIENTEMAC0DCMLOCKED_ipd : std_ulogic; + signal CLIENTEMAC0PAUSEREQ_ipd : std_ulogic; + signal CLIENTEMAC0PAUSEVAL_ipd : std_logic_vector(15 downto 0); + signal CLIENTEMAC0RXCLIENTCLKIN_ipd : std_ulogic; + signal CLIENTEMAC0TXCLIENTCLKIN_ipd : std_ulogic; + signal CLIENTEMAC0TXD_ipd : std_logic_vector(15 downto 0); + signal CLIENTEMAC0TXDVLD_ipd : std_ulogic; + signal CLIENTEMAC0TXDVLDMSW_ipd : std_ulogic; + signal CLIENTEMAC0TXFIRSTBYTE_ipd : std_ulogic; + signal PHYEMAC0TXGMIIMIICLKIN_ipd : std_ulogic; + signal CLIENTEMAC0TXIFGDELAY_ipd : std_logic_vector(7 downto 0); + signal CLIENTEMAC0TXUNDERRUN_ipd : std_ulogic; + signal CLIENTEMAC1DCMLOCKED_ipd : std_ulogic; + signal CLIENTEMAC1PAUSEREQ_ipd : std_ulogic; + signal CLIENTEMAC1PAUSEVAL_ipd : std_logic_vector(15 downto 0); + signal CLIENTEMAC1RXCLIENTCLKIN_ipd : std_ulogic; + signal CLIENTEMAC1TXCLIENTCLKIN_ipd : std_ulogic; + signal CLIENTEMAC1TXD_ipd : std_logic_vector(15 downto 0); + signal CLIENTEMAC1TXDVLD_ipd : std_ulogic; + signal CLIENTEMAC1TXDVLDMSW_ipd : std_ulogic; + signal CLIENTEMAC1TXFIRSTBYTE_ipd : std_ulogic; + signal PHYEMAC1TXGMIIMIICLKIN_ipd : std_ulogic; + signal CLIENTEMAC1TXIFGDELAY_ipd : std_logic_vector(7 downto 0); + signal CLIENTEMAC1TXUNDERRUN_ipd : std_ulogic; + signal DCREMACABUS_ipd : std_logic_vector(0 to 9); + signal DCREMACCLK_ipd : std_ulogic; + signal DCREMACDBUS_ipd : std_logic_vector(0 to 31); + signal DCREMACENABLE_ipd : std_ulogic; + signal DCREMACREAD_ipd : std_ulogic; + signal DCREMACWRITE_ipd : std_ulogic; + signal HOSTADDR_ipd : std_logic_vector(9 downto 0); + signal HOSTCLK_ipd : std_ulogic; + signal HOSTEMAC1SEL_ipd : std_ulogic; + signal HOSTMIIMSEL_ipd : std_ulogic; + signal HOSTOPCODE_ipd : std_logic_vector(1 downto 0); + signal HOSTREQ_ipd : std_ulogic; + signal HOSTWRDATA_ipd : std_logic_vector(31 downto 0); + signal PHYEMAC0COL_ipd : std_ulogic; + signal PHYEMAC0CRS_ipd : std_ulogic; + signal PHYEMAC0GTXCLK_ipd : std_ulogic; + signal PHYEMAC0MCLKIN_ipd : std_ulogic; + signal PHYEMAC0MDIN_ipd : std_ulogic; + signal PHYEMAC0MIITXCLK_ipd : std_ulogic; + signal PHYEMAC0PHYAD_ipd : std_logic_vector(4 downto 0); + signal PHYEMAC0RXBUFERR_ipd : std_ulogic; + signal PHYEMAC0RXBUFSTATUS_ipd : std_logic_vector(1 downto 0); + signal PHYEMAC0RXCHARISCOMMA_ipd : std_ulogic; + signal PHYEMAC0RXCHARISK_ipd : std_ulogic; + signal PHYEMAC0RXCHECKINGCRC_ipd : std_ulogic; + signal PHYEMAC0RXCLK_ipd : std_ulogic; + signal PHYEMAC0RXCLKCORCNT_ipd : std_logic_vector(2 downto 0); + signal PHYEMAC0RXCOMMADET_ipd : std_ulogic; + signal PHYEMAC0RXD_ipd : std_logic_vector(7 downto 0); + signal PHYEMAC0RXDISPERR_ipd : std_ulogic; + signal PHYEMAC0RXDV_ipd : std_ulogic; + signal PHYEMAC0RXER_ipd : std_ulogic; + signal PHYEMAC0RXLOSSOFSYNC_ipd : std_logic_vector(1 downto 0); + signal PHYEMAC0RXNOTINTABLE_ipd : std_ulogic; + signal PHYEMAC0RXRUNDISP_ipd : std_ulogic; + signal PHYEMAC0SIGNALDET_ipd : std_ulogic; + signal PHYEMAC0TXBUFERR_ipd : std_ulogic; + signal PHYEMAC1COL_ipd : std_ulogic; + signal PHYEMAC1CRS_ipd : std_ulogic; + signal PHYEMAC1GTXCLK_ipd : std_ulogic; + signal PHYEMAC1MCLKIN_ipd : std_ulogic; + signal PHYEMAC1MDIN_ipd : std_ulogic; + signal PHYEMAC1MIITXCLK_ipd : std_ulogic; + signal PHYEMAC1PHYAD_ipd : std_logic_vector(4 downto 0); + signal PHYEMAC1RXBUFERR_ipd : std_ulogic; + signal PHYEMAC1RXBUFSTATUS_ipd : std_logic_vector(1 downto 0); + signal PHYEMAC1RXCHARISCOMMA_ipd : std_ulogic; + signal PHYEMAC1RXCHARISK_ipd : std_ulogic; + signal PHYEMAC1RXCHECKINGCRC_ipd : std_ulogic; + signal PHYEMAC1RXCLK_ipd : std_ulogic; + signal PHYEMAC1RXCLKCORCNT_ipd : std_logic_vector(2 downto 0); + signal PHYEMAC1RXCOMMADET_ipd : std_ulogic; + signal PHYEMAC1RXD_ipd : std_logic_vector(7 downto 0); + signal PHYEMAC1RXDISPERR_ipd : std_ulogic; + signal PHYEMAC1RXDV_ipd : std_ulogic; + signal PHYEMAC1RXER_ipd : std_ulogic; + signal PHYEMAC1RXLOSSOFSYNC_ipd : std_logic_vector(1 downto 0); + signal PHYEMAC1RXNOTINTABLE_ipd : std_ulogic; + signal PHYEMAC1RXRUNDISP_ipd : std_ulogic; + signal PHYEMAC1SIGNALDET_ipd : std_ulogic; + signal PHYEMAC1TXBUFERR_ipd : std_ulogic; + signal RESET_ipd : std_ulogic; + + signal CLIENTEMAC0DCMLOCKED_indelay : std_ulogic; + signal CLIENTEMAC0PAUSEREQ_indelay : std_ulogic; + signal CLIENTEMAC0PAUSEVAL_indelay : std_logic_vector(15 downto 0); + signal CLIENTEMAC0RXCLIENTCLKIN_indelay : std_ulogic; + signal CLIENTEMAC0TXCLIENTCLKIN_indelay : std_ulogic; + signal CLIENTEMAC0TXD_indelay : std_logic_vector(15 downto 0); + signal CLIENTEMAC0TXDVLD_indelay : std_ulogic; + signal CLIENTEMAC0TXDVLDMSW_indelay : std_ulogic; + signal CLIENTEMAC0TXFIRSTBYTE_indelay : std_ulogic; + signal PHYEMAC0TXGMIIMIICLKIN_indelay : std_ulogic; + signal CLIENTEMAC0TXIFGDELAY_indelay : std_logic_vector(7 downto 0); + signal CLIENTEMAC0TXUNDERRUN_indelay : std_ulogic; + signal CLIENTEMAC1DCMLOCKED_indelay : std_ulogic; + signal CLIENTEMAC1PAUSEREQ_indelay : std_ulogic; + signal CLIENTEMAC1PAUSEVAL_indelay : std_logic_vector(15 downto 0); + signal CLIENTEMAC1RXCLIENTCLKIN_indelay : std_ulogic; + signal CLIENTEMAC1TXCLIENTCLKIN_indelay : std_ulogic; + signal CLIENTEMAC1TXD_indelay : std_logic_vector(15 downto 0); + signal CLIENTEMAC1TXDVLD_indelay : std_ulogic; + signal CLIENTEMAC1TXDVLDMSW_indelay : std_ulogic; + signal CLIENTEMAC1TXFIRSTBYTE_indelay : std_ulogic; + signal PHYEMAC1TXGMIIMIICLKIN_indelay : std_ulogic; + signal CLIENTEMAC1TXIFGDELAY_indelay : std_logic_vector(7 downto 0); + signal CLIENTEMAC1TXUNDERRUN_indelay : std_ulogic; + signal DCREMACABUS_indelay : std_logic_vector(0 to 9); + signal DCREMACCLK_indelay : std_ulogic; + signal DCREMACDBUS_indelay : std_logic_vector(0 to 31); + signal DCREMACENABLE_indelay : std_ulogic; + signal DCREMACREAD_indelay : std_ulogic; + signal DCREMACWRITE_indelay : std_ulogic; + signal HOSTADDR_indelay : std_logic_vector(9 downto 0); + signal HOSTCLK_indelay : std_ulogic; + signal HOSTEMAC1SEL_indelay : std_ulogic; + signal HOSTMIIMSEL_indelay : std_ulogic; + signal HOSTOPCODE_indelay : std_logic_vector(1 downto 0); + signal HOSTREQ_indelay : std_ulogic; + signal HOSTWRDATA_indelay : std_logic_vector(31 downto 0); + signal PHYEMAC0COL_indelay : std_ulogic; + signal PHYEMAC0CRS_indelay : std_ulogic; + signal PHYEMAC0GTXCLK_indelay : std_ulogic; + signal PHYEMAC0MCLKIN_indelay : std_ulogic; + signal PHYEMAC0MDIN_indelay : std_ulogic; + signal PHYEMAC0MIITXCLK_indelay : std_ulogic; + signal PHYEMAC0PHYAD_indelay : std_logic_vector(4 downto 0); + signal PHYEMAC0RXBUFERR_indelay : std_ulogic; + signal PHYEMAC0RXBUFSTATUS_indelay : std_logic_vector(1 downto 0); + signal PHYEMAC0RXCHARISCOMMA_indelay : std_ulogic; + signal PHYEMAC0RXCHARISK_indelay : std_ulogic; + signal PHYEMAC0RXCHECKINGCRC_indelay : std_ulogic; + signal PHYEMAC0RXCLK_indelay : std_ulogic; + signal PHYEMAC0RXCLKCORCNT_indelay : std_logic_vector(2 downto 0); + signal PHYEMAC0RXCOMMADET_indelay : std_ulogic; + signal PHYEMAC0RXD_indelay : std_logic_vector(7 downto 0); + signal PHYEMAC0RXDISPERR_indelay : std_ulogic; + signal PHYEMAC0RXDV_indelay : std_ulogic; + signal PHYEMAC0RXER_indelay : std_ulogic; + signal PHYEMAC0RXLOSSOFSYNC_indelay : std_logic_vector(1 downto 0); + signal PHYEMAC0RXNOTINTABLE_indelay : std_ulogic; + signal PHYEMAC0RXRUNDISP_indelay : std_ulogic; + signal PHYEMAC0SIGNALDET_indelay : std_ulogic; + signal PHYEMAC0TXBUFERR_indelay : std_ulogic; + signal PHYEMAC1COL_indelay : std_ulogic; + signal PHYEMAC1CRS_indelay : std_ulogic; + signal PHYEMAC1GTXCLK_indelay : std_ulogic; + signal PHYEMAC1MCLKIN_indelay : std_ulogic; + signal PHYEMAC1MDIN_indelay : std_ulogic; + signal PHYEMAC1MIITXCLK_indelay : std_ulogic; + signal PHYEMAC1PHYAD_indelay : std_logic_vector(4 downto 0); + signal PHYEMAC1RXBUFERR_indelay : std_ulogic; + signal PHYEMAC1RXBUFSTATUS_indelay : std_logic_vector(1 downto 0); + signal PHYEMAC1RXCHARISCOMMA_indelay : std_ulogic; + signal PHYEMAC1RXCHARISK_indelay : std_ulogic; + signal PHYEMAC1RXCHECKINGCRC_indelay : std_ulogic; + signal PHYEMAC1RXCLK_indelay : std_ulogic; + signal PHYEMAC1RXCLKCORCNT_indelay : std_logic_vector(2 downto 0); + signal PHYEMAC1RXCOMMADET_indelay : std_ulogic; + signal PHYEMAC1RXD_indelay : std_logic_vector(7 downto 0); + signal PHYEMAC1RXDISPERR_indelay : std_ulogic; + signal PHYEMAC1RXDV_indelay : std_ulogic; + signal PHYEMAC1RXER_indelay : std_ulogic; + signal PHYEMAC1RXLOSSOFSYNC_indelay : std_logic_vector(1 downto 0); + signal PHYEMAC1RXNOTINTABLE_indelay : std_ulogic; + signal PHYEMAC1RXRUNDISP_indelay : std_ulogic; + signal PHYEMAC1SIGNALDET_indelay : std_ulogic; + signal PHYEMAC1TXBUFERR_indelay : std_ulogic; + signal RESET_indelay : std_ulogic; + + begin + + EMAC0CLIENTRXCLIENTCLKOUT_out <= EMAC0CLIENTRXCLIENTCLKOUT_outdelay after CLK_DELAY; + EMAC0CLIENTTXCLIENTCLKOUT_out <= EMAC0CLIENTTXCLIENTCLKOUT_outdelay after CLK_DELAY; + EMAC0PHYMCLKOUT_out <= EMAC0PHYMCLKOUT_outdelay after CLK_DELAY; + EMAC0PHYTXCLK_out <= EMAC0PHYTXCLK_outdelay after CLK_DELAY; + EMAC0PHYTXGMIIMIICLKOUT_out <= EMAC0PHYTXGMIIMIICLKOUT_outdelay after CLK_DELAY; + EMAC1CLIENTRXCLIENTCLKOUT_out <= EMAC1CLIENTRXCLIENTCLKOUT_outdelay after CLK_DELAY; + EMAC1CLIENTTXCLIENTCLKOUT_out <= EMAC1CLIENTTXCLIENTCLKOUT_outdelay after CLK_DELAY; + EMAC1PHYMCLKOUT_out <= EMAC1PHYMCLKOUT_outdelay after CLK_DELAY; + EMAC1PHYTXCLK_out <= EMAC1PHYTXCLK_outdelay after CLK_DELAY; + EMAC1PHYTXGMIIMIICLKOUT_out <= EMAC1PHYTXGMIIMIICLKOUT_outdelay after CLK_DELAY; + + DCRHOSTDONEIR_out <= DCRHOSTDONEIR_outdelay after OUT_DELAY; + EMAC0CLIENTANINTERRUPT_out <= EMAC0CLIENTANINTERRUPT_outdelay after OUT_DELAY; + EMAC0CLIENTRXBADFRAME_out <= EMAC0CLIENTRXBADFRAME_outdelay after OUT_DELAY; + EMAC0CLIENTRXDVLDMSW_out <= EMAC0CLIENTRXDVLDMSW_outdelay after OUT_DELAY; + EMAC0CLIENTRXDVLD_out <= EMAC0CLIENTRXDVLD_outdelay after OUT_DELAY; + EMAC0CLIENTRXD_out <= EMAC0CLIENTRXD_outdelay after OUT_DELAY; + EMAC0CLIENTRXFRAMEDROP_out <= EMAC0CLIENTRXFRAMEDROP_outdelay after OUT_DELAY; + EMAC0CLIENTRXGOODFRAME_out <= EMAC0CLIENTRXGOODFRAME_outdelay after OUT_DELAY; + EMAC0CLIENTRXSTATSBYTEVLD_out <= EMAC0CLIENTRXSTATSBYTEVLD_outdelay after OUT_DELAY; + EMAC0CLIENTRXSTATSVLD_out <= EMAC0CLIENTRXSTATSVLD_outdelay after OUT_DELAY; + EMAC0CLIENTRXSTATS_out <= EMAC0CLIENTRXSTATS_outdelay after OUT_DELAY; + EMAC0CLIENTTXACK_out <= EMAC0CLIENTTXACK_outdelay after OUT_DELAY; + EMAC0CLIENTTXCOLLISION_out <= EMAC0CLIENTTXCOLLISION_outdelay after OUT_DELAY; + EMAC0CLIENTTXRETRANSMIT_out <= EMAC0CLIENTTXRETRANSMIT_outdelay after OUT_DELAY; + EMAC0CLIENTTXSTATSBYTEVLD_out <= EMAC0CLIENTTXSTATSBYTEVLD_outdelay after OUT_DELAY; + EMAC0CLIENTTXSTATSVLD_out <= EMAC0CLIENTTXSTATSVLD_outdelay after OUT_DELAY; + EMAC0CLIENTTXSTATS_out <= EMAC0CLIENTTXSTATS_outdelay after OUT_DELAY; + EMAC0PHYENCOMMAALIGN_out <= EMAC0PHYENCOMMAALIGN_outdelay after OUT_DELAY; + EMAC0PHYLOOPBACKMSB_out <= EMAC0PHYLOOPBACKMSB_outdelay after OUT_DELAY; + EMAC0PHYMDOUT_out <= EMAC0PHYMDOUT_outdelay after OUT_DELAY; + EMAC0PHYMDTRI_out <= EMAC0PHYMDTRI_outdelay after OUT_DELAY; + EMAC0PHYMGTRXRESET_out <= EMAC0PHYMGTRXRESET_outdelay after OUT_DELAY; + EMAC0PHYMGTTXRESET_out <= EMAC0PHYMGTTXRESET_outdelay after OUT_DELAY; + EMAC0PHYPOWERDOWN_out <= EMAC0PHYPOWERDOWN_outdelay after OUT_DELAY; + EMAC0PHYSYNCACQSTATUS_out <= EMAC0PHYSYNCACQSTATUS_outdelay after OUT_DELAY; + EMAC0PHYTXCHARDISPMODE_out <= EMAC0PHYTXCHARDISPMODE_outdelay after OUT_DELAY; + EMAC0PHYTXCHARDISPVAL_out <= EMAC0PHYTXCHARDISPVAL_outdelay after OUT_DELAY; + EMAC0PHYTXCHARISK_out <= EMAC0PHYTXCHARISK_outdelay after OUT_DELAY; + EMAC0PHYTXD_out <= EMAC0PHYTXD_outdelay after OUT_DELAY; + EMAC0PHYTXEN_out <= EMAC0PHYTXEN_outdelay after OUT_DELAY; + EMAC0PHYTXER_out <= EMAC0PHYTXER_outdelay after OUT_DELAY; + EMAC0SPEEDIS10100_out <= EMAC0SPEEDIS10100_outdelay after OUT_DELAY; + EMAC1CLIENTANINTERRUPT_out <= EMAC1CLIENTANINTERRUPT_outdelay after OUT_DELAY; + EMAC1CLIENTRXBADFRAME_out <= EMAC1CLIENTRXBADFRAME_outdelay after OUT_DELAY; + EMAC1CLIENTRXDVLDMSW_out <= EMAC1CLIENTRXDVLDMSW_outdelay after OUT_DELAY; + EMAC1CLIENTRXDVLD_out <= EMAC1CLIENTRXDVLD_outdelay after OUT_DELAY; + EMAC1CLIENTRXD_out <= EMAC1CLIENTRXD_outdelay after OUT_DELAY; + EMAC1CLIENTRXFRAMEDROP_out <= EMAC1CLIENTRXFRAMEDROP_outdelay after OUT_DELAY; + EMAC1CLIENTRXGOODFRAME_out <= EMAC1CLIENTRXGOODFRAME_outdelay after OUT_DELAY; + EMAC1CLIENTRXSTATSBYTEVLD_out <= EMAC1CLIENTRXSTATSBYTEVLD_outdelay after OUT_DELAY; + EMAC1CLIENTRXSTATSVLD_out <= EMAC1CLIENTRXSTATSVLD_outdelay after OUT_DELAY; + EMAC1CLIENTRXSTATS_out <= EMAC1CLIENTRXSTATS_outdelay after OUT_DELAY; + EMAC1CLIENTTXACK_out <= EMAC1CLIENTTXACK_outdelay after OUT_DELAY; + EMAC1CLIENTTXCOLLISION_out <= EMAC1CLIENTTXCOLLISION_outdelay after OUT_DELAY; + EMAC1CLIENTTXRETRANSMIT_out <= EMAC1CLIENTTXRETRANSMIT_outdelay after OUT_DELAY; + EMAC1CLIENTTXSTATSBYTEVLD_out <= EMAC1CLIENTTXSTATSBYTEVLD_outdelay after OUT_DELAY; + EMAC1CLIENTTXSTATSVLD_out <= EMAC1CLIENTTXSTATSVLD_outdelay after OUT_DELAY; + EMAC1CLIENTTXSTATS_out <= EMAC1CLIENTTXSTATS_outdelay after OUT_DELAY; + EMAC1PHYENCOMMAALIGN_out <= EMAC1PHYENCOMMAALIGN_outdelay after OUT_DELAY; + EMAC1PHYLOOPBACKMSB_out <= EMAC1PHYLOOPBACKMSB_outdelay after OUT_DELAY; + EMAC1PHYMDOUT_out <= EMAC1PHYMDOUT_outdelay after OUT_DELAY; + EMAC1PHYMDTRI_out <= EMAC1PHYMDTRI_outdelay after OUT_DELAY; + EMAC1PHYMGTRXRESET_out <= EMAC1PHYMGTRXRESET_outdelay after OUT_DELAY; + EMAC1PHYMGTTXRESET_out <= EMAC1PHYMGTTXRESET_outdelay after OUT_DELAY; + EMAC1PHYPOWERDOWN_out <= EMAC1PHYPOWERDOWN_outdelay after OUT_DELAY; + EMAC1PHYSYNCACQSTATUS_out <= EMAC1PHYSYNCACQSTATUS_outdelay after OUT_DELAY; + EMAC1PHYTXCHARDISPMODE_out <= EMAC1PHYTXCHARDISPMODE_outdelay after OUT_DELAY; + EMAC1PHYTXCHARDISPVAL_out <= EMAC1PHYTXCHARDISPVAL_outdelay after OUT_DELAY; + EMAC1PHYTXCHARISK_out <= EMAC1PHYTXCHARISK_outdelay after OUT_DELAY; + EMAC1PHYTXD_out <= EMAC1PHYTXD_outdelay after OUT_DELAY; + EMAC1PHYTXEN_out <= EMAC1PHYTXEN_outdelay after OUT_DELAY; + EMAC1PHYTXER_out <= EMAC1PHYTXER_outdelay after OUT_DELAY; + EMAC1SPEEDIS10100_out <= EMAC1SPEEDIS10100_outdelay after OUT_DELAY; + EMACDCRACK_out <= EMACDCRACK_outdelay after OUT_DELAY; + EMACDCRDBUS_out <= EMACDCRDBUS_outdelay after OUT_DELAY; + HOSTMIIMRDY_out <= HOSTMIIMRDY_outdelay after OUT_DELAY; + HOSTRDDATA_out <= HOSTRDDATA_outdelay after OUT_DELAY; + + CLIENTEMAC0RXCLIENTCLKIN_ipd <= CLIENTEMAC0RXCLIENTCLKIN after CLK_DELAY; + CLIENTEMAC0TXCLIENTCLKIN_ipd <= CLIENTEMAC0TXCLIENTCLKIN after CLK_DELAY; + CLIENTEMAC1RXCLIENTCLKIN_ipd <= CLIENTEMAC1RXCLIENTCLKIN after CLK_DELAY; + CLIENTEMAC1TXCLIENTCLKIN_ipd <= CLIENTEMAC1TXCLIENTCLKIN after CLK_DELAY; + DCREMACCLK_ipd <= DCREMACCLK after CLK_DELAY; + HOSTCLK_ipd <= HOSTCLK after CLK_DELAY; + PHYEMAC0GTXCLK_ipd <= PHYEMAC0GTXCLK after CLK_DELAY; + PHYEMAC0MCLKIN_ipd <= PHYEMAC0MCLKIN after CLK_DELAY; + PHYEMAC0MIITXCLK_ipd <= PHYEMAC0MIITXCLK after EMAC0MIITXCLK_DELAY; + PHYEMAC0RXCLK_ipd <= PHYEMAC0RXCLK after CLK_DELAY; + PHYEMAC0TXGMIIMIICLKIN_ipd <= PHYEMAC0TXGMIIMIICLKIN after CLK_DELAY; + PHYEMAC1GTXCLK_ipd <= PHYEMAC1GTXCLK after CLK_DELAY; + PHYEMAC1MCLKIN_ipd <= PHYEMAC1MCLKIN after CLK_DELAY; + PHYEMAC1MIITXCLK_ipd <= PHYEMAC1MIITXCLK after EMAC1MIITXCLK_DELAY; + PHYEMAC1RXCLK_ipd <= PHYEMAC1RXCLK after CLK_DELAY; + PHYEMAC1TXGMIIMIICLKIN_ipd <= PHYEMAC1TXGMIIMIICLKIN after CLK_DELAY; + + CLIENTEMAC0DCMLOCKED_ipd <= CLIENTEMAC0DCMLOCKED after CLK_DELAY; + CLIENTEMAC0PAUSEREQ_ipd <= CLIENTEMAC0PAUSEREQ after CLK_DELAY; + CLIENTEMAC0PAUSEVAL_ipd <= CLIENTEMAC0PAUSEVAL after CLK_DELAY; + CLIENTEMAC0TXDVLDMSW_ipd <= CLIENTEMAC0TXDVLDMSW after CLK_DELAY; + CLIENTEMAC0TXDVLD_ipd <= CLIENTEMAC0TXDVLD after CLK_DELAY; + CLIENTEMAC0TXD_ipd <= CLIENTEMAC0TXD after CLK_DELAY; + CLIENTEMAC0TXFIRSTBYTE_ipd <= CLIENTEMAC0TXFIRSTBYTE after CLK_DELAY; + CLIENTEMAC0TXIFGDELAY_ipd <= CLIENTEMAC0TXIFGDELAY after CLK_DELAY; + CLIENTEMAC0TXUNDERRUN_ipd <= CLIENTEMAC0TXUNDERRUN after CLK_DELAY; + CLIENTEMAC1DCMLOCKED_ipd <= CLIENTEMAC1DCMLOCKED after CLK_DELAY; + CLIENTEMAC1PAUSEREQ_ipd <= CLIENTEMAC1PAUSEREQ after CLK_DELAY; + CLIENTEMAC1PAUSEVAL_ipd <= CLIENTEMAC1PAUSEVAL after CLK_DELAY; + CLIENTEMAC1TXDVLDMSW_ipd <= CLIENTEMAC1TXDVLDMSW after CLK_DELAY; + CLIENTEMAC1TXDVLD_ipd <= CLIENTEMAC1TXDVLD after CLK_DELAY; + CLIENTEMAC1TXD_ipd <= CLIENTEMAC1TXD after CLK_DELAY; + CLIENTEMAC1TXFIRSTBYTE_ipd <= CLIENTEMAC1TXFIRSTBYTE after CLK_DELAY; + CLIENTEMAC1TXIFGDELAY_ipd <= CLIENTEMAC1TXIFGDELAY after CLK_DELAY; + CLIENTEMAC1TXUNDERRUN_ipd <= CLIENTEMAC1TXUNDERRUN after CLK_DELAY; + DCREMACABUS_ipd <= DCREMACABUS after CLK_DELAY; + DCREMACDBUS_ipd <= DCREMACDBUS after CLK_DELAY; + DCREMACENABLE_ipd <= DCREMACENABLE after CLK_DELAY; + DCREMACREAD_ipd <= DCREMACREAD after CLK_DELAY; + DCREMACWRITE_ipd <= DCREMACWRITE after CLK_DELAY; + HOSTADDR_ipd <= HOSTADDR after CLK_DELAY; + HOSTEMAC1SEL_ipd <= HOSTEMAC1SEL after CLK_DELAY; + HOSTMIIMSEL_ipd <= HOSTMIIMSEL after CLK_DELAY; + HOSTOPCODE_ipd <= HOSTOPCODE after CLK_DELAY; + HOSTREQ_ipd <= HOSTREQ after CLK_DELAY; + HOSTWRDATA_ipd <= HOSTWRDATA after CLK_DELAY; + PHYEMAC0COL_ipd <= PHYEMAC0COL after CLK_DELAY; + PHYEMAC0CRS_ipd <= PHYEMAC0CRS after CLK_DELAY; + PHYEMAC0MDIN_ipd <= PHYEMAC0MDIN after CLK_DELAY; + PHYEMAC0PHYAD_ipd <= PHYEMAC0PHYAD after CLK_DELAY; + PHYEMAC0RXBUFERR_ipd <= PHYEMAC0RXBUFERR after CLK_DELAY; + PHYEMAC0RXBUFSTATUS_ipd <= PHYEMAC0RXBUFSTATUS after CLK_DELAY; + PHYEMAC0RXCHARISCOMMA_ipd <= PHYEMAC0RXCHARISCOMMA after CLK_DELAY; + PHYEMAC0RXCHARISK_ipd <= PHYEMAC0RXCHARISK after CLK_DELAY; + PHYEMAC0RXCHECKINGCRC_ipd <= PHYEMAC0RXCHECKINGCRC after CLK_DELAY; + PHYEMAC0RXCLKCORCNT_ipd <= PHYEMAC0RXCLKCORCNT after CLK_DELAY; + PHYEMAC0RXCOMMADET_ipd <= PHYEMAC0RXCOMMADET after CLK_DELAY; + PHYEMAC0RXDISPERR_ipd <= PHYEMAC0RXDISPERR after CLK_DELAY; + PHYEMAC0RXDV_ipd <= PHYEMAC0RXDV after CLK_DELAY; + PHYEMAC0RXD_ipd <= PHYEMAC0RXD after CLK_DELAY; + PHYEMAC0RXER_ipd <= PHYEMAC0RXER after CLK_DELAY; + PHYEMAC0RXLOSSOFSYNC_ipd <= PHYEMAC0RXLOSSOFSYNC after CLK_DELAY; + PHYEMAC0RXNOTINTABLE_ipd <= PHYEMAC0RXNOTINTABLE after CLK_DELAY; + PHYEMAC0RXRUNDISP_ipd <= PHYEMAC0RXRUNDISP after CLK_DELAY; + PHYEMAC0SIGNALDET_ipd <= PHYEMAC0SIGNALDET after CLK_DELAY; + PHYEMAC0TXBUFERR_ipd <= PHYEMAC0TXBUFERR after CLK_DELAY; + PHYEMAC1COL_ipd <= PHYEMAC1COL after CLK_DELAY; + PHYEMAC1CRS_ipd <= PHYEMAC1CRS after CLK_DELAY; + PHYEMAC1MDIN_ipd <= PHYEMAC1MDIN after CLK_DELAY; + PHYEMAC1PHYAD_ipd <= PHYEMAC1PHYAD after CLK_DELAY; + PHYEMAC1RXBUFERR_ipd <= PHYEMAC1RXBUFERR after CLK_DELAY; + PHYEMAC1RXBUFSTATUS_ipd <= PHYEMAC1RXBUFSTATUS after CLK_DELAY; + PHYEMAC1RXCHARISCOMMA_ipd <= PHYEMAC1RXCHARISCOMMA after CLK_DELAY; + PHYEMAC1RXCHARISK_ipd <= PHYEMAC1RXCHARISK after CLK_DELAY; + PHYEMAC1RXCHECKINGCRC_ipd <= PHYEMAC1RXCHECKINGCRC after CLK_DELAY; + PHYEMAC1RXCLKCORCNT_ipd <= PHYEMAC1RXCLKCORCNT after CLK_DELAY; + PHYEMAC1RXCOMMADET_ipd <= PHYEMAC1RXCOMMADET after CLK_DELAY; + PHYEMAC1RXDISPERR_ipd <= PHYEMAC1RXDISPERR after CLK_DELAY; + PHYEMAC1RXDV_ipd <= PHYEMAC1RXDV after CLK_DELAY; + PHYEMAC1RXD_ipd <= PHYEMAC1RXD after CLK_DELAY; + PHYEMAC1RXER_ipd <= PHYEMAC1RXER after CLK_DELAY; + PHYEMAC1RXLOSSOFSYNC_ipd <= PHYEMAC1RXLOSSOFSYNC after CLK_DELAY; + PHYEMAC1RXNOTINTABLE_ipd <= PHYEMAC1RXNOTINTABLE after CLK_DELAY; + PHYEMAC1RXRUNDISP_ipd <= PHYEMAC1RXRUNDISP after CLK_DELAY; + PHYEMAC1SIGNALDET_ipd <= PHYEMAC1SIGNALDET after CLK_DELAY; + PHYEMAC1TXBUFERR_ipd <= PHYEMAC1TXBUFERR after CLK_DELAY; + RESET_ipd <= RESET after CLK_DELAY; + + CLIENTEMAC0RXCLIENTCLKIN_indelay <= CLIENTEMAC0RXCLIENTCLKIN_ipd after CLK_DELAY; + CLIENTEMAC0TXCLIENTCLKIN_indelay <= CLIENTEMAC0TXCLIENTCLKIN_ipd after CLK_DELAY; + CLIENTEMAC1RXCLIENTCLKIN_indelay <= CLIENTEMAC1RXCLIENTCLKIN_ipd after CLK_DELAY; + CLIENTEMAC1TXCLIENTCLKIN_indelay <= CLIENTEMAC1TXCLIENTCLKIN_ipd after CLK_DELAY; + DCREMACCLK_indelay <= DCREMACCLK_ipd after CLK_DELAY; + HOSTCLK_indelay <= HOSTCLK_ipd after CLK_DELAY; + PHYEMAC0GTXCLK_indelay <= PHYEMAC0GTXCLK_ipd after CLK_DELAY; + PHYEMAC0MCLKIN_indelay <= PHYEMAC0MCLKIN_ipd after CLK_DELAY; + PHYEMAC0MIITXCLK_indelay <= PHYEMAC0MIITXCLK_ipd after EMAC0MIITXCLK_DELAY; + PHYEMAC0RXCLK_indelay <= PHYEMAC0RXCLK_ipd after CLK_DELAY; + PHYEMAC0TXGMIIMIICLKIN_indelay <= PHYEMAC0TXGMIIMIICLKIN_ipd after CLK_DELAY; + PHYEMAC1GTXCLK_indelay <= PHYEMAC1GTXCLK_ipd after CLK_DELAY; + PHYEMAC1MCLKIN_indelay <= PHYEMAC1MCLKIN_ipd after CLK_DELAY; + PHYEMAC1MIITXCLK_indelay <= PHYEMAC1MIITXCLK_ipd after EMAC1MIITXCLK_DELAY; + PHYEMAC1RXCLK_indelay <= PHYEMAC1RXCLK_ipd after CLK_DELAY; + PHYEMAC1TXGMIIMIICLKIN_indelay <= PHYEMAC1TXGMIIMIICLKIN_ipd after CLK_DELAY; + + CLIENTEMAC0DCMLOCKED_indelay <= CLIENTEMAC0DCMLOCKED_ipd after IN_DELAY; + CLIENTEMAC0PAUSEREQ_indelay <= CLIENTEMAC0PAUSEREQ_ipd after IN_DELAY; + CLIENTEMAC0PAUSEVAL_indelay <= CLIENTEMAC0PAUSEVAL_ipd after IN_DELAY; + CLIENTEMAC0TXDVLDMSW_indelay <= CLIENTEMAC0TXDVLDMSW_ipd after IN_DELAY; + CLIENTEMAC0TXDVLD_indelay <= CLIENTEMAC0TXDVLD_ipd after IN_DELAY; + CLIENTEMAC0TXD_indelay <= CLIENTEMAC0TXD_ipd after IN_DELAY; + CLIENTEMAC0TXFIRSTBYTE_indelay <= CLIENTEMAC0TXFIRSTBYTE_ipd after IN_DELAY; + CLIENTEMAC0TXIFGDELAY_indelay <= CLIENTEMAC0TXIFGDELAY_ipd after IN_DELAY; + CLIENTEMAC0TXUNDERRUN_indelay <= CLIENTEMAC0TXUNDERRUN_ipd after IN_DELAY; + CLIENTEMAC1DCMLOCKED_indelay <= CLIENTEMAC1DCMLOCKED_ipd after IN_DELAY; + CLIENTEMAC1PAUSEREQ_indelay <= CLIENTEMAC1PAUSEREQ_ipd after IN_DELAY; + CLIENTEMAC1PAUSEVAL_indelay <= CLIENTEMAC1PAUSEVAL_ipd after IN_DELAY; + CLIENTEMAC1TXDVLDMSW_indelay <= CLIENTEMAC1TXDVLDMSW_ipd after IN_DELAY; + CLIENTEMAC1TXDVLD_indelay <= CLIENTEMAC1TXDVLD_ipd after IN_DELAY; + CLIENTEMAC1TXD_indelay <= CLIENTEMAC1TXD_ipd after IN_DELAY; + CLIENTEMAC1TXFIRSTBYTE_indelay <= CLIENTEMAC1TXFIRSTBYTE_ipd after IN_DELAY; + CLIENTEMAC1TXIFGDELAY_indelay <= CLIENTEMAC1TXIFGDELAY_ipd after IN_DELAY; + CLIENTEMAC1TXUNDERRUN_indelay <= CLIENTEMAC1TXUNDERRUN_ipd after IN_DELAY; + DCREMACABUS_indelay <= DCREMACABUS_ipd after IN_DELAY; + DCREMACDBUS_indelay <= DCREMACDBUS_ipd after IN_DELAY; + DCREMACENABLE_indelay <= DCREMACENABLE_ipd after IN_DELAY; + DCREMACREAD_indelay <= DCREMACREAD_ipd after IN_DELAY; + DCREMACWRITE_indelay <= DCREMACWRITE_ipd after IN_DELAY; + HOSTADDR_indelay <= HOSTADDR_ipd after IN_DELAY; + HOSTEMAC1SEL_indelay <= HOSTEMAC1SEL_ipd after IN_DELAY; + HOSTMIIMSEL_indelay <= HOSTMIIMSEL_ipd after IN_DELAY; + HOSTOPCODE_indelay <= HOSTOPCODE_ipd after IN_DELAY; + HOSTREQ_indelay <= HOSTREQ_ipd after IN_DELAY; + HOSTWRDATA_indelay <= HOSTWRDATA_ipd after IN_DELAY; + PHYEMAC0COL_indelay <= PHYEMAC0COL_ipd after IN_DELAY; + PHYEMAC0CRS_indelay <= PHYEMAC0CRS_ipd after IN_DELAY; + PHYEMAC0MDIN_indelay <= PHYEMAC0MDIN_ipd after IN_DELAY; + PHYEMAC0PHYAD_indelay <= PHYEMAC0PHYAD_ipd after IN_DELAY; + PHYEMAC0RXBUFERR_indelay <= PHYEMAC0RXBUFERR_ipd after IN_DELAY; + PHYEMAC0RXBUFSTATUS_indelay <= PHYEMAC0RXBUFSTATUS_ipd after IN_DELAY; + PHYEMAC0RXCHARISCOMMA_indelay <= PHYEMAC0RXCHARISCOMMA_ipd after IN_DELAY; + PHYEMAC0RXCHARISK_indelay <= PHYEMAC0RXCHARISK_ipd after IN_DELAY; + PHYEMAC0RXCHECKINGCRC_indelay <= PHYEMAC0RXCHECKINGCRC_ipd after IN_DELAY; + PHYEMAC0RXCLKCORCNT_indelay <= PHYEMAC0RXCLKCORCNT_ipd after IN_DELAY; + PHYEMAC0RXCOMMADET_indelay <= PHYEMAC0RXCOMMADET_ipd after IN_DELAY; + PHYEMAC0RXDISPERR_indelay <= PHYEMAC0RXDISPERR_ipd after IN_DELAY; + PHYEMAC0RXDV_indelay <= PHYEMAC0RXDV_ipd after IN_DELAY; + PHYEMAC0RXD_indelay <= PHYEMAC0RXD_ipd after IN_DELAY; + PHYEMAC0RXER_indelay <= PHYEMAC0RXER_ipd after IN_DELAY; + PHYEMAC0RXLOSSOFSYNC_indelay <= PHYEMAC0RXLOSSOFSYNC_ipd after IN_DELAY; + PHYEMAC0RXNOTINTABLE_indelay <= PHYEMAC0RXNOTINTABLE_ipd after IN_DELAY; + PHYEMAC0RXRUNDISP_indelay <= PHYEMAC0RXRUNDISP_ipd after IN_DELAY; + PHYEMAC0SIGNALDET_indelay <= PHYEMAC0SIGNALDET_ipd after IN_DELAY; + PHYEMAC0TXBUFERR_indelay <= PHYEMAC0TXBUFERR_ipd after IN_DELAY; + PHYEMAC1COL_indelay <= PHYEMAC1COL_ipd after IN_DELAY; + PHYEMAC1CRS_indelay <= PHYEMAC1CRS_ipd after IN_DELAY; + PHYEMAC1MDIN_indelay <= PHYEMAC1MDIN_ipd after IN_DELAY; + PHYEMAC1PHYAD_indelay <= PHYEMAC1PHYAD_ipd after IN_DELAY; + PHYEMAC1RXBUFERR_indelay <= PHYEMAC1RXBUFERR_ipd after IN_DELAY; + PHYEMAC1RXBUFSTATUS_indelay <= PHYEMAC1RXBUFSTATUS_ipd after IN_DELAY; + PHYEMAC1RXCHARISCOMMA_indelay <= PHYEMAC1RXCHARISCOMMA_ipd after IN_DELAY; + PHYEMAC1RXCHARISK_indelay <= PHYEMAC1RXCHARISK_ipd after IN_DELAY; + PHYEMAC1RXCHECKINGCRC_indelay <= PHYEMAC1RXCHECKINGCRC_ipd after IN_DELAY; + PHYEMAC1RXCLKCORCNT_indelay <= PHYEMAC1RXCLKCORCNT_ipd after IN_DELAY; + PHYEMAC1RXCOMMADET_indelay <= PHYEMAC1RXCOMMADET_ipd after IN_DELAY; + PHYEMAC1RXDISPERR_indelay <= PHYEMAC1RXDISPERR_ipd after IN_DELAY; + PHYEMAC1RXDV_indelay <= PHYEMAC1RXDV_ipd after IN_DELAY; + PHYEMAC1RXD_indelay <= PHYEMAC1RXD_ipd after IN_DELAY; + PHYEMAC1RXER_indelay <= PHYEMAC1RXER_ipd after IN_DELAY; + PHYEMAC1RXLOSSOFSYNC_indelay <= PHYEMAC1RXLOSSOFSYNC_ipd after IN_DELAY; + PHYEMAC1RXNOTINTABLE_indelay <= PHYEMAC1RXNOTINTABLE_ipd after IN_DELAY; + PHYEMAC1RXRUNDISP_indelay <= PHYEMAC1RXRUNDISP_ipd after IN_DELAY; + PHYEMAC1SIGNALDET_indelay <= PHYEMAC1SIGNALDET_ipd after IN_DELAY; + PHYEMAC1TXBUFERR_indelay <= PHYEMAC1TXBUFERR_ipd after IN_DELAY; + RESET_indelay <= RESET_ipd after IN_DELAY; + + temac_swift_bw_1 : TEMAC_SWIFT + port map ( + EMAC0_1000BASEX_ENABLE => EMAC0_1000BASEX_ENABLE_BINARY, + EMAC0_ADDRFILTER_ENABLE => EMAC0_ADDRFILTER_ENABLE_BINARY, + EMAC0_BYTEPHY => EMAC0_BYTEPHY_BINARY, + EMAC0_CONFIGVEC_79 => EMAC0_CONFIGVEC_79_BINARY, + EMAC0_DCRBASEADDR => EMAC0_DCRBASEADDR_BINARY, + EMAC0_GTLOOPBACK => EMAC0_GTLOOPBACK_BINARY, + EMAC0_HOST_ENABLE => EMAC0_HOST_ENABLE_BINARY, + EMAC0_LINKTIMERVAL => EMAC0_LINKTIMERVAL_BINARY, + EMAC0_LTCHECK_DISABLE => EMAC0_LTCHECK_DISABLE_BINARY, + EMAC0_MDIO_ENABLE => EMAC0_MDIO_ENABLE_BINARY, + EMAC0_PAUSEADDR => EMAC0_PAUSEADDR_BINARY, + EMAC0_PHYINITAUTONEG_ENABLE => EMAC0_PHYINITAUTONEG_ENABLE_BINARY, + EMAC0_PHYISOLATE => EMAC0_PHYISOLATE_BINARY, + EMAC0_PHYLOOPBACKMSB => EMAC0_PHYLOOPBACKMSB_BINARY, + EMAC0_PHYPOWERDOWN => EMAC0_PHYPOWERDOWN_BINARY, + EMAC0_PHYRESET => EMAC0_PHYRESET_BINARY, + EMAC0_RGMII_ENABLE => EMAC0_RGMII_ENABLE_BINARY, + EMAC0_RX16BITCLIENT_ENABLE => EMAC0_RX16BITCLIENT_ENABLE_BINARY, + EMAC0_RXFLOWCTRL_ENABLE => EMAC0_RXFLOWCTRL_ENABLE_BINARY, + EMAC0_RXHALFDUPLEX => EMAC0_RXHALFDUPLEX_BINARY, + EMAC0_RXINBANDFCS_ENABLE => EMAC0_RXINBANDFCS_ENABLE_BINARY, + EMAC0_RXJUMBOFRAME_ENABLE => EMAC0_RXJUMBOFRAME_ENABLE_BINARY, + EMAC0_RXRESET => EMAC0_RXRESET_BINARY, + EMAC0_RXVLAN_ENABLE => EMAC0_RXVLAN_ENABLE_BINARY, + EMAC0_RX_ENABLE => EMAC0_RX_ENABLE_BINARY, + EMAC0_SGMII_ENABLE => EMAC0_SGMII_ENABLE_BINARY, + EMAC0_SPEED_LSB => EMAC0_SPEED_LSB_BINARY, + EMAC0_SPEED_MSB => EMAC0_SPEED_MSB_BINARY, + EMAC0_TX16BITCLIENT_ENABLE => EMAC0_TX16BITCLIENT_ENABLE_BINARY, + EMAC0_TXFLOWCTRL_ENABLE => EMAC0_TXFLOWCTRL_ENABLE_BINARY, + EMAC0_TXHALFDUPLEX => EMAC0_TXHALFDUPLEX_BINARY, + EMAC0_TXIFGADJUST_ENABLE => EMAC0_TXIFGADJUST_ENABLE_BINARY, + EMAC0_TXINBANDFCS_ENABLE => EMAC0_TXINBANDFCS_ENABLE_BINARY, + EMAC0_TXJUMBOFRAME_ENABLE => EMAC0_TXJUMBOFRAME_ENABLE_BINARY, + EMAC0_TXRESET => EMAC0_TXRESET_BINARY, + EMAC0_TXVLAN_ENABLE => EMAC0_TXVLAN_ENABLE_BINARY, + EMAC0_TX_ENABLE => EMAC0_TX_ENABLE_BINARY, + EMAC0_UNICASTADDR => EMAC0_UNICASTADDR_BINARY, + EMAC0_UNIDIRECTION_ENABLE => EMAC0_UNIDIRECTION_ENABLE_BINARY, + EMAC0_USECLKEN => EMAC0_USECLKEN_BINARY, + EMAC1_1000BASEX_ENABLE => EMAC1_1000BASEX_ENABLE_BINARY, + EMAC1_ADDRFILTER_ENABLE => EMAC1_ADDRFILTER_ENABLE_BINARY, + EMAC1_BYTEPHY => EMAC1_BYTEPHY_BINARY, + EMAC1_CONFIGVEC_79 => EMAC1_CONFIGVEC_79_BINARY, + EMAC1_DCRBASEADDR => EMAC1_DCRBASEADDR_BINARY, + EMAC1_GTLOOPBACK => EMAC1_GTLOOPBACK_BINARY, + EMAC1_HOST_ENABLE => EMAC1_HOST_ENABLE_BINARY, + EMAC1_LINKTIMERVAL => EMAC1_LINKTIMERVAL_BINARY, + EMAC1_LTCHECK_DISABLE => EMAC1_LTCHECK_DISABLE_BINARY, + EMAC1_MDIO_ENABLE => EMAC1_MDIO_ENABLE_BINARY, + EMAC1_PAUSEADDR => EMAC1_PAUSEADDR_BINARY, + EMAC1_PHYINITAUTONEG_ENABLE => EMAC1_PHYINITAUTONEG_ENABLE_BINARY, + EMAC1_PHYISOLATE => EMAC1_PHYISOLATE_BINARY, + EMAC1_PHYLOOPBACKMSB => EMAC1_PHYLOOPBACKMSB_BINARY, + EMAC1_PHYPOWERDOWN => EMAC1_PHYPOWERDOWN_BINARY, + EMAC1_PHYRESET => EMAC1_PHYRESET_BINARY, + EMAC1_RGMII_ENABLE => EMAC1_RGMII_ENABLE_BINARY, + EMAC1_RX16BITCLIENT_ENABLE => EMAC1_RX16BITCLIENT_ENABLE_BINARY, + EMAC1_RXFLOWCTRL_ENABLE => EMAC1_RXFLOWCTRL_ENABLE_BINARY, + EMAC1_RXHALFDUPLEX => EMAC1_RXHALFDUPLEX_BINARY, + EMAC1_RXINBANDFCS_ENABLE => EMAC1_RXINBANDFCS_ENABLE_BINARY, + EMAC1_RXJUMBOFRAME_ENABLE => EMAC1_RXJUMBOFRAME_ENABLE_BINARY, + EMAC1_RXRESET => EMAC1_RXRESET_BINARY, + EMAC1_RXVLAN_ENABLE => EMAC1_RXVLAN_ENABLE_BINARY, + EMAC1_RX_ENABLE => EMAC1_RX_ENABLE_BINARY, + EMAC1_SGMII_ENABLE => EMAC1_SGMII_ENABLE_BINARY, + EMAC1_SPEED_LSB => EMAC1_SPEED_LSB_BINARY, + EMAC1_SPEED_MSB => EMAC1_SPEED_MSB_BINARY, + EMAC1_TX16BITCLIENT_ENABLE => EMAC1_TX16BITCLIENT_ENABLE_BINARY, + EMAC1_TXFLOWCTRL_ENABLE => EMAC1_TXFLOWCTRL_ENABLE_BINARY, + EMAC1_TXHALFDUPLEX => EMAC1_TXHALFDUPLEX_BINARY, + EMAC1_TXIFGADJUST_ENABLE => EMAC1_TXIFGADJUST_ENABLE_BINARY, + EMAC1_TXINBANDFCS_ENABLE => EMAC1_TXINBANDFCS_ENABLE_BINARY, + EMAC1_TXJUMBOFRAME_ENABLE => EMAC1_TXJUMBOFRAME_ENABLE_BINARY, + EMAC1_TXRESET => EMAC1_TXRESET_BINARY, + EMAC1_TXVLAN_ENABLE => EMAC1_TXVLAN_ENABLE_BINARY, + EMAC1_TX_ENABLE => EMAC1_TX_ENABLE_BINARY, + EMAC1_UNICASTADDR => EMAC1_UNICASTADDR_BINARY, + EMAC1_UNIDIRECTION_ENABLE => EMAC1_UNIDIRECTION_ENABLE_BINARY, + EMAC1_USECLKEN => EMAC1_USECLKEN_BINARY, + + DCRHOSTDONEIR => DCRHOSTDONEIR_outdelay, + EMAC0CLIENTANINTERRUPT => EMAC0CLIENTANINTERRUPT_outdelay, + EMAC0CLIENTRXBADFRAME => EMAC0CLIENTRXBADFRAME_outdelay, + EMAC0CLIENTRXCLIENTCLKOUT => EMAC0CLIENTRXCLIENTCLKOUT_outdelay, + EMAC0CLIENTRXD => EMAC0CLIENTRXD_outdelay, + EMAC0CLIENTRXDVLD => EMAC0CLIENTRXDVLD_outdelay, + EMAC0CLIENTRXDVLDMSW => EMAC0CLIENTRXDVLDMSW_outdelay, + EMAC0CLIENTRXFRAMEDROP => EMAC0CLIENTRXFRAMEDROP_outdelay, + EMAC0CLIENTRXGOODFRAME => EMAC0CLIENTRXGOODFRAME_outdelay, + EMAC0CLIENTRXSTATS => EMAC0CLIENTRXSTATS_outdelay, + EMAC0CLIENTRXSTATSBYTEVLD => EMAC0CLIENTRXSTATSBYTEVLD_outdelay, + EMAC0CLIENTRXSTATSVLD => EMAC0CLIENTRXSTATSVLD_outdelay, + EMAC0CLIENTTXACK => EMAC0CLIENTTXACK_outdelay, + EMAC0CLIENTTXCLIENTCLKOUT => EMAC0CLIENTTXCLIENTCLKOUT_outdelay, + EMAC0CLIENTTXCOLLISION => EMAC0CLIENTTXCOLLISION_outdelay, + EMAC0CLIENTTXRETRANSMIT => EMAC0CLIENTTXRETRANSMIT_outdelay, + EMAC0CLIENTTXSTATS => EMAC0CLIENTTXSTATS_outdelay, + EMAC0CLIENTTXSTATSBYTEVLD => EMAC0CLIENTTXSTATSBYTEVLD_outdelay, + EMAC0CLIENTTXSTATSVLD => EMAC0CLIENTTXSTATSVLD_outdelay, + EMAC0PHYENCOMMAALIGN => EMAC0PHYENCOMMAALIGN_outdelay, + EMAC0PHYLOOPBACKMSB => EMAC0PHYLOOPBACKMSB_outdelay, + EMAC0PHYMCLKOUT => EMAC0PHYMCLKOUT_outdelay, + EMAC0PHYMDOUT => EMAC0PHYMDOUT_outdelay, + EMAC0PHYMDTRI => EMAC0PHYMDTRI_outdelay, + EMAC0PHYMGTRXRESET => EMAC0PHYMGTRXRESET_outdelay, + EMAC0PHYMGTTXRESET => EMAC0PHYMGTTXRESET_outdelay, + EMAC0PHYPOWERDOWN => EMAC0PHYPOWERDOWN_outdelay, + EMAC0PHYSYNCACQSTATUS => EMAC0PHYSYNCACQSTATUS_outdelay, + EMAC0PHYTXCHARDISPMODE => EMAC0PHYTXCHARDISPMODE_outdelay, + EMAC0PHYTXCHARDISPVAL => EMAC0PHYTXCHARDISPVAL_outdelay, + EMAC0PHYTXCHARISK => EMAC0PHYTXCHARISK_outdelay, + EMAC0PHYTXCLK => EMAC0PHYTXCLK_outdelay, + EMAC0PHYTXD => EMAC0PHYTXD_outdelay, + EMAC0PHYTXEN => EMAC0PHYTXEN_outdelay, + EMAC0PHYTXER => EMAC0PHYTXER_outdelay, + EMAC0PHYTXGMIIMIICLKOUT => EMAC0PHYTXGMIIMIICLKOUT_outdelay, + EMAC0SPEEDIS10100 => EMAC0SPEEDIS10100_outdelay, + EMAC1CLIENTANINTERRUPT => EMAC1CLIENTANINTERRUPT_outdelay, + EMAC1CLIENTRXBADFRAME => EMAC1CLIENTRXBADFRAME_outdelay, + EMAC1CLIENTRXCLIENTCLKOUT => EMAC1CLIENTRXCLIENTCLKOUT_outdelay, + EMAC1CLIENTRXD => EMAC1CLIENTRXD_outdelay, + EMAC1CLIENTRXDVLD => EMAC1CLIENTRXDVLD_outdelay, + EMAC1CLIENTRXDVLDMSW => EMAC1CLIENTRXDVLDMSW_outdelay, + EMAC1CLIENTRXFRAMEDROP => EMAC1CLIENTRXFRAMEDROP_outdelay, + EMAC1CLIENTRXGOODFRAME => EMAC1CLIENTRXGOODFRAME_outdelay, + EMAC1CLIENTRXSTATS => EMAC1CLIENTRXSTATS_outdelay, + EMAC1CLIENTRXSTATSBYTEVLD => EMAC1CLIENTRXSTATSBYTEVLD_outdelay, + EMAC1CLIENTRXSTATSVLD => EMAC1CLIENTRXSTATSVLD_outdelay, + EMAC1CLIENTTXACK => EMAC1CLIENTTXACK_outdelay, + EMAC1CLIENTTXCLIENTCLKOUT => EMAC1CLIENTTXCLIENTCLKOUT_outdelay, + EMAC1CLIENTTXCOLLISION => EMAC1CLIENTTXCOLLISION_outdelay, + EMAC1CLIENTTXRETRANSMIT => EMAC1CLIENTTXRETRANSMIT_outdelay, + EMAC1CLIENTTXSTATS => EMAC1CLIENTTXSTATS_outdelay, + EMAC1CLIENTTXSTATSBYTEVLD => EMAC1CLIENTTXSTATSBYTEVLD_outdelay, + EMAC1CLIENTTXSTATSVLD => EMAC1CLIENTTXSTATSVLD_outdelay, + EMAC1PHYENCOMMAALIGN => EMAC1PHYENCOMMAALIGN_outdelay, + EMAC1PHYLOOPBACKMSB => EMAC1PHYLOOPBACKMSB_outdelay, + EMAC1PHYMCLKOUT => EMAC1PHYMCLKOUT_outdelay, + EMAC1PHYMDOUT => EMAC1PHYMDOUT_outdelay, + EMAC1PHYMDTRI => EMAC1PHYMDTRI_outdelay, + EMAC1PHYMGTRXRESET => EMAC1PHYMGTRXRESET_outdelay, + EMAC1PHYMGTTXRESET => EMAC1PHYMGTTXRESET_outdelay, + EMAC1PHYPOWERDOWN => EMAC1PHYPOWERDOWN_outdelay, + EMAC1PHYSYNCACQSTATUS => EMAC1PHYSYNCACQSTATUS_outdelay, + EMAC1PHYTXCHARDISPMODE => EMAC1PHYTXCHARDISPMODE_outdelay, + EMAC1PHYTXCHARDISPVAL => EMAC1PHYTXCHARDISPVAL_outdelay, + EMAC1PHYTXCHARISK => EMAC1PHYTXCHARISK_outdelay, + EMAC1PHYTXCLK => EMAC1PHYTXCLK_outdelay, + EMAC1PHYTXD => EMAC1PHYTXD_outdelay, + EMAC1PHYTXEN => EMAC1PHYTXEN_outdelay, + EMAC1PHYTXER => EMAC1PHYTXER_outdelay, + EMAC1PHYTXGMIIMIICLKOUT => EMAC1PHYTXGMIIMIICLKOUT_outdelay, + EMAC1SPEEDIS10100 => EMAC1SPEEDIS10100_outdelay, + EMACDCRACK => EMACDCRACK_outdelay, + EMACDCRDBUS => EMACDCRDBUS_outdelay, + HOSTMIIMRDY => HOSTMIIMRDY_outdelay, + HOSTRDDATA => HOSTRDDATA_outdelay, + + CLIENTEMAC0DCMLOCKED => CLIENTEMAC0DCMLOCKED_indelay, + CLIENTEMAC0PAUSEREQ => CLIENTEMAC0PAUSEREQ_indelay, + CLIENTEMAC0PAUSEVAL => CLIENTEMAC0PAUSEVAL_indelay, + CLIENTEMAC0RXCLIENTCLKIN => CLIENTEMAC0RXCLIENTCLKIN_indelay, + CLIENTEMAC0TXCLIENTCLKIN => CLIENTEMAC0TXCLIENTCLKIN_indelay, + CLIENTEMAC0TXD => CLIENTEMAC0TXD_indelay, + CLIENTEMAC0TXDVLD => CLIENTEMAC0TXDVLD_indelay, + CLIENTEMAC0TXDVLDMSW => CLIENTEMAC0TXDVLDMSW_indelay, + CLIENTEMAC0TXFIRSTBYTE => CLIENTEMAC0TXFIRSTBYTE_indelay, + CLIENTEMAC0TXIFGDELAY => CLIENTEMAC0TXIFGDELAY_indelay, + CLIENTEMAC0TXUNDERRUN => CLIENTEMAC0TXUNDERRUN_indelay, + CLIENTEMAC1DCMLOCKED => CLIENTEMAC1DCMLOCKED_indelay, + CLIENTEMAC1PAUSEREQ => CLIENTEMAC1PAUSEREQ_indelay, + CLIENTEMAC1PAUSEVAL => CLIENTEMAC1PAUSEVAL_indelay, + CLIENTEMAC1RXCLIENTCLKIN => CLIENTEMAC1RXCLIENTCLKIN_indelay, + CLIENTEMAC1TXCLIENTCLKIN => CLIENTEMAC1TXCLIENTCLKIN_indelay, + CLIENTEMAC1TXD => CLIENTEMAC1TXD_indelay, + CLIENTEMAC1TXDVLD => CLIENTEMAC1TXDVLD_indelay, + CLIENTEMAC1TXDVLDMSW => CLIENTEMAC1TXDVLDMSW_indelay, + CLIENTEMAC1TXFIRSTBYTE => CLIENTEMAC1TXFIRSTBYTE_indelay, + CLIENTEMAC1TXIFGDELAY => CLIENTEMAC1TXIFGDELAY_indelay, + CLIENTEMAC1TXUNDERRUN => CLIENTEMAC1TXUNDERRUN_indelay, + DCREMACABUS => DCREMACABUS_indelay, + DCREMACCLK => DCREMACCLK_indelay, + DCREMACDBUS => DCREMACDBUS_indelay, + DCREMACENABLE => DCREMACENABLE_indelay, + DCREMACREAD => DCREMACREAD_indelay, + DCREMACWRITE => DCREMACWRITE_indelay, + HOSTADDR => HOSTADDR_indelay, + HOSTCLK => HOSTCLK_indelay, + HOSTEMAC1SEL => HOSTEMAC1SEL_indelay, + HOSTMIIMSEL => HOSTMIIMSEL_indelay, + HOSTOPCODE => HOSTOPCODE_indelay, + HOSTREQ => HOSTREQ_indelay, + HOSTWRDATA => HOSTWRDATA_indelay, + PHYEMAC0COL => PHYEMAC0COL_indelay, + PHYEMAC0CRS => PHYEMAC0CRS_indelay, + PHYEMAC0GTXCLK => PHYEMAC0GTXCLK_indelay, + PHYEMAC0MCLKIN => PHYEMAC0MCLKIN_indelay, + PHYEMAC0MDIN => PHYEMAC0MDIN_indelay, + PHYEMAC0MIITXCLK => PHYEMAC0MIITXCLK_indelay, + PHYEMAC0PHYAD => PHYEMAC0PHYAD_indelay, + PHYEMAC0RXBUFERR => PHYEMAC0RXBUFERR_indelay, + PHYEMAC0RXBUFSTATUS => PHYEMAC0RXBUFSTATUS_indelay, + PHYEMAC0RXCHARISCOMMA => PHYEMAC0RXCHARISCOMMA_indelay, + PHYEMAC0RXCHARISK => PHYEMAC0RXCHARISK_indelay, + PHYEMAC0RXCHECKINGCRC => PHYEMAC0RXCHECKINGCRC_indelay, + PHYEMAC0RXCLK => PHYEMAC0RXCLK_indelay, + PHYEMAC0RXCLKCORCNT => PHYEMAC0RXCLKCORCNT_indelay, + PHYEMAC0RXCOMMADET => PHYEMAC0RXCOMMADET_indelay, + PHYEMAC0RXD => PHYEMAC0RXD_indelay, + PHYEMAC0RXDISPERR => PHYEMAC0RXDISPERR_indelay, + PHYEMAC0RXDV => PHYEMAC0RXDV_indelay, + PHYEMAC0RXER => PHYEMAC0RXER_indelay, + PHYEMAC0RXLOSSOFSYNC => PHYEMAC0RXLOSSOFSYNC_indelay, + PHYEMAC0RXNOTINTABLE => PHYEMAC0RXNOTINTABLE_indelay, + PHYEMAC0RXRUNDISP => PHYEMAC0RXRUNDISP_indelay, + PHYEMAC0SIGNALDET => PHYEMAC0SIGNALDET_indelay, + PHYEMAC0TXBUFERR => PHYEMAC0TXBUFERR_indelay, + PHYEMAC0TXGMIIMIICLKIN => PHYEMAC0TXGMIIMIICLKIN_indelay, + PHYEMAC1COL => PHYEMAC1COL_indelay, + PHYEMAC1CRS => PHYEMAC1CRS_indelay, + PHYEMAC1GTXCLK => PHYEMAC1GTXCLK_indelay, + PHYEMAC1MCLKIN => PHYEMAC1MCLKIN_indelay, + PHYEMAC1MDIN => PHYEMAC1MDIN_indelay, + PHYEMAC1MIITXCLK => PHYEMAC1MIITXCLK_indelay, + PHYEMAC1PHYAD => PHYEMAC1PHYAD_indelay, + PHYEMAC1RXBUFERR => PHYEMAC1RXBUFERR_indelay, + PHYEMAC1RXBUFSTATUS => PHYEMAC1RXBUFSTATUS_indelay, + PHYEMAC1RXCHARISCOMMA => PHYEMAC1RXCHARISCOMMA_indelay, + PHYEMAC1RXCHARISK => PHYEMAC1RXCHARISK_indelay, + PHYEMAC1RXCHECKINGCRC => PHYEMAC1RXCHECKINGCRC_indelay, + PHYEMAC1RXCLK => PHYEMAC1RXCLK_indelay, + PHYEMAC1RXCLKCORCNT => PHYEMAC1RXCLKCORCNT_indelay, + PHYEMAC1RXCOMMADET => PHYEMAC1RXCOMMADET_indelay, + PHYEMAC1RXD => PHYEMAC1RXD_indelay, + PHYEMAC1RXDISPERR => PHYEMAC1RXDISPERR_indelay, + PHYEMAC1RXDV => PHYEMAC1RXDV_indelay, + PHYEMAC1RXER => PHYEMAC1RXER_indelay, + PHYEMAC1RXLOSSOFSYNC => PHYEMAC1RXLOSSOFSYNC_indelay, + PHYEMAC1RXNOTINTABLE => PHYEMAC1RXNOTINTABLE_indelay, + PHYEMAC1RXRUNDISP => PHYEMAC1RXRUNDISP_indelay, + PHYEMAC1SIGNALDET => PHYEMAC1SIGNALDET_indelay, + PHYEMAC1TXBUFERR => PHYEMAC1TXBUFERR_indelay, + PHYEMAC1TXGMIIMIICLKIN => PHYEMAC1TXGMIIMIICLKIN_indelay, + RESET => RESET_indelay + ); + + INIPROC : process + begin + case EMAC0_RXHALFDUPLEX is + when FALSE => EMAC0_RXHALFDUPLEX_BINARY <= '0'; + when TRUE => EMAC0_RXHALFDUPLEX_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_RXHALFDUPLEX is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_RXVLAN_ENABLE is + when FALSE => EMAC0_RXVLAN_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_RXVLAN_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_RXVLAN_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_RX_ENABLE is + when FALSE => EMAC0_RX_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_RX_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_RX_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_RXINBANDFCS_ENABLE is + when FALSE => EMAC0_RXINBANDFCS_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_RXINBANDFCS_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_RXINBANDFCS_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_RXJUMBOFRAME_ENABLE is + when FALSE => EMAC0_RXJUMBOFRAME_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_RXJUMBOFRAME_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_RXJUMBOFRAME_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_RXRESET is + when FALSE => EMAC0_RXRESET_BINARY <= '0'; + when TRUE => EMAC0_RXRESET_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_RXRESET is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_TXIFGADJUST_ENABLE is + when FALSE => EMAC0_TXIFGADJUST_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_TXIFGADJUST_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_TXIFGADJUST_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_TXHALFDUPLEX is + when FALSE => EMAC0_TXHALFDUPLEX_BINARY <= '0'; + when TRUE => EMAC0_TXHALFDUPLEX_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_TXHALFDUPLEX is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_TXVLAN_ENABLE is + when FALSE => EMAC0_TXVLAN_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_TXVLAN_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_TXVLAN_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_TX_ENABLE is + when FALSE => EMAC0_TX_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_TX_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_TX_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_TXINBANDFCS_ENABLE is + when FALSE => EMAC0_TXINBANDFCS_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_TXINBANDFCS_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_TXINBANDFCS_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_TXJUMBOFRAME_ENABLE is + when FALSE => EMAC0_TXJUMBOFRAME_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_TXJUMBOFRAME_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_TXJUMBOFRAME_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_TXRESET is + when FALSE => EMAC0_TXRESET_BINARY <= '0'; + when TRUE => EMAC0_TXRESET_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_TXRESET is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_TXFLOWCTRL_ENABLE is + when FALSE => EMAC0_TXFLOWCTRL_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_TXFLOWCTRL_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_TXFLOWCTRL_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_RXFLOWCTRL_ENABLE is + when FALSE => EMAC0_RXFLOWCTRL_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_RXFLOWCTRL_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_RXFLOWCTRL_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_LTCHECK_DISABLE is + when FALSE => EMAC0_LTCHECK_DISABLE_BINARY <= '0'; + when TRUE => EMAC0_LTCHECK_DISABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_LTCHECK_DISABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_ADDRFILTER_ENABLE is + when FALSE => EMAC0_ADDRFILTER_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_ADDRFILTER_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_ADDRFILTER_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_RX16BITCLIENT_ENABLE is + when FALSE => EMAC0_RX16BITCLIENT_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_RX16BITCLIENT_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_RX16BITCLIENT_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_TX16BITCLIENT_ENABLE is + when FALSE => EMAC0_TX16BITCLIENT_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_TX16BITCLIENT_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_TX16BITCLIENT_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_HOST_ENABLE is + when FALSE => EMAC0_HOST_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_HOST_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_HOST_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_1000BASEX_ENABLE is + when FALSE => EMAC0_1000BASEX_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_1000BASEX_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_1000BASEX_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_SGMII_ENABLE is + when FALSE => EMAC0_SGMII_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_SGMII_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_SGMII_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_RGMII_ENABLE is + when FALSE => EMAC0_RGMII_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_RGMII_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_RGMII_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_SPEED_LSB is + when FALSE => EMAC0_SPEED_LSB_BINARY <= '0'; + when TRUE => EMAC0_SPEED_LSB_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_SPEED_LSB is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_SPEED_MSB is + when FALSE => EMAC0_SPEED_MSB_BINARY <= '0'; + when TRUE => EMAC0_SPEED_MSB_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_SPEED_MSB is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_MDIO_ENABLE is + when FALSE => EMAC0_MDIO_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_MDIO_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_MDIO_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_PHYLOOPBACKMSB is + when FALSE => EMAC0_PHYLOOPBACKMSB_BINARY <= '0'; + when TRUE => EMAC0_PHYLOOPBACKMSB_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_PHYLOOPBACKMSB is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_PHYPOWERDOWN is + when FALSE => EMAC0_PHYPOWERDOWN_BINARY <= '0'; + when TRUE => EMAC0_PHYPOWERDOWN_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_PHYPOWERDOWN is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_PHYISOLATE is + when FALSE => EMAC0_PHYISOLATE_BINARY <= '0'; + when TRUE => EMAC0_PHYISOLATE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_PHYISOLATE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_PHYINITAUTONEG_ENABLE is + when FALSE => EMAC0_PHYINITAUTONEG_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_PHYINITAUTONEG_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_PHYINITAUTONEG_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_PHYRESET is + when FALSE => EMAC0_PHYRESET_BINARY <= '0'; + when TRUE => EMAC0_PHYRESET_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_PHYRESET is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_CONFIGVEC_79 is + when FALSE => EMAC0_CONFIGVEC_79_BINARY <= '0'; + when TRUE => EMAC0_CONFIGVEC_79_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_CONFIGVEC_79 is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_UNIDIRECTION_ENABLE is + when FALSE => EMAC0_UNIDIRECTION_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_UNIDIRECTION_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_UNIDIRECTION_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_GTLOOPBACK is + when FALSE => EMAC0_GTLOOPBACK_BINARY <= '0'; + when TRUE => EMAC0_GTLOOPBACK_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_GTLOOPBACK is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_BYTEPHY is + when FALSE => EMAC0_BYTEPHY_BINARY <= '0'; + when TRUE => EMAC0_BYTEPHY_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_BYTEPHY is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_USECLKEN is + when FALSE => EMAC0_USECLKEN_BINARY <= '0'; + when TRUE => EMAC0_USECLKEN_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_USECLKEN is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_RXHALFDUPLEX is + when FALSE => EMAC1_RXHALFDUPLEX_BINARY <= '0'; + when TRUE => EMAC1_RXHALFDUPLEX_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_RXHALFDUPLEX is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_RXVLAN_ENABLE is + when FALSE => EMAC1_RXVLAN_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_RXVLAN_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_RXVLAN_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_RX_ENABLE is + when FALSE => EMAC1_RX_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_RX_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_RX_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_RXINBANDFCS_ENABLE is + when FALSE => EMAC1_RXINBANDFCS_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_RXINBANDFCS_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_RXINBANDFCS_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_RXJUMBOFRAME_ENABLE is + when FALSE => EMAC1_RXJUMBOFRAME_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_RXJUMBOFRAME_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_RXJUMBOFRAME_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_RXRESET is + when FALSE => EMAC1_RXRESET_BINARY <= '0'; + when TRUE => EMAC1_RXRESET_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_RXRESET is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_TXIFGADJUST_ENABLE is + when FALSE => EMAC1_TXIFGADJUST_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_TXIFGADJUST_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_TXIFGADJUST_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_TXHALFDUPLEX is + when FALSE => EMAC1_TXHALFDUPLEX_BINARY <= '0'; + when TRUE => EMAC1_TXHALFDUPLEX_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_TXHALFDUPLEX is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_TXVLAN_ENABLE is + when FALSE => EMAC1_TXVLAN_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_TXVLAN_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_TXVLAN_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_TX_ENABLE is + when FALSE => EMAC1_TX_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_TX_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_TX_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_TXINBANDFCS_ENABLE is + when FALSE => EMAC1_TXINBANDFCS_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_TXINBANDFCS_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_TXINBANDFCS_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_TXJUMBOFRAME_ENABLE is + when FALSE => EMAC1_TXJUMBOFRAME_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_TXJUMBOFRAME_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_TXJUMBOFRAME_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_TXRESET is + when FALSE => EMAC1_TXRESET_BINARY <= '0'; + when TRUE => EMAC1_TXRESET_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_TXRESET is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_TXFLOWCTRL_ENABLE is + when FALSE => EMAC1_TXFLOWCTRL_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_TXFLOWCTRL_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_TXFLOWCTRL_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_RXFLOWCTRL_ENABLE is + when FALSE => EMAC1_RXFLOWCTRL_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_RXFLOWCTRL_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_RXFLOWCTRL_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_LTCHECK_DISABLE is + when FALSE => EMAC1_LTCHECK_DISABLE_BINARY <= '0'; + when TRUE => EMAC1_LTCHECK_DISABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_LTCHECK_DISABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_ADDRFILTER_ENABLE is + when FALSE => EMAC1_ADDRFILTER_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_ADDRFILTER_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_ADDRFILTER_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_RX16BITCLIENT_ENABLE is + when FALSE => EMAC1_RX16BITCLIENT_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_RX16BITCLIENT_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_RX16BITCLIENT_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_TX16BITCLIENT_ENABLE is + when FALSE => EMAC1_TX16BITCLIENT_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_TX16BITCLIENT_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_TX16BITCLIENT_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_HOST_ENABLE is + when FALSE => EMAC1_HOST_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_HOST_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_HOST_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_1000BASEX_ENABLE is + when FALSE => EMAC1_1000BASEX_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_1000BASEX_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_1000BASEX_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_SGMII_ENABLE is + when FALSE => EMAC1_SGMII_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_SGMII_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_SGMII_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_RGMII_ENABLE is + when FALSE => EMAC1_RGMII_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_RGMII_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_RGMII_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_SPEED_LSB is + when FALSE => EMAC1_SPEED_LSB_BINARY <= '0'; + when TRUE => EMAC1_SPEED_LSB_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_SPEED_LSB is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_SPEED_MSB is + when FALSE => EMAC1_SPEED_MSB_BINARY <= '0'; + when TRUE => EMAC1_SPEED_MSB_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_SPEED_MSB is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_MDIO_ENABLE is + when FALSE => EMAC1_MDIO_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_MDIO_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_MDIO_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_PHYLOOPBACKMSB is + when FALSE => EMAC1_PHYLOOPBACKMSB_BINARY <= '0'; + when TRUE => EMAC1_PHYLOOPBACKMSB_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_PHYLOOPBACKMSB is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_PHYPOWERDOWN is + when FALSE => EMAC1_PHYPOWERDOWN_BINARY <= '0'; + when TRUE => EMAC1_PHYPOWERDOWN_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_PHYPOWERDOWN is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_PHYISOLATE is + when FALSE => EMAC1_PHYISOLATE_BINARY <= '0'; + when TRUE => EMAC1_PHYISOLATE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_PHYISOLATE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_PHYINITAUTONEG_ENABLE is + when FALSE => EMAC1_PHYINITAUTONEG_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_PHYINITAUTONEG_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_PHYINITAUTONEG_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_PHYRESET is + when FALSE => EMAC1_PHYRESET_BINARY <= '0'; + when TRUE => EMAC1_PHYRESET_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_PHYRESET is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_CONFIGVEC_79 is + when FALSE => EMAC1_CONFIGVEC_79_BINARY <= '0'; + when TRUE => EMAC1_CONFIGVEC_79_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_CONFIGVEC_79 is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_UNIDIRECTION_ENABLE is + when FALSE => EMAC1_UNIDIRECTION_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_UNIDIRECTION_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_UNIDIRECTION_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_GTLOOPBACK is + when FALSE => EMAC1_GTLOOPBACK_BINARY <= '0'; + when TRUE => EMAC1_GTLOOPBACK_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_GTLOOPBACK is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_BYTEPHY is + when FALSE => EMAC1_BYTEPHY_BINARY <= '0'; + when TRUE => EMAC1_BYTEPHY_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_BYTEPHY is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_USECLKEN is + when FALSE => EMAC1_USECLKEN_BINARY <= '0'; + when TRUE => EMAC1_USECLKEN_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_USECLKEN is neither TRUE nor FALSE." severity error; + end case; + wait; + end process INIPROC; + + TIMING : process + + variable DCRHOSTDONEIR_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTANINTERRUPT_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXBADFRAME_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD0_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD1_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD2_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD3_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD4_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD5_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD6_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD7_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD8_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD9_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD10_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD11_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD12_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD13_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD14_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD15_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXDVLD_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXDVLDMSW_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXFRAMEDROP_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXGOODFRAME_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS0_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS1_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS2_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS3_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS4_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS5_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS6_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATSVLD_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXACK_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXCOLLISION_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXGMIIMIICLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXRETRANSMIT_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXSTATS_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXSTATSVLD_GlitchData : VitalGlitchDataType; + variable EMAC0PHYENCOMMAALIGN_GlitchData : VitalGlitchDataType; + variable EMAC0PHYLOOPBACKMSB_GlitchData : VitalGlitchDataType; + variable EMAC0PHYMCLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC0PHYMDOUT_GlitchData : VitalGlitchDataType; + variable EMAC0PHYMDTRI_GlitchData : VitalGlitchDataType; + variable EMAC0PHYMGTRXRESET_GlitchData : VitalGlitchDataType; + variable EMAC0PHYMGTTXRESET_GlitchData : VitalGlitchDataType; + variable EMAC0PHYPOWERDOWN_GlitchData : VitalGlitchDataType; + variable EMAC0PHYSYNCACQSTATUS_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXCHARDISPMODE_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXCHARDISPVAL_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXCHARISK_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXCLK_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD0_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD1_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD2_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD3_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD4_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD5_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD6_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD7_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXEN_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXER_GlitchData : VitalGlitchDataType; + variable EMAC0SPEEDIS10100_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTANINTERRUPT_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXBADFRAME_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD0_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD1_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD2_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD3_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD4_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD5_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD6_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD7_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD8_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD9_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD10_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD11_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD12_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD13_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD14_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD15_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXDVLD_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXDVLDMSW_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXFRAMEDROP_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXGOODFRAME_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS0_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS1_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS2_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS3_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS4_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS5_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS6_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATSVLD_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXACK_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXCOLLISION_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXGMIIMIICLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXRETRANSMIT_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXSTATS_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXSTATSVLD_GlitchData : VitalGlitchDataType; + variable EMAC1PHYENCOMMAALIGN_GlitchData : VitalGlitchDataType; + variable EMAC1PHYLOOPBACKMSB_GlitchData : VitalGlitchDataType; + variable EMAC1PHYMCLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC1PHYMDOUT_GlitchData : VitalGlitchDataType; + variable EMAC1PHYMDTRI_GlitchData : VitalGlitchDataType; + variable EMAC1PHYMGTRXRESET_GlitchData : VitalGlitchDataType; + variable EMAC1PHYMGTTXRESET_GlitchData : VitalGlitchDataType; + variable EMAC1PHYPOWERDOWN_GlitchData : VitalGlitchDataType; + variable EMAC1PHYSYNCACQSTATUS_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXCHARDISPMODE_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXCHARDISPVAL_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXCHARISK_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXCLK_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD0_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD1_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD2_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD3_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD4_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD5_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD6_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD7_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXEN_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXER_GlitchData : VitalGlitchDataType; + variable EMAC1SPEEDIS10100_GlitchData : VitalGlitchDataType; + variable EMACDCRACK_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS0_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS1_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS2_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS3_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS4_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS5_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS6_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS7_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS8_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS9_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS10_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS11_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS12_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS13_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS14_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS15_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS16_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS17_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS18_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS19_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS20_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS21_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS22_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS23_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS24_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS25_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS26_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS27_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS28_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS29_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS30_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS31_GlitchData : VitalGlitchDataType; + variable HOSTMIIMRDY_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA0_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA1_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA2_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA3_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA4_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA5_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA6_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA7_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA8_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA9_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA10_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA11_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA12_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA13_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA14_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA15_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA16_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA17_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA18_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA19_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA20_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA21_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA22_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA23_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA24_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA25_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA26_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA27_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA28_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA29_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA30_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA31_GlitchData : VitalGlitchDataType; +begin + + VitalPathDelay01 + ( + OutSignal => DCRHOSTDONEIR, + GlitchData => DCRHOSTDONEIR_GlitchData, + OutSignalName => "DCRHOSTDONEIR", + OutTemp => DCRHOSTDONEIR_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTANINTERRUPT, + GlitchData => EMAC0CLIENTANINTERRUPT_GlitchData, + OutSignalName => "EMAC0CLIENTANINTERRUPT", + OutTemp => EMAC0CLIENTANINTERRUPT_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXBADFRAME, + GlitchData => EMAC0CLIENTRXBADFRAME_GlitchData, + OutSignalName => "EMAC0CLIENTRXBADFRAME", + OutTemp => EMAC0CLIENTRXBADFRAME_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXBADFRAME, + GlitchData => EMAC0CLIENTRXBADFRAME_GlitchData, + OutSignalName => "EMAC0CLIENTRXBADFRAME", + OutTemp => EMAC0CLIENTRXBADFRAME_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXBADFRAME, + GlitchData => EMAC0CLIENTRXBADFRAME_GlitchData, + OutSignalName => "EMAC0CLIENTRXBADFRAME", + OutTemp => EMAC0CLIENTRXBADFRAME_OUT, + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXCLIENTCLKOUT, + GlitchData => EMAC0CLIENTRXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC0CLIENTRXCLIENTCLKOUT", + OutTemp => EMAC0CLIENTRXCLIENTCLKOUT_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXCLIENTCLKOUT, + GlitchData => EMAC0CLIENTRXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC0CLIENTRXCLIENTCLKOUT", + OutTemp => EMAC0CLIENTRXCLIENTCLKOUT_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXCLIENTCLKOUT, + GlitchData => EMAC0CLIENTRXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC0CLIENTRXCLIENTCLKOUT", + OutTemp => EMAC0CLIENTRXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXCLIENTCLKOUT, + GlitchData => EMAC0CLIENTRXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC0CLIENTRXCLIENTCLKOUT", + OutTemp => EMAC0CLIENTRXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(0), + GlitchData => EMAC0CLIENTRXD0_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(0)", + OutTemp => EMAC0CLIENTRXD_OUT(0), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(0), + GlitchData => EMAC0CLIENTRXD0_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(0)", + OutTemp => EMAC0CLIENTRXD_OUT(0), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(0), + GlitchData => EMAC0CLIENTRXD0_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(0)", + OutTemp => EMAC0CLIENTRXD_OUT(0), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(1), + GlitchData => EMAC0CLIENTRXD1_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(1)", + OutTemp => EMAC0CLIENTRXD_OUT(1), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(1), + GlitchData => EMAC0CLIENTRXD1_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(1)", + OutTemp => EMAC0CLIENTRXD_OUT(1), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(1), + GlitchData => EMAC0CLIENTRXD1_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(1)", + OutTemp => EMAC0CLIENTRXD_OUT(1), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(2), + GlitchData => EMAC0CLIENTRXD2_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(2)", + OutTemp => EMAC0CLIENTRXD_OUT(2), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(2), + GlitchData => EMAC0CLIENTRXD2_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(2)", + OutTemp => EMAC0CLIENTRXD_OUT(2), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(2), + GlitchData => EMAC0CLIENTRXD2_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(2)", + OutTemp => EMAC0CLIENTRXD_OUT(2), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(3), + GlitchData => EMAC0CLIENTRXD3_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(3)", + OutTemp => EMAC0CLIENTRXD_OUT(3), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(3), + GlitchData => EMAC0CLIENTRXD3_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(3)", + OutTemp => EMAC0CLIENTRXD_OUT(3), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(3), + GlitchData => EMAC0CLIENTRXD3_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(3)", + OutTemp => EMAC0CLIENTRXD_OUT(3), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(4), + GlitchData => EMAC0CLIENTRXD4_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(4)", + OutTemp => EMAC0CLIENTRXD_OUT(4), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(4), + GlitchData => EMAC0CLIENTRXD4_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(4)", + OutTemp => EMAC0CLIENTRXD_OUT(4), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(4), + GlitchData => EMAC0CLIENTRXD4_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(4)", + OutTemp => EMAC0CLIENTRXD_OUT(4), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(5), + GlitchData => EMAC0CLIENTRXD5_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(5)", + OutTemp => EMAC0CLIENTRXD_OUT(5), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(5), + GlitchData => EMAC0CLIENTRXD5_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(5)", + OutTemp => EMAC0CLIENTRXD_OUT(5), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(5), + GlitchData => EMAC0CLIENTRXD5_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(5)", + OutTemp => EMAC0CLIENTRXD_OUT(5), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(6), + GlitchData => EMAC0CLIENTRXD6_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(6)", + OutTemp => EMAC0CLIENTRXD_OUT(6), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(6), + GlitchData => EMAC0CLIENTRXD6_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(6)", + OutTemp => EMAC0CLIENTRXD_OUT(6), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(6), + GlitchData => EMAC0CLIENTRXD6_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(6)", + OutTemp => EMAC0CLIENTRXD_OUT(6), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(7), + GlitchData => EMAC0CLIENTRXD7_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(7)", + OutTemp => EMAC0CLIENTRXD_OUT(7), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(7), + GlitchData => EMAC0CLIENTRXD7_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(7)", + OutTemp => EMAC0CLIENTRXD_OUT(7), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(7), + GlitchData => EMAC0CLIENTRXD7_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(7)", + OutTemp => EMAC0CLIENTRXD_OUT(7), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(8), + GlitchData => EMAC0CLIENTRXD8_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(8)", + OutTemp => EMAC0CLIENTRXD_OUT(8), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(8), + GlitchData => EMAC0CLIENTRXD8_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(8)", + OutTemp => EMAC0CLIENTRXD_OUT(8), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(8), + GlitchData => EMAC0CLIENTRXD8_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(8)", + OutTemp => EMAC0CLIENTRXD_OUT(8), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(9), + GlitchData => EMAC0CLIENTRXD9_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(9)", + OutTemp => EMAC0CLIENTRXD_OUT(9), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(9), + GlitchData => EMAC0CLIENTRXD9_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(9)", + OutTemp => EMAC0CLIENTRXD_OUT(9), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(9), + GlitchData => EMAC0CLIENTRXD9_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(9)", + OutTemp => EMAC0CLIENTRXD_OUT(9), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(10), + GlitchData => EMAC0CLIENTRXD10_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(10)", + OutTemp => EMAC0CLIENTRXD_OUT(10), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(10), + GlitchData => EMAC0CLIENTRXD10_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(10)", + OutTemp => EMAC0CLIENTRXD_OUT(10), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(10), + GlitchData => EMAC0CLIENTRXD10_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(10)", + OutTemp => EMAC0CLIENTRXD_OUT(10), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(11), + GlitchData => EMAC0CLIENTRXD11_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(11)", + OutTemp => EMAC0CLIENTRXD_OUT(11), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(11), + GlitchData => EMAC0CLIENTRXD11_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(11)", + OutTemp => EMAC0CLIENTRXD_OUT(11), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(11), + GlitchData => EMAC0CLIENTRXD11_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(11)", + OutTemp => EMAC0CLIENTRXD_OUT(11), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(12), + GlitchData => EMAC0CLIENTRXD12_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(12)", + OutTemp => EMAC0CLIENTRXD_OUT(12), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(12), + GlitchData => EMAC0CLIENTRXD12_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(12)", + OutTemp => EMAC0CLIENTRXD_OUT(12), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(12), + GlitchData => EMAC0CLIENTRXD12_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(12)", + OutTemp => EMAC0CLIENTRXD_OUT(12), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(13), + GlitchData => EMAC0CLIENTRXD13_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(13)", + OutTemp => EMAC0CLIENTRXD_OUT(13), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(13), + GlitchData => EMAC0CLIENTRXD13_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(13)", + OutTemp => EMAC0CLIENTRXD_OUT(13), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(13), + GlitchData => EMAC0CLIENTRXD13_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(13)", + OutTemp => EMAC0CLIENTRXD_OUT(13), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(14), + GlitchData => EMAC0CLIENTRXD14_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(14)", + OutTemp => EMAC0CLIENTRXD_OUT(14), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(14), + GlitchData => EMAC0CLIENTRXD14_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(14)", + OutTemp => EMAC0CLIENTRXD_OUT(14), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(14), + GlitchData => EMAC0CLIENTRXD14_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(14)", + OutTemp => EMAC0CLIENTRXD_OUT(14), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(15), + GlitchData => EMAC0CLIENTRXD15_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(15)", + OutTemp => EMAC0CLIENTRXD_OUT(15), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(15), + GlitchData => EMAC0CLIENTRXD15_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(15)", + OutTemp => EMAC0CLIENTRXD_OUT(15), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(15), + GlitchData => EMAC0CLIENTRXD15_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(15)", + OutTemp => EMAC0CLIENTRXD_OUT(15), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXDVLD, + GlitchData => EMAC0CLIENTRXDVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXDVLD", + OutTemp => EMAC0CLIENTRXDVLD_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXDVLD, + GlitchData => EMAC0CLIENTRXDVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXDVLD", + OutTemp => EMAC0CLIENTRXDVLD_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXDVLD, + GlitchData => EMAC0CLIENTRXDVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXDVLD", + OutTemp => EMAC0CLIENTRXDVLD_OUT, + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXDVLDMSW, + GlitchData => EMAC0CLIENTRXDVLDMSW_GlitchData, + OutSignalName => "EMAC0CLIENTRXDVLDMSW", + OutTemp => EMAC0CLIENTRXDVLDMSW_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXDVLDMSW, + GlitchData => EMAC0CLIENTRXDVLDMSW_GlitchData, + OutSignalName => "EMAC0CLIENTRXDVLDMSW", + OutTemp => EMAC0CLIENTRXDVLDMSW_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXDVLDMSW, + GlitchData => EMAC0CLIENTRXDVLDMSW_GlitchData, + OutSignalName => "EMAC0CLIENTRXDVLDMSW", + OutTemp => EMAC0CLIENTRXDVLDMSW_OUT, + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXFRAMEDROP, + GlitchData => EMAC0CLIENTRXFRAMEDROP_GlitchData, + OutSignalName => "EMAC0CLIENTRXFRAMEDROP", + OutTemp => EMAC0CLIENTRXFRAMEDROP_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXFRAMEDROP, + GlitchData => EMAC0CLIENTRXFRAMEDROP_GlitchData, + OutSignalName => "EMAC0CLIENTRXFRAMEDROP", + OutTemp => EMAC0CLIENTRXFRAMEDROP_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXFRAMEDROP, + GlitchData => EMAC0CLIENTRXFRAMEDROP_GlitchData, + OutSignalName => "EMAC0CLIENTRXFRAMEDROP", + OutTemp => EMAC0CLIENTRXFRAMEDROP_OUT, + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXGOODFRAME, + GlitchData => EMAC0CLIENTRXGOODFRAME_GlitchData, + OutSignalName => "EMAC0CLIENTRXGOODFRAME", + OutTemp => EMAC0CLIENTRXGOODFRAME_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXGOODFRAME, + GlitchData => EMAC0CLIENTRXGOODFRAME_GlitchData, + OutSignalName => "EMAC0CLIENTRXGOODFRAME", + OutTemp => EMAC0CLIENTRXGOODFRAME_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXGOODFRAME, + GlitchData => EMAC0CLIENTRXGOODFRAME_GlitchData, + OutSignalName => "EMAC0CLIENTRXGOODFRAME", + OutTemp => EMAC0CLIENTRXGOODFRAME_OUT, + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(0), + GlitchData => EMAC0CLIENTRXSTATS0_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(0)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(0), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(0), + GlitchData => EMAC0CLIENTRXSTATS0_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(0)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(0), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(0), + GlitchData => EMAC0CLIENTRXSTATS0_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(0)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(0), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(1), + GlitchData => EMAC0CLIENTRXSTATS1_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(1)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(1), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(1), + GlitchData => EMAC0CLIENTRXSTATS1_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(1)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(1), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(1), + GlitchData => EMAC0CLIENTRXSTATS1_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(1)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(1), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(2), + GlitchData => EMAC0CLIENTRXSTATS2_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(2)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(2), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(2), + GlitchData => EMAC0CLIENTRXSTATS2_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(2)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(2), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(2), + GlitchData => EMAC0CLIENTRXSTATS2_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(2)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(2), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(3), + GlitchData => EMAC0CLIENTRXSTATS3_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(3)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(3), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(3), + GlitchData => EMAC0CLIENTRXSTATS3_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(3)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(3), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(3), + GlitchData => EMAC0CLIENTRXSTATS3_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(3)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(3), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(4), + GlitchData => EMAC0CLIENTRXSTATS4_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(4)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(4), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(4), + GlitchData => EMAC0CLIENTRXSTATS4_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(4)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(4), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(4), + GlitchData => EMAC0CLIENTRXSTATS4_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(4)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(4), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(5), + GlitchData => EMAC0CLIENTRXSTATS5_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(5)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(5), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(5), + GlitchData => EMAC0CLIENTRXSTATS5_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(5)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(5), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(5), + GlitchData => EMAC0CLIENTRXSTATS5_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(5)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(5), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(6), + GlitchData => EMAC0CLIENTRXSTATS6_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(6)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(6), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(6), + GlitchData => EMAC0CLIENTRXSTATS6_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(6)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(6), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(6), + GlitchData => EMAC0CLIENTRXSTATS6_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(6)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(6), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATSBYTEVLD, + GlitchData => EMAC0CLIENTRXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATSBYTEVLD", + OutTemp => EMAC0CLIENTRXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATSBYTEVLD, + GlitchData => EMAC0CLIENTRXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATSBYTEVLD", + OutTemp => EMAC0CLIENTRXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATSBYTEVLD, + GlitchData => EMAC0CLIENTRXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATSBYTEVLD", + OutTemp => EMAC0CLIENTRXSTATSBYTEVLD_OUT, + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATSVLD, + GlitchData => EMAC0CLIENTRXSTATSVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATSVLD", + OutTemp => EMAC0CLIENTRXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATSVLD, + GlitchData => EMAC0CLIENTRXSTATSVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATSVLD", + OutTemp => EMAC0CLIENTRXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATSVLD, + GlitchData => EMAC0CLIENTRXSTATSVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATSVLD", + OutTemp => EMAC0CLIENTRXSTATSVLD_OUT, + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXACK, + GlitchData => EMAC0CLIENTTXACK_GlitchData, + OutSignalName => "EMAC0CLIENTTXACK", + OutTemp => EMAC0CLIENTTXACK_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXACK, + GlitchData => EMAC0CLIENTTXACK_GlitchData, + OutSignalName => "EMAC0CLIENTTXACK", + OutTemp => EMAC0CLIENTTXACK_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXACK, + GlitchData => EMAC0CLIENTTXACK_GlitchData, + OutSignalName => "EMAC0CLIENTTXACK", + OutTemp => EMAC0CLIENTTXACK_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXCLIENTCLKOUT, + GlitchData => EMAC0CLIENTTXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC0CLIENTTXCLIENTCLKOUT", + OutTemp => EMAC0CLIENTTXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXCLIENTCLKOUT, + GlitchData => EMAC0CLIENTTXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC0CLIENTTXCLIENTCLKOUT", + OutTemp => EMAC0CLIENTTXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC0MIITXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXCLIENTCLKOUT, + GlitchData => EMAC0CLIENTTXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC0CLIENTTXCLIENTCLKOUT", + OutTemp => EMAC0CLIENTTXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXCOLLISION, + GlitchData => EMAC0CLIENTTXCOLLISION_GlitchData, + OutSignalName => "EMAC0CLIENTTXCOLLISION", + OutTemp => EMAC0CLIENTTXCOLLISION_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXCOLLISION, + GlitchData => EMAC0CLIENTTXCOLLISION_GlitchData, + OutSignalName => "EMAC0CLIENTTXCOLLISION", + OutTemp => EMAC0CLIENTTXCOLLISION_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXCOLLISION, + GlitchData => EMAC0CLIENTTXCOLLISION_GlitchData, + OutSignalName => "EMAC0CLIENTTXCOLLISION", + OutTemp => EMAC0CLIENTTXCOLLISION_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXGMIIMIICLKOUT, + GlitchData => EMAC0PHYTXGMIIMIICLKOUT_GlitchData, + OutSignalName => "EMAC0PHYTXGMIIMIICLKOUT", + OutTemp => EMAC0PHYTXGMIIMIICLKOUT_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXGMIIMIICLKOUT, + GlitchData => EMAC0PHYTXGMIIMIICLKOUT_GlitchData, + OutSignalName => "EMAC0PHYTXGMIIMIICLKOUT", + OutTemp => EMAC0PHYTXGMIIMIICLKOUT_OUT, + Paths => (0 => (PHYEMAC0MIITXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXRETRANSMIT, + GlitchData => EMAC0CLIENTTXRETRANSMIT_GlitchData, + OutSignalName => "EMAC0CLIENTTXRETRANSMIT", + OutTemp => EMAC0CLIENTTXRETRANSMIT_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXRETRANSMIT, + GlitchData => EMAC0CLIENTTXRETRANSMIT_GlitchData, + OutSignalName => "EMAC0CLIENTTXRETRANSMIT", + OutTemp => EMAC0CLIENTTXRETRANSMIT_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXRETRANSMIT, + GlitchData => EMAC0CLIENTTXRETRANSMIT_GlitchData, + OutSignalName => "EMAC0CLIENTTXRETRANSMIT", + OutTemp => EMAC0CLIENTTXRETRANSMIT_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATS, + GlitchData => EMAC0CLIENTTXSTATS_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATS", + OutTemp => EMAC0CLIENTTXSTATS_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATS, + GlitchData => EMAC0CLIENTTXSTATS_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATS", + OutTemp => EMAC0CLIENTTXSTATS_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATS, + GlitchData => EMAC0CLIENTTXSTATS_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATS", + OutTemp => EMAC0CLIENTTXSTATS_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATSBYTEVLD, + GlitchData => EMAC0CLIENTTXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATSBYTEVLD", + OutTemp => EMAC0CLIENTTXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATSBYTEVLD, + GlitchData => EMAC0CLIENTTXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATSBYTEVLD", + OutTemp => EMAC0CLIENTTXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATSBYTEVLD, + GlitchData => EMAC0CLIENTTXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATSBYTEVLD", + OutTemp => EMAC0CLIENTTXSTATSBYTEVLD_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATSVLD, + GlitchData => EMAC0CLIENTTXSTATSVLD_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATSVLD", + OutTemp => EMAC0CLIENTTXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATSVLD, + GlitchData => EMAC0CLIENTTXSTATSVLD_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATSVLD", + OutTemp => EMAC0CLIENTTXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATSVLD, + GlitchData => EMAC0CLIENTTXSTATSVLD_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATSVLD", + OutTemp => EMAC0CLIENTTXSTATSVLD_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYENCOMMAALIGN, + GlitchData => EMAC0PHYENCOMMAALIGN_GlitchData, + OutSignalName => "EMAC0PHYENCOMMAALIGN", + OutTemp => EMAC0PHYENCOMMAALIGN_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYLOOPBACKMSB, + GlitchData => EMAC0PHYLOOPBACKMSB_GlitchData, + OutSignalName => "EMAC0PHYLOOPBACKMSB", + OutTemp => EMAC0PHYLOOPBACKMSB_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMCLKOUT, + GlitchData => EMAC0PHYMCLKOUT_GlitchData, + OutSignalName => "EMAC0PHYMCLKOUT", + OutTemp => EMAC0PHYMCLKOUT_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMCLKOUT, + GlitchData => EMAC0PHYMCLKOUT_GlitchData, + OutSignalName => "EMAC0PHYMCLKOUT", + OutTemp => EMAC0PHYMCLKOUT_OUT, + Paths => (0 => (PHYEMAC0MCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMDOUT, + GlitchData => EMAC0PHYMDOUT_GlitchData, + OutSignalName => "EMAC0PHYMDOUT", + OutTemp => EMAC0PHYMDOUT_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMDOUT, + GlitchData => EMAC0PHYMDOUT_GlitchData, + OutSignalName => "EMAC0PHYMDOUT", + OutTemp => EMAC0PHYMDOUT_OUT, + Paths => (0 => (PHYEMAC0MCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMDTRI, + GlitchData => EMAC0PHYMDTRI_GlitchData, + OutSignalName => "EMAC0PHYMDTRI", + OutTemp => EMAC0PHYMDTRI_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMDTRI, + GlitchData => EMAC0PHYMDTRI_GlitchData, + OutSignalName => "EMAC0PHYMDTRI", + OutTemp => EMAC0PHYMDTRI_OUT, + Paths => (0 => (PHYEMAC0MCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMGTRXRESET, + GlitchData => EMAC0PHYMGTRXRESET_GlitchData, + OutSignalName => "EMAC0PHYMGTRXRESET", + OutTemp => EMAC0PHYMGTRXRESET_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMGTTXRESET, + GlitchData => EMAC0PHYMGTTXRESET_GlitchData, + OutSignalName => "EMAC0PHYMGTTXRESET", + OutTemp => EMAC0PHYMGTTXRESET_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYPOWERDOWN, + GlitchData => EMAC0PHYPOWERDOWN_GlitchData, + OutSignalName => "EMAC0PHYPOWERDOWN", + OutTemp => EMAC0PHYPOWERDOWN_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYSYNCACQSTATUS, + GlitchData => EMAC0PHYSYNCACQSTATUS_GlitchData, + OutSignalName => "EMAC0PHYSYNCACQSTATUS", + OutTemp => EMAC0PHYSYNCACQSTATUS_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYSYNCACQSTATUS, + GlitchData => EMAC0PHYSYNCACQSTATUS_GlitchData, + OutSignalName => "EMAC0PHYSYNCACQSTATUS", + OutTemp => EMAC0PHYSYNCACQSTATUS_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYSYNCACQSTATUS, + GlitchData => EMAC0PHYSYNCACQSTATUS_GlitchData, + OutSignalName => "EMAC0PHYSYNCACQSTATUS", + OutTemp => EMAC0PHYSYNCACQSTATUS_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARDISPMODE, + GlitchData => EMAC0PHYTXCHARDISPMODE_GlitchData, + OutSignalName => "EMAC0PHYTXCHARDISPMODE", + OutTemp => EMAC0PHYTXCHARDISPMODE_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARDISPMODE, + GlitchData => EMAC0PHYTXCHARDISPMODE_GlitchData, + OutSignalName => "EMAC0PHYTXCHARDISPMODE", + OutTemp => EMAC0PHYTXCHARDISPMODE_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARDISPMODE, + GlitchData => EMAC0PHYTXCHARDISPMODE_GlitchData, + OutSignalName => "EMAC0PHYTXCHARDISPMODE", + OutTemp => EMAC0PHYTXCHARDISPMODE_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARDISPVAL, + GlitchData => EMAC0PHYTXCHARDISPVAL_GlitchData, + OutSignalName => "EMAC0PHYTXCHARDISPVAL", + OutTemp => EMAC0PHYTXCHARDISPVAL_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARDISPVAL, + GlitchData => EMAC0PHYTXCHARDISPVAL_GlitchData, + OutSignalName => "EMAC0PHYTXCHARDISPVAL", + OutTemp => EMAC0PHYTXCHARDISPVAL_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARDISPVAL, + GlitchData => EMAC0PHYTXCHARDISPVAL_GlitchData, + OutSignalName => "EMAC0PHYTXCHARDISPVAL", + OutTemp => EMAC0PHYTXCHARDISPVAL_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARISK, + GlitchData => EMAC0PHYTXCHARISK_GlitchData, + OutSignalName => "EMAC0PHYTXCHARISK", + OutTemp => EMAC0PHYTXCHARISK_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARISK, + GlitchData => EMAC0PHYTXCHARISK_GlitchData, + OutSignalName => "EMAC0PHYTXCHARISK", + OutTemp => EMAC0PHYTXCHARISK_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARISK, + GlitchData => EMAC0PHYTXCHARISK_GlitchData, + OutSignalName => "EMAC0PHYTXCHARISK", + OutTemp => EMAC0PHYTXCHARISK_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCLK, + GlitchData => EMAC0PHYTXCLK_GlitchData, + OutSignalName => "EMAC0PHYTXCLK", + OutTemp => EMAC0PHYTXCLK_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCLK, + GlitchData => EMAC0PHYTXCLK_GlitchData, + OutSignalName => "EMAC0PHYTXCLK", + OutTemp => EMAC0PHYTXCLK_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCLK, + GlitchData => EMAC0PHYTXCLK_GlitchData, + OutSignalName => "EMAC0PHYTXCLK", + OutTemp => EMAC0PHYTXCLK_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(0), + GlitchData => EMAC0PHYTXD0_GlitchData, + OutSignalName => "EMAC0PHYTXD(0)", + OutTemp => EMAC0PHYTXD_OUT(0), + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(0), + GlitchData => EMAC0PHYTXD0_GlitchData, + OutSignalName => "EMAC0PHYTXD(0)", + OutTemp => EMAC0PHYTXD_OUT(0), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(0), + GlitchData => EMAC0PHYTXD0_GlitchData, + OutSignalName => "EMAC0PHYTXD(0)", + OutTemp => EMAC0PHYTXD_OUT(0), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(1), + GlitchData => EMAC0PHYTXD1_GlitchData, + OutSignalName => "EMAC0PHYTXD(1)", + OutTemp => EMAC0PHYTXD_OUT(1), + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(1), + GlitchData => EMAC0PHYTXD1_GlitchData, + OutSignalName => "EMAC0PHYTXD(1)", + OutTemp => EMAC0PHYTXD_OUT(1), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(1), + GlitchData => EMAC0PHYTXD1_GlitchData, + OutSignalName => "EMAC0PHYTXD(1)", + OutTemp => EMAC0PHYTXD_OUT(1), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(2), + GlitchData => EMAC0PHYTXD2_GlitchData, + OutSignalName => "EMAC0PHYTXD(2)", + OutTemp => EMAC0PHYTXD_OUT(2), + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(2), + GlitchData => EMAC0PHYTXD2_GlitchData, + OutSignalName => "EMAC0PHYTXD(2)", + OutTemp => EMAC0PHYTXD_OUT(2), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(2), + GlitchData => EMAC0PHYTXD2_GlitchData, + OutSignalName => "EMAC0PHYTXD(2)", + OutTemp => EMAC0PHYTXD_OUT(2), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(3), + GlitchData => EMAC0PHYTXD3_GlitchData, + OutSignalName => "EMAC0PHYTXD(3)", + OutTemp => EMAC0PHYTXD_OUT(3), + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(3), + GlitchData => EMAC0PHYTXD3_GlitchData, + OutSignalName => "EMAC0PHYTXD(3)", + OutTemp => EMAC0PHYTXD_OUT(3), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(3), + GlitchData => EMAC0PHYTXD3_GlitchData, + OutSignalName => "EMAC0PHYTXD(3)", + OutTemp => EMAC0PHYTXD_OUT(3), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(4), + GlitchData => EMAC0PHYTXD4_GlitchData, + OutSignalName => "EMAC0PHYTXD(4)", + OutTemp => EMAC0PHYTXD_OUT(4), + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(4), + GlitchData => EMAC0PHYTXD4_GlitchData, + OutSignalName => "EMAC0PHYTXD(4)", + OutTemp => EMAC0PHYTXD_OUT(4), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(4), + GlitchData => EMAC0PHYTXD4_GlitchData, + OutSignalName => "EMAC0PHYTXD(4)", + OutTemp => EMAC0PHYTXD_OUT(4), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(4), + GlitchData => EMAC0PHYTXD4_GlitchData, + OutSignalName => "EMAC0PHYTXD(4)", + OutTemp => EMAC0PHYTXD_OUT(4), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(5), + GlitchData => EMAC0PHYTXD5_GlitchData, + OutSignalName => "EMAC0PHYTXD(5)", + OutTemp => EMAC0PHYTXD_OUT(5), + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(5), + GlitchData => EMAC0PHYTXD5_GlitchData, + OutSignalName => "EMAC0PHYTXD(5)", + OutTemp => EMAC0PHYTXD_OUT(5), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(5), + GlitchData => EMAC0PHYTXD5_GlitchData, + OutSignalName => "EMAC0PHYTXD(5)", + OutTemp => EMAC0PHYTXD_OUT(5), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(5), + GlitchData => EMAC0PHYTXD5_GlitchData, + OutSignalName => "EMAC0PHYTXD(5)", + OutTemp => EMAC0PHYTXD_OUT(5), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(6), + GlitchData => EMAC0PHYTXD6_GlitchData, + OutSignalName => "EMAC0PHYTXD(6)", + OutTemp => EMAC0PHYTXD_OUT(6), + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(6), + GlitchData => EMAC0PHYTXD6_GlitchData, + OutSignalName => "EMAC0PHYTXD(6)", + OutTemp => EMAC0PHYTXD_OUT(6), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(6), + GlitchData => EMAC0PHYTXD6_GlitchData, + OutSignalName => "EMAC0PHYTXD(6)", + OutTemp => EMAC0PHYTXD_OUT(6), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(6), + GlitchData => EMAC0PHYTXD6_GlitchData, + OutSignalName => "EMAC0PHYTXD(6)", + OutTemp => EMAC0PHYTXD_OUT(6), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(7), + GlitchData => EMAC0PHYTXD7_GlitchData, + OutSignalName => "EMAC0PHYTXD(7)", + OutTemp => EMAC0PHYTXD_OUT(7), + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(7), + GlitchData => EMAC0PHYTXD7_GlitchData, + OutSignalName => "EMAC0PHYTXD(7)", + OutTemp => EMAC0PHYTXD_OUT(7), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(7), + GlitchData => EMAC0PHYTXD7_GlitchData, + OutSignalName => "EMAC0PHYTXD(7)", + OutTemp => EMAC0PHYTXD_OUT(7), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(7), + GlitchData => EMAC0PHYTXD7_GlitchData, + OutSignalName => "EMAC0PHYTXD(7)", + OutTemp => EMAC0PHYTXD_OUT(7), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXEN, + GlitchData => EMAC0PHYTXEN_GlitchData, + OutSignalName => "EMAC0PHYTXEN", + OutTemp => EMAC0PHYTXEN_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXEN, + GlitchData => EMAC0PHYTXEN_GlitchData, + OutSignalName => "EMAC0PHYTXEN", + OutTemp => EMAC0PHYTXEN_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXEN, + GlitchData => EMAC0PHYTXEN_GlitchData, + OutSignalName => "EMAC0PHYTXEN", + OutTemp => EMAC0PHYTXEN_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXER, + GlitchData => EMAC0PHYTXER_GlitchData, + OutSignalName => "EMAC0PHYTXER", + OutTemp => EMAC0PHYTXER_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXER, + GlitchData => EMAC0PHYTXER_GlitchData, + OutSignalName => "EMAC0PHYTXER", + OutTemp => EMAC0PHYTXER_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXER, + GlitchData => EMAC0PHYTXER_GlitchData, + OutSignalName => "EMAC0PHYTXER", + OutTemp => EMAC0PHYTXER_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXER, + GlitchData => EMAC0PHYTXER_GlitchData, + OutSignalName => "EMAC0PHYTXER", + OutTemp => EMAC0PHYTXER_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0SPEEDIS10100, + GlitchData => EMAC0SPEEDIS10100_GlitchData, + OutSignalName => "EMAC0SPEEDIS10100", + OutTemp => EMAC0SPEEDIS10100_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTANINTERRUPT, + GlitchData => EMAC1CLIENTANINTERRUPT_GlitchData, + OutSignalName => "EMAC1CLIENTANINTERRUPT", + OutTemp => EMAC1CLIENTANINTERRUPT_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXBADFRAME, + GlitchData => EMAC1CLIENTRXBADFRAME_GlitchData, + OutSignalName => "EMAC1CLIENTRXBADFRAME", + OutTemp => EMAC1CLIENTRXBADFRAME_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXBADFRAME, + GlitchData => EMAC1CLIENTRXBADFRAME_GlitchData, + OutSignalName => "EMAC1CLIENTRXBADFRAME", + OutTemp => EMAC1CLIENTRXBADFRAME_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXBADFRAME, + GlitchData => EMAC1CLIENTRXBADFRAME_GlitchData, + OutSignalName => "EMAC1CLIENTRXBADFRAME", + OutTemp => EMAC1CLIENTRXBADFRAME_OUT, + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXCLIENTCLKOUT, + GlitchData => EMAC1CLIENTRXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC1CLIENTRXCLIENTCLKOUT", + OutTemp => EMAC1CLIENTRXCLIENTCLKOUT_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXCLIENTCLKOUT, + GlitchData => EMAC1CLIENTRXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC1CLIENTRXCLIENTCLKOUT", + OutTemp => EMAC1CLIENTRXCLIENTCLKOUT_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXCLIENTCLKOUT, + GlitchData => EMAC1CLIENTRXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC1CLIENTRXCLIENTCLKOUT", + OutTemp => EMAC1CLIENTRXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXCLIENTCLKOUT, + GlitchData => EMAC1CLIENTRXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC1CLIENTRXCLIENTCLKOUT", + OutTemp => EMAC1CLIENTRXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(0), + GlitchData => EMAC1CLIENTRXD0_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(0)", + OutTemp => EMAC1CLIENTRXD_OUT(0), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(0), + GlitchData => EMAC1CLIENTRXD0_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(0)", + OutTemp => EMAC1CLIENTRXD_OUT(0), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(0), + GlitchData => EMAC1CLIENTRXD0_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(0)", + OutTemp => EMAC1CLIENTRXD_OUT(0), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(1), + GlitchData => EMAC1CLIENTRXD1_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(1)", + OutTemp => EMAC1CLIENTRXD_OUT(1), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(1), + GlitchData => EMAC1CLIENTRXD1_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(1)", + OutTemp => EMAC1CLIENTRXD_OUT(1), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(1), + GlitchData => EMAC1CLIENTRXD1_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(1)", + OutTemp => EMAC1CLIENTRXD_OUT(1), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(2), + GlitchData => EMAC1CLIENTRXD2_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(2)", + OutTemp => EMAC1CLIENTRXD_OUT(2), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(2), + GlitchData => EMAC1CLIENTRXD2_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(2)", + OutTemp => EMAC1CLIENTRXD_OUT(2), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(2), + GlitchData => EMAC1CLIENTRXD2_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(2)", + OutTemp => EMAC1CLIENTRXD_OUT(2), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(3), + GlitchData => EMAC1CLIENTRXD3_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(3)", + OutTemp => EMAC1CLIENTRXD_OUT(3), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(3), + GlitchData => EMAC1CLIENTRXD3_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(3)", + OutTemp => EMAC1CLIENTRXD_OUT(3), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(3), + GlitchData => EMAC1CLIENTRXD3_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(3)", + OutTemp => EMAC1CLIENTRXD_OUT(3), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(4), + GlitchData => EMAC1CLIENTRXD4_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(4)", + OutTemp => EMAC1CLIENTRXD_OUT(4), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(4), + GlitchData => EMAC1CLIENTRXD4_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(4)", + OutTemp => EMAC1CLIENTRXD_OUT(4), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(4), + GlitchData => EMAC1CLIENTRXD4_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(4)", + OutTemp => EMAC1CLIENTRXD_OUT(4), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(5), + GlitchData => EMAC1CLIENTRXD5_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(5)", + OutTemp => EMAC1CLIENTRXD_OUT(5), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(5), + GlitchData => EMAC1CLIENTRXD5_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(5)", + OutTemp => EMAC1CLIENTRXD_OUT(5), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(5), + GlitchData => EMAC1CLIENTRXD5_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(5)", + OutTemp => EMAC1CLIENTRXD_OUT(5), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(6), + GlitchData => EMAC1CLIENTRXD6_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(6)", + OutTemp => EMAC1CLIENTRXD_OUT(6), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(6), + GlitchData => EMAC1CLIENTRXD6_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(6)", + OutTemp => EMAC1CLIENTRXD_OUT(6), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(6), + GlitchData => EMAC1CLIENTRXD6_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(6)", + OutTemp => EMAC1CLIENTRXD_OUT(6), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(7), + GlitchData => EMAC1CLIENTRXD7_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(7)", + OutTemp => EMAC1CLIENTRXD_OUT(7), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(7), + GlitchData => EMAC1CLIENTRXD7_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(7)", + OutTemp => EMAC1CLIENTRXD_OUT(7), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(7), + GlitchData => EMAC1CLIENTRXD7_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(7)", + OutTemp => EMAC1CLIENTRXD_OUT(7), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(8), + GlitchData => EMAC1CLIENTRXD8_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(8)", + OutTemp => EMAC1CLIENTRXD_OUT(8), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(8), + GlitchData => EMAC1CLIENTRXD8_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(8)", + OutTemp => EMAC1CLIENTRXD_OUT(8), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(8), + GlitchData => EMAC1CLIENTRXD8_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(8)", + OutTemp => EMAC1CLIENTRXD_OUT(8), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(9), + GlitchData => EMAC1CLIENTRXD9_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(9)", + OutTemp => EMAC1CLIENTRXD_OUT(9), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(9), + GlitchData => EMAC1CLIENTRXD9_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(9)", + OutTemp => EMAC1CLIENTRXD_OUT(9), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(9), + GlitchData => EMAC1CLIENTRXD9_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(9)", + OutTemp => EMAC1CLIENTRXD_OUT(9), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(10), + GlitchData => EMAC1CLIENTRXD10_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(10)", + OutTemp => EMAC1CLIENTRXD_OUT(10), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(10), + GlitchData => EMAC1CLIENTRXD10_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(10)", + OutTemp => EMAC1CLIENTRXD_OUT(10), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(10), + GlitchData => EMAC1CLIENTRXD10_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(10)", + OutTemp => EMAC1CLIENTRXD_OUT(10), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(11), + GlitchData => EMAC1CLIENTRXD11_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(11)", + OutTemp => EMAC1CLIENTRXD_OUT(11), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(11), + GlitchData => EMAC1CLIENTRXD11_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(11)", + OutTemp => EMAC1CLIENTRXD_OUT(11), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(11), + GlitchData => EMAC1CLIENTRXD11_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(11)", + OutTemp => EMAC1CLIENTRXD_OUT(11), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(12), + GlitchData => EMAC1CLIENTRXD12_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(12)", + OutTemp => EMAC1CLIENTRXD_OUT(12), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(12), + GlitchData => EMAC1CLIENTRXD12_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(12)", + OutTemp => EMAC1CLIENTRXD_OUT(12), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(12), + GlitchData => EMAC1CLIENTRXD12_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(12)", + OutTemp => EMAC1CLIENTRXD_OUT(12), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(13), + GlitchData => EMAC1CLIENTRXD13_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(13)", + OutTemp => EMAC1CLIENTRXD_OUT(13), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(13), + GlitchData => EMAC1CLIENTRXD13_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(13)", + OutTemp => EMAC1CLIENTRXD_OUT(13), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(13), + GlitchData => EMAC1CLIENTRXD13_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(13)", + OutTemp => EMAC1CLIENTRXD_OUT(13), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(14), + GlitchData => EMAC1CLIENTRXD14_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(14)", + OutTemp => EMAC1CLIENTRXD_OUT(14), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(14), + GlitchData => EMAC1CLIENTRXD14_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(14)", + OutTemp => EMAC1CLIENTRXD_OUT(14), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(14), + GlitchData => EMAC1CLIENTRXD14_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(14)", + OutTemp => EMAC1CLIENTRXD_OUT(14), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(15), + GlitchData => EMAC1CLIENTRXD15_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(15)", + OutTemp => EMAC1CLIENTRXD_OUT(15), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(15), + GlitchData => EMAC1CLIENTRXD15_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(15)", + OutTemp => EMAC1CLIENTRXD_OUT(15), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(15), + GlitchData => EMAC1CLIENTRXD15_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(15)", + OutTemp => EMAC1CLIENTRXD_OUT(15), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXDVLD, + GlitchData => EMAC1CLIENTRXDVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXDVLD", + OutTemp => EMAC1CLIENTRXDVLD_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXDVLD, + GlitchData => EMAC1CLIENTRXDVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXDVLD", + OutTemp => EMAC1CLIENTRXDVLD_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXDVLD, + GlitchData => EMAC1CLIENTRXDVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXDVLD", + OutTemp => EMAC1CLIENTRXDVLD_OUT, + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXDVLDMSW, + GlitchData => EMAC1CLIENTRXDVLDMSW_GlitchData, + OutSignalName => "EMAC1CLIENTRXDVLDMSW", + OutTemp => EMAC1CLIENTRXDVLDMSW_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXDVLDMSW, + GlitchData => EMAC1CLIENTRXDVLDMSW_GlitchData, + OutSignalName => "EMAC1CLIENTRXDVLDMSW", + OutTemp => EMAC1CLIENTRXDVLDMSW_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXDVLDMSW, + GlitchData => EMAC1CLIENTRXDVLDMSW_GlitchData, + OutSignalName => "EMAC1CLIENTRXDVLDMSW", + OutTemp => EMAC1CLIENTRXDVLDMSW_OUT, + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXFRAMEDROP, + GlitchData => EMAC1CLIENTRXFRAMEDROP_GlitchData, + OutSignalName => "EMAC1CLIENTRXFRAMEDROP", + OutTemp => EMAC1CLIENTRXFRAMEDROP_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXFRAMEDROP, + GlitchData => EMAC1CLIENTRXFRAMEDROP_GlitchData, + OutSignalName => "EMAC1CLIENTRXFRAMEDROP", + OutTemp => EMAC1CLIENTRXFRAMEDROP_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXFRAMEDROP, + GlitchData => EMAC1CLIENTRXFRAMEDROP_GlitchData, + OutSignalName => "EMAC1CLIENTRXFRAMEDROP", + OutTemp => EMAC1CLIENTRXFRAMEDROP_OUT, + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXGOODFRAME, + GlitchData => EMAC1CLIENTRXGOODFRAME_GlitchData, + OutSignalName => "EMAC1CLIENTRXGOODFRAME", + OutTemp => EMAC1CLIENTRXGOODFRAME_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXGOODFRAME, + GlitchData => EMAC1CLIENTRXGOODFRAME_GlitchData, + OutSignalName => "EMAC1CLIENTRXGOODFRAME", + OutTemp => EMAC1CLIENTRXGOODFRAME_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXGOODFRAME, + GlitchData => EMAC1CLIENTRXGOODFRAME_GlitchData, + OutSignalName => "EMAC1CLIENTRXGOODFRAME", + OutTemp => EMAC1CLIENTRXGOODFRAME_OUT, + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(0), + GlitchData => EMAC1CLIENTRXSTATS0_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(0)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(0), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(0), + GlitchData => EMAC1CLIENTRXSTATS0_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(0)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(0), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(0), + GlitchData => EMAC1CLIENTRXSTATS0_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(0)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(0), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(1), + GlitchData => EMAC1CLIENTRXSTATS1_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(1)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(1), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(1), + GlitchData => EMAC1CLIENTRXSTATS1_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(1)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(1), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(1), + GlitchData => EMAC1CLIENTRXSTATS1_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(1)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(1), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(2), + GlitchData => EMAC1CLIENTRXSTATS2_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(2)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(2), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(2), + GlitchData => EMAC1CLIENTRXSTATS2_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(2)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(2), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(2), + GlitchData => EMAC1CLIENTRXSTATS2_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(2)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(2), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(3), + GlitchData => EMAC1CLIENTRXSTATS3_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(3)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(3), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(3), + GlitchData => EMAC1CLIENTRXSTATS3_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(3)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(3), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(3), + GlitchData => EMAC1CLIENTRXSTATS3_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(3)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(3), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(4), + GlitchData => EMAC1CLIENTRXSTATS4_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(4)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(4), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(4), + GlitchData => EMAC1CLIENTRXSTATS4_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(4)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(4), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(4), + GlitchData => EMAC1CLIENTRXSTATS4_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(4)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(4), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(5), + GlitchData => EMAC1CLIENTRXSTATS5_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(5)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(5), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(5), + GlitchData => EMAC1CLIENTRXSTATS5_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(5)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(5), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(5), + GlitchData => EMAC1CLIENTRXSTATS5_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(5)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(5), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(6), + GlitchData => EMAC1CLIENTRXSTATS6_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(6)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(6), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(6), + GlitchData => EMAC1CLIENTRXSTATS6_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(6)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(6), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(6), + GlitchData => EMAC1CLIENTRXSTATS6_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(6)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(6), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATSBYTEVLD, + GlitchData => EMAC1CLIENTRXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATSBYTEVLD", + OutTemp => EMAC1CLIENTRXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATSBYTEVLD, + GlitchData => EMAC1CLIENTRXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATSBYTEVLD", + OutTemp => EMAC1CLIENTRXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATSBYTEVLD, + GlitchData => EMAC1CLIENTRXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATSBYTEVLD", + OutTemp => EMAC1CLIENTRXSTATSBYTEVLD_OUT, + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATSVLD, + GlitchData => EMAC1CLIENTRXSTATSVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATSVLD", + OutTemp => EMAC1CLIENTRXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATSVLD, + GlitchData => EMAC1CLIENTRXSTATSVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATSVLD", + OutTemp => EMAC1CLIENTRXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATSVLD, + GlitchData => EMAC1CLIENTRXSTATSVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATSVLD", + OutTemp => EMAC1CLIENTRXSTATSVLD_OUT, + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXACK, + GlitchData => EMAC1CLIENTTXACK_GlitchData, + OutSignalName => "EMAC1CLIENTTXACK", + OutTemp => EMAC1CLIENTTXACK_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXACK, + GlitchData => EMAC1CLIENTTXACK_GlitchData, + OutSignalName => "EMAC1CLIENTTXACK", + OutTemp => EMAC1CLIENTTXACK_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXACK, + GlitchData => EMAC1CLIENTTXACK_GlitchData, + OutSignalName => "EMAC1CLIENTTXACK", + OutTemp => EMAC1CLIENTTXACK_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXCLIENTCLKOUT, + GlitchData => EMAC1CLIENTTXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC1CLIENTTXCLIENTCLKOUT", + OutTemp => EMAC1CLIENTTXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXCLIENTCLKOUT, + GlitchData => EMAC1CLIENTTXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC1CLIENTTXCLIENTCLKOUT", + OutTemp => EMAC1CLIENTTXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC1MIITXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXCLIENTCLKOUT, + GlitchData => EMAC1CLIENTTXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC1CLIENTTXCLIENTCLKOUT", + OutTemp => EMAC1CLIENTTXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXCOLLISION, + GlitchData => EMAC1CLIENTTXCOLLISION_GlitchData, + OutSignalName => "EMAC1CLIENTTXCOLLISION", + OutTemp => EMAC1CLIENTTXCOLLISION_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXCOLLISION, + GlitchData => EMAC1CLIENTTXCOLLISION_GlitchData, + OutSignalName => "EMAC1CLIENTTXCOLLISION", + OutTemp => EMAC1CLIENTTXCOLLISION_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXCOLLISION, + GlitchData => EMAC1CLIENTTXCOLLISION_GlitchData, + OutSignalName => "EMAC1CLIENTTXCOLLISION", + OutTemp => EMAC1CLIENTTXCOLLISION_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXGMIIMIICLKOUT, + GlitchData => EMAC1PHYTXGMIIMIICLKOUT_GlitchData, + OutSignalName => "EMAC1PHYTXGMIIMIICLKOUT", + OutTemp => EMAC1PHYTXGMIIMIICLKOUT_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXGMIIMIICLKOUT, + GlitchData => EMAC1PHYTXGMIIMIICLKOUT_GlitchData, + OutSignalName => "EMAC1PHYTXGMIIMIICLKOUT", + OutTemp => EMAC1PHYTXGMIIMIICLKOUT_OUT, + Paths => (0 => (PHYEMAC1MIITXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXRETRANSMIT, + GlitchData => EMAC1CLIENTTXRETRANSMIT_GlitchData, + OutSignalName => "EMAC1CLIENTTXRETRANSMIT", + OutTemp => EMAC1CLIENTTXRETRANSMIT_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXRETRANSMIT, + GlitchData => EMAC1CLIENTTXRETRANSMIT_GlitchData, + OutSignalName => "EMAC1CLIENTTXRETRANSMIT", + OutTemp => EMAC1CLIENTTXRETRANSMIT_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXRETRANSMIT, + GlitchData => EMAC1CLIENTTXRETRANSMIT_GlitchData, + OutSignalName => "EMAC1CLIENTTXRETRANSMIT", + OutTemp => EMAC1CLIENTTXRETRANSMIT_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATS, + GlitchData => EMAC1CLIENTTXSTATS_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATS", + OutTemp => EMAC1CLIENTTXSTATS_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATS, + GlitchData => EMAC1CLIENTTXSTATS_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATS", + OutTemp => EMAC1CLIENTTXSTATS_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATS, + GlitchData => EMAC1CLIENTTXSTATS_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATS", + OutTemp => EMAC1CLIENTTXSTATS_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATSBYTEVLD, + GlitchData => EMAC1CLIENTTXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATSBYTEVLD", + OutTemp => EMAC1CLIENTTXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATSBYTEVLD, + GlitchData => EMAC1CLIENTTXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATSBYTEVLD", + OutTemp => EMAC1CLIENTTXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATSBYTEVLD, + GlitchData => EMAC1CLIENTTXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATSBYTEVLD", + OutTemp => EMAC1CLIENTTXSTATSBYTEVLD_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATSVLD, + GlitchData => EMAC1CLIENTTXSTATSVLD_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATSVLD", + OutTemp => EMAC1CLIENTTXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATSVLD, + GlitchData => EMAC1CLIENTTXSTATSVLD_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATSVLD", + OutTemp => EMAC1CLIENTTXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATSVLD, + GlitchData => EMAC1CLIENTTXSTATSVLD_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATSVLD", + OutTemp => EMAC1CLIENTTXSTATSVLD_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYENCOMMAALIGN, + GlitchData => EMAC1PHYENCOMMAALIGN_GlitchData, + OutSignalName => "EMAC1PHYENCOMMAALIGN", + OutTemp => EMAC1PHYENCOMMAALIGN_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYLOOPBACKMSB, + GlitchData => EMAC1PHYLOOPBACKMSB_GlitchData, + OutSignalName => "EMAC1PHYLOOPBACKMSB", + OutTemp => EMAC1PHYLOOPBACKMSB_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMCLKOUT, + GlitchData => EMAC1PHYMCLKOUT_GlitchData, + OutSignalName => "EMAC1PHYMCLKOUT", + OutTemp => EMAC1PHYMCLKOUT_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMCLKOUT, + GlitchData => EMAC1PHYMCLKOUT_GlitchData, + OutSignalName => "EMAC1PHYMCLKOUT", + OutTemp => EMAC1PHYMCLKOUT_OUT, + Paths => (0 => (PHYEMAC1MCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMDOUT, + GlitchData => EMAC1PHYMDOUT_GlitchData, + OutSignalName => "EMAC1PHYMDOUT", + OutTemp => EMAC1PHYMDOUT_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMDOUT, + GlitchData => EMAC1PHYMDOUT_GlitchData, + OutSignalName => "EMAC1PHYMDOUT", + OutTemp => EMAC1PHYMDOUT_OUT, + Paths => (0 => (PHYEMAC1MCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMDTRI, + GlitchData => EMAC1PHYMDTRI_GlitchData, + OutSignalName => "EMAC1PHYMDTRI", + OutTemp => EMAC1PHYMDTRI_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMDTRI, + GlitchData => EMAC1PHYMDTRI_GlitchData, + OutSignalName => "EMAC1PHYMDTRI", + OutTemp => EMAC1PHYMDTRI_OUT, + Paths => (0 => (PHYEMAC1MCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMGTRXRESET, + GlitchData => EMAC1PHYMGTRXRESET_GlitchData, + OutSignalName => "EMAC1PHYMGTRXRESET", + OutTemp => EMAC1PHYMGTRXRESET_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMGTTXRESET, + GlitchData => EMAC1PHYMGTTXRESET_GlitchData, + OutSignalName => "EMAC1PHYMGTTXRESET", + OutTemp => EMAC1PHYMGTTXRESET_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYPOWERDOWN, + GlitchData => EMAC1PHYPOWERDOWN_GlitchData, + OutSignalName => "EMAC1PHYPOWERDOWN", + OutTemp => EMAC1PHYPOWERDOWN_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYSYNCACQSTATUS, + GlitchData => EMAC1PHYSYNCACQSTATUS_GlitchData, + OutSignalName => "EMAC1PHYSYNCACQSTATUS", + OutTemp => EMAC1PHYSYNCACQSTATUS_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYSYNCACQSTATUS, + GlitchData => EMAC1PHYSYNCACQSTATUS_GlitchData, + OutSignalName => "EMAC1PHYSYNCACQSTATUS", + OutTemp => EMAC1PHYSYNCACQSTATUS_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYSYNCACQSTATUS, + GlitchData => EMAC1PHYSYNCACQSTATUS_GlitchData, + OutSignalName => "EMAC1PHYSYNCACQSTATUS", + OutTemp => EMAC1PHYSYNCACQSTATUS_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARDISPMODE, + GlitchData => EMAC1PHYTXCHARDISPMODE_GlitchData, + OutSignalName => "EMAC1PHYTXCHARDISPMODE", + OutTemp => EMAC1PHYTXCHARDISPMODE_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARDISPMODE, + GlitchData => EMAC1PHYTXCHARDISPMODE_GlitchData, + OutSignalName => "EMAC1PHYTXCHARDISPMODE", + OutTemp => EMAC1PHYTXCHARDISPMODE_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARDISPMODE, + GlitchData => EMAC1PHYTXCHARDISPMODE_GlitchData, + OutSignalName => "EMAC1PHYTXCHARDISPMODE", + OutTemp => EMAC1PHYTXCHARDISPMODE_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARDISPVAL, + GlitchData => EMAC1PHYTXCHARDISPVAL_GlitchData, + OutSignalName => "EMAC1PHYTXCHARDISPVAL", + OutTemp => EMAC1PHYTXCHARDISPVAL_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARDISPVAL, + GlitchData => EMAC1PHYTXCHARDISPVAL_GlitchData, + OutSignalName => "EMAC1PHYTXCHARDISPVAL", + OutTemp => EMAC1PHYTXCHARDISPVAL_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARDISPVAL, + GlitchData => EMAC1PHYTXCHARDISPVAL_GlitchData, + OutSignalName => "EMAC1PHYTXCHARDISPVAL", + OutTemp => EMAC1PHYTXCHARDISPVAL_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARISK, + GlitchData => EMAC1PHYTXCHARISK_GlitchData, + OutSignalName => "EMAC1PHYTXCHARISK", + OutTemp => EMAC1PHYTXCHARISK_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARISK, + GlitchData => EMAC1PHYTXCHARISK_GlitchData, + OutSignalName => "EMAC1PHYTXCHARISK", + OutTemp => EMAC1PHYTXCHARISK_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARISK, + GlitchData => EMAC1PHYTXCHARISK_GlitchData, + OutSignalName => "EMAC1PHYTXCHARISK", + OutTemp => EMAC1PHYTXCHARISK_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCLK, + GlitchData => EMAC1PHYTXCLK_GlitchData, + OutSignalName => "EMAC1PHYTXCLK", + OutTemp => EMAC1PHYTXCLK_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCLK, + GlitchData => EMAC1PHYTXCLK_GlitchData, + OutSignalName => "EMAC1PHYTXCLK", + OutTemp => EMAC1PHYTXCLK_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCLK, + GlitchData => EMAC1PHYTXCLK_GlitchData, + OutSignalName => "EMAC1PHYTXCLK", + OutTemp => EMAC1PHYTXCLK_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(0), + GlitchData => EMAC1PHYTXD0_GlitchData, + OutSignalName => "EMAC1PHYTXD(0)", + OutTemp => EMAC1PHYTXD_OUT(0), + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(0), + GlitchData => EMAC1PHYTXD0_GlitchData, + OutSignalName => "EMAC1PHYTXD(0)", + OutTemp => EMAC1PHYTXD_OUT(0), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(0), + GlitchData => EMAC1PHYTXD0_GlitchData, + OutSignalName => "EMAC1PHYTXD(0)", + OutTemp => EMAC1PHYTXD_OUT(0), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(1), + GlitchData => EMAC1PHYTXD1_GlitchData, + OutSignalName => "EMAC1PHYTXD(1)", + OutTemp => EMAC1PHYTXD_OUT(1), + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(1), + GlitchData => EMAC1PHYTXD1_GlitchData, + OutSignalName => "EMAC1PHYTXD(1)", + OutTemp => EMAC1PHYTXD_OUT(1), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(1), + GlitchData => EMAC1PHYTXD1_GlitchData, + OutSignalName => "EMAC1PHYTXD(1)", + OutTemp => EMAC1PHYTXD_OUT(1), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(2), + GlitchData => EMAC1PHYTXD2_GlitchData, + OutSignalName => "EMAC1PHYTXD(2)", + OutTemp => EMAC1PHYTXD_OUT(2), + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(2), + GlitchData => EMAC1PHYTXD2_GlitchData, + OutSignalName => "EMAC1PHYTXD(2)", + OutTemp => EMAC1PHYTXD_OUT(2), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(2), + GlitchData => EMAC1PHYTXD2_GlitchData, + OutSignalName => "EMAC1PHYTXD(2)", + OutTemp => EMAC1PHYTXD_OUT(2), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(3), + GlitchData => EMAC1PHYTXD3_GlitchData, + OutSignalName => "EMAC1PHYTXD(3)", + OutTemp => EMAC1PHYTXD_OUT(3), + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(3), + GlitchData => EMAC1PHYTXD3_GlitchData, + OutSignalName => "EMAC1PHYTXD(3)", + OutTemp => EMAC1PHYTXD_OUT(3), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(3), + GlitchData => EMAC1PHYTXD3_GlitchData, + OutSignalName => "EMAC1PHYTXD(3)", + OutTemp => EMAC1PHYTXD_OUT(3), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(4), + GlitchData => EMAC1PHYTXD4_GlitchData, + OutSignalName => "EMAC1PHYTXD(4)", + OutTemp => EMAC1PHYTXD_OUT(4), + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(4), + GlitchData => EMAC1PHYTXD4_GlitchData, + OutSignalName => "EMAC1PHYTXD(4)", + OutTemp => EMAC1PHYTXD_OUT(4), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(4), + GlitchData => EMAC1PHYTXD4_GlitchData, + OutSignalName => "EMAC1PHYTXD(4)", + OutTemp => EMAC1PHYTXD_OUT(4), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(4), + GlitchData => EMAC1PHYTXD4_GlitchData, + OutSignalName => "EMAC1PHYTXD(4)", + OutTemp => EMAC1PHYTXD_OUT(4), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(5), + GlitchData => EMAC1PHYTXD5_GlitchData, + OutSignalName => "EMAC1PHYTXD(5)", + OutTemp => EMAC1PHYTXD_OUT(5), + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(5), + GlitchData => EMAC1PHYTXD5_GlitchData, + OutSignalName => "EMAC1PHYTXD(5)", + OutTemp => EMAC1PHYTXD_OUT(5), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(5), + GlitchData => EMAC1PHYTXD5_GlitchData, + OutSignalName => "EMAC1PHYTXD(5)", + OutTemp => EMAC1PHYTXD_OUT(5), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(5), + GlitchData => EMAC1PHYTXD5_GlitchData, + OutSignalName => "EMAC1PHYTXD(5)", + OutTemp => EMAC1PHYTXD_OUT(5), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(6), + GlitchData => EMAC1PHYTXD6_GlitchData, + OutSignalName => "EMAC1PHYTXD(6)", + OutTemp => EMAC1PHYTXD_OUT(6), + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(6), + GlitchData => EMAC1PHYTXD6_GlitchData, + OutSignalName => "EMAC1PHYTXD(6)", + OutTemp => EMAC1PHYTXD_OUT(6), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(6), + GlitchData => EMAC1PHYTXD6_GlitchData, + OutSignalName => "EMAC1PHYTXD(6)", + OutTemp => EMAC1PHYTXD_OUT(6), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(6), + GlitchData => EMAC1PHYTXD6_GlitchData, + OutSignalName => "EMAC1PHYTXD(6)", + OutTemp => EMAC1PHYTXD_OUT(6), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(7), + GlitchData => EMAC1PHYTXD7_GlitchData, + OutSignalName => "EMAC1PHYTXD(7)", + OutTemp => EMAC1PHYTXD_OUT(7), + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(7), + GlitchData => EMAC1PHYTXD7_GlitchData, + OutSignalName => "EMAC1PHYTXD(7)", + OutTemp => EMAC1PHYTXD_OUT(7), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(7), + GlitchData => EMAC1PHYTXD7_GlitchData, + OutSignalName => "EMAC1PHYTXD(7)", + OutTemp => EMAC1PHYTXD_OUT(7), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(7), + GlitchData => EMAC1PHYTXD7_GlitchData, + OutSignalName => "EMAC1PHYTXD(7)", + OutTemp => EMAC1PHYTXD_OUT(7), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXEN, + GlitchData => EMAC1PHYTXEN_GlitchData, + OutSignalName => "EMAC1PHYTXEN", + OutTemp => EMAC1PHYTXEN_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXEN, + GlitchData => EMAC1PHYTXEN_GlitchData, + OutSignalName => "EMAC1PHYTXEN", + OutTemp => EMAC1PHYTXEN_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXEN, + GlitchData => EMAC1PHYTXEN_GlitchData, + OutSignalName => "EMAC1PHYTXEN", + OutTemp => EMAC1PHYTXEN_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXER, + GlitchData => EMAC1PHYTXER_GlitchData, + OutSignalName => "EMAC1PHYTXER", + OutTemp => EMAC1PHYTXER_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXER, + GlitchData => EMAC1PHYTXER_GlitchData, + OutSignalName => "EMAC1PHYTXER", + OutTemp => EMAC1PHYTXER_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXER, + GlitchData => EMAC1PHYTXER_GlitchData, + OutSignalName => "EMAC1PHYTXER", + OutTemp => EMAC1PHYTXER_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXER, + GlitchData => EMAC1PHYTXER_GlitchData, + OutSignalName => "EMAC1PHYTXER", + OutTemp => EMAC1PHYTXER_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1SPEEDIS10100, + GlitchData => EMAC1SPEEDIS10100_GlitchData, + OutSignalName => "EMAC1SPEEDIS10100", + OutTemp => EMAC1SPEEDIS10100_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRACK, + GlitchData => EMACDCRACK_GlitchData, + OutSignalName => "EMACDCRACK", + OutTemp => EMACDCRACK_OUT, + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(0), + GlitchData => EMACDCRDBUS0_GlitchData, + OutSignalName => "EMACDCRDBUS(0)", + OutTemp => EMACDCRDBUS_OUT(0), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(1), + GlitchData => EMACDCRDBUS1_GlitchData, + OutSignalName => "EMACDCRDBUS(1)", + OutTemp => EMACDCRDBUS_OUT(1), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(2), + GlitchData => EMACDCRDBUS2_GlitchData, + OutSignalName => "EMACDCRDBUS(2)", + OutTemp => EMACDCRDBUS_OUT(2), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(3), + GlitchData => EMACDCRDBUS3_GlitchData, + OutSignalName => "EMACDCRDBUS(3)", + OutTemp => EMACDCRDBUS_OUT(3), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(4), + GlitchData => EMACDCRDBUS4_GlitchData, + OutSignalName => "EMACDCRDBUS(4)", + OutTemp => EMACDCRDBUS_OUT(4), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(5), + GlitchData => EMACDCRDBUS5_GlitchData, + OutSignalName => "EMACDCRDBUS(5)", + OutTemp => EMACDCRDBUS_OUT(5), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(6), + GlitchData => EMACDCRDBUS6_GlitchData, + OutSignalName => "EMACDCRDBUS(6)", + OutTemp => EMACDCRDBUS_OUT(6), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(7), + GlitchData => EMACDCRDBUS7_GlitchData, + OutSignalName => "EMACDCRDBUS(7)", + OutTemp => EMACDCRDBUS_OUT(7), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(8), + GlitchData => EMACDCRDBUS8_GlitchData, + OutSignalName => "EMACDCRDBUS(8)", + OutTemp => EMACDCRDBUS_OUT(8), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(9), + GlitchData => EMACDCRDBUS9_GlitchData, + OutSignalName => "EMACDCRDBUS(9)", + OutTemp => EMACDCRDBUS_OUT(9), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(10), + GlitchData => EMACDCRDBUS10_GlitchData, + OutSignalName => "EMACDCRDBUS(10)", + OutTemp => EMACDCRDBUS_OUT(10), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(11), + GlitchData => EMACDCRDBUS11_GlitchData, + OutSignalName => "EMACDCRDBUS(11)", + OutTemp => EMACDCRDBUS_OUT(11), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(12), + GlitchData => EMACDCRDBUS12_GlitchData, + OutSignalName => "EMACDCRDBUS(12)", + OutTemp => EMACDCRDBUS_OUT(12), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(13), + GlitchData => EMACDCRDBUS13_GlitchData, + OutSignalName => "EMACDCRDBUS(13)", + OutTemp => EMACDCRDBUS_OUT(13), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(14), + GlitchData => EMACDCRDBUS14_GlitchData, + OutSignalName => "EMACDCRDBUS(14)", + OutTemp => EMACDCRDBUS_OUT(14), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(15), + GlitchData => EMACDCRDBUS15_GlitchData, + OutSignalName => "EMACDCRDBUS(15)", + OutTemp => EMACDCRDBUS_OUT(15), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(16), + GlitchData => EMACDCRDBUS16_GlitchData, + OutSignalName => "EMACDCRDBUS(16)", + OutTemp => EMACDCRDBUS_OUT(16), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(17), + GlitchData => EMACDCRDBUS17_GlitchData, + OutSignalName => "EMACDCRDBUS(17)", + OutTemp => EMACDCRDBUS_OUT(17), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(18), + GlitchData => EMACDCRDBUS18_GlitchData, + OutSignalName => "EMACDCRDBUS(18)", + OutTemp => EMACDCRDBUS_OUT(18), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(19), + GlitchData => EMACDCRDBUS19_GlitchData, + OutSignalName => "EMACDCRDBUS(19)", + OutTemp => EMACDCRDBUS_OUT(19), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(20), + GlitchData => EMACDCRDBUS20_GlitchData, + OutSignalName => "EMACDCRDBUS(20)", + OutTemp => EMACDCRDBUS_OUT(20), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(21), + GlitchData => EMACDCRDBUS21_GlitchData, + OutSignalName => "EMACDCRDBUS(21)", + OutTemp => EMACDCRDBUS_OUT(21), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(22), + GlitchData => EMACDCRDBUS22_GlitchData, + OutSignalName => "EMACDCRDBUS(22)", + OutTemp => EMACDCRDBUS_OUT(22), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(23), + GlitchData => EMACDCRDBUS23_GlitchData, + OutSignalName => "EMACDCRDBUS(23)", + OutTemp => EMACDCRDBUS_OUT(23), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(24), + GlitchData => EMACDCRDBUS24_GlitchData, + OutSignalName => "EMACDCRDBUS(24)", + OutTemp => EMACDCRDBUS_OUT(24), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(25), + GlitchData => EMACDCRDBUS25_GlitchData, + OutSignalName => "EMACDCRDBUS(25)", + OutTemp => EMACDCRDBUS_OUT(25), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(26), + GlitchData => EMACDCRDBUS26_GlitchData, + OutSignalName => "EMACDCRDBUS(26)", + OutTemp => EMACDCRDBUS_OUT(26), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(27), + GlitchData => EMACDCRDBUS27_GlitchData, + OutSignalName => "EMACDCRDBUS(27)", + OutTemp => EMACDCRDBUS_OUT(27), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(28), + GlitchData => EMACDCRDBUS28_GlitchData, + OutSignalName => "EMACDCRDBUS(28)", + OutTemp => EMACDCRDBUS_OUT(28), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(29), + GlitchData => EMACDCRDBUS29_GlitchData, + OutSignalName => "EMACDCRDBUS(29)", + OutTemp => EMACDCRDBUS_OUT(29), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(30), + GlitchData => EMACDCRDBUS30_GlitchData, + OutSignalName => "EMACDCRDBUS(30)", + OutTemp => EMACDCRDBUS_OUT(30), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(31), + GlitchData => EMACDCRDBUS31_GlitchData, + OutSignalName => "EMACDCRDBUS(31)", + OutTemp => EMACDCRDBUS_OUT(31), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTMIIMRDY, + GlitchData => HOSTMIIMRDY_GlitchData, + OutSignalName => "HOSTMIIMRDY", + OutTemp => HOSTMIIMRDY_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(0), + GlitchData => HOSTRDDATA0_GlitchData, + OutSignalName => "HOSTRDDATA(0)", + OutTemp => HOSTRDDATA_OUT(0), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(1), + GlitchData => HOSTRDDATA1_GlitchData, + OutSignalName => "HOSTRDDATA(1)", + OutTemp => HOSTRDDATA_OUT(1), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(2), + GlitchData => HOSTRDDATA2_GlitchData, + OutSignalName => "HOSTRDDATA(2)", + OutTemp => HOSTRDDATA_OUT(2), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(3), + GlitchData => HOSTRDDATA3_GlitchData, + OutSignalName => "HOSTRDDATA(3)", + OutTemp => HOSTRDDATA_OUT(3), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(4), + GlitchData => HOSTRDDATA4_GlitchData, + OutSignalName => "HOSTRDDATA(4)", + OutTemp => HOSTRDDATA_OUT(4), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(5), + GlitchData => HOSTRDDATA5_GlitchData, + OutSignalName => "HOSTRDDATA(5)", + OutTemp => HOSTRDDATA_OUT(5), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(6), + GlitchData => HOSTRDDATA6_GlitchData, + OutSignalName => "HOSTRDDATA(6)", + OutTemp => HOSTRDDATA_OUT(6), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(7), + GlitchData => HOSTRDDATA7_GlitchData, + OutSignalName => "HOSTRDDATA(7)", + OutTemp => HOSTRDDATA_OUT(7), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(8), + GlitchData => HOSTRDDATA8_GlitchData, + OutSignalName => "HOSTRDDATA(8)", + OutTemp => HOSTRDDATA_OUT(8), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(9), + GlitchData => HOSTRDDATA9_GlitchData, + OutSignalName => "HOSTRDDATA(9)", + OutTemp => HOSTRDDATA_OUT(9), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(10), + GlitchData => HOSTRDDATA10_GlitchData, + OutSignalName => "HOSTRDDATA(10)", + OutTemp => HOSTRDDATA_OUT(10), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(11), + GlitchData => HOSTRDDATA11_GlitchData, + OutSignalName => "HOSTRDDATA(11)", + OutTemp => HOSTRDDATA_OUT(11), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(12), + GlitchData => HOSTRDDATA12_GlitchData, + OutSignalName => "HOSTRDDATA(12)", + OutTemp => HOSTRDDATA_OUT(12), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(13), + GlitchData => HOSTRDDATA13_GlitchData, + OutSignalName => "HOSTRDDATA(13)", + OutTemp => HOSTRDDATA_OUT(13), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(14), + GlitchData => HOSTRDDATA14_GlitchData, + OutSignalName => "HOSTRDDATA(14)", + OutTemp => HOSTRDDATA_OUT(14), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(15), + GlitchData => HOSTRDDATA15_GlitchData, + OutSignalName => "HOSTRDDATA(15)", + OutTemp => HOSTRDDATA_OUT(15), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(16), + GlitchData => HOSTRDDATA16_GlitchData, + OutSignalName => "HOSTRDDATA(16)", + OutTemp => HOSTRDDATA_OUT(16), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(17), + GlitchData => HOSTRDDATA17_GlitchData, + OutSignalName => "HOSTRDDATA(17)", + OutTemp => HOSTRDDATA_OUT(17), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(18), + GlitchData => HOSTRDDATA18_GlitchData, + OutSignalName => "HOSTRDDATA(18)", + OutTemp => HOSTRDDATA_OUT(18), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(19), + GlitchData => HOSTRDDATA19_GlitchData, + OutSignalName => "HOSTRDDATA(19)", + OutTemp => HOSTRDDATA_OUT(19), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(20), + GlitchData => HOSTRDDATA20_GlitchData, + OutSignalName => "HOSTRDDATA(20)", + OutTemp => HOSTRDDATA_OUT(20), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(21), + GlitchData => HOSTRDDATA21_GlitchData, + OutSignalName => "HOSTRDDATA(21)", + OutTemp => HOSTRDDATA_OUT(21), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(22), + GlitchData => HOSTRDDATA22_GlitchData, + OutSignalName => "HOSTRDDATA(22)", + OutTemp => HOSTRDDATA_OUT(22), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(23), + GlitchData => HOSTRDDATA23_GlitchData, + OutSignalName => "HOSTRDDATA(23)", + OutTemp => HOSTRDDATA_OUT(23), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(24), + GlitchData => HOSTRDDATA24_GlitchData, + OutSignalName => "HOSTRDDATA(24)", + OutTemp => HOSTRDDATA_OUT(24), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(25), + GlitchData => HOSTRDDATA25_GlitchData, + OutSignalName => "HOSTRDDATA(25)", + OutTemp => HOSTRDDATA_OUT(25), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(26), + GlitchData => HOSTRDDATA26_GlitchData, + OutSignalName => "HOSTRDDATA(26)", + OutTemp => HOSTRDDATA_OUT(26), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(27), + GlitchData => HOSTRDDATA27_GlitchData, + OutSignalName => "HOSTRDDATA(27)", + OutTemp => HOSTRDDATA_OUT(27), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(28), + GlitchData => HOSTRDDATA28_GlitchData, + OutSignalName => "HOSTRDDATA(28)", + OutTemp => HOSTRDDATA_OUT(28), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(29), + GlitchData => HOSTRDDATA29_GlitchData, + OutSignalName => "HOSTRDDATA(29)", + OutTemp => HOSTRDDATA_OUT(29), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(30), + GlitchData => HOSTRDDATA30_GlitchData, + OutSignalName => "HOSTRDDATA(30)", + OutTemp => HOSTRDDATA_OUT(30), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(31), + GlitchData => HOSTRDDATA31_GlitchData, + OutSignalName => "HOSTRDDATA(31)", + OutTemp => HOSTRDDATA_OUT(31), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + + + wait on + DCRHOSTDONEIR_out, + EMAC0CLIENTANINTERRUPT_out, + EMAC0CLIENTRXBADFRAME_out, + EMAC0CLIENTRXCLIENTCLKOUT_out, + EMAC0CLIENTRXDVLDMSW_out, + EMAC0CLIENTRXDVLD_out, + EMAC0CLIENTRXD_out, + EMAC0CLIENTRXFRAMEDROP_out, + EMAC0CLIENTRXGOODFRAME_out, + EMAC0CLIENTRXSTATSBYTEVLD_out, + EMAC0CLIENTRXSTATSVLD_out, + EMAC0CLIENTRXSTATS_out, + EMAC0CLIENTTXACK_out, + EMAC0CLIENTTXCLIENTCLKOUT_out, + EMAC0CLIENTTXCOLLISION_out, + EMAC0CLIENTTXRETRANSMIT_out, + EMAC0CLIENTTXSTATSBYTEVLD_out, + EMAC0CLIENTTXSTATSVLD_out, + EMAC0CLIENTTXSTATS_out, + EMAC0PHYENCOMMAALIGN_out, + EMAC0PHYLOOPBACKMSB_out, + EMAC0PHYMCLKOUT_out, + EMAC0PHYMDOUT_out, + EMAC0PHYMDTRI_out, + EMAC0PHYMGTRXRESET_out, + EMAC0PHYMGTTXRESET_out, + EMAC0PHYPOWERDOWN_out, + EMAC0PHYSYNCACQSTATUS_out, + EMAC0PHYTXCHARDISPMODE_out, + EMAC0PHYTXCHARDISPVAL_out, + EMAC0PHYTXCHARISK_out, + EMAC0PHYTXCLK_out, + EMAC0PHYTXD_out, + EMAC0PHYTXEN_out, + EMAC0PHYTXER_out, + EMAC0PHYTXGMIIMIICLKOUT_out, + EMAC0SPEEDIS10100_out, + EMAC1CLIENTANINTERRUPT_out, + EMAC1CLIENTRXBADFRAME_out, + EMAC1CLIENTRXCLIENTCLKOUT_out, + EMAC1CLIENTRXDVLDMSW_out, + EMAC1CLIENTRXDVLD_out, + EMAC1CLIENTRXD_out, + EMAC1CLIENTRXFRAMEDROP_out, + EMAC1CLIENTRXGOODFRAME_out, + EMAC1CLIENTRXSTATSBYTEVLD_out, + EMAC1CLIENTRXSTATSVLD_out, + EMAC1CLIENTRXSTATS_out, + EMAC1CLIENTTXACK_out, + EMAC1CLIENTTXCLIENTCLKOUT_out, + EMAC1CLIENTTXCOLLISION_out, + EMAC1CLIENTTXRETRANSMIT_out, + EMAC1CLIENTTXSTATSBYTEVLD_out, + EMAC1CLIENTTXSTATSVLD_out, + EMAC1CLIENTTXSTATS_out, + EMAC1PHYENCOMMAALIGN_out, + EMAC1PHYLOOPBACKMSB_out, + EMAC1PHYMCLKOUT_out, + EMAC1PHYMDOUT_out, + EMAC1PHYMDTRI_out, + EMAC1PHYMGTRXRESET_out, + EMAC1PHYMGTTXRESET_out, + EMAC1PHYPOWERDOWN_out, + EMAC1PHYSYNCACQSTATUS_out, + EMAC1PHYTXCHARDISPMODE_out, + EMAC1PHYTXCHARDISPVAL_out, + EMAC1PHYTXCHARISK_out, + EMAC1PHYTXCLK_out, + EMAC1PHYTXD_out, + EMAC1PHYTXEN_out, + EMAC1PHYTXER_out, + EMAC1PHYTXGMIIMIICLKOUT_out, + EMAC1SPEEDIS10100_out, + EMACDCRACK_out, + EMACDCRDBUS_out, + HOSTMIIMRDY_out, + HOSTRDDATA_out, + + CLIENTEMAC0DCMLOCKED_ipd, + CLIENTEMAC0PAUSEREQ_ipd, + CLIENTEMAC0PAUSEVAL_ipd, + CLIENTEMAC0RXCLIENTCLKIN_ipd, + CLIENTEMAC0TXCLIENTCLKIN_ipd, + CLIENTEMAC0TXDVLDMSW_ipd, + CLIENTEMAC0TXDVLD_ipd, + CLIENTEMAC0TXD_ipd, + CLIENTEMAC0TXFIRSTBYTE_ipd, + CLIENTEMAC0TXIFGDELAY_ipd, + CLIENTEMAC0TXUNDERRUN_ipd, + CLIENTEMAC1DCMLOCKED_ipd, + CLIENTEMAC1PAUSEREQ_ipd, + CLIENTEMAC1PAUSEVAL_ipd, + CLIENTEMAC1RXCLIENTCLKIN_ipd, + CLIENTEMAC1TXCLIENTCLKIN_ipd, + CLIENTEMAC1TXDVLDMSW_ipd, + CLIENTEMAC1TXDVLD_ipd, + CLIENTEMAC1TXD_ipd, + CLIENTEMAC1TXFIRSTBYTE_ipd, + CLIENTEMAC1TXIFGDELAY_ipd, + CLIENTEMAC1TXUNDERRUN_ipd, + DCREMACABUS_ipd, + DCREMACCLK_ipd, + DCREMACDBUS_ipd, + DCREMACENABLE_ipd, + DCREMACREAD_ipd, + DCREMACWRITE_ipd, + HOSTADDR_ipd, + HOSTCLK_ipd, + HOSTEMAC1SEL_ipd, + HOSTMIIMSEL_ipd, + HOSTOPCODE_ipd, + HOSTREQ_ipd, + HOSTWRDATA_ipd, + PHYEMAC0COL_ipd, + PHYEMAC0CRS_ipd, + PHYEMAC0GTXCLK_ipd, + PHYEMAC0MCLKIN_ipd, + PHYEMAC0MDIN_ipd, + PHYEMAC0MIITXCLK_ipd, + PHYEMAC0PHYAD_ipd, + PHYEMAC0RXBUFERR_ipd, + PHYEMAC0RXBUFSTATUS_ipd, + PHYEMAC0RXCHARISCOMMA_ipd, + PHYEMAC0RXCHARISK_ipd, + PHYEMAC0RXCHECKINGCRC_ipd, + PHYEMAC0RXCLKCORCNT_ipd, + PHYEMAC0RXCLK_ipd, + PHYEMAC0RXCOMMADET_ipd, + PHYEMAC0RXDISPERR_ipd, + PHYEMAC0RXDV_ipd, + PHYEMAC0RXD_ipd, + PHYEMAC0RXER_ipd, + PHYEMAC0RXLOSSOFSYNC_ipd, + PHYEMAC0RXNOTINTABLE_ipd, + PHYEMAC0RXRUNDISP_ipd, + PHYEMAC0SIGNALDET_ipd, + PHYEMAC0TXBUFERR_ipd, + PHYEMAC0TXGMIIMIICLKIN_ipd, + PHYEMAC1COL_ipd, + PHYEMAC1CRS_ipd, + PHYEMAC1GTXCLK_ipd, + PHYEMAC1MCLKIN_ipd, + PHYEMAC1MDIN_ipd, + PHYEMAC1MIITXCLK_ipd, + PHYEMAC1PHYAD_ipd, + PHYEMAC1RXBUFERR_ipd, + PHYEMAC1RXBUFSTATUS_ipd, + PHYEMAC1RXCHARISCOMMA_ipd, + PHYEMAC1RXCHARISK_ipd, + PHYEMAC1RXCHECKINGCRC_ipd, + PHYEMAC1RXCLKCORCNT_ipd, + PHYEMAC1RXCLK_ipd, + PHYEMAC1RXCOMMADET_ipd, + PHYEMAC1RXDISPERR_ipd, + PHYEMAC1RXDV_ipd, + PHYEMAC1RXD_ipd, + PHYEMAC1RXER_ipd, + PHYEMAC1RXLOSSOFSYNC_ipd, + PHYEMAC1RXNOTINTABLE_ipd, + PHYEMAC1RXRUNDISP_ipd, + PHYEMAC1SIGNALDET_ipd, + PHYEMAC1TXBUFERR_ipd, + PHYEMAC1TXGMIIMIICLKIN_ipd, + RESET_ipd; + + end process TIMING; +end TEMAC_V; +------------------------------------------------------- +-- Copyright (c) 1995/2006 Xilinx Inc. +-- All Right Reserved. +------------------------------------------------------- +-- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : +-- / / +-- /___/ /\ Filename : GTX_DUAL.vhd +-- \ \ / \ Timestamp : Tue Jan 9 10:05:31 2007 +-- \__ \/\__ \ +-- +-- 09/12/06 - CR#423671 - Initial version. +-- 12/05/06 - CR#426138 - J.31 spreadsheet update +-- 01/23/07 - CR#430426 - J.32 pinTime added +-- 02/20/07 - CR#434096 - Parameter default value update PLL_RXDIVSEL_OUT_0/1 +-- 06/18/07 - CR#441601 - BT1445 - Test attributes made visible +-- 06/18/07 - CR#441576 - BT1488 - Add STEPPING attribute +-- 10/05/07 - CR#451343 - BT1514 - Add ES1 (ES1 mapped to 0) as STEPPING value +-- 11/05/07 - CR#452590 - BT1514 - Remove STEPPING attribute from unisim/simprim wrapper +-- 02/05/08 - CR#459742 - Attribute default changes +-- 03/14/08 - CR#468285 - Updated timing checks +-- 03/17/08 - CR#467692 - Add SIM_MODE attribute with values LEGACY & FAST model +-- 04/24/08 - CR#472011 - OOBDETECT_THRESHOLD_0/1 default from 001 to 110, range changes from 000-111 to 110-111 +-- 05/13/08 - CR#472931 - OOBDETECT_THRESHOLD_0/1 case statement updates +-- 06/24/08 - CR472608, CR472665 - Update SIM_MODE default to FAST +------------------------------------------------------- + +----- CELL GTX_DUAL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + + +library unisim; +use unisim.VCOMPONENTS.all; + +library secureip; +use secureip.all; + +entity GTX_DUAL is +generic ( + AC_CAP_DIS_0 : boolean := TRUE; + AC_CAP_DIS_1 : boolean := TRUE; + ALIGN_COMMA_WORD_0 : integer := 1; + ALIGN_COMMA_WORD_1 : integer := 1; + CB2_INH_CC_PERIOD_0 : integer := 8; + CB2_INH_CC_PERIOD_1 : integer := 8; + CDR_PH_ADJ_TIME : bit_vector := "01010"; + CHAN_BOND_1_MAX_SKEW_0 : integer := 7; + CHAN_BOND_1_MAX_SKEW_1 : integer := 7; + CHAN_BOND_2_MAX_SKEW_0 : integer := 7; + CHAN_BOND_2_MAX_SKEW_1 : integer := 7; + CHAN_BOND_KEEP_ALIGN_0 : boolean := FALSE; + CHAN_BOND_KEEP_ALIGN_1 : boolean := FALSE; + CHAN_BOND_LEVEL_0 : integer := 0; + CHAN_BOND_LEVEL_1 : integer := 0; + CHAN_BOND_MODE_0 : string := "OFF"; + CHAN_BOND_MODE_1 : string := "OFF"; + CHAN_BOND_SEQ_1_1_0 : bit_vector := "0101111100"; + CHAN_BOND_SEQ_1_1_1 : bit_vector := "0101111100"; + CHAN_BOND_SEQ_1_2_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_2_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_3_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_3_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_4_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_4_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_ENABLE_0 : bit_vector := "0001"; + CHAN_BOND_SEQ_1_ENABLE_1 : bit_vector := "0001"; + CHAN_BOND_SEQ_2_1_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_1_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_2_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_2_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_3_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_3_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_4_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_4_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_ENABLE_0 : bit_vector := "0000"; + CHAN_BOND_SEQ_2_ENABLE_1 : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE_0 : boolean := FALSE; + CHAN_BOND_SEQ_2_USE_1 : boolean := FALSE; + CHAN_BOND_SEQ_LEN_0 : integer := 1; + CHAN_BOND_SEQ_LEN_1 : integer := 1; + CLK25_DIVIDER : integer := 10; + CLKINDC_B : boolean := TRUE; + CLKRCV_TRST : boolean := TRUE; + CLK_CORRECT_USE_0 : boolean := TRUE; + CLK_CORRECT_USE_1 : boolean := TRUE; + CLK_COR_ADJ_LEN_0 : integer := 1; + CLK_COR_ADJ_LEN_1 : integer := 1; + CLK_COR_DET_LEN_0 : integer := 1; + CLK_COR_DET_LEN_1 : integer := 1; + CLK_COR_INSERT_IDLE_FLAG_0 : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG_1 : boolean := FALSE; + CLK_COR_KEEP_IDLE_0 : boolean := FALSE; + CLK_COR_KEEP_IDLE_1 : boolean := FALSE; + CLK_COR_MAX_LAT_0 : integer := 20; + CLK_COR_MAX_LAT_1 : integer := 20; + CLK_COR_MIN_LAT_0 : integer := 18; + CLK_COR_MIN_LAT_1 : integer := 18; + CLK_COR_PRECEDENCE_0 : boolean := TRUE; + CLK_COR_PRECEDENCE_1 : boolean := TRUE; + CLK_COR_REPEAT_WAIT_0 : integer := 0; + CLK_COR_REPEAT_WAIT_1 : integer := 0; + CLK_COR_SEQ_1_1_0 : bit_vector := "0100011100"; + CLK_COR_SEQ_1_1_1 : bit_vector := "0100011100"; + CLK_COR_SEQ_1_2_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_2_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_3_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_3_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_4_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_4_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_ENABLE_0 : bit_vector := "0001"; + CLK_COR_SEQ_1_ENABLE_1 : bit_vector := "0001"; + CLK_COR_SEQ_2_1_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_1_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_2_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_2_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_3_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_3_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_4_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_4_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_ENABLE_0 : bit_vector := "0000"; + CLK_COR_SEQ_2_ENABLE_1 : bit_vector := "0000"; + CLK_COR_SEQ_2_USE_0 : boolean := FALSE; + CLK_COR_SEQ_2_USE_1 : boolean := FALSE; + CM_TRIM_0 : bit_vector := "10"; + CM_TRIM_1 : bit_vector := "10"; + COMMA_10B_ENABLE_0 : bit_vector := "0001111111"; + COMMA_10B_ENABLE_1 : bit_vector := "0001111111"; + COMMA_DOUBLE_0 : boolean := FALSE; + COMMA_DOUBLE_1 : boolean := FALSE; + COM_BURST_VAL_0 : bit_vector := "1111"; + COM_BURST_VAL_1 : bit_vector := "1111"; + DEC_MCOMMA_DETECT_0 : boolean := TRUE; + DEC_MCOMMA_DETECT_1 : boolean := TRUE; + DEC_PCOMMA_DETECT_0 : boolean := TRUE; + DEC_PCOMMA_DETECT_1 : boolean := TRUE; + DEC_VALID_COMMA_ONLY_0 : boolean := TRUE; + DEC_VALID_COMMA_ONLY_1 : boolean := TRUE; + DFE_CAL_TIME : bit_vector := "00110"; + DFE_CFG_0 : bit_vector := "1101111011"; + DFE_CFG_1 : bit_vector := "1101111011"; + GEARBOX_ENDEC_0 : bit_vector := "000"; + GEARBOX_ENDEC_1 : bit_vector := "000"; + MCOMMA_10B_VALUE_0 : bit_vector := "1010000011"; + MCOMMA_10B_VALUE_1 : bit_vector := "1010000011"; + MCOMMA_DETECT_0 : boolean := TRUE; + MCOMMA_DETECT_1 : boolean := TRUE; + OOBDETECT_THRESHOLD_0 : bit_vector := "110"; + OOBDETECT_THRESHOLD_1 : bit_vector := "110"; + OOB_CLK_DIVIDER : integer := 6; + OVERSAMPLE_MODE : boolean := FALSE; + PCI_EXPRESS_MODE_0 : boolean := FALSE; + PCI_EXPRESS_MODE_1 : boolean := FALSE; + PCOMMA_10B_VALUE_0 : bit_vector := "0101111100"; + PCOMMA_10B_VALUE_1 : bit_vector := "0101111100"; + PCOMMA_DETECT_0 : boolean := TRUE; + PCOMMA_DETECT_1 : boolean := TRUE; + PLL_COM_CFG : bit_vector := X"21680a"; + PLL_CP_CFG : bit_vector := X"00"; + PLL_DIVSEL_FB : integer := 2; + PLL_DIVSEL_REF : integer := 1; + PLL_FB_DCCEN : boolean := FALSE; + PLL_LKDET_CFG : bit_vector := "101"; + PLL_RXDIVSEL_OUT_0 : integer := 1; + PLL_RXDIVSEL_OUT_1 : integer := 1; + PLL_SATA_0 : boolean := FALSE; + PLL_SATA_1 : boolean := FALSE; + PLL_TDCC_CFG : bit_vector := "000"; + PLL_TXDIVSEL_OUT_0 : integer := 1; + PLL_TXDIVSEL_OUT_1 : integer := 1; + PMA_CDR_SCAN_0 : bit_vector := X"6404035"; + PMA_CDR_SCAN_1 : bit_vector := X"6404035"; + PMA_COM_CFG : bit_vector := X"000000000000000000"; + PMA_RXSYNC_CFG_0 : bit_vector := X"00"; + PMA_RXSYNC_CFG_1 : bit_vector := X"00"; + PMA_RX_CFG_0 : bit_vector := X"0f44089"; + PMA_RX_CFG_1 : bit_vector := X"0f44089"; + PMA_TX_CFG_0 : bit_vector := X"80082"; + PMA_TX_CFG_1 : bit_vector := X"80082"; + PRBS_ERR_THRESHOLD_0 : bit_vector := X"00000001"; + PRBS_ERR_THRESHOLD_1 : bit_vector := X"00000001"; + RCV_TERM_GND_0 : boolean := FALSE; + RCV_TERM_GND_1 : boolean := FALSE; + RCV_TERM_VTTRX_0 : boolean := FALSE; + RCV_TERM_VTTRX_1 : boolean := FALSE; + RXGEARBOX_USE_0 : boolean := FALSE; + RXGEARBOX_USE_1 : boolean := FALSE; + RX_BUFFER_USE_0 : boolean := TRUE; + RX_BUFFER_USE_1 : boolean := TRUE; + RX_DECODE_SEQ_MATCH_0 : boolean := TRUE; + RX_DECODE_SEQ_MATCH_1 : boolean := TRUE; + RX_EN_IDLE_HOLD_CDR : boolean := FALSE; + RX_EN_IDLE_HOLD_DFE_0 : boolean := TRUE; + RX_EN_IDLE_HOLD_DFE_1 : boolean := TRUE; + RX_EN_IDLE_RESET_BUF_0 : boolean := TRUE; + RX_EN_IDLE_RESET_BUF_1 : boolean := TRUE; + RX_EN_IDLE_RESET_FR : boolean := TRUE; + RX_EN_IDLE_RESET_PH : boolean := TRUE; + RX_IDLE_HI_CNT_0 : bit_vector := "1000"; + RX_IDLE_HI_CNT_1 : bit_vector := "1000"; + RX_IDLE_LO_CNT_0 : bit_vector := "0000"; + RX_IDLE_LO_CNT_1 : bit_vector := "0000"; + RX_LOSS_OF_SYNC_FSM_0 : boolean := FALSE; + RX_LOSS_OF_SYNC_FSM_1 : boolean := FALSE; + RX_LOS_INVALID_INCR_0 : integer := 1; + RX_LOS_INVALID_INCR_1 : integer := 1; + RX_LOS_THRESHOLD_0 : integer := 4; + RX_LOS_THRESHOLD_1 : integer := 4; + RX_SLIDE_MODE_0 : string := "PCS"; + RX_SLIDE_MODE_1 : string := "PCS"; + RX_STATUS_FMT_0 : string := "PCIE"; + RX_STATUS_FMT_1 : string := "PCIE"; + RX_XCLK_SEL_0 : string := "RXREC"; + RX_XCLK_SEL_1 : string := "RXREC"; + SATA_BURST_VAL_0 : bit_vector := "100"; + SATA_BURST_VAL_1 : bit_vector := "100"; + SATA_IDLE_VAL_0 : bit_vector := "100"; + SATA_IDLE_VAL_1 : bit_vector := "100"; + SATA_MAX_BURST_0 : integer := 7; + SATA_MAX_BURST_1 : integer := 7; + SATA_MAX_INIT_0 : integer := 22; + SATA_MAX_INIT_1 : integer := 22; + SATA_MAX_WAKE_0 : integer := 7; + SATA_MAX_WAKE_1 : integer := 7; + SATA_MIN_BURST_0 : integer := 4; + SATA_MIN_BURST_1 : integer := 4; + SATA_MIN_INIT_0 : integer := 12; + SATA_MIN_INIT_1 : integer := 12; + SATA_MIN_WAKE_0 : integer := 4; + SATA_MIN_WAKE_1 : integer := 4; + SIM_GTXRESET_SPEEDUP : integer := 1; + SIM_MODE : string := "FAST"; + SIM_PLL_PERDIV2 : bit_vector := X"140"; + SIM_RECEIVER_DETECT_PASS_0 : boolean := TRUE; + SIM_RECEIVER_DETECT_PASS_1 : boolean := TRUE; + TERMINATION_CTRL : bit_vector := "10100"; + TERMINATION_IMP_0 : integer := 50; + TERMINATION_IMP_1 : integer := 50; + TERMINATION_OVRD : boolean := FALSE; + TRANS_TIME_FROM_P2_0 : bit_vector := X"03c"; + TRANS_TIME_FROM_P2_1 : bit_vector := X"03c"; + TRANS_TIME_NON_P2_0 : bit_vector := X"19"; + TRANS_TIME_NON_P2_1 : bit_vector := X"19"; + TRANS_TIME_TO_P2_0 : bit_vector := X"064"; + TRANS_TIME_TO_P2_1 : bit_vector := X"064"; + TXGEARBOX_USE_0 : boolean := FALSE; + TXGEARBOX_USE_1 : boolean := FALSE; + TXRX_INVERT_0 : bit_vector := "011"; + TXRX_INVERT_1 : bit_vector := "011"; + TX_BUFFER_USE_0 : boolean := TRUE; + TX_BUFFER_USE_1 : boolean := TRUE; + TX_DETECT_RX_CFG_0 : bit_vector := X"1832"; + TX_DETECT_RX_CFG_1 : bit_vector := X"1832"; + TX_IDLE_DELAY_0 : bit_vector := "010"; + TX_IDLE_DELAY_1 : bit_vector := "010"; + TX_XCLK_SEL_0 : string := "TXOUT"; + TX_XCLK_SEL_1 : string := "TXOUT" + + + + ); + +port ( + DFECLKDLYADJMONITOR0 : out std_logic_vector(5 downto 0); + DFECLKDLYADJMONITOR1 : out std_logic_vector(5 downto 0); + DFEEYEDACMONITOR0 : out std_logic_vector(4 downto 0); + DFEEYEDACMONITOR1 : out std_logic_vector(4 downto 0); + DFESENSCAL0 : out std_logic_vector(2 downto 0); + DFESENSCAL1 : out std_logic_vector(2 downto 0); + DFETAP1MONITOR0 : out std_logic_vector(4 downto 0); + DFETAP1MONITOR1 : out std_logic_vector(4 downto 0); + DFETAP2MONITOR0 : out std_logic_vector(4 downto 0); + DFETAP2MONITOR1 : out std_logic_vector(4 downto 0); + DFETAP3MONITOR0 : out std_logic_vector(3 downto 0); + DFETAP3MONITOR1 : out std_logic_vector(3 downto 0); + DFETAP4MONITOR0 : out std_logic_vector(3 downto 0); + DFETAP4MONITOR1 : out std_logic_vector(3 downto 0); + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + PHYSTATUS0 : out std_ulogic; + PHYSTATUS1 : out std_ulogic; + PLLLKDET : out std_ulogic; + REFCLKOUT : out std_ulogic; + RESETDONE0 : out std_ulogic; + RESETDONE1 : out std_ulogic; + RXBUFSTATUS0 : out std_logic_vector(2 downto 0); + RXBUFSTATUS1 : out std_logic_vector(2 downto 0); + RXBYTEISALIGNED0 : out std_ulogic; + RXBYTEISALIGNED1 : out std_ulogic; + RXBYTEREALIGN0 : out std_ulogic; + RXBYTEREALIGN1 : out std_ulogic; + RXCHANBONDSEQ0 : out std_ulogic; + RXCHANBONDSEQ1 : out std_ulogic; + RXCHANISALIGNED0 : out std_ulogic; + RXCHANISALIGNED1 : out std_ulogic; + RXCHANREALIGN0 : out std_ulogic; + RXCHANREALIGN1 : out std_ulogic; + RXCHARISCOMMA0 : out std_logic_vector(3 downto 0); + RXCHARISCOMMA1 : out std_logic_vector(3 downto 0); + RXCHARISK0 : out std_logic_vector(3 downto 0); + RXCHARISK1 : out std_logic_vector(3 downto 0); + RXCHBONDO0 : out std_logic_vector(3 downto 0); + RXCHBONDO1 : out std_logic_vector(3 downto 0); + RXCLKCORCNT0 : out std_logic_vector(2 downto 0); + RXCLKCORCNT1 : out std_logic_vector(2 downto 0); + RXCOMMADET0 : out std_ulogic; + RXCOMMADET1 : out std_ulogic; + RXDATA0 : out std_logic_vector(31 downto 0); + RXDATA1 : out std_logic_vector(31 downto 0); + RXDATAVALID0 : out std_ulogic; + RXDATAVALID1 : out std_ulogic; + RXDISPERR0 : out std_logic_vector(3 downto 0); + RXDISPERR1 : out std_logic_vector(3 downto 0); + RXELECIDLE0 : out std_ulogic; + RXELECIDLE1 : out std_ulogic; + RXHEADER0 : out std_logic_vector(2 downto 0); + RXHEADER1 : out std_logic_vector(2 downto 0); + RXHEADERVALID0 : out std_ulogic; + RXHEADERVALID1 : out std_ulogic; + RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); + RXNOTINTABLE0 : out std_logic_vector(3 downto 0); + RXNOTINTABLE1 : out std_logic_vector(3 downto 0); + RXOVERSAMPLEERR0 : out std_ulogic; + RXOVERSAMPLEERR1 : out std_ulogic; + RXPRBSERR0 : out std_ulogic; + RXPRBSERR1 : out std_ulogic; + RXRECCLK0 : out std_ulogic; + RXRECCLK1 : out std_ulogic; + RXRUNDISP0 : out std_logic_vector(3 downto 0); + RXRUNDISP1 : out std_logic_vector(3 downto 0); + RXSTARTOFSEQ0 : out std_ulogic; + RXSTARTOFSEQ1 : out std_ulogic; + RXSTATUS0 : out std_logic_vector(2 downto 0); + RXSTATUS1 : out std_logic_vector(2 downto 0); + RXVALID0 : out std_ulogic; + RXVALID1 : out std_ulogic; + TXBUFSTATUS0 : out std_logic_vector(1 downto 0); + TXBUFSTATUS1 : out std_logic_vector(1 downto 0); + TXGEARBOXREADY0 : out std_ulogic; + TXGEARBOXREADY1 : out std_ulogic; + TXKERR0 : out std_logic_vector(3 downto 0); + TXKERR1 : out std_logic_vector(3 downto 0); + TXN0 : out std_ulogic; + TXN1 : out std_ulogic; + TXOUTCLK0 : out std_ulogic; + TXOUTCLK1 : out std_ulogic; + TXP0 : out std_ulogic; + TXP1 : out std_ulogic; + TXRUNDISP0 : out std_logic_vector(3 downto 0); + TXRUNDISP1 : out std_logic_vector(3 downto 0); + + CLKIN : in std_ulogic; + DADDR : in std_logic_vector(6 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DFECLKDLYADJ0 : in std_logic_vector(5 downto 0); + DFECLKDLYADJ1 : in std_logic_vector(5 downto 0); + DFETAP10 : in std_logic_vector(4 downto 0); + DFETAP11 : in std_logic_vector(4 downto 0); + DFETAP20 : in std_logic_vector(4 downto 0); + DFETAP21 : in std_logic_vector(4 downto 0); + DFETAP30 : in std_logic_vector(3 downto 0); + DFETAP31 : in std_logic_vector(3 downto 0); + DFETAP40 : in std_logic_vector(3 downto 0); + DFETAP41 : in std_logic_vector(3 downto 0); + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + GTXRESET : in std_ulogic; + GTXTEST : in std_logic_vector(13 downto 0); + INTDATAWIDTH : in std_ulogic; + LOOPBACK0 : in std_logic_vector(2 downto 0); + LOOPBACK1 : in std_logic_vector(2 downto 0); + PLLLKDETEN : in std_ulogic; + PLLPOWERDOWN : in std_ulogic; + PRBSCNTRESET0 : in std_ulogic; + PRBSCNTRESET1 : in std_ulogic; + REFCLKPWRDNB : in std_ulogic; + RXBUFRESET0 : in std_ulogic; + RXBUFRESET1 : in std_ulogic; + RXCDRRESET0 : in std_ulogic; + RXCDRRESET1 : in std_ulogic; + RXCHBONDI0 : in std_logic_vector(3 downto 0); + RXCHBONDI1 : in std_logic_vector(3 downto 0); + RXCOMMADETUSE0 : in std_ulogic; + RXCOMMADETUSE1 : in std_ulogic; + RXDATAWIDTH0 : in std_logic_vector(1 downto 0); + RXDATAWIDTH1 : in std_logic_vector(1 downto 0); + RXDEC8B10BUSE0 : in std_ulogic; + RXDEC8B10BUSE1 : in std_ulogic; + RXENCHANSYNC0 : in std_ulogic; + RXENCHANSYNC1 : in std_ulogic; + RXENEQB0 : in std_ulogic; + RXENEQB1 : in std_ulogic; + RXENMCOMMAALIGN0 : in std_ulogic; + RXENMCOMMAALIGN1 : in std_ulogic; + RXENPCOMMAALIGN0 : in std_ulogic; + RXENPCOMMAALIGN1 : in std_ulogic; + RXENPMAPHASEALIGN0 : in std_ulogic; + RXENPMAPHASEALIGN1 : in std_ulogic; + RXENPRBSTST0 : in std_logic_vector(1 downto 0); + RXENPRBSTST1 : in std_logic_vector(1 downto 0); + RXENSAMPLEALIGN0 : in std_ulogic; + RXENSAMPLEALIGN1 : in std_ulogic; + RXEQMIX0 : in std_logic_vector(1 downto 0); + RXEQMIX1 : in std_logic_vector(1 downto 0); + RXEQPOLE0 : in std_logic_vector(3 downto 0); + RXEQPOLE1 : in std_logic_vector(3 downto 0); + RXGEARBOXSLIP0 : in std_ulogic; + RXGEARBOXSLIP1 : in std_ulogic; + RXN0 : in std_ulogic; + RXN1 : in std_ulogic; + RXP0 : in std_ulogic; + RXP1 : in std_ulogic; + RXPMASETPHASE0 : in std_ulogic; + RXPMASETPHASE1 : in std_ulogic; + RXPOLARITY0 : in std_ulogic; + RXPOLARITY1 : in std_ulogic; + RXPOWERDOWN0 : in std_logic_vector(1 downto 0); + RXPOWERDOWN1 : in std_logic_vector(1 downto 0); + RXRESET0 : in std_ulogic; + RXRESET1 : in std_ulogic; + RXSLIDE0 : in std_ulogic; + RXSLIDE1 : in std_ulogic; + RXUSRCLK0 : in std_ulogic; + RXUSRCLK1 : in std_ulogic; + RXUSRCLK20 : in std_ulogic; + RXUSRCLK21 : in std_ulogic; + TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXBYPASS8B10B0 : in std_logic_vector(3 downto 0); + TXBYPASS8B10B1 : in std_logic_vector(3 downto 0); + TXCHARDISPMODE0 : in std_logic_vector(3 downto 0); + TXCHARDISPMODE1 : in std_logic_vector(3 downto 0); + TXCHARDISPVAL0 : in std_logic_vector(3 downto 0); + TXCHARDISPVAL1 : in std_logic_vector(3 downto 0); + TXCHARISK0 : in std_logic_vector(3 downto 0); + TXCHARISK1 : in std_logic_vector(3 downto 0); + TXCOMSTART0 : in std_ulogic; + TXCOMSTART1 : in std_ulogic; + TXCOMTYPE0 : in std_ulogic; + TXCOMTYPE1 : in std_ulogic; + TXDATA0 : in std_logic_vector(31 downto 0); + TXDATA1 : in std_logic_vector(31 downto 0); + TXDATAWIDTH0 : in std_logic_vector(1 downto 0); + TXDATAWIDTH1 : in std_logic_vector(1 downto 0); + TXDETECTRX0 : in std_ulogic; + TXDETECTRX1 : in std_ulogic; + TXDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXELECIDLE0 : in std_ulogic; + TXELECIDLE1 : in std_ulogic; + TXENC8B10BUSE0 : in std_ulogic; + TXENC8B10BUSE1 : in std_ulogic; + TXENPMAPHASEALIGN0 : in std_ulogic; + TXENPMAPHASEALIGN1 : in std_ulogic; + TXENPRBSTST0 : in std_logic_vector(1 downto 0); + TXENPRBSTST1 : in std_logic_vector(1 downto 0); + TXHEADER0 : in std_logic_vector(2 downto 0); + TXHEADER1 : in std_logic_vector(2 downto 0); + TXINHIBIT0 : in std_ulogic; + TXINHIBIT1 : in std_ulogic; + TXPMASETPHASE0 : in std_ulogic; + TXPMASETPHASE1 : in std_ulogic; + TXPOLARITY0 : in std_ulogic; + TXPOLARITY1 : in std_ulogic; + TXPOWERDOWN0 : in std_logic_vector(1 downto 0); + TXPOWERDOWN1 : in std_logic_vector(1 downto 0); + TXPREEMPHASIS0 : in std_logic_vector(3 downto 0); + TXPREEMPHASIS1 : in std_logic_vector(3 downto 0); + TXRESET0 : in std_ulogic; + TXRESET1 : in std_ulogic; + TXSEQUENCE0 : in std_logic_vector(6 downto 0); + TXSEQUENCE1 : in std_logic_vector(6 downto 0); + TXSTARTSEQ0 : in std_ulogic; + TXSTARTSEQ1 : in std_ulogic; + TXUSRCLK0 : in std_ulogic; + TXUSRCLK1 : in std_ulogic; + TXUSRCLK20 : in std_ulogic; + TXUSRCLK21 : in std_ulogic + ); +end GTX_DUAL; + +architecture GTX_DUAL_V of GTX_DUAL is + + component GTX_DUAL_SWIFT + port ( + DFECLKDLYADJMONITOR0 : out std_logic_vector(5 downto 0); + DFECLKDLYADJMONITOR1 : out std_logic_vector(5 downto 0); + DFEEYEDACMONITOR0 : out std_logic_vector(4 downto 0); + DFEEYEDACMONITOR1 : out std_logic_vector(4 downto 0); + DFESENSCAL0 : out std_logic_vector(2 downto 0); + DFESENSCAL1 : out std_logic_vector(2 downto 0); + DFETAP1MONITOR0 : out std_logic_vector(4 downto 0); + DFETAP1MONITOR1 : out std_logic_vector(4 downto 0); + DFETAP2MONITOR0 : out std_logic_vector(4 downto 0); + DFETAP2MONITOR1 : out std_logic_vector(4 downto 0); + DFETAP3MONITOR0 : out std_logic_vector(3 downto 0); + DFETAP3MONITOR1 : out std_logic_vector(3 downto 0); + DFETAP4MONITOR0 : out std_logic_vector(3 downto 0); + DFETAP4MONITOR1 : out std_logic_vector(3 downto 0); + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + PHYSTATUS0 : out std_ulogic; + PHYSTATUS1 : out std_ulogic; + PLLLKDET : out std_ulogic; + REFCLKOUT : out std_ulogic; + RESETDONE0 : out std_ulogic; + RESETDONE1 : out std_ulogic; + RXBUFSTATUS0 : out std_logic_vector(2 downto 0); + RXBUFSTATUS1 : out std_logic_vector(2 downto 0); + RXBYTEISALIGNED0 : out std_ulogic; + RXBYTEISALIGNED1 : out std_ulogic; + RXBYTEREALIGN0 : out std_ulogic; + RXBYTEREALIGN1 : out std_ulogic; + RXCHANBONDSEQ0 : out std_ulogic; + RXCHANBONDSEQ1 : out std_ulogic; + RXCHANISALIGNED0 : out std_ulogic; + RXCHANISALIGNED1 : out std_ulogic; + RXCHANREALIGN0 : out std_ulogic; + RXCHANREALIGN1 : out std_ulogic; + RXCHARISCOMMA0 : out std_logic_vector(3 downto 0); + RXCHARISCOMMA1 : out std_logic_vector(3 downto 0); + RXCHARISK0 : out std_logic_vector(3 downto 0); + RXCHARISK1 : out std_logic_vector(3 downto 0); + RXCHBONDO0 : out std_logic_vector(3 downto 0); + RXCHBONDO1 : out std_logic_vector(3 downto 0); + RXCLKCORCNT0 : out std_logic_vector(2 downto 0); + RXCLKCORCNT1 : out std_logic_vector(2 downto 0); + RXCOMMADET0 : out std_ulogic; + RXCOMMADET1 : out std_ulogic; + RXDATA0 : out std_logic_vector(31 downto 0); + RXDATA1 : out std_logic_vector(31 downto 0); + RXDATAVALID0 : out std_ulogic; + RXDATAVALID1 : out std_ulogic; + RXDISPERR0 : out std_logic_vector(3 downto 0); + RXDISPERR1 : out std_logic_vector(3 downto 0); + RXELECIDLE0 : out std_ulogic; + RXELECIDLE1 : out std_ulogic; + RXHEADER0 : out std_logic_vector(2 downto 0); + RXHEADER1 : out std_logic_vector(2 downto 0); + RXHEADERVALID0 : out std_ulogic; + RXHEADERVALID1 : out std_ulogic; + RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); + RXNOTINTABLE0 : out std_logic_vector(3 downto 0); + RXNOTINTABLE1 : out std_logic_vector(3 downto 0); + RXOVERSAMPLEERR0 : out std_ulogic; + RXOVERSAMPLEERR1 : out std_ulogic; + RXPRBSERR0 : out std_ulogic; + RXPRBSERR1 : out std_ulogic; + RXRECCLK0 : out std_ulogic; + RXRECCLK1 : out std_ulogic; + RXRUNDISP0 : out std_logic_vector(3 downto 0); + RXRUNDISP1 : out std_logic_vector(3 downto 0); + RXSTARTOFSEQ0 : out std_ulogic; + RXSTARTOFSEQ1 : out std_ulogic; + RXSTATUS0 : out std_logic_vector(2 downto 0); + RXSTATUS1 : out std_logic_vector(2 downto 0); + RXVALID0 : out std_ulogic; + RXVALID1 : out std_ulogic; + TXBUFSTATUS0 : out std_logic_vector(1 downto 0); + TXBUFSTATUS1 : out std_logic_vector(1 downto 0); + TXGEARBOXREADY0 : out std_ulogic; + TXGEARBOXREADY1 : out std_ulogic; + TXKERR0 : out std_logic_vector(3 downto 0); + TXKERR1 : out std_logic_vector(3 downto 0); + TXN0 : out std_ulogic; + TXN1 : out std_ulogic; + TXOUTCLK0 : out std_ulogic; + TXOUTCLK1 : out std_ulogic; + TXP0 : out std_ulogic; + TXP1 : out std_ulogic; + TXRUNDISP0 : out std_logic_vector(3 downto 0); + TXRUNDISP1 : out std_logic_vector(3 downto 0); + + CLKIN : in std_ulogic; + DADDR : in std_logic_vector(6 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DFECLKDLYADJ0 : in std_logic_vector(5 downto 0); + DFECLKDLYADJ1 : in std_logic_vector(5 downto 0); + DFETAP10 : in std_logic_vector(4 downto 0); + DFETAP11 : in std_logic_vector(4 downto 0); + DFETAP20 : in std_logic_vector(4 downto 0); + DFETAP21 : in std_logic_vector(4 downto 0); + DFETAP30 : in std_logic_vector(3 downto 0); + DFETAP31 : in std_logic_vector(3 downto 0); + DFETAP40 : in std_logic_vector(3 downto 0); + DFETAP41 : in std_logic_vector(3 downto 0); + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + GSR : in std_ulogic; + GTXRESET : in std_ulogic; + GTXTEST : in std_logic_vector(13 downto 0); + INTDATAWIDTH : in std_ulogic; + LOOPBACK0 : in std_logic_vector(2 downto 0); + LOOPBACK1 : in std_logic_vector(2 downto 0); + PLLLKDETEN : in std_ulogic; + PLLPOWERDOWN : in std_ulogic; + PRBSCNTRESET0 : in std_ulogic; + PRBSCNTRESET1 : in std_ulogic; + REFCLKPWRDNB : in std_ulogic; + RXBUFRESET0 : in std_ulogic; + RXBUFRESET1 : in std_ulogic; + RXCDRRESET0 : in std_ulogic; + RXCDRRESET1 : in std_ulogic; + RXCHBONDI0 : in std_logic_vector(3 downto 0); + RXCHBONDI1 : in std_logic_vector(3 downto 0); + RXCOMMADETUSE0 : in std_ulogic; + RXCOMMADETUSE1 : in std_ulogic; + RXDATAWIDTH0 : in std_logic_vector(1 downto 0); + RXDATAWIDTH1 : in std_logic_vector(1 downto 0); + RXDEC8B10BUSE0 : in std_ulogic; + RXDEC8B10BUSE1 : in std_ulogic; + RXENCHANSYNC0 : in std_ulogic; + RXENCHANSYNC1 : in std_ulogic; + RXENEQB0 : in std_ulogic; + RXENEQB1 : in std_ulogic; + RXENMCOMMAALIGN0 : in std_ulogic; + RXENMCOMMAALIGN1 : in std_ulogic; + RXENPCOMMAALIGN0 : in std_ulogic; + RXENPCOMMAALIGN1 : in std_ulogic; + RXENPMAPHASEALIGN0 : in std_ulogic; + RXENPMAPHASEALIGN1 : in std_ulogic; + RXENPRBSTST0 : in std_logic_vector(1 downto 0); + RXENPRBSTST1 : in std_logic_vector(1 downto 0); + RXENSAMPLEALIGN0 : in std_ulogic; + RXENSAMPLEALIGN1 : in std_ulogic; + RXEQMIX0 : in std_logic_vector(1 downto 0); + RXEQMIX1 : in std_logic_vector(1 downto 0); + RXEQPOLE0 : in std_logic_vector(3 downto 0); + RXEQPOLE1 : in std_logic_vector(3 downto 0); + RXGEARBOXSLIP0 : in std_ulogic; + RXGEARBOXSLIP1 : in std_ulogic; + RXN0 : in std_ulogic; + RXN1 : in std_ulogic; + RXP0 : in std_ulogic; + RXP1 : in std_ulogic; + RXPMASETPHASE0 : in std_ulogic; + RXPMASETPHASE1 : in std_ulogic; + RXPOLARITY0 : in std_ulogic; + RXPOLARITY1 : in std_ulogic; + RXPOWERDOWN0 : in std_logic_vector(1 downto 0); + RXPOWERDOWN1 : in std_logic_vector(1 downto 0); + RXRESET0 : in std_ulogic; + RXRESET1 : in std_ulogic; + RXSLIDE0 : in std_ulogic; + RXSLIDE1 : in std_ulogic; + RXUSRCLK0 : in std_ulogic; + RXUSRCLK1 : in std_ulogic; + RXUSRCLK20 : in std_ulogic; + RXUSRCLK21 : in std_ulogic; + TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXBYPASS8B10B0 : in std_logic_vector(3 downto 0); + TXBYPASS8B10B1 : in std_logic_vector(3 downto 0); + TXCHARDISPMODE0 : in std_logic_vector(3 downto 0); + TXCHARDISPMODE1 : in std_logic_vector(3 downto 0); + TXCHARDISPVAL0 : in std_logic_vector(3 downto 0); + TXCHARDISPVAL1 : in std_logic_vector(3 downto 0); + TXCHARISK0 : in std_logic_vector(3 downto 0); + TXCHARISK1 : in std_logic_vector(3 downto 0); + TXCOMSTART0 : in std_ulogic; + TXCOMSTART1 : in std_ulogic; + TXCOMTYPE0 : in std_ulogic; + TXCOMTYPE1 : in std_ulogic; + TXDATA0 : in std_logic_vector(31 downto 0); + TXDATA1 : in std_logic_vector(31 downto 0); + TXDATAWIDTH0 : in std_logic_vector(1 downto 0); + TXDATAWIDTH1 : in std_logic_vector(1 downto 0); + TXDETECTRX0 : in std_ulogic; + TXDETECTRX1 : in std_ulogic; + TXDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXELECIDLE0 : in std_ulogic; + TXELECIDLE1 : in std_ulogic; + TXENC8B10BUSE0 : in std_ulogic; + TXENC8B10BUSE1 : in std_ulogic; + TXENPMAPHASEALIGN0 : in std_ulogic; + TXENPMAPHASEALIGN1 : in std_ulogic; + TXENPRBSTST0 : in std_logic_vector(1 downto 0); + TXENPRBSTST1 : in std_logic_vector(1 downto 0); + TXHEADER0 : in std_logic_vector(2 downto 0); + TXHEADER1 : in std_logic_vector(2 downto 0); + TXINHIBIT0 : in std_ulogic; + TXINHIBIT1 : in std_ulogic; + TXPMASETPHASE0 : in std_ulogic; + TXPMASETPHASE1 : in std_ulogic; + TXPOLARITY0 : in std_ulogic; + TXPOLARITY1 : in std_ulogic; + TXPOWERDOWN0 : in std_logic_vector(1 downto 0); + TXPOWERDOWN1 : in std_logic_vector(1 downto 0); + TXPREEMPHASIS0 : in std_logic_vector(3 downto 0); + TXPREEMPHASIS1 : in std_logic_vector(3 downto 0); + TXRESET0 : in std_ulogic; + TXRESET1 : in std_ulogic; + TXSEQUENCE0 : in std_logic_vector(6 downto 0); + TXSEQUENCE1 : in std_logic_vector(6 downto 0); + TXSTARTSEQ0 : in std_ulogic; + TXSTARTSEQ1 : in std_ulogic; + TXUSRCLK0 : in std_ulogic; + TXUSRCLK1 : in std_ulogic; + TXUSRCLK20 : in std_ulogic; + TXUSRCLK21 : in std_ulogic; + + STEPPING : in std_ulogic; + AC_CAP_DIS_0 : in std_ulogic; + AC_CAP_DIS_1 : in std_ulogic; + ALIGN_COMMA_WORD_0 : in std_ulogic; + ALIGN_COMMA_WORD_1 : in std_ulogic; + CB2_INH_CC_PERIOD_0 : in std_logic_vector(3 downto 0); + CB2_INH_CC_PERIOD_1 : in std_logic_vector(3 downto 0); + CDR_PH_ADJ_TIME : in std_logic_vector(4 downto 0); + CHAN_BOND_1_MAX_SKEW_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_1_MAX_SKEW_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_2_MAX_SKEW_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_2_MAX_SKEW_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_KEEP_ALIGN_0 : in std_ulogic; + CHAN_BOND_KEEP_ALIGN_1 : in std_ulogic; + CHAN_BOND_LEVEL_0 : in std_logic_vector(2 downto 0); + CHAN_BOND_LEVEL_1 : in std_logic_vector(2 downto 0); + CHAN_BOND_MODE_0 : in std_logic_vector(1 downto 0); + CHAN_BOND_MODE_1 : in std_logic_vector(1 downto 0); + CHAN_BOND_SEQ_1_1_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_1_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_2_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_2_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_3_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_3_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_4_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_4_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_1_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_1_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_2_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_2_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_3_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_3_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_4_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_4_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_USE_0 : in std_ulogic; + CHAN_BOND_SEQ_2_USE_1 : in std_ulogic; + CHAN_BOND_SEQ_LEN_0 : in std_logic_vector(1 downto 0); + CHAN_BOND_SEQ_LEN_1 : in std_logic_vector(1 downto 0); + CLK25_DIVIDER : in std_logic_vector(2 downto 0); + CLKINDC_B : in std_ulogic; + CLKRCV_TRST : in std_ulogic; + CLK_CORRECT_USE_0 : in std_ulogic; + CLK_CORRECT_USE_1 : in std_ulogic; + CLK_COR_ADJ_LEN_0 : in std_logic_vector(1 downto 0); + CLK_COR_ADJ_LEN_1 : in std_logic_vector(1 downto 0); + CLK_COR_DET_LEN_0 : in std_logic_vector(1 downto 0); + CLK_COR_DET_LEN_1 : in std_logic_vector(1 downto 0); + CLK_COR_INSERT_IDLE_FLAG_0 : in std_ulogic; + CLK_COR_INSERT_IDLE_FLAG_1 : in std_ulogic; + CLK_COR_KEEP_IDLE_0 : in std_ulogic; + CLK_COR_KEEP_IDLE_1 : in std_ulogic; + CLK_COR_MAX_LAT_0 : in std_logic_vector(5 downto 0); + CLK_COR_MAX_LAT_1 : in std_logic_vector(5 downto 0); + CLK_COR_MIN_LAT_0 : in std_logic_vector(5 downto 0); + CLK_COR_MIN_LAT_1 : in std_logic_vector(5 downto 0); + CLK_COR_PRECEDENCE_0 : in std_ulogic; + CLK_COR_PRECEDENCE_1 : in std_ulogic; + CLK_COR_REPEAT_WAIT_0 : in std_logic_vector(4 downto 0); + CLK_COR_REPEAT_WAIT_1 : in std_logic_vector(4 downto 0); + CLK_COR_SEQ_1_1_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_1_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_2_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_2_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_3_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_3_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_4_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_4_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_1_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_1_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_2_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_2_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_3_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_3_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_4_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_4_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_USE_0 : in std_ulogic; + CLK_COR_SEQ_2_USE_1 : in std_ulogic; + CM_TRIM_0 : in std_logic_vector(1 downto 0); + CM_TRIM_1 : in std_logic_vector(1 downto 0); + COMMA_10B_ENABLE_0 : in std_logic_vector(9 downto 0); + COMMA_10B_ENABLE_1 : in std_logic_vector(9 downto 0); + COMMA_DOUBLE_0 : in std_ulogic; + COMMA_DOUBLE_1 : in std_ulogic; + COM_BURST_VAL_0 : in std_logic_vector(3 downto 0); + COM_BURST_VAL_1 : in std_logic_vector(3 downto 0); + DEC_MCOMMA_DETECT_0 : in std_ulogic; + DEC_MCOMMA_DETECT_1 : in std_ulogic; + DEC_PCOMMA_DETECT_0 : in std_ulogic; + DEC_PCOMMA_DETECT_1 : in std_ulogic; + DEC_VALID_COMMA_ONLY_0 : in std_ulogic; + DEC_VALID_COMMA_ONLY_1 : in std_ulogic; + DFE_CAL_TIME : in std_logic_vector(4 downto 0); + DFE_CFG_0 : in std_logic_vector(9 downto 0); + DFE_CFG_1 : in std_logic_vector(9 downto 0); + GEARBOX_ENDEC_0 : in std_logic_vector(2 downto 0); + GEARBOX_ENDEC_1 : in std_logic_vector(2 downto 0); + MCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); + MCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); + MCOMMA_DETECT_0 : in std_ulogic; + MCOMMA_DETECT_1 : in std_ulogic; + OOBDETECT_THRESHOLD_0 : in std_logic_vector(2 downto 0); + OOBDETECT_THRESHOLD_1 : in std_logic_vector(2 downto 0); + OOB_CLK_DIVIDER : in std_logic_vector(2 downto 0); + OVERSAMPLE_MODE : in std_ulogic; + PCI_EXPRESS_MODE_0 : in std_ulogic; + PCI_EXPRESS_MODE_1 : in std_ulogic; + PCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); + PCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); + PCOMMA_DETECT_0 : in std_ulogic; + PCOMMA_DETECT_1 : in std_ulogic; + PLL_COM_CFG : in std_logic_vector(23 downto 0); + PLL_CP_CFG : in std_logic_vector(7 downto 0); + PLL_DIVSEL_FB : in std_logic_vector(4 downto 0); + PLL_DIVSEL_REF : in std_logic_vector(5 downto 0); + PLL_FB_DCCEN : in std_ulogic; + PLL_LKDET_CFG : in std_logic_vector(2 downto 0); + PLL_RXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); + PLL_RXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); + PLL_SATA_0 : in std_ulogic; + PLL_SATA_1 : in std_ulogic; + PLL_TDCC_CFG : in std_logic_vector(2 downto 0); + PLL_TXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); + PLL_TXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); + PMA_CDR_SCAN_0 : in std_logic_vector(26 downto 0); + PMA_CDR_SCAN_1 : in std_logic_vector(26 downto 0); + PMA_COM_CFG : in std_logic_vector(68 downto 0); + PMA_RXSYNC_CFG_0 : in std_logic_vector(6 downto 0); + PMA_RXSYNC_CFG_1 : in std_logic_vector(6 downto 0); + PMA_RX_CFG_0 : in std_logic_vector(24 downto 0); + PMA_RX_CFG_1 : in std_logic_vector(24 downto 0); + PMA_TX_CFG_0 : in std_logic_vector(19 downto 0); + PMA_TX_CFG_1 : in std_logic_vector(19 downto 0); + PRBS_ERR_THRESHOLD_0 : in std_logic_vector(31 downto 0); + PRBS_ERR_THRESHOLD_1 : in std_logic_vector(31 downto 0); + RCV_TERM_GND_0 : in std_ulogic; + RCV_TERM_GND_1 : in std_ulogic; + RCV_TERM_VTTRX_0 : in std_ulogic; + RCV_TERM_VTTRX_1 : in std_ulogic; + RXGEARBOX_USE_0 : in std_ulogic; + RXGEARBOX_USE_1 : in std_ulogic; + RX_BUFFER_USE_0 : in std_ulogic; + RX_BUFFER_USE_1 : in std_ulogic; + RX_DECODE_SEQ_MATCH_0 : in std_ulogic; + RX_DECODE_SEQ_MATCH_1 : in std_ulogic; + RX_EN_IDLE_HOLD_CDR : in std_ulogic; + RX_EN_IDLE_HOLD_DFE_0 : in std_ulogic; + RX_EN_IDLE_HOLD_DFE_1 : in std_ulogic; + RX_EN_IDLE_RESET_BUF_0 : in std_ulogic; + RX_EN_IDLE_RESET_BUF_1 : in std_ulogic; + RX_EN_IDLE_RESET_FR : in std_ulogic; + RX_EN_IDLE_RESET_PH : in std_ulogic; + RX_IDLE_HI_CNT_0 : in std_logic_vector(3 downto 0); + RX_IDLE_HI_CNT_1 : in std_logic_vector(3 downto 0); + RX_IDLE_LO_CNT_0 : in std_logic_vector(3 downto 0); + RX_IDLE_LO_CNT_1 : in std_logic_vector(3 downto 0); + RX_LOSS_OF_SYNC_FSM_0 : in std_ulogic; + RX_LOSS_OF_SYNC_FSM_1 : in std_ulogic; + RX_LOS_INVALID_INCR_0 : in std_logic_vector(2 downto 0); + RX_LOS_INVALID_INCR_1 : in std_logic_vector(2 downto 0); + RX_LOS_THRESHOLD_0 : in std_logic_vector(2 downto 0); + RX_LOS_THRESHOLD_1 : in std_logic_vector(2 downto 0); + RX_SLIDE_MODE_0 : in std_ulogic; + RX_SLIDE_MODE_1 : in std_ulogic; + RX_STATUS_FMT_0 : in std_ulogic; + RX_STATUS_FMT_1 : in std_ulogic; + RX_XCLK_SEL_0 : in std_ulogic; + RX_XCLK_SEL_1 : in std_ulogic; + SATA_BURST_VAL_0 : in std_logic_vector(2 downto 0); + SATA_BURST_VAL_1 : in std_logic_vector(2 downto 0); + SATA_IDLE_VAL_0 : in std_logic_vector(2 downto 0); + SATA_IDLE_VAL_1 : in std_logic_vector(2 downto 0); + SATA_MAX_BURST_0 : in std_logic_vector(5 downto 0); + SATA_MAX_BURST_1 : in std_logic_vector(5 downto 0); + SATA_MAX_INIT_0 : in std_logic_vector(5 downto 0); + SATA_MAX_INIT_1 : in std_logic_vector(5 downto 0); + SATA_MAX_WAKE_0 : in std_logic_vector(5 downto 0); + SATA_MAX_WAKE_1 : in std_logic_vector(5 downto 0); + SATA_MIN_BURST_0 : in std_logic_vector(5 downto 0); + SATA_MIN_BURST_1 : in std_logic_vector(5 downto 0); + SATA_MIN_INIT_0 : in std_logic_vector(5 downto 0); + SATA_MIN_INIT_1 : in std_logic_vector(5 downto 0); + SATA_MIN_WAKE_0 : in std_logic_vector(5 downto 0); + SATA_MIN_WAKE_1 : in std_logic_vector(5 downto 0); + SIM_GTXRESET_SPEEDUP : in std_ulogic; + SIM_PLL_PERDIV2 : in std_logic_vector(8 downto 0); + SIM_RECEIVER_DETECT_PASS_0 : in std_ulogic; + SIM_RECEIVER_DETECT_PASS_1 : in std_ulogic; + TERMINATION_CTRL : in std_logic_vector(4 downto 0); + TERMINATION_IMP_0 : in std_ulogic; + TERMINATION_IMP_1 : in std_ulogic; + TERMINATION_OVRD : in std_ulogic; + TRANS_TIME_FROM_P2_0 : in std_logic_vector(11 downto 0); + TRANS_TIME_FROM_P2_1 : in std_logic_vector(11 downto 0); + TRANS_TIME_NON_P2_0 : in std_logic_vector(7 downto 0); + TRANS_TIME_NON_P2_1 : in std_logic_vector(7 downto 0); + TRANS_TIME_TO_P2_0 : in std_logic_vector(9 downto 0); + TRANS_TIME_TO_P2_1 : in std_logic_vector(9 downto 0); + TXGEARBOX_USE_0 : in std_ulogic; + TXGEARBOX_USE_1 : in std_ulogic; + TXRX_INVERT_0 : in std_logic_vector(2 downto 0); + TXRX_INVERT_1 : in std_logic_vector(2 downto 0); + TX_BUFFER_USE_0 : in std_ulogic; + TX_BUFFER_USE_1 : in std_ulogic; + TX_DETECT_RX_CFG_0 : in std_logic_vector(13 downto 0); + TX_DETECT_RX_CFG_1 : in std_logic_vector(13 downto 0); + TX_IDLE_DELAY_0 : in std_logic_vector(2 downto 0); + TX_IDLE_DELAY_1 : in std_logic_vector(2 downto 0); + TX_XCLK_SEL_0 : in std_ulogic; + TX_XCLK_SEL_1 : in std_ulogic + ); + end component; + + component GTX_DUAL_FAST + port ( + DFECLKDLYADJMONITOR0 : out std_logic_vector(5 downto 0); + DFECLKDLYADJMONITOR1 : out std_logic_vector(5 downto 0); + DFEEYEDACMONITOR0 : out std_logic_vector(4 downto 0); + DFEEYEDACMONITOR1 : out std_logic_vector(4 downto 0); + DFESENSCAL0 : out std_logic_vector(2 downto 0); + DFESENSCAL1 : out std_logic_vector(2 downto 0); + DFETAP1MONITOR0 : out std_logic_vector(4 downto 0); + DFETAP1MONITOR1 : out std_logic_vector(4 downto 0); + DFETAP2MONITOR0 : out std_logic_vector(4 downto 0); + DFETAP2MONITOR1 : out std_logic_vector(4 downto 0); + DFETAP3MONITOR0 : out std_logic_vector(3 downto 0); + DFETAP3MONITOR1 : out std_logic_vector(3 downto 0); + DFETAP4MONITOR0 : out std_logic_vector(3 downto 0); + DFETAP4MONITOR1 : out std_logic_vector(3 downto 0); + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + PHYSTATUS0 : out std_ulogic; + PHYSTATUS1 : out std_ulogic; + PLLLKDET : out std_ulogic; + REFCLKOUT : out std_ulogic; + RESETDONE0 : out std_ulogic; + RESETDONE1 : out std_ulogic; + RXBUFSTATUS0 : out std_logic_vector(2 downto 0); + RXBUFSTATUS1 : out std_logic_vector(2 downto 0); + RXBYTEISALIGNED0 : out std_ulogic; + RXBYTEISALIGNED1 : out std_ulogic; + RXBYTEREALIGN0 : out std_ulogic; + RXBYTEREALIGN1 : out std_ulogic; + RXCHANBONDSEQ0 : out std_ulogic; + RXCHANBONDSEQ1 : out std_ulogic; + RXCHANISALIGNED0 : out std_ulogic; + RXCHANISALIGNED1 : out std_ulogic; + RXCHANREALIGN0 : out std_ulogic; + RXCHANREALIGN1 : out std_ulogic; + RXCHARISCOMMA0 : out std_logic_vector(3 downto 0); + RXCHARISCOMMA1 : out std_logic_vector(3 downto 0); + RXCHARISK0 : out std_logic_vector(3 downto 0); + RXCHARISK1 : out std_logic_vector(3 downto 0); + RXCHBONDO0 : out std_logic_vector(3 downto 0); + RXCHBONDO1 : out std_logic_vector(3 downto 0); + RXCLKCORCNT0 : out std_logic_vector(2 downto 0); + RXCLKCORCNT1 : out std_logic_vector(2 downto 0); + RXCOMMADET0 : out std_ulogic; + RXCOMMADET1 : out std_ulogic; + RXDATA0 : out std_logic_vector(31 downto 0); + RXDATA1 : out std_logic_vector(31 downto 0); + RXDATAVALID0 : out std_ulogic; + RXDATAVALID1 : out std_ulogic; + RXDISPERR0 : out std_logic_vector(3 downto 0); + RXDISPERR1 : out std_logic_vector(3 downto 0); + RXELECIDLE0 : out std_ulogic; + RXELECIDLE1 : out std_ulogic; + RXHEADER0 : out std_logic_vector(2 downto 0); + RXHEADER1 : out std_logic_vector(2 downto 0); + RXHEADERVALID0 : out std_ulogic; + RXHEADERVALID1 : out std_ulogic; + RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); + RXNOTINTABLE0 : out std_logic_vector(3 downto 0); + RXNOTINTABLE1 : out std_logic_vector(3 downto 0); + RXOVERSAMPLEERR0 : out std_ulogic; + RXOVERSAMPLEERR1 : out std_ulogic; + RXPRBSERR0 : out std_ulogic; + RXPRBSERR1 : out std_ulogic; + RXRECCLK0 : out std_ulogic; + RXRECCLK1 : out std_ulogic; + RXRUNDISP0 : out std_logic_vector(3 downto 0); + RXRUNDISP1 : out std_logic_vector(3 downto 0); + RXSTARTOFSEQ0 : out std_ulogic; + RXSTARTOFSEQ1 : out std_ulogic; + RXSTATUS0 : out std_logic_vector(2 downto 0); + RXSTATUS1 : out std_logic_vector(2 downto 0); + RXVALID0 : out std_ulogic; + RXVALID1 : out std_ulogic; + TXBUFSTATUS0 : out std_logic_vector(1 downto 0); + TXBUFSTATUS1 : out std_logic_vector(1 downto 0); + TXGEARBOXREADY0 : out std_ulogic; + TXGEARBOXREADY1 : out std_ulogic; + TXKERR0 : out std_logic_vector(3 downto 0); + TXKERR1 : out std_logic_vector(3 downto 0); + TXN0 : out std_ulogic; + TXN1 : out std_ulogic; + TXOUTCLK0 : out std_ulogic; + TXOUTCLK1 : out std_ulogic; + TXP0 : out std_ulogic; + TXP1 : out std_ulogic; + TXRUNDISP0 : out std_logic_vector(3 downto 0); + TXRUNDISP1 : out std_logic_vector(3 downto 0); + + CLKIN : in std_ulogic; + DADDR : in std_logic_vector(6 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DFECLKDLYADJ0 : in std_logic_vector(5 downto 0); + DFECLKDLYADJ1 : in std_logic_vector(5 downto 0); + DFETAP10 : in std_logic_vector(4 downto 0); + DFETAP11 : in std_logic_vector(4 downto 0); + DFETAP20 : in std_logic_vector(4 downto 0); + DFETAP21 : in std_logic_vector(4 downto 0); + DFETAP30 : in std_logic_vector(3 downto 0); + DFETAP31 : in std_logic_vector(3 downto 0); + DFETAP40 : in std_logic_vector(3 downto 0); + DFETAP41 : in std_logic_vector(3 downto 0); + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + GSR : in std_ulogic; + GTXRESET : in std_ulogic; + GTXTEST : in std_logic_vector(13 downto 0); + INTDATAWIDTH : in std_ulogic; + LOOPBACK0 : in std_logic_vector(2 downto 0); + LOOPBACK1 : in std_logic_vector(2 downto 0); + PLLLKDETEN : in std_ulogic; + PLLPOWERDOWN : in std_ulogic; + PRBSCNTRESET0 : in std_ulogic; + PRBSCNTRESET1 : in std_ulogic; + REFCLKPWRDNB : in std_ulogic; + RXBUFRESET0 : in std_ulogic; + RXBUFRESET1 : in std_ulogic; + RXCDRRESET0 : in std_ulogic; + RXCDRRESET1 : in std_ulogic; + RXCHBONDI0 : in std_logic_vector(3 downto 0); + RXCHBONDI1 : in std_logic_vector(3 downto 0); + RXCOMMADETUSE0 : in std_ulogic; + RXCOMMADETUSE1 : in std_ulogic; + RXDATAWIDTH0 : in std_logic_vector(1 downto 0); + RXDATAWIDTH1 : in std_logic_vector(1 downto 0); + RXDEC8B10BUSE0 : in std_ulogic; + RXDEC8B10BUSE1 : in std_ulogic; + RXENCHANSYNC0 : in std_ulogic; + RXENCHANSYNC1 : in std_ulogic; + RXENEQB0 : in std_ulogic; + RXENEQB1 : in std_ulogic; + RXENMCOMMAALIGN0 : in std_ulogic; + RXENMCOMMAALIGN1 : in std_ulogic; + RXENPCOMMAALIGN0 : in std_ulogic; + RXENPCOMMAALIGN1 : in std_ulogic; + RXENPMAPHASEALIGN0 : in std_ulogic; + RXENPMAPHASEALIGN1 : in std_ulogic; + RXENPRBSTST0 : in std_logic_vector(1 downto 0); + RXENPRBSTST1 : in std_logic_vector(1 downto 0); + RXENSAMPLEALIGN0 : in std_ulogic; + RXENSAMPLEALIGN1 : in std_ulogic; + RXEQMIX0 : in std_logic_vector(1 downto 0); + RXEQMIX1 : in std_logic_vector(1 downto 0); + RXEQPOLE0 : in std_logic_vector(3 downto 0); + RXEQPOLE1 : in std_logic_vector(3 downto 0); + RXGEARBOXSLIP0 : in std_ulogic; + RXGEARBOXSLIP1 : in std_ulogic; + RXN0 : in std_ulogic; + RXN1 : in std_ulogic; + RXP0 : in std_ulogic; + RXP1 : in std_ulogic; + RXPMASETPHASE0 : in std_ulogic; + RXPMASETPHASE1 : in std_ulogic; + RXPOLARITY0 : in std_ulogic; + RXPOLARITY1 : in std_ulogic; + RXPOWERDOWN0 : in std_logic_vector(1 downto 0); + RXPOWERDOWN1 : in std_logic_vector(1 downto 0); + RXRESET0 : in std_ulogic; + RXRESET1 : in std_ulogic; + RXSLIDE0 : in std_ulogic; + RXSLIDE1 : in std_ulogic; + RXUSRCLK0 : in std_ulogic; + RXUSRCLK1 : in std_ulogic; + RXUSRCLK20 : in std_ulogic; + RXUSRCLK21 : in std_ulogic; + TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXBYPASS8B10B0 : in std_logic_vector(3 downto 0); + TXBYPASS8B10B1 : in std_logic_vector(3 downto 0); + TXCHARDISPMODE0 : in std_logic_vector(3 downto 0); + TXCHARDISPMODE1 : in std_logic_vector(3 downto 0); + TXCHARDISPVAL0 : in std_logic_vector(3 downto 0); + TXCHARDISPVAL1 : in std_logic_vector(3 downto 0); + TXCHARISK0 : in std_logic_vector(3 downto 0); + TXCHARISK1 : in std_logic_vector(3 downto 0); + TXCOMSTART0 : in std_ulogic; + TXCOMSTART1 : in std_ulogic; + TXCOMTYPE0 : in std_ulogic; + TXCOMTYPE1 : in std_ulogic; + TXDATA0 : in std_logic_vector(31 downto 0); + TXDATA1 : in std_logic_vector(31 downto 0); + TXDATAWIDTH0 : in std_logic_vector(1 downto 0); + TXDATAWIDTH1 : in std_logic_vector(1 downto 0); + TXDETECTRX0 : in std_ulogic; + TXDETECTRX1 : in std_ulogic; + TXDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXELECIDLE0 : in std_ulogic; + TXELECIDLE1 : in std_ulogic; + TXENC8B10BUSE0 : in std_ulogic; + TXENC8B10BUSE1 : in std_ulogic; + TXENPMAPHASEALIGN0 : in std_ulogic; + TXENPMAPHASEALIGN1 : in std_ulogic; + TXENPRBSTST0 : in std_logic_vector(1 downto 0); + TXENPRBSTST1 : in std_logic_vector(1 downto 0); + TXHEADER0 : in std_logic_vector(2 downto 0); + TXHEADER1 : in std_logic_vector(2 downto 0); + TXINHIBIT0 : in std_ulogic; + TXINHIBIT1 : in std_ulogic; + TXPMASETPHASE0 : in std_ulogic; + TXPMASETPHASE1 : in std_ulogic; + TXPOLARITY0 : in std_ulogic; + TXPOLARITY1 : in std_ulogic; + TXPOWERDOWN0 : in std_logic_vector(1 downto 0); + TXPOWERDOWN1 : in std_logic_vector(1 downto 0); + TXPREEMPHASIS0 : in std_logic_vector(3 downto 0); + TXPREEMPHASIS1 : in std_logic_vector(3 downto 0); + TXRESET0 : in std_ulogic; + TXRESET1 : in std_ulogic; + TXSEQUENCE0 : in std_logic_vector(6 downto 0); + TXSEQUENCE1 : in std_logic_vector(6 downto 0); + TXSTARTSEQ0 : in std_ulogic; + TXSTARTSEQ1 : in std_ulogic; + TXUSRCLK0 : in std_ulogic; + TXUSRCLK1 : in std_ulogic; + TXUSRCLK20 : in std_ulogic; + TXUSRCLK21 : in std_ulogic; + + STEPPING : in std_ulogic; + AC_CAP_DIS_0 : in std_ulogic; + AC_CAP_DIS_1 : in std_ulogic; + ALIGN_COMMA_WORD_0 : in std_ulogic; + ALIGN_COMMA_WORD_1 : in std_ulogic; + CB2_INH_CC_PERIOD_0 : in std_logic_vector(3 downto 0); + CB2_INH_CC_PERIOD_1 : in std_logic_vector(3 downto 0); + CDR_PH_ADJ_TIME : in std_logic_vector(4 downto 0); + CHAN_BOND_1_MAX_SKEW_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_1_MAX_SKEW_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_2_MAX_SKEW_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_2_MAX_SKEW_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_KEEP_ALIGN_0 : in std_ulogic; + CHAN_BOND_KEEP_ALIGN_1 : in std_ulogic; + CHAN_BOND_LEVEL_0 : in std_logic_vector(2 downto 0); + CHAN_BOND_LEVEL_1 : in std_logic_vector(2 downto 0); + CHAN_BOND_MODE_0 : in std_logic_vector(1 downto 0); + CHAN_BOND_MODE_1 : in std_logic_vector(1 downto 0); + CHAN_BOND_SEQ_1_1_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_1_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_2_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_2_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_3_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_3_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_4_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_4_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_1_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_1_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_2_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_2_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_3_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_3_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_4_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_4_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_USE_0 : in std_ulogic; + CHAN_BOND_SEQ_2_USE_1 : in std_ulogic; + CHAN_BOND_SEQ_LEN_0 : in std_logic_vector(1 downto 0); + CHAN_BOND_SEQ_LEN_1 : in std_logic_vector(1 downto 0); + CLK25_DIVIDER : in std_logic_vector(2 downto 0); + CLKINDC_B : in std_ulogic; + CLKRCV_TRST : in std_ulogic; + CLK_CORRECT_USE_0 : in std_ulogic; + CLK_CORRECT_USE_1 : in std_ulogic; + CLK_COR_ADJ_LEN_0 : in std_logic_vector(1 downto 0); + CLK_COR_ADJ_LEN_1 : in std_logic_vector(1 downto 0); + CLK_COR_DET_LEN_0 : in std_logic_vector(1 downto 0); + CLK_COR_DET_LEN_1 : in std_logic_vector(1 downto 0); + CLK_COR_INSERT_IDLE_FLAG_0 : in std_ulogic; + CLK_COR_INSERT_IDLE_FLAG_1 : in std_ulogic; + CLK_COR_KEEP_IDLE_0 : in std_ulogic; + CLK_COR_KEEP_IDLE_1 : in std_ulogic; + CLK_COR_MAX_LAT_0 : in std_logic_vector(5 downto 0); + CLK_COR_MAX_LAT_1 : in std_logic_vector(5 downto 0); + CLK_COR_MIN_LAT_0 : in std_logic_vector(5 downto 0); + CLK_COR_MIN_LAT_1 : in std_logic_vector(5 downto 0); + CLK_COR_PRECEDENCE_0 : in std_ulogic; + CLK_COR_PRECEDENCE_1 : in std_ulogic; + CLK_COR_REPEAT_WAIT_0 : in std_logic_vector(4 downto 0); + CLK_COR_REPEAT_WAIT_1 : in std_logic_vector(4 downto 0); + CLK_COR_SEQ_1_1_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_1_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_2_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_2_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_3_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_3_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_4_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_4_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_1_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_1_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_2_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_2_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_3_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_3_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_4_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_4_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_USE_0 : in std_ulogic; + CLK_COR_SEQ_2_USE_1 : in std_ulogic; + CM_TRIM_0 : in std_logic_vector(1 downto 0); + CM_TRIM_1 : in std_logic_vector(1 downto 0); + COMMA_10B_ENABLE_0 : in std_logic_vector(9 downto 0); + COMMA_10B_ENABLE_1 : in std_logic_vector(9 downto 0); + COMMA_DOUBLE_0 : in std_ulogic; + COMMA_DOUBLE_1 : in std_ulogic; + COM_BURST_VAL_0 : in std_logic_vector(3 downto 0); + COM_BURST_VAL_1 : in std_logic_vector(3 downto 0); + DEC_MCOMMA_DETECT_0 : in std_ulogic; + DEC_MCOMMA_DETECT_1 : in std_ulogic; + DEC_PCOMMA_DETECT_0 : in std_ulogic; + DEC_PCOMMA_DETECT_1 : in std_ulogic; + DEC_VALID_COMMA_ONLY_0 : in std_ulogic; + DEC_VALID_COMMA_ONLY_1 : in std_ulogic; + DFE_CAL_TIME : in std_logic_vector(4 downto 0); + DFE_CFG_0 : in std_logic_vector(9 downto 0); + DFE_CFG_1 : in std_logic_vector(9 downto 0); + GEARBOX_ENDEC_0 : in std_logic_vector(2 downto 0); + GEARBOX_ENDEC_1 : in std_logic_vector(2 downto 0); + MCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); + MCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); + MCOMMA_DETECT_0 : in std_ulogic; + MCOMMA_DETECT_1 : in std_ulogic; + OOBDETECT_THRESHOLD_0 : in std_logic_vector(2 downto 0); + OOBDETECT_THRESHOLD_1 : in std_logic_vector(2 downto 0); + OOB_CLK_DIVIDER : in std_logic_vector(2 downto 0); + OVERSAMPLE_MODE : in std_ulogic; + PCI_EXPRESS_MODE_0 : in std_ulogic; + PCI_EXPRESS_MODE_1 : in std_ulogic; + PCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); + PCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); + PCOMMA_DETECT_0 : in std_ulogic; + PCOMMA_DETECT_1 : in std_ulogic; + PLL_COM_CFG : in std_logic_vector(23 downto 0); + PLL_CP_CFG : in std_logic_vector(7 downto 0); + PLL_DIVSEL_FB : in std_logic_vector(4 downto 0); + PLL_DIVSEL_REF : in std_logic_vector(5 downto 0); + PLL_FB_DCCEN : in std_ulogic; + PLL_LKDET_CFG : in std_logic_vector(2 downto 0); + PLL_RXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); + PLL_RXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); + PLL_SATA_0 : in std_ulogic; + PLL_SATA_1 : in std_ulogic; + PLL_TDCC_CFG : in std_logic_vector(2 downto 0); + PLL_TXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); + PLL_TXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); + PMA_CDR_SCAN_0 : in std_logic_vector(26 downto 0); + PMA_CDR_SCAN_1 : in std_logic_vector(26 downto 0); + PMA_COM_CFG : in std_logic_vector(68 downto 0); + PMA_RXSYNC_CFG_0 : in std_logic_vector(6 downto 0); + PMA_RXSYNC_CFG_1 : in std_logic_vector(6 downto 0); + PMA_RX_CFG_0 : in std_logic_vector(24 downto 0); + PMA_RX_CFG_1 : in std_logic_vector(24 downto 0); + PMA_TX_CFG_0 : in std_logic_vector(19 downto 0); + PMA_TX_CFG_1 : in std_logic_vector(19 downto 0); + PRBS_ERR_THRESHOLD_0 : in std_logic_vector(31 downto 0); + PRBS_ERR_THRESHOLD_1 : in std_logic_vector(31 downto 0); + RCV_TERM_GND_0 : in std_ulogic; + RCV_TERM_GND_1 : in std_ulogic; + RCV_TERM_VTTRX_0 : in std_ulogic; + RCV_TERM_VTTRX_1 : in std_ulogic; + RXGEARBOX_USE_0 : in std_ulogic; + RXGEARBOX_USE_1 : in std_ulogic; + RX_BUFFER_USE_0 : in std_ulogic; + RX_BUFFER_USE_1 : in std_ulogic; + RX_DECODE_SEQ_MATCH_0 : in std_ulogic; + RX_DECODE_SEQ_MATCH_1 : in std_ulogic; + RX_EN_IDLE_HOLD_CDR : in std_ulogic; + RX_EN_IDLE_HOLD_DFE_0 : in std_ulogic; + RX_EN_IDLE_HOLD_DFE_1 : in std_ulogic; + RX_EN_IDLE_RESET_BUF_0 : in std_ulogic; + RX_EN_IDLE_RESET_BUF_1 : in std_ulogic; + RX_EN_IDLE_RESET_FR : in std_ulogic; + RX_EN_IDLE_RESET_PH : in std_ulogic; + RX_IDLE_HI_CNT_0 : in std_logic_vector(3 downto 0); + RX_IDLE_HI_CNT_1 : in std_logic_vector(3 downto 0); + RX_IDLE_LO_CNT_0 : in std_logic_vector(3 downto 0); + RX_IDLE_LO_CNT_1 : in std_logic_vector(3 downto 0); + RX_LOSS_OF_SYNC_FSM_0 : in std_ulogic; + RX_LOSS_OF_SYNC_FSM_1 : in std_ulogic; + RX_LOS_INVALID_INCR_0 : in std_logic_vector(2 downto 0); + RX_LOS_INVALID_INCR_1 : in std_logic_vector(2 downto 0); + RX_LOS_THRESHOLD_0 : in std_logic_vector(2 downto 0); + RX_LOS_THRESHOLD_1 : in std_logic_vector(2 downto 0); + RX_SLIDE_MODE_0 : in std_ulogic; + RX_SLIDE_MODE_1 : in std_ulogic; + RX_STATUS_FMT_0 : in std_ulogic; + RX_STATUS_FMT_1 : in std_ulogic; + RX_XCLK_SEL_0 : in std_ulogic; + RX_XCLK_SEL_1 : in std_ulogic; + SATA_BURST_VAL_0 : in std_logic_vector(2 downto 0); + SATA_BURST_VAL_1 : in std_logic_vector(2 downto 0); + SATA_IDLE_VAL_0 : in std_logic_vector(2 downto 0); + SATA_IDLE_VAL_1 : in std_logic_vector(2 downto 0); + SATA_MAX_BURST_0 : in std_logic_vector(5 downto 0); + SATA_MAX_BURST_1 : in std_logic_vector(5 downto 0); + SATA_MAX_INIT_0 : in std_logic_vector(5 downto 0); + SATA_MAX_INIT_1 : in std_logic_vector(5 downto 0); + SATA_MAX_WAKE_0 : in std_logic_vector(5 downto 0); + SATA_MAX_WAKE_1 : in std_logic_vector(5 downto 0); + SATA_MIN_BURST_0 : in std_logic_vector(5 downto 0); + SATA_MIN_BURST_1 : in std_logic_vector(5 downto 0); + SATA_MIN_INIT_0 : in std_logic_vector(5 downto 0); + SATA_MIN_INIT_1 : in std_logic_vector(5 downto 0); + SATA_MIN_WAKE_0 : in std_logic_vector(5 downto 0); + SATA_MIN_WAKE_1 : in std_logic_vector(5 downto 0); + SIM_GTXRESET_SPEEDUP : in std_ulogic; + SIM_PLL_PERDIV2 : in std_logic_vector(8 downto 0); + SIM_RECEIVER_DETECT_PASS_0 : in std_ulogic; + SIM_RECEIVER_DETECT_PASS_1 : in std_ulogic; + TERMINATION_CTRL : in std_logic_vector(4 downto 0); + TERMINATION_IMP_0 : in std_ulogic; + TERMINATION_IMP_1 : in std_ulogic; + TERMINATION_OVRD : in std_ulogic; + TRANS_TIME_FROM_P2_0 : in std_logic_vector(11 downto 0); + TRANS_TIME_FROM_P2_1 : in std_logic_vector(11 downto 0); + TRANS_TIME_NON_P2_0 : in std_logic_vector(7 downto 0); + TRANS_TIME_NON_P2_1 : in std_logic_vector(7 downto 0); + TRANS_TIME_TO_P2_0 : in std_logic_vector(9 downto 0); + TRANS_TIME_TO_P2_1 : in std_logic_vector(9 downto 0); + TXGEARBOX_USE_0 : in std_ulogic; + TXGEARBOX_USE_1 : in std_ulogic; + TXRX_INVERT_0 : in std_logic_vector(2 downto 0); + TXRX_INVERT_1 : in std_logic_vector(2 downto 0); + TX_BUFFER_USE_0 : in std_ulogic; + TX_BUFFER_USE_1 : in std_ulogic; + TX_DETECT_RX_CFG_0 : in std_logic_vector(13 downto 0); + TX_DETECT_RX_CFG_1 : in std_logic_vector(13 downto 0); + TX_IDLE_DELAY_0 : in std_logic_vector(2 downto 0); + TX_IDLE_DELAY_1 : in std_logic_vector(2 downto 0); + TX_XCLK_SEL_0 : in std_ulogic; + TX_XCLK_SEL_1 : in std_ulogic + ); + end component; + + + constant IN_DELAY : time := 0 ps; + constant OUT_DELAY : time := 0 ps; + constant CLK_DELAY : time := 0 ps; + + constant PATH_DELAY : VitalDelayType01 := (100 ps, 100 ps); + + + signal PLL_TXDIVSEL_OUT_0_BINARY : std_logic_vector(1 downto 0); + signal PLL_RXDIVSEL_OUT_0_BINARY : std_logic_vector(1 downto 0); + signal PLL_TXDIVSEL_OUT_1_BINARY : std_logic_vector(1 downto 0); + signal PLL_RXDIVSEL_OUT_1_BINARY : std_logic_vector(1 downto 0); + signal PLL_DIVSEL_FB_BINARY : std_logic_vector(4 downto 0); + signal PLL_DIVSEL_REF_BINARY : std_logic_vector(5 downto 0); + signal PLL_SATA_0_BINARY : std_ulogic; + signal PLL_SATA_1_BINARY : std_ulogic; + signal OOBDETECT_THRESHOLD_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(OOBDETECT_THRESHOLD_0)(2 downto 0); + signal OOBDETECT_THRESHOLD_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(OOBDETECT_THRESHOLD_1)(2 downto 0); + signal PMA_CDR_SCAN_0_BINARY : std_logic_vector(26 downto 0) := To_StdLogicVector(PMA_CDR_SCAN_0)(26 downto 0); + signal PMA_CDR_SCAN_1_BINARY : std_logic_vector(26 downto 0) := To_StdLogicVector(PMA_CDR_SCAN_1)(26 downto 0); + signal PMA_RX_CFG_0_BINARY : std_logic_vector(24 downto 0) := To_StdLogicVector(PMA_RX_CFG_0)(24 downto 0); + signal PMA_RX_CFG_1_BINARY : std_logic_vector(24 downto 0) := To_StdLogicVector(PMA_RX_CFG_1)(24 downto 0); + signal PLL_TDCC_CFG_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PLL_TDCC_CFG); + signal PMA_COM_CFG_BINARY : std_logic_vector(68 downto 0) := To_StdLogicVector(PMA_COM_CFG)(68 downto 0); + signal PMA_RXSYNC_CFG_0_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(PMA_RXSYNC_CFG_0)(6 downto 0); + signal PMA_RXSYNC_CFG_1_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(PMA_RXSYNC_CFG_1)(6 downto 0); + signal OOB_CLK_DIVIDER_BINARY : std_logic_vector(2 downto 0); + signal STEPPING_BINARY : std_ulogic := '0'; + signal AC_CAP_DIS_0_BINARY : std_ulogic; + signal AC_CAP_DIS_1_BINARY : std_ulogic; + signal RCV_TERM_GND_0_BINARY : std_ulogic; + signal RCV_TERM_GND_1_BINARY : std_ulogic; + signal TERMINATION_IMP_0_BINARY : std_ulogic; + signal TERMINATION_IMP_1_BINARY : std_ulogic; + signal TERMINATION_OVRD_BINARY : std_ulogic; + signal TERMINATION_CTRL_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TERMINATION_CTRL)(4 downto 0); + signal RCV_TERM_VTTRX_0_BINARY : std_ulogic; + signal RCV_TERM_VTTRX_1_BINARY : std_ulogic; + signal PLL_LKDET_CFG_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PLL_LKDET_CFG); + signal TXRX_INVERT_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TXRX_INVERT_0)(2 downto 0); + signal TXRX_INVERT_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TXRX_INVERT_1)(2 downto 0); + signal CLKINDC_B_BINARY : std_ulogic; + signal PCOMMA_DETECT_0_BINARY : std_ulogic; + signal MCOMMA_DETECT_0_BINARY : std_ulogic; + signal PCOMMA_10B_VALUE_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(PCOMMA_10B_VALUE_0)(9 downto 0); + signal MCOMMA_10B_VALUE_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(MCOMMA_10B_VALUE_0)(9 downto 0); + signal COMMA_10B_ENABLE_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(COMMA_10B_ENABLE_0)(9 downto 0); + signal COMMA_DOUBLE_0_BINARY : std_ulogic; + signal ALIGN_COMMA_WORD_0_BINARY : std_ulogic; + signal DEC_PCOMMA_DETECT_0_BINARY : std_ulogic; + signal DEC_MCOMMA_DETECT_0_BINARY : std_ulogic; + signal DEC_VALID_COMMA_ONLY_0_BINARY : std_ulogic; + signal PCOMMA_DETECT_1_BINARY : std_ulogic; + signal MCOMMA_DETECT_1_BINARY : std_ulogic; + signal PCOMMA_10B_VALUE_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(PCOMMA_10B_VALUE_1)(9 downto 0); + signal MCOMMA_10B_VALUE_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(MCOMMA_10B_VALUE_1)(9 downto 0); + signal COMMA_10B_ENABLE_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(COMMA_10B_ENABLE_1)(9 downto 0); + signal COMMA_DOUBLE_1_BINARY : std_ulogic; + signal ALIGN_COMMA_WORD_1_BINARY : std_ulogic; + signal DEC_PCOMMA_DETECT_1_BINARY : std_ulogic; + signal DEC_MCOMMA_DETECT_1_BINARY : std_ulogic; + signal DEC_VALID_COMMA_ONLY_1_BINARY : std_ulogic; + signal RX_LOSS_OF_SYNC_FSM_0_BINARY : std_ulogic; + signal RX_LOS_INVALID_INCR_0_BINARY : std_logic_vector(2 downto 0); + signal RX_LOS_THRESHOLD_0_BINARY : std_logic_vector(2 downto 0); + signal RX_LOSS_OF_SYNC_FSM_1_BINARY : std_ulogic; + signal RX_LOS_INVALID_INCR_1_BINARY : std_logic_vector(2 downto 0); + signal RX_LOS_THRESHOLD_1_BINARY : std_logic_vector(2 downto 0); + signal RX_BUFFER_USE_0_BINARY : std_ulogic; + signal RX_DECODE_SEQ_MATCH_0_BINARY : std_ulogic; + signal RX_BUFFER_USE_1_BINARY : std_ulogic; + signal RX_DECODE_SEQ_MATCH_1_BINARY : std_ulogic; + signal CLK_COR_MIN_LAT_0_BINARY : std_logic_vector(5 downto 0); + signal CLK_COR_MAX_LAT_0_BINARY : std_logic_vector(5 downto 0); + signal CLK_CORRECT_USE_0_BINARY : std_ulogic; + signal CLK_COR_PRECEDENCE_0_BINARY : std_ulogic; + signal CLK_COR_DET_LEN_0_BINARY : std_logic_vector(1 downto 0); + signal CLK_COR_ADJ_LEN_0_BINARY : std_logic_vector(1 downto 0); + signal CLK_COR_KEEP_IDLE_0_BINARY : std_ulogic; + signal CLK_COR_INSERT_IDLE_FLAG_0_BINARY : std_ulogic; + signal CLK_COR_REPEAT_WAIT_0_BINARY : std_logic_vector(4 downto 0); + signal CLK_COR_SEQ_2_USE_0_BINARY : std_ulogic; + signal CLK_COR_SEQ_1_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1_0)(9 downto 0); + signal CLK_COR_SEQ_1_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2_0)(9 downto 0); + signal CLK_COR_SEQ_1_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3_0)(9 downto 0); + signal CLK_COR_SEQ_1_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4_0)(9 downto 0); + signal CLK_COR_SEQ_2_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1_0)(9 downto 0); + signal CLK_COR_SEQ_2_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2_0)(9 downto 0); + signal CLK_COR_SEQ_2_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3_0)(9 downto 0); + signal CLK_COR_SEQ_2_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4_0)(9 downto 0); + signal CLK_COR_SEQ_1_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_ENABLE_0)(3 downto 0); + signal CLK_COR_SEQ_2_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_ENABLE_0)(3 downto 0); + signal CLK_COR_MIN_LAT_1_BINARY : std_logic_vector(5 downto 0); + signal CLK_COR_MAX_LAT_1_BINARY : std_logic_vector(5 downto 0); + signal CLK_CORRECT_USE_1_BINARY : std_ulogic; + signal CLK_COR_PRECEDENCE_1_BINARY : std_ulogic; + signal CLK_COR_DET_LEN_1_BINARY : std_logic_vector(1 downto 0); + signal CLK_COR_ADJ_LEN_1_BINARY : std_logic_vector(1 downto 0); + signal CLK_COR_KEEP_IDLE_1_BINARY : std_ulogic; + signal CLK_COR_INSERT_IDLE_FLAG_1_BINARY : std_ulogic; + signal CLK_COR_REPEAT_WAIT_1_BINARY : std_logic_vector(4 downto 0); + signal CLK_COR_SEQ_2_USE_1_BINARY : std_ulogic; + signal CLK_COR_SEQ_1_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1_1)(9 downto 0); + signal CLK_COR_SEQ_1_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2_1)(9 downto 0); + signal CLK_COR_SEQ_1_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3_1)(9 downto 0); + signal CLK_COR_SEQ_1_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4_1)(9 downto 0); + signal CLK_COR_SEQ_2_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1_1)(9 downto 0); + signal CLK_COR_SEQ_2_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2_1)(9 downto 0); + signal CLK_COR_SEQ_2_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3_1)(9 downto 0); + signal CLK_COR_SEQ_2_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4_1)(9 downto 0); + signal CLK_COR_SEQ_1_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_ENABLE_1)(3 downto 0); + signal CLK_COR_SEQ_2_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_ENABLE_1)(3 downto 0); + signal CHAN_BOND_MODE_0_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_LEVEL_0_BINARY : std_logic_vector(2 downto 0); + signal CHAN_BOND_SEQ_LEN_0_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_SEQ_2_USE_0_BINARY : std_ulogic; + signal CHAN_BOND_SEQ_1_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1_0)(9 downto 0); + signal CHAN_BOND_SEQ_1_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2_0)(9 downto 0); + signal CHAN_BOND_SEQ_1_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3_0)(9 downto 0); + signal CHAN_BOND_SEQ_1_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4_0)(9 downto 0); + signal CHAN_BOND_SEQ_2_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1_0)(9 downto 0); + signal CHAN_BOND_SEQ_2_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2_0)(9 downto 0); + signal CHAN_BOND_SEQ_2_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3_0)(9 downto 0); + signal CHAN_BOND_SEQ_2_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4_0)(9 downto 0); + signal CHAN_BOND_SEQ_1_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_ENABLE_0)(3 downto 0); + signal CHAN_BOND_SEQ_2_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_ENABLE_0)(3 downto 0); + signal CHAN_BOND_1_MAX_SKEW_0_BINARY : std_logic_vector(3 downto 0); + signal CHAN_BOND_2_MAX_SKEW_0_BINARY : std_logic_vector(3 downto 0); + signal CHAN_BOND_KEEP_ALIGN_0_BINARY : std_ulogic; + signal CB2_INH_CC_PERIOD_0_BINARY : std_logic_vector(3 downto 0); + signal CHAN_BOND_MODE_1_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_LEVEL_1_BINARY : std_logic_vector(2 downto 0); + signal CHAN_BOND_SEQ_LEN_1_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_SEQ_2_USE_1_BINARY : std_ulogic; + signal CHAN_BOND_SEQ_1_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1_1)(9 downto 0); + signal CHAN_BOND_SEQ_1_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2_1)(9 downto 0); + signal CHAN_BOND_SEQ_1_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3_1)(9 downto 0); + signal CHAN_BOND_SEQ_1_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4_1)(9 downto 0); + signal CHAN_BOND_SEQ_2_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1_1)(9 downto 0); + signal CHAN_BOND_SEQ_2_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2_1)(9 downto 0); + signal CHAN_BOND_SEQ_2_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3_1)(9 downto 0); + signal CHAN_BOND_SEQ_2_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4_1)(9 downto 0); + signal CHAN_BOND_SEQ_1_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_ENABLE_1)(3 downto 0); + signal CHAN_BOND_SEQ_2_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_ENABLE_1)(3 downto 0); + signal CHAN_BOND_1_MAX_SKEW_1_BINARY : std_logic_vector(3 downto 0); + signal CHAN_BOND_2_MAX_SKEW_1_BINARY : std_logic_vector(3 downto 0); + signal CHAN_BOND_KEEP_ALIGN_1_BINARY : std_ulogic; + signal CB2_INH_CC_PERIOD_1_BINARY : std_logic_vector(3 downto 0); + signal PCI_EXPRESS_MODE_0_BINARY : std_ulogic; + signal TRANS_TIME_FROM_P2_0_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(TRANS_TIME_FROM_P2_0)(11 downto 0); + signal TRANS_TIME_NON_P2_0_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(TRANS_TIME_NON_P2_0)(7 downto 0); + signal TRANS_TIME_TO_P2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(TRANS_TIME_TO_P2_0)(9 downto 0); + signal PCI_EXPRESS_MODE_1_BINARY : std_ulogic; + signal TRANS_TIME_FROM_P2_1_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(TRANS_TIME_FROM_P2_1)(11 downto 0); + signal TRANS_TIME_NON_P2_1_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(TRANS_TIME_NON_P2_1)(7 downto 0); + signal TRANS_TIME_TO_P2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(TRANS_TIME_TO_P2_1)(9 downto 0); + signal RX_STATUS_FMT_0_BINARY : std_ulogic; + signal TX_BUFFER_USE_0_BINARY : std_ulogic; + signal TX_XCLK_SEL_0_BINARY : std_ulogic; + signal RX_XCLK_SEL_0_BINARY : std_ulogic; + signal RX_STATUS_FMT_1_BINARY : std_ulogic; + signal TX_BUFFER_USE_1_BINARY : std_ulogic; + signal TX_XCLK_SEL_1_BINARY : std_ulogic; + signal RX_XCLK_SEL_1_BINARY : std_ulogic; + signal PRBS_ERR_THRESHOLD_0_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(PRBS_ERR_THRESHOLD_0)(31 downto 0); + signal RX_SLIDE_MODE_0_BINARY : std_ulogic; + signal PRBS_ERR_THRESHOLD_1_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(PRBS_ERR_THRESHOLD_1)(31 downto 0); + signal RX_SLIDE_MODE_1_BINARY : std_ulogic; + signal SATA_MIN_BURST_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_BURST_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_INIT_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_INIT_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_WAKE_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_WAKE_0_BINARY : std_logic_vector(5 downto 0); + signal TX_DETECT_RX_CFG_0_BINARY : std_logic_vector(13 downto 0) := To_StdLogicVector(TX_DETECT_RX_CFG_0)(13 downto 0); + signal SATA_BURST_VAL_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_BURST_VAL_0)(2 downto 0); + signal SATA_IDLE_VAL_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_IDLE_VAL_0)(2 downto 0); + signal COM_BURST_VAL_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(COM_BURST_VAL_0)(3 downto 0); + signal SATA_MIN_BURST_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_BURST_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_INIT_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_INIT_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_WAKE_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_WAKE_1_BINARY : std_logic_vector(5 downto 0); + signal TX_DETECT_RX_CFG_1_BINARY : std_logic_vector(13 downto 0) := To_StdLogicVector(TX_DETECT_RX_CFG_1)(13 downto 0); + signal SATA_BURST_VAL_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_BURST_VAL_1)(2 downto 0); + signal SATA_IDLE_VAL_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_IDLE_VAL_1)(2 downto 0); + signal COM_BURST_VAL_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(COM_BURST_VAL_1)(3 downto 0); + signal CLK25_DIVIDER_BINARY : std_logic_vector(2 downto 0); + signal PLL_COM_CFG_BINARY : std_logic_vector(23 downto 0) := To_StdLogicVector(PLL_COM_CFG); + signal PLL_CP_CFG_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PLL_CP_CFG); + signal OVERSAMPLE_MODE_BINARY : std_ulogic; + signal TXGEARBOX_USE_0_BINARY : std_ulogic; + signal RXGEARBOX_USE_0_BINARY : std_ulogic; + signal GEARBOX_ENDEC_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(GEARBOX_ENDEC_0)(2 downto 0); + signal TXGEARBOX_USE_1_BINARY : std_ulogic; + signal RXGEARBOX_USE_1_BINARY : std_ulogic; + signal GEARBOX_ENDEC_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(GEARBOX_ENDEC_1)(2 downto 0); + signal DFE_CFG_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(DFE_CFG_0)(9 downto 0); + signal DFE_CFG_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(DFE_CFG_1)(9 downto 0); + signal PMA_TX_CFG_0_BINARY : std_logic_vector(19 downto 0) := To_StdLogicVector(PMA_TX_CFG_0)(19 downto 0); + signal CM_TRIM_0_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(CM_TRIM_0)(1 downto 0); + signal PMA_TX_CFG_1_BINARY : std_logic_vector(19 downto 0) := To_StdLogicVector(PMA_TX_CFG_1)(19 downto 0); + signal CM_TRIM_1_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(CM_TRIM_1)(1 downto 0); + signal PLL_FB_DCCEN_BINARY : std_ulogic; + signal CLKRCV_TRST_BINARY : std_ulogic; + signal TX_IDLE_DELAY_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TX_IDLE_DELAY_0)(2 downto 0); + signal RX_EN_IDLE_HOLD_DFE_0_BINARY : std_ulogic; + signal RX_EN_IDLE_RESET_BUF_0_BINARY : std_ulogic; + signal RX_IDLE_HI_CNT_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RX_IDLE_HI_CNT_0)(3 downto 0); + signal RX_IDLE_LO_CNT_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RX_IDLE_LO_CNT_0)(3 downto 0); + signal TX_IDLE_DELAY_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TX_IDLE_DELAY_1)(2 downto 0); + signal RX_EN_IDLE_HOLD_DFE_1_BINARY : std_ulogic; + signal RX_EN_IDLE_RESET_BUF_1_BINARY : std_ulogic; + signal RX_IDLE_HI_CNT_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RX_IDLE_HI_CNT_1)(3 downto 0); + signal RX_IDLE_LO_CNT_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RX_IDLE_LO_CNT_1)(3 downto 0); + signal RX_EN_IDLE_HOLD_CDR_BINARY : std_ulogic; + signal RX_EN_IDLE_RESET_PH_BINARY : std_ulogic; + signal RX_EN_IDLE_RESET_FR_BINARY : std_ulogic; + signal DFE_CAL_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(DFE_CAL_TIME)(4 downto 0); + signal CDR_PH_ADJ_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(CDR_PH_ADJ_TIME)(4 downto 0); + signal SIM_GTXRESET_SPEEDUP_BINARY : std_ulogic; + signal SIM_MODE_BINARY : std_ulogic; + signal SIM_PLL_PERDIV2_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(SIM_PLL_PERDIV2)(8 downto 0); + signal SIM_RECEIVER_DETECT_PASS_0_BINARY : std_ulogic; + signal SIM_RECEIVER_DETECT_PASS_1_BINARY : std_ulogic; + + + signal REFCLKOUT_out : std_ulogic; + signal RXRECCLK0_out : std_ulogic; + signal TXOUTCLK0_out : std_ulogic; + signal RXRECCLK1_out : std_ulogic; + signal TXOUTCLK1_out : std_ulogic; + signal TXP0_out : std_ulogic; + signal TXN0_out : std_ulogic; + signal TXP1_out : std_ulogic; + signal TXN1_out : std_ulogic; + signal RXDATA0_out : std_logic_vector(31 downto 0); + signal RXNOTINTABLE0_out : std_logic_vector(3 downto 0); + signal RXDISPERR0_out : std_logic_vector(3 downto 0); + signal RXCHARISK0_out : std_logic_vector(3 downto 0); + signal RXRUNDISP0_out : std_logic_vector(3 downto 0); + signal RXCHARISCOMMA0_out : std_logic_vector(3 downto 0); + signal RXVALID0_out : std_ulogic; + signal RXDATA1_out : std_logic_vector(31 downto 0); + signal RXNOTINTABLE1_out : std_logic_vector(3 downto 0); + signal RXDISPERR1_out : std_logic_vector(3 downto 0); + signal RXCHARISK1_out : std_logic_vector(3 downto 0); + signal RXRUNDISP1_out : std_logic_vector(3 downto 0); + signal RXCHARISCOMMA1_out : std_logic_vector(3 downto 0); + signal RXVALID1_out : std_ulogic; + signal RESETDONE0_out : std_ulogic; + signal RESETDONE1_out : std_ulogic; + signal TXKERR0_out : std_logic_vector(3 downto 0); + signal TXRUNDISP0_out : std_logic_vector(3 downto 0); + signal TXBUFSTATUS0_out : std_logic_vector(1 downto 0); + signal TXKERR1_out : std_logic_vector(3 downto 0); + signal TXRUNDISP1_out : std_logic_vector(3 downto 0); + signal TXBUFSTATUS1_out : std_logic_vector(1 downto 0); + signal RXCOMMADET0_out : std_ulogic; + signal RXBYTEREALIGN0_out : std_ulogic; + signal RXBYTEISALIGNED0_out : std_ulogic; + signal RXLOSSOFSYNC0_out : std_logic_vector(1 downto 0); + signal RXCHBONDO0_out : std_logic_vector(3 downto 0); + signal RXCHANBONDSEQ0_out : std_ulogic; + signal RXCHANREALIGN0_out : std_ulogic; + signal RXCHANISALIGNED0_out : std_ulogic; + signal RXBUFSTATUS0_out : std_logic_vector(2 downto 0); + signal RXCOMMADET1_out : std_ulogic; + signal RXBYTEREALIGN1_out : std_ulogic; + signal RXBYTEISALIGNED1_out : std_ulogic; + signal RXLOSSOFSYNC1_out : std_logic_vector(1 downto 0); + signal RXCHBONDO1_out : std_logic_vector(3 downto 0); + signal RXCHANBONDSEQ1_out : std_ulogic; + signal RXCHANREALIGN1_out : std_ulogic; + signal RXCHANISALIGNED1_out : std_ulogic; + signal RXBUFSTATUS1_out : std_logic_vector(2 downto 0); + signal PHYSTATUS0_out : std_ulogic; + signal PHYSTATUS1_out : std_ulogic; + signal RXELECIDLE0_out : std_ulogic; + signal RXSTATUS0_out : std_logic_vector(2 downto 0); + signal RXCLKCORCNT0_out : std_logic_vector(2 downto 0); + signal RXELECIDLE1_out : std_ulogic; + signal RXSTATUS1_out : std_logic_vector(2 downto 0); + signal RXCLKCORCNT1_out : std_logic_vector(2 downto 0); + signal PLLLKDET_out : std_ulogic; + signal RXPRBSERR0_out : std_ulogic; + signal RXPRBSERR1_out : std_ulogic; + signal DO_out : std_logic_vector(15 downto 0); + signal DRDY_out : std_ulogic; + signal RXOVERSAMPLEERR0_out : std_ulogic; + signal RXOVERSAMPLEERR1_out : std_ulogic; + signal TXGEARBOXREADY0_out : std_ulogic; + signal RXHEADER0_out : std_logic_vector(2 downto 0); + signal RXHEADERVALID0_out : std_ulogic; + signal RXDATAVALID0_out : std_ulogic; + signal RXSTARTOFSEQ0_out : std_ulogic; + signal TXGEARBOXREADY1_out : std_ulogic; + signal RXHEADER1_out : std_logic_vector(2 downto 0); + signal RXHEADERVALID1_out : std_ulogic; + signal RXDATAVALID1_out : std_ulogic; + signal RXSTARTOFSEQ1_out : std_ulogic; + signal DFECLKDLYADJMONITOR0_out : std_logic_vector(5 downto 0); + signal DFEEYEDACMONITOR0_out : std_logic_vector(4 downto 0); + signal DFETAP1MONITOR0_out : std_logic_vector(4 downto 0); + signal DFETAP2MONITOR0_out : std_logic_vector(4 downto 0); + signal DFETAP3MONITOR0_out : std_logic_vector(3 downto 0); + signal DFETAP4MONITOR0_out : std_logic_vector(3 downto 0); + signal DFECLKDLYADJMONITOR1_out : std_logic_vector(5 downto 0); + signal DFEEYEDACMONITOR1_out : std_logic_vector(4 downto 0); + signal DFETAP1MONITOR1_out : std_logic_vector(4 downto 0); + signal DFETAP2MONITOR1_out : std_logic_vector(4 downto 0); + signal DFETAP3MONITOR1_out : std_logic_vector(3 downto 0); + signal DFETAP4MONITOR1_out : std_logic_vector(3 downto 0); + signal DFESENSCAL0_out : std_logic_vector(2 downto 0); + signal DFESENSCAL1_out : std_logic_vector(2 downto 0); + + signal REFCLKOUT_outdelay : std_logic; + signal RXRECCLK0_outdelay : std_logic; + signal TXOUTCLK0_outdelay : std_logic; + signal RXRECCLK1_outdelay : std_logic; + signal TXOUTCLK1_outdelay : std_logic; + signal RXCLKCORCNT0_outdelay : std_logic_vector(2 downto 0); + signal RXCLKCORCNT1_outdelay : std_logic_vector(2 downto 0); + signal DFECLKDLYADJMONITOR0_outdelay : std_logic_vector(5 downto 0); + signal DFECLKDLYADJMONITOR1_outdelay : std_logic_vector(5 downto 0); + + signal TXP0_outdelay : std_logic; + signal TXN0_outdelay : std_logic; + signal TXP1_outdelay : std_logic; + signal TXN1_outdelay : std_logic; + signal RXDATA0_outdelay : std_logic_vector(31 downto 0); + signal RXNOTINTABLE0_outdelay : std_logic_vector(3 downto 0); + signal RXDISPERR0_outdelay : std_logic_vector(3 downto 0); + signal RXCHARISK0_outdelay : std_logic_vector(3 downto 0); + signal RXRUNDISP0_outdelay : std_logic_vector(3 downto 0); + signal RXCHARISCOMMA0_outdelay : std_logic_vector(3 downto 0); + signal RXVALID0_outdelay : std_logic; + signal RXDATA1_outdelay : std_logic_vector(31 downto 0); + signal RXNOTINTABLE1_outdelay : std_logic_vector(3 downto 0); + signal RXDISPERR1_outdelay : std_logic_vector(3 downto 0); + signal RXCHARISK1_outdelay : std_logic_vector(3 downto 0); + signal RXRUNDISP1_outdelay : std_logic_vector(3 downto 0); + signal RXCHARISCOMMA1_outdelay : std_logic_vector(3 downto 0); + signal RXVALID1_outdelay : std_logic; + signal RESETDONE0_outdelay : std_logic; + signal RESETDONE1_outdelay : std_logic; + signal TXKERR0_outdelay : std_logic_vector(3 downto 0); + signal TXRUNDISP0_outdelay : std_logic_vector(3 downto 0); + signal TXBUFSTATUS0_outdelay : std_logic_vector(1 downto 0); + signal TXKERR1_outdelay : std_logic_vector(3 downto 0); + signal TXRUNDISP1_outdelay : std_logic_vector(3 downto 0); + signal TXBUFSTATUS1_outdelay : std_logic_vector(1 downto 0); + signal RXCOMMADET0_outdelay : std_logic; + signal RXBYTEREALIGN0_outdelay : std_logic; + signal RXBYTEISALIGNED0_outdelay : std_logic; + signal RXLOSSOFSYNC0_outdelay : std_logic_vector(1 downto 0); + signal RXCHBONDO0_outdelay : std_logic_vector(3 downto 0); + signal RXCHANBONDSEQ0_outdelay : std_logic; + signal RXCHANREALIGN0_outdelay : std_logic; + signal RXCHANISALIGNED0_outdelay : std_logic; + signal RXBUFSTATUS0_outdelay : std_logic_vector(2 downto 0); + signal RXCOMMADET1_outdelay : std_logic; + signal RXBYTEREALIGN1_outdelay : std_logic; + signal RXBYTEISALIGNED1_outdelay : std_logic; + signal RXLOSSOFSYNC1_outdelay : std_logic_vector(1 downto 0); + signal RXCHBONDO1_outdelay : std_logic_vector(3 downto 0); + signal RXCHANBONDSEQ1_outdelay : std_logic; + signal RXCHANREALIGN1_outdelay : std_logic; + signal RXCHANISALIGNED1_outdelay : std_logic; + signal RXBUFSTATUS1_outdelay : std_logic_vector(2 downto 0); + signal PHYSTATUS0_outdelay : std_logic; + signal PHYSTATUS1_outdelay : std_logic; + signal RXELECIDLE0_outdelay : std_logic; + signal RXSTATUS0_outdelay : std_logic_vector(2 downto 0); + signal RXELECIDLE1_outdelay : std_logic; + signal RXSTATUS1_outdelay : std_logic_vector(2 downto 0); + signal PLLLKDET_outdelay : std_logic; + signal RXPRBSERR0_outdelay : std_logic; + signal RXPRBSERR1_outdelay : std_logic; + signal DO_outdelay : std_logic_vector(15 downto 0); + signal DRDY_outdelay : std_logic; + signal RXOVERSAMPLEERR0_outdelay : std_logic; + signal RXOVERSAMPLEERR1_outdelay : std_logic; + signal TXGEARBOXREADY0_outdelay : std_logic; + signal RXHEADER0_outdelay : std_logic_vector(2 downto 0); + signal RXHEADERVALID0_outdelay : std_logic; + signal RXDATAVALID0_outdelay : std_logic; + signal RXSTARTOFSEQ0_outdelay : std_logic; + signal TXGEARBOXREADY1_outdelay : std_logic; + signal RXHEADER1_outdelay : std_logic_vector(2 downto 0); + signal RXHEADERVALID1_outdelay : std_logic; + signal RXDATAVALID1_outdelay : std_logic; + signal RXSTARTOFSEQ1_outdelay : std_logic; + signal DFEEYEDACMONITOR0_outdelay : std_logic_vector(4 downto 0); + signal DFETAP1MONITOR0_outdelay : std_logic_vector(4 downto 0); + signal DFETAP2MONITOR0_outdelay : std_logic_vector(4 downto 0); + signal DFETAP3MONITOR0_outdelay : std_logic_vector(3 downto 0); + signal DFETAP4MONITOR0_outdelay : std_logic_vector(3 downto 0); + signal DFEEYEDACMONITOR1_outdelay : std_logic_vector(4 downto 0); + signal DFETAP1MONITOR1_outdelay : std_logic_vector(4 downto 0); + signal DFETAP2MONITOR1_outdelay : std_logic_vector(4 downto 0); + signal DFETAP3MONITOR1_outdelay : std_logic_vector(3 downto 0); + signal DFETAP4MONITOR1_outdelay : std_logic_vector(3 downto 0); + signal DFESENSCAL0_outdelay : std_logic_vector(2 downto 0); + signal DFESENSCAL1_outdelay : std_logic_vector(2 downto 0); + + signal CLKIN_ipd : std_ulogic; + signal TXUSRCLK0_ipd : std_ulogic; + signal TXUSRCLK20_ipd : std_ulogic; + signal RXUSRCLK0_ipd : std_ulogic; + signal RXUSRCLK20_ipd : std_ulogic; + signal TXUSRCLK1_ipd : std_ulogic; + signal TXUSRCLK21_ipd : std_ulogic; + signal RXUSRCLK1_ipd : std_ulogic; + signal RXUSRCLK21_ipd : std_ulogic; + signal RXP0_ipd : std_ulogic; + signal RXN0_ipd : std_ulogic; + signal TXDATA0_ipd : std_logic_vector(31 downto 0); + signal TXBYPASS8B10B0_ipd : std_logic_vector(3 downto 0); + signal TXCHARISK0_ipd : std_logic_vector(3 downto 0); + signal TXCHARDISPMODE0_ipd : std_logic_vector(3 downto 0); + signal TXCHARDISPVAL0_ipd : std_logic_vector(3 downto 0); + signal RXP1_ipd : std_ulogic; + signal RXN1_ipd : std_ulogic; + signal TXDATA1_ipd : std_logic_vector(31 downto 0); + signal TXBYPASS8B10B1_ipd : std_logic_vector(3 downto 0); + signal TXCHARISK1_ipd : std_logic_vector(3 downto 0); + signal TXCHARDISPMODE1_ipd : std_logic_vector(3 downto 0); + signal TXCHARDISPVAL1_ipd : std_logic_vector(3 downto 0); + signal GTXRESET_ipd : std_ulogic; + signal RXCDRRESET0_ipd : std_ulogic; + signal TXRESET0_ipd : std_ulogic; + signal RXRESET0_ipd : std_ulogic; + signal RXBUFRESET0_ipd : std_ulogic; + signal RXCDRRESET1_ipd : std_ulogic; + signal TXRESET1_ipd : std_ulogic; + signal RXRESET1_ipd : std_ulogic; + signal RXBUFRESET1_ipd : std_ulogic; + signal TXPOWERDOWN0_ipd : std_logic_vector(1 downto 0); + signal RXPOWERDOWN0_ipd : std_logic_vector(1 downto 0); + signal TXPOWERDOWN1_ipd : std_logic_vector(1 downto 0); + signal RXPOWERDOWN1_ipd : std_logic_vector(1 downto 0); + signal PLLPOWERDOWN_ipd : std_ulogic; + signal REFCLKPWRDNB_ipd : std_ulogic; + signal LOOPBACK0_ipd : std_logic_vector(2 downto 0); + signal LOOPBACK1_ipd : std_logic_vector(2 downto 0); + signal TXDIFFCTRL0_ipd : std_logic_vector(2 downto 0); + signal TXBUFDIFFCTRL0_ipd : std_logic_vector(2 downto 0); + signal TXPREEMPHASIS0_ipd : std_logic_vector(3 downto 0); + signal TXDIFFCTRL1_ipd : std_logic_vector(2 downto 0); + signal TXBUFDIFFCTRL1_ipd : std_logic_vector(2 downto 0); + signal TXPREEMPHASIS1_ipd : std_logic_vector(3 downto 0); + signal RXENEQB0_ipd : std_ulogic; + signal RXEQMIX0_ipd : std_logic_vector(1 downto 0); + signal RXEQPOLE0_ipd : std_logic_vector(3 downto 0); + signal RXENEQB1_ipd : std_ulogic; + signal RXEQMIX1_ipd : std_logic_vector(1 downto 0); + signal RXEQPOLE1_ipd : std_logic_vector(3 downto 0); + signal INTDATAWIDTH_ipd : std_ulogic; + signal TXDATAWIDTH0_ipd : std_logic_vector(1 downto 0); + signal TXDATAWIDTH1_ipd : std_logic_vector(1 downto 0); + signal TXENPMAPHASEALIGN0_ipd : std_ulogic; + signal TXPMASETPHASE0_ipd : std_ulogic; + signal RXENPMAPHASEALIGN0_ipd : std_ulogic; + signal RXPMASETPHASE0_ipd : std_ulogic; + signal TXENPMAPHASEALIGN1_ipd : std_ulogic; + signal TXPMASETPHASE1_ipd : std_ulogic; + signal RXENPMAPHASEALIGN1_ipd : std_ulogic; + signal RXPMASETPHASE1_ipd : std_ulogic; + signal TXENC8B10BUSE0_ipd : std_ulogic; + signal TXPOLARITY0_ipd : std_ulogic; + signal TXINHIBIT0_ipd : std_ulogic; + signal TXENC8B10BUSE1_ipd : std_ulogic; + signal TXPOLARITY1_ipd : std_ulogic; + signal TXINHIBIT1_ipd : std_ulogic; + signal RXPOLARITY0_ipd : std_ulogic; + signal RXENPCOMMAALIGN0_ipd : std_ulogic; + signal RXENMCOMMAALIGN0_ipd : std_ulogic; + signal RXSLIDE0_ipd : std_ulogic; + signal RXCOMMADETUSE0_ipd : std_ulogic; + signal RXDEC8B10BUSE0_ipd : std_ulogic; + signal RXENCHANSYNC0_ipd : std_ulogic; + signal RXCHBONDI0_ipd : std_logic_vector(3 downto 0); + signal RXDATAWIDTH0_ipd : std_logic_vector(1 downto 0); + signal RXPOLARITY1_ipd : std_ulogic; + signal RXENPCOMMAALIGN1_ipd : std_ulogic; + signal RXENMCOMMAALIGN1_ipd : std_ulogic; + signal RXSLIDE1_ipd : std_ulogic; + signal RXCOMMADETUSE1_ipd : std_ulogic; + signal RXDEC8B10BUSE1_ipd : std_ulogic; + signal RXENCHANSYNC1_ipd : std_ulogic; + signal RXCHBONDI1_ipd : std_logic_vector(3 downto 0); + signal RXDATAWIDTH1_ipd : std_logic_vector(1 downto 0); + signal TXELECIDLE0_ipd : std_ulogic; + signal TXDETECTRX0_ipd : std_ulogic; + signal TXELECIDLE1_ipd : std_ulogic; + signal TXDETECTRX1_ipd : std_ulogic; + signal TXCOMSTART0_ipd : std_ulogic; + signal TXCOMTYPE0_ipd : std_ulogic; + signal TXCOMSTART1_ipd : std_ulogic; + signal TXCOMTYPE1_ipd : std_ulogic; + signal PLLLKDETEN_ipd : std_ulogic; + signal TXENPRBSTST0_ipd : std_logic_vector(1 downto 0); + signal RXENPRBSTST0_ipd : std_logic_vector(1 downto 0); + signal PRBSCNTRESET0_ipd : std_ulogic; + signal TXENPRBSTST1_ipd : std_logic_vector(1 downto 0); + signal RXENPRBSTST1_ipd : std_logic_vector(1 downto 0); + signal PRBSCNTRESET1_ipd : std_ulogic; + signal DCLK_ipd : std_ulogic; + signal DADDR_ipd : std_logic_vector(6 downto 0); + signal DI_ipd : std_logic_vector(15 downto 0); + signal DEN_ipd : std_ulogic; + signal DWE_ipd : std_ulogic; + signal RXENSAMPLEALIGN0_ipd : std_ulogic; + signal RXENSAMPLEALIGN1_ipd : std_ulogic; + signal GTXTEST_ipd : std_logic_vector(13 downto 0); + signal TXHEADER0_ipd : std_logic_vector(2 downto 0); + signal TXSEQUENCE0_ipd : std_logic_vector(6 downto 0); + signal TXSTARTSEQ0_ipd : std_ulogic; + signal RXGEARBOXSLIP0_ipd : std_ulogic; + signal TXHEADER1_ipd : std_logic_vector(2 downto 0); + signal TXSEQUENCE1_ipd : std_logic_vector(6 downto 0); + signal TXSTARTSEQ1_ipd : std_ulogic; + signal RXGEARBOXSLIP1_ipd : std_ulogic; + signal DFECLKDLYADJ0_ipd : std_logic_vector(5 downto 0); + signal DFETAP10_ipd : std_logic_vector(4 downto 0); + signal DFETAP20_ipd : std_logic_vector(4 downto 0); + signal DFETAP30_ipd : std_logic_vector(3 downto 0); + signal DFETAP40_ipd : std_logic_vector(3 downto 0); + signal DFECLKDLYADJ1_ipd : std_logic_vector(5 downto 0); + signal DFETAP11_ipd : std_logic_vector(4 downto 0); + signal DFETAP21_ipd : std_logic_vector(4 downto 0); + signal DFETAP31_ipd : std_logic_vector(3 downto 0); + signal DFETAP41_ipd : std_logic_vector(3 downto 0); + + + signal CLKIN_indelay : std_ulogic; + signal TXUSRCLK0_indelay : std_ulogic; + signal TXUSRCLK20_indelay : std_ulogic; + signal RXUSRCLK0_indelay : std_ulogic; + signal RXUSRCLK20_indelay : std_ulogic; + signal TXUSRCLK1_indelay : std_ulogic; + signal TXUSRCLK21_indelay : std_ulogic; + signal RXUSRCLK1_indelay : std_ulogic; + signal RXUSRCLK21_indelay : std_ulogic; + signal RXP0_indelay : std_ulogic; + signal RXN0_indelay : std_ulogic; + signal TXDATA0_indelay : std_logic_vector(31 downto 0); + signal TXBYPASS8B10B0_indelay : std_logic_vector(3 downto 0); + signal TXCHARISK0_indelay : std_logic_vector(3 downto 0); + signal TXCHARDISPMODE0_indelay : std_logic_vector(3 downto 0); + signal TXCHARDISPVAL0_indelay : std_logic_vector(3 downto 0); + signal RXP1_indelay : std_ulogic; + signal RXN1_indelay : std_ulogic; + signal TXDATA1_indelay : std_logic_vector(31 downto 0); + signal TXBYPASS8B10B1_indelay : std_logic_vector(3 downto 0); + signal TXCHARISK1_indelay : std_logic_vector(3 downto 0); + signal TXCHARDISPMODE1_indelay : std_logic_vector(3 downto 0); + signal TXCHARDISPVAL1_indelay : std_logic_vector(3 downto 0); + signal GTXRESET_indelay : std_ulogic; + signal RXCDRRESET0_indelay : std_ulogic; + signal TXRESET0_indelay : std_ulogic; + signal RXRESET0_indelay : std_ulogic; + signal RXBUFRESET0_indelay : std_ulogic; + signal RXCDRRESET1_indelay : std_ulogic; + signal TXRESET1_indelay : std_ulogic; + signal RXRESET1_indelay : std_ulogic; + signal RXBUFRESET1_indelay : std_ulogic; + signal TXPOWERDOWN0_indelay : std_logic_vector(1 downto 0); + signal RXPOWERDOWN0_indelay : std_logic_vector(1 downto 0); + signal TXPOWERDOWN1_indelay : std_logic_vector(1 downto 0); + signal RXPOWERDOWN1_indelay : std_logic_vector(1 downto 0); + signal PLLPOWERDOWN_indelay : std_ulogic; + signal REFCLKPWRDNB_indelay : std_ulogic; + signal LOOPBACK0_indelay : std_logic_vector(2 downto 0); + signal LOOPBACK1_indelay : std_logic_vector(2 downto 0); + signal TXDIFFCTRL0_indelay : std_logic_vector(2 downto 0); + signal TXBUFDIFFCTRL0_indelay : std_logic_vector(2 downto 0); + signal TXPREEMPHASIS0_indelay : std_logic_vector(3 downto 0); + signal TXDIFFCTRL1_indelay : std_logic_vector(2 downto 0); + signal TXBUFDIFFCTRL1_indelay : std_logic_vector(2 downto 0); + signal TXPREEMPHASIS1_indelay : std_logic_vector(3 downto 0); + signal RXENEQB0_indelay : std_ulogic; + signal RXEQMIX0_indelay : std_logic_vector(1 downto 0); + signal RXEQPOLE0_indelay : std_logic_vector(3 downto 0); + signal RXENEQB1_indelay : std_ulogic; + signal RXEQMIX1_indelay : std_logic_vector(1 downto 0); + signal RXEQPOLE1_indelay : std_logic_vector(3 downto 0); + signal INTDATAWIDTH_indelay : std_ulogic; + signal TXDATAWIDTH0_indelay : std_logic_vector(1 downto 0); + signal TXDATAWIDTH1_indelay : std_logic_vector(1 downto 0); + signal TXENPMAPHASEALIGN0_indelay : std_ulogic; + signal TXPMASETPHASE0_indelay : std_ulogic; + signal RXENPMAPHASEALIGN0_indelay : std_ulogic; + signal RXPMASETPHASE0_indelay : std_ulogic; + signal TXENPMAPHASEALIGN1_indelay : std_ulogic; + signal TXPMASETPHASE1_indelay : std_ulogic; + signal RXENPMAPHASEALIGN1_indelay : std_ulogic; + signal RXPMASETPHASE1_indelay : std_ulogic; + signal TXENC8B10BUSE0_indelay : std_ulogic; + signal TXPOLARITY0_indelay : std_ulogic; + signal TXINHIBIT0_indelay : std_ulogic; + signal TXENC8B10BUSE1_indelay : std_ulogic; + signal TXPOLARITY1_indelay : std_ulogic; + signal TXINHIBIT1_indelay : std_ulogic; + signal RXPOLARITY0_indelay : std_ulogic; + signal RXENPCOMMAALIGN0_indelay : std_ulogic; + signal RXENMCOMMAALIGN0_indelay : std_ulogic; + signal RXSLIDE0_indelay : std_ulogic; + signal RXCOMMADETUSE0_indelay : std_ulogic; + signal RXDEC8B10BUSE0_indelay : std_ulogic; + signal RXENCHANSYNC0_indelay : std_ulogic; + signal RXCHBONDI0_indelay : std_logic_vector(3 downto 0); + signal RXDATAWIDTH0_indelay : std_logic_vector(1 downto 0); + signal RXPOLARITY1_indelay : std_ulogic; + signal RXENPCOMMAALIGN1_indelay : std_ulogic; + signal RXENMCOMMAALIGN1_indelay : std_ulogic; + signal RXSLIDE1_indelay : std_ulogic; + signal RXCOMMADETUSE1_indelay : std_ulogic; + signal RXDEC8B10BUSE1_indelay : std_ulogic; + signal RXENCHANSYNC1_indelay : std_ulogic; + signal RXCHBONDI1_indelay : std_logic_vector(3 downto 0); + signal RXDATAWIDTH1_indelay : std_logic_vector(1 downto 0); + signal TXELECIDLE0_indelay : std_ulogic; + signal TXDETECTRX0_indelay : std_ulogic; + signal TXELECIDLE1_indelay : std_ulogic; + signal TXDETECTRX1_indelay : std_ulogic; + signal TXCOMSTART0_indelay : std_ulogic; + signal TXCOMTYPE0_indelay : std_ulogic; + signal TXCOMSTART1_indelay : std_ulogic; + signal TXCOMTYPE1_indelay : std_ulogic; + signal PLLLKDETEN_indelay : std_ulogic; + signal TXENPRBSTST0_indelay : std_logic_vector(1 downto 0); + signal RXENPRBSTST0_indelay : std_logic_vector(1 downto 0); + signal PRBSCNTRESET0_indelay : std_ulogic; + signal TXENPRBSTST1_indelay : std_logic_vector(1 downto 0); + signal RXENPRBSTST1_indelay : std_logic_vector(1 downto 0); + signal PRBSCNTRESET1_indelay : std_ulogic; + signal DCLK_indelay : std_ulogic; + signal DADDR_indelay : std_logic_vector(6 downto 0); + signal DI_indelay : std_logic_vector(15 downto 0); + signal DEN_indelay : std_ulogic; + signal DWE_indelay : std_ulogic; + signal RXENSAMPLEALIGN0_indelay : std_ulogic; + signal RXENSAMPLEALIGN1_indelay : std_ulogic; + signal GTXTEST_indelay : std_logic_vector(13 downto 0); + signal TXHEADER0_indelay : std_logic_vector(2 downto 0); + signal TXSEQUENCE0_indelay : std_logic_vector(6 downto 0); + signal TXSTARTSEQ0_indelay : std_ulogic; + signal RXGEARBOXSLIP0_indelay : std_ulogic; + signal TXHEADER1_indelay : std_logic_vector(2 downto 0); + signal TXSEQUENCE1_indelay : std_logic_vector(6 downto 0); + signal TXSTARTSEQ1_indelay : std_ulogic; + signal RXGEARBOXSLIP1_indelay : std_ulogic; + signal DFECLKDLYADJ0_indelay : std_logic_vector(5 downto 0); + signal DFETAP10_indelay : std_logic_vector(4 downto 0); + signal DFETAP20_indelay : std_logic_vector(4 downto 0); + signal DFETAP30_indelay : std_logic_vector(3 downto 0); + signal DFETAP40_indelay : std_logic_vector(3 downto 0); + signal DFECLKDLYADJ1_indelay : std_logic_vector(5 downto 0); + signal DFETAP11_indelay : std_logic_vector(4 downto 0); + signal DFETAP21_indelay : std_logic_vector(4 downto 0); + signal DFETAP31_indelay : std_logic_vector(3 downto 0); + signal DFETAP41_indelay : std_logic_vector(3 downto 0); + +begin + + DFECLKDLYADJMONITOR0_out <= DFECLKDLYADJMONITOR0_outdelay after CLK_DELAY; + DFECLKDLYADJMONITOR1_out <= DFECLKDLYADJMONITOR1_outdelay after CLK_DELAY; + REFCLKOUT_out <= REFCLKOUT_outdelay after CLK_DELAY; + RXCLKCORCNT0_out <= RXCLKCORCNT0_outdelay after CLK_DELAY; + RXCLKCORCNT1_out <= RXCLKCORCNT1_outdelay after CLK_DELAY; + RXRECCLK0_out <= RXRECCLK0_outdelay after CLK_DELAY; + RXRECCLK1_out <= RXRECCLK1_outdelay after CLK_DELAY; + TXOUTCLK0_out <= TXOUTCLK0_outdelay after CLK_DELAY; + TXOUTCLK1_out <= TXOUTCLK1_outdelay after CLK_DELAY; + + DFEEYEDACMONITOR0_out <= DFEEYEDACMONITOR0_outdelay after OUT_DELAY; + DFEEYEDACMONITOR1_out <= DFEEYEDACMONITOR1_outdelay after OUT_DELAY; + DFESENSCAL0_out <= DFESENSCAL0_outdelay after OUT_DELAY; + DFESENSCAL1_out <= DFESENSCAL1_outdelay after OUT_DELAY; + DFETAP1MONITOR0_out <= DFETAP1MONITOR0_outdelay after OUT_DELAY; + DFETAP1MONITOR1_out <= DFETAP1MONITOR1_outdelay after OUT_DELAY; + DFETAP2MONITOR0_out <= DFETAP2MONITOR0_outdelay after OUT_DELAY; + DFETAP2MONITOR1_out <= DFETAP2MONITOR1_outdelay after OUT_DELAY; + DFETAP3MONITOR0_out <= DFETAP3MONITOR0_outdelay after OUT_DELAY; + DFETAP3MONITOR1_out <= DFETAP3MONITOR1_outdelay after OUT_DELAY; + DFETAP4MONITOR0_out <= DFETAP4MONITOR0_outdelay after OUT_DELAY; + DFETAP4MONITOR1_out <= DFETAP4MONITOR1_outdelay after OUT_DELAY; + DO_out <= DO_outdelay after OUT_DELAY; + DRDY_out <= DRDY_outdelay after OUT_DELAY; + PHYSTATUS0_out <= PHYSTATUS0_outdelay after OUT_DELAY; + PHYSTATUS1_out <= PHYSTATUS1_outdelay after OUT_DELAY; + PLLLKDET_out <= PLLLKDET_outdelay after OUT_DELAY; + RESETDONE0_out <= RESETDONE0_outdelay after OUT_DELAY; + RESETDONE1_out <= RESETDONE1_outdelay after OUT_DELAY; + RXBUFSTATUS0_out <= RXBUFSTATUS0_outdelay after OUT_DELAY; + RXBUFSTATUS1_out <= RXBUFSTATUS1_outdelay after OUT_DELAY; + RXBYTEISALIGNED0_out <= RXBYTEISALIGNED0_outdelay after OUT_DELAY; + RXBYTEISALIGNED1_out <= RXBYTEISALIGNED1_outdelay after OUT_DELAY; + RXBYTEREALIGN0_out <= RXBYTEREALIGN0_outdelay after OUT_DELAY; + RXBYTEREALIGN1_out <= RXBYTEREALIGN1_outdelay after OUT_DELAY; + RXCHANBONDSEQ0_out <= RXCHANBONDSEQ0_outdelay after OUT_DELAY; + RXCHANBONDSEQ1_out <= RXCHANBONDSEQ1_outdelay after OUT_DELAY; + RXCHANISALIGNED0_out <= RXCHANISALIGNED0_outdelay after OUT_DELAY; + RXCHANISALIGNED1_out <= RXCHANISALIGNED1_outdelay after OUT_DELAY; + RXCHANREALIGN0_out <= RXCHANREALIGN0_outdelay after OUT_DELAY; + RXCHANREALIGN1_out <= RXCHANREALIGN1_outdelay after OUT_DELAY; + RXCHARISCOMMA0_out <= RXCHARISCOMMA0_outdelay after OUT_DELAY; + RXCHARISCOMMA1_out <= RXCHARISCOMMA1_outdelay after OUT_DELAY; + RXCHARISK0_out <= RXCHARISK0_outdelay after OUT_DELAY; + RXCHARISK1_out <= RXCHARISK1_outdelay after OUT_DELAY; + RXCHBONDO0_out <= RXCHBONDO0_outdelay after OUT_DELAY; + RXCHBONDO1_out <= RXCHBONDO1_outdelay after OUT_DELAY; + RXCOMMADET0_out <= RXCOMMADET0_outdelay after OUT_DELAY; + RXCOMMADET1_out <= RXCOMMADET1_outdelay after OUT_DELAY; + RXDATA0_out <= RXDATA0_outdelay after OUT_DELAY; + RXDATA1_out <= RXDATA1_outdelay after OUT_DELAY; + RXDATAVALID0_out <= RXDATAVALID0_outdelay after OUT_DELAY; + RXDATAVALID1_out <= RXDATAVALID1_outdelay after OUT_DELAY; + RXDISPERR0_out <= RXDISPERR0_outdelay after OUT_DELAY; + RXDISPERR1_out <= RXDISPERR1_outdelay after OUT_DELAY; + RXELECIDLE0_out <= RXELECIDLE0_outdelay after OUT_DELAY; + RXELECIDLE1_out <= RXELECIDLE1_outdelay after OUT_DELAY; + RXHEADER0_out <= RXHEADER0_outdelay after OUT_DELAY; + RXHEADER1_out <= RXHEADER1_outdelay after OUT_DELAY; + RXHEADERVALID0_out <= RXHEADERVALID0_outdelay after OUT_DELAY; + RXHEADERVALID1_out <= RXHEADERVALID1_outdelay after OUT_DELAY; + RXLOSSOFSYNC0_out <= RXLOSSOFSYNC0_outdelay after OUT_DELAY; + RXLOSSOFSYNC1_out <= RXLOSSOFSYNC1_outdelay after OUT_DELAY; + RXNOTINTABLE0_out <= RXNOTINTABLE0_outdelay after OUT_DELAY; + RXNOTINTABLE1_out <= RXNOTINTABLE1_outdelay after OUT_DELAY; + RXOVERSAMPLEERR0_out <= RXOVERSAMPLEERR0_outdelay after OUT_DELAY; + RXOVERSAMPLEERR1_out <= RXOVERSAMPLEERR1_outdelay after OUT_DELAY; + RXPRBSERR0_out <= RXPRBSERR0_outdelay after OUT_DELAY; + RXPRBSERR1_out <= RXPRBSERR1_outdelay after OUT_DELAY; + RXRUNDISP0_out <= RXRUNDISP0_outdelay after OUT_DELAY; + RXRUNDISP1_out <= RXRUNDISP1_outdelay after OUT_DELAY; + RXSTARTOFSEQ0_out <= RXSTARTOFSEQ0_outdelay after OUT_DELAY; + RXSTARTOFSEQ1_out <= RXSTARTOFSEQ1_outdelay after OUT_DELAY; + RXSTATUS0_out <= RXSTATUS0_outdelay after OUT_DELAY; + RXSTATUS1_out <= RXSTATUS1_outdelay after OUT_DELAY; + RXVALID0_out <= RXVALID0_outdelay after OUT_DELAY; + RXVALID1_out <= RXVALID1_outdelay after OUT_DELAY; + TXBUFSTATUS0_out <= TXBUFSTATUS0_outdelay after OUT_DELAY; + TXBUFSTATUS1_out <= TXBUFSTATUS1_outdelay after OUT_DELAY; + TXGEARBOXREADY0_out <= TXGEARBOXREADY0_outdelay after OUT_DELAY; + TXGEARBOXREADY1_out <= TXGEARBOXREADY1_outdelay after OUT_DELAY; + TXKERR0_out <= TXKERR0_outdelay after OUT_DELAY; + TXKERR1_out <= TXKERR1_outdelay after OUT_DELAY; + TXN0_out <= TXN0_outdelay after OUT_DELAY; + TXN1_out <= TXN1_outdelay after OUT_DELAY; + TXP0_out <= TXP0_outdelay after OUT_DELAY; + TXP1_out <= TXP1_outdelay after OUT_DELAY; + TXRUNDISP0_out <= TXRUNDISP0_outdelay after OUT_DELAY; + TXRUNDISP1_out <= TXRUNDISP1_outdelay after OUT_DELAY; + + DCLK_ipd <= DCLK after CLK_DELAY; + RXUSRCLK0_ipd <= RXUSRCLK0 after CLK_DELAY; + RXUSRCLK1_ipd <= RXUSRCLK1 after CLK_DELAY; + RXUSRCLK20_ipd <= RXUSRCLK20 after CLK_DELAY; + RXUSRCLK21_ipd <= RXUSRCLK21 after CLK_DELAY; + TXUSRCLK0_ipd <= TXUSRCLK0 after CLK_DELAY; + TXUSRCLK1_ipd <= TXUSRCLK1 after CLK_DELAY; + TXUSRCLK20_ipd <= TXUSRCLK20 after CLK_DELAY; + TXUSRCLK21_ipd <= TXUSRCLK21 after CLK_DELAY; + + CLKIN_ipd <= CLKIN after CLK_DELAY; + DADDR_ipd <= DADDR after CLK_DELAY; + DEN_ipd <= DEN after CLK_DELAY; + DFECLKDLYADJ0_ipd <= DFECLKDLYADJ0 after CLK_DELAY; + DFECLKDLYADJ1_ipd <= DFECLKDLYADJ1 after CLK_DELAY; + DFETAP10_ipd <= DFETAP10 after CLK_DELAY; + DFETAP11_ipd <= DFETAP11 after CLK_DELAY; + DFETAP20_ipd <= DFETAP20 after CLK_DELAY; + DFETAP21_ipd <= DFETAP21 after CLK_DELAY; + DFETAP30_ipd <= DFETAP30 after CLK_DELAY; + DFETAP31_ipd <= DFETAP31 after CLK_DELAY; + DFETAP40_ipd <= DFETAP40 after CLK_DELAY; + DFETAP41_ipd <= DFETAP41 after CLK_DELAY; + DI_ipd <= DI after CLK_DELAY; + DWE_ipd <= DWE after CLK_DELAY; + GTXRESET_ipd <= GTXRESET after CLK_DELAY; + GTXTEST_ipd <= GTXTEST after CLK_DELAY; + INTDATAWIDTH_ipd <= INTDATAWIDTH after CLK_DELAY; + LOOPBACK0_ipd <= LOOPBACK0 after CLK_DELAY; + LOOPBACK1_ipd <= LOOPBACK1 after CLK_DELAY; + PLLLKDETEN_ipd <= PLLLKDETEN after CLK_DELAY; + PLLPOWERDOWN_ipd <= PLLPOWERDOWN after CLK_DELAY; + PRBSCNTRESET0_ipd <= PRBSCNTRESET0 after CLK_DELAY; + PRBSCNTRESET1_ipd <= PRBSCNTRESET1 after CLK_DELAY; + REFCLKPWRDNB_ipd <= REFCLKPWRDNB after CLK_DELAY; + RXBUFRESET0_ipd <= RXBUFRESET0 after CLK_DELAY; + RXBUFRESET1_ipd <= RXBUFRESET1 after CLK_DELAY; + RXCDRRESET0_ipd <= RXCDRRESET0 after CLK_DELAY; + RXCDRRESET1_ipd <= RXCDRRESET1 after CLK_DELAY; + RXCHBONDI0_ipd <= RXCHBONDI0 after CLK_DELAY; + RXCHBONDI1_ipd <= RXCHBONDI1 after CLK_DELAY; + RXCOMMADETUSE0_ipd <= RXCOMMADETUSE0 after CLK_DELAY; + RXCOMMADETUSE1_ipd <= RXCOMMADETUSE1 after CLK_DELAY; + RXDATAWIDTH0_ipd <= RXDATAWIDTH0 after CLK_DELAY; + RXDATAWIDTH1_ipd <= RXDATAWIDTH1 after CLK_DELAY; + RXDEC8B10BUSE0_ipd <= RXDEC8B10BUSE0 after CLK_DELAY; + RXDEC8B10BUSE1_ipd <= RXDEC8B10BUSE1 after CLK_DELAY; + RXENCHANSYNC0_ipd <= RXENCHANSYNC0 after CLK_DELAY; + RXENCHANSYNC1_ipd <= RXENCHANSYNC1 after CLK_DELAY; + RXENEQB0_ipd <= RXENEQB0 after CLK_DELAY; + RXENEQB1_ipd <= RXENEQB1 after CLK_DELAY; + RXENMCOMMAALIGN0_ipd <= RXENMCOMMAALIGN0 after CLK_DELAY; + RXENMCOMMAALIGN1_ipd <= RXENMCOMMAALIGN1 after CLK_DELAY; + RXENPCOMMAALIGN0_ipd <= RXENPCOMMAALIGN0 after CLK_DELAY; + RXENPCOMMAALIGN1_ipd <= RXENPCOMMAALIGN1 after CLK_DELAY; + RXENPMAPHASEALIGN0_ipd <= RXENPMAPHASEALIGN0 after CLK_DELAY; + RXENPMAPHASEALIGN1_ipd <= RXENPMAPHASEALIGN1 after CLK_DELAY; + RXENPRBSTST0_ipd <= RXENPRBSTST0 after CLK_DELAY; + RXENPRBSTST1_ipd <= RXENPRBSTST1 after CLK_DELAY; + RXENSAMPLEALIGN0_ipd <= RXENSAMPLEALIGN0 after CLK_DELAY; + RXENSAMPLEALIGN1_ipd <= RXENSAMPLEALIGN1 after CLK_DELAY; + RXEQMIX0_ipd <= RXEQMIX0 after CLK_DELAY; + RXEQMIX1_ipd <= RXEQMIX1 after CLK_DELAY; + RXEQPOLE0_ipd <= RXEQPOLE0 after CLK_DELAY; + RXEQPOLE1_ipd <= RXEQPOLE1 after CLK_DELAY; + RXGEARBOXSLIP0_ipd <= RXGEARBOXSLIP0 after CLK_DELAY; + RXGEARBOXSLIP1_ipd <= RXGEARBOXSLIP1 after CLK_DELAY; + RXN0_ipd <= RXN0 after CLK_DELAY; + RXN1_ipd <= RXN1 after CLK_DELAY; + RXP0_ipd <= RXP0 after CLK_DELAY; + RXP1_ipd <= RXP1 after CLK_DELAY; + RXPMASETPHASE0_ipd <= RXPMASETPHASE0 after CLK_DELAY; + RXPMASETPHASE1_ipd <= RXPMASETPHASE1 after CLK_DELAY; + RXPOLARITY0_ipd <= RXPOLARITY0 after CLK_DELAY; + RXPOLARITY1_ipd <= RXPOLARITY1 after CLK_DELAY; + RXPOWERDOWN0_ipd <= RXPOWERDOWN0 after CLK_DELAY; + RXPOWERDOWN1_ipd <= RXPOWERDOWN1 after CLK_DELAY; + RXRESET0_ipd <= RXRESET0 after CLK_DELAY; + RXRESET1_ipd <= RXRESET1 after CLK_DELAY; + RXSLIDE0_ipd <= RXSLIDE0 after CLK_DELAY; + RXSLIDE1_ipd <= RXSLIDE1 after CLK_DELAY; + TXBUFDIFFCTRL0_ipd <= TXBUFDIFFCTRL0 after CLK_DELAY; + TXBUFDIFFCTRL1_ipd <= TXBUFDIFFCTRL1 after CLK_DELAY; + TXBYPASS8B10B0_ipd <= TXBYPASS8B10B0 after CLK_DELAY; + TXBYPASS8B10B1_ipd <= TXBYPASS8B10B1 after CLK_DELAY; + TXCHARDISPMODE0_ipd <= TXCHARDISPMODE0 after CLK_DELAY; + TXCHARDISPMODE1_ipd <= TXCHARDISPMODE1 after CLK_DELAY; + TXCHARDISPVAL0_ipd <= TXCHARDISPVAL0 after CLK_DELAY; + TXCHARDISPVAL1_ipd <= TXCHARDISPVAL1 after CLK_DELAY; + TXCHARISK0_ipd <= TXCHARISK0 after CLK_DELAY; + TXCHARISK1_ipd <= TXCHARISK1 after CLK_DELAY; + TXCOMSTART0_ipd <= TXCOMSTART0 after CLK_DELAY; + TXCOMSTART1_ipd <= TXCOMSTART1 after CLK_DELAY; + TXCOMTYPE0_ipd <= TXCOMTYPE0 after CLK_DELAY; + TXCOMTYPE1_ipd <= TXCOMTYPE1 after CLK_DELAY; + TXDATA0_ipd <= TXDATA0 after CLK_DELAY; + TXDATA1_ipd <= TXDATA1 after CLK_DELAY; + TXDATAWIDTH0_ipd <= TXDATAWIDTH0 after CLK_DELAY; + TXDATAWIDTH1_ipd <= TXDATAWIDTH1 after CLK_DELAY; + TXDETECTRX0_ipd <= TXDETECTRX0 after CLK_DELAY; + TXDETECTRX1_ipd <= TXDETECTRX1 after CLK_DELAY; + TXDIFFCTRL0_ipd <= TXDIFFCTRL0 after CLK_DELAY; + TXDIFFCTRL1_ipd <= TXDIFFCTRL1 after CLK_DELAY; + TXELECIDLE0_ipd <= TXELECIDLE0 after CLK_DELAY; + TXELECIDLE1_ipd <= TXELECIDLE1 after CLK_DELAY; + TXENC8B10BUSE0_ipd <= TXENC8B10BUSE0 after CLK_DELAY; + TXENC8B10BUSE1_ipd <= TXENC8B10BUSE1 after CLK_DELAY; + TXENPMAPHASEALIGN0_ipd <= TXENPMAPHASEALIGN0 after CLK_DELAY; + TXENPMAPHASEALIGN1_ipd <= TXENPMAPHASEALIGN1 after CLK_DELAY; + TXENPRBSTST0_ipd <= TXENPRBSTST0 after CLK_DELAY; + TXENPRBSTST1_ipd <= TXENPRBSTST1 after CLK_DELAY; + TXHEADER0_ipd <= TXHEADER0 after CLK_DELAY; + TXHEADER1_ipd <= TXHEADER1 after CLK_DELAY; + TXINHIBIT0_ipd <= TXINHIBIT0 after CLK_DELAY; + TXINHIBIT1_ipd <= TXINHIBIT1 after CLK_DELAY; + TXPMASETPHASE0_ipd <= TXPMASETPHASE0 after CLK_DELAY; + TXPMASETPHASE1_ipd <= TXPMASETPHASE1 after CLK_DELAY; + TXPOLARITY0_ipd <= TXPOLARITY0 after CLK_DELAY; + TXPOLARITY1_ipd <= TXPOLARITY1 after CLK_DELAY; + TXPOWERDOWN0_ipd <= TXPOWERDOWN0 after CLK_DELAY; + TXPOWERDOWN1_ipd <= TXPOWERDOWN1 after CLK_DELAY; + TXPREEMPHASIS0_ipd <= TXPREEMPHASIS0 after CLK_DELAY; + TXPREEMPHASIS1_ipd <= TXPREEMPHASIS1 after CLK_DELAY; + TXRESET0_ipd <= TXRESET0 after CLK_DELAY; + TXRESET1_ipd <= TXRESET1 after CLK_DELAY; + TXSEQUENCE0_ipd <= TXSEQUENCE0 after CLK_DELAY; + TXSEQUENCE1_ipd <= TXSEQUENCE1 after CLK_DELAY; + TXSTARTSEQ0_ipd <= TXSTARTSEQ0 after CLK_DELAY; + TXSTARTSEQ1_ipd <= TXSTARTSEQ1 after CLK_DELAY; + + DCLK_indelay <= DCLK_ipd after CLK_DELAY; + RXUSRCLK0_indelay <= RXUSRCLK0_ipd after CLK_DELAY; + RXUSRCLK1_indelay <= RXUSRCLK1_ipd after CLK_DELAY; + RXUSRCLK20_indelay <= RXUSRCLK20_ipd after CLK_DELAY; + RXUSRCLK21_indelay <= RXUSRCLK21_ipd after CLK_DELAY; + TXUSRCLK0_indelay <= TXUSRCLK0_ipd after CLK_DELAY; + TXUSRCLK1_indelay <= TXUSRCLK1_ipd after CLK_DELAY; + TXUSRCLK20_indelay <= TXUSRCLK20_ipd after CLK_DELAY; + TXUSRCLK21_indelay <= TXUSRCLK21_ipd after CLK_DELAY; + + CLKIN_indelay <= CLKIN_ipd after IN_DELAY; + DADDR_indelay <= DADDR_ipd after IN_DELAY; + DEN_indelay <= DEN_ipd after IN_DELAY; + DFECLKDLYADJ0_indelay <= DFECLKDLYADJ0_ipd after IN_DELAY; + DFECLKDLYADJ1_indelay <= DFECLKDLYADJ1_ipd after IN_DELAY; + DFETAP10_indelay <= DFETAP10_ipd after IN_DELAY; + DFETAP11_indelay <= DFETAP11_ipd after IN_DELAY; + DFETAP20_indelay <= DFETAP20_ipd after IN_DELAY; + DFETAP21_indelay <= DFETAP21_ipd after IN_DELAY; + DFETAP30_indelay <= DFETAP30_ipd after IN_DELAY; + DFETAP31_indelay <= DFETAP31_ipd after IN_DELAY; + DFETAP40_indelay <= DFETAP40_ipd after IN_DELAY; + DFETAP41_indelay <= DFETAP41_ipd after IN_DELAY; + DI_indelay <= DI_ipd after IN_DELAY; + DWE_indelay <= DWE_ipd after IN_DELAY; + GTXRESET_indelay <= GTXRESET_ipd after IN_DELAY; + GTXTEST_indelay <= GTXTEST_ipd after IN_DELAY; + INTDATAWIDTH_indelay <= INTDATAWIDTH_ipd after IN_DELAY; + LOOPBACK0_indelay <= LOOPBACK0_ipd after IN_DELAY; + LOOPBACK1_indelay <= LOOPBACK1_ipd after IN_DELAY; + PLLLKDETEN_indelay <= PLLLKDETEN_ipd after IN_DELAY; + PLLPOWERDOWN_indelay <= PLLPOWERDOWN_ipd after IN_DELAY; + PRBSCNTRESET0_indelay <= PRBSCNTRESET0_ipd after IN_DELAY; + PRBSCNTRESET1_indelay <= PRBSCNTRESET1_ipd after IN_DELAY; + REFCLKPWRDNB_indelay <= REFCLKPWRDNB_ipd after IN_DELAY; + RXBUFRESET0_indelay <= RXBUFRESET0_ipd after IN_DELAY; + RXBUFRESET1_indelay <= RXBUFRESET1_ipd after IN_DELAY; + RXCDRRESET0_indelay <= RXCDRRESET0_ipd after IN_DELAY; + RXCDRRESET1_indelay <= RXCDRRESET1_ipd after IN_DELAY; + RXCHBONDI0_indelay <= RXCHBONDI0_ipd after IN_DELAY; + RXCHBONDI1_indelay <= RXCHBONDI1_ipd after IN_DELAY; + RXCOMMADETUSE0_indelay <= RXCOMMADETUSE0_ipd after IN_DELAY; + RXCOMMADETUSE1_indelay <= RXCOMMADETUSE1_ipd after IN_DELAY; + RXDATAWIDTH0_indelay <= RXDATAWIDTH0_ipd after IN_DELAY; + RXDATAWIDTH1_indelay <= RXDATAWIDTH1_ipd after IN_DELAY; + RXDEC8B10BUSE0_indelay <= RXDEC8B10BUSE0_ipd after IN_DELAY; + RXDEC8B10BUSE1_indelay <= RXDEC8B10BUSE1_ipd after IN_DELAY; + RXENCHANSYNC0_indelay <= RXENCHANSYNC0_ipd after IN_DELAY; + RXENCHANSYNC1_indelay <= RXENCHANSYNC1_ipd after IN_DELAY; + RXENEQB0_indelay <= RXENEQB0_ipd after IN_DELAY; + RXENEQB1_indelay <= RXENEQB1_ipd after IN_DELAY; + RXENMCOMMAALIGN0_indelay <= RXENMCOMMAALIGN0_ipd after IN_DELAY; + RXENMCOMMAALIGN1_indelay <= RXENMCOMMAALIGN1_ipd after IN_DELAY; + RXENPCOMMAALIGN0_indelay <= RXENPCOMMAALIGN0_ipd after IN_DELAY; + RXENPCOMMAALIGN1_indelay <= RXENPCOMMAALIGN1_ipd after IN_DELAY; + RXENPMAPHASEALIGN0_indelay <= RXENPMAPHASEALIGN0_ipd after IN_DELAY; + RXENPMAPHASEALIGN1_indelay <= RXENPMAPHASEALIGN1_ipd after IN_DELAY; + RXENPRBSTST0_indelay <= RXENPRBSTST0_ipd after IN_DELAY; + RXENPRBSTST1_indelay <= RXENPRBSTST1_ipd after IN_DELAY; + RXENSAMPLEALIGN0_indelay <= RXENSAMPLEALIGN0_ipd after IN_DELAY; + RXENSAMPLEALIGN1_indelay <= RXENSAMPLEALIGN1_ipd after IN_DELAY; + RXEQMIX0_indelay <= RXEQMIX0_ipd after IN_DELAY; + RXEQMIX1_indelay <= RXEQMIX1_ipd after IN_DELAY; + RXEQPOLE0_indelay <= RXEQPOLE0_ipd after IN_DELAY; + RXEQPOLE1_indelay <= RXEQPOLE1_ipd after IN_DELAY; + RXGEARBOXSLIP0_indelay <= RXGEARBOXSLIP0_ipd after IN_DELAY; + RXGEARBOXSLIP1_indelay <= RXGEARBOXSLIP1_ipd after IN_DELAY; + RXN0_indelay <= RXN0_ipd after IN_DELAY; + RXN1_indelay <= RXN1_ipd after IN_DELAY; + RXP0_indelay <= RXP0_ipd after IN_DELAY; + RXP1_indelay <= RXP1_ipd after IN_DELAY; + RXPMASETPHASE0_indelay <= RXPMASETPHASE0_ipd after IN_DELAY; + RXPMASETPHASE1_indelay <= RXPMASETPHASE1_ipd after IN_DELAY; + RXPOLARITY0_indelay <= RXPOLARITY0_ipd after IN_DELAY; + RXPOLARITY1_indelay <= RXPOLARITY1_ipd after IN_DELAY; + RXPOWERDOWN0_indelay <= RXPOWERDOWN0_ipd after IN_DELAY; + RXPOWERDOWN1_indelay <= RXPOWERDOWN1_ipd after IN_DELAY; + RXRESET0_indelay <= RXRESET0_ipd after IN_DELAY; + RXRESET1_indelay <= RXRESET1_ipd after IN_DELAY; + RXSLIDE0_indelay <= RXSLIDE0_ipd after IN_DELAY; + RXSLIDE1_indelay <= RXSLIDE1_ipd after IN_DELAY; + TXBUFDIFFCTRL0_indelay <= TXBUFDIFFCTRL0_ipd after IN_DELAY; + TXBUFDIFFCTRL1_indelay <= TXBUFDIFFCTRL1_ipd after IN_DELAY; + TXBYPASS8B10B0_indelay <= TXBYPASS8B10B0_ipd after IN_DELAY; + TXBYPASS8B10B1_indelay <= TXBYPASS8B10B1_ipd after IN_DELAY; + TXCHARDISPMODE0_indelay <= TXCHARDISPMODE0_ipd after IN_DELAY; + TXCHARDISPMODE1_indelay <= TXCHARDISPMODE1_ipd after IN_DELAY; + TXCHARDISPVAL0_indelay <= TXCHARDISPVAL0_ipd after IN_DELAY; + TXCHARDISPVAL1_indelay <= TXCHARDISPVAL1_ipd after IN_DELAY; + TXCHARISK0_indelay <= TXCHARISK0_ipd after IN_DELAY; + TXCHARISK1_indelay <= TXCHARISK1_ipd after IN_DELAY; + TXCOMSTART0_indelay <= TXCOMSTART0_ipd after IN_DELAY; + TXCOMSTART1_indelay <= TXCOMSTART1_ipd after IN_DELAY; + TXCOMTYPE0_indelay <= TXCOMTYPE0_ipd after IN_DELAY; + TXCOMTYPE1_indelay <= TXCOMTYPE1_ipd after IN_DELAY; + TXDATA0_indelay <= TXDATA0_ipd after IN_DELAY; + TXDATA1_indelay <= TXDATA1_ipd after IN_DELAY; + TXDATAWIDTH0_indelay <= TXDATAWIDTH0_ipd after IN_DELAY; + TXDATAWIDTH1_indelay <= TXDATAWIDTH1_ipd after IN_DELAY; + TXDETECTRX0_indelay <= TXDETECTRX0_ipd after IN_DELAY; + TXDETECTRX1_indelay <= TXDETECTRX1_ipd after IN_DELAY; + TXDIFFCTRL0_indelay <= TXDIFFCTRL0_ipd after IN_DELAY; + TXDIFFCTRL1_indelay <= TXDIFFCTRL1_ipd after IN_DELAY; + TXELECIDLE0_indelay <= TXELECIDLE0_ipd after IN_DELAY; + TXELECIDLE1_indelay <= TXELECIDLE1_ipd after IN_DELAY; + TXENC8B10BUSE0_indelay <= TXENC8B10BUSE0_ipd after IN_DELAY; + TXENC8B10BUSE1_indelay <= TXENC8B10BUSE1_ipd after IN_DELAY; + TXENPMAPHASEALIGN0_indelay <= TXENPMAPHASEALIGN0_ipd after IN_DELAY; + TXENPMAPHASEALIGN1_indelay <= TXENPMAPHASEALIGN1_ipd after IN_DELAY; + TXENPRBSTST0_indelay <= TXENPRBSTST0_ipd after IN_DELAY; + TXENPRBSTST1_indelay <= TXENPRBSTST1_ipd after IN_DELAY; + TXHEADER0_indelay <= TXHEADER0_ipd after IN_DELAY; + TXHEADER1_indelay <= TXHEADER1_ipd after IN_DELAY; + TXINHIBIT0_indelay <= TXINHIBIT0_ipd after IN_DELAY; + TXINHIBIT1_indelay <= TXINHIBIT1_ipd after IN_DELAY; + TXPMASETPHASE0_indelay <= TXPMASETPHASE0_ipd after IN_DELAY; + TXPMASETPHASE1_indelay <= TXPMASETPHASE1_ipd after IN_DELAY; + TXPOLARITY0_indelay <= TXPOLARITY0_ipd after IN_DELAY; + TXPOLARITY1_indelay <= TXPOLARITY1_ipd after IN_DELAY; + TXPOWERDOWN0_indelay <= TXPOWERDOWN0_ipd after IN_DELAY; + TXPOWERDOWN1_indelay <= TXPOWERDOWN1_ipd after IN_DELAY; + TXPREEMPHASIS0_indelay <= TXPREEMPHASIS0_ipd after IN_DELAY; + TXPREEMPHASIS1_indelay <= TXPREEMPHASIS1_ipd after IN_DELAY; + TXRESET0_indelay <= TXRESET0_ipd after IN_DELAY; + TXRESET1_indelay <= TXRESET1_ipd after IN_DELAY; + TXSEQUENCE0_indelay <= TXSEQUENCE0_ipd after IN_DELAY; + TXSEQUENCE1_indelay <= TXSEQUENCE1_ipd after IN_DELAY; + TXSTARTSEQ0_indelay <= TXSTARTSEQ0_ipd after IN_DELAY; + TXSTARTSEQ1_indelay <= TXSTARTSEQ1_ipd after IN_DELAY; + + + legacy_model: if SIM_MODE = "LEGACY" generate + gtx_dual_swift_bw_1 : GTX_DUAL_SWIFT + port map ( + STEPPING => STEPPING_BINARY, + AC_CAP_DIS_0 => AC_CAP_DIS_0_BINARY, + AC_CAP_DIS_1 => AC_CAP_DIS_1_BINARY, + ALIGN_COMMA_WORD_0 => ALIGN_COMMA_WORD_0_BINARY, + ALIGN_COMMA_WORD_1 => ALIGN_COMMA_WORD_1_BINARY, + CB2_INH_CC_PERIOD_0 => CB2_INH_CC_PERIOD_0_BINARY, + CB2_INH_CC_PERIOD_1 => CB2_INH_CC_PERIOD_1_BINARY, + CDR_PH_ADJ_TIME => CDR_PH_ADJ_TIME_BINARY, + CHAN_BOND_1_MAX_SKEW_0 => CHAN_BOND_1_MAX_SKEW_0_BINARY, + CHAN_BOND_1_MAX_SKEW_1 => CHAN_BOND_1_MAX_SKEW_1_BINARY, + CHAN_BOND_2_MAX_SKEW_0 => CHAN_BOND_2_MAX_SKEW_0_BINARY, + CHAN_BOND_2_MAX_SKEW_1 => CHAN_BOND_2_MAX_SKEW_1_BINARY, + CHAN_BOND_KEEP_ALIGN_0 => CHAN_BOND_KEEP_ALIGN_0_BINARY, + CHAN_BOND_KEEP_ALIGN_1 => CHAN_BOND_KEEP_ALIGN_1_BINARY, + CHAN_BOND_LEVEL_0 => CHAN_BOND_LEVEL_0_BINARY, + CHAN_BOND_LEVEL_1 => CHAN_BOND_LEVEL_1_BINARY, + CHAN_BOND_MODE_0 => CHAN_BOND_MODE_0_BINARY, + CHAN_BOND_MODE_1 => CHAN_BOND_MODE_1_BINARY, + CHAN_BOND_SEQ_1_1_0 => CHAN_BOND_SEQ_1_1_0_BINARY, + CHAN_BOND_SEQ_1_1_1 => CHAN_BOND_SEQ_1_1_1_BINARY, + CHAN_BOND_SEQ_1_2_0 => CHAN_BOND_SEQ_1_2_0_BINARY, + CHAN_BOND_SEQ_1_2_1 => CHAN_BOND_SEQ_1_2_1_BINARY, + CHAN_BOND_SEQ_1_3_0 => CHAN_BOND_SEQ_1_3_0_BINARY, + CHAN_BOND_SEQ_1_3_1 => CHAN_BOND_SEQ_1_3_1_BINARY, + CHAN_BOND_SEQ_1_4_0 => CHAN_BOND_SEQ_1_4_0_BINARY, + CHAN_BOND_SEQ_1_4_1 => CHAN_BOND_SEQ_1_4_1_BINARY, + CHAN_BOND_SEQ_1_ENABLE_0 => CHAN_BOND_SEQ_1_ENABLE_0_BINARY, + CHAN_BOND_SEQ_1_ENABLE_1 => CHAN_BOND_SEQ_1_ENABLE_1_BINARY, + CHAN_BOND_SEQ_2_1_0 => CHAN_BOND_SEQ_2_1_0_BINARY, + CHAN_BOND_SEQ_2_1_1 => CHAN_BOND_SEQ_2_1_1_BINARY, + CHAN_BOND_SEQ_2_2_0 => CHAN_BOND_SEQ_2_2_0_BINARY, + CHAN_BOND_SEQ_2_2_1 => CHAN_BOND_SEQ_2_2_1_BINARY, + CHAN_BOND_SEQ_2_3_0 => CHAN_BOND_SEQ_2_3_0_BINARY, + CHAN_BOND_SEQ_2_3_1 => CHAN_BOND_SEQ_2_3_1_BINARY, + CHAN_BOND_SEQ_2_4_0 => CHAN_BOND_SEQ_2_4_0_BINARY, + CHAN_BOND_SEQ_2_4_1 => CHAN_BOND_SEQ_2_4_1_BINARY, + CHAN_BOND_SEQ_2_ENABLE_0 => CHAN_BOND_SEQ_2_ENABLE_0_BINARY, + CHAN_BOND_SEQ_2_ENABLE_1 => CHAN_BOND_SEQ_2_ENABLE_1_BINARY, + CHAN_BOND_SEQ_2_USE_0 => CHAN_BOND_SEQ_2_USE_0_BINARY, + CHAN_BOND_SEQ_2_USE_1 => CHAN_BOND_SEQ_2_USE_1_BINARY, + CHAN_BOND_SEQ_LEN_0 => CHAN_BOND_SEQ_LEN_0_BINARY, + CHAN_BOND_SEQ_LEN_1 => CHAN_BOND_SEQ_LEN_1_BINARY, + CLK25_DIVIDER => CLK25_DIVIDER_BINARY, + CLKINDC_B => CLKINDC_B_BINARY, + CLKRCV_TRST => CLKRCV_TRST_BINARY, + CLK_CORRECT_USE_0 => CLK_CORRECT_USE_0_BINARY, + CLK_CORRECT_USE_1 => CLK_CORRECT_USE_1_BINARY, + CLK_COR_ADJ_LEN_0 => CLK_COR_ADJ_LEN_0_BINARY, + CLK_COR_ADJ_LEN_1 => CLK_COR_ADJ_LEN_1_BINARY, + CLK_COR_DET_LEN_0 => CLK_COR_DET_LEN_0_BINARY, + CLK_COR_DET_LEN_1 => CLK_COR_DET_LEN_1_BINARY, + CLK_COR_INSERT_IDLE_FLAG_0 => CLK_COR_INSERT_IDLE_FLAG_0_BINARY, + CLK_COR_INSERT_IDLE_FLAG_1 => CLK_COR_INSERT_IDLE_FLAG_1_BINARY, + CLK_COR_KEEP_IDLE_0 => CLK_COR_KEEP_IDLE_0_BINARY, + CLK_COR_KEEP_IDLE_1 => CLK_COR_KEEP_IDLE_1_BINARY, + CLK_COR_MAX_LAT_0 => CLK_COR_MAX_LAT_0_BINARY, + CLK_COR_MAX_LAT_1 => CLK_COR_MAX_LAT_1_BINARY, + CLK_COR_MIN_LAT_0 => CLK_COR_MIN_LAT_0_BINARY, + CLK_COR_MIN_LAT_1 => CLK_COR_MIN_LAT_1_BINARY, + CLK_COR_PRECEDENCE_0 => CLK_COR_PRECEDENCE_0_BINARY, + CLK_COR_PRECEDENCE_1 => CLK_COR_PRECEDENCE_1_BINARY, + CLK_COR_REPEAT_WAIT_0 => CLK_COR_REPEAT_WAIT_0_BINARY, + CLK_COR_REPEAT_WAIT_1 => CLK_COR_REPEAT_WAIT_1_BINARY, + CLK_COR_SEQ_1_1_0 => CLK_COR_SEQ_1_1_0_BINARY, + CLK_COR_SEQ_1_1_1 => CLK_COR_SEQ_1_1_1_BINARY, + CLK_COR_SEQ_1_2_0 => CLK_COR_SEQ_1_2_0_BINARY, + CLK_COR_SEQ_1_2_1 => CLK_COR_SEQ_1_2_1_BINARY, + CLK_COR_SEQ_1_3_0 => CLK_COR_SEQ_1_3_0_BINARY, + CLK_COR_SEQ_1_3_1 => CLK_COR_SEQ_1_3_1_BINARY, + CLK_COR_SEQ_1_4_0 => CLK_COR_SEQ_1_4_0_BINARY, + CLK_COR_SEQ_1_4_1 => CLK_COR_SEQ_1_4_1_BINARY, + CLK_COR_SEQ_1_ENABLE_0 => CLK_COR_SEQ_1_ENABLE_0_BINARY, + CLK_COR_SEQ_1_ENABLE_1 => CLK_COR_SEQ_1_ENABLE_1_BINARY, + CLK_COR_SEQ_2_1_0 => CLK_COR_SEQ_2_1_0_BINARY, + CLK_COR_SEQ_2_1_1 => CLK_COR_SEQ_2_1_1_BINARY, + CLK_COR_SEQ_2_2_0 => CLK_COR_SEQ_2_2_0_BINARY, + CLK_COR_SEQ_2_2_1 => CLK_COR_SEQ_2_2_1_BINARY, + CLK_COR_SEQ_2_3_0 => CLK_COR_SEQ_2_3_0_BINARY, + CLK_COR_SEQ_2_3_1 => CLK_COR_SEQ_2_3_1_BINARY, + CLK_COR_SEQ_2_4_0 => CLK_COR_SEQ_2_4_0_BINARY, + CLK_COR_SEQ_2_4_1 => CLK_COR_SEQ_2_4_1_BINARY, + CLK_COR_SEQ_2_ENABLE_0 => CLK_COR_SEQ_2_ENABLE_0_BINARY, + CLK_COR_SEQ_2_ENABLE_1 => CLK_COR_SEQ_2_ENABLE_1_BINARY, + CLK_COR_SEQ_2_USE_0 => CLK_COR_SEQ_2_USE_0_BINARY, + CLK_COR_SEQ_2_USE_1 => CLK_COR_SEQ_2_USE_1_BINARY, + CM_TRIM_0 => CM_TRIM_0_BINARY, + CM_TRIM_1 => CM_TRIM_1_BINARY, + COMMA_10B_ENABLE_0 => COMMA_10B_ENABLE_0_BINARY, + COMMA_10B_ENABLE_1 => COMMA_10B_ENABLE_1_BINARY, + COMMA_DOUBLE_0 => COMMA_DOUBLE_0_BINARY, + COMMA_DOUBLE_1 => COMMA_DOUBLE_1_BINARY, + COM_BURST_VAL_0 => COM_BURST_VAL_0_BINARY, + COM_BURST_VAL_1 => COM_BURST_VAL_1_BINARY, + DEC_MCOMMA_DETECT_0 => DEC_MCOMMA_DETECT_0_BINARY, + DEC_MCOMMA_DETECT_1 => DEC_MCOMMA_DETECT_1_BINARY, + DEC_PCOMMA_DETECT_0 => DEC_PCOMMA_DETECT_0_BINARY, + DEC_PCOMMA_DETECT_1 => DEC_PCOMMA_DETECT_1_BINARY, + DEC_VALID_COMMA_ONLY_0 => DEC_VALID_COMMA_ONLY_0_BINARY, + DEC_VALID_COMMA_ONLY_1 => DEC_VALID_COMMA_ONLY_1_BINARY, + DFE_CAL_TIME => DFE_CAL_TIME_BINARY, + DFE_CFG_0 => DFE_CFG_0_BINARY, + DFE_CFG_1 => DFE_CFG_1_BINARY, + GEARBOX_ENDEC_0 => GEARBOX_ENDEC_0_BINARY, + GEARBOX_ENDEC_1 => GEARBOX_ENDEC_1_BINARY, + MCOMMA_10B_VALUE_0 => MCOMMA_10B_VALUE_0_BINARY, + MCOMMA_10B_VALUE_1 => MCOMMA_10B_VALUE_1_BINARY, + MCOMMA_DETECT_0 => MCOMMA_DETECT_0_BINARY, + MCOMMA_DETECT_1 => MCOMMA_DETECT_1_BINARY, + OOBDETECT_THRESHOLD_0 => OOBDETECT_THRESHOLD_0_BINARY, + OOBDETECT_THRESHOLD_1 => OOBDETECT_THRESHOLD_1_BINARY, + OOB_CLK_DIVIDER => OOB_CLK_DIVIDER_BINARY, + OVERSAMPLE_MODE => OVERSAMPLE_MODE_BINARY, + PCI_EXPRESS_MODE_0 => PCI_EXPRESS_MODE_0_BINARY, + PCI_EXPRESS_MODE_1 => PCI_EXPRESS_MODE_1_BINARY, + PCOMMA_10B_VALUE_0 => PCOMMA_10B_VALUE_0_BINARY, + PCOMMA_10B_VALUE_1 => PCOMMA_10B_VALUE_1_BINARY, + PCOMMA_DETECT_0 => PCOMMA_DETECT_0_BINARY, + PCOMMA_DETECT_1 => PCOMMA_DETECT_1_BINARY, + PLL_COM_CFG => PLL_COM_CFG_BINARY, + PLL_CP_CFG => PLL_CP_CFG_BINARY, + PLL_DIVSEL_FB => PLL_DIVSEL_FB_BINARY, + PLL_DIVSEL_REF => PLL_DIVSEL_REF_BINARY, + PLL_FB_DCCEN => PLL_FB_DCCEN_BINARY, + PLL_LKDET_CFG => PLL_LKDET_CFG_BINARY, + PLL_RXDIVSEL_OUT_0 => PLL_RXDIVSEL_OUT_0_BINARY, + PLL_RXDIVSEL_OUT_1 => PLL_RXDIVSEL_OUT_1_BINARY, + PLL_SATA_0 => PLL_SATA_0_BINARY, + PLL_SATA_1 => PLL_SATA_1_BINARY, + PLL_TDCC_CFG => PLL_TDCC_CFG_BINARY, + PLL_TXDIVSEL_OUT_0 => PLL_TXDIVSEL_OUT_0_BINARY, + PLL_TXDIVSEL_OUT_1 => PLL_TXDIVSEL_OUT_1_BINARY, + PMA_CDR_SCAN_0 => PMA_CDR_SCAN_0_BINARY, + PMA_CDR_SCAN_1 => PMA_CDR_SCAN_1_BINARY, + PMA_COM_CFG => PMA_COM_CFG_BINARY, + PMA_RXSYNC_CFG_0 => PMA_RXSYNC_CFG_0_BINARY, + PMA_RXSYNC_CFG_1 => PMA_RXSYNC_CFG_1_BINARY, + PMA_RX_CFG_0 => PMA_RX_CFG_0_BINARY, + PMA_RX_CFG_1 => PMA_RX_CFG_1_BINARY, + PMA_TX_CFG_0 => PMA_TX_CFG_0_BINARY, + PMA_TX_CFG_1 => PMA_TX_CFG_1_BINARY, + PRBS_ERR_THRESHOLD_0 => PRBS_ERR_THRESHOLD_0_BINARY, + PRBS_ERR_THRESHOLD_1 => PRBS_ERR_THRESHOLD_1_BINARY, + RCV_TERM_GND_0 => RCV_TERM_GND_0_BINARY, + RCV_TERM_GND_1 => RCV_TERM_GND_1_BINARY, + RCV_TERM_VTTRX_0 => RCV_TERM_VTTRX_0_BINARY, + RCV_TERM_VTTRX_1 => RCV_TERM_VTTRX_1_BINARY, + RXGEARBOX_USE_0 => RXGEARBOX_USE_0_BINARY, + RXGEARBOX_USE_1 => RXGEARBOX_USE_1_BINARY, + RX_BUFFER_USE_0 => RX_BUFFER_USE_0_BINARY, + RX_BUFFER_USE_1 => RX_BUFFER_USE_1_BINARY, + RX_DECODE_SEQ_MATCH_0 => RX_DECODE_SEQ_MATCH_0_BINARY, + RX_DECODE_SEQ_MATCH_1 => RX_DECODE_SEQ_MATCH_1_BINARY, + RX_EN_IDLE_HOLD_CDR => RX_EN_IDLE_HOLD_CDR_BINARY, + RX_EN_IDLE_HOLD_DFE_0 => RX_EN_IDLE_HOLD_DFE_0_BINARY, + RX_EN_IDLE_HOLD_DFE_1 => RX_EN_IDLE_HOLD_DFE_1_BINARY, + RX_EN_IDLE_RESET_BUF_0 => RX_EN_IDLE_RESET_BUF_0_BINARY, + RX_EN_IDLE_RESET_BUF_1 => RX_EN_IDLE_RESET_BUF_1_BINARY, + RX_EN_IDLE_RESET_FR => RX_EN_IDLE_RESET_FR_BINARY, + RX_EN_IDLE_RESET_PH => RX_EN_IDLE_RESET_PH_BINARY, + RX_IDLE_HI_CNT_0 => RX_IDLE_HI_CNT_0_BINARY, + RX_IDLE_HI_CNT_1 => RX_IDLE_HI_CNT_1_BINARY, + RX_IDLE_LO_CNT_0 => RX_IDLE_LO_CNT_0_BINARY, + RX_IDLE_LO_CNT_1 => RX_IDLE_LO_CNT_1_BINARY, + RX_LOSS_OF_SYNC_FSM_0 => RX_LOSS_OF_SYNC_FSM_0_BINARY, + RX_LOSS_OF_SYNC_FSM_1 => RX_LOSS_OF_SYNC_FSM_1_BINARY, + RX_LOS_INVALID_INCR_0 => RX_LOS_INVALID_INCR_0_BINARY, + RX_LOS_INVALID_INCR_1 => RX_LOS_INVALID_INCR_1_BINARY, + RX_LOS_THRESHOLD_0 => RX_LOS_THRESHOLD_0_BINARY, + RX_LOS_THRESHOLD_1 => RX_LOS_THRESHOLD_1_BINARY, + RX_SLIDE_MODE_0 => RX_SLIDE_MODE_0_BINARY, + RX_SLIDE_MODE_1 => RX_SLIDE_MODE_1_BINARY, + RX_STATUS_FMT_0 => RX_STATUS_FMT_0_BINARY, + RX_STATUS_FMT_1 => RX_STATUS_FMT_1_BINARY, + RX_XCLK_SEL_0 => RX_XCLK_SEL_0_BINARY, + RX_XCLK_SEL_1 => RX_XCLK_SEL_1_BINARY, + SATA_BURST_VAL_0 => SATA_BURST_VAL_0_BINARY, + SATA_BURST_VAL_1 => SATA_BURST_VAL_1_BINARY, + SATA_IDLE_VAL_0 => SATA_IDLE_VAL_0_BINARY, + SATA_IDLE_VAL_1 => SATA_IDLE_VAL_1_BINARY, + SATA_MAX_BURST_0 => SATA_MAX_BURST_0_BINARY, + SATA_MAX_BURST_1 => SATA_MAX_BURST_1_BINARY, + SATA_MAX_INIT_0 => SATA_MAX_INIT_0_BINARY, + SATA_MAX_INIT_1 => SATA_MAX_INIT_1_BINARY, + SATA_MAX_WAKE_0 => SATA_MAX_WAKE_0_BINARY, + SATA_MAX_WAKE_1 => SATA_MAX_WAKE_1_BINARY, + SATA_MIN_BURST_0 => SATA_MIN_BURST_0_BINARY, + SATA_MIN_BURST_1 => SATA_MIN_BURST_1_BINARY, + SATA_MIN_INIT_0 => SATA_MIN_INIT_0_BINARY, + SATA_MIN_INIT_1 => SATA_MIN_INIT_1_BINARY, + SATA_MIN_WAKE_0 => SATA_MIN_WAKE_0_BINARY, + SATA_MIN_WAKE_1 => SATA_MIN_WAKE_1_BINARY, + SIM_GTXRESET_SPEEDUP => SIM_GTXRESET_SPEEDUP_BINARY, + SIM_PLL_PERDIV2 => SIM_PLL_PERDIV2_BINARY, + SIM_RECEIVER_DETECT_PASS_0 => SIM_RECEIVER_DETECT_PASS_0_BINARY, + SIM_RECEIVER_DETECT_PASS_1 => SIM_RECEIVER_DETECT_PASS_1_BINARY, + TERMINATION_CTRL => TERMINATION_CTRL_BINARY, + TERMINATION_IMP_0 => TERMINATION_IMP_0_BINARY, + TERMINATION_IMP_1 => TERMINATION_IMP_1_BINARY, + TERMINATION_OVRD => TERMINATION_OVRD_BINARY, + TRANS_TIME_FROM_P2_0 => TRANS_TIME_FROM_P2_0_BINARY, + TRANS_TIME_FROM_P2_1 => TRANS_TIME_FROM_P2_1_BINARY, + TRANS_TIME_NON_P2_0 => TRANS_TIME_NON_P2_0_BINARY, + TRANS_TIME_NON_P2_1 => TRANS_TIME_NON_P2_1_BINARY, + TRANS_TIME_TO_P2_0 => TRANS_TIME_TO_P2_0_BINARY, + TRANS_TIME_TO_P2_1 => TRANS_TIME_TO_P2_1_BINARY, + TXGEARBOX_USE_0 => TXGEARBOX_USE_0_BINARY, + TXGEARBOX_USE_1 => TXGEARBOX_USE_1_BINARY, + TXRX_INVERT_0 => TXRX_INVERT_0_BINARY, + TXRX_INVERT_1 => TXRX_INVERT_1_BINARY, + TX_BUFFER_USE_0 => TX_BUFFER_USE_0_BINARY, + TX_BUFFER_USE_1 => TX_BUFFER_USE_1_BINARY, + TX_DETECT_RX_CFG_0 => TX_DETECT_RX_CFG_0_BINARY, + TX_DETECT_RX_CFG_1 => TX_DETECT_RX_CFG_1_BINARY, + TX_IDLE_DELAY_0 => TX_IDLE_DELAY_0_BINARY, + TX_IDLE_DELAY_1 => TX_IDLE_DELAY_1_BINARY, + TX_XCLK_SEL_0 => TX_XCLK_SEL_0_BINARY, + TX_XCLK_SEL_1 => TX_XCLK_SEL_1_BINARY, + + DFECLKDLYADJMONITOR0 => DFECLKDLYADJMONITOR0_outdelay, + DFECLKDLYADJMONITOR1 => DFECLKDLYADJMONITOR1_outdelay, + DFEEYEDACMONITOR0 => DFEEYEDACMONITOR0_outdelay, + DFEEYEDACMONITOR1 => DFEEYEDACMONITOR1_outdelay, + DFESENSCAL0 => DFESENSCAL0_outdelay, + DFESENSCAL1 => DFESENSCAL1_outdelay, + DFETAP1MONITOR0 => DFETAP1MONITOR0_outdelay, + DFETAP1MONITOR1 => DFETAP1MONITOR1_outdelay, + DFETAP2MONITOR0 => DFETAP2MONITOR0_outdelay, + DFETAP2MONITOR1 => DFETAP2MONITOR1_outdelay, + DFETAP3MONITOR0 => DFETAP3MONITOR0_outdelay, + DFETAP3MONITOR1 => DFETAP3MONITOR1_outdelay, + DFETAP4MONITOR0 => DFETAP4MONITOR0_outdelay, + DFETAP4MONITOR1 => DFETAP4MONITOR1_outdelay, + DO => DO_outdelay, + DRDY => DRDY_outdelay, + PHYSTATUS0 => PHYSTATUS0_outdelay, + PHYSTATUS1 => PHYSTATUS1_outdelay, + PLLLKDET => PLLLKDET_outdelay, + REFCLKOUT => REFCLKOUT_outdelay, + RESETDONE0 => RESETDONE0_outdelay, + RESETDONE1 => RESETDONE1_outdelay, + RXBUFSTATUS0 => RXBUFSTATUS0_outdelay, + RXBUFSTATUS1 => RXBUFSTATUS1_outdelay, + RXBYTEISALIGNED0 => RXBYTEISALIGNED0_outdelay, + RXBYTEISALIGNED1 => RXBYTEISALIGNED1_outdelay, + RXBYTEREALIGN0 => RXBYTEREALIGN0_outdelay, + RXBYTEREALIGN1 => RXBYTEREALIGN1_outdelay, + RXCHANBONDSEQ0 => RXCHANBONDSEQ0_outdelay, + RXCHANBONDSEQ1 => RXCHANBONDSEQ1_outdelay, + RXCHANISALIGNED0 => RXCHANISALIGNED0_outdelay, + RXCHANISALIGNED1 => RXCHANISALIGNED1_outdelay, + RXCHANREALIGN0 => RXCHANREALIGN0_outdelay, + RXCHANREALIGN1 => RXCHANREALIGN1_outdelay, + RXCHARISCOMMA0 => RXCHARISCOMMA0_outdelay, + RXCHARISCOMMA1 => RXCHARISCOMMA1_outdelay, + RXCHARISK0 => RXCHARISK0_outdelay, + RXCHARISK1 => RXCHARISK1_outdelay, + RXCHBONDO0 => RXCHBONDO0_outdelay, + RXCHBONDO1 => RXCHBONDO1_outdelay, + RXCLKCORCNT0 => RXCLKCORCNT0_outdelay, + RXCLKCORCNT1 => RXCLKCORCNT1_outdelay, + RXCOMMADET0 => RXCOMMADET0_outdelay, + RXCOMMADET1 => RXCOMMADET1_outdelay, + RXDATA0 => RXDATA0_outdelay, + RXDATA1 => RXDATA1_outdelay, + RXDATAVALID0 => RXDATAVALID0_outdelay, + RXDATAVALID1 => RXDATAVALID1_outdelay, + RXDISPERR0 => RXDISPERR0_outdelay, + RXDISPERR1 => RXDISPERR1_outdelay, + RXELECIDLE0 => RXELECIDLE0_outdelay, + RXELECIDLE1 => RXELECIDLE1_outdelay, + RXHEADER0 => RXHEADER0_outdelay, + RXHEADER1 => RXHEADER1_outdelay, + RXHEADERVALID0 => RXHEADERVALID0_outdelay, + RXHEADERVALID1 => RXHEADERVALID1_outdelay, + RXLOSSOFSYNC0 => RXLOSSOFSYNC0_outdelay, + RXLOSSOFSYNC1 => RXLOSSOFSYNC1_outdelay, + RXNOTINTABLE0 => RXNOTINTABLE0_outdelay, + RXNOTINTABLE1 => RXNOTINTABLE1_outdelay, + RXOVERSAMPLEERR0 => RXOVERSAMPLEERR0_outdelay, + RXOVERSAMPLEERR1 => RXOVERSAMPLEERR1_outdelay, + RXPRBSERR0 => RXPRBSERR0_outdelay, + RXPRBSERR1 => RXPRBSERR1_outdelay, + RXRECCLK0 => RXRECCLK0_outdelay, + RXRECCLK1 => RXRECCLK1_outdelay, + RXRUNDISP0 => RXRUNDISP0_outdelay, + RXRUNDISP1 => RXRUNDISP1_outdelay, + RXSTARTOFSEQ0 => RXSTARTOFSEQ0_outdelay, + RXSTARTOFSEQ1 => RXSTARTOFSEQ1_outdelay, + RXSTATUS0 => RXSTATUS0_outdelay, + RXSTATUS1 => RXSTATUS1_outdelay, + RXVALID0 => RXVALID0_outdelay, + RXVALID1 => RXVALID1_outdelay, + TXBUFSTATUS0 => TXBUFSTATUS0_outdelay, + TXBUFSTATUS1 => TXBUFSTATUS1_outdelay, + TXGEARBOXREADY0 => TXGEARBOXREADY0_outdelay, + TXGEARBOXREADY1 => TXGEARBOXREADY1_outdelay, + TXKERR0 => TXKERR0_outdelay, + TXKERR1 => TXKERR1_outdelay, + TXN0 => TXN0_outdelay, + TXN1 => TXN1_outdelay, + TXOUTCLK0 => TXOUTCLK0_outdelay, + TXOUTCLK1 => TXOUTCLK1_outdelay, + TXP0 => TXP0_outdelay, + TXP1 => TXP1_outdelay, + TXRUNDISP0 => TXRUNDISP0_outdelay, + TXRUNDISP1 => TXRUNDISP1_outdelay, + + CLKIN => CLKIN_indelay, + DADDR => DADDR_indelay, + DCLK => DCLK_indelay, + DEN => DEN_indelay, + DFECLKDLYADJ0 => DFECLKDLYADJ0_indelay, + DFECLKDLYADJ1 => DFECLKDLYADJ1_indelay, + DFETAP10 => DFETAP10_indelay, + DFETAP11 => DFETAP11_indelay, + DFETAP20 => DFETAP20_indelay, + DFETAP21 => DFETAP21_indelay, + DFETAP30 => DFETAP30_indelay, + DFETAP31 => DFETAP31_indelay, + DFETAP40 => DFETAP40_indelay, + DFETAP41 => DFETAP41_indelay, + DI => DI_indelay, + DWE => DWE_indelay, + GSR => GSR, + GTXRESET => GTXRESET_indelay, + GTXTEST => GTXTEST_indelay, + INTDATAWIDTH => INTDATAWIDTH_indelay, + LOOPBACK0 => LOOPBACK0_indelay, + LOOPBACK1 => LOOPBACK1_indelay, + PLLLKDETEN => PLLLKDETEN_indelay, + PLLPOWERDOWN => PLLPOWERDOWN_indelay, + PRBSCNTRESET0 => PRBSCNTRESET0_indelay, + PRBSCNTRESET1 => PRBSCNTRESET1_indelay, + REFCLKPWRDNB => REFCLKPWRDNB_indelay, + RXBUFRESET0 => RXBUFRESET0_indelay, + RXBUFRESET1 => RXBUFRESET1_indelay, + RXCDRRESET0 => RXCDRRESET0_indelay, + RXCDRRESET1 => RXCDRRESET1_indelay, + RXCHBONDI0 => RXCHBONDI0_indelay, + RXCHBONDI1 => RXCHBONDI1_indelay, + RXCOMMADETUSE0 => RXCOMMADETUSE0_indelay, + RXCOMMADETUSE1 => RXCOMMADETUSE1_indelay, + RXDATAWIDTH0 => RXDATAWIDTH0_indelay, + RXDATAWIDTH1 => RXDATAWIDTH1_indelay, + RXDEC8B10BUSE0 => RXDEC8B10BUSE0_indelay, + RXDEC8B10BUSE1 => RXDEC8B10BUSE1_indelay, + RXENCHANSYNC0 => RXENCHANSYNC0_indelay, + RXENCHANSYNC1 => RXENCHANSYNC1_indelay, + RXENEQB0 => RXENEQB0_indelay, + RXENEQB1 => RXENEQB1_indelay, + RXENMCOMMAALIGN0 => RXENMCOMMAALIGN0_indelay, + RXENMCOMMAALIGN1 => RXENMCOMMAALIGN1_indelay, + RXENPCOMMAALIGN0 => RXENPCOMMAALIGN0_indelay, + RXENPCOMMAALIGN1 => RXENPCOMMAALIGN1_indelay, + RXENPMAPHASEALIGN0 => RXENPMAPHASEALIGN0_indelay, + RXENPMAPHASEALIGN1 => RXENPMAPHASEALIGN1_indelay, + RXENPRBSTST0 => RXENPRBSTST0_indelay, + RXENPRBSTST1 => RXENPRBSTST1_indelay, + RXENSAMPLEALIGN0 => RXENSAMPLEALIGN0_indelay, + RXENSAMPLEALIGN1 => RXENSAMPLEALIGN1_indelay, + RXEQMIX0 => RXEQMIX0_indelay, + RXEQMIX1 => RXEQMIX1_indelay, + RXEQPOLE0 => RXEQPOLE0_indelay, + RXEQPOLE1 => RXEQPOLE1_indelay, + RXGEARBOXSLIP0 => RXGEARBOXSLIP0_indelay, + RXGEARBOXSLIP1 => RXGEARBOXSLIP1_indelay, + RXN0 => RXN0_indelay, + RXN1 => RXN1_indelay, + RXP0 => RXP0_indelay, + RXP1 => RXP1_indelay, + RXPMASETPHASE0 => RXPMASETPHASE0_indelay, + RXPMASETPHASE1 => RXPMASETPHASE1_indelay, + RXPOLARITY0 => RXPOLARITY0_indelay, + RXPOLARITY1 => RXPOLARITY1_indelay, + RXPOWERDOWN0 => RXPOWERDOWN0_indelay, + RXPOWERDOWN1 => RXPOWERDOWN1_indelay, + RXRESET0 => RXRESET0_indelay, + RXRESET1 => RXRESET1_indelay, + RXSLIDE0 => RXSLIDE0_indelay, + RXSLIDE1 => RXSLIDE1_indelay, + RXUSRCLK0 => RXUSRCLK0_indelay, + RXUSRCLK1 => RXUSRCLK1_indelay, + RXUSRCLK20 => RXUSRCLK20_indelay, + RXUSRCLK21 => RXUSRCLK21_indelay, + TXBUFDIFFCTRL0 => TXBUFDIFFCTRL0_indelay, + TXBUFDIFFCTRL1 => TXBUFDIFFCTRL1_indelay, + TXBYPASS8B10B0 => TXBYPASS8B10B0_indelay, + TXBYPASS8B10B1 => TXBYPASS8B10B1_indelay, + TXCHARDISPMODE0 => TXCHARDISPMODE0_indelay, + TXCHARDISPMODE1 => TXCHARDISPMODE1_indelay, + TXCHARDISPVAL0 => TXCHARDISPVAL0_indelay, + TXCHARDISPVAL1 => TXCHARDISPVAL1_indelay, + TXCHARISK0 => TXCHARISK0_indelay, + TXCHARISK1 => TXCHARISK1_indelay, + TXCOMSTART0 => TXCOMSTART0_indelay, + TXCOMSTART1 => TXCOMSTART1_indelay, + TXCOMTYPE0 => TXCOMTYPE0_indelay, + TXCOMTYPE1 => TXCOMTYPE1_indelay, + TXDATA0 => TXDATA0_indelay, + TXDATA1 => TXDATA1_indelay, + TXDATAWIDTH0 => TXDATAWIDTH0_indelay, + TXDATAWIDTH1 => TXDATAWIDTH1_indelay, + TXDETECTRX0 => TXDETECTRX0_indelay, + TXDETECTRX1 => TXDETECTRX1_indelay, + TXDIFFCTRL0 => TXDIFFCTRL0_indelay, + TXDIFFCTRL1 => TXDIFFCTRL1_indelay, + TXELECIDLE0 => TXELECIDLE0_indelay, + TXELECIDLE1 => TXELECIDLE1_indelay, + TXENC8B10BUSE0 => TXENC8B10BUSE0_indelay, + TXENC8B10BUSE1 => TXENC8B10BUSE1_indelay, + TXENPMAPHASEALIGN0 => TXENPMAPHASEALIGN0_indelay, + TXENPMAPHASEALIGN1 => TXENPMAPHASEALIGN1_indelay, + TXENPRBSTST0 => TXENPRBSTST0_indelay, + TXENPRBSTST1 => TXENPRBSTST1_indelay, + TXHEADER0 => TXHEADER0_indelay, + TXHEADER1 => TXHEADER1_indelay, + TXINHIBIT0 => TXINHIBIT0_indelay, + TXINHIBIT1 => TXINHIBIT1_indelay, + TXPMASETPHASE0 => TXPMASETPHASE0_indelay, + TXPMASETPHASE1 => TXPMASETPHASE1_indelay, + TXPOLARITY0 => TXPOLARITY0_indelay, + TXPOLARITY1 => TXPOLARITY1_indelay, + TXPOWERDOWN0 => TXPOWERDOWN0_indelay, + TXPOWERDOWN1 => TXPOWERDOWN1_indelay, + TXPREEMPHASIS0 => TXPREEMPHASIS0_indelay, + TXPREEMPHASIS1 => TXPREEMPHASIS1_indelay, + TXRESET0 => TXRESET0_indelay, + TXRESET1 => TXRESET1_indelay, + TXSEQUENCE0 => TXSEQUENCE0_indelay, + TXSEQUENCE1 => TXSEQUENCE1_indelay, + TXSTARTSEQ0 => TXSTARTSEQ0_indelay, + TXSTARTSEQ1 => TXSTARTSEQ1_indelay, + TXUSRCLK0 => TXUSRCLK0_indelay, + TXUSRCLK1 => TXUSRCLK1_indelay, + TXUSRCLK20 => TXUSRCLK20_indelay, + TXUSRCLK21 => TXUSRCLK21_indelay + ); + end generate legacy_model; + + fast_model: if SIM_MODE = "FAST" generate + gtx_dual_fast_bw_1 : GTX_DUAL_FAST + port map ( + STEPPING => STEPPING_BINARY, + AC_CAP_DIS_0 => AC_CAP_DIS_0_BINARY, + AC_CAP_DIS_1 => AC_CAP_DIS_1_BINARY, + ALIGN_COMMA_WORD_0 => ALIGN_COMMA_WORD_0_BINARY, + ALIGN_COMMA_WORD_1 => ALIGN_COMMA_WORD_1_BINARY, + CB2_INH_CC_PERIOD_0 => CB2_INH_CC_PERIOD_0_BINARY, + CB2_INH_CC_PERIOD_1 => CB2_INH_CC_PERIOD_1_BINARY, + CDR_PH_ADJ_TIME => CDR_PH_ADJ_TIME_BINARY, + CHAN_BOND_1_MAX_SKEW_0 => CHAN_BOND_1_MAX_SKEW_0_BINARY, + CHAN_BOND_1_MAX_SKEW_1 => CHAN_BOND_1_MAX_SKEW_1_BINARY, + CHAN_BOND_2_MAX_SKEW_0 => CHAN_BOND_2_MAX_SKEW_0_BINARY, + CHAN_BOND_2_MAX_SKEW_1 => CHAN_BOND_2_MAX_SKEW_1_BINARY, + CHAN_BOND_KEEP_ALIGN_0 => CHAN_BOND_KEEP_ALIGN_0_BINARY, + CHAN_BOND_KEEP_ALIGN_1 => CHAN_BOND_KEEP_ALIGN_1_BINARY, + CHAN_BOND_LEVEL_0 => CHAN_BOND_LEVEL_0_BINARY, + CHAN_BOND_LEVEL_1 => CHAN_BOND_LEVEL_1_BINARY, + CHAN_BOND_MODE_0 => CHAN_BOND_MODE_0_BINARY, + CHAN_BOND_MODE_1 => CHAN_BOND_MODE_1_BINARY, + CHAN_BOND_SEQ_1_1_0 => CHAN_BOND_SEQ_1_1_0_BINARY, + CHAN_BOND_SEQ_1_1_1 => CHAN_BOND_SEQ_1_1_1_BINARY, + CHAN_BOND_SEQ_1_2_0 => CHAN_BOND_SEQ_1_2_0_BINARY, + CHAN_BOND_SEQ_1_2_1 => CHAN_BOND_SEQ_1_2_1_BINARY, + CHAN_BOND_SEQ_1_3_0 => CHAN_BOND_SEQ_1_3_0_BINARY, + CHAN_BOND_SEQ_1_3_1 => CHAN_BOND_SEQ_1_3_1_BINARY, + CHAN_BOND_SEQ_1_4_0 => CHAN_BOND_SEQ_1_4_0_BINARY, + CHAN_BOND_SEQ_1_4_1 => CHAN_BOND_SEQ_1_4_1_BINARY, + CHAN_BOND_SEQ_1_ENABLE_0 => CHAN_BOND_SEQ_1_ENABLE_0_BINARY, + CHAN_BOND_SEQ_1_ENABLE_1 => CHAN_BOND_SEQ_1_ENABLE_1_BINARY, + CHAN_BOND_SEQ_2_1_0 => CHAN_BOND_SEQ_2_1_0_BINARY, + CHAN_BOND_SEQ_2_1_1 => CHAN_BOND_SEQ_2_1_1_BINARY, + CHAN_BOND_SEQ_2_2_0 => CHAN_BOND_SEQ_2_2_0_BINARY, + CHAN_BOND_SEQ_2_2_1 => CHAN_BOND_SEQ_2_2_1_BINARY, + CHAN_BOND_SEQ_2_3_0 => CHAN_BOND_SEQ_2_3_0_BINARY, + CHAN_BOND_SEQ_2_3_1 => CHAN_BOND_SEQ_2_3_1_BINARY, + CHAN_BOND_SEQ_2_4_0 => CHAN_BOND_SEQ_2_4_0_BINARY, + CHAN_BOND_SEQ_2_4_1 => CHAN_BOND_SEQ_2_4_1_BINARY, + CHAN_BOND_SEQ_2_ENABLE_0 => CHAN_BOND_SEQ_2_ENABLE_0_BINARY, + CHAN_BOND_SEQ_2_ENABLE_1 => CHAN_BOND_SEQ_2_ENABLE_1_BINARY, + CHAN_BOND_SEQ_2_USE_0 => CHAN_BOND_SEQ_2_USE_0_BINARY, + CHAN_BOND_SEQ_2_USE_1 => CHAN_BOND_SEQ_2_USE_1_BINARY, + CHAN_BOND_SEQ_LEN_0 => CHAN_BOND_SEQ_LEN_0_BINARY, + CHAN_BOND_SEQ_LEN_1 => CHAN_BOND_SEQ_LEN_1_BINARY, + CLK25_DIVIDER => CLK25_DIVIDER_BINARY, + CLKINDC_B => CLKINDC_B_BINARY, + CLKRCV_TRST => CLKRCV_TRST_BINARY, + CLK_CORRECT_USE_0 => CLK_CORRECT_USE_0_BINARY, + CLK_CORRECT_USE_1 => CLK_CORRECT_USE_1_BINARY, + CLK_COR_ADJ_LEN_0 => CLK_COR_ADJ_LEN_0_BINARY, + CLK_COR_ADJ_LEN_1 => CLK_COR_ADJ_LEN_1_BINARY, + CLK_COR_DET_LEN_0 => CLK_COR_DET_LEN_0_BINARY, + CLK_COR_DET_LEN_1 => CLK_COR_DET_LEN_1_BINARY, + CLK_COR_INSERT_IDLE_FLAG_0 => CLK_COR_INSERT_IDLE_FLAG_0_BINARY, + CLK_COR_INSERT_IDLE_FLAG_1 => CLK_COR_INSERT_IDLE_FLAG_1_BINARY, + CLK_COR_KEEP_IDLE_0 => CLK_COR_KEEP_IDLE_0_BINARY, + CLK_COR_KEEP_IDLE_1 => CLK_COR_KEEP_IDLE_1_BINARY, + CLK_COR_MAX_LAT_0 => CLK_COR_MAX_LAT_0_BINARY, + CLK_COR_MAX_LAT_1 => CLK_COR_MAX_LAT_1_BINARY, + CLK_COR_MIN_LAT_0 => CLK_COR_MIN_LAT_0_BINARY, + CLK_COR_MIN_LAT_1 => CLK_COR_MIN_LAT_1_BINARY, + CLK_COR_PRECEDENCE_0 => CLK_COR_PRECEDENCE_0_BINARY, + CLK_COR_PRECEDENCE_1 => CLK_COR_PRECEDENCE_1_BINARY, + CLK_COR_REPEAT_WAIT_0 => CLK_COR_REPEAT_WAIT_0_BINARY, + CLK_COR_REPEAT_WAIT_1 => CLK_COR_REPEAT_WAIT_1_BINARY, + CLK_COR_SEQ_1_1_0 => CLK_COR_SEQ_1_1_0_BINARY, + CLK_COR_SEQ_1_1_1 => CLK_COR_SEQ_1_1_1_BINARY, + CLK_COR_SEQ_1_2_0 => CLK_COR_SEQ_1_2_0_BINARY, + CLK_COR_SEQ_1_2_1 => CLK_COR_SEQ_1_2_1_BINARY, + CLK_COR_SEQ_1_3_0 => CLK_COR_SEQ_1_3_0_BINARY, + CLK_COR_SEQ_1_3_1 => CLK_COR_SEQ_1_3_1_BINARY, + CLK_COR_SEQ_1_4_0 => CLK_COR_SEQ_1_4_0_BINARY, + CLK_COR_SEQ_1_4_1 => CLK_COR_SEQ_1_4_1_BINARY, + CLK_COR_SEQ_1_ENABLE_0 => CLK_COR_SEQ_1_ENABLE_0_BINARY, + CLK_COR_SEQ_1_ENABLE_1 => CLK_COR_SEQ_1_ENABLE_1_BINARY, + CLK_COR_SEQ_2_1_0 => CLK_COR_SEQ_2_1_0_BINARY, + CLK_COR_SEQ_2_1_1 => CLK_COR_SEQ_2_1_1_BINARY, + CLK_COR_SEQ_2_2_0 => CLK_COR_SEQ_2_2_0_BINARY, + CLK_COR_SEQ_2_2_1 => CLK_COR_SEQ_2_2_1_BINARY, + CLK_COR_SEQ_2_3_0 => CLK_COR_SEQ_2_3_0_BINARY, + CLK_COR_SEQ_2_3_1 => CLK_COR_SEQ_2_3_1_BINARY, + CLK_COR_SEQ_2_4_0 => CLK_COR_SEQ_2_4_0_BINARY, + CLK_COR_SEQ_2_4_1 => CLK_COR_SEQ_2_4_1_BINARY, + CLK_COR_SEQ_2_ENABLE_0 => CLK_COR_SEQ_2_ENABLE_0_BINARY, + CLK_COR_SEQ_2_ENABLE_1 => CLK_COR_SEQ_2_ENABLE_1_BINARY, + CLK_COR_SEQ_2_USE_0 => CLK_COR_SEQ_2_USE_0_BINARY, + CLK_COR_SEQ_2_USE_1 => CLK_COR_SEQ_2_USE_1_BINARY, + CM_TRIM_0 => CM_TRIM_0_BINARY, + CM_TRIM_1 => CM_TRIM_1_BINARY, + COMMA_10B_ENABLE_0 => COMMA_10B_ENABLE_0_BINARY, + COMMA_10B_ENABLE_1 => COMMA_10B_ENABLE_1_BINARY, + COMMA_DOUBLE_0 => COMMA_DOUBLE_0_BINARY, + COMMA_DOUBLE_1 => COMMA_DOUBLE_1_BINARY, + COM_BURST_VAL_0 => COM_BURST_VAL_0_BINARY, + COM_BURST_VAL_1 => COM_BURST_VAL_1_BINARY, + DEC_MCOMMA_DETECT_0 => DEC_MCOMMA_DETECT_0_BINARY, + DEC_MCOMMA_DETECT_1 => DEC_MCOMMA_DETECT_1_BINARY, + DEC_PCOMMA_DETECT_0 => DEC_PCOMMA_DETECT_0_BINARY, + DEC_PCOMMA_DETECT_1 => DEC_PCOMMA_DETECT_1_BINARY, + DEC_VALID_COMMA_ONLY_0 => DEC_VALID_COMMA_ONLY_0_BINARY, + DEC_VALID_COMMA_ONLY_1 => DEC_VALID_COMMA_ONLY_1_BINARY, + DFE_CAL_TIME => DFE_CAL_TIME_BINARY, + DFE_CFG_0 => DFE_CFG_0_BINARY, + DFE_CFG_1 => DFE_CFG_1_BINARY, + GEARBOX_ENDEC_0 => GEARBOX_ENDEC_0_BINARY, + GEARBOX_ENDEC_1 => GEARBOX_ENDEC_1_BINARY, + MCOMMA_10B_VALUE_0 => MCOMMA_10B_VALUE_0_BINARY, + MCOMMA_10B_VALUE_1 => MCOMMA_10B_VALUE_1_BINARY, + MCOMMA_DETECT_0 => MCOMMA_DETECT_0_BINARY, + MCOMMA_DETECT_1 => MCOMMA_DETECT_1_BINARY, + OOBDETECT_THRESHOLD_0 => OOBDETECT_THRESHOLD_0_BINARY, + OOBDETECT_THRESHOLD_1 => OOBDETECT_THRESHOLD_1_BINARY, + OOB_CLK_DIVIDER => OOB_CLK_DIVIDER_BINARY, + OVERSAMPLE_MODE => OVERSAMPLE_MODE_BINARY, + PCI_EXPRESS_MODE_0 => PCI_EXPRESS_MODE_0_BINARY, + PCI_EXPRESS_MODE_1 => PCI_EXPRESS_MODE_1_BINARY, + PCOMMA_10B_VALUE_0 => PCOMMA_10B_VALUE_0_BINARY, + PCOMMA_10B_VALUE_1 => PCOMMA_10B_VALUE_1_BINARY, + PCOMMA_DETECT_0 => PCOMMA_DETECT_0_BINARY, + PCOMMA_DETECT_1 => PCOMMA_DETECT_1_BINARY, + PLL_COM_CFG => PLL_COM_CFG_BINARY, + PLL_CP_CFG => PLL_CP_CFG_BINARY, + PLL_DIVSEL_FB => PLL_DIVSEL_FB_BINARY, + PLL_DIVSEL_REF => PLL_DIVSEL_REF_BINARY, + PLL_FB_DCCEN => PLL_FB_DCCEN_BINARY, + PLL_LKDET_CFG => PLL_LKDET_CFG_BINARY, + PLL_RXDIVSEL_OUT_0 => PLL_RXDIVSEL_OUT_0_BINARY, + PLL_RXDIVSEL_OUT_1 => PLL_RXDIVSEL_OUT_1_BINARY, + PLL_SATA_0 => PLL_SATA_0_BINARY, + PLL_SATA_1 => PLL_SATA_1_BINARY, + PLL_TDCC_CFG => PLL_TDCC_CFG_BINARY, + PLL_TXDIVSEL_OUT_0 => PLL_TXDIVSEL_OUT_0_BINARY, + PLL_TXDIVSEL_OUT_1 => PLL_TXDIVSEL_OUT_1_BINARY, + PMA_CDR_SCAN_0 => PMA_CDR_SCAN_0_BINARY, + PMA_CDR_SCAN_1 => PMA_CDR_SCAN_1_BINARY, + PMA_COM_CFG => PMA_COM_CFG_BINARY, + PMA_RXSYNC_CFG_0 => PMA_RXSYNC_CFG_0_BINARY, + PMA_RXSYNC_CFG_1 => PMA_RXSYNC_CFG_1_BINARY, + PMA_RX_CFG_0 => PMA_RX_CFG_0_BINARY, + PMA_RX_CFG_1 => PMA_RX_CFG_1_BINARY, + PMA_TX_CFG_0 => PMA_TX_CFG_0_BINARY, + PMA_TX_CFG_1 => PMA_TX_CFG_1_BINARY, + PRBS_ERR_THRESHOLD_0 => PRBS_ERR_THRESHOLD_0_BINARY, + PRBS_ERR_THRESHOLD_1 => PRBS_ERR_THRESHOLD_1_BINARY, + RCV_TERM_GND_0 => RCV_TERM_GND_0_BINARY, + RCV_TERM_GND_1 => RCV_TERM_GND_1_BINARY, + RCV_TERM_VTTRX_0 => RCV_TERM_VTTRX_0_BINARY, + RCV_TERM_VTTRX_1 => RCV_TERM_VTTRX_1_BINARY, + RXGEARBOX_USE_0 => RXGEARBOX_USE_0_BINARY, + RXGEARBOX_USE_1 => RXGEARBOX_USE_1_BINARY, + RX_BUFFER_USE_0 => RX_BUFFER_USE_0_BINARY, + RX_BUFFER_USE_1 => RX_BUFFER_USE_1_BINARY, + RX_DECODE_SEQ_MATCH_0 => RX_DECODE_SEQ_MATCH_0_BINARY, + RX_DECODE_SEQ_MATCH_1 => RX_DECODE_SEQ_MATCH_1_BINARY, + RX_EN_IDLE_HOLD_CDR => RX_EN_IDLE_HOLD_CDR_BINARY, + RX_EN_IDLE_HOLD_DFE_0 => RX_EN_IDLE_HOLD_DFE_0_BINARY, + RX_EN_IDLE_HOLD_DFE_1 => RX_EN_IDLE_HOLD_DFE_1_BINARY, + RX_EN_IDLE_RESET_BUF_0 => RX_EN_IDLE_RESET_BUF_0_BINARY, + RX_EN_IDLE_RESET_BUF_1 => RX_EN_IDLE_RESET_BUF_1_BINARY, + RX_EN_IDLE_RESET_FR => RX_EN_IDLE_RESET_FR_BINARY, + RX_EN_IDLE_RESET_PH => RX_EN_IDLE_RESET_PH_BINARY, + RX_IDLE_HI_CNT_0 => RX_IDLE_HI_CNT_0_BINARY, + RX_IDLE_HI_CNT_1 => RX_IDLE_HI_CNT_1_BINARY, + RX_IDLE_LO_CNT_0 => RX_IDLE_LO_CNT_0_BINARY, + RX_IDLE_LO_CNT_1 => RX_IDLE_LO_CNT_1_BINARY, + RX_LOSS_OF_SYNC_FSM_0 => RX_LOSS_OF_SYNC_FSM_0_BINARY, + RX_LOSS_OF_SYNC_FSM_1 => RX_LOSS_OF_SYNC_FSM_1_BINARY, + RX_LOS_INVALID_INCR_0 => RX_LOS_INVALID_INCR_0_BINARY, + RX_LOS_INVALID_INCR_1 => RX_LOS_INVALID_INCR_1_BINARY, + RX_LOS_THRESHOLD_0 => RX_LOS_THRESHOLD_0_BINARY, + RX_LOS_THRESHOLD_1 => RX_LOS_THRESHOLD_1_BINARY, + RX_SLIDE_MODE_0 => RX_SLIDE_MODE_0_BINARY, + RX_SLIDE_MODE_1 => RX_SLIDE_MODE_1_BINARY, + RX_STATUS_FMT_0 => RX_STATUS_FMT_0_BINARY, + RX_STATUS_FMT_1 => RX_STATUS_FMT_1_BINARY, + RX_XCLK_SEL_0 => RX_XCLK_SEL_0_BINARY, + RX_XCLK_SEL_1 => RX_XCLK_SEL_1_BINARY, + SATA_BURST_VAL_0 => SATA_BURST_VAL_0_BINARY, + SATA_BURST_VAL_1 => SATA_BURST_VAL_1_BINARY, + SATA_IDLE_VAL_0 => SATA_IDLE_VAL_0_BINARY, + SATA_IDLE_VAL_1 => SATA_IDLE_VAL_1_BINARY, + SATA_MAX_BURST_0 => SATA_MAX_BURST_0_BINARY, + SATA_MAX_BURST_1 => SATA_MAX_BURST_1_BINARY, + SATA_MAX_INIT_0 => SATA_MAX_INIT_0_BINARY, + SATA_MAX_INIT_1 => SATA_MAX_INIT_1_BINARY, + SATA_MAX_WAKE_0 => SATA_MAX_WAKE_0_BINARY, + SATA_MAX_WAKE_1 => SATA_MAX_WAKE_1_BINARY, + SATA_MIN_BURST_0 => SATA_MIN_BURST_0_BINARY, + SATA_MIN_BURST_1 => SATA_MIN_BURST_1_BINARY, + SATA_MIN_INIT_0 => SATA_MIN_INIT_0_BINARY, + SATA_MIN_INIT_1 => SATA_MIN_INIT_1_BINARY, + SATA_MIN_WAKE_0 => SATA_MIN_WAKE_0_BINARY, + SATA_MIN_WAKE_1 => SATA_MIN_WAKE_1_BINARY, + SIM_GTXRESET_SPEEDUP => SIM_GTXRESET_SPEEDUP_BINARY, + SIM_PLL_PERDIV2 => SIM_PLL_PERDIV2_BINARY, + SIM_RECEIVER_DETECT_PASS_0 => SIM_RECEIVER_DETECT_PASS_0_BINARY, + SIM_RECEIVER_DETECT_PASS_1 => SIM_RECEIVER_DETECT_PASS_1_BINARY, + TERMINATION_CTRL => TERMINATION_CTRL_BINARY, + TERMINATION_IMP_0 => TERMINATION_IMP_0_BINARY, + TERMINATION_IMP_1 => TERMINATION_IMP_1_BINARY, + TERMINATION_OVRD => TERMINATION_OVRD_BINARY, + TRANS_TIME_FROM_P2_0 => TRANS_TIME_FROM_P2_0_BINARY, + TRANS_TIME_FROM_P2_1 => TRANS_TIME_FROM_P2_1_BINARY, + TRANS_TIME_NON_P2_0 => TRANS_TIME_NON_P2_0_BINARY, + TRANS_TIME_NON_P2_1 => TRANS_TIME_NON_P2_1_BINARY, + TRANS_TIME_TO_P2_0 => TRANS_TIME_TO_P2_0_BINARY, + TRANS_TIME_TO_P2_1 => TRANS_TIME_TO_P2_1_BINARY, + TXGEARBOX_USE_0 => TXGEARBOX_USE_0_BINARY, + TXGEARBOX_USE_1 => TXGEARBOX_USE_1_BINARY, + TXRX_INVERT_0 => TXRX_INVERT_0_BINARY, + TXRX_INVERT_1 => TXRX_INVERT_1_BINARY, + TX_BUFFER_USE_0 => TX_BUFFER_USE_0_BINARY, + TX_BUFFER_USE_1 => TX_BUFFER_USE_1_BINARY, + TX_DETECT_RX_CFG_0 => TX_DETECT_RX_CFG_0_BINARY, + TX_DETECT_RX_CFG_1 => TX_DETECT_RX_CFG_1_BINARY, + TX_IDLE_DELAY_0 => TX_IDLE_DELAY_0_BINARY, + TX_IDLE_DELAY_1 => TX_IDLE_DELAY_1_BINARY, + TX_XCLK_SEL_0 => TX_XCLK_SEL_0_BINARY, + TX_XCLK_SEL_1 => TX_XCLK_SEL_1_BINARY, + + DFECLKDLYADJMONITOR0 => DFECLKDLYADJMONITOR0_outdelay, + DFECLKDLYADJMONITOR1 => DFECLKDLYADJMONITOR1_outdelay, + DFEEYEDACMONITOR0 => DFEEYEDACMONITOR0_outdelay, + DFEEYEDACMONITOR1 => DFEEYEDACMONITOR1_outdelay, + DFESENSCAL0 => DFESENSCAL0_outdelay, + DFESENSCAL1 => DFESENSCAL1_outdelay, + DFETAP1MONITOR0 => DFETAP1MONITOR0_outdelay, + DFETAP1MONITOR1 => DFETAP1MONITOR1_outdelay, + DFETAP2MONITOR0 => DFETAP2MONITOR0_outdelay, + DFETAP2MONITOR1 => DFETAP2MONITOR1_outdelay, + DFETAP3MONITOR0 => DFETAP3MONITOR0_outdelay, + DFETAP3MONITOR1 => DFETAP3MONITOR1_outdelay, + DFETAP4MONITOR0 => DFETAP4MONITOR0_outdelay, + DFETAP4MONITOR1 => DFETAP4MONITOR1_outdelay, + DO => DO_outdelay, + DRDY => DRDY_outdelay, + PHYSTATUS0 => PHYSTATUS0_outdelay, + PHYSTATUS1 => PHYSTATUS1_outdelay, + PLLLKDET => PLLLKDET_outdelay, + REFCLKOUT => REFCLKOUT_outdelay, + RESETDONE0 => RESETDONE0_outdelay, + RESETDONE1 => RESETDONE1_outdelay, + RXBUFSTATUS0 => RXBUFSTATUS0_outdelay, + RXBUFSTATUS1 => RXBUFSTATUS1_outdelay, + RXBYTEISALIGNED0 => RXBYTEISALIGNED0_outdelay, + RXBYTEISALIGNED1 => RXBYTEISALIGNED1_outdelay, + RXBYTEREALIGN0 => RXBYTEREALIGN0_outdelay, + RXBYTEREALIGN1 => RXBYTEREALIGN1_outdelay, + RXCHANBONDSEQ0 => RXCHANBONDSEQ0_outdelay, + RXCHANBONDSEQ1 => RXCHANBONDSEQ1_outdelay, + RXCHANISALIGNED0 => RXCHANISALIGNED0_outdelay, + RXCHANISALIGNED1 => RXCHANISALIGNED1_outdelay, + RXCHANREALIGN0 => RXCHANREALIGN0_outdelay, + RXCHANREALIGN1 => RXCHANREALIGN1_outdelay, + RXCHARISCOMMA0 => RXCHARISCOMMA0_outdelay, + RXCHARISCOMMA1 => RXCHARISCOMMA1_outdelay, + RXCHARISK0 => RXCHARISK0_outdelay, + RXCHARISK1 => RXCHARISK1_outdelay, + RXCHBONDO0 => RXCHBONDO0_outdelay, + RXCHBONDO1 => RXCHBONDO1_outdelay, + RXCLKCORCNT0 => RXCLKCORCNT0_outdelay, + RXCLKCORCNT1 => RXCLKCORCNT1_outdelay, + RXCOMMADET0 => RXCOMMADET0_outdelay, + RXCOMMADET1 => RXCOMMADET1_outdelay, + RXDATA0 => RXDATA0_outdelay, + RXDATA1 => RXDATA1_outdelay, + RXDATAVALID0 => RXDATAVALID0_outdelay, + RXDATAVALID1 => RXDATAVALID1_outdelay, + RXDISPERR0 => RXDISPERR0_outdelay, + RXDISPERR1 => RXDISPERR1_outdelay, + RXELECIDLE0 => RXELECIDLE0_outdelay, + RXELECIDLE1 => RXELECIDLE1_outdelay, + RXHEADER0 => RXHEADER0_outdelay, + RXHEADER1 => RXHEADER1_outdelay, + RXHEADERVALID0 => RXHEADERVALID0_outdelay, + RXHEADERVALID1 => RXHEADERVALID1_outdelay, + RXLOSSOFSYNC0 => RXLOSSOFSYNC0_outdelay, + RXLOSSOFSYNC1 => RXLOSSOFSYNC1_outdelay, + RXNOTINTABLE0 => RXNOTINTABLE0_outdelay, + RXNOTINTABLE1 => RXNOTINTABLE1_outdelay, + RXOVERSAMPLEERR0 => RXOVERSAMPLEERR0_outdelay, + RXOVERSAMPLEERR1 => RXOVERSAMPLEERR1_outdelay, + RXPRBSERR0 => RXPRBSERR0_outdelay, + RXPRBSERR1 => RXPRBSERR1_outdelay, + RXRECCLK0 => RXRECCLK0_outdelay, + RXRECCLK1 => RXRECCLK1_outdelay, + RXRUNDISP0 => RXRUNDISP0_outdelay, + RXRUNDISP1 => RXRUNDISP1_outdelay, + RXSTARTOFSEQ0 => RXSTARTOFSEQ0_outdelay, + RXSTARTOFSEQ1 => RXSTARTOFSEQ1_outdelay, + RXSTATUS0 => RXSTATUS0_outdelay, + RXSTATUS1 => RXSTATUS1_outdelay, + RXVALID0 => RXVALID0_outdelay, + RXVALID1 => RXVALID1_outdelay, + TXBUFSTATUS0 => TXBUFSTATUS0_outdelay, + TXBUFSTATUS1 => TXBUFSTATUS1_outdelay, + TXGEARBOXREADY0 => TXGEARBOXREADY0_outdelay, + TXGEARBOXREADY1 => TXGEARBOXREADY1_outdelay, + TXKERR0 => TXKERR0_outdelay, + TXKERR1 => TXKERR1_outdelay, + TXN0 => TXN0_outdelay, + TXN1 => TXN1_outdelay, + TXOUTCLK0 => TXOUTCLK0_outdelay, + TXOUTCLK1 => TXOUTCLK1_outdelay, + TXP0 => TXP0_outdelay, + TXP1 => TXP1_outdelay, + TXRUNDISP0 => TXRUNDISP0_outdelay, + TXRUNDISP1 => TXRUNDISP1_outdelay, + + CLKIN => CLKIN_indelay, + DADDR => DADDR_indelay, + DCLK => DCLK_indelay, + DEN => DEN_indelay, + DFECLKDLYADJ0 => DFECLKDLYADJ0_indelay, + DFECLKDLYADJ1 => DFECLKDLYADJ1_indelay, + DFETAP10 => DFETAP10_indelay, + DFETAP11 => DFETAP11_indelay, + DFETAP20 => DFETAP20_indelay, + DFETAP21 => DFETAP21_indelay, + DFETAP30 => DFETAP30_indelay, + DFETAP31 => DFETAP31_indelay, + DFETAP40 => DFETAP40_indelay, + DFETAP41 => DFETAP41_indelay, + DI => DI_indelay, + DWE => DWE_indelay, + GSR => GSR, + GTXRESET => GTXRESET_indelay, + GTXTEST => GTXTEST_indelay, + INTDATAWIDTH => INTDATAWIDTH_indelay, + LOOPBACK0 => LOOPBACK0_indelay, + LOOPBACK1 => LOOPBACK1_indelay, + PLLLKDETEN => PLLLKDETEN_indelay, + PLLPOWERDOWN => PLLPOWERDOWN_indelay, + PRBSCNTRESET0 => PRBSCNTRESET0_indelay, + PRBSCNTRESET1 => PRBSCNTRESET1_indelay, + REFCLKPWRDNB => REFCLKPWRDNB_indelay, + RXBUFRESET0 => RXBUFRESET0_indelay, + RXBUFRESET1 => RXBUFRESET1_indelay, + RXCDRRESET0 => RXCDRRESET0_indelay, + RXCDRRESET1 => RXCDRRESET1_indelay, + RXCHBONDI0 => RXCHBONDI0_indelay, + RXCHBONDI1 => RXCHBONDI1_indelay, + RXCOMMADETUSE0 => RXCOMMADETUSE0_indelay, + RXCOMMADETUSE1 => RXCOMMADETUSE1_indelay, + RXDATAWIDTH0 => RXDATAWIDTH0_indelay, + RXDATAWIDTH1 => RXDATAWIDTH1_indelay, + RXDEC8B10BUSE0 => RXDEC8B10BUSE0_indelay, + RXDEC8B10BUSE1 => RXDEC8B10BUSE1_indelay, + RXENCHANSYNC0 => RXENCHANSYNC0_indelay, + RXENCHANSYNC1 => RXENCHANSYNC1_indelay, + RXENEQB0 => RXENEQB0_indelay, + RXENEQB1 => RXENEQB1_indelay, + RXENMCOMMAALIGN0 => RXENMCOMMAALIGN0_indelay, + RXENMCOMMAALIGN1 => RXENMCOMMAALIGN1_indelay, + RXENPCOMMAALIGN0 => RXENPCOMMAALIGN0_indelay, + RXENPCOMMAALIGN1 => RXENPCOMMAALIGN1_indelay, + RXENPMAPHASEALIGN0 => RXENPMAPHASEALIGN0_indelay, + RXENPMAPHASEALIGN1 => RXENPMAPHASEALIGN1_indelay, + RXENPRBSTST0 => RXENPRBSTST0_indelay, + RXENPRBSTST1 => RXENPRBSTST1_indelay, + RXENSAMPLEALIGN0 => RXENSAMPLEALIGN0_indelay, + RXENSAMPLEALIGN1 => RXENSAMPLEALIGN1_indelay, + RXEQMIX0 => RXEQMIX0_indelay, + RXEQMIX1 => RXEQMIX1_indelay, + RXEQPOLE0 => RXEQPOLE0_indelay, + RXEQPOLE1 => RXEQPOLE1_indelay, + RXGEARBOXSLIP0 => RXGEARBOXSLIP0_indelay, + RXGEARBOXSLIP1 => RXGEARBOXSLIP1_indelay, + RXN0 => RXN0_indelay, + RXN1 => RXN1_indelay, + RXP0 => RXP0_indelay, + RXP1 => RXP1_indelay, + RXPMASETPHASE0 => RXPMASETPHASE0_indelay, + RXPMASETPHASE1 => RXPMASETPHASE1_indelay, + RXPOLARITY0 => RXPOLARITY0_indelay, + RXPOLARITY1 => RXPOLARITY1_indelay, + RXPOWERDOWN0 => RXPOWERDOWN0_indelay, + RXPOWERDOWN1 => RXPOWERDOWN1_indelay, + RXRESET0 => RXRESET0_indelay, + RXRESET1 => RXRESET1_indelay, + RXSLIDE0 => RXSLIDE0_indelay, + RXSLIDE1 => RXSLIDE1_indelay, + RXUSRCLK0 => RXUSRCLK0_indelay, + RXUSRCLK1 => RXUSRCLK1_indelay, + RXUSRCLK20 => RXUSRCLK20_indelay, + RXUSRCLK21 => RXUSRCLK21_indelay, + TXBUFDIFFCTRL0 => TXBUFDIFFCTRL0_indelay, + TXBUFDIFFCTRL1 => TXBUFDIFFCTRL1_indelay, + TXBYPASS8B10B0 => TXBYPASS8B10B0_indelay, + TXBYPASS8B10B1 => TXBYPASS8B10B1_indelay, + TXCHARDISPMODE0 => TXCHARDISPMODE0_indelay, + TXCHARDISPMODE1 => TXCHARDISPMODE1_indelay, + TXCHARDISPVAL0 => TXCHARDISPVAL0_indelay, + TXCHARDISPVAL1 => TXCHARDISPVAL1_indelay, + TXCHARISK0 => TXCHARISK0_indelay, + TXCHARISK1 => TXCHARISK1_indelay, + TXCOMSTART0 => TXCOMSTART0_indelay, + TXCOMSTART1 => TXCOMSTART1_indelay, + TXCOMTYPE0 => TXCOMTYPE0_indelay, + TXCOMTYPE1 => TXCOMTYPE1_indelay, + TXDATA0 => TXDATA0_indelay, + TXDATA1 => TXDATA1_indelay, + TXDATAWIDTH0 => TXDATAWIDTH0_indelay, + TXDATAWIDTH1 => TXDATAWIDTH1_indelay, + TXDETECTRX0 => TXDETECTRX0_indelay, + TXDETECTRX1 => TXDETECTRX1_indelay, + TXDIFFCTRL0 => TXDIFFCTRL0_indelay, + TXDIFFCTRL1 => TXDIFFCTRL1_indelay, + TXELECIDLE0 => TXELECIDLE0_indelay, + TXELECIDLE1 => TXELECIDLE1_indelay, + TXENC8B10BUSE0 => TXENC8B10BUSE0_indelay, + TXENC8B10BUSE1 => TXENC8B10BUSE1_indelay, + TXENPMAPHASEALIGN0 => TXENPMAPHASEALIGN0_indelay, + TXENPMAPHASEALIGN1 => TXENPMAPHASEALIGN1_indelay, + TXENPRBSTST0 => TXENPRBSTST0_indelay, + TXENPRBSTST1 => TXENPRBSTST1_indelay, + TXHEADER0 => TXHEADER0_indelay, + TXHEADER1 => TXHEADER1_indelay, + TXINHIBIT0 => TXINHIBIT0_indelay, + TXINHIBIT1 => TXINHIBIT1_indelay, + TXPMASETPHASE0 => TXPMASETPHASE0_indelay, + TXPMASETPHASE1 => TXPMASETPHASE1_indelay, + TXPOLARITY0 => TXPOLARITY0_indelay, + TXPOLARITY1 => TXPOLARITY1_indelay, + TXPOWERDOWN0 => TXPOWERDOWN0_indelay, + TXPOWERDOWN1 => TXPOWERDOWN1_indelay, + TXPREEMPHASIS0 => TXPREEMPHASIS0_indelay, + TXPREEMPHASIS1 => TXPREEMPHASIS1_indelay, + TXRESET0 => TXRESET0_indelay, + TXRESET1 => TXRESET1_indelay, + TXSEQUENCE0 => TXSEQUENCE0_indelay, + TXSEQUENCE1 => TXSEQUENCE1_indelay, + TXSTARTSEQ0 => TXSTARTSEQ0_indelay, + TXSTARTSEQ1 => TXSTARTSEQ1_indelay, + TXUSRCLK0 => TXUSRCLK0_indelay, + TXUSRCLK1 => TXUSRCLK1_indelay, + TXUSRCLK20 => TXUSRCLK20_indelay, + TXUSRCLK21 => TXUSRCLK21_indelay + ); + end generate fast_model; + + INIPROC : process + begin + case PLL_TXDIVSEL_OUT_0 is + when 1 => PLL_TXDIVSEL_OUT_0_BINARY <= "00"; + when 2 => PLL_TXDIVSEL_OUT_0_BINARY <= "01"; + when 4 => PLL_TXDIVSEL_OUT_0_BINARY <= "10"; + when others => assert FALSE report "Error : PLL_TXDIVSEL_OUT_0 is not in 1, 2, 4." severity error; + end case; + case PLL_RXDIVSEL_OUT_0 is + when 1 => PLL_RXDIVSEL_OUT_0_BINARY <= "00"; + when 2 => PLL_RXDIVSEL_OUT_0_BINARY <= "01"; + when 4 => PLL_RXDIVSEL_OUT_0_BINARY <= "10"; + when others => assert FALSE report "Error : PLL_RXDIVSEL_OUT_0 is not in 1, 2, 4." severity error; + end case; + case PLL_TXDIVSEL_OUT_1 is + when 1 => PLL_TXDIVSEL_OUT_1_BINARY <= "00"; + when 2 => PLL_TXDIVSEL_OUT_1_BINARY <= "01"; + when 4 => PLL_TXDIVSEL_OUT_1_BINARY <= "10"; + when others => assert FALSE report "Error : PLL_TXDIVSEL_OUT_1 is not in 1, 2, 4." severity error; + end case; + case PLL_RXDIVSEL_OUT_1 is + when 1 => PLL_RXDIVSEL_OUT_1_BINARY <= "00"; + when 2 => PLL_RXDIVSEL_OUT_1_BINARY <= "01"; + when 4 => PLL_RXDIVSEL_OUT_1_BINARY <= "10"; + when others => assert FALSE report "Error : PLL_RXDIVSEL_OUT_1 is not in 1, 2, 4." severity error; + end case; + case PLL_DIVSEL_FB is + when 1 => PLL_DIVSEL_FB_BINARY <= "10000"; + when 2 => PLL_DIVSEL_FB_BINARY <= "00000"; + when 3 => PLL_DIVSEL_FB_BINARY <= "00001"; + when 4 => PLL_DIVSEL_FB_BINARY <= "00010"; + when 5 => PLL_DIVSEL_FB_BINARY <= "00011"; + when 8 => PLL_DIVSEL_FB_BINARY <= "00110"; + when 10 => PLL_DIVSEL_FB_BINARY <= "00111"; + when others => assert FALSE report "Error : PLL_DIVSEL_FB is not in 1, 2, 3, 4, 5, 8, 10." severity error; + end case; + case PLL_DIVSEL_REF is + when 1 => PLL_DIVSEL_REF_BINARY <= "010000"; + when 2 => PLL_DIVSEL_REF_BINARY <= "000000"; + when 3 => PLL_DIVSEL_REF_BINARY <= "000001"; + when 4 => PLL_DIVSEL_REF_BINARY <= "000010"; + when 5 => PLL_DIVSEL_REF_BINARY <= "000011"; + when 6 => PLL_DIVSEL_REF_BINARY <= "000101"; + when 8 => PLL_DIVSEL_REF_BINARY <= "000110"; + when 10 => PLL_DIVSEL_REF_BINARY <= "000111"; + when 12 => PLL_DIVSEL_REF_BINARY <= "001101"; + when 16 => PLL_DIVSEL_REF_BINARY <= "001110"; + when 20 => PLL_DIVSEL_REF_BINARY <= "001111"; + when others => assert FALSE report "Error : PLL_DIVSEL_REF is not in 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20." severity error; + end case; + case PLL_SATA_0 is + when FALSE => PLL_SATA_0_BINARY <= '0'; + when TRUE => PLL_SATA_0_BINARY <= '1'; + when others => assert FALSE report "Error : PLL_SATA_0 is neither TRUE nor FALSE." severity error; + end case; + case PLL_SATA_1 is + when FALSE => PLL_SATA_1_BINARY <= '0'; + when TRUE => PLL_SATA_1_BINARY <= '1'; + when others => assert FALSE report "Error : PLL_SATA_1 is neither TRUE nor FALSE." severity error; + end case; + case OOB_CLK_DIVIDER is + when 1 => OOB_CLK_DIVIDER_BINARY <= "000"; + when 2 => OOB_CLK_DIVIDER_BINARY <= "001"; + when 4 => OOB_CLK_DIVIDER_BINARY <= "010"; + when 6 => OOB_CLK_DIVIDER_BINARY <= "011"; + when 8 => OOB_CLK_DIVIDER_BINARY <= "100"; + when 10 => OOB_CLK_DIVIDER_BINARY <= "101"; + when 12 => OOB_CLK_DIVIDER_BINARY <= "110"; + when 14 => OOB_CLK_DIVIDER_BINARY <= "111"; + when others => assert FALSE report "Error : OOB_CLK_DIVIDER is not in 1, 2, 4, 6, 8, 10, 12, 14." severity error; + end case; + + if (OOBDETECT_THRESHOLD_0 = "110") then + OOBDETECT_THRESHOLD_0_BINARY <= "110"; + elsif (OOBDETECT_THRESHOLD_0 = "111") then + OOBDETECT_THRESHOLD_0_BINARY <= "111"; + else + assert FALSE report "Warning : OOBDETECT_THRESHOLD_0 is not in 110, 111." severity warning; + end if; + + if (OOBDETECT_THRESHOLD_1 = "110") then + OOBDETECT_THRESHOLD_1_BINARY <= "110"; + elsif (OOBDETECT_THRESHOLD_1 = "111") then + OOBDETECT_THRESHOLD_1_BINARY <= "111"; + else + assert FALSE report "Warning : OOBDETECT_THRESHOLD_1 is not in 110, 111." severity warning; + end if; + + case AC_CAP_DIS_0 is + when FALSE => AC_CAP_DIS_0_BINARY <= '0'; + when TRUE => AC_CAP_DIS_0_BINARY <= '1'; + when others => assert FALSE report "Error : AC_CAP_DIS_0 is neither TRUE nor FALSE." severity error; + end case; + case AC_CAP_DIS_1 is + when FALSE => AC_CAP_DIS_1_BINARY <= '0'; + when TRUE => AC_CAP_DIS_1_BINARY <= '1'; + when others => assert FALSE report "Error : AC_CAP_DIS_1 is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_GND_0 is + when FALSE => RCV_TERM_GND_0_BINARY <= '0'; + when TRUE => RCV_TERM_GND_0_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_GND_0 is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_GND_1 is + when FALSE => RCV_TERM_GND_1_BINARY <= '0'; + when TRUE => RCV_TERM_GND_1_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_GND_1 is neither TRUE nor FALSE." severity error; + end case; + case TERMINATION_IMP_0 is + when 50 => TERMINATION_IMP_0_BINARY <= '0'; + when 75 => TERMINATION_IMP_0_BINARY <= '1'; + when others => assert FALSE report "Error : TERMINATION_IMP_0 is not in 50, 75." severity error; + end case; + case TERMINATION_IMP_1 is + when 50 => TERMINATION_IMP_1_BINARY <= '0'; + when 75 => TERMINATION_IMP_1_BINARY <= '1'; + when others => assert FALSE report "Error : TERMINATION_IMP_1 is not in 50, 75." severity error; + end case; + case TERMINATION_OVRD is + when FALSE => TERMINATION_OVRD_BINARY <= '0'; + when TRUE => TERMINATION_OVRD_BINARY <= '1'; + when others => assert FALSE report "Error : TERMINATION_OVRD is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_VTTRX_0 is + when FALSE => RCV_TERM_VTTRX_0_BINARY <= '0'; + when TRUE => RCV_TERM_VTTRX_0_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_VTTRX_0 is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_VTTRX_1 is + when FALSE => RCV_TERM_VTTRX_1_BINARY <= '0'; + when TRUE => RCV_TERM_VTTRX_1_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_VTTRX_1 is neither TRUE nor FALSE." severity error; + end case; + case CLKINDC_B is + when FALSE => CLKINDC_B_BINARY <= '0'; + when TRUE => CLKINDC_B_BINARY <= '1'; + when others => assert FALSE report "Error : CLKINDC_B is neither TRUE nor FALSE." severity error; + end case; + case PCOMMA_DETECT_0 is + when FALSE => PCOMMA_DETECT_0_BINARY <= '0'; + when TRUE => PCOMMA_DETECT_0_BINARY <= '1'; + when others => assert FALSE report "Error : PCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; + end case; + case MCOMMA_DETECT_0 is + when FALSE => MCOMMA_DETECT_0_BINARY <= '0'; + when TRUE => MCOMMA_DETECT_0_BINARY <= '1'; + when others => assert FALSE report "Error : MCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; + end case; + case COMMA_DOUBLE_0 is + when FALSE => COMMA_DOUBLE_0_BINARY <= '0'; + when TRUE => COMMA_DOUBLE_0_BINARY <= '1'; + when others => assert FALSE report "Error : COMMA_DOUBLE_0 is neither TRUE nor FALSE." severity error; + end case; + case ALIGN_COMMA_WORD_0 is + when 1 => ALIGN_COMMA_WORD_0_BINARY <= '0'; + when 2 => ALIGN_COMMA_WORD_0_BINARY <= '1'; + when others => assert FALSE report "Error : ALIGN_COMMA_WORD_0 is not in 1, 2." severity error; + end case; + case DEC_PCOMMA_DETECT_0 is + when FALSE => DEC_PCOMMA_DETECT_0_BINARY <= '0'; + when TRUE => DEC_PCOMMA_DETECT_0_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_PCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; + end case; + case DEC_MCOMMA_DETECT_0 is + when FALSE => DEC_MCOMMA_DETECT_0_BINARY <= '0'; + when TRUE => DEC_MCOMMA_DETECT_0_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_MCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; + end case; + case DEC_VALID_COMMA_ONLY_0 is + when FALSE => DEC_VALID_COMMA_ONLY_0_BINARY <= '0'; + when TRUE => DEC_VALID_COMMA_ONLY_0_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_VALID_COMMA_ONLY_0 is neither TRUE nor FALSE." severity error; + end case; + case PCOMMA_DETECT_1 is + when FALSE => PCOMMA_DETECT_1_BINARY <= '0'; + when TRUE => PCOMMA_DETECT_1_BINARY <= '1'; + when others => assert FALSE report "Error : PCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; + end case; + case MCOMMA_DETECT_1 is + when FALSE => MCOMMA_DETECT_1_BINARY <= '0'; + when TRUE => MCOMMA_DETECT_1_BINARY <= '1'; + when others => assert FALSE report "Error : MCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; + end case; + case COMMA_DOUBLE_1 is + when FALSE => COMMA_DOUBLE_1_BINARY <= '0'; + when TRUE => COMMA_DOUBLE_1_BINARY <= '1'; + when others => assert FALSE report "Error : COMMA_DOUBLE_1 is neither TRUE nor FALSE." severity error; + end case; + case ALIGN_COMMA_WORD_1 is + when 1 => ALIGN_COMMA_WORD_1_BINARY <= '0'; + when 2 => ALIGN_COMMA_WORD_1_BINARY <= '1'; + when others => assert FALSE report "Error : ALIGN_COMMA_WORD_1 is not in 1, 2." severity error; + end case; + case DEC_PCOMMA_DETECT_1 is + when FALSE => DEC_PCOMMA_DETECT_1_BINARY <= '0'; + when TRUE => DEC_PCOMMA_DETECT_1_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_PCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; + end case; + case DEC_MCOMMA_DETECT_1 is + when FALSE => DEC_MCOMMA_DETECT_1_BINARY <= '0'; + when TRUE => DEC_MCOMMA_DETECT_1_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_MCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; + end case; + case DEC_VALID_COMMA_ONLY_1 is + when FALSE => DEC_VALID_COMMA_ONLY_1_BINARY <= '0'; + when TRUE => DEC_VALID_COMMA_ONLY_1_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_VALID_COMMA_ONLY_1 is neither TRUE nor FALSE." severity error; + end case; + case RX_LOSS_OF_SYNC_FSM_0 is + when FALSE => RX_LOSS_OF_SYNC_FSM_0_BINARY <= '0'; + when TRUE => RX_LOSS_OF_SYNC_FSM_0_BINARY <= '1'; + when others => assert FALSE report "Error : RX_LOSS_OF_SYNC_FSM_0 is neither TRUE nor FALSE." severity error; + end case; + case RX_LOS_INVALID_INCR_0 is + when 1 => RX_LOS_INVALID_INCR_0_BINARY <= "000"; + when 2 => RX_LOS_INVALID_INCR_0_BINARY <= "001"; + when 4 => RX_LOS_INVALID_INCR_0_BINARY <= "010"; + when 8 => RX_LOS_INVALID_INCR_0_BINARY <= "011"; + when 16 => RX_LOS_INVALID_INCR_0_BINARY <= "100"; + when 32 => RX_LOS_INVALID_INCR_0_BINARY <= "101"; + when 64 => RX_LOS_INVALID_INCR_0_BINARY <= "110"; + when 128 => RX_LOS_INVALID_INCR_0_BINARY <= "111"; + when others => assert FALSE report "Error : RX_LOS_INVALID_INCR_0 is not in 1, 2, 4, 8, 16, 32, 64, 128." severity error; + end case; + case RX_LOS_THRESHOLD_0 is + when 4 => RX_LOS_THRESHOLD_0_BINARY <= "000"; + when 8 => RX_LOS_THRESHOLD_0_BINARY <= "001"; + when 16 => RX_LOS_THRESHOLD_0_BINARY <= "010"; + when 32 => RX_LOS_THRESHOLD_0_BINARY <= "011"; + when 64 => RX_LOS_THRESHOLD_0_BINARY <= "100"; + when 128 => RX_LOS_THRESHOLD_0_BINARY <= "101"; + when 256 => RX_LOS_THRESHOLD_0_BINARY <= "110"; + when 512 => RX_LOS_THRESHOLD_0_BINARY <= "111"; + when others => assert FALSE report "Error : RX_LOS_THRESHOLD_0 is not in 4, 8, 16, 32, 64, 128, 256, 512." severity error; + end case; + case RX_LOSS_OF_SYNC_FSM_1 is + when FALSE => RX_LOSS_OF_SYNC_FSM_1_BINARY <= '0'; + when TRUE => RX_LOSS_OF_SYNC_FSM_1_BINARY <= '1'; + when others => assert FALSE report "Error : RX_LOSS_OF_SYNC_FSM_1 is neither TRUE nor FALSE." severity error; + end case; + case RX_LOS_INVALID_INCR_1 is + when 1 => RX_LOS_INVALID_INCR_1_BINARY <= "000"; + when 2 => RX_LOS_INVALID_INCR_1_BINARY <= "001"; + when 4 => RX_LOS_INVALID_INCR_1_BINARY <= "010"; + when 8 => RX_LOS_INVALID_INCR_1_BINARY <= "011"; + when 16 => RX_LOS_INVALID_INCR_1_BINARY <= "100"; + when 32 => RX_LOS_INVALID_INCR_1_BINARY <= "101"; + when 64 => RX_LOS_INVALID_INCR_1_BINARY <= "110"; + when 128 => RX_LOS_INVALID_INCR_1_BINARY <= "111"; + when others => assert FALSE report "Error : RX_LOS_INVALID_INCR_1 is not in 1, 2, 4, 8, 16, 32, 64, 128." severity error; + end case; + case RX_LOS_THRESHOLD_1 is + when 4 => RX_LOS_THRESHOLD_1_BINARY <= "000"; + when 8 => RX_LOS_THRESHOLD_1_BINARY <= "001"; + when 16 => RX_LOS_THRESHOLD_1_BINARY <= "010"; + when 32 => RX_LOS_THRESHOLD_1_BINARY <= "011"; + when 64 => RX_LOS_THRESHOLD_1_BINARY <= "100"; + when 128 => RX_LOS_THRESHOLD_1_BINARY <= "101"; + when 256 => RX_LOS_THRESHOLD_1_BINARY <= "110"; + when 512 => RX_LOS_THRESHOLD_1_BINARY <= "111"; + when others => assert FALSE report "Error : RX_LOS_THRESHOLD_1 is not in 4, 8, 16, 32, 64, 128, 256, 512." severity error; + end case; + case RX_BUFFER_USE_0 is + when FALSE => RX_BUFFER_USE_0_BINARY <= '0'; + when TRUE => RX_BUFFER_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : RX_BUFFER_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case RX_DECODE_SEQ_MATCH_0 is + when FALSE => RX_DECODE_SEQ_MATCH_0_BINARY <= '0'; + when TRUE => RX_DECODE_SEQ_MATCH_0_BINARY <= '1'; + when others => assert FALSE report "Error : RX_DECODE_SEQ_MATCH_0 is neither TRUE nor FALSE." severity error; + end case; + case RX_BUFFER_USE_1 is + when FALSE => RX_BUFFER_USE_1_BINARY <= '0'; + when TRUE => RX_BUFFER_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : RX_BUFFER_USE_1 is neither TRUE nor FALSE." severity error; + end case; + case RX_DECODE_SEQ_MATCH_1 is + when FALSE => RX_DECODE_SEQ_MATCH_1_BINARY <= '0'; + when TRUE => RX_DECODE_SEQ_MATCH_1_BINARY <= '1'; + when others => assert FALSE report "Error : RX_DECODE_SEQ_MATCH_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_MIN_LAT_0 is + when 3 => CLK_COR_MIN_LAT_0_BINARY <= "000011"; + when 4 => CLK_COR_MIN_LAT_0_BINARY <= "000100"; + when 5 => CLK_COR_MIN_LAT_0_BINARY <= "000101"; + when 6 => CLK_COR_MIN_LAT_0_BINARY <= "000110"; + when 7 => CLK_COR_MIN_LAT_0_BINARY <= "000111"; + when 8 => CLK_COR_MIN_LAT_0_BINARY <= "001000"; + when 9 => CLK_COR_MIN_LAT_0_BINARY <= "001001"; + when 10 => CLK_COR_MIN_LAT_0_BINARY <= "001010"; + when 11 => CLK_COR_MIN_LAT_0_BINARY <= "001011"; + when 12 => CLK_COR_MIN_LAT_0_BINARY <= "001100"; + when 13 => CLK_COR_MIN_LAT_0_BINARY <= "001101"; + when 14 => CLK_COR_MIN_LAT_0_BINARY <= "001110"; + when 15 => CLK_COR_MIN_LAT_0_BINARY <= "001111"; + when 16 => CLK_COR_MIN_LAT_0_BINARY <= "010000"; + when 17 => CLK_COR_MIN_LAT_0_BINARY <= "010001"; + when 18 => CLK_COR_MIN_LAT_0_BINARY <= "010010"; + when 19 => CLK_COR_MIN_LAT_0_BINARY <= "010011"; + when 20 => CLK_COR_MIN_LAT_0_BINARY <= "010100"; + when 21 => CLK_COR_MIN_LAT_0_BINARY <= "010101"; + when 22 => CLK_COR_MIN_LAT_0_BINARY <= "010110"; + when 23 => CLK_COR_MIN_LAT_0_BINARY <= "010111"; + when 24 => CLK_COR_MIN_LAT_0_BINARY <= "011000"; + when 25 => CLK_COR_MIN_LAT_0_BINARY <= "011001"; + when 26 => CLK_COR_MIN_LAT_0_BINARY <= "011010"; + when 27 => CLK_COR_MIN_LAT_0_BINARY <= "011011"; + when 28 => CLK_COR_MIN_LAT_0_BINARY <= "011100"; + when 29 => CLK_COR_MIN_LAT_0_BINARY <= "011101"; + when 30 => CLK_COR_MIN_LAT_0_BINARY <= "011110"; + when 31 => CLK_COR_MIN_LAT_0_BINARY <= "011111"; + when 32 => CLK_COR_MIN_LAT_0_BINARY <= "100000"; + when 33 => CLK_COR_MIN_LAT_0_BINARY <= "100001"; + when 34 => CLK_COR_MIN_LAT_0_BINARY <= "100010"; + when 35 => CLK_COR_MIN_LAT_0_BINARY <= "100011"; + when 36 => CLK_COR_MIN_LAT_0_BINARY <= "100100"; + when 37 => CLK_COR_MIN_LAT_0_BINARY <= "100101"; + when 38 => CLK_COR_MIN_LAT_0_BINARY <= "100110"; + when 39 => CLK_COR_MIN_LAT_0_BINARY <= "100111"; + when 40 => CLK_COR_MIN_LAT_0_BINARY <= "101000"; + when 41 => CLK_COR_MIN_LAT_0_BINARY <= "101001"; + when 42 => CLK_COR_MIN_LAT_0_BINARY <= "101010"; + when 43 => CLK_COR_MIN_LAT_0_BINARY <= "101011"; + when 44 => CLK_COR_MIN_LAT_0_BINARY <= "101100"; + when 45 => CLK_COR_MIN_LAT_0_BINARY <= "101101"; + when 46 => CLK_COR_MIN_LAT_0_BINARY <= "101110"; + when 47 => CLK_COR_MIN_LAT_0_BINARY <= "101111"; + when 48 => CLK_COR_MIN_LAT_0_BINARY <= "110000"; + when others => assert FALSE report "Error : CLK_COR_MIN_LAT_0 is not in range 3...48." severity error; + end case; + case CLK_COR_MAX_LAT_0 is + when 3 => CLK_COR_MAX_LAT_0_BINARY <= "000011"; + when 4 => CLK_COR_MAX_LAT_0_BINARY <= "000100"; + when 5 => CLK_COR_MAX_LAT_0_BINARY <= "000101"; + when 6 => CLK_COR_MAX_LAT_0_BINARY <= "000110"; + when 7 => CLK_COR_MAX_LAT_0_BINARY <= "000111"; + when 8 => CLK_COR_MAX_LAT_0_BINARY <= "001000"; + when 9 => CLK_COR_MAX_LAT_0_BINARY <= "001001"; + when 10 => CLK_COR_MAX_LAT_0_BINARY <= "001010"; + when 11 => CLK_COR_MAX_LAT_0_BINARY <= "001011"; + when 12 => CLK_COR_MAX_LAT_0_BINARY <= "001100"; + when 13 => CLK_COR_MAX_LAT_0_BINARY <= "001101"; + when 14 => CLK_COR_MAX_LAT_0_BINARY <= "001110"; + when 15 => CLK_COR_MAX_LAT_0_BINARY <= "001111"; + when 16 => CLK_COR_MAX_LAT_0_BINARY <= "010000"; + when 17 => CLK_COR_MAX_LAT_0_BINARY <= "010001"; + when 18 => CLK_COR_MAX_LAT_0_BINARY <= "010010"; + when 19 => CLK_COR_MAX_LAT_0_BINARY <= "010011"; + when 20 => CLK_COR_MAX_LAT_0_BINARY <= "010100"; + when 21 => CLK_COR_MAX_LAT_0_BINARY <= "010101"; + when 22 => CLK_COR_MAX_LAT_0_BINARY <= "010110"; + when 23 => CLK_COR_MAX_LAT_0_BINARY <= "010111"; + when 24 => CLK_COR_MAX_LAT_0_BINARY <= "011000"; + when 25 => CLK_COR_MAX_LAT_0_BINARY <= "011001"; + when 26 => CLK_COR_MAX_LAT_0_BINARY <= "011010"; + when 27 => CLK_COR_MAX_LAT_0_BINARY <= "011011"; + when 28 => CLK_COR_MAX_LAT_0_BINARY <= "011100"; + when 29 => CLK_COR_MAX_LAT_0_BINARY <= "011101"; + when 30 => CLK_COR_MAX_LAT_0_BINARY <= "011110"; + when 31 => CLK_COR_MAX_LAT_0_BINARY <= "011111"; + when 32 => CLK_COR_MAX_LAT_0_BINARY <= "100000"; + when 33 => CLK_COR_MAX_LAT_0_BINARY <= "100001"; + when 34 => CLK_COR_MAX_LAT_0_BINARY <= "100010"; + when 35 => CLK_COR_MAX_LAT_0_BINARY <= "100011"; + when 36 => CLK_COR_MAX_LAT_0_BINARY <= "100100"; + when 37 => CLK_COR_MAX_LAT_0_BINARY <= "100101"; + when 38 => CLK_COR_MAX_LAT_0_BINARY <= "100110"; + when 39 => CLK_COR_MAX_LAT_0_BINARY <= "100111"; + when 40 => CLK_COR_MAX_LAT_0_BINARY <= "101000"; + when 41 => CLK_COR_MAX_LAT_0_BINARY <= "101001"; + when 42 => CLK_COR_MAX_LAT_0_BINARY <= "101010"; + when 43 => CLK_COR_MAX_LAT_0_BINARY <= "101011"; + when 44 => CLK_COR_MAX_LAT_0_BINARY <= "101100"; + when 45 => CLK_COR_MAX_LAT_0_BINARY <= "101101"; + when 46 => CLK_COR_MAX_LAT_0_BINARY <= "101110"; + when 47 => CLK_COR_MAX_LAT_0_BINARY <= "101111"; + when 48 => CLK_COR_MAX_LAT_0_BINARY <= "110000"; + when others => assert FALSE report "Error : CLK_COR_MAX_LAT_0 is not in range 3...48." severity error; + end case; + case CLK_CORRECT_USE_0 is + when FALSE => CLK_CORRECT_USE_0_BINARY <= '0'; + when TRUE => CLK_CORRECT_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_CORRECT_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_PRECEDENCE_0 is + when FALSE => CLK_COR_PRECEDENCE_0_BINARY <= '0'; + when TRUE => CLK_COR_PRECEDENCE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_PRECEDENCE_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_DET_LEN_0 is + when 1 => CLK_COR_DET_LEN_0_BINARY <= "00"; + when 2 => CLK_COR_DET_LEN_0_BINARY <= "01"; + when 3 => CLK_COR_DET_LEN_0_BINARY <= "10"; + when 4 => CLK_COR_DET_LEN_0_BINARY <= "11"; + when others => assert FALSE report "Error : CLK_COR_DET_LEN_0 is not in 1, 2, 3, 4." severity error; + end case; + case CLK_COR_ADJ_LEN_0 is + when 1 => CLK_COR_ADJ_LEN_0_BINARY <= "00"; + when 2 => CLK_COR_ADJ_LEN_0_BINARY <= "01"; + when 3 => CLK_COR_ADJ_LEN_0_BINARY <= "10"; + when 4 => CLK_COR_ADJ_LEN_0_BINARY <= "11"; + when others => assert FALSE report "Error : CLK_COR_ADJ_LEN_0 is not in 1, 2, 3, 4." severity error; + end case; + case CLK_COR_KEEP_IDLE_0 is + when FALSE => CLK_COR_KEEP_IDLE_0_BINARY <= '0'; + when TRUE => CLK_COR_KEEP_IDLE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_KEEP_IDLE_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_INSERT_IDLE_FLAG_0 is + when FALSE => CLK_COR_INSERT_IDLE_FLAG_0_BINARY <= '0'; + when TRUE => CLK_COR_INSERT_IDLE_FLAG_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_INSERT_IDLE_FLAG_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_REPEAT_WAIT_0 is + when 0 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00000"; + when 1 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00001"; + when 2 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00010"; + when 3 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00011"; + when 4 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00100"; + when 5 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00101"; + when 6 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00110"; + when 7 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00111"; + when 8 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01000"; + when 9 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01001"; + when 10 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01010"; + when 11 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01011"; + when 12 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01100"; + when 13 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01101"; + when 14 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01110"; + when 15 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01111"; + when 16 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10000"; + when 17 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10001"; + when 18 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10010"; + when 19 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10011"; + when 20 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10100"; + when 21 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10101"; + when 22 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10110"; + when 23 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10111"; + when 24 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11000"; + when 25 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11001"; + when 26 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11010"; + when 27 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11011"; + when 28 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11100"; + when 29 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11101"; + when 30 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11110"; + when 31 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11111"; + when others => assert FALSE report "Error : CLK_COR_REPEAT_WAIT_0 is not in range 0...31." severity error; + end case; + case CLK_COR_SEQ_2_USE_0 is + when FALSE => CLK_COR_SEQ_2_USE_0_BINARY <= '0'; + when TRUE => CLK_COR_SEQ_2_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_SEQ_2_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_MIN_LAT_1 is + when 3 => CLK_COR_MIN_LAT_1_BINARY <= "000011"; + when 4 => CLK_COR_MIN_LAT_1_BINARY <= "000100"; + when 5 => CLK_COR_MIN_LAT_1_BINARY <= "000101"; + when 6 => CLK_COR_MIN_LAT_1_BINARY <= "000110"; + when 7 => CLK_COR_MIN_LAT_1_BINARY <= "000111"; + when 8 => CLK_COR_MIN_LAT_1_BINARY <= "001000"; + when 9 => CLK_COR_MIN_LAT_1_BINARY <= "001001"; + when 10 => CLK_COR_MIN_LAT_1_BINARY <= "001010"; + when 11 => CLK_COR_MIN_LAT_1_BINARY <= "001011"; + when 12 => CLK_COR_MIN_LAT_1_BINARY <= "001100"; + when 13 => CLK_COR_MIN_LAT_1_BINARY <= "001101"; + when 14 => CLK_COR_MIN_LAT_1_BINARY <= "001110"; + when 15 => CLK_COR_MIN_LAT_1_BINARY <= "001111"; + when 16 => CLK_COR_MIN_LAT_1_BINARY <= "010000"; + when 17 => CLK_COR_MIN_LAT_1_BINARY <= "010001"; + when 18 => CLK_COR_MIN_LAT_1_BINARY <= "010010"; + when 19 => CLK_COR_MIN_LAT_1_BINARY <= "010011"; + when 20 => CLK_COR_MIN_LAT_1_BINARY <= "010100"; + when 21 => CLK_COR_MIN_LAT_1_BINARY <= "010101"; + when 22 => CLK_COR_MIN_LAT_1_BINARY <= "010110"; + when 23 => CLK_COR_MIN_LAT_1_BINARY <= "010111"; + when 24 => CLK_COR_MIN_LAT_1_BINARY <= "011000"; + when 25 => CLK_COR_MIN_LAT_1_BINARY <= "011001"; + when 26 => CLK_COR_MIN_LAT_1_BINARY <= "011010"; + when 27 => CLK_COR_MIN_LAT_1_BINARY <= "011011"; + when 28 => CLK_COR_MIN_LAT_1_BINARY <= "011100"; + when 29 => CLK_COR_MIN_LAT_1_BINARY <= "011101"; + when 30 => CLK_COR_MIN_LAT_1_BINARY <= "011110"; + when 31 => CLK_COR_MIN_LAT_1_BINARY <= "011111"; + when 32 => CLK_COR_MIN_LAT_1_BINARY <= "100000"; + when 33 => CLK_COR_MIN_LAT_1_BINARY <= "100001"; + when 34 => CLK_COR_MIN_LAT_1_BINARY <= "100010"; + when 35 => CLK_COR_MIN_LAT_1_BINARY <= "100011"; + when 36 => CLK_COR_MIN_LAT_1_BINARY <= "100100"; + when 37 => CLK_COR_MIN_LAT_1_BINARY <= "100101"; + when 38 => CLK_COR_MIN_LAT_1_BINARY <= "100110"; + when 39 => CLK_COR_MIN_LAT_1_BINARY <= "100111"; + when 40 => CLK_COR_MIN_LAT_1_BINARY <= "101000"; + when 41 => CLK_COR_MIN_LAT_1_BINARY <= "101001"; + when 42 => CLK_COR_MIN_LAT_1_BINARY <= "101010"; + when 43 => CLK_COR_MIN_LAT_1_BINARY <= "101011"; + when 44 => CLK_COR_MIN_LAT_1_BINARY <= "101100"; + when 45 => CLK_COR_MIN_LAT_1_BINARY <= "101101"; + when 46 => CLK_COR_MIN_LAT_1_BINARY <= "101110"; + when 47 => CLK_COR_MIN_LAT_1_BINARY <= "101111"; + when 48 => CLK_COR_MIN_LAT_1_BINARY <= "110000"; + when others => assert FALSE report "Error : CLK_COR_MIN_LAT_1 is not in range 3...48." severity error; + end case; + case CLK_COR_MAX_LAT_1 is + when 3 => CLK_COR_MAX_LAT_1_BINARY <= "000011"; + when 4 => CLK_COR_MAX_LAT_1_BINARY <= "000100"; + when 5 => CLK_COR_MAX_LAT_1_BINARY <= "000101"; + when 6 => CLK_COR_MAX_LAT_1_BINARY <= "000110"; + when 7 => CLK_COR_MAX_LAT_1_BINARY <= "000111"; + when 8 => CLK_COR_MAX_LAT_1_BINARY <= "001000"; + when 9 => CLK_COR_MAX_LAT_1_BINARY <= "001001"; + when 10 => CLK_COR_MAX_LAT_1_BINARY <= "001010"; + when 11 => CLK_COR_MAX_LAT_1_BINARY <= "001011"; + when 12 => CLK_COR_MAX_LAT_1_BINARY <= "001100"; + when 13 => CLK_COR_MAX_LAT_1_BINARY <= "001101"; + when 14 => CLK_COR_MAX_LAT_1_BINARY <= "001110"; + when 15 => CLK_COR_MAX_LAT_1_BINARY <= "001111"; + when 16 => CLK_COR_MAX_LAT_1_BINARY <= "010000"; + when 17 => CLK_COR_MAX_LAT_1_BINARY <= "010001"; + when 18 => CLK_COR_MAX_LAT_1_BINARY <= "010010"; + when 19 => CLK_COR_MAX_LAT_1_BINARY <= "010011"; + when 20 => CLK_COR_MAX_LAT_1_BINARY <= "010100"; + when 21 => CLK_COR_MAX_LAT_1_BINARY <= "010101"; + when 22 => CLK_COR_MAX_LAT_1_BINARY <= "010110"; + when 23 => CLK_COR_MAX_LAT_1_BINARY <= "010111"; + when 24 => CLK_COR_MAX_LAT_1_BINARY <= "011000"; + when 25 => CLK_COR_MAX_LAT_1_BINARY <= "011001"; + when 26 => CLK_COR_MAX_LAT_1_BINARY <= "011010"; + when 27 => CLK_COR_MAX_LAT_1_BINARY <= "011011"; + when 28 => CLK_COR_MAX_LAT_1_BINARY <= "011100"; + when 29 => CLK_COR_MAX_LAT_1_BINARY <= "011101"; + when 30 => CLK_COR_MAX_LAT_1_BINARY <= "011110"; + when 31 => CLK_COR_MAX_LAT_1_BINARY <= "011111"; + when 32 => CLK_COR_MAX_LAT_1_BINARY <= "100000"; + when 33 => CLK_COR_MAX_LAT_1_BINARY <= "100001"; + when 34 => CLK_COR_MAX_LAT_1_BINARY <= "100010"; + when 35 => CLK_COR_MAX_LAT_1_BINARY <= "100011"; + when 36 => CLK_COR_MAX_LAT_1_BINARY <= "100100"; + when 37 => CLK_COR_MAX_LAT_1_BINARY <= "100101"; + when 38 => CLK_COR_MAX_LAT_1_BINARY <= "100110"; + when 39 => CLK_COR_MAX_LAT_1_BINARY <= "100111"; + when 40 => CLK_COR_MAX_LAT_1_BINARY <= "101000"; + when 41 => CLK_COR_MAX_LAT_1_BINARY <= "101001"; + when 42 => CLK_COR_MAX_LAT_1_BINARY <= "101010"; + when 43 => CLK_COR_MAX_LAT_1_BINARY <= "101011"; + when 44 => CLK_COR_MAX_LAT_1_BINARY <= "101100"; + when 45 => CLK_COR_MAX_LAT_1_BINARY <= "101101"; + when 46 => CLK_COR_MAX_LAT_1_BINARY <= "101110"; + when 47 => CLK_COR_MAX_LAT_1_BINARY <= "101111"; + when 48 => CLK_COR_MAX_LAT_1_BINARY <= "110000"; + when others => assert FALSE report "Error : CLK_COR_MAX_LAT_1 is not in range 3...48." severity error; + end case; + case CLK_CORRECT_USE_1 is + when FALSE => CLK_CORRECT_USE_1_BINARY <= '0'; + when TRUE => CLK_CORRECT_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_CORRECT_USE_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_PRECEDENCE_1 is + when FALSE => CLK_COR_PRECEDENCE_1_BINARY <= '0'; + when TRUE => CLK_COR_PRECEDENCE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_PRECEDENCE_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_DET_LEN_1 is + when 1 => CLK_COR_DET_LEN_1_BINARY <= "00"; + when 2 => CLK_COR_DET_LEN_1_BINARY <= "01"; + when 3 => CLK_COR_DET_LEN_1_BINARY <= "10"; + when 4 => CLK_COR_DET_LEN_1_BINARY <= "11"; + when others => assert FALSE report "Error : CLK_COR_DET_LEN_1 is not in 1, 2, 3, 4." severity error; + end case; + case CLK_COR_ADJ_LEN_1 is + when 1 => CLK_COR_ADJ_LEN_1_BINARY <= "00"; + when 2 => CLK_COR_ADJ_LEN_1_BINARY <= "01"; + when 3 => CLK_COR_ADJ_LEN_1_BINARY <= "10"; + when 4 => CLK_COR_ADJ_LEN_1_BINARY <= "11"; + when others => assert FALSE report "Error : CLK_COR_ADJ_LEN_1 is not in 1, 2, 3, 4." severity error; + end case; + case CLK_COR_KEEP_IDLE_1 is + when FALSE => CLK_COR_KEEP_IDLE_1_BINARY <= '0'; + when TRUE => CLK_COR_KEEP_IDLE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_KEEP_IDLE_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_INSERT_IDLE_FLAG_1 is + when FALSE => CLK_COR_INSERT_IDLE_FLAG_1_BINARY <= '0'; + when TRUE => CLK_COR_INSERT_IDLE_FLAG_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_INSERT_IDLE_FLAG_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_REPEAT_WAIT_1 is + when 0 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00000"; + when 1 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00001"; + when 2 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00010"; + when 3 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00011"; + when 4 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00100"; + when 5 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00101"; + when 6 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00110"; + when 7 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00111"; + when 8 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01000"; + when 9 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01001"; + when 10 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01010"; + when 11 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01011"; + when 12 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01100"; + when 13 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01101"; + when 14 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01110"; + when 15 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01111"; + when 16 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10000"; + when 17 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10001"; + when 18 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10010"; + when 19 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10011"; + when 20 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10100"; + when 21 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10101"; + when 22 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10110"; + when 23 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10111"; + when 24 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11000"; + when 25 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11001"; + when 26 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11010"; + when 27 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11011"; + when 28 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11100"; + when 29 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11101"; + when 30 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11110"; + when 31 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11111"; + when others => assert FALSE report "Error : CLK_COR_REPEAT_WAIT_1 is not in range 0...31." severity error; + end case; + case CLK_COR_SEQ_2_USE_1 is + when FALSE => CLK_COR_SEQ_2_USE_1_BINARY <= '0'; + when TRUE => CLK_COR_SEQ_2_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_SEQ_2_USE_1 is neither TRUE nor FALSE." severity error; + end case; +-- case CHAN_BOND_MODE_0 is + if((CHAN_BOND_MODE_0 = "OFF") or (CHAN_BOND_MODE_0 = "off")) then + CHAN_BOND_MODE_0_BINARY <= "00"; + elsif((CHAN_BOND_MODE_0 = "MASTER") or (CHAN_BOND_MODE_0 = "master")) then + CHAN_BOND_MODE_0_BINARY <= "01"; + elsif((CHAN_BOND_MODE_0 = "SLAVE") or (CHAN_BOND_MODE_0 = "slave")) then + CHAN_BOND_MODE_0_BINARY <= "10"; + else + assert FALSE report "Error : CHAN_BOND_MODE_0 = is not OFF, MASTER, SLAVE." severity error; + end if; +-- end case; + case CHAN_BOND_LEVEL_0 is + when 0 => CHAN_BOND_LEVEL_0_BINARY <= "000"; + when 1 => CHAN_BOND_LEVEL_0_BINARY <= "001"; + when 2 => CHAN_BOND_LEVEL_0_BINARY <= "010"; + when 3 => CHAN_BOND_LEVEL_0_BINARY <= "011"; + when 4 => CHAN_BOND_LEVEL_0_BINARY <= "100"; + when 5 => CHAN_BOND_LEVEL_0_BINARY <= "101"; + when 6 => CHAN_BOND_LEVEL_0_BINARY <= "110"; + when 7 => CHAN_BOND_LEVEL_0_BINARY <= "111"; + when others => assert FALSE report "Error : CHAN_BOND_LEVEL_0 is not in range 0...7." severity error; + end case; + case CHAN_BOND_SEQ_LEN_0 is + when 1 => CHAN_BOND_SEQ_LEN_0_BINARY <= "00"; + when 2 => CHAN_BOND_SEQ_LEN_0_BINARY <= "01"; + when 3 => CHAN_BOND_SEQ_LEN_0_BINARY <= "10"; + when 4 => CHAN_BOND_SEQ_LEN_0_BINARY <= "11"; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_LEN_0 is not in 1, 2, 3, 4." severity error; + end case; + case CHAN_BOND_SEQ_2_USE_0 is + when FALSE => CHAN_BOND_SEQ_2_USE_0_BINARY <= '0'; + when TRUE => CHAN_BOND_SEQ_2_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_2_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case CHAN_BOND_1_MAX_SKEW_0 is + when 1 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0001"; + when 2 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0010"; + when 3 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0011"; + when 4 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0100"; + when 5 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0101"; + when 6 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0110"; + when 7 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0111"; + when 8 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1000"; + when 9 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1001"; + when 10 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1010"; + when 11 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1011"; + when 12 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1100"; + when 13 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1101"; + when 14 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1110"; + when others => assert FALSE report "Error : CHAN_BOND_1_MAX_SKEW_0 is not in range 1...14." severity error; + end case; + case CHAN_BOND_2_MAX_SKEW_0 is + when 1 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0001"; + when 2 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0010"; + when 3 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0011"; + when 4 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0100"; + when 5 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0101"; + when 6 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0110"; + when 7 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0111"; + when 8 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1000"; + when 9 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1001"; + when 10 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1010"; + when 11 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1011"; + when 12 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1100"; + when 13 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1101"; + when 14 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1110"; + when others => assert FALSE report "Error : CHAN_BOND_2_MAX_SKEW_0 is not in range 1...14." severity error; + end case; + case CHAN_BOND_KEEP_ALIGN_0 is + when FALSE => CHAN_BOND_KEEP_ALIGN_0_BINARY <= '0'; + when TRUE => CHAN_BOND_KEEP_ALIGN_0_BINARY <= '1'; + when others => assert FALSE report "Error : CHAN_BOND_KEEP_ALIGN_0 is neither TRUE nor FALSE." severity error; + end case; + case CB2_INH_CC_PERIOD_0 is + when 0 => CB2_INH_CC_PERIOD_0_BINARY <= "0000"; + when 1 => CB2_INH_CC_PERIOD_0_BINARY <= "0001"; + when 2 => CB2_INH_CC_PERIOD_0_BINARY <= "0010"; + when 3 => CB2_INH_CC_PERIOD_0_BINARY <= "0011"; + when 4 => CB2_INH_CC_PERIOD_0_BINARY <= "0100"; + when 5 => CB2_INH_CC_PERIOD_0_BINARY <= "0101"; + when 6 => CB2_INH_CC_PERIOD_0_BINARY <= "0110"; + when 7 => CB2_INH_CC_PERIOD_0_BINARY <= "0111"; + when 8 => CB2_INH_CC_PERIOD_0_BINARY <= "1000"; + when 9 => CB2_INH_CC_PERIOD_0_BINARY <= "1001"; + when 10 => CB2_INH_CC_PERIOD_0_BINARY <= "1010"; + when 11 => CB2_INH_CC_PERIOD_0_BINARY <= "1011"; + when 12 => CB2_INH_CC_PERIOD_0_BINARY <= "1100"; + when 13 => CB2_INH_CC_PERIOD_0_BINARY <= "1101"; + when 14 => CB2_INH_CC_PERIOD_0_BINARY <= "1110"; + when 15 => CB2_INH_CC_PERIOD_0_BINARY <= "1111"; + when others => assert FALSE report "Error : CB2_INH_CC_PERIOD_0 is not in range 0...15." severity error; + end case; +-- case CHAN_BOND_MODE_1 is + if((CHAN_BOND_MODE_1 = "OFF") or (CHAN_BOND_MODE_1 = "off")) then + CHAN_BOND_MODE_1_BINARY <= "00"; + elsif((CHAN_BOND_MODE_1 = "MASTER") or (CHAN_BOND_MODE_1 = "master")) then + CHAN_BOND_MODE_1_BINARY <= "01"; + elsif((CHAN_BOND_MODE_1 = "SLAVE") or (CHAN_BOND_MODE_1 = "slave")) then + CHAN_BOND_MODE_1_BINARY <= "10"; + else + assert FALSE report "Error : CHAN_BOND_MODE_1 = is not OFF, MASTER, SLAVE." severity error; + end if; +-- end case; + case CHAN_BOND_LEVEL_1 is + when 0 => CHAN_BOND_LEVEL_1_BINARY <= "000"; + when 1 => CHAN_BOND_LEVEL_1_BINARY <= "001"; + when 2 => CHAN_BOND_LEVEL_1_BINARY <= "010"; + when 3 => CHAN_BOND_LEVEL_1_BINARY <= "011"; + when 4 => CHAN_BOND_LEVEL_1_BINARY <= "100"; + when 5 => CHAN_BOND_LEVEL_1_BINARY <= "101"; + when 6 => CHAN_BOND_LEVEL_1_BINARY <= "110"; + when 7 => CHAN_BOND_LEVEL_1_BINARY <= "111"; + when others => assert FALSE report "Error : CHAN_BOND_LEVEL_1 is not in range 0...7." severity error; + end case; + case CHAN_BOND_SEQ_LEN_1 is + when 1 => CHAN_BOND_SEQ_LEN_1_BINARY <= "00"; + when 2 => CHAN_BOND_SEQ_LEN_1_BINARY <= "01"; + when 3 => CHAN_BOND_SEQ_LEN_1_BINARY <= "10"; + when 4 => CHAN_BOND_SEQ_LEN_1_BINARY <= "11"; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_LEN_1 is not in 1, 2, 3, 4." severity error; + end case; + case CHAN_BOND_SEQ_2_USE_1 is + when FALSE => CHAN_BOND_SEQ_2_USE_1_BINARY <= '0'; + when TRUE => CHAN_BOND_SEQ_2_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_2_USE_1 is neither TRUE nor FALSE." severity error; + end case; + case CHAN_BOND_1_MAX_SKEW_1 is + when 1 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0001"; + when 2 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0010"; + when 3 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0011"; + when 4 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0100"; + when 5 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0101"; + when 6 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0110"; + when 7 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0111"; + when 8 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1000"; + when 9 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1001"; + when 10 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1010"; + when 11 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1011"; + when 12 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1100"; + when 13 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1101"; + when 14 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1110"; + when others => assert FALSE report "Error : CHAN_BOND_1_MAX_SKEW_1 is not in range 1...14." severity error; + end case; + case CHAN_BOND_2_MAX_SKEW_1 is + when 1 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0001"; + when 2 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0010"; + when 3 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0011"; + when 4 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0100"; + when 5 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0101"; + when 6 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0110"; + when 7 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0111"; + when 8 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1000"; + when 9 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1001"; + when 10 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1010"; + when 11 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1011"; + when 12 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1100"; + when 13 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1101"; + when 14 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1110"; + when others => assert FALSE report "Error : CHAN_BOND_2_MAX_SKEW_1 is not in range 1...14." severity error; + end case; + case CHAN_BOND_KEEP_ALIGN_1 is + when FALSE => CHAN_BOND_KEEP_ALIGN_1_BINARY <= '0'; + when TRUE => CHAN_BOND_KEEP_ALIGN_1_BINARY <= '1'; + when others => assert FALSE report "Error : CHAN_BOND_KEEP_ALIGN_1 is neither TRUE nor FALSE." severity error; + end case; + case CB2_INH_CC_PERIOD_1 is + when 0 => CB2_INH_CC_PERIOD_1_BINARY <= "0000"; + when 1 => CB2_INH_CC_PERIOD_1_BINARY <= "0001"; + when 2 => CB2_INH_CC_PERIOD_1_BINARY <= "0010"; + when 3 => CB2_INH_CC_PERIOD_1_BINARY <= "0011"; + when 4 => CB2_INH_CC_PERIOD_1_BINARY <= "0100"; + when 5 => CB2_INH_CC_PERIOD_1_BINARY <= "0101"; + when 6 => CB2_INH_CC_PERIOD_1_BINARY <= "0110"; + when 7 => CB2_INH_CC_PERIOD_1_BINARY <= "0111"; + when 8 => CB2_INH_CC_PERIOD_1_BINARY <= "1000"; + when 9 => CB2_INH_CC_PERIOD_1_BINARY <= "1001"; + when 10 => CB2_INH_CC_PERIOD_1_BINARY <= "1010"; + when 11 => CB2_INH_CC_PERIOD_1_BINARY <= "1011"; + when 12 => CB2_INH_CC_PERIOD_1_BINARY <= "1100"; + when 13 => CB2_INH_CC_PERIOD_1_BINARY <= "1101"; + when 14 => CB2_INH_CC_PERIOD_1_BINARY <= "1110"; + when 15 => CB2_INH_CC_PERIOD_1_BINARY <= "1111"; + when others => assert FALSE report "Error : CB2_INH_CC_PERIOD_1 is not in range 0...15." severity error; + end case; + case PCI_EXPRESS_MODE_0 is + when FALSE => PCI_EXPRESS_MODE_0_BINARY <= '0'; + when TRUE => PCI_EXPRESS_MODE_0_BINARY <= '1'; + when others => assert FALSE report "Error : PCI_EXPRESS_MODE_0 is neither TRUE nor FALSE." severity error; + end case; + case PCI_EXPRESS_MODE_1 is + when FALSE => PCI_EXPRESS_MODE_1_BINARY <= '0'; + when TRUE => PCI_EXPRESS_MODE_1_BINARY <= '1'; + when others => assert FALSE report "Error : PCI_EXPRESS_MODE_1 is neither TRUE nor FALSE." severity error; + end case; +-- case RX_STATUS_FMT_0 is + if((RX_STATUS_FMT_0 = "PCIE") or (RX_STATUS_FMT_0 = "pcie")) then + RX_STATUS_FMT_0_BINARY <= '0'; + elsif((RX_STATUS_FMT_0 = "SATA") or (RX_STATUS_FMT_0 = "sata")) then + RX_STATUS_FMT_0_BINARY <= '1'; + else + assert FALSE report "Error : RX_STATUS_FMT_0 = is not PCIE, SATA." severity error; + end if; +-- end case; + case TX_BUFFER_USE_0 is + when FALSE => TX_BUFFER_USE_0_BINARY <= '0'; + when TRUE => TX_BUFFER_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : TX_BUFFER_USE_0 is neither TRUE nor FALSE." severity error; + end case; +-- case TX_XCLK_SEL_0 is + if((TX_XCLK_SEL_0 = "TXUSR") or (TX_XCLK_SEL_0 = "txusr")) then + TX_XCLK_SEL_0_BINARY <= '1'; + elsif((TX_XCLK_SEL_0 = "TXOUT") or (TX_XCLK_SEL_0 = "txout")) then + TX_XCLK_SEL_0_BINARY <= '0'; + else + assert FALSE report "Error : TX_XCLK_SEL_0 = is not TXUSR, TXOUT." severity error; + end if; +-- end case; +-- case RX_XCLK_SEL_0 is + if((RX_XCLK_SEL_0 = "RXREC") or (RX_XCLK_SEL_0 = "rxrec")) then + RX_XCLK_SEL_0_BINARY <= '0'; + elsif((RX_XCLK_SEL_0 = "RXUSR") or (RX_XCLK_SEL_0 = "rxusr")) then + RX_XCLK_SEL_0_BINARY <= '1'; + else + assert FALSE report "Error : RX_XCLK_SEL_0 = is not RXREC, RXUSR." severity error; + end if; +-- end case; +-- case RX_STATUS_FMT_1 is + if((RX_STATUS_FMT_1 = "PCIE") or (RX_STATUS_FMT_1 = "pcie")) then + RX_STATUS_FMT_1_BINARY <= '0'; + elsif((RX_STATUS_FMT_1 = "SATA") or (RX_STATUS_FMT_1 = "sata")) then + RX_STATUS_FMT_1_BINARY <= '1'; + else + assert FALSE report "Error : RX_STATUS_FMT_1 = is not PCIE, SATA." severity error; + end if; +-- end case; + case TX_BUFFER_USE_1 is + when FALSE => TX_BUFFER_USE_1_BINARY <= '0'; + when TRUE => TX_BUFFER_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : TX_BUFFER_USE_1 is neither TRUE nor FALSE." severity error; + end case; +-- case TX_XCLK_SEL_1 is + if((TX_XCLK_SEL_1 = "TXUSR") or (TX_XCLK_SEL_1 = "txusr")) then + TX_XCLK_SEL_1_BINARY <= '1'; + elsif((TX_XCLK_SEL_1 = "TXOUT") or (TX_XCLK_SEL_1 = "txout")) then + TX_XCLK_SEL_1_BINARY <= '0'; + else + assert FALSE report "Error : TX_XCLK_SEL_1 = is not TXUSR, TXOUT." severity error; + end if; +-- end case; +-- case RX_XCLK_SEL_1 is + if((RX_XCLK_SEL_1 = "RXREC") or (RX_XCLK_SEL_1 = "rxrec")) then + RX_XCLK_SEL_1_BINARY <= '0'; + elsif((RX_XCLK_SEL_1 = "RXUSR") or (RX_XCLK_SEL_1 = "rxusr")) then + RX_XCLK_SEL_1_BINARY <= '1'; + else + assert FALSE report "Error : RX_XCLK_SEL_1 = is not RXREC, RXUSR." severity error; + end if; +-- end case; +-- case RX_SLIDE_MODE_0 is + if((RX_SLIDE_MODE_0 = "PCS") or (RX_SLIDE_MODE_0 = "pcs")) then + RX_SLIDE_MODE_0_BINARY <= '0'; + elsif((RX_SLIDE_MODE_0 = "PMA") or (RX_SLIDE_MODE_0 = "pma")) then + RX_SLIDE_MODE_0_BINARY <= '1'; + else + assert FALSE report "Error : RX_SLIDE_MODE_0 = is not PCS, PMA." severity error; + end if; +-- end case; +-- case RX_SLIDE_MODE_1 is + if((RX_SLIDE_MODE_1 = "PCS") or (RX_SLIDE_MODE_1 = "pcs")) then + RX_SLIDE_MODE_1_BINARY <= '0'; + elsif((RX_SLIDE_MODE_1 = "PMA") or (RX_SLIDE_MODE_1 = "pma")) then + RX_SLIDE_MODE_1_BINARY <= '1'; + else + assert FALSE report "Error : RX_SLIDE_MODE_1 = is not PCS, PMA." severity error; + end if; +-- end case; + case SATA_MIN_BURST_0 is + when 1 => SATA_MIN_BURST_0_BINARY <= "000001"; + when 2 => SATA_MIN_BURST_0_BINARY <= "000010"; + when 3 => SATA_MIN_BURST_0_BINARY <= "000011"; + when 4 => SATA_MIN_BURST_0_BINARY <= "000100"; + when 5 => SATA_MIN_BURST_0_BINARY <= "000101"; + when 6 => SATA_MIN_BURST_0_BINARY <= "000110"; + when 7 => SATA_MIN_BURST_0_BINARY <= "000111"; + when 8 => SATA_MIN_BURST_0_BINARY <= "001000"; + when 9 => SATA_MIN_BURST_0_BINARY <= "001001"; + when 10 => SATA_MIN_BURST_0_BINARY <= "001010"; + when 11 => SATA_MIN_BURST_0_BINARY <= "001011"; + when 12 => SATA_MIN_BURST_0_BINARY <= "001100"; + when 13 => SATA_MIN_BURST_0_BINARY <= "001101"; + when 14 => SATA_MIN_BURST_0_BINARY <= "001110"; + when 15 => SATA_MIN_BURST_0_BINARY <= "001111"; + when 16 => SATA_MIN_BURST_0_BINARY <= "010000"; + when 17 => SATA_MIN_BURST_0_BINARY <= "010001"; + when 18 => SATA_MIN_BURST_0_BINARY <= "010010"; + when 19 => SATA_MIN_BURST_0_BINARY <= "010011"; + when 20 => SATA_MIN_BURST_0_BINARY <= "010100"; + when 21 => SATA_MIN_BURST_0_BINARY <= "010101"; + when 22 => SATA_MIN_BURST_0_BINARY <= "010110"; + when 23 => SATA_MIN_BURST_0_BINARY <= "010111"; + when 24 => SATA_MIN_BURST_0_BINARY <= "011000"; + when 25 => SATA_MIN_BURST_0_BINARY <= "011001"; + when 26 => SATA_MIN_BURST_0_BINARY <= "011010"; + when 27 => SATA_MIN_BURST_0_BINARY <= "011011"; + when 28 => SATA_MIN_BURST_0_BINARY <= "011100"; + when 29 => SATA_MIN_BURST_0_BINARY <= "011101"; + when 30 => SATA_MIN_BURST_0_BINARY <= "011110"; + when 31 => SATA_MIN_BURST_0_BINARY <= "011111"; + when 32 => SATA_MIN_BURST_0_BINARY <= "100000"; + when 33 => SATA_MIN_BURST_0_BINARY <= "100001"; + when 34 => SATA_MIN_BURST_0_BINARY <= "100010"; + when 35 => SATA_MIN_BURST_0_BINARY <= "100011"; + when 36 => SATA_MIN_BURST_0_BINARY <= "100100"; + when 37 => SATA_MIN_BURST_0_BINARY <= "100101"; + when 38 => SATA_MIN_BURST_0_BINARY <= "100110"; + when 39 => SATA_MIN_BURST_0_BINARY <= "100111"; + when 40 => SATA_MIN_BURST_0_BINARY <= "101000"; + when 41 => SATA_MIN_BURST_0_BINARY <= "101001"; + when 42 => SATA_MIN_BURST_0_BINARY <= "101010"; + when 43 => SATA_MIN_BURST_0_BINARY <= "101011"; + when 44 => SATA_MIN_BURST_0_BINARY <= "101100"; + when 45 => SATA_MIN_BURST_0_BINARY <= "101101"; + when 46 => SATA_MIN_BURST_0_BINARY <= "101110"; + when 47 => SATA_MIN_BURST_0_BINARY <= "101111"; + when 48 => SATA_MIN_BURST_0_BINARY <= "110000"; + when 49 => SATA_MIN_BURST_0_BINARY <= "110001"; + when 50 => SATA_MIN_BURST_0_BINARY <= "110010"; + when 51 => SATA_MIN_BURST_0_BINARY <= "110011"; + when 52 => SATA_MIN_BURST_0_BINARY <= "110100"; + when 53 => SATA_MIN_BURST_0_BINARY <= "110101"; + when 54 => SATA_MIN_BURST_0_BINARY <= "110110"; + when 55 => SATA_MIN_BURST_0_BINARY <= "110111"; + when 56 => SATA_MIN_BURST_0_BINARY <= "111000"; + when 57 => SATA_MIN_BURST_0_BINARY <= "111001"; + when 58 => SATA_MIN_BURST_0_BINARY <= "111010"; + when 59 => SATA_MIN_BURST_0_BINARY <= "111011"; + when 60 => SATA_MIN_BURST_0_BINARY <= "111100"; + when 61 => SATA_MIN_BURST_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_BURST_0 is not in range 1...61." severity error; + end case; + case SATA_MAX_BURST_0 is + when 1 => SATA_MAX_BURST_0_BINARY <= "000001"; + when 2 => SATA_MAX_BURST_0_BINARY <= "000010"; + when 3 => SATA_MAX_BURST_0_BINARY <= "000011"; + when 4 => SATA_MAX_BURST_0_BINARY <= "000100"; + when 5 => SATA_MAX_BURST_0_BINARY <= "000101"; + when 6 => SATA_MAX_BURST_0_BINARY <= "000110"; + when 7 => SATA_MAX_BURST_0_BINARY <= "000111"; + when 8 => SATA_MAX_BURST_0_BINARY <= "001000"; + when 9 => SATA_MAX_BURST_0_BINARY <= "001001"; + when 10 => SATA_MAX_BURST_0_BINARY <= "001010"; + when 11 => SATA_MAX_BURST_0_BINARY <= "001011"; + when 12 => SATA_MAX_BURST_0_BINARY <= "001100"; + when 13 => SATA_MAX_BURST_0_BINARY <= "001101"; + when 14 => SATA_MAX_BURST_0_BINARY <= "001110"; + when 15 => SATA_MAX_BURST_0_BINARY <= "001111"; + when 16 => SATA_MAX_BURST_0_BINARY <= "010000"; + when 17 => SATA_MAX_BURST_0_BINARY <= "010001"; + when 18 => SATA_MAX_BURST_0_BINARY <= "010010"; + when 19 => SATA_MAX_BURST_0_BINARY <= "010011"; + when 20 => SATA_MAX_BURST_0_BINARY <= "010100"; + when 21 => SATA_MAX_BURST_0_BINARY <= "010101"; + when 22 => SATA_MAX_BURST_0_BINARY <= "010110"; + when 23 => SATA_MAX_BURST_0_BINARY <= "010111"; + when 24 => SATA_MAX_BURST_0_BINARY <= "011000"; + when 25 => SATA_MAX_BURST_0_BINARY <= "011001"; + when 26 => SATA_MAX_BURST_0_BINARY <= "011010"; + when 27 => SATA_MAX_BURST_0_BINARY <= "011011"; + when 28 => SATA_MAX_BURST_0_BINARY <= "011100"; + when 29 => SATA_MAX_BURST_0_BINARY <= "011101"; + when 30 => SATA_MAX_BURST_0_BINARY <= "011110"; + when 31 => SATA_MAX_BURST_0_BINARY <= "011111"; + when 32 => SATA_MAX_BURST_0_BINARY <= "100000"; + when 33 => SATA_MAX_BURST_0_BINARY <= "100001"; + when 34 => SATA_MAX_BURST_0_BINARY <= "100010"; + when 35 => SATA_MAX_BURST_0_BINARY <= "100011"; + when 36 => SATA_MAX_BURST_0_BINARY <= "100100"; + when 37 => SATA_MAX_BURST_0_BINARY <= "100101"; + when 38 => SATA_MAX_BURST_0_BINARY <= "100110"; + when 39 => SATA_MAX_BURST_0_BINARY <= "100111"; + when 40 => SATA_MAX_BURST_0_BINARY <= "101000"; + when 41 => SATA_MAX_BURST_0_BINARY <= "101001"; + when 42 => SATA_MAX_BURST_0_BINARY <= "101010"; + when 43 => SATA_MAX_BURST_0_BINARY <= "101011"; + when 44 => SATA_MAX_BURST_0_BINARY <= "101100"; + when 45 => SATA_MAX_BURST_0_BINARY <= "101101"; + when 46 => SATA_MAX_BURST_0_BINARY <= "101110"; + when 47 => SATA_MAX_BURST_0_BINARY <= "101111"; + when 48 => SATA_MAX_BURST_0_BINARY <= "110000"; + when 49 => SATA_MAX_BURST_0_BINARY <= "110001"; + when 50 => SATA_MAX_BURST_0_BINARY <= "110010"; + when 51 => SATA_MAX_BURST_0_BINARY <= "110011"; + when 52 => SATA_MAX_BURST_0_BINARY <= "110100"; + when 53 => SATA_MAX_BURST_0_BINARY <= "110101"; + when 54 => SATA_MAX_BURST_0_BINARY <= "110110"; + when 55 => SATA_MAX_BURST_0_BINARY <= "110111"; + when 56 => SATA_MAX_BURST_0_BINARY <= "111000"; + when 57 => SATA_MAX_BURST_0_BINARY <= "111001"; + when 58 => SATA_MAX_BURST_0_BINARY <= "111010"; + when 59 => SATA_MAX_BURST_0_BINARY <= "111011"; + when 60 => SATA_MAX_BURST_0_BINARY <= "111100"; + when 61 => SATA_MAX_BURST_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_BURST_0 is not in range 1...61." severity error; + end case; + case SATA_MIN_INIT_0 is + when 1 => SATA_MIN_INIT_0_BINARY <= "000001"; + when 2 => SATA_MIN_INIT_0_BINARY <= "000010"; + when 3 => SATA_MIN_INIT_0_BINARY <= "000011"; + when 4 => SATA_MIN_INIT_0_BINARY <= "000100"; + when 5 => SATA_MIN_INIT_0_BINARY <= "000101"; + when 6 => SATA_MIN_INIT_0_BINARY <= "000110"; + when 7 => SATA_MIN_INIT_0_BINARY <= "000111"; + when 8 => SATA_MIN_INIT_0_BINARY <= "001000"; + when 9 => SATA_MIN_INIT_0_BINARY <= "001001"; + when 10 => SATA_MIN_INIT_0_BINARY <= "001010"; + when 11 => SATA_MIN_INIT_0_BINARY <= "001011"; + when 12 => SATA_MIN_INIT_0_BINARY <= "001100"; + when 13 => SATA_MIN_INIT_0_BINARY <= "001101"; + when 14 => SATA_MIN_INIT_0_BINARY <= "001110"; + when 15 => SATA_MIN_INIT_0_BINARY <= "001111"; + when 16 => SATA_MIN_INIT_0_BINARY <= "010000"; + when 17 => SATA_MIN_INIT_0_BINARY <= "010001"; + when 18 => SATA_MIN_INIT_0_BINARY <= "010010"; + when 19 => SATA_MIN_INIT_0_BINARY <= "010011"; + when 20 => SATA_MIN_INIT_0_BINARY <= "010100"; + when 21 => SATA_MIN_INIT_0_BINARY <= "010101"; + when 22 => SATA_MIN_INIT_0_BINARY <= "010110"; + when 23 => SATA_MIN_INIT_0_BINARY <= "010111"; + when 24 => SATA_MIN_INIT_0_BINARY <= "011000"; + when 25 => SATA_MIN_INIT_0_BINARY <= "011001"; + when 26 => SATA_MIN_INIT_0_BINARY <= "011010"; + when 27 => SATA_MIN_INIT_0_BINARY <= "011011"; + when 28 => SATA_MIN_INIT_0_BINARY <= "011100"; + when 29 => SATA_MIN_INIT_0_BINARY <= "011101"; + when 30 => SATA_MIN_INIT_0_BINARY <= "011110"; + when 31 => SATA_MIN_INIT_0_BINARY <= "011111"; + when 32 => SATA_MIN_INIT_0_BINARY <= "100000"; + when 33 => SATA_MIN_INIT_0_BINARY <= "100001"; + when 34 => SATA_MIN_INIT_0_BINARY <= "100010"; + when 35 => SATA_MIN_INIT_0_BINARY <= "100011"; + when 36 => SATA_MIN_INIT_0_BINARY <= "100100"; + when 37 => SATA_MIN_INIT_0_BINARY <= "100101"; + when 38 => SATA_MIN_INIT_0_BINARY <= "100110"; + when 39 => SATA_MIN_INIT_0_BINARY <= "100111"; + when 40 => SATA_MIN_INIT_0_BINARY <= "101000"; + when 41 => SATA_MIN_INIT_0_BINARY <= "101001"; + when 42 => SATA_MIN_INIT_0_BINARY <= "101010"; + when 43 => SATA_MIN_INIT_0_BINARY <= "101011"; + when 44 => SATA_MIN_INIT_0_BINARY <= "101100"; + when 45 => SATA_MIN_INIT_0_BINARY <= "101101"; + when 46 => SATA_MIN_INIT_0_BINARY <= "101110"; + when 47 => SATA_MIN_INIT_0_BINARY <= "101111"; + when 48 => SATA_MIN_INIT_0_BINARY <= "110000"; + when 49 => SATA_MIN_INIT_0_BINARY <= "110001"; + when 50 => SATA_MIN_INIT_0_BINARY <= "110010"; + when 51 => SATA_MIN_INIT_0_BINARY <= "110011"; + when 52 => SATA_MIN_INIT_0_BINARY <= "110100"; + when 53 => SATA_MIN_INIT_0_BINARY <= "110101"; + when 54 => SATA_MIN_INIT_0_BINARY <= "110110"; + when 55 => SATA_MIN_INIT_0_BINARY <= "110111"; + when 56 => SATA_MIN_INIT_0_BINARY <= "111000"; + when 57 => SATA_MIN_INIT_0_BINARY <= "111001"; + when 58 => SATA_MIN_INIT_0_BINARY <= "111010"; + when 59 => SATA_MIN_INIT_0_BINARY <= "111011"; + when 60 => SATA_MIN_INIT_0_BINARY <= "111100"; + when 61 => SATA_MIN_INIT_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_INIT_0 is not in range 1...61." severity error; + end case; + case SATA_MAX_INIT_0 is + when 1 => SATA_MAX_INIT_0_BINARY <= "000001"; + when 2 => SATA_MAX_INIT_0_BINARY <= "000010"; + when 3 => SATA_MAX_INIT_0_BINARY <= "000011"; + when 4 => SATA_MAX_INIT_0_BINARY <= "000100"; + when 5 => SATA_MAX_INIT_0_BINARY <= "000101"; + when 6 => SATA_MAX_INIT_0_BINARY <= "000110"; + when 7 => SATA_MAX_INIT_0_BINARY <= "000111"; + when 8 => SATA_MAX_INIT_0_BINARY <= "001000"; + when 9 => SATA_MAX_INIT_0_BINARY <= "001001"; + when 10 => SATA_MAX_INIT_0_BINARY <= "001010"; + when 11 => SATA_MAX_INIT_0_BINARY <= "001011"; + when 12 => SATA_MAX_INIT_0_BINARY <= "001100"; + when 13 => SATA_MAX_INIT_0_BINARY <= "001101"; + when 14 => SATA_MAX_INIT_0_BINARY <= "001110"; + when 15 => SATA_MAX_INIT_0_BINARY <= "001111"; + when 16 => SATA_MAX_INIT_0_BINARY <= "010000"; + when 17 => SATA_MAX_INIT_0_BINARY <= "010001"; + when 18 => SATA_MAX_INIT_0_BINARY <= "010010"; + when 19 => SATA_MAX_INIT_0_BINARY <= "010011"; + when 20 => SATA_MAX_INIT_0_BINARY <= "010100"; + when 21 => SATA_MAX_INIT_0_BINARY <= "010101"; + when 22 => SATA_MAX_INIT_0_BINARY <= "010110"; + when 23 => SATA_MAX_INIT_0_BINARY <= "010111"; + when 24 => SATA_MAX_INIT_0_BINARY <= "011000"; + when 25 => SATA_MAX_INIT_0_BINARY <= "011001"; + when 26 => SATA_MAX_INIT_0_BINARY <= "011010"; + when 27 => SATA_MAX_INIT_0_BINARY <= "011011"; + when 28 => SATA_MAX_INIT_0_BINARY <= "011100"; + when 29 => SATA_MAX_INIT_0_BINARY <= "011101"; + when 30 => SATA_MAX_INIT_0_BINARY <= "011110"; + when 31 => SATA_MAX_INIT_0_BINARY <= "011111"; + when 32 => SATA_MAX_INIT_0_BINARY <= "100000"; + when 33 => SATA_MAX_INIT_0_BINARY <= "100001"; + when 34 => SATA_MAX_INIT_0_BINARY <= "100010"; + when 35 => SATA_MAX_INIT_0_BINARY <= "100011"; + when 36 => SATA_MAX_INIT_0_BINARY <= "100100"; + when 37 => SATA_MAX_INIT_0_BINARY <= "100101"; + when 38 => SATA_MAX_INIT_0_BINARY <= "100110"; + when 39 => SATA_MAX_INIT_0_BINARY <= "100111"; + when 40 => SATA_MAX_INIT_0_BINARY <= "101000"; + when 41 => SATA_MAX_INIT_0_BINARY <= "101001"; + when 42 => SATA_MAX_INIT_0_BINARY <= "101010"; + when 43 => SATA_MAX_INIT_0_BINARY <= "101011"; + when 44 => SATA_MAX_INIT_0_BINARY <= "101100"; + when 45 => SATA_MAX_INIT_0_BINARY <= "101101"; + when 46 => SATA_MAX_INIT_0_BINARY <= "101110"; + when 47 => SATA_MAX_INIT_0_BINARY <= "101111"; + when 48 => SATA_MAX_INIT_0_BINARY <= "110000"; + when 49 => SATA_MAX_INIT_0_BINARY <= "110001"; + when 50 => SATA_MAX_INIT_0_BINARY <= "110010"; + when 51 => SATA_MAX_INIT_0_BINARY <= "110011"; + when 52 => SATA_MAX_INIT_0_BINARY <= "110100"; + when 53 => SATA_MAX_INIT_0_BINARY <= "110101"; + when 54 => SATA_MAX_INIT_0_BINARY <= "110110"; + when 55 => SATA_MAX_INIT_0_BINARY <= "110111"; + when 56 => SATA_MAX_INIT_0_BINARY <= "111000"; + when 57 => SATA_MAX_INIT_0_BINARY <= "111001"; + when 58 => SATA_MAX_INIT_0_BINARY <= "111010"; + when 59 => SATA_MAX_INIT_0_BINARY <= "111011"; + when 60 => SATA_MAX_INIT_0_BINARY <= "111100"; + when 61 => SATA_MAX_INIT_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_INIT_0 is not in range 1...61." severity error; + end case; + case SATA_MIN_WAKE_0 is + when 1 => SATA_MIN_WAKE_0_BINARY <= "000001"; + when 2 => SATA_MIN_WAKE_0_BINARY <= "000010"; + when 3 => SATA_MIN_WAKE_0_BINARY <= "000011"; + when 4 => SATA_MIN_WAKE_0_BINARY <= "000100"; + when 5 => SATA_MIN_WAKE_0_BINARY <= "000101"; + when 6 => SATA_MIN_WAKE_0_BINARY <= "000110"; + when 7 => SATA_MIN_WAKE_0_BINARY <= "000111"; + when 8 => SATA_MIN_WAKE_0_BINARY <= "001000"; + when 9 => SATA_MIN_WAKE_0_BINARY <= "001001"; + when 10 => SATA_MIN_WAKE_0_BINARY <= "001010"; + when 11 => SATA_MIN_WAKE_0_BINARY <= "001011"; + when 12 => SATA_MIN_WAKE_0_BINARY <= "001100"; + when 13 => SATA_MIN_WAKE_0_BINARY <= "001101"; + when 14 => SATA_MIN_WAKE_0_BINARY <= "001110"; + when 15 => SATA_MIN_WAKE_0_BINARY <= "001111"; + when 16 => SATA_MIN_WAKE_0_BINARY <= "010000"; + when 17 => SATA_MIN_WAKE_0_BINARY <= "010001"; + when 18 => SATA_MIN_WAKE_0_BINARY <= "010010"; + when 19 => SATA_MIN_WAKE_0_BINARY <= "010011"; + when 20 => SATA_MIN_WAKE_0_BINARY <= "010100"; + when 21 => SATA_MIN_WAKE_0_BINARY <= "010101"; + when 22 => SATA_MIN_WAKE_0_BINARY <= "010110"; + when 23 => SATA_MIN_WAKE_0_BINARY <= "010111"; + when 24 => SATA_MIN_WAKE_0_BINARY <= "011000"; + when 25 => SATA_MIN_WAKE_0_BINARY <= "011001"; + when 26 => SATA_MIN_WAKE_0_BINARY <= "011010"; + when 27 => SATA_MIN_WAKE_0_BINARY <= "011011"; + when 28 => SATA_MIN_WAKE_0_BINARY <= "011100"; + when 29 => SATA_MIN_WAKE_0_BINARY <= "011101"; + when 30 => SATA_MIN_WAKE_0_BINARY <= "011110"; + when 31 => SATA_MIN_WAKE_0_BINARY <= "011111"; + when 32 => SATA_MIN_WAKE_0_BINARY <= "100000"; + when 33 => SATA_MIN_WAKE_0_BINARY <= "100001"; + when 34 => SATA_MIN_WAKE_0_BINARY <= "100010"; + when 35 => SATA_MIN_WAKE_0_BINARY <= "100011"; + when 36 => SATA_MIN_WAKE_0_BINARY <= "100100"; + when 37 => SATA_MIN_WAKE_0_BINARY <= "100101"; + when 38 => SATA_MIN_WAKE_0_BINARY <= "100110"; + when 39 => SATA_MIN_WAKE_0_BINARY <= "100111"; + when 40 => SATA_MIN_WAKE_0_BINARY <= "101000"; + when 41 => SATA_MIN_WAKE_0_BINARY <= "101001"; + when 42 => SATA_MIN_WAKE_0_BINARY <= "101010"; + when 43 => SATA_MIN_WAKE_0_BINARY <= "101011"; + when 44 => SATA_MIN_WAKE_0_BINARY <= "101100"; + when 45 => SATA_MIN_WAKE_0_BINARY <= "101101"; + when 46 => SATA_MIN_WAKE_0_BINARY <= "101110"; + when 47 => SATA_MIN_WAKE_0_BINARY <= "101111"; + when 48 => SATA_MIN_WAKE_0_BINARY <= "110000"; + when 49 => SATA_MIN_WAKE_0_BINARY <= "110001"; + when 50 => SATA_MIN_WAKE_0_BINARY <= "110010"; + when 51 => SATA_MIN_WAKE_0_BINARY <= "110011"; + when 52 => SATA_MIN_WAKE_0_BINARY <= "110100"; + when 53 => SATA_MIN_WAKE_0_BINARY <= "110101"; + when 54 => SATA_MIN_WAKE_0_BINARY <= "110110"; + when 55 => SATA_MIN_WAKE_0_BINARY <= "110111"; + when 56 => SATA_MIN_WAKE_0_BINARY <= "111000"; + when 57 => SATA_MIN_WAKE_0_BINARY <= "111001"; + when 58 => SATA_MIN_WAKE_0_BINARY <= "111010"; + when 59 => SATA_MIN_WAKE_0_BINARY <= "111011"; + when 60 => SATA_MIN_WAKE_0_BINARY <= "111100"; + when 61 => SATA_MIN_WAKE_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_WAKE_0 is not in range 1...61." severity error; + end case; + case SATA_MAX_WAKE_0 is + when 1 => SATA_MAX_WAKE_0_BINARY <= "000001"; + when 2 => SATA_MAX_WAKE_0_BINARY <= "000010"; + when 3 => SATA_MAX_WAKE_0_BINARY <= "000011"; + when 4 => SATA_MAX_WAKE_0_BINARY <= "000100"; + when 5 => SATA_MAX_WAKE_0_BINARY <= "000101"; + when 6 => SATA_MAX_WAKE_0_BINARY <= "000110"; + when 7 => SATA_MAX_WAKE_0_BINARY <= "000111"; + when 8 => SATA_MAX_WAKE_0_BINARY <= "001000"; + when 9 => SATA_MAX_WAKE_0_BINARY <= "001001"; + when 10 => SATA_MAX_WAKE_0_BINARY <= "001010"; + when 11 => SATA_MAX_WAKE_0_BINARY <= "001011"; + when 12 => SATA_MAX_WAKE_0_BINARY <= "001100"; + when 13 => SATA_MAX_WAKE_0_BINARY <= "001101"; + when 14 => SATA_MAX_WAKE_0_BINARY <= "001110"; + when 15 => SATA_MAX_WAKE_0_BINARY <= "001111"; + when 16 => SATA_MAX_WAKE_0_BINARY <= "010000"; + when 17 => SATA_MAX_WAKE_0_BINARY <= "010001"; + when 18 => SATA_MAX_WAKE_0_BINARY <= "010010"; + when 19 => SATA_MAX_WAKE_0_BINARY <= "010011"; + when 20 => SATA_MAX_WAKE_0_BINARY <= "010100"; + when 21 => SATA_MAX_WAKE_0_BINARY <= "010101"; + when 22 => SATA_MAX_WAKE_0_BINARY <= "010110"; + when 23 => SATA_MAX_WAKE_0_BINARY <= "010111"; + when 24 => SATA_MAX_WAKE_0_BINARY <= "011000"; + when 25 => SATA_MAX_WAKE_0_BINARY <= "011001"; + when 26 => SATA_MAX_WAKE_0_BINARY <= "011010"; + when 27 => SATA_MAX_WAKE_0_BINARY <= "011011"; + when 28 => SATA_MAX_WAKE_0_BINARY <= "011100"; + when 29 => SATA_MAX_WAKE_0_BINARY <= "011101"; + when 30 => SATA_MAX_WAKE_0_BINARY <= "011110"; + when 31 => SATA_MAX_WAKE_0_BINARY <= "011111"; + when 32 => SATA_MAX_WAKE_0_BINARY <= "100000"; + when 33 => SATA_MAX_WAKE_0_BINARY <= "100001"; + when 34 => SATA_MAX_WAKE_0_BINARY <= "100010"; + when 35 => SATA_MAX_WAKE_0_BINARY <= "100011"; + when 36 => SATA_MAX_WAKE_0_BINARY <= "100100"; + when 37 => SATA_MAX_WAKE_0_BINARY <= "100101"; + when 38 => SATA_MAX_WAKE_0_BINARY <= "100110"; + when 39 => SATA_MAX_WAKE_0_BINARY <= "100111"; + when 40 => SATA_MAX_WAKE_0_BINARY <= "101000"; + when 41 => SATA_MAX_WAKE_0_BINARY <= "101001"; + when 42 => SATA_MAX_WAKE_0_BINARY <= "101010"; + when 43 => SATA_MAX_WAKE_0_BINARY <= "101011"; + when 44 => SATA_MAX_WAKE_0_BINARY <= "101100"; + when 45 => SATA_MAX_WAKE_0_BINARY <= "101101"; + when 46 => SATA_MAX_WAKE_0_BINARY <= "101110"; + when 47 => SATA_MAX_WAKE_0_BINARY <= "101111"; + when 48 => SATA_MAX_WAKE_0_BINARY <= "110000"; + when 49 => SATA_MAX_WAKE_0_BINARY <= "110001"; + when 50 => SATA_MAX_WAKE_0_BINARY <= "110010"; + when 51 => SATA_MAX_WAKE_0_BINARY <= "110011"; + when 52 => SATA_MAX_WAKE_0_BINARY <= "110100"; + when 53 => SATA_MAX_WAKE_0_BINARY <= "110101"; + when 54 => SATA_MAX_WAKE_0_BINARY <= "110110"; + when 55 => SATA_MAX_WAKE_0_BINARY <= "110111"; + when 56 => SATA_MAX_WAKE_0_BINARY <= "111000"; + when 57 => SATA_MAX_WAKE_0_BINARY <= "111001"; + when 58 => SATA_MAX_WAKE_0_BINARY <= "111010"; + when 59 => SATA_MAX_WAKE_0_BINARY <= "111011"; + when 60 => SATA_MAX_WAKE_0_BINARY <= "111100"; + when 61 => SATA_MAX_WAKE_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_WAKE_0 is not in range 1...61." severity error; + end case; + case SATA_MIN_BURST_1 is + when 1 => SATA_MIN_BURST_1_BINARY <= "000001"; + when 2 => SATA_MIN_BURST_1_BINARY <= "000010"; + when 3 => SATA_MIN_BURST_1_BINARY <= "000011"; + when 4 => SATA_MIN_BURST_1_BINARY <= "000100"; + when 5 => SATA_MIN_BURST_1_BINARY <= "000101"; + when 6 => SATA_MIN_BURST_1_BINARY <= "000110"; + when 7 => SATA_MIN_BURST_1_BINARY <= "000111"; + when 8 => SATA_MIN_BURST_1_BINARY <= "001000"; + when 9 => SATA_MIN_BURST_1_BINARY <= "001001"; + when 10 => SATA_MIN_BURST_1_BINARY <= "001010"; + when 11 => SATA_MIN_BURST_1_BINARY <= "001011"; + when 12 => SATA_MIN_BURST_1_BINARY <= "001100"; + when 13 => SATA_MIN_BURST_1_BINARY <= "001101"; + when 14 => SATA_MIN_BURST_1_BINARY <= "001110"; + when 15 => SATA_MIN_BURST_1_BINARY <= "001111"; + when 16 => SATA_MIN_BURST_1_BINARY <= "010000"; + when 17 => SATA_MIN_BURST_1_BINARY <= "010001"; + when 18 => SATA_MIN_BURST_1_BINARY <= "010010"; + when 19 => SATA_MIN_BURST_1_BINARY <= "010011"; + when 20 => SATA_MIN_BURST_1_BINARY <= "010100"; + when 21 => SATA_MIN_BURST_1_BINARY <= "010101"; + when 22 => SATA_MIN_BURST_1_BINARY <= "010110"; + when 23 => SATA_MIN_BURST_1_BINARY <= "010111"; + when 24 => SATA_MIN_BURST_1_BINARY <= "011000"; + when 25 => SATA_MIN_BURST_1_BINARY <= "011001"; + when 26 => SATA_MIN_BURST_1_BINARY <= "011010"; + when 27 => SATA_MIN_BURST_1_BINARY <= "011011"; + when 28 => SATA_MIN_BURST_1_BINARY <= "011100"; + when 29 => SATA_MIN_BURST_1_BINARY <= "011101"; + when 30 => SATA_MIN_BURST_1_BINARY <= "011110"; + when 31 => SATA_MIN_BURST_1_BINARY <= "011111"; + when 32 => SATA_MIN_BURST_1_BINARY <= "100000"; + when 33 => SATA_MIN_BURST_1_BINARY <= "100001"; + when 34 => SATA_MIN_BURST_1_BINARY <= "100010"; + when 35 => SATA_MIN_BURST_1_BINARY <= "100011"; + when 36 => SATA_MIN_BURST_1_BINARY <= "100100"; + when 37 => SATA_MIN_BURST_1_BINARY <= "100101"; + when 38 => SATA_MIN_BURST_1_BINARY <= "100110"; + when 39 => SATA_MIN_BURST_1_BINARY <= "100111"; + when 40 => SATA_MIN_BURST_1_BINARY <= "101000"; + when 41 => SATA_MIN_BURST_1_BINARY <= "101001"; + when 42 => SATA_MIN_BURST_1_BINARY <= "101010"; + when 43 => SATA_MIN_BURST_1_BINARY <= "101011"; + when 44 => SATA_MIN_BURST_1_BINARY <= "101100"; + when 45 => SATA_MIN_BURST_1_BINARY <= "101101"; + when 46 => SATA_MIN_BURST_1_BINARY <= "101110"; + when 47 => SATA_MIN_BURST_1_BINARY <= "101111"; + when 48 => SATA_MIN_BURST_1_BINARY <= "110000"; + when 49 => SATA_MIN_BURST_1_BINARY <= "110001"; + when 50 => SATA_MIN_BURST_1_BINARY <= "110010"; + when 51 => SATA_MIN_BURST_1_BINARY <= "110011"; + when 52 => SATA_MIN_BURST_1_BINARY <= "110100"; + when 53 => SATA_MIN_BURST_1_BINARY <= "110101"; + when 54 => SATA_MIN_BURST_1_BINARY <= "110110"; + when 55 => SATA_MIN_BURST_1_BINARY <= "110111"; + when 56 => SATA_MIN_BURST_1_BINARY <= "111000"; + when 57 => SATA_MIN_BURST_1_BINARY <= "111001"; + when 58 => SATA_MIN_BURST_1_BINARY <= "111010"; + when 59 => SATA_MIN_BURST_1_BINARY <= "111011"; + when 60 => SATA_MIN_BURST_1_BINARY <= "111100"; + when 61 => SATA_MIN_BURST_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_BURST_1 is not in range 1...61." severity error; + end case; + case SATA_MAX_BURST_1 is + when 1 => SATA_MAX_BURST_1_BINARY <= "000001"; + when 2 => SATA_MAX_BURST_1_BINARY <= "000010"; + when 3 => SATA_MAX_BURST_1_BINARY <= "000011"; + when 4 => SATA_MAX_BURST_1_BINARY <= "000100"; + when 5 => SATA_MAX_BURST_1_BINARY <= "000101"; + when 6 => SATA_MAX_BURST_1_BINARY <= "000110"; + when 7 => SATA_MAX_BURST_1_BINARY <= "000111"; + when 8 => SATA_MAX_BURST_1_BINARY <= "001000"; + when 9 => SATA_MAX_BURST_1_BINARY <= "001001"; + when 10 => SATA_MAX_BURST_1_BINARY <= "001010"; + when 11 => SATA_MAX_BURST_1_BINARY <= "001011"; + when 12 => SATA_MAX_BURST_1_BINARY <= "001100"; + when 13 => SATA_MAX_BURST_1_BINARY <= "001101"; + when 14 => SATA_MAX_BURST_1_BINARY <= "001110"; + when 15 => SATA_MAX_BURST_1_BINARY <= "001111"; + when 16 => SATA_MAX_BURST_1_BINARY <= "010000"; + when 17 => SATA_MAX_BURST_1_BINARY <= "010001"; + when 18 => SATA_MAX_BURST_1_BINARY <= "010010"; + when 19 => SATA_MAX_BURST_1_BINARY <= "010011"; + when 20 => SATA_MAX_BURST_1_BINARY <= "010100"; + when 21 => SATA_MAX_BURST_1_BINARY <= "010101"; + when 22 => SATA_MAX_BURST_1_BINARY <= "010110"; + when 23 => SATA_MAX_BURST_1_BINARY <= "010111"; + when 24 => SATA_MAX_BURST_1_BINARY <= "011000"; + when 25 => SATA_MAX_BURST_1_BINARY <= "011001"; + when 26 => SATA_MAX_BURST_1_BINARY <= "011010"; + when 27 => SATA_MAX_BURST_1_BINARY <= "011011"; + when 28 => SATA_MAX_BURST_1_BINARY <= "011100"; + when 29 => SATA_MAX_BURST_1_BINARY <= "011101"; + when 30 => SATA_MAX_BURST_1_BINARY <= "011110"; + when 31 => SATA_MAX_BURST_1_BINARY <= "011111"; + when 32 => SATA_MAX_BURST_1_BINARY <= "100000"; + when 33 => SATA_MAX_BURST_1_BINARY <= "100001"; + when 34 => SATA_MAX_BURST_1_BINARY <= "100010"; + when 35 => SATA_MAX_BURST_1_BINARY <= "100011"; + when 36 => SATA_MAX_BURST_1_BINARY <= "100100"; + when 37 => SATA_MAX_BURST_1_BINARY <= "100101"; + when 38 => SATA_MAX_BURST_1_BINARY <= "100110"; + when 39 => SATA_MAX_BURST_1_BINARY <= "100111"; + when 40 => SATA_MAX_BURST_1_BINARY <= "101000"; + when 41 => SATA_MAX_BURST_1_BINARY <= "101001"; + when 42 => SATA_MAX_BURST_1_BINARY <= "101010"; + when 43 => SATA_MAX_BURST_1_BINARY <= "101011"; + when 44 => SATA_MAX_BURST_1_BINARY <= "101100"; + when 45 => SATA_MAX_BURST_1_BINARY <= "101101"; + when 46 => SATA_MAX_BURST_1_BINARY <= "101110"; + when 47 => SATA_MAX_BURST_1_BINARY <= "101111"; + when 48 => SATA_MAX_BURST_1_BINARY <= "110000"; + when 49 => SATA_MAX_BURST_1_BINARY <= "110001"; + when 50 => SATA_MAX_BURST_1_BINARY <= "110010"; + when 51 => SATA_MAX_BURST_1_BINARY <= "110011"; + when 52 => SATA_MAX_BURST_1_BINARY <= "110100"; + when 53 => SATA_MAX_BURST_1_BINARY <= "110101"; + when 54 => SATA_MAX_BURST_1_BINARY <= "110110"; + when 55 => SATA_MAX_BURST_1_BINARY <= "110111"; + when 56 => SATA_MAX_BURST_1_BINARY <= "111000"; + when 57 => SATA_MAX_BURST_1_BINARY <= "111001"; + when 58 => SATA_MAX_BURST_1_BINARY <= "111010"; + when 59 => SATA_MAX_BURST_1_BINARY <= "111011"; + when 60 => SATA_MAX_BURST_1_BINARY <= "111100"; + when 61 => SATA_MAX_BURST_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_BURST_1 is not in range 1...61." severity error; + end case; + case SATA_MIN_INIT_1 is + when 1 => SATA_MIN_INIT_1_BINARY <= "000001"; + when 2 => SATA_MIN_INIT_1_BINARY <= "000010"; + when 3 => SATA_MIN_INIT_1_BINARY <= "000011"; + when 4 => SATA_MIN_INIT_1_BINARY <= "000100"; + when 5 => SATA_MIN_INIT_1_BINARY <= "000101"; + when 6 => SATA_MIN_INIT_1_BINARY <= "000110"; + when 7 => SATA_MIN_INIT_1_BINARY <= "000111"; + when 8 => SATA_MIN_INIT_1_BINARY <= "001000"; + when 9 => SATA_MIN_INIT_1_BINARY <= "001001"; + when 10 => SATA_MIN_INIT_1_BINARY <= "001010"; + when 11 => SATA_MIN_INIT_1_BINARY <= "001011"; + when 12 => SATA_MIN_INIT_1_BINARY <= "001100"; + when 13 => SATA_MIN_INIT_1_BINARY <= "001101"; + when 14 => SATA_MIN_INIT_1_BINARY <= "001110"; + when 15 => SATA_MIN_INIT_1_BINARY <= "001111"; + when 16 => SATA_MIN_INIT_1_BINARY <= "010000"; + when 17 => SATA_MIN_INIT_1_BINARY <= "010001"; + when 18 => SATA_MIN_INIT_1_BINARY <= "010010"; + when 19 => SATA_MIN_INIT_1_BINARY <= "010011"; + when 20 => SATA_MIN_INIT_1_BINARY <= "010100"; + when 21 => SATA_MIN_INIT_1_BINARY <= "010101"; + when 22 => SATA_MIN_INIT_1_BINARY <= "010110"; + when 23 => SATA_MIN_INIT_1_BINARY <= "010111"; + when 24 => SATA_MIN_INIT_1_BINARY <= "011000"; + when 25 => SATA_MIN_INIT_1_BINARY <= "011001"; + when 26 => SATA_MIN_INIT_1_BINARY <= "011010"; + when 27 => SATA_MIN_INIT_1_BINARY <= "011011"; + when 28 => SATA_MIN_INIT_1_BINARY <= "011100"; + when 29 => SATA_MIN_INIT_1_BINARY <= "011101"; + when 30 => SATA_MIN_INIT_1_BINARY <= "011110"; + when 31 => SATA_MIN_INIT_1_BINARY <= "011111"; + when 32 => SATA_MIN_INIT_1_BINARY <= "100000"; + when 33 => SATA_MIN_INIT_1_BINARY <= "100001"; + when 34 => SATA_MIN_INIT_1_BINARY <= "100010"; + when 35 => SATA_MIN_INIT_1_BINARY <= "100011"; + when 36 => SATA_MIN_INIT_1_BINARY <= "100100"; + when 37 => SATA_MIN_INIT_1_BINARY <= "100101"; + when 38 => SATA_MIN_INIT_1_BINARY <= "100110"; + when 39 => SATA_MIN_INIT_1_BINARY <= "100111"; + when 40 => SATA_MIN_INIT_1_BINARY <= "101000"; + when 41 => SATA_MIN_INIT_1_BINARY <= "101001"; + when 42 => SATA_MIN_INIT_1_BINARY <= "101010"; + when 43 => SATA_MIN_INIT_1_BINARY <= "101011"; + when 44 => SATA_MIN_INIT_1_BINARY <= "101100"; + when 45 => SATA_MIN_INIT_1_BINARY <= "101101"; + when 46 => SATA_MIN_INIT_1_BINARY <= "101110"; + when 47 => SATA_MIN_INIT_1_BINARY <= "101111"; + when 48 => SATA_MIN_INIT_1_BINARY <= "110000"; + when 49 => SATA_MIN_INIT_1_BINARY <= "110001"; + when 50 => SATA_MIN_INIT_1_BINARY <= "110010"; + when 51 => SATA_MIN_INIT_1_BINARY <= "110011"; + when 52 => SATA_MIN_INIT_1_BINARY <= "110100"; + when 53 => SATA_MIN_INIT_1_BINARY <= "110101"; + when 54 => SATA_MIN_INIT_1_BINARY <= "110110"; + when 55 => SATA_MIN_INIT_1_BINARY <= "110111"; + when 56 => SATA_MIN_INIT_1_BINARY <= "111000"; + when 57 => SATA_MIN_INIT_1_BINARY <= "111001"; + when 58 => SATA_MIN_INIT_1_BINARY <= "111010"; + when 59 => SATA_MIN_INIT_1_BINARY <= "111011"; + when 60 => SATA_MIN_INIT_1_BINARY <= "111100"; + when 61 => SATA_MIN_INIT_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_INIT_1 is not in range 1...61." severity error; + end case; + case SATA_MAX_INIT_1 is + when 1 => SATA_MAX_INIT_1_BINARY <= "000001"; + when 2 => SATA_MAX_INIT_1_BINARY <= "000010"; + when 3 => SATA_MAX_INIT_1_BINARY <= "000011"; + when 4 => SATA_MAX_INIT_1_BINARY <= "000100"; + when 5 => SATA_MAX_INIT_1_BINARY <= "000101"; + when 6 => SATA_MAX_INIT_1_BINARY <= "000110"; + when 7 => SATA_MAX_INIT_1_BINARY <= "000111"; + when 8 => SATA_MAX_INIT_1_BINARY <= "001000"; + when 9 => SATA_MAX_INIT_1_BINARY <= "001001"; + when 10 => SATA_MAX_INIT_1_BINARY <= "001010"; + when 11 => SATA_MAX_INIT_1_BINARY <= "001011"; + when 12 => SATA_MAX_INIT_1_BINARY <= "001100"; + when 13 => SATA_MAX_INIT_1_BINARY <= "001101"; + when 14 => SATA_MAX_INIT_1_BINARY <= "001110"; + when 15 => SATA_MAX_INIT_1_BINARY <= "001111"; + when 16 => SATA_MAX_INIT_1_BINARY <= "010000"; + when 17 => SATA_MAX_INIT_1_BINARY <= "010001"; + when 18 => SATA_MAX_INIT_1_BINARY <= "010010"; + when 19 => SATA_MAX_INIT_1_BINARY <= "010011"; + when 20 => SATA_MAX_INIT_1_BINARY <= "010100"; + when 21 => SATA_MAX_INIT_1_BINARY <= "010101"; + when 22 => SATA_MAX_INIT_1_BINARY <= "010110"; + when 23 => SATA_MAX_INIT_1_BINARY <= "010111"; + when 24 => SATA_MAX_INIT_1_BINARY <= "011000"; + when 25 => SATA_MAX_INIT_1_BINARY <= "011001"; + when 26 => SATA_MAX_INIT_1_BINARY <= "011010"; + when 27 => SATA_MAX_INIT_1_BINARY <= "011011"; + when 28 => SATA_MAX_INIT_1_BINARY <= "011100"; + when 29 => SATA_MAX_INIT_1_BINARY <= "011101"; + when 30 => SATA_MAX_INIT_1_BINARY <= "011110"; + when 31 => SATA_MAX_INIT_1_BINARY <= "011111"; + when 32 => SATA_MAX_INIT_1_BINARY <= "100000"; + when 33 => SATA_MAX_INIT_1_BINARY <= "100001"; + when 34 => SATA_MAX_INIT_1_BINARY <= "100010"; + when 35 => SATA_MAX_INIT_1_BINARY <= "100011"; + when 36 => SATA_MAX_INIT_1_BINARY <= "100100"; + when 37 => SATA_MAX_INIT_1_BINARY <= "100101"; + when 38 => SATA_MAX_INIT_1_BINARY <= "100110"; + when 39 => SATA_MAX_INIT_1_BINARY <= "100111"; + when 40 => SATA_MAX_INIT_1_BINARY <= "101000"; + when 41 => SATA_MAX_INIT_1_BINARY <= "101001"; + when 42 => SATA_MAX_INIT_1_BINARY <= "101010"; + when 43 => SATA_MAX_INIT_1_BINARY <= "101011"; + when 44 => SATA_MAX_INIT_1_BINARY <= "101100"; + when 45 => SATA_MAX_INIT_1_BINARY <= "101101"; + when 46 => SATA_MAX_INIT_1_BINARY <= "101110"; + when 47 => SATA_MAX_INIT_1_BINARY <= "101111"; + when 48 => SATA_MAX_INIT_1_BINARY <= "110000"; + when 49 => SATA_MAX_INIT_1_BINARY <= "110001"; + when 50 => SATA_MAX_INIT_1_BINARY <= "110010"; + when 51 => SATA_MAX_INIT_1_BINARY <= "110011"; + when 52 => SATA_MAX_INIT_1_BINARY <= "110100"; + when 53 => SATA_MAX_INIT_1_BINARY <= "110101"; + when 54 => SATA_MAX_INIT_1_BINARY <= "110110"; + when 55 => SATA_MAX_INIT_1_BINARY <= "110111"; + when 56 => SATA_MAX_INIT_1_BINARY <= "111000"; + when 57 => SATA_MAX_INIT_1_BINARY <= "111001"; + when 58 => SATA_MAX_INIT_1_BINARY <= "111010"; + when 59 => SATA_MAX_INIT_1_BINARY <= "111011"; + when 60 => SATA_MAX_INIT_1_BINARY <= "111100"; + when 61 => SATA_MAX_INIT_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_INIT_1 is not in range 1...61." severity error; + end case; + case SATA_MIN_WAKE_1 is + when 1 => SATA_MIN_WAKE_1_BINARY <= "000001"; + when 2 => SATA_MIN_WAKE_1_BINARY <= "000010"; + when 3 => SATA_MIN_WAKE_1_BINARY <= "000011"; + when 4 => SATA_MIN_WAKE_1_BINARY <= "000100"; + when 5 => SATA_MIN_WAKE_1_BINARY <= "000101"; + when 6 => SATA_MIN_WAKE_1_BINARY <= "000110"; + when 7 => SATA_MIN_WAKE_1_BINARY <= "000111"; + when 8 => SATA_MIN_WAKE_1_BINARY <= "001000"; + when 9 => SATA_MIN_WAKE_1_BINARY <= "001001"; + when 10 => SATA_MIN_WAKE_1_BINARY <= "001010"; + when 11 => SATA_MIN_WAKE_1_BINARY <= "001011"; + when 12 => SATA_MIN_WAKE_1_BINARY <= "001100"; + when 13 => SATA_MIN_WAKE_1_BINARY <= "001101"; + when 14 => SATA_MIN_WAKE_1_BINARY <= "001110"; + when 15 => SATA_MIN_WAKE_1_BINARY <= "001111"; + when 16 => SATA_MIN_WAKE_1_BINARY <= "010000"; + when 17 => SATA_MIN_WAKE_1_BINARY <= "010001"; + when 18 => SATA_MIN_WAKE_1_BINARY <= "010010"; + when 19 => SATA_MIN_WAKE_1_BINARY <= "010011"; + when 20 => SATA_MIN_WAKE_1_BINARY <= "010100"; + when 21 => SATA_MIN_WAKE_1_BINARY <= "010101"; + when 22 => SATA_MIN_WAKE_1_BINARY <= "010110"; + when 23 => SATA_MIN_WAKE_1_BINARY <= "010111"; + when 24 => SATA_MIN_WAKE_1_BINARY <= "011000"; + when 25 => SATA_MIN_WAKE_1_BINARY <= "011001"; + when 26 => SATA_MIN_WAKE_1_BINARY <= "011010"; + when 27 => SATA_MIN_WAKE_1_BINARY <= "011011"; + when 28 => SATA_MIN_WAKE_1_BINARY <= "011100"; + when 29 => SATA_MIN_WAKE_1_BINARY <= "011101"; + when 30 => SATA_MIN_WAKE_1_BINARY <= "011110"; + when 31 => SATA_MIN_WAKE_1_BINARY <= "011111"; + when 32 => SATA_MIN_WAKE_1_BINARY <= "100000"; + when 33 => SATA_MIN_WAKE_1_BINARY <= "100001"; + when 34 => SATA_MIN_WAKE_1_BINARY <= "100010"; + when 35 => SATA_MIN_WAKE_1_BINARY <= "100011"; + when 36 => SATA_MIN_WAKE_1_BINARY <= "100100"; + when 37 => SATA_MIN_WAKE_1_BINARY <= "100101"; + when 38 => SATA_MIN_WAKE_1_BINARY <= "100110"; + when 39 => SATA_MIN_WAKE_1_BINARY <= "100111"; + when 40 => SATA_MIN_WAKE_1_BINARY <= "101000"; + when 41 => SATA_MIN_WAKE_1_BINARY <= "101001"; + when 42 => SATA_MIN_WAKE_1_BINARY <= "101010"; + when 43 => SATA_MIN_WAKE_1_BINARY <= "101011"; + when 44 => SATA_MIN_WAKE_1_BINARY <= "101100"; + when 45 => SATA_MIN_WAKE_1_BINARY <= "101101"; + when 46 => SATA_MIN_WAKE_1_BINARY <= "101110"; + when 47 => SATA_MIN_WAKE_1_BINARY <= "101111"; + when 48 => SATA_MIN_WAKE_1_BINARY <= "110000"; + when 49 => SATA_MIN_WAKE_1_BINARY <= "110001"; + when 50 => SATA_MIN_WAKE_1_BINARY <= "110010"; + when 51 => SATA_MIN_WAKE_1_BINARY <= "110011"; + when 52 => SATA_MIN_WAKE_1_BINARY <= "110100"; + when 53 => SATA_MIN_WAKE_1_BINARY <= "110101"; + when 54 => SATA_MIN_WAKE_1_BINARY <= "110110"; + when 55 => SATA_MIN_WAKE_1_BINARY <= "110111"; + when 56 => SATA_MIN_WAKE_1_BINARY <= "111000"; + when 57 => SATA_MIN_WAKE_1_BINARY <= "111001"; + when 58 => SATA_MIN_WAKE_1_BINARY <= "111010"; + when 59 => SATA_MIN_WAKE_1_BINARY <= "111011"; + when 60 => SATA_MIN_WAKE_1_BINARY <= "111100"; + when 61 => SATA_MIN_WAKE_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_WAKE_1 is not in range 1...61." severity error; + end case; + case SATA_MAX_WAKE_1 is + when 1 => SATA_MAX_WAKE_1_BINARY <= "000001"; + when 2 => SATA_MAX_WAKE_1_BINARY <= "000010"; + when 3 => SATA_MAX_WAKE_1_BINARY <= "000011"; + when 4 => SATA_MAX_WAKE_1_BINARY <= "000100"; + when 5 => SATA_MAX_WAKE_1_BINARY <= "000101"; + when 6 => SATA_MAX_WAKE_1_BINARY <= "000110"; + when 7 => SATA_MAX_WAKE_1_BINARY <= "000111"; + when 8 => SATA_MAX_WAKE_1_BINARY <= "001000"; + when 9 => SATA_MAX_WAKE_1_BINARY <= "001001"; + when 10 => SATA_MAX_WAKE_1_BINARY <= "001010"; + when 11 => SATA_MAX_WAKE_1_BINARY <= "001011"; + when 12 => SATA_MAX_WAKE_1_BINARY <= "001100"; + when 13 => SATA_MAX_WAKE_1_BINARY <= "001101"; + when 14 => SATA_MAX_WAKE_1_BINARY <= "001110"; + when 15 => SATA_MAX_WAKE_1_BINARY <= "001111"; + when 16 => SATA_MAX_WAKE_1_BINARY <= "010000"; + when 17 => SATA_MAX_WAKE_1_BINARY <= "010001"; + when 18 => SATA_MAX_WAKE_1_BINARY <= "010010"; + when 19 => SATA_MAX_WAKE_1_BINARY <= "010011"; + when 20 => SATA_MAX_WAKE_1_BINARY <= "010100"; + when 21 => SATA_MAX_WAKE_1_BINARY <= "010101"; + when 22 => SATA_MAX_WAKE_1_BINARY <= "010110"; + when 23 => SATA_MAX_WAKE_1_BINARY <= "010111"; + when 24 => SATA_MAX_WAKE_1_BINARY <= "011000"; + when 25 => SATA_MAX_WAKE_1_BINARY <= "011001"; + when 26 => SATA_MAX_WAKE_1_BINARY <= "011010"; + when 27 => SATA_MAX_WAKE_1_BINARY <= "011011"; + when 28 => SATA_MAX_WAKE_1_BINARY <= "011100"; + when 29 => SATA_MAX_WAKE_1_BINARY <= "011101"; + when 30 => SATA_MAX_WAKE_1_BINARY <= "011110"; + when 31 => SATA_MAX_WAKE_1_BINARY <= "011111"; + when 32 => SATA_MAX_WAKE_1_BINARY <= "100000"; + when 33 => SATA_MAX_WAKE_1_BINARY <= "100001"; + when 34 => SATA_MAX_WAKE_1_BINARY <= "100010"; + when 35 => SATA_MAX_WAKE_1_BINARY <= "100011"; + when 36 => SATA_MAX_WAKE_1_BINARY <= "100100"; + when 37 => SATA_MAX_WAKE_1_BINARY <= "100101"; + when 38 => SATA_MAX_WAKE_1_BINARY <= "100110"; + when 39 => SATA_MAX_WAKE_1_BINARY <= "100111"; + when 40 => SATA_MAX_WAKE_1_BINARY <= "101000"; + when 41 => SATA_MAX_WAKE_1_BINARY <= "101001"; + when 42 => SATA_MAX_WAKE_1_BINARY <= "101010"; + when 43 => SATA_MAX_WAKE_1_BINARY <= "101011"; + when 44 => SATA_MAX_WAKE_1_BINARY <= "101100"; + when 45 => SATA_MAX_WAKE_1_BINARY <= "101101"; + when 46 => SATA_MAX_WAKE_1_BINARY <= "101110"; + when 47 => SATA_MAX_WAKE_1_BINARY <= "101111"; + when 48 => SATA_MAX_WAKE_1_BINARY <= "110000"; + when 49 => SATA_MAX_WAKE_1_BINARY <= "110001"; + when 50 => SATA_MAX_WAKE_1_BINARY <= "110010"; + when 51 => SATA_MAX_WAKE_1_BINARY <= "110011"; + when 52 => SATA_MAX_WAKE_1_BINARY <= "110100"; + when 53 => SATA_MAX_WAKE_1_BINARY <= "110101"; + when 54 => SATA_MAX_WAKE_1_BINARY <= "110110"; + when 55 => SATA_MAX_WAKE_1_BINARY <= "110111"; + when 56 => SATA_MAX_WAKE_1_BINARY <= "111000"; + when 57 => SATA_MAX_WAKE_1_BINARY <= "111001"; + when 58 => SATA_MAX_WAKE_1_BINARY <= "111010"; + when 59 => SATA_MAX_WAKE_1_BINARY <= "111011"; + when 60 => SATA_MAX_WAKE_1_BINARY <= "111100"; + when 61 => SATA_MAX_WAKE_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_WAKE_1 is not in range 1...61." severity error; + end case; + case CLK25_DIVIDER is + when 1 => CLK25_DIVIDER_BINARY <= "000"; + when 2 => CLK25_DIVIDER_BINARY <= "001"; + when 3 => CLK25_DIVIDER_BINARY <= "010"; + when 4 => CLK25_DIVIDER_BINARY <= "011"; + when 5 => CLK25_DIVIDER_BINARY <= "100"; + when 6 => CLK25_DIVIDER_BINARY <= "101"; + when 10 => CLK25_DIVIDER_BINARY <= "110"; + when 12 => CLK25_DIVIDER_BINARY <= "111"; + when others => assert FALSE report "Error : CLK25_DIVIDER is not in 1, 2, 3, 4, 5, 6, 10, 12." severity error; + end case; + case OVERSAMPLE_MODE is + when FALSE => OVERSAMPLE_MODE_BINARY <= '0'; + when TRUE => OVERSAMPLE_MODE_BINARY <= '1'; + when others => assert FALSE report "Error : OVERSAMPLE_MODE is neither TRUE nor FALSE." severity error; + end case; + case TXGEARBOX_USE_0 is + when FALSE => TXGEARBOX_USE_0_BINARY <= '0'; + when TRUE => TXGEARBOX_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : TXGEARBOX_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case RXGEARBOX_USE_0 is + when FALSE => RXGEARBOX_USE_0_BINARY <= '0'; + when TRUE => RXGEARBOX_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : RXGEARBOX_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case TXGEARBOX_USE_1 is + when FALSE => TXGEARBOX_USE_1_BINARY <= '0'; + when TRUE => TXGEARBOX_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : TXGEARBOX_USE_1 is neither TRUE nor FALSE." severity error; + end case; + case RXGEARBOX_USE_1 is + when FALSE => RXGEARBOX_USE_1_BINARY <= '0'; + when TRUE => RXGEARBOX_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : RXGEARBOX_USE_1 is neither TRUE nor FALSE." severity error; + end case; + case PLL_FB_DCCEN is + when FALSE => PLL_FB_DCCEN_BINARY <= '0'; + when TRUE => PLL_FB_DCCEN_BINARY <= '1'; + when others => assert FALSE report "Error : PLL_FB_DCCEN is neither TRUE nor FALSE." severity error; + end case; + case CLKRCV_TRST is + when FALSE => CLKRCV_TRST_BINARY <= '0'; + when TRUE => CLKRCV_TRST_BINARY <= '1'; + when others => assert FALSE report "Error : CLKRCV_TRST is neither TRUE nor FALSE." severity error; + end case; + case RX_EN_IDLE_HOLD_DFE_0 is + when FALSE => RX_EN_IDLE_HOLD_DFE_0_BINARY <= '0'; + when TRUE => RX_EN_IDLE_HOLD_DFE_0_BINARY <= '1'; + when others => assert FALSE report "Error : RX_EN_IDLE_HOLD_DFE_0 is neither TRUE nor FALSE." severity error; + end case; + case RX_EN_IDLE_RESET_BUF_0 is + when FALSE => RX_EN_IDLE_RESET_BUF_0_BINARY <= '0'; + when TRUE => RX_EN_IDLE_RESET_BUF_0_BINARY <= '1'; + when others => assert FALSE report "Error : RX_EN_IDLE_RESET_BUF_0 is neither TRUE nor FALSE." severity error; + end case; + case RX_EN_IDLE_HOLD_DFE_1 is + when FALSE => RX_EN_IDLE_HOLD_DFE_1_BINARY <= '0'; + when TRUE => RX_EN_IDLE_HOLD_DFE_1_BINARY <= '1'; + when others => assert FALSE report "Error : RX_EN_IDLE_HOLD_DFE_1 is neither TRUE nor FALSE." severity error; + end case; + case RX_EN_IDLE_RESET_BUF_1 is + when FALSE => RX_EN_IDLE_RESET_BUF_1_BINARY <= '0'; + when TRUE => RX_EN_IDLE_RESET_BUF_1_BINARY <= '1'; + when others => assert FALSE report "Error : RX_EN_IDLE_RESET_BUF_1 is neither TRUE nor FALSE." severity error; + end case; + case RX_EN_IDLE_HOLD_CDR is + when FALSE => RX_EN_IDLE_HOLD_CDR_BINARY <= '0'; + when TRUE => RX_EN_IDLE_HOLD_CDR_BINARY <= '1'; + when others => assert FALSE report "Error : RX_EN_IDLE_HOLD_CDR is neither TRUE nor FALSE." severity error; + end case; + case RX_EN_IDLE_RESET_PH is + when FALSE => RX_EN_IDLE_RESET_PH_BINARY <= '0'; + when TRUE => RX_EN_IDLE_RESET_PH_BINARY <= '1'; + when others => assert FALSE report "Error : RX_EN_IDLE_RESET_PH is neither TRUE nor FALSE." severity error; + end case; + case RX_EN_IDLE_RESET_FR is + when FALSE => RX_EN_IDLE_RESET_FR_BINARY <= '0'; + when TRUE => RX_EN_IDLE_RESET_FR_BINARY <= '1'; + when others => assert FALSE report "Error : RX_EN_IDLE_RESET_FR is neither TRUE nor FALSE." severity error; + end case; + case SIM_GTXRESET_SPEEDUP is + when 0 => SIM_GTXRESET_SPEEDUP_BINARY <= '0'; + when 1 => SIM_GTXRESET_SPEEDUP_BINARY <= '1'; + when others => assert FALSE report "Error : SIM_GTXRESET_SPEEDUP is not in 0, 1." severity error; + end case; +-- case SIM_MODE is + if((SIM_MODE = "LEGACY") or (SIM_MODE = "legacy")) then + SIM_MODE_BINARY <= '1'; + elsif((SIM_MODE = "FAST") or (SIM_MODE = "fast")) then + SIM_MODE_BINARY <= '0'; + else + assert FALSE report "Error : SIM_MODE = is not LEGACY, FAST." severity error; + end if; +-- end case; + case SIM_RECEIVER_DETECT_PASS_0 is + when FALSE => SIM_RECEIVER_DETECT_PASS_0_BINARY <= '0'; + when TRUE => SIM_RECEIVER_DETECT_PASS_0_BINARY <= '1'; + when others => assert FALSE report "Error : SIM_RECEIVER_DETECT_PASS_0 is neither TRUE nor FALSE." severity error; + end case; + case SIM_RECEIVER_DETECT_PASS_1 is + when FALSE => SIM_RECEIVER_DETECT_PASS_1_BINARY <= '0'; + when TRUE => SIM_RECEIVER_DETECT_PASS_1_BINARY <= '1'; + when others => assert FALSE report "Error : SIM_RECEIVER_DETECT_PASS_1 is neither TRUE nor FALSE." severity error; + end case; + wait; + end process INIPROC; + + TIMING : process + + + + variable REFCLKOUT_GlitchData : VitalGlitchDataType; + variable RXRECCLK0_GlitchData : VitalGlitchDataType; + variable TXOUTCLK0_GlitchData : VitalGlitchDataType; + variable RXRECCLK1_GlitchData : VitalGlitchDataType; + variable TXOUTCLK1_GlitchData : VitalGlitchDataType; + variable TXP0_GlitchData : VitalGlitchDataType; + variable TXN0_GlitchData : VitalGlitchDataType; + variable TXP1_GlitchData : VitalGlitchDataType; + variable TXN1_GlitchData : VitalGlitchDataType; + variable RXDATA00_GlitchData : VitalGlitchDataType; + variable RXDATA01_GlitchData : VitalGlitchDataType; + variable RXDATA02_GlitchData : VitalGlitchDataType; + variable RXDATA03_GlitchData : VitalGlitchDataType; + variable RXDATA04_GlitchData : VitalGlitchDataType; + variable RXDATA05_GlitchData : VitalGlitchDataType; + variable RXDATA06_GlitchData : VitalGlitchDataType; + variable RXDATA07_GlitchData : VitalGlitchDataType; + variable RXDATA08_GlitchData : VitalGlitchDataType; + variable RXDATA09_GlitchData : VitalGlitchDataType; + variable RXDATA010_GlitchData : VitalGlitchDataType; + variable RXDATA011_GlitchData : VitalGlitchDataType; + variable RXDATA012_GlitchData : VitalGlitchDataType; + variable RXDATA013_GlitchData : VitalGlitchDataType; + variable RXDATA014_GlitchData : VitalGlitchDataType; + variable RXDATA015_GlitchData : VitalGlitchDataType; + variable RXDATA016_GlitchData : VitalGlitchDataType; + variable RXDATA017_GlitchData : VitalGlitchDataType; + variable RXDATA018_GlitchData : VitalGlitchDataType; + variable RXDATA019_GlitchData : VitalGlitchDataType; + variable RXDATA020_GlitchData : VitalGlitchDataType; + variable RXDATA021_GlitchData : VitalGlitchDataType; + variable RXDATA022_GlitchData : VitalGlitchDataType; + variable RXDATA023_GlitchData : VitalGlitchDataType; + variable RXDATA024_GlitchData : VitalGlitchDataType; + variable RXDATA025_GlitchData : VitalGlitchDataType; + variable RXDATA026_GlitchData : VitalGlitchDataType; + variable RXDATA027_GlitchData : VitalGlitchDataType; + variable RXDATA028_GlitchData : VitalGlitchDataType; + variable RXDATA029_GlitchData : VitalGlitchDataType; + variable RXDATA030_GlitchData : VitalGlitchDataType; + variable RXDATA031_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE00_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE01_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE02_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE03_GlitchData : VitalGlitchDataType; + variable RXDISPERR00_GlitchData : VitalGlitchDataType; + variable RXDISPERR01_GlitchData : VitalGlitchDataType; + variable RXDISPERR02_GlitchData : VitalGlitchDataType; + variable RXDISPERR03_GlitchData : VitalGlitchDataType; + variable RXCHARISK00_GlitchData : VitalGlitchDataType; + variable RXCHARISK01_GlitchData : VitalGlitchDataType; + variable RXCHARISK02_GlitchData : VitalGlitchDataType; + variable RXCHARISK03_GlitchData : VitalGlitchDataType; + variable RXRUNDISP00_GlitchData : VitalGlitchDataType; + variable RXRUNDISP01_GlitchData : VitalGlitchDataType; + variable RXRUNDISP02_GlitchData : VitalGlitchDataType; + variable RXRUNDISP03_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA00_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA01_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA02_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA03_GlitchData : VitalGlitchDataType; + variable RXVALID0_GlitchData : VitalGlitchDataType; + variable RXDATA10_GlitchData : VitalGlitchDataType; + variable RXDATA11_GlitchData : VitalGlitchDataType; + variable RXDATA12_GlitchData : VitalGlitchDataType; + variable RXDATA13_GlitchData : VitalGlitchDataType; + variable RXDATA14_GlitchData : VitalGlitchDataType; + variable RXDATA15_GlitchData : VitalGlitchDataType; + variable RXDATA16_GlitchData : VitalGlitchDataType; + variable RXDATA17_GlitchData : VitalGlitchDataType; + variable RXDATA18_GlitchData : VitalGlitchDataType; + variable RXDATA19_GlitchData : VitalGlitchDataType; + variable RXDATA110_GlitchData : VitalGlitchDataType; + variable RXDATA111_GlitchData : VitalGlitchDataType; + variable RXDATA112_GlitchData : VitalGlitchDataType; + variable RXDATA113_GlitchData : VitalGlitchDataType; + variable RXDATA114_GlitchData : VitalGlitchDataType; + variable RXDATA115_GlitchData : VitalGlitchDataType; + variable RXDATA116_GlitchData : VitalGlitchDataType; + variable RXDATA117_GlitchData : VitalGlitchDataType; + variable RXDATA118_GlitchData : VitalGlitchDataType; + variable RXDATA119_GlitchData : VitalGlitchDataType; + variable RXDATA120_GlitchData : VitalGlitchDataType; + variable RXDATA121_GlitchData : VitalGlitchDataType; + variable RXDATA122_GlitchData : VitalGlitchDataType; + variable RXDATA123_GlitchData : VitalGlitchDataType; + variable RXDATA124_GlitchData : VitalGlitchDataType; + variable RXDATA125_GlitchData : VitalGlitchDataType; + variable RXDATA126_GlitchData : VitalGlitchDataType; + variable RXDATA127_GlitchData : VitalGlitchDataType; + variable RXDATA128_GlitchData : VitalGlitchDataType; + variable RXDATA129_GlitchData : VitalGlitchDataType; + variable RXDATA130_GlitchData : VitalGlitchDataType; + variable RXDATA131_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE10_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE11_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE12_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE13_GlitchData : VitalGlitchDataType; + variable RXDISPERR10_GlitchData : VitalGlitchDataType; + variable RXDISPERR11_GlitchData : VitalGlitchDataType; + variable RXDISPERR12_GlitchData : VitalGlitchDataType; + variable RXDISPERR13_GlitchData : VitalGlitchDataType; + variable RXCHARISK10_GlitchData : VitalGlitchDataType; + variable RXCHARISK11_GlitchData : VitalGlitchDataType; + variable RXCHARISK12_GlitchData : VitalGlitchDataType; + variable RXCHARISK13_GlitchData : VitalGlitchDataType; + variable RXRUNDISP10_GlitchData : VitalGlitchDataType; + variable RXRUNDISP11_GlitchData : VitalGlitchDataType; + variable RXRUNDISP12_GlitchData : VitalGlitchDataType; + variable RXRUNDISP13_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA10_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA11_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA12_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA13_GlitchData : VitalGlitchDataType; + variable RXVALID1_GlitchData : VitalGlitchDataType; + variable RESETDONE0_GlitchData : VitalGlitchDataType; + variable RESETDONE1_GlitchData : VitalGlitchDataType; + variable TXKERR00_GlitchData : VitalGlitchDataType; + variable TXKERR01_GlitchData : VitalGlitchDataType; + variable TXKERR02_GlitchData : VitalGlitchDataType; + variable TXKERR03_GlitchData : VitalGlitchDataType; + variable TXRUNDISP00_GlitchData : VitalGlitchDataType; + variable TXRUNDISP01_GlitchData : VitalGlitchDataType; + variable TXRUNDISP02_GlitchData : VitalGlitchDataType; + variable TXRUNDISP03_GlitchData : VitalGlitchDataType; + variable TXBUFSTATUS00_GlitchData : VitalGlitchDataType; + variable TXBUFSTATUS01_GlitchData : VitalGlitchDataType; + variable TXKERR10_GlitchData : VitalGlitchDataType; + variable TXKERR11_GlitchData : VitalGlitchDataType; + variable TXKERR12_GlitchData : VitalGlitchDataType; + variable TXKERR13_GlitchData : VitalGlitchDataType; + variable TXRUNDISP10_GlitchData : VitalGlitchDataType; + variable TXRUNDISP11_GlitchData : VitalGlitchDataType; + variable TXRUNDISP12_GlitchData : VitalGlitchDataType; + variable TXRUNDISP13_GlitchData : VitalGlitchDataType; + variable TXBUFSTATUS10_GlitchData : VitalGlitchDataType; + variable TXBUFSTATUS11_GlitchData : VitalGlitchDataType; + variable RXCOMMADET0_GlitchData : VitalGlitchDataType; + variable RXBYTEREALIGN0_GlitchData : VitalGlitchDataType; + variable RXBYTEISALIGNED0_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC00_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC01_GlitchData : VitalGlitchDataType; + variable RXCHBONDO00_GlitchData : VitalGlitchDataType; + variable RXCHBONDO01_GlitchData : VitalGlitchDataType; + variable RXCHBONDO02_GlitchData : VitalGlitchDataType; + variable RXCHBONDO03_GlitchData : VitalGlitchDataType; + variable RXCHANBONDSEQ0_GlitchData : VitalGlitchDataType; + variable RXCHANREALIGN0_GlitchData : VitalGlitchDataType; + variable RXCHANISALIGNED0_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS00_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS01_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS02_GlitchData : VitalGlitchDataType; + variable RXCOMMADET1_GlitchData : VitalGlitchDataType; + variable RXBYTEREALIGN1_GlitchData : VitalGlitchDataType; + variable RXBYTEISALIGNED1_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC10_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC11_GlitchData : VitalGlitchDataType; + variable RXCHBONDO10_GlitchData : VitalGlitchDataType; + variable RXCHBONDO11_GlitchData : VitalGlitchDataType; + variable RXCHBONDO12_GlitchData : VitalGlitchDataType; + variable RXCHBONDO13_GlitchData : VitalGlitchDataType; + variable RXCHANBONDSEQ1_GlitchData : VitalGlitchDataType; + variable RXCHANREALIGN1_GlitchData : VitalGlitchDataType; + variable RXCHANISALIGNED1_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS10_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS11_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS12_GlitchData : VitalGlitchDataType; + variable PHYSTATUS0_GlitchData : VitalGlitchDataType; + variable PHYSTATUS1_GlitchData : VitalGlitchDataType; + variable RXELECIDLE0_GlitchData : VitalGlitchDataType; + variable RXSTATUS00_GlitchData : VitalGlitchDataType; + variable RXSTATUS01_GlitchData : VitalGlitchDataType; + variable RXSTATUS02_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT00_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT01_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT02_GlitchData : VitalGlitchDataType; + variable RXELECIDLE1_GlitchData : VitalGlitchDataType; + variable RXSTATUS10_GlitchData : VitalGlitchDataType; + variable RXSTATUS11_GlitchData : VitalGlitchDataType; + variable RXSTATUS12_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT10_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT11_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT12_GlitchData : VitalGlitchDataType; + variable PLLLKDET_GlitchData : VitalGlitchDataType; + variable RXPRBSERR0_GlitchData : VitalGlitchDataType; + variable RXPRBSERR1_GlitchData : VitalGlitchDataType; + variable DO0_GlitchData : VitalGlitchDataType; + variable DO1_GlitchData : VitalGlitchDataType; + variable DO2_GlitchData : VitalGlitchDataType; + variable DO3_GlitchData : VitalGlitchDataType; + variable DO4_GlitchData : VitalGlitchDataType; + variable DO5_GlitchData : VitalGlitchDataType; + variable DO6_GlitchData : VitalGlitchDataType; + variable DO7_GlitchData : VitalGlitchDataType; + variable DO8_GlitchData : VitalGlitchDataType; + variable DO9_GlitchData : VitalGlitchDataType; + variable DO10_GlitchData : VitalGlitchDataType; + variable DO11_GlitchData : VitalGlitchDataType; + variable DO12_GlitchData : VitalGlitchDataType; + variable DO13_GlitchData : VitalGlitchDataType; + variable DO14_GlitchData : VitalGlitchDataType; + variable DO15_GlitchData : VitalGlitchDataType; + variable DRDY_GlitchData : VitalGlitchDataType; + variable RXOVERSAMPLEERR0_GlitchData : VitalGlitchDataType; + variable RXOVERSAMPLEERR1_GlitchData : VitalGlitchDataType; + variable TXGEARBOXREADY0_GlitchData : VitalGlitchDataType; + variable RXHEADER00_GlitchData : VitalGlitchDataType; + variable RXHEADER01_GlitchData : VitalGlitchDataType; + variable RXHEADER02_GlitchData : VitalGlitchDataType; + variable RXHEADERVALID0_GlitchData : VitalGlitchDataType; + variable RXDATAVALID0_GlitchData : VitalGlitchDataType; + variable RXSTARTOFSEQ0_GlitchData : VitalGlitchDataType; + variable TXGEARBOXREADY1_GlitchData : VitalGlitchDataType; + variable RXHEADER10_GlitchData : VitalGlitchDataType; + variable RXHEADER11_GlitchData : VitalGlitchDataType; + variable RXHEADER12_GlitchData : VitalGlitchDataType; + variable RXHEADERVALID1_GlitchData : VitalGlitchDataType; + variable RXDATAVALID1_GlitchData : VitalGlitchDataType; + variable RXSTARTOFSEQ1_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR00_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR01_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR02_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR03_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR04_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR05_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR00_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR01_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR02_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR03_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR04_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR00_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR01_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR02_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR03_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR04_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR00_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR01_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR02_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR03_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR04_GlitchData : VitalGlitchDataType; + variable DFETAP3MONITOR00_GlitchData : VitalGlitchDataType; + variable DFETAP3MONITOR01_GlitchData : VitalGlitchDataType; + variable DFETAP3MONITOR02_GlitchData : VitalGlitchDataType; + variable DFETAP3MONITOR03_GlitchData : VitalGlitchDataType; + variable DFETAP4MONITOR00_GlitchData : VitalGlitchDataType; + variable DFETAP4MONITOR01_GlitchData : VitalGlitchDataType; + variable DFETAP4MONITOR02_GlitchData : VitalGlitchDataType; + variable DFETAP4MONITOR03_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR10_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR11_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR12_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR13_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR14_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR15_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR10_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR11_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR12_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR13_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR14_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR10_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR11_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR12_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR13_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR14_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR10_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR11_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR12_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR13_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR14_GlitchData : VitalGlitchDataType; + variable DFETAP3MONITOR10_GlitchData : VitalGlitchDataType; + variable DFETAP3MONITOR11_GlitchData : VitalGlitchDataType; + variable DFETAP3MONITOR12_GlitchData : VitalGlitchDataType; + variable DFETAP3MONITOR13_GlitchData : VitalGlitchDataType; + variable DFETAP4MONITOR10_GlitchData : VitalGlitchDataType; + variable DFETAP4MONITOR11_GlitchData : VitalGlitchDataType; + variable DFETAP4MONITOR12_GlitchData : VitalGlitchDataType; + variable DFETAP4MONITOR13_GlitchData : VitalGlitchDataType; + variable DFESENSCAL00_GlitchData : VitalGlitchDataType; + variable DFESENSCAL01_GlitchData : VitalGlitchDataType; + variable DFESENSCAL02_GlitchData : VitalGlitchDataType; + variable DFESENSCAL10_GlitchData : VitalGlitchDataType; + variable DFESENSCAL11_GlitchData : VitalGlitchDataType; + variable DFESENSCAL12_GlitchData : VitalGlitchDataType; +begin + + VitalPathDelay01 + ( + OutSignal => REFCLKOUT, + GlitchData => REFCLKOUT_GlitchData, + OutSignalName => "REFCLKOUT", + OutTemp => REFCLKOUT_OUT, + Paths => (0 => (CLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(0), + GlitchData => RXDATA00_GlitchData, + OutSignalName => "RXDATA0(0)", + OutTemp => RXDATA0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(1), + GlitchData => RXDATA01_GlitchData, + OutSignalName => "RXDATA0(1)", + OutTemp => RXDATA0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(2), + GlitchData => RXDATA02_GlitchData, + OutSignalName => "RXDATA0(2)", + OutTemp => RXDATA0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(3), + GlitchData => RXDATA03_GlitchData, + OutSignalName => "RXDATA0(3)", + OutTemp => RXDATA0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(4), + GlitchData => RXDATA04_GlitchData, + OutSignalName => "RXDATA0(4)", + OutTemp => RXDATA0_OUT(4), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(5), + GlitchData => RXDATA05_GlitchData, + OutSignalName => "RXDATA0(5)", + OutTemp => RXDATA0_OUT(5), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(6), + GlitchData => RXDATA06_GlitchData, + OutSignalName => "RXDATA0(6)", + OutTemp => RXDATA0_OUT(6), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(7), + GlitchData => RXDATA07_GlitchData, + OutSignalName => "RXDATA0(7)", + OutTemp => RXDATA0_OUT(7), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(8), + GlitchData => RXDATA08_GlitchData, + OutSignalName => "RXDATA0(8)", + OutTemp => RXDATA0_OUT(8), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(9), + GlitchData => RXDATA09_GlitchData, + OutSignalName => "RXDATA0(9)", + OutTemp => RXDATA0_OUT(9), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(10), + GlitchData => RXDATA010_GlitchData, + OutSignalName => "RXDATA0(10)", + OutTemp => RXDATA0_OUT(10), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(11), + GlitchData => RXDATA011_GlitchData, + OutSignalName => "RXDATA0(11)", + OutTemp => RXDATA0_OUT(11), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(12), + GlitchData => RXDATA012_GlitchData, + OutSignalName => "RXDATA0(12)", + OutTemp => RXDATA0_OUT(12), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(13), + GlitchData => RXDATA013_GlitchData, + OutSignalName => "RXDATA0(13)", + OutTemp => RXDATA0_OUT(13), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(14), + GlitchData => RXDATA014_GlitchData, + OutSignalName => "RXDATA0(14)", + OutTemp => RXDATA0_OUT(14), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(15), + GlitchData => RXDATA015_GlitchData, + OutSignalName => "RXDATA0(15)", + OutTemp => RXDATA0_OUT(15), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(16), + GlitchData => RXDATA016_GlitchData, + OutSignalName => "RXDATA0(16)", + OutTemp => RXDATA0_OUT(16), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(17), + GlitchData => RXDATA017_GlitchData, + OutSignalName => "RXDATA0(17)", + OutTemp => RXDATA0_OUT(17), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(18), + GlitchData => RXDATA018_GlitchData, + OutSignalName => "RXDATA0(18)", + OutTemp => RXDATA0_OUT(18), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(19), + GlitchData => RXDATA019_GlitchData, + OutSignalName => "RXDATA0(19)", + OutTemp => RXDATA0_OUT(19), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(20), + GlitchData => RXDATA020_GlitchData, + OutSignalName => "RXDATA0(20)", + OutTemp => RXDATA0_OUT(20), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(21), + GlitchData => RXDATA021_GlitchData, + OutSignalName => "RXDATA0(21)", + OutTemp => RXDATA0_OUT(21), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(22), + GlitchData => RXDATA022_GlitchData, + OutSignalName => "RXDATA0(22)", + OutTemp => RXDATA0_OUT(22), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(23), + GlitchData => RXDATA023_GlitchData, + OutSignalName => "RXDATA0(23)", + OutTemp => RXDATA0_OUT(23), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(24), + GlitchData => RXDATA024_GlitchData, + OutSignalName => "RXDATA0(24)", + OutTemp => RXDATA0_OUT(24), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(25), + GlitchData => RXDATA025_GlitchData, + OutSignalName => "RXDATA0(25)", + OutTemp => RXDATA0_OUT(25), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(26), + GlitchData => RXDATA026_GlitchData, + OutSignalName => "RXDATA0(26)", + OutTemp => RXDATA0_OUT(26), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(27), + GlitchData => RXDATA027_GlitchData, + OutSignalName => "RXDATA0(27)", + OutTemp => RXDATA0_OUT(27), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(28), + GlitchData => RXDATA028_GlitchData, + OutSignalName => "RXDATA0(28)", + OutTemp => RXDATA0_OUT(28), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(29), + GlitchData => RXDATA029_GlitchData, + OutSignalName => "RXDATA0(29)", + OutTemp => RXDATA0_OUT(29), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(30), + GlitchData => RXDATA030_GlitchData, + OutSignalName => "RXDATA0(30)", + OutTemp => RXDATA0_OUT(30), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(31), + GlitchData => RXDATA031_GlitchData, + OutSignalName => "RXDATA0(31)", + OutTemp => RXDATA0_OUT(31), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE0(0), + GlitchData => RXNOTINTABLE00_GlitchData, + OutSignalName => "RXNOTINTABLE0(0)", + OutTemp => RXNOTINTABLE0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE0(1), + GlitchData => RXNOTINTABLE01_GlitchData, + OutSignalName => "RXNOTINTABLE0(1)", + OutTemp => RXNOTINTABLE0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE0(2), + GlitchData => RXNOTINTABLE02_GlitchData, + OutSignalName => "RXNOTINTABLE0(2)", + OutTemp => RXNOTINTABLE0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE0(3), + GlitchData => RXNOTINTABLE03_GlitchData, + OutSignalName => "RXNOTINTABLE0(3)", + OutTemp => RXNOTINTABLE0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR0(0), + GlitchData => RXDISPERR00_GlitchData, + OutSignalName => "RXDISPERR0(0)", + OutTemp => RXDISPERR0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR0(1), + GlitchData => RXDISPERR01_GlitchData, + OutSignalName => "RXDISPERR0(1)", + OutTemp => RXDISPERR0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR0(2), + GlitchData => RXDISPERR02_GlitchData, + OutSignalName => "RXDISPERR0(2)", + OutTemp => RXDISPERR0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR0(3), + GlitchData => RXDISPERR03_GlitchData, + OutSignalName => "RXDISPERR0(3)", + OutTemp => RXDISPERR0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK0(0), + GlitchData => RXCHARISK00_GlitchData, + OutSignalName => "RXCHARISK0(0)", + OutTemp => RXCHARISK0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK0(1), + GlitchData => RXCHARISK01_GlitchData, + OutSignalName => "RXCHARISK0(1)", + OutTemp => RXCHARISK0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK0(2), + GlitchData => RXCHARISK02_GlitchData, + OutSignalName => "RXCHARISK0(2)", + OutTemp => RXCHARISK0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK0(3), + GlitchData => RXCHARISK03_GlitchData, + OutSignalName => "RXCHARISK0(3)", + OutTemp => RXCHARISK0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP0(0), + GlitchData => RXRUNDISP00_GlitchData, + OutSignalName => "RXRUNDISP0(0)", + OutTemp => RXRUNDISP0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP0(1), + GlitchData => RXRUNDISP01_GlitchData, + OutSignalName => "RXRUNDISP0(1)", + OutTemp => RXRUNDISP0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP0(2), + GlitchData => RXRUNDISP02_GlitchData, + OutSignalName => "RXRUNDISP0(2)", + OutTemp => RXRUNDISP0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP0(3), + GlitchData => RXRUNDISP03_GlitchData, + OutSignalName => "RXRUNDISP0(3)", + OutTemp => RXRUNDISP0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA0(0), + GlitchData => RXCHARISCOMMA00_GlitchData, + OutSignalName => "RXCHARISCOMMA0(0)", + OutTemp => RXCHARISCOMMA0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA0(1), + GlitchData => RXCHARISCOMMA01_GlitchData, + OutSignalName => "RXCHARISCOMMA0(1)", + OutTemp => RXCHARISCOMMA0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA0(2), + GlitchData => RXCHARISCOMMA02_GlitchData, + OutSignalName => "RXCHARISCOMMA0(2)", + OutTemp => RXCHARISCOMMA0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA0(3), + GlitchData => RXCHARISCOMMA03_GlitchData, + OutSignalName => "RXCHARISCOMMA0(3)", + OutTemp => RXCHARISCOMMA0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXVALID0, + GlitchData => RXVALID0_GlitchData, + OutSignalName => "RXVALID0", + OutTemp => RXVALID0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(0), + GlitchData => RXDATA10_GlitchData, + OutSignalName => "RXDATA1(0)", + OutTemp => RXDATA1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(1), + GlitchData => RXDATA11_GlitchData, + OutSignalName => "RXDATA1(1)", + OutTemp => RXDATA1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(2), + GlitchData => RXDATA12_GlitchData, + OutSignalName => "RXDATA1(2)", + OutTemp => RXDATA1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(3), + GlitchData => RXDATA13_GlitchData, + OutSignalName => "RXDATA1(3)", + OutTemp => RXDATA1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(4), + GlitchData => RXDATA14_GlitchData, + OutSignalName => "RXDATA1(4)", + OutTemp => RXDATA1_OUT(4), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(5), + GlitchData => RXDATA15_GlitchData, + OutSignalName => "RXDATA1(5)", + OutTemp => RXDATA1_OUT(5), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(6), + GlitchData => RXDATA16_GlitchData, + OutSignalName => "RXDATA1(6)", + OutTemp => RXDATA1_OUT(6), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(7), + GlitchData => RXDATA17_GlitchData, + OutSignalName => "RXDATA1(7)", + OutTemp => RXDATA1_OUT(7), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(8), + GlitchData => RXDATA18_GlitchData, + OutSignalName => "RXDATA1(8)", + OutTemp => RXDATA1_OUT(8), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(9), + GlitchData => RXDATA19_GlitchData, + OutSignalName => "RXDATA1(9)", + OutTemp => RXDATA1_OUT(9), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(10), + GlitchData => RXDATA110_GlitchData, + OutSignalName => "RXDATA1(10)", + OutTemp => RXDATA1_OUT(10), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(11), + GlitchData => RXDATA111_GlitchData, + OutSignalName => "RXDATA1(11)", + OutTemp => RXDATA1_OUT(11), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(12), + GlitchData => RXDATA112_GlitchData, + OutSignalName => "RXDATA1(12)", + OutTemp => RXDATA1_OUT(12), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(13), + GlitchData => RXDATA113_GlitchData, + OutSignalName => "RXDATA1(13)", + OutTemp => RXDATA1_OUT(13), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(14), + GlitchData => RXDATA114_GlitchData, + OutSignalName => "RXDATA1(14)", + OutTemp => RXDATA1_OUT(14), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(15), + GlitchData => RXDATA115_GlitchData, + OutSignalName => "RXDATA1(15)", + OutTemp => RXDATA1_OUT(15), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(16), + GlitchData => RXDATA116_GlitchData, + OutSignalName => "RXDATA1(16)", + OutTemp => RXDATA1_OUT(16), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(17), + GlitchData => RXDATA117_GlitchData, + OutSignalName => "RXDATA1(17)", + OutTemp => RXDATA1_OUT(17), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(18), + GlitchData => RXDATA118_GlitchData, + OutSignalName => "RXDATA1(18)", + OutTemp => RXDATA1_OUT(18), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(19), + GlitchData => RXDATA119_GlitchData, + OutSignalName => "RXDATA1(19)", + OutTemp => RXDATA1_OUT(19), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(20), + GlitchData => RXDATA120_GlitchData, + OutSignalName => "RXDATA1(20)", + OutTemp => RXDATA1_OUT(20), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(21), + GlitchData => RXDATA121_GlitchData, + OutSignalName => "RXDATA1(21)", + OutTemp => RXDATA1_OUT(21), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(22), + GlitchData => RXDATA122_GlitchData, + OutSignalName => "RXDATA1(22)", + OutTemp => RXDATA1_OUT(22), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(23), + GlitchData => RXDATA123_GlitchData, + OutSignalName => "RXDATA1(23)", + OutTemp => RXDATA1_OUT(23), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(24), + GlitchData => RXDATA124_GlitchData, + OutSignalName => "RXDATA1(24)", + OutTemp => RXDATA1_OUT(24), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(25), + GlitchData => RXDATA125_GlitchData, + OutSignalName => "RXDATA1(25)", + OutTemp => RXDATA1_OUT(25), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(26), + GlitchData => RXDATA126_GlitchData, + OutSignalName => "RXDATA1(26)", + OutTemp => RXDATA1_OUT(26), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(27), + GlitchData => RXDATA127_GlitchData, + OutSignalName => "RXDATA1(27)", + OutTemp => RXDATA1_OUT(27), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(28), + GlitchData => RXDATA128_GlitchData, + OutSignalName => "RXDATA1(28)", + OutTemp => RXDATA1_OUT(28), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(29), + GlitchData => RXDATA129_GlitchData, + OutSignalName => "RXDATA1(29)", + OutTemp => RXDATA1_OUT(29), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(30), + GlitchData => RXDATA130_GlitchData, + OutSignalName => "RXDATA1(30)", + OutTemp => RXDATA1_OUT(30), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(31), + GlitchData => RXDATA131_GlitchData, + OutSignalName => "RXDATA1(31)", + OutTemp => RXDATA1_OUT(31), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE1(0), + GlitchData => RXNOTINTABLE10_GlitchData, + OutSignalName => "RXNOTINTABLE1(0)", + OutTemp => RXNOTINTABLE1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE1(1), + GlitchData => RXNOTINTABLE11_GlitchData, + OutSignalName => "RXNOTINTABLE1(1)", + OutTemp => RXNOTINTABLE1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE1(2), + GlitchData => RXNOTINTABLE12_GlitchData, + OutSignalName => "RXNOTINTABLE1(2)", + OutTemp => RXNOTINTABLE1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE1(3), + GlitchData => RXNOTINTABLE13_GlitchData, + OutSignalName => "RXNOTINTABLE1(3)", + OutTemp => RXNOTINTABLE1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR1(0), + GlitchData => RXDISPERR10_GlitchData, + OutSignalName => "RXDISPERR1(0)", + OutTemp => RXDISPERR1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR1(1), + GlitchData => RXDISPERR11_GlitchData, + OutSignalName => "RXDISPERR1(1)", + OutTemp => RXDISPERR1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR1(2), + GlitchData => RXDISPERR12_GlitchData, + OutSignalName => "RXDISPERR1(2)", + OutTemp => RXDISPERR1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR1(3), + GlitchData => RXDISPERR13_GlitchData, + OutSignalName => "RXDISPERR1(3)", + OutTemp => RXDISPERR1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK1(0), + GlitchData => RXCHARISK10_GlitchData, + OutSignalName => "RXCHARISK1(0)", + OutTemp => RXCHARISK1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK1(1), + GlitchData => RXCHARISK11_GlitchData, + OutSignalName => "RXCHARISK1(1)", + OutTemp => RXCHARISK1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK1(2), + GlitchData => RXCHARISK12_GlitchData, + OutSignalName => "RXCHARISK1(2)", + OutTemp => RXCHARISK1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK1(3), + GlitchData => RXCHARISK13_GlitchData, + OutSignalName => "RXCHARISK1(3)", + OutTemp => RXCHARISK1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP1(0), + GlitchData => RXRUNDISP10_GlitchData, + OutSignalName => "RXRUNDISP1(0)", + OutTemp => RXRUNDISP1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP1(1), + GlitchData => RXRUNDISP11_GlitchData, + OutSignalName => "RXRUNDISP1(1)", + OutTemp => RXRUNDISP1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP1(2), + GlitchData => RXRUNDISP12_GlitchData, + OutSignalName => "RXRUNDISP1(2)", + OutTemp => RXRUNDISP1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP1(3), + GlitchData => RXRUNDISP13_GlitchData, + OutSignalName => "RXRUNDISP1(3)", + OutTemp => RXRUNDISP1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA1(0), + GlitchData => RXCHARISCOMMA10_GlitchData, + OutSignalName => "RXCHARISCOMMA1(0)", + OutTemp => RXCHARISCOMMA1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA1(1), + GlitchData => RXCHARISCOMMA11_GlitchData, + OutSignalName => "RXCHARISCOMMA1(1)", + OutTemp => RXCHARISCOMMA1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA1(2), + GlitchData => RXCHARISCOMMA12_GlitchData, + OutSignalName => "RXCHARISCOMMA1(2)", + OutTemp => RXCHARISCOMMA1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA1(3), + GlitchData => RXCHARISCOMMA13_GlitchData, + OutSignalName => "RXCHARISCOMMA1(3)", + OutTemp => RXCHARISCOMMA1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXVALID1, + GlitchData => RXVALID1_GlitchData, + OutSignalName => "RXVALID1", + OutTemp => RXVALID1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR0(0), + GlitchData => TXKERR00_GlitchData, + OutSignalName => "TXKERR0(0)", + OutTemp => TXKERR0_OUT(0), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR0(1), + GlitchData => TXKERR01_GlitchData, + OutSignalName => "TXKERR0(1)", + OutTemp => TXKERR0_OUT(1), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR0(2), + GlitchData => TXKERR02_GlitchData, + OutSignalName => "TXKERR0(2)", + OutTemp => TXKERR0_OUT(2), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR0(3), + GlitchData => TXKERR03_GlitchData, + OutSignalName => "TXKERR0(3)", + OutTemp => TXKERR0_OUT(3), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP0(0), + GlitchData => TXRUNDISP00_GlitchData, + OutSignalName => "TXRUNDISP0(0)", + OutTemp => TXRUNDISP0_OUT(0), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP0(1), + GlitchData => TXRUNDISP01_GlitchData, + OutSignalName => "TXRUNDISP0(1)", + OutTemp => TXRUNDISP0_OUT(1), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP0(2), + GlitchData => TXRUNDISP02_GlitchData, + OutSignalName => "TXRUNDISP0(2)", + OutTemp => TXRUNDISP0_OUT(2), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP0(3), + GlitchData => TXRUNDISP03_GlitchData, + OutSignalName => "TXRUNDISP0(3)", + OutTemp => TXRUNDISP0_OUT(3), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXBUFSTATUS0(0), + GlitchData => TXBUFSTATUS00_GlitchData, + OutSignalName => "TXBUFSTATUS0(0)", + OutTemp => TXBUFSTATUS0_OUT(0), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXBUFSTATUS0(1), + GlitchData => TXBUFSTATUS01_GlitchData, + OutSignalName => "TXBUFSTATUS0(1)", + OutTemp => TXBUFSTATUS0_OUT(1), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR1(0), + GlitchData => TXKERR10_GlitchData, + OutSignalName => "TXKERR1(0)", + OutTemp => TXKERR1_OUT(0), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR1(1), + GlitchData => TXKERR11_GlitchData, + OutSignalName => "TXKERR1(1)", + OutTemp => TXKERR1_OUT(1), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR1(2), + GlitchData => TXKERR12_GlitchData, + OutSignalName => "TXKERR1(2)", + OutTemp => TXKERR1_OUT(2), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR1(3), + GlitchData => TXKERR13_GlitchData, + OutSignalName => "TXKERR1(3)", + OutTemp => TXKERR1_OUT(3), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP1(0), + GlitchData => TXRUNDISP10_GlitchData, + OutSignalName => "TXRUNDISP1(0)", + OutTemp => TXRUNDISP1_OUT(0), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP1(1), + GlitchData => TXRUNDISP11_GlitchData, + OutSignalName => "TXRUNDISP1(1)", + OutTemp => TXRUNDISP1_OUT(1), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP1(2), + GlitchData => TXRUNDISP12_GlitchData, + OutSignalName => "TXRUNDISP1(2)", + OutTemp => TXRUNDISP1_OUT(2), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP1(3), + GlitchData => TXRUNDISP13_GlitchData, + OutSignalName => "TXRUNDISP1(3)", + OutTemp => TXRUNDISP1_OUT(3), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXBUFSTATUS1(0), + GlitchData => TXBUFSTATUS10_GlitchData, + OutSignalName => "TXBUFSTATUS1(0)", + OutTemp => TXBUFSTATUS1_OUT(0), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXBUFSTATUS1(1), + GlitchData => TXBUFSTATUS11_GlitchData, + OutSignalName => "TXBUFSTATUS1(1)", + OutTemp => TXBUFSTATUS1_OUT(1), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCOMMADET0, + GlitchData => RXCOMMADET0_GlitchData, + OutSignalName => "RXCOMMADET0", + OutTemp => RXCOMMADET0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBYTEREALIGN0, + GlitchData => RXBYTEREALIGN0_GlitchData, + OutSignalName => "RXBYTEREALIGN0", + OutTemp => RXBYTEREALIGN0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBYTEISALIGNED0, + GlitchData => RXBYTEISALIGNED0_GlitchData, + OutSignalName => "RXBYTEISALIGNED0", + OutTemp => RXBYTEISALIGNED0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC0(0), + GlitchData => RXLOSSOFSYNC00_GlitchData, + OutSignalName => "RXLOSSOFSYNC0(0)", + OutTemp => RXLOSSOFSYNC0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC0(1), + GlitchData => RXLOSSOFSYNC01_GlitchData, + OutSignalName => "RXLOSSOFSYNC0(1)", + OutTemp => RXLOSSOFSYNC0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO0(0), + GlitchData => RXCHBONDO00_GlitchData, + OutSignalName => "RXCHBONDO0(0)", + OutTemp => RXCHBONDO0_OUT(0), + Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO0(1), + GlitchData => RXCHBONDO01_GlitchData, + OutSignalName => "RXCHBONDO0(1)", + OutTemp => RXCHBONDO0_OUT(1), + Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO0(2), + GlitchData => RXCHBONDO02_GlitchData, + OutSignalName => "RXCHBONDO0(2)", + OutTemp => RXCHBONDO0_OUT(2), + Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO0(3), + GlitchData => RXCHBONDO03_GlitchData, + OutSignalName => "RXCHBONDO0(3)", + OutTemp => RXCHBONDO0_OUT(3), + Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANBONDSEQ0, + GlitchData => RXCHANBONDSEQ0_GlitchData, + OutSignalName => "RXCHANBONDSEQ0", + OutTemp => RXCHANBONDSEQ0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANREALIGN0, + GlitchData => RXCHANREALIGN0_GlitchData, + OutSignalName => "RXCHANREALIGN0", + OutTemp => RXCHANREALIGN0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANISALIGNED0, + GlitchData => RXCHANISALIGNED0_GlitchData, + OutSignalName => "RXCHANISALIGNED0", + OutTemp => RXCHANISALIGNED0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS0(0), + GlitchData => RXBUFSTATUS00_GlitchData, + OutSignalName => "RXBUFSTATUS0(0)", + OutTemp => RXBUFSTATUS0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS0(1), + GlitchData => RXBUFSTATUS01_GlitchData, + OutSignalName => "RXBUFSTATUS0(1)", + OutTemp => RXBUFSTATUS0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS0(2), + GlitchData => RXBUFSTATUS02_GlitchData, + OutSignalName => "RXBUFSTATUS0(2)", + OutTemp => RXBUFSTATUS0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCOMMADET1, + GlitchData => RXCOMMADET1_GlitchData, + OutSignalName => "RXCOMMADET1", + OutTemp => RXCOMMADET1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBYTEREALIGN1, + GlitchData => RXBYTEREALIGN1_GlitchData, + OutSignalName => "RXBYTEREALIGN1", + OutTemp => RXBYTEREALIGN1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBYTEISALIGNED1, + GlitchData => RXBYTEISALIGNED1_GlitchData, + OutSignalName => "RXBYTEISALIGNED1", + OutTemp => RXBYTEISALIGNED1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC1(0), + GlitchData => RXLOSSOFSYNC10_GlitchData, + OutSignalName => "RXLOSSOFSYNC1(0)", + OutTemp => RXLOSSOFSYNC1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC1(1), + GlitchData => RXLOSSOFSYNC11_GlitchData, + OutSignalName => "RXLOSSOFSYNC1(1)", + OutTemp => RXLOSSOFSYNC1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO1(0), + GlitchData => RXCHBONDO10_GlitchData, + OutSignalName => "RXCHBONDO1(0)", + OutTemp => RXCHBONDO1_OUT(0), + Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO1(1), + GlitchData => RXCHBONDO11_GlitchData, + OutSignalName => "RXCHBONDO1(1)", + OutTemp => RXCHBONDO1_OUT(1), + Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO1(2), + GlitchData => RXCHBONDO12_GlitchData, + OutSignalName => "RXCHBONDO1(2)", + OutTemp => RXCHBONDO1_OUT(2), + Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO1(3), + GlitchData => RXCHBONDO13_GlitchData, + OutSignalName => "RXCHBONDO1(3)", + OutTemp => RXCHBONDO1_OUT(3), + Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANBONDSEQ1, + GlitchData => RXCHANBONDSEQ1_GlitchData, + OutSignalName => "RXCHANBONDSEQ1", + OutTemp => RXCHANBONDSEQ1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANREALIGN1, + GlitchData => RXCHANREALIGN1_GlitchData, + OutSignalName => "RXCHANREALIGN1", + OutTemp => RXCHANREALIGN1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANISALIGNED1, + GlitchData => RXCHANISALIGNED1_GlitchData, + OutSignalName => "RXCHANISALIGNED1", + OutTemp => RXCHANISALIGNED1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS1(0), + GlitchData => RXBUFSTATUS10_GlitchData, + OutSignalName => "RXBUFSTATUS1(0)", + OutTemp => RXBUFSTATUS1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS1(1), + GlitchData => RXBUFSTATUS11_GlitchData, + OutSignalName => "RXBUFSTATUS1(1)", + OutTemp => RXBUFSTATUS1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS1(2), + GlitchData => RXBUFSTATUS12_GlitchData, + OutSignalName => "RXBUFSTATUS1(2)", + OutTemp => RXBUFSTATUS1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PHYSTATUS0, + GlitchData => PHYSTATUS0_GlitchData, + OutSignalName => "PHYSTATUS0", + OutTemp => PHYSTATUS0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PHYSTATUS1, + GlitchData => PHYSTATUS1_GlitchData, + OutSignalName => "PHYSTATUS1", + OutTemp => PHYSTATUS1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS0(0), + GlitchData => RXSTATUS00_GlitchData, + OutSignalName => "RXSTATUS0(0)", + OutTemp => RXSTATUS0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS0(1), + GlitchData => RXSTATUS01_GlitchData, + OutSignalName => "RXSTATUS0(1)", + OutTemp => RXSTATUS0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS0(2), + GlitchData => RXSTATUS02_GlitchData, + OutSignalName => "RXSTATUS0(2)", + OutTemp => RXSTATUS0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT0(0), + GlitchData => RXCLKCORCNT00_GlitchData, + OutSignalName => "RXCLKCORCNT0(0)", + OutTemp => RXCLKCORCNT0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT0(1), + GlitchData => RXCLKCORCNT01_GlitchData, + OutSignalName => "RXCLKCORCNT0(1)", + OutTemp => RXCLKCORCNT0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT0(2), + GlitchData => RXCLKCORCNT02_GlitchData, + OutSignalName => "RXCLKCORCNT0(2)", + OutTemp => RXCLKCORCNT0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS1(0), + GlitchData => RXSTATUS10_GlitchData, + OutSignalName => "RXSTATUS1(0)", + OutTemp => RXSTATUS1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS1(1), + GlitchData => RXSTATUS11_GlitchData, + OutSignalName => "RXSTATUS1(1)", + OutTemp => RXSTATUS1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS1(2), + GlitchData => RXSTATUS12_GlitchData, + OutSignalName => "RXSTATUS1(2)", + OutTemp => RXSTATUS1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT1(0), + GlitchData => RXCLKCORCNT10_GlitchData, + OutSignalName => "RXCLKCORCNT1(0)", + OutTemp => RXCLKCORCNT1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT1(1), + GlitchData => RXCLKCORCNT11_GlitchData, + OutSignalName => "RXCLKCORCNT1(1)", + OutTemp => RXCLKCORCNT1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT1(2), + GlitchData => RXCLKCORCNT12_GlitchData, + OutSignalName => "RXCLKCORCNT1(2)", + OutTemp => RXCLKCORCNT1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXPRBSERR0, + GlitchData => RXPRBSERR0_GlitchData, + OutSignalName => "RXPRBSERR0", + OutTemp => RXPRBSERR0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXPRBSERR1, + GlitchData => RXPRBSERR1_GlitchData, + OutSignalName => "RXPRBSERR1", + OutTemp => RXPRBSERR1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(0), + GlitchData => DO0_GlitchData, + OutSignalName => "DO(0)", + OutTemp => DO_OUT(0), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(1), + GlitchData => DO1_GlitchData, + OutSignalName => "DO(1)", + OutTemp => DO_OUT(1), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(2), + GlitchData => DO2_GlitchData, + OutSignalName => "DO(2)", + OutTemp => DO_OUT(2), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(3), + GlitchData => DO3_GlitchData, + OutSignalName => "DO(3)", + OutTemp => DO_OUT(3), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(4), + GlitchData => DO4_GlitchData, + OutSignalName => "DO(4)", + OutTemp => DO_OUT(4), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(5), + GlitchData => DO5_GlitchData, + OutSignalName => "DO(5)", + OutTemp => DO_OUT(5), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(6), + GlitchData => DO6_GlitchData, + OutSignalName => "DO(6)", + OutTemp => DO_OUT(6), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(7), + GlitchData => DO7_GlitchData, + OutSignalName => "DO(7)", + OutTemp => DO_OUT(7), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(8), + GlitchData => DO8_GlitchData, + OutSignalName => "DO(8)", + OutTemp => DO_OUT(8), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(9), + GlitchData => DO9_GlitchData, + OutSignalName => "DO(9)", + OutTemp => DO_OUT(9), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(10), + GlitchData => DO10_GlitchData, + OutSignalName => "DO(10)", + OutTemp => DO_OUT(10), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(11), + GlitchData => DO11_GlitchData, + OutSignalName => "DO(11)", + OutTemp => DO_OUT(11), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(12), + GlitchData => DO12_GlitchData, + OutSignalName => "DO(12)", + OutTemp => DO_OUT(12), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(13), + GlitchData => DO13_GlitchData, + OutSignalName => "DO(13)", + OutTemp => DO_OUT(13), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(14), + GlitchData => DO14_GlitchData, + OutSignalName => "DO(14)", + OutTemp => DO_OUT(14), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(15), + GlitchData => DO15_GlitchData, + OutSignalName => "DO(15)", + OutTemp => DO_OUT(15), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DRDY, + GlitchData => DRDY_GlitchData, + OutSignalName => "DRDY", + OutTemp => DRDY_OUT, + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXOVERSAMPLEERR0, + GlitchData => RXOVERSAMPLEERR0_GlitchData, + OutSignalName => "RXOVERSAMPLEERR0", + OutTemp => RXOVERSAMPLEERR0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXOVERSAMPLEERR1, + GlitchData => RXOVERSAMPLEERR1_GlitchData, + OutSignalName => "RXOVERSAMPLEERR1", + OutTemp => RXOVERSAMPLEERR1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXGEARBOXREADY0, + GlitchData => TXGEARBOXREADY0_GlitchData, + OutSignalName => "TXGEARBOXREADY0", + OutTemp => TXGEARBOXREADY0_OUT, + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXHEADER0(0), + GlitchData => RXHEADER00_GlitchData, + OutSignalName => "RXHEADER0(0)", + OutTemp => RXHEADER0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXHEADER0(1), + GlitchData => RXHEADER01_GlitchData, + OutSignalName => "RXHEADER0(1)", + OutTemp => RXHEADER0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXHEADER0(2), + GlitchData => RXHEADER02_GlitchData, + OutSignalName => "RXHEADER0(2)", + OutTemp => RXHEADER0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXHEADERVALID0, + GlitchData => RXHEADERVALID0_GlitchData, + OutSignalName => "RXHEADERVALID0", + OutTemp => RXHEADERVALID0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATAVALID0, + GlitchData => RXDATAVALID0_GlitchData, + OutSignalName => "RXDATAVALID0", + OutTemp => RXDATAVALID0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTARTOFSEQ0, + GlitchData => RXSTARTOFSEQ0_GlitchData, + OutSignalName => "RXSTARTOFSEQ0", + OutTemp => RXSTARTOFSEQ0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXGEARBOXREADY1, + GlitchData => TXGEARBOXREADY1_GlitchData, + OutSignalName => "TXGEARBOXREADY1", + OutTemp => TXGEARBOXREADY1_OUT, + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXHEADER1(0), + GlitchData => RXHEADER10_GlitchData, + OutSignalName => "RXHEADER1(0)", + OutTemp => RXHEADER1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXHEADER1(1), + GlitchData => RXHEADER11_GlitchData, + OutSignalName => "RXHEADER1(1)", + OutTemp => RXHEADER1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXHEADER1(2), + GlitchData => RXHEADER12_GlitchData, + OutSignalName => "RXHEADER1(2)", + OutTemp => RXHEADER1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXHEADERVALID1, + GlitchData => RXHEADERVALID1_GlitchData, + OutSignalName => "RXHEADERVALID1", + OutTemp => RXHEADERVALID1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATAVALID1, + GlitchData => RXDATAVALID1_GlitchData, + OutSignalName => "RXDATAVALID1", + OutTemp => RXDATAVALID1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTARTOFSEQ1, + GlitchData => RXSTARTOFSEQ1_GlitchData, + OutSignalName => "RXSTARTOFSEQ1", + OutTemp => RXSTARTOFSEQ1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR0(0), + GlitchData => DFECLKDLYADJMONITOR00_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR0(0)", + OutTemp => DFECLKDLYADJMONITOR0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR0(1), + GlitchData => DFECLKDLYADJMONITOR01_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR0(1)", + OutTemp => DFECLKDLYADJMONITOR0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR0(2), + GlitchData => DFECLKDLYADJMONITOR02_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR0(2)", + OutTemp => DFECLKDLYADJMONITOR0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR0(3), + GlitchData => DFECLKDLYADJMONITOR03_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR0(3)", + OutTemp => DFECLKDLYADJMONITOR0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR0(4), + GlitchData => DFECLKDLYADJMONITOR04_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR0(4)", + OutTemp => DFECLKDLYADJMONITOR0_OUT(4), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR0(5), + GlitchData => DFECLKDLYADJMONITOR05_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR0(5)", + OutTemp => DFECLKDLYADJMONITOR0_OUT(5), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR0(0), + GlitchData => DFEEYEDACMONITOR00_GlitchData, + OutSignalName => "DFEEYEDACMONITOR0(0)", + OutTemp => DFEEYEDACMONITOR0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR0(1), + GlitchData => DFEEYEDACMONITOR01_GlitchData, + OutSignalName => "DFEEYEDACMONITOR0(1)", + OutTemp => DFEEYEDACMONITOR0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR0(2), + GlitchData => DFEEYEDACMONITOR02_GlitchData, + OutSignalName => "DFEEYEDACMONITOR0(2)", + OutTemp => DFEEYEDACMONITOR0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR0(3), + GlitchData => DFEEYEDACMONITOR03_GlitchData, + OutSignalName => "DFEEYEDACMONITOR0(3)", + OutTemp => DFEEYEDACMONITOR0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR0(4), + GlitchData => DFEEYEDACMONITOR04_GlitchData, + OutSignalName => "DFEEYEDACMONITOR0(4)", + OutTemp => DFEEYEDACMONITOR0_OUT(4), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR0(0), + GlitchData => DFETAP1MONITOR00_GlitchData, + OutSignalName => "DFETAP1MONITOR0(0)", + OutTemp => DFETAP1MONITOR0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR0(1), + GlitchData => DFETAP1MONITOR01_GlitchData, + OutSignalName => "DFETAP1MONITOR0(1)", + OutTemp => DFETAP1MONITOR0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR0(2), + GlitchData => DFETAP1MONITOR02_GlitchData, + OutSignalName => "DFETAP1MONITOR0(2)", + OutTemp => DFETAP1MONITOR0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR0(3), + GlitchData => DFETAP1MONITOR03_GlitchData, + OutSignalName => "DFETAP1MONITOR0(3)", + OutTemp => DFETAP1MONITOR0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR0(4), + GlitchData => DFETAP1MONITOR04_GlitchData, + OutSignalName => "DFETAP1MONITOR0(4)", + OutTemp => DFETAP1MONITOR0_OUT(4), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR0(0), + GlitchData => DFETAP2MONITOR00_GlitchData, + OutSignalName => "DFETAP2MONITOR0(0)", + OutTemp => DFETAP2MONITOR0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR0(1), + GlitchData => DFETAP2MONITOR01_GlitchData, + OutSignalName => "DFETAP2MONITOR0(1)", + OutTemp => DFETAP2MONITOR0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR0(2), + GlitchData => DFETAP2MONITOR02_GlitchData, + OutSignalName => "DFETAP2MONITOR0(2)", + OutTemp => DFETAP2MONITOR0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR0(3), + GlitchData => DFETAP2MONITOR03_GlitchData, + OutSignalName => "DFETAP2MONITOR0(3)", + OutTemp => DFETAP2MONITOR0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR0(4), + GlitchData => DFETAP2MONITOR04_GlitchData, + OutSignalName => "DFETAP2MONITOR0(4)", + OutTemp => DFETAP2MONITOR0_OUT(4), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP3MONITOR0(0), + GlitchData => DFETAP3MONITOR00_GlitchData, + OutSignalName => "DFETAP3MONITOR0(0)", + OutTemp => DFETAP3MONITOR0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP3MONITOR0(1), + GlitchData => DFETAP3MONITOR01_GlitchData, + OutSignalName => "DFETAP3MONITOR0(1)", + OutTemp => DFETAP3MONITOR0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP3MONITOR0(2), + GlitchData => DFETAP3MONITOR02_GlitchData, + OutSignalName => "DFETAP3MONITOR0(2)", + OutTemp => DFETAP3MONITOR0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP3MONITOR0(3), + GlitchData => DFETAP3MONITOR03_GlitchData, + OutSignalName => "DFETAP3MONITOR0(3)", + OutTemp => DFETAP3MONITOR0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP4MONITOR0(0), + GlitchData => DFETAP4MONITOR00_GlitchData, + OutSignalName => "DFETAP4MONITOR0(0)", + OutTemp => DFETAP4MONITOR0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP4MONITOR0(1), + GlitchData => DFETAP4MONITOR01_GlitchData, + OutSignalName => "DFETAP4MONITOR0(1)", + OutTemp => DFETAP4MONITOR0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP4MONITOR0(2), + GlitchData => DFETAP4MONITOR02_GlitchData, + OutSignalName => "DFETAP4MONITOR0(2)", + OutTemp => DFETAP4MONITOR0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP4MONITOR0(3), + GlitchData => DFETAP4MONITOR03_GlitchData, + OutSignalName => "DFETAP4MONITOR0(3)", + OutTemp => DFETAP4MONITOR0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR1(0), + GlitchData => DFECLKDLYADJMONITOR10_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR1(0)", + OutTemp => DFECLKDLYADJMONITOR1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR1(1), + GlitchData => DFECLKDLYADJMONITOR11_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR1(1)", + OutTemp => DFECLKDLYADJMONITOR1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR1(2), + GlitchData => DFECLKDLYADJMONITOR12_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR1(2)", + OutTemp => DFECLKDLYADJMONITOR1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR1(3), + GlitchData => DFECLKDLYADJMONITOR13_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR1(3)", + OutTemp => DFECLKDLYADJMONITOR1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR1(4), + GlitchData => DFECLKDLYADJMONITOR14_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR1(4)", + OutTemp => DFECLKDLYADJMONITOR1_OUT(4), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR1(5), + GlitchData => DFECLKDLYADJMONITOR15_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR1(5)", + OutTemp => DFECLKDLYADJMONITOR1_OUT(5), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR1(0), + GlitchData => DFEEYEDACMONITOR10_GlitchData, + OutSignalName => "DFEEYEDACMONITOR1(0)", + OutTemp => DFEEYEDACMONITOR1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR1(1), + GlitchData => DFEEYEDACMONITOR11_GlitchData, + OutSignalName => "DFEEYEDACMONITOR1(1)", + OutTemp => DFEEYEDACMONITOR1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR1(2), + GlitchData => DFEEYEDACMONITOR12_GlitchData, + OutSignalName => "DFEEYEDACMONITOR1(2)", + OutTemp => DFEEYEDACMONITOR1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR1(3), + GlitchData => DFEEYEDACMONITOR13_GlitchData, + OutSignalName => "DFEEYEDACMONITOR1(3)", + OutTemp => DFEEYEDACMONITOR1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR1(4), + GlitchData => DFEEYEDACMONITOR14_GlitchData, + OutSignalName => "DFEEYEDACMONITOR1(4)", + OutTemp => DFEEYEDACMONITOR1_OUT(4), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR1(0), + GlitchData => DFETAP1MONITOR10_GlitchData, + OutSignalName => "DFETAP1MONITOR1(0)", + OutTemp => DFETAP1MONITOR1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR1(1), + GlitchData => DFETAP1MONITOR11_GlitchData, + OutSignalName => "DFETAP1MONITOR1(1)", + OutTemp => DFETAP1MONITOR1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR1(2), + GlitchData => DFETAP1MONITOR12_GlitchData, + OutSignalName => "DFETAP1MONITOR1(2)", + OutTemp => DFETAP1MONITOR1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR1(3), + GlitchData => DFETAP1MONITOR13_GlitchData, + OutSignalName => "DFETAP1MONITOR1(3)", + OutTemp => DFETAP1MONITOR1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR1(4), + GlitchData => DFETAP1MONITOR14_GlitchData, + OutSignalName => "DFETAP1MONITOR1(4)", + OutTemp => DFETAP1MONITOR1_OUT(4), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR1(0), + GlitchData => DFETAP2MONITOR10_GlitchData, + OutSignalName => "DFETAP2MONITOR1(0)", + OutTemp => DFETAP2MONITOR1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR1(1), + GlitchData => DFETAP2MONITOR11_GlitchData, + OutSignalName => "DFETAP2MONITOR1(1)", + OutTemp => DFETAP2MONITOR1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR1(2), + GlitchData => DFETAP2MONITOR12_GlitchData, + OutSignalName => "DFETAP2MONITOR1(2)", + OutTemp => DFETAP2MONITOR1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR1(3), + GlitchData => DFETAP2MONITOR13_GlitchData, + OutSignalName => "DFETAP2MONITOR1(3)", + OutTemp => DFETAP2MONITOR1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR1(4), + GlitchData => DFETAP2MONITOR14_GlitchData, + OutSignalName => "DFETAP2MONITOR1(4)", + OutTemp => DFETAP2MONITOR1_OUT(4), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP3MONITOR1(0), + GlitchData => DFETAP3MONITOR10_GlitchData, + OutSignalName => "DFETAP3MONITOR1(0)", + OutTemp => DFETAP3MONITOR1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP3MONITOR1(1), + GlitchData => DFETAP3MONITOR11_GlitchData, + OutSignalName => "DFETAP3MONITOR1(1)", + OutTemp => DFETAP3MONITOR1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP3MONITOR1(2), + GlitchData => DFETAP3MONITOR12_GlitchData, + OutSignalName => "DFETAP3MONITOR1(2)", + OutTemp => DFETAP3MONITOR1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP3MONITOR1(3), + GlitchData => DFETAP3MONITOR13_GlitchData, + OutSignalName => "DFETAP3MONITOR1(3)", + OutTemp => DFETAP3MONITOR1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP4MONITOR1(0), + GlitchData => DFETAP4MONITOR10_GlitchData, + OutSignalName => "DFETAP4MONITOR1(0)", + OutTemp => DFETAP4MONITOR1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP4MONITOR1(1), + GlitchData => DFETAP4MONITOR11_GlitchData, + OutSignalName => "DFETAP4MONITOR1(1)", + OutTemp => DFETAP4MONITOR1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP4MONITOR1(2), + GlitchData => DFETAP4MONITOR12_GlitchData, + OutSignalName => "DFETAP4MONITOR1(2)", + OutTemp => DFETAP4MONITOR1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP4MONITOR1(3), + GlitchData => DFETAP4MONITOR13_GlitchData, + OutSignalName => "DFETAP4MONITOR1(3)", + OutTemp => DFETAP4MONITOR1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFESENSCAL0(0), + GlitchData => DFESENSCAL00_GlitchData, + OutSignalName => "DFESENSCAL0(0)", + OutTemp => DFESENSCAL0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFESENSCAL0(1), + GlitchData => DFESENSCAL01_GlitchData, + OutSignalName => "DFESENSCAL0(1)", + OutTemp => DFESENSCAL0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFESENSCAL0(2), + GlitchData => DFESENSCAL02_GlitchData, + OutSignalName => "DFESENSCAL0(2)", + OutTemp => DFESENSCAL0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFESENSCAL1(0), + GlitchData => DFESENSCAL10_GlitchData, + OutSignalName => "DFESENSCAL1(0)", + OutTemp => DFESENSCAL1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFESENSCAL1(1), + GlitchData => DFESENSCAL11_GlitchData, + OutSignalName => "DFESENSCAL1(1)", + OutTemp => DFESENSCAL1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFESENSCAL1(2), + GlitchData => DFESENSCAL12_GlitchData, + OutSignalName => "DFESENSCAL1(2)", + OutTemp => DFESENSCAL1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + + wait on + DFECLKDLYADJMONITOR0_out, + DFECLKDLYADJMONITOR1_out, + DFEEYEDACMONITOR0_out, + DFEEYEDACMONITOR1_out, + DFESENSCAL0_out, + DFESENSCAL1_out, + DFETAP1MONITOR0_out, + DFETAP1MONITOR1_out, + DFETAP2MONITOR0_out, + DFETAP2MONITOR1_out, + DFETAP3MONITOR0_out, + DFETAP3MONITOR1_out, + DFETAP4MONITOR0_out, + DFETAP4MONITOR1_out, + DO_out, + DRDY_out, + REFCLKOUT_out, + RXBUFSTATUS0_out, + RXBUFSTATUS1_out, + RXBYTEISALIGNED0_out, + RXBYTEISALIGNED1_out, + RXBYTEREALIGN0_out, + RXBYTEREALIGN1_out, + RXCHANBONDSEQ0_out, + RXCHANBONDSEQ1_out, + RXCHANISALIGNED0_out, + RXCHANISALIGNED1_out, + RXCHANREALIGN0_out, + RXCHANREALIGN1_out, + RXCHARISCOMMA0_out, + RXCHARISCOMMA1_out, + RXCHARISK0_out, + RXCHARISK1_out, + RXCHBONDO0_out, + RXCHBONDO1_out, + RXCLKCORCNT0_out, + RXCLKCORCNT1_out, + RXCOMMADET0_out, + RXCOMMADET1_out, + RXDATA0_out, + RXDATA1_out, + RXDATAVALID0_out, + RXDATAVALID1_out, + RXDISPERR0_out, + RXDISPERR1_out, + RXHEADER0_out, + RXHEADER1_out, + RXHEADERVALID0_out, + RXHEADERVALID1_out, + RXLOSSOFSYNC0_out, + RXLOSSOFSYNC1_out, + RXNOTINTABLE0_out, + RXNOTINTABLE1_out, + RXOVERSAMPLEERR0_out, + RXOVERSAMPLEERR1_out, + RXPRBSERR0_out, + RXPRBSERR1_out, + RXRUNDISP0_out, + RXRUNDISP1_out, + RXSTARTOFSEQ0_out, + RXSTARTOFSEQ1_out, + RXSTATUS0_out, + RXSTATUS1_out, + RXVALID0_out, + RXVALID1_out, + TXBUFSTATUS0_out, + TXBUFSTATUS1_out, + TXGEARBOXREADY0_out, + TXGEARBOXREADY1_out, + TXKERR0_out, + TXKERR1_out, + TXRUNDISP0_out, + TXRUNDISP1_out, + + CLKIN_ipd, + DADDR_ipd, + DCLK_ipd, + DEN_ipd, + DFECLKDLYADJ0_ipd, + DFECLKDLYADJ1_ipd, + DFETAP10_ipd, + DFETAP11_ipd, + DFETAP20_ipd, + DFETAP21_ipd, + DFETAP30_ipd, + DFETAP31_ipd, + DFETAP40_ipd, + DFETAP41_ipd, + DI_ipd, + DWE_ipd, + GTXRESET_ipd, + GTXTEST_ipd, + INTDATAWIDTH_ipd, + LOOPBACK0_ipd, + LOOPBACK1_ipd, + PLLLKDETEN_ipd, + PLLPOWERDOWN_ipd, + PRBSCNTRESET0_ipd, + PRBSCNTRESET1_ipd, + REFCLKPWRDNB_ipd, + RXBUFRESET0_ipd, + RXBUFRESET1_ipd, + RXCDRRESET0_ipd, + RXCDRRESET1_ipd, + RXCHBONDI0_ipd, + RXCHBONDI1_ipd, + RXCOMMADETUSE0_ipd, + RXCOMMADETUSE1_ipd, + RXDATAWIDTH0_ipd, + RXDATAWIDTH1_ipd, + RXDEC8B10BUSE0_ipd, + RXDEC8B10BUSE1_ipd, + RXENCHANSYNC0_ipd, + RXENCHANSYNC1_ipd, + RXENEQB0_ipd, + RXENEQB1_ipd, + RXENMCOMMAALIGN0_ipd, + RXENMCOMMAALIGN1_ipd, + RXENPCOMMAALIGN0_ipd, + RXENPCOMMAALIGN1_ipd, + RXENPMAPHASEALIGN0_ipd, + RXENPMAPHASEALIGN1_ipd, + RXENPRBSTST0_ipd, + RXENPRBSTST1_ipd, + RXENSAMPLEALIGN0_ipd, + RXENSAMPLEALIGN1_ipd, + RXEQMIX0_ipd, + RXEQMIX1_ipd, + RXEQPOLE0_ipd, + RXEQPOLE1_ipd, + RXGEARBOXSLIP0_ipd, + RXGEARBOXSLIP1_ipd, + RXN0_ipd, + RXN1_ipd, + RXP0_ipd, + RXP1_ipd, + RXPMASETPHASE0_ipd, + RXPMASETPHASE1_ipd, + RXPOLARITY0_ipd, + RXPOLARITY1_ipd, + RXPOWERDOWN0_ipd, + RXPOWERDOWN1_ipd, + RXRESET0_ipd, + RXRESET1_ipd, + RXSLIDE0_ipd, + RXSLIDE1_ipd, + RXUSRCLK0_ipd, + RXUSRCLK1_ipd, + RXUSRCLK20_ipd, + RXUSRCLK21_ipd, + TXBUFDIFFCTRL0_ipd, + TXBUFDIFFCTRL1_ipd, + TXBYPASS8B10B0_ipd, + TXBYPASS8B10B1_ipd, + TXCHARDISPMODE0_ipd, + TXCHARDISPMODE1_ipd, + TXCHARDISPVAL0_ipd, + TXCHARDISPVAL1_ipd, + TXCHARISK0_ipd, + TXCHARISK1_ipd, + TXCOMSTART0_ipd, + TXCOMSTART1_ipd, + TXCOMTYPE0_ipd, + TXCOMTYPE1_ipd, + TXDATA0_ipd, + TXDATA1_ipd, + TXDATAWIDTH0_ipd, + TXDATAWIDTH1_ipd, + TXDETECTRX0_ipd, + TXDETECTRX1_ipd, + TXDIFFCTRL0_ipd, + TXDIFFCTRL1_ipd, + TXELECIDLE0_ipd, + TXELECIDLE1_ipd, + TXENC8B10BUSE0_ipd, + TXENC8B10BUSE1_ipd, + TXENPMAPHASEALIGN0_ipd, + TXENPMAPHASEALIGN1_ipd, + TXENPRBSTST0_ipd, + TXENPRBSTST1_ipd, + TXHEADER0_ipd, + TXHEADER1_ipd, + TXINHIBIT0_ipd, + TXINHIBIT1_ipd, + TXPMASETPHASE0_ipd, + TXPMASETPHASE1_ipd, + TXPOLARITY0_ipd, + TXPOLARITY1_ipd, + TXPOWERDOWN0_ipd, + TXPOWERDOWN1_ipd, + TXPREEMPHASIS0_ipd, + TXPREEMPHASIS1_ipd, + TXRESET0_ipd, + TXRESET1_ipd, + TXSEQUENCE0_ipd, + TXSEQUENCE1_ipd, + TXSTARTSEQ0_ipd, + TXSTARTSEQ1_ipd, + TXUSRCLK0_ipd, + TXUSRCLK1_ipd, + TXUSRCLK20_ipd, + TXUSRCLK21_ipd; + + end process TIMING; + + PLLLKDET <= PLLLKDET_out; + RESETDONE0 <= RESETDONE0_out; + RESETDONE1 <= RESETDONE1_out; + RXELECIDLE0 <= RXELECIDLE0_out; + RXELECIDLE1 <= RXELECIDLE1_out; + RXRECCLK0 <= RXRECCLK0_out; + RXRECCLK1 <= RXRECCLK1_out; + TXN0 <= TXN0_out; + TXN1 <= TXN1_out; + TXOUTCLK0 <= TXOUTCLK0_out; + TXOUTCLK1 <= TXOUTCLK1_out; + TXP0 <= TXP0_out; + TXP1 <= TXP1_out; + +end GTX_DUAL_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex5fxt/SMODEL/Attic/jtagppc440.vhd,v 1.1 2006/09/18 21:16:09 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / JTAG Primitive for Virtex5 Power PC +-- /___/ /\ Filename : JTAGPPC440.vhd +-- \ \ / \ Timestamp : hu Aug 18 13:47:04 PDT 2005 +-- \___\/\___\ +-- +-- Revision: +-- 08/19/05 - Initial version. + +----- CELL JTAGPPC440 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +library secureip; +use secureip.all; + +entity JTAGPPC440 is + port ( + TCK : out std_ulogic; + TDIPPC : out std_ulogic; + TMS : out std_ulogic; + + TDOPPC : in std_ulogic + ); +end JTAGPPC440; + +architecture JTAGPPC440_v of JTAGPPC440 is + begin + TCK <= '1'; + TDIPPC <= '1'; + TMS <= '1'; +end JTAGPPC440_v; +------------------------------------------------------- +-- Copyright (c) 1995/2006 Xilinx Inc. +-- All Right Reserved. +------------------------------------------------------- +-- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : +-- / / +-- /___/ /\ Filename : PPC440.vhd +-- \ \ / \ Timestamp : Thu Apr 19 15:56:12 2007 + +-- \__ \/\__ \ +-- +-- Generated by : write_vhdl +-- Revision: +------------------------------------------------------- + +----- CELL PPC440 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library IEEE; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +library secureip; +use secureip.all; + +entity PPC440 is +generic ( + APU_CONTROL : bit_vector := X"02000"; + APU_UDI0 : bit_vector := X"000000"; + APU_UDI1 : bit_vector := X"000000"; + APU_UDI10 : bit_vector := X"000000"; + APU_UDI11 : bit_vector := X"000000"; + APU_UDI12 : bit_vector := X"000000"; + APU_UDI13 : bit_vector := X"000000"; + APU_UDI14 : bit_vector := X"000000"; + APU_UDI15 : bit_vector := X"000000"; + APU_UDI2 : bit_vector := X"000000"; + APU_UDI3 : bit_vector := X"000000"; + APU_UDI4 : bit_vector := X"000000"; + APU_UDI5 : bit_vector := X"000000"; + APU_UDI6 : bit_vector := X"000000"; + APU_UDI7 : bit_vector := X"000000"; + APU_UDI8 : bit_vector := X"000000"; + APU_UDI9 : bit_vector := X"000000"; + CLOCK_DELAY : boolean := FALSE; + DCR_AUTOLOCK_ENABLE : boolean := TRUE; + DMA0_CONTROL : bit_vector := X"00"; + DMA0_RXCHANNELCTRL : bit_vector := X"01010000"; + DMA0_RXIRQTIMER : bit_vector := X"3FF"; + DMA0_TXCHANNELCTRL : bit_vector := X"01010000"; + DMA0_TXIRQTIMER : bit_vector := X"3FF"; + DMA1_CONTROL : bit_vector := X"00"; + DMA1_RXCHANNELCTRL : bit_vector := X"01010000"; + DMA1_RXIRQTIMER : bit_vector := X"3FF"; + DMA1_TXCHANNELCTRL : bit_vector := X"01010000"; + DMA1_TXIRQTIMER : bit_vector := X"3FF"; + DMA2_CONTROL : bit_vector := X"00"; + DMA2_RXCHANNELCTRL : bit_vector := X"01010000"; + DMA2_RXIRQTIMER : bit_vector := X"3FF"; + DMA2_TXCHANNELCTRL : bit_vector := X"01010000"; + DMA2_TXIRQTIMER : bit_vector := X"3FF"; + DMA3_CONTROL : bit_vector := X"00"; + DMA3_RXCHANNELCTRL : bit_vector := X"01010000"; + DMA3_RXIRQTIMER : bit_vector := X"3FF"; + DMA3_TXCHANNELCTRL : bit_vector := X"01010000"; + DMA3_TXIRQTIMER : bit_vector := X"3FF"; + INTERCONNECT_IMASK : bit_vector := X"FFFFFFFF"; + INTERCONNECT_TMPL_SEL : bit_vector := X"3FFFFFFF"; + MI_ARBCONFIG : bit_vector := X"00432010"; + MI_BANKCONFLICT_MASK : bit_vector := X"00000000"; + MI_CONTROL : bit_vector := X"0000008F"; + MI_ROWCONFLICT_MASK : bit_vector := X"00000000"; + PPCDM_ASYNCMODE : boolean := FALSE; + PPCDS_ASYNCMODE : boolean := FALSE; + PPCM_ARBCONFIG : bit_vector := X"00432010"; + PPCM_CONTROL : bit_vector := X"8000009F"; + PPCM_COUNTER : bit_vector := X"00000500"; + PPCS0_ADDRMAP_TMPL0 : bit_vector := X"FFFFFFFF"; + PPCS0_ADDRMAP_TMPL1 : bit_vector := X"FFFFFFFF"; + PPCS0_ADDRMAP_TMPL2 : bit_vector := X"FFFFFFFF"; + PPCS0_ADDRMAP_TMPL3 : bit_vector := X"FFFFFFFF"; + PPCS0_CONTROL : bit_vector := X"8033336C"; + PPCS0_WIDTH_128N64 : boolean := TRUE; + PPCS1_ADDRMAP_TMPL0 : bit_vector := X"FFFFFFFF"; + PPCS1_ADDRMAP_TMPL1 : bit_vector := X"FFFFFFFF"; + PPCS1_ADDRMAP_TMPL2 : bit_vector := X"FFFFFFFF"; + PPCS1_ADDRMAP_TMPL3 : bit_vector := X"FFFFFFFF"; + PPCS1_CONTROL : bit_vector := X"8033336C"; + PPCS1_WIDTH_128N64 : boolean := TRUE; + XBAR_ADDRMAP_TMPL0 : bit_vector := X"FFFF0000"; + XBAR_ADDRMAP_TMPL1 : bit_vector := X"00000000"; + XBAR_ADDRMAP_TMPL2 : bit_vector := X"00000000"; + XBAR_ADDRMAP_TMPL3 : bit_vector := X"00000000" + + + + + ); + +port ( + APUFCMDECFPUOP : out std_ulogic; + APUFCMDECLDSTXFERSIZE : out std_logic_vector(0 to 2); + APUFCMDECLOAD : out std_ulogic; + APUFCMDECNONAUTON : out std_ulogic; + APUFCMDECSTORE : out std_ulogic; + APUFCMDECUDI : out std_logic_vector(0 to 3); + APUFCMDECUDIVALID : out std_ulogic; + APUFCMENDIAN : out std_ulogic; + APUFCMFLUSH : out std_ulogic; + APUFCMINSTRUCTION : out std_logic_vector(0 to 31); + APUFCMINSTRVALID : out std_ulogic; + APUFCMLOADBYTEADDR : out std_logic_vector(0 to 3); + APUFCMLOADDATA : out std_logic_vector(0 to 127); + APUFCMLOADDVALID : out std_ulogic; + APUFCMMSRFE0 : out std_ulogic; + APUFCMMSRFE1 : out std_ulogic; + APUFCMNEXTINSTRREADY : out std_ulogic; + APUFCMOPERANDVALID : out std_ulogic; + APUFCMRADATA : out std_logic_vector(0 to 31); + APUFCMRBDATA : out std_logic_vector(0 to 31); + APUFCMWRITEBACKOK : out std_ulogic; + C440CPMCORESLEEPREQ : out std_ulogic; + C440CPMDECIRPTREQ : out std_ulogic; + C440CPMFITIRPTREQ : out std_ulogic; + C440CPMMSRCE : out std_ulogic; + C440CPMMSREE : out std_ulogic; + C440CPMTIMERRESETREQ : out std_ulogic; + C440CPMWDIRPTREQ : out std_ulogic; + C440DBGSYSTEMCONTROL : out std_logic_vector(0 to 7); + C440JTGTDO : out std_ulogic; + C440JTGTDOEN : out std_ulogic; + C440MACHINECHECK : out std_ulogic; + C440RSTCHIPRESETREQ : out std_ulogic; + C440RSTCORERESETREQ : out std_ulogic; + C440RSTSYSTEMRESETREQ : out std_ulogic; + C440TRCBRANCHSTATUS : out std_logic_vector(0 to 2); + C440TRCCYCLE : out std_ulogic; + C440TRCEXECUTIONSTATUS : out std_logic_vector(0 to 4); + C440TRCTRACESTATUS : out std_logic_vector(0 to 6); + C440TRCTRIGGEREVENTOUT : out std_ulogic; + C440TRCTRIGGEREVENTTYPE : out std_logic_vector(0 to 13); + DMA0LLRSTENGINEACK : out std_ulogic; + DMA0LLRXDSTRDYN : out std_ulogic; + DMA0LLTXD : out std_logic_vector(0 to 31); + DMA0LLTXEOFN : out std_ulogic; + DMA0LLTXEOPN : out std_ulogic; + DMA0LLTXREM : out std_logic_vector(0 to 3); + DMA0LLTXSOFN : out std_ulogic; + DMA0LLTXSOPN : out std_ulogic; + DMA0LLTXSRCRDYN : out std_ulogic; + DMA0RXIRQ : out std_ulogic; + DMA0TXIRQ : out std_ulogic; + DMA1LLRSTENGINEACK : out std_ulogic; + DMA1LLRXDSTRDYN : out std_ulogic; + DMA1LLTXD : out std_logic_vector(0 to 31); + DMA1LLTXEOFN : out std_ulogic; + DMA1LLTXEOPN : out std_ulogic; + DMA1LLTXREM : out std_logic_vector(0 to 3); + DMA1LLTXSOFN : out std_ulogic; + DMA1LLTXSOPN : out std_ulogic; + DMA1LLTXSRCRDYN : out std_ulogic; + DMA1RXIRQ : out std_ulogic; + DMA1TXIRQ : out std_ulogic; + DMA2LLRSTENGINEACK : out std_ulogic; + DMA2LLRXDSTRDYN : out std_ulogic; + DMA2LLTXD : out std_logic_vector(0 to 31); + DMA2LLTXEOFN : out std_ulogic; + DMA2LLTXEOPN : out std_ulogic; + DMA2LLTXREM : out std_logic_vector(0 to 3); + DMA2LLTXSOFN : out std_ulogic; + DMA2LLTXSOPN : out std_ulogic; + DMA2LLTXSRCRDYN : out std_ulogic; + DMA2RXIRQ : out std_ulogic; + DMA2TXIRQ : out std_ulogic; + DMA3LLRSTENGINEACK : out std_ulogic; + DMA3LLRXDSTRDYN : out std_ulogic; + DMA3LLTXD : out std_logic_vector(0 to 31); + DMA3LLTXEOFN : out std_ulogic; + DMA3LLTXEOPN : out std_ulogic; + DMA3LLTXREM : out std_logic_vector(0 to 3); + DMA3LLTXSOFN : out std_ulogic; + DMA3LLTXSOPN : out std_ulogic; + DMA3LLTXSRCRDYN : out std_ulogic; + DMA3RXIRQ : out std_ulogic; + DMA3TXIRQ : out std_ulogic; + MIMCADDRESS : out std_logic_vector(0 to 35); + MIMCADDRESSVALID : out std_ulogic; + MIMCBANKCONFLICT : out std_ulogic; + MIMCBYTEENABLE : out std_logic_vector(0 to 15); + MIMCREADNOTWRITE : out std_ulogic; + MIMCROWCONFLICT : out std_ulogic; + MIMCWRITEDATA : out std_logic_vector(0 to 127); + MIMCWRITEDATAVALID : out std_ulogic; + PPCCPMINTERCONNECTBUSY : out std_ulogic; + PPCDMDCRABUS : out std_logic_vector(0 to 9); + PPCDMDCRDBUSOUT : out std_logic_vector(0 to 31); + PPCDMDCRREAD : out std_ulogic; + PPCDMDCRUABUS : out std_logic_vector(20 to 21); + PPCDMDCRWRITE : out std_ulogic; + PPCDSDCRACK : out std_ulogic; + PPCDSDCRDBUSIN : out std_logic_vector(0 to 31); + PPCDSDCRTIMEOUTWAIT : out std_ulogic; + PPCEICINTERCONNECTIRQ : out std_ulogic; + PPCMPLBABORT : out std_ulogic; + PPCMPLBABUS : out std_logic_vector(0 to 31); + PPCMPLBBE : out std_logic_vector(0 to 15); + PPCMPLBBUSLOCK : out std_ulogic; + PPCMPLBLOCKERR : out std_ulogic; + PPCMPLBPRIORITY : out std_logic_vector(0 to 1); + PPCMPLBRDBURST : out std_ulogic; + PPCMPLBREQUEST : out std_ulogic; + PPCMPLBRNW : out std_ulogic; + PPCMPLBSIZE : out std_logic_vector(0 to 3); + PPCMPLBTATTRIBUTE : out std_logic_vector(0 to 15); + PPCMPLBTYPE : out std_logic_vector(0 to 2); + PPCMPLBUABUS : out std_logic_vector(28 to 31); + PPCMPLBWRBURST : out std_ulogic; + PPCMPLBWRDBUS : out std_logic_vector(0 to 127); + PPCS0PLBADDRACK : out std_ulogic; + PPCS0PLBMBUSY : out std_logic_vector(0 to 3); + PPCS0PLBMIRQ : out std_logic_vector(0 to 3); + PPCS0PLBMRDERR : out std_logic_vector(0 to 3); + PPCS0PLBMWRERR : out std_logic_vector(0 to 3); + PPCS0PLBRDBTERM : out std_ulogic; + PPCS0PLBRDCOMP : out std_ulogic; + PPCS0PLBRDDACK : out std_ulogic; + PPCS0PLBRDDBUS : out std_logic_vector(0 to 127); + PPCS0PLBRDWDADDR : out std_logic_vector(0 to 3); + PPCS0PLBREARBITRATE : out std_ulogic; + PPCS0PLBSSIZE : out std_logic_vector(0 to 1); + PPCS0PLBWAIT : out std_ulogic; + PPCS0PLBWRBTERM : out std_ulogic; + PPCS0PLBWRCOMP : out std_ulogic; + PPCS0PLBWRDACK : out std_ulogic; + PPCS1PLBADDRACK : out std_ulogic; + PPCS1PLBMBUSY : out std_logic_vector(0 to 3); + PPCS1PLBMIRQ : out std_logic_vector(0 to 3); + PPCS1PLBMRDERR : out std_logic_vector(0 to 3); + PPCS1PLBMWRERR : out std_logic_vector(0 to 3); + PPCS1PLBRDBTERM : out std_ulogic; + PPCS1PLBRDCOMP : out std_ulogic; + PPCS1PLBRDDACK : out std_ulogic; + PPCS1PLBRDDBUS : out std_logic_vector(0 to 127); + PPCS1PLBRDWDADDR : out std_logic_vector(0 to 3); + PPCS1PLBREARBITRATE : out std_ulogic; + PPCS1PLBSSIZE : out std_logic_vector(0 to 1); + PPCS1PLBWAIT : out std_ulogic; + PPCS1PLBWRBTERM : out std_ulogic; + PPCS1PLBWRCOMP : out std_ulogic; + PPCS1PLBWRDACK : out std_ulogic; + + CPMC440CLK : in std_ulogic; + CPMC440CLKEN : in std_ulogic; + CPMC440CORECLOCKINACTIVE : in std_ulogic; + CPMC440TIMERCLOCK : in std_ulogic; + CPMDCRCLK : in std_ulogic; + CPMDMA0LLCLK : in std_ulogic; + CPMDMA1LLCLK : in std_ulogic; + CPMDMA2LLCLK : in std_ulogic; + CPMDMA3LLCLK : in std_ulogic; + CPMFCMCLK : in std_ulogic; + CPMINTERCONNECTCLK : in std_ulogic; + CPMINTERCONNECTCLKEN : in std_ulogic; + CPMINTERCONNECTCLKNTO1 : in std_ulogic; + CPMMCCLK : in std_ulogic; + CPMPPCMPLBCLK : in std_ulogic; + CPMPPCS0PLBCLK : in std_ulogic; + CPMPPCS1PLBCLK : in std_ulogic; + DBGC440DEBUGHALT : in std_ulogic; + DBGC440SYSTEMSTATUS : in std_logic_vector(0 to 4); + DBGC440UNCONDDEBUGEVENT : in std_ulogic; + DCRPPCDMACK : in std_ulogic; + DCRPPCDMDBUSIN : in std_logic_vector(0 to 31); + DCRPPCDMTIMEOUTWAIT : in std_ulogic; + DCRPPCDSABUS : in std_logic_vector(0 to 9); + DCRPPCDSDBUSOUT : in std_logic_vector(0 to 31); + DCRPPCDSREAD : in std_ulogic; + DCRPPCDSWRITE : in std_ulogic; + EICC440CRITIRQ : in std_ulogic; + EICC440EXTIRQ : in std_ulogic; + FCMAPUCONFIRMINSTR : in std_ulogic; + FCMAPUCR : in std_logic_vector(0 to 3); + FCMAPUDONE : in std_ulogic; + FCMAPUEXCEPTION : in std_ulogic; + FCMAPUFPSCRFEX : in std_ulogic; + FCMAPURESULT : in std_logic_vector(0 to 31); + FCMAPURESULTVALID : in std_ulogic; + FCMAPUSLEEPNOTREADY : in std_ulogic; + FCMAPUSTOREDATA : in std_logic_vector(0 to 127); + JTGC440TCK : in std_ulogic; + JTGC440TDI : in std_ulogic; + JTGC440TMS : in std_ulogic; + JTGC440TRSTNEG : in std_ulogic; + LLDMA0RSTENGINEREQ : in std_ulogic; + LLDMA0RXD : in std_logic_vector(0 to 31); + LLDMA0RXEOFN : in std_ulogic; + LLDMA0RXEOPN : in std_ulogic; + LLDMA0RXREM : in std_logic_vector(0 to 3); + LLDMA0RXSOFN : in std_ulogic; + LLDMA0RXSOPN : in std_ulogic; + LLDMA0RXSRCRDYN : in std_ulogic; + LLDMA0TXDSTRDYN : in std_ulogic; + LLDMA1RSTENGINEREQ : in std_ulogic; + LLDMA1RXD : in std_logic_vector(0 to 31); + LLDMA1RXEOFN : in std_ulogic; + LLDMA1RXEOPN : in std_ulogic; + LLDMA1RXREM : in std_logic_vector(0 to 3); + LLDMA1RXSOFN : in std_ulogic; + LLDMA1RXSOPN : in std_ulogic; + LLDMA1RXSRCRDYN : in std_ulogic; + LLDMA1TXDSTRDYN : in std_ulogic; + LLDMA2RSTENGINEREQ : in std_ulogic; + LLDMA2RXD : in std_logic_vector(0 to 31); + LLDMA2RXEOFN : in std_ulogic; + LLDMA2RXEOPN : in std_ulogic; + LLDMA2RXREM : in std_logic_vector(0 to 3); + LLDMA2RXSOFN : in std_ulogic; + LLDMA2RXSOPN : in std_ulogic; + LLDMA2RXSRCRDYN : in std_ulogic; + LLDMA2TXDSTRDYN : in std_ulogic; + LLDMA3RSTENGINEREQ : in std_ulogic; + LLDMA3RXD : in std_logic_vector(0 to 31); + LLDMA3RXEOFN : in std_ulogic; + LLDMA3RXEOPN : in std_ulogic; + LLDMA3RXREM : in std_logic_vector(0 to 3); + LLDMA3RXSOFN : in std_ulogic; + LLDMA3RXSOPN : in std_ulogic; + LLDMA3RXSRCRDYN : in std_ulogic; + LLDMA3TXDSTRDYN : in std_ulogic; + MCMIADDRREADYTOACCEPT : in std_ulogic; + MCMIREADDATA : in std_logic_vector(0 to 127); + MCMIREADDATAERR : in std_ulogic; + MCMIREADDATAVALID : in std_ulogic; + PLBPPCMADDRACK : in std_ulogic; + PLBPPCMMBUSY : in std_ulogic; + PLBPPCMMIRQ : in std_ulogic; + PLBPPCMMRDERR : in std_ulogic; + PLBPPCMMWRERR : in std_ulogic; + PLBPPCMRDBTERM : in std_ulogic; + PLBPPCMRDDACK : in std_ulogic; + PLBPPCMRDDBUS : in std_logic_vector(0 to 127); + PLBPPCMRDPENDPRI : in std_logic_vector(0 to 1); + PLBPPCMRDPENDREQ : in std_ulogic; + PLBPPCMRDWDADDR : in std_logic_vector(0 to 3); + PLBPPCMREARBITRATE : in std_ulogic; + PLBPPCMREQPRI : in std_logic_vector(0 to 1); + PLBPPCMSSIZE : in std_logic_vector(0 to 1); + PLBPPCMTIMEOUT : in std_ulogic; + PLBPPCMWRBTERM : in std_ulogic; + PLBPPCMWRDACK : in std_ulogic; + PLBPPCMWRPENDPRI : in std_logic_vector(0 to 1); + PLBPPCMWRPENDREQ : in std_ulogic; + PLBPPCS0ABORT : in std_ulogic; + PLBPPCS0ABUS : in std_logic_vector(0 to 31); + PLBPPCS0BE : in std_logic_vector(0 to 15); + PLBPPCS0BUSLOCK : in std_ulogic; + PLBPPCS0LOCKERR : in std_ulogic; + PLBPPCS0MASTERID : in std_logic_vector(0 to 1); + PLBPPCS0MSIZE : in std_logic_vector(0 to 1); + PLBPPCS0PAVALID : in std_ulogic; + PLBPPCS0RDBURST : in std_ulogic; + PLBPPCS0RDPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS0RDPENDREQ : in std_ulogic; + PLBPPCS0RDPRIM : in std_ulogic; + PLBPPCS0REQPRI : in std_logic_vector(0 to 1); + PLBPPCS0RNW : in std_ulogic; + PLBPPCS0SAVALID : in std_ulogic; + PLBPPCS0SIZE : in std_logic_vector(0 to 3); + PLBPPCS0TATTRIBUTE : in std_logic_vector(0 to 15); + PLBPPCS0TYPE : in std_logic_vector(0 to 2); + PLBPPCS0UABUS : in std_logic_vector(28 to 31); + PLBPPCS0WRBURST : in std_ulogic; + PLBPPCS0WRDBUS : in std_logic_vector(0 to 127); + PLBPPCS0WRPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS0WRPENDREQ : in std_ulogic; + PLBPPCS0WRPRIM : in std_ulogic; + PLBPPCS1ABORT : in std_ulogic; + PLBPPCS1ABUS : in std_logic_vector(0 to 31); + PLBPPCS1BE : in std_logic_vector(0 to 15); + PLBPPCS1BUSLOCK : in std_ulogic; + PLBPPCS1LOCKERR : in std_ulogic; + PLBPPCS1MASTERID : in std_logic_vector(0 to 1); + PLBPPCS1MSIZE : in std_logic_vector(0 to 1); + PLBPPCS1PAVALID : in std_ulogic; + PLBPPCS1RDBURST : in std_ulogic; + PLBPPCS1RDPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS1RDPENDREQ : in std_ulogic; + PLBPPCS1RDPRIM : in std_ulogic; + PLBPPCS1REQPRI : in std_logic_vector(0 to 1); + PLBPPCS1RNW : in std_ulogic; + PLBPPCS1SAVALID : in std_ulogic; + PLBPPCS1SIZE : in std_logic_vector(0 to 3); + PLBPPCS1TATTRIBUTE : in std_logic_vector(0 to 15); + PLBPPCS1TYPE : in std_logic_vector(0 to 2); + PLBPPCS1UABUS : in std_logic_vector(28 to 31); + PLBPPCS1WRBURST : in std_ulogic; + PLBPPCS1WRDBUS : in std_logic_vector(0 to 127); + PLBPPCS1WRPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS1WRPENDREQ : in std_ulogic; + PLBPPCS1WRPRIM : in std_ulogic; + RSTC440RESETCHIP : in std_ulogic; + RSTC440RESETCORE : in std_ulogic; + RSTC440RESETSYSTEM : in std_ulogic; + TIEC440DCURDLDCACHEPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCURDNONCACHEPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCURDTOUCHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCURDURGENTPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCUWRFLUSHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCUWRSTOREPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCUWRURGENTPLBPRIO : in std_logic_vector(0 to 1); + TIEC440ENDIANRESET : in std_ulogic; + TIEC440ERPNRESET : in std_logic_vector(0 to 3); + TIEC440ICURDFETCHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440ICURDSPECPLBPRIO : in std_logic_vector(0 to 1); + TIEC440ICURDTOUCHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440PIR : in std_logic_vector(28 to 31); + TIEC440PVR : in std_logic_vector(28 to 31); + TIEC440USERRESET : in std_logic_vector(0 to 3); + TIEDCRBASEADDR : in std_logic_vector(0 to 1); + TRCC440TRACEDISABLE : in std_ulogic; + TRCC440TRIGGEREVENTIN : in std_ulogic + ); +end PPC440; + +architecture PPC440_V of PPC440 is + + component PPC440_SWIFT + port ( + APUFCMDECFPUOP : out std_ulogic; + APUFCMDECLDSTXFERSIZE : out std_logic_vector(0 to 2); + APUFCMDECLOAD : out std_ulogic; + APUFCMDECNONAUTON : out std_ulogic; + APUFCMDECSTORE : out std_ulogic; + APUFCMDECUDI : out std_logic_vector(0 to 3); + APUFCMDECUDIVALID : out std_ulogic; + APUFCMENDIAN : out std_ulogic; + APUFCMFLUSH : out std_ulogic; + APUFCMINSTRUCTION : out std_logic_vector(0 to 31); + APUFCMINSTRVALID : out std_ulogic; + APUFCMLOADBYTEADDR : out std_logic_vector(0 to 3); + APUFCMLOADDATA : out std_logic_vector(0 to 127); + APUFCMLOADDVALID : out std_ulogic; + APUFCMMSRFE0 : out std_ulogic; + APUFCMMSRFE1 : out std_ulogic; + APUFCMNEXTINSTRREADY : out std_ulogic; + APUFCMOPERANDVALID : out std_ulogic; + APUFCMRADATA : out std_logic_vector(0 to 31); + APUFCMRBDATA : out std_logic_vector(0 to 31); + APUFCMWRITEBACKOK : out std_ulogic; + C440CPMCORESLEEPREQ : out std_ulogic; + C440CPMDECIRPTREQ : out std_ulogic; + C440CPMFITIRPTREQ : out std_ulogic; + C440CPMMSRCE : out std_ulogic; + C440CPMMSREE : out std_ulogic; + C440CPMTIMERRESETREQ : out std_ulogic; + C440CPMWDIRPTREQ : out std_ulogic; + C440DBGSYSTEMCONTROL : out std_logic_vector(0 to 7); + C440JTGTDO : out std_ulogic; + C440JTGTDOEN : out std_ulogic; + C440MACHINECHECK : out std_ulogic; + C440RSTCHIPRESETREQ : out std_ulogic; + C440RSTCORERESETREQ : out std_ulogic; + C440RSTSYSTEMRESETREQ : out std_ulogic; + C440TRCBRANCHSTATUS : out std_logic_vector(0 to 2); + C440TRCCYCLE : out std_ulogic; + C440TRCEXECUTIONSTATUS : out std_logic_vector(0 to 4); + C440TRCTRACESTATUS : out std_logic_vector(0 to 6); + C440TRCTRIGGEREVENTOUT : out std_ulogic; + C440TRCTRIGGEREVENTTYPE : out std_logic_vector(0 to 13); + DMA0LLRSTENGINEACK : out std_ulogic; + DMA0LLRXDSTRDYN : out std_ulogic; + DMA0LLTXD : out std_logic_vector(0 to 31); + DMA0LLTXEOFN : out std_ulogic; + DMA0LLTXEOPN : out std_ulogic; + DMA0LLTXREM : out std_logic_vector(0 to 3); + DMA0LLTXSOFN : out std_ulogic; + DMA0LLTXSOPN : out std_ulogic; + DMA0LLTXSRCRDYN : out std_ulogic; + DMA0RXIRQ : out std_ulogic; + DMA0TXIRQ : out std_ulogic; + DMA1LLRSTENGINEACK : out std_ulogic; + DMA1LLRXDSTRDYN : out std_ulogic; + DMA1LLTXD : out std_logic_vector(0 to 31); + DMA1LLTXEOFN : out std_ulogic; + DMA1LLTXEOPN : out std_ulogic; + DMA1LLTXREM : out std_logic_vector(0 to 3); + DMA1LLTXSOFN : out std_ulogic; + DMA1LLTXSOPN : out std_ulogic; + DMA1LLTXSRCRDYN : out std_ulogic; + DMA1RXIRQ : out std_ulogic; + DMA1TXIRQ : out std_ulogic; + DMA2LLRSTENGINEACK : out std_ulogic; + DMA2LLRXDSTRDYN : out std_ulogic; + DMA2LLTXD : out std_logic_vector(0 to 31); + DMA2LLTXEOFN : out std_ulogic; + DMA2LLTXEOPN : out std_ulogic; + DMA2LLTXREM : out std_logic_vector(0 to 3); + DMA2LLTXSOFN : out std_ulogic; + DMA2LLTXSOPN : out std_ulogic; + DMA2LLTXSRCRDYN : out std_ulogic; + DMA2RXIRQ : out std_ulogic; + DMA2TXIRQ : out std_ulogic; + DMA3LLRSTENGINEACK : out std_ulogic; + DMA3LLRXDSTRDYN : out std_ulogic; + DMA3LLTXD : out std_logic_vector(0 to 31); + DMA3LLTXEOFN : out std_ulogic; + DMA3LLTXEOPN : out std_ulogic; + DMA3LLTXREM : out std_logic_vector(0 to 3); + DMA3LLTXSOFN : out std_ulogic; + DMA3LLTXSOPN : out std_ulogic; + DMA3LLTXSRCRDYN : out std_ulogic; + DMA3RXIRQ : out std_ulogic; + DMA3TXIRQ : out std_ulogic; + MIMCADDRESS : out std_logic_vector(0 to 35); + MIMCADDRESSVALID : out std_ulogic; + MIMCBANKCONFLICT : out std_ulogic; + MIMCBYTEENABLE : out std_logic_vector(0 to 15); + MIMCREADNOTWRITE : out std_ulogic; + MIMCROWCONFLICT : out std_ulogic; + MIMCWRITEDATA : out std_logic_vector(0 to 127); + MIMCWRITEDATAVALID : out std_ulogic; + PPCCPMINTERCONNECTBUSY : out std_ulogic; + PPCDMDCRABUS : out std_logic_vector(0 to 9); + PPCDMDCRDBUSOUT : out std_logic_vector(0 to 31); + PPCDMDCRREAD : out std_ulogic; + PPCDMDCRUABUS : out std_logic_vector(20 to 21); + PPCDMDCRWRITE : out std_ulogic; + PPCDSDCRACK : out std_ulogic; + PPCDSDCRDBUSIN : out std_logic_vector(0 to 31); + PPCDSDCRTIMEOUTWAIT : out std_ulogic; + PPCEICINTERCONNECTIRQ : out std_ulogic; + PPCMPLBABORT : out std_ulogic; + PPCMPLBABUS : out std_logic_vector(0 to 31); + PPCMPLBBE : out std_logic_vector(0 to 15); + PPCMPLBBUSLOCK : out std_ulogic; + PPCMPLBLOCKERR : out std_ulogic; + PPCMPLBPRIORITY : out std_logic_vector(0 to 1); + PPCMPLBRDBURST : out std_ulogic; + PPCMPLBREQUEST : out std_ulogic; + PPCMPLBRNW : out std_ulogic; + PPCMPLBSIZE : out std_logic_vector(0 to 3); + PPCMPLBTATTRIBUTE : out std_logic_vector(0 to 15); + PPCMPLBTYPE : out std_logic_vector(0 to 2); + PPCMPLBUABUS : out std_logic_vector(28 to 31); + PPCMPLBWRBURST : out std_ulogic; + PPCMPLBWRDBUS : out std_logic_vector(0 to 127); + PPCS0PLBADDRACK : out std_ulogic; + PPCS0PLBMBUSY : out std_logic_vector(0 to 3); + PPCS0PLBMIRQ : out std_logic_vector(0 to 3); + PPCS0PLBMRDERR : out std_logic_vector(0 to 3); + PPCS0PLBMWRERR : out std_logic_vector(0 to 3); + PPCS0PLBRDBTERM : out std_ulogic; + PPCS0PLBRDCOMP : out std_ulogic; + PPCS0PLBRDDACK : out std_ulogic; + PPCS0PLBRDDBUS : out std_logic_vector(0 to 127); + PPCS0PLBRDWDADDR : out std_logic_vector(0 to 3); + PPCS0PLBREARBITRATE : out std_ulogic; + PPCS0PLBSSIZE : out std_logic_vector(0 to 1); + PPCS0PLBWAIT : out std_ulogic; + PPCS0PLBWRBTERM : out std_ulogic; + PPCS0PLBWRCOMP : out std_ulogic; + PPCS0PLBWRDACK : out std_ulogic; + PPCS1PLBADDRACK : out std_ulogic; + PPCS1PLBMBUSY : out std_logic_vector(0 to 3); + PPCS1PLBMIRQ : out std_logic_vector(0 to 3); + PPCS1PLBMRDERR : out std_logic_vector(0 to 3); + PPCS1PLBMWRERR : out std_logic_vector(0 to 3); + PPCS1PLBRDBTERM : out std_ulogic; + PPCS1PLBRDCOMP : out std_ulogic; + PPCS1PLBRDDACK : out std_ulogic; + PPCS1PLBRDDBUS : out std_logic_vector(0 to 127); + PPCS1PLBRDWDADDR : out std_logic_vector(0 to 3); + PPCS1PLBREARBITRATE : out std_ulogic; + PPCS1PLBSSIZE : out std_logic_vector(0 to 1); + PPCS1PLBWAIT : out std_ulogic; + PPCS1PLBWRBTERM : out std_ulogic; + PPCS1PLBWRCOMP : out std_ulogic; + PPCS1PLBWRDACK : out std_ulogic; + + CPMC440CLK : in std_ulogic; + CPMC440CLKEN : in std_ulogic; + CPMC440CORECLOCKINACTIVE : in std_ulogic; + CPMC440TIMERCLOCK : in std_ulogic; + CPMDCRCLK : in std_ulogic; + CPMDMA0LLCLK : in std_ulogic; + CPMDMA1LLCLK : in std_ulogic; + CPMDMA2LLCLK : in std_ulogic; + CPMDMA3LLCLK : in std_ulogic; + CPMFCMCLK : in std_ulogic; + CPMINTERCONNECTCLK : in std_ulogic; + CPMINTERCONNECTCLKEN : in std_ulogic; + CPMINTERCONNECTCLKNTO1 : in std_ulogic; + CPMMCCLK : in std_ulogic; + CPMPPCMPLBCLK : in std_ulogic; + CPMPPCS0PLBCLK : in std_ulogic; + CPMPPCS1PLBCLK : in std_ulogic; + DBGC440DEBUGHALT : in std_ulogic; + DBGC440SYSTEMSTATUS : in std_logic_vector(0 to 4); + DBGC440UNCONDDEBUGEVENT : in std_ulogic; + DCRPPCDMACK : in std_ulogic; + DCRPPCDMDBUSIN : in std_logic_vector(0 to 31); + DCRPPCDMTIMEOUTWAIT : in std_ulogic; + DCRPPCDSABUS : in std_logic_vector(0 to 9); + DCRPPCDSDBUSOUT : in std_logic_vector(0 to 31); + DCRPPCDSREAD : in std_ulogic; + DCRPPCDSWRITE : in std_ulogic; + EICC440CRITIRQ : in std_ulogic; + EICC440EXTIRQ : in std_ulogic; + FCMAPUCONFIRMINSTR : in std_ulogic; + FCMAPUCR : in std_logic_vector(0 to 3); + FCMAPUDONE : in std_ulogic; + FCMAPUEXCEPTION : in std_ulogic; + FCMAPUFPSCRFEX : in std_ulogic; + FCMAPURESULT : in std_logic_vector(0 to 31); + FCMAPURESULTVALID : in std_ulogic; + FCMAPUSLEEPNOTREADY : in std_ulogic; + FCMAPUSTOREDATA : in std_logic_vector(0 to 127); + GSR : in std_ulogic; + JTGC440TCK : in std_ulogic; + JTGC440TDI : in std_ulogic; + JTGC440TMS : in std_ulogic; + JTGC440TRSTNEG : in std_ulogic; + LLDMA0RSTENGINEREQ : in std_ulogic; + LLDMA0RXD : in std_logic_vector(0 to 31); + LLDMA0RXEOFN : in std_ulogic; + LLDMA0RXEOPN : in std_ulogic; + LLDMA0RXREM : in std_logic_vector(0 to 3); + LLDMA0RXSOFN : in std_ulogic; + LLDMA0RXSOPN : in std_ulogic; + LLDMA0RXSRCRDYN : in std_ulogic; + LLDMA0TXDSTRDYN : in std_ulogic; + LLDMA1RSTENGINEREQ : in std_ulogic; + LLDMA1RXD : in std_logic_vector(0 to 31); + LLDMA1RXEOFN : in std_ulogic; + LLDMA1RXEOPN : in std_ulogic; + LLDMA1RXREM : in std_logic_vector(0 to 3); + LLDMA1RXSOFN : in std_ulogic; + LLDMA1RXSOPN : in std_ulogic; + LLDMA1RXSRCRDYN : in std_ulogic; + LLDMA1TXDSTRDYN : in std_ulogic; + LLDMA2RSTENGINEREQ : in std_ulogic; + LLDMA2RXD : in std_logic_vector(0 to 31); + LLDMA2RXEOFN : in std_ulogic; + LLDMA2RXEOPN : in std_ulogic; + LLDMA2RXREM : in std_logic_vector(0 to 3); + LLDMA2RXSOFN : in std_ulogic; + LLDMA2RXSOPN : in std_ulogic; + LLDMA2RXSRCRDYN : in std_ulogic; + LLDMA2TXDSTRDYN : in std_ulogic; + LLDMA3RSTENGINEREQ : in std_ulogic; + LLDMA3RXD : in std_logic_vector(0 to 31); + LLDMA3RXEOFN : in std_ulogic; + LLDMA3RXEOPN : in std_ulogic; + LLDMA3RXREM : in std_logic_vector(0 to 3); + LLDMA3RXSOFN : in std_ulogic; + LLDMA3RXSOPN : in std_ulogic; + LLDMA3RXSRCRDYN : in std_ulogic; + LLDMA3TXDSTRDYN : in std_ulogic; + MCMIADDRREADYTOACCEPT : in std_ulogic; + MCMIREADDATA : in std_logic_vector(0 to 127); + MCMIREADDATAERR : in std_ulogic; + MCMIREADDATAVALID : in std_ulogic; + PLBPPCMADDRACK : in std_ulogic; + PLBPPCMMBUSY : in std_ulogic; + PLBPPCMMIRQ : in std_ulogic; + PLBPPCMMRDERR : in std_ulogic; + PLBPPCMMWRERR : in std_ulogic; + PLBPPCMRDBTERM : in std_ulogic; + PLBPPCMRDDACK : in std_ulogic; + PLBPPCMRDDBUS : in std_logic_vector(0 to 127); + PLBPPCMRDPENDPRI : in std_logic_vector(0 to 1); + PLBPPCMRDPENDREQ : in std_ulogic; + PLBPPCMRDWDADDR : in std_logic_vector(0 to 3); + PLBPPCMREARBITRATE : in std_ulogic; + PLBPPCMREQPRI : in std_logic_vector(0 to 1); + PLBPPCMSSIZE : in std_logic_vector(0 to 1); + PLBPPCMTIMEOUT : in std_ulogic; + PLBPPCMWRBTERM : in std_ulogic; + PLBPPCMWRDACK : in std_ulogic; + PLBPPCMWRPENDPRI : in std_logic_vector(0 to 1); + PLBPPCMWRPENDREQ : in std_ulogic; + PLBPPCS0ABORT : in std_ulogic; + PLBPPCS0ABUS : in std_logic_vector(0 to 31); + PLBPPCS0BE : in std_logic_vector(0 to 15); + PLBPPCS0BUSLOCK : in std_ulogic; + PLBPPCS0LOCKERR : in std_ulogic; + PLBPPCS0MASTERID : in std_logic_vector(0 to 1); + PLBPPCS0MSIZE : in std_logic_vector(0 to 1); + PLBPPCS0PAVALID : in std_ulogic; + PLBPPCS0RDBURST : in std_ulogic; + PLBPPCS0RDPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS0RDPENDREQ : in std_ulogic; + PLBPPCS0RDPRIM : in std_ulogic; + PLBPPCS0REQPRI : in std_logic_vector(0 to 1); + PLBPPCS0RNW : in std_ulogic; + PLBPPCS0SAVALID : in std_ulogic; + PLBPPCS0SIZE : in std_logic_vector(0 to 3); + PLBPPCS0TATTRIBUTE : in std_logic_vector(0 to 15); + PLBPPCS0TYPE : in std_logic_vector(0 to 2); + PLBPPCS0UABUS : in std_logic_vector(28 to 31); + PLBPPCS0WRBURST : in std_ulogic; + PLBPPCS0WRDBUS : in std_logic_vector(0 to 127); + PLBPPCS0WRPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS0WRPENDREQ : in std_ulogic; + PLBPPCS0WRPRIM : in std_ulogic; + PLBPPCS1ABORT : in std_ulogic; + PLBPPCS1ABUS : in std_logic_vector(0 to 31); + PLBPPCS1BE : in std_logic_vector(0 to 15); + PLBPPCS1BUSLOCK : in std_ulogic; + PLBPPCS1LOCKERR : in std_ulogic; + PLBPPCS1MASTERID : in std_logic_vector(0 to 1); + PLBPPCS1MSIZE : in std_logic_vector(0 to 1); + PLBPPCS1PAVALID : in std_ulogic; + PLBPPCS1RDBURST : in std_ulogic; + PLBPPCS1RDPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS1RDPENDREQ : in std_ulogic; + PLBPPCS1RDPRIM : in std_ulogic; + PLBPPCS1REQPRI : in std_logic_vector(0 to 1); + PLBPPCS1RNW : in std_ulogic; + PLBPPCS1SAVALID : in std_ulogic; + PLBPPCS1SIZE : in std_logic_vector(0 to 3); + PLBPPCS1TATTRIBUTE : in std_logic_vector(0 to 15); + PLBPPCS1TYPE : in std_logic_vector(0 to 2); + PLBPPCS1UABUS : in std_logic_vector(28 to 31); + PLBPPCS1WRBURST : in std_ulogic; + PLBPPCS1WRDBUS : in std_logic_vector(0 to 127); + PLBPPCS1WRPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS1WRPENDREQ : in std_ulogic; + PLBPPCS1WRPRIM : in std_ulogic; + RSTC440RESETCHIP : in std_ulogic; + RSTC440RESETCORE : in std_ulogic; + RSTC440RESETSYSTEM : in std_ulogic; + TIEC440DCURDLDCACHEPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCURDNONCACHEPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCURDTOUCHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCURDURGENTPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCUWRFLUSHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCUWRSTOREPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCUWRURGENTPLBPRIO : in std_logic_vector(0 to 1); + TIEC440ENDIANRESET : in std_ulogic; + TIEC440ERPNRESET : in std_logic_vector(0 to 3); + TIEC440ICURDFETCHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440ICURDSPECPLBPRIO : in std_logic_vector(0 to 1); + TIEC440ICURDTOUCHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440PIR : in std_logic_vector(28 to 31); + TIEC440PVR : in std_logic_vector(28 to 31); + TIEC440USERRESET : in std_logic_vector(0 to 3); + TIEDCRBASEADDR : in std_logic_vector(0 to 1); + TRCC440TRACEDISABLE : in std_ulogic; + TRCC440TRIGGEREVENTIN : in std_ulogic; + + APU_CONTROL : in std_logic_vector(0 to 16); + APU_UDI0 : in std_logic_vector(0 to 23); + APU_UDI1 : in std_logic_vector(0 to 23); + APU_UDI10 : in std_logic_vector(0 to 23); + APU_UDI11 : in std_logic_vector(0 to 23); + APU_UDI12 : in std_logic_vector(0 to 23); + APU_UDI13 : in std_logic_vector(0 to 23); + APU_UDI14 : in std_logic_vector(0 to 23); + APU_UDI15 : in std_logic_vector(0 to 23); + APU_UDI2 : in std_logic_vector(0 to 23); + APU_UDI3 : in std_logic_vector(0 to 23); + APU_UDI4 : in std_logic_vector(0 to 23); + APU_UDI5 : in std_logic_vector(0 to 23); + APU_UDI6 : in std_logic_vector(0 to 23); + APU_UDI7 : in std_logic_vector(0 to 23); + APU_UDI8 : in std_logic_vector(0 to 23); + APU_UDI9 : in std_logic_vector(0 to 23); +-- CLOCK_DELAY : in std_ulogic; + CLOCK_DELAY : in std_logic_vector(0 to 4); + DCR_AUTOLOCK_ENABLE : in std_ulogic; + DMA0_CONTROL : in std_logic_vector(0 to 7); + DMA0_RXCHANNELCTRL : in std_logic_vector(0 to 31); + DMA0_RXIRQTIMER : in std_logic_vector(0 to 9); + DMA0_TXCHANNELCTRL : in std_logic_vector(0 to 31); + DMA0_TXIRQTIMER : in std_logic_vector(0 to 9); + DMA1_CONTROL : in std_logic_vector(0 to 7); + DMA1_RXCHANNELCTRL : in std_logic_vector(0 to 31); + DMA1_RXIRQTIMER : in std_logic_vector(0 to 9); + DMA1_TXCHANNELCTRL : in std_logic_vector(0 to 31); + DMA1_TXIRQTIMER : in std_logic_vector(0 to 9); + DMA2_CONTROL : in std_logic_vector(0 to 7); + DMA2_RXCHANNELCTRL : in std_logic_vector(0 to 31); + DMA2_RXIRQTIMER : in std_logic_vector(0 to 9); + DMA2_TXCHANNELCTRL : in std_logic_vector(0 to 31); + DMA2_TXIRQTIMER : in std_logic_vector(0 to 9); + DMA3_CONTROL : in std_logic_vector(0 to 7); + DMA3_RXCHANNELCTRL : in std_logic_vector(0 to 31); + DMA3_RXIRQTIMER : in std_logic_vector(0 to 9); + DMA3_TXCHANNELCTRL : in std_logic_vector(0 to 31); + DMA3_TXIRQTIMER : in std_logic_vector(0 to 9); + INTERCONNECT_IMASK : in std_logic_vector(0 to 31); + INTERCONNECT_TMPL_SEL : in std_logic_vector(0 to 31); + MI_ARBCONFIG : in std_logic_vector(0 to 31); + MI_BANKCONFLICT_MASK : in std_logic_vector(0 to 31); + MI_CONTROL : in std_logic_vector(0 to 31); + MI_ROWCONFLICT_MASK : in std_logic_vector(0 to 31); + PPCDM_ASYNCMODE : in std_ulogic; + PPCDS_ASYNCMODE : in std_ulogic; + PPCM_ARBCONFIG : in std_logic_vector(0 to 31); + PPCM_CONTROL : in std_logic_vector(0 to 31); + PPCM_COUNTER : in std_logic_vector(0 to 31); + PPCS0_ADDRMAP_TMPL0 : in std_logic_vector(0 to 31); + PPCS0_ADDRMAP_TMPL1 : in std_logic_vector(0 to 31); + PPCS0_ADDRMAP_TMPL2 : in std_logic_vector(0 to 31); + PPCS0_ADDRMAP_TMPL3 : in std_logic_vector(0 to 31); + PPCS0_CONTROL : in std_logic_vector(0 to 31); + PPCS0_WIDTH_128N64 : in std_ulogic; + PPCS1_ADDRMAP_TMPL0 : in std_logic_vector(0 to 31); + PPCS1_ADDRMAP_TMPL1 : in std_logic_vector(0 to 31); + PPCS1_ADDRMAP_TMPL2 : in std_logic_vector(0 to 31); + PPCS1_ADDRMAP_TMPL3 : in std_logic_vector(0 to 31); + PPCS1_CONTROL : in std_logic_vector(0 to 31); + PPCS1_WIDTH_128N64 : in std_ulogic; + XBAR_ADDRMAP_TMPL0 : in std_logic_vector(0 to 31); + XBAR_ADDRMAP_TMPL1 : in std_logic_vector(0 to 31); + XBAR_ADDRMAP_TMPL2 : in std_logic_vector(0 to 31); + XBAR_ADDRMAP_TMPL3 : in std_logic_vector(0 to 31) + ); + end component; + + constant IN_DELAY : time := 1 ps; + constant OUT_DELAY : time := 0 ps; + constant CLK_DELAY : time := 0 ps; + constant ZERO_DELAY : time := 0 ps; + + constant PATH_DELAY : VitalDelayType01 := (100 ps, 100 ps); + + + signal DMA3_TXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA3_TXCHANNELCTRL); + signal DMA3_CONTROL_BINARY : std_logic_vector(0 to 7) := To_StdLogicVector(DMA3_CONTROL); + signal DMA3_RXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA3_RXCHANNELCTRL); + signal DMA3_TXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA3_TXIRQTIMER)(9 downto 0); + signal DMA3_RXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA3_RXIRQTIMER)(9 downto 0); + signal DMA2_TXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA2_TXCHANNELCTRL); + signal DMA2_CONTROL_BINARY : std_logic_vector(0 to 7) := To_StdLogicVector(DMA2_CONTROL); + signal DMA2_RXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA2_RXCHANNELCTRL); + signal DMA2_TXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA2_TXIRQTIMER)(9 downto 0); + signal DMA2_RXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA2_RXIRQTIMER)(9 downto 0); + signal PPCM_CONTROL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCM_CONTROL); + signal PPCM_COUNTER_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCM_COUNTER); + signal PPCM_ARBCONFIG_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCM_ARBCONFIG); + signal DMA1_RXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA1_RXIRQTIMER)(9 downto 0); + signal DMA1_TXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA1_TXIRQTIMER)(9 downto 0); + signal DMA1_RXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA1_RXCHANNELCTRL); + signal DMA1_CONTROL_BINARY : std_logic_vector(0 to 7) := To_StdLogicVector(DMA1_CONTROL); + signal DMA1_TXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA1_TXCHANNELCTRL); + signal DMA0_RXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA0_RXIRQTIMER)(9 downto 0); + signal DMA0_TXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA0_TXIRQTIMER)(9 downto 0); + signal DMA0_RXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA0_RXCHANNELCTRL); + signal DMA0_CONTROL_BINARY : std_logic_vector(0 to 7) := To_StdLogicVector(DMA0_CONTROL); + signal DMA0_TXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA0_TXCHANNELCTRL); + signal MI_ROWCONFLICT_MASK_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(MI_ROWCONFLICT_MASK); + signal MI_BANKCONFLICT_MASK_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(MI_BANKCONFLICT_MASK); + signal MI_ARBCONFIG_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(MI_ARBCONFIG); + signal MI_CONTROL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(MI_CONTROL); + signal APU_UDI0_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI0); + signal APU_UDI1_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI1); + signal APU_UDI2_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI2); + signal APU_UDI3_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI3); + signal APU_UDI4_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI4); + signal APU_UDI5_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI5); + signal APU_UDI6_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI6); + signal APU_UDI7_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI7); + signal APU_UDI8_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI8); + signal APU_UDI9_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI9); + signal APU_UDI10_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI10); + signal APU_UDI11_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI11); + signal APU_UDI12_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI12); + signal APU_UDI13_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI13); + signal APU_UDI14_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI14); + signal APU_UDI15_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI15); + signal APU_CONTROL_BINARY : std_logic_vector(0 to 16) := To_StdLogicVector(APU_CONTROL)(16 downto 0); + signal INTERCONNECT_IMASK_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(INTERCONNECT_IMASK); + signal XBAR_ADDRMAP_TMPL0_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(XBAR_ADDRMAP_TMPL0); + signal XBAR_ADDRMAP_TMPL1_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(XBAR_ADDRMAP_TMPL1); + signal XBAR_ADDRMAP_TMPL2_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(XBAR_ADDRMAP_TMPL2); + signal XBAR_ADDRMAP_TMPL3_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(XBAR_ADDRMAP_TMPL3); + signal INTERCONNECT_TMPL_SEL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(INTERCONNECT_TMPL_SEL); + signal PPCS0_CONTROL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS0_CONTROL); + signal PPCS0_WIDTH_128N64_BINARY : std_ulogic; + signal PPCS0_ADDRMAP_TMPL0_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS0_ADDRMAP_TMPL0); + signal PPCS0_ADDRMAP_TMPL1_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS0_ADDRMAP_TMPL1); + signal PPCS0_ADDRMAP_TMPL2_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS0_ADDRMAP_TMPL2); + signal PPCS0_ADDRMAP_TMPL3_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS0_ADDRMAP_TMPL3); + signal PPCS1_CONTROL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS1_CONTROL); + signal PPCS1_WIDTH_128N64_BINARY : std_ulogic; + signal PPCS1_ADDRMAP_TMPL0_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS1_ADDRMAP_TMPL0); + signal PPCS1_ADDRMAP_TMPL1_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS1_ADDRMAP_TMPL1); + signal PPCS1_ADDRMAP_TMPL2_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS1_ADDRMAP_TMPL2); + signal PPCS1_ADDRMAP_TMPL3_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS1_ADDRMAP_TMPL3); + signal PPCDM_ASYNCMODE_BINARY : std_ulogic; + signal PPCDS_ASYNCMODE_BINARY : std_ulogic; + signal DCR_AUTOLOCK_ENABLE_BINARY : std_ulogic; + signal CLOCK_DELAY_BINARY : std_logic_vector(0 to 4); + + signal DMA0LLRSTENGINEACK_out : std_ulogic; + signal DMA0LLRXDSTRDYN_out : std_ulogic; + signal DMA0LLTXD_out : std_logic_vector(0 to 31); + signal DMA0LLTXEOFN_out : std_ulogic; + signal DMA0LLTXEOPN_out : std_ulogic; + signal DMA0LLTXREM_out : std_logic_vector(0 to 3); + signal DMA0LLTXSOFN_out : std_ulogic; + signal DMA0LLTXSOPN_out : std_ulogic; + signal DMA0LLTXSRCRDYN_out : std_ulogic; + signal DMA0RXIRQ_out : std_ulogic; + signal DMA0TXIRQ_out : std_ulogic; + signal DMA1LLRSTENGINEACK_out : std_ulogic; + signal DMA1LLRXDSTRDYN_out : std_ulogic; + signal DMA1LLTXD_out : std_logic_vector(0 to 31); + signal DMA1LLTXEOFN_out : std_ulogic; + signal DMA1LLTXEOPN_out : std_ulogic; + signal DMA1LLTXREM_out : std_logic_vector(0 to 3); + signal DMA1LLTXSOFN_out : std_ulogic; + signal DMA1LLTXSOPN_out : std_ulogic; + signal DMA1LLTXSRCRDYN_out : std_ulogic; + signal DMA1RXIRQ_out : std_ulogic; + signal DMA1TXIRQ_out : std_ulogic; + signal DMA2LLRSTENGINEACK_out : std_ulogic; + signal DMA2LLRXDSTRDYN_out : std_ulogic; + signal DMA2LLTXD_out : std_logic_vector(0 to 31); + signal DMA2LLTXEOFN_out : std_ulogic; + signal DMA2LLTXEOPN_out : std_ulogic; + signal DMA2LLTXREM_out : std_logic_vector(0 to 3); + signal DMA2LLTXSOFN_out : std_ulogic; + signal DMA2LLTXSOPN_out : std_ulogic; + signal DMA2LLTXSRCRDYN_out : std_ulogic; + signal DMA2RXIRQ_out : std_ulogic; + signal DMA2TXIRQ_out : std_ulogic; + signal DMA3LLRSTENGINEACK_out : std_ulogic; + signal DMA3LLRXDSTRDYN_out : std_ulogic; + signal DMA3LLTXD_out : std_logic_vector(0 to 31); + signal DMA3LLTXEOFN_out : std_ulogic; + signal DMA3LLTXEOPN_out : std_ulogic; + signal DMA3LLTXREM_out : std_logic_vector(0 to 3); + signal DMA3LLTXSOFN_out : std_ulogic; + signal DMA3LLTXSOPN_out : std_ulogic; + signal DMA3LLTXSRCRDYN_out : std_ulogic; + signal DMA3RXIRQ_out : std_ulogic; + signal DMA3TXIRQ_out : std_ulogic; + signal PPCDMDCRABUS_out : std_logic_vector(0 to 9); + signal PPCDMDCRDBUSOUT_out : std_logic_vector(0 to 31); + signal PPCDMDCRREAD_out : std_ulogic; + signal PPCDMDCRUABUS_out : std_logic_vector(20 to 21); + signal PPCDMDCRWRITE_out : std_ulogic; + signal PPCMPLBABORT_out : std_ulogic; + signal PPCMPLBABUS_out : std_logic_vector(0 to 31); + signal PPCMPLBBE_out : std_logic_vector(0 to 15); + signal PPCMPLBBUSLOCK_out : std_ulogic; + signal PPCMPLBLOCKERR_out : std_ulogic; + signal PPCMPLBPRIORITY_out : std_logic_vector(0 to 1); + signal PPCMPLBRDBURST_out : std_ulogic; + signal PPCMPLBREQUEST_out : std_ulogic; + signal PPCMPLBRNW_out : std_ulogic; + signal PPCMPLBSIZE_out : std_logic_vector(0 to 3); + signal PPCMPLBTATTRIBUTE_out : std_logic_vector(0 to 15); + signal PPCMPLBTYPE_out : std_logic_vector(0 to 2); + signal PPCMPLBUABUS_out : std_logic_vector(28 to 31); + signal PPCMPLBWRBURST_out : std_ulogic; + signal PPCMPLBWRDBUS_out : std_logic_vector(0 to 127); + signal PPCS0PLBADDRACK_out : std_ulogic; + signal PPCS0PLBMBUSY_out : std_logic_vector(0 to 3); + signal PPCS0PLBMIRQ_out : std_logic_vector(0 to 3); + signal PPCS0PLBMRDERR_out : std_logic_vector(0 to 3); + signal PPCS0PLBMWRERR_out : std_logic_vector(0 to 3); + signal PPCS0PLBRDBTERM_out : std_ulogic; + signal PPCS0PLBRDCOMP_out : std_ulogic; + signal PPCS0PLBRDDACK_out : std_ulogic; + signal PPCS0PLBRDDBUS_out : std_logic_vector(0 to 127); + signal PPCS0PLBRDWDADDR_out : std_logic_vector(0 to 3); + signal PPCS0PLBREARBITRATE_out : std_ulogic; + signal PPCS0PLBSSIZE_out : std_logic_vector(0 to 1); + signal PPCS0PLBWAIT_out : std_ulogic; + signal PPCS0PLBWRBTERM_out : std_ulogic; + signal PPCS0PLBWRCOMP_out : std_ulogic; + signal PPCS0PLBWRDACK_out : std_ulogic; + signal PPCS1PLBADDRACK_out : std_ulogic; + signal PPCS1PLBMBUSY_out : std_logic_vector(0 to 3); + signal PPCS1PLBMIRQ_out : std_logic_vector(0 to 3); + signal PPCS1PLBMRDERR_out : std_logic_vector(0 to 3); + signal PPCS1PLBMWRERR_out : std_logic_vector(0 to 3); + signal PPCS1PLBRDBTERM_out : std_ulogic; + signal PPCS1PLBRDCOMP_out : std_ulogic; + signal PPCS1PLBRDDACK_out : std_ulogic; + signal PPCS1PLBRDDBUS_out : std_logic_vector(0 to 127); + signal PPCS1PLBRDWDADDR_out : std_logic_vector(0 to 3); + signal PPCS1PLBREARBITRATE_out : std_ulogic; + signal PPCS1PLBSSIZE_out : std_logic_vector(0 to 1); + signal PPCS1PLBWAIT_out : std_ulogic; + signal PPCS1PLBWRBTERM_out : std_ulogic; + signal PPCS1PLBWRCOMP_out : std_ulogic; + signal PPCS1PLBWRDACK_out : std_ulogic; + signal APUFCMDECFPUOP_out : std_ulogic; + signal APUFCMDECLDSTXFERSIZE_out : std_logic_vector(0 to 2); + signal APUFCMDECLOAD_out : std_ulogic; + signal APUFCMDECNONAUTON_out : std_ulogic; + signal APUFCMDECSTORE_out : std_ulogic; + signal APUFCMDECUDI_out : std_logic_vector(0 to 3); + signal APUFCMDECUDIVALID_out : std_ulogic; + signal APUFCMENDIAN_out : std_ulogic; + signal APUFCMFLUSH_out : std_ulogic; + signal APUFCMINSTRUCTION_out : std_logic_vector(0 to 31); + signal APUFCMINSTRVALID_out : std_ulogic; + signal APUFCMLOADBYTEADDR_out : std_logic_vector(0 to 3); + signal APUFCMLOADDATA_out : std_logic_vector(0 to 127); + signal APUFCMLOADDVALID_out : std_ulogic; + signal APUFCMMSRFE0_out : std_ulogic; + signal APUFCMMSRFE1_out : std_ulogic; + signal APUFCMNEXTINSTRREADY_out : std_ulogic; + signal APUFCMOPERANDVALID_out : std_ulogic; + signal APUFCMRADATA_out : std_logic_vector(0 to 31); + signal APUFCMRBDATA_out : std_logic_vector(0 to 31); + signal APUFCMWRITEBACKOK_out : std_ulogic; + signal C440CPMCORESLEEPREQ_out : std_ulogic; + signal C440CPMDECIRPTREQ_out : std_ulogic; + signal C440CPMFITIRPTREQ_out : std_ulogic; + signal C440CPMMSRCE_out : std_ulogic; + signal C440CPMMSREE_out : std_ulogic; + signal C440CPMTIMERRESETREQ_out : std_ulogic; + signal C440CPMWDIRPTREQ_out : std_ulogic; + signal C440DBGSYSTEMCONTROL_out : std_logic_vector(0 to 7); + signal C440JTGTDO_out : std_ulogic; + signal C440JTGTDOEN_out : std_ulogic; + signal C440MACHINECHECK_out : std_ulogic; + signal C440RSTCHIPRESETREQ_out : std_ulogic; + signal C440RSTCORERESETREQ_out : std_ulogic; + signal C440RSTSYSTEMRESETREQ_out : std_ulogic; + signal C440TRCBRANCHSTATUS_out : std_logic_vector(0 to 2); + signal C440TRCCYCLE_out : std_ulogic; + signal C440TRCEXECUTIONSTATUS_out : std_logic_vector(0 to 4); + signal C440TRCTRACESTATUS_out : std_logic_vector(0 to 6); + signal C440TRCTRIGGEREVENTOUT_out : std_ulogic; + signal C440TRCTRIGGEREVENTTYPE_out : std_logic_vector(0 to 13); + signal MIMCADDRESS_out : std_logic_vector(0 to 35); + signal MIMCADDRESSVALID_out : std_ulogic; + signal MIMCBANKCONFLICT_out : std_ulogic; + signal MIMCBYTEENABLE_out : std_logic_vector(0 to 15); + signal MIMCREADNOTWRITE_out : std_ulogic; + signal MIMCROWCONFLICT_out : std_ulogic; + signal MIMCWRITEDATA_out : std_logic_vector(0 to 127); + signal MIMCWRITEDATAVALID_out : std_ulogic; + signal PPCCPMINTERCONNECTBUSY_out : std_ulogic; + signal PPCDSDCRACK_out : std_ulogic; + signal PPCDSDCRTIMEOUTWAIT_out : std_ulogic; + signal PPCDSDCRDBUSIN_out : std_logic_vector(0 to 31); + signal PPCEICINTERCONNECTIRQ_out : std_ulogic; + + + signal DMA0LLRSTENGINEACK_outdelay : std_ulogic; + signal DMA0LLRXDSTRDYN_outdelay : std_ulogic; + signal DMA0LLTXD_outdelay : std_logic_vector(0 to 31); + signal DMA0LLTXEOFN_outdelay : std_ulogic; + signal DMA0LLTXEOPN_outdelay : std_ulogic; + signal DMA0LLTXREM_outdelay : std_logic_vector(0 to 3); + signal DMA0LLTXSOFN_outdelay : std_ulogic; + signal DMA0LLTXSOPN_outdelay : std_ulogic; + signal DMA0LLTXSRCRDYN_outdelay : std_ulogic; + signal DMA0RXIRQ_outdelay : std_ulogic; + signal DMA0TXIRQ_outdelay : std_ulogic; + signal DMA1LLRSTENGINEACK_outdelay : std_ulogic; + signal DMA1LLRXDSTRDYN_outdelay : std_ulogic; + signal DMA1LLTXD_outdelay : std_logic_vector(0 to 31); + signal DMA1LLTXEOFN_outdelay : std_ulogic; + signal DMA1LLTXEOPN_outdelay : std_ulogic; + signal DMA1LLTXREM_outdelay : std_logic_vector(0 to 3); + signal DMA1LLTXSOFN_outdelay : std_ulogic; + signal DMA1LLTXSOPN_outdelay : std_ulogic; + signal DMA1LLTXSRCRDYN_outdelay : std_ulogic; + signal DMA1RXIRQ_outdelay : std_ulogic; + signal DMA1TXIRQ_outdelay : std_ulogic; + signal DMA2LLRSTENGINEACK_outdelay : std_ulogic; + signal DMA2LLRXDSTRDYN_outdelay : std_ulogic; + signal DMA2LLTXD_outdelay : std_logic_vector(0 to 31); + signal DMA2LLTXEOFN_outdelay : std_ulogic; + signal DMA2LLTXEOPN_outdelay : std_ulogic; + signal DMA2LLTXREM_outdelay : std_logic_vector(0 to 3); + signal DMA2LLTXSOFN_outdelay : std_ulogic; + signal DMA2LLTXSOPN_outdelay : std_ulogic; + signal DMA2LLTXSRCRDYN_outdelay : std_ulogic; + signal DMA2RXIRQ_outdelay : std_ulogic; + signal DMA2TXIRQ_outdelay : std_ulogic; + signal DMA3LLRSTENGINEACK_outdelay : std_ulogic; + signal DMA3LLRXDSTRDYN_outdelay : std_ulogic; + signal DMA3LLTXD_outdelay : std_logic_vector(0 to 31); + signal DMA3LLTXEOFN_outdelay : std_ulogic; + signal DMA3LLTXEOPN_outdelay : std_ulogic; + signal DMA3LLTXREM_outdelay : std_logic_vector(0 to 3); + signal DMA3LLTXSOFN_outdelay : std_ulogic; + signal DMA3LLTXSOPN_outdelay : std_ulogic; + signal DMA3LLTXSRCRDYN_outdelay : std_ulogic; + signal DMA3RXIRQ_outdelay : std_ulogic; + signal DMA3TXIRQ_outdelay : std_ulogic; + signal PPCDMDCRABUS_outdelay : std_logic_vector(0 to 9); + signal PPCDMDCRDBUSOUT_outdelay : std_logic_vector(0 to 31); + signal PPCDMDCRREAD_outdelay : std_ulogic; + signal PPCDMDCRUABUS_outdelay : std_logic_vector(20 to 21); + signal PPCDMDCRWRITE_outdelay : std_ulogic; + signal PPCMPLBABORT_outdelay : std_ulogic; + signal PPCMPLBABUS_outdelay : std_logic_vector(0 to 31); + signal PPCMPLBBE_outdelay : std_logic_vector(0 to 15); + signal PPCMPLBBUSLOCK_outdelay : std_ulogic; + signal PPCMPLBLOCKERR_outdelay : std_ulogic; + signal PPCMPLBPRIORITY_outdelay : std_logic_vector(0 to 1); + signal PPCMPLBRDBURST_outdelay : std_ulogic; + signal PPCMPLBREQUEST_outdelay : std_ulogic; + signal PPCMPLBRNW_outdelay : std_ulogic; + signal PPCMPLBSIZE_outdelay : std_logic_vector(0 to 3); + signal PPCMPLBTATTRIBUTE_outdelay : std_logic_vector(0 to 15); + signal PPCMPLBTYPE_outdelay : std_logic_vector(0 to 2); + signal PPCMPLBUABUS_outdelay : std_logic_vector(28 to 31); + signal PPCMPLBWRBURST_outdelay : std_ulogic; + signal PPCMPLBWRDBUS_outdelay : std_logic_vector(0 to 127); + signal PPCS0PLBADDRACK_outdelay : std_ulogic; + signal PPCS0PLBMBUSY_outdelay : std_logic_vector(0 to 3); + signal PPCS0PLBMIRQ_outdelay : std_logic_vector(0 to 3); + signal PPCS0PLBMRDERR_outdelay : std_logic_vector(0 to 3); + signal PPCS0PLBMWRERR_outdelay : std_logic_vector(0 to 3); + signal PPCS0PLBRDBTERM_outdelay : std_ulogic; + signal PPCS0PLBRDCOMP_outdelay : std_ulogic; + signal PPCS0PLBRDDACK_outdelay : std_ulogic; + signal PPCS0PLBRDDBUS_outdelay : std_logic_vector(0 to 127); + signal PPCS0PLBRDWDADDR_outdelay : std_logic_vector(0 to 3); + signal PPCS0PLBREARBITRATE_outdelay : std_ulogic; + signal PPCS0PLBSSIZE_outdelay : std_logic_vector(0 to 1); + signal PPCS0PLBWAIT_outdelay : std_ulogic; + signal PPCS0PLBWRBTERM_outdelay : std_ulogic; + signal PPCS0PLBWRCOMP_outdelay : std_ulogic; + signal PPCS0PLBWRDACK_outdelay : std_ulogic; + signal PPCS1PLBADDRACK_outdelay : std_ulogic; + signal PPCS1PLBMBUSY_outdelay : std_logic_vector(0 to 3); + signal PPCS1PLBMIRQ_outdelay : std_logic_vector(0 to 3); + signal PPCS1PLBMRDERR_outdelay : std_logic_vector(0 to 3); + signal PPCS1PLBMWRERR_outdelay : std_logic_vector(0 to 3); + signal PPCS1PLBRDBTERM_outdelay : std_ulogic; + signal PPCS1PLBRDCOMP_outdelay : std_ulogic; + signal PPCS1PLBRDDACK_outdelay : std_ulogic; + signal PPCS1PLBRDDBUS_outdelay : std_logic_vector(0 to 127); + signal PPCS1PLBRDWDADDR_outdelay : std_logic_vector(0 to 3); + signal PPCS1PLBREARBITRATE_outdelay : std_ulogic; + signal PPCS1PLBSSIZE_outdelay : std_logic_vector(0 to 1); + signal PPCS1PLBWAIT_outdelay : std_ulogic; + signal PPCS1PLBWRBTERM_outdelay : std_ulogic; + signal PPCS1PLBWRCOMP_outdelay : std_ulogic; + signal PPCS1PLBWRDACK_outdelay : std_ulogic; + signal APUFCMDECFPUOP_outdelay : std_ulogic; + signal APUFCMDECLDSTXFERSIZE_outdelay : std_logic_vector(0 to 2); + signal APUFCMDECLOAD_outdelay : std_ulogic; + signal APUFCMDECNONAUTON_outdelay : std_ulogic; + signal APUFCMDECSTORE_outdelay : std_ulogic; + signal APUFCMDECUDI_outdelay : std_logic_vector(0 to 3); + signal APUFCMDECUDIVALID_outdelay : std_ulogic; + signal APUFCMENDIAN_outdelay : std_ulogic; + signal APUFCMFLUSH_outdelay : std_ulogic; + signal APUFCMINSTRUCTION_outdelay : std_logic_vector(0 to 31); + signal APUFCMINSTRVALID_outdelay : std_ulogic; + signal APUFCMLOADBYTEADDR_outdelay : std_logic_vector(0 to 3); + signal APUFCMLOADDATA_outdelay : std_logic_vector(0 to 127); + signal APUFCMLOADDVALID_outdelay : std_ulogic; + signal APUFCMMSRFE0_outdelay : std_ulogic; + signal APUFCMMSRFE1_outdelay : std_ulogic; + signal APUFCMNEXTINSTRREADY_outdelay : std_ulogic; + signal APUFCMOPERANDVALID_outdelay : std_ulogic; + signal APUFCMRADATA_outdelay : std_logic_vector(0 to 31); + signal APUFCMRBDATA_outdelay : std_logic_vector(0 to 31); + signal APUFCMWRITEBACKOK_outdelay : std_ulogic; + signal C440CPMCORESLEEPREQ_outdelay : std_ulogic; + signal C440CPMDECIRPTREQ_outdelay : std_ulogic; + signal C440CPMFITIRPTREQ_outdelay : std_ulogic; + signal C440CPMMSRCE_outdelay : std_ulogic; + signal C440CPMMSREE_outdelay : std_ulogic; + signal C440CPMTIMERRESETREQ_outdelay : std_ulogic; + signal C440CPMWDIRPTREQ_outdelay : std_ulogic; + signal C440DBGSYSTEMCONTROL_outdelay : std_logic_vector(0 to 7); + signal C440JTGTDO_outdelay : std_ulogic; + signal C440JTGTDOEN_outdelay : std_ulogic; + signal C440MACHINECHECK_outdelay : std_ulogic; + signal C440RSTCHIPRESETREQ_outdelay : std_ulogic; + signal C440RSTCORERESETREQ_outdelay : std_ulogic; + signal C440RSTSYSTEMRESETREQ_outdelay : std_ulogic; + signal C440TRCBRANCHSTATUS_outdelay : std_logic_vector(0 to 2); + signal C440TRCCYCLE_outdelay : std_ulogic; + signal C440TRCEXECUTIONSTATUS_outdelay : std_logic_vector(0 to 4); + signal C440TRCTRACESTATUS_outdelay : std_logic_vector(0 to 6); + signal C440TRCTRIGGEREVENTOUT_outdelay : std_ulogic; + signal C440TRCTRIGGEREVENTTYPE_outdelay : std_logic_vector(0 to 13); + signal MIMCADDRESS_outdelay : std_logic_vector(0 to 35); + signal MIMCADDRESSVALID_outdelay : std_ulogic; + signal MIMCBANKCONFLICT_outdelay : std_ulogic; + signal MIMCBYTEENABLE_outdelay : std_logic_vector(0 to 15); + signal MIMCREADNOTWRITE_outdelay : std_ulogic; + signal MIMCROWCONFLICT_outdelay : std_ulogic; + signal MIMCWRITEDATA_outdelay : std_logic_vector(0 to 127); + signal MIMCWRITEDATAVALID_outdelay : std_ulogic; + signal PPCCPMINTERCONNECTBUSY_outdelay : std_ulogic; + signal PPCDSDCRACK_outdelay : std_ulogic; + signal PPCDSDCRTIMEOUTWAIT_outdelay : std_ulogic; + signal PPCDSDCRDBUSIN_outdelay : std_logic_vector(0 to 31); + signal PPCEICINTERCONNECTIRQ_outdelay : std_ulogic; + + signal PLBPPCS0RNW_ipd : std_ulogic; + signal PLBPPCS1RNW_ipd : std_ulogic; + signal CPMDCRCLK_ipd : std_ulogic; + signal CPMDMA0LLCLK_ipd : std_ulogic; + signal CPMDMA1LLCLK_ipd : std_ulogic; + signal CPMDMA2LLCLK_ipd : std_ulogic; + signal CPMDMA3LLCLK_ipd : std_ulogic; + signal CPMINTERCONNECTCLKNTO1_ipd : std_ulogic; + signal CPMPPCMPLBCLK_ipd : std_ulogic; + signal CPMPPCS0PLBCLK_ipd : std_ulogic; + signal CPMPPCS1PLBCLK_ipd : std_ulogic; + signal DCRPPCDMACK_ipd : std_ulogic; + signal DCRPPCDMDBUSIN_ipd : std_logic_vector(0 to 31); + signal DCRPPCDMTIMEOUTWAIT_ipd : std_ulogic; + signal LLDMA0RSTENGINEREQ_ipd : std_ulogic; + signal LLDMA0RXD_ipd : std_logic_vector(0 to 31); + signal LLDMA0RXEOFN_ipd : std_ulogic; + signal LLDMA0RXEOPN_ipd : std_ulogic; + signal LLDMA0RXREM_ipd : std_logic_vector(0 to 3); + signal LLDMA0RXSOFN_ipd : std_ulogic; + signal LLDMA0RXSOPN_ipd : std_ulogic; + signal LLDMA0RXSRCRDYN_ipd : std_ulogic; + signal LLDMA0TXDSTRDYN_ipd : std_ulogic; + signal LLDMA1RSTENGINEREQ_ipd : std_ulogic; + signal LLDMA1RXD_ipd : std_logic_vector(0 to 31); + signal LLDMA1RXEOFN_ipd : std_ulogic; + signal LLDMA1RXEOPN_ipd : std_ulogic; + signal LLDMA1RXREM_ipd : std_logic_vector(0 to 3); + signal LLDMA1RXSOFN_ipd : std_ulogic; + signal LLDMA1RXSOPN_ipd : std_ulogic; + signal LLDMA1RXSRCRDYN_ipd : std_ulogic; + signal LLDMA1TXDSTRDYN_ipd : std_ulogic; + signal LLDMA2RSTENGINEREQ_ipd : std_ulogic; + signal LLDMA2RXD_ipd : std_logic_vector(0 to 31); + signal LLDMA2RXEOFN_ipd : std_ulogic; + signal LLDMA2RXEOPN_ipd : std_ulogic; + signal LLDMA2RXREM_ipd : std_logic_vector(0 to 3); + signal LLDMA2RXSOFN_ipd : std_ulogic; + signal LLDMA2RXSOPN_ipd : std_ulogic; + signal LLDMA2RXSRCRDYN_ipd : std_ulogic; + signal LLDMA2TXDSTRDYN_ipd : std_ulogic; + signal LLDMA3RSTENGINEREQ_ipd : std_ulogic; + signal LLDMA3RXD_ipd : std_logic_vector(0 to 31); + signal LLDMA3RXEOFN_ipd : std_ulogic; + signal LLDMA3RXEOPN_ipd : std_ulogic; + signal LLDMA3RXREM_ipd : std_logic_vector(0 to 3); + signal LLDMA3RXSOFN_ipd : std_ulogic; + signal LLDMA3RXSOPN_ipd : std_ulogic; + signal LLDMA3RXSRCRDYN_ipd : std_ulogic; + signal LLDMA3TXDSTRDYN_ipd : std_ulogic; + signal PLBPPCMADDRACK_ipd : std_ulogic; + signal PLBPPCMMBUSY_ipd : std_ulogic; + signal PLBPPCMMIRQ_ipd : std_ulogic; + signal PLBPPCMMRDERR_ipd : std_ulogic; + signal PLBPPCMMWRERR_ipd : std_ulogic; + signal PLBPPCMRDBTERM_ipd : std_ulogic; + signal PLBPPCMRDDACK_ipd : std_ulogic; + signal PLBPPCMRDDBUS_ipd : std_logic_vector(0 to 127); + signal PLBPPCMRDPENDPRI_ipd : std_logic_vector(0 to 1); + signal PLBPPCMRDPENDREQ_ipd : std_ulogic; + signal PLBPPCMRDWDADDR_ipd : std_logic_vector(0 to 3); + signal PLBPPCMREARBITRATE_ipd : std_ulogic; + signal PLBPPCMREQPRI_ipd : std_logic_vector(0 to 1); + signal PLBPPCMSSIZE_ipd : std_logic_vector(0 to 1); + signal PLBPPCMTIMEOUT_ipd : std_ulogic; + signal PLBPPCMWRBTERM_ipd : std_ulogic; + signal PLBPPCMWRDACK_ipd : std_ulogic; + signal PLBPPCMWRPENDPRI_ipd : std_logic_vector(0 to 1); + signal PLBPPCMWRPENDREQ_ipd : std_ulogic; + signal PLBPPCS0ABORT_ipd : std_ulogic; + signal PLBPPCS0ABUS_ipd : std_logic_vector(0 to 31); + signal PLBPPCS0BE_ipd : std_logic_vector(0 to 15); + signal PLBPPCS0BUSLOCK_ipd : std_ulogic; + signal PLBPPCS0LOCKERR_ipd : std_ulogic; + signal PLBPPCS0MASTERID_ipd : std_logic_vector(0 to 1); + signal PLBPPCS0MSIZE_ipd : std_logic_vector(0 to 1); + signal PLBPPCS0PAVALID_ipd : std_ulogic; + signal PLBPPCS0RDBURST_ipd : std_ulogic; + signal PLBPPCS0RDPENDPRI_ipd : std_logic_vector(0 to 1); + signal PLBPPCS0RDPENDREQ_ipd : std_ulogic; + signal PLBPPCS0RDPRIM_ipd : std_ulogic; + signal PLBPPCS0REQPRI_ipd : std_logic_vector(0 to 1); + signal PLBPPCS0SAVALID_ipd : std_ulogic; + signal PLBPPCS0SIZE_ipd : std_logic_vector(0 to 3); + signal PLBPPCS0TATTRIBUTE_ipd : std_logic_vector(0 to 15); + signal PLBPPCS0TYPE_ipd : std_logic_vector(0 to 2); + signal PLBPPCS0UABUS_ipd : std_logic_vector(28 to 31); + signal PLBPPCS0WRBURST_ipd : std_ulogic; + signal PLBPPCS0WRDBUS_ipd : std_logic_vector(0 to 127); + signal PLBPPCS0WRPENDPRI_ipd : std_logic_vector(0 to 1); + signal PLBPPCS0WRPENDREQ_ipd : std_ulogic; + signal PLBPPCS0WRPRIM_ipd : std_ulogic; + signal PLBPPCS1ABORT_ipd : std_ulogic; + signal PLBPPCS1ABUS_ipd : std_logic_vector(0 to 31); + signal PLBPPCS1BE_ipd : std_logic_vector(0 to 15); + signal PLBPPCS1BUSLOCK_ipd : std_ulogic; + signal PLBPPCS1LOCKERR_ipd : std_ulogic; + signal PLBPPCS1MASTERID_ipd : std_logic_vector(0 to 1); + signal PLBPPCS1MSIZE_ipd : std_logic_vector(0 to 1); + signal PLBPPCS1PAVALID_ipd : std_ulogic; + signal PLBPPCS1RDBURST_ipd : std_ulogic; + signal PLBPPCS1RDPENDPRI_ipd : std_logic_vector(0 to 1); + signal PLBPPCS1RDPENDREQ_ipd : std_ulogic; + signal PLBPPCS1RDPRIM_ipd : std_ulogic; + signal PLBPPCS1REQPRI_ipd : std_logic_vector(0 to 1); + signal PLBPPCS1SAVALID_ipd : std_ulogic; + signal PLBPPCS1SIZE_ipd : std_logic_vector(0 to 3); + signal PLBPPCS1TATTRIBUTE_ipd : std_logic_vector(0 to 15); + signal PLBPPCS1TYPE_ipd : std_logic_vector(0 to 2); + signal PLBPPCS1UABUS_ipd : std_logic_vector(28 to 31); + signal PLBPPCS1WRBURST_ipd : std_ulogic; + signal PLBPPCS1WRDBUS_ipd : std_logic_vector(0 to 127); + signal PLBPPCS1WRPENDPRI_ipd : std_logic_vector(0 to 1); + signal PLBPPCS1WRPENDREQ_ipd : std_ulogic; + signal PLBPPCS1WRPRIM_ipd : std_ulogic; + signal TIEDCRBASEADDR_ipd : std_logic_vector(0 to 1); + signal CPMC440CLK_ipd : std_ulogic; + signal CPMC440CLKEN_ipd : std_ulogic; + signal CPMC440CORECLOCKINACTIVE_ipd : std_ulogic; + signal CPMC440TIMERCLOCK_ipd : std_ulogic; + signal CPMFCMCLK_ipd : std_ulogic; + signal CPMINTERCONNECTCLK_ipd : std_ulogic; + signal CPMINTERCONNECTCLKEN_ipd : std_ulogic; + signal CPMMCCLK_ipd : std_ulogic; + signal DBGC440DEBUGHALT_ipd : std_ulogic; + signal DBGC440SYSTEMSTATUS_ipd : std_logic_vector(0 to 4); + signal DBGC440UNCONDDEBUGEVENT_ipd : std_ulogic; + signal DCRPPCDSABUS_ipd : std_logic_vector(0 to 9); + signal DCRPPCDSDBUSOUT_ipd : std_logic_vector(0 to 31); + signal DCRPPCDSREAD_ipd : std_ulogic; + signal DCRPPCDSWRITE_ipd : std_ulogic; + signal EICC440CRITIRQ_ipd : std_ulogic; + signal EICC440EXTIRQ_ipd : std_ulogic; + signal FCMAPUCONFIRMINSTR_ipd : std_ulogic; + signal FCMAPUCR_ipd : std_logic_vector(0 to 3); + signal FCMAPUDONE_ipd : std_ulogic; + signal FCMAPUEXCEPTION_ipd : std_ulogic; + signal FCMAPUFPSCRFEX_ipd : std_ulogic; + signal FCMAPURESULT_ipd : std_logic_vector(0 to 31); + signal FCMAPURESULTVALID_ipd : std_ulogic; + signal FCMAPUSLEEPNOTREADY_ipd : std_ulogic; + signal FCMAPUSTOREDATA_ipd : std_logic_vector(0 to 127); + signal JTGC440TCK_ipd : std_ulogic; + signal JTGC440TDI_ipd : std_ulogic; + signal JTGC440TMS_ipd : std_ulogic; + signal JTGC440TRSTNEG_ipd : std_ulogic; + signal MCMIADDRREADYTOACCEPT_ipd : std_ulogic; + signal MCMIREADDATA_ipd : std_logic_vector(0 to 127); + signal MCMIREADDATAERR_ipd : std_ulogic; + signal MCMIREADDATAVALID_ipd : std_ulogic; + signal RSTC440RESETCHIP_ipd : std_ulogic; + signal RSTC440RESETCORE_ipd : std_ulogic; + signal RSTC440RESETSYSTEM_ipd : std_ulogic; + signal TIEC440DCURDLDCACHEPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440DCURDNONCACHEPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440DCURDTOUCHPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440DCURDURGENTPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440DCUWRFLUSHPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440DCUWRSTOREPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440DCUWRURGENTPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440ENDIANRESET_ipd : std_ulogic; + signal TIEC440ERPNRESET_ipd : std_logic_vector(0 to 3); + signal TIEC440ICURDFETCHPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440ICURDSPECPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440ICURDTOUCHPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440PIR_ipd : std_logic_vector(28 to 31); + signal TIEC440PVR_ipd : std_logic_vector(28 to 31); + signal TIEC440USERRESET_ipd : std_logic_vector(0 to 3); + signal TRCC440TRACEDISABLE_ipd : std_ulogic; + signal TRCC440TRIGGEREVENTIN_ipd : std_ulogic; + + + signal PLBPPCS0RNW_indelay : std_ulogic; + signal PLBPPCS1RNW_indelay : std_ulogic; + signal CPMDCRCLK_indelay : std_ulogic; + signal CPMDMA0LLCLK_indelay : std_ulogic; + signal CPMDMA1LLCLK_indelay : std_ulogic; + signal CPMDMA2LLCLK_indelay : std_ulogic; + signal CPMDMA3LLCLK_indelay : std_ulogic; + signal CPMINTERCONNECTCLKNTO1_indelay : std_ulogic; + signal CPMPPCMPLBCLK_indelay : std_ulogic; + signal CPMPPCS0PLBCLK_indelay : std_ulogic; + signal CPMPPCS1PLBCLK_indelay : std_ulogic; + signal DCRPPCDMACK_indelay : std_ulogic; + signal DCRPPCDMDBUSIN_indelay : std_logic_vector(0 to 31); + signal DCRPPCDMTIMEOUTWAIT_indelay : std_ulogic; + signal LLDMA0RSTENGINEREQ_indelay : std_ulogic; + signal LLDMA0RXD_indelay : std_logic_vector(0 to 31); + signal LLDMA0RXEOFN_indelay : std_ulogic; + signal LLDMA0RXEOPN_indelay : std_ulogic; + signal LLDMA0RXREM_indelay : std_logic_vector(0 to 3); + signal LLDMA0RXSOFN_indelay : std_ulogic; + signal LLDMA0RXSOPN_indelay : std_ulogic; + signal LLDMA0RXSRCRDYN_indelay : std_ulogic; + signal LLDMA0TXDSTRDYN_indelay : std_ulogic; + signal LLDMA1RSTENGINEREQ_indelay : std_ulogic; + signal LLDMA1RXD_indelay : std_logic_vector(0 to 31); + signal LLDMA1RXEOFN_indelay : std_ulogic; + signal LLDMA1RXEOPN_indelay : std_ulogic; + signal LLDMA1RXREM_indelay : std_logic_vector(0 to 3); + signal LLDMA1RXSOFN_indelay : std_ulogic; + signal LLDMA1RXSOPN_indelay : std_ulogic; + signal LLDMA1RXSRCRDYN_indelay : std_ulogic; + signal LLDMA1TXDSTRDYN_indelay : std_ulogic; + signal LLDMA2RSTENGINEREQ_indelay : std_ulogic; + signal LLDMA2RXD_indelay : std_logic_vector(0 to 31); + signal LLDMA2RXEOFN_indelay : std_ulogic; + signal LLDMA2RXEOPN_indelay : std_ulogic; + signal LLDMA2RXREM_indelay : std_logic_vector(0 to 3); + signal LLDMA2RXSOFN_indelay : std_ulogic; + signal LLDMA2RXSOPN_indelay : std_ulogic; + signal LLDMA2RXSRCRDYN_indelay : std_ulogic; + signal LLDMA2TXDSTRDYN_indelay : std_ulogic; + signal LLDMA3RSTENGINEREQ_indelay : std_ulogic; + signal LLDMA3RXD_indelay : std_logic_vector(0 to 31); + signal LLDMA3RXEOFN_indelay : std_ulogic; + signal LLDMA3RXEOPN_indelay : std_ulogic; + signal LLDMA3RXREM_indelay : std_logic_vector(0 to 3); + signal LLDMA3RXSOFN_indelay : std_ulogic; + signal LLDMA3RXSOPN_indelay : std_ulogic; + signal LLDMA3RXSRCRDYN_indelay : std_ulogic; + signal LLDMA3TXDSTRDYN_indelay : std_ulogic; + signal PLBPPCMADDRACK_indelay : std_ulogic; + signal PLBPPCMMBUSY_indelay : std_ulogic; + signal PLBPPCMMIRQ_indelay : std_ulogic; + signal PLBPPCMMRDERR_indelay : std_ulogic; + signal PLBPPCMMWRERR_indelay : std_ulogic; + signal PLBPPCMRDBTERM_indelay : std_ulogic; + signal PLBPPCMRDDACK_indelay : std_ulogic; + signal PLBPPCMRDDBUS_indelay : std_logic_vector(0 to 127); + signal PLBPPCMRDPENDPRI_indelay : std_logic_vector(0 to 1); + signal PLBPPCMRDPENDREQ_indelay : std_ulogic; + signal PLBPPCMRDWDADDR_indelay : std_logic_vector(0 to 3); + signal PLBPPCMREARBITRATE_indelay : std_ulogic; + signal PLBPPCMREQPRI_indelay : std_logic_vector(0 to 1); + signal PLBPPCMSSIZE_indelay : std_logic_vector(0 to 1); + signal PLBPPCMTIMEOUT_indelay : std_ulogic; + signal PLBPPCMWRBTERM_indelay : std_ulogic; + signal PLBPPCMWRDACK_indelay : std_ulogic; + signal PLBPPCMWRPENDPRI_indelay : std_logic_vector(0 to 1); + signal PLBPPCMWRPENDREQ_indelay : std_ulogic; + signal PLBPPCS0ABORT_indelay : std_ulogic; + signal PLBPPCS0ABUS_indelay : std_logic_vector(0 to 31); + signal PLBPPCS0BE_indelay : std_logic_vector(0 to 15); + signal PLBPPCS0BUSLOCK_indelay : std_ulogic; + signal PLBPPCS0LOCKERR_indelay : std_ulogic; + signal PLBPPCS0MASTERID_indelay : std_logic_vector(0 to 1); + signal PLBPPCS0MSIZE_indelay : std_logic_vector(0 to 1); + signal PLBPPCS0PAVALID_indelay : std_ulogic; + signal PLBPPCS0RDBURST_indelay : std_ulogic; + signal PLBPPCS0RDPENDPRI_indelay : std_logic_vector(0 to 1); + signal PLBPPCS0RDPENDREQ_indelay : std_ulogic; + signal PLBPPCS0RDPRIM_indelay : std_ulogic; + signal PLBPPCS0REQPRI_indelay : std_logic_vector(0 to 1); + signal PLBPPCS0SAVALID_indelay : std_ulogic; + signal PLBPPCS0SIZE_indelay : std_logic_vector(0 to 3); + signal PLBPPCS0TATTRIBUTE_indelay : std_logic_vector(0 to 15); + signal PLBPPCS0TYPE_indelay : std_logic_vector(0 to 2); + signal PLBPPCS0UABUS_indelay : std_logic_vector(28 to 31); + signal PLBPPCS0WRBURST_indelay : std_ulogic; + signal PLBPPCS0WRDBUS_indelay : std_logic_vector(0 to 127); + signal PLBPPCS0WRPENDPRI_indelay : std_logic_vector(0 to 1); + signal PLBPPCS0WRPENDREQ_indelay : std_ulogic; + signal PLBPPCS0WRPRIM_indelay : std_ulogic; + signal PLBPPCS1ABORT_indelay : std_ulogic; + signal PLBPPCS1ABUS_indelay : std_logic_vector(0 to 31); + signal PLBPPCS1BE_indelay : std_logic_vector(0 to 15); + signal PLBPPCS1BUSLOCK_indelay : std_ulogic; + signal PLBPPCS1LOCKERR_indelay : std_ulogic; + signal PLBPPCS1MASTERID_indelay : std_logic_vector(0 to 1); + signal PLBPPCS1MSIZE_indelay : std_logic_vector(0 to 1); + signal PLBPPCS1PAVALID_indelay : std_ulogic; + signal PLBPPCS1RDBURST_indelay : std_ulogic; + signal PLBPPCS1RDPENDPRI_indelay : std_logic_vector(0 to 1); + signal PLBPPCS1RDPENDREQ_indelay : std_ulogic; + signal PLBPPCS1RDPRIM_indelay : std_ulogic; + signal PLBPPCS1REQPRI_indelay : std_logic_vector(0 to 1); + signal PLBPPCS1SAVALID_indelay : std_ulogic; + signal PLBPPCS1SIZE_indelay : std_logic_vector(0 to 3); + signal PLBPPCS1TATTRIBUTE_indelay : std_logic_vector(0 to 15); + signal PLBPPCS1TYPE_indelay : std_logic_vector(0 to 2); + signal PLBPPCS1UABUS_indelay : std_logic_vector(28 to 31); + signal PLBPPCS1WRBURST_indelay : std_ulogic; + signal PLBPPCS1WRDBUS_indelay : std_logic_vector(0 to 127); + signal PLBPPCS1WRPENDPRI_indelay : std_logic_vector(0 to 1); + signal PLBPPCS1WRPENDREQ_indelay : std_ulogic; + signal PLBPPCS1WRPRIM_indelay : std_ulogic; + signal TIEDCRBASEADDR_indelay : std_logic_vector(0 to 1); + signal CPMC440CLK_indelay : std_ulogic; + signal CPMC440CLKEN_indelay : std_ulogic; + signal CPMC440CORECLOCKINACTIVE_indelay : std_ulogic; + signal CPMC440TIMERCLOCK_indelay : std_ulogic; + signal CPMFCMCLK_indelay : std_ulogic; + signal CPMINTERCONNECTCLK_indelay : std_ulogic; + signal CPMINTERCONNECTCLKEN_indelay : std_ulogic; + signal CPMMCCLK_indelay : std_ulogic; + signal DBGC440DEBUGHALT_indelay : std_ulogic; + signal DBGC440SYSTEMSTATUS_indelay : std_logic_vector(0 to 4); + signal DBGC440UNCONDDEBUGEVENT_indelay : std_ulogic; + signal DCRPPCDSABUS_indelay : std_logic_vector(0 to 9); + signal DCRPPCDSDBUSOUT_indelay : std_logic_vector(0 to 31); + signal DCRPPCDSREAD_indelay : std_ulogic; + signal DCRPPCDSWRITE_indelay : std_ulogic; + signal EICC440CRITIRQ_indelay : std_ulogic; + signal EICC440EXTIRQ_indelay : std_ulogic; + signal FCMAPUCONFIRMINSTR_indelay : std_ulogic; + signal FCMAPUCR_indelay : std_logic_vector(0 to 3); + signal FCMAPUDONE_indelay : std_ulogic; + signal FCMAPUEXCEPTION_indelay : std_ulogic; + signal FCMAPUFPSCRFEX_indelay : std_ulogic; + signal FCMAPURESULT_indelay : std_logic_vector(0 to 31); + signal FCMAPURESULTVALID_indelay : std_ulogic; + signal FCMAPUSLEEPNOTREADY_indelay : std_ulogic; + signal FCMAPUSTOREDATA_indelay : std_logic_vector(0 to 127); + signal JTGC440TCK_indelay : std_ulogic; + signal JTGC440TDI_indelay : std_ulogic; + signal JTGC440TMS_indelay : std_ulogic; + signal JTGC440TRSTNEG_indelay : std_ulogic; + signal MCMIADDRREADYTOACCEPT_indelay : std_ulogic; + signal MCMIREADDATA_indelay : std_logic_vector(0 to 127); + signal MCMIREADDATAERR_indelay : std_ulogic; + signal MCMIREADDATAVALID_indelay : std_ulogic; + signal RSTC440RESETCHIP_indelay : std_ulogic; + signal RSTC440RESETCORE_indelay : std_ulogic; + signal RSTC440RESETSYSTEM_indelay : std_ulogic; + signal TIEC440DCURDLDCACHEPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440DCURDNONCACHEPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440DCURDTOUCHPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440DCURDURGENTPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440DCUWRFLUSHPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440DCUWRSTOREPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440DCUWRURGENTPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440ENDIANRESET_indelay : std_ulogic; + signal TIEC440ERPNRESET_indelay : std_logic_vector(0 to 3); + signal TIEC440ICURDFETCHPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440ICURDSPECPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440ICURDTOUCHPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440PIR_indelay : std_logic_vector(28 to 31); + signal TIEC440PVR_indelay : std_logic_vector(28 to 31); + signal TIEC440USERRESET_indelay : std_logic_vector(0 to 3); + signal TRCC440TRACEDISABLE_indelay : std_ulogic; + signal TRCC440TRIGGEREVENTIN_indelay : std_ulogic; + +begin + + + APUFCMDECFPUOP_out <= APUFCMDECFPUOP_outdelay after OUT_DELAY; + APUFCMDECLDSTXFERSIZE_out <= APUFCMDECLDSTXFERSIZE_outdelay after OUT_DELAY; + APUFCMDECLOAD_out <= APUFCMDECLOAD_outdelay after OUT_DELAY; + APUFCMDECNONAUTON_out <= APUFCMDECNONAUTON_outdelay after OUT_DELAY; + APUFCMDECSTORE_out <= APUFCMDECSTORE_outdelay after OUT_DELAY; + APUFCMDECUDIVALID_out <= APUFCMDECUDIVALID_outdelay after OUT_DELAY; + APUFCMDECUDI_out <= APUFCMDECUDI_outdelay after OUT_DELAY; + APUFCMENDIAN_out <= APUFCMENDIAN_outdelay after OUT_DELAY; + APUFCMFLUSH_out <= APUFCMFLUSH_outdelay after OUT_DELAY; + APUFCMINSTRUCTION_out <= APUFCMINSTRUCTION_outdelay after OUT_DELAY; + APUFCMINSTRVALID_out <= APUFCMINSTRVALID_outdelay after OUT_DELAY; + APUFCMLOADBYTEADDR_out <= APUFCMLOADBYTEADDR_outdelay after OUT_DELAY; + APUFCMLOADDATA_out <= APUFCMLOADDATA_outdelay after OUT_DELAY; + APUFCMLOADDVALID_out <= APUFCMLOADDVALID_outdelay after OUT_DELAY; + APUFCMMSRFE0_out <= APUFCMMSRFE0_outdelay after OUT_DELAY; + APUFCMMSRFE1_out <= APUFCMMSRFE1_outdelay after OUT_DELAY; + APUFCMNEXTINSTRREADY_out <= APUFCMNEXTINSTRREADY_outdelay after OUT_DELAY; + APUFCMOPERANDVALID_out <= APUFCMOPERANDVALID_outdelay after OUT_DELAY; + APUFCMRADATA_out <= APUFCMRADATA_outdelay after OUT_DELAY; + APUFCMRBDATA_out <= APUFCMRBDATA_outdelay after OUT_DELAY; + APUFCMWRITEBACKOK_out <= APUFCMWRITEBACKOK_outdelay after OUT_DELAY; + C440CPMCORESLEEPREQ_out <= C440CPMCORESLEEPREQ_outdelay after OUT_DELAY; + C440CPMDECIRPTREQ_out <= C440CPMDECIRPTREQ_outdelay after OUT_DELAY; + C440CPMFITIRPTREQ_out <= C440CPMFITIRPTREQ_outdelay after OUT_DELAY; + C440CPMMSRCE_out <= C440CPMMSRCE_outdelay after OUT_DELAY; + C440CPMMSREE_out <= C440CPMMSREE_outdelay after OUT_DELAY; + C440CPMTIMERRESETREQ_out <= C440CPMTIMERRESETREQ_outdelay after OUT_DELAY; + C440CPMWDIRPTREQ_out <= C440CPMWDIRPTREQ_outdelay after OUT_DELAY; + C440DBGSYSTEMCONTROL_out <= C440DBGSYSTEMCONTROL_outdelay after OUT_DELAY; + C440JTGTDOEN_out <= C440JTGTDOEN_outdelay after OUT_DELAY; + C440JTGTDO_out <= C440JTGTDO_outdelay after OUT_DELAY; + C440MACHINECHECK_out <= C440MACHINECHECK_outdelay after OUT_DELAY; + C440RSTCHIPRESETREQ_out <= C440RSTCHIPRESETREQ_outdelay after OUT_DELAY; + C440RSTCORERESETREQ_out <= C440RSTCORERESETREQ_outdelay after OUT_DELAY; + C440RSTSYSTEMRESETREQ_out <= C440RSTSYSTEMRESETREQ_outdelay after OUT_DELAY; + C440TRCBRANCHSTATUS_out <= C440TRCBRANCHSTATUS_outdelay after OUT_DELAY; + C440TRCCYCLE_out <= C440TRCCYCLE_outdelay after OUT_DELAY; + C440TRCEXECUTIONSTATUS_out <= C440TRCEXECUTIONSTATUS_outdelay after OUT_DELAY; + C440TRCTRACESTATUS_out <= C440TRCTRACESTATUS_outdelay after OUT_DELAY; + C440TRCTRIGGEREVENTOUT_out <= C440TRCTRIGGEREVENTOUT_outdelay after OUT_DELAY; + C440TRCTRIGGEREVENTTYPE_out <= C440TRCTRIGGEREVENTTYPE_outdelay after OUT_DELAY; + DMA0LLRSTENGINEACK_out <= DMA0LLRSTENGINEACK_outdelay after OUT_DELAY; + DMA0LLRXDSTRDYN_out <= DMA0LLRXDSTRDYN_outdelay after OUT_DELAY; + DMA0LLTXD_out <= DMA0LLTXD_outdelay after OUT_DELAY; + DMA0LLTXEOFN_out <= DMA0LLTXEOFN_outdelay after OUT_DELAY; + DMA0LLTXEOPN_out <= DMA0LLTXEOPN_outdelay after OUT_DELAY; + DMA0LLTXREM_out <= DMA0LLTXREM_outdelay after OUT_DELAY; + DMA0LLTXSOFN_out <= DMA0LLTXSOFN_outdelay after OUT_DELAY; + DMA0LLTXSOPN_out <= DMA0LLTXSOPN_outdelay after OUT_DELAY; + DMA0LLTXSRCRDYN_out <= DMA0LLTXSRCRDYN_outdelay after OUT_DELAY; + DMA0RXIRQ_out <= DMA0RXIRQ_outdelay after OUT_DELAY; + DMA0TXIRQ_out <= DMA0TXIRQ_outdelay after OUT_DELAY; + DMA1LLRSTENGINEACK_out <= DMA1LLRSTENGINEACK_outdelay after OUT_DELAY; + DMA1LLRXDSTRDYN_out <= DMA1LLRXDSTRDYN_outdelay after OUT_DELAY; + DMA1LLTXD_out <= DMA1LLTXD_outdelay after OUT_DELAY; + DMA1LLTXEOFN_out <= DMA1LLTXEOFN_outdelay after OUT_DELAY; + DMA1LLTXEOPN_out <= DMA1LLTXEOPN_outdelay after OUT_DELAY; + DMA1LLTXREM_out <= DMA1LLTXREM_outdelay after OUT_DELAY; + DMA1LLTXSOFN_out <= DMA1LLTXSOFN_outdelay after OUT_DELAY; + DMA1LLTXSOPN_out <= DMA1LLTXSOPN_outdelay after OUT_DELAY; + DMA1LLTXSRCRDYN_out <= DMA1LLTXSRCRDYN_outdelay after OUT_DELAY; + DMA1RXIRQ_out <= DMA1RXIRQ_outdelay after OUT_DELAY; + DMA1TXIRQ_out <= DMA1TXIRQ_outdelay after OUT_DELAY; + DMA2LLRSTENGINEACK_out <= DMA2LLRSTENGINEACK_outdelay after OUT_DELAY; + DMA2LLRXDSTRDYN_out <= DMA2LLRXDSTRDYN_outdelay after OUT_DELAY; + DMA2LLTXD_out <= DMA2LLTXD_outdelay after OUT_DELAY; + DMA2LLTXEOFN_out <= DMA2LLTXEOFN_outdelay after OUT_DELAY; + DMA2LLTXEOPN_out <= DMA2LLTXEOPN_outdelay after OUT_DELAY; + DMA2LLTXREM_out <= DMA2LLTXREM_outdelay after OUT_DELAY; + DMA2LLTXSOFN_out <= DMA2LLTXSOFN_outdelay after OUT_DELAY; + DMA2LLTXSOPN_out <= DMA2LLTXSOPN_outdelay after OUT_DELAY; + DMA2LLTXSRCRDYN_out <= DMA2LLTXSRCRDYN_outdelay after OUT_DELAY; + DMA2RXIRQ_out <= DMA2RXIRQ_outdelay after OUT_DELAY; + DMA2TXIRQ_out <= DMA2TXIRQ_outdelay after OUT_DELAY; + DMA3LLRSTENGINEACK_out <= DMA3LLRSTENGINEACK_outdelay after OUT_DELAY; + DMA3LLRXDSTRDYN_out <= DMA3LLRXDSTRDYN_outdelay after OUT_DELAY; + DMA3LLTXD_out <= DMA3LLTXD_outdelay after OUT_DELAY; + DMA3LLTXEOFN_out <= DMA3LLTXEOFN_outdelay after OUT_DELAY; + DMA3LLTXEOPN_out <= DMA3LLTXEOPN_outdelay after OUT_DELAY; + DMA3LLTXREM_out <= DMA3LLTXREM_outdelay after OUT_DELAY; + DMA3LLTXSOFN_out <= DMA3LLTXSOFN_outdelay after OUT_DELAY; + DMA3LLTXSOPN_out <= DMA3LLTXSOPN_outdelay after OUT_DELAY; + DMA3LLTXSRCRDYN_out <= DMA3LLTXSRCRDYN_outdelay after OUT_DELAY; + DMA3RXIRQ_out <= DMA3RXIRQ_outdelay after OUT_DELAY; + DMA3TXIRQ_out <= DMA3TXIRQ_outdelay after OUT_DELAY; + MIMCADDRESSVALID_out <= MIMCADDRESSVALID_outdelay after OUT_DELAY; + MIMCADDRESS_out <= MIMCADDRESS_outdelay after OUT_DELAY; + MIMCBANKCONFLICT_out <= MIMCBANKCONFLICT_outdelay after OUT_DELAY; + MIMCBYTEENABLE_out <= MIMCBYTEENABLE_outdelay after OUT_DELAY; + MIMCREADNOTWRITE_out <= MIMCREADNOTWRITE_outdelay after OUT_DELAY; + MIMCROWCONFLICT_out <= MIMCROWCONFLICT_outdelay after OUT_DELAY; + MIMCWRITEDATAVALID_out <= MIMCWRITEDATAVALID_outdelay after OUT_DELAY; + MIMCWRITEDATA_out <= MIMCWRITEDATA_outdelay after OUT_DELAY; + PPCCPMINTERCONNECTBUSY_out <= PPCCPMINTERCONNECTBUSY_outdelay after OUT_DELAY; + PPCDMDCRABUS_out <= PPCDMDCRABUS_outdelay after OUT_DELAY; + PPCDMDCRDBUSOUT_out <= PPCDMDCRDBUSOUT_outdelay after OUT_DELAY; + PPCDMDCRREAD_out <= PPCDMDCRREAD_outdelay after OUT_DELAY; + PPCDMDCRUABUS_out <= PPCDMDCRUABUS_outdelay after OUT_DELAY; + PPCDMDCRWRITE_out <= PPCDMDCRWRITE_outdelay after OUT_DELAY; + PPCDSDCRACK_out <= PPCDSDCRACK_outdelay after OUT_DELAY; + PPCDSDCRDBUSIN_out <= PPCDSDCRDBUSIN_outdelay after OUT_DELAY; + PPCDSDCRTIMEOUTWAIT_out <= PPCDSDCRTIMEOUTWAIT_outdelay after OUT_DELAY; + PPCEICINTERCONNECTIRQ_out <= PPCEICINTERCONNECTIRQ_outdelay after OUT_DELAY; + PPCMPLBABORT_out <= PPCMPLBABORT_outdelay after OUT_DELAY; + PPCMPLBABUS_out <= PPCMPLBABUS_outdelay after OUT_DELAY; + PPCMPLBBE_out <= PPCMPLBBE_outdelay after OUT_DELAY; + PPCMPLBBUSLOCK_out <= PPCMPLBBUSLOCK_outdelay after OUT_DELAY; + PPCMPLBLOCKERR_out <= PPCMPLBLOCKERR_outdelay after OUT_DELAY; + PPCMPLBPRIORITY_out <= PPCMPLBPRIORITY_outdelay after OUT_DELAY; + PPCMPLBRDBURST_out <= PPCMPLBRDBURST_outdelay after OUT_DELAY; + PPCMPLBREQUEST_out <= PPCMPLBREQUEST_outdelay after OUT_DELAY; + PPCMPLBRNW_out <= PPCMPLBRNW_outdelay after OUT_DELAY; + PPCMPLBSIZE_out <= PPCMPLBSIZE_outdelay after OUT_DELAY; + PPCMPLBTATTRIBUTE_out <= PPCMPLBTATTRIBUTE_outdelay after OUT_DELAY; + PPCMPLBTYPE_out <= PPCMPLBTYPE_outdelay after OUT_DELAY; + PPCMPLBUABUS_out <= PPCMPLBUABUS_outdelay after OUT_DELAY; + PPCMPLBWRBURST_out <= PPCMPLBWRBURST_outdelay after OUT_DELAY; + PPCMPLBWRDBUS_out <= PPCMPLBWRDBUS_outdelay after OUT_DELAY; + PPCS0PLBADDRACK_out <= PPCS0PLBADDRACK_outdelay after OUT_DELAY; + PPCS0PLBMBUSY_out <= PPCS0PLBMBUSY_outdelay after OUT_DELAY; + PPCS0PLBMIRQ_out <= PPCS0PLBMIRQ_outdelay after OUT_DELAY; + PPCS0PLBMRDERR_out <= PPCS0PLBMRDERR_outdelay after OUT_DELAY; + PPCS0PLBMWRERR_out <= PPCS0PLBMWRERR_outdelay after OUT_DELAY; + PPCS0PLBRDBTERM_out <= PPCS0PLBRDBTERM_outdelay after OUT_DELAY; + PPCS0PLBRDCOMP_out <= PPCS0PLBRDCOMP_outdelay after OUT_DELAY; + PPCS0PLBRDDACK_out <= PPCS0PLBRDDACK_outdelay after OUT_DELAY; + PPCS0PLBRDDBUS_out <= PPCS0PLBRDDBUS_outdelay after OUT_DELAY; + PPCS0PLBRDWDADDR_out <= PPCS0PLBRDWDADDR_outdelay after OUT_DELAY; + PPCS0PLBREARBITRATE_out <= PPCS0PLBREARBITRATE_outdelay after OUT_DELAY; + PPCS0PLBSSIZE_out <= PPCS0PLBSSIZE_outdelay after OUT_DELAY; + PPCS0PLBWAIT_out <= PPCS0PLBWAIT_outdelay after OUT_DELAY; + PPCS0PLBWRBTERM_out <= PPCS0PLBWRBTERM_outdelay after OUT_DELAY; + PPCS0PLBWRCOMP_out <= PPCS0PLBWRCOMP_outdelay after OUT_DELAY; + PPCS0PLBWRDACK_out <= PPCS0PLBWRDACK_outdelay after OUT_DELAY; + PPCS1PLBADDRACK_out <= PPCS1PLBADDRACK_outdelay after OUT_DELAY; + PPCS1PLBMBUSY_out <= PPCS1PLBMBUSY_outdelay after OUT_DELAY; + PPCS1PLBMIRQ_out <= PPCS1PLBMIRQ_outdelay after OUT_DELAY; + PPCS1PLBMRDERR_out <= PPCS1PLBMRDERR_outdelay after OUT_DELAY; + PPCS1PLBMWRERR_out <= PPCS1PLBMWRERR_outdelay after OUT_DELAY; + PPCS1PLBRDBTERM_out <= PPCS1PLBRDBTERM_outdelay after OUT_DELAY; + PPCS1PLBRDCOMP_out <= PPCS1PLBRDCOMP_outdelay after OUT_DELAY; + PPCS1PLBRDDACK_out <= PPCS1PLBRDDACK_outdelay after OUT_DELAY; + PPCS1PLBRDDBUS_out <= PPCS1PLBRDDBUS_outdelay after OUT_DELAY; + PPCS1PLBRDWDADDR_out <= PPCS1PLBRDWDADDR_outdelay after OUT_DELAY; + PPCS1PLBREARBITRATE_out <= PPCS1PLBREARBITRATE_outdelay after OUT_DELAY; + PPCS1PLBSSIZE_out <= PPCS1PLBSSIZE_outdelay after OUT_DELAY; + PPCS1PLBWAIT_out <= PPCS1PLBWAIT_outdelay after OUT_DELAY; + PPCS1PLBWRBTERM_out <= PPCS1PLBWRBTERM_outdelay after OUT_DELAY; + PPCS1PLBWRCOMP_out <= PPCS1PLBWRCOMP_outdelay after OUT_DELAY; + PPCS1PLBWRDACK_out <= PPCS1PLBWRDACK_outdelay after OUT_DELAY; + + CPMC440CLK_ipd <= CPMC440CLK after ZERO_DELAY; + CPMC440TIMERCLOCK_ipd <= CPMC440TIMERCLOCK after ZERO_DELAY; + CPMDCRCLK_ipd <= CPMDCRCLK after ZERO_DELAY; + CPMDMA0LLCLK_ipd <= CPMDMA0LLCLK after ZERO_DELAY; + CPMDMA1LLCLK_ipd <= CPMDMA1LLCLK after ZERO_DELAY; + CPMDMA2LLCLK_ipd <= CPMDMA2LLCLK after ZERO_DELAY; + CPMDMA3LLCLK_ipd <= CPMDMA3LLCLK after ZERO_DELAY; + CPMFCMCLK_ipd <= CPMFCMCLK after ZERO_DELAY; + CPMINTERCONNECTCLK_ipd <= CPMINTERCONNECTCLK after ZERO_DELAY; + CPMMCCLK_ipd <= CPMMCCLK after ZERO_DELAY; + CPMPPCMPLBCLK_ipd <= CPMPPCMPLBCLK after ZERO_DELAY; + CPMPPCS0PLBCLK_ipd <= CPMPPCS0PLBCLK after ZERO_DELAY; + CPMPPCS1PLBCLK_ipd <= CPMPPCS1PLBCLK after ZERO_DELAY; + JTGC440TCK_ipd <= JTGC440TCK after ZERO_DELAY; + + CPMC440CLKEN_ipd <= CPMC440CLKEN after ZERO_DELAY; + CPMC440CORECLOCKINACTIVE_ipd <= CPMC440CORECLOCKINACTIVE after ZERO_DELAY; + CPMINTERCONNECTCLKEN_ipd <= CPMINTERCONNECTCLKEN after ZERO_DELAY; + CPMINTERCONNECTCLKNTO1_ipd <= CPMINTERCONNECTCLKNTO1 after ZERO_DELAY; + DBGC440DEBUGHALT_ipd <= DBGC440DEBUGHALT after ZERO_DELAY; + DBGC440SYSTEMSTATUS_ipd <= DBGC440SYSTEMSTATUS after ZERO_DELAY; + DBGC440UNCONDDEBUGEVENT_ipd <= DBGC440UNCONDDEBUGEVENT after ZERO_DELAY; + DCRPPCDMACK_ipd <= DCRPPCDMACK after ZERO_DELAY; + DCRPPCDMDBUSIN_ipd <= DCRPPCDMDBUSIN after ZERO_DELAY; + DCRPPCDMTIMEOUTWAIT_ipd <= DCRPPCDMTIMEOUTWAIT after ZERO_DELAY; + DCRPPCDSABUS_ipd <= DCRPPCDSABUS after ZERO_DELAY; + DCRPPCDSDBUSOUT_ipd <= DCRPPCDSDBUSOUT after ZERO_DELAY; + DCRPPCDSREAD_ipd <= DCRPPCDSREAD after ZERO_DELAY; + DCRPPCDSWRITE_ipd <= DCRPPCDSWRITE after ZERO_DELAY; + EICC440CRITIRQ_ipd <= EICC440CRITIRQ after ZERO_DELAY; + EICC440EXTIRQ_ipd <= EICC440EXTIRQ after ZERO_DELAY; + FCMAPUCONFIRMINSTR_ipd <= FCMAPUCONFIRMINSTR after ZERO_DELAY; + FCMAPUCR_ipd <= FCMAPUCR after ZERO_DELAY; + FCMAPUDONE_ipd <= FCMAPUDONE after ZERO_DELAY; + FCMAPUEXCEPTION_ipd <= FCMAPUEXCEPTION after ZERO_DELAY; + FCMAPUFPSCRFEX_ipd <= FCMAPUFPSCRFEX after ZERO_DELAY; + FCMAPURESULTVALID_ipd <= FCMAPURESULTVALID after ZERO_DELAY; + FCMAPURESULT_ipd <= FCMAPURESULT after ZERO_DELAY; + FCMAPUSLEEPNOTREADY_ipd <= FCMAPUSLEEPNOTREADY after ZERO_DELAY; + FCMAPUSTOREDATA_ipd <= FCMAPUSTOREDATA after ZERO_DELAY; + JTGC440TDI_ipd <= JTGC440TDI after ZERO_DELAY; + JTGC440TMS_ipd <= JTGC440TMS after ZERO_DELAY; + JTGC440TRSTNEG_ipd <= JTGC440TRSTNEG after ZERO_DELAY; + LLDMA0RSTENGINEREQ_ipd <= LLDMA0RSTENGINEREQ after ZERO_DELAY; + LLDMA0RXD_ipd <= LLDMA0RXD after ZERO_DELAY; + LLDMA0RXEOFN_ipd <= LLDMA0RXEOFN after ZERO_DELAY; + LLDMA0RXEOPN_ipd <= LLDMA0RXEOPN after ZERO_DELAY; + LLDMA0RXREM_ipd <= LLDMA0RXREM after ZERO_DELAY; + LLDMA0RXSOFN_ipd <= LLDMA0RXSOFN after ZERO_DELAY; + LLDMA0RXSOPN_ipd <= LLDMA0RXSOPN after ZERO_DELAY; + LLDMA0RXSRCRDYN_ipd <= LLDMA0RXSRCRDYN after ZERO_DELAY; + LLDMA0TXDSTRDYN_ipd <= LLDMA0TXDSTRDYN after ZERO_DELAY; + LLDMA1RSTENGINEREQ_ipd <= LLDMA1RSTENGINEREQ after ZERO_DELAY; + LLDMA1RXD_ipd <= LLDMA1RXD after ZERO_DELAY; + LLDMA1RXEOFN_ipd <= LLDMA1RXEOFN after ZERO_DELAY; + LLDMA1RXEOPN_ipd <= LLDMA1RXEOPN after ZERO_DELAY; + LLDMA1RXREM_ipd <= LLDMA1RXREM after ZERO_DELAY; + LLDMA1RXSOFN_ipd <= LLDMA1RXSOFN after ZERO_DELAY; + LLDMA1RXSOPN_ipd <= LLDMA1RXSOPN after ZERO_DELAY; + LLDMA1RXSRCRDYN_ipd <= LLDMA1RXSRCRDYN after ZERO_DELAY; + LLDMA1TXDSTRDYN_ipd <= LLDMA1TXDSTRDYN after ZERO_DELAY; + LLDMA2RSTENGINEREQ_ipd <= LLDMA2RSTENGINEREQ after ZERO_DELAY; + LLDMA2RXD_ipd <= LLDMA2RXD after ZERO_DELAY; + LLDMA2RXEOFN_ipd <= LLDMA2RXEOFN after ZERO_DELAY; + LLDMA2RXEOPN_ipd <= LLDMA2RXEOPN after ZERO_DELAY; + LLDMA2RXREM_ipd <= LLDMA2RXREM after ZERO_DELAY; + LLDMA2RXSOFN_ipd <= LLDMA2RXSOFN after ZERO_DELAY; + LLDMA2RXSOPN_ipd <= LLDMA2RXSOPN after ZERO_DELAY; + LLDMA2RXSRCRDYN_ipd <= LLDMA2RXSRCRDYN after ZERO_DELAY; + LLDMA2TXDSTRDYN_ipd <= LLDMA2TXDSTRDYN after ZERO_DELAY; + LLDMA3RSTENGINEREQ_ipd <= LLDMA3RSTENGINEREQ after ZERO_DELAY; + LLDMA3RXD_ipd <= LLDMA3RXD after ZERO_DELAY; + LLDMA3RXEOFN_ipd <= LLDMA3RXEOFN after ZERO_DELAY; + LLDMA3RXEOPN_ipd <= LLDMA3RXEOPN after ZERO_DELAY; + LLDMA3RXREM_ipd <= LLDMA3RXREM after ZERO_DELAY; + LLDMA3RXSOFN_ipd <= LLDMA3RXSOFN after ZERO_DELAY; + LLDMA3RXSOPN_ipd <= LLDMA3RXSOPN after ZERO_DELAY; + LLDMA3RXSRCRDYN_ipd <= LLDMA3RXSRCRDYN after ZERO_DELAY; + LLDMA3TXDSTRDYN_ipd <= LLDMA3TXDSTRDYN after ZERO_DELAY; + MCMIADDRREADYTOACCEPT_ipd <= MCMIADDRREADYTOACCEPT after ZERO_DELAY; + MCMIREADDATAERR_ipd <= MCMIREADDATAERR after ZERO_DELAY; + MCMIREADDATAVALID_ipd <= MCMIREADDATAVALID after ZERO_DELAY; + MCMIREADDATA_ipd <= MCMIREADDATA after ZERO_DELAY; + PLBPPCMADDRACK_ipd <= PLBPPCMADDRACK after ZERO_DELAY; + PLBPPCMMBUSY_ipd <= PLBPPCMMBUSY after ZERO_DELAY; + PLBPPCMMIRQ_ipd <= PLBPPCMMIRQ after ZERO_DELAY; + PLBPPCMMRDERR_ipd <= PLBPPCMMRDERR after ZERO_DELAY; + PLBPPCMMWRERR_ipd <= PLBPPCMMWRERR after ZERO_DELAY; + PLBPPCMRDBTERM_ipd <= PLBPPCMRDBTERM after ZERO_DELAY; + PLBPPCMRDDACK_ipd <= PLBPPCMRDDACK after ZERO_DELAY; + PLBPPCMRDDBUS_ipd <= PLBPPCMRDDBUS after ZERO_DELAY; + PLBPPCMRDPENDPRI_ipd <= PLBPPCMRDPENDPRI after ZERO_DELAY; + PLBPPCMRDPENDREQ_ipd <= PLBPPCMRDPENDREQ after ZERO_DELAY; + PLBPPCMRDWDADDR_ipd <= PLBPPCMRDWDADDR after ZERO_DELAY; + PLBPPCMREARBITRATE_ipd <= PLBPPCMREARBITRATE after ZERO_DELAY; + PLBPPCMREQPRI_ipd <= PLBPPCMREQPRI after ZERO_DELAY; + PLBPPCMSSIZE_ipd <= PLBPPCMSSIZE after ZERO_DELAY; + PLBPPCMTIMEOUT_ipd <= PLBPPCMTIMEOUT after ZERO_DELAY; + PLBPPCMWRBTERM_ipd <= PLBPPCMWRBTERM after ZERO_DELAY; + PLBPPCMWRDACK_ipd <= PLBPPCMWRDACK after ZERO_DELAY; + PLBPPCMWRPENDPRI_ipd <= PLBPPCMWRPENDPRI after ZERO_DELAY; + PLBPPCMWRPENDREQ_ipd <= PLBPPCMWRPENDREQ after ZERO_DELAY; + PLBPPCS0ABORT_ipd <= PLBPPCS0ABORT after ZERO_DELAY; + PLBPPCS0ABUS_ipd <= PLBPPCS0ABUS after ZERO_DELAY; + PLBPPCS0BE_ipd <= PLBPPCS0BE after ZERO_DELAY; + PLBPPCS0BUSLOCK_ipd <= PLBPPCS0BUSLOCK after ZERO_DELAY; + PLBPPCS0LOCKERR_ipd <= PLBPPCS0LOCKERR after ZERO_DELAY; + PLBPPCS0MASTERID_ipd <= PLBPPCS0MASTERID after ZERO_DELAY; + PLBPPCS0MSIZE_ipd <= PLBPPCS0MSIZE after ZERO_DELAY; + PLBPPCS0PAVALID_ipd <= PLBPPCS0PAVALID after ZERO_DELAY; + PLBPPCS0RDBURST_ipd <= PLBPPCS0RDBURST after ZERO_DELAY; + PLBPPCS0RDPENDPRI_ipd <= PLBPPCS0RDPENDPRI after ZERO_DELAY; + PLBPPCS0RDPENDREQ_ipd <= PLBPPCS0RDPENDREQ after ZERO_DELAY; + PLBPPCS0RDPRIM_ipd <= PLBPPCS0RDPRIM after ZERO_DELAY; + PLBPPCS0REQPRI_ipd <= PLBPPCS0REQPRI after ZERO_DELAY; + PLBPPCS0RNW_ipd <= PLBPPCS0RNW after ZERO_DELAY; + PLBPPCS0SAVALID_ipd <= PLBPPCS0SAVALID after ZERO_DELAY; + PLBPPCS0SIZE_ipd <= PLBPPCS0SIZE after ZERO_DELAY; + PLBPPCS0TATTRIBUTE_ipd <= PLBPPCS0TATTRIBUTE after ZERO_DELAY; + PLBPPCS0TYPE_ipd <= PLBPPCS0TYPE after ZERO_DELAY; + PLBPPCS0UABUS_ipd <= PLBPPCS0UABUS after ZERO_DELAY; + PLBPPCS0WRBURST_ipd <= PLBPPCS0WRBURST after ZERO_DELAY; + PLBPPCS0WRDBUS_ipd <= PLBPPCS0WRDBUS after ZERO_DELAY; + PLBPPCS0WRPENDPRI_ipd <= PLBPPCS0WRPENDPRI after ZERO_DELAY; + PLBPPCS0WRPENDREQ_ipd <= PLBPPCS0WRPENDREQ after ZERO_DELAY; + PLBPPCS0WRPRIM_ipd <= PLBPPCS0WRPRIM after ZERO_DELAY; + PLBPPCS1ABORT_ipd <= PLBPPCS1ABORT after ZERO_DELAY; + PLBPPCS1ABUS_ipd <= PLBPPCS1ABUS after ZERO_DELAY; + PLBPPCS1BE_ipd <= PLBPPCS1BE after ZERO_DELAY; + PLBPPCS1BUSLOCK_ipd <= PLBPPCS1BUSLOCK after ZERO_DELAY; + PLBPPCS1LOCKERR_ipd <= PLBPPCS1LOCKERR after ZERO_DELAY; + PLBPPCS1MASTERID_ipd <= PLBPPCS1MASTERID after ZERO_DELAY; + PLBPPCS1MSIZE_ipd <= PLBPPCS1MSIZE after ZERO_DELAY; + PLBPPCS1PAVALID_ipd <= PLBPPCS1PAVALID after ZERO_DELAY; + PLBPPCS1RDBURST_ipd <= PLBPPCS1RDBURST after ZERO_DELAY; + PLBPPCS1RDPENDPRI_ipd <= PLBPPCS1RDPENDPRI after ZERO_DELAY; + PLBPPCS1RDPENDREQ_ipd <= PLBPPCS1RDPENDREQ after ZERO_DELAY; + PLBPPCS1RDPRIM_ipd <= PLBPPCS1RDPRIM after ZERO_DELAY; + PLBPPCS1REQPRI_ipd <= PLBPPCS1REQPRI after ZERO_DELAY; + PLBPPCS1RNW_ipd <= PLBPPCS1RNW after ZERO_DELAY; + PLBPPCS1SAVALID_ipd <= PLBPPCS1SAVALID after ZERO_DELAY; + PLBPPCS1SIZE_ipd <= PLBPPCS1SIZE after ZERO_DELAY; + PLBPPCS1TATTRIBUTE_ipd <= PLBPPCS1TATTRIBUTE after ZERO_DELAY; + PLBPPCS1TYPE_ipd <= PLBPPCS1TYPE after ZERO_DELAY; + PLBPPCS1UABUS_ipd <= PLBPPCS1UABUS after ZERO_DELAY; + PLBPPCS1WRBURST_ipd <= PLBPPCS1WRBURST after ZERO_DELAY; + PLBPPCS1WRDBUS_ipd <= PLBPPCS1WRDBUS after ZERO_DELAY; + PLBPPCS1WRPENDPRI_ipd <= PLBPPCS1WRPENDPRI after ZERO_DELAY; + PLBPPCS1WRPENDREQ_ipd <= PLBPPCS1WRPENDREQ after ZERO_DELAY; + PLBPPCS1WRPRIM_ipd <= PLBPPCS1WRPRIM after ZERO_DELAY; + RSTC440RESETCHIP_ipd <= RSTC440RESETCHIP after ZERO_DELAY; + RSTC440RESETCORE_ipd <= RSTC440RESETCORE after ZERO_DELAY; + RSTC440RESETSYSTEM_ipd <= RSTC440RESETSYSTEM after ZERO_DELAY; + TIEC440DCURDLDCACHEPLBPRIO_ipd <= TIEC440DCURDLDCACHEPLBPRIO after ZERO_DELAY; + TIEC440DCURDNONCACHEPLBPRIO_ipd <= TIEC440DCURDNONCACHEPLBPRIO after ZERO_DELAY; + TIEC440DCURDTOUCHPLBPRIO_ipd <= TIEC440DCURDTOUCHPLBPRIO after ZERO_DELAY; + TIEC440DCURDURGENTPLBPRIO_ipd <= TIEC440DCURDURGENTPLBPRIO after ZERO_DELAY; + TIEC440DCUWRFLUSHPLBPRIO_ipd <= TIEC440DCUWRFLUSHPLBPRIO after ZERO_DELAY; + TIEC440DCUWRSTOREPLBPRIO_ipd <= TIEC440DCUWRSTOREPLBPRIO after ZERO_DELAY; + TIEC440DCUWRURGENTPLBPRIO_ipd <= TIEC440DCUWRURGENTPLBPRIO after ZERO_DELAY; + TIEC440ENDIANRESET_ipd <= TIEC440ENDIANRESET after ZERO_DELAY; + TIEC440ERPNRESET_ipd <= TIEC440ERPNRESET after ZERO_DELAY; + TIEC440ICURDFETCHPLBPRIO_ipd <= TIEC440ICURDFETCHPLBPRIO after ZERO_DELAY; + TIEC440ICURDSPECPLBPRIO_ipd <= TIEC440ICURDSPECPLBPRIO after ZERO_DELAY; + TIEC440ICURDTOUCHPLBPRIO_ipd <= TIEC440ICURDTOUCHPLBPRIO after ZERO_DELAY; + TIEC440PIR_ipd <= TIEC440PIR after ZERO_DELAY; + TIEC440PVR_ipd <= TIEC440PVR after ZERO_DELAY; + TIEC440USERRESET_ipd <= TIEC440USERRESET after ZERO_DELAY; + TIEDCRBASEADDR_ipd <= TIEDCRBASEADDR after ZERO_DELAY; + TRCC440TRACEDISABLE_ipd <= TRCC440TRACEDISABLE after ZERO_DELAY; + TRCC440TRIGGEREVENTIN_ipd <= TRCC440TRIGGEREVENTIN after ZERO_DELAY; + + + CPMC440CLK_indelay <= CPMC440CLK_ipd after CLK_DELAY; + CPMC440TIMERCLOCK_indelay <= CPMC440TIMERCLOCK_ipd after CLK_DELAY; + CPMDCRCLK_indelay <= CPMDCRCLK_ipd after CLK_DELAY; + CPMDMA0LLCLK_indelay <= CPMDMA0LLCLK_ipd after CLK_DELAY; + CPMDMA1LLCLK_indelay <= CPMDMA1LLCLK_ipd after CLK_DELAY; + CPMDMA2LLCLK_indelay <= CPMDMA2LLCLK_ipd after CLK_DELAY; + CPMDMA3LLCLK_indelay <= CPMDMA3LLCLK_ipd after CLK_DELAY; + CPMFCMCLK_indelay <= CPMFCMCLK_ipd after CLK_DELAY; + CPMINTERCONNECTCLK_indelay <= CPMINTERCONNECTCLK_ipd after CLK_DELAY; + CPMMCCLK_indelay <= CPMMCCLK_ipd after CLK_DELAY; + CPMPPCMPLBCLK_indelay <= CPMPPCMPLBCLK_ipd after CLK_DELAY; + CPMPPCS0PLBCLK_indelay <= CPMPPCS0PLBCLK_ipd after CLK_DELAY; + CPMPPCS1PLBCLK_indelay <= CPMPPCS1PLBCLK_ipd after CLK_DELAY; + JTGC440TCK_indelay <= JTGC440TCK_ipd after CLK_DELAY; + + CPMC440CLKEN_indelay <= CPMC440CLKEN_ipd after IN_DELAY; + CPMC440CORECLOCKINACTIVE_indelay <= CPMC440CORECLOCKINACTIVE_ipd after IN_DELAY; + CPMINTERCONNECTCLKEN_indelay <= CPMINTERCONNECTCLKEN_ipd after IN_DELAY; + CPMINTERCONNECTCLKNTO1_indelay <= CPMINTERCONNECTCLKNTO1_ipd after IN_DELAY; + DBGC440DEBUGHALT_indelay <= DBGC440DEBUGHALT_ipd after IN_DELAY; + DBGC440SYSTEMSTATUS_indelay <= DBGC440SYSTEMSTATUS_ipd after IN_DELAY; + DBGC440UNCONDDEBUGEVENT_indelay <= DBGC440UNCONDDEBUGEVENT_ipd after IN_DELAY; + DCRPPCDMACK_indelay <= DCRPPCDMACK_ipd after IN_DELAY; + DCRPPCDMDBUSIN_indelay <= DCRPPCDMDBUSIN_ipd after IN_DELAY; + DCRPPCDMTIMEOUTWAIT_indelay <= DCRPPCDMTIMEOUTWAIT_ipd after IN_DELAY; + DCRPPCDSABUS_indelay <= DCRPPCDSABUS_ipd after IN_DELAY; + DCRPPCDSDBUSOUT_indelay <= DCRPPCDSDBUSOUT_ipd after IN_DELAY; + DCRPPCDSREAD_indelay <= DCRPPCDSREAD_ipd after IN_DELAY; + DCRPPCDSWRITE_indelay <= DCRPPCDSWRITE_ipd after IN_DELAY; + EICC440CRITIRQ_indelay <= EICC440CRITIRQ_ipd after IN_DELAY; + EICC440EXTIRQ_indelay <= EICC440EXTIRQ_ipd after IN_DELAY; + FCMAPUCONFIRMINSTR_indelay <= FCMAPUCONFIRMINSTR_ipd after IN_DELAY; + FCMAPUCR_indelay <= FCMAPUCR_ipd after IN_DELAY; + FCMAPUDONE_indelay <= FCMAPUDONE_ipd after IN_DELAY; + FCMAPUEXCEPTION_indelay <= FCMAPUEXCEPTION_ipd after IN_DELAY; + FCMAPUFPSCRFEX_indelay <= FCMAPUFPSCRFEX_ipd after IN_DELAY; + FCMAPURESULTVALID_indelay <= FCMAPURESULTVALID_ipd after IN_DELAY; + FCMAPURESULT_indelay <= FCMAPURESULT_ipd after IN_DELAY; + FCMAPUSLEEPNOTREADY_indelay <= FCMAPUSLEEPNOTREADY_ipd after IN_DELAY; + FCMAPUSTOREDATA_indelay <= FCMAPUSTOREDATA_ipd after IN_DELAY; + JTGC440TDI_indelay <= JTGC440TDI_ipd after IN_DELAY; + JTGC440TMS_indelay <= JTGC440TMS_ipd after IN_DELAY; + JTGC440TRSTNEG_indelay <= JTGC440TRSTNEG_ipd after IN_DELAY; + LLDMA0RSTENGINEREQ_indelay <= LLDMA0RSTENGINEREQ_ipd after IN_DELAY; + LLDMA0RXD_indelay <= LLDMA0RXD_ipd after IN_DELAY; + LLDMA0RXEOFN_indelay <= LLDMA0RXEOFN_ipd after IN_DELAY; + LLDMA0RXEOPN_indelay <= LLDMA0RXEOPN_ipd after IN_DELAY; + LLDMA0RXREM_indelay <= LLDMA0RXREM_ipd after IN_DELAY; + LLDMA0RXSOFN_indelay <= LLDMA0RXSOFN_ipd after IN_DELAY; + LLDMA0RXSOPN_indelay <= LLDMA0RXSOPN_ipd after IN_DELAY; + LLDMA0RXSRCRDYN_indelay <= LLDMA0RXSRCRDYN_ipd after IN_DELAY; + LLDMA0TXDSTRDYN_indelay <= LLDMA0TXDSTRDYN_ipd after IN_DELAY; + LLDMA1RSTENGINEREQ_indelay <= LLDMA1RSTENGINEREQ_ipd after IN_DELAY; + LLDMA1RXD_indelay <= LLDMA1RXD_ipd after IN_DELAY; + LLDMA1RXEOFN_indelay <= LLDMA1RXEOFN_ipd after IN_DELAY; + LLDMA1RXEOPN_indelay <= LLDMA1RXEOPN_ipd after IN_DELAY; + LLDMA1RXREM_indelay <= LLDMA1RXREM_ipd after IN_DELAY; + LLDMA1RXSOFN_indelay <= LLDMA1RXSOFN_ipd after IN_DELAY; + LLDMA1RXSOPN_indelay <= LLDMA1RXSOPN_ipd after IN_DELAY; + LLDMA1RXSRCRDYN_indelay <= LLDMA1RXSRCRDYN_ipd after IN_DELAY; + LLDMA1TXDSTRDYN_indelay <= LLDMA1TXDSTRDYN_ipd after IN_DELAY; + LLDMA2RSTENGINEREQ_indelay <= LLDMA2RSTENGINEREQ_ipd after IN_DELAY; + LLDMA2RXD_indelay <= LLDMA2RXD_ipd after IN_DELAY; + LLDMA2RXEOFN_indelay <= LLDMA2RXEOFN_ipd after IN_DELAY; + LLDMA2RXEOPN_indelay <= LLDMA2RXEOPN_ipd after IN_DELAY; + LLDMA2RXREM_indelay <= LLDMA2RXREM_ipd after IN_DELAY; + LLDMA2RXSOFN_indelay <= LLDMA2RXSOFN_ipd after IN_DELAY; + LLDMA2RXSOPN_indelay <= LLDMA2RXSOPN_ipd after IN_DELAY; + LLDMA2RXSRCRDYN_indelay <= LLDMA2RXSRCRDYN_ipd after IN_DELAY; + LLDMA2TXDSTRDYN_indelay <= LLDMA2TXDSTRDYN_ipd after IN_DELAY; + LLDMA3RSTENGINEREQ_indelay <= LLDMA3RSTENGINEREQ_ipd after IN_DELAY; + LLDMA3RXD_indelay <= LLDMA3RXD_ipd after IN_DELAY; + LLDMA3RXEOFN_indelay <= LLDMA3RXEOFN_ipd after IN_DELAY; + LLDMA3RXEOPN_indelay <= LLDMA3RXEOPN_ipd after IN_DELAY; + LLDMA3RXREM_indelay <= LLDMA3RXREM_ipd after IN_DELAY; + LLDMA3RXSOFN_indelay <= LLDMA3RXSOFN_ipd after IN_DELAY; + LLDMA3RXSOPN_indelay <= LLDMA3RXSOPN_ipd after IN_DELAY; + LLDMA3RXSRCRDYN_indelay <= LLDMA3RXSRCRDYN_ipd after IN_DELAY; + LLDMA3TXDSTRDYN_indelay <= LLDMA3TXDSTRDYN_ipd after IN_DELAY; + MCMIADDRREADYTOACCEPT_indelay <= MCMIADDRREADYTOACCEPT_ipd after IN_DELAY; + MCMIREADDATAERR_indelay <= MCMIREADDATAERR_ipd after IN_DELAY; + MCMIREADDATAVALID_indelay <= MCMIREADDATAVALID_ipd after IN_DELAY; + MCMIREADDATA_indelay <= MCMIREADDATA_ipd after IN_DELAY; + PLBPPCMADDRACK_indelay <= PLBPPCMADDRACK_ipd after IN_DELAY; + PLBPPCMMBUSY_indelay <= PLBPPCMMBUSY_ipd after IN_DELAY; + PLBPPCMMIRQ_indelay <= PLBPPCMMIRQ_ipd after IN_DELAY; + PLBPPCMMRDERR_indelay <= PLBPPCMMRDERR_ipd after IN_DELAY; + PLBPPCMMWRERR_indelay <= PLBPPCMMWRERR_ipd after IN_DELAY; + PLBPPCMRDBTERM_indelay <= PLBPPCMRDBTERM_ipd after IN_DELAY; + PLBPPCMRDDACK_indelay <= PLBPPCMRDDACK_ipd after IN_DELAY; + PLBPPCMRDDBUS_indelay <= PLBPPCMRDDBUS_ipd after IN_DELAY; + PLBPPCMRDPENDPRI_indelay <= PLBPPCMRDPENDPRI_ipd after IN_DELAY; + PLBPPCMRDPENDREQ_indelay <= PLBPPCMRDPENDREQ_ipd after IN_DELAY; + PLBPPCMRDWDADDR_indelay <= PLBPPCMRDWDADDR_ipd after IN_DELAY; + PLBPPCMREARBITRATE_indelay <= PLBPPCMREARBITRATE_ipd after IN_DELAY; + PLBPPCMREQPRI_indelay <= PLBPPCMREQPRI_ipd after IN_DELAY; + PLBPPCMSSIZE_indelay <= PLBPPCMSSIZE_ipd after IN_DELAY; + PLBPPCMTIMEOUT_indelay <= PLBPPCMTIMEOUT_ipd after IN_DELAY; + PLBPPCMWRBTERM_indelay <= PLBPPCMWRBTERM_ipd after IN_DELAY; + PLBPPCMWRDACK_indelay <= PLBPPCMWRDACK_ipd after IN_DELAY; + PLBPPCMWRPENDPRI_indelay <= PLBPPCMWRPENDPRI_ipd after IN_DELAY; + PLBPPCMWRPENDREQ_indelay <= PLBPPCMWRPENDREQ_ipd after IN_DELAY; + PLBPPCS0ABORT_indelay <= PLBPPCS0ABORT_ipd after IN_DELAY; + PLBPPCS0ABUS_indelay <= PLBPPCS0ABUS_ipd after IN_DELAY; + PLBPPCS0BE_indelay <= PLBPPCS0BE_ipd after IN_DELAY; + PLBPPCS0BUSLOCK_indelay <= PLBPPCS0BUSLOCK_ipd after IN_DELAY; + PLBPPCS0LOCKERR_indelay <= PLBPPCS0LOCKERR_ipd after IN_DELAY; + PLBPPCS0MASTERID_indelay <= PLBPPCS0MASTERID_ipd after IN_DELAY; + PLBPPCS0MSIZE_indelay <= PLBPPCS0MSIZE_ipd after IN_DELAY; + PLBPPCS0PAVALID_indelay <= PLBPPCS0PAVALID_ipd after IN_DELAY; + PLBPPCS0RDBURST_indelay <= PLBPPCS0RDBURST_ipd after IN_DELAY; + PLBPPCS0RDPENDPRI_indelay <= PLBPPCS0RDPENDPRI_ipd after IN_DELAY; + PLBPPCS0RDPENDREQ_indelay <= PLBPPCS0RDPENDREQ_ipd after IN_DELAY; + PLBPPCS0RDPRIM_indelay <= PLBPPCS0RDPRIM_ipd after IN_DELAY; + PLBPPCS0REQPRI_indelay <= PLBPPCS0REQPRI_ipd after IN_DELAY; + PLBPPCS0RNW_indelay <= PLBPPCS0RNW_ipd after IN_DELAY; + PLBPPCS0SAVALID_indelay <= PLBPPCS0SAVALID_ipd after IN_DELAY; + PLBPPCS0SIZE_indelay <= PLBPPCS0SIZE_ipd after IN_DELAY; + PLBPPCS0TATTRIBUTE_indelay <= PLBPPCS0TATTRIBUTE_ipd after IN_DELAY; + PLBPPCS0TYPE_indelay <= PLBPPCS0TYPE_ipd after IN_DELAY; + PLBPPCS0UABUS_indelay <= PLBPPCS0UABUS_ipd after IN_DELAY; + PLBPPCS0WRBURST_indelay <= PLBPPCS0WRBURST_ipd after IN_DELAY; + PLBPPCS0WRDBUS_indelay <= PLBPPCS0WRDBUS_ipd after IN_DELAY; + PLBPPCS0WRPENDPRI_indelay <= PLBPPCS0WRPENDPRI_ipd after IN_DELAY; + PLBPPCS0WRPENDREQ_indelay <= PLBPPCS0WRPENDREQ_ipd after IN_DELAY; + PLBPPCS0WRPRIM_indelay <= PLBPPCS0WRPRIM_ipd after IN_DELAY; + PLBPPCS1ABORT_indelay <= PLBPPCS1ABORT_ipd after IN_DELAY; + PLBPPCS1ABUS_indelay <= PLBPPCS1ABUS_ipd after IN_DELAY; + PLBPPCS1BE_indelay <= PLBPPCS1BE_ipd after IN_DELAY; + PLBPPCS1BUSLOCK_indelay <= PLBPPCS1BUSLOCK_ipd after IN_DELAY; + PLBPPCS1LOCKERR_indelay <= PLBPPCS1LOCKERR_ipd after IN_DELAY; + PLBPPCS1MASTERID_indelay <= PLBPPCS1MASTERID_ipd after IN_DELAY; + PLBPPCS1MSIZE_indelay <= PLBPPCS1MSIZE_ipd after IN_DELAY; + PLBPPCS1PAVALID_indelay <= PLBPPCS1PAVALID_ipd after IN_DELAY; + PLBPPCS1RDBURST_indelay <= PLBPPCS1RDBURST_ipd after IN_DELAY; + PLBPPCS1RDPENDPRI_indelay <= PLBPPCS1RDPENDPRI_ipd after IN_DELAY; + PLBPPCS1RDPENDREQ_indelay <= PLBPPCS1RDPENDREQ_ipd after IN_DELAY; + PLBPPCS1RDPRIM_indelay <= PLBPPCS1RDPRIM_ipd after IN_DELAY; + PLBPPCS1REQPRI_indelay <= PLBPPCS1REQPRI_ipd after IN_DELAY; + PLBPPCS1RNW_indelay <= PLBPPCS1RNW_ipd after IN_DELAY; + PLBPPCS1SAVALID_indelay <= PLBPPCS1SAVALID_ipd after IN_DELAY; + PLBPPCS1SIZE_indelay <= PLBPPCS1SIZE_ipd after IN_DELAY; + PLBPPCS1TATTRIBUTE_indelay <= PLBPPCS1TATTRIBUTE_ipd after IN_DELAY; + PLBPPCS1TYPE_indelay <= PLBPPCS1TYPE_ipd after IN_DELAY; + PLBPPCS1UABUS_indelay <= PLBPPCS1UABUS_ipd after IN_DELAY; + PLBPPCS1WRBURST_indelay <= PLBPPCS1WRBURST_ipd after IN_DELAY; + PLBPPCS1WRDBUS_indelay <= PLBPPCS1WRDBUS_ipd after IN_DELAY; + PLBPPCS1WRPENDPRI_indelay <= PLBPPCS1WRPENDPRI_ipd after IN_DELAY; + PLBPPCS1WRPENDREQ_indelay <= PLBPPCS1WRPENDREQ_ipd after IN_DELAY; + PLBPPCS1WRPRIM_indelay <= PLBPPCS1WRPRIM_ipd after IN_DELAY; + RSTC440RESETCHIP_indelay <= RSTC440RESETCHIP_ipd after IN_DELAY; + RSTC440RESETCORE_indelay <= RSTC440RESETCORE_ipd after IN_DELAY; + RSTC440RESETSYSTEM_indelay <= RSTC440RESETSYSTEM_ipd after IN_DELAY; + TIEC440DCURDLDCACHEPLBPRIO_indelay <= TIEC440DCURDLDCACHEPLBPRIO_ipd after IN_DELAY; + TIEC440DCURDNONCACHEPLBPRIO_indelay <= TIEC440DCURDNONCACHEPLBPRIO_ipd after IN_DELAY; + TIEC440DCURDTOUCHPLBPRIO_indelay <= TIEC440DCURDTOUCHPLBPRIO_ipd after IN_DELAY; + TIEC440DCURDURGENTPLBPRIO_indelay <= TIEC440DCURDURGENTPLBPRIO_ipd after IN_DELAY; + TIEC440DCUWRFLUSHPLBPRIO_indelay <= TIEC440DCUWRFLUSHPLBPRIO_ipd after IN_DELAY; + TIEC440DCUWRSTOREPLBPRIO_indelay <= TIEC440DCUWRSTOREPLBPRIO_ipd after IN_DELAY; + TIEC440DCUWRURGENTPLBPRIO_indelay <= TIEC440DCUWRURGENTPLBPRIO_ipd after IN_DELAY; + TIEC440ENDIANRESET_indelay <= TIEC440ENDIANRESET_ipd after IN_DELAY; + TIEC440ERPNRESET_indelay <= TIEC440ERPNRESET_ipd after IN_DELAY; + TIEC440ICURDFETCHPLBPRIO_indelay <= TIEC440ICURDFETCHPLBPRIO_ipd after IN_DELAY; + TIEC440ICURDSPECPLBPRIO_indelay <= TIEC440ICURDSPECPLBPRIO_ipd after IN_DELAY; + TIEC440ICURDTOUCHPLBPRIO_indelay <= TIEC440ICURDTOUCHPLBPRIO_ipd after IN_DELAY; + TIEC440PIR_indelay <= TIEC440PIR_ipd after IN_DELAY; + TIEC440PVR_indelay <= TIEC440PVR_ipd after IN_DELAY; + TIEC440USERRESET_indelay <= TIEC440USERRESET_ipd after IN_DELAY; + TIEDCRBASEADDR_indelay <= TIEDCRBASEADDR_ipd after IN_DELAY; + TRCC440TRACEDISABLE_indelay <= TRCC440TRACEDISABLE_ipd after IN_DELAY; + TRCC440TRIGGEREVENTIN_indelay <= TRCC440TRIGGEREVENTIN_ipd after IN_DELAY; + + + ppc440_swift_1 : PPC440_SWIFT + port map ( + APU_CONTROL => APU_CONTROL_BINARY, + APU_UDI0 => APU_UDI0_BINARY, + APU_UDI1 => APU_UDI1_BINARY, + APU_UDI10 => APU_UDI10_BINARY, + APU_UDI11 => APU_UDI11_BINARY, + APU_UDI12 => APU_UDI12_BINARY, + APU_UDI13 => APU_UDI13_BINARY, + APU_UDI14 => APU_UDI14_BINARY, + APU_UDI15 => APU_UDI15_BINARY, + APU_UDI2 => APU_UDI2_BINARY, + APU_UDI3 => APU_UDI3_BINARY, + APU_UDI4 => APU_UDI4_BINARY, + APU_UDI5 => APU_UDI5_BINARY, + APU_UDI6 => APU_UDI6_BINARY, + APU_UDI7 => APU_UDI7_BINARY, + APU_UDI8 => APU_UDI8_BINARY, + APU_UDI9 => APU_UDI9_BINARY, + CLOCK_DELAY => CLOCK_DELAY_BINARY, + DCR_AUTOLOCK_ENABLE => DCR_AUTOLOCK_ENABLE_BINARY, + DMA0_CONTROL => DMA0_CONTROL_BINARY, + DMA0_RXCHANNELCTRL => DMA0_RXCHANNELCTRL_BINARY, + DMA0_RXIRQTIMER => DMA0_RXIRQTIMER_BINARY, + DMA0_TXCHANNELCTRL => DMA0_TXCHANNELCTRL_BINARY, + DMA0_TXIRQTIMER => DMA0_TXIRQTIMER_BINARY, + DMA1_CONTROL => DMA1_CONTROL_BINARY, + DMA1_RXCHANNELCTRL => DMA1_RXCHANNELCTRL_BINARY, + DMA1_RXIRQTIMER => DMA1_RXIRQTIMER_BINARY, + DMA1_TXCHANNELCTRL => DMA1_TXCHANNELCTRL_BINARY, + DMA1_TXIRQTIMER => DMA1_TXIRQTIMER_BINARY, + DMA2_CONTROL => DMA2_CONTROL_BINARY, + DMA2_RXCHANNELCTRL => DMA2_RXCHANNELCTRL_BINARY, + DMA2_RXIRQTIMER => DMA2_RXIRQTIMER_BINARY, + DMA2_TXCHANNELCTRL => DMA2_TXCHANNELCTRL_BINARY, + DMA2_TXIRQTIMER => DMA2_TXIRQTIMER_BINARY, + DMA3_CONTROL => DMA3_CONTROL_BINARY, + DMA3_RXCHANNELCTRL => DMA3_RXCHANNELCTRL_BINARY, + DMA3_RXIRQTIMER => DMA3_RXIRQTIMER_BINARY, + DMA3_TXCHANNELCTRL => DMA3_TXCHANNELCTRL_BINARY, + DMA3_TXIRQTIMER => DMA3_TXIRQTIMER_BINARY, + INTERCONNECT_IMASK => INTERCONNECT_IMASK_BINARY, + INTERCONNECT_TMPL_SEL => INTERCONNECT_TMPL_SEL_BINARY, + MI_ARBCONFIG => MI_ARBCONFIG_BINARY, + MI_BANKCONFLICT_MASK => MI_BANKCONFLICT_MASK_BINARY, + MI_CONTROL => MI_CONTROL_BINARY, + MI_ROWCONFLICT_MASK => MI_ROWCONFLICT_MASK_BINARY, + PPCDM_ASYNCMODE => PPCDM_ASYNCMODE_BINARY, + PPCDS_ASYNCMODE => PPCDS_ASYNCMODE_BINARY, + PPCM_ARBCONFIG => PPCM_ARBCONFIG_BINARY, + PPCM_CONTROL => PPCM_CONTROL_BINARY, + PPCM_COUNTER => PPCM_COUNTER_BINARY, + PPCS0_ADDRMAP_TMPL0 => PPCS0_ADDRMAP_TMPL0_BINARY, + PPCS0_ADDRMAP_TMPL1 => PPCS0_ADDRMAP_TMPL1_BINARY, + PPCS0_ADDRMAP_TMPL2 => PPCS0_ADDRMAP_TMPL2_BINARY, + PPCS0_ADDRMAP_TMPL3 => PPCS0_ADDRMAP_TMPL3_BINARY, + PPCS0_CONTROL => PPCS0_CONTROL_BINARY, + PPCS0_WIDTH_128N64 => PPCS0_WIDTH_128N64_BINARY, + PPCS1_ADDRMAP_TMPL0 => PPCS1_ADDRMAP_TMPL0_BINARY, + PPCS1_ADDRMAP_TMPL1 => PPCS1_ADDRMAP_TMPL1_BINARY, + PPCS1_ADDRMAP_TMPL2 => PPCS1_ADDRMAP_TMPL2_BINARY, + PPCS1_ADDRMAP_TMPL3 => PPCS1_ADDRMAP_TMPL3_BINARY, + PPCS1_CONTROL => PPCS1_CONTROL_BINARY, + PPCS1_WIDTH_128N64 => PPCS1_WIDTH_128N64_BINARY, + XBAR_ADDRMAP_TMPL0 => XBAR_ADDRMAP_TMPL0_BINARY, + XBAR_ADDRMAP_TMPL1 => XBAR_ADDRMAP_TMPL1_BINARY, + XBAR_ADDRMAP_TMPL2 => XBAR_ADDRMAP_TMPL2_BINARY, + XBAR_ADDRMAP_TMPL3 => XBAR_ADDRMAP_TMPL3_BINARY, + + APUFCMDECFPUOP => APUFCMDECFPUOP_outdelay, + APUFCMDECLDSTXFERSIZE => APUFCMDECLDSTXFERSIZE_outdelay, + APUFCMDECLOAD => APUFCMDECLOAD_outdelay, + APUFCMDECNONAUTON => APUFCMDECNONAUTON_outdelay, + APUFCMDECSTORE => APUFCMDECSTORE_outdelay, + APUFCMDECUDI => APUFCMDECUDI_outdelay, + APUFCMDECUDIVALID => APUFCMDECUDIVALID_outdelay, + APUFCMENDIAN => APUFCMENDIAN_outdelay, + APUFCMFLUSH => APUFCMFLUSH_outdelay, + APUFCMINSTRUCTION => APUFCMINSTRUCTION_outdelay, + APUFCMINSTRVALID => APUFCMINSTRVALID_outdelay, + APUFCMLOADBYTEADDR => APUFCMLOADBYTEADDR_outdelay, + APUFCMLOADDATA => APUFCMLOADDATA_outdelay, + APUFCMLOADDVALID => APUFCMLOADDVALID_outdelay, + APUFCMMSRFE0 => APUFCMMSRFE0_outdelay, + APUFCMMSRFE1 => APUFCMMSRFE1_outdelay, + APUFCMNEXTINSTRREADY => APUFCMNEXTINSTRREADY_outdelay, + APUFCMOPERANDVALID => APUFCMOPERANDVALID_outdelay, + APUFCMRADATA => APUFCMRADATA_outdelay, + APUFCMRBDATA => APUFCMRBDATA_outdelay, + APUFCMWRITEBACKOK => APUFCMWRITEBACKOK_outdelay, + C440CPMCORESLEEPREQ => C440CPMCORESLEEPREQ_outdelay, + C440CPMDECIRPTREQ => C440CPMDECIRPTREQ_outdelay, + C440CPMFITIRPTREQ => C440CPMFITIRPTREQ_outdelay, + C440CPMMSRCE => C440CPMMSRCE_outdelay, + C440CPMMSREE => C440CPMMSREE_outdelay, + C440CPMTIMERRESETREQ => C440CPMTIMERRESETREQ_outdelay, + C440CPMWDIRPTREQ => C440CPMWDIRPTREQ_outdelay, + C440DBGSYSTEMCONTROL => C440DBGSYSTEMCONTROL_outdelay, + C440JTGTDO => C440JTGTDO_outdelay, + C440JTGTDOEN => C440JTGTDOEN_outdelay, + C440MACHINECHECK => C440MACHINECHECK_outdelay, + C440RSTCHIPRESETREQ => C440RSTCHIPRESETREQ_outdelay, + C440RSTCORERESETREQ => C440RSTCORERESETREQ_outdelay, + C440RSTSYSTEMRESETREQ => C440RSTSYSTEMRESETREQ_outdelay, + C440TRCBRANCHSTATUS => C440TRCBRANCHSTATUS_outdelay, + C440TRCCYCLE => C440TRCCYCLE_outdelay, + C440TRCEXECUTIONSTATUS => C440TRCEXECUTIONSTATUS_outdelay, + C440TRCTRACESTATUS => C440TRCTRACESTATUS_outdelay, + C440TRCTRIGGEREVENTOUT => C440TRCTRIGGEREVENTOUT_outdelay, + C440TRCTRIGGEREVENTTYPE => C440TRCTRIGGEREVENTTYPE_outdelay, + DMA0LLRSTENGINEACK => DMA0LLRSTENGINEACK_outdelay, + DMA0LLRXDSTRDYN => DMA0LLRXDSTRDYN_outdelay, + DMA0LLTXD => DMA0LLTXD_outdelay, + DMA0LLTXEOFN => DMA0LLTXEOFN_outdelay, + DMA0LLTXEOPN => DMA0LLTXEOPN_outdelay, + DMA0LLTXREM => DMA0LLTXREM_outdelay, + DMA0LLTXSOFN => DMA0LLTXSOFN_outdelay, + DMA0LLTXSOPN => DMA0LLTXSOPN_outdelay, + DMA0LLTXSRCRDYN => DMA0LLTXSRCRDYN_outdelay, + DMA0RXIRQ => DMA0RXIRQ_outdelay, + DMA0TXIRQ => DMA0TXIRQ_outdelay, + DMA1LLRSTENGINEACK => DMA1LLRSTENGINEACK_outdelay, + DMA1LLRXDSTRDYN => DMA1LLRXDSTRDYN_outdelay, + DMA1LLTXD => DMA1LLTXD_outdelay, + DMA1LLTXEOFN => DMA1LLTXEOFN_outdelay, + DMA1LLTXEOPN => DMA1LLTXEOPN_outdelay, + DMA1LLTXREM => DMA1LLTXREM_outdelay, + DMA1LLTXSOFN => DMA1LLTXSOFN_outdelay, + DMA1LLTXSOPN => DMA1LLTXSOPN_outdelay, + DMA1LLTXSRCRDYN => DMA1LLTXSRCRDYN_outdelay, + DMA1RXIRQ => DMA1RXIRQ_outdelay, + DMA1TXIRQ => DMA1TXIRQ_outdelay, + DMA2LLRSTENGINEACK => DMA2LLRSTENGINEACK_outdelay, + DMA2LLRXDSTRDYN => DMA2LLRXDSTRDYN_outdelay, + DMA2LLTXD => DMA2LLTXD_outdelay, + DMA2LLTXEOFN => DMA2LLTXEOFN_outdelay, + DMA2LLTXEOPN => DMA2LLTXEOPN_outdelay, + DMA2LLTXREM => DMA2LLTXREM_outdelay, + DMA2LLTXSOFN => DMA2LLTXSOFN_outdelay, + DMA2LLTXSOPN => DMA2LLTXSOPN_outdelay, + DMA2LLTXSRCRDYN => DMA2LLTXSRCRDYN_outdelay, + DMA2RXIRQ => DMA2RXIRQ_outdelay, + DMA2TXIRQ => DMA2TXIRQ_outdelay, + DMA3LLRSTENGINEACK => DMA3LLRSTENGINEACK_outdelay, + DMA3LLRXDSTRDYN => DMA3LLRXDSTRDYN_outdelay, + DMA3LLTXD => DMA3LLTXD_outdelay, + DMA3LLTXEOFN => DMA3LLTXEOFN_outdelay, + DMA3LLTXEOPN => DMA3LLTXEOPN_outdelay, + DMA3LLTXREM => DMA3LLTXREM_outdelay, + DMA3LLTXSOFN => DMA3LLTXSOFN_outdelay, + DMA3LLTXSOPN => DMA3LLTXSOPN_outdelay, + DMA3LLTXSRCRDYN => DMA3LLTXSRCRDYN_outdelay, + DMA3RXIRQ => DMA3RXIRQ_outdelay, + DMA3TXIRQ => DMA3TXIRQ_outdelay, + MIMCADDRESS => MIMCADDRESS_outdelay, + MIMCADDRESSVALID => MIMCADDRESSVALID_outdelay, + MIMCBANKCONFLICT => MIMCBANKCONFLICT_outdelay, + MIMCBYTEENABLE => MIMCBYTEENABLE_outdelay, + MIMCREADNOTWRITE => MIMCREADNOTWRITE_outdelay, + MIMCROWCONFLICT => MIMCROWCONFLICT_outdelay, + MIMCWRITEDATA => MIMCWRITEDATA_outdelay, + MIMCWRITEDATAVALID => MIMCWRITEDATAVALID_outdelay, + PPCCPMINTERCONNECTBUSY => PPCCPMINTERCONNECTBUSY_outdelay, + PPCDMDCRABUS => PPCDMDCRABUS_outdelay, + PPCDMDCRDBUSOUT => PPCDMDCRDBUSOUT_outdelay, + PPCDMDCRREAD => PPCDMDCRREAD_outdelay, + PPCDMDCRUABUS => PPCDMDCRUABUS_outdelay, + PPCDMDCRWRITE => PPCDMDCRWRITE_outdelay, + PPCDSDCRACK => PPCDSDCRACK_outdelay, + PPCDSDCRDBUSIN => PPCDSDCRDBUSIN_outdelay, + PPCDSDCRTIMEOUTWAIT => PPCDSDCRTIMEOUTWAIT_outdelay, + PPCEICINTERCONNECTIRQ => PPCEICINTERCONNECTIRQ_outdelay, + PPCMPLBABORT => PPCMPLBABORT_outdelay, + PPCMPLBABUS => PPCMPLBABUS_outdelay, + PPCMPLBBE => PPCMPLBBE_outdelay, + PPCMPLBBUSLOCK => PPCMPLBBUSLOCK_outdelay, + PPCMPLBLOCKERR => PPCMPLBLOCKERR_outdelay, + PPCMPLBPRIORITY => PPCMPLBPRIORITY_outdelay, + PPCMPLBRDBURST => PPCMPLBRDBURST_outdelay, + PPCMPLBREQUEST => PPCMPLBREQUEST_outdelay, + PPCMPLBRNW => PPCMPLBRNW_outdelay, + PPCMPLBSIZE => PPCMPLBSIZE_outdelay, + PPCMPLBTATTRIBUTE => PPCMPLBTATTRIBUTE_outdelay, + PPCMPLBTYPE => PPCMPLBTYPE_outdelay, + PPCMPLBUABUS => PPCMPLBUABUS_outdelay, + PPCMPLBWRBURST => PPCMPLBWRBURST_outdelay, + PPCMPLBWRDBUS => PPCMPLBWRDBUS_outdelay, + PPCS0PLBADDRACK => PPCS0PLBADDRACK_outdelay, + PPCS0PLBMBUSY => PPCS0PLBMBUSY_outdelay, + PPCS0PLBMIRQ => PPCS0PLBMIRQ_outdelay, + PPCS0PLBMRDERR => PPCS0PLBMRDERR_outdelay, + PPCS0PLBMWRERR => PPCS0PLBMWRERR_outdelay, + PPCS0PLBRDBTERM => PPCS0PLBRDBTERM_outdelay, + PPCS0PLBRDCOMP => PPCS0PLBRDCOMP_outdelay, + PPCS0PLBRDDACK => PPCS0PLBRDDACK_outdelay, + PPCS0PLBRDDBUS => PPCS0PLBRDDBUS_outdelay, + PPCS0PLBRDWDADDR => PPCS0PLBRDWDADDR_outdelay, + PPCS0PLBREARBITRATE => PPCS0PLBREARBITRATE_outdelay, + PPCS0PLBSSIZE => PPCS0PLBSSIZE_outdelay, + PPCS0PLBWAIT => PPCS0PLBWAIT_outdelay, + PPCS0PLBWRBTERM => PPCS0PLBWRBTERM_outdelay, + PPCS0PLBWRCOMP => PPCS0PLBWRCOMP_outdelay, + PPCS0PLBWRDACK => PPCS0PLBWRDACK_outdelay, + PPCS1PLBADDRACK => PPCS1PLBADDRACK_outdelay, + PPCS1PLBMBUSY => PPCS1PLBMBUSY_outdelay, + PPCS1PLBMIRQ => PPCS1PLBMIRQ_outdelay, + PPCS1PLBMRDERR => PPCS1PLBMRDERR_outdelay, + PPCS1PLBMWRERR => PPCS1PLBMWRERR_outdelay, + PPCS1PLBRDBTERM => PPCS1PLBRDBTERM_outdelay, + PPCS1PLBRDCOMP => PPCS1PLBRDCOMP_outdelay, + PPCS1PLBRDDACK => PPCS1PLBRDDACK_outdelay, + PPCS1PLBRDDBUS => PPCS1PLBRDDBUS_outdelay, + PPCS1PLBRDWDADDR => PPCS1PLBRDWDADDR_outdelay, + PPCS1PLBREARBITRATE => PPCS1PLBREARBITRATE_outdelay, + PPCS1PLBSSIZE => PPCS1PLBSSIZE_outdelay, + PPCS1PLBWAIT => PPCS1PLBWAIT_outdelay, + PPCS1PLBWRBTERM => PPCS1PLBWRBTERM_outdelay, + PPCS1PLBWRCOMP => PPCS1PLBWRCOMP_outdelay, + PPCS1PLBWRDACK => PPCS1PLBWRDACK_outdelay, + + CPMC440CLK => CPMC440CLK_indelay, + CPMC440CLKEN => CPMC440CLKEN_indelay, + CPMC440CORECLOCKINACTIVE => CPMC440CORECLOCKINACTIVE_indelay, + CPMC440TIMERCLOCK => CPMC440TIMERCLOCK_indelay, + CPMDCRCLK => CPMDCRCLK_indelay, + CPMDMA0LLCLK => CPMDMA0LLCLK_indelay, + CPMDMA1LLCLK => CPMDMA1LLCLK_indelay, + CPMDMA2LLCLK => CPMDMA2LLCLK_indelay, + CPMDMA3LLCLK => CPMDMA3LLCLK_indelay, + CPMFCMCLK => CPMFCMCLK_indelay, + CPMINTERCONNECTCLK => CPMINTERCONNECTCLK_indelay, + CPMINTERCONNECTCLKEN => CPMINTERCONNECTCLKEN_indelay, + CPMINTERCONNECTCLKNTO1 => CPMINTERCONNECTCLKNTO1_indelay, + CPMMCCLK => CPMMCCLK_indelay, + CPMPPCMPLBCLK => CPMPPCMPLBCLK_indelay, + CPMPPCS0PLBCLK => CPMPPCS0PLBCLK_indelay, + CPMPPCS1PLBCLK => CPMPPCS1PLBCLK_indelay, + DBGC440DEBUGHALT => DBGC440DEBUGHALT_indelay, + DBGC440SYSTEMSTATUS => DBGC440SYSTEMSTATUS_indelay, + DBGC440UNCONDDEBUGEVENT => DBGC440UNCONDDEBUGEVENT_indelay, + DCRPPCDMACK => DCRPPCDMACK_indelay, + DCRPPCDMDBUSIN => DCRPPCDMDBUSIN_indelay, + DCRPPCDMTIMEOUTWAIT => DCRPPCDMTIMEOUTWAIT_indelay, + DCRPPCDSABUS => DCRPPCDSABUS_indelay, + DCRPPCDSDBUSOUT => DCRPPCDSDBUSOUT_indelay, + DCRPPCDSREAD => DCRPPCDSREAD_indelay, + DCRPPCDSWRITE => DCRPPCDSWRITE_indelay, + EICC440CRITIRQ => EICC440CRITIRQ_indelay, + EICC440EXTIRQ => EICC440EXTIRQ_indelay, + FCMAPUCONFIRMINSTR => FCMAPUCONFIRMINSTR_indelay, + FCMAPUCR => FCMAPUCR_indelay, + FCMAPUDONE => FCMAPUDONE_indelay, + FCMAPUEXCEPTION => FCMAPUEXCEPTION_indelay, + FCMAPUFPSCRFEX => FCMAPUFPSCRFEX_indelay, + FCMAPURESULT => FCMAPURESULT_indelay, + FCMAPURESULTVALID => FCMAPURESULTVALID_indelay, + FCMAPUSLEEPNOTREADY => FCMAPUSLEEPNOTREADY_indelay, + FCMAPUSTOREDATA => FCMAPUSTOREDATA_indelay, + GSR => GSR, + JTGC440TCK => JTGC440TCK_indelay, + JTGC440TDI => JTGC440TDI_indelay, + JTGC440TMS => JTGC440TMS_indelay, + JTGC440TRSTNEG => JTGC440TRSTNEG_indelay, + LLDMA0RSTENGINEREQ => LLDMA0RSTENGINEREQ_indelay, + LLDMA0RXD => LLDMA0RXD_indelay, + LLDMA0RXEOFN => LLDMA0RXEOFN_indelay, + LLDMA0RXEOPN => LLDMA0RXEOPN_indelay, + LLDMA0RXREM => LLDMA0RXREM_indelay, + LLDMA0RXSOFN => LLDMA0RXSOFN_indelay, + LLDMA0RXSOPN => LLDMA0RXSOPN_indelay, + LLDMA0RXSRCRDYN => LLDMA0RXSRCRDYN_indelay, + LLDMA0TXDSTRDYN => LLDMA0TXDSTRDYN_indelay, + LLDMA1RSTENGINEREQ => LLDMA1RSTENGINEREQ_indelay, + LLDMA1RXD => LLDMA1RXD_indelay, + LLDMA1RXEOFN => LLDMA1RXEOFN_indelay, + LLDMA1RXEOPN => LLDMA1RXEOPN_indelay, + LLDMA1RXREM => LLDMA1RXREM_indelay, + LLDMA1RXSOFN => LLDMA1RXSOFN_indelay, + LLDMA1RXSOPN => LLDMA1RXSOPN_indelay, + LLDMA1RXSRCRDYN => LLDMA1RXSRCRDYN_indelay, + LLDMA1TXDSTRDYN => LLDMA1TXDSTRDYN_indelay, + LLDMA2RSTENGINEREQ => LLDMA2RSTENGINEREQ_indelay, + LLDMA2RXD => LLDMA2RXD_indelay, + LLDMA2RXEOFN => LLDMA2RXEOFN_indelay, + LLDMA2RXEOPN => LLDMA2RXEOPN_indelay, + LLDMA2RXREM => LLDMA2RXREM_indelay, + LLDMA2RXSOFN => LLDMA2RXSOFN_indelay, + LLDMA2RXSOPN => LLDMA2RXSOPN_indelay, + LLDMA2RXSRCRDYN => LLDMA2RXSRCRDYN_indelay, + LLDMA2TXDSTRDYN => LLDMA2TXDSTRDYN_indelay, + LLDMA3RSTENGINEREQ => LLDMA3RSTENGINEREQ_indelay, + LLDMA3RXD => LLDMA3RXD_indelay, + LLDMA3RXEOFN => LLDMA3RXEOFN_indelay, + LLDMA3RXEOPN => LLDMA3RXEOPN_indelay, + LLDMA3RXREM => LLDMA3RXREM_indelay, + LLDMA3RXSOFN => LLDMA3RXSOFN_indelay, + LLDMA3RXSOPN => LLDMA3RXSOPN_indelay, + LLDMA3RXSRCRDYN => LLDMA3RXSRCRDYN_indelay, + LLDMA3TXDSTRDYN => LLDMA3TXDSTRDYN_indelay, + MCMIADDRREADYTOACCEPT => MCMIADDRREADYTOACCEPT_indelay, + MCMIREADDATA => MCMIREADDATA_indelay, + MCMIREADDATAERR => MCMIREADDATAERR_indelay, + MCMIREADDATAVALID => MCMIREADDATAVALID_indelay, + PLBPPCMADDRACK => PLBPPCMADDRACK_indelay, + PLBPPCMMBUSY => PLBPPCMMBUSY_indelay, + PLBPPCMMIRQ => PLBPPCMMIRQ_indelay, + PLBPPCMMRDERR => PLBPPCMMRDERR_indelay, + PLBPPCMMWRERR => PLBPPCMMWRERR_indelay, + PLBPPCMRDBTERM => PLBPPCMRDBTERM_indelay, + PLBPPCMRDDACK => PLBPPCMRDDACK_indelay, + PLBPPCMRDDBUS => PLBPPCMRDDBUS_indelay, + PLBPPCMRDPENDPRI => PLBPPCMRDPENDPRI_indelay, + PLBPPCMRDPENDREQ => PLBPPCMRDPENDREQ_indelay, + PLBPPCMRDWDADDR => PLBPPCMRDWDADDR_indelay, + PLBPPCMREARBITRATE => PLBPPCMREARBITRATE_indelay, + PLBPPCMREQPRI => PLBPPCMREQPRI_indelay, + PLBPPCMSSIZE => PLBPPCMSSIZE_indelay, + PLBPPCMTIMEOUT => PLBPPCMTIMEOUT_indelay, + PLBPPCMWRBTERM => PLBPPCMWRBTERM_indelay, + PLBPPCMWRDACK => PLBPPCMWRDACK_indelay, + PLBPPCMWRPENDPRI => PLBPPCMWRPENDPRI_indelay, + PLBPPCMWRPENDREQ => PLBPPCMWRPENDREQ_indelay, + PLBPPCS0ABORT => PLBPPCS0ABORT_indelay, + PLBPPCS0ABUS => PLBPPCS0ABUS_indelay, + PLBPPCS0BE => PLBPPCS0BE_indelay, + PLBPPCS0BUSLOCK => PLBPPCS0BUSLOCK_indelay, + PLBPPCS0LOCKERR => PLBPPCS0LOCKERR_indelay, + PLBPPCS0MASTERID => PLBPPCS0MASTERID_indelay, + PLBPPCS0MSIZE => PLBPPCS0MSIZE_indelay, + PLBPPCS0PAVALID => PLBPPCS0PAVALID_indelay, + PLBPPCS0RDBURST => PLBPPCS0RDBURST_indelay, + PLBPPCS0RDPENDPRI => PLBPPCS0RDPENDPRI_indelay, + PLBPPCS0RDPENDREQ => PLBPPCS0RDPENDREQ_indelay, + PLBPPCS0RDPRIM => PLBPPCS0RDPRIM_indelay, + PLBPPCS0REQPRI => PLBPPCS0REQPRI_indelay, + PLBPPCS0RNW => PLBPPCS0RNW_indelay, + PLBPPCS0SAVALID => PLBPPCS0SAVALID_indelay, + PLBPPCS0SIZE => PLBPPCS0SIZE_indelay, + PLBPPCS0TATTRIBUTE => PLBPPCS0TATTRIBUTE_indelay, + PLBPPCS0TYPE => PLBPPCS0TYPE_indelay, + PLBPPCS0UABUS => PLBPPCS0UABUS_indelay, + PLBPPCS0WRBURST => PLBPPCS0WRBURST_indelay, + PLBPPCS0WRDBUS => PLBPPCS0WRDBUS_indelay, + PLBPPCS0WRPENDPRI => PLBPPCS0WRPENDPRI_indelay, + PLBPPCS0WRPENDREQ => PLBPPCS0WRPENDREQ_indelay, + PLBPPCS0WRPRIM => PLBPPCS0WRPRIM_indelay, + PLBPPCS1ABORT => PLBPPCS1ABORT_indelay, + PLBPPCS1ABUS => PLBPPCS1ABUS_indelay, + PLBPPCS1BE => PLBPPCS1BE_indelay, + PLBPPCS1BUSLOCK => PLBPPCS1BUSLOCK_indelay, + PLBPPCS1LOCKERR => PLBPPCS1LOCKERR_indelay, + PLBPPCS1MASTERID => PLBPPCS1MASTERID_indelay, + PLBPPCS1MSIZE => PLBPPCS1MSIZE_indelay, + PLBPPCS1PAVALID => PLBPPCS1PAVALID_indelay, + PLBPPCS1RDBURST => PLBPPCS1RDBURST_indelay, + PLBPPCS1RDPENDPRI => PLBPPCS1RDPENDPRI_indelay, + PLBPPCS1RDPENDREQ => PLBPPCS1RDPENDREQ_indelay, + PLBPPCS1RDPRIM => PLBPPCS1RDPRIM_indelay, + PLBPPCS1REQPRI => PLBPPCS1REQPRI_indelay, + PLBPPCS1RNW => PLBPPCS1RNW_indelay, + PLBPPCS1SAVALID => PLBPPCS1SAVALID_indelay, + PLBPPCS1SIZE => PLBPPCS1SIZE_indelay, + PLBPPCS1TATTRIBUTE => PLBPPCS1TATTRIBUTE_indelay, + PLBPPCS1TYPE => PLBPPCS1TYPE_indelay, + PLBPPCS1UABUS => PLBPPCS1UABUS_indelay, + PLBPPCS1WRBURST => PLBPPCS1WRBURST_indelay, + PLBPPCS1WRDBUS => PLBPPCS1WRDBUS_indelay, + PLBPPCS1WRPENDPRI => PLBPPCS1WRPENDPRI_indelay, + PLBPPCS1WRPENDREQ => PLBPPCS1WRPENDREQ_indelay, + PLBPPCS1WRPRIM => PLBPPCS1WRPRIM_indelay, + RSTC440RESETCHIP => RSTC440RESETCHIP_indelay, + RSTC440RESETCORE => RSTC440RESETCORE_indelay, + RSTC440RESETSYSTEM => RSTC440RESETSYSTEM_indelay, + TIEC440DCURDLDCACHEPLBPRIO => TIEC440DCURDLDCACHEPLBPRIO_indelay, + TIEC440DCURDNONCACHEPLBPRIO => TIEC440DCURDNONCACHEPLBPRIO_indelay, + TIEC440DCURDTOUCHPLBPRIO => TIEC440DCURDTOUCHPLBPRIO_indelay, + TIEC440DCURDURGENTPLBPRIO => TIEC440DCURDURGENTPLBPRIO_indelay, + TIEC440DCUWRFLUSHPLBPRIO => TIEC440DCUWRFLUSHPLBPRIO_indelay, + TIEC440DCUWRSTOREPLBPRIO => TIEC440DCUWRSTOREPLBPRIO_indelay, + TIEC440DCUWRURGENTPLBPRIO => TIEC440DCUWRURGENTPLBPRIO_indelay, + TIEC440ENDIANRESET => TIEC440ENDIANRESET_indelay, + TIEC440ERPNRESET => TIEC440ERPNRESET_indelay, + TIEC440ICURDFETCHPLBPRIO => TIEC440ICURDFETCHPLBPRIO_indelay, + TIEC440ICURDSPECPLBPRIO => TIEC440ICURDSPECPLBPRIO_indelay, + TIEC440ICURDTOUCHPLBPRIO => TIEC440ICURDTOUCHPLBPRIO_indelay, + TIEC440PIR => TIEC440PIR_indelay, + TIEC440PVR => TIEC440PVR_indelay, + TIEC440USERRESET => TIEC440USERRESET_indelay, + TIEDCRBASEADDR => TIEDCRBASEADDR_indelay, + TRCC440TRACEDISABLE => TRCC440TRACEDISABLE_indelay, + TRCC440TRIGGEREVENTIN => TRCC440TRIGGEREVENTIN_indelay + ); + + INIPROC : process + begin + case PPCS0_WIDTH_128N64 is + when FALSE => PPCS0_WIDTH_128N64_BINARY <= '0'; + when TRUE => PPCS0_WIDTH_128N64_BINARY <= '1'; + when others => assert FALSE report "Error : PPCS0_WIDTH_128N64 is neither TRUE nor FALSE." severity error; + end case; + case PPCS1_WIDTH_128N64 is + when FALSE => PPCS1_WIDTH_128N64_BINARY <= '0'; + when TRUE => PPCS1_WIDTH_128N64_BINARY <= '1'; + when others => assert FALSE report "Error : PPCS1_WIDTH_128N64 is neither TRUE nor FALSE." severity error; + end case; + case PPCDM_ASYNCMODE is + when FALSE => PPCDM_ASYNCMODE_BINARY <= '0'; + when TRUE => PPCDM_ASYNCMODE_BINARY <= '1'; + when others => assert FALSE report "Error : PPCDM_ASYNCMODE is neither TRUE nor FALSE." severity error; + end case; + case PPCDS_ASYNCMODE is + when FALSE => PPCDS_ASYNCMODE_BINARY <= '0'; + when TRUE => PPCDS_ASYNCMODE_BINARY <= '1'; + when others => assert FALSE report "Error : PPCDS_ASYNCMODE is neither TRUE nor FALSE." severity error; + end case; + case DCR_AUTOLOCK_ENABLE is + when FALSE => DCR_AUTOLOCK_ENABLE_BINARY <= '0'; + when TRUE => DCR_AUTOLOCK_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : DCR_AUTOLOCK_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case CLOCK_DELAY is + when FALSE => CLOCK_DELAY_BINARY <= "10000"; + when TRUE => CLOCK_DELAY_BINARY <= "00000"; + when others => assert FALSE report "Error : CLOCK_DELAY is neither TRUE nor FALSE." severity error; + end case; + wait; + end process INIPROC; + + TIMING : process + + + + variable DMA0LLRSTENGINEACK_GlitchData : VitalGlitchDataType; + variable DMA0LLRXDSTRDYN_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD0_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD1_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD2_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD3_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD4_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD5_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD6_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD7_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD8_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD9_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD10_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD11_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD12_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD13_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD14_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD15_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD16_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD17_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD18_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD19_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD20_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD21_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD22_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD23_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD24_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD25_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD26_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD27_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD28_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD29_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD30_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD31_GlitchData : VitalGlitchDataType; + variable DMA0LLTXEOFN_GlitchData : VitalGlitchDataType; + variable DMA0LLTXEOPN_GlitchData : VitalGlitchDataType; + variable DMA0LLTXREM0_GlitchData : VitalGlitchDataType; + variable DMA0LLTXREM1_GlitchData : VitalGlitchDataType; + variable DMA0LLTXREM2_GlitchData : VitalGlitchDataType; + variable DMA0LLTXREM3_GlitchData : VitalGlitchDataType; + variable DMA0LLTXSOFN_GlitchData : VitalGlitchDataType; + variable DMA0LLTXSOPN_GlitchData : VitalGlitchDataType; + variable DMA0LLTXSRCRDYN_GlitchData : VitalGlitchDataType; + variable DMA0RXIRQ_GlitchData : VitalGlitchDataType; + variable DMA0TXIRQ_GlitchData : VitalGlitchDataType; + variable DMA1LLRSTENGINEACK_GlitchData : VitalGlitchDataType; + variable DMA1LLRXDSTRDYN_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD0_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD1_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD2_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD3_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD4_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD5_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD6_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD7_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD8_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD9_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD10_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD11_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD12_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD13_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD14_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD15_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD16_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD17_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD18_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD19_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD20_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD21_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD22_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD23_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD24_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD25_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD26_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD27_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD28_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD29_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD30_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD31_GlitchData : VitalGlitchDataType; + variable DMA1LLTXEOFN_GlitchData : VitalGlitchDataType; + variable DMA1LLTXEOPN_GlitchData : VitalGlitchDataType; + variable DMA1LLTXREM0_GlitchData : VitalGlitchDataType; + variable DMA1LLTXREM1_GlitchData : VitalGlitchDataType; + variable DMA1LLTXREM2_GlitchData : VitalGlitchDataType; + variable DMA1LLTXREM3_GlitchData : VitalGlitchDataType; + variable DMA1LLTXSOFN_GlitchData : VitalGlitchDataType; + variable DMA1LLTXSOPN_GlitchData : VitalGlitchDataType; + variable DMA1LLTXSRCRDYN_GlitchData : VitalGlitchDataType; + variable DMA1RXIRQ_GlitchData : VitalGlitchDataType; + variable DMA1TXIRQ_GlitchData : VitalGlitchDataType; + variable DMA2LLRSTENGINEACK_GlitchData : VitalGlitchDataType; + variable DMA2LLRXDSTRDYN_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD0_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD1_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD2_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD3_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD4_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD5_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD6_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD7_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD8_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD9_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD10_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD11_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD12_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD13_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD14_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD15_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD16_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD17_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD18_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD19_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD20_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD21_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD22_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD23_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD24_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD25_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD26_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD27_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD28_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD29_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD30_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD31_GlitchData : VitalGlitchDataType; + variable DMA2LLTXEOFN_GlitchData : VitalGlitchDataType; + variable DMA2LLTXEOPN_GlitchData : VitalGlitchDataType; + variable DMA2LLTXREM0_GlitchData : VitalGlitchDataType; + variable DMA2LLTXREM1_GlitchData : VitalGlitchDataType; + variable DMA2LLTXREM2_GlitchData : VitalGlitchDataType; + variable DMA2LLTXREM3_GlitchData : VitalGlitchDataType; + variable DMA2LLTXSOFN_GlitchData : VitalGlitchDataType; + variable DMA2LLTXSOPN_GlitchData : VitalGlitchDataType; + variable DMA2LLTXSRCRDYN_GlitchData : VitalGlitchDataType; + variable DMA2RXIRQ_GlitchData : VitalGlitchDataType; + variable DMA2TXIRQ_GlitchData : VitalGlitchDataType; + variable DMA3LLRSTENGINEACK_GlitchData : VitalGlitchDataType; + variable DMA3LLRXDSTRDYN_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD0_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD1_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD2_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD3_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD4_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD5_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD6_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD7_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD8_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD9_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD10_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD11_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD12_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD13_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD14_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD15_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD16_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD17_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD18_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD19_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD20_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD21_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD22_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD23_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD24_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD25_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD26_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD27_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD28_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD29_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD30_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD31_GlitchData : VitalGlitchDataType; + variable DMA3LLTXEOFN_GlitchData : VitalGlitchDataType; + variable DMA3LLTXEOPN_GlitchData : VitalGlitchDataType; + variable DMA3LLTXREM0_GlitchData : VitalGlitchDataType; + variable DMA3LLTXREM1_GlitchData : VitalGlitchDataType; + variable DMA3LLTXREM2_GlitchData : VitalGlitchDataType; + variable DMA3LLTXREM3_GlitchData : VitalGlitchDataType; + variable DMA3LLTXSOFN_GlitchData : VitalGlitchDataType; + variable DMA3LLTXSOPN_GlitchData : VitalGlitchDataType; + variable DMA3LLTXSRCRDYN_GlitchData : VitalGlitchDataType; + variable DMA3RXIRQ_GlitchData : VitalGlitchDataType; + variable DMA3TXIRQ_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS0_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS1_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS2_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS3_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS4_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS5_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS6_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS7_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS8_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS9_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT0_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT1_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT2_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT3_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT4_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT5_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT6_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT7_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT8_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT9_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT10_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT11_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT12_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT13_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT14_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT15_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT16_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT17_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT18_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT19_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT20_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT21_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT22_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT23_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT24_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT25_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT26_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT27_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT28_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT29_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT30_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT31_GlitchData : VitalGlitchDataType; + variable PPCDMDCRREAD_GlitchData : VitalGlitchDataType; + variable PPCDMDCRUABUS20_GlitchData : VitalGlitchDataType; + variable PPCDMDCRUABUS21_GlitchData : VitalGlitchDataType; + variable PPCDMDCRWRITE_GlitchData : VitalGlitchDataType; + variable PPCMPLBABORT_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS0_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS1_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS2_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS3_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS4_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS5_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS6_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS7_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS8_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS9_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS10_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS11_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS12_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS13_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS14_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS15_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS16_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS17_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS18_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS19_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS20_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS21_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS22_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS23_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS24_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS25_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS26_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS27_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS28_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS29_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS30_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS31_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE0_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE1_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE2_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE3_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE4_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE5_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE6_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE7_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE8_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE9_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE10_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE11_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE12_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE13_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE14_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE15_GlitchData : VitalGlitchDataType; + variable PPCMPLBBUSLOCK_GlitchData : VitalGlitchDataType; + variable PPCMPLBLOCKERR_GlitchData : VitalGlitchDataType; + variable PPCMPLBPRIORITY0_GlitchData : VitalGlitchDataType; + variable PPCMPLBPRIORITY1_GlitchData : VitalGlitchDataType; + variable PPCMPLBRDBURST_GlitchData : VitalGlitchDataType; + variable PPCMPLBREQUEST_GlitchData : VitalGlitchDataType; + variable PPCMPLBRNW_GlitchData : VitalGlitchDataType; + variable PPCMPLBSIZE0_GlitchData : VitalGlitchDataType; + variable PPCMPLBSIZE1_GlitchData : VitalGlitchDataType; + variable PPCMPLBSIZE2_GlitchData : VitalGlitchDataType; + variable PPCMPLBSIZE3_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE0_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE1_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE2_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE3_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE4_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE5_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE6_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE7_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE8_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE9_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE10_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE11_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE12_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE13_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE14_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE15_GlitchData : VitalGlitchDataType; + variable PPCMPLBTYPE0_GlitchData : VitalGlitchDataType; + variable PPCMPLBTYPE1_GlitchData : VitalGlitchDataType; + variable PPCMPLBTYPE2_GlitchData : VitalGlitchDataType; + variable PPCMPLBUABUS28_GlitchData : VitalGlitchDataType; + variable PPCMPLBUABUS29_GlitchData : VitalGlitchDataType; + variable PPCMPLBUABUS30_GlitchData : VitalGlitchDataType; + variable PPCMPLBUABUS31_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRBURST_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS0_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS1_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS2_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS3_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS4_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS5_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS6_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS7_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS8_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS9_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS10_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS11_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS12_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS13_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS14_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS15_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS16_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS17_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS18_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS19_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS20_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS21_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS22_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS23_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS24_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS25_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS26_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS27_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS28_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS29_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS30_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS31_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS32_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS33_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS34_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS35_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS36_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS37_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS38_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS39_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS40_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS41_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS42_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS43_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS44_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS45_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS46_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS47_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS48_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS49_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS50_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS51_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS52_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS53_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS54_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS55_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS56_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS57_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS58_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS59_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS60_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS61_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS62_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS63_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS64_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS65_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS66_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS67_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS68_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS69_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS70_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS71_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS72_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS73_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS74_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS75_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS76_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS77_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS78_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS79_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS80_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS81_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS82_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS83_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS84_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS85_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS86_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS87_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS88_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS89_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS90_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS91_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS92_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS93_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS94_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS95_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS96_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS97_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS98_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS99_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS100_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS101_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS102_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS103_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS104_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS105_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS106_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS107_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS108_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS109_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS110_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS111_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS112_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS113_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS114_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS115_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS116_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS117_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS118_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS119_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS120_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS121_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS122_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS123_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS124_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS125_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS126_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS127_GlitchData : VitalGlitchDataType; + variable PPCS0PLBADDRACK_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMBUSY0_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMBUSY1_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMBUSY2_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMBUSY3_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMIRQ0_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMIRQ1_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMIRQ2_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMIRQ3_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMRDERR0_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMRDERR1_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMRDERR2_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMRDERR3_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMWRERR0_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMWRERR1_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMWRERR2_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMWRERR3_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDBTERM_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDCOMP_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDACK_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS0_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS1_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS2_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS3_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS4_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS5_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS6_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS7_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS8_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS9_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS10_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS11_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS12_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS13_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS14_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS15_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS16_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS17_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS18_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS19_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS20_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS21_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS22_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS23_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS24_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS25_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS26_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS27_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS28_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS29_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS30_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS31_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS32_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS33_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS34_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS35_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS36_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS37_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS38_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS39_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS40_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS41_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS42_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS43_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS44_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS45_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS46_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS47_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS48_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS49_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS50_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS51_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS52_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS53_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS54_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS55_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS56_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS57_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS58_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS59_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS60_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS61_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS62_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS63_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS64_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS65_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS66_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS67_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS68_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS69_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS70_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS71_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS72_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS73_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS74_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS75_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS76_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS77_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS78_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS79_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS80_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS81_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS82_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS83_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS84_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS85_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS86_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS87_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS88_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS89_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS90_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS91_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS92_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS93_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS94_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS95_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS96_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS97_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS98_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS99_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS100_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS101_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS102_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS103_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS104_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS105_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS106_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS107_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS108_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS109_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS110_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS111_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS112_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS113_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS114_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS115_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS116_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS117_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS118_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS119_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS120_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS121_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS122_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS123_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS124_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS125_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS126_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS127_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDWDADDR0_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDWDADDR1_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDWDADDR2_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDWDADDR3_GlitchData : VitalGlitchDataType; + variable PPCS0PLBREARBITRATE_GlitchData : VitalGlitchDataType; + variable PPCS0PLBSSIZE0_GlitchData : VitalGlitchDataType; + variable PPCS0PLBSSIZE1_GlitchData : VitalGlitchDataType; + variable PPCS0PLBWAIT_GlitchData : VitalGlitchDataType; + variable PPCS0PLBWRBTERM_GlitchData : VitalGlitchDataType; + variable PPCS0PLBWRCOMP_GlitchData : VitalGlitchDataType; + variable PPCS0PLBWRDACK_GlitchData : VitalGlitchDataType; + variable PPCS1PLBADDRACK_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMBUSY0_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMBUSY1_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMBUSY2_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMBUSY3_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMIRQ0_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMIRQ1_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMIRQ2_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMIRQ3_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMRDERR0_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMRDERR1_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMRDERR2_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMRDERR3_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMWRERR0_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMWRERR1_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMWRERR2_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMWRERR3_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDBTERM_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDCOMP_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDACK_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS0_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS1_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS2_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS3_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS4_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS5_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS6_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS7_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS8_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS9_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS10_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS11_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS12_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS13_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS14_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS15_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS16_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS17_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS18_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS19_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS20_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS21_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS22_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS23_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS24_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS25_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS26_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS27_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS28_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS29_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS30_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS31_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS32_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS33_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS34_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS35_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS36_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS37_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS38_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS39_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS40_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS41_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS42_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS43_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS44_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS45_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS46_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS47_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS48_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS49_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS50_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS51_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS52_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS53_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS54_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS55_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS56_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS57_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS58_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS59_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS60_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS61_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS62_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS63_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS64_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS65_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS66_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS67_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS68_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS69_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS70_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS71_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS72_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS73_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS74_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS75_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS76_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS77_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS78_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS79_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS80_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS81_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS82_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS83_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS84_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS85_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS86_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS87_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS88_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS89_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS90_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS91_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS92_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS93_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS94_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS95_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS96_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS97_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS98_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS99_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS100_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS101_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS102_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS103_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS104_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS105_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS106_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS107_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS108_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS109_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS110_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS111_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS112_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS113_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS114_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS115_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS116_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS117_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS118_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS119_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS120_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS121_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS122_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS123_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS124_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS125_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS126_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS127_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDWDADDR0_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDWDADDR1_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDWDADDR2_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDWDADDR3_GlitchData : VitalGlitchDataType; + variable PPCS1PLBREARBITRATE_GlitchData : VitalGlitchDataType; + variable PPCS1PLBSSIZE0_GlitchData : VitalGlitchDataType; + variable PPCS1PLBSSIZE1_GlitchData : VitalGlitchDataType; + variable PPCS1PLBWAIT_GlitchData : VitalGlitchDataType; + variable PPCS1PLBWRBTERM_GlitchData : VitalGlitchDataType; + variable PPCS1PLBWRCOMP_GlitchData : VitalGlitchDataType; + variable PPCS1PLBWRDACK_GlitchData : VitalGlitchDataType; + variable APUFCMDECFPUOP_GlitchData : VitalGlitchDataType; + variable APUFCMDECLDSTXFERSIZE0_GlitchData : VitalGlitchDataType; + variable APUFCMDECLDSTXFERSIZE1_GlitchData : VitalGlitchDataType; + variable APUFCMDECLDSTXFERSIZE2_GlitchData : VitalGlitchDataType; + variable APUFCMDECLOAD_GlitchData : VitalGlitchDataType; + variable APUFCMDECNONAUTON_GlitchData : VitalGlitchDataType; + variable APUFCMDECSTORE_GlitchData : VitalGlitchDataType; + variable APUFCMDECUDI0_GlitchData : VitalGlitchDataType; + variable APUFCMDECUDI1_GlitchData : VitalGlitchDataType; + variable APUFCMDECUDI2_GlitchData : VitalGlitchDataType; + variable APUFCMDECUDI3_GlitchData : VitalGlitchDataType; + variable APUFCMDECUDIVALID_GlitchData : VitalGlitchDataType; + variable APUFCMENDIAN_GlitchData : VitalGlitchDataType; + variable APUFCMFLUSH_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION0_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION1_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION2_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION3_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION4_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION5_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION6_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION7_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION8_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION9_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION10_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION11_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION12_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION13_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION14_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION15_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION16_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION17_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION18_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION19_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION20_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION21_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION22_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION23_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION24_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION25_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION26_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION27_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION28_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION29_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION30_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION31_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRVALID_GlitchData : VitalGlitchDataType; + variable APUFCMLOADBYTEADDR0_GlitchData : VitalGlitchDataType; + variable APUFCMLOADBYTEADDR1_GlitchData : VitalGlitchDataType; + variable APUFCMLOADBYTEADDR2_GlitchData : VitalGlitchDataType; + variable APUFCMLOADBYTEADDR3_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA0_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA1_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA2_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA3_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA4_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA5_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA6_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA7_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA8_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA9_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA10_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA11_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA12_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA13_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA14_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA15_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA16_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA17_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA18_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA19_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA20_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA21_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA22_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA23_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA24_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA25_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA26_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA27_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA28_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA29_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA30_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA31_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA32_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA33_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA34_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA35_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA36_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA37_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA38_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA39_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA40_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA41_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA42_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA43_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA44_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA45_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA46_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA47_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA48_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA49_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA50_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA51_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA52_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA53_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA54_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA55_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA56_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA57_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA58_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA59_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA60_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA61_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA62_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA63_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA64_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA65_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA66_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA67_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA68_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA69_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA70_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA71_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA72_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA73_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA74_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA75_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA76_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA77_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA78_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA79_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA80_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA81_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA82_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA83_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA84_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA85_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA86_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA87_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA88_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA89_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA90_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA91_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA92_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA93_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA94_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA95_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA96_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA97_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA98_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA99_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA100_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA101_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA102_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA103_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA104_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA105_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA106_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA107_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA108_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA109_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA110_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA111_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA112_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA113_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA114_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA115_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA116_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA117_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA118_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA119_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA120_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA121_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA122_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA123_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA124_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA125_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA126_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA127_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDVALID_GlitchData : VitalGlitchDataType; + variable APUFCMMSRFE0_GlitchData : VitalGlitchDataType; + variable APUFCMMSRFE1_GlitchData : VitalGlitchDataType; + variable APUFCMNEXTINSTRREADY_GlitchData : VitalGlitchDataType; + variable APUFCMOPERANDVALID_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA0_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA1_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA2_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA3_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA4_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA5_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA6_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA7_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA8_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA9_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA10_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA11_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA12_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA13_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA14_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA15_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA16_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA17_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA18_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA19_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA20_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA21_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA22_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA23_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA24_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA25_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA26_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA27_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA28_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA29_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA30_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA31_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA0_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA1_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA2_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA3_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA4_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA5_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA6_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA7_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA8_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA9_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA10_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA11_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA12_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA13_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA14_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA15_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA16_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA17_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA18_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA19_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA20_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA21_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA22_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA23_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA24_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA25_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA26_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA27_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA28_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA29_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA30_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA31_GlitchData : VitalGlitchDataType; + variable APUFCMWRITEBACKOK_GlitchData : VitalGlitchDataType; + variable C440CPMCORESLEEPREQ_GlitchData : VitalGlitchDataType; + variable C440CPMDECIRPTREQ_GlitchData : VitalGlitchDataType; + variable C440CPMFITIRPTREQ_GlitchData : VitalGlitchDataType; + variable C440CPMMSRCE_GlitchData : VitalGlitchDataType; + variable C440CPMMSREE_GlitchData : VitalGlitchDataType; + variable C440CPMTIMERRESETREQ_GlitchData : VitalGlitchDataType; + variable C440CPMWDIRPTREQ_GlitchData : VitalGlitchDataType; + variable C440DBGSYSTEMCONTROL0_GlitchData : VitalGlitchDataType; + variable C440DBGSYSTEMCONTROL1_GlitchData : VitalGlitchDataType; + variable C440DBGSYSTEMCONTROL2_GlitchData : VitalGlitchDataType; + variable C440DBGSYSTEMCONTROL3_GlitchData : VitalGlitchDataType; + variable C440DBGSYSTEMCONTROL4_GlitchData : VitalGlitchDataType; + variable C440DBGSYSTEMCONTROL5_GlitchData : VitalGlitchDataType; + variable C440DBGSYSTEMCONTROL6_GlitchData : VitalGlitchDataType; + variable C440DBGSYSTEMCONTROL7_GlitchData : VitalGlitchDataType; + variable C440JTGTDO_GlitchData : VitalGlitchDataType; + variable C440JTGTDOEN_GlitchData : VitalGlitchDataType; + variable C440MACHINECHECK_GlitchData : VitalGlitchDataType; + variable C440RSTCHIPRESETREQ_GlitchData : VitalGlitchDataType; + variable C440RSTCORERESETREQ_GlitchData : VitalGlitchDataType; + variable C440RSTSYSTEMRESETREQ_GlitchData : VitalGlitchDataType; + variable C440TRCBRANCHSTATUS0_GlitchData : VitalGlitchDataType; + variable C440TRCBRANCHSTATUS1_GlitchData : VitalGlitchDataType; + variable C440TRCBRANCHSTATUS2_GlitchData : VitalGlitchDataType; + variable C440TRCCYCLE_GlitchData : VitalGlitchDataType; + variable C440TRCEXECUTIONSTATUS0_GlitchData : VitalGlitchDataType; + variable C440TRCEXECUTIONSTATUS1_GlitchData : VitalGlitchDataType; + variable C440TRCEXECUTIONSTATUS2_GlitchData : VitalGlitchDataType; + variable C440TRCEXECUTIONSTATUS3_GlitchData : VitalGlitchDataType; + variable C440TRCEXECUTIONSTATUS4_GlitchData : VitalGlitchDataType; + variable C440TRCTRACESTATUS0_GlitchData : VitalGlitchDataType; + variable C440TRCTRACESTATUS1_GlitchData : VitalGlitchDataType; + variable C440TRCTRACESTATUS2_GlitchData : VitalGlitchDataType; + variable C440TRCTRACESTATUS3_GlitchData : VitalGlitchDataType; + variable C440TRCTRACESTATUS4_GlitchData : VitalGlitchDataType; + variable C440TRCTRACESTATUS5_GlitchData : VitalGlitchDataType; + variable C440TRCTRACESTATUS6_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTOUT_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE0_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE1_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE2_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE3_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE4_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE5_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE6_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE7_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE8_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE9_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE10_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE11_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE12_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE13_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS0_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS1_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS2_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS3_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS4_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS5_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS6_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS7_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS8_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS9_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS10_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS11_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS12_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS13_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS14_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS15_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS16_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS17_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS18_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS19_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS20_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS21_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS22_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS23_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS24_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS25_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS26_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS27_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS28_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS29_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS30_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS31_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS32_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS33_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS34_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS35_GlitchData : VitalGlitchDataType; + variable MIMCADDRESSVALID_GlitchData : VitalGlitchDataType; + variable MIMCBANKCONFLICT_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE0_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE1_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE2_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE3_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE4_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE5_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE6_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE7_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE8_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE9_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE10_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE11_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE12_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE13_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE14_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE15_GlitchData : VitalGlitchDataType; + variable MIMCREADNOTWRITE_GlitchData : VitalGlitchDataType; + variable MIMCROWCONFLICT_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA0_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA1_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA2_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA3_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA4_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA5_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA6_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA7_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA8_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA9_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA10_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA11_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA12_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA13_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA14_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA15_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA16_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA17_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA18_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA19_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA20_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA21_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA22_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA23_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA24_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA25_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA26_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA27_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA28_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA29_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA30_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA31_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA32_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA33_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA34_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA35_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA36_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA37_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA38_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA39_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA40_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA41_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA42_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA43_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA44_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA45_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA46_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA47_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA48_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA49_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA50_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA51_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA52_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA53_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA54_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA55_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA56_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA57_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA58_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA59_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA60_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA61_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA62_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA63_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA64_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA65_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA66_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA67_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA68_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA69_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA70_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA71_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA72_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA73_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA74_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA75_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA76_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA77_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA78_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA79_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA80_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA81_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA82_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA83_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA84_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA85_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA86_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA87_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA88_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA89_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA90_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA91_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA92_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA93_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA94_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA95_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA96_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA97_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA98_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA99_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA100_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA101_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA102_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA103_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA104_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA105_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA106_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA107_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA108_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA109_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA110_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA111_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA112_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA113_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA114_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA115_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA116_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA117_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA118_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA119_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA120_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA121_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA122_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA123_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA124_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA125_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA126_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA127_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATAVALID_GlitchData : VitalGlitchDataType; + variable PPCCPMINTERCONNECTBUSY_GlitchData : VitalGlitchDataType; + variable PPCDSDCRACK_GlitchData : VitalGlitchDataType; + variable PPCDSDCRTIMEOUTWAIT_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN0_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN1_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN2_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN3_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN4_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN5_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN6_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN7_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN8_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN9_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN10_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN11_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN12_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN13_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN14_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN15_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN16_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN17_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN18_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN19_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN20_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN21_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN22_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN23_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN24_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN25_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN26_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN27_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN28_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN29_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN30_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN31_GlitchData : VitalGlitchDataType; + variable PPCEICINTERCONNECTIRQ_GlitchData : VitalGlitchDataType; +begin + + VitalPathDelay01 + ( + OutSignal => DMA0LLRSTENGINEACK, + GlitchData => DMA0LLRSTENGINEACK_GlitchData, + OutSignalName => "DMA0LLRSTENGINEACK", + OutTemp => DMA0LLRSTENGINEACK_OUT, + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLRXDSTRDYN, + GlitchData => DMA0LLRXDSTRDYN_GlitchData, + OutSignalName => "DMA0LLRXDSTRDYN", + OutTemp => DMA0LLRXDSTRDYN_OUT, + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(0), + GlitchData => DMA0LLTXD0_GlitchData, + OutSignalName => "DMA0LLTXD(0)", + OutTemp => DMA0LLTXD_OUT(0), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(1), + GlitchData => DMA0LLTXD1_GlitchData, + OutSignalName => "DMA0LLTXD(1)", + OutTemp => DMA0LLTXD_OUT(1), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(2), + GlitchData => DMA0LLTXD2_GlitchData, + OutSignalName => "DMA0LLTXD(2)", + OutTemp => DMA0LLTXD_OUT(2), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(3), + GlitchData => DMA0LLTXD3_GlitchData, + OutSignalName => "DMA0LLTXD(3)", + OutTemp => DMA0LLTXD_OUT(3), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(4), + GlitchData => DMA0LLTXD4_GlitchData, + OutSignalName => "DMA0LLTXD(4)", + OutTemp => DMA0LLTXD_OUT(4), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(5), + GlitchData => DMA0LLTXD5_GlitchData, + OutSignalName => "DMA0LLTXD(5)", + OutTemp => DMA0LLTXD_OUT(5), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(6), + GlitchData => DMA0LLTXD6_GlitchData, + OutSignalName => "DMA0LLTXD(6)", + OutTemp => DMA0LLTXD_OUT(6), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(7), + GlitchData => DMA0LLTXD7_GlitchData, + OutSignalName => "DMA0LLTXD(7)", + OutTemp => DMA0LLTXD_OUT(7), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(8), + GlitchData => DMA0LLTXD8_GlitchData, + OutSignalName => "DMA0LLTXD(8)", + OutTemp => DMA0LLTXD_OUT(8), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(9), + GlitchData => DMA0LLTXD9_GlitchData, + OutSignalName => "DMA0LLTXD(9)", + OutTemp => DMA0LLTXD_OUT(9), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(10), + GlitchData => DMA0LLTXD10_GlitchData, + OutSignalName => "DMA0LLTXD(10)", + OutTemp => DMA0LLTXD_OUT(10), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(11), + GlitchData => DMA0LLTXD11_GlitchData, + OutSignalName => "DMA0LLTXD(11)", + OutTemp => DMA0LLTXD_OUT(11), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(12), + GlitchData => DMA0LLTXD12_GlitchData, + OutSignalName => "DMA0LLTXD(12)", + OutTemp => DMA0LLTXD_OUT(12), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(13), + GlitchData => DMA0LLTXD13_GlitchData, + OutSignalName => "DMA0LLTXD(13)", + OutTemp => DMA0LLTXD_OUT(13), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(14), + GlitchData => DMA0LLTXD14_GlitchData, + OutSignalName => "DMA0LLTXD(14)", + OutTemp => DMA0LLTXD_OUT(14), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(15), + GlitchData => DMA0LLTXD15_GlitchData, + OutSignalName => "DMA0LLTXD(15)", + OutTemp => DMA0LLTXD_OUT(15), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(16), + GlitchData => DMA0LLTXD16_GlitchData, + OutSignalName => "DMA0LLTXD(16)", + OutTemp => DMA0LLTXD_OUT(16), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(17), + GlitchData => DMA0LLTXD17_GlitchData, + OutSignalName => "DMA0LLTXD(17)", + OutTemp => DMA0LLTXD_OUT(17), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(18), + GlitchData => DMA0LLTXD18_GlitchData, + OutSignalName => "DMA0LLTXD(18)", + OutTemp => DMA0LLTXD_OUT(18), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(19), + GlitchData => DMA0LLTXD19_GlitchData, + OutSignalName => "DMA0LLTXD(19)", + OutTemp => DMA0LLTXD_OUT(19), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(20), + GlitchData => DMA0LLTXD20_GlitchData, + OutSignalName => "DMA0LLTXD(20)", + OutTemp => DMA0LLTXD_OUT(20), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(21), + GlitchData => DMA0LLTXD21_GlitchData, + OutSignalName => "DMA0LLTXD(21)", + OutTemp => DMA0LLTXD_OUT(21), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(22), + GlitchData => DMA0LLTXD22_GlitchData, + OutSignalName => "DMA0LLTXD(22)", + OutTemp => DMA0LLTXD_OUT(22), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(23), + GlitchData => DMA0LLTXD23_GlitchData, + OutSignalName => "DMA0LLTXD(23)", + OutTemp => DMA0LLTXD_OUT(23), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(24), + GlitchData => DMA0LLTXD24_GlitchData, + OutSignalName => "DMA0LLTXD(24)", + OutTemp => DMA0LLTXD_OUT(24), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(25), + GlitchData => DMA0LLTXD25_GlitchData, + OutSignalName => "DMA0LLTXD(25)", + OutTemp => DMA0LLTXD_OUT(25), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(26), + GlitchData => DMA0LLTXD26_GlitchData, + OutSignalName => "DMA0LLTXD(26)", + OutTemp => DMA0LLTXD_OUT(26), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(27), + GlitchData => DMA0LLTXD27_GlitchData, + OutSignalName => "DMA0LLTXD(27)", + OutTemp => DMA0LLTXD_OUT(27), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(28), + GlitchData => DMA0LLTXD28_GlitchData, + OutSignalName => "DMA0LLTXD(28)", + OutTemp => DMA0LLTXD_OUT(28), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(29), + GlitchData => DMA0LLTXD29_GlitchData, + OutSignalName => "DMA0LLTXD(29)", + OutTemp => DMA0LLTXD_OUT(29), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(30), + GlitchData => DMA0LLTXD30_GlitchData, + OutSignalName => "DMA0LLTXD(30)", + OutTemp => DMA0LLTXD_OUT(30), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(31), + GlitchData => DMA0LLTXD31_GlitchData, + OutSignalName => "DMA0LLTXD(31)", + OutTemp => DMA0LLTXD_OUT(31), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXEOFN, + GlitchData => DMA0LLTXEOFN_GlitchData, + OutSignalName => "DMA0LLTXEOFN", + OutTemp => DMA0LLTXEOFN_OUT, + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXEOPN, + GlitchData => DMA0LLTXEOPN_GlitchData, + OutSignalName => "DMA0LLTXEOPN", + OutTemp => DMA0LLTXEOPN_OUT, + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXREM(0), + GlitchData => DMA0LLTXREM0_GlitchData, + OutSignalName => "DMA0LLTXREM(0)", + OutTemp => DMA0LLTXREM_OUT(0), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXREM(1), + GlitchData => DMA0LLTXREM1_GlitchData, + OutSignalName => "DMA0LLTXREM(1)", + OutTemp => DMA0LLTXREM_OUT(1), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXREM(2), + GlitchData => DMA0LLTXREM2_GlitchData, + OutSignalName => "DMA0LLTXREM(2)", + OutTemp => DMA0LLTXREM_OUT(2), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXREM(3), + GlitchData => DMA0LLTXREM3_GlitchData, + OutSignalName => "DMA0LLTXREM(3)", + OutTemp => DMA0LLTXREM_OUT(3), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXSOFN, + GlitchData => DMA0LLTXSOFN_GlitchData, + OutSignalName => "DMA0LLTXSOFN", + OutTemp => DMA0LLTXSOFN_OUT, + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXSOPN, + GlitchData => DMA0LLTXSOPN_GlitchData, + OutSignalName => "DMA0LLTXSOPN", + OutTemp => DMA0LLTXSOPN_OUT, + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXSRCRDYN, + GlitchData => DMA0LLTXSRCRDYN_GlitchData, + OutSignalName => "DMA0LLTXSRCRDYN", + OutTemp => DMA0LLTXSRCRDYN_OUT, + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0RXIRQ, + GlitchData => DMA0RXIRQ_GlitchData, + OutSignalName => "DMA0RXIRQ", + OutTemp => DMA0RXIRQ_OUT, + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0TXIRQ, + GlitchData => DMA0TXIRQ_GlitchData, + OutSignalName => "DMA0TXIRQ", + OutTemp => DMA0TXIRQ_OUT, + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLRSTENGINEACK, + GlitchData => DMA1LLRSTENGINEACK_GlitchData, + OutSignalName => "DMA1LLRSTENGINEACK", + OutTemp => DMA1LLRSTENGINEACK_OUT, + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLRXDSTRDYN, + GlitchData => DMA1LLRXDSTRDYN_GlitchData, + OutSignalName => "DMA1LLRXDSTRDYN", + OutTemp => DMA1LLRXDSTRDYN_OUT, + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(0), + GlitchData => DMA1LLTXD0_GlitchData, + OutSignalName => "DMA1LLTXD(0)", + OutTemp => DMA1LLTXD_OUT(0), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(1), + GlitchData => DMA1LLTXD1_GlitchData, + OutSignalName => "DMA1LLTXD(1)", + OutTemp => DMA1LLTXD_OUT(1), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(2), + GlitchData => DMA1LLTXD2_GlitchData, + OutSignalName => "DMA1LLTXD(2)", + OutTemp => DMA1LLTXD_OUT(2), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(3), + GlitchData => DMA1LLTXD3_GlitchData, + OutSignalName => "DMA1LLTXD(3)", + OutTemp => DMA1LLTXD_OUT(3), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(4), + GlitchData => DMA1LLTXD4_GlitchData, + OutSignalName => "DMA1LLTXD(4)", + OutTemp => DMA1LLTXD_OUT(4), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(5), + GlitchData => DMA1LLTXD5_GlitchData, + OutSignalName => "DMA1LLTXD(5)", + OutTemp => DMA1LLTXD_OUT(5), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(6), + GlitchData => DMA1LLTXD6_GlitchData, + OutSignalName => "DMA1LLTXD(6)", + OutTemp => DMA1LLTXD_OUT(6), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(7), + GlitchData => DMA1LLTXD7_GlitchData, + OutSignalName => "DMA1LLTXD(7)", + OutTemp => DMA1LLTXD_OUT(7), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(8), + GlitchData => DMA1LLTXD8_GlitchData, + OutSignalName => "DMA1LLTXD(8)", + OutTemp => DMA1LLTXD_OUT(8), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(9), + GlitchData => DMA1LLTXD9_GlitchData, + OutSignalName => "DMA1LLTXD(9)", + OutTemp => DMA1LLTXD_OUT(9), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(10), + GlitchData => DMA1LLTXD10_GlitchData, + OutSignalName => "DMA1LLTXD(10)", + OutTemp => DMA1LLTXD_OUT(10), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(11), + GlitchData => DMA1LLTXD11_GlitchData, + OutSignalName => "DMA1LLTXD(11)", + OutTemp => DMA1LLTXD_OUT(11), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(12), + GlitchData => DMA1LLTXD12_GlitchData, + OutSignalName => "DMA1LLTXD(12)", + OutTemp => DMA1LLTXD_OUT(12), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(13), + GlitchData => DMA1LLTXD13_GlitchData, + OutSignalName => "DMA1LLTXD(13)", + OutTemp => DMA1LLTXD_OUT(13), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(14), + GlitchData => DMA1LLTXD14_GlitchData, + OutSignalName => "DMA1LLTXD(14)", + OutTemp => DMA1LLTXD_OUT(14), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(15), + GlitchData => DMA1LLTXD15_GlitchData, + OutSignalName => "DMA1LLTXD(15)", + OutTemp => DMA1LLTXD_OUT(15), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(16), + GlitchData => DMA1LLTXD16_GlitchData, + OutSignalName => "DMA1LLTXD(16)", + OutTemp => DMA1LLTXD_OUT(16), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(17), + GlitchData => DMA1LLTXD17_GlitchData, + OutSignalName => "DMA1LLTXD(17)", + OutTemp => DMA1LLTXD_OUT(17), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(18), + GlitchData => DMA1LLTXD18_GlitchData, + OutSignalName => "DMA1LLTXD(18)", + OutTemp => DMA1LLTXD_OUT(18), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(19), + GlitchData => DMA1LLTXD19_GlitchData, + OutSignalName => "DMA1LLTXD(19)", + OutTemp => DMA1LLTXD_OUT(19), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(20), + GlitchData => DMA1LLTXD20_GlitchData, + OutSignalName => "DMA1LLTXD(20)", + OutTemp => DMA1LLTXD_OUT(20), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(21), + GlitchData => DMA1LLTXD21_GlitchData, + OutSignalName => "DMA1LLTXD(21)", + OutTemp => DMA1LLTXD_OUT(21), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(22), + GlitchData => DMA1LLTXD22_GlitchData, + OutSignalName => "DMA1LLTXD(22)", + OutTemp => DMA1LLTXD_OUT(22), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(23), + GlitchData => DMA1LLTXD23_GlitchData, + OutSignalName => "DMA1LLTXD(23)", + OutTemp => DMA1LLTXD_OUT(23), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(24), + GlitchData => DMA1LLTXD24_GlitchData, + OutSignalName => "DMA1LLTXD(24)", + OutTemp => DMA1LLTXD_OUT(24), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(25), + GlitchData => DMA1LLTXD25_GlitchData, + OutSignalName => "DMA1LLTXD(25)", + OutTemp => DMA1LLTXD_OUT(25), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(26), + GlitchData => DMA1LLTXD26_GlitchData, + OutSignalName => "DMA1LLTXD(26)", + OutTemp => DMA1LLTXD_OUT(26), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(27), + GlitchData => DMA1LLTXD27_GlitchData, + OutSignalName => "DMA1LLTXD(27)", + OutTemp => DMA1LLTXD_OUT(27), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(28), + GlitchData => DMA1LLTXD28_GlitchData, + OutSignalName => "DMA1LLTXD(28)", + OutTemp => DMA1LLTXD_OUT(28), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(29), + GlitchData => DMA1LLTXD29_GlitchData, + OutSignalName => "DMA1LLTXD(29)", + OutTemp => DMA1LLTXD_OUT(29), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(30), + GlitchData => DMA1LLTXD30_GlitchData, + OutSignalName => "DMA1LLTXD(30)", + OutTemp => DMA1LLTXD_OUT(30), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(31), + GlitchData => DMA1LLTXD31_GlitchData, + OutSignalName => "DMA1LLTXD(31)", + OutTemp => DMA1LLTXD_OUT(31), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXEOFN, + GlitchData => DMA1LLTXEOFN_GlitchData, + OutSignalName => "DMA1LLTXEOFN", + OutTemp => DMA1LLTXEOFN_OUT, + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXEOPN, + GlitchData => DMA1LLTXEOPN_GlitchData, + OutSignalName => "DMA1LLTXEOPN", + OutTemp => DMA1LLTXEOPN_OUT, + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXREM(0), + GlitchData => DMA1LLTXREM0_GlitchData, + OutSignalName => "DMA1LLTXREM(0)", + OutTemp => DMA1LLTXREM_OUT(0), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXREM(1), + GlitchData => DMA1LLTXREM1_GlitchData, + OutSignalName => "DMA1LLTXREM(1)", + OutTemp => DMA1LLTXREM_OUT(1), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXREM(2), + GlitchData => DMA1LLTXREM2_GlitchData, + OutSignalName => "DMA1LLTXREM(2)", + OutTemp => DMA1LLTXREM_OUT(2), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXREM(3), + GlitchData => DMA1LLTXREM3_GlitchData, + OutSignalName => "DMA1LLTXREM(3)", + OutTemp => DMA1LLTXREM_OUT(3), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXSOFN, + GlitchData => DMA1LLTXSOFN_GlitchData, + OutSignalName => "DMA1LLTXSOFN", + OutTemp => DMA1LLTXSOFN_OUT, + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXSOPN, + GlitchData => DMA1LLTXSOPN_GlitchData, + OutSignalName => "DMA1LLTXSOPN", + OutTemp => DMA1LLTXSOPN_OUT, + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXSRCRDYN, + GlitchData => DMA1LLTXSRCRDYN_GlitchData, + OutSignalName => "DMA1LLTXSRCRDYN", + OutTemp => DMA1LLTXSRCRDYN_OUT, + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1RXIRQ, + GlitchData => DMA1RXIRQ_GlitchData, + OutSignalName => "DMA1RXIRQ", + OutTemp => DMA1RXIRQ_OUT, + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1TXIRQ, + GlitchData => DMA1TXIRQ_GlitchData, + OutSignalName => "DMA1TXIRQ", + OutTemp => DMA1TXIRQ_OUT, + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLRSTENGINEACK, + GlitchData => DMA2LLRSTENGINEACK_GlitchData, + OutSignalName => "DMA2LLRSTENGINEACK", + OutTemp => DMA2LLRSTENGINEACK_OUT, + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLRXDSTRDYN, + GlitchData => DMA2LLRXDSTRDYN_GlitchData, + OutSignalName => "DMA2LLRXDSTRDYN", + OutTemp => DMA2LLRXDSTRDYN_OUT, + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(0), + GlitchData => DMA2LLTXD0_GlitchData, + OutSignalName => "DMA2LLTXD(0)", + OutTemp => DMA2LLTXD_OUT(0), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(1), + GlitchData => DMA2LLTXD1_GlitchData, + OutSignalName => "DMA2LLTXD(1)", + OutTemp => DMA2LLTXD_OUT(1), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(2), + GlitchData => DMA2LLTXD2_GlitchData, + OutSignalName => "DMA2LLTXD(2)", + OutTemp => DMA2LLTXD_OUT(2), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(3), + GlitchData => DMA2LLTXD3_GlitchData, + OutSignalName => "DMA2LLTXD(3)", + OutTemp => DMA2LLTXD_OUT(3), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(4), + GlitchData => DMA2LLTXD4_GlitchData, + OutSignalName => "DMA2LLTXD(4)", + OutTemp => DMA2LLTXD_OUT(4), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(5), + GlitchData => DMA2LLTXD5_GlitchData, + OutSignalName => "DMA2LLTXD(5)", + OutTemp => DMA2LLTXD_OUT(5), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(6), + GlitchData => DMA2LLTXD6_GlitchData, + OutSignalName => "DMA2LLTXD(6)", + OutTemp => DMA2LLTXD_OUT(6), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(7), + GlitchData => DMA2LLTXD7_GlitchData, + OutSignalName => "DMA2LLTXD(7)", + OutTemp => DMA2LLTXD_OUT(7), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(8), + GlitchData => DMA2LLTXD8_GlitchData, + OutSignalName => "DMA2LLTXD(8)", + OutTemp => DMA2LLTXD_OUT(8), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(9), + GlitchData => DMA2LLTXD9_GlitchData, + OutSignalName => "DMA2LLTXD(9)", + OutTemp => DMA2LLTXD_OUT(9), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(10), + GlitchData => DMA2LLTXD10_GlitchData, + OutSignalName => "DMA2LLTXD(10)", + OutTemp => DMA2LLTXD_OUT(10), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(11), + GlitchData => DMA2LLTXD11_GlitchData, + OutSignalName => "DMA2LLTXD(11)", + OutTemp => DMA2LLTXD_OUT(11), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(12), + GlitchData => DMA2LLTXD12_GlitchData, + OutSignalName => "DMA2LLTXD(12)", + OutTemp => DMA2LLTXD_OUT(12), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(13), + GlitchData => DMA2LLTXD13_GlitchData, + OutSignalName => "DMA2LLTXD(13)", + OutTemp => DMA2LLTXD_OUT(13), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(14), + GlitchData => DMA2LLTXD14_GlitchData, + OutSignalName => "DMA2LLTXD(14)", + OutTemp => DMA2LLTXD_OUT(14), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(15), + GlitchData => DMA2LLTXD15_GlitchData, + OutSignalName => "DMA2LLTXD(15)", + OutTemp => DMA2LLTXD_OUT(15), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(16), + GlitchData => DMA2LLTXD16_GlitchData, + OutSignalName => "DMA2LLTXD(16)", + OutTemp => DMA2LLTXD_OUT(16), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(17), + GlitchData => DMA2LLTXD17_GlitchData, + OutSignalName => "DMA2LLTXD(17)", + OutTemp => DMA2LLTXD_OUT(17), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(18), + GlitchData => DMA2LLTXD18_GlitchData, + OutSignalName => "DMA2LLTXD(18)", + OutTemp => DMA2LLTXD_OUT(18), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(19), + GlitchData => DMA2LLTXD19_GlitchData, + OutSignalName => "DMA2LLTXD(19)", + OutTemp => DMA2LLTXD_OUT(19), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(20), + GlitchData => DMA2LLTXD20_GlitchData, + OutSignalName => "DMA2LLTXD(20)", + OutTemp => DMA2LLTXD_OUT(20), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(21), + GlitchData => DMA2LLTXD21_GlitchData, + OutSignalName => "DMA2LLTXD(21)", + OutTemp => DMA2LLTXD_OUT(21), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(22), + GlitchData => DMA2LLTXD22_GlitchData, + OutSignalName => "DMA2LLTXD(22)", + OutTemp => DMA2LLTXD_OUT(22), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(23), + GlitchData => DMA2LLTXD23_GlitchData, + OutSignalName => "DMA2LLTXD(23)", + OutTemp => DMA2LLTXD_OUT(23), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(24), + GlitchData => DMA2LLTXD24_GlitchData, + OutSignalName => "DMA2LLTXD(24)", + OutTemp => DMA2LLTXD_OUT(24), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(25), + GlitchData => DMA2LLTXD25_GlitchData, + OutSignalName => "DMA2LLTXD(25)", + OutTemp => DMA2LLTXD_OUT(25), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(26), + GlitchData => DMA2LLTXD26_GlitchData, + OutSignalName => "DMA2LLTXD(26)", + OutTemp => DMA2LLTXD_OUT(26), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(27), + GlitchData => DMA2LLTXD27_GlitchData, + OutSignalName => "DMA2LLTXD(27)", + OutTemp => DMA2LLTXD_OUT(27), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(28), + GlitchData => DMA2LLTXD28_GlitchData, + OutSignalName => "DMA2LLTXD(28)", + OutTemp => DMA2LLTXD_OUT(28), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(29), + GlitchData => DMA2LLTXD29_GlitchData, + OutSignalName => "DMA2LLTXD(29)", + OutTemp => DMA2LLTXD_OUT(29), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(30), + GlitchData => DMA2LLTXD30_GlitchData, + OutSignalName => "DMA2LLTXD(30)", + OutTemp => DMA2LLTXD_OUT(30), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(31), + GlitchData => DMA2LLTXD31_GlitchData, + OutSignalName => "DMA2LLTXD(31)", + OutTemp => DMA2LLTXD_OUT(31), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXEOFN, + GlitchData => DMA2LLTXEOFN_GlitchData, + OutSignalName => "DMA2LLTXEOFN", + OutTemp => DMA2LLTXEOFN_OUT, + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXEOPN, + GlitchData => DMA2LLTXEOPN_GlitchData, + OutSignalName => "DMA2LLTXEOPN", + OutTemp => DMA2LLTXEOPN_OUT, + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXREM(0), + GlitchData => DMA2LLTXREM0_GlitchData, + OutSignalName => "DMA2LLTXREM(0)", + OutTemp => DMA2LLTXREM_OUT(0), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXREM(1), + GlitchData => DMA2LLTXREM1_GlitchData, + OutSignalName => "DMA2LLTXREM(1)", + OutTemp => DMA2LLTXREM_OUT(1), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXREM(2), + GlitchData => DMA2LLTXREM2_GlitchData, + OutSignalName => "DMA2LLTXREM(2)", + OutTemp => DMA2LLTXREM_OUT(2), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXREM(3), + GlitchData => DMA2LLTXREM3_GlitchData, + OutSignalName => "DMA2LLTXREM(3)", + OutTemp => DMA2LLTXREM_OUT(3), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXSOFN, + GlitchData => DMA2LLTXSOFN_GlitchData, + OutSignalName => "DMA2LLTXSOFN", + OutTemp => DMA2LLTXSOFN_OUT, + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXSOPN, + GlitchData => DMA2LLTXSOPN_GlitchData, + OutSignalName => "DMA2LLTXSOPN", + OutTemp => DMA2LLTXSOPN_OUT, + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXSRCRDYN, + GlitchData => DMA2LLTXSRCRDYN_GlitchData, + OutSignalName => "DMA2LLTXSRCRDYN", + OutTemp => DMA2LLTXSRCRDYN_OUT, + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2RXIRQ, + GlitchData => DMA2RXIRQ_GlitchData, + OutSignalName => "DMA2RXIRQ", + OutTemp => DMA2RXIRQ_OUT, + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2TXIRQ, + GlitchData => DMA2TXIRQ_GlitchData, + OutSignalName => "DMA2TXIRQ", + OutTemp => DMA2TXIRQ_OUT, + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLRSTENGINEACK, + GlitchData => DMA3LLRSTENGINEACK_GlitchData, + OutSignalName => "DMA3LLRSTENGINEACK", + OutTemp => DMA3LLRSTENGINEACK_OUT, + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLRXDSTRDYN, + GlitchData => DMA3LLRXDSTRDYN_GlitchData, + OutSignalName => "DMA3LLRXDSTRDYN", + OutTemp => DMA3LLRXDSTRDYN_OUT, + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(0), + GlitchData => DMA3LLTXD0_GlitchData, + OutSignalName => "DMA3LLTXD(0)", + OutTemp => DMA3LLTXD_OUT(0), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(1), + GlitchData => DMA3LLTXD1_GlitchData, + OutSignalName => "DMA3LLTXD(1)", + OutTemp => DMA3LLTXD_OUT(1), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(2), + GlitchData => DMA3LLTXD2_GlitchData, + OutSignalName => "DMA3LLTXD(2)", + OutTemp => DMA3LLTXD_OUT(2), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(3), + GlitchData => DMA3LLTXD3_GlitchData, + OutSignalName => "DMA3LLTXD(3)", + OutTemp => DMA3LLTXD_OUT(3), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(4), + GlitchData => DMA3LLTXD4_GlitchData, + OutSignalName => "DMA3LLTXD(4)", + OutTemp => DMA3LLTXD_OUT(4), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(5), + GlitchData => DMA3LLTXD5_GlitchData, + OutSignalName => "DMA3LLTXD(5)", + OutTemp => DMA3LLTXD_OUT(5), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(6), + GlitchData => DMA3LLTXD6_GlitchData, + OutSignalName => "DMA3LLTXD(6)", + OutTemp => DMA3LLTXD_OUT(6), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(7), + GlitchData => DMA3LLTXD7_GlitchData, + OutSignalName => "DMA3LLTXD(7)", + OutTemp => DMA3LLTXD_OUT(7), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(8), + GlitchData => DMA3LLTXD8_GlitchData, + OutSignalName => "DMA3LLTXD(8)", + OutTemp => DMA3LLTXD_OUT(8), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(9), + GlitchData => DMA3LLTXD9_GlitchData, + OutSignalName => "DMA3LLTXD(9)", + OutTemp => DMA3LLTXD_OUT(9), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(10), + GlitchData => DMA3LLTXD10_GlitchData, + OutSignalName => "DMA3LLTXD(10)", + OutTemp => DMA3LLTXD_OUT(10), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(11), + GlitchData => DMA3LLTXD11_GlitchData, + OutSignalName => "DMA3LLTXD(11)", + OutTemp => DMA3LLTXD_OUT(11), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(12), + GlitchData => DMA3LLTXD12_GlitchData, + OutSignalName => "DMA3LLTXD(12)", + OutTemp => DMA3LLTXD_OUT(12), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(13), + GlitchData => DMA3LLTXD13_GlitchData, + OutSignalName => "DMA3LLTXD(13)", + OutTemp => DMA3LLTXD_OUT(13), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(14), + GlitchData => DMA3LLTXD14_GlitchData, + OutSignalName => "DMA3LLTXD(14)", + OutTemp => DMA3LLTXD_OUT(14), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(15), + GlitchData => DMA3LLTXD15_GlitchData, + OutSignalName => "DMA3LLTXD(15)", + OutTemp => DMA3LLTXD_OUT(15), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(16), + GlitchData => DMA3LLTXD16_GlitchData, + OutSignalName => "DMA3LLTXD(16)", + OutTemp => DMA3LLTXD_OUT(16), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(17), + GlitchData => DMA3LLTXD17_GlitchData, + OutSignalName => "DMA3LLTXD(17)", + OutTemp => DMA3LLTXD_OUT(17), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(18), + GlitchData => DMA3LLTXD18_GlitchData, + OutSignalName => "DMA3LLTXD(18)", + OutTemp => DMA3LLTXD_OUT(18), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(19), + GlitchData => DMA3LLTXD19_GlitchData, + OutSignalName => "DMA3LLTXD(19)", + OutTemp => DMA3LLTXD_OUT(19), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(20), + GlitchData => DMA3LLTXD20_GlitchData, + OutSignalName => "DMA3LLTXD(20)", + OutTemp => DMA3LLTXD_OUT(20), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(21), + GlitchData => DMA3LLTXD21_GlitchData, + OutSignalName => "DMA3LLTXD(21)", + OutTemp => DMA3LLTXD_OUT(21), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(22), + GlitchData => DMA3LLTXD22_GlitchData, + OutSignalName => "DMA3LLTXD(22)", + OutTemp => DMA3LLTXD_OUT(22), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(23), + GlitchData => DMA3LLTXD23_GlitchData, + OutSignalName => "DMA3LLTXD(23)", + OutTemp => DMA3LLTXD_OUT(23), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(24), + GlitchData => DMA3LLTXD24_GlitchData, + OutSignalName => "DMA3LLTXD(24)", + OutTemp => DMA3LLTXD_OUT(24), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(25), + GlitchData => DMA3LLTXD25_GlitchData, + OutSignalName => "DMA3LLTXD(25)", + OutTemp => DMA3LLTXD_OUT(25), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(26), + GlitchData => DMA3LLTXD26_GlitchData, + OutSignalName => "DMA3LLTXD(26)", + OutTemp => DMA3LLTXD_OUT(26), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(27), + GlitchData => DMA3LLTXD27_GlitchData, + OutSignalName => "DMA3LLTXD(27)", + OutTemp => DMA3LLTXD_OUT(27), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(28), + GlitchData => DMA3LLTXD28_GlitchData, + OutSignalName => "DMA3LLTXD(28)", + OutTemp => DMA3LLTXD_OUT(28), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(29), + GlitchData => DMA3LLTXD29_GlitchData, + OutSignalName => "DMA3LLTXD(29)", + OutTemp => DMA3LLTXD_OUT(29), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(30), + GlitchData => DMA3LLTXD30_GlitchData, + OutSignalName => "DMA3LLTXD(30)", + OutTemp => DMA3LLTXD_OUT(30), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(31), + GlitchData => DMA3LLTXD31_GlitchData, + OutSignalName => "DMA3LLTXD(31)", + OutTemp => DMA3LLTXD_OUT(31), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXEOFN, + GlitchData => DMA3LLTXEOFN_GlitchData, + OutSignalName => "DMA3LLTXEOFN", + OutTemp => DMA3LLTXEOFN_OUT, + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXEOPN, + GlitchData => DMA3LLTXEOPN_GlitchData, + OutSignalName => "DMA3LLTXEOPN", + OutTemp => DMA3LLTXEOPN_OUT, + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXREM(0), + GlitchData => DMA3LLTXREM0_GlitchData, + OutSignalName => "DMA3LLTXREM(0)", + OutTemp => DMA3LLTXREM_OUT(0), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXREM(1), + GlitchData => DMA3LLTXREM1_GlitchData, + OutSignalName => "DMA3LLTXREM(1)", + OutTemp => DMA3LLTXREM_OUT(1), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXREM(2), + GlitchData => DMA3LLTXREM2_GlitchData, + OutSignalName => "DMA3LLTXREM(2)", + OutTemp => DMA3LLTXREM_OUT(2), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXREM(3), + GlitchData => DMA3LLTXREM3_GlitchData, + OutSignalName => "DMA3LLTXREM(3)", + OutTemp => DMA3LLTXREM_OUT(3), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXSOFN, + GlitchData => DMA3LLTXSOFN_GlitchData, + OutSignalName => "DMA3LLTXSOFN", + OutTemp => DMA3LLTXSOFN_OUT, + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXSOPN, + GlitchData => DMA3LLTXSOPN_GlitchData, + OutSignalName => "DMA3LLTXSOPN", + OutTemp => DMA3LLTXSOPN_OUT, + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXSRCRDYN, + GlitchData => DMA3LLTXSRCRDYN_GlitchData, + OutSignalName => "DMA3LLTXSRCRDYN", + OutTemp => DMA3LLTXSRCRDYN_OUT, + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3RXIRQ, + GlitchData => DMA3RXIRQ_GlitchData, + OutSignalName => "DMA3RXIRQ", + OutTemp => DMA3RXIRQ_OUT, + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3TXIRQ, + GlitchData => DMA3TXIRQ_GlitchData, + OutSignalName => "DMA3TXIRQ", + OutTemp => DMA3TXIRQ_OUT, + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(0), + GlitchData => PPCDMDCRABUS0_GlitchData, + OutSignalName => "PPCDMDCRABUS(0)", + OutTemp => PPCDMDCRABUS_OUT(0), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(1), + GlitchData => PPCDMDCRABUS1_GlitchData, + OutSignalName => "PPCDMDCRABUS(1)", + OutTemp => PPCDMDCRABUS_OUT(1), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(2), + GlitchData => PPCDMDCRABUS2_GlitchData, + OutSignalName => "PPCDMDCRABUS(2)", + OutTemp => PPCDMDCRABUS_OUT(2), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(3), + GlitchData => PPCDMDCRABUS3_GlitchData, + OutSignalName => "PPCDMDCRABUS(3)", + OutTemp => PPCDMDCRABUS_OUT(3), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(4), + GlitchData => PPCDMDCRABUS4_GlitchData, + OutSignalName => "PPCDMDCRABUS(4)", + OutTemp => PPCDMDCRABUS_OUT(4), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(5), + GlitchData => PPCDMDCRABUS5_GlitchData, + OutSignalName => "PPCDMDCRABUS(5)", + OutTemp => PPCDMDCRABUS_OUT(5), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(6), + GlitchData => PPCDMDCRABUS6_GlitchData, + OutSignalName => "PPCDMDCRABUS(6)", + OutTemp => PPCDMDCRABUS_OUT(6), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(7), + GlitchData => PPCDMDCRABUS7_GlitchData, + OutSignalName => "PPCDMDCRABUS(7)", + OutTemp => PPCDMDCRABUS_OUT(7), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(8), + GlitchData => PPCDMDCRABUS8_GlitchData, + OutSignalName => "PPCDMDCRABUS(8)", + OutTemp => PPCDMDCRABUS_OUT(8), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(9), + GlitchData => PPCDMDCRABUS9_GlitchData, + OutSignalName => "PPCDMDCRABUS(9)", + OutTemp => PPCDMDCRABUS_OUT(9), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(0), + GlitchData => PPCDMDCRDBUSOUT0_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(0)", + OutTemp => PPCDMDCRDBUSOUT_OUT(0), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(1), + GlitchData => PPCDMDCRDBUSOUT1_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(1)", + OutTemp => PPCDMDCRDBUSOUT_OUT(1), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(2), + GlitchData => PPCDMDCRDBUSOUT2_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(2)", + OutTemp => PPCDMDCRDBUSOUT_OUT(2), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(3), + GlitchData => PPCDMDCRDBUSOUT3_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(3)", + OutTemp => PPCDMDCRDBUSOUT_OUT(3), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(4), + GlitchData => PPCDMDCRDBUSOUT4_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(4)", + OutTemp => PPCDMDCRDBUSOUT_OUT(4), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(5), + GlitchData => PPCDMDCRDBUSOUT5_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(5)", + OutTemp => PPCDMDCRDBUSOUT_OUT(5), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(6), + GlitchData => PPCDMDCRDBUSOUT6_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(6)", + OutTemp => PPCDMDCRDBUSOUT_OUT(6), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(7), + GlitchData => PPCDMDCRDBUSOUT7_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(7)", + OutTemp => PPCDMDCRDBUSOUT_OUT(7), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(8), + GlitchData => PPCDMDCRDBUSOUT8_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(8)", + OutTemp => PPCDMDCRDBUSOUT_OUT(8), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(9), + GlitchData => PPCDMDCRDBUSOUT9_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(9)", + OutTemp => PPCDMDCRDBUSOUT_OUT(9), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(10), + GlitchData => PPCDMDCRDBUSOUT10_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(10)", + OutTemp => PPCDMDCRDBUSOUT_OUT(10), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(11), + GlitchData => PPCDMDCRDBUSOUT11_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(11)", + OutTemp => PPCDMDCRDBUSOUT_OUT(11), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(12), + GlitchData => PPCDMDCRDBUSOUT12_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(12)", + OutTemp => PPCDMDCRDBUSOUT_OUT(12), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(13), + GlitchData => PPCDMDCRDBUSOUT13_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(13)", + OutTemp => PPCDMDCRDBUSOUT_OUT(13), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(14), + GlitchData => PPCDMDCRDBUSOUT14_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(14)", + OutTemp => PPCDMDCRDBUSOUT_OUT(14), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(15), + GlitchData => PPCDMDCRDBUSOUT15_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(15)", + OutTemp => PPCDMDCRDBUSOUT_OUT(15), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(16), + GlitchData => PPCDMDCRDBUSOUT16_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(16)", + OutTemp => PPCDMDCRDBUSOUT_OUT(16), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(17), + GlitchData => PPCDMDCRDBUSOUT17_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(17)", + OutTemp => PPCDMDCRDBUSOUT_OUT(17), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(18), + GlitchData => PPCDMDCRDBUSOUT18_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(18)", + OutTemp => PPCDMDCRDBUSOUT_OUT(18), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(19), + GlitchData => PPCDMDCRDBUSOUT19_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(19)", + OutTemp => PPCDMDCRDBUSOUT_OUT(19), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(20), + GlitchData => PPCDMDCRDBUSOUT20_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(20)", + OutTemp => PPCDMDCRDBUSOUT_OUT(20), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(21), + GlitchData => PPCDMDCRDBUSOUT21_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(21)", + OutTemp => PPCDMDCRDBUSOUT_OUT(21), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(22), + GlitchData => PPCDMDCRDBUSOUT22_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(22)", + OutTemp => PPCDMDCRDBUSOUT_OUT(22), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(23), + GlitchData => PPCDMDCRDBUSOUT23_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(23)", + OutTemp => PPCDMDCRDBUSOUT_OUT(23), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(24), + GlitchData => PPCDMDCRDBUSOUT24_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(24)", + OutTemp => PPCDMDCRDBUSOUT_OUT(24), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(25), + GlitchData => PPCDMDCRDBUSOUT25_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(25)", + OutTemp => PPCDMDCRDBUSOUT_OUT(25), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(26), + GlitchData => PPCDMDCRDBUSOUT26_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(26)", + OutTemp => PPCDMDCRDBUSOUT_OUT(26), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(27), + GlitchData => PPCDMDCRDBUSOUT27_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(27)", + OutTemp => PPCDMDCRDBUSOUT_OUT(27), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(28), + GlitchData => PPCDMDCRDBUSOUT28_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(28)", + OutTemp => PPCDMDCRDBUSOUT_OUT(28), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(29), + GlitchData => PPCDMDCRDBUSOUT29_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(29)", + OutTemp => PPCDMDCRDBUSOUT_OUT(29), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(30), + GlitchData => PPCDMDCRDBUSOUT30_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(30)", + OutTemp => PPCDMDCRDBUSOUT_OUT(30), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(31), + GlitchData => PPCDMDCRDBUSOUT31_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(31)", + OutTemp => PPCDMDCRDBUSOUT_OUT(31), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRREAD, + GlitchData => PPCDMDCRREAD_GlitchData, + OutSignalName => "PPCDMDCRREAD", + OutTemp => PPCDMDCRREAD_OUT, + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRUABUS(20), + GlitchData => PPCDMDCRUABUS20_GlitchData, + OutSignalName => "PPCDMDCRUABUS(20)", + OutTemp => PPCDMDCRUABUS_OUT(20), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRUABUS(21), + GlitchData => PPCDMDCRUABUS21_GlitchData, + OutSignalName => "PPCDMDCRUABUS(21)", + OutTemp => PPCDMDCRUABUS_OUT(21), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRWRITE, + GlitchData => PPCDMDCRWRITE_GlitchData, + OutSignalName => "PPCDMDCRWRITE", + OutTemp => PPCDMDCRWRITE_OUT, + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABORT, + GlitchData => PPCMPLBABORT_GlitchData, + OutSignalName => "PPCMPLBABORT", + OutTemp => PPCMPLBABORT_OUT, + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(0), + GlitchData => PPCMPLBABUS0_GlitchData, + OutSignalName => "PPCMPLBABUS(0)", + OutTemp => PPCMPLBABUS_OUT(0), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(1), + GlitchData => PPCMPLBABUS1_GlitchData, + OutSignalName => "PPCMPLBABUS(1)", + OutTemp => PPCMPLBABUS_OUT(1), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(2), + GlitchData => PPCMPLBABUS2_GlitchData, + OutSignalName => "PPCMPLBABUS(2)", + OutTemp => PPCMPLBABUS_OUT(2), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(3), + GlitchData => PPCMPLBABUS3_GlitchData, + OutSignalName => "PPCMPLBABUS(3)", + OutTemp => PPCMPLBABUS_OUT(3), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(4), + GlitchData => PPCMPLBABUS4_GlitchData, + OutSignalName => "PPCMPLBABUS(4)", + OutTemp => PPCMPLBABUS_OUT(4), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(5), + GlitchData => PPCMPLBABUS5_GlitchData, + OutSignalName => "PPCMPLBABUS(5)", + OutTemp => PPCMPLBABUS_OUT(5), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(6), + GlitchData => PPCMPLBABUS6_GlitchData, + OutSignalName => "PPCMPLBABUS(6)", + OutTemp => PPCMPLBABUS_OUT(6), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(7), + GlitchData => PPCMPLBABUS7_GlitchData, + OutSignalName => "PPCMPLBABUS(7)", + OutTemp => PPCMPLBABUS_OUT(7), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(8), + GlitchData => PPCMPLBABUS8_GlitchData, + OutSignalName => "PPCMPLBABUS(8)", + OutTemp => PPCMPLBABUS_OUT(8), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(9), + GlitchData => PPCMPLBABUS9_GlitchData, + OutSignalName => "PPCMPLBABUS(9)", + OutTemp => PPCMPLBABUS_OUT(9), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(10), + GlitchData => PPCMPLBABUS10_GlitchData, + OutSignalName => "PPCMPLBABUS(10)", + OutTemp => PPCMPLBABUS_OUT(10), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(11), + GlitchData => PPCMPLBABUS11_GlitchData, + OutSignalName => "PPCMPLBABUS(11)", + OutTemp => PPCMPLBABUS_OUT(11), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(12), + GlitchData => PPCMPLBABUS12_GlitchData, + OutSignalName => "PPCMPLBABUS(12)", + OutTemp => PPCMPLBABUS_OUT(12), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(13), + GlitchData => PPCMPLBABUS13_GlitchData, + OutSignalName => "PPCMPLBABUS(13)", + OutTemp => PPCMPLBABUS_OUT(13), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(14), + GlitchData => PPCMPLBABUS14_GlitchData, + OutSignalName => "PPCMPLBABUS(14)", + OutTemp => PPCMPLBABUS_OUT(14), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(15), + GlitchData => PPCMPLBABUS15_GlitchData, + OutSignalName => "PPCMPLBABUS(15)", + OutTemp => PPCMPLBABUS_OUT(15), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(16), + GlitchData => PPCMPLBABUS16_GlitchData, + OutSignalName => "PPCMPLBABUS(16)", + OutTemp => PPCMPLBABUS_OUT(16), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(17), + GlitchData => PPCMPLBABUS17_GlitchData, + OutSignalName => "PPCMPLBABUS(17)", + OutTemp => PPCMPLBABUS_OUT(17), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(18), + GlitchData => PPCMPLBABUS18_GlitchData, + OutSignalName => "PPCMPLBABUS(18)", + OutTemp => PPCMPLBABUS_OUT(18), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(19), + GlitchData => PPCMPLBABUS19_GlitchData, + OutSignalName => "PPCMPLBABUS(19)", + OutTemp => PPCMPLBABUS_OUT(19), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(20), + GlitchData => PPCMPLBABUS20_GlitchData, + OutSignalName => "PPCMPLBABUS(20)", + OutTemp => PPCMPLBABUS_OUT(20), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(21), + GlitchData => PPCMPLBABUS21_GlitchData, + OutSignalName => "PPCMPLBABUS(21)", + OutTemp => PPCMPLBABUS_OUT(21), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(22), + GlitchData => PPCMPLBABUS22_GlitchData, + OutSignalName => "PPCMPLBABUS(22)", + OutTemp => PPCMPLBABUS_OUT(22), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(23), + GlitchData => PPCMPLBABUS23_GlitchData, + OutSignalName => "PPCMPLBABUS(23)", + OutTemp => PPCMPLBABUS_OUT(23), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(24), + GlitchData => PPCMPLBABUS24_GlitchData, + OutSignalName => "PPCMPLBABUS(24)", + OutTemp => PPCMPLBABUS_OUT(24), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(25), + GlitchData => PPCMPLBABUS25_GlitchData, + OutSignalName => "PPCMPLBABUS(25)", + OutTemp => PPCMPLBABUS_OUT(25), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(26), + GlitchData => PPCMPLBABUS26_GlitchData, + OutSignalName => "PPCMPLBABUS(26)", + OutTemp => PPCMPLBABUS_OUT(26), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(27), + GlitchData => PPCMPLBABUS27_GlitchData, + OutSignalName => "PPCMPLBABUS(27)", + OutTemp => PPCMPLBABUS_OUT(27), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(28), + GlitchData => PPCMPLBABUS28_GlitchData, + OutSignalName => "PPCMPLBABUS(28)", + OutTemp => PPCMPLBABUS_OUT(28), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(29), + GlitchData => PPCMPLBABUS29_GlitchData, + OutSignalName => "PPCMPLBABUS(29)", + OutTemp => PPCMPLBABUS_OUT(29), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(30), + GlitchData => PPCMPLBABUS30_GlitchData, + OutSignalName => "PPCMPLBABUS(30)", + OutTemp => PPCMPLBABUS_OUT(30), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(31), + GlitchData => PPCMPLBABUS31_GlitchData, + OutSignalName => "PPCMPLBABUS(31)", + OutTemp => PPCMPLBABUS_OUT(31), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(0), + GlitchData => PPCMPLBBE0_GlitchData, + OutSignalName => "PPCMPLBBE(0)", + OutTemp => PPCMPLBBE_OUT(0), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(1), + GlitchData => PPCMPLBBE1_GlitchData, + OutSignalName => "PPCMPLBBE(1)", + OutTemp => PPCMPLBBE_OUT(1), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(2), + GlitchData => PPCMPLBBE2_GlitchData, + OutSignalName => "PPCMPLBBE(2)", + OutTemp => PPCMPLBBE_OUT(2), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(3), + GlitchData => PPCMPLBBE3_GlitchData, + OutSignalName => "PPCMPLBBE(3)", + OutTemp => PPCMPLBBE_OUT(3), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(4), + GlitchData => PPCMPLBBE4_GlitchData, + OutSignalName => "PPCMPLBBE(4)", + OutTemp => PPCMPLBBE_OUT(4), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(5), + GlitchData => PPCMPLBBE5_GlitchData, + OutSignalName => "PPCMPLBBE(5)", + OutTemp => PPCMPLBBE_OUT(5), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(6), + GlitchData => PPCMPLBBE6_GlitchData, + OutSignalName => "PPCMPLBBE(6)", + OutTemp => PPCMPLBBE_OUT(6), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(7), + GlitchData => PPCMPLBBE7_GlitchData, + OutSignalName => "PPCMPLBBE(7)", + OutTemp => PPCMPLBBE_OUT(7), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(8), + GlitchData => PPCMPLBBE8_GlitchData, + OutSignalName => "PPCMPLBBE(8)", + OutTemp => PPCMPLBBE_OUT(8), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(9), + GlitchData => PPCMPLBBE9_GlitchData, + OutSignalName => "PPCMPLBBE(9)", + OutTemp => PPCMPLBBE_OUT(9), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(10), + GlitchData => PPCMPLBBE10_GlitchData, + OutSignalName => "PPCMPLBBE(10)", + OutTemp => PPCMPLBBE_OUT(10), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(11), + GlitchData => PPCMPLBBE11_GlitchData, + OutSignalName => "PPCMPLBBE(11)", + OutTemp => PPCMPLBBE_OUT(11), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(12), + GlitchData => PPCMPLBBE12_GlitchData, + OutSignalName => "PPCMPLBBE(12)", + OutTemp => PPCMPLBBE_OUT(12), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(13), + GlitchData => PPCMPLBBE13_GlitchData, + OutSignalName => "PPCMPLBBE(13)", + OutTemp => PPCMPLBBE_OUT(13), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(14), + GlitchData => PPCMPLBBE14_GlitchData, + OutSignalName => "PPCMPLBBE(14)", + OutTemp => PPCMPLBBE_OUT(14), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(15), + GlitchData => PPCMPLBBE15_GlitchData, + OutSignalName => "PPCMPLBBE(15)", + OutTemp => PPCMPLBBE_OUT(15), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBUSLOCK, + GlitchData => PPCMPLBBUSLOCK_GlitchData, + OutSignalName => "PPCMPLBBUSLOCK", + OutTemp => PPCMPLBBUSLOCK_OUT, + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBLOCKERR, + GlitchData => PPCMPLBLOCKERR_GlitchData, + OutSignalName => "PPCMPLBLOCKERR", + OutTemp => PPCMPLBLOCKERR_OUT, + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBPRIORITY(0), + GlitchData => PPCMPLBPRIORITY0_GlitchData, + OutSignalName => "PPCMPLBPRIORITY(0)", + OutTemp => PPCMPLBPRIORITY_OUT(0), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBPRIORITY(1), + GlitchData => PPCMPLBPRIORITY1_GlitchData, + OutSignalName => "PPCMPLBPRIORITY(1)", + OutTemp => PPCMPLBPRIORITY_OUT(1), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBRDBURST, + GlitchData => PPCMPLBRDBURST_GlitchData, + OutSignalName => "PPCMPLBRDBURST", + OutTemp => PPCMPLBRDBURST_OUT, + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBREQUEST, + GlitchData => PPCMPLBREQUEST_GlitchData, + OutSignalName => "PPCMPLBREQUEST", + OutTemp => PPCMPLBREQUEST_OUT, + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBRNW, + GlitchData => PPCMPLBRNW_GlitchData, + OutSignalName => "PPCMPLBRNW", + OutTemp => PPCMPLBRNW_OUT, + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBSIZE(0), + GlitchData => PPCMPLBSIZE0_GlitchData, + OutSignalName => "PPCMPLBSIZE(0)", + OutTemp => PPCMPLBSIZE_OUT(0), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBSIZE(1), + GlitchData => PPCMPLBSIZE1_GlitchData, + OutSignalName => "PPCMPLBSIZE(1)", + OutTemp => PPCMPLBSIZE_OUT(1), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBSIZE(2), + GlitchData => PPCMPLBSIZE2_GlitchData, + OutSignalName => "PPCMPLBSIZE(2)", + OutTemp => PPCMPLBSIZE_OUT(2), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBSIZE(3), + GlitchData => PPCMPLBSIZE3_GlitchData, + OutSignalName => "PPCMPLBSIZE(3)", + OutTemp => PPCMPLBSIZE_OUT(3), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(0), + GlitchData => PPCMPLBTATTRIBUTE0_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(0)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(0), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(1), + GlitchData => PPCMPLBTATTRIBUTE1_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(1)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(1), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(2), + GlitchData => PPCMPLBTATTRIBUTE2_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(2)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(2), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(3), + GlitchData => PPCMPLBTATTRIBUTE3_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(3)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(3), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(4), + GlitchData => PPCMPLBTATTRIBUTE4_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(4)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(4), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(5), + GlitchData => PPCMPLBTATTRIBUTE5_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(5)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(5), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(6), + GlitchData => PPCMPLBTATTRIBUTE6_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(6)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(6), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(7), + GlitchData => PPCMPLBTATTRIBUTE7_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(7)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(7), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(8), + GlitchData => PPCMPLBTATTRIBUTE8_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(8)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(8), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(9), + GlitchData => PPCMPLBTATTRIBUTE9_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(9)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(9), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(10), + GlitchData => PPCMPLBTATTRIBUTE10_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(10)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(10), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(11), + GlitchData => PPCMPLBTATTRIBUTE11_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(11)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(11), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(12), + GlitchData => PPCMPLBTATTRIBUTE12_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(12)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(12), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(13), + GlitchData => PPCMPLBTATTRIBUTE13_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(13)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(13), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(14), + GlitchData => PPCMPLBTATTRIBUTE14_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(14)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(14), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(15), + GlitchData => PPCMPLBTATTRIBUTE15_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(15)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(15), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTYPE(0), + GlitchData => PPCMPLBTYPE0_GlitchData, + OutSignalName => "PPCMPLBTYPE(0)", + OutTemp => PPCMPLBTYPE_OUT(0), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTYPE(1), + GlitchData => PPCMPLBTYPE1_GlitchData, + OutSignalName => "PPCMPLBTYPE(1)", + OutTemp => PPCMPLBTYPE_OUT(1), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTYPE(2), + GlitchData => PPCMPLBTYPE2_GlitchData, + OutSignalName => "PPCMPLBTYPE(2)", + OutTemp => PPCMPLBTYPE_OUT(2), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBUABUS(28), + GlitchData => PPCMPLBUABUS28_GlitchData, + OutSignalName => "PPCMPLBUABUS(28)", + OutTemp => PPCMPLBUABUS_OUT(28), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBUABUS(29), + GlitchData => PPCMPLBUABUS29_GlitchData, + OutSignalName => "PPCMPLBUABUS(29)", + OutTemp => PPCMPLBUABUS_OUT(29), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBUABUS(30), + GlitchData => PPCMPLBUABUS30_GlitchData, + OutSignalName => "PPCMPLBUABUS(30)", + OutTemp => PPCMPLBUABUS_OUT(30), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBUABUS(31), + GlitchData => PPCMPLBUABUS31_GlitchData, + OutSignalName => "PPCMPLBUABUS(31)", + OutTemp => PPCMPLBUABUS_OUT(31), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRBURST, + GlitchData => PPCMPLBWRBURST_GlitchData, + OutSignalName => "PPCMPLBWRBURST", + OutTemp => PPCMPLBWRBURST_OUT, + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(0), + GlitchData => PPCMPLBWRDBUS0_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(0)", + OutTemp => PPCMPLBWRDBUS_OUT(0), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(1), + GlitchData => PPCMPLBWRDBUS1_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(1)", + OutTemp => PPCMPLBWRDBUS_OUT(1), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(2), + GlitchData => PPCMPLBWRDBUS2_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(2)", + OutTemp => PPCMPLBWRDBUS_OUT(2), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(3), + GlitchData => PPCMPLBWRDBUS3_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(3)", + OutTemp => PPCMPLBWRDBUS_OUT(3), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(4), + GlitchData => PPCMPLBWRDBUS4_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(4)", + OutTemp => PPCMPLBWRDBUS_OUT(4), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(5), + GlitchData => PPCMPLBWRDBUS5_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(5)", + OutTemp => PPCMPLBWRDBUS_OUT(5), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(6), + GlitchData => PPCMPLBWRDBUS6_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(6)", + OutTemp => PPCMPLBWRDBUS_OUT(6), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(7), + GlitchData => PPCMPLBWRDBUS7_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(7)", + OutTemp => PPCMPLBWRDBUS_OUT(7), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(8), + GlitchData => PPCMPLBWRDBUS8_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(8)", + OutTemp => PPCMPLBWRDBUS_OUT(8), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(9), + GlitchData => PPCMPLBWRDBUS9_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(9)", + OutTemp => PPCMPLBWRDBUS_OUT(9), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(10), + GlitchData => PPCMPLBWRDBUS10_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(10)", + OutTemp => PPCMPLBWRDBUS_OUT(10), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(11), + GlitchData => PPCMPLBWRDBUS11_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(11)", + OutTemp => PPCMPLBWRDBUS_OUT(11), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(12), + GlitchData => PPCMPLBWRDBUS12_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(12)", + OutTemp => PPCMPLBWRDBUS_OUT(12), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(13), + GlitchData => PPCMPLBWRDBUS13_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(13)", + OutTemp => PPCMPLBWRDBUS_OUT(13), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(14), + GlitchData => PPCMPLBWRDBUS14_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(14)", + OutTemp => PPCMPLBWRDBUS_OUT(14), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(15), + GlitchData => PPCMPLBWRDBUS15_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(15)", + OutTemp => PPCMPLBWRDBUS_OUT(15), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(16), + GlitchData => PPCMPLBWRDBUS16_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(16)", + OutTemp => PPCMPLBWRDBUS_OUT(16), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(17), + GlitchData => PPCMPLBWRDBUS17_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(17)", + OutTemp => PPCMPLBWRDBUS_OUT(17), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(18), + GlitchData => PPCMPLBWRDBUS18_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(18)", + OutTemp => PPCMPLBWRDBUS_OUT(18), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(19), + GlitchData => PPCMPLBWRDBUS19_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(19)", + OutTemp => PPCMPLBWRDBUS_OUT(19), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(20), + GlitchData => PPCMPLBWRDBUS20_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(20)", + OutTemp => PPCMPLBWRDBUS_OUT(20), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(21), + GlitchData => PPCMPLBWRDBUS21_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(21)", + OutTemp => PPCMPLBWRDBUS_OUT(21), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(22), + GlitchData => PPCMPLBWRDBUS22_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(22)", + OutTemp => PPCMPLBWRDBUS_OUT(22), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(23), + GlitchData => PPCMPLBWRDBUS23_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(23)", + OutTemp => PPCMPLBWRDBUS_OUT(23), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(24), + GlitchData => PPCMPLBWRDBUS24_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(24)", + OutTemp => PPCMPLBWRDBUS_OUT(24), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(25), + GlitchData => PPCMPLBWRDBUS25_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(25)", + OutTemp => PPCMPLBWRDBUS_OUT(25), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(26), + GlitchData => PPCMPLBWRDBUS26_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(26)", + OutTemp => PPCMPLBWRDBUS_OUT(26), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(27), + GlitchData => PPCMPLBWRDBUS27_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(27)", + OutTemp => PPCMPLBWRDBUS_OUT(27), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(28), + GlitchData => PPCMPLBWRDBUS28_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(28)", + OutTemp => PPCMPLBWRDBUS_OUT(28), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(29), + GlitchData => PPCMPLBWRDBUS29_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(29)", + OutTemp => PPCMPLBWRDBUS_OUT(29), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(30), + GlitchData => PPCMPLBWRDBUS30_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(30)", + OutTemp => PPCMPLBWRDBUS_OUT(30), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(31), + GlitchData => PPCMPLBWRDBUS31_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(31)", + OutTemp => PPCMPLBWRDBUS_OUT(31), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(32), + GlitchData => PPCMPLBWRDBUS32_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(32)", + OutTemp => PPCMPLBWRDBUS_OUT(32), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(33), + GlitchData => PPCMPLBWRDBUS33_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(33)", + OutTemp => PPCMPLBWRDBUS_OUT(33), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(34), + GlitchData => PPCMPLBWRDBUS34_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(34)", + OutTemp => PPCMPLBWRDBUS_OUT(34), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(35), + GlitchData => PPCMPLBWRDBUS35_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(35)", + OutTemp => PPCMPLBWRDBUS_OUT(35), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(36), + GlitchData => PPCMPLBWRDBUS36_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(36)", + OutTemp => PPCMPLBWRDBUS_OUT(36), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(37), + GlitchData => PPCMPLBWRDBUS37_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(37)", + OutTemp => PPCMPLBWRDBUS_OUT(37), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(38), + GlitchData => PPCMPLBWRDBUS38_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(38)", + OutTemp => PPCMPLBWRDBUS_OUT(38), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(39), + GlitchData => PPCMPLBWRDBUS39_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(39)", + OutTemp => PPCMPLBWRDBUS_OUT(39), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(40), + GlitchData => PPCMPLBWRDBUS40_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(40)", + OutTemp => PPCMPLBWRDBUS_OUT(40), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(41), + GlitchData => PPCMPLBWRDBUS41_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(41)", + OutTemp => PPCMPLBWRDBUS_OUT(41), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(42), + GlitchData => PPCMPLBWRDBUS42_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(42)", + OutTemp => PPCMPLBWRDBUS_OUT(42), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(43), + GlitchData => PPCMPLBWRDBUS43_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(43)", + OutTemp => PPCMPLBWRDBUS_OUT(43), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(44), + GlitchData => PPCMPLBWRDBUS44_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(44)", + OutTemp => PPCMPLBWRDBUS_OUT(44), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(45), + GlitchData => PPCMPLBWRDBUS45_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(45)", + OutTemp => PPCMPLBWRDBUS_OUT(45), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(46), + GlitchData => PPCMPLBWRDBUS46_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(46)", + OutTemp => PPCMPLBWRDBUS_OUT(46), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(47), + GlitchData => PPCMPLBWRDBUS47_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(47)", + OutTemp => PPCMPLBWRDBUS_OUT(47), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(48), + GlitchData => PPCMPLBWRDBUS48_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(48)", + OutTemp => PPCMPLBWRDBUS_OUT(48), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(49), + GlitchData => PPCMPLBWRDBUS49_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(49)", + OutTemp => PPCMPLBWRDBUS_OUT(49), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(50), + GlitchData => PPCMPLBWRDBUS50_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(50)", + OutTemp => PPCMPLBWRDBUS_OUT(50), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(51), + GlitchData => PPCMPLBWRDBUS51_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(51)", + OutTemp => PPCMPLBWRDBUS_OUT(51), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(52), + GlitchData => PPCMPLBWRDBUS52_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(52)", + OutTemp => PPCMPLBWRDBUS_OUT(52), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(53), + GlitchData => PPCMPLBWRDBUS53_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(53)", + OutTemp => PPCMPLBWRDBUS_OUT(53), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(54), + GlitchData => PPCMPLBWRDBUS54_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(54)", + OutTemp => PPCMPLBWRDBUS_OUT(54), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(55), + GlitchData => PPCMPLBWRDBUS55_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(55)", + OutTemp => PPCMPLBWRDBUS_OUT(55), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(56), + GlitchData => PPCMPLBWRDBUS56_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(56)", + OutTemp => PPCMPLBWRDBUS_OUT(56), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(57), + GlitchData => PPCMPLBWRDBUS57_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(57)", + OutTemp => PPCMPLBWRDBUS_OUT(57), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(58), + GlitchData => PPCMPLBWRDBUS58_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(58)", + OutTemp => PPCMPLBWRDBUS_OUT(58), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(59), + GlitchData => PPCMPLBWRDBUS59_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(59)", + OutTemp => PPCMPLBWRDBUS_OUT(59), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(60), + GlitchData => PPCMPLBWRDBUS60_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(60)", + OutTemp => PPCMPLBWRDBUS_OUT(60), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(61), + GlitchData => PPCMPLBWRDBUS61_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(61)", + OutTemp => PPCMPLBWRDBUS_OUT(61), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(62), + GlitchData => PPCMPLBWRDBUS62_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(62)", + OutTemp => PPCMPLBWRDBUS_OUT(62), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(63), + GlitchData => PPCMPLBWRDBUS63_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(63)", + OutTemp => PPCMPLBWRDBUS_OUT(63), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(64), + GlitchData => PPCMPLBWRDBUS64_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(64)", + OutTemp => PPCMPLBWRDBUS_OUT(64), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(65), + GlitchData => PPCMPLBWRDBUS65_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(65)", + OutTemp => PPCMPLBWRDBUS_OUT(65), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(66), + GlitchData => PPCMPLBWRDBUS66_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(66)", + OutTemp => PPCMPLBWRDBUS_OUT(66), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(67), + GlitchData => PPCMPLBWRDBUS67_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(67)", + OutTemp => PPCMPLBWRDBUS_OUT(67), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(68), + GlitchData => PPCMPLBWRDBUS68_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(68)", + OutTemp => PPCMPLBWRDBUS_OUT(68), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(69), + GlitchData => PPCMPLBWRDBUS69_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(69)", + OutTemp => PPCMPLBWRDBUS_OUT(69), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(70), + GlitchData => PPCMPLBWRDBUS70_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(70)", + OutTemp => PPCMPLBWRDBUS_OUT(70), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(71), + GlitchData => PPCMPLBWRDBUS71_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(71)", + OutTemp => PPCMPLBWRDBUS_OUT(71), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(72), + GlitchData => PPCMPLBWRDBUS72_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(72)", + OutTemp => PPCMPLBWRDBUS_OUT(72), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(73), + GlitchData => PPCMPLBWRDBUS73_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(73)", + OutTemp => PPCMPLBWRDBUS_OUT(73), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(74), + GlitchData => PPCMPLBWRDBUS74_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(74)", + OutTemp => PPCMPLBWRDBUS_OUT(74), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(75), + GlitchData => PPCMPLBWRDBUS75_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(75)", + OutTemp => PPCMPLBWRDBUS_OUT(75), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(76), + GlitchData => PPCMPLBWRDBUS76_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(76)", + OutTemp => PPCMPLBWRDBUS_OUT(76), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(77), + GlitchData => PPCMPLBWRDBUS77_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(77)", + OutTemp => PPCMPLBWRDBUS_OUT(77), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(78), + GlitchData => PPCMPLBWRDBUS78_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(78)", + OutTemp => PPCMPLBWRDBUS_OUT(78), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(79), + GlitchData => PPCMPLBWRDBUS79_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(79)", + OutTemp => PPCMPLBWRDBUS_OUT(79), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(80), + GlitchData => PPCMPLBWRDBUS80_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(80)", + OutTemp => PPCMPLBWRDBUS_OUT(80), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(81), + GlitchData => PPCMPLBWRDBUS81_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(81)", + OutTemp => PPCMPLBWRDBUS_OUT(81), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(82), + GlitchData => PPCMPLBWRDBUS82_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(82)", + OutTemp => PPCMPLBWRDBUS_OUT(82), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(83), + GlitchData => PPCMPLBWRDBUS83_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(83)", + OutTemp => PPCMPLBWRDBUS_OUT(83), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(84), + GlitchData => PPCMPLBWRDBUS84_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(84)", + OutTemp => PPCMPLBWRDBUS_OUT(84), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(85), + GlitchData => PPCMPLBWRDBUS85_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(85)", + OutTemp => PPCMPLBWRDBUS_OUT(85), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(86), + GlitchData => PPCMPLBWRDBUS86_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(86)", + OutTemp => PPCMPLBWRDBUS_OUT(86), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(87), + GlitchData => PPCMPLBWRDBUS87_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(87)", + OutTemp => PPCMPLBWRDBUS_OUT(87), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(88), + GlitchData => PPCMPLBWRDBUS88_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(88)", + OutTemp => PPCMPLBWRDBUS_OUT(88), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(89), + GlitchData => PPCMPLBWRDBUS89_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(89)", + OutTemp => PPCMPLBWRDBUS_OUT(89), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(90), + GlitchData => PPCMPLBWRDBUS90_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(90)", + OutTemp => PPCMPLBWRDBUS_OUT(90), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(91), + GlitchData => PPCMPLBWRDBUS91_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(91)", + OutTemp => PPCMPLBWRDBUS_OUT(91), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(92), + GlitchData => PPCMPLBWRDBUS92_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(92)", + OutTemp => PPCMPLBWRDBUS_OUT(92), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(93), + GlitchData => PPCMPLBWRDBUS93_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(93)", + OutTemp => PPCMPLBWRDBUS_OUT(93), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(94), + GlitchData => PPCMPLBWRDBUS94_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(94)", + OutTemp => PPCMPLBWRDBUS_OUT(94), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(95), + GlitchData => PPCMPLBWRDBUS95_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(95)", + OutTemp => PPCMPLBWRDBUS_OUT(95), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(96), + GlitchData => PPCMPLBWRDBUS96_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(96)", + OutTemp => PPCMPLBWRDBUS_OUT(96), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(97), + GlitchData => PPCMPLBWRDBUS97_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(97)", + OutTemp => PPCMPLBWRDBUS_OUT(97), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(98), + GlitchData => PPCMPLBWRDBUS98_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(98)", + OutTemp => PPCMPLBWRDBUS_OUT(98), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(99), + GlitchData => PPCMPLBWRDBUS99_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(99)", + OutTemp => PPCMPLBWRDBUS_OUT(99), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(100), + GlitchData => PPCMPLBWRDBUS100_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(100)", + OutTemp => PPCMPLBWRDBUS_OUT(100), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(101), + GlitchData => PPCMPLBWRDBUS101_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(101)", + OutTemp => PPCMPLBWRDBUS_OUT(101), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(102), + GlitchData => PPCMPLBWRDBUS102_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(102)", + OutTemp => PPCMPLBWRDBUS_OUT(102), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(103), + GlitchData => PPCMPLBWRDBUS103_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(103)", + OutTemp => PPCMPLBWRDBUS_OUT(103), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(104), + GlitchData => PPCMPLBWRDBUS104_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(104)", + OutTemp => PPCMPLBWRDBUS_OUT(104), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(105), + GlitchData => PPCMPLBWRDBUS105_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(105)", + OutTemp => PPCMPLBWRDBUS_OUT(105), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(106), + GlitchData => PPCMPLBWRDBUS106_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(106)", + OutTemp => PPCMPLBWRDBUS_OUT(106), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(107), + GlitchData => PPCMPLBWRDBUS107_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(107)", + OutTemp => PPCMPLBWRDBUS_OUT(107), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(108), + GlitchData => PPCMPLBWRDBUS108_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(108)", + OutTemp => PPCMPLBWRDBUS_OUT(108), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(109), + GlitchData => PPCMPLBWRDBUS109_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(109)", + OutTemp => PPCMPLBWRDBUS_OUT(109), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(110), + GlitchData => PPCMPLBWRDBUS110_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(110)", + OutTemp => PPCMPLBWRDBUS_OUT(110), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(111), + GlitchData => PPCMPLBWRDBUS111_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(111)", + OutTemp => PPCMPLBWRDBUS_OUT(111), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(112), + GlitchData => PPCMPLBWRDBUS112_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(112)", + OutTemp => PPCMPLBWRDBUS_OUT(112), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(113), + GlitchData => PPCMPLBWRDBUS113_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(113)", + OutTemp => PPCMPLBWRDBUS_OUT(113), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(114), + GlitchData => PPCMPLBWRDBUS114_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(114)", + OutTemp => PPCMPLBWRDBUS_OUT(114), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(115), + GlitchData => PPCMPLBWRDBUS115_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(115)", + OutTemp => PPCMPLBWRDBUS_OUT(115), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(116), + GlitchData => PPCMPLBWRDBUS116_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(116)", + OutTemp => PPCMPLBWRDBUS_OUT(116), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(117), + GlitchData => PPCMPLBWRDBUS117_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(117)", + OutTemp => PPCMPLBWRDBUS_OUT(117), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(118), + GlitchData => PPCMPLBWRDBUS118_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(118)", + OutTemp => PPCMPLBWRDBUS_OUT(118), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(119), + GlitchData => PPCMPLBWRDBUS119_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(119)", + OutTemp => PPCMPLBWRDBUS_OUT(119), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(120), + GlitchData => PPCMPLBWRDBUS120_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(120)", + OutTemp => PPCMPLBWRDBUS_OUT(120), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(121), + GlitchData => PPCMPLBWRDBUS121_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(121)", + OutTemp => PPCMPLBWRDBUS_OUT(121), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(122), + GlitchData => PPCMPLBWRDBUS122_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(122)", + OutTemp => PPCMPLBWRDBUS_OUT(122), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(123), + GlitchData => PPCMPLBWRDBUS123_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(123)", + OutTemp => PPCMPLBWRDBUS_OUT(123), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(124), + GlitchData => PPCMPLBWRDBUS124_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(124)", + OutTemp => PPCMPLBWRDBUS_OUT(124), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(125), + GlitchData => PPCMPLBWRDBUS125_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(125)", + OutTemp => PPCMPLBWRDBUS_OUT(125), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(126), + GlitchData => PPCMPLBWRDBUS126_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(126)", + OutTemp => PPCMPLBWRDBUS_OUT(126), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(127), + GlitchData => PPCMPLBWRDBUS127_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(127)", + OutTemp => PPCMPLBWRDBUS_OUT(127), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBADDRACK, + GlitchData => PPCS0PLBADDRACK_GlitchData, + OutSignalName => "PPCS0PLBADDRACK", + OutTemp => PPCS0PLBADDRACK_OUT, + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMBUSY(0), + GlitchData => PPCS0PLBMBUSY0_GlitchData, + OutSignalName => "PPCS0PLBMBUSY(0)", + OutTemp => PPCS0PLBMBUSY_OUT(0), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMBUSY(1), + GlitchData => PPCS0PLBMBUSY1_GlitchData, + OutSignalName => "PPCS0PLBMBUSY(1)", + OutTemp => PPCS0PLBMBUSY_OUT(1), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMBUSY(2), + GlitchData => PPCS0PLBMBUSY2_GlitchData, + OutSignalName => "PPCS0PLBMBUSY(2)", + OutTemp => PPCS0PLBMBUSY_OUT(2), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMBUSY(3), + GlitchData => PPCS0PLBMBUSY3_GlitchData, + OutSignalName => "PPCS0PLBMBUSY(3)", + OutTemp => PPCS0PLBMBUSY_OUT(3), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMIRQ(0), + GlitchData => PPCS0PLBMIRQ0_GlitchData, + OutSignalName => "PPCS0PLBMIRQ(0)", + OutTemp => PPCS0PLBMIRQ_OUT(0), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMIRQ(1), + GlitchData => PPCS0PLBMIRQ1_GlitchData, + OutSignalName => "PPCS0PLBMIRQ(1)", + OutTemp => PPCS0PLBMIRQ_OUT(1), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMIRQ(2), + GlitchData => PPCS0PLBMIRQ2_GlitchData, + OutSignalName => "PPCS0PLBMIRQ(2)", + OutTemp => PPCS0PLBMIRQ_OUT(2), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMIRQ(3), + GlitchData => PPCS0PLBMIRQ3_GlitchData, + OutSignalName => "PPCS0PLBMIRQ(3)", + OutTemp => PPCS0PLBMIRQ_OUT(3), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMRDERR(0), + GlitchData => PPCS0PLBMRDERR0_GlitchData, + OutSignalName => "PPCS0PLBMRDERR(0)", + OutTemp => PPCS0PLBMRDERR_OUT(0), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMRDERR(1), + GlitchData => PPCS0PLBMRDERR1_GlitchData, + OutSignalName => "PPCS0PLBMRDERR(1)", + OutTemp => PPCS0PLBMRDERR_OUT(1), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMRDERR(2), + GlitchData => PPCS0PLBMRDERR2_GlitchData, + OutSignalName => "PPCS0PLBMRDERR(2)", + OutTemp => PPCS0PLBMRDERR_OUT(2), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMRDERR(3), + GlitchData => PPCS0PLBMRDERR3_GlitchData, + OutSignalName => "PPCS0PLBMRDERR(3)", + OutTemp => PPCS0PLBMRDERR_OUT(3), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMWRERR(0), + GlitchData => PPCS0PLBMWRERR0_GlitchData, + OutSignalName => "PPCS0PLBMWRERR(0)", + OutTemp => PPCS0PLBMWRERR_OUT(0), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMWRERR(1), + GlitchData => PPCS0PLBMWRERR1_GlitchData, + OutSignalName => "PPCS0PLBMWRERR(1)", + OutTemp => PPCS0PLBMWRERR_OUT(1), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMWRERR(2), + GlitchData => PPCS0PLBMWRERR2_GlitchData, + OutSignalName => "PPCS0PLBMWRERR(2)", + OutTemp => PPCS0PLBMWRERR_OUT(2), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMWRERR(3), + GlitchData => PPCS0PLBMWRERR3_GlitchData, + OutSignalName => "PPCS0PLBMWRERR(3)", + OutTemp => PPCS0PLBMWRERR_OUT(3), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDBTERM, + GlitchData => PPCS0PLBRDBTERM_GlitchData, + OutSignalName => "PPCS0PLBRDBTERM", + OutTemp => PPCS0PLBRDBTERM_OUT, + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDCOMP, + GlitchData => PPCS0PLBRDCOMP_GlitchData, + OutSignalName => "PPCS0PLBRDCOMP", + OutTemp => PPCS0PLBRDCOMP_OUT, + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDACK, + GlitchData => PPCS0PLBRDDACK_GlitchData, + OutSignalName => "PPCS0PLBRDDACK", + OutTemp => PPCS0PLBRDDACK_OUT, + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(0), + GlitchData => PPCS0PLBRDDBUS0_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(0)", + OutTemp => PPCS0PLBRDDBUS_OUT(0), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(1), + GlitchData => PPCS0PLBRDDBUS1_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(1)", + OutTemp => PPCS0PLBRDDBUS_OUT(1), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(2), + GlitchData => PPCS0PLBRDDBUS2_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(2)", + OutTemp => PPCS0PLBRDDBUS_OUT(2), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(3), + GlitchData => PPCS0PLBRDDBUS3_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(3)", + OutTemp => PPCS0PLBRDDBUS_OUT(3), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(4), + GlitchData => PPCS0PLBRDDBUS4_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(4)", + OutTemp => PPCS0PLBRDDBUS_OUT(4), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(5), + GlitchData => PPCS0PLBRDDBUS5_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(5)", + OutTemp => PPCS0PLBRDDBUS_OUT(5), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(6), + GlitchData => PPCS0PLBRDDBUS6_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(6)", + OutTemp => PPCS0PLBRDDBUS_OUT(6), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(7), + GlitchData => PPCS0PLBRDDBUS7_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(7)", + OutTemp => PPCS0PLBRDDBUS_OUT(7), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(8), + GlitchData => PPCS0PLBRDDBUS8_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(8)", + OutTemp => PPCS0PLBRDDBUS_OUT(8), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(9), + GlitchData => PPCS0PLBRDDBUS9_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(9)", + OutTemp => PPCS0PLBRDDBUS_OUT(9), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(10), + GlitchData => PPCS0PLBRDDBUS10_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(10)", + OutTemp => PPCS0PLBRDDBUS_OUT(10), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(11), + GlitchData => PPCS0PLBRDDBUS11_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(11)", + OutTemp => PPCS0PLBRDDBUS_OUT(11), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(12), + GlitchData => PPCS0PLBRDDBUS12_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(12)", + OutTemp => PPCS0PLBRDDBUS_OUT(12), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(13), + GlitchData => PPCS0PLBRDDBUS13_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(13)", + OutTemp => PPCS0PLBRDDBUS_OUT(13), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(14), + GlitchData => PPCS0PLBRDDBUS14_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(14)", + OutTemp => PPCS0PLBRDDBUS_OUT(14), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(15), + GlitchData => PPCS0PLBRDDBUS15_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(15)", + OutTemp => PPCS0PLBRDDBUS_OUT(15), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(16), + GlitchData => PPCS0PLBRDDBUS16_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(16)", + OutTemp => PPCS0PLBRDDBUS_OUT(16), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(17), + GlitchData => PPCS0PLBRDDBUS17_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(17)", + OutTemp => PPCS0PLBRDDBUS_OUT(17), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(18), + GlitchData => PPCS0PLBRDDBUS18_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(18)", + OutTemp => PPCS0PLBRDDBUS_OUT(18), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(19), + GlitchData => PPCS0PLBRDDBUS19_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(19)", + OutTemp => PPCS0PLBRDDBUS_OUT(19), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(20), + GlitchData => PPCS0PLBRDDBUS20_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(20)", + OutTemp => PPCS0PLBRDDBUS_OUT(20), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(21), + GlitchData => PPCS0PLBRDDBUS21_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(21)", + OutTemp => PPCS0PLBRDDBUS_OUT(21), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(22), + GlitchData => PPCS0PLBRDDBUS22_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(22)", + OutTemp => PPCS0PLBRDDBUS_OUT(22), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(23), + GlitchData => PPCS0PLBRDDBUS23_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(23)", + OutTemp => PPCS0PLBRDDBUS_OUT(23), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(24), + GlitchData => PPCS0PLBRDDBUS24_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(24)", + OutTemp => PPCS0PLBRDDBUS_OUT(24), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(25), + GlitchData => PPCS0PLBRDDBUS25_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(25)", + OutTemp => PPCS0PLBRDDBUS_OUT(25), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(26), + GlitchData => PPCS0PLBRDDBUS26_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(26)", + OutTemp => PPCS0PLBRDDBUS_OUT(26), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(27), + GlitchData => PPCS0PLBRDDBUS27_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(27)", + OutTemp => PPCS0PLBRDDBUS_OUT(27), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(28), + GlitchData => PPCS0PLBRDDBUS28_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(28)", + OutTemp => PPCS0PLBRDDBUS_OUT(28), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(29), + GlitchData => PPCS0PLBRDDBUS29_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(29)", + OutTemp => PPCS0PLBRDDBUS_OUT(29), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(30), + GlitchData => PPCS0PLBRDDBUS30_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(30)", + OutTemp => PPCS0PLBRDDBUS_OUT(30), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(31), + GlitchData => PPCS0PLBRDDBUS31_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(31)", + OutTemp => PPCS0PLBRDDBUS_OUT(31), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(32), + GlitchData => PPCS0PLBRDDBUS32_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(32)", + OutTemp => PPCS0PLBRDDBUS_OUT(32), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(33), + GlitchData => PPCS0PLBRDDBUS33_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(33)", + OutTemp => PPCS0PLBRDDBUS_OUT(33), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(34), + GlitchData => PPCS0PLBRDDBUS34_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(34)", + OutTemp => PPCS0PLBRDDBUS_OUT(34), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(35), + GlitchData => PPCS0PLBRDDBUS35_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(35)", + OutTemp => PPCS0PLBRDDBUS_OUT(35), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(36), + GlitchData => PPCS0PLBRDDBUS36_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(36)", + OutTemp => PPCS0PLBRDDBUS_OUT(36), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(37), + GlitchData => PPCS0PLBRDDBUS37_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(37)", + OutTemp => PPCS0PLBRDDBUS_OUT(37), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(38), + GlitchData => PPCS0PLBRDDBUS38_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(38)", + OutTemp => PPCS0PLBRDDBUS_OUT(38), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(39), + GlitchData => PPCS0PLBRDDBUS39_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(39)", + OutTemp => PPCS0PLBRDDBUS_OUT(39), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(40), + GlitchData => PPCS0PLBRDDBUS40_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(40)", + OutTemp => PPCS0PLBRDDBUS_OUT(40), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(41), + GlitchData => PPCS0PLBRDDBUS41_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(41)", + OutTemp => PPCS0PLBRDDBUS_OUT(41), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(42), + GlitchData => PPCS0PLBRDDBUS42_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(42)", + OutTemp => PPCS0PLBRDDBUS_OUT(42), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(43), + GlitchData => PPCS0PLBRDDBUS43_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(43)", + OutTemp => PPCS0PLBRDDBUS_OUT(43), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(44), + GlitchData => PPCS0PLBRDDBUS44_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(44)", + OutTemp => PPCS0PLBRDDBUS_OUT(44), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(45), + GlitchData => PPCS0PLBRDDBUS45_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(45)", + OutTemp => PPCS0PLBRDDBUS_OUT(45), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(46), + GlitchData => PPCS0PLBRDDBUS46_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(46)", + OutTemp => PPCS0PLBRDDBUS_OUT(46), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(47), + GlitchData => PPCS0PLBRDDBUS47_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(47)", + OutTemp => PPCS0PLBRDDBUS_OUT(47), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(48), + GlitchData => PPCS0PLBRDDBUS48_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(48)", + OutTemp => PPCS0PLBRDDBUS_OUT(48), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(49), + GlitchData => PPCS0PLBRDDBUS49_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(49)", + OutTemp => PPCS0PLBRDDBUS_OUT(49), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(50), + GlitchData => PPCS0PLBRDDBUS50_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(50)", + OutTemp => PPCS0PLBRDDBUS_OUT(50), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(51), + GlitchData => PPCS0PLBRDDBUS51_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(51)", + OutTemp => PPCS0PLBRDDBUS_OUT(51), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(52), + GlitchData => PPCS0PLBRDDBUS52_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(52)", + OutTemp => PPCS0PLBRDDBUS_OUT(52), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(53), + GlitchData => PPCS0PLBRDDBUS53_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(53)", + OutTemp => PPCS0PLBRDDBUS_OUT(53), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(54), + GlitchData => PPCS0PLBRDDBUS54_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(54)", + OutTemp => PPCS0PLBRDDBUS_OUT(54), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(55), + GlitchData => PPCS0PLBRDDBUS55_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(55)", + OutTemp => PPCS0PLBRDDBUS_OUT(55), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(56), + GlitchData => PPCS0PLBRDDBUS56_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(56)", + OutTemp => PPCS0PLBRDDBUS_OUT(56), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(57), + GlitchData => PPCS0PLBRDDBUS57_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(57)", + OutTemp => PPCS0PLBRDDBUS_OUT(57), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(58), + GlitchData => PPCS0PLBRDDBUS58_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(58)", + OutTemp => PPCS0PLBRDDBUS_OUT(58), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(59), + GlitchData => PPCS0PLBRDDBUS59_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(59)", + OutTemp => PPCS0PLBRDDBUS_OUT(59), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(60), + GlitchData => PPCS0PLBRDDBUS60_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(60)", + OutTemp => PPCS0PLBRDDBUS_OUT(60), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(61), + GlitchData => PPCS0PLBRDDBUS61_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(61)", + OutTemp => PPCS0PLBRDDBUS_OUT(61), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(62), + GlitchData => PPCS0PLBRDDBUS62_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(62)", + OutTemp => PPCS0PLBRDDBUS_OUT(62), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(63), + GlitchData => PPCS0PLBRDDBUS63_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(63)", + OutTemp => PPCS0PLBRDDBUS_OUT(63), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(64), + GlitchData => PPCS0PLBRDDBUS64_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(64)", + OutTemp => PPCS0PLBRDDBUS_OUT(64), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(65), + GlitchData => PPCS0PLBRDDBUS65_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(65)", + OutTemp => PPCS0PLBRDDBUS_OUT(65), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(66), + GlitchData => PPCS0PLBRDDBUS66_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(66)", + OutTemp => PPCS0PLBRDDBUS_OUT(66), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(67), + GlitchData => PPCS0PLBRDDBUS67_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(67)", + OutTemp => PPCS0PLBRDDBUS_OUT(67), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(68), + GlitchData => PPCS0PLBRDDBUS68_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(68)", + OutTemp => PPCS0PLBRDDBUS_OUT(68), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(69), + GlitchData => PPCS0PLBRDDBUS69_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(69)", + OutTemp => PPCS0PLBRDDBUS_OUT(69), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(70), + GlitchData => PPCS0PLBRDDBUS70_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(70)", + OutTemp => PPCS0PLBRDDBUS_OUT(70), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(71), + GlitchData => PPCS0PLBRDDBUS71_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(71)", + OutTemp => PPCS0PLBRDDBUS_OUT(71), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(72), + GlitchData => PPCS0PLBRDDBUS72_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(72)", + OutTemp => PPCS0PLBRDDBUS_OUT(72), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(73), + GlitchData => PPCS0PLBRDDBUS73_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(73)", + OutTemp => PPCS0PLBRDDBUS_OUT(73), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(74), + GlitchData => PPCS0PLBRDDBUS74_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(74)", + OutTemp => PPCS0PLBRDDBUS_OUT(74), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(75), + GlitchData => PPCS0PLBRDDBUS75_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(75)", + OutTemp => PPCS0PLBRDDBUS_OUT(75), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(76), + GlitchData => PPCS0PLBRDDBUS76_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(76)", + OutTemp => PPCS0PLBRDDBUS_OUT(76), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(77), + GlitchData => PPCS0PLBRDDBUS77_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(77)", + OutTemp => PPCS0PLBRDDBUS_OUT(77), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(78), + GlitchData => PPCS0PLBRDDBUS78_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(78)", + OutTemp => PPCS0PLBRDDBUS_OUT(78), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(79), + GlitchData => PPCS0PLBRDDBUS79_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(79)", + OutTemp => PPCS0PLBRDDBUS_OUT(79), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(80), + GlitchData => PPCS0PLBRDDBUS80_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(80)", + OutTemp => PPCS0PLBRDDBUS_OUT(80), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(81), + GlitchData => PPCS0PLBRDDBUS81_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(81)", + OutTemp => PPCS0PLBRDDBUS_OUT(81), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(82), + GlitchData => PPCS0PLBRDDBUS82_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(82)", + OutTemp => PPCS0PLBRDDBUS_OUT(82), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(83), + GlitchData => PPCS0PLBRDDBUS83_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(83)", + OutTemp => PPCS0PLBRDDBUS_OUT(83), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(84), + GlitchData => PPCS0PLBRDDBUS84_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(84)", + OutTemp => PPCS0PLBRDDBUS_OUT(84), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(85), + GlitchData => PPCS0PLBRDDBUS85_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(85)", + OutTemp => PPCS0PLBRDDBUS_OUT(85), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(86), + GlitchData => PPCS0PLBRDDBUS86_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(86)", + OutTemp => PPCS0PLBRDDBUS_OUT(86), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(87), + GlitchData => PPCS0PLBRDDBUS87_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(87)", + OutTemp => PPCS0PLBRDDBUS_OUT(87), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(88), + GlitchData => PPCS0PLBRDDBUS88_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(88)", + OutTemp => PPCS0PLBRDDBUS_OUT(88), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(89), + GlitchData => PPCS0PLBRDDBUS89_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(89)", + OutTemp => PPCS0PLBRDDBUS_OUT(89), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(90), + GlitchData => PPCS0PLBRDDBUS90_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(90)", + OutTemp => PPCS0PLBRDDBUS_OUT(90), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(91), + GlitchData => PPCS0PLBRDDBUS91_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(91)", + OutTemp => PPCS0PLBRDDBUS_OUT(91), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(92), + GlitchData => PPCS0PLBRDDBUS92_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(92)", + OutTemp => PPCS0PLBRDDBUS_OUT(92), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(93), + GlitchData => PPCS0PLBRDDBUS93_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(93)", + OutTemp => PPCS0PLBRDDBUS_OUT(93), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(94), + GlitchData => PPCS0PLBRDDBUS94_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(94)", + OutTemp => PPCS0PLBRDDBUS_OUT(94), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(95), + GlitchData => PPCS0PLBRDDBUS95_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(95)", + OutTemp => PPCS0PLBRDDBUS_OUT(95), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(96), + GlitchData => PPCS0PLBRDDBUS96_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(96)", + OutTemp => PPCS0PLBRDDBUS_OUT(96), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(97), + GlitchData => PPCS0PLBRDDBUS97_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(97)", + OutTemp => PPCS0PLBRDDBUS_OUT(97), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(98), + GlitchData => PPCS0PLBRDDBUS98_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(98)", + OutTemp => PPCS0PLBRDDBUS_OUT(98), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(99), + GlitchData => PPCS0PLBRDDBUS99_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(99)", + OutTemp => PPCS0PLBRDDBUS_OUT(99), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(100), + GlitchData => PPCS0PLBRDDBUS100_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(100)", + OutTemp => PPCS0PLBRDDBUS_OUT(100), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(101), + GlitchData => PPCS0PLBRDDBUS101_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(101)", + OutTemp => PPCS0PLBRDDBUS_OUT(101), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(102), + GlitchData => PPCS0PLBRDDBUS102_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(102)", + OutTemp => PPCS0PLBRDDBUS_OUT(102), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(103), + GlitchData => PPCS0PLBRDDBUS103_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(103)", + OutTemp => PPCS0PLBRDDBUS_OUT(103), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(104), + GlitchData => PPCS0PLBRDDBUS104_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(104)", + OutTemp => PPCS0PLBRDDBUS_OUT(104), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(105), + GlitchData => PPCS0PLBRDDBUS105_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(105)", + OutTemp => PPCS0PLBRDDBUS_OUT(105), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(106), + GlitchData => PPCS0PLBRDDBUS106_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(106)", + OutTemp => PPCS0PLBRDDBUS_OUT(106), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(107), + GlitchData => PPCS0PLBRDDBUS107_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(107)", + OutTemp => PPCS0PLBRDDBUS_OUT(107), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(108), + GlitchData => PPCS0PLBRDDBUS108_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(108)", + OutTemp => PPCS0PLBRDDBUS_OUT(108), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(109), + GlitchData => PPCS0PLBRDDBUS109_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(109)", + OutTemp => PPCS0PLBRDDBUS_OUT(109), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(110), + GlitchData => PPCS0PLBRDDBUS110_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(110)", + OutTemp => PPCS0PLBRDDBUS_OUT(110), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(111), + GlitchData => PPCS0PLBRDDBUS111_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(111)", + OutTemp => PPCS0PLBRDDBUS_OUT(111), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(112), + GlitchData => PPCS0PLBRDDBUS112_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(112)", + OutTemp => PPCS0PLBRDDBUS_OUT(112), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(113), + GlitchData => PPCS0PLBRDDBUS113_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(113)", + OutTemp => PPCS0PLBRDDBUS_OUT(113), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(114), + GlitchData => PPCS0PLBRDDBUS114_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(114)", + OutTemp => PPCS0PLBRDDBUS_OUT(114), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(115), + GlitchData => PPCS0PLBRDDBUS115_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(115)", + OutTemp => PPCS0PLBRDDBUS_OUT(115), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(116), + GlitchData => PPCS0PLBRDDBUS116_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(116)", + OutTemp => PPCS0PLBRDDBUS_OUT(116), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(117), + GlitchData => PPCS0PLBRDDBUS117_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(117)", + OutTemp => PPCS0PLBRDDBUS_OUT(117), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(118), + GlitchData => PPCS0PLBRDDBUS118_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(118)", + OutTemp => PPCS0PLBRDDBUS_OUT(118), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(119), + GlitchData => PPCS0PLBRDDBUS119_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(119)", + OutTemp => PPCS0PLBRDDBUS_OUT(119), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(120), + GlitchData => PPCS0PLBRDDBUS120_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(120)", + OutTemp => PPCS0PLBRDDBUS_OUT(120), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(121), + GlitchData => PPCS0PLBRDDBUS121_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(121)", + OutTemp => PPCS0PLBRDDBUS_OUT(121), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(122), + GlitchData => PPCS0PLBRDDBUS122_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(122)", + OutTemp => PPCS0PLBRDDBUS_OUT(122), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(123), + GlitchData => PPCS0PLBRDDBUS123_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(123)", + OutTemp => PPCS0PLBRDDBUS_OUT(123), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(124), + GlitchData => PPCS0PLBRDDBUS124_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(124)", + OutTemp => PPCS0PLBRDDBUS_OUT(124), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(125), + GlitchData => PPCS0PLBRDDBUS125_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(125)", + OutTemp => PPCS0PLBRDDBUS_OUT(125), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(126), + GlitchData => PPCS0PLBRDDBUS126_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(126)", + OutTemp => PPCS0PLBRDDBUS_OUT(126), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(127), + GlitchData => PPCS0PLBRDDBUS127_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(127)", + OutTemp => PPCS0PLBRDDBUS_OUT(127), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDWDADDR(0), + GlitchData => PPCS0PLBRDWDADDR0_GlitchData, + OutSignalName => "PPCS0PLBRDWDADDR(0)", + OutTemp => PPCS0PLBRDWDADDR_OUT(0), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDWDADDR(1), + GlitchData => PPCS0PLBRDWDADDR1_GlitchData, + OutSignalName => "PPCS0PLBRDWDADDR(1)", + OutTemp => PPCS0PLBRDWDADDR_OUT(1), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDWDADDR(2), + GlitchData => PPCS0PLBRDWDADDR2_GlitchData, + OutSignalName => "PPCS0PLBRDWDADDR(2)", + OutTemp => PPCS0PLBRDWDADDR_OUT(2), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDWDADDR(3), + GlitchData => PPCS0PLBRDWDADDR3_GlitchData, + OutSignalName => "PPCS0PLBRDWDADDR(3)", + OutTemp => PPCS0PLBRDWDADDR_OUT(3), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBREARBITRATE, + GlitchData => PPCS0PLBREARBITRATE_GlitchData, + OutSignalName => "PPCS0PLBREARBITRATE", + OutTemp => PPCS0PLBREARBITRATE_OUT, + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBSSIZE(0), + GlitchData => PPCS0PLBSSIZE0_GlitchData, + OutSignalName => "PPCS0PLBSSIZE(0)", + OutTemp => PPCS0PLBSSIZE_OUT(0), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBSSIZE(1), + GlitchData => PPCS0PLBSSIZE1_GlitchData, + OutSignalName => "PPCS0PLBSSIZE(1)", + OutTemp => PPCS0PLBSSIZE_OUT(1), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBWAIT, + GlitchData => PPCS0PLBWAIT_GlitchData, + OutSignalName => "PPCS0PLBWAIT", + OutTemp => PPCS0PLBWAIT_OUT, + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBWRBTERM, + GlitchData => PPCS0PLBWRBTERM_GlitchData, + OutSignalName => "PPCS0PLBWRBTERM", + OutTemp => PPCS0PLBWRBTERM_OUT, + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBWRCOMP, + GlitchData => PPCS0PLBWRCOMP_GlitchData, + OutSignalName => "PPCS0PLBWRCOMP", + OutTemp => PPCS0PLBWRCOMP_OUT, + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBWRDACK, + GlitchData => PPCS0PLBWRDACK_GlitchData, + OutSignalName => "PPCS0PLBWRDACK", + OutTemp => PPCS0PLBWRDACK_OUT, + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBADDRACK, + GlitchData => PPCS1PLBADDRACK_GlitchData, + OutSignalName => "PPCS1PLBADDRACK", + OutTemp => PPCS1PLBADDRACK_OUT, + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMBUSY(0), + GlitchData => PPCS1PLBMBUSY0_GlitchData, + OutSignalName => "PPCS1PLBMBUSY(0)", + OutTemp => PPCS1PLBMBUSY_OUT(0), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMBUSY(1), + GlitchData => PPCS1PLBMBUSY1_GlitchData, + OutSignalName => "PPCS1PLBMBUSY(1)", + OutTemp => PPCS1PLBMBUSY_OUT(1), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMBUSY(2), + GlitchData => PPCS1PLBMBUSY2_GlitchData, + OutSignalName => "PPCS1PLBMBUSY(2)", + OutTemp => PPCS1PLBMBUSY_OUT(2), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMBUSY(3), + GlitchData => PPCS1PLBMBUSY3_GlitchData, + OutSignalName => "PPCS1PLBMBUSY(3)", + OutTemp => PPCS1PLBMBUSY_OUT(3), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMIRQ(0), + GlitchData => PPCS1PLBMIRQ0_GlitchData, + OutSignalName => "PPCS1PLBMIRQ(0)", + OutTemp => PPCS1PLBMIRQ_OUT(0), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMIRQ(1), + GlitchData => PPCS1PLBMIRQ1_GlitchData, + OutSignalName => "PPCS1PLBMIRQ(1)", + OutTemp => PPCS1PLBMIRQ_OUT(1), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMIRQ(2), + GlitchData => PPCS1PLBMIRQ2_GlitchData, + OutSignalName => "PPCS1PLBMIRQ(2)", + OutTemp => PPCS1PLBMIRQ_OUT(2), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMIRQ(3), + GlitchData => PPCS1PLBMIRQ3_GlitchData, + OutSignalName => "PPCS1PLBMIRQ(3)", + OutTemp => PPCS1PLBMIRQ_OUT(3), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMRDERR(0), + GlitchData => PPCS1PLBMRDERR0_GlitchData, + OutSignalName => "PPCS1PLBMRDERR(0)", + OutTemp => PPCS1PLBMRDERR_OUT(0), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMRDERR(1), + GlitchData => PPCS1PLBMRDERR1_GlitchData, + OutSignalName => "PPCS1PLBMRDERR(1)", + OutTemp => PPCS1PLBMRDERR_OUT(1), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMRDERR(2), + GlitchData => PPCS1PLBMRDERR2_GlitchData, + OutSignalName => "PPCS1PLBMRDERR(2)", + OutTemp => PPCS1PLBMRDERR_OUT(2), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMRDERR(3), + GlitchData => PPCS1PLBMRDERR3_GlitchData, + OutSignalName => "PPCS1PLBMRDERR(3)", + OutTemp => PPCS1PLBMRDERR_OUT(3), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMWRERR(0), + GlitchData => PPCS1PLBMWRERR0_GlitchData, + OutSignalName => "PPCS1PLBMWRERR(0)", + OutTemp => PPCS1PLBMWRERR_OUT(0), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMWRERR(1), + GlitchData => PPCS1PLBMWRERR1_GlitchData, + OutSignalName => "PPCS1PLBMWRERR(1)", + OutTemp => PPCS1PLBMWRERR_OUT(1), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMWRERR(2), + GlitchData => PPCS1PLBMWRERR2_GlitchData, + OutSignalName => "PPCS1PLBMWRERR(2)", + OutTemp => PPCS1PLBMWRERR_OUT(2), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMWRERR(3), + GlitchData => PPCS1PLBMWRERR3_GlitchData, + OutSignalName => "PPCS1PLBMWRERR(3)", + OutTemp => PPCS1PLBMWRERR_OUT(3), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDBTERM, + GlitchData => PPCS1PLBRDBTERM_GlitchData, + OutSignalName => "PPCS1PLBRDBTERM", + OutTemp => PPCS1PLBRDBTERM_OUT, + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDCOMP, + GlitchData => PPCS1PLBRDCOMP_GlitchData, + OutSignalName => "PPCS1PLBRDCOMP", + OutTemp => PPCS1PLBRDCOMP_OUT, + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDACK, + GlitchData => PPCS1PLBRDDACK_GlitchData, + OutSignalName => "PPCS1PLBRDDACK", + OutTemp => PPCS1PLBRDDACK_OUT, + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(0), + GlitchData => PPCS1PLBRDDBUS0_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(0)", + OutTemp => PPCS1PLBRDDBUS_OUT(0), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(1), + GlitchData => PPCS1PLBRDDBUS1_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(1)", + OutTemp => PPCS1PLBRDDBUS_OUT(1), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(2), + GlitchData => PPCS1PLBRDDBUS2_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(2)", + OutTemp => PPCS1PLBRDDBUS_OUT(2), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(3), + GlitchData => PPCS1PLBRDDBUS3_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(3)", + OutTemp => PPCS1PLBRDDBUS_OUT(3), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(4), + GlitchData => PPCS1PLBRDDBUS4_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(4)", + OutTemp => PPCS1PLBRDDBUS_OUT(4), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(5), + GlitchData => PPCS1PLBRDDBUS5_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(5)", + OutTemp => PPCS1PLBRDDBUS_OUT(5), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(6), + GlitchData => PPCS1PLBRDDBUS6_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(6)", + OutTemp => PPCS1PLBRDDBUS_OUT(6), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(7), + GlitchData => PPCS1PLBRDDBUS7_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(7)", + OutTemp => PPCS1PLBRDDBUS_OUT(7), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(8), + GlitchData => PPCS1PLBRDDBUS8_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(8)", + OutTemp => PPCS1PLBRDDBUS_OUT(8), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(9), + GlitchData => PPCS1PLBRDDBUS9_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(9)", + OutTemp => PPCS1PLBRDDBUS_OUT(9), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(10), + GlitchData => PPCS1PLBRDDBUS10_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(10)", + OutTemp => PPCS1PLBRDDBUS_OUT(10), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(11), + GlitchData => PPCS1PLBRDDBUS11_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(11)", + OutTemp => PPCS1PLBRDDBUS_OUT(11), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(12), + GlitchData => PPCS1PLBRDDBUS12_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(12)", + OutTemp => PPCS1PLBRDDBUS_OUT(12), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(13), + GlitchData => PPCS1PLBRDDBUS13_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(13)", + OutTemp => PPCS1PLBRDDBUS_OUT(13), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(14), + GlitchData => PPCS1PLBRDDBUS14_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(14)", + OutTemp => PPCS1PLBRDDBUS_OUT(14), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(15), + GlitchData => PPCS1PLBRDDBUS15_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(15)", + OutTemp => PPCS1PLBRDDBUS_OUT(15), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(16), + GlitchData => PPCS1PLBRDDBUS16_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(16)", + OutTemp => PPCS1PLBRDDBUS_OUT(16), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(17), + GlitchData => PPCS1PLBRDDBUS17_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(17)", + OutTemp => PPCS1PLBRDDBUS_OUT(17), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(18), + GlitchData => PPCS1PLBRDDBUS18_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(18)", + OutTemp => PPCS1PLBRDDBUS_OUT(18), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(19), + GlitchData => PPCS1PLBRDDBUS19_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(19)", + OutTemp => PPCS1PLBRDDBUS_OUT(19), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(20), + GlitchData => PPCS1PLBRDDBUS20_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(20)", + OutTemp => PPCS1PLBRDDBUS_OUT(20), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(21), + GlitchData => PPCS1PLBRDDBUS21_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(21)", + OutTemp => PPCS1PLBRDDBUS_OUT(21), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(22), + GlitchData => PPCS1PLBRDDBUS22_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(22)", + OutTemp => PPCS1PLBRDDBUS_OUT(22), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(23), + GlitchData => PPCS1PLBRDDBUS23_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(23)", + OutTemp => PPCS1PLBRDDBUS_OUT(23), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(24), + GlitchData => PPCS1PLBRDDBUS24_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(24)", + OutTemp => PPCS1PLBRDDBUS_OUT(24), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(25), + GlitchData => PPCS1PLBRDDBUS25_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(25)", + OutTemp => PPCS1PLBRDDBUS_OUT(25), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(26), + GlitchData => PPCS1PLBRDDBUS26_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(26)", + OutTemp => PPCS1PLBRDDBUS_OUT(26), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(27), + GlitchData => PPCS1PLBRDDBUS27_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(27)", + OutTemp => PPCS1PLBRDDBUS_OUT(27), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(28), + GlitchData => PPCS1PLBRDDBUS28_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(28)", + OutTemp => PPCS1PLBRDDBUS_OUT(28), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(29), + GlitchData => PPCS1PLBRDDBUS29_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(29)", + OutTemp => PPCS1PLBRDDBUS_OUT(29), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(30), + GlitchData => PPCS1PLBRDDBUS30_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(30)", + OutTemp => PPCS1PLBRDDBUS_OUT(30), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(31), + GlitchData => PPCS1PLBRDDBUS31_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(31)", + OutTemp => PPCS1PLBRDDBUS_OUT(31), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(32), + GlitchData => PPCS1PLBRDDBUS32_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(32)", + OutTemp => PPCS1PLBRDDBUS_OUT(32), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(33), + GlitchData => PPCS1PLBRDDBUS33_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(33)", + OutTemp => PPCS1PLBRDDBUS_OUT(33), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(34), + GlitchData => PPCS1PLBRDDBUS34_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(34)", + OutTemp => PPCS1PLBRDDBUS_OUT(34), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(35), + GlitchData => PPCS1PLBRDDBUS35_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(35)", + OutTemp => PPCS1PLBRDDBUS_OUT(35), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(36), + GlitchData => PPCS1PLBRDDBUS36_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(36)", + OutTemp => PPCS1PLBRDDBUS_OUT(36), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(37), + GlitchData => PPCS1PLBRDDBUS37_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(37)", + OutTemp => PPCS1PLBRDDBUS_OUT(37), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(38), + GlitchData => PPCS1PLBRDDBUS38_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(38)", + OutTemp => PPCS1PLBRDDBUS_OUT(38), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(39), + GlitchData => PPCS1PLBRDDBUS39_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(39)", + OutTemp => PPCS1PLBRDDBUS_OUT(39), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(40), + GlitchData => PPCS1PLBRDDBUS40_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(40)", + OutTemp => PPCS1PLBRDDBUS_OUT(40), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(41), + GlitchData => PPCS1PLBRDDBUS41_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(41)", + OutTemp => PPCS1PLBRDDBUS_OUT(41), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(42), + GlitchData => PPCS1PLBRDDBUS42_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(42)", + OutTemp => PPCS1PLBRDDBUS_OUT(42), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(43), + GlitchData => PPCS1PLBRDDBUS43_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(43)", + OutTemp => PPCS1PLBRDDBUS_OUT(43), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(44), + GlitchData => PPCS1PLBRDDBUS44_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(44)", + OutTemp => PPCS1PLBRDDBUS_OUT(44), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(45), + GlitchData => PPCS1PLBRDDBUS45_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(45)", + OutTemp => PPCS1PLBRDDBUS_OUT(45), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(46), + GlitchData => PPCS1PLBRDDBUS46_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(46)", + OutTemp => PPCS1PLBRDDBUS_OUT(46), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(47), + GlitchData => PPCS1PLBRDDBUS47_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(47)", + OutTemp => PPCS1PLBRDDBUS_OUT(47), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(48), + GlitchData => PPCS1PLBRDDBUS48_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(48)", + OutTemp => PPCS1PLBRDDBUS_OUT(48), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(49), + GlitchData => PPCS1PLBRDDBUS49_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(49)", + OutTemp => PPCS1PLBRDDBUS_OUT(49), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(50), + GlitchData => PPCS1PLBRDDBUS50_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(50)", + OutTemp => PPCS1PLBRDDBUS_OUT(50), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(51), + GlitchData => PPCS1PLBRDDBUS51_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(51)", + OutTemp => PPCS1PLBRDDBUS_OUT(51), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(52), + GlitchData => PPCS1PLBRDDBUS52_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(52)", + OutTemp => PPCS1PLBRDDBUS_OUT(52), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(53), + GlitchData => PPCS1PLBRDDBUS53_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(53)", + OutTemp => PPCS1PLBRDDBUS_OUT(53), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(54), + GlitchData => PPCS1PLBRDDBUS54_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(54)", + OutTemp => PPCS1PLBRDDBUS_OUT(54), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(55), + GlitchData => PPCS1PLBRDDBUS55_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(55)", + OutTemp => PPCS1PLBRDDBUS_OUT(55), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(56), + GlitchData => PPCS1PLBRDDBUS56_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(56)", + OutTemp => PPCS1PLBRDDBUS_OUT(56), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(57), + GlitchData => PPCS1PLBRDDBUS57_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(57)", + OutTemp => PPCS1PLBRDDBUS_OUT(57), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(58), + GlitchData => PPCS1PLBRDDBUS58_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(58)", + OutTemp => PPCS1PLBRDDBUS_OUT(58), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(59), + GlitchData => PPCS1PLBRDDBUS59_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(59)", + OutTemp => PPCS1PLBRDDBUS_OUT(59), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(60), + GlitchData => PPCS1PLBRDDBUS60_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(60)", + OutTemp => PPCS1PLBRDDBUS_OUT(60), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(61), + GlitchData => PPCS1PLBRDDBUS61_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(61)", + OutTemp => PPCS1PLBRDDBUS_OUT(61), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(62), + GlitchData => PPCS1PLBRDDBUS62_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(62)", + OutTemp => PPCS1PLBRDDBUS_OUT(62), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(63), + GlitchData => PPCS1PLBRDDBUS63_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(63)", + OutTemp => PPCS1PLBRDDBUS_OUT(63), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(64), + GlitchData => PPCS1PLBRDDBUS64_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(64)", + OutTemp => PPCS1PLBRDDBUS_OUT(64), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(65), + GlitchData => PPCS1PLBRDDBUS65_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(65)", + OutTemp => PPCS1PLBRDDBUS_OUT(65), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(66), + GlitchData => PPCS1PLBRDDBUS66_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(66)", + OutTemp => PPCS1PLBRDDBUS_OUT(66), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(67), + GlitchData => PPCS1PLBRDDBUS67_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(67)", + OutTemp => PPCS1PLBRDDBUS_OUT(67), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(68), + GlitchData => PPCS1PLBRDDBUS68_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(68)", + OutTemp => PPCS1PLBRDDBUS_OUT(68), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(69), + GlitchData => PPCS1PLBRDDBUS69_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(69)", + OutTemp => PPCS1PLBRDDBUS_OUT(69), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(70), + GlitchData => PPCS1PLBRDDBUS70_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(70)", + OutTemp => PPCS1PLBRDDBUS_OUT(70), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(71), + GlitchData => PPCS1PLBRDDBUS71_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(71)", + OutTemp => PPCS1PLBRDDBUS_OUT(71), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(72), + GlitchData => PPCS1PLBRDDBUS72_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(72)", + OutTemp => PPCS1PLBRDDBUS_OUT(72), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(73), + GlitchData => PPCS1PLBRDDBUS73_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(73)", + OutTemp => PPCS1PLBRDDBUS_OUT(73), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(74), + GlitchData => PPCS1PLBRDDBUS74_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(74)", + OutTemp => PPCS1PLBRDDBUS_OUT(74), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(75), + GlitchData => PPCS1PLBRDDBUS75_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(75)", + OutTemp => PPCS1PLBRDDBUS_OUT(75), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(76), + GlitchData => PPCS1PLBRDDBUS76_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(76)", + OutTemp => PPCS1PLBRDDBUS_OUT(76), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(77), + GlitchData => PPCS1PLBRDDBUS77_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(77)", + OutTemp => PPCS1PLBRDDBUS_OUT(77), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(78), + GlitchData => PPCS1PLBRDDBUS78_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(78)", + OutTemp => PPCS1PLBRDDBUS_OUT(78), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(79), + GlitchData => PPCS1PLBRDDBUS79_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(79)", + OutTemp => PPCS1PLBRDDBUS_OUT(79), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(80), + GlitchData => PPCS1PLBRDDBUS80_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(80)", + OutTemp => PPCS1PLBRDDBUS_OUT(80), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(81), + GlitchData => PPCS1PLBRDDBUS81_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(81)", + OutTemp => PPCS1PLBRDDBUS_OUT(81), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(82), + GlitchData => PPCS1PLBRDDBUS82_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(82)", + OutTemp => PPCS1PLBRDDBUS_OUT(82), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(83), + GlitchData => PPCS1PLBRDDBUS83_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(83)", + OutTemp => PPCS1PLBRDDBUS_OUT(83), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(84), + GlitchData => PPCS1PLBRDDBUS84_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(84)", + OutTemp => PPCS1PLBRDDBUS_OUT(84), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(85), + GlitchData => PPCS1PLBRDDBUS85_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(85)", + OutTemp => PPCS1PLBRDDBUS_OUT(85), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(86), + GlitchData => PPCS1PLBRDDBUS86_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(86)", + OutTemp => PPCS1PLBRDDBUS_OUT(86), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(87), + GlitchData => PPCS1PLBRDDBUS87_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(87)", + OutTemp => PPCS1PLBRDDBUS_OUT(87), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(88), + GlitchData => PPCS1PLBRDDBUS88_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(88)", + OutTemp => PPCS1PLBRDDBUS_OUT(88), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(89), + GlitchData => PPCS1PLBRDDBUS89_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(89)", + OutTemp => PPCS1PLBRDDBUS_OUT(89), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(90), + GlitchData => PPCS1PLBRDDBUS90_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(90)", + OutTemp => PPCS1PLBRDDBUS_OUT(90), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(91), + GlitchData => PPCS1PLBRDDBUS91_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(91)", + OutTemp => PPCS1PLBRDDBUS_OUT(91), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(92), + GlitchData => PPCS1PLBRDDBUS92_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(92)", + OutTemp => PPCS1PLBRDDBUS_OUT(92), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(93), + GlitchData => PPCS1PLBRDDBUS93_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(93)", + OutTemp => PPCS1PLBRDDBUS_OUT(93), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(94), + GlitchData => PPCS1PLBRDDBUS94_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(94)", + OutTemp => PPCS1PLBRDDBUS_OUT(94), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(95), + GlitchData => PPCS1PLBRDDBUS95_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(95)", + OutTemp => PPCS1PLBRDDBUS_OUT(95), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(96), + GlitchData => PPCS1PLBRDDBUS96_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(96)", + OutTemp => PPCS1PLBRDDBUS_OUT(96), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(97), + GlitchData => PPCS1PLBRDDBUS97_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(97)", + OutTemp => PPCS1PLBRDDBUS_OUT(97), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(98), + GlitchData => PPCS1PLBRDDBUS98_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(98)", + OutTemp => PPCS1PLBRDDBUS_OUT(98), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(99), + GlitchData => PPCS1PLBRDDBUS99_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(99)", + OutTemp => PPCS1PLBRDDBUS_OUT(99), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(100), + GlitchData => PPCS1PLBRDDBUS100_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(100)", + OutTemp => PPCS1PLBRDDBUS_OUT(100), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(101), + GlitchData => PPCS1PLBRDDBUS101_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(101)", + OutTemp => PPCS1PLBRDDBUS_OUT(101), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(102), + GlitchData => PPCS1PLBRDDBUS102_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(102)", + OutTemp => PPCS1PLBRDDBUS_OUT(102), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(103), + GlitchData => PPCS1PLBRDDBUS103_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(103)", + OutTemp => PPCS1PLBRDDBUS_OUT(103), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(104), + GlitchData => PPCS1PLBRDDBUS104_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(104)", + OutTemp => PPCS1PLBRDDBUS_OUT(104), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(105), + GlitchData => PPCS1PLBRDDBUS105_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(105)", + OutTemp => PPCS1PLBRDDBUS_OUT(105), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(106), + GlitchData => PPCS1PLBRDDBUS106_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(106)", + OutTemp => PPCS1PLBRDDBUS_OUT(106), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(107), + GlitchData => PPCS1PLBRDDBUS107_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(107)", + OutTemp => PPCS1PLBRDDBUS_OUT(107), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(108), + GlitchData => PPCS1PLBRDDBUS108_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(108)", + OutTemp => PPCS1PLBRDDBUS_OUT(108), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(109), + GlitchData => PPCS1PLBRDDBUS109_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(109)", + OutTemp => PPCS1PLBRDDBUS_OUT(109), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(110), + GlitchData => PPCS1PLBRDDBUS110_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(110)", + OutTemp => PPCS1PLBRDDBUS_OUT(110), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(111), + GlitchData => PPCS1PLBRDDBUS111_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(111)", + OutTemp => PPCS1PLBRDDBUS_OUT(111), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(112), + GlitchData => PPCS1PLBRDDBUS112_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(112)", + OutTemp => PPCS1PLBRDDBUS_OUT(112), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(113), + GlitchData => PPCS1PLBRDDBUS113_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(113)", + OutTemp => PPCS1PLBRDDBUS_OUT(113), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(114), + GlitchData => PPCS1PLBRDDBUS114_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(114)", + OutTemp => PPCS1PLBRDDBUS_OUT(114), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(115), + GlitchData => PPCS1PLBRDDBUS115_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(115)", + OutTemp => PPCS1PLBRDDBUS_OUT(115), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(116), + GlitchData => PPCS1PLBRDDBUS116_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(116)", + OutTemp => PPCS1PLBRDDBUS_OUT(116), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(117), + GlitchData => PPCS1PLBRDDBUS117_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(117)", + OutTemp => PPCS1PLBRDDBUS_OUT(117), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(118), + GlitchData => PPCS1PLBRDDBUS118_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(118)", + OutTemp => PPCS1PLBRDDBUS_OUT(118), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(119), + GlitchData => PPCS1PLBRDDBUS119_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(119)", + OutTemp => PPCS1PLBRDDBUS_OUT(119), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(120), + GlitchData => PPCS1PLBRDDBUS120_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(120)", + OutTemp => PPCS1PLBRDDBUS_OUT(120), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(121), + GlitchData => PPCS1PLBRDDBUS121_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(121)", + OutTemp => PPCS1PLBRDDBUS_OUT(121), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(122), + GlitchData => PPCS1PLBRDDBUS122_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(122)", + OutTemp => PPCS1PLBRDDBUS_OUT(122), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(123), + GlitchData => PPCS1PLBRDDBUS123_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(123)", + OutTemp => PPCS1PLBRDDBUS_OUT(123), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(124), + GlitchData => PPCS1PLBRDDBUS124_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(124)", + OutTemp => PPCS1PLBRDDBUS_OUT(124), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(125), + GlitchData => PPCS1PLBRDDBUS125_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(125)", + OutTemp => PPCS1PLBRDDBUS_OUT(125), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(126), + GlitchData => PPCS1PLBRDDBUS126_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(126)", + OutTemp => PPCS1PLBRDDBUS_OUT(126), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(127), + GlitchData => PPCS1PLBRDDBUS127_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(127)", + OutTemp => PPCS1PLBRDDBUS_OUT(127), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDWDADDR(0), + GlitchData => PPCS1PLBRDWDADDR0_GlitchData, + OutSignalName => "PPCS1PLBRDWDADDR(0)", + OutTemp => PPCS1PLBRDWDADDR_OUT(0), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDWDADDR(1), + GlitchData => PPCS1PLBRDWDADDR1_GlitchData, + OutSignalName => "PPCS1PLBRDWDADDR(1)", + OutTemp => PPCS1PLBRDWDADDR_OUT(1), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDWDADDR(2), + GlitchData => PPCS1PLBRDWDADDR2_GlitchData, + OutSignalName => "PPCS1PLBRDWDADDR(2)", + OutTemp => PPCS1PLBRDWDADDR_OUT(2), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDWDADDR(3), + GlitchData => PPCS1PLBRDWDADDR3_GlitchData, + OutSignalName => "PPCS1PLBRDWDADDR(3)", + OutTemp => PPCS1PLBRDWDADDR_OUT(3), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBREARBITRATE, + GlitchData => PPCS1PLBREARBITRATE_GlitchData, + OutSignalName => "PPCS1PLBREARBITRATE", + OutTemp => PPCS1PLBREARBITRATE_OUT, + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBSSIZE(0), + GlitchData => PPCS1PLBSSIZE0_GlitchData, + OutSignalName => "PPCS1PLBSSIZE(0)", + OutTemp => PPCS1PLBSSIZE_OUT(0), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBSSIZE(1), + GlitchData => PPCS1PLBSSIZE1_GlitchData, + OutSignalName => "PPCS1PLBSSIZE(1)", + OutTemp => PPCS1PLBSSIZE_OUT(1), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBWAIT, + GlitchData => PPCS1PLBWAIT_GlitchData, + OutSignalName => "PPCS1PLBWAIT", + OutTemp => PPCS1PLBWAIT_OUT, + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBWRBTERM, + GlitchData => PPCS1PLBWRBTERM_GlitchData, + OutSignalName => "PPCS1PLBWRBTERM", + OutTemp => PPCS1PLBWRBTERM_OUT, + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBWRCOMP, + GlitchData => PPCS1PLBWRCOMP_GlitchData, + OutSignalName => "PPCS1PLBWRCOMP", + OutTemp => PPCS1PLBWRCOMP_OUT, + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBWRDACK, + GlitchData => PPCS1PLBWRDACK_GlitchData, + OutSignalName => "PPCS1PLBWRDACK", + OutTemp => PPCS1PLBWRDACK_OUT, + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECFPUOP, + GlitchData => APUFCMDECFPUOP_GlitchData, + OutSignalName => "APUFCMDECFPUOP", + OutTemp => APUFCMDECFPUOP_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECLDSTXFERSIZE(0), + GlitchData => APUFCMDECLDSTXFERSIZE0_GlitchData, + OutSignalName => "APUFCMDECLDSTXFERSIZE(0)", + OutTemp => APUFCMDECLDSTXFERSIZE_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECLDSTXFERSIZE(1), + GlitchData => APUFCMDECLDSTXFERSIZE1_GlitchData, + OutSignalName => "APUFCMDECLDSTXFERSIZE(1)", + OutTemp => APUFCMDECLDSTXFERSIZE_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECLDSTXFERSIZE(2), + GlitchData => APUFCMDECLDSTXFERSIZE2_GlitchData, + OutSignalName => "APUFCMDECLDSTXFERSIZE(2)", + OutTemp => APUFCMDECLDSTXFERSIZE_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECLOAD, + GlitchData => APUFCMDECLOAD_GlitchData, + OutSignalName => "APUFCMDECLOAD", + OutTemp => APUFCMDECLOAD_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECNONAUTON, + GlitchData => APUFCMDECNONAUTON_GlitchData, + OutSignalName => "APUFCMDECNONAUTON", + OutTemp => APUFCMDECNONAUTON_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECSTORE, + GlitchData => APUFCMDECSTORE_GlitchData, + OutSignalName => "APUFCMDECSTORE", + OutTemp => APUFCMDECSTORE_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECUDI(0), + GlitchData => APUFCMDECUDI0_GlitchData, + OutSignalName => "APUFCMDECUDI(0)", + OutTemp => APUFCMDECUDI_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECUDI(1), + GlitchData => APUFCMDECUDI1_GlitchData, + OutSignalName => "APUFCMDECUDI(1)", + OutTemp => APUFCMDECUDI_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECUDI(2), + GlitchData => APUFCMDECUDI2_GlitchData, + OutSignalName => "APUFCMDECUDI(2)", + OutTemp => APUFCMDECUDI_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECUDI(3), + GlitchData => APUFCMDECUDI3_GlitchData, + OutSignalName => "APUFCMDECUDI(3)", + OutTemp => APUFCMDECUDI_OUT(3), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECUDIVALID, + GlitchData => APUFCMDECUDIVALID_GlitchData, + OutSignalName => "APUFCMDECUDIVALID", + OutTemp => APUFCMDECUDIVALID_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMENDIAN, + GlitchData => APUFCMENDIAN_GlitchData, + OutSignalName => "APUFCMENDIAN", + OutTemp => APUFCMENDIAN_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMFLUSH, + GlitchData => APUFCMFLUSH_GlitchData, + OutSignalName => "APUFCMFLUSH", + OutTemp => APUFCMFLUSH_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(0), + GlitchData => APUFCMINSTRUCTION0_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(0)", + OutTemp => APUFCMINSTRUCTION_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(1), + GlitchData => APUFCMINSTRUCTION1_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(1)", + OutTemp => APUFCMINSTRUCTION_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(2), + GlitchData => APUFCMINSTRUCTION2_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(2)", + OutTemp => APUFCMINSTRUCTION_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(3), + GlitchData => APUFCMINSTRUCTION3_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(3)", + OutTemp => APUFCMINSTRUCTION_OUT(3), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(4), + GlitchData => APUFCMINSTRUCTION4_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(4)", + OutTemp => APUFCMINSTRUCTION_OUT(4), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(5), + GlitchData => APUFCMINSTRUCTION5_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(5)", + OutTemp => APUFCMINSTRUCTION_OUT(5), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(6), + GlitchData => APUFCMINSTRUCTION6_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(6)", + OutTemp => APUFCMINSTRUCTION_OUT(6), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(7), + GlitchData => APUFCMINSTRUCTION7_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(7)", + OutTemp => APUFCMINSTRUCTION_OUT(7), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(8), + GlitchData => APUFCMINSTRUCTION8_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(8)", + OutTemp => APUFCMINSTRUCTION_OUT(8), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(9), + GlitchData => APUFCMINSTRUCTION9_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(9)", + OutTemp => APUFCMINSTRUCTION_OUT(9), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(10), + GlitchData => APUFCMINSTRUCTION10_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(10)", + OutTemp => APUFCMINSTRUCTION_OUT(10), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(11), + GlitchData => APUFCMINSTRUCTION11_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(11)", + OutTemp => APUFCMINSTRUCTION_OUT(11), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(12), + GlitchData => APUFCMINSTRUCTION12_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(12)", + OutTemp => APUFCMINSTRUCTION_OUT(12), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(13), + GlitchData => APUFCMINSTRUCTION13_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(13)", + OutTemp => APUFCMINSTRUCTION_OUT(13), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(14), + GlitchData => APUFCMINSTRUCTION14_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(14)", + OutTemp => APUFCMINSTRUCTION_OUT(14), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(15), + GlitchData => APUFCMINSTRUCTION15_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(15)", + OutTemp => APUFCMINSTRUCTION_OUT(15), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(16), + GlitchData => APUFCMINSTRUCTION16_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(16)", + OutTemp => APUFCMINSTRUCTION_OUT(16), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(17), + GlitchData => APUFCMINSTRUCTION17_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(17)", + OutTemp => APUFCMINSTRUCTION_OUT(17), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(18), + GlitchData => APUFCMINSTRUCTION18_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(18)", + OutTemp => APUFCMINSTRUCTION_OUT(18), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(19), + GlitchData => APUFCMINSTRUCTION19_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(19)", + OutTemp => APUFCMINSTRUCTION_OUT(19), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(20), + GlitchData => APUFCMINSTRUCTION20_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(20)", + OutTemp => APUFCMINSTRUCTION_OUT(20), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(21), + GlitchData => APUFCMINSTRUCTION21_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(21)", + OutTemp => APUFCMINSTRUCTION_OUT(21), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(22), + GlitchData => APUFCMINSTRUCTION22_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(22)", + OutTemp => APUFCMINSTRUCTION_OUT(22), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(23), + GlitchData => APUFCMINSTRUCTION23_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(23)", + OutTemp => APUFCMINSTRUCTION_OUT(23), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(24), + GlitchData => APUFCMINSTRUCTION24_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(24)", + OutTemp => APUFCMINSTRUCTION_OUT(24), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(25), + GlitchData => APUFCMINSTRUCTION25_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(25)", + OutTemp => APUFCMINSTRUCTION_OUT(25), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(26), + GlitchData => APUFCMINSTRUCTION26_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(26)", + OutTemp => APUFCMINSTRUCTION_OUT(26), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(27), + GlitchData => APUFCMINSTRUCTION27_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(27)", + OutTemp => APUFCMINSTRUCTION_OUT(27), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(28), + GlitchData => APUFCMINSTRUCTION28_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(28)", + OutTemp => APUFCMINSTRUCTION_OUT(28), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(29), + GlitchData => APUFCMINSTRUCTION29_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(29)", + OutTemp => APUFCMINSTRUCTION_OUT(29), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(30), + GlitchData => APUFCMINSTRUCTION30_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(30)", + OutTemp => APUFCMINSTRUCTION_OUT(30), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(31), + GlitchData => APUFCMINSTRUCTION31_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(31)", + OutTemp => APUFCMINSTRUCTION_OUT(31), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRVALID, + GlitchData => APUFCMINSTRVALID_GlitchData, + OutSignalName => "APUFCMINSTRVALID", + OutTemp => APUFCMINSTRVALID_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADBYTEADDR(0), + GlitchData => APUFCMLOADBYTEADDR0_GlitchData, + OutSignalName => "APUFCMLOADBYTEADDR(0)", + OutTemp => APUFCMLOADBYTEADDR_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADBYTEADDR(1), + GlitchData => APUFCMLOADBYTEADDR1_GlitchData, + OutSignalName => "APUFCMLOADBYTEADDR(1)", + OutTemp => APUFCMLOADBYTEADDR_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADBYTEADDR(2), + GlitchData => APUFCMLOADBYTEADDR2_GlitchData, + OutSignalName => "APUFCMLOADBYTEADDR(2)", + OutTemp => APUFCMLOADBYTEADDR_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADBYTEADDR(3), + GlitchData => APUFCMLOADBYTEADDR3_GlitchData, + OutSignalName => "APUFCMLOADBYTEADDR(3)", + OutTemp => APUFCMLOADBYTEADDR_OUT(3), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(0), + GlitchData => APUFCMLOADDATA0_GlitchData, + OutSignalName => "APUFCMLOADDATA(0)", + OutTemp => APUFCMLOADDATA_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(1), + GlitchData => APUFCMLOADDATA1_GlitchData, + OutSignalName => "APUFCMLOADDATA(1)", + OutTemp => APUFCMLOADDATA_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(2), + GlitchData => APUFCMLOADDATA2_GlitchData, + OutSignalName => "APUFCMLOADDATA(2)", + OutTemp => APUFCMLOADDATA_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(3), + GlitchData => APUFCMLOADDATA3_GlitchData, + OutSignalName => "APUFCMLOADDATA(3)", + OutTemp => APUFCMLOADDATA_OUT(3), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(4), + GlitchData => APUFCMLOADDATA4_GlitchData, + OutSignalName => "APUFCMLOADDATA(4)", + OutTemp => APUFCMLOADDATA_OUT(4), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(5), + GlitchData => APUFCMLOADDATA5_GlitchData, + OutSignalName => "APUFCMLOADDATA(5)", + OutTemp => APUFCMLOADDATA_OUT(5), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(6), + GlitchData => APUFCMLOADDATA6_GlitchData, + OutSignalName => "APUFCMLOADDATA(6)", + OutTemp => APUFCMLOADDATA_OUT(6), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(7), + GlitchData => APUFCMLOADDATA7_GlitchData, + OutSignalName => "APUFCMLOADDATA(7)", + OutTemp => APUFCMLOADDATA_OUT(7), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(8), + GlitchData => APUFCMLOADDATA8_GlitchData, + OutSignalName => "APUFCMLOADDATA(8)", + OutTemp => APUFCMLOADDATA_OUT(8), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(9), + GlitchData => APUFCMLOADDATA9_GlitchData, + OutSignalName => "APUFCMLOADDATA(9)", + OutTemp => APUFCMLOADDATA_OUT(9), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(10), + GlitchData => APUFCMLOADDATA10_GlitchData, + OutSignalName => "APUFCMLOADDATA(10)", + OutTemp => APUFCMLOADDATA_OUT(10), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(11), + GlitchData => APUFCMLOADDATA11_GlitchData, + OutSignalName => "APUFCMLOADDATA(11)", + OutTemp => APUFCMLOADDATA_OUT(11), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(12), + GlitchData => APUFCMLOADDATA12_GlitchData, + OutSignalName => "APUFCMLOADDATA(12)", + OutTemp => APUFCMLOADDATA_OUT(12), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(13), + GlitchData => APUFCMLOADDATA13_GlitchData, + OutSignalName => "APUFCMLOADDATA(13)", + OutTemp => APUFCMLOADDATA_OUT(13), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(14), + GlitchData => APUFCMLOADDATA14_GlitchData, + OutSignalName => "APUFCMLOADDATA(14)", + OutTemp => APUFCMLOADDATA_OUT(14), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(15), + GlitchData => APUFCMLOADDATA15_GlitchData, + OutSignalName => "APUFCMLOADDATA(15)", + OutTemp => APUFCMLOADDATA_OUT(15), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(16), + GlitchData => APUFCMLOADDATA16_GlitchData, + OutSignalName => "APUFCMLOADDATA(16)", + OutTemp => APUFCMLOADDATA_OUT(16), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(17), + GlitchData => APUFCMLOADDATA17_GlitchData, + OutSignalName => "APUFCMLOADDATA(17)", + OutTemp => APUFCMLOADDATA_OUT(17), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(18), + GlitchData => APUFCMLOADDATA18_GlitchData, + OutSignalName => "APUFCMLOADDATA(18)", + OutTemp => APUFCMLOADDATA_OUT(18), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(19), + GlitchData => APUFCMLOADDATA19_GlitchData, + OutSignalName => "APUFCMLOADDATA(19)", + OutTemp => APUFCMLOADDATA_OUT(19), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(20), + GlitchData => APUFCMLOADDATA20_GlitchData, + OutSignalName => "APUFCMLOADDATA(20)", + OutTemp => APUFCMLOADDATA_OUT(20), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(21), + GlitchData => APUFCMLOADDATA21_GlitchData, + OutSignalName => "APUFCMLOADDATA(21)", + OutTemp => APUFCMLOADDATA_OUT(21), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(22), + GlitchData => APUFCMLOADDATA22_GlitchData, + OutSignalName => "APUFCMLOADDATA(22)", + OutTemp => APUFCMLOADDATA_OUT(22), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(23), + GlitchData => APUFCMLOADDATA23_GlitchData, + OutSignalName => "APUFCMLOADDATA(23)", + OutTemp => APUFCMLOADDATA_OUT(23), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(24), + GlitchData => APUFCMLOADDATA24_GlitchData, + OutSignalName => "APUFCMLOADDATA(24)", + OutTemp => APUFCMLOADDATA_OUT(24), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(25), + GlitchData => APUFCMLOADDATA25_GlitchData, + OutSignalName => "APUFCMLOADDATA(25)", + OutTemp => APUFCMLOADDATA_OUT(25), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(26), + GlitchData => APUFCMLOADDATA26_GlitchData, + OutSignalName => "APUFCMLOADDATA(26)", + OutTemp => APUFCMLOADDATA_OUT(26), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(27), + GlitchData => APUFCMLOADDATA27_GlitchData, + OutSignalName => "APUFCMLOADDATA(27)", + OutTemp => APUFCMLOADDATA_OUT(27), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(28), + GlitchData => APUFCMLOADDATA28_GlitchData, + OutSignalName => "APUFCMLOADDATA(28)", + OutTemp => APUFCMLOADDATA_OUT(28), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(29), + GlitchData => APUFCMLOADDATA29_GlitchData, + OutSignalName => "APUFCMLOADDATA(29)", + OutTemp => APUFCMLOADDATA_OUT(29), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(30), + GlitchData => APUFCMLOADDATA30_GlitchData, + OutSignalName => "APUFCMLOADDATA(30)", + OutTemp => APUFCMLOADDATA_OUT(30), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(31), + GlitchData => APUFCMLOADDATA31_GlitchData, + OutSignalName => "APUFCMLOADDATA(31)", + OutTemp => APUFCMLOADDATA_OUT(31), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(32), + GlitchData => APUFCMLOADDATA32_GlitchData, + OutSignalName => "APUFCMLOADDATA(32)", + OutTemp => APUFCMLOADDATA_OUT(32), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(33), + GlitchData => APUFCMLOADDATA33_GlitchData, + OutSignalName => "APUFCMLOADDATA(33)", + OutTemp => APUFCMLOADDATA_OUT(33), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(34), + GlitchData => APUFCMLOADDATA34_GlitchData, + OutSignalName => "APUFCMLOADDATA(34)", + OutTemp => APUFCMLOADDATA_OUT(34), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(35), + GlitchData => APUFCMLOADDATA35_GlitchData, + OutSignalName => "APUFCMLOADDATA(35)", + OutTemp => APUFCMLOADDATA_OUT(35), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(36), + GlitchData => APUFCMLOADDATA36_GlitchData, + OutSignalName => "APUFCMLOADDATA(36)", + OutTemp => APUFCMLOADDATA_OUT(36), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(37), + GlitchData => APUFCMLOADDATA37_GlitchData, + OutSignalName => "APUFCMLOADDATA(37)", + OutTemp => APUFCMLOADDATA_OUT(37), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(38), + GlitchData => APUFCMLOADDATA38_GlitchData, + OutSignalName => "APUFCMLOADDATA(38)", + OutTemp => APUFCMLOADDATA_OUT(38), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(39), + GlitchData => APUFCMLOADDATA39_GlitchData, + OutSignalName => "APUFCMLOADDATA(39)", + OutTemp => APUFCMLOADDATA_OUT(39), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(40), + GlitchData => APUFCMLOADDATA40_GlitchData, + OutSignalName => "APUFCMLOADDATA(40)", + OutTemp => APUFCMLOADDATA_OUT(40), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(41), + GlitchData => APUFCMLOADDATA41_GlitchData, + OutSignalName => "APUFCMLOADDATA(41)", + OutTemp => APUFCMLOADDATA_OUT(41), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(42), + GlitchData => APUFCMLOADDATA42_GlitchData, + OutSignalName => "APUFCMLOADDATA(42)", + OutTemp => APUFCMLOADDATA_OUT(42), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(43), + GlitchData => APUFCMLOADDATA43_GlitchData, + OutSignalName => "APUFCMLOADDATA(43)", + OutTemp => APUFCMLOADDATA_OUT(43), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(44), + GlitchData => APUFCMLOADDATA44_GlitchData, + OutSignalName => "APUFCMLOADDATA(44)", + OutTemp => APUFCMLOADDATA_OUT(44), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(45), + GlitchData => APUFCMLOADDATA45_GlitchData, + OutSignalName => "APUFCMLOADDATA(45)", + OutTemp => APUFCMLOADDATA_OUT(45), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(46), + GlitchData => APUFCMLOADDATA46_GlitchData, + OutSignalName => "APUFCMLOADDATA(46)", + OutTemp => APUFCMLOADDATA_OUT(46), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(47), + GlitchData => APUFCMLOADDATA47_GlitchData, + OutSignalName => "APUFCMLOADDATA(47)", + OutTemp => APUFCMLOADDATA_OUT(47), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(48), + GlitchData => APUFCMLOADDATA48_GlitchData, + OutSignalName => "APUFCMLOADDATA(48)", + OutTemp => APUFCMLOADDATA_OUT(48), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(49), + GlitchData => APUFCMLOADDATA49_GlitchData, + OutSignalName => "APUFCMLOADDATA(49)", + OutTemp => APUFCMLOADDATA_OUT(49), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(50), + GlitchData => APUFCMLOADDATA50_GlitchData, + OutSignalName => "APUFCMLOADDATA(50)", + OutTemp => APUFCMLOADDATA_OUT(50), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(51), + GlitchData => APUFCMLOADDATA51_GlitchData, + OutSignalName => "APUFCMLOADDATA(51)", + OutTemp => APUFCMLOADDATA_OUT(51), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(52), + GlitchData => APUFCMLOADDATA52_GlitchData, + OutSignalName => "APUFCMLOADDATA(52)", + OutTemp => APUFCMLOADDATA_OUT(52), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(53), + GlitchData => APUFCMLOADDATA53_GlitchData, + OutSignalName => "APUFCMLOADDATA(53)", + OutTemp => APUFCMLOADDATA_OUT(53), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(54), + GlitchData => APUFCMLOADDATA54_GlitchData, + OutSignalName => "APUFCMLOADDATA(54)", + OutTemp => APUFCMLOADDATA_OUT(54), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(55), + GlitchData => APUFCMLOADDATA55_GlitchData, + OutSignalName => "APUFCMLOADDATA(55)", + OutTemp => APUFCMLOADDATA_OUT(55), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(56), + GlitchData => APUFCMLOADDATA56_GlitchData, + OutSignalName => "APUFCMLOADDATA(56)", + OutTemp => APUFCMLOADDATA_OUT(56), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(57), + GlitchData => APUFCMLOADDATA57_GlitchData, + OutSignalName => "APUFCMLOADDATA(57)", + OutTemp => APUFCMLOADDATA_OUT(57), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(58), + GlitchData => APUFCMLOADDATA58_GlitchData, + OutSignalName => "APUFCMLOADDATA(58)", + OutTemp => APUFCMLOADDATA_OUT(58), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(59), + GlitchData => APUFCMLOADDATA59_GlitchData, + OutSignalName => "APUFCMLOADDATA(59)", + OutTemp => APUFCMLOADDATA_OUT(59), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(60), + GlitchData => APUFCMLOADDATA60_GlitchData, + OutSignalName => "APUFCMLOADDATA(60)", + OutTemp => APUFCMLOADDATA_OUT(60), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(61), + GlitchData => APUFCMLOADDATA61_GlitchData, + OutSignalName => "APUFCMLOADDATA(61)", + OutTemp => APUFCMLOADDATA_OUT(61), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(62), + GlitchData => APUFCMLOADDATA62_GlitchData, + OutSignalName => "APUFCMLOADDATA(62)", + OutTemp => APUFCMLOADDATA_OUT(62), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(63), + GlitchData => APUFCMLOADDATA63_GlitchData, + OutSignalName => "APUFCMLOADDATA(63)", + OutTemp => APUFCMLOADDATA_OUT(63), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(64), + GlitchData => APUFCMLOADDATA64_GlitchData, + OutSignalName => "APUFCMLOADDATA(64)", + OutTemp => APUFCMLOADDATA_OUT(64), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(65), + GlitchData => APUFCMLOADDATA65_GlitchData, + OutSignalName => "APUFCMLOADDATA(65)", + OutTemp => APUFCMLOADDATA_OUT(65), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(66), + GlitchData => APUFCMLOADDATA66_GlitchData, + OutSignalName => "APUFCMLOADDATA(66)", + OutTemp => APUFCMLOADDATA_OUT(66), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(67), + GlitchData => APUFCMLOADDATA67_GlitchData, + OutSignalName => "APUFCMLOADDATA(67)", + OutTemp => APUFCMLOADDATA_OUT(67), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(68), + GlitchData => APUFCMLOADDATA68_GlitchData, + OutSignalName => "APUFCMLOADDATA(68)", + OutTemp => APUFCMLOADDATA_OUT(68), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(69), + GlitchData => APUFCMLOADDATA69_GlitchData, + OutSignalName => "APUFCMLOADDATA(69)", + OutTemp => APUFCMLOADDATA_OUT(69), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(70), + GlitchData => APUFCMLOADDATA70_GlitchData, + OutSignalName => "APUFCMLOADDATA(70)", + OutTemp => APUFCMLOADDATA_OUT(70), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(71), + GlitchData => APUFCMLOADDATA71_GlitchData, + OutSignalName => "APUFCMLOADDATA(71)", + OutTemp => APUFCMLOADDATA_OUT(71), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(72), + GlitchData => APUFCMLOADDATA72_GlitchData, + OutSignalName => "APUFCMLOADDATA(72)", + OutTemp => APUFCMLOADDATA_OUT(72), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(73), + GlitchData => APUFCMLOADDATA73_GlitchData, + OutSignalName => "APUFCMLOADDATA(73)", + OutTemp => APUFCMLOADDATA_OUT(73), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(74), + GlitchData => APUFCMLOADDATA74_GlitchData, + OutSignalName => "APUFCMLOADDATA(74)", + OutTemp => APUFCMLOADDATA_OUT(74), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(75), + GlitchData => APUFCMLOADDATA75_GlitchData, + OutSignalName => "APUFCMLOADDATA(75)", + OutTemp => APUFCMLOADDATA_OUT(75), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(76), + GlitchData => APUFCMLOADDATA76_GlitchData, + OutSignalName => "APUFCMLOADDATA(76)", + OutTemp => APUFCMLOADDATA_OUT(76), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(77), + GlitchData => APUFCMLOADDATA77_GlitchData, + OutSignalName => "APUFCMLOADDATA(77)", + OutTemp => APUFCMLOADDATA_OUT(77), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(78), + GlitchData => APUFCMLOADDATA78_GlitchData, + OutSignalName => "APUFCMLOADDATA(78)", + OutTemp => APUFCMLOADDATA_OUT(78), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(79), + GlitchData => APUFCMLOADDATA79_GlitchData, + OutSignalName => "APUFCMLOADDATA(79)", + OutTemp => APUFCMLOADDATA_OUT(79), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(80), + GlitchData => APUFCMLOADDATA80_GlitchData, + OutSignalName => "APUFCMLOADDATA(80)", + OutTemp => APUFCMLOADDATA_OUT(80), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(81), + GlitchData => APUFCMLOADDATA81_GlitchData, + OutSignalName => "APUFCMLOADDATA(81)", + OutTemp => APUFCMLOADDATA_OUT(81), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(82), + GlitchData => APUFCMLOADDATA82_GlitchData, + OutSignalName => "APUFCMLOADDATA(82)", + OutTemp => APUFCMLOADDATA_OUT(82), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(83), + GlitchData => APUFCMLOADDATA83_GlitchData, + OutSignalName => "APUFCMLOADDATA(83)", + OutTemp => APUFCMLOADDATA_OUT(83), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(84), + GlitchData => APUFCMLOADDATA84_GlitchData, + OutSignalName => "APUFCMLOADDATA(84)", + OutTemp => APUFCMLOADDATA_OUT(84), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(85), + GlitchData => APUFCMLOADDATA85_GlitchData, + OutSignalName => "APUFCMLOADDATA(85)", + OutTemp => APUFCMLOADDATA_OUT(85), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(86), + GlitchData => APUFCMLOADDATA86_GlitchData, + OutSignalName => "APUFCMLOADDATA(86)", + OutTemp => APUFCMLOADDATA_OUT(86), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(87), + GlitchData => APUFCMLOADDATA87_GlitchData, + OutSignalName => "APUFCMLOADDATA(87)", + OutTemp => APUFCMLOADDATA_OUT(87), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(88), + GlitchData => APUFCMLOADDATA88_GlitchData, + OutSignalName => "APUFCMLOADDATA(88)", + OutTemp => APUFCMLOADDATA_OUT(88), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(89), + GlitchData => APUFCMLOADDATA89_GlitchData, + OutSignalName => "APUFCMLOADDATA(89)", + OutTemp => APUFCMLOADDATA_OUT(89), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(90), + GlitchData => APUFCMLOADDATA90_GlitchData, + OutSignalName => "APUFCMLOADDATA(90)", + OutTemp => APUFCMLOADDATA_OUT(90), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(91), + GlitchData => APUFCMLOADDATA91_GlitchData, + OutSignalName => "APUFCMLOADDATA(91)", + OutTemp => APUFCMLOADDATA_OUT(91), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(92), + GlitchData => APUFCMLOADDATA92_GlitchData, + OutSignalName => "APUFCMLOADDATA(92)", + OutTemp => APUFCMLOADDATA_OUT(92), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(93), + GlitchData => APUFCMLOADDATA93_GlitchData, + OutSignalName => "APUFCMLOADDATA(93)", + OutTemp => APUFCMLOADDATA_OUT(93), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(94), + GlitchData => APUFCMLOADDATA94_GlitchData, + OutSignalName => "APUFCMLOADDATA(94)", + OutTemp => APUFCMLOADDATA_OUT(94), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(95), + GlitchData => APUFCMLOADDATA95_GlitchData, + OutSignalName => "APUFCMLOADDATA(95)", + OutTemp => APUFCMLOADDATA_OUT(95), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(96), + GlitchData => APUFCMLOADDATA96_GlitchData, + OutSignalName => "APUFCMLOADDATA(96)", + OutTemp => APUFCMLOADDATA_OUT(96), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(97), + GlitchData => APUFCMLOADDATA97_GlitchData, + OutSignalName => "APUFCMLOADDATA(97)", + OutTemp => APUFCMLOADDATA_OUT(97), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(98), + GlitchData => APUFCMLOADDATA98_GlitchData, + OutSignalName => "APUFCMLOADDATA(98)", + OutTemp => APUFCMLOADDATA_OUT(98), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(99), + GlitchData => APUFCMLOADDATA99_GlitchData, + OutSignalName => "APUFCMLOADDATA(99)", + OutTemp => APUFCMLOADDATA_OUT(99), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(100), + GlitchData => APUFCMLOADDATA100_GlitchData, + OutSignalName => "APUFCMLOADDATA(100)", + OutTemp => APUFCMLOADDATA_OUT(100), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(101), + GlitchData => APUFCMLOADDATA101_GlitchData, + OutSignalName => "APUFCMLOADDATA(101)", + OutTemp => APUFCMLOADDATA_OUT(101), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(102), + GlitchData => APUFCMLOADDATA102_GlitchData, + OutSignalName => "APUFCMLOADDATA(102)", + OutTemp => APUFCMLOADDATA_OUT(102), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(103), + GlitchData => APUFCMLOADDATA103_GlitchData, + OutSignalName => "APUFCMLOADDATA(103)", + OutTemp => APUFCMLOADDATA_OUT(103), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(104), + GlitchData => APUFCMLOADDATA104_GlitchData, + OutSignalName => "APUFCMLOADDATA(104)", + OutTemp => APUFCMLOADDATA_OUT(104), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(105), + GlitchData => APUFCMLOADDATA105_GlitchData, + OutSignalName => "APUFCMLOADDATA(105)", + OutTemp => APUFCMLOADDATA_OUT(105), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(106), + GlitchData => APUFCMLOADDATA106_GlitchData, + OutSignalName => "APUFCMLOADDATA(106)", + OutTemp => APUFCMLOADDATA_OUT(106), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(107), + GlitchData => APUFCMLOADDATA107_GlitchData, + OutSignalName => "APUFCMLOADDATA(107)", + OutTemp => APUFCMLOADDATA_OUT(107), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(108), + GlitchData => APUFCMLOADDATA108_GlitchData, + OutSignalName => "APUFCMLOADDATA(108)", + OutTemp => APUFCMLOADDATA_OUT(108), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(109), + GlitchData => APUFCMLOADDATA109_GlitchData, + OutSignalName => "APUFCMLOADDATA(109)", + OutTemp => APUFCMLOADDATA_OUT(109), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(110), + GlitchData => APUFCMLOADDATA110_GlitchData, + OutSignalName => "APUFCMLOADDATA(110)", + OutTemp => APUFCMLOADDATA_OUT(110), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(111), + GlitchData => APUFCMLOADDATA111_GlitchData, + OutSignalName => "APUFCMLOADDATA(111)", + OutTemp => APUFCMLOADDATA_OUT(111), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(112), + GlitchData => APUFCMLOADDATA112_GlitchData, + OutSignalName => "APUFCMLOADDATA(112)", + OutTemp => APUFCMLOADDATA_OUT(112), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(113), + GlitchData => APUFCMLOADDATA113_GlitchData, + OutSignalName => "APUFCMLOADDATA(113)", + OutTemp => APUFCMLOADDATA_OUT(113), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(114), + GlitchData => APUFCMLOADDATA114_GlitchData, + OutSignalName => "APUFCMLOADDATA(114)", + OutTemp => APUFCMLOADDATA_OUT(114), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(115), + GlitchData => APUFCMLOADDATA115_GlitchData, + OutSignalName => "APUFCMLOADDATA(115)", + OutTemp => APUFCMLOADDATA_OUT(115), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(116), + GlitchData => APUFCMLOADDATA116_GlitchData, + OutSignalName => "APUFCMLOADDATA(116)", + OutTemp => APUFCMLOADDATA_OUT(116), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(117), + GlitchData => APUFCMLOADDATA117_GlitchData, + OutSignalName => "APUFCMLOADDATA(117)", + OutTemp => APUFCMLOADDATA_OUT(117), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(118), + GlitchData => APUFCMLOADDATA118_GlitchData, + OutSignalName => "APUFCMLOADDATA(118)", + OutTemp => APUFCMLOADDATA_OUT(118), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(119), + GlitchData => APUFCMLOADDATA119_GlitchData, + OutSignalName => "APUFCMLOADDATA(119)", + OutTemp => APUFCMLOADDATA_OUT(119), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(120), + GlitchData => APUFCMLOADDATA120_GlitchData, + OutSignalName => "APUFCMLOADDATA(120)", + OutTemp => APUFCMLOADDATA_OUT(120), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(121), + GlitchData => APUFCMLOADDATA121_GlitchData, + OutSignalName => "APUFCMLOADDATA(121)", + OutTemp => APUFCMLOADDATA_OUT(121), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(122), + GlitchData => APUFCMLOADDATA122_GlitchData, + OutSignalName => "APUFCMLOADDATA(122)", + OutTemp => APUFCMLOADDATA_OUT(122), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(123), + GlitchData => APUFCMLOADDATA123_GlitchData, + OutSignalName => "APUFCMLOADDATA(123)", + OutTemp => APUFCMLOADDATA_OUT(123), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(124), + GlitchData => APUFCMLOADDATA124_GlitchData, + OutSignalName => "APUFCMLOADDATA(124)", + OutTemp => APUFCMLOADDATA_OUT(124), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(125), + GlitchData => APUFCMLOADDATA125_GlitchData, + OutSignalName => "APUFCMLOADDATA(125)", + OutTemp => APUFCMLOADDATA_OUT(125), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(126), + GlitchData => APUFCMLOADDATA126_GlitchData, + OutSignalName => "APUFCMLOADDATA(126)", + OutTemp => APUFCMLOADDATA_OUT(126), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(127), + GlitchData => APUFCMLOADDATA127_GlitchData, + OutSignalName => "APUFCMLOADDATA(127)", + OutTemp => APUFCMLOADDATA_OUT(127), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDVALID, + GlitchData => APUFCMLOADDVALID_GlitchData, + OutSignalName => "APUFCMLOADDVALID", + OutTemp => APUFCMLOADDVALID_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMMSRFE0, + GlitchData => APUFCMMSRFE0_GlitchData, + OutSignalName => "APUFCMMSRFE0", + OutTemp => APUFCMMSRFE0_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMMSRFE1, + GlitchData => APUFCMMSRFE1_GlitchData, + OutSignalName => "APUFCMMSRFE1", + OutTemp => APUFCMMSRFE1_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMNEXTINSTRREADY, + GlitchData => APUFCMNEXTINSTRREADY_GlitchData, + OutSignalName => "APUFCMNEXTINSTRREADY", + OutTemp => APUFCMNEXTINSTRREADY_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMOPERANDVALID, + GlitchData => APUFCMOPERANDVALID_GlitchData, + OutSignalName => "APUFCMOPERANDVALID", + OutTemp => APUFCMOPERANDVALID_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(0), + GlitchData => APUFCMRADATA0_GlitchData, + OutSignalName => "APUFCMRADATA(0)", + OutTemp => APUFCMRADATA_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(1), + GlitchData => APUFCMRADATA1_GlitchData, + OutSignalName => "APUFCMRADATA(1)", + OutTemp => APUFCMRADATA_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(2), + GlitchData => APUFCMRADATA2_GlitchData, + OutSignalName => "APUFCMRADATA(2)", + OutTemp => APUFCMRADATA_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(3), + GlitchData => APUFCMRADATA3_GlitchData, + OutSignalName => "APUFCMRADATA(3)", + OutTemp => APUFCMRADATA_OUT(3), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(4), + GlitchData => APUFCMRADATA4_GlitchData, + OutSignalName => "APUFCMRADATA(4)", + OutTemp => APUFCMRADATA_OUT(4), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(5), + GlitchData => APUFCMRADATA5_GlitchData, + OutSignalName => "APUFCMRADATA(5)", + OutTemp => APUFCMRADATA_OUT(5), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(6), + GlitchData => APUFCMRADATA6_GlitchData, + OutSignalName => "APUFCMRADATA(6)", + OutTemp => APUFCMRADATA_OUT(6), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(7), + GlitchData => APUFCMRADATA7_GlitchData, + OutSignalName => "APUFCMRADATA(7)", + OutTemp => APUFCMRADATA_OUT(7), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(8), + GlitchData => APUFCMRADATA8_GlitchData, + OutSignalName => "APUFCMRADATA(8)", + OutTemp => APUFCMRADATA_OUT(8), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(9), + GlitchData => APUFCMRADATA9_GlitchData, + OutSignalName => "APUFCMRADATA(9)", + OutTemp => APUFCMRADATA_OUT(9), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(10), + GlitchData => APUFCMRADATA10_GlitchData, + OutSignalName => "APUFCMRADATA(10)", + OutTemp => APUFCMRADATA_OUT(10), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(11), + GlitchData => APUFCMRADATA11_GlitchData, + OutSignalName => "APUFCMRADATA(11)", + OutTemp => APUFCMRADATA_OUT(11), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(12), + GlitchData => APUFCMRADATA12_GlitchData, + OutSignalName => "APUFCMRADATA(12)", + OutTemp => APUFCMRADATA_OUT(12), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(13), + GlitchData => APUFCMRADATA13_GlitchData, + OutSignalName => "APUFCMRADATA(13)", + OutTemp => APUFCMRADATA_OUT(13), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(14), + GlitchData => APUFCMRADATA14_GlitchData, + OutSignalName => "APUFCMRADATA(14)", + OutTemp => APUFCMRADATA_OUT(14), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(15), + GlitchData => APUFCMRADATA15_GlitchData, + OutSignalName => "APUFCMRADATA(15)", + OutTemp => APUFCMRADATA_OUT(15), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(16), + GlitchData => APUFCMRADATA16_GlitchData, + OutSignalName => "APUFCMRADATA(16)", + OutTemp => APUFCMRADATA_OUT(16), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(17), + GlitchData => APUFCMRADATA17_GlitchData, + OutSignalName => "APUFCMRADATA(17)", + OutTemp => APUFCMRADATA_OUT(17), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(18), + GlitchData => APUFCMRADATA18_GlitchData, + OutSignalName => "APUFCMRADATA(18)", + OutTemp => APUFCMRADATA_OUT(18), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(19), + GlitchData => APUFCMRADATA19_GlitchData, + OutSignalName => "APUFCMRADATA(19)", + OutTemp => APUFCMRADATA_OUT(19), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(20), + GlitchData => APUFCMRADATA20_GlitchData, + OutSignalName => "APUFCMRADATA(20)", + OutTemp => APUFCMRADATA_OUT(20), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(21), + GlitchData => APUFCMRADATA21_GlitchData, + OutSignalName => "APUFCMRADATA(21)", + OutTemp => APUFCMRADATA_OUT(21), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(22), + GlitchData => APUFCMRADATA22_GlitchData, + OutSignalName => "APUFCMRADATA(22)", + OutTemp => APUFCMRADATA_OUT(22), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(23), + GlitchData => APUFCMRADATA23_GlitchData, + OutSignalName => "APUFCMRADATA(23)", + OutTemp => APUFCMRADATA_OUT(23), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(24), + GlitchData => APUFCMRADATA24_GlitchData, + OutSignalName => "APUFCMRADATA(24)", + OutTemp => APUFCMRADATA_OUT(24), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(25), + GlitchData => APUFCMRADATA25_GlitchData, + OutSignalName => "APUFCMRADATA(25)", + OutTemp => APUFCMRADATA_OUT(25), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(26), + GlitchData => APUFCMRADATA26_GlitchData, + OutSignalName => "APUFCMRADATA(26)", + OutTemp => APUFCMRADATA_OUT(26), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(27), + GlitchData => APUFCMRADATA27_GlitchData, + OutSignalName => "APUFCMRADATA(27)", + OutTemp => APUFCMRADATA_OUT(27), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(28), + GlitchData => APUFCMRADATA28_GlitchData, + OutSignalName => "APUFCMRADATA(28)", + OutTemp => APUFCMRADATA_OUT(28), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(29), + GlitchData => APUFCMRADATA29_GlitchData, + OutSignalName => "APUFCMRADATA(29)", + OutTemp => APUFCMRADATA_OUT(29), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(30), + GlitchData => APUFCMRADATA30_GlitchData, + OutSignalName => "APUFCMRADATA(30)", + OutTemp => APUFCMRADATA_OUT(30), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(31), + GlitchData => APUFCMRADATA31_GlitchData, + OutSignalName => "APUFCMRADATA(31)", + OutTemp => APUFCMRADATA_OUT(31), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(0), + GlitchData => APUFCMRBDATA0_GlitchData, + OutSignalName => "APUFCMRBDATA(0)", + OutTemp => APUFCMRBDATA_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(1), + GlitchData => APUFCMRBDATA1_GlitchData, + OutSignalName => "APUFCMRBDATA(1)", + OutTemp => APUFCMRBDATA_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(2), + GlitchData => APUFCMRBDATA2_GlitchData, + OutSignalName => "APUFCMRBDATA(2)", + OutTemp => APUFCMRBDATA_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(3), + GlitchData => APUFCMRBDATA3_GlitchData, + OutSignalName => "APUFCMRBDATA(3)", + OutTemp => APUFCMRBDATA_OUT(3), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(4), + GlitchData => APUFCMRBDATA4_GlitchData, + OutSignalName => "APUFCMRBDATA(4)", + OutTemp => APUFCMRBDATA_OUT(4), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(5), + GlitchData => APUFCMRBDATA5_GlitchData, + OutSignalName => "APUFCMRBDATA(5)", + OutTemp => APUFCMRBDATA_OUT(5), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(6), + GlitchData => APUFCMRBDATA6_GlitchData, + OutSignalName => "APUFCMRBDATA(6)", + OutTemp => APUFCMRBDATA_OUT(6), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(7), + GlitchData => APUFCMRBDATA7_GlitchData, + OutSignalName => "APUFCMRBDATA(7)", + OutTemp => APUFCMRBDATA_OUT(7), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(8), + GlitchData => APUFCMRBDATA8_GlitchData, + OutSignalName => "APUFCMRBDATA(8)", + OutTemp => APUFCMRBDATA_OUT(8), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(9), + GlitchData => APUFCMRBDATA9_GlitchData, + OutSignalName => "APUFCMRBDATA(9)", + OutTemp => APUFCMRBDATA_OUT(9), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(10), + GlitchData => APUFCMRBDATA10_GlitchData, + OutSignalName => "APUFCMRBDATA(10)", + OutTemp => APUFCMRBDATA_OUT(10), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(11), + GlitchData => APUFCMRBDATA11_GlitchData, + OutSignalName => "APUFCMRBDATA(11)", + OutTemp => APUFCMRBDATA_OUT(11), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(12), + GlitchData => APUFCMRBDATA12_GlitchData, + OutSignalName => "APUFCMRBDATA(12)", + OutTemp => APUFCMRBDATA_OUT(12), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(13), + GlitchData => APUFCMRBDATA13_GlitchData, + OutSignalName => "APUFCMRBDATA(13)", + OutTemp => APUFCMRBDATA_OUT(13), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(14), + GlitchData => APUFCMRBDATA14_GlitchData, + OutSignalName => "APUFCMRBDATA(14)", + OutTemp => APUFCMRBDATA_OUT(14), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(15), + GlitchData => APUFCMRBDATA15_GlitchData, + OutSignalName => "APUFCMRBDATA(15)", + OutTemp => APUFCMRBDATA_OUT(15), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(16), + GlitchData => APUFCMRBDATA16_GlitchData, + OutSignalName => "APUFCMRBDATA(16)", + OutTemp => APUFCMRBDATA_OUT(16), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(17), + GlitchData => APUFCMRBDATA17_GlitchData, + OutSignalName => "APUFCMRBDATA(17)", + OutTemp => APUFCMRBDATA_OUT(17), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(18), + GlitchData => APUFCMRBDATA18_GlitchData, + OutSignalName => "APUFCMRBDATA(18)", + OutTemp => APUFCMRBDATA_OUT(18), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(19), + GlitchData => APUFCMRBDATA19_GlitchData, + OutSignalName => "APUFCMRBDATA(19)", + OutTemp => APUFCMRBDATA_OUT(19), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(20), + GlitchData => APUFCMRBDATA20_GlitchData, + OutSignalName => "APUFCMRBDATA(20)", + OutTemp => APUFCMRBDATA_OUT(20), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(21), + GlitchData => APUFCMRBDATA21_GlitchData, + OutSignalName => "APUFCMRBDATA(21)", + OutTemp => APUFCMRBDATA_OUT(21), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(22), + GlitchData => APUFCMRBDATA22_GlitchData, + OutSignalName => "APUFCMRBDATA(22)", + OutTemp => APUFCMRBDATA_OUT(22), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(23), + GlitchData => APUFCMRBDATA23_GlitchData, + OutSignalName => "APUFCMRBDATA(23)", + OutTemp => APUFCMRBDATA_OUT(23), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(24), + GlitchData => APUFCMRBDATA24_GlitchData, + OutSignalName => "APUFCMRBDATA(24)", + OutTemp => APUFCMRBDATA_OUT(24), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(25), + GlitchData => APUFCMRBDATA25_GlitchData, + OutSignalName => "APUFCMRBDATA(25)", + OutTemp => APUFCMRBDATA_OUT(25), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(26), + GlitchData => APUFCMRBDATA26_GlitchData, + OutSignalName => "APUFCMRBDATA(26)", + OutTemp => APUFCMRBDATA_OUT(26), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(27), + GlitchData => APUFCMRBDATA27_GlitchData, + OutSignalName => "APUFCMRBDATA(27)", + OutTemp => APUFCMRBDATA_OUT(27), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(28), + GlitchData => APUFCMRBDATA28_GlitchData, + OutSignalName => "APUFCMRBDATA(28)", + OutTemp => APUFCMRBDATA_OUT(28), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(29), + GlitchData => APUFCMRBDATA29_GlitchData, + OutSignalName => "APUFCMRBDATA(29)", + OutTemp => APUFCMRBDATA_OUT(29), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(30), + GlitchData => APUFCMRBDATA30_GlitchData, + OutSignalName => "APUFCMRBDATA(30)", + OutTemp => APUFCMRBDATA_OUT(30), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(31), + GlitchData => APUFCMRBDATA31_GlitchData, + OutSignalName => "APUFCMRBDATA(31)", + OutTemp => APUFCMRBDATA_OUT(31), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMWRITEBACKOK, + GlitchData => APUFCMWRITEBACKOK_GlitchData, + OutSignalName => "APUFCMWRITEBACKOK", + OutTemp => APUFCMWRITEBACKOK_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440CPMCORESLEEPREQ, + GlitchData => C440CPMCORESLEEPREQ_GlitchData, + OutSignalName => "C440CPMCORESLEEPREQ", + OutTemp => C440CPMCORESLEEPREQ_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440CPMDECIRPTREQ, + GlitchData => C440CPMDECIRPTREQ_GlitchData, + OutSignalName => "C440CPMDECIRPTREQ", + OutTemp => C440CPMDECIRPTREQ_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440CPMFITIRPTREQ, + GlitchData => C440CPMFITIRPTREQ_GlitchData, + OutSignalName => "C440CPMFITIRPTREQ", + OutTemp => C440CPMFITIRPTREQ_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440CPMMSRCE, + GlitchData => C440CPMMSRCE_GlitchData, + OutSignalName => "C440CPMMSRCE", + OutTemp => C440CPMMSRCE_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440CPMMSREE, + GlitchData => C440CPMMSREE_GlitchData, + OutSignalName => "C440CPMMSREE", + OutTemp => C440CPMMSREE_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440CPMTIMERRESETREQ, + GlitchData => C440CPMTIMERRESETREQ_GlitchData, + OutSignalName => "C440CPMTIMERRESETREQ", + OutTemp => C440CPMTIMERRESETREQ_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440CPMWDIRPTREQ, + GlitchData => C440CPMWDIRPTREQ_GlitchData, + OutSignalName => "C440CPMWDIRPTREQ", + OutTemp => C440CPMWDIRPTREQ_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440DBGSYSTEMCONTROL(0), + GlitchData => C440DBGSYSTEMCONTROL0_GlitchData, + OutSignalName => "C440DBGSYSTEMCONTROL(0)", + OutTemp => C440DBGSYSTEMCONTROL_OUT(0), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440DBGSYSTEMCONTROL(1), + GlitchData => C440DBGSYSTEMCONTROL1_GlitchData, + OutSignalName => "C440DBGSYSTEMCONTROL(1)", + OutTemp => C440DBGSYSTEMCONTROL_OUT(1), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440DBGSYSTEMCONTROL(2), + GlitchData => C440DBGSYSTEMCONTROL2_GlitchData, + OutSignalName => "C440DBGSYSTEMCONTROL(2)", + OutTemp => C440DBGSYSTEMCONTROL_OUT(2), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440DBGSYSTEMCONTROL(3), + GlitchData => C440DBGSYSTEMCONTROL3_GlitchData, + OutSignalName => "C440DBGSYSTEMCONTROL(3)", + OutTemp => C440DBGSYSTEMCONTROL_OUT(3), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440DBGSYSTEMCONTROL(4), + GlitchData => C440DBGSYSTEMCONTROL4_GlitchData, + OutSignalName => "C440DBGSYSTEMCONTROL(4)", + OutTemp => C440DBGSYSTEMCONTROL_OUT(4), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440DBGSYSTEMCONTROL(5), + GlitchData => C440DBGSYSTEMCONTROL5_GlitchData, + OutSignalName => "C440DBGSYSTEMCONTROL(5)", + OutTemp => C440DBGSYSTEMCONTROL_OUT(5), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440DBGSYSTEMCONTROL(6), + GlitchData => C440DBGSYSTEMCONTROL6_GlitchData, + OutSignalName => "C440DBGSYSTEMCONTROL(6)", + OutTemp => C440DBGSYSTEMCONTROL_OUT(6), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440DBGSYSTEMCONTROL(7), + GlitchData => C440DBGSYSTEMCONTROL7_GlitchData, + OutSignalName => "C440DBGSYSTEMCONTROL(7)", + OutTemp => C440DBGSYSTEMCONTROL_OUT(7), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440JTGTDO, + GlitchData => C440JTGTDO_GlitchData, + OutSignalName => "C440JTGTDO", + OutTemp => C440JTGTDO_OUT, + Paths => (0 => (JTGC440TCK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440JTGTDOEN, + GlitchData => C440JTGTDOEN_GlitchData, + OutSignalName => "C440JTGTDOEN", + OutTemp => C440JTGTDOEN_OUT, + Paths => (0 => (JTGC440TCK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440MACHINECHECK, + GlitchData => C440MACHINECHECK_GlitchData, + OutSignalName => "C440MACHINECHECK", + OutTemp => C440MACHINECHECK_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440RSTCHIPRESETREQ, + GlitchData => C440RSTCHIPRESETREQ_GlitchData, + OutSignalName => "C440RSTCHIPRESETREQ", + OutTemp => C440RSTCHIPRESETREQ_OUT, + Paths => (0 => (CPMINTERCONNECTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440RSTCORERESETREQ, + GlitchData => C440RSTCORERESETREQ_GlitchData, + OutSignalName => "C440RSTCORERESETREQ", + OutTemp => C440RSTCORERESETREQ_OUT, + Paths => (0 => (CPMINTERCONNECTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440RSTSYSTEMRESETREQ, + GlitchData => C440RSTSYSTEMRESETREQ_GlitchData, + OutSignalName => "C440RSTSYSTEMRESETREQ", + OutTemp => C440RSTSYSTEMRESETREQ_OUT, + Paths => (0 => (CPMINTERCONNECTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCBRANCHSTATUS(0), + GlitchData => C440TRCBRANCHSTATUS0_GlitchData, + OutSignalName => "C440TRCBRANCHSTATUS(0)", + OutTemp => C440TRCBRANCHSTATUS_OUT(0), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCBRANCHSTATUS(1), + GlitchData => C440TRCBRANCHSTATUS1_GlitchData, + OutSignalName => "C440TRCBRANCHSTATUS(1)", + OutTemp => C440TRCBRANCHSTATUS_OUT(1), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCBRANCHSTATUS(2), + GlitchData => C440TRCBRANCHSTATUS2_GlitchData, + OutSignalName => "C440TRCBRANCHSTATUS(2)", + OutTemp => C440TRCBRANCHSTATUS_OUT(2), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCCYCLE, + GlitchData => C440TRCCYCLE_GlitchData, + OutSignalName => "C440TRCCYCLE", + OutTemp => C440TRCCYCLE_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCEXECUTIONSTATUS(0), + GlitchData => C440TRCEXECUTIONSTATUS0_GlitchData, + OutSignalName => "C440TRCEXECUTIONSTATUS(0)", + OutTemp => C440TRCEXECUTIONSTATUS_OUT(0), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCEXECUTIONSTATUS(1), + GlitchData => C440TRCEXECUTIONSTATUS1_GlitchData, + OutSignalName => "C440TRCEXECUTIONSTATUS(1)", + OutTemp => C440TRCEXECUTIONSTATUS_OUT(1), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCEXECUTIONSTATUS(2), + GlitchData => C440TRCEXECUTIONSTATUS2_GlitchData, + OutSignalName => "C440TRCEXECUTIONSTATUS(2)", + OutTemp => C440TRCEXECUTIONSTATUS_OUT(2), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCEXECUTIONSTATUS(3), + GlitchData => C440TRCEXECUTIONSTATUS3_GlitchData, + OutSignalName => "C440TRCEXECUTIONSTATUS(3)", + OutTemp => C440TRCEXECUTIONSTATUS_OUT(3), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCEXECUTIONSTATUS(4), + GlitchData => C440TRCEXECUTIONSTATUS4_GlitchData, + OutSignalName => "C440TRCEXECUTIONSTATUS(4)", + OutTemp => C440TRCEXECUTIONSTATUS_OUT(4), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRACESTATUS(0), + GlitchData => C440TRCTRACESTATUS0_GlitchData, + OutSignalName => "C440TRCTRACESTATUS(0)", + OutTemp => C440TRCTRACESTATUS_OUT(0), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRACESTATUS(1), + GlitchData => C440TRCTRACESTATUS1_GlitchData, + OutSignalName => "C440TRCTRACESTATUS(1)", + OutTemp => C440TRCTRACESTATUS_OUT(1), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRACESTATUS(2), + GlitchData => C440TRCTRACESTATUS2_GlitchData, + OutSignalName => "C440TRCTRACESTATUS(2)", + OutTemp => C440TRCTRACESTATUS_OUT(2), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRACESTATUS(3), + GlitchData => C440TRCTRACESTATUS3_GlitchData, + OutSignalName => "C440TRCTRACESTATUS(3)", + OutTemp => C440TRCTRACESTATUS_OUT(3), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRACESTATUS(4), + GlitchData => C440TRCTRACESTATUS4_GlitchData, + OutSignalName => "C440TRCTRACESTATUS(4)", + OutTemp => C440TRCTRACESTATUS_OUT(4), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRACESTATUS(5), + GlitchData => C440TRCTRACESTATUS5_GlitchData, + OutSignalName => "C440TRCTRACESTATUS(5)", + OutTemp => C440TRCTRACESTATUS_OUT(5), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRACESTATUS(6), + GlitchData => C440TRCTRACESTATUS6_GlitchData, + OutSignalName => "C440TRCTRACESTATUS(6)", + OutTemp => C440TRCTRACESTATUS_OUT(6), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTOUT, + GlitchData => C440TRCTRIGGEREVENTOUT_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTOUT", + OutTemp => C440TRCTRIGGEREVENTOUT_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(0), + GlitchData => C440TRCTRIGGEREVENTTYPE0_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(0)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(0), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(1), + GlitchData => C440TRCTRIGGEREVENTTYPE1_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(1)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(1), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(2), + GlitchData => C440TRCTRIGGEREVENTTYPE2_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(2)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(2), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(3), + GlitchData => C440TRCTRIGGEREVENTTYPE3_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(3)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(3), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(4), + GlitchData => C440TRCTRIGGEREVENTTYPE4_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(4)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(4), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(5), + GlitchData => C440TRCTRIGGEREVENTTYPE5_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(5)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(5), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(6), + GlitchData => C440TRCTRIGGEREVENTTYPE6_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(6)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(6), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(7), + GlitchData => C440TRCTRIGGEREVENTTYPE7_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(7)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(7), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(8), + GlitchData => C440TRCTRIGGEREVENTTYPE8_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(8)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(8), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(9), + GlitchData => C440TRCTRIGGEREVENTTYPE9_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(9)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(9), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(10), + GlitchData => C440TRCTRIGGEREVENTTYPE10_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(10)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(10), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(11), + GlitchData => C440TRCTRIGGEREVENTTYPE11_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(11)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(11), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(12), + GlitchData => C440TRCTRIGGEREVENTTYPE12_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(12)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(12), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(13), + GlitchData => C440TRCTRIGGEREVENTTYPE13_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(13)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(13), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(0), + GlitchData => MIMCADDRESS0_GlitchData, + OutSignalName => "MIMCADDRESS(0)", + OutTemp => MIMCADDRESS_OUT(0), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(1), + GlitchData => MIMCADDRESS1_GlitchData, + OutSignalName => "MIMCADDRESS(1)", + OutTemp => MIMCADDRESS_OUT(1), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(2), + GlitchData => MIMCADDRESS2_GlitchData, + OutSignalName => "MIMCADDRESS(2)", + OutTemp => MIMCADDRESS_OUT(2), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(3), + GlitchData => MIMCADDRESS3_GlitchData, + OutSignalName => "MIMCADDRESS(3)", + OutTemp => MIMCADDRESS_OUT(3), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(4), + GlitchData => MIMCADDRESS4_GlitchData, + OutSignalName => "MIMCADDRESS(4)", + OutTemp => MIMCADDRESS_OUT(4), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(5), + GlitchData => MIMCADDRESS5_GlitchData, + OutSignalName => "MIMCADDRESS(5)", + OutTemp => MIMCADDRESS_OUT(5), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(6), + GlitchData => MIMCADDRESS6_GlitchData, + OutSignalName => "MIMCADDRESS(6)", + OutTemp => MIMCADDRESS_OUT(6), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(7), + GlitchData => MIMCADDRESS7_GlitchData, + OutSignalName => "MIMCADDRESS(7)", + OutTemp => MIMCADDRESS_OUT(7), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(8), + GlitchData => MIMCADDRESS8_GlitchData, + OutSignalName => "MIMCADDRESS(8)", + OutTemp => MIMCADDRESS_OUT(8), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(9), + GlitchData => MIMCADDRESS9_GlitchData, + OutSignalName => "MIMCADDRESS(9)", + OutTemp => MIMCADDRESS_OUT(9), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(10), + GlitchData => MIMCADDRESS10_GlitchData, + OutSignalName => "MIMCADDRESS(10)", + OutTemp => MIMCADDRESS_OUT(10), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(11), + GlitchData => MIMCADDRESS11_GlitchData, + OutSignalName => "MIMCADDRESS(11)", + OutTemp => MIMCADDRESS_OUT(11), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(12), + GlitchData => MIMCADDRESS12_GlitchData, + OutSignalName => "MIMCADDRESS(12)", + OutTemp => MIMCADDRESS_OUT(12), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(13), + GlitchData => MIMCADDRESS13_GlitchData, + OutSignalName => "MIMCADDRESS(13)", + OutTemp => MIMCADDRESS_OUT(13), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(14), + GlitchData => MIMCADDRESS14_GlitchData, + OutSignalName => "MIMCADDRESS(14)", + OutTemp => MIMCADDRESS_OUT(14), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(15), + GlitchData => MIMCADDRESS15_GlitchData, + OutSignalName => "MIMCADDRESS(15)", + OutTemp => MIMCADDRESS_OUT(15), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(16), + GlitchData => MIMCADDRESS16_GlitchData, + OutSignalName => "MIMCADDRESS(16)", + OutTemp => MIMCADDRESS_OUT(16), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(17), + GlitchData => MIMCADDRESS17_GlitchData, + OutSignalName => "MIMCADDRESS(17)", + OutTemp => MIMCADDRESS_OUT(17), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(18), + GlitchData => MIMCADDRESS18_GlitchData, + OutSignalName => "MIMCADDRESS(18)", + OutTemp => MIMCADDRESS_OUT(18), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(19), + GlitchData => MIMCADDRESS19_GlitchData, + OutSignalName => "MIMCADDRESS(19)", + OutTemp => MIMCADDRESS_OUT(19), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(20), + GlitchData => MIMCADDRESS20_GlitchData, + OutSignalName => "MIMCADDRESS(20)", + OutTemp => MIMCADDRESS_OUT(20), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(21), + GlitchData => MIMCADDRESS21_GlitchData, + OutSignalName => "MIMCADDRESS(21)", + OutTemp => MIMCADDRESS_OUT(21), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(22), + GlitchData => MIMCADDRESS22_GlitchData, + OutSignalName => "MIMCADDRESS(22)", + OutTemp => MIMCADDRESS_OUT(22), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(23), + GlitchData => MIMCADDRESS23_GlitchData, + OutSignalName => "MIMCADDRESS(23)", + OutTemp => MIMCADDRESS_OUT(23), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(24), + GlitchData => MIMCADDRESS24_GlitchData, + OutSignalName => "MIMCADDRESS(24)", + OutTemp => MIMCADDRESS_OUT(24), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(25), + GlitchData => MIMCADDRESS25_GlitchData, + OutSignalName => "MIMCADDRESS(25)", + OutTemp => MIMCADDRESS_OUT(25), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(26), + GlitchData => MIMCADDRESS26_GlitchData, + OutSignalName => "MIMCADDRESS(26)", + OutTemp => MIMCADDRESS_OUT(26), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(27), + GlitchData => MIMCADDRESS27_GlitchData, + OutSignalName => "MIMCADDRESS(27)", + OutTemp => MIMCADDRESS_OUT(27), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(28), + GlitchData => MIMCADDRESS28_GlitchData, + OutSignalName => "MIMCADDRESS(28)", + OutTemp => MIMCADDRESS_OUT(28), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(29), + GlitchData => MIMCADDRESS29_GlitchData, + OutSignalName => "MIMCADDRESS(29)", + OutTemp => MIMCADDRESS_OUT(29), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(30), + GlitchData => MIMCADDRESS30_GlitchData, + OutSignalName => "MIMCADDRESS(30)", + OutTemp => MIMCADDRESS_OUT(30), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(31), + GlitchData => MIMCADDRESS31_GlitchData, + OutSignalName => "MIMCADDRESS(31)", + OutTemp => MIMCADDRESS_OUT(31), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(32), + GlitchData => MIMCADDRESS32_GlitchData, + OutSignalName => "MIMCADDRESS(32)", + OutTemp => MIMCADDRESS_OUT(32), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(33), + GlitchData => MIMCADDRESS33_GlitchData, + OutSignalName => "MIMCADDRESS(33)", + OutTemp => MIMCADDRESS_OUT(33), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(34), + GlitchData => MIMCADDRESS34_GlitchData, + OutSignalName => "MIMCADDRESS(34)", + OutTemp => MIMCADDRESS_OUT(34), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(35), + GlitchData => MIMCADDRESS35_GlitchData, + OutSignalName => "MIMCADDRESS(35)", + OutTemp => MIMCADDRESS_OUT(35), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESSVALID, + GlitchData => MIMCADDRESSVALID_GlitchData, + OutSignalName => "MIMCADDRESSVALID", + OutTemp => MIMCADDRESSVALID_OUT, + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBANKCONFLICT, + GlitchData => MIMCBANKCONFLICT_GlitchData, + OutSignalName => "MIMCBANKCONFLICT", + OutTemp => MIMCBANKCONFLICT_OUT, + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(0), + GlitchData => MIMCBYTEENABLE0_GlitchData, + OutSignalName => "MIMCBYTEENABLE(0)", + OutTemp => MIMCBYTEENABLE_OUT(0), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(1), + GlitchData => MIMCBYTEENABLE1_GlitchData, + OutSignalName => "MIMCBYTEENABLE(1)", + OutTemp => MIMCBYTEENABLE_OUT(1), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(2), + GlitchData => MIMCBYTEENABLE2_GlitchData, + OutSignalName => "MIMCBYTEENABLE(2)", + OutTemp => MIMCBYTEENABLE_OUT(2), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(3), + GlitchData => MIMCBYTEENABLE3_GlitchData, + OutSignalName => "MIMCBYTEENABLE(3)", + OutTemp => MIMCBYTEENABLE_OUT(3), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(4), + GlitchData => MIMCBYTEENABLE4_GlitchData, + OutSignalName => "MIMCBYTEENABLE(4)", + OutTemp => MIMCBYTEENABLE_OUT(4), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(5), + GlitchData => MIMCBYTEENABLE5_GlitchData, + OutSignalName => "MIMCBYTEENABLE(5)", + OutTemp => MIMCBYTEENABLE_OUT(5), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(6), + GlitchData => MIMCBYTEENABLE6_GlitchData, + OutSignalName => "MIMCBYTEENABLE(6)", + OutTemp => MIMCBYTEENABLE_OUT(6), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(7), + GlitchData => MIMCBYTEENABLE7_GlitchData, + OutSignalName => "MIMCBYTEENABLE(7)", + OutTemp => MIMCBYTEENABLE_OUT(7), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(8), + GlitchData => MIMCBYTEENABLE8_GlitchData, + OutSignalName => "MIMCBYTEENABLE(8)", + OutTemp => MIMCBYTEENABLE_OUT(8), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(9), + GlitchData => MIMCBYTEENABLE9_GlitchData, + OutSignalName => "MIMCBYTEENABLE(9)", + OutTemp => MIMCBYTEENABLE_OUT(9), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(10), + GlitchData => MIMCBYTEENABLE10_GlitchData, + OutSignalName => "MIMCBYTEENABLE(10)", + OutTemp => MIMCBYTEENABLE_OUT(10), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(11), + GlitchData => MIMCBYTEENABLE11_GlitchData, + OutSignalName => "MIMCBYTEENABLE(11)", + OutTemp => MIMCBYTEENABLE_OUT(11), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(12), + GlitchData => MIMCBYTEENABLE12_GlitchData, + OutSignalName => "MIMCBYTEENABLE(12)", + OutTemp => MIMCBYTEENABLE_OUT(12), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(13), + GlitchData => MIMCBYTEENABLE13_GlitchData, + OutSignalName => "MIMCBYTEENABLE(13)", + OutTemp => MIMCBYTEENABLE_OUT(13), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(14), + GlitchData => MIMCBYTEENABLE14_GlitchData, + OutSignalName => "MIMCBYTEENABLE(14)", + OutTemp => MIMCBYTEENABLE_OUT(14), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(15), + GlitchData => MIMCBYTEENABLE15_GlitchData, + OutSignalName => "MIMCBYTEENABLE(15)", + OutTemp => MIMCBYTEENABLE_OUT(15), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCREADNOTWRITE, + GlitchData => MIMCREADNOTWRITE_GlitchData, + OutSignalName => "MIMCREADNOTWRITE", + OutTemp => MIMCREADNOTWRITE_OUT, + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCROWCONFLICT, + GlitchData => MIMCROWCONFLICT_GlitchData, + OutSignalName => "MIMCROWCONFLICT", + OutTemp => MIMCROWCONFLICT_OUT, + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(0), + GlitchData => MIMCWRITEDATA0_GlitchData, + OutSignalName => "MIMCWRITEDATA(0)", + OutTemp => MIMCWRITEDATA_OUT(0), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(1), + GlitchData => MIMCWRITEDATA1_GlitchData, + OutSignalName => "MIMCWRITEDATA(1)", + OutTemp => MIMCWRITEDATA_OUT(1), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(2), + GlitchData => MIMCWRITEDATA2_GlitchData, + OutSignalName => "MIMCWRITEDATA(2)", + OutTemp => MIMCWRITEDATA_OUT(2), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(3), + GlitchData => MIMCWRITEDATA3_GlitchData, + OutSignalName => "MIMCWRITEDATA(3)", + OutTemp => MIMCWRITEDATA_OUT(3), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(4), + GlitchData => MIMCWRITEDATA4_GlitchData, + OutSignalName => "MIMCWRITEDATA(4)", + OutTemp => MIMCWRITEDATA_OUT(4), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(5), + GlitchData => MIMCWRITEDATA5_GlitchData, + OutSignalName => "MIMCWRITEDATA(5)", + OutTemp => MIMCWRITEDATA_OUT(5), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(6), + GlitchData => MIMCWRITEDATA6_GlitchData, + OutSignalName => "MIMCWRITEDATA(6)", + OutTemp => MIMCWRITEDATA_OUT(6), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(7), + GlitchData => MIMCWRITEDATA7_GlitchData, + OutSignalName => "MIMCWRITEDATA(7)", + OutTemp => MIMCWRITEDATA_OUT(7), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(8), + GlitchData => MIMCWRITEDATA8_GlitchData, + OutSignalName => "MIMCWRITEDATA(8)", + OutTemp => MIMCWRITEDATA_OUT(8), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(9), + GlitchData => MIMCWRITEDATA9_GlitchData, + OutSignalName => "MIMCWRITEDATA(9)", + OutTemp => MIMCWRITEDATA_OUT(9), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(10), + GlitchData => MIMCWRITEDATA10_GlitchData, + OutSignalName => "MIMCWRITEDATA(10)", + OutTemp => MIMCWRITEDATA_OUT(10), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(11), + GlitchData => MIMCWRITEDATA11_GlitchData, + OutSignalName => "MIMCWRITEDATA(11)", + OutTemp => MIMCWRITEDATA_OUT(11), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(12), + GlitchData => MIMCWRITEDATA12_GlitchData, + OutSignalName => "MIMCWRITEDATA(12)", + OutTemp => MIMCWRITEDATA_OUT(12), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(13), + GlitchData => MIMCWRITEDATA13_GlitchData, + OutSignalName => "MIMCWRITEDATA(13)", + OutTemp => MIMCWRITEDATA_OUT(13), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(14), + GlitchData => MIMCWRITEDATA14_GlitchData, + OutSignalName => "MIMCWRITEDATA(14)", + OutTemp => MIMCWRITEDATA_OUT(14), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(15), + GlitchData => MIMCWRITEDATA15_GlitchData, + OutSignalName => "MIMCWRITEDATA(15)", + OutTemp => MIMCWRITEDATA_OUT(15), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(16), + GlitchData => MIMCWRITEDATA16_GlitchData, + OutSignalName => "MIMCWRITEDATA(16)", + OutTemp => MIMCWRITEDATA_OUT(16), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(17), + GlitchData => MIMCWRITEDATA17_GlitchData, + OutSignalName => "MIMCWRITEDATA(17)", + OutTemp => MIMCWRITEDATA_OUT(17), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(18), + GlitchData => MIMCWRITEDATA18_GlitchData, + OutSignalName => "MIMCWRITEDATA(18)", + OutTemp => MIMCWRITEDATA_OUT(18), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(19), + GlitchData => MIMCWRITEDATA19_GlitchData, + OutSignalName => "MIMCWRITEDATA(19)", + OutTemp => MIMCWRITEDATA_OUT(19), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(20), + GlitchData => MIMCWRITEDATA20_GlitchData, + OutSignalName => "MIMCWRITEDATA(20)", + OutTemp => MIMCWRITEDATA_OUT(20), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(21), + GlitchData => MIMCWRITEDATA21_GlitchData, + OutSignalName => "MIMCWRITEDATA(21)", + OutTemp => MIMCWRITEDATA_OUT(21), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(22), + GlitchData => MIMCWRITEDATA22_GlitchData, + OutSignalName => "MIMCWRITEDATA(22)", + OutTemp => MIMCWRITEDATA_OUT(22), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(23), + GlitchData => MIMCWRITEDATA23_GlitchData, + OutSignalName => "MIMCWRITEDATA(23)", + OutTemp => MIMCWRITEDATA_OUT(23), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(24), + GlitchData => MIMCWRITEDATA24_GlitchData, + OutSignalName => "MIMCWRITEDATA(24)", + OutTemp => MIMCWRITEDATA_OUT(24), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(25), + GlitchData => MIMCWRITEDATA25_GlitchData, + OutSignalName => "MIMCWRITEDATA(25)", + OutTemp => MIMCWRITEDATA_OUT(25), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(26), + GlitchData => MIMCWRITEDATA26_GlitchData, + OutSignalName => "MIMCWRITEDATA(26)", + OutTemp => MIMCWRITEDATA_OUT(26), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(27), + GlitchData => MIMCWRITEDATA27_GlitchData, + OutSignalName => "MIMCWRITEDATA(27)", + OutTemp => MIMCWRITEDATA_OUT(27), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(28), + GlitchData => MIMCWRITEDATA28_GlitchData, + OutSignalName => "MIMCWRITEDATA(28)", + OutTemp => MIMCWRITEDATA_OUT(28), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(29), + GlitchData => MIMCWRITEDATA29_GlitchData, + OutSignalName => "MIMCWRITEDATA(29)", + OutTemp => MIMCWRITEDATA_OUT(29), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(30), + GlitchData => MIMCWRITEDATA30_GlitchData, + OutSignalName => "MIMCWRITEDATA(30)", + OutTemp => MIMCWRITEDATA_OUT(30), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(31), + GlitchData => MIMCWRITEDATA31_GlitchData, + OutSignalName => "MIMCWRITEDATA(31)", + OutTemp => MIMCWRITEDATA_OUT(31), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(32), + GlitchData => MIMCWRITEDATA32_GlitchData, + OutSignalName => "MIMCWRITEDATA(32)", + OutTemp => MIMCWRITEDATA_OUT(32), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(33), + GlitchData => MIMCWRITEDATA33_GlitchData, + OutSignalName => "MIMCWRITEDATA(33)", + OutTemp => MIMCWRITEDATA_OUT(33), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(34), + GlitchData => MIMCWRITEDATA34_GlitchData, + OutSignalName => "MIMCWRITEDATA(34)", + OutTemp => MIMCWRITEDATA_OUT(34), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(35), + GlitchData => MIMCWRITEDATA35_GlitchData, + OutSignalName => "MIMCWRITEDATA(35)", + OutTemp => MIMCWRITEDATA_OUT(35), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(36), + GlitchData => MIMCWRITEDATA36_GlitchData, + OutSignalName => "MIMCWRITEDATA(36)", + OutTemp => MIMCWRITEDATA_OUT(36), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(37), + GlitchData => MIMCWRITEDATA37_GlitchData, + OutSignalName => "MIMCWRITEDATA(37)", + OutTemp => MIMCWRITEDATA_OUT(37), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(38), + GlitchData => MIMCWRITEDATA38_GlitchData, + OutSignalName => "MIMCWRITEDATA(38)", + OutTemp => MIMCWRITEDATA_OUT(38), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(39), + GlitchData => MIMCWRITEDATA39_GlitchData, + OutSignalName => "MIMCWRITEDATA(39)", + OutTemp => MIMCWRITEDATA_OUT(39), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(40), + GlitchData => MIMCWRITEDATA40_GlitchData, + OutSignalName => "MIMCWRITEDATA(40)", + OutTemp => MIMCWRITEDATA_OUT(40), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(41), + GlitchData => MIMCWRITEDATA41_GlitchData, + OutSignalName => "MIMCWRITEDATA(41)", + OutTemp => MIMCWRITEDATA_OUT(41), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(42), + GlitchData => MIMCWRITEDATA42_GlitchData, + OutSignalName => "MIMCWRITEDATA(42)", + OutTemp => MIMCWRITEDATA_OUT(42), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(43), + GlitchData => MIMCWRITEDATA43_GlitchData, + OutSignalName => "MIMCWRITEDATA(43)", + OutTemp => MIMCWRITEDATA_OUT(43), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(44), + GlitchData => MIMCWRITEDATA44_GlitchData, + OutSignalName => "MIMCWRITEDATA(44)", + OutTemp => MIMCWRITEDATA_OUT(44), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(45), + GlitchData => MIMCWRITEDATA45_GlitchData, + OutSignalName => "MIMCWRITEDATA(45)", + OutTemp => MIMCWRITEDATA_OUT(45), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(46), + GlitchData => MIMCWRITEDATA46_GlitchData, + OutSignalName => "MIMCWRITEDATA(46)", + OutTemp => MIMCWRITEDATA_OUT(46), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(47), + GlitchData => MIMCWRITEDATA47_GlitchData, + OutSignalName => "MIMCWRITEDATA(47)", + OutTemp => MIMCWRITEDATA_OUT(47), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(48), + GlitchData => MIMCWRITEDATA48_GlitchData, + OutSignalName => "MIMCWRITEDATA(48)", + OutTemp => MIMCWRITEDATA_OUT(48), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(49), + GlitchData => MIMCWRITEDATA49_GlitchData, + OutSignalName => "MIMCWRITEDATA(49)", + OutTemp => MIMCWRITEDATA_OUT(49), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(50), + GlitchData => MIMCWRITEDATA50_GlitchData, + OutSignalName => "MIMCWRITEDATA(50)", + OutTemp => MIMCWRITEDATA_OUT(50), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(51), + GlitchData => MIMCWRITEDATA51_GlitchData, + OutSignalName => "MIMCWRITEDATA(51)", + OutTemp => MIMCWRITEDATA_OUT(51), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(52), + GlitchData => MIMCWRITEDATA52_GlitchData, + OutSignalName => "MIMCWRITEDATA(52)", + OutTemp => MIMCWRITEDATA_OUT(52), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(53), + GlitchData => MIMCWRITEDATA53_GlitchData, + OutSignalName => "MIMCWRITEDATA(53)", + OutTemp => MIMCWRITEDATA_OUT(53), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(54), + GlitchData => MIMCWRITEDATA54_GlitchData, + OutSignalName => "MIMCWRITEDATA(54)", + OutTemp => MIMCWRITEDATA_OUT(54), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(55), + GlitchData => MIMCWRITEDATA55_GlitchData, + OutSignalName => "MIMCWRITEDATA(55)", + OutTemp => MIMCWRITEDATA_OUT(55), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(56), + GlitchData => MIMCWRITEDATA56_GlitchData, + OutSignalName => "MIMCWRITEDATA(56)", + OutTemp => MIMCWRITEDATA_OUT(56), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(57), + GlitchData => MIMCWRITEDATA57_GlitchData, + OutSignalName => "MIMCWRITEDATA(57)", + OutTemp => MIMCWRITEDATA_OUT(57), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(58), + GlitchData => MIMCWRITEDATA58_GlitchData, + OutSignalName => "MIMCWRITEDATA(58)", + OutTemp => MIMCWRITEDATA_OUT(58), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(59), + GlitchData => MIMCWRITEDATA59_GlitchData, + OutSignalName => "MIMCWRITEDATA(59)", + OutTemp => MIMCWRITEDATA_OUT(59), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(60), + GlitchData => MIMCWRITEDATA60_GlitchData, + OutSignalName => "MIMCWRITEDATA(60)", + OutTemp => MIMCWRITEDATA_OUT(60), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(61), + GlitchData => MIMCWRITEDATA61_GlitchData, + OutSignalName => "MIMCWRITEDATA(61)", + OutTemp => MIMCWRITEDATA_OUT(61), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(62), + GlitchData => MIMCWRITEDATA62_GlitchData, + OutSignalName => "MIMCWRITEDATA(62)", + OutTemp => MIMCWRITEDATA_OUT(62), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(63), + GlitchData => MIMCWRITEDATA63_GlitchData, + OutSignalName => "MIMCWRITEDATA(63)", + OutTemp => MIMCWRITEDATA_OUT(63), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(64), + GlitchData => MIMCWRITEDATA64_GlitchData, + OutSignalName => "MIMCWRITEDATA(64)", + OutTemp => MIMCWRITEDATA_OUT(64), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(65), + GlitchData => MIMCWRITEDATA65_GlitchData, + OutSignalName => "MIMCWRITEDATA(65)", + OutTemp => MIMCWRITEDATA_OUT(65), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(66), + GlitchData => MIMCWRITEDATA66_GlitchData, + OutSignalName => "MIMCWRITEDATA(66)", + OutTemp => MIMCWRITEDATA_OUT(66), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(67), + GlitchData => MIMCWRITEDATA67_GlitchData, + OutSignalName => "MIMCWRITEDATA(67)", + OutTemp => MIMCWRITEDATA_OUT(67), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(68), + GlitchData => MIMCWRITEDATA68_GlitchData, + OutSignalName => "MIMCWRITEDATA(68)", + OutTemp => MIMCWRITEDATA_OUT(68), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(69), + GlitchData => MIMCWRITEDATA69_GlitchData, + OutSignalName => "MIMCWRITEDATA(69)", + OutTemp => MIMCWRITEDATA_OUT(69), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(70), + GlitchData => MIMCWRITEDATA70_GlitchData, + OutSignalName => "MIMCWRITEDATA(70)", + OutTemp => MIMCWRITEDATA_OUT(70), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(71), + GlitchData => MIMCWRITEDATA71_GlitchData, + OutSignalName => "MIMCWRITEDATA(71)", + OutTemp => MIMCWRITEDATA_OUT(71), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(72), + GlitchData => MIMCWRITEDATA72_GlitchData, + OutSignalName => "MIMCWRITEDATA(72)", + OutTemp => MIMCWRITEDATA_OUT(72), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(73), + GlitchData => MIMCWRITEDATA73_GlitchData, + OutSignalName => "MIMCWRITEDATA(73)", + OutTemp => MIMCWRITEDATA_OUT(73), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(74), + GlitchData => MIMCWRITEDATA74_GlitchData, + OutSignalName => "MIMCWRITEDATA(74)", + OutTemp => MIMCWRITEDATA_OUT(74), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(75), + GlitchData => MIMCWRITEDATA75_GlitchData, + OutSignalName => "MIMCWRITEDATA(75)", + OutTemp => MIMCWRITEDATA_OUT(75), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(76), + GlitchData => MIMCWRITEDATA76_GlitchData, + OutSignalName => "MIMCWRITEDATA(76)", + OutTemp => MIMCWRITEDATA_OUT(76), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(77), + GlitchData => MIMCWRITEDATA77_GlitchData, + OutSignalName => "MIMCWRITEDATA(77)", + OutTemp => MIMCWRITEDATA_OUT(77), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(78), + GlitchData => MIMCWRITEDATA78_GlitchData, + OutSignalName => "MIMCWRITEDATA(78)", + OutTemp => MIMCWRITEDATA_OUT(78), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(79), + GlitchData => MIMCWRITEDATA79_GlitchData, + OutSignalName => "MIMCWRITEDATA(79)", + OutTemp => MIMCWRITEDATA_OUT(79), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(80), + GlitchData => MIMCWRITEDATA80_GlitchData, + OutSignalName => "MIMCWRITEDATA(80)", + OutTemp => MIMCWRITEDATA_OUT(80), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(81), + GlitchData => MIMCWRITEDATA81_GlitchData, + OutSignalName => "MIMCWRITEDATA(81)", + OutTemp => MIMCWRITEDATA_OUT(81), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(82), + GlitchData => MIMCWRITEDATA82_GlitchData, + OutSignalName => "MIMCWRITEDATA(82)", + OutTemp => MIMCWRITEDATA_OUT(82), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(83), + GlitchData => MIMCWRITEDATA83_GlitchData, + OutSignalName => "MIMCWRITEDATA(83)", + OutTemp => MIMCWRITEDATA_OUT(83), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(84), + GlitchData => MIMCWRITEDATA84_GlitchData, + OutSignalName => "MIMCWRITEDATA(84)", + OutTemp => MIMCWRITEDATA_OUT(84), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(85), + GlitchData => MIMCWRITEDATA85_GlitchData, + OutSignalName => "MIMCWRITEDATA(85)", + OutTemp => MIMCWRITEDATA_OUT(85), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(86), + GlitchData => MIMCWRITEDATA86_GlitchData, + OutSignalName => "MIMCWRITEDATA(86)", + OutTemp => MIMCWRITEDATA_OUT(86), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(87), + GlitchData => MIMCWRITEDATA87_GlitchData, + OutSignalName => "MIMCWRITEDATA(87)", + OutTemp => MIMCWRITEDATA_OUT(87), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(88), + GlitchData => MIMCWRITEDATA88_GlitchData, + OutSignalName => "MIMCWRITEDATA(88)", + OutTemp => MIMCWRITEDATA_OUT(88), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(89), + GlitchData => MIMCWRITEDATA89_GlitchData, + OutSignalName => "MIMCWRITEDATA(89)", + OutTemp => MIMCWRITEDATA_OUT(89), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(90), + GlitchData => MIMCWRITEDATA90_GlitchData, + OutSignalName => "MIMCWRITEDATA(90)", + OutTemp => MIMCWRITEDATA_OUT(90), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(91), + GlitchData => MIMCWRITEDATA91_GlitchData, + OutSignalName => "MIMCWRITEDATA(91)", + OutTemp => MIMCWRITEDATA_OUT(91), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(92), + GlitchData => MIMCWRITEDATA92_GlitchData, + OutSignalName => "MIMCWRITEDATA(92)", + OutTemp => MIMCWRITEDATA_OUT(92), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(93), + GlitchData => MIMCWRITEDATA93_GlitchData, + OutSignalName => "MIMCWRITEDATA(93)", + OutTemp => MIMCWRITEDATA_OUT(93), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(94), + GlitchData => MIMCWRITEDATA94_GlitchData, + OutSignalName => "MIMCWRITEDATA(94)", + OutTemp => MIMCWRITEDATA_OUT(94), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(95), + GlitchData => MIMCWRITEDATA95_GlitchData, + OutSignalName => "MIMCWRITEDATA(95)", + OutTemp => MIMCWRITEDATA_OUT(95), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(96), + GlitchData => MIMCWRITEDATA96_GlitchData, + OutSignalName => "MIMCWRITEDATA(96)", + OutTemp => MIMCWRITEDATA_OUT(96), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(97), + GlitchData => MIMCWRITEDATA97_GlitchData, + OutSignalName => "MIMCWRITEDATA(97)", + OutTemp => MIMCWRITEDATA_OUT(97), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(98), + GlitchData => MIMCWRITEDATA98_GlitchData, + OutSignalName => "MIMCWRITEDATA(98)", + OutTemp => MIMCWRITEDATA_OUT(98), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(99), + GlitchData => MIMCWRITEDATA99_GlitchData, + OutSignalName => "MIMCWRITEDATA(99)", + OutTemp => MIMCWRITEDATA_OUT(99), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(100), + GlitchData => MIMCWRITEDATA100_GlitchData, + OutSignalName => "MIMCWRITEDATA(100)", + OutTemp => MIMCWRITEDATA_OUT(100), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(101), + GlitchData => MIMCWRITEDATA101_GlitchData, + OutSignalName => "MIMCWRITEDATA(101)", + OutTemp => MIMCWRITEDATA_OUT(101), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(102), + GlitchData => MIMCWRITEDATA102_GlitchData, + OutSignalName => "MIMCWRITEDATA(102)", + OutTemp => MIMCWRITEDATA_OUT(102), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(103), + GlitchData => MIMCWRITEDATA103_GlitchData, + OutSignalName => "MIMCWRITEDATA(103)", + OutTemp => MIMCWRITEDATA_OUT(103), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(104), + GlitchData => MIMCWRITEDATA104_GlitchData, + OutSignalName => "MIMCWRITEDATA(104)", + OutTemp => MIMCWRITEDATA_OUT(104), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(105), + GlitchData => MIMCWRITEDATA105_GlitchData, + OutSignalName => "MIMCWRITEDATA(105)", + OutTemp => MIMCWRITEDATA_OUT(105), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(106), + GlitchData => MIMCWRITEDATA106_GlitchData, + OutSignalName => "MIMCWRITEDATA(106)", + OutTemp => MIMCWRITEDATA_OUT(106), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(107), + GlitchData => MIMCWRITEDATA107_GlitchData, + OutSignalName => "MIMCWRITEDATA(107)", + OutTemp => MIMCWRITEDATA_OUT(107), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(108), + GlitchData => MIMCWRITEDATA108_GlitchData, + OutSignalName => "MIMCWRITEDATA(108)", + OutTemp => MIMCWRITEDATA_OUT(108), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(109), + GlitchData => MIMCWRITEDATA109_GlitchData, + OutSignalName => "MIMCWRITEDATA(109)", + OutTemp => MIMCWRITEDATA_OUT(109), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(110), + GlitchData => MIMCWRITEDATA110_GlitchData, + OutSignalName => "MIMCWRITEDATA(110)", + OutTemp => MIMCWRITEDATA_OUT(110), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(111), + GlitchData => MIMCWRITEDATA111_GlitchData, + OutSignalName => "MIMCWRITEDATA(111)", + OutTemp => MIMCWRITEDATA_OUT(111), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(112), + GlitchData => MIMCWRITEDATA112_GlitchData, + OutSignalName => "MIMCWRITEDATA(112)", + OutTemp => MIMCWRITEDATA_OUT(112), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(113), + GlitchData => MIMCWRITEDATA113_GlitchData, + OutSignalName => "MIMCWRITEDATA(113)", + OutTemp => MIMCWRITEDATA_OUT(113), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(114), + GlitchData => MIMCWRITEDATA114_GlitchData, + OutSignalName => "MIMCWRITEDATA(114)", + OutTemp => MIMCWRITEDATA_OUT(114), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(115), + GlitchData => MIMCWRITEDATA115_GlitchData, + OutSignalName => "MIMCWRITEDATA(115)", + OutTemp => MIMCWRITEDATA_OUT(115), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(116), + GlitchData => MIMCWRITEDATA116_GlitchData, + OutSignalName => "MIMCWRITEDATA(116)", + OutTemp => MIMCWRITEDATA_OUT(116), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(117), + GlitchData => MIMCWRITEDATA117_GlitchData, + OutSignalName => "MIMCWRITEDATA(117)", + OutTemp => MIMCWRITEDATA_OUT(117), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(118), + GlitchData => MIMCWRITEDATA118_GlitchData, + OutSignalName => "MIMCWRITEDATA(118)", + OutTemp => MIMCWRITEDATA_OUT(118), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(119), + GlitchData => MIMCWRITEDATA119_GlitchData, + OutSignalName => "MIMCWRITEDATA(119)", + OutTemp => MIMCWRITEDATA_OUT(119), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(120), + GlitchData => MIMCWRITEDATA120_GlitchData, + OutSignalName => "MIMCWRITEDATA(120)", + OutTemp => MIMCWRITEDATA_OUT(120), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(121), + GlitchData => MIMCWRITEDATA121_GlitchData, + OutSignalName => "MIMCWRITEDATA(121)", + OutTemp => MIMCWRITEDATA_OUT(121), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(122), + GlitchData => MIMCWRITEDATA122_GlitchData, + OutSignalName => "MIMCWRITEDATA(122)", + OutTemp => MIMCWRITEDATA_OUT(122), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(123), + GlitchData => MIMCWRITEDATA123_GlitchData, + OutSignalName => "MIMCWRITEDATA(123)", + OutTemp => MIMCWRITEDATA_OUT(123), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(124), + GlitchData => MIMCWRITEDATA124_GlitchData, + OutSignalName => "MIMCWRITEDATA(124)", + OutTemp => MIMCWRITEDATA_OUT(124), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(125), + GlitchData => MIMCWRITEDATA125_GlitchData, + OutSignalName => "MIMCWRITEDATA(125)", + OutTemp => MIMCWRITEDATA_OUT(125), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(126), + GlitchData => MIMCWRITEDATA126_GlitchData, + OutSignalName => "MIMCWRITEDATA(126)", + OutTemp => MIMCWRITEDATA_OUT(126), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(127), + GlitchData => MIMCWRITEDATA127_GlitchData, + OutSignalName => "MIMCWRITEDATA(127)", + OutTemp => MIMCWRITEDATA_OUT(127), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATAVALID, + GlitchData => MIMCWRITEDATAVALID_GlitchData, + OutSignalName => "MIMCWRITEDATAVALID", + OutTemp => MIMCWRITEDATAVALID_OUT, + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCCPMINTERCONNECTBUSY, + GlitchData => PPCCPMINTERCONNECTBUSY_GlitchData, + OutSignalName => "PPCCPMINTERCONNECTBUSY", + OutTemp => PPCCPMINTERCONNECTBUSY_OUT, + Paths => (0 => (CPMINTERCONNECTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRACK, + GlitchData => PPCDSDCRACK_GlitchData, + OutSignalName => "PPCDSDCRACK", + OutTemp => PPCDSDCRACK_OUT, + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRTIMEOUTWAIT, + GlitchData => PPCDSDCRTIMEOUTWAIT_GlitchData, + OutSignalName => "PPCDSDCRTIMEOUTWAIT", + OutTemp => PPCDSDCRTIMEOUTWAIT_OUT, + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(0), + GlitchData => PPCDSDCRDBUSIN0_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(0)", + OutTemp => PPCDSDCRDBUSIN_OUT(0), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(1), + GlitchData => PPCDSDCRDBUSIN1_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(1)", + OutTemp => PPCDSDCRDBUSIN_OUT(1), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(2), + GlitchData => PPCDSDCRDBUSIN2_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(2)", + OutTemp => PPCDSDCRDBUSIN_OUT(2), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(3), + GlitchData => PPCDSDCRDBUSIN3_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(3)", + OutTemp => PPCDSDCRDBUSIN_OUT(3), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(4), + GlitchData => PPCDSDCRDBUSIN4_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(4)", + OutTemp => PPCDSDCRDBUSIN_OUT(4), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(5), + GlitchData => PPCDSDCRDBUSIN5_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(5)", + OutTemp => PPCDSDCRDBUSIN_OUT(5), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(6), + GlitchData => PPCDSDCRDBUSIN6_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(6)", + OutTemp => PPCDSDCRDBUSIN_OUT(6), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(7), + GlitchData => PPCDSDCRDBUSIN7_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(7)", + OutTemp => PPCDSDCRDBUSIN_OUT(7), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(8), + GlitchData => PPCDSDCRDBUSIN8_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(8)", + OutTemp => PPCDSDCRDBUSIN_OUT(8), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(9), + GlitchData => PPCDSDCRDBUSIN9_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(9)", + OutTemp => PPCDSDCRDBUSIN_OUT(9), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(10), + GlitchData => PPCDSDCRDBUSIN10_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(10)", + OutTemp => PPCDSDCRDBUSIN_OUT(10), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(11), + GlitchData => PPCDSDCRDBUSIN11_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(11)", + OutTemp => PPCDSDCRDBUSIN_OUT(11), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(12), + GlitchData => PPCDSDCRDBUSIN12_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(12)", + OutTemp => PPCDSDCRDBUSIN_OUT(12), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(13), + GlitchData => PPCDSDCRDBUSIN13_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(13)", + OutTemp => PPCDSDCRDBUSIN_OUT(13), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(14), + GlitchData => PPCDSDCRDBUSIN14_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(14)", + OutTemp => PPCDSDCRDBUSIN_OUT(14), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(15), + GlitchData => PPCDSDCRDBUSIN15_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(15)", + OutTemp => PPCDSDCRDBUSIN_OUT(15), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(16), + GlitchData => PPCDSDCRDBUSIN16_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(16)", + OutTemp => PPCDSDCRDBUSIN_OUT(16), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(17), + GlitchData => PPCDSDCRDBUSIN17_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(17)", + OutTemp => PPCDSDCRDBUSIN_OUT(17), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(18), + GlitchData => PPCDSDCRDBUSIN18_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(18)", + OutTemp => PPCDSDCRDBUSIN_OUT(18), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(19), + GlitchData => PPCDSDCRDBUSIN19_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(19)", + OutTemp => PPCDSDCRDBUSIN_OUT(19), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(20), + GlitchData => PPCDSDCRDBUSIN20_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(20)", + OutTemp => PPCDSDCRDBUSIN_OUT(20), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(21), + GlitchData => PPCDSDCRDBUSIN21_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(21)", + OutTemp => PPCDSDCRDBUSIN_OUT(21), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(22), + GlitchData => PPCDSDCRDBUSIN22_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(22)", + OutTemp => PPCDSDCRDBUSIN_OUT(22), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(23), + GlitchData => PPCDSDCRDBUSIN23_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(23)", + OutTemp => PPCDSDCRDBUSIN_OUT(23), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(24), + GlitchData => PPCDSDCRDBUSIN24_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(24)", + OutTemp => PPCDSDCRDBUSIN_OUT(24), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(25), + GlitchData => PPCDSDCRDBUSIN25_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(25)", + OutTemp => PPCDSDCRDBUSIN_OUT(25), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(26), + GlitchData => PPCDSDCRDBUSIN26_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(26)", + OutTemp => PPCDSDCRDBUSIN_OUT(26), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(27), + GlitchData => PPCDSDCRDBUSIN27_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(27)", + OutTemp => PPCDSDCRDBUSIN_OUT(27), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(28), + GlitchData => PPCDSDCRDBUSIN28_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(28)", + OutTemp => PPCDSDCRDBUSIN_OUT(28), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(29), + GlitchData => PPCDSDCRDBUSIN29_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(29)", + OutTemp => PPCDSDCRDBUSIN_OUT(29), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(30), + GlitchData => PPCDSDCRDBUSIN30_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(30)", + OutTemp => PPCDSDCRDBUSIN_OUT(30), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(31), + GlitchData => PPCDSDCRDBUSIN31_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(31)", + OutTemp => PPCDSDCRDBUSIN_OUT(31), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCEICINTERCONNECTIRQ, + GlitchData => PPCEICINTERCONNECTIRQ_GlitchData, + OutSignalName => "PPCEICINTERCONNECTIRQ", + OutTemp => PPCEICINTERCONNECTIRQ_OUT, + Paths => (0 => (CPMINTERCONNECTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + + wait on + APUFCMDECFPUOP_out, + APUFCMDECLDSTXFERSIZE_out, + APUFCMDECLOAD_out, + APUFCMDECNONAUTON_out, + APUFCMDECSTORE_out, + APUFCMDECUDIVALID_out, + APUFCMDECUDI_out, + APUFCMENDIAN_out, + APUFCMFLUSH_out, + APUFCMINSTRUCTION_out, + APUFCMINSTRVALID_out, + APUFCMLOADBYTEADDR_out, + APUFCMLOADDATA_out, + APUFCMLOADDVALID_out, + APUFCMMSRFE0_out, + APUFCMMSRFE1_out, + APUFCMNEXTINSTRREADY_out, + APUFCMOPERANDVALID_out, + APUFCMRADATA_out, + APUFCMRBDATA_out, + APUFCMWRITEBACKOK_out, + C440CPMCORESLEEPREQ_out, + C440CPMDECIRPTREQ_out, + C440CPMFITIRPTREQ_out, + C440CPMMSRCE_out, + C440CPMMSREE_out, + C440CPMTIMERRESETREQ_out, + C440CPMWDIRPTREQ_out, + C440DBGSYSTEMCONTROL_out, + C440JTGTDOEN_out, + C440JTGTDO_out, + C440MACHINECHECK_out, + C440RSTCHIPRESETREQ_out, + C440RSTCORERESETREQ_out, + C440RSTSYSTEMRESETREQ_out, + C440TRCBRANCHSTATUS_out, + C440TRCCYCLE_out, + C440TRCEXECUTIONSTATUS_out, + C440TRCTRACESTATUS_out, + C440TRCTRIGGEREVENTOUT_out, + C440TRCTRIGGEREVENTTYPE_out, + DMA0LLRSTENGINEACK_out, + DMA0LLRXDSTRDYN_out, + DMA0LLTXD_out, + DMA0LLTXEOFN_out, + DMA0LLTXEOPN_out, + DMA0LLTXREM_out, + DMA0LLTXSOFN_out, + DMA0LLTXSOPN_out, + DMA0LLTXSRCRDYN_out, + DMA0RXIRQ_out, + DMA0TXIRQ_out, + DMA1LLRSTENGINEACK_out, + DMA1LLRXDSTRDYN_out, + DMA1LLTXD_out, + DMA1LLTXEOFN_out, + DMA1LLTXEOPN_out, + DMA1LLTXREM_out, + DMA1LLTXSOFN_out, + DMA1LLTXSOPN_out, + DMA1LLTXSRCRDYN_out, + DMA1RXIRQ_out, + DMA1TXIRQ_out, + DMA2LLRSTENGINEACK_out, + DMA2LLRXDSTRDYN_out, + DMA2LLTXD_out, + DMA2LLTXEOFN_out, + DMA2LLTXEOPN_out, + DMA2LLTXREM_out, + DMA2LLTXSOFN_out, + DMA2LLTXSOPN_out, + DMA2LLTXSRCRDYN_out, + DMA2RXIRQ_out, + DMA2TXIRQ_out, + DMA3LLRSTENGINEACK_out, + DMA3LLRXDSTRDYN_out, + DMA3LLTXD_out, + DMA3LLTXEOFN_out, + DMA3LLTXEOPN_out, + DMA3LLTXREM_out, + DMA3LLTXSOFN_out, + DMA3LLTXSOPN_out, + DMA3LLTXSRCRDYN_out, + DMA3RXIRQ_out, + DMA3TXIRQ_out, + MIMCADDRESSVALID_out, + MIMCADDRESS_out, + MIMCBANKCONFLICT_out, + MIMCBYTEENABLE_out, + MIMCREADNOTWRITE_out, + MIMCROWCONFLICT_out, + MIMCWRITEDATAVALID_out, + MIMCWRITEDATA_out, + PPCCPMINTERCONNECTBUSY_out, + PPCDMDCRABUS_out, + PPCDMDCRDBUSOUT_out, + PPCDMDCRREAD_out, + PPCDMDCRUABUS_out, + PPCDMDCRWRITE_out, + PPCDSDCRACK_out, + PPCDSDCRDBUSIN_out, + PPCDSDCRTIMEOUTWAIT_out, + PPCEICINTERCONNECTIRQ_out, + PPCMPLBABORT_out, + PPCMPLBABUS_out, + PPCMPLBBE_out, + PPCMPLBBUSLOCK_out, + PPCMPLBLOCKERR_out, + PPCMPLBPRIORITY_out, + PPCMPLBRDBURST_out, + PPCMPLBREQUEST_out, + PPCMPLBRNW_out, + PPCMPLBSIZE_out, + PPCMPLBTATTRIBUTE_out, + PPCMPLBTYPE_out, + PPCMPLBUABUS_out, + PPCMPLBWRBURST_out, + PPCMPLBWRDBUS_out, + PPCS0PLBADDRACK_out, + PPCS0PLBMBUSY_out, + PPCS0PLBMIRQ_out, + PPCS0PLBMRDERR_out, + PPCS0PLBMWRERR_out, + PPCS0PLBRDBTERM_out, + PPCS0PLBRDCOMP_out, + PPCS0PLBRDDACK_out, + PPCS0PLBRDDBUS_out, + PPCS0PLBRDWDADDR_out, + PPCS0PLBREARBITRATE_out, + PPCS0PLBSSIZE_out, + PPCS0PLBWAIT_out, + PPCS0PLBWRBTERM_out, + PPCS0PLBWRCOMP_out, + PPCS0PLBWRDACK_out, + PPCS1PLBADDRACK_out, + PPCS1PLBMBUSY_out, + PPCS1PLBMIRQ_out, + PPCS1PLBMRDERR_out, + PPCS1PLBMWRERR_out, + PPCS1PLBRDBTERM_out, + PPCS1PLBRDCOMP_out, + PPCS1PLBRDDACK_out, + PPCS1PLBRDDBUS_out, + PPCS1PLBRDWDADDR_out, + PPCS1PLBREARBITRATE_out, + PPCS1PLBSSIZE_out, + PPCS1PLBWAIT_out, + PPCS1PLBWRBTERM_out, + PPCS1PLBWRCOMP_out, + PPCS1PLBWRDACK_out, + + CPMC440CLKEN_ipd, + CPMC440CLK_ipd, + CPMC440CORECLOCKINACTIVE_ipd, + CPMC440TIMERCLOCK_ipd, + CPMDCRCLK_ipd, + CPMDMA0LLCLK_ipd, + CPMDMA1LLCLK_ipd, + CPMDMA2LLCLK_ipd, + CPMDMA3LLCLK_ipd, + CPMFCMCLK_ipd, + CPMINTERCONNECTCLKEN_ipd, + CPMINTERCONNECTCLKNTO1_ipd, + CPMINTERCONNECTCLK_ipd, + CPMMCCLK_ipd, + CPMPPCMPLBCLK_ipd, + CPMPPCS0PLBCLK_ipd, + CPMPPCS1PLBCLK_ipd, + DBGC440DEBUGHALT_ipd, + DBGC440SYSTEMSTATUS_ipd, + DBGC440UNCONDDEBUGEVENT_ipd, + DCRPPCDMACK_ipd, + DCRPPCDMDBUSIN_ipd, + DCRPPCDMTIMEOUTWAIT_ipd, + DCRPPCDSABUS_ipd, + DCRPPCDSDBUSOUT_ipd, + DCRPPCDSREAD_ipd, + DCRPPCDSWRITE_ipd, + EICC440CRITIRQ_ipd, + EICC440EXTIRQ_ipd, + FCMAPUCONFIRMINSTR_ipd, + FCMAPUCR_ipd, + FCMAPUDONE_ipd, + FCMAPUEXCEPTION_ipd, + FCMAPUFPSCRFEX_ipd, + FCMAPURESULTVALID_ipd, + FCMAPURESULT_ipd, + FCMAPUSLEEPNOTREADY_ipd, + FCMAPUSTOREDATA_ipd, + JTGC440TCK_ipd, + JTGC440TDI_ipd, + JTGC440TMS_ipd, + JTGC440TRSTNEG_ipd, + LLDMA0RSTENGINEREQ_ipd, + LLDMA0RXD_ipd, + LLDMA0RXEOFN_ipd, + LLDMA0RXEOPN_ipd, + LLDMA0RXREM_ipd, + LLDMA0RXSOFN_ipd, + LLDMA0RXSOPN_ipd, + LLDMA0RXSRCRDYN_ipd, + LLDMA0TXDSTRDYN_ipd, + LLDMA1RSTENGINEREQ_ipd, + LLDMA1RXD_ipd, + LLDMA1RXEOFN_ipd, + LLDMA1RXEOPN_ipd, + LLDMA1RXREM_ipd, + LLDMA1RXSOFN_ipd, + LLDMA1RXSOPN_ipd, + LLDMA1RXSRCRDYN_ipd, + LLDMA1TXDSTRDYN_ipd, + LLDMA2RSTENGINEREQ_ipd, + LLDMA2RXD_ipd, + LLDMA2RXEOFN_ipd, + LLDMA2RXEOPN_ipd, + LLDMA2RXREM_ipd, + LLDMA2RXSOFN_ipd, + LLDMA2RXSOPN_ipd, + LLDMA2RXSRCRDYN_ipd, + LLDMA2TXDSTRDYN_ipd, + LLDMA3RSTENGINEREQ_ipd, + LLDMA3RXD_ipd, + LLDMA3RXEOFN_ipd, + LLDMA3RXEOPN_ipd, + LLDMA3RXREM_ipd, + LLDMA3RXSOFN_ipd, + LLDMA3RXSOPN_ipd, + LLDMA3RXSRCRDYN_ipd, + LLDMA3TXDSTRDYN_ipd, + MCMIADDRREADYTOACCEPT_ipd, + MCMIREADDATAERR_ipd, + MCMIREADDATAVALID_ipd, + MCMIREADDATA_ipd, + PLBPPCMADDRACK_ipd, + PLBPPCMMBUSY_ipd, + PLBPPCMMIRQ_ipd, + PLBPPCMMRDERR_ipd, + PLBPPCMMWRERR_ipd, + PLBPPCMRDBTERM_ipd, + PLBPPCMRDDACK_ipd, + PLBPPCMRDDBUS_ipd, + PLBPPCMRDPENDPRI_ipd, + PLBPPCMRDPENDREQ_ipd, + PLBPPCMRDWDADDR_ipd, + PLBPPCMREARBITRATE_ipd, + PLBPPCMREQPRI_ipd, + PLBPPCMSSIZE_ipd, + PLBPPCMTIMEOUT_ipd, + PLBPPCMWRBTERM_ipd, + PLBPPCMWRDACK_ipd, + PLBPPCMWRPENDPRI_ipd, + PLBPPCMWRPENDREQ_ipd, + PLBPPCS0ABORT_ipd, + PLBPPCS0ABUS_ipd, + PLBPPCS0BE_ipd, + PLBPPCS0BUSLOCK_ipd, + PLBPPCS0LOCKERR_ipd, + PLBPPCS0MASTERID_ipd, + PLBPPCS0MSIZE_ipd, + PLBPPCS0PAVALID_ipd, + PLBPPCS0RDBURST_ipd, + PLBPPCS0RDPENDPRI_ipd, + PLBPPCS0RDPENDREQ_ipd, + PLBPPCS0RDPRIM_ipd, + PLBPPCS0REQPRI_ipd, + PLBPPCS0RNW_ipd, + PLBPPCS0SAVALID_ipd, + PLBPPCS0SIZE_ipd, + PLBPPCS0TATTRIBUTE_ipd, + PLBPPCS0TYPE_ipd, + PLBPPCS0UABUS_ipd, + PLBPPCS0WRBURST_ipd, + PLBPPCS0WRDBUS_ipd, + PLBPPCS0WRPENDPRI_ipd, + PLBPPCS0WRPENDREQ_ipd, + PLBPPCS0WRPRIM_ipd, + PLBPPCS1ABORT_ipd, + PLBPPCS1ABUS_ipd, + PLBPPCS1BE_ipd, + PLBPPCS1BUSLOCK_ipd, + PLBPPCS1LOCKERR_ipd, + PLBPPCS1MASTERID_ipd, + PLBPPCS1MSIZE_ipd, + PLBPPCS1PAVALID_ipd, + PLBPPCS1RDBURST_ipd, + PLBPPCS1RDPENDPRI_ipd, + PLBPPCS1RDPENDREQ_ipd, + PLBPPCS1RDPRIM_ipd, + PLBPPCS1REQPRI_ipd, + PLBPPCS1RNW_ipd, + PLBPPCS1SAVALID_ipd, + PLBPPCS1SIZE_ipd, + PLBPPCS1TATTRIBUTE_ipd, + PLBPPCS1TYPE_ipd, + PLBPPCS1UABUS_ipd, + PLBPPCS1WRBURST_ipd, + PLBPPCS1WRDBUS_ipd, + PLBPPCS1WRPENDPRI_ipd, + PLBPPCS1WRPENDREQ_ipd, + PLBPPCS1WRPRIM_ipd, + RSTC440RESETCHIP_ipd, + RSTC440RESETCORE_ipd, + RSTC440RESETSYSTEM_ipd, + TIEC440DCURDLDCACHEPLBPRIO_ipd, + TIEC440DCURDNONCACHEPLBPRIO_ipd, + TIEC440DCURDTOUCHPLBPRIO_ipd, + TIEC440DCURDURGENTPLBPRIO_ipd, + TIEC440DCUWRFLUSHPLBPRIO_ipd, + TIEC440DCUWRSTOREPLBPRIO_ipd, + TIEC440DCUWRURGENTPLBPRIO_ipd, + TIEC440ENDIANRESET_ipd, + TIEC440ERPNRESET_ipd, + TIEC440ICURDFETCHPLBPRIO_ipd, + TIEC440ICURDSPECPLBPRIO_ipd, + TIEC440ICURDTOUCHPLBPRIO_ipd, + TIEC440PIR_ipd, + TIEC440PVR_ipd, + TIEC440USERRESET_ipd, + TIEDCRBASEADDR_ipd, + TRCC440TRACEDISABLE_ipd, + TRCC440TRIGGEREVENTIN_ipd; + + end process TIMING; + + +end PPC440_V; diff --git a/Common/sim/xilinx/libsrc/unisims/unisim_SMODEL.vhd b/Common/sim/xilinx/libsrc/unisims/unisim_SMODEL.vhd new file mode 100644 index 0000000..4089d1f --- /dev/null +++ b/Common/sim/xilinx/libsrc/unisims/unisim_SMODEL.vhd @@ -0,0 +1,41318 @@ +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/dcc_fpgacore.vhd,v 1.5 2006/03/16 00:57:41 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Digital Configuration Controller for FPGACORE +-- /___/ /\ Filename : DCC_FPGACORE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:07 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL DCC_FPGACORE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity DCC_FPGACORE is + generic ( + DEVICE_SIZE : integer := 10 + ); + + port ( + BCLK : out std_ulogic; + DONEOUT : out std_ulogic; + DOUT0 : out std_ulogic; + DOUT1 : out std_ulogic; + DOUT2 : out std_ulogic; + DOUT3 : out std_ulogic; + DOUT4 : out std_ulogic; + DOUT5 : out std_ulogic; + DOUT6 : out std_ulogic; + DOUT7 : out std_ulogic; + GSR : out std_ulogic; + GTS : out std_ulogic; + GWE : out std_ulogic; + INITBOUT : out std_ulogic; + TDO : out std_ulogic; + + CCLK : in std_ulogic; + CSB : in std_ulogic; + DIN0 : in std_ulogic; + DIN1 : in std_ulogic; + DIN2 : in std_ulogic; + DIN3 : in std_ulogic; + DIN4 : in std_ulogic; + DIN5 : in std_ulogic; + DIN6 : in std_ulogic; + DIN7 : in std_ulogic; + DONEIN : in std_ulogic; + LBISTISOLATEB : in std_ulogic; + M0 : in std_ulogic; + M1 : in std_ulogic; + M2 : in std_ulogic; + PROGB : in std_ulogic; + TCK : in std_ulogic; + TDI : in std_ulogic; + TMS : in std_ulogic; + WRITEB : in std_ulogic + ); +end DCC_FPGACORE; + +architecture DCC_FPGACORE_V of DCC_FPGACORE is + component DCC_FPGACORE_SWIFT_BUS +port ( + BCLK : out std_ulogic; + DONEOUT : out std_ulogic; + DOUT0 : out std_ulogic; + DOUT1 : out std_ulogic; + DOUT2 : out std_ulogic; + DOUT3 : out std_ulogic; + DOUT4 : out std_ulogic; + DOUT5 : out std_ulogic; + DOUT6 : out std_ulogic; + DOUT7 : out std_ulogic; + GSR : out std_ulogic; + GTS : out std_ulogic; + GWE : out std_ulogic; + INITBOUT : out std_ulogic; + TDO : out std_ulogic; + + CCLK : in std_ulogic; + CSB : in std_ulogic; + DIN0 : in std_ulogic; + DIN1 : in std_ulogic; + DIN2 : in std_ulogic; + DIN3 : in std_ulogic; + DIN4 : in std_ulogic; + DIN5 : in std_ulogic; + DIN6 : in std_ulogic; + DIN7 : in std_ulogic; + DONEIN : in std_ulogic; + LBISTISOLATEB : in std_ulogic; + M0 : in std_ulogic; + M1 : in std_ulogic; + M2 : in std_ulogic; + PROGB : in std_ulogic; + TCK : in std_ulogic; + TDI : in std_ulogic; + TMS : in std_ulogic; + WRITEB : in std_ulogic; + XBID : in std_logic_vector(8 downto 0) + ); + end component; + signal XBID_BINARY : std_logic_vector(8 downto 0); + +begin + + DCC_FPGACORE_inst : DCC_FPGACORE_SWIFT_BUS + port map ( + XBID => XBID_BINARY, + CCLK => CCLK, + CSB => CSB, + DIN0 => DIN0, + DIN1 => DIN1, + DIN2 => DIN2, + DIN3 => DIN3, + DIN4 => DIN4, + DIN5 => DIN5, + DIN6 => DIN6, + DIN7 => DIN7, + DONEIN => DONEIN, + LBISTISOLATEB => LBISTISOLATEB, + M0 => M0, + M1 => M1, + M2 => M2, + PROGB => PROGB, + TCK => TCK, + TDI => TDI, + TMS => TMS, + WRITEB => WRITEB, + BCLK => BCLK, + DONEOUT => DONEOUT, + DOUT0 => DOUT0, + DOUT1 => DOUT1, + DOUT2 => DOUT2, + DOUT3 => DOUT3, + DOUT4 => DOUT4, + DOUT5 => DOUT5, + DOUT6 => DOUT6, + DOUT7 => DOUT7, + GSR => GSR, + GTS => GTS, + GWE => GWE, + INITBOUT => INITBOUT, + TDO => TDO + + ); + + INIPROC : process + begin + case DEVICE_SIZE is + when 10 => XBID_BINARY <= "000001010"; + when 20 => XBID_BINARY <= "000010100"; + when 40 => XBID_BINARY <= "000101000"; + when others => assert FALSE report "Error : DEVICE_SIZE is not in 10, 20, 40." severity warning; + end case; + wait; + end process INIPROC; +end DCC_FPGACORE_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_10ge_4.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for 10GE I/O Standard 4 Byte Data +-- /___/ /\ Filename : GT10_10GE_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:07 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_10GE_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_10GE_4 is +generic ( + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := TRUE; + CHAN_BOND_64B66B_SV : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := TRUE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_CORRECT_USE : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_10GE_4; + +-- Architecture body -- + +architecture GT10_10GE_4_V of GT10_10GE_4 is + +signal OPEN4 : std_logic_vector(3 downto 0); +signal OPEN32 : std_logic_vector(31 downto 0); +signal z4 : std_logic_vector(3 downto 0) := "0000"; +signal z32 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00000000000", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, + CHAN_BOND_SEQ_LEN => 8, + CHAN_BOND_64B66B_SV => CHAN_BOND_64B66B_SV, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_SEQ_1_1 => "10000011110", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => 8, + CLK_CORRECT_USE => CLK_CORRECT_USE, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "6_32", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SH_CNT_MAX => SH_CNT_MAX, + SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(3 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(7 downto 4) => OPEN4, + RXCHARISK(3 downto 0) => RXCHARISK, + RXCHARISK(7 downto 4) => OPEN4, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA(31 downto 0) => RXDATA, + RXDATA(63 downto 32) => OPEN32, + RXDISPERR(3 downto 0) => RXDISPERR, + RXDISPERR(7 downto 4) => OPEN4, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(3 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(7 downto 4) => OPEN4, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(3 downto 0) => RXRUNDISP, + RXRUNDISP(7 downto 4) => OPEN4, + TXBUFERR => TXBUFERR, + TXKERR(3 downto 0) => TXKERR, + TXKERR(7 downto 4) => OPEN4, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP(3 downto 0) => TXRUNDISP, + TXRUNDISP(7 downto 4) => OPEN4, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(3 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(7 downto 4) => z4, + TXCHARDISPMODE(3 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(7 downto 4) => z4, + TXCHARDISPVAL(3 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(7 downto 4) => z4, + TXCHARISK(3 downto 0) => TXCHARISK, + TXCHARISK(7 downto 4) => z4, + TXDATA(31 downto 0) => TXDATA, + TXDATA(63 downto 32) => z32, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_10GE_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_10ge_8.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for 10GE I/O Standard 8 Byte Data +-- /___/ /\ Filename : GT10_10GE_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:07 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_10GE_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_10GE_8 is +generic ( + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := TRUE; + CHAN_BOND_64B66B_SV : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := TRUE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_CORRECT_USE : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDISPERR : out std_logic_vector(7 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(7 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(7 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(7 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(7 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXDATA : in std_logic_vector(63 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_10GE_8; + +-- Architecture body -- + +architecture GT10_10GE_8_V of GT10_10GE_8 is + + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00000000000", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, + CHAN_BOND_SEQ_LEN => 8, + CHAN_BOND_64B66B_SV => CHAN_BOND_64B66B_SV, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_SEQ_1_1 => "10000011110", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => 8, + CLK_CORRECT_USE => CLK_CORRECT_USE, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "6_64", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SH_CNT_MAX => SH_CNT_MAX, + SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA => RXCHARISCOMMA, + RXCHARISK => RXCHARISK, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA => RXDATA, + RXDISPERR => RXDISPERR, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE => RXNOTINTABLE, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP => RXRUNDISP, + TXBUFERR => TXBUFERR, + TXKERR => TXKERR, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP => TXRUNDISP, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B => TXBYPASS8B10B, + TXCHARDISPMODE => TXCHARDISPMODE, + TXCHARDISPVAL => TXCHARDISPVAL, + TXCHARISK => TXCHARISK, + TXDATA => TXDATA, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_10GE_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_10gfc_4.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for 10GFC I/O Standard 4 Byte Data +-- /___/ /\ Filename : GT10_10GFC_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:07 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_10GFC_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_10GFC_4 is +generic ( + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := TRUE; + CHAN_BOND_64B66B_SV : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := TRUE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_CORRECT_USE : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_10GFC_4; + +-- Architecture body -- + +architecture GT10_10GFC_4_V of GT10_10GFC_4 is + +signal OPEN4 : std_logic_vector(3 downto 0); +signal OPEN32 : std_logic_vector(31 downto 0); +signal z4 : std_logic_vector(3 downto 0) := "0000"; +signal z32 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00000000000", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, + CHAN_BOND_SEQ_LEN => 8, + CHAN_BOND_64B66B_SV => CHAN_BOND_64B66B_SV, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_SEQ_1_1 => "10000011110", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => 8, + CLK_CORRECT_USE => CLK_CORRECT_USE, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "0_32", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SH_CNT_MAX => SH_CNT_MAX, + SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(3 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(7 downto 4) => OPEN4, + RXCHARISK(3 downto 0) => RXCHARISK, + RXCHARISK(7 downto 4) => OPEN4, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA(31 downto 0) => RXDATA, + RXDATA(63 downto 32) => OPEN32, + RXDISPERR(3 downto 0) => RXDISPERR, + RXDISPERR(7 downto 4) => OPEN4, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(3 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(7 downto 4) => OPEN4, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(3 downto 0) => RXRUNDISP, + RXRUNDISP(7 downto 4) => OPEN4, + TXBUFERR => TXBUFERR, + TXKERR(3 downto 0) => TXKERR, + TXKERR(7 downto 4) => OPEN4, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP(3 downto 0) => TXRUNDISP, + TXRUNDISP(7 downto 4) => OPEN4, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(3 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(7 downto 4) => z4, + TXCHARDISPMODE(3 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(7 downto 4) => z4, + TXCHARDISPVAL(3 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(7 downto 4) => z4, + TXCHARISK(3 downto 0) => TXCHARISK, + TXCHARISK(7 downto 4) => z4, + TXDATA(31 downto 0) => TXDATA, + TXDATA(63 downto 32) => z32, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_10GFC_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_10gfc_8.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for 10GFC I/O Standard 8 Byte Data +-- /___/ /\ Filename : GT10_10GFC_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:07 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_10GFC_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_10GFC_8 is +generic ( + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := TRUE; + CHAN_BOND_64B66B_SV : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := TRUE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_CORRECT_USE : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDISPERR : out std_logic_vector(7 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(7 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(7 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(7 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(7 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXDATA : in std_logic_vector(63 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_10GFC_8; + +-- Architecture body -- + +architecture GT10_10GFC_8_V of GT10_10GFC_8 is + + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00000000000", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, + CHAN_BOND_SEQ_LEN => 8, + CHAN_BOND_64B66B_SV => CHAN_BOND_64B66B_SV, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_SEQ_1_1 => "10000011110", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => 8, + CLK_CORRECT_USE => CLK_CORRECT_USE, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "0_64", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SH_CNT_MAX => SH_CNT_MAX, + SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA => RXCHARISCOMMA, + RXCHARISK => RXCHARISK, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA => RXDATA, + RXDISPERR => RXDISPERR, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE => RXNOTINTABLE, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP => RXRUNDISP, + TXBUFERR => TXBUFERR, + TXKERR => TXKERR, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP => TXRUNDISP, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B => TXBYPASS8B10B, + TXCHARDISPMODE => TXCHARDISPMODE, + TXCHARDISPVAL => TXCHARDISPVAL, + TXCHARISK => TXCHARISK, + TXDATA => TXDATA, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_10GFC_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_aurora_1.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for AURORA I/O Standard 1 Byte Data +-- /___/ /\ Filename : GT10_AURORA_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_AURORA_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_AURORA_1 is +generic ( + ALIGN_COMMA_WORD : integer := 1; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_CORRECT_USE : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00fc0db00b0f32263068090104a628"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_AURORA_1; + +-- Architecture body -- + +architecture GT10_AURORA_1_V of GT10_AURORA_1 is + +signal OPEN7 : std_logic_vector(6 downto 0); +signal OPEN56 : std_logic_vector(55 downto 0); +signal z7 : std_logic_vector(6 downto 0) := "0000000"; +signal z56 : std_logic_vector(55 downto 0) := "00000000000000000000000000000000000000000000000000000000"; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00110111100", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00001001010", + CHAN_BOND_SEQ_1_4 => "00001001010", + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_SEQ_2_1 => "00110111100", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00001000101", + CHAN_BOND_SEQ_2_4 => "00001000101", + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + CHAN_BOND_SEQ_2_USE => FALSE, + CHAN_BOND_SEQ_LEN => 2, + CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_SEQ_1_1 => "00100011100", + CLK_COR_SEQ_1_2 => "00100011100", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_SEQ_2_USE => FALSE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => 2, + CLK_CORRECT_USE => CLK_CORRECT_USE, + COMMA_10B_MASK => "0001111111", + DEC_MCOMMA_DETECT => TRUE, + DEC_PCOMMA_DETECT => TRUE, + DEC_VALID_COMMA_ONLY => TRUE, + MCOMMA_10B_VALUE => "1010000011", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0101111100", + PCOMMA_DETECT => TRUE, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "25_10", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(7 downto 1) => OPEN7, + RXCHARISK(0 downto 0) => RXCHARISK, + RXCHARISK(7 downto 1) => OPEN7, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA(7 downto 0) => RXDATA, + RXDATA(63 downto 8) => OPEN56, + RXDISPERR(0 downto 0) => RXDISPERR, + RXDISPERR(7 downto 1) => OPEN7, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(7 downto 1) => OPEN7, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(0 downto 0) => RXRUNDISP, + RXRUNDISP(7 downto 1) => OPEN7, + TXBUFERR => TXBUFERR, + TXKERR(0 downto 0) => TXKERR, + TXKERR(7 downto 1) => OPEN7, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP(0 downto 0) => TXRUNDISP, + TXRUNDISP(7 downto 1) => OPEN7, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(7 downto 1) => z7, + TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(7 downto 1) => z7, + TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(7 downto 1) => z7, + TXCHARISK(0 downto 0) => TXCHARISK, + TXCHARISK(7 downto 1) => z7, + TXDATA(7 downto 0) => TXDATA, + TXDATA(63 downto 8) => z56, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_AURORA_1_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_aurora_2.vhd,v 1.6 2005/07/23 00:03:51 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for AURORA I/O Standard 2 Byte Data +-- /___/ /\ Filename : GT10_AURORA_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_AURORA_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_AURORA_2 is +generic ( + ALIGN_COMMA_WORD : integer := 1; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_CORRECT_USE : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00fc0db00b0f32663068090105a628"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_AURORA_2; + +-- Architecture body -- + +architecture GT10_AURORA_2_V of GT10_AURORA_2 is + +signal OPEN6 : std_logic_vector(5 downto 0); +signal OPEN48 : std_logic_vector(47 downto 0); +signal z6 : std_logic_vector(5 downto 0) := "000000"; +signal z48 : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00110111100", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00001001010", + CHAN_BOND_SEQ_1_4 => "00001001010", + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_SEQ_2_1 => "00110111100", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00001000101", + CHAN_BOND_SEQ_2_4 => "00001000101", + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + CHAN_BOND_SEQ_2_USE => FALSE, + CHAN_BOND_SEQ_LEN => 2, + CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_SEQ_1_1 => "00100011100", + CLK_COR_SEQ_1_2 => "00100011100", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_SEQ_2_USE => FALSE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => 2, + CLK_CORRECT_USE => CLK_CORRECT_USE, + COMMA_10B_MASK => "0001111111", + DEC_MCOMMA_DETECT => TRUE, + DEC_PCOMMA_DETECT => TRUE, + DEC_VALID_COMMA_ONLY => TRUE, + MCOMMA_10B_VALUE => "1010000011", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0101111100", + PCOMMA_DETECT => TRUE, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "25_20", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(7 downto 2) => OPEN6, + RXCHARISK(1 downto 0) => RXCHARISK, + RXCHARISK(7 downto 2) => OPEN6, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA(15 downto 0) => RXDATA, + RXDATA(63 downto 16) => OPEN48, + RXDISPERR(1 downto 0) => RXDISPERR, + RXDISPERR(7 downto 2) => OPEN6, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(7 downto 2) => OPEN6, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(1 downto 0) => RXRUNDISP, + RXRUNDISP(7 downto 2) => OPEN6, + TXBUFERR => TXBUFERR, + TXKERR(1 downto 0) => TXKERR, + TXKERR(7 downto 2) => OPEN6, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP(1 downto 0) => TXRUNDISP, + TXRUNDISP(7 downto 2) => OPEN6, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(7 downto 2) => z6, + TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(7 downto 2) => z6, + TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(7 downto 2) => z6, + TXCHARISK(1 downto 0) => TXCHARISK, + TXCHARISK(7 downto 2) => z6, + TXDATA(15 downto 0) => TXDATA, + TXDATA(63 downto 16) => z48, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_AURORA_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_aurora_4.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for AURORA I/O Standard 4 Byte Data +-- /___/ /\ Filename : GT10_AURORA_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_AURORA_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_AURORA_4 is +generic ( + ALIGN_COMMA_WORD : integer := 1; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_CORRECT_USE : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd500b0132663068090105a628"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_AURORA_4; + +-- Architecture body -- + +architecture GT10_AURORA_4_V of GT10_AURORA_4 is + +signal OPEN4 : std_logic_vector(3 downto 0); +signal OPEN32 : std_logic_vector(31 downto 0); +signal z4 : std_logic_vector(3 downto 0) := "0000"; +signal z32 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00110111100", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00001001010", + CHAN_BOND_SEQ_1_4 => "00001001010", + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_SEQ_2_1 => "00110111100", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00001000101", + CHAN_BOND_SEQ_2_4 => "00001000101", + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + CHAN_BOND_SEQ_2_USE => FALSE, + CHAN_BOND_SEQ_LEN => 4, + CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_SEQ_1_1 => "00100011100", + CLK_COR_SEQ_1_2 => "00100011100", + CLK_COR_SEQ_1_3 => "00100011100", + CLK_COR_SEQ_1_4 => "00100011100", + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_SEQ_2_USE => FALSE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => 4, + CLK_CORRECT_USE => CLK_CORRECT_USE, + COMMA_10B_MASK => "0001111111", + DEC_MCOMMA_DETECT => TRUE, + DEC_PCOMMA_DETECT => TRUE, + DEC_VALID_COMMA_ONLY => TRUE, + MCOMMA_10B_VALUE => "1010000011", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0101111100", + PCOMMA_DETECT => TRUE, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "25_40", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(3 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(7 downto 4) => OPEN4, + RXCHARISK(3 downto 0) => RXCHARISK, + RXCHARISK(7 downto 4) => OPEN4, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA(31 downto 0) => RXDATA, + RXDATA(63 downto 32) => OPEN32, + RXDISPERR(3 downto 0) => RXDISPERR, + RXDISPERR(7 downto 4) => OPEN4, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(3 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(7 downto 4) => OPEN4, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(3 downto 0) => RXRUNDISP, + RXRUNDISP(7 downto 4) => OPEN4, + TXBUFERR => TXBUFERR, + TXKERR(3 downto 0) => TXKERR, + TXKERR(7 downto 4) => OPEN4, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP(3 downto 0) => TXRUNDISP, + TXRUNDISP(7 downto 4) => OPEN4, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(3 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(7 downto 4) => z4, + TXCHARDISPMODE(3 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(7 downto 4) => z4, + TXCHARDISPVAL(3 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(7 downto 4) => z4, + TXCHARISK(3 downto 0) => TXCHARISK, + TXCHARISK(7 downto 4) => z4, + TXDATA(31 downto 0) => TXDATA, + TXDATA(63 downto 32) => z32, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_AURORA_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_aurorax_4.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for AURORAX I/O Standard 4 Byte Data +-- /___/ /\ Filename : GT10_AURORAX_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_AURORAX_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_AURORAX_4 is +generic ( + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_64B66B_SV : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_CORRECT_USE : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_AURORAX_4; + +-- Architecture body -- + +architecture GT10_AURORAX_4_V of GT10_AURORAX_4 is + +signal OPEN4 : std_logic_vector(3 downto 0); +signal OPEN32 : std_logic_vector(31 downto 0); +signal z4 : std_logic_vector(3 downto 0) := "0000"; +signal z32 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00000000000", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + CHAN_BOND_SEQ_2_USE => FALSE, + CHAN_BOND_SEQ_LEN => 8, + CHAN_BOND_64B66B_SV => CHAN_BOND_64B66B_SV, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_SEQ_1_1 => "10000011110", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_SEQ_2_USE => TRUE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => 8, + CLK_CORRECT_USE => CLK_CORRECT_USE, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "0_32", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SH_CNT_MAX => SH_CNT_MAX, + SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(3 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(7 downto 4) => OPEN4, + RXCHARISK(3 downto 0) => RXCHARISK, + RXCHARISK(7 downto 4) => OPEN4, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA(31 downto 0) => RXDATA, + RXDATA(63 downto 32) => OPEN32, + RXDISPERR(3 downto 0) => RXDISPERR, + RXDISPERR(7 downto 4) => OPEN4, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(3 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(7 downto 4) => OPEN4, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(3 downto 0) => RXRUNDISP, + RXRUNDISP(7 downto 4) => OPEN4, + TXBUFERR => TXBUFERR, + TXKERR(3 downto 0) => TXKERR, + TXKERR(7 downto 4) => OPEN4, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP(3 downto 0) => TXRUNDISP, + TXRUNDISP(7 downto 4) => OPEN4, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(3 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(7 downto 4) => z4, + TXCHARDISPMODE(3 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(7 downto 4) => z4, + TXCHARDISPVAL(3 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(7 downto 4) => z4, + TXCHARISK(3 downto 0) => TXCHARISK, + TXCHARISK(7 downto 4) => z4, + TXDATA(31 downto 0) => TXDATA, + TXDATA(63 downto 32) => z32, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_AURORAX_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_aurorax_8.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for AURORAX I/O Standard 8 Byte Data +-- /___/ /\ Filename : GT10_AURORAX_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_AURORAX_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_AURORAX_8 is +generic ( + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_64B66B_SV : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_CORRECT_USE : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDISPERR : out std_logic_vector(7 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(7 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(7 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(7 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(7 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXDATA : in std_logic_vector(63 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_AURORAX_8; + +-- Architecture body -- + +architecture GT10_AURORAX_8_V of GT10_AURORAX_8 is + + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00000000000", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + CHAN_BOND_SEQ_2_USE => FALSE, + CHAN_BOND_SEQ_LEN => 8, + CHAN_BOND_64B66B_SV => CHAN_BOND_64B66B_SV, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_SEQ_1_1 => "10000011110", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_SEQ_2_USE => TRUE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => 8, + CLK_CORRECT_USE => CLK_CORRECT_USE, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "0_64", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SH_CNT_MAX => SH_CNT_MAX, + SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA => RXCHARISCOMMA, + RXCHARISK => RXCHARISK, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA => RXDATA, + RXDISPERR => RXDISPERR, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE => RXNOTINTABLE, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP => RXRUNDISP, + TXBUFERR => TXBUFERR, + TXKERR => TXKERR, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP => TXRUNDISP, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B => TXBYPASS8B10B, + TXCHARDISPMODE => TXCHARDISPMODE, + TXCHARDISPVAL => TXCHARDISPVAL, + TXCHARISK => TXCHARISK, + TXDATA => TXDATA, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_AURORAX_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_custom.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for CUSTOM I/O Standard +-- /___/ /\ Filename : GT10_CUSTOM.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_CUSTOM ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_CUSTOM is +generic ( + ALIGN_COMMA_WORD : integer := 1; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 1; + CHAN_BOND_64B66B_SV : boolean := FALSE; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 1; + CLK_CORRECT_USE : boolean := TRUE; + COMMA_10B_MASK : bit_vector := "0001111111"; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + MCOMMA_10B_VALUE : bit_vector := "1010000011"; + MCOMMA_DETECT : boolean := TRUE; + PCOMMA_10B_VALUE : bit_vector := "0101111100"; + PCOMMA_DETECT : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED : string := "0_32"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDISPERR : out std_logic_vector(7 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(7 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(7 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(7 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(7 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXDATA : in std_logic_vector(63 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_CUSTOM; + +-- Architecture body -- + +architecture GT10_CUSTOM_V of GT10_CUSTOM is + + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => CHAN_BOND_SEQ_1_1, + CHAN_BOND_SEQ_1_2 => CHAN_BOND_SEQ_1_2, + CHAN_BOND_SEQ_1_3 => CHAN_BOND_SEQ_1_3, + CHAN_BOND_SEQ_1_4 => CHAN_BOND_SEQ_1_4, + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_SEQ_2_1 => CHAN_BOND_SEQ_2_1, + CHAN_BOND_SEQ_2_2 => CHAN_BOND_SEQ_2_2, + CHAN_BOND_SEQ_2_3 => CHAN_BOND_SEQ_2_3, + CHAN_BOND_SEQ_2_4 => CHAN_BOND_SEQ_2_4, + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, + CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, + CHAN_BOND_64B66B_SV => CHAN_BOND_64B66B_SV, + CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_SEQ_1_1 => CLK_COR_SEQ_1_1, + CLK_COR_SEQ_1_2 => CLK_COR_SEQ_1_2, + CLK_COR_SEQ_1_3 => CLK_COR_SEQ_1_3, + CLK_COR_SEQ_1_4 => CLK_COR_SEQ_1_4, + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + CLK_COR_SEQ_2_1 => CLK_COR_SEQ_2_1, + CLK_COR_SEQ_2_2 => CLK_COR_SEQ_2_2, + CLK_COR_SEQ_2_3 => CLK_COR_SEQ_2_3, + CLK_COR_SEQ_2_4 => CLK_COR_SEQ_2_4, + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, + CLK_CORRECT_USE => CLK_CORRECT_USE, + COMMA_10B_MASK => COMMA_10B_MASK, + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, + DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, + MCOMMA_10B_VALUE => MCOMMA_10B_VALUE, + MCOMMA_DETECT => MCOMMA_DETECT, + PCOMMA_10B_VALUE => PCOMMA_10B_VALUE, + PCOMMA_DETECT => PCOMMA_DETECT, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => PMA_SPEED, + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SH_CNT_MAX => SH_CNT_MAX, + SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA => RXCHARISCOMMA, + RXCHARISK => RXCHARISK, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA => RXDATA, + RXDISPERR => RXDISPERR, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE => RXNOTINTABLE, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP => RXRUNDISP, + TXBUFERR => TXBUFERR, + TXKERR => TXKERR, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP => TXRUNDISP, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B => TXBYPASS8B10B, + TXCHARDISPMODE => TXCHARDISPMODE, + TXCHARDISPVAL => TXCHARDISPVAL, + TXCHARISK => TXCHARISK, + TXDATA => TXDATA, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_CUSTOM_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_infiniband_1.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for INFINIBAND I/O Standard 1 Byte Data +-- /___/ /\ Filename : GT10_INFINIBAND_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_INFINIBAND_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_INFINIBAND_1 is +generic ( + ALIGN_COMMA_WORD : integer := 2; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_LEN : integer := 2; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 2; + CLK_CORRECT_USE : boolean := TRUE; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + LANE_ID : bit_vector := "00000000000"; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd500b0132263068090104a620"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_INFINIBAND_1; + +-- Architecture body -- + +architecture GT10_INFINIBAND_1_V of GT10_INFINIBAND_1 is + +signal OPEN7 : std_logic_vector(6 downto 0); +signal OPEN56 : std_logic_vector(55 downto 0); +signal z7 : std_logic_vector(6 downto 0) := "0000000"; +signal z56 : std_logic_vector(55 downto 0) := "00000000000000000000000000000000000000000000000000000000"; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00110111100", + CHAN_BOND_SEQ_1_2 => LANE_ID, + CHAN_BOND_SEQ_1_3 => "00001001010", + CHAN_BOND_SEQ_1_4 => "00001001010", + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_SEQ_2_1 => "00110111100", + CHAN_BOND_SEQ_2_2 => LANE_ID, + CHAN_BOND_SEQ_2_3 => "00001000101", + CHAN_BOND_SEQ_2_4 => "00001000101", + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + CHAN_BOND_SEQ_2_USE => TRUE, + CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, + CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_SEQ_1_1 => "00100011100", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, + CLK_CORRECT_USE => CLK_CORRECT_USE, + COMMA_10B_MASK => "0001111111", + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, + DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, + MCOMMA_10B_VALUE => "1010000011", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0101111100", + PCOMMA_DETECT => TRUE, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "28_10", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(7 downto 1) => OPEN7, + RXCHARISK(0 downto 0) => RXCHARISK, + RXCHARISK(7 downto 1) => OPEN7, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA(7 downto 0) => RXDATA, + RXDATA(63 downto 8) => OPEN56, + RXDISPERR(0 downto 0) => RXDISPERR, + RXDISPERR(7 downto 1) => OPEN7, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(7 downto 1) => OPEN7, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(0 downto 0) => RXRUNDISP, + RXRUNDISP(7 downto 1) => OPEN7, + TXBUFERR => TXBUFERR, + TXKERR(0 downto 0) => TXKERR, + TXKERR(7 downto 1) => OPEN7, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP(0 downto 0) => TXRUNDISP, + TXRUNDISP(7 downto 1) => OPEN7, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(7 downto 1) => z7, + TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(7 downto 1) => z7, + TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(7 downto 1) => z7, + TXCHARISK(0 downto 0) => TXCHARISK, + TXCHARISK(7 downto 1) => z7, + TXDATA(7 downto 0) => TXDATA, + TXDATA(63 downto 8) => z56, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_INFINIBAND_1_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_infiniband_2.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for INFINIBAND I/O Standard 2 Byte Data +-- /___/ /\ Filename : GT10_INFINIBAND_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_INFINIBAND_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_INFINIBAND_2 is +generic ( + ALIGN_COMMA_WORD : integer := 2; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_LEN : integer := 2; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 2; + CLK_CORRECT_USE : boolean := TRUE; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + LANE_ID : bit_vector := "00000000000"; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00fc0d300b0f32663068090105a620"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_INFINIBAND_2; + +-- Architecture body -- + +architecture GT10_INFINIBAND_2_V of GT10_INFINIBAND_2 is + +signal OPEN6 : std_logic_vector(5 downto 0); +signal OPEN48 : std_logic_vector(47 downto 0); +signal z6 : std_logic_vector(5 downto 0) := "000000"; +signal z48 : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00110111100", + CHAN_BOND_SEQ_1_2 => LANE_ID, + CHAN_BOND_SEQ_1_3 => "00001001010", + CHAN_BOND_SEQ_1_4 => "00001001010", + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_SEQ_2_1 => "00110111100", + CHAN_BOND_SEQ_2_2 => LANE_ID, + CHAN_BOND_SEQ_2_3 => "00001000101", + CHAN_BOND_SEQ_2_4 => "00001000101", + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + CHAN_BOND_SEQ_2_USE => TRUE, + CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, + CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_SEQ_1_1 => "00100011100", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, + CLK_CORRECT_USE => CLK_CORRECT_USE, + COMMA_10B_MASK => "0001111111", + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, + DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, + MCOMMA_10B_VALUE => "1010000011", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0101111100", + PCOMMA_DETECT => TRUE, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "28_20", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(7 downto 2) => OPEN6, + RXCHARISK(1 downto 0) => RXCHARISK, + RXCHARISK(7 downto 2) => OPEN6, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA(15 downto 0) => RXDATA, + RXDATA(63 downto 16) => OPEN48, + RXDISPERR(1 downto 0) => RXDISPERR, + RXDISPERR(7 downto 2) => OPEN6, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(7 downto 2) => OPEN6, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(1 downto 0) => RXRUNDISP, + RXRUNDISP(7 downto 2) => OPEN6, + TXBUFERR => TXBUFERR, + TXKERR(1 downto 0) => TXKERR, + TXKERR(7 downto 2) => OPEN6, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP(1 downto 0) => TXRUNDISP, + TXRUNDISP(7 downto 2) => OPEN6, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(7 downto 2) => z6, + TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(7 downto 2) => z6, + TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(7 downto 2) => z6, + TXCHARISK(1 downto 0) => TXCHARISK, + TXCHARISK(7 downto 2) => z6, + TXDATA(15 downto 0) => TXDATA, + TXDATA(63 downto 16) => z48, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_INFINIBAND_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_infiniband_4.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for INFINIBAND I/O Standard 4 Byte Data +-- /___/ /\ Filename : GT10_INFINIBAND_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_INFINIBAND_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_INFINIBAND_4 is +generic ( + ALIGN_COMMA_WORD : integer := 2; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_LEN : integer := 2; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 2; + CLK_CORRECT_USE : boolean := TRUE; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + LANE_ID : bit_vector := "00000000000"; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd500b0132663068090105a620"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_INFINIBAND_4; + +-- Architecture body -- + +architecture GT10_INFINIBAND_4_V of GT10_INFINIBAND_4 is + +signal OPEN4 : std_logic_vector(3 downto 0); +signal OPEN32 : std_logic_vector(31 downto 0); +signal z4 : std_logic_vector(3 downto 0) := "0000"; +signal z32 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00110111100", + CHAN_BOND_SEQ_1_2 => LANE_ID, + CHAN_BOND_SEQ_1_3 => "00001001010", + CHAN_BOND_SEQ_1_4 => "00001001010", + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_SEQ_2_1 => "00110111100", + CHAN_BOND_SEQ_2_2 => LANE_ID, + CHAN_BOND_SEQ_2_3 => "00001000101", + CHAN_BOND_SEQ_2_4 => "00001000101", + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + CHAN_BOND_SEQ_2_USE => TRUE, + CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, + CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_SEQ_1_1 => "00100011100", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, + CLK_CORRECT_USE => CLK_CORRECT_USE, + COMMA_10B_MASK => "0001111111", + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, + DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, + MCOMMA_10B_VALUE => "1010000011", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0101111100", + PCOMMA_DETECT => TRUE, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "28_40", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(3 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(7 downto 4) => OPEN4, + RXCHARISK(3 downto 0) => RXCHARISK, + RXCHARISK(7 downto 4) => OPEN4, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA(31 downto 0) => RXDATA, + RXDATA(63 downto 32) => OPEN32, + RXDISPERR(3 downto 0) => RXDISPERR, + RXDISPERR(7 downto 4) => OPEN4, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(3 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(7 downto 4) => OPEN4, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(3 downto 0) => RXRUNDISP, + RXRUNDISP(7 downto 4) => OPEN4, + TXBUFERR => TXBUFERR, + TXKERR(3 downto 0) => TXKERR, + TXKERR(7 downto 4) => OPEN4, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP(3 downto 0) => TXRUNDISP, + TXRUNDISP(7 downto 4) => OPEN4, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(3 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(7 downto 4) => z4, + TXCHARDISPMODE(3 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(7 downto 4) => z4, + TXCHARDISPVAL(3 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(7 downto 4) => z4, + TXCHARISK(3 downto 0) => TXCHARISK, + TXCHARISK(7 downto 4) => z4, + TXDATA(31 downto 0) => TXDATA, + TXDATA(63 downto 32) => z32, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_INFINIBAND_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_oc192_4.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for OC192 I/O Standard 4 Byte Data +-- /___/ /\ Filename : GT10_OC192_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:09 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_OC192_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_OC192_4 is +generic ( + ALIGN_COMMA_WORD : integer := 1; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + MCOMMA_10B_VALUE : bit_vector := "0010101010"; + MCOMMA_DETECT : boolean := TRUE; + PCOMMA_10B_VALUE : bit_vector := "0010101010"; + PCOMMA_DETECT : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504c00208c9050d0068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLKBSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_OC192_4; + +-- Architecture body -- + +architecture GT10_OC192_4_V of GT10_OC192_4 is + +signal z1 : std_ulogic := '0'; +signal OPEN4 : std_logic_vector(3 downto 0); +signal OPEN32 : std_logic_vector(31 downto 0); +signal z4 : std_logic_vector(3 downto 0) := "0000"; +signal z32 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + COMMA_10B_MASK => "0011111111", + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, + MCOMMA_10B_VALUE => MCOMMA_10B_VALUE, + MCOMMA_DETECT => MCOMMA_DETECT, + PCOMMA_10B_VALUE => PCOMMA_10B_VALUE, + PCOMMA_DETECT => PCOMMA_DETECT, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "15_32", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + REFCLK => z1, + REFCLK2 => z1, + REFCLKSEL => z1, + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(3 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(7 downto 4) => OPEN4, + RXCHARISK(3 downto 0) => RXCHARISK, + RXCHARISK(7 downto 4) => OPEN4, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA(31 downto 0) => RXDATA, + RXDATA(63 downto 32) => OPEN32, + RXDISPERR(3 downto 0) => RXDISPERR, + RXDISPERR(7 downto 4) => OPEN4, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(3 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(7 downto 4) => OPEN4, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(3 downto 0) => RXRUNDISP, + RXRUNDISP(7 downto 4) => OPEN4, + TXBUFERR => TXBUFERR, + TXKERR(3 downto 0) => TXKERR, + TXKERR(7 downto 4) => OPEN4, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP(3 downto 0) => TXRUNDISP, + TXRUNDISP(7 downto 4) => OPEN4, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLKBSEL => REFCLKBSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(3 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(7 downto 4) => z4, + TXCHARDISPMODE(3 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(7 downto 4) => z4, + TXCHARDISPVAL(3 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(7 downto 4) => z4, + TXCHARISK(3 downto 0) => TXCHARISK, + TXCHARISK(7 downto 4) => z4, + TXDATA(31 downto 0) => TXDATA, + TXDATA(63 downto 32) => z32, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_OC192_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_oc192_8.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for OC192 I/O Standard 8 Byte Data +-- /___/ /\ Filename : GT10_OC192_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:09 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_OC192_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_OC192_8 is +generic ( + ALIGN_COMMA_WORD : integer := 1; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + MCOMMA_10B_VALUE : bit_vector := "0010101010"; + MCOMMA_DETECT : boolean := TRUE; + PCOMMA_10B_VALUE : bit_vector := "0010101010"; + PCOMMA_DETECT : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504c00208c9050d0068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDISPERR : out std_logic_vector(7 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(7 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(7 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(7 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLKBSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(7 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXDATA : in std_logic_vector(63 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_OC192_8; + +-- Architecture body -- + +architecture GT10_OC192_8_V of GT10_OC192_8 is + +signal z1 : std_ulogic := '0'; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + COMMA_10B_MASK => "0011111111", + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, + MCOMMA_10B_VALUE => MCOMMA_10B_VALUE, + MCOMMA_DETECT => MCOMMA_DETECT, + PCOMMA_10B_VALUE => PCOMMA_10B_VALUE, + PCOMMA_DETECT => PCOMMA_DETECT, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "15_64", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + REFCLK => z1, + REFCLK2 => z1, + REFCLKSEL => z1, + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA => RXCHARISCOMMA, + RXCHARISK => RXCHARISK, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA => RXDATA, + RXDISPERR => RXDISPERR, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE => RXNOTINTABLE, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP => RXRUNDISP, + TXBUFERR => TXBUFERR, + TXKERR => TXKERR, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP => TXRUNDISP, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLKBSEL => REFCLKBSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B => TXBYPASS8B10B, + TXCHARDISPMODE => TXCHARDISPMODE, + TXCHARDISPVAL => TXCHARDISPVAL, + TXCHARISK => TXCHARISK, + TXDATA => TXDATA, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_OC192_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_oc48_1.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for OC48 I/O Standard 1 Byte Data +-- /___/ /\ Filename : GT10_OC48_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:09 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_OC48_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_OC48_1 is +generic ( + ALIGN_COMMA_WORD : integer := 1; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + MCOMMA_10B_VALUE : bit_vector := "0010101010"; + MCOMMA_DETECT : boolean := TRUE; + PCOMMA_10B_VALUE : bit_vector := "0010101010"; + PCOMMA_DETECT : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd500b01300830680901040820"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_OC48_1; + +-- Architecture body -- + +architecture GT10_OC48_1_V of GT10_OC48_1 is + +signal OPEN7 : std_logic_vector(6 downto 0); +signal OPEN56 : std_logic_vector(55 downto 0); +signal z7 : std_logic_vector(6 downto 0) := "0000000"; +signal z56 : std_logic_vector(55 downto 0) := "00000000000000000000000000000000000000000000000000000000"; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + COMMA_10B_MASK => "0011111111", + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, + MCOMMA_10B_VALUE => MCOMMA_10B_VALUE, + MCOMMA_DETECT => MCOMMA_DETECT, + PCOMMA_10B_VALUE => PCOMMA_10B_VALUE, + PCOMMA_DETECT => PCOMMA_DETECT, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "31_8", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(7 downto 1) => OPEN7, + RXCHARISK(0 downto 0) => RXCHARISK, + RXCHARISK(7 downto 1) => OPEN7, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA(7 downto 0) => RXDATA, + RXDATA(63 downto 8) => OPEN56, + RXDISPERR(0 downto 0) => RXDISPERR, + RXDISPERR(7 downto 1) => OPEN7, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(7 downto 1) => OPEN7, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(0 downto 0) => RXRUNDISP, + RXRUNDISP(7 downto 1) => OPEN7, + TXBUFERR => TXBUFERR, + TXKERR(0 downto 0) => TXKERR, + TXKERR(7 downto 1) => OPEN7, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP(0 downto 0) => TXRUNDISP, + TXRUNDISP(7 downto 1) => OPEN7, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(7 downto 1) => z7, + TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(7 downto 1) => z7, + TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(7 downto 1) => z7, + TXCHARISK(0 downto 0) => TXCHARISK, + TXCHARISK(7 downto 1) => z7, + TXDATA(7 downto 0) => TXDATA, + TXDATA(63 downto 8) => z56, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_OC48_1_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_oc48_2.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for OC48 I/O Standard 2 Byte Data +-- /___/ /\ Filename : GT10_OC48_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:09 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_OC48_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_OC48_2 is +generic ( + ALIGN_COMMA_WORD : integer := 1; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + MCOMMA_10B_VALUE : bit_vector := "0010101010"; + MCOMMA_DETECT : boolean := TRUE; + PCOMMA_10B_VALUE : bit_vector := "0010101010"; + PCOMMA_DETECT : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00fc0d300b0f304830680901050820"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_OC48_2; + +-- Architecture body -- + +architecture GT10_OC48_2_V of GT10_OC48_2 is + +signal OPEN6 : std_logic_vector(5 downto 0); +signal OPEN48 : std_logic_vector(47 downto 0); +signal z6 : std_logic_vector(5 downto 0) := "000000"; +signal z48 : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + COMMA_10B_MASK => "0011111111", + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, + MCOMMA_10B_VALUE => MCOMMA_10B_VALUE, + MCOMMA_DETECT => MCOMMA_DETECT, + PCOMMA_10B_VALUE => PCOMMA_10B_VALUE, + PCOMMA_DETECT => PCOMMA_DETECT, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "31_16", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(7 downto 2) => OPEN6, + RXCHARISK(1 downto 0) => RXCHARISK, + RXCHARISK(7 downto 2) => OPEN6, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA(15 downto 0) => RXDATA, + RXDATA(63 downto 16) => OPEN48, + RXDISPERR(1 downto 0) => RXDISPERR, + RXDISPERR(7 downto 2) => OPEN6, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(7 downto 2) => OPEN6, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(1 downto 0) => RXRUNDISP, + RXRUNDISP(7 downto 2) => OPEN6, + TXBUFERR => TXBUFERR, + TXKERR(1 downto 0) => TXKERR, + TXKERR(7 downto 2) => OPEN6, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP(1 downto 0) => TXRUNDISP, + TXRUNDISP(7 downto 2) => OPEN6, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(7 downto 2) => z6, + TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(7 downto 2) => z6, + TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(7 downto 2) => z6, + TXCHARISK(1 downto 0) => TXCHARISK, + TXCHARISK(7 downto 2) => z6, + TXDATA(15 downto 0) => TXDATA, + TXDATA(63 downto 16) => z48, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_OC48_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_oc48_4.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for OC48 I/O Standard 4 Byte Data +-- /___/ /\ Filename : GT10_OC48_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:09 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_OC48_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_OC48_4 is +generic ( + ALIGN_COMMA_WORD : integer := 1; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + MCOMMA_10B_VALUE : bit_vector := "0010101010"; + MCOMMA_DETECT : boolean := TRUE; + PCOMMA_10B_VALUE : bit_vector := "0010101010"; + PCOMMA_DETECT : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd500b01304830680901050820"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_OC48_4; + +-- Architecture body -- + +architecture GT10_OC48_4_V of GT10_OC48_4 is + +signal OPEN4 : std_logic_vector(3 downto 0); +signal OPEN32 : std_logic_vector(31 downto 0); +signal z4 : std_logic_vector(3 downto 0) := "0000"; +signal z32 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + COMMA_10B_MASK => "0011111111", + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, + MCOMMA_10B_VALUE => MCOMMA_10B_VALUE, + MCOMMA_DETECT => MCOMMA_DETECT, + PCOMMA_10B_VALUE => PCOMMA_10B_VALUE, + PCOMMA_DETECT => PCOMMA_DETECT, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "31_32", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(3 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(7 downto 4) => OPEN4, + RXCHARISK(3 downto 0) => RXCHARISK, + RXCHARISK(7 downto 4) => OPEN4, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA(31 downto 0) => RXDATA, + RXDATA(63 downto 32) => OPEN32, + RXDISPERR(3 downto 0) => RXDISPERR, + RXDISPERR(7 downto 4) => OPEN4, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(3 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(7 downto 4) => OPEN4, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(3 downto 0) => RXRUNDISP, + RXRUNDISP(7 downto 4) => OPEN4, + TXBUFERR => TXBUFERR, + TXKERR(3 downto 0) => TXKERR, + TXKERR(7 downto 4) => OPEN4, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP(3 downto 0) => TXRUNDISP, + TXRUNDISP(7 downto 4) => OPEN4, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(3 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(7 downto 4) => z4, + TXCHARDISPMODE(3 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(7 downto 4) => z4, + TXCHARDISPVAL(3 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(7 downto 4) => z4, + TXCHARISK(3 downto 0) => TXCHARISK, + TXCHARISK(7 downto 4) => z4, + TXDATA(31 downto 0) => TXDATA, + TXDATA(63 downto 32) => z32, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_OC48_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_pci_express_1.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for PCI_EXPRESS I/O Standard 1 Byte Data +-- /___/ /\ Filename : GT10_PCI_EXPRESS_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:09 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_PCI_EXPRESS_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_PCI_EXPRESS_1 is +generic ( + ALIGN_COMMA_WORD : integer := 2; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 2; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 2; + CLK_CORRECT_USE : boolean := TRUE; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd500b0132263068090104a620"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_PCI_EXPRESS_1; + +-- Architecture body -- + +architecture GT10_PCI_EXPRESS_1_V of GT10_PCI_EXPRESS_1 is + +signal OPEN7 : std_logic_vector(6 downto 0); +signal OPEN56 : std_logic_vector(55 downto 0); +signal z7 : std_logic_vector(6 downto 0) := "0000000"; +signal z56 : std_logic_vector(55 downto 0) := "00000000000000000000000000000000000000000000000000000000"; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00110111100", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00001001010", + CHAN_BOND_SEQ_1_4 => "00001001010", + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_SEQ_2_1 => "00110111100", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00001000101", + CHAN_BOND_SEQ_2_4 => "00001000101", + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, + CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, + CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_SEQ_1_1 => "00100011100", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, + CLK_CORRECT_USE => CLK_CORRECT_USE, + COMMA_10B_MASK => "0001111111", + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, + DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, + MCOMMA_10B_VALUE => "1010000011", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0101111100", + PCOMMA_DETECT => TRUE, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "28_10", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(7 downto 1) => OPEN7, + RXCHARISK(0 downto 0) => RXCHARISK, + RXCHARISK(7 downto 1) => OPEN7, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA(7 downto 0) => RXDATA, + RXDATA(63 downto 8) => OPEN56, + RXDISPERR(0 downto 0) => RXDISPERR, + RXDISPERR(7 downto 1) => OPEN7, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(7 downto 1) => OPEN7, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(0 downto 0) => RXRUNDISP, + RXRUNDISP(7 downto 1) => OPEN7, + TXBUFERR => TXBUFERR, + TXKERR(0 downto 0) => TXKERR, + TXKERR(7 downto 1) => OPEN7, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP(0 downto 0) => TXRUNDISP, + TXRUNDISP(7 downto 1) => OPEN7, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(7 downto 1) => z7, + TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(7 downto 1) => z7, + TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(7 downto 1) => z7, + TXCHARISK(0 downto 0) => TXCHARISK, + TXCHARISK(7 downto 1) => z7, + TXDATA(7 downto 0) => TXDATA, + TXDATA(63 downto 8) => z56, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_PCI_EXPRESS_1_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_pci_express_2.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for PCI_EXPRESS I/O Standard 2 Byte Data +-- /___/ /\ Filename : GT10_PCI_EXPRESS_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:09 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_PCI_EXPRESS_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_PCI_EXPRESS_2 is +generic ( + ALIGN_COMMA_WORD : integer := 2; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 2; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 2; + CLK_CORRECT_USE : boolean := TRUE; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00fc0d300b0f32663068090105a620"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_PCI_EXPRESS_2; + +-- Architecture body -- + +architecture GT10_PCI_EXPRESS_2_V of GT10_PCI_EXPRESS_2 is + +signal OPEN6 : std_logic_vector(5 downto 0); +signal OPEN48 : std_logic_vector(47 downto 0); +signal z6 : std_logic_vector(5 downto 0) := "000000"; +signal z48 : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00110111100", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00001001010", + CHAN_BOND_SEQ_1_4 => "00001001010", + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_SEQ_2_1 => "00110111100", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00001000101", + CHAN_BOND_SEQ_2_4 => "00001000101", + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, + CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, + CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_SEQ_1_1 => "00100011100", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, + CLK_CORRECT_USE => CLK_CORRECT_USE, + COMMA_10B_MASK => "0001111111", + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, + DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, + MCOMMA_10B_VALUE => "1010000011", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0101111100", + PCOMMA_DETECT => TRUE, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "28_20", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(7 downto 2) => OPEN6, + RXCHARISK(1 downto 0) => RXCHARISK, + RXCHARISK(7 downto 2) => OPEN6, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA(15 downto 0) => RXDATA, + RXDATA(63 downto 16) => OPEN48, + RXDISPERR(1 downto 0) => RXDISPERR, + RXDISPERR(7 downto 2) => OPEN6, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(7 downto 2) => OPEN6, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(1 downto 0) => RXRUNDISP, + RXRUNDISP(7 downto 2) => OPEN6, + TXBUFERR => TXBUFERR, + TXKERR(1 downto 0) => TXKERR, + TXKERR(7 downto 2) => OPEN6, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP(1 downto 0) => TXRUNDISP, + TXRUNDISP(7 downto 2) => OPEN6, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(7 downto 2) => z6, + TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(7 downto 2) => z6, + TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(7 downto 2) => z6, + TXCHARISK(1 downto 0) => TXCHARISK, + TXCHARISK(7 downto 2) => z6, + TXDATA(15 downto 0) => TXDATA, + TXDATA(63 downto 16) => z48, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_PCI_EXPRESS_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_pci_express_4.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for PCI_EXPRESS I/O Standard 4 Byte Data +-- /___/ /\ Filename : GT10_PCI_EXPRESS_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:09 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_PCI_EXPRESS_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_PCI_EXPRESS_4 is +generic ( + ALIGN_COMMA_WORD : integer := 2; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 2; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 2; + CLK_CORRECT_USE : boolean := TRUE; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd500b0132663068090105a620"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_PCI_EXPRESS_4; + +-- Architecture body -- + +architecture GT10_PCI_EXPRESS_4_V of GT10_PCI_EXPRESS_4 is + +signal OPEN4 : std_logic_vector(3 downto 0); +signal OPEN32 : std_logic_vector(31 downto 0); +signal z4 : std_logic_vector(3 downto 0) := "0000"; +signal z32 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00110111100", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00001001010", + CHAN_BOND_SEQ_1_4 => "00001001010", + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_SEQ_2_1 => "00110111100", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00001000101", + CHAN_BOND_SEQ_2_4 => "00001000101", + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, + CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, + CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_SEQ_1_1 => "00100011100", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, + CLK_CORRECT_USE => CLK_CORRECT_USE, + COMMA_10B_MASK => "0001111111", + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, + DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, + MCOMMA_10B_VALUE => "1010000011", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0101111100", + PCOMMA_DETECT => TRUE, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "28_40", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(3 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(7 downto 4) => OPEN4, + RXCHARISK(3 downto 0) => RXCHARISK, + RXCHARISK(7 downto 4) => OPEN4, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA(31 downto 0) => RXDATA, + RXDATA(63 downto 32) => OPEN32, + RXDISPERR(3 downto 0) => RXDISPERR, + RXDISPERR(7 downto 4) => OPEN4, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(3 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(7 downto 4) => OPEN4, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(3 downto 0) => RXRUNDISP, + RXRUNDISP(7 downto 4) => OPEN4, + TXBUFERR => TXBUFERR, + TXKERR(3 downto 0) => TXKERR, + TXKERR(7 downto 4) => OPEN4, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP(3 downto 0) => TXRUNDISP, + TXRUNDISP(7 downto 4) => OPEN4, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(3 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(7 downto 4) => z4, + TXCHARDISPMODE(3 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(7 downto 4) => z4, + TXCHARDISPVAL(3 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(7 downto 4) => z4, + TXCHARISK(3 downto 0) => TXCHARISK, + TXCHARISK(7 downto 4) => z4, + TXDATA(31 downto 0) => TXDATA, + TXDATA(63 downto 32) => z32, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_PCI_EXPRESS_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10.vhd,v 1.8 2006/03/16 00:57:41 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for High-Speed I/O for Simulation Model +-- /___/ /\ Filename : GT10.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:07 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10 is +generic ( + in_delay : time := 0 ps; + out_delay : VitalDelayType01 := (100 ps, 100 ps); + + ALIGN_COMMA_WORD : integer := 1; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 1; + CHAN_BOND_64B66B_SV : boolean := FALSE; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 1; + CLK_CORRECT_USE : boolean := TRUE; + COMMA_10B_MASK : bit_vector := "0001111111"; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + MCOMMA_10B_VALUE : bit_vector := "1010000011"; + MCOMMA_DETECT : boolean := TRUE; + PCOMMA_10B_VALUE : bit_vector := "0101111100"; + PCOMMA_DETECT : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED : string := "0_32"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDISPERR : out std_logic_vector(7 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(7 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(7 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(7 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(7 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXDATA : in std_logic_vector(63 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10; + +-- Architecture body -- + +architecture GT10_V of GT10 is +component GT10_SWIFT_BUS + port ( + CHBONDDONE : out STD_ULOGIC; + CHBONDO : out STD_LOGIC_VECTOR(4 downto 0); + PMARXLOCK : out STD_ULOGIC; + RXBUFSTATUS : out STD_LOGIC_VECTOR(1 downto 0); + RXCHARISCOMMA : out STD_LOGIC_VECTOR(7 downto 0); + RXCHARISK : out STD_LOGIC_VECTOR(7 downto 0); + RXCLKCORCNT : out STD_LOGIC_VECTOR(2 downto 0); + RXCOMMADET : out STD_ULOGIC; + RXDATA : out STD_LOGIC_VECTOR(63 downto 0); + RXDISPERR : out STD_LOGIC_VECTOR(7 downto 0); + RXLOSSOFSYNC : out STD_LOGIC_VECTOR(1 downto 0); + RXNOTINTABLE : out STD_LOGIC_VECTOR(7 downto 0); + RXREALIGN : out STD_ULOGIC; + RXRECCLK : out STD_ULOGIC; + RXRUNDISP : out STD_LOGIC_VECTOR(7 downto 0); + TXBUFERR : out STD_ULOGIC; + TXKERR : out STD_LOGIC_VECTOR(7 downto 0); + TXN : out STD_ULOGIC; + TXOUTCLK : out STD_ULOGIC; + TXP : out STD_ULOGIC; + TXRUNDISP : out STD_LOGIC_VECTOR(7 downto 0); + + BREFCLKNIN : in STD_ULOGIC; + BREFCLKPIN : in STD_ULOGIC; + CHBONDI : in STD_LOGIC_VECTOR(4 downto 0); + ENCHANSYNC : in STD_ULOGIC; + ENMCOMMAALIGN : in STD_ULOGIC; + ENPCOMMAALIGN : in STD_ULOGIC; + LOOPBACK : in STD_LOGIC_VECTOR(1 downto 0); + PMAINIT : in STD_ULOGIC; + PMAREGADDR : in STD_LOGIC_VECTOR(5 downto 0); + PMAREGDATAIN : in STD_LOGIC_VECTOR(7 downto 0); + PMAREGRW : in STD_ULOGIC; + PMAREGSTROBE : in STD_ULOGIC; + PMARXLOCKSEL : in STD_LOGIC_VECTOR(1 downto 0); + POWERDOWN : in STD_ULOGIC; + REFCLK : in STD_ULOGIC; + REFCLK2 : in STD_ULOGIC; + REFCLKBSEL : in STD_ULOGIC; + REFCLKSEL : in STD_ULOGIC; + RXBLOCKSYNC64B66BUSE : in STD_ULOGIC; + RXCOMMADETUSE : in STD_ULOGIC; + RXDATAWIDTH : in STD_LOGIC_VECTOR(1 downto 0); + RXDEC64B66BUSE : in STD_ULOGIC; + RXDEC8B10BUSE : in STD_ULOGIC; + RXDESCRAM64B66BUSE : in STD_ULOGIC; + RXIGNOREBTF : in STD_ULOGIC; + RXINTDATAWIDTH : in STD_LOGIC_VECTOR(1 downto 0); + RXN : in STD_ULOGIC; + RXP : in STD_ULOGIC; + RXPOLARITY : in STD_ULOGIC; + RXRESET : in STD_ULOGIC; + RXSLIDE : in STD_ULOGIC; + RXUSRCLK : in STD_ULOGIC; + RXUSRCLK2 : in STD_ULOGIC; + TXBYPASS8B10B : in STD_LOGIC_VECTOR(7 downto 0); + TXCHARDISPMODE : in STD_LOGIC_VECTOR(7 downto 0); + TXCHARDISPVAL : in STD_LOGIC_VECTOR(7 downto 0); + TXCHARISK : in STD_LOGIC_VECTOR(7 downto 0); + TXDATA : in STD_LOGIC_VECTOR(63 downto 0); + TXDATAWIDTH : in STD_LOGIC_VECTOR(1 downto 0); + TXENC64B66BUSE : in STD_ULOGIC; + TXENC8B10BUSE : in STD_ULOGIC; + TXGEARBOX64B66BUSE : in STD_ULOGIC; + TXINHIBIT : in STD_ULOGIC; + TXINTDATAWIDTH : in STD_LOGIC_VECTOR(1 downto 0); + TXPOLARITY : in STD_ULOGIC; + TXRESET : in STD_ULOGIC; + TXSCRAM64B66BUSE : in STD_ULOGIC; + TXUSRCLK : in STD_ULOGIC; + TXUSRCLK2 : in STD_ULOGIC; + ALIGN_COMMA_WORD : in STD_LOGIC_VECTOR(1 downto 0); + CHAN_BOND_LIMIT : in STD_LOGIC_VECTOR(5 downto 0); + CHAN_BOND_MODE : in STD_LOGIC_VECTOR(1 downto 0); + CHAN_BOND_ONE_SHOT : in STD_ULOGIC; + CHAN_BOND_SEQ_1_1 : in STD_LOGIC_VECTOR(10 downto 0); + CHAN_BOND_SEQ_1_2 : in STD_LOGIC_VECTOR(10 downto 0); + CHAN_BOND_SEQ_1_3 : in STD_LOGIC_VECTOR(10 downto 0); + CHAN_BOND_SEQ_1_4 : in STD_LOGIC_VECTOR(10 downto 0); + CHAN_BOND_SEQ_1_MASK : in STD_LOGIC_VECTOR(3 downto 0); + CHAN_BOND_SEQ_2_1 : in STD_LOGIC_VECTOR(10 downto 0); + CHAN_BOND_SEQ_2_2 : in STD_LOGIC_VECTOR(10 downto 0); + CHAN_BOND_SEQ_2_3 : in STD_LOGIC_VECTOR(10 downto 0); + CHAN_BOND_SEQ_2_4 : in STD_LOGIC_VECTOR(10 downto 0); + CHAN_BOND_SEQ_2_MASK : in STD_LOGIC_VECTOR(3 downto 0); + CHAN_BOND_SEQ_2_USE : in STD_ULOGIC; + CHAN_BOND_SEQ_LEN : in STD_LOGIC_VECTOR(2 downto 0); + CHAN_BOND_64B66B_SV : in std_ulogic; + CLK_COR_8B10B_DE : in STD_ULOGIC; + CLK_COR_MAX_LAT : in STD_LOGIC_VECTOR(5 downto 0); + CLK_COR_MIN_LAT : in STD_LOGIC_VECTOR(5 downto 0); + CLK_COR_SEQ_1_1 : in STD_LOGIC_VECTOR(10 downto 0); + CLK_COR_SEQ_1_2 : in STD_LOGIC_VECTOR(10 downto 0); + CLK_COR_SEQ_1_3 : in STD_LOGIC_VECTOR(10 downto 0); + CLK_COR_SEQ_1_4 : in STD_LOGIC_VECTOR(10 downto 0); + CLK_COR_SEQ_1_MASK : in STD_LOGIC_VECTOR(3 downto 0); + CLK_COR_SEQ_2_1 : in STD_LOGIC_VECTOR(10 downto 0); + CLK_COR_SEQ_2_2 : in STD_LOGIC_VECTOR(10 downto 0); + CLK_COR_SEQ_2_3 : in STD_LOGIC_VECTOR(10 downto 0); + CLK_COR_SEQ_2_4 : in STD_LOGIC_VECTOR(10 downto 0); + CLK_COR_SEQ_2_MASK : in STD_LOGIC_VECTOR(3 downto 0); + CLK_COR_SEQ_2_USE : in STD_ULOGIC; + CLK_COR_SEQ_DROP : in STD_ULOGIC; + CLK_COR_SEQ_LEN : in STD_LOGIC_VECTOR(2 downto 0); + CLK_CORRECT_USE : in STD_ULOGIC; + COMMA_10B_MASK : in STD_LOGIC_VECTOR(9 downto 0); + DEC_MCOMMA_DETECT : in STD_ULOGIC; + DEC_PCOMMA_DETECT : in STD_ULOGIC; + DEC_VALID_COMMA_ONLY : in STD_ULOGIC; + MCOMMA_10B_VALUE : in STD_LOGIC_VECTOR(9 downto 0); + MCOMMA_DETECT : in STD_ULOGIC; + PCOMMA_10B_VALUE : in STD_LOGIC_VECTOR(9 downto 0); + PCOMMA_DETECT : in STD_ULOGIC; + PMA_SPEED : in STD_LOGIC_VECTOR(119 downto 0); + PMA_PWR_CNTRL : in STD_LOGIC_VECTOR(7 downto 0); + RX_BUFFER_USE : in STD_ULOGIC; + RX_LOS_INVALID_INCR : in STD_LOGIC_VECTOR(7 downto 0); + RX_LOS_THRESHOLD : in STD_LOGIC_VECTOR(7 downto 0); + RX_LOSS_OF_SYNC_FSM : in STD_ULOGIC; + SH_CNT_MAX : in STD_LOGIC_VECTOR(7 downto 0); + SH_INVALID_CNT_MAX : in STD_LOGIC_VECTOR(7 downto 0); + TX_BUFFER_USE : in STD_ULOGIC; + GSR : in STD_ULOGIC + ); +end component; +-- Attribute-to-Cell mapping signals + signal ALIGN_COMMA_WORD_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_LIMIT_BINARY : std_logic_vector(5 downto 0); + signal CHAN_BOND_MODE_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_ONE_SHOT_BINARY : std_ulogic; + signal CHAN_BOND_SEQ_1_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1); + signal CHAN_BOND_SEQ_1_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2); + signal CHAN_BOND_SEQ_1_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3); + signal CHAN_BOND_SEQ_1_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4); + signal CHAN_BOND_SEQ_1_MASK_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_MASK); + signal CHAN_BOND_SEQ_2_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1); + signal CHAN_BOND_SEQ_2_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2); + signal CHAN_BOND_SEQ_2_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3); + signal CHAN_BOND_SEQ_2_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4); + signal CHAN_BOND_SEQ_2_MASK_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_MASK); + signal CHAN_BOND_SEQ_2_USE_BINARY : std_ulogic; + signal CHAN_BOND_SEQ_LEN_BINARY : std_logic_vector(2 downto 0); + signal CHAN_BOND_64B66B_SV_BINARY : std_ulogic; + signal CLK_COR_8B10B_DE_BINARY : std_ulogic; + signal CLK_COR_MAX_LAT_BINARY : std_logic_vector(5 downto 0); + signal CLK_COR_MIN_LAT_BINARY : std_logic_vector(5 downto 0); + signal CLK_COR_SEQ_1_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1); + signal CLK_COR_SEQ_1_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2); + signal CLK_COR_SEQ_1_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3); + signal CLK_COR_SEQ_1_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4); + signal CLK_COR_SEQ_1_MASK_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_MASK); + signal CLK_COR_SEQ_2_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1); + signal CLK_COR_SEQ_2_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2); + signal CLK_COR_SEQ_2_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3); + signal CLK_COR_SEQ_2_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4); + signal CLK_COR_SEQ_2_MASK_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_MASK); + signal CLK_COR_SEQ_2_USE_BINARY : std_ulogic; + signal CLK_COR_SEQ_DROP_BINARY : std_ulogic; + signal CLK_COR_SEQ_LEN_BINARY : std_logic_vector(2 downto 0); + signal CLK_CORRECT_USE_BINARY : std_ulogic; + signal COMMA_10B_MASK_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(COMMA_10B_MASK); + signal DEC_MCOMMA_DETECT_BINARY : std_ulogic; + signal DEC_PCOMMA_DETECT_BINARY : std_ulogic; + signal DEC_VALID_COMMA_ONLY_BINARY : std_ulogic; + signal MCOMMA_10B_VALUE_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(MCOMMA_10B_VALUE); + signal MCOMMA_DETECT_BINARY : std_ulogic; + signal PCOMMA_10B_VALUE_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(PCOMMA_10B_VALUE); + signal PCOMMA_DETECT_BINARY : std_ulogic; + signal PMA_PWR_CNTRL_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMA_PWR_CNTRL); + signal PMA_SPEED_BINARY : std_logic_vector(119 downto 0); + signal RX_BUFFER_USE_BINARY : std_ulogic; + signal RX_LOS_INVALID_INCR_BINARY : std_logic_vector(7 downto 0); + signal RX_LOS_THRESHOLD_BINARY : std_logic_vector(7 downto 0); + signal RX_LOSS_OF_SYNC_FSM_BINARY : std_ulogic; + signal SH_CNT_MAX_BINARY : std_logic_vector(7 downto 0); + signal SH_INVALID_CNT_MAX_BINARY : std_logic_vector(7 downto 0); + signal TX_BUFFER_USE_BINARY : std_ulogic; + +-- Input/Output Pin signals + signal CHBONDDONE_out : std_ulogic; + signal CHBONDO_out : std_logic_vector(4 downto 0); + signal PMARXLOCK_out : std_ulogic; + signal RXBUFSTATUS_out : std_logic_vector(1 downto 0); + signal RXCHARISCOMMA_out : std_logic_vector(7 downto 0); + signal RXCHARISK_out : std_logic_vector(7 downto 0); + signal RXCLKCORCNT_out : std_logic_vector(2 downto 0); + signal RXCOMMADET_out : std_ulogic; + signal RXDATA_out : std_logic_vector(63 downto 0); + signal RXDISPERR_out : std_logic_vector(7 downto 0); + signal RXLOSSOFSYNC_out : std_logic_vector(1 downto 0); + signal RXNOTINTABLE_out : std_logic_vector(7 downto 0); + signal RXREALIGN_out : std_ulogic; + signal RXRECCLK_out : std_ulogic; + signal RXRUNDISP_out : std_logic_vector(7 downto 0); + signal TXBUFERR_out : std_ulogic; + signal TXKERR_out : std_logic_vector(7 downto 0); + signal TXN_out : std_ulogic; + signal TXOUTCLK_out : std_ulogic; + signal TXP_out : std_ulogic; + signal TXRUNDISP_out : std_logic_vector(7 downto 0); + + signal BREFCLKNIN_ipd : std_ulogic; + signal BREFCLKPIN_ipd : std_ulogic; + signal CHBONDI_ipd : std_logic_vector(4 downto 0); + signal ENCHANSYNC_ipd : std_ulogic; + signal ENMCOMMAALIGN_ipd : std_ulogic; + signal ENPCOMMAALIGN_ipd : std_ulogic; + signal LOOPBACK_ipd : std_logic_vector(1 downto 0); + signal PMAINIT_ipd : std_ulogic; + signal PMAREGADDR_ipd : std_logic_vector(5 downto 0); + signal PMAREGDATAIN_ipd : std_logic_vector(7 downto 0); + signal PMAREGRW_ipd : std_ulogic; + signal PMAREGSTROBE_ipd : std_ulogic; + signal PMARXLOCKSEL_ipd : std_logic_vector(1 downto 0); + signal POWERDOWN_ipd : std_ulogic; + signal REFCLK_ipd : std_ulogic; + signal REFCLK2_ipd : std_ulogic; + signal REFCLKBSEL_ipd : std_ulogic; + signal REFCLKSEL_ipd : std_ulogic; + signal RXBLOCKSYNC64B66BUSE_ipd : std_ulogic; + signal RXCOMMADETUSE_ipd : std_ulogic; + signal RXDATAWIDTH_ipd : std_logic_vector(1 downto 0); + signal RXDEC64B66BUSE_ipd : std_ulogic; + signal RXDEC8B10BUSE_ipd : std_ulogic; + signal RXDESCRAM64B66BUSE_ipd : std_ulogic; + signal RXIGNOREBTF_ipd : std_ulogic; + signal RXINTDATAWIDTH_ipd : std_logic_vector(1 downto 0); + signal RXN_ipd : std_ulogic; + signal RXP_ipd : std_ulogic; + signal RXPOLARITY_ipd : std_ulogic; + signal RXRESET_ipd : std_ulogic; + signal RXSLIDE_ipd : std_ulogic; + signal RXUSRCLK_ipd : std_ulogic; + signal RXUSRCLK2_ipd : std_ulogic; + signal TXBYPASS8B10B_ipd : std_logic_vector(7 downto 0); + signal TXCHARDISPMODE_ipd : std_logic_vector(7 downto 0); + signal TXCHARDISPVAL_ipd : std_logic_vector(7 downto 0); + signal TXCHARISK_ipd : std_logic_vector(7 downto 0); + signal TXDATA_ipd : std_logic_vector(63 downto 0); + signal TXDATAWIDTH_ipd : std_logic_vector(1 downto 0); + signal TXENC64B66BUSE_ipd : std_ulogic; + signal TXENC8B10BUSE_ipd : std_ulogic; + signal TXGEARBOX64B66BUSE_ipd : std_ulogic; + signal TXINHIBIT_ipd : std_ulogic; + signal TXINTDATAWIDTH_ipd : std_logic_vector(1 downto 0); + signal TXPOLARITY_ipd : std_ulogic; + signal TXRESET_ipd : std_ulogic; + signal TXSCRAM64B66BUSE_ipd : std_ulogic; + signal TXUSRCLK_ipd : std_ulogic; + signal TXUSRCLK2_ipd : std_ulogic; + + +begin + +BREFCLKNIN_ipd <= BREFCLKNIN after in_delay; +BREFCLKPIN_ipd <= BREFCLKPIN after in_delay; +CHBONDI_ipd <= CHBONDI after in_delay; +ENCHANSYNC_ipd <= ENCHANSYNC after in_delay; +ENMCOMMAALIGN_ipd <= ENMCOMMAALIGN after in_delay; +ENPCOMMAALIGN_ipd <= ENPCOMMAALIGN after in_delay; +LOOPBACK_ipd <= LOOPBACK after in_delay; +PMAINIT_ipd <= PMAINIT after in_delay; +PMAREGADDR_ipd <= PMAREGADDR after in_delay; +PMAREGDATAIN_ipd <= PMAREGDATAIN after in_delay; +PMAREGRW_ipd <= PMAREGRW after in_delay; +PMAREGSTROBE_ipd <= PMAREGSTROBE after in_delay; +PMARXLOCKSEL_ipd <= PMARXLOCKSEL after in_delay; +POWERDOWN_ipd <= POWERDOWN after in_delay; +REFCLK_ipd <= REFCLK after in_delay; +REFCLK2_ipd <= REFCLK2 after in_delay; +REFCLKBSEL_ipd <= REFCLKBSEL after in_delay; +REFCLKSEL_ipd <= REFCLKSEL after in_delay; +RXBLOCKSYNC64B66BUSE_ipd <= RXBLOCKSYNC64B66BUSE after in_delay; +RXCOMMADETUSE_ipd <= RXCOMMADETUSE after in_delay; +RXDATAWIDTH_ipd <= RXDATAWIDTH after in_delay; +RXDEC64B66BUSE_ipd <= RXDEC64B66BUSE after in_delay; +RXDEC8B10BUSE_ipd <= RXDEC8B10BUSE after in_delay; +RXDESCRAM64B66BUSE_ipd <= RXDESCRAM64B66BUSE after in_delay; +RXIGNOREBTF_ipd <= RXIGNOREBTF after in_delay; +RXINTDATAWIDTH_ipd <= RXINTDATAWIDTH after in_delay; +RXN_ipd <= RXN after in_delay; +RXP_ipd <= RXP after in_delay; +RXPOLARITY_ipd <= RXPOLARITY after in_delay; +RXRESET_ipd <= RXRESET after in_delay; +RXSLIDE_ipd <= RXSLIDE after in_delay; +RXUSRCLK_ipd <= RXUSRCLK after in_delay; +RXUSRCLK2_ipd <= RXUSRCLK2 after in_delay; +TXBYPASS8B10B_ipd <= TXBYPASS8B10B after in_delay; +TXCHARDISPMODE_ipd <= TXCHARDISPMODE after in_delay; +TXCHARDISPVAL_ipd <= TXCHARDISPVAL after in_delay; +TXCHARISK_ipd <= TXCHARISK after in_delay; +TXDATA_ipd <= TXDATA after in_delay; +TXDATAWIDTH_ipd <= TXDATAWIDTH after in_delay; +TXENC64B66BUSE_ipd <= TXENC64B66BUSE after in_delay; +TXENC8B10BUSE_ipd <= TXENC8B10BUSE after in_delay; +TXGEARBOX64B66BUSE_ipd <= TXGEARBOX64B66BUSE after in_delay; +TXINHIBIT_ipd <= TXINHIBIT after in_delay; +TXINTDATAWIDTH_ipd <= TXINTDATAWIDTH after in_delay; +TXPOLARITY_ipd <= TXPOLARITY after in_delay; +TXRESET_ipd <= TXRESET after in_delay; +TXSCRAM64B66BUSE_ipd <= TXSCRAM64B66BUSE after in_delay; +TXUSRCLK_ipd <= TXUSRCLK after in_delay; +TXUSRCLK2_ipd <= TXUSRCLK2 after in_delay; + + gt10_swift_bw_1 : GT10_SWIFT_BUS + port map ( + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD_BINARY, + BREFCLKNIN => BREFCLKNIN_ipd, + BREFCLKPIN => BREFCLKPIN_ipd, + CHAN_BOND_64B66B_SV => CHAN_BOND_64B66B_SV_BINARY, + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT_BINARY, + CHAN_BOND_MODE => CHAN_BOND_MODE_BINARY, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT_BINARY, + CHAN_BOND_SEQ_1_1 => CHAN_BOND_SEQ_1_1_BINARY, + CHAN_BOND_SEQ_1_2 => CHAN_BOND_SEQ_1_2_BINARY, + CHAN_BOND_SEQ_1_3 => CHAN_BOND_SEQ_1_3_BINARY, + CHAN_BOND_SEQ_1_4 => CHAN_BOND_SEQ_1_4_BINARY, + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK_BINARY, + CHAN_BOND_SEQ_2_1 => CHAN_BOND_SEQ_2_1_BINARY, + CHAN_BOND_SEQ_2_2 => CHAN_BOND_SEQ_2_2_BINARY, + CHAN_BOND_SEQ_2_3 => CHAN_BOND_SEQ_2_3_BINARY, + CHAN_BOND_SEQ_2_4 => CHAN_BOND_SEQ_2_4_BINARY, + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK_BINARY, + CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE_BINARY, + CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN_BINARY, + CHBONDDONE => CHBONDDONE_out, + CHBONDI => CHBONDI_ipd, + CHBONDO => CHBONDO_out, + CLK_CORRECT_USE => CLK_CORRECT_USE_BINARY, + CLK_COR_8B10B_DE => CLK_COR_8B10B_DE_BINARY, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT_BINARY, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT_BINARY, + CLK_COR_SEQ_1_1 => CLK_COR_SEQ_1_1_BINARY, + CLK_COR_SEQ_1_2 => CLK_COR_SEQ_1_2_BINARY, + CLK_COR_SEQ_1_3 => CLK_COR_SEQ_1_3_BINARY, + CLK_COR_SEQ_1_4 => CLK_COR_SEQ_1_4_BINARY, + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK_BINARY, + CLK_COR_SEQ_2_1 => CLK_COR_SEQ_2_1_BINARY, + CLK_COR_SEQ_2_2 => CLK_COR_SEQ_2_2_BINARY, + CLK_COR_SEQ_2_3 => CLK_COR_SEQ_2_3_BINARY, + CLK_COR_SEQ_2_4 => CLK_COR_SEQ_2_4_BINARY, + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK_BINARY, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE_BINARY, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP_BINARY, + CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN_BINARY, + COMMA_10B_MASK => COMMA_10B_MASK_BINARY, + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT_BINARY, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT_BINARY, + DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY_BINARY, + ENCHANSYNC => ENCHANSYNC_ipd, + ENMCOMMAALIGN => ENMCOMMAALIGN_ipd, + ENPCOMMAALIGN => ENPCOMMAALIGN_ipd, + GSR => GSR, + LOOPBACK => LOOPBACK_ipd, + MCOMMA_10B_VALUE => MCOMMA_10B_VALUE_BINARY, + MCOMMA_DETECT => MCOMMA_DETECT_BINARY, + PCOMMA_10B_VALUE => PCOMMA_10B_VALUE_BINARY, + PCOMMA_DETECT => PCOMMA_DETECT_BINARY, + PMAINIT => PMAINIT_ipd, + PMAREGADDR => PMAREGADDR_ipd, + PMAREGDATAIN => PMAREGDATAIN_ipd, + PMAREGRW => PMAREGRW_ipd, + PMAREGSTROBE => PMAREGSTROBE_ipd, + PMARXLOCK => PMARXLOCK_out, + PMARXLOCKSEL => PMARXLOCKSEL_ipd, + PMA_PWR_CNTRL => PMA_PWR_CNTRL_BINARY, + PMA_SPEED => PMA_SPEED_BINARY, + POWERDOWN => POWERDOWN_ipd, + REFCLK => REFCLK_ipd, + REFCLK2 => REFCLK2_ipd, + REFCLKBSEL => REFCLKBSEL_ipd, + REFCLKSEL => REFCLKSEL_ipd, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE_ipd, + RXBUFSTATUS => RXBUFSTATUS_out, + RXCHARISCOMMA => RXCHARISCOMMA_out, + RXCHARISK => RXCHARISK_out, + RXCLKCORCNT => RXCLKCORCNT_out, + RXCOMMADET => RXCOMMADET_out, + RXCOMMADETUSE => RXCOMMADETUSE_ipd, + RXDATA => RXDATA_out, + RXDATAWIDTH => RXDATAWIDTH_ipd, + RXDEC64B66BUSE => RXDEC64B66BUSE_ipd, + RXDEC8B10BUSE => RXDEC8B10BUSE_ipd, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE_ipd, + RXDISPERR => RXDISPERR_out, + RXIGNOREBTF => RXIGNOREBTF_ipd, + RXINTDATAWIDTH => RXINTDATAWIDTH_ipd, + RXLOSSOFSYNC => RXLOSSOFSYNC_out, + RXN => RXN_ipd, + RXNOTINTABLE => RXNOTINTABLE_out, + RXP => RXP_ipd, + RXPOLARITY => RXPOLARITY_ipd, + RXREALIGN => RXREALIGN_out, + RXRECCLK => RXRECCLK_out, + RXRESET => RXRESET_ipd, + RXRUNDISP => RXRUNDISP_out, + RXSLIDE => RXSLIDE_ipd, + RXUSRCLK => RXUSRCLK_ipd, + RXUSRCLK2 => RXUSRCLK2_ipd, + RX_BUFFER_USE => RX_BUFFER_USE_BINARY, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM_BINARY, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR_BINARY, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD_BINARY, + SH_CNT_MAX => SH_CNT_MAX_BINARY, + SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX_BINARY, + TXBUFERR => TXBUFERR_out, + TXBYPASS8B10B => TXBYPASS8B10B_ipd, + TXCHARDISPMODE => TXCHARDISPMODE_ipd, + TXCHARDISPVAL => TXCHARDISPVAL_ipd, + TXCHARISK => TXCHARISK_ipd, + TXDATA => TXDATA_ipd, + TXDATAWIDTH => TXDATAWIDTH_ipd, + TXENC64B66BUSE => TXENC64B66BUSE_ipd, + TXENC8B10BUSE => TXENC8B10BUSE_ipd, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE_ipd, + TXINHIBIT => TXINHIBIT_ipd, + TXINTDATAWIDTH => TXINTDATAWIDTH_ipd, + TXKERR => TXKERR_out, + TXN => TXN_out, + TXOUTCLK => TXOUTCLK_out, + TXP => TXP_out, + TXPOLARITY => TXPOLARITY_ipd, + TXRESET => TXRESET_ipd, + TXRUNDISP => TXRUNDISP_out, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE_ipd, + TXUSRCLK => TXUSRCLK_ipd, + TXUSRCLK2 => TXUSRCLK2_ipd, + TX_BUFFER_USE => TX_BUFFER_USE_BINARY + + ); + + INIPROC : process + variable PMA_SPEED_BIT_VECTOR : bit_vector(119 downto 0); + begin + case ALIGN_COMMA_WORD is + when 1 => ALIGN_COMMA_WORD_BINARY <= "00"; + when 2 => ALIGN_COMMA_WORD_BINARY <= "01"; + when 4 => ALIGN_COMMA_WORD_BINARY <= "10"; + when others => assert FALSE report "Error : ALIGN_COMMA_WORD is not in 1, 2, 4." severity warning; + end case; + case CHAN_BOND_LIMIT is + when 0 => CHAN_BOND_LIMIT_BINARY <= "000000"; + when 1 => CHAN_BOND_LIMIT_BINARY <= "000001"; + when 2 => CHAN_BOND_LIMIT_BINARY <= "000010"; + when 3 => CHAN_BOND_LIMIT_BINARY <= "000011"; + when 4 => CHAN_BOND_LIMIT_BINARY <= "000100"; + when 5 => CHAN_BOND_LIMIT_BINARY <= "000101"; + when 6 => CHAN_BOND_LIMIT_BINARY <= "000110"; + when 7 => CHAN_BOND_LIMIT_BINARY <= "000111"; + when 8 => CHAN_BOND_LIMIT_BINARY <= "001000"; + when 9 => CHAN_BOND_LIMIT_BINARY <= "001001"; + when 10 => CHAN_BOND_LIMIT_BINARY <= "001010"; + when 11 => CHAN_BOND_LIMIT_BINARY <= "001011"; + when 12 => CHAN_BOND_LIMIT_BINARY <= "001100"; + when 13 => CHAN_BOND_LIMIT_BINARY <= "001101"; + when 14 => CHAN_BOND_LIMIT_BINARY <= "001110"; + when 15 => CHAN_BOND_LIMIT_BINARY <= "001111"; + when 16 => CHAN_BOND_LIMIT_BINARY <= "010000"; + when 17 => CHAN_BOND_LIMIT_BINARY <= "010001"; + when 18 => CHAN_BOND_LIMIT_BINARY <= "010010"; + when 19 => CHAN_BOND_LIMIT_BINARY <= "010011"; + when 20 => CHAN_BOND_LIMIT_BINARY <= "010100"; + when 21 => CHAN_BOND_LIMIT_BINARY <= "010101"; + when 22 => CHAN_BOND_LIMIT_BINARY <= "010110"; + when 23 => CHAN_BOND_LIMIT_BINARY <= "010111"; + when 24 => CHAN_BOND_LIMIT_BINARY <= "011000"; + when 25 => CHAN_BOND_LIMIT_BINARY <= "011001"; + when 26 => CHAN_BOND_LIMIT_BINARY <= "011010"; + when 27 => CHAN_BOND_LIMIT_BINARY <= "011011"; + when 28 => CHAN_BOND_LIMIT_BINARY <= "011100"; + when 29 => CHAN_BOND_LIMIT_BINARY <= "011101"; + when 30 => CHAN_BOND_LIMIT_BINARY <= "011110"; + when 31 => CHAN_BOND_LIMIT_BINARY <= "011111"; + when 32 => CHAN_BOND_LIMIT_BINARY <= "100000"; + when 33 => CHAN_BOND_LIMIT_BINARY <= "100001"; + when 34 => CHAN_BOND_LIMIT_BINARY <= "100010"; + when 35 => CHAN_BOND_LIMIT_BINARY <= "100011"; + when 36 => CHAN_BOND_LIMIT_BINARY <= "100100"; + when 37 => CHAN_BOND_LIMIT_BINARY <= "100101"; + when 38 => CHAN_BOND_LIMIT_BINARY <= "100110"; + when 39 => CHAN_BOND_LIMIT_BINARY <= "100111"; + when 40 => CHAN_BOND_LIMIT_BINARY <= "101000"; + when 41 => CHAN_BOND_LIMIT_BINARY <= "101001"; + when 42 => CHAN_BOND_LIMIT_BINARY <= "101010"; + when 43 => CHAN_BOND_LIMIT_BINARY <= "101011"; + when 44 => CHAN_BOND_LIMIT_BINARY <= "101100"; + when 45 => CHAN_BOND_LIMIT_BINARY <= "101101"; + when 46 => CHAN_BOND_LIMIT_BINARY <= "101110"; + when 47 => CHAN_BOND_LIMIT_BINARY <= "101111"; + when 48 => CHAN_BOND_LIMIT_BINARY <= "110000"; + when 49 => CHAN_BOND_LIMIT_BINARY <= "110001"; + when 50 => CHAN_BOND_LIMIT_BINARY <= "110010"; + when 51 => CHAN_BOND_LIMIT_BINARY <= "110011"; + when 52 => CHAN_BOND_LIMIT_BINARY <= "110100"; + when 53 => CHAN_BOND_LIMIT_BINARY <= "110101"; + when 54 => CHAN_BOND_LIMIT_BINARY <= "110110"; + when 55 => CHAN_BOND_LIMIT_BINARY <= "110111"; + when 56 => CHAN_BOND_LIMIT_BINARY <= "111000"; + when 57 => CHAN_BOND_LIMIT_BINARY <= "111001"; + when 58 => CHAN_BOND_LIMIT_BINARY <= "111010"; + when 59 => CHAN_BOND_LIMIT_BINARY <= "111011"; + when 60 => CHAN_BOND_LIMIT_BINARY <= "111100"; + when 61 => CHAN_BOND_LIMIT_BINARY <= "111101"; + when 62 => CHAN_BOND_LIMIT_BINARY <= "111110"; + when 63 => CHAN_BOND_LIMIT_BINARY <= "111111"; + when others => assert FALSE report "Error : CHAN_BOND_LIMIT is not in range 0...63." severity warning; + end case; +-- case CHAN_BOND_MODE is + if((CHAN_BOND_MODE = "OFF") or (CHAN_BOND_MODE = "off")) then + CHAN_BOND_MODE_BINARY <= "00"; + elsif((CHAN_BOND_MODE = "MASTER") or (CHAN_BOND_MODE = "master")) then + CHAN_BOND_MODE_BINARY <= "01"; + elsif((CHAN_BOND_MODE = "SLAVE_1_HOP") or (CHAN_BOND_MODE = "slave_1_hop")) then + CHAN_BOND_MODE_BINARY <= "10"; + elsif((CHAN_BOND_MODE = "SLAVE_2_HOPS") or (CHAN_BOND_MODE = "slave_2_hops")) then + CHAN_BOND_MODE_BINARY <= "11"; + else + assert FALSE report "Error : CHAN_BOND_MODE = is not OFF, MASTER, SLAVE_1_HOP, SLAVE_2_HOPS." severity warning; + end if; +-- end case; + case CHAN_BOND_ONE_SHOT is + when FALSE => CHAN_BOND_ONE_SHOT_BINARY <= '0'; + when TRUE => CHAN_BOND_ONE_SHOT_BINARY <= '1'; + when others => assert FALSE report "Error : CHAN_BOND_ONE_SHOT is neither TRUE nor FALSE." severity warning; + end case; + case CHAN_BOND_SEQ_2_USE is + when FALSE => CHAN_BOND_SEQ_2_USE_BINARY <= '0'; + when TRUE => CHAN_BOND_SEQ_2_USE_BINARY <= '1'; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_2_USE is neither TRUE nor FALSE." severity warning; + end case; + case CHAN_BOND_SEQ_LEN is + when 1 => CHAN_BOND_SEQ_LEN_BINARY <= "000"; + when 2 => CHAN_BOND_SEQ_LEN_BINARY <= "001"; + when 3 => CHAN_BOND_SEQ_LEN_BINARY <= "010"; + when 4 => CHAN_BOND_SEQ_LEN_BINARY <= "011"; + when 8 => CHAN_BOND_SEQ_LEN_BINARY <= "111"; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_LEN is not in 1, 2, 3, 4, 8." severity warning; + end case; + case CHAN_BOND_64B66B_SV is + when FALSE => CHAN_BOND_64B66B_SV_BINARY <= '0'; + when TRUE => CHAN_BOND_64B66B_SV_BINARY <= '1'; + when others => assert FALSE report "Error : CHAN_BOND_64B66B_SV is neither TRUE nor FALSE." severity warning; + end case; + case CLK_COR_8B10B_DE is + when FALSE => CLK_COR_8B10B_DE_BINARY <= '0'; + when TRUE => CLK_COR_8B10B_DE_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_8B10B_DE is neither TRUE nor FALSE." severity warning; + end case; + case CLK_COR_MAX_LAT is + when 0 => CLK_COR_MAX_LAT_BINARY <= "000000"; + when 1 => CLK_COR_MAX_LAT_BINARY <= "000001"; + when 2 => CLK_COR_MAX_LAT_BINARY <= "000010"; + when 3 => CLK_COR_MAX_LAT_BINARY <= "000011"; + when 4 => CLK_COR_MAX_LAT_BINARY <= "000100"; + when 5 => CLK_COR_MAX_LAT_BINARY <= "000101"; + when 6 => CLK_COR_MAX_LAT_BINARY <= "000110"; + when 7 => CLK_COR_MAX_LAT_BINARY <= "000111"; + when 8 => CLK_COR_MAX_LAT_BINARY <= "001000"; + when 9 => CLK_COR_MAX_LAT_BINARY <= "001001"; + when 10 => CLK_COR_MAX_LAT_BINARY <= "001010"; + when 11 => CLK_COR_MAX_LAT_BINARY <= "001011"; + when 12 => CLK_COR_MAX_LAT_BINARY <= "001100"; + when 13 => CLK_COR_MAX_LAT_BINARY <= "001101"; + when 14 => CLK_COR_MAX_LAT_BINARY <= "001110"; + when 15 => CLK_COR_MAX_LAT_BINARY <= "001111"; + when 16 => CLK_COR_MAX_LAT_BINARY <= "010000"; + when 17 => CLK_COR_MAX_LAT_BINARY <= "010001"; + when 18 => CLK_COR_MAX_LAT_BINARY <= "010010"; + when 19 => CLK_COR_MAX_LAT_BINARY <= "010011"; + when 20 => CLK_COR_MAX_LAT_BINARY <= "010100"; + when 21 => CLK_COR_MAX_LAT_BINARY <= "010101"; + when 22 => CLK_COR_MAX_LAT_BINARY <= "010110"; + when 23 => CLK_COR_MAX_LAT_BINARY <= "010111"; + when 24 => CLK_COR_MAX_LAT_BINARY <= "011000"; + when 25 => CLK_COR_MAX_LAT_BINARY <= "011001"; + when 26 => CLK_COR_MAX_LAT_BINARY <= "011010"; + when 27 => CLK_COR_MAX_LAT_BINARY <= "011011"; + when 28 => CLK_COR_MAX_LAT_BINARY <= "011100"; + when 29 => CLK_COR_MAX_LAT_BINARY <= "011101"; + when 30 => CLK_COR_MAX_LAT_BINARY <= "011110"; + when 31 => CLK_COR_MAX_LAT_BINARY <= "011111"; + when 32 => CLK_COR_MAX_LAT_BINARY <= "100000"; + when 33 => CLK_COR_MAX_LAT_BINARY <= "100001"; + when 34 => CLK_COR_MAX_LAT_BINARY <= "100010"; + when 35 => CLK_COR_MAX_LAT_BINARY <= "100011"; + when 36 => CLK_COR_MAX_LAT_BINARY <= "100100"; + when 37 => CLK_COR_MAX_LAT_BINARY <= "100101"; + when 38 => CLK_COR_MAX_LAT_BINARY <= "100110"; + when 39 => CLK_COR_MAX_LAT_BINARY <= "100111"; + when 40 => CLK_COR_MAX_LAT_BINARY <= "101000"; + when 41 => CLK_COR_MAX_LAT_BINARY <= "101001"; + when 42 => CLK_COR_MAX_LAT_BINARY <= "101010"; + when 43 => CLK_COR_MAX_LAT_BINARY <= "101011"; + when 44 => CLK_COR_MAX_LAT_BINARY <= "101100"; + when 45 => CLK_COR_MAX_LAT_BINARY <= "101101"; + when 46 => CLK_COR_MAX_LAT_BINARY <= "101110"; + when 47 => CLK_COR_MAX_LAT_BINARY <= "101111"; + when 48 => CLK_COR_MAX_LAT_BINARY <= "110000"; + when 49 => CLK_COR_MAX_LAT_BINARY <= "110001"; + when 50 => CLK_COR_MAX_LAT_BINARY <= "110010"; + when 51 => CLK_COR_MAX_LAT_BINARY <= "110011"; + when 52 => CLK_COR_MAX_LAT_BINARY <= "110100"; + when 53 => CLK_COR_MAX_LAT_BINARY <= "110101"; + when 54 => CLK_COR_MAX_LAT_BINARY <= "110110"; + when 55 => CLK_COR_MAX_LAT_BINARY <= "110111"; + when 56 => CLK_COR_MAX_LAT_BINARY <= "111000"; + when 57 => CLK_COR_MAX_LAT_BINARY <= "111001"; + when 58 => CLK_COR_MAX_LAT_BINARY <= "111010"; + when 59 => CLK_COR_MAX_LAT_BINARY <= "111011"; + when 60 => CLK_COR_MAX_LAT_BINARY <= "111100"; + when 61 => CLK_COR_MAX_LAT_BINARY <= "111101"; + when 62 => CLK_COR_MAX_LAT_BINARY <= "111110"; + when 63 => CLK_COR_MAX_LAT_BINARY <= "111111"; + when others => assert FALSE report "Error : CLK_COR_MAX_LAT is not in range 0...63." severity warning; + end case; + case CLK_COR_MIN_LAT is + when 0 => CLK_COR_MIN_LAT_BINARY <= "000000"; + when 1 => CLK_COR_MIN_LAT_BINARY <= "000001"; + when 2 => CLK_COR_MIN_LAT_BINARY <= "000010"; + when 3 => CLK_COR_MIN_LAT_BINARY <= "000011"; + when 4 => CLK_COR_MIN_LAT_BINARY <= "000100"; + when 5 => CLK_COR_MIN_LAT_BINARY <= "000101"; + when 6 => CLK_COR_MIN_LAT_BINARY <= "000110"; + when 7 => CLK_COR_MIN_LAT_BINARY <= "000111"; + when 8 => CLK_COR_MIN_LAT_BINARY <= "001000"; + when 9 => CLK_COR_MIN_LAT_BINARY <= "001001"; + when 10 => CLK_COR_MIN_LAT_BINARY <= "001010"; + when 11 => CLK_COR_MIN_LAT_BINARY <= "001011"; + when 12 => CLK_COR_MIN_LAT_BINARY <= "001100"; + when 13 => CLK_COR_MIN_LAT_BINARY <= "001101"; + when 14 => CLK_COR_MIN_LAT_BINARY <= "001110"; + when 15 => CLK_COR_MIN_LAT_BINARY <= "001111"; + when 16 => CLK_COR_MIN_LAT_BINARY <= "010000"; + when 17 => CLK_COR_MIN_LAT_BINARY <= "010001"; + when 18 => CLK_COR_MIN_LAT_BINARY <= "010010"; + when 19 => CLK_COR_MIN_LAT_BINARY <= "010011"; + when 20 => CLK_COR_MIN_LAT_BINARY <= "010100"; + when 21 => CLK_COR_MIN_LAT_BINARY <= "010101"; + when 22 => CLK_COR_MIN_LAT_BINARY <= "010110"; + when 23 => CLK_COR_MIN_LAT_BINARY <= "010111"; + when 24 => CLK_COR_MIN_LAT_BINARY <= "011000"; + when 25 => CLK_COR_MIN_LAT_BINARY <= "011001"; + when 26 => CLK_COR_MIN_LAT_BINARY <= "011010"; + when 27 => CLK_COR_MIN_LAT_BINARY <= "011011"; + when 28 => CLK_COR_MIN_LAT_BINARY <= "011100"; + when 29 => CLK_COR_MIN_LAT_BINARY <= "011101"; + when 30 => CLK_COR_MIN_LAT_BINARY <= "011110"; + when 31 => CLK_COR_MIN_LAT_BINARY <= "011111"; + when 32 => CLK_COR_MIN_LAT_BINARY <= "100000"; + when 33 => CLK_COR_MIN_LAT_BINARY <= "100001"; + when 34 => CLK_COR_MIN_LAT_BINARY <= "100010"; + when 35 => CLK_COR_MIN_LAT_BINARY <= "100011"; + when 36 => CLK_COR_MIN_LAT_BINARY <= "100100"; + when 37 => CLK_COR_MIN_LAT_BINARY <= "100101"; + when 38 => CLK_COR_MIN_LAT_BINARY <= "100110"; + when 39 => CLK_COR_MIN_LAT_BINARY <= "100111"; + when 40 => CLK_COR_MIN_LAT_BINARY <= "101000"; + when 41 => CLK_COR_MIN_LAT_BINARY <= "101001"; + when 42 => CLK_COR_MIN_LAT_BINARY <= "101010"; + when 43 => CLK_COR_MIN_LAT_BINARY <= "101011"; + when 44 => CLK_COR_MIN_LAT_BINARY <= "101100"; + when 45 => CLK_COR_MIN_LAT_BINARY <= "101101"; + when 46 => CLK_COR_MIN_LAT_BINARY <= "101110"; + when 47 => CLK_COR_MIN_LAT_BINARY <= "101111"; + when 48 => CLK_COR_MIN_LAT_BINARY <= "110000"; + when 49 => CLK_COR_MIN_LAT_BINARY <= "110001"; + when 50 => CLK_COR_MIN_LAT_BINARY <= "110010"; + when 51 => CLK_COR_MIN_LAT_BINARY <= "110011"; + when 52 => CLK_COR_MIN_LAT_BINARY <= "110100"; + when 53 => CLK_COR_MIN_LAT_BINARY <= "110101"; + when 54 => CLK_COR_MIN_LAT_BINARY <= "110110"; + when 55 => CLK_COR_MIN_LAT_BINARY <= "110111"; + when 56 => CLK_COR_MIN_LAT_BINARY <= "111000"; + when 57 => CLK_COR_MIN_LAT_BINARY <= "111001"; + when 58 => CLK_COR_MIN_LAT_BINARY <= "111010"; + when 59 => CLK_COR_MIN_LAT_BINARY <= "111011"; + when 60 => CLK_COR_MIN_LAT_BINARY <= "111100"; + when 61 => CLK_COR_MIN_LAT_BINARY <= "111101"; + when 62 => CLK_COR_MIN_LAT_BINARY <= "111110"; + when 63 => CLK_COR_MIN_LAT_BINARY <= "111111"; + when others => assert FALSE report "Error : CLK_COR_MIN_LAT is not in range 0...63." severity warning; + end case; + case CLK_COR_SEQ_2_USE is + when FALSE => CLK_COR_SEQ_2_USE_BINARY <= '0'; + when TRUE => CLK_COR_SEQ_2_USE_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_SEQ_2_USE is neither TRUE nor FALSE." severity warning; + end case; + case CLK_COR_SEQ_DROP is + when FALSE => CLK_COR_SEQ_DROP_BINARY <= '0'; + when TRUE => CLK_COR_SEQ_DROP_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_SEQ_DROP is neither TRUE nor FALSE." severity warning; + end case; + case CLK_COR_SEQ_LEN is + when 1 => CLK_COR_SEQ_LEN_BINARY <= "000"; + when 2 => CLK_COR_SEQ_LEN_BINARY <= "001"; + when 3 => CLK_COR_SEQ_LEN_BINARY <= "010"; + when 4 => CLK_COR_SEQ_LEN_BINARY <= "011"; + when 8 => CLK_COR_SEQ_LEN_BINARY <= "111"; + when others => assert FALSE report "Error : CLK_COR_SEQ_LEN is not in 1, 2, 3, 4, 8." severity warning; + end case; + case CLK_CORRECT_USE is + when FALSE => CLK_CORRECT_USE_BINARY <= '0'; + when TRUE => CLK_CORRECT_USE_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_CORRECT_USE is neither TRUE nor FALSE." severity warning; + end case; + case DEC_MCOMMA_DETECT is + when FALSE => DEC_MCOMMA_DETECT_BINARY <= '0'; + when TRUE => DEC_MCOMMA_DETECT_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_MCOMMA_DETECT is neither TRUE nor FALSE." severity warning; + end case; + case DEC_PCOMMA_DETECT is + when FALSE => DEC_PCOMMA_DETECT_BINARY <= '0'; + when TRUE => DEC_PCOMMA_DETECT_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_PCOMMA_DETECT is neither TRUE nor FALSE." severity warning; + end case; + case DEC_VALID_COMMA_ONLY is + when FALSE => DEC_VALID_COMMA_ONLY_BINARY <= '0'; + when TRUE => DEC_VALID_COMMA_ONLY_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_VALID_COMMA_ONLY is neither TRUE nor FALSE." severity warning; + end case; + case MCOMMA_DETECT is + when FALSE => MCOMMA_DETECT_BINARY <= '0'; + when TRUE => MCOMMA_DETECT_BINARY <= '1'; + when others => assert FALSE report "Error : MCOMMA_DETECT is neither TRUE nor FALSE." severity warning; + end case; + case PCOMMA_DETECT is + when FALSE => PCOMMA_DETECT_BINARY <= '0'; + when TRUE => PCOMMA_DETECT_BINARY <= '1'; + when others => assert FALSE report "Error : PCOMMA_DETECT is neither TRUE nor FALSE." severity warning; + end case; +-- case PMA_SPEED_USE is + if((PMA_SPEED_USE = "PMA_SPEED") or (PMA_SPEED_USE = "pma_speed")) then +-- case PMA_SPEED is + if (PMA_SPEED = "0_32") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d00208c9050d4068"; + elsif (PMA_SPEED = "0_64") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d00208c9050d4068"; + elsif (PMA_SPEED = "1_32") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d10208c9050d4168"; + elsif (PMA_SPEED = "1_64") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d10208c9050d4168"; + elsif (PMA_SPEED = "2_32") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d40208c9060d4468"; + elsif (PMA_SPEED = "2_64") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d40208c9060d4468"; + elsif (PMA_SPEED = "3_32") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d50208c9060d4568"; + elsif (PMA_SPEED = "3_64") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d50208c9060d4568"; + elsif (PMA_SPEED = "4_32") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d80208c9020d4868"; + elsif (PMA_SPEED = "4_64") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d80208c9020d4868"; + elsif (PMA_SPEED = "5_32") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d90208c9020d4968"; + elsif (PMA_SPEED = "5_64") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d90208c9020d4968"; + elsif (PMA_SPEED = "6_32") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d00208c9050d4068"; + elsif (PMA_SPEED = "6_64") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d00208c9050d4068"; + elsif (PMA_SPEED = "7_32") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d10208c9050d4168"; + elsif (PMA_SPEED = "7_64") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d10208c9050d4168"; + elsif (PMA_SPEED = "8_32") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d40208c9050d4468"; + elsif (PMA_SPEED = "8_64") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d40208c9050d4468"; + elsif (PMA_SPEED = "9_32") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d50208c9050d4568"; + elsif (PMA_SPEED = "9_64") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d50208c9050d4568"; + elsif (PMA_SPEED = "10_32") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d80208c9020d4868"; + elsif (PMA_SPEED = "10_64") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d80208c9020d4868"; + elsif (PMA_SPEED = "11_32") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d90208c9020d4968"; + elsif (PMA_SPEED = "11_64") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d90208c9020d4968"; + elsif (PMA_SPEED = "12_40") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1506e20208c9050da268"; + elsif (PMA_SPEED = "12_80") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1506e20208c9050da268"; + elsif (PMA_SPEED = "13_40") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1506e60208c9050da668"; + elsif (PMA_SPEED = "13_80") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1506e60208c9050da668"; + elsif (PMA_SPEED = "14_40") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1506ea0208c9020daa68"; + elsif (PMA_SPEED = "14_80") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1506ea0208c9020daa68"; + elsif (PMA_SPEED = "15_32") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504c00208c9050d0068"; + elsif (PMA_SPEED = "15_64") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504c00208c9050d0068"; + elsif (PMA_SPEED = "16_32") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504c40208c9050d0468"; + elsif (PMA_SPEED = "16_64") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504c40208c9050d0468"; + elsif (PMA_SPEED = "17_32") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504c80208c9010d0868"; + elsif (PMA_SPEED = "17_64") then + PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504c80208c9010d0868"; + elsif (PMA_SPEED = "18_40") then + PMA_SPEED_BIT_VECTOR := X"00ffcd50ca1106e21208c9050da228"; + elsif (PMA_SPEED = "18_80") then + PMA_SPEED_BIT_VECTOR := X"00ffcd50ca1106e21208c9050da228"; + elsif (PMA_SPEED = "19_40") then + PMA_SPEED_BIT_VECTOR := X"00ffcd50ca1106e21208c9050da228"; + elsif (PMA_SPEED = "19_80") then + PMA_SPEED_BIT_VECTOR := X"00ffcd50ca1106e21208c9050da228"; + elsif (PMA_SPEED = "20_40") then + PMA_SPEED_BIT_VECTOR := X"00ffcd30ca1106e21208c9050da228"; + elsif (PMA_SPEED = "20_80") then + PMA_SPEED_BIT_VECTOR := X"00ffcd50ca1106e21208c9050da228"; + elsif (PMA_SPEED = "21_40") then + PMA_SPEED_BIT_VECTOR := X"00ffcd50ca0d06e21208c9050da228"; + elsif (PMA_SPEED = "21_80") then + PMA_SPEED_BIT_VECTOR := X"00ffcd50ca0d06e21208c9050da228"; + elsif (PMA_SPEED = "22_40") then + PMA_SPEED_BIT_VECTOR := X"00ffcd50ca0d06e61208c9010da628"; + elsif (PMA_SPEED = "22_80") then + PMA_SPEED_BIT_VECTOR := X"00ffcd50ca0d06e61208c9010da628"; + elsif (PMA_SPEED = "23_10") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132263068090104a628"; + elsif (PMA_SPEED = "23_20") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132663068090105a628"; + elsif (PMA_SPEED = "23_40") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132663068090105a628"; + elsif (PMA_SPEED = "24_10") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132223068090504a228"; + elsif (PMA_SPEED = "24_20") then + PMA_SPEED_BIT_VECTOR := X"00fc0db00b0f32623068090505a228"; + elsif (PMA_SPEED = "24_40") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132623068090505a228"; + elsif (PMA_SPEED = "25_10") then + PMA_SPEED_BIT_VECTOR := X"00fc0db00b0f32263068090104a628"; + elsif (PMA_SPEED = "25_20") then + PMA_SPEED_BIT_VECTOR := X"00fc0db00b0f32663068090105a628"; + elsif (PMA_SPEED = "25_40") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132663068090105a628"; + elsif (PMA_SPEED = "26_10") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b01322a3068090104aa28"; + elsif (PMA_SPEED = "26_20") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b01326a3068090105aa28"; + elsif (PMA_SPEED = "26_40") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b01326a3068090105aa28"; + elsif (PMA_SPEED = "27_10") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132223068090504a220"; + elsif (PMA_SPEED = "27_20") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132623068090505a220"; + elsif (PMA_SPEED = "27_40") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132623068090505a220"; + elsif (PMA_SPEED = "28_10") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132263068090104a620"; + elsif (PMA_SPEED = "28_20") then + PMA_SPEED_BIT_VECTOR := X"00fc0d300b0f32663068090105a620"; + elsif (PMA_SPEED = "28_40") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132663068090105a620"; + elsif (PMA_SPEED = "29_10") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b01322a3068090104aa20"; + elsif (PMA_SPEED = "29_20") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b01326a3068090105aa20"; + elsif (PMA_SPEED = "29_40") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b01326a3068090105aa20"; + elsif (PMA_SPEED = "30_16") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b01304430680901050420"; + elsif (PMA_SPEED = "30_32") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b01304430680901050420"; + elsif (PMA_SPEED = "30_8") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b01300430680901040420"; + elsif (PMA_SPEED = "31_16") then + PMA_SPEED_BIT_VECTOR := X"00fc0d300b0f304830680901050820"; + elsif (PMA_SPEED = "31_32") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b01304830680901050820"; + elsif (PMA_SPEED = "31_8") then + PMA_SPEED_BIT_VECTOR := X"00ffcd500b01300830680901040820"; + else + assert FALSE report "Error : PMA_SPEED = is not 0_32, 0_64, 1_32, 1_64, 2_32, 2_64, 3_32, 3_64, 4_32, 4_64, 5_32, 5_64, 6_32, 6_64, 7_32, 7_64, 8_32, 8_64, 9_32, 9_64, 10_32, 10_64, 11_32, 11_64, 12_40, 12_80, 13_40, 13_80, 14_40, 14_80, 15_32, 15_64, 16_32, 16_64, 17_32, 17_64, 18_40, 18_80, 19_40, 19_80, 20_40, 20_80, 21_40, 21_80, 22_40, 22_80, 23_10, 23_20, 23_40, 24_10, 24_20, 24_40, 25_10, 25_20, 25_40, 26_10, 26_20, 26_40, 27_10, 27_20, 27_40, 28_10, 28_20, 28_40, 29_10, 29_20, 29_40, 30_16, 30_32, 30_8, 31_16, 31_32, 31_8." severity warning; + end if; +-- end case; + elsif((PMA_SPEED_USE = "PMA_SPEED_HEX") or (PMA_SPEED_USE = "pma_speed_hex")) then + PMA_SPEED_BIT_VECTOR := PMA_SPEED_HEX; + else + assert FALSE report "Error : PMA_SPEED_USE is neither PMA_SPEED nor PMA_SPEED_HEX ." severity warning; + end if; +-- end case; + + + PMA_SPEED_BINARY <= To_StdLogicVector(PMA_SPEED_BIT_VECTOR); + + case RX_BUFFER_USE is + when FALSE => RX_BUFFER_USE_BINARY <= '0'; + when TRUE => RX_BUFFER_USE_BINARY <= '1'; + when others => assert FALSE report "Error : RX_BUFFER_USE is neither TRUE nor FALSE." severity warning; + end case; + case RX_LOS_INVALID_INCR is + when 1 => RX_LOS_INVALID_INCR_BINARY <= "00000001"; + when 2 => RX_LOS_INVALID_INCR_BINARY <= "00000010"; + when 4 => RX_LOS_INVALID_INCR_BINARY <= "00000100"; + when 8 => RX_LOS_INVALID_INCR_BINARY <= "00001000"; + when 16 => RX_LOS_INVALID_INCR_BINARY <= "00010000"; + when 32 => RX_LOS_INVALID_INCR_BINARY <= "00100000"; + when 64 => RX_LOS_INVALID_INCR_BINARY <= "01000000"; + when 128 => RX_LOS_INVALID_INCR_BINARY <= "10000000"; + when others => assert FALSE report "Error : RX_LOS_INVALID_INCR is not in 1, 2, 4, 8, 16, 32, 64, 128." severity warning; + end case; + case RX_LOS_THRESHOLD is + when 4 => RX_LOS_THRESHOLD_BINARY <= "00000001"; + when 8 => RX_LOS_THRESHOLD_BINARY <= "00000010"; + when 16 => RX_LOS_THRESHOLD_BINARY <= "00000100"; + when 32 => RX_LOS_THRESHOLD_BINARY <= "00001000"; + when 64 => RX_LOS_THRESHOLD_BINARY <= "00010000"; + when 128 => RX_LOS_THRESHOLD_BINARY <= "00100000"; + when 256 => RX_LOS_THRESHOLD_BINARY <= "01000000"; + when 512 => RX_LOS_THRESHOLD_BINARY <= "10000000"; + when others => assert FALSE report "Error : RX_LOS_THRESHOLD is not in 4, 8, 16, 32, 64, 128, 256, 512." severity warning; + end case; + case RX_LOSS_OF_SYNC_FSM is + when FALSE => RX_LOSS_OF_SYNC_FSM_BINARY <= '0'; + when TRUE => RX_LOSS_OF_SYNC_FSM_BINARY <= '1'; + when others => assert FALSE report "Error : RX_LOSS_OF_SYNC_FSM is neither TRUE nor FALSE." severity warning; + end case; + case SH_CNT_MAX is + when 1 => SH_CNT_MAX_BINARY <= "00000000"; + when 2 => SH_CNT_MAX_BINARY <= "00000001"; + when 3 => SH_CNT_MAX_BINARY <= "00000010"; + when 4 => SH_CNT_MAX_BINARY <= "00000011"; + when 5 => SH_CNT_MAX_BINARY <= "00000100"; + when 6 => SH_CNT_MAX_BINARY <= "00000101"; + when 7 => SH_CNT_MAX_BINARY <= "00000110"; + when 8 => SH_CNT_MAX_BINARY <= "00000111"; + when 9 => SH_CNT_MAX_BINARY <= "00001000"; + when 10 => SH_CNT_MAX_BINARY <= "00001001"; + when 11 => SH_CNT_MAX_BINARY <= "00001010"; + when 12 => SH_CNT_MAX_BINARY <= "00001011"; + when 13 => SH_CNT_MAX_BINARY <= "00001100"; + when 14 => SH_CNT_MAX_BINARY <= "00001101"; + when 15 => SH_CNT_MAX_BINARY <= "00001110"; + when 16 => SH_CNT_MAX_BINARY <= "00001111"; + when 17 => SH_CNT_MAX_BINARY <= "00010000"; + when 18 => SH_CNT_MAX_BINARY <= "00010001"; + when 19 => SH_CNT_MAX_BINARY <= "00010010"; + when 20 => SH_CNT_MAX_BINARY <= "00010011"; + when 21 => SH_CNT_MAX_BINARY <= "00010100"; + when 22 => SH_CNT_MAX_BINARY <= "00010101"; + when 23 => SH_CNT_MAX_BINARY <= "00010110"; + when 24 => SH_CNT_MAX_BINARY <= "00010111"; + when 25 => SH_CNT_MAX_BINARY <= "00011000"; + when 26 => SH_CNT_MAX_BINARY <= "00011001"; + when 27 => SH_CNT_MAX_BINARY <= "00011010"; + when 28 => SH_CNT_MAX_BINARY <= "00011011"; + when 29 => SH_CNT_MAX_BINARY <= "00011100"; + when 30 => SH_CNT_MAX_BINARY <= "00011101"; + when 31 => SH_CNT_MAX_BINARY <= "00011110"; + when 32 => SH_CNT_MAX_BINARY <= "00011111"; + when 33 => SH_CNT_MAX_BINARY <= "00100000"; + when 34 => SH_CNT_MAX_BINARY <= "00100001"; + when 35 => SH_CNT_MAX_BINARY <= "00100010"; + when 36 => SH_CNT_MAX_BINARY <= "00100011"; + when 37 => SH_CNT_MAX_BINARY <= "00100100"; + when 38 => SH_CNT_MAX_BINARY <= "00100101"; + when 39 => SH_CNT_MAX_BINARY <= "00100110"; + when 40 => SH_CNT_MAX_BINARY <= "00100111"; + when 41 => SH_CNT_MAX_BINARY <= "00101000"; + when 42 => SH_CNT_MAX_BINARY <= "00101001"; + when 43 => SH_CNT_MAX_BINARY <= "00101010"; + when 44 => SH_CNT_MAX_BINARY <= "00101011"; + when 45 => SH_CNT_MAX_BINARY <= "00101100"; + when 46 => SH_CNT_MAX_BINARY <= "00101101"; + when 47 => SH_CNT_MAX_BINARY <= "00101110"; + when 48 => SH_CNT_MAX_BINARY <= "00101111"; + when 49 => SH_CNT_MAX_BINARY <= "00110000"; + when 50 => SH_CNT_MAX_BINARY <= "00110001"; + when 51 => SH_CNT_MAX_BINARY <= "00110010"; + when 52 => SH_CNT_MAX_BINARY <= "00110011"; + when 53 => SH_CNT_MAX_BINARY <= "00110100"; + when 54 => SH_CNT_MAX_BINARY <= "00110101"; + when 55 => SH_CNT_MAX_BINARY <= "00110110"; + when 56 => SH_CNT_MAX_BINARY <= "00110111"; + when 57 => SH_CNT_MAX_BINARY <= "00111000"; + when 58 => SH_CNT_MAX_BINARY <= "00111001"; + when 59 => SH_CNT_MAX_BINARY <= "00111010"; + when 60 => SH_CNT_MAX_BINARY <= "00111011"; + when 61 => SH_CNT_MAX_BINARY <= "00111100"; + when 62 => SH_CNT_MAX_BINARY <= "00111101"; + when 63 => SH_CNT_MAX_BINARY <= "00111110"; + when 64 => SH_CNT_MAX_BINARY <= "00111111"; + when 65 => SH_CNT_MAX_BINARY <= "01000000"; + when 66 => SH_CNT_MAX_BINARY <= "01000001"; + when 67 => SH_CNT_MAX_BINARY <= "01000010"; + when 68 => SH_CNT_MAX_BINARY <= "01000011"; + when 69 => SH_CNT_MAX_BINARY <= "01000100"; + when 70 => SH_CNT_MAX_BINARY <= "01000101"; + when 71 => SH_CNT_MAX_BINARY <= "01000110"; + when 72 => SH_CNT_MAX_BINARY <= "01000111"; + when 73 => SH_CNT_MAX_BINARY <= "01001000"; + when 74 => SH_CNT_MAX_BINARY <= "01001001"; + when 75 => SH_CNT_MAX_BINARY <= "01001010"; + when 76 => SH_CNT_MAX_BINARY <= "01001011"; + when 77 => SH_CNT_MAX_BINARY <= "01001100"; + when 78 => SH_CNT_MAX_BINARY <= "01001101"; + when 79 => SH_CNT_MAX_BINARY <= "01001110"; + when 80 => SH_CNT_MAX_BINARY <= "01001111"; + when 81 => SH_CNT_MAX_BINARY <= "01010000"; + when 82 => SH_CNT_MAX_BINARY <= "01010001"; + when 83 => SH_CNT_MAX_BINARY <= "01010010"; + when 84 => SH_CNT_MAX_BINARY <= "01010011"; + when 85 => SH_CNT_MAX_BINARY <= "01010100"; + when 86 => SH_CNT_MAX_BINARY <= "01010101"; + when 87 => SH_CNT_MAX_BINARY <= "01010110"; + when 88 => SH_CNT_MAX_BINARY <= "01010111"; + when 89 => SH_CNT_MAX_BINARY <= "01011000"; + when 90 => SH_CNT_MAX_BINARY <= "01011001"; + when 91 => SH_CNT_MAX_BINARY <= "01011010"; + when 92 => SH_CNT_MAX_BINARY <= "01011011"; + when 93 => SH_CNT_MAX_BINARY <= "01011100"; + when 94 => SH_CNT_MAX_BINARY <= "01011101"; + when 95 => SH_CNT_MAX_BINARY <= "01011110"; + when 96 => SH_CNT_MAX_BINARY <= "01011111"; + when 97 => SH_CNT_MAX_BINARY <= "01100000"; + when 98 => SH_CNT_MAX_BINARY <= "01100001"; + when 99 => SH_CNT_MAX_BINARY <= "01100010"; + when 100 => SH_CNT_MAX_BINARY <= "01100011"; + when 101 => SH_CNT_MAX_BINARY <= "01100100"; + when 102 => SH_CNT_MAX_BINARY <= "01100101"; + when 103 => SH_CNT_MAX_BINARY <= "01100110"; + when 104 => SH_CNT_MAX_BINARY <= "01100111"; + when 105 => SH_CNT_MAX_BINARY <= "01101000"; + when 106 => SH_CNT_MAX_BINARY <= "01101001"; + when 107 => SH_CNT_MAX_BINARY <= "01101010"; + when 108 => SH_CNT_MAX_BINARY <= "01101011"; + when 109 => SH_CNT_MAX_BINARY <= "01101100"; + when 110 => SH_CNT_MAX_BINARY <= "01101101"; + when 111 => SH_CNT_MAX_BINARY <= "01101110"; + when 112 => SH_CNT_MAX_BINARY <= "01101111"; + when 113 => SH_CNT_MAX_BINARY <= "01110000"; + when 114 => SH_CNT_MAX_BINARY <= "01110001"; + when 115 => SH_CNT_MAX_BINARY <= "01110010"; + when 116 => SH_CNT_MAX_BINARY <= "01110011"; + when 117 => SH_CNT_MAX_BINARY <= "01110100"; + when 118 => SH_CNT_MAX_BINARY <= "01110101"; + when 119 => SH_CNT_MAX_BINARY <= "01110110"; + when 120 => SH_CNT_MAX_BINARY <= "01110111"; + when 121 => SH_CNT_MAX_BINARY <= "01111000"; + when 122 => SH_CNT_MAX_BINARY <= "01111001"; + when 123 => SH_CNT_MAX_BINARY <= "01111010"; + when 124 => SH_CNT_MAX_BINARY <= "01111011"; + when 125 => SH_CNT_MAX_BINARY <= "01111100"; + when 126 => SH_CNT_MAX_BINARY <= "01111101"; + when 127 => SH_CNT_MAX_BINARY <= "01111110"; + when 128 => SH_CNT_MAX_BINARY <= "01111111"; + when 129 => SH_CNT_MAX_BINARY <= "10000000"; + when 130 => SH_CNT_MAX_BINARY <= "10000001"; + when 131 => SH_CNT_MAX_BINARY <= "10000010"; + when 132 => SH_CNT_MAX_BINARY <= "10000011"; + when 133 => SH_CNT_MAX_BINARY <= "10000100"; + when 134 => SH_CNT_MAX_BINARY <= "10000101"; + when 135 => SH_CNT_MAX_BINARY <= "10000110"; + when 136 => SH_CNT_MAX_BINARY <= "10000111"; + when 137 => SH_CNT_MAX_BINARY <= "10001000"; + when 138 => SH_CNT_MAX_BINARY <= "10001001"; + when 139 => SH_CNT_MAX_BINARY <= "10001010"; + when 140 => SH_CNT_MAX_BINARY <= "10001011"; + when 141 => SH_CNT_MAX_BINARY <= "10001100"; + when 142 => SH_CNT_MAX_BINARY <= "10001101"; + when 143 => SH_CNT_MAX_BINARY <= "10001110"; + when 144 => SH_CNT_MAX_BINARY <= "10001111"; + when 145 => SH_CNT_MAX_BINARY <= "10010000"; + when 146 => SH_CNT_MAX_BINARY <= "10010001"; + when 147 => SH_CNT_MAX_BINARY <= "10010010"; + when 148 => SH_CNT_MAX_BINARY <= "10010011"; + when 149 => SH_CNT_MAX_BINARY <= "10010100"; + when 150 => SH_CNT_MAX_BINARY <= "10010101"; + when 151 => SH_CNT_MAX_BINARY <= "10010110"; + when 152 => SH_CNT_MAX_BINARY <= "10010111"; + when 153 => SH_CNT_MAX_BINARY <= "10011000"; + when 154 => SH_CNT_MAX_BINARY <= "10011001"; + when 155 => SH_CNT_MAX_BINARY <= "10011010"; + when 156 => SH_CNT_MAX_BINARY <= "10011011"; + when 157 => SH_CNT_MAX_BINARY <= "10011100"; + when 158 => SH_CNT_MAX_BINARY <= "10011101"; + when 159 => SH_CNT_MAX_BINARY <= "10011110"; + when 160 => SH_CNT_MAX_BINARY <= "10011111"; + when 161 => SH_CNT_MAX_BINARY <= "10100000"; + when 162 => SH_CNT_MAX_BINARY <= "10100001"; + when 163 => SH_CNT_MAX_BINARY <= "10100010"; + when 164 => SH_CNT_MAX_BINARY <= "10100011"; + when 165 => SH_CNT_MAX_BINARY <= "10100100"; + when 166 => SH_CNT_MAX_BINARY <= "10100101"; + when 167 => SH_CNT_MAX_BINARY <= "10100110"; + when 168 => SH_CNT_MAX_BINARY <= "10100111"; + when 169 => SH_CNT_MAX_BINARY <= "10101000"; + when 170 => SH_CNT_MAX_BINARY <= "10101001"; + when 171 => SH_CNT_MAX_BINARY <= "10101010"; + when 172 => SH_CNT_MAX_BINARY <= "10101011"; + when 173 => SH_CNT_MAX_BINARY <= "10101100"; + when 174 => SH_CNT_MAX_BINARY <= "10101101"; + when 175 => SH_CNT_MAX_BINARY <= "10101110"; + when 176 => SH_CNT_MAX_BINARY <= "10101111"; + when 177 => SH_CNT_MAX_BINARY <= "10110000"; + when 178 => SH_CNT_MAX_BINARY <= "10110001"; + when 179 => SH_CNT_MAX_BINARY <= "10110010"; + when 180 => SH_CNT_MAX_BINARY <= "10110011"; + when 181 => SH_CNT_MAX_BINARY <= "10110100"; + when 182 => SH_CNT_MAX_BINARY <= "10110101"; + when 183 => SH_CNT_MAX_BINARY <= "10110110"; + when 184 => SH_CNT_MAX_BINARY <= "10110111"; + when 185 => SH_CNT_MAX_BINARY <= "10111000"; + when 186 => SH_CNT_MAX_BINARY <= "10111001"; + when 187 => SH_CNT_MAX_BINARY <= "10111010"; + when 188 => SH_CNT_MAX_BINARY <= "10111011"; + when 189 => SH_CNT_MAX_BINARY <= "10111100"; + when 190 => SH_CNT_MAX_BINARY <= "10111101"; + when 191 => SH_CNT_MAX_BINARY <= "10111110"; + when 192 => SH_CNT_MAX_BINARY <= "10111111"; + when 193 => SH_CNT_MAX_BINARY <= "11000000"; + when 194 => SH_CNT_MAX_BINARY <= "11000001"; + when 195 => SH_CNT_MAX_BINARY <= "11000010"; + when 196 => SH_CNT_MAX_BINARY <= "11000011"; + when 197 => SH_CNT_MAX_BINARY <= "11000100"; + when 198 => SH_CNT_MAX_BINARY <= "11000101"; + when 199 => SH_CNT_MAX_BINARY <= "11000110"; + when 200 => SH_CNT_MAX_BINARY <= "11000111"; + when 201 => SH_CNT_MAX_BINARY <= "11001000"; + when 202 => SH_CNT_MAX_BINARY <= "11001001"; + when 203 => SH_CNT_MAX_BINARY <= "11001010"; + when 204 => SH_CNT_MAX_BINARY <= "11001011"; + when 205 => SH_CNT_MAX_BINARY <= "11001100"; + when 206 => SH_CNT_MAX_BINARY <= "11001101"; + when 207 => SH_CNT_MAX_BINARY <= "11001110"; + when 208 => SH_CNT_MAX_BINARY <= "11001111"; + when 209 => SH_CNT_MAX_BINARY <= "11010000"; + when 210 => SH_CNT_MAX_BINARY <= "11010001"; + when 211 => SH_CNT_MAX_BINARY <= "11010010"; + when 212 => SH_CNT_MAX_BINARY <= "11010011"; + when 213 => SH_CNT_MAX_BINARY <= "11010100"; + when 214 => SH_CNT_MAX_BINARY <= "11010101"; + when 215 => SH_CNT_MAX_BINARY <= "11010110"; + when 216 => SH_CNT_MAX_BINARY <= "11010111"; + when 217 => SH_CNT_MAX_BINARY <= "11011000"; + when 218 => SH_CNT_MAX_BINARY <= "11011001"; + when 219 => SH_CNT_MAX_BINARY <= "11011010"; + when 220 => SH_CNT_MAX_BINARY <= "11011011"; + when 221 => SH_CNT_MAX_BINARY <= "11011100"; + when 222 => SH_CNT_MAX_BINARY <= "11011101"; + when 223 => SH_CNT_MAX_BINARY <= "11011110"; + when 224 => SH_CNT_MAX_BINARY <= "11011111"; + when 225 => SH_CNT_MAX_BINARY <= "11100000"; + when 226 => SH_CNT_MAX_BINARY <= "11100001"; + when 227 => SH_CNT_MAX_BINARY <= "11100010"; + when 228 => SH_CNT_MAX_BINARY <= "11100011"; + when 229 => SH_CNT_MAX_BINARY <= "11100100"; + when 230 => SH_CNT_MAX_BINARY <= "11100101"; + when 231 => SH_CNT_MAX_BINARY <= "11100110"; + when 232 => SH_CNT_MAX_BINARY <= "11100111"; + when 233 => SH_CNT_MAX_BINARY <= "11101000"; + when 234 => SH_CNT_MAX_BINARY <= "11101001"; + when 235 => SH_CNT_MAX_BINARY <= "11101010"; + when 236 => SH_CNT_MAX_BINARY <= "11101011"; + when 237 => SH_CNT_MAX_BINARY <= "11101100"; + when 238 => SH_CNT_MAX_BINARY <= "11101101"; + when 239 => SH_CNT_MAX_BINARY <= "11101110"; + when 240 => SH_CNT_MAX_BINARY <= "11101111"; + when 241 => SH_CNT_MAX_BINARY <= "11110000"; + when 242 => SH_CNT_MAX_BINARY <= "11110001"; + when 243 => SH_CNT_MAX_BINARY <= "11110010"; + when 244 => SH_CNT_MAX_BINARY <= "11110011"; + when 245 => SH_CNT_MAX_BINARY <= "11110100"; + when 246 => SH_CNT_MAX_BINARY <= "11110101"; + when 247 => SH_CNT_MAX_BINARY <= "11110110"; + when 248 => SH_CNT_MAX_BINARY <= "11110111"; + when 249 => SH_CNT_MAX_BINARY <= "11111000"; + when 250 => SH_CNT_MAX_BINARY <= "11111001"; + when 251 => SH_CNT_MAX_BINARY <= "11111010"; + when 252 => SH_CNT_MAX_BINARY <= "11111011"; + when 253 => SH_CNT_MAX_BINARY <= "11111100"; + when 254 => SH_CNT_MAX_BINARY <= "11111101"; + when 255 => SH_CNT_MAX_BINARY <= "11111110"; + when 256 => SH_CNT_MAX_BINARY <= "11111111"; + when others => assert FALSE report "Error : SH_CNT_MAX is not in range 1...256." severity warning; + end case; + case SH_INVALID_CNT_MAX is + when 1 => SH_INVALID_CNT_MAX_BINARY <= "00000000"; + when 2 => SH_INVALID_CNT_MAX_BINARY <= "00000001"; + when 3 => SH_INVALID_CNT_MAX_BINARY <= "00000010"; + when 4 => SH_INVALID_CNT_MAX_BINARY <= "00000011"; + when 5 => SH_INVALID_CNT_MAX_BINARY <= "00000100"; + when 6 => SH_INVALID_CNT_MAX_BINARY <= "00000101"; + when 7 => SH_INVALID_CNT_MAX_BINARY <= "00000110"; + when 8 => SH_INVALID_CNT_MAX_BINARY <= "00000111"; + when 9 => SH_INVALID_CNT_MAX_BINARY <= "00001000"; + when 10 => SH_INVALID_CNT_MAX_BINARY <= "00001001"; + when 11 => SH_INVALID_CNT_MAX_BINARY <= "00001010"; + when 12 => SH_INVALID_CNT_MAX_BINARY <= "00001011"; + when 13 => SH_INVALID_CNT_MAX_BINARY <= "00001100"; + when 14 => SH_INVALID_CNT_MAX_BINARY <= "00001101"; + when 15 => SH_INVALID_CNT_MAX_BINARY <= "00001110"; + when 16 => SH_INVALID_CNT_MAX_BINARY <= "00001111"; + when 17 => SH_INVALID_CNT_MAX_BINARY <= "00010000"; + when 18 => SH_INVALID_CNT_MAX_BINARY <= "00010001"; + when 19 => SH_INVALID_CNT_MAX_BINARY <= "00010010"; + when 20 => SH_INVALID_CNT_MAX_BINARY <= "00010011"; + when 21 => SH_INVALID_CNT_MAX_BINARY <= "00010100"; + when 22 => SH_INVALID_CNT_MAX_BINARY <= "00010101"; + when 23 => SH_INVALID_CNT_MAX_BINARY <= "00010110"; + when 24 => SH_INVALID_CNT_MAX_BINARY <= "00010111"; + when 25 => SH_INVALID_CNT_MAX_BINARY <= "00011000"; + when 26 => SH_INVALID_CNT_MAX_BINARY <= "00011001"; + when 27 => SH_INVALID_CNT_MAX_BINARY <= "00011010"; + when 28 => SH_INVALID_CNT_MAX_BINARY <= "00011011"; + when 29 => SH_INVALID_CNT_MAX_BINARY <= "00011100"; + when 30 => SH_INVALID_CNT_MAX_BINARY <= "00011101"; + when 31 => SH_INVALID_CNT_MAX_BINARY <= "00011110"; + when 32 => SH_INVALID_CNT_MAX_BINARY <= "00011111"; + when 33 => SH_INVALID_CNT_MAX_BINARY <= "00100000"; + when 34 => SH_INVALID_CNT_MAX_BINARY <= "00100001"; + when 35 => SH_INVALID_CNT_MAX_BINARY <= "00100010"; + when 36 => SH_INVALID_CNT_MAX_BINARY <= "00100011"; + when 37 => SH_INVALID_CNT_MAX_BINARY <= "00100100"; + when 38 => SH_INVALID_CNT_MAX_BINARY <= "00100101"; + when 39 => SH_INVALID_CNT_MAX_BINARY <= "00100110"; + when 40 => SH_INVALID_CNT_MAX_BINARY <= "00100111"; + when 41 => SH_INVALID_CNT_MAX_BINARY <= "00101000"; + when 42 => SH_INVALID_CNT_MAX_BINARY <= "00101001"; + when 43 => SH_INVALID_CNT_MAX_BINARY <= "00101010"; + when 44 => SH_INVALID_CNT_MAX_BINARY <= "00101011"; + when 45 => SH_INVALID_CNT_MAX_BINARY <= "00101100"; + when 46 => SH_INVALID_CNT_MAX_BINARY <= "00101101"; + when 47 => SH_INVALID_CNT_MAX_BINARY <= "00101110"; + when 48 => SH_INVALID_CNT_MAX_BINARY <= "00101111"; + when 49 => SH_INVALID_CNT_MAX_BINARY <= "00110000"; + when 50 => SH_INVALID_CNT_MAX_BINARY <= "00110001"; + when 51 => SH_INVALID_CNT_MAX_BINARY <= "00110010"; + when 52 => SH_INVALID_CNT_MAX_BINARY <= "00110011"; + when 53 => SH_INVALID_CNT_MAX_BINARY <= "00110100"; + when 54 => SH_INVALID_CNT_MAX_BINARY <= "00110101"; + when 55 => SH_INVALID_CNT_MAX_BINARY <= "00110110"; + when 56 => SH_INVALID_CNT_MAX_BINARY <= "00110111"; + when 57 => SH_INVALID_CNT_MAX_BINARY <= "00111000"; + when 58 => SH_INVALID_CNT_MAX_BINARY <= "00111001"; + when 59 => SH_INVALID_CNT_MAX_BINARY <= "00111010"; + when 60 => SH_INVALID_CNT_MAX_BINARY <= "00111011"; + when 61 => SH_INVALID_CNT_MAX_BINARY <= "00111100"; + when 62 => SH_INVALID_CNT_MAX_BINARY <= "00111101"; + when 63 => SH_INVALID_CNT_MAX_BINARY <= "00111110"; + when 64 => SH_INVALID_CNT_MAX_BINARY <= "00111111"; + when 65 => SH_INVALID_CNT_MAX_BINARY <= "01000000"; + when 66 => SH_INVALID_CNT_MAX_BINARY <= "01000001"; + when 67 => SH_INVALID_CNT_MAX_BINARY <= "01000010"; + when 68 => SH_INVALID_CNT_MAX_BINARY <= "01000011"; + when 69 => SH_INVALID_CNT_MAX_BINARY <= "01000100"; + when 70 => SH_INVALID_CNT_MAX_BINARY <= "01000101"; + when 71 => SH_INVALID_CNT_MAX_BINARY <= "01000110"; + when 72 => SH_INVALID_CNT_MAX_BINARY <= "01000111"; + when 73 => SH_INVALID_CNT_MAX_BINARY <= "01001000"; + when 74 => SH_INVALID_CNT_MAX_BINARY <= "01001001"; + when 75 => SH_INVALID_CNT_MAX_BINARY <= "01001010"; + when 76 => SH_INVALID_CNT_MAX_BINARY <= "01001011"; + when 77 => SH_INVALID_CNT_MAX_BINARY <= "01001100"; + when 78 => SH_INVALID_CNT_MAX_BINARY <= "01001101"; + when 79 => SH_INVALID_CNT_MAX_BINARY <= "01001110"; + when 80 => SH_INVALID_CNT_MAX_BINARY <= "01001111"; + when 81 => SH_INVALID_CNT_MAX_BINARY <= "01010000"; + when 82 => SH_INVALID_CNT_MAX_BINARY <= "01010001"; + when 83 => SH_INVALID_CNT_MAX_BINARY <= "01010010"; + when 84 => SH_INVALID_CNT_MAX_BINARY <= "01010011"; + when 85 => SH_INVALID_CNT_MAX_BINARY <= "01010100"; + when 86 => SH_INVALID_CNT_MAX_BINARY <= "01010101"; + when 87 => SH_INVALID_CNT_MAX_BINARY <= "01010110"; + when 88 => SH_INVALID_CNT_MAX_BINARY <= "01010111"; + when 89 => SH_INVALID_CNT_MAX_BINARY <= "01011000"; + when 90 => SH_INVALID_CNT_MAX_BINARY <= "01011001"; + when 91 => SH_INVALID_CNT_MAX_BINARY <= "01011010"; + when 92 => SH_INVALID_CNT_MAX_BINARY <= "01011011"; + when 93 => SH_INVALID_CNT_MAX_BINARY <= "01011100"; + when 94 => SH_INVALID_CNT_MAX_BINARY <= "01011101"; + when 95 => SH_INVALID_CNT_MAX_BINARY <= "01011110"; + when 96 => SH_INVALID_CNT_MAX_BINARY <= "01011111"; + when 97 => SH_INVALID_CNT_MAX_BINARY <= "01100000"; + when 98 => SH_INVALID_CNT_MAX_BINARY <= "01100001"; + when 99 => SH_INVALID_CNT_MAX_BINARY <= "01100010"; + when 100 => SH_INVALID_CNT_MAX_BINARY <= "01100011"; + when 101 => SH_INVALID_CNT_MAX_BINARY <= "01100100"; + when 102 => SH_INVALID_CNT_MAX_BINARY <= "01100101"; + when 103 => SH_INVALID_CNT_MAX_BINARY <= "01100110"; + when 104 => SH_INVALID_CNT_MAX_BINARY <= "01100111"; + when 105 => SH_INVALID_CNT_MAX_BINARY <= "01101000"; + when 106 => SH_INVALID_CNT_MAX_BINARY <= "01101001"; + when 107 => SH_INVALID_CNT_MAX_BINARY <= "01101010"; + when 108 => SH_INVALID_CNT_MAX_BINARY <= "01101011"; + when 109 => SH_INVALID_CNT_MAX_BINARY <= "01101100"; + when 110 => SH_INVALID_CNT_MAX_BINARY <= "01101101"; + when 111 => SH_INVALID_CNT_MAX_BINARY <= "01101110"; + when 112 => SH_INVALID_CNT_MAX_BINARY <= "01101111"; + when 113 => SH_INVALID_CNT_MAX_BINARY <= "01110000"; + when 114 => SH_INVALID_CNT_MAX_BINARY <= "01110001"; + when 115 => SH_INVALID_CNT_MAX_BINARY <= "01110010"; + when 116 => SH_INVALID_CNT_MAX_BINARY <= "01110011"; + when 117 => SH_INVALID_CNT_MAX_BINARY <= "01110100"; + when 118 => SH_INVALID_CNT_MAX_BINARY <= "01110101"; + when 119 => SH_INVALID_CNT_MAX_BINARY <= "01110110"; + when 120 => SH_INVALID_CNT_MAX_BINARY <= "01110111"; + when 121 => SH_INVALID_CNT_MAX_BINARY <= "01111000"; + when 122 => SH_INVALID_CNT_MAX_BINARY <= "01111001"; + when 123 => SH_INVALID_CNT_MAX_BINARY <= "01111010"; + when 124 => SH_INVALID_CNT_MAX_BINARY <= "01111011"; + when 125 => SH_INVALID_CNT_MAX_BINARY <= "01111100"; + when 126 => SH_INVALID_CNT_MAX_BINARY <= "01111101"; + when 127 => SH_INVALID_CNT_MAX_BINARY <= "01111110"; + when 128 => SH_INVALID_CNT_MAX_BINARY <= "01111111"; + when 129 => SH_INVALID_CNT_MAX_BINARY <= "10000000"; + when 130 => SH_INVALID_CNT_MAX_BINARY <= "10000001"; + when 131 => SH_INVALID_CNT_MAX_BINARY <= "10000010"; + when 132 => SH_INVALID_CNT_MAX_BINARY <= "10000011"; + when 133 => SH_INVALID_CNT_MAX_BINARY <= "10000100"; + when 134 => SH_INVALID_CNT_MAX_BINARY <= "10000101"; + when 135 => SH_INVALID_CNT_MAX_BINARY <= "10000110"; + when 136 => SH_INVALID_CNT_MAX_BINARY <= "10000111"; + when 137 => SH_INVALID_CNT_MAX_BINARY <= "10001000"; + when 138 => SH_INVALID_CNT_MAX_BINARY <= "10001001"; + when 139 => SH_INVALID_CNT_MAX_BINARY <= "10001010"; + when 140 => SH_INVALID_CNT_MAX_BINARY <= "10001011"; + when 141 => SH_INVALID_CNT_MAX_BINARY <= "10001100"; + when 142 => SH_INVALID_CNT_MAX_BINARY <= "10001101"; + when 143 => SH_INVALID_CNT_MAX_BINARY <= "10001110"; + when 144 => SH_INVALID_CNT_MAX_BINARY <= "10001111"; + when 145 => SH_INVALID_CNT_MAX_BINARY <= "10010000"; + when 146 => SH_INVALID_CNT_MAX_BINARY <= "10010001"; + when 147 => SH_INVALID_CNT_MAX_BINARY <= "10010010"; + when 148 => SH_INVALID_CNT_MAX_BINARY <= "10010011"; + when 149 => SH_INVALID_CNT_MAX_BINARY <= "10010100"; + when 150 => SH_INVALID_CNT_MAX_BINARY <= "10010101"; + when 151 => SH_INVALID_CNT_MAX_BINARY <= "10010110"; + when 152 => SH_INVALID_CNT_MAX_BINARY <= "10010111"; + when 153 => SH_INVALID_CNT_MAX_BINARY <= "10011000"; + when 154 => SH_INVALID_CNT_MAX_BINARY <= "10011001"; + when 155 => SH_INVALID_CNT_MAX_BINARY <= "10011010"; + when 156 => SH_INVALID_CNT_MAX_BINARY <= "10011011"; + when 157 => SH_INVALID_CNT_MAX_BINARY <= "10011100"; + when 158 => SH_INVALID_CNT_MAX_BINARY <= "10011101"; + when 159 => SH_INVALID_CNT_MAX_BINARY <= "10011110"; + when 160 => SH_INVALID_CNT_MAX_BINARY <= "10011111"; + when 161 => SH_INVALID_CNT_MAX_BINARY <= "10100000"; + when 162 => SH_INVALID_CNT_MAX_BINARY <= "10100001"; + when 163 => SH_INVALID_CNT_MAX_BINARY <= "10100010"; + when 164 => SH_INVALID_CNT_MAX_BINARY <= "10100011"; + when 165 => SH_INVALID_CNT_MAX_BINARY <= "10100100"; + when 166 => SH_INVALID_CNT_MAX_BINARY <= "10100101"; + when 167 => SH_INVALID_CNT_MAX_BINARY <= "10100110"; + when 168 => SH_INVALID_CNT_MAX_BINARY <= "10100111"; + when 169 => SH_INVALID_CNT_MAX_BINARY <= "10101000"; + when 170 => SH_INVALID_CNT_MAX_BINARY <= "10101001"; + when 171 => SH_INVALID_CNT_MAX_BINARY <= "10101010"; + when 172 => SH_INVALID_CNT_MAX_BINARY <= "10101011"; + when 173 => SH_INVALID_CNT_MAX_BINARY <= "10101100"; + when 174 => SH_INVALID_CNT_MAX_BINARY <= "10101101"; + when 175 => SH_INVALID_CNT_MAX_BINARY <= "10101110"; + when 176 => SH_INVALID_CNT_MAX_BINARY <= "10101111"; + when 177 => SH_INVALID_CNT_MAX_BINARY <= "10110000"; + when 178 => SH_INVALID_CNT_MAX_BINARY <= "10110001"; + when 179 => SH_INVALID_CNT_MAX_BINARY <= "10110010"; + when 180 => SH_INVALID_CNT_MAX_BINARY <= "10110011"; + when 181 => SH_INVALID_CNT_MAX_BINARY <= "10110100"; + when 182 => SH_INVALID_CNT_MAX_BINARY <= "10110101"; + when 183 => SH_INVALID_CNT_MAX_BINARY <= "10110110"; + when 184 => SH_INVALID_CNT_MAX_BINARY <= "10110111"; + when 185 => SH_INVALID_CNT_MAX_BINARY <= "10111000"; + when 186 => SH_INVALID_CNT_MAX_BINARY <= "10111001"; + when 187 => SH_INVALID_CNT_MAX_BINARY <= "10111010"; + when 188 => SH_INVALID_CNT_MAX_BINARY <= "10111011"; + when 189 => SH_INVALID_CNT_MAX_BINARY <= "10111100"; + when 190 => SH_INVALID_CNT_MAX_BINARY <= "10111101"; + when 191 => SH_INVALID_CNT_MAX_BINARY <= "10111110"; + when 192 => SH_INVALID_CNT_MAX_BINARY <= "10111111"; + when 193 => SH_INVALID_CNT_MAX_BINARY <= "11000000"; + when 194 => SH_INVALID_CNT_MAX_BINARY <= "11000001"; + when 195 => SH_INVALID_CNT_MAX_BINARY <= "11000010"; + when 196 => SH_INVALID_CNT_MAX_BINARY <= "11000011"; + when 197 => SH_INVALID_CNT_MAX_BINARY <= "11000100"; + when 198 => SH_INVALID_CNT_MAX_BINARY <= "11000101"; + when 199 => SH_INVALID_CNT_MAX_BINARY <= "11000110"; + when 200 => SH_INVALID_CNT_MAX_BINARY <= "11000111"; + when 201 => SH_INVALID_CNT_MAX_BINARY <= "11001000"; + when 202 => SH_INVALID_CNT_MAX_BINARY <= "11001001"; + when 203 => SH_INVALID_CNT_MAX_BINARY <= "11001010"; + when 204 => SH_INVALID_CNT_MAX_BINARY <= "11001011"; + when 205 => SH_INVALID_CNT_MAX_BINARY <= "11001100"; + when 206 => SH_INVALID_CNT_MAX_BINARY <= "11001101"; + when 207 => SH_INVALID_CNT_MAX_BINARY <= "11001110"; + when 208 => SH_INVALID_CNT_MAX_BINARY <= "11001111"; + when 209 => SH_INVALID_CNT_MAX_BINARY <= "11010000"; + when 210 => SH_INVALID_CNT_MAX_BINARY <= "11010001"; + when 211 => SH_INVALID_CNT_MAX_BINARY <= "11010010"; + when 212 => SH_INVALID_CNT_MAX_BINARY <= "11010011"; + when 213 => SH_INVALID_CNT_MAX_BINARY <= "11010100"; + when 214 => SH_INVALID_CNT_MAX_BINARY <= "11010101"; + when 215 => SH_INVALID_CNT_MAX_BINARY <= "11010110"; + when 216 => SH_INVALID_CNT_MAX_BINARY <= "11010111"; + when 217 => SH_INVALID_CNT_MAX_BINARY <= "11011000"; + when 218 => SH_INVALID_CNT_MAX_BINARY <= "11011001"; + when 219 => SH_INVALID_CNT_MAX_BINARY <= "11011010"; + when 220 => SH_INVALID_CNT_MAX_BINARY <= "11011011"; + when 221 => SH_INVALID_CNT_MAX_BINARY <= "11011100"; + when 222 => SH_INVALID_CNT_MAX_BINARY <= "11011101"; + when 223 => SH_INVALID_CNT_MAX_BINARY <= "11011110"; + when 224 => SH_INVALID_CNT_MAX_BINARY <= "11011111"; + when 225 => SH_INVALID_CNT_MAX_BINARY <= "11100000"; + when 226 => SH_INVALID_CNT_MAX_BINARY <= "11100001"; + when 227 => SH_INVALID_CNT_MAX_BINARY <= "11100010"; + when 228 => SH_INVALID_CNT_MAX_BINARY <= "11100011"; + when 229 => SH_INVALID_CNT_MAX_BINARY <= "11100100"; + when 230 => SH_INVALID_CNT_MAX_BINARY <= "11100101"; + when 231 => SH_INVALID_CNT_MAX_BINARY <= "11100110"; + when 232 => SH_INVALID_CNT_MAX_BINARY <= "11100111"; + when 233 => SH_INVALID_CNT_MAX_BINARY <= "11101000"; + when 234 => SH_INVALID_CNT_MAX_BINARY <= "11101001"; + when 235 => SH_INVALID_CNT_MAX_BINARY <= "11101010"; + when 236 => SH_INVALID_CNT_MAX_BINARY <= "11101011"; + when 237 => SH_INVALID_CNT_MAX_BINARY <= "11101100"; + when 238 => SH_INVALID_CNT_MAX_BINARY <= "11101101"; + when 239 => SH_INVALID_CNT_MAX_BINARY <= "11101110"; + when 240 => SH_INVALID_CNT_MAX_BINARY <= "11101111"; + when 241 => SH_INVALID_CNT_MAX_BINARY <= "11110000"; + when 242 => SH_INVALID_CNT_MAX_BINARY <= "11110001"; + when 243 => SH_INVALID_CNT_MAX_BINARY <= "11110010"; + when 244 => SH_INVALID_CNT_MAX_BINARY <= "11110011"; + when 245 => SH_INVALID_CNT_MAX_BINARY <= "11110100"; + when 246 => SH_INVALID_CNT_MAX_BINARY <= "11110101"; + when 247 => SH_INVALID_CNT_MAX_BINARY <= "11110110"; + when 248 => SH_INVALID_CNT_MAX_BINARY <= "11110111"; + when 249 => SH_INVALID_CNT_MAX_BINARY <= "11111000"; + when 250 => SH_INVALID_CNT_MAX_BINARY <= "11111001"; + when 251 => SH_INVALID_CNT_MAX_BINARY <= "11111010"; + when 252 => SH_INVALID_CNT_MAX_BINARY <= "11111011"; + when 253 => SH_INVALID_CNT_MAX_BINARY <= "11111100"; + when 254 => SH_INVALID_CNT_MAX_BINARY <= "11111101"; + when 255 => SH_INVALID_CNT_MAX_BINARY <= "11111110"; + when 256 => SH_INVALID_CNT_MAX_BINARY <= "11111111"; + when others => assert FALSE report "Error : SH_INVALID_CNT_MAX is not in range 1...256." severity warning; + end case; + case TX_BUFFER_USE is + when FALSE => TX_BUFFER_USE_BINARY <= '0'; + when TRUE => TX_BUFFER_USE_BINARY <= '1'; + when others => assert FALSE report "Error : TX_BUFFER_USE is neither TRUE nor FALSE." severity warning; + end case; + wait; + end process INIPROC; + + TIMING : process + +-- Pin timing violations (clock input pins) + +-- Pin Timing Violations (all input pins) +-- Output Pin glitch declaration + variable CHBONDDONE_GlitchData : VitalGlitchDataType; + variable CHBONDO0_GlitchData : VitalGlitchDataType; + variable CHBONDO1_GlitchData : VitalGlitchDataType; + variable CHBONDO2_GlitchData : VitalGlitchDataType; + variable CHBONDO3_GlitchData : VitalGlitchDataType; + variable CHBONDO4_GlitchData : VitalGlitchDataType; + variable PMARXLOCK_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS0_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS1_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA0_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA1_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA2_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA3_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA4_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA5_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA6_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA7_GlitchData : VitalGlitchDataType; + variable RXCHARISK0_GlitchData : VitalGlitchDataType; + variable RXCHARISK1_GlitchData : VitalGlitchDataType; + variable RXCHARISK2_GlitchData : VitalGlitchDataType; + variable RXCHARISK3_GlitchData : VitalGlitchDataType; + variable RXCHARISK4_GlitchData : VitalGlitchDataType; + variable RXCHARISK5_GlitchData : VitalGlitchDataType; + variable RXCHARISK6_GlitchData : VitalGlitchDataType; + variable RXCHARISK7_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT0_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT1_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT2_GlitchData : VitalGlitchDataType; + variable RXCOMMADET_GlitchData : VitalGlitchDataType; + variable RXDATA0_GlitchData : VitalGlitchDataType; + variable RXDATA1_GlitchData : VitalGlitchDataType; + variable RXDATA2_GlitchData : VitalGlitchDataType; + variable RXDATA3_GlitchData : VitalGlitchDataType; + variable RXDATA4_GlitchData : VitalGlitchDataType; + variable RXDATA5_GlitchData : VitalGlitchDataType; + variable RXDATA6_GlitchData : VitalGlitchDataType; + variable RXDATA7_GlitchData : VitalGlitchDataType; + variable RXDATA8_GlitchData : VitalGlitchDataType; + variable RXDATA9_GlitchData : VitalGlitchDataType; + variable RXDATA10_GlitchData : VitalGlitchDataType; + variable RXDATA11_GlitchData : VitalGlitchDataType; + variable RXDATA12_GlitchData : VitalGlitchDataType; + variable RXDATA13_GlitchData : VitalGlitchDataType; + variable RXDATA14_GlitchData : VitalGlitchDataType; + variable RXDATA15_GlitchData : VitalGlitchDataType; + variable RXDATA16_GlitchData : VitalGlitchDataType; + variable RXDATA17_GlitchData : VitalGlitchDataType; + variable RXDATA18_GlitchData : VitalGlitchDataType; + variable RXDATA19_GlitchData : VitalGlitchDataType; + variable RXDATA20_GlitchData : VitalGlitchDataType; + variable RXDATA21_GlitchData : VitalGlitchDataType; + variable RXDATA22_GlitchData : VitalGlitchDataType; + variable RXDATA23_GlitchData : VitalGlitchDataType; + variable RXDATA24_GlitchData : VitalGlitchDataType; + variable RXDATA25_GlitchData : VitalGlitchDataType; + variable RXDATA26_GlitchData : VitalGlitchDataType; + variable RXDATA27_GlitchData : VitalGlitchDataType; + variable RXDATA28_GlitchData : VitalGlitchDataType; + variable RXDATA29_GlitchData : VitalGlitchDataType; + variable RXDATA30_GlitchData : VitalGlitchDataType; + variable RXDATA31_GlitchData : VitalGlitchDataType; + variable RXDATA32_GlitchData : VitalGlitchDataType; + variable RXDATA33_GlitchData : VitalGlitchDataType; + variable RXDATA34_GlitchData : VitalGlitchDataType; + variable RXDATA35_GlitchData : VitalGlitchDataType; + variable RXDATA36_GlitchData : VitalGlitchDataType; + variable RXDATA37_GlitchData : VitalGlitchDataType; + variable RXDATA38_GlitchData : VitalGlitchDataType; + variable RXDATA39_GlitchData : VitalGlitchDataType; + variable RXDATA40_GlitchData : VitalGlitchDataType; + variable RXDATA41_GlitchData : VitalGlitchDataType; + variable RXDATA42_GlitchData : VitalGlitchDataType; + variable RXDATA43_GlitchData : VitalGlitchDataType; + variable RXDATA44_GlitchData : VitalGlitchDataType; + variable RXDATA45_GlitchData : VitalGlitchDataType; + variable RXDATA46_GlitchData : VitalGlitchDataType; + variable RXDATA47_GlitchData : VitalGlitchDataType; + variable RXDATA48_GlitchData : VitalGlitchDataType; + variable RXDATA49_GlitchData : VitalGlitchDataType; + variable RXDATA50_GlitchData : VitalGlitchDataType; + variable RXDATA51_GlitchData : VitalGlitchDataType; + variable RXDATA52_GlitchData : VitalGlitchDataType; + variable RXDATA53_GlitchData : VitalGlitchDataType; + variable RXDATA54_GlitchData : VitalGlitchDataType; + variable RXDATA55_GlitchData : VitalGlitchDataType; + variable RXDATA56_GlitchData : VitalGlitchDataType; + variable RXDATA57_GlitchData : VitalGlitchDataType; + variable RXDATA58_GlitchData : VitalGlitchDataType; + variable RXDATA59_GlitchData : VitalGlitchDataType; + variable RXDATA60_GlitchData : VitalGlitchDataType; + variable RXDATA61_GlitchData : VitalGlitchDataType; + variable RXDATA62_GlitchData : VitalGlitchDataType; + variable RXDATA63_GlitchData : VitalGlitchDataType; + variable RXDISPERR0_GlitchData : VitalGlitchDataType; + variable RXDISPERR1_GlitchData : VitalGlitchDataType; + variable RXDISPERR2_GlitchData : VitalGlitchDataType; + variable RXDISPERR3_GlitchData : VitalGlitchDataType; + variable RXDISPERR4_GlitchData : VitalGlitchDataType; + variable RXDISPERR5_GlitchData : VitalGlitchDataType; + variable RXDISPERR6_GlitchData : VitalGlitchDataType; + variable RXDISPERR7_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC0_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC1_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE0_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE1_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE2_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE3_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE4_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE5_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE6_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE7_GlitchData : VitalGlitchDataType; + variable RXREALIGN_GlitchData : VitalGlitchDataType; +-- variable RXRECCLK_GlitchData : VitalGlitchDataType; + variable RXRUNDISP0_GlitchData : VitalGlitchDataType; + variable RXRUNDISP1_GlitchData : VitalGlitchDataType; + variable RXRUNDISP2_GlitchData : VitalGlitchDataType; + variable RXRUNDISP3_GlitchData : VitalGlitchDataType; + variable RXRUNDISP4_GlitchData : VitalGlitchDataType; + variable RXRUNDISP5_GlitchData : VitalGlitchDataType; + variable RXRUNDISP6_GlitchData : VitalGlitchDataType; + variable RXRUNDISP7_GlitchData : VitalGlitchDataType; + variable TXBUFERR_GlitchData : VitalGlitchDataType; + variable TXKERR0_GlitchData : VitalGlitchDataType; + variable TXKERR1_GlitchData : VitalGlitchDataType; + variable TXKERR2_GlitchData : VitalGlitchDataType; + variable TXKERR3_GlitchData : VitalGlitchDataType; + variable TXKERR4_GlitchData : VitalGlitchDataType; + variable TXKERR5_GlitchData : VitalGlitchDataType; + variable TXKERR6_GlitchData : VitalGlitchDataType; + variable TXKERR7_GlitchData : VitalGlitchDataType; +-- variable TXN_GlitchData : VitalGlitchDataType; +-- variable TXOUTCLK_GlitchData : VitalGlitchDataType; +-- variable TXP_GlitchData : VitalGlitchDataType; + variable TXRUNDISP0_GlitchData : VitalGlitchDataType; + variable TXRUNDISP1_GlitchData : VitalGlitchDataType; + variable TXRUNDISP2_GlitchData : VitalGlitchDataType; + variable TXRUNDISP3_GlitchData : VitalGlitchDataType; + variable TXRUNDISP4_GlitchData : VitalGlitchDataType; + variable TXRUNDISP5_GlitchData : VitalGlitchDataType; + variable TXRUNDISP6_GlitchData : VitalGlitchDataType; + variable TXRUNDISP7_GlitchData : VitalGlitchDataType; +begin + +-- Setup/Hold Check Violations (all input pins) + + +-- End of (TimingChecksOn) + +-- Output-to-Clock path delay + VitalPathDelay01 + ( + OutSignal => CHBONDDONE, + GlitchData => CHBONDDONE_GlitchData, + OutSignalName => "CHBONDDONE", + OutTemp => CHBONDDONE_OUT, + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CHBONDO(0), + GlitchData => CHBONDO0_GlitchData, + OutSignalName => "CHBONDO(0)", + OutTemp => CHBONDO_OUT(0), + Paths => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CHBONDO(1), + GlitchData => CHBONDO1_GlitchData, + OutSignalName => "CHBONDO(1)", + OutTemp => CHBONDO_OUT(1), + Paths => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CHBONDO(2), + GlitchData => CHBONDO2_GlitchData, + OutSignalName => "CHBONDO(2)", + OutTemp => CHBONDO_OUT(2), + Paths => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CHBONDO(3), + GlitchData => CHBONDO3_GlitchData, + OutSignalName => "CHBONDO(3)", + OutTemp => CHBONDO_OUT(3), + Paths => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CHBONDO(4), + GlitchData => CHBONDO4_GlitchData, + OutSignalName => "CHBONDO(4)", + OutTemp => CHBONDO_OUT(4), + Paths => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS(0), + GlitchData => RXBUFSTATUS0_GlitchData, + OutSignalName => "RXBUFSTATUS(0)", + OutTemp => RXBUFSTATUS_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS(1), + GlitchData => RXBUFSTATUS1_GlitchData, + OutSignalName => "RXBUFSTATUS(1)", + OutTemp => RXBUFSTATUS_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(0), + GlitchData => RXCHARISCOMMA0_GlitchData, + OutSignalName => "RXCHARISCOMMA(0)", + OutTemp => RXCHARISCOMMA_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(1), + GlitchData => RXCHARISCOMMA1_GlitchData, + OutSignalName => "RXCHARISCOMMA(1)", + OutTemp => RXCHARISCOMMA_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(2), + GlitchData => RXCHARISCOMMA2_GlitchData, + OutSignalName => "RXCHARISCOMMA(2)", + OutTemp => RXCHARISCOMMA_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(3), + GlitchData => RXCHARISCOMMA3_GlitchData, + OutSignalName => "RXCHARISCOMMA(3)", + OutTemp => RXCHARISCOMMA_OUT(3), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(4), + GlitchData => RXCHARISCOMMA4_GlitchData, + OutSignalName => "RXCHARISCOMMA(4)", + OutTemp => RXCHARISCOMMA_OUT(4), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(5), + GlitchData => RXCHARISCOMMA5_GlitchData, + OutSignalName => "RXCHARISCOMMA(5)", + OutTemp => RXCHARISCOMMA_OUT(5), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(6), + GlitchData => RXCHARISCOMMA6_GlitchData, + OutSignalName => "RXCHARISCOMMA(6)", + OutTemp => RXCHARISCOMMA_OUT(6), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(7), + GlitchData => RXCHARISCOMMA7_GlitchData, + OutSignalName => "RXCHARISCOMMA(7)", + OutTemp => RXCHARISCOMMA_OUT(7), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(0), + GlitchData => RXCHARISK0_GlitchData, + OutSignalName => "RXCHARISK(0)", + OutTemp => RXCHARISK_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(1), + GlitchData => RXCHARISK1_GlitchData, + OutSignalName => "RXCHARISK(1)", + OutTemp => RXCHARISK_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(2), + GlitchData => RXCHARISK2_GlitchData, + OutSignalName => "RXCHARISK(2)", + OutTemp => RXCHARISK_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(3), + GlitchData => RXCHARISK3_GlitchData, + OutSignalName => "RXCHARISK(3)", + OutTemp => RXCHARISK_OUT(3), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(4), + GlitchData => RXCHARISK4_GlitchData, + OutSignalName => "RXCHARISK(4)", + OutTemp => RXCHARISK_OUT(4), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(5), + GlitchData => RXCHARISK5_GlitchData, + OutSignalName => "RXCHARISK(5)", + OutTemp => RXCHARISK_OUT(5), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(6), + GlitchData => RXCHARISK6_GlitchData, + OutSignalName => "RXCHARISK(6)", + OutTemp => RXCHARISK_OUT(6), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(7), + GlitchData => RXCHARISK7_GlitchData, + OutSignalName => "RXCHARISK(7)", + OutTemp => RXCHARISK_OUT(7), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT(0), + GlitchData => RXCLKCORCNT0_GlitchData, + OutSignalName => "RXCLKCORCNT(0)", + OutTemp => RXCLKCORCNT_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT(1), + GlitchData => RXCLKCORCNT1_GlitchData, + OutSignalName => "RXCLKCORCNT(1)", + OutTemp => RXCLKCORCNT_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT(2), + GlitchData => RXCLKCORCNT2_GlitchData, + OutSignalName => "RXCLKCORCNT(2)", + OutTemp => RXCLKCORCNT_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCOMMADET, + GlitchData => RXCOMMADET_GlitchData, + OutSignalName => "RXCOMMADET", + OutTemp => RXCOMMADET_OUT, + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(0), + GlitchData => RXDATA0_GlitchData, + OutSignalName => "RXDATA(0)", + OutTemp => RXDATA_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(1), + GlitchData => RXDATA1_GlitchData, + OutSignalName => "RXDATA(1)", + OutTemp => RXDATA_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(2), + GlitchData => RXDATA2_GlitchData, + OutSignalName => "RXDATA(2)", + OutTemp => RXDATA_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(3), + GlitchData => RXDATA3_GlitchData, + OutSignalName => "RXDATA(3)", + OutTemp => RXDATA_OUT(3), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(4), + GlitchData => RXDATA4_GlitchData, + OutSignalName => "RXDATA(4)", + OutTemp => RXDATA_OUT(4), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(5), + GlitchData => RXDATA5_GlitchData, + OutSignalName => "RXDATA(5)", + OutTemp => RXDATA_OUT(5), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(6), + GlitchData => RXDATA6_GlitchData, + OutSignalName => "RXDATA(6)", + OutTemp => RXDATA_OUT(6), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(7), + GlitchData => RXDATA7_GlitchData, + OutSignalName => "RXDATA(7)", + OutTemp => RXDATA_OUT(7), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(8), + GlitchData => RXDATA8_GlitchData, + OutSignalName => "RXDATA(8)", + OutTemp => RXDATA_OUT(8), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(9), + GlitchData => RXDATA9_GlitchData, + OutSignalName => "RXDATA(9)", + OutTemp => RXDATA_OUT(9), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(10), + GlitchData => RXDATA10_GlitchData, + OutSignalName => "RXDATA(10)", + OutTemp => RXDATA_OUT(10), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(11), + GlitchData => RXDATA11_GlitchData, + OutSignalName => "RXDATA(11)", + OutTemp => RXDATA_OUT(11), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(12), + GlitchData => RXDATA12_GlitchData, + OutSignalName => "RXDATA(12)", + OutTemp => RXDATA_OUT(12), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(13), + GlitchData => RXDATA13_GlitchData, + OutSignalName => "RXDATA(13)", + OutTemp => RXDATA_OUT(13), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(14), + GlitchData => RXDATA14_GlitchData, + OutSignalName => "RXDATA(14)", + OutTemp => RXDATA_OUT(14), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(15), + GlitchData => RXDATA15_GlitchData, + OutSignalName => "RXDATA(15)", + OutTemp => RXDATA_OUT(15), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(16), + GlitchData => RXDATA16_GlitchData, + OutSignalName => "RXDATA(16)", + OutTemp => RXDATA_OUT(16), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(17), + GlitchData => RXDATA17_GlitchData, + OutSignalName => "RXDATA(17)", + OutTemp => RXDATA_OUT(17), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(18), + GlitchData => RXDATA18_GlitchData, + OutSignalName => "RXDATA(18)", + OutTemp => RXDATA_OUT(18), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(19), + GlitchData => RXDATA19_GlitchData, + OutSignalName => "RXDATA(19)", + OutTemp => RXDATA_OUT(19), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(20), + GlitchData => RXDATA20_GlitchData, + OutSignalName => "RXDATA(20)", + OutTemp => RXDATA_OUT(20), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(21), + GlitchData => RXDATA21_GlitchData, + OutSignalName => "RXDATA(21)", + OutTemp => RXDATA_OUT(21), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(22), + GlitchData => RXDATA22_GlitchData, + OutSignalName => "RXDATA(22)", + OutTemp => RXDATA_OUT(22), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(23), + GlitchData => RXDATA23_GlitchData, + OutSignalName => "RXDATA(23)", + OutTemp => RXDATA_OUT(23), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(24), + GlitchData => RXDATA24_GlitchData, + OutSignalName => "RXDATA(24)", + OutTemp => RXDATA_OUT(24), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(25), + GlitchData => RXDATA25_GlitchData, + OutSignalName => "RXDATA(25)", + OutTemp => RXDATA_OUT(25), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(26), + GlitchData => RXDATA26_GlitchData, + OutSignalName => "RXDATA(26)", + OutTemp => RXDATA_OUT(26), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(27), + GlitchData => RXDATA27_GlitchData, + OutSignalName => "RXDATA(27)", + OutTemp => RXDATA_OUT(27), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(28), + GlitchData => RXDATA28_GlitchData, + OutSignalName => "RXDATA(28)", + OutTemp => RXDATA_OUT(28), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(29), + GlitchData => RXDATA29_GlitchData, + OutSignalName => "RXDATA(29)", + OutTemp => RXDATA_OUT(29), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(30), + GlitchData => RXDATA30_GlitchData, + OutSignalName => "RXDATA(30)", + OutTemp => RXDATA_OUT(30), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(31), + GlitchData => RXDATA31_GlitchData, + OutSignalName => "RXDATA(31)", + OutTemp => RXDATA_OUT(31), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(32), + GlitchData => RXDATA32_GlitchData, + OutSignalName => "RXDATA(32)", + OutTemp => RXDATA_OUT(32), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(33), + GlitchData => RXDATA33_GlitchData, + OutSignalName => "RXDATA(33)", + OutTemp => RXDATA_OUT(33), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(34), + GlitchData => RXDATA34_GlitchData, + OutSignalName => "RXDATA(34)", + OutTemp => RXDATA_OUT(34), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(35), + GlitchData => RXDATA35_GlitchData, + OutSignalName => "RXDATA(35)", + OutTemp => RXDATA_OUT(35), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(36), + GlitchData => RXDATA36_GlitchData, + OutSignalName => "RXDATA(36)", + OutTemp => RXDATA_OUT(36), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(37), + GlitchData => RXDATA37_GlitchData, + OutSignalName => "RXDATA(37)", + OutTemp => RXDATA_OUT(37), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(38), + GlitchData => RXDATA38_GlitchData, + OutSignalName => "RXDATA(38)", + OutTemp => RXDATA_OUT(38), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(39), + GlitchData => RXDATA39_GlitchData, + OutSignalName => "RXDATA(39)", + OutTemp => RXDATA_OUT(39), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(40), + GlitchData => RXDATA40_GlitchData, + OutSignalName => "RXDATA(40)", + OutTemp => RXDATA_OUT(40), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(41), + GlitchData => RXDATA41_GlitchData, + OutSignalName => "RXDATA(41)", + OutTemp => RXDATA_OUT(41), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(42), + GlitchData => RXDATA42_GlitchData, + OutSignalName => "RXDATA(42)", + OutTemp => RXDATA_OUT(42), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(43), + GlitchData => RXDATA43_GlitchData, + OutSignalName => "RXDATA(43)", + OutTemp => RXDATA_OUT(43), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(44), + GlitchData => RXDATA44_GlitchData, + OutSignalName => "RXDATA(44)", + OutTemp => RXDATA_OUT(44), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(45), + GlitchData => RXDATA45_GlitchData, + OutSignalName => "RXDATA(45)", + OutTemp => RXDATA_OUT(45), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(46), + GlitchData => RXDATA46_GlitchData, + OutSignalName => "RXDATA(46)", + OutTemp => RXDATA_OUT(46), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(47), + GlitchData => RXDATA47_GlitchData, + OutSignalName => "RXDATA(47)", + OutTemp => RXDATA_OUT(47), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(48), + GlitchData => RXDATA48_GlitchData, + OutSignalName => "RXDATA(48)", + OutTemp => RXDATA_OUT(48), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(49), + GlitchData => RXDATA49_GlitchData, + OutSignalName => "RXDATA(49)", + OutTemp => RXDATA_OUT(49), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(50), + GlitchData => RXDATA50_GlitchData, + OutSignalName => "RXDATA(50)", + OutTemp => RXDATA_OUT(50), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(51), + GlitchData => RXDATA51_GlitchData, + OutSignalName => "RXDATA(51)", + OutTemp => RXDATA_OUT(51), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(52), + GlitchData => RXDATA52_GlitchData, + OutSignalName => "RXDATA(52)", + OutTemp => RXDATA_OUT(52), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(53), + GlitchData => RXDATA53_GlitchData, + OutSignalName => "RXDATA(53)", + OutTemp => RXDATA_OUT(53), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(54), + GlitchData => RXDATA54_GlitchData, + OutSignalName => "RXDATA(54)", + OutTemp => RXDATA_OUT(54), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(55), + GlitchData => RXDATA55_GlitchData, + OutSignalName => "RXDATA(55)", + OutTemp => RXDATA_OUT(55), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(56), + GlitchData => RXDATA56_GlitchData, + OutSignalName => "RXDATA(56)", + OutTemp => RXDATA_OUT(56), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(57), + GlitchData => RXDATA57_GlitchData, + OutSignalName => "RXDATA(57)", + OutTemp => RXDATA_OUT(57), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(58), + GlitchData => RXDATA58_GlitchData, + OutSignalName => "RXDATA(58)", + OutTemp => RXDATA_OUT(58), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(59), + GlitchData => RXDATA59_GlitchData, + OutSignalName => "RXDATA(59)", + OutTemp => RXDATA_OUT(59), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(60), + GlitchData => RXDATA60_GlitchData, + OutSignalName => "RXDATA(60)", + OutTemp => RXDATA_OUT(60), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(61), + GlitchData => RXDATA61_GlitchData, + OutSignalName => "RXDATA(61)", + OutTemp => RXDATA_OUT(61), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(62), + GlitchData => RXDATA62_GlitchData, + OutSignalName => "RXDATA(62)", + OutTemp => RXDATA_OUT(62), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(63), + GlitchData => RXDATA63_GlitchData, + OutSignalName => "RXDATA(63)", + OutTemp => RXDATA_OUT(63), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(0), + GlitchData => RXDISPERR0_GlitchData, + OutSignalName => "RXDISPERR(0)", + OutTemp => RXDISPERR_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(1), + GlitchData => RXDISPERR1_GlitchData, + OutSignalName => "RXDISPERR(1)", + OutTemp => RXDISPERR_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(2), + GlitchData => RXDISPERR2_GlitchData, + OutSignalName => "RXDISPERR(2)", + OutTemp => RXDISPERR_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(3), + GlitchData => RXDISPERR3_GlitchData, + OutSignalName => "RXDISPERR(3)", + OutTemp => RXDISPERR_OUT(3), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(4), + GlitchData => RXDISPERR4_GlitchData, + OutSignalName => "RXDISPERR(4)", + OutTemp => RXDISPERR_OUT(4), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(5), + GlitchData => RXDISPERR5_GlitchData, + OutSignalName => "RXDISPERR(5)", + OutTemp => RXDISPERR_OUT(5), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(6), + GlitchData => RXDISPERR6_GlitchData, + OutSignalName => "RXDISPERR(6)", + OutTemp => RXDISPERR_OUT(6), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(7), + GlitchData => RXDISPERR7_GlitchData, + OutSignalName => "RXDISPERR(7)", + OutTemp => RXDISPERR_OUT(7), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC(0), + GlitchData => RXLOSSOFSYNC0_GlitchData, + OutSignalName => "RXLOSSOFSYNC(0)", + OutTemp => RXLOSSOFSYNC_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC(1), + GlitchData => RXLOSSOFSYNC1_GlitchData, + OutSignalName => "RXLOSSOFSYNC(1)", + OutTemp => RXLOSSOFSYNC_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(0), + GlitchData => RXNOTINTABLE0_GlitchData, + OutSignalName => "RXNOTINTABLE(0)", + OutTemp => RXNOTINTABLE_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(1), + GlitchData => RXNOTINTABLE1_GlitchData, + OutSignalName => "RXNOTINTABLE(1)", + OutTemp => RXNOTINTABLE_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(2), + GlitchData => RXNOTINTABLE2_GlitchData, + OutSignalName => "RXNOTINTABLE(2)", + OutTemp => RXNOTINTABLE_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(3), + GlitchData => RXNOTINTABLE3_GlitchData, + OutSignalName => "RXNOTINTABLE(3)", + OutTemp => RXNOTINTABLE_OUT(3), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(4), + GlitchData => RXNOTINTABLE4_GlitchData, + OutSignalName => "RXNOTINTABLE(4)", + OutTemp => RXNOTINTABLE_OUT(4), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(5), + GlitchData => RXNOTINTABLE5_GlitchData, + OutSignalName => "RXNOTINTABLE(5)", + OutTemp => RXNOTINTABLE_OUT(5), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(6), + GlitchData => RXNOTINTABLE6_GlitchData, + OutSignalName => "RXNOTINTABLE(6)", + OutTemp => RXNOTINTABLE_OUT(6), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(7), + GlitchData => RXNOTINTABLE7_GlitchData, + OutSignalName => "RXNOTINTABLE(7)", + OutTemp => RXNOTINTABLE_OUT(7), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXREALIGN, + GlitchData => RXREALIGN_GlitchData, + OutSignalName => "RXREALIGN", + OutTemp => RXREALIGN_OUT, + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(0), + GlitchData => RXRUNDISP0_GlitchData, + OutSignalName => "RXRUNDISP(0)", + OutTemp => RXRUNDISP_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(1), + GlitchData => RXRUNDISP1_GlitchData, + OutSignalName => "RXRUNDISP(1)", + OutTemp => RXRUNDISP_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(2), + GlitchData => RXRUNDISP2_GlitchData, + OutSignalName => "RXRUNDISP(2)", + OutTemp => RXRUNDISP_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(3), + GlitchData => RXRUNDISP3_GlitchData, + OutSignalName => "RXRUNDISP(3)", + OutTemp => RXRUNDISP_OUT(3), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(4), + GlitchData => RXRUNDISP4_GlitchData, + OutSignalName => "RXRUNDISP(4)", + OutTemp => RXRUNDISP_OUT(4), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(5), + GlitchData => RXRUNDISP5_GlitchData, + OutSignalName => "RXRUNDISP(5)", + OutTemp => RXRUNDISP_OUT(5), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(6), + GlitchData => RXRUNDISP6_GlitchData, + OutSignalName => "RXRUNDISP(6)", + OutTemp => RXRUNDISP_OUT(6), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(7), + GlitchData => RXRUNDISP7_GlitchData, + OutSignalName => "RXRUNDISP(7)", + OutTemp => RXRUNDISP_OUT(7), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXBUFERR, + GlitchData => TXBUFERR_GlitchData, + OutSignalName => "TXBUFERR", + OutTemp => TXBUFERR_OUT, + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(0), + GlitchData => TXKERR0_GlitchData, + OutSignalName => "TXKERR(0)", + OutTemp => TXKERR_OUT(0), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(1), + GlitchData => TXKERR1_GlitchData, + OutSignalName => "TXKERR(1)", + OutTemp => TXKERR_OUT(1), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(2), + GlitchData => TXKERR2_GlitchData, + OutSignalName => "TXKERR(2)", + OutTemp => TXKERR_OUT(2), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(3), + GlitchData => TXKERR3_GlitchData, + OutSignalName => "TXKERR(3)", + OutTemp => TXKERR_OUT(3), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(4), + GlitchData => TXKERR4_GlitchData, + OutSignalName => "TXKERR(4)", + OutTemp => TXKERR_OUT(4), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(5), + GlitchData => TXKERR5_GlitchData, + OutSignalName => "TXKERR(5)", + OutTemp => TXKERR_OUT(5), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(6), + GlitchData => TXKERR6_GlitchData, + OutSignalName => "TXKERR(6)", + OutTemp => TXKERR_OUT(6), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(7), + GlitchData => TXKERR7_GlitchData, + OutSignalName => "TXKERR(7)", + OutTemp => TXKERR_OUT(7), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(0), + GlitchData => TXRUNDISP0_GlitchData, + OutSignalName => "TXRUNDISP(0)", + OutTemp => TXRUNDISP_OUT(0), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(1), + GlitchData => TXRUNDISP1_GlitchData, + OutSignalName => "TXRUNDISP(1)", + OutTemp => TXRUNDISP_OUT(1), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(2), + GlitchData => TXRUNDISP2_GlitchData, + OutSignalName => "TXRUNDISP(2)", + OutTemp => TXRUNDISP_OUT(2), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(3), + GlitchData => TXRUNDISP3_GlitchData, + OutSignalName => "TXRUNDISP(3)", + OutTemp => TXRUNDISP_OUT(3), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(4), + GlitchData => TXRUNDISP4_GlitchData, + OutSignalName => "TXRUNDISP(4)", + OutTemp => TXRUNDISP_OUT(4), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(5), + GlitchData => TXRUNDISP5_GlitchData, + OutSignalName => "TXRUNDISP(5)", + OutTemp => TXRUNDISP_OUT(5), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(6), + GlitchData => TXRUNDISP6_GlitchData, + OutSignalName => "TXRUNDISP(6)", + OutTemp => TXRUNDISP_OUT(6), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(7), + GlitchData => TXRUNDISP7_GlitchData, + OutSignalName => "TXRUNDISP(7)", + OutTemp => TXRUNDISP_OUT(7), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + +-- Wait signal (input/output pins) + wait on + CHBONDDONE_OUT, + CHBONDO_OUT, +-- PMARXLOCK_OUT, + RXBUFSTATUS_OUT, + RXCHARISCOMMA_OUT, + RXCHARISK_OUT, + RXCLKCORCNT_OUT, + RXCOMMADET_OUT, + RXDATA_OUT, + RXDISPERR_OUT, + RXLOSSOFSYNC_OUT, + RXNOTINTABLE_OUT, + RXREALIGN_OUT, +-- RXRECCLK_OUT, + RXRUNDISP_OUT, + TXBUFERR_OUT, + TXKERR_OUT, +-- TXN_OUT, +-- TXOUTCLK_OUT, +-- TXP_OUT, + TXRUNDISP_OUT, + BREFCLKNIN_ipd, + BREFCLKPIN_ipd, + CHBONDI_ipd, + ENCHANSYNC_ipd, + ENMCOMMAALIGN_ipd, + ENPCOMMAALIGN_ipd, + LOOPBACK_ipd, + PMAINIT_ipd, + PMAREGADDR_ipd, + PMAREGDATAIN_ipd, + PMAREGRW_ipd, + PMAREGSTROBE_ipd, + PMARXLOCKSEL_ipd, + POWERDOWN_ipd, + REFCLK_ipd, + REFCLK2_ipd, + REFCLKBSEL_ipd, + REFCLKSEL_ipd, + RXBLOCKSYNC64B66BUSE_ipd, + RXCOMMADETUSE_ipd, + RXDATAWIDTH_ipd, + RXDEC64B66BUSE_ipd, + RXDEC8B10BUSE_ipd, + RXDESCRAM64B66BUSE_ipd, + RXIGNOREBTF_ipd, + RXINTDATAWIDTH_ipd, + RXN_ipd, + RXP_ipd, + RXPOLARITY_ipd, + RXRESET_ipd, + RXSLIDE_ipd, + RXUSRCLK_ipd, + RXUSRCLK2_ipd, + TXBYPASS8B10B_ipd, + TXCHARDISPMODE_ipd, + TXCHARDISPVAL_ipd, + TXCHARISK_ipd, + TXDATA_ipd, + TXDATAWIDTH_ipd, + TXENC64B66BUSE_ipd, + TXENC8B10BUSE_ipd, + TXGEARBOX64B66BUSE_ipd, + TXINHIBIT_ipd, + TXINTDATAWIDTH_ipd, + TXPOLARITY_ipd, + TXRESET_ipd, + TXSCRAM64B66BUSE_ipd, + TXUSRCLK_ipd, + TXUSRCLK2_ipd; + + end process TIMING; + + TXN <= TXN_OUT; + TXP <= TXP_OUT; + RXRECCLK <= RXRECCLK_OUT; + TXOUTCLK <= TXOUTCLK_OUT; + PMARXLOCK <= PMARXLOCK_OUT; +end GT10_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_xaui_1.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for XAUI I/O Standard 1 Byte Data +-- /___/ /\ Filename : GT10_XAUI_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:09 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_XAUI_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_XAUI_1 is +generic ( + ALIGN_COMMA_WORD : integer := 2; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 2; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 2; + CLK_CORRECT_USE : boolean := TRUE; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00fc0db00b0f32263068090104a628"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_XAUI_1; + +-- Architecture body -- + +architecture GT10_XAUI_1_V of GT10_XAUI_1 is + +signal OPEN7 : std_logic_vector(6 downto 0); +signal OPEN56 : std_logic_vector(55 downto 0); +signal z7 : std_logic_vector(6 downto 0) := "0000000"; +signal z56 : std_logic_vector(55 downto 0) := "00000000000000000000000000000000000000000000000000000000"; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00101111100", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, + CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, + CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_SEQ_1_1 => "00100011100", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, + CLK_CORRECT_USE => CLK_CORRECT_USE, + COMMA_10B_MASK => "0001111111", + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, + DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, + MCOMMA_10B_VALUE => "1010000011", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0101111100", + PCOMMA_DETECT => TRUE, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "25_10", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(7 downto 1) => OPEN7, + RXCHARISK(0 downto 0) => RXCHARISK, + RXCHARISK(7 downto 1) => OPEN7, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA(7 downto 0) => RXDATA, + RXDATA(63 downto 8) => OPEN56, + RXDISPERR(0 downto 0) => RXDISPERR, + RXDISPERR(7 downto 1) => OPEN7, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(7 downto 1) => OPEN7, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(0 downto 0) => RXRUNDISP, + RXRUNDISP(7 downto 1) => OPEN7, + TXBUFERR => TXBUFERR, + TXKERR(0 downto 0) => TXKERR, + TXKERR(7 downto 1) => OPEN7, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP(0 downto 0) => TXRUNDISP, + TXRUNDISP(7 downto 1) => OPEN7, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(7 downto 1) => z7, + TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(7 downto 1) => z7, + TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(7 downto 1) => z7, + TXCHARISK(0 downto 0) => TXCHARISK, + TXCHARISK(7 downto 1) => z7, + TXDATA(7 downto 0) => TXDATA, + TXDATA(63 downto 8) => z56, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_XAUI_1_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_xaui_2.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for XAUI I/O Standard 2 Byte Data +-- /___/ /\ Filename : GT10_XAUI_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:10 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_XAUI_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_XAUI_2 is +generic ( + ALIGN_COMMA_WORD : integer := 2; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 2; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 2; + CLK_CORRECT_USE : boolean := TRUE; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00fc0db00b0f32663068090105a628"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_XAUI_2; + +-- Architecture body -- + +architecture GT10_XAUI_2_V of GT10_XAUI_2 is + +signal OPEN6 : std_logic_vector(5 downto 0); +signal OPEN48 : std_logic_vector(47 downto 0); +signal z6 : std_logic_vector(5 downto 0) := "000000"; +signal z48 : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00101111100", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, + CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, + CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_SEQ_1_1 => "00100011100", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, + CLK_CORRECT_USE => CLK_CORRECT_USE, + COMMA_10B_MASK => "0001111111", + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, + DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, + MCOMMA_10B_VALUE => "1010000011", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0101111100", + PCOMMA_DETECT => TRUE, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "25_20", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(7 downto 2) => OPEN6, + RXCHARISK(1 downto 0) => RXCHARISK, + RXCHARISK(7 downto 2) => OPEN6, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA(15 downto 0) => RXDATA, + RXDATA(63 downto 16) => OPEN48, + RXDISPERR(1 downto 0) => RXDISPERR, + RXDISPERR(7 downto 2) => OPEN6, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(7 downto 2) => OPEN6, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(1 downto 0) => RXRUNDISP, + RXRUNDISP(7 downto 2) => OPEN6, + TXBUFERR => TXBUFERR, + TXKERR(1 downto 0) => TXKERR, + TXKERR(7 downto 2) => OPEN6, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP(1 downto 0) => TXRUNDISP, + TXRUNDISP(7 downto 2) => OPEN6, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(7 downto 2) => z6, + TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(7 downto 2) => z6, + TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(7 downto 2) => z6, + TXCHARISK(1 downto 0) => TXCHARISK, + TXCHARISK(7 downto 2) => z6, + TXDATA(15 downto 0) => TXDATA, + TXDATA(63 downto 16) => z48, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_XAUI_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_xaui_4.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 10-Gigabit Transceiver for XAUI I/O Standard 4 Byte Data +-- /___/ /\ Filename : GT10_XAUI_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:10 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT10_XAUI_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT10_XAUI_4 is +generic ( + ALIGN_COMMA_WORD : integer := 2; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 2; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 2; + CLK_CORRECT_USE : boolean := TRUE; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd500b0132663068090105a628"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT10_XAUI_4; + +-- Architecture body -- + +architecture GT10_XAUI_4_V of GT10_XAUI_4 is + +signal OPEN4 : std_logic_vector(3 downto 0); +signal OPEN32 : std_logic_vector(31 downto 0); +signal z4 : std_logic_vector(3 downto 0) := "0000"; +signal z32 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + +begin +-- GT10 Instatiation (port map, generic map) +GT10_inst : GT10 + generic map ( + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00101111100", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, + CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, + CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + CLK_COR_SEQ_1_1 => "00100011100", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, + CLK_CORRECT_USE => CLK_CORRECT_USE, + COMMA_10B_MASK => "0001111111", + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, + DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, + MCOMMA_10B_VALUE => "1010000011", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0101111100", + PCOMMA_DETECT => TRUE, + PMA_PWR_CNTRL => PMA_PWR_CNTRL, + PMA_SPEED => "25_40", + PMA_SPEED_HEX => PMA_SPEED_HEX, + PMA_SPEED_USE => PMA_SPEED_USE, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + TX_BUFFER_USE => TX_BUFFER_USE +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + PMARXLOCK => PMARXLOCK, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(3 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(7 downto 4) => OPEN4, + RXCHARISK(3 downto 0) => RXCHARISK, + RXCHARISK(7 downto 4) => OPEN4, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXDATA(31 downto 0) => RXDATA, + RXDATA(63 downto 32) => OPEN32, + RXDISPERR(3 downto 0) => RXDISPERR, + RXDISPERR(7 downto 4) => OPEN4, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(3 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(7 downto 4) => OPEN4, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(3 downto 0) => RXRUNDISP, + RXRUNDISP(7 downto 4) => OPEN4, + TXBUFERR => TXBUFERR, + TXKERR(3 downto 0) => TXKERR, + TXKERR(7 downto 4) => OPEN4, + TXN => TXN, + TXOUTCLK => TXOUTCLK, + TXP => TXP, + TXRUNDISP(3 downto 0) => TXRUNDISP, + TXRUNDISP(7 downto 4) => OPEN4, + BREFCLKNIN => BREFCLKNIN, + BREFCLKPIN => BREFCLKPIN, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + PMAINIT => PMAINIT, + PMAREGADDR => PMAREGADDR, + PMAREGDATAIN => PMAREGDATAIN, + PMAREGRW => PMAREGRW, + PMAREGSTROBE => PMAREGSTROBE, + PMARXLOCKSEL => PMARXLOCKSEL, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKBSEL => REFCLKBSEL, + REFCLKSEL => REFCLKSEL, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(3 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(7 downto 4) => z4, + TXCHARDISPMODE(3 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(7 downto 4) => z4, + TXCHARDISPVAL(3 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(7 downto 4) => z4, + TXCHARISK(3 downto 0) => TXCHARISK, + TXCHARISK(7 downto 4) => z4, + TXDATA(31 downto 0) => TXDATA, + TXDATA(63 downto 32) => z32, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT10_XAUI_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_aurora_1.vhd,v 1.4 2004/04/08 18:46:22 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Gigabit Transceiver for AURORA I/O Standard 1 Byte Data +-- /___/ /\ Filename : GT_AURORA_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:10 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT_AURORA_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT_AURORA_1 is +generic ( + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT_AURORA_1; + +-- Architecture body -- + +architecture GT_AURORA_1_V of GT_AURORA_1 is + +signal OPEN3 : std_logic_vector(2 downto 0); +signal OPEN24 : std_logic_vector(23 downto 0); +signal z3 : std_logic_vector(2 downto 0) := "000"; +signal z24 : std_logic_vector(23 downto 0) := "000000000000000000000000"; + +begin +-- GT Instatiation (port map, generic map) +GT_inst : GT + generic map ( + ALIGN_COMMA_MSB => FALSE, + CHAN_BOND_LIMIT => 16, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_OFFSET => 8, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00101111100", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_USE => FALSE, + CHAN_BOND_SEQ_LEN => 1, + CHAN_BOND_WAIT => 8, + CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, + CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, + CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, + CLK_COR_SEQ_1_1 => "00111110111", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_USE => FALSE, + CLK_COR_SEQ_LEN => 1, + CLK_CORRECT_USE => TRUE, + COMMA_10B_MASK => "1111111111", + CRC_END_OF_PKT => "K29_7", + CRC_FORMAT => "USER_MODE", + CRC_START_OF_PKT => "K27_7", + DEC_MCOMMA_DETECT => TRUE, + DEC_PCOMMA_DETECT => TRUE, + DEC_VALID_COMMA_ONLY => TRUE, + MCOMMA_10B_VALUE => "1100000101", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0011111010", + PCOMMA_DETECT => TRUE, + REF_CLK_V_SEL => REF_CLK_V_SEL, + RX_BUFFER_USE => TRUE, + RX_CRC_USE => RX_CRC_USE, + RX_DATA_WIDTH => 1, + RX_DECODE_USE => TRUE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SERDES_10B => SERDES_10B, + TERMINATION_IMP => TERMINATION_IMP, + TX_BUFFER_USE => TRUE, + TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, + TX_CRC_USE => TX_CRC_USE, + TX_DATA_WIDTH => 1, + TX_DIFF_CTRL => TX_DIFF_CTRL, + TX_PREEMPHASIS => TX_PREEMPHASIS +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + CONFIGOUT => CONFIGOUT, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(3 downto 1) => OPEN3, + RXCHARISK(0 downto 0) => RXCHARISK, + RXCHARISK(3 downto 1) => OPEN3, + RXCHECKINGCRC => RXCHECKINGCRC, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXCRCERR => RXCRCERR, + RXDATA(7 downto 0) => RXDATA, + RXDATA(31 downto 8) => OPEN24, + RXDISPERR(0 downto 0) => RXDISPERR, + RXDISPERR(3 downto 1) => OPEN3, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(3 downto 1) => OPEN3, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(0 downto 0) => RXRUNDISP, + RXRUNDISP(3 downto 1) => OPEN3, + TXBUFERR => TXBUFERR, + TXKERR(0 downto 0) => TXKERR, + TXKERR(3 downto 1) => OPEN3, + TXN => TXN, + TXP => TXP, + TXRUNDISP(0 downto 0) => TXRUNDISP, + TXRUNDISP(3 downto 1) => OPEN3, + BREFCLK => BREFCLK, + BREFCLK2 => BREFCLK2, + CHBONDI => CHBONDI, + CONFIGENABLE => CONFIGENABLE, + CONFIGIN => CONFIGIN, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKSEL => REFCLKSEL, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(3 downto 1) => z3, + TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(3 downto 1) => z3, + TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(3 downto 1) => z3, + TXCHARISK(0 downto 0) => TXCHARISK, + TXCHARISK(3 downto 1) => z3, + TXDATA(7 downto 0) => TXDATA, + TXDATA(31 downto 8) => z24, + TXFORCECRCERR => TXFORCECRCERR, + TXINHIBIT => TXINHIBIT, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT_AURORA_1_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_aurora_2.vhd,v 1.4 2004/04/08 18:46:22 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Gigabit Transceiver for AURORA I/O Standard 2 Byte Data +-- /___/ /\ Filename : GT_AURORA_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:10 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT_AURORA_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT_AURORA_2 is +generic ( + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT_AURORA_2; + +-- Architecture body -- + +architecture GT_AURORA_2_V of GT_AURORA_2 is + +signal OPEN2 : std_logic_vector(1 downto 0); +signal OPEN16 : std_logic_vector(15 downto 0); +signal z2 : std_logic_vector(1 downto 0) := "00"; +signal z16 : std_logic_vector(15 downto 0) := "0000000000000000"; + +begin +-- GT Instatiation (port map, generic map) +GT_inst : GT + generic map ( + ALIGN_COMMA_MSB => FALSE, + CHAN_BOND_LIMIT => 16, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_OFFSET => 8, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00101111100", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_USE => FALSE, + CHAN_BOND_SEQ_LEN => 1, + CHAN_BOND_WAIT => 8, + CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, + CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, + CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, + CLK_COR_SEQ_1_1 => "00111110111", + CLK_COR_SEQ_1_2 => "00111110111", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_USE => FALSE, + CLK_COR_SEQ_LEN => 2, + CLK_CORRECT_USE => TRUE, + COMMA_10B_MASK => "1111111111", + CRC_END_OF_PKT => "K29_7", + CRC_FORMAT => "USER_MODE", + CRC_START_OF_PKT => "K27_7", + DEC_MCOMMA_DETECT => TRUE, + DEC_PCOMMA_DETECT => TRUE, + DEC_VALID_COMMA_ONLY => TRUE, + MCOMMA_10B_VALUE => "1100000101", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0011111010", + PCOMMA_DETECT => TRUE, + REF_CLK_V_SEL => REF_CLK_V_SEL, + RX_BUFFER_USE => TRUE, + RX_CRC_USE => RX_CRC_USE, + RX_DATA_WIDTH => 2, + RX_DECODE_USE => TRUE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SERDES_10B => SERDES_10B, + TERMINATION_IMP => TERMINATION_IMP, + TX_BUFFER_USE => TRUE, + TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, + TX_CRC_USE => TX_CRC_USE, + TX_DATA_WIDTH => 2, + TX_DIFF_CTRL => TX_DIFF_CTRL, + TX_PREEMPHASIS => TX_PREEMPHASIS +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + CONFIGOUT => CONFIGOUT, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(3 downto 2) => OPEN2, + RXCHARISK(1 downto 0) => RXCHARISK, + RXCHARISK(3 downto 2) => OPEN2, + RXCHECKINGCRC => RXCHECKINGCRC, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXCRCERR => RXCRCERR, + RXDATA(15 downto 0) => RXDATA, + RXDATA(31 downto 16) => OPEN16, + RXDISPERR(1 downto 0) => RXDISPERR, + RXDISPERR(3 downto 2) => OPEN2, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(3 downto 2) => OPEN2, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(1 downto 0) => RXRUNDISP, + RXRUNDISP(3 downto 2) => OPEN2, + TXBUFERR => TXBUFERR, + TXKERR(1 downto 0) => TXKERR, + TXKERR(3 downto 2) => OPEN2, + TXN => TXN, + TXP => TXP, + TXRUNDISP(1 downto 0) => TXRUNDISP, + TXRUNDISP(3 downto 2) => OPEN2, + BREFCLK => BREFCLK, + BREFCLK2 => BREFCLK2, + CHBONDI => CHBONDI, + CONFIGENABLE => CONFIGENABLE, + CONFIGIN => CONFIGIN, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKSEL => REFCLKSEL, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(3 downto 2) => z2, + TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(3 downto 2) => z2, + TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(3 downto 2) => z2, + TXCHARISK(1 downto 0) => TXCHARISK, + TXCHARISK(3 downto 2) => z2, + TXDATA(15 downto 0) => TXDATA, + TXDATA(31 downto 16) => z16, + TXFORCECRCERR => TXFORCECRCERR, + TXINHIBIT => TXINHIBIT, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT_AURORA_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_aurora_4.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Gigabit Transceiver for AURORA I/O Standard 4 Byte Data +-- /___/ /\ Filename : GT_AURORA_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:10 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT_AURORA_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT_AURORA_4 is +generic ( + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT_AURORA_4; + +-- Architecture body -- + +architecture GT_AURORA_4_V of GT_AURORA_4 is + + +begin +-- GT Instatiation (port map, generic map) +GT_inst : GT + generic map ( + ALIGN_COMMA_MSB => FALSE, + CHAN_BOND_LIMIT => 16, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_OFFSET => 8, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00101111100", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_USE => FALSE, + CHAN_BOND_SEQ_LEN => 1, + CHAN_BOND_WAIT => 8, + CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, + CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, + CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, + CLK_COR_SEQ_1_1 => "00111110111", + CLK_COR_SEQ_1_2 => "00111110111", + CLK_COR_SEQ_1_3 => "00111110111", + CLK_COR_SEQ_1_4 => "00111110111", + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_USE => FALSE, + CLK_COR_SEQ_LEN => 4, + CLK_CORRECT_USE => TRUE, + COMMA_10B_MASK => "1111111111", + CRC_END_OF_PKT => "K29_7", + CRC_FORMAT => "USER_MODE", + CRC_START_OF_PKT => "K27_7", + DEC_MCOMMA_DETECT => TRUE, + DEC_PCOMMA_DETECT => TRUE, + DEC_VALID_COMMA_ONLY => TRUE, + MCOMMA_10B_VALUE => "1100000101", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0011111010", + PCOMMA_DETECT => TRUE, + REF_CLK_V_SEL => REF_CLK_V_SEL, + RX_BUFFER_USE => TRUE, + RX_CRC_USE => RX_CRC_USE, + RX_DATA_WIDTH => 4, + RX_DECODE_USE => TRUE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SERDES_10B => SERDES_10B, + TERMINATION_IMP => TERMINATION_IMP, + TX_BUFFER_USE => TRUE, + TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, + TX_CRC_USE => TX_CRC_USE, + TX_DATA_WIDTH => 4, + TX_DIFF_CTRL => TX_DIFF_CTRL, + TX_PREEMPHASIS => TX_PREEMPHASIS +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + CONFIGOUT => CONFIGOUT, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA => RXCHARISCOMMA, + RXCHARISK => RXCHARISK, + RXCHECKINGCRC => RXCHECKINGCRC, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXCRCERR => RXCRCERR, + RXDATA => RXDATA, + RXDISPERR => RXDISPERR, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE => RXNOTINTABLE, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP => RXRUNDISP, + TXBUFERR => TXBUFERR, + TXKERR => TXKERR, + TXN => TXN, + TXP => TXP, + TXRUNDISP => TXRUNDISP, + BREFCLK => BREFCLK, + BREFCLK2 => BREFCLK2, + CHBONDI => CHBONDI, + CONFIGENABLE => CONFIGENABLE, + CONFIGIN => CONFIGIN, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKSEL => REFCLKSEL, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B => TXBYPASS8B10B, + TXCHARDISPMODE => TXCHARDISPMODE, + TXCHARDISPVAL => TXCHARDISPVAL, + TXCHARISK => TXCHARISK, + TXDATA => TXDATA, + TXFORCECRCERR => TXFORCECRCERR, + TXINHIBIT => TXINHIBIT, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT_AURORA_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_custom.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Gigabit Transceiver for CUSTOM I/O Standard +-- /___/ /\ Filename : GT_CUSTOM.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:10 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT_CUSTOM ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT_CUSTOM is +generic ( + ALIGN_COMMA_MSB : boolean := FALSE; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_OFFSET : integer := 8; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 1; + CHAN_BOND_WAIT : integer := 8; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + CLK_COR_SEQ_1_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 1; + CLK_CORRECT_USE : boolean := TRUE; + COMMA_10B_MASK : bit_vector := "1111111000"; + CRC_END_OF_PKT : string := "K29_7"; + CRC_FORMAT : string := "USER_MODE"; + CRC_START_OF_PKT : string := "K27_7"; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + MCOMMA_10B_VALUE : bit_vector := "1100000000"; + MCOMMA_DETECT : boolean := TRUE; + PCOMMA_10B_VALUE : bit_vector := "0011111000"; + PCOMMA_DETECT : boolean := TRUE; + REF_CLK_V_SEL : integer := 0; + RX_BUFFER_USE : boolean := TRUE; + RX_CRC_USE : boolean := FALSE; + RX_DATA_WIDTH : integer := 2; + RX_DECODE_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_BUFFER_USE : boolean := TRUE; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DATA_WIDTH : integer := 2; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT_CUSTOM; + +-- Architecture body -- + +architecture GT_CUSTOM_V of GT_CUSTOM is + + +begin +-- GT Instatiation (port map, generic map) +GT_inst : GT + generic map ( + ALIGN_COMMA_MSB => ALIGN_COMMA_MSB, + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_OFFSET => CHAN_BOND_OFFSET, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => CHAN_BOND_SEQ_1_1, + CHAN_BOND_SEQ_1_2 => CHAN_BOND_SEQ_1_2, + CHAN_BOND_SEQ_1_3 => CHAN_BOND_SEQ_1_3, + CHAN_BOND_SEQ_1_4 => CHAN_BOND_SEQ_1_4, + CHAN_BOND_SEQ_2_1 => CHAN_BOND_SEQ_2_1, + CHAN_BOND_SEQ_2_2 => CHAN_BOND_SEQ_2_2, + CHAN_BOND_SEQ_2_3 => CHAN_BOND_SEQ_2_3, + CHAN_BOND_SEQ_2_4 => CHAN_BOND_SEQ_2_4, + CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, + CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, + CHAN_BOND_WAIT => CHAN_BOND_WAIT, + CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, + CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, + CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, + CLK_COR_SEQ_1_1 => CLK_COR_SEQ_1_1, + CLK_COR_SEQ_1_2 => CLK_COR_SEQ_1_2, + CLK_COR_SEQ_1_3 => CLK_COR_SEQ_1_3, + CLK_COR_SEQ_1_4 => CLK_COR_SEQ_1_4, + CLK_COR_SEQ_2_1 => CLK_COR_SEQ_2_1, + CLK_COR_SEQ_2_2 => CLK_COR_SEQ_2_2, + CLK_COR_SEQ_2_3 => CLK_COR_SEQ_2_3, + CLK_COR_SEQ_2_4 => CLK_COR_SEQ_2_4, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, + CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, + CLK_CORRECT_USE => CLK_CORRECT_USE, + COMMA_10B_MASK => COMMA_10B_MASK, + CRC_END_OF_PKT => CRC_END_OF_PKT, + CRC_FORMAT => CRC_FORMAT, + CRC_START_OF_PKT => CRC_START_OF_PKT, + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, + DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, + MCOMMA_10B_VALUE => MCOMMA_10B_VALUE, + MCOMMA_DETECT => MCOMMA_DETECT, + PCOMMA_10B_VALUE => PCOMMA_10B_VALUE, + PCOMMA_DETECT => PCOMMA_DETECT, + REF_CLK_V_SEL => REF_CLK_V_SEL, + RX_BUFFER_USE => RX_BUFFER_USE, + RX_CRC_USE => RX_CRC_USE, + RX_DATA_WIDTH => RX_DATA_WIDTH, + RX_DECODE_USE => RX_DECODE_USE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SERDES_10B => SERDES_10B, + TERMINATION_IMP => TERMINATION_IMP, + TX_BUFFER_USE => TX_BUFFER_USE, + TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, + TX_CRC_USE => TX_CRC_USE, + TX_DATA_WIDTH => TX_DATA_WIDTH, + TX_DIFF_CTRL => TX_DIFF_CTRL, + TX_PREEMPHASIS => TX_PREEMPHASIS +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + CONFIGOUT => CONFIGOUT, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA => RXCHARISCOMMA, + RXCHARISK => RXCHARISK, + RXCHECKINGCRC => RXCHECKINGCRC, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXCRCERR => RXCRCERR, + RXDATA => RXDATA, + RXDISPERR => RXDISPERR, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE => RXNOTINTABLE, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP => RXRUNDISP, + TXBUFERR => TXBUFERR, + TXKERR => TXKERR, + TXN => TXN, + TXP => TXP, + TXRUNDISP => TXRUNDISP, + BREFCLK => BREFCLK, + BREFCLK2 => BREFCLK2, + CHBONDI => CHBONDI, + CONFIGENABLE => CONFIGENABLE, + CONFIGIN => CONFIGIN, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKSEL => REFCLKSEL, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B => TXBYPASS8B10B, + TXCHARDISPMODE => TXCHARDISPMODE, + TXCHARDISPVAL => TXCHARDISPVAL, + TXCHARISK => TXCHARISK, + TXDATA => TXDATA, + TXFORCECRCERR => TXFORCECRCERR, + TXINHIBIT => TXINHIBIT, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT_CUSTOM_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_ethernet_1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Gigabit Transceiver for ETHERNET I/O Standard 1 Byte Data +-- /___/ /\ Filename : GT_ETHERNET_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:10 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT_ETHERNET_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT_ETHERNET_1 is +generic ( + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + + + ); + +port ( + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT_ETHERNET_1; + +-- Architecture body -- + +architecture GT_ETHERNET_1_V of GT_ETHERNET_1 is + +signal OPEN1 : std_ulogic; +signal OPEN4 : std_logic_vector(3 downto 0); +signal z4 : std_logic_vector(3 downto 0) := "0000"; +signal z1 : std_ulogic := '0'; +signal OPEN3 : std_logic_vector(2 downto 0); +signal OPEN24 : std_logic_vector(23 downto 0); +signal z3 : std_logic_vector(2 downto 0) := "000"; +signal z24 : std_logic_vector(23 downto 0) := "000000000000000000000000"; + +begin +-- GT Instatiation (port map, generic map) +GT_inst : GT + generic map ( + ALIGN_COMMA_MSB => FALSE, + CHAN_BOND_LIMIT => 1, + CHAN_BOND_MODE => "OFF", + CHAN_BOND_OFFSET => 0, + CHAN_BOND_ONE_SHOT => TRUE, + CHAN_BOND_SEQ_1_1 => "00000000000", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_USE => FALSE, + CHAN_BOND_SEQ_LEN => 1, + CHAN_BOND_WAIT => 7, + CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, + CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, + CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, + CLK_COR_SEQ_1_1 => "00110111100", + CLK_COR_SEQ_1_2 => "00001010000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_USE => FALSE, + CLK_COR_SEQ_LEN => 2, + CLK_CORRECT_USE => TRUE, + COMMA_10B_MASK => "1111111000", + CRC_END_OF_PKT => "K29_7", + CRC_FORMAT => "ETHERNET", + CRC_START_OF_PKT => "K27_7", + DEC_MCOMMA_DETECT => TRUE, + DEC_PCOMMA_DETECT => TRUE, + DEC_VALID_COMMA_ONLY => TRUE, + MCOMMA_10B_VALUE => "1100000000", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0011111000", + PCOMMA_DETECT => TRUE, + REF_CLK_V_SEL => REF_CLK_V_SEL, + RX_BUFFER_USE => TRUE, + RX_CRC_USE => RX_CRC_USE, + RX_DATA_WIDTH => 1, + RX_DECODE_USE => TRUE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SERDES_10B => SERDES_10B, + TERMINATION_IMP => TERMINATION_IMP, + TX_BUFFER_USE => TRUE, + TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, + TX_CRC_USE => TX_CRC_USE, + TX_DATA_WIDTH => 1, + TX_DIFF_CTRL => TX_DIFF_CTRL, + TX_PREEMPHASIS => TX_PREEMPHASIS +) +port map ( + CHBONDDONE => OPEN1, + CHBONDO => OPEN4, + CHBONDI => z4, + ENCHANSYNC => z1, + CONFIGOUT => CONFIGOUT, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(3 downto 1) => OPEN3, + RXCHARISK(0 downto 0) => RXCHARISK, + RXCHARISK(3 downto 1) => OPEN3, + RXCHECKINGCRC => RXCHECKINGCRC, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXCRCERR => RXCRCERR, + RXDATA(7 downto 0) => RXDATA, + RXDATA(31 downto 8) => OPEN24, + RXDISPERR(0 downto 0) => RXDISPERR, + RXDISPERR(3 downto 1) => OPEN3, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(3 downto 1) => OPEN3, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(0 downto 0) => RXRUNDISP, + RXRUNDISP(3 downto 1) => OPEN3, + TXBUFERR => TXBUFERR, + TXKERR(0 downto 0) => TXKERR, + TXKERR(3 downto 1) => OPEN3, + TXN => TXN, + TXP => TXP, + TXRUNDISP(0 downto 0) => TXRUNDISP, + TXRUNDISP(3 downto 1) => OPEN3, + BREFCLK => BREFCLK, + BREFCLK2 => BREFCLK2, + CONFIGENABLE => CONFIGENABLE, + CONFIGIN => CONFIGIN, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKSEL => REFCLKSEL, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(3 downto 1) => z3, + TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(3 downto 1) => z3, + TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(3 downto 1) => z3, + TXCHARISK(0 downto 0) => TXCHARISK, + TXCHARISK(3 downto 1) => z3, + TXDATA(7 downto 0) => TXDATA, + TXDATA(31 downto 8) => z24, + TXFORCECRCERR => TXFORCECRCERR, + TXINHIBIT => TXINHIBIT, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT_ETHERNET_1_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_ethernet_2.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Gigabit Transceiver for ETHERNET I/O Standard 2 Byte Data +-- /___/ /\ Filename : GT_ETHERNET_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:10 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT_ETHERNET_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT_ETHERNET_2 is +generic ( + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + + + ); + +port ( + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT_ETHERNET_2; + +-- Architecture body -- + +architecture GT_ETHERNET_2_V of GT_ETHERNET_2 is + +signal OPEN1 : std_ulogic; +signal OPEN4 : std_logic_vector(3 downto 0); +signal z4 : std_logic_vector(3 downto 0) := "0000"; +signal z1 : std_ulogic := '0'; +signal OPEN2 : std_logic_vector(1 downto 0); +signal OPEN16 : std_logic_vector(15 downto 0); +signal z2 : std_logic_vector(1 downto 0) := "00"; +signal z16 : std_logic_vector(15 downto 0) := "0000000000000000"; + +begin +-- GT Instatiation (port map, generic map) +GT_inst : GT + generic map ( + ALIGN_COMMA_MSB => FALSE, + CHAN_BOND_LIMIT => 1, + CHAN_BOND_MODE => "OFF", + CHAN_BOND_OFFSET => 0, + CHAN_BOND_ONE_SHOT => TRUE, + CHAN_BOND_SEQ_1_1 => "00000000000", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_USE => FALSE, + CHAN_BOND_SEQ_LEN => 1, + CHAN_BOND_WAIT => 7, + CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, + CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, + CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, + CLK_COR_SEQ_1_1 => "00110111100", + CLK_COR_SEQ_1_2 => "00001010000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_USE => FALSE, + CLK_COR_SEQ_LEN => 2, + CLK_CORRECT_USE => TRUE, + COMMA_10B_MASK => "1111111000", + CRC_END_OF_PKT => "K29_7", + CRC_FORMAT => "ETHERNET", + CRC_START_OF_PKT => "K27_7", + DEC_MCOMMA_DETECT => TRUE, + DEC_PCOMMA_DETECT => TRUE, + DEC_VALID_COMMA_ONLY => TRUE, + MCOMMA_10B_VALUE => "1100000000", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0011111000", + PCOMMA_DETECT => TRUE, + REF_CLK_V_SEL => REF_CLK_V_SEL, + RX_BUFFER_USE => TRUE, + RX_CRC_USE => RX_CRC_USE, + RX_DATA_WIDTH => 2, + RX_DECODE_USE => TRUE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SERDES_10B => SERDES_10B, + TERMINATION_IMP => TERMINATION_IMP, + TX_BUFFER_USE => TRUE, + TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, + TX_CRC_USE => TX_CRC_USE, + TX_DATA_WIDTH => 2, + TX_DIFF_CTRL => TX_DIFF_CTRL, + TX_PREEMPHASIS => TX_PREEMPHASIS +) +port map ( + CHBONDDONE => OPEN1, + CHBONDO => OPEN4, + CHBONDI => z4, + ENCHANSYNC => z1, + CONFIGOUT => CONFIGOUT, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(3 downto 2) => OPEN2, + RXCHARISK(1 downto 0) => RXCHARISK, + RXCHARISK(3 downto 2) => OPEN2, + RXCHECKINGCRC => RXCHECKINGCRC, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXCRCERR => RXCRCERR, + RXDATA(15 downto 0) => RXDATA, + RXDATA(31 downto 16) => OPEN16, + RXDISPERR(1 downto 0) => RXDISPERR, + RXDISPERR(3 downto 2) => OPEN2, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(3 downto 2) => OPEN2, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(1 downto 0) => RXRUNDISP, + RXRUNDISP(3 downto 2) => OPEN2, + TXBUFERR => TXBUFERR, + TXKERR(1 downto 0) => TXKERR, + TXKERR(3 downto 2) => OPEN2, + TXN => TXN, + TXP => TXP, + TXRUNDISP(1 downto 0) => TXRUNDISP, + TXRUNDISP(3 downto 2) => OPEN2, + BREFCLK => BREFCLK, + BREFCLK2 => BREFCLK2, + CONFIGENABLE => CONFIGENABLE, + CONFIGIN => CONFIGIN, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKSEL => REFCLKSEL, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(3 downto 2) => z2, + TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(3 downto 2) => z2, + TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(3 downto 2) => z2, + TXCHARISK(1 downto 0) => TXCHARISK, + TXCHARISK(3 downto 2) => z2, + TXDATA(15 downto 0) => TXDATA, + TXDATA(31 downto 16) => z16, + TXFORCECRCERR => TXFORCECRCERR, + TXINHIBIT => TXINHIBIT, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT_ETHERNET_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_ethernet_4.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Gigabit Transceiver for ETHERNET I/O Standard 4 Byte Data +-- /___/ /\ Filename : GT_ETHERNET_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:10 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT_ETHERNET_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT_ETHERNET_4 is +generic ( + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + + + ); + +port ( + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT_ETHERNET_4; + +-- Architecture body -- + +architecture GT_ETHERNET_4_V of GT_ETHERNET_4 is + +signal OPEN1 : std_ulogic; +signal OPEN4 : std_logic_vector(3 downto 0); +signal z4 : std_logic_vector(3 downto 0) := "0000"; +signal z1 : std_ulogic := '0'; + +begin +-- GT Instatiation (port map, generic map) +GT_inst : GT + generic map ( + ALIGN_COMMA_MSB => FALSE, + CHAN_BOND_LIMIT => 1, + CHAN_BOND_MODE => "OFF", + CHAN_BOND_OFFSET => 0, + CHAN_BOND_ONE_SHOT => TRUE, + CHAN_BOND_SEQ_1_1 => "00000000000", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_USE => FALSE, + CHAN_BOND_SEQ_LEN => 1, + CHAN_BOND_WAIT => 7, + CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, + CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, + CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, + CLK_COR_SEQ_1_1 => "00110111100", + CLK_COR_SEQ_1_2 => "00001010000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_USE => FALSE, + CLK_COR_SEQ_LEN => 2, + CLK_CORRECT_USE => TRUE, + COMMA_10B_MASK => "1111111000", + CRC_END_OF_PKT => "K29_7", + CRC_FORMAT => "ETHERNET", + CRC_START_OF_PKT => "K27_7", + DEC_MCOMMA_DETECT => TRUE, + DEC_PCOMMA_DETECT => TRUE, + DEC_VALID_COMMA_ONLY => TRUE, + MCOMMA_10B_VALUE => "1100000000", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0011111000", + PCOMMA_DETECT => TRUE, + REF_CLK_V_SEL => REF_CLK_V_SEL, + RX_BUFFER_USE => TRUE, + RX_CRC_USE => RX_CRC_USE, + RX_DATA_WIDTH => 4, + RX_DECODE_USE => TRUE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SERDES_10B => SERDES_10B, + TERMINATION_IMP => TERMINATION_IMP, + TX_BUFFER_USE => TRUE, + TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, + TX_CRC_USE => TX_CRC_USE, + TX_DATA_WIDTH => 4, + TX_DIFF_CTRL => TX_DIFF_CTRL, + TX_PREEMPHASIS => TX_PREEMPHASIS +) +port map ( + CHBONDDONE => OPEN1, + CHBONDO => OPEN4, + CHBONDI => z4, + ENCHANSYNC => z1, + CONFIGOUT => CONFIGOUT, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA => RXCHARISCOMMA, + RXCHARISK => RXCHARISK, + RXCHECKINGCRC => RXCHECKINGCRC, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXCRCERR => RXCRCERR, + RXDATA => RXDATA, + RXDISPERR => RXDISPERR, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE => RXNOTINTABLE, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP => RXRUNDISP, + TXBUFERR => TXBUFERR, + TXKERR => TXKERR, + TXN => TXN, + TXP => TXP, + TXRUNDISP => TXRUNDISP, + BREFCLK => BREFCLK, + BREFCLK2 => BREFCLK2, + CONFIGENABLE => CONFIGENABLE, + CONFIGIN => CONFIGIN, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKSEL => REFCLKSEL, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B => TXBYPASS8B10B, + TXCHARDISPMODE => TXCHARDISPMODE, + TXCHARDISPVAL => TXCHARDISPVAL, + TXCHARISK => TXCHARISK, + TXDATA => TXDATA, + TXFORCECRCERR => TXFORCECRCERR, + TXINHIBIT => TXINHIBIT, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT_ETHERNET_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_fibre_chan_1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Gigabit Transceiver for FIBRE_CHAN I/O Standard 1 Byte Data +-- /___/ /\ Filename : GT_FIBRE_CHAN_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:11 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT_FIBRE_CHAN_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT_FIBRE_CHAN_1 is +generic ( + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 2; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + + + ); + +port ( + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT_FIBRE_CHAN_1; + +-- Architecture body -- + +architecture GT_FIBRE_CHAN_1_V of GT_FIBRE_CHAN_1 is + +signal OPEN1 : std_ulogic; +signal OPEN4 : std_logic_vector(3 downto 0); +signal z4 : std_logic_vector(3 downto 0) := "0000"; +signal z1 : std_ulogic := '0'; +signal OPEN3 : std_logic_vector(2 downto 0); +signal OPEN24 : std_logic_vector(23 downto 0); +signal z3 : std_logic_vector(2 downto 0) := "000"; +signal z24 : std_logic_vector(23 downto 0) := "000000000000000000000000"; + +begin +-- GT Instatiation (port map, generic map) +GT_inst : GT + generic map ( + ALIGN_COMMA_MSB => FALSE, + CHAN_BOND_LIMIT => 1, + CHAN_BOND_MODE => "OFF", + CHAN_BOND_OFFSET => 0, + CHAN_BOND_ONE_SHOT => TRUE, + CHAN_BOND_SEQ_1_1 => "00000000000", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_USE => FALSE, + CHAN_BOND_SEQ_LEN => 1, + CHAN_BOND_WAIT => 7, + CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, + CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, + CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, + CLK_COR_SEQ_1_1 => "00110111100", + CLK_COR_SEQ_1_2 => "00010010101", + CLK_COR_SEQ_1_3 => "00010110101", + CLK_COR_SEQ_1_4 => "00010110101", + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_USE => FALSE, + CLK_COR_SEQ_LEN => 4, + CLK_CORRECT_USE => TRUE, + COMMA_10B_MASK => "1111111000", + CRC_END_OF_PKT => "K29_7", + CRC_FORMAT => "FIBRE_CHAN", + CRC_START_OF_PKT => "K27_7", + DEC_MCOMMA_DETECT => TRUE, + DEC_PCOMMA_DETECT => TRUE, + DEC_VALID_COMMA_ONLY => TRUE, + MCOMMA_10B_VALUE => "1100000000", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0011111000", + PCOMMA_DETECT => TRUE, + REF_CLK_V_SEL => REF_CLK_V_SEL, + RX_BUFFER_USE => TRUE, + RX_CRC_USE => RX_CRC_USE, + RX_DATA_WIDTH => 1, + RX_DECODE_USE => TRUE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SERDES_10B => SERDES_10B, + TERMINATION_IMP => TERMINATION_IMP, + TX_BUFFER_USE => TRUE, + TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, + TX_CRC_USE => TX_CRC_USE, + TX_DATA_WIDTH => 1, + TX_DIFF_CTRL => TX_DIFF_CTRL, + TX_PREEMPHASIS => TX_PREEMPHASIS +) +port map ( + CHBONDDONE => OPEN1, + CHBONDO => OPEN4, + CHBONDI => z4, + ENCHANSYNC => z1, + CONFIGOUT => CONFIGOUT, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(3 downto 1) => OPEN3, + RXCHARISK(0 downto 0) => RXCHARISK, + RXCHARISK(3 downto 1) => OPEN3, + RXCHECKINGCRC => RXCHECKINGCRC, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXCRCERR => RXCRCERR, + RXDATA(7 downto 0) => RXDATA, + RXDATA(31 downto 8) => OPEN24, + RXDISPERR(0 downto 0) => RXDISPERR, + RXDISPERR(3 downto 1) => OPEN3, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(3 downto 1) => OPEN3, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(0 downto 0) => RXRUNDISP, + RXRUNDISP(3 downto 1) => OPEN3, + TXBUFERR => TXBUFERR, + TXKERR(0 downto 0) => TXKERR, + TXKERR(3 downto 1) => OPEN3, + TXN => TXN, + TXP => TXP, + TXRUNDISP(0 downto 0) => TXRUNDISP, + TXRUNDISP(3 downto 1) => OPEN3, + BREFCLK => BREFCLK, + BREFCLK2 => BREFCLK2, + CONFIGENABLE => CONFIGENABLE, + CONFIGIN => CONFIGIN, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKSEL => REFCLKSEL, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(3 downto 1) => z3, + TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(3 downto 1) => z3, + TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(3 downto 1) => z3, + TXCHARISK(0 downto 0) => TXCHARISK, + TXCHARISK(3 downto 1) => z3, + TXDATA(7 downto 0) => TXDATA, + TXDATA(31 downto 8) => z24, + TXFORCECRCERR => TXFORCECRCERR, + TXINHIBIT => TXINHIBIT, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT_FIBRE_CHAN_1_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_fibre_chan_2.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Gigabit Transceiver for FIBRE_CHAN I/O Standard 2 Byte Data +-- /___/ /\ Filename : GT_FIBRE_CHAN_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:11 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT_FIBRE_CHAN_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT_FIBRE_CHAN_2 is +generic ( + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 2; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + + + ); + +port ( + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT_FIBRE_CHAN_2; + +-- Architecture body -- + +architecture GT_FIBRE_CHAN_2_V of GT_FIBRE_CHAN_2 is + +signal OPEN1 : std_ulogic; +signal OPEN4 : std_logic_vector(3 downto 0); +signal z4 : std_logic_vector(3 downto 0) := "0000"; +signal z1 : std_ulogic := '0'; +signal OPEN2 : std_logic_vector(1 downto 0); +signal OPEN16 : std_logic_vector(15 downto 0); +signal z2 : std_logic_vector(1 downto 0) := "00"; +signal z16 : std_logic_vector(15 downto 0) := "0000000000000000"; + +begin +-- GT Instatiation (port map, generic map) +GT_inst : GT + generic map ( + ALIGN_COMMA_MSB => FALSE, + CHAN_BOND_LIMIT => 1, + CHAN_BOND_MODE => "OFF", + CHAN_BOND_OFFSET => 0, + CHAN_BOND_ONE_SHOT => TRUE, + CHAN_BOND_SEQ_1_1 => "00000000000", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_USE => FALSE, + CHAN_BOND_SEQ_LEN => 1, + CHAN_BOND_WAIT => 7, + CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, + CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, + CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, + CLK_COR_SEQ_1_1 => "00110111100", + CLK_COR_SEQ_1_2 => "00010010101", + CLK_COR_SEQ_1_3 => "00010110101", + CLK_COR_SEQ_1_4 => "00010110101", + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_USE => FALSE, + CLK_COR_SEQ_LEN => 4, + CLK_CORRECT_USE => TRUE, + COMMA_10B_MASK => "1111111000", + CRC_END_OF_PKT => "K29_7", + CRC_FORMAT => "FIBRE_CHAN", + CRC_START_OF_PKT => "K27_7", + DEC_MCOMMA_DETECT => TRUE, + DEC_PCOMMA_DETECT => TRUE, + DEC_VALID_COMMA_ONLY => TRUE, + MCOMMA_10B_VALUE => "1100000000", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0011111000", + PCOMMA_DETECT => TRUE, + REF_CLK_V_SEL => REF_CLK_V_SEL, + RX_BUFFER_USE => TRUE, + RX_CRC_USE => RX_CRC_USE, + RX_DATA_WIDTH => 2, + RX_DECODE_USE => TRUE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SERDES_10B => SERDES_10B, + TERMINATION_IMP => TERMINATION_IMP, + TX_BUFFER_USE => TRUE, + TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, + TX_CRC_USE => TX_CRC_USE, + TX_DATA_WIDTH => 2, + TX_DIFF_CTRL => TX_DIFF_CTRL, + TX_PREEMPHASIS => TX_PREEMPHASIS +) +port map ( + CHBONDDONE => OPEN1, + CHBONDO => OPEN4, + CHBONDI => z4, + ENCHANSYNC => z1, + CONFIGOUT => CONFIGOUT, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(3 downto 2) => OPEN2, + RXCHARISK(1 downto 0) => RXCHARISK, + RXCHARISK(3 downto 2) => OPEN2, + RXCHECKINGCRC => RXCHECKINGCRC, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXCRCERR => RXCRCERR, + RXDATA(15 downto 0) => RXDATA, + RXDATA(31 downto 16) => OPEN16, + RXDISPERR(1 downto 0) => RXDISPERR, + RXDISPERR(3 downto 2) => OPEN2, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(3 downto 2) => OPEN2, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(1 downto 0) => RXRUNDISP, + RXRUNDISP(3 downto 2) => OPEN2, + TXBUFERR => TXBUFERR, + TXKERR(1 downto 0) => TXKERR, + TXKERR(3 downto 2) => OPEN2, + TXN => TXN, + TXP => TXP, + TXRUNDISP(1 downto 0) => TXRUNDISP, + TXRUNDISP(3 downto 2) => OPEN2, + BREFCLK => BREFCLK, + BREFCLK2 => BREFCLK2, + CONFIGENABLE => CONFIGENABLE, + CONFIGIN => CONFIGIN, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKSEL => REFCLKSEL, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(3 downto 2) => z2, + TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(3 downto 2) => z2, + TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(3 downto 2) => z2, + TXCHARISK(1 downto 0) => TXCHARISK, + TXCHARISK(3 downto 2) => z2, + TXDATA(15 downto 0) => TXDATA, + TXDATA(31 downto 16) => z16, + TXFORCECRCERR => TXFORCECRCERR, + TXINHIBIT => TXINHIBIT, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT_FIBRE_CHAN_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_fibre_chan_4.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Gigabit Transceiver for FIBRE_CHAN I/O Standard 4 Byte Data +-- /___/ /\ Filename : GT_FIBRE_CHAN_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:11 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT_FIBRE_CHAN_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT_FIBRE_CHAN_4 is +generic ( + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 2; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + + + ); + +port ( + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT_FIBRE_CHAN_4; + +-- Architecture body -- + +architecture GT_FIBRE_CHAN_4_V of GT_FIBRE_CHAN_4 is + +signal OPEN1 : std_ulogic; +signal OPEN4 : std_logic_vector(3 downto 0); +signal z4 : std_logic_vector(3 downto 0) := "0000"; +signal z1 : std_ulogic := '0'; + +begin +-- GT Instatiation (port map, generic map) +GT_inst : GT + generic map ( + ALIGN_COMMA_MSB => FALSE, + CHAN_BOND_LIMIT => 1, + CHAN_BOND_MODE => "OFF", + CHAN_BOND_OFFSET => 0, + CHAN_BOND_ONE_SHOT => TRUE, + CHAN_BOND_SEQ_1_1 => "00000000000", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_USE => FALSE, + CHAN_BOND_SEQ_LEN => 1, + CHAN_BOND_WAIT => 7, + CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, + CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, + CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, + CLK_COR_SEQ_1_1 => "00110111100", + CLK_COR_SEQ_1_2 => "00010010101", + CLK_COR_SEQ_1_3 => "00010110101", + CLK_COR_SEQ_1_4 => "00010110101", + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_USE => FALSE, + CLK_COR_SEQ_LEN => 4, + CLK_CORRECT_USE => TRUE, + COMMA_10B_MASK => "1111111000", + CRC_END_OF_PKT => "K29_7", + CRC_FORMAT => "FIBRE_CHAN", + CRC_START_OF_PKT => "K27_7", + DEC_MCOMMA_DETECT => TRUE, + DEC_PCOMMA_DETECT => TRUE, + DEC_VALID_COMMA_ONLY => TRUE, + MCOMMA_10B_VALUE => "1100000000", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0011111000", + PCOMMA_DETECT => TRUE, + REF_CLK_V_SEL => REF_CLK_V_SEL, + RX_BUFFER_USE => TRUE, + RX_CRC_USE => RX_CRC_USE, + RX_DATA_WIDTH => 4, + RX_DECODE_USE => TRUE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SERDES_10B => SERDES_10B, + TERMINATION_IMP => TERMINATION_IMP, + TX_BUFFER_USE => TRUE, + TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, + TX_CRC_USE => TX_CRC_USE, + TX_DATA_WIDTH => 4, + TX_DIFF_CTRL => TX_DIFF_CTRL, + TX_PREEMPHASIS => TX_PREEMPHASIS +) +port map ( + CHBONDDONE => OPEN1, + CHBONDO => OPEN4, + CHBONDI => z4, + ENCHANSYNC => z1, + CONFIGOUT => CONFIGOUT, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA => RXCHARISCOMMA, + RXCHARISK => RXCHARISK, + RXCHECKINGCRC => RXCHECKINGCRC, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXCRCERR => RXCRCERR, + RXDATA => RXDATA, + RXDISPERR => RXDISPERR, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE => RXNOTINTABLE, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP => RXRUNDISP, + TXBUFERR => TXBUFERR, + TXKERR => TXKERR, + TXN => TXN, + TXP => TXP, + TXRUNDISP => TXRUNDISP, + BREFCLK => BREFCLK, + BREFCLK2 => BREFCLK2, + CONFIGENABLE => CONFIGENABLE, + CONFIGIN => CONFIGIN, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKSEL => REFCLKSEL, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B => TXBYPASS8B10B, + TXCHARDISPMODE => TXCHARDISPMODE, + TXCHARDISPVAL => TXCHARDISPVAL, + TXCHARISK => TXCHARISK, + TXDATA => TXDATA, + TXFORCECRCERR => TXFORCECRCERR, + TXINHIBIT => TXINHIBIT, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT_FIBRE_CHAN_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_infiniband_1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Gigabit Transceiver for INFINIBAND I/O Standard 1 Byte Data +-- /___/ /\ Filename : GT_INFINIBAND_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:11 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT_INFINIBAND_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT_INFINIBAND_1 is +generic ( + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + LANE_ID : bit_vector := "00000000000"; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT_INFINIBAND_1; + +-- Architecture body -- + +architecture GT_INFINIBAND_1_V of GT_INFINIBAND_1 is + +signal OPEN3 : std_logic_vector(2 downto 0); +signal OPEN24 : std_logic_vector(23 downto 0); +signal z3 : std_logic_vector(2 downto 0) := "000"; +signal z24 : std_logic_vector(23 downto 0) := "000000000000000000000000"; + +begin +-- GT Instatiation (port map, generic map) +GT_inst : GT + generic map ( + ALIGN_COMMA_MSB => FALSE, + CHAN_BOND_LIMIT => 16, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_OFFSET => 8, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00110111100", + CHAN_BOND_SEQ_1_2 => LANE_ID, + CHAN_BOND_SEQ_1_3 => "00001001010", + CHAN_BOND_SEQ_1_4 => "00001001010", + CHAN_BOND_SEQ_2_1 => "00110111100", + CHAN_BOND_SEQ_2_2 => LANE_ID, + CHAN_BOND_SEQ_2_3 => "00001000101", + CHAN_BOND_SEQ_2_4 => "00001000101", + CHAN_BOND_SEQ_2_USE => TRUE, + CHAN_BOND_SEQ_LEN => 4, + CHAN_BOND_WAIT => 8, + CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, + CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, + CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, + CLK_COR_SEQ_1_1 => "00100011100", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_USE => FALSE, + CLK_COR_SEQ_LEN => 1, + CLK_CORRECT_USE => TRUE, + COMMA_10B_MASK => "1111111000", + CRC_END_OF_PKT => "K29_7", + CRC_FORMAT => "INFINIBAND", + CRC_START_OF_PKT => "K27_7", + DEC_MCOMMA_DETECT => TRUE, + DEC_PCOMMA_DETECT => TRUE, + DEC_VALID_COMMA_ONLY => TRUE, + MCOMMA_10B_VALUE => "1100000000", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0011111000", + PCOMMA_DETECT => TRUE, + REF_CLK_V_SEL => REF_CLK_V_SEL, + RX_BUFFER_USE => TRUE, + RX_CRC_USE => RX_CRC_USE, + RX_DATA_WIDTH => 1, + RX_DECODE_USE => TRUE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SERDES_10B => SERDES_10B, + TERMINATION_IMP => TERMINATION_IMP, + TX_BUFFER_USE => TRUE, + TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, + TX_CRC_USE => TX_CRC_USE, + TX_DATA_WIDTH => 1, + TX_DIFF_CTRL => TX_DIFF_CTRL, + TX_PREEMPHASIS => TX_PREEMPHASIS +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + CONFIGOUT => CONFIGOUT, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(3 downto 1) => OPEN3, + RXCHARISK(0 downto 0) => RXCHARISK, + RXCHARISK(3 downto 1) => OPEN3, + RXCHECKINGCRC => RXCHECKINGCRC, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXCRCERR => RXCRCERR, + RXDATA(7 downto 0) => RXDATA, + RXDATA(31 downto 8) => OPEN24, + RXDISPERR(0 downto 0) => RXDISPERR, + RXDISPERR(3 downto 1) => OPEN3, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(3 downto 1) => OPEN3, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(0 downto 0) => RXRUNDISP, + RXRUNDISP(3 downto 1) => OPEN3, + TXBUFERR => TXBUFERR, + TXKERR(0 downto 0) => TXKERR, + TXKERR(3 downto 1) => OPEN3, + TXN => TXN, + TXP => TXP, + TXRUNDISP(0 downto 0) => TXRUNDISP, + TXRUNDISP(3 downto 1) => OPEN3, + BREFCLK => BREFCLK, + BREFCLK2 => BREFCLK2, + CHBONDI => CHBONDI, + CONFIGENABLE => CONFIGENABLE, + CONFIGIN => CONFIGIN, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKSEL => REFCLKSEL, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(3 downto 1) => z3, + TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(3 downto 1) => z3, + TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(3 downto 1) => z3, + TXCHARISK(0 downto 0) => TXCHARISK, + TXCHARISK(3 downto 1) => z3, + TXDATA(7 downto 0) => TXDATA, + TXDATA(31 downto 8) => z24, + TXFORCECRCERR => TXFORCECRCERR, + TXINHIBIT => TXINHIBIT, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT_INFINIBAND_1_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_infiniband_2.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Gigabit Transceiver for INFINIBAND I/O Standard 2 Byte Data +-- /___/ /\ Filename : GT_INFINIBAND_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:11 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT_INFINIBAND_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT_INFINIBAND_2 is +generic ( + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + LANE_ID : bit_vector := "00000000000"; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT_INFINIBAND_2; + +-- Architecture body -- + +architecture GT_INFINIBAND_2_V of GT_INFINIBAND_2 is + +signal OPEN2 : std_logic_vector(1 downto 0); +signal OPEN16 : std_logic_vector(15 downto 0); +signal z2 : std_logic_vector(1 downto 0) := "00"; +signal z16 : std_logic_vector(15 downto 0) := "0000000000000000"; + +begin +-- GT Instatiation (port map, generic map) +GT_inst : GT + generic map ( + ALIGN_COMMA_MSB => FALSE, + CHAN_BOND_LIMIT => 16, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_OFFSET => 8, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00110111100", + CHAN_BOND_SEQ_1_2 => LANE_ID, + CHAN_BOND_SEQ_1_3 => "00001001010", + CHAN_BOND_SEQ_1_4 => "00001001010", + CHAN_BOND_SEQ_2_1 => "00110111100", + CHAN_BOND_SEQ_2_2 => LANE_ID, + CHAN_BOND_SEQ_2_3 => "00001000101", + CHAN_BOND_SEQ_2_4 => "00001000101", + CHAN_BOND_SEQ_2_USE => TRUE, + CHAN_BOND_SEQ_LEN => 4, + CHAN_BOND_WAIT => 8, + CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, + CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, + CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, + CLK_COR_SEQ_1_1 => "00100011100", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_USE => FALSE, + CLK_COR_SEQ_LEN => 1, + CLK_CORRECT_USE => TRUE, + COMMA_10B_MASK => "1111111000", + CRC_END_OF_PKT => "K29_7", + CRC_FORMAT => "INFINIBAND", + CRC_START_OF_PKT => "K27_7", + DEC_MCOMMA_DETECT => TRUE, + DEC_PCOMMA_DETECT => TRUE, + DEC_VALID_COMMA_ONLY => TRUE, + MCOMMA_10B_VALUE => "1100000000", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0011111000", + PCOMMA_DETECT => TRUE, + REF_CLK_V_SEL => REF_CLK_V_SEL, + RX_BUFFER_USE => TRUE, + RX_CRC_USE => RX_CRC_USE, + RX_DATA_WIDTH => 2, + RX_DECODE_USE => TRUE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SERDES_10B => SERDES_10B, + TERMINATION_IMP => TERMINATION_IMP, + TX_BUFFER_USE => TRUE, + TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, + TX_CRC_USE => TX_CRC_USE, + TX_DATA_WIDTH => 2, + TX_DIFF_CTRL => TX_DIFF_CTRL, + TX_PREEMPHASIS => TX_PREEMPHASIS +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + CONFIGOUT => CONFIGOUT, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(3 downto 2) => OPEN2, + RXCHARISK(1 downto 0) => RXCHARISK, + RXCHARISK(3 downto 2) => OPEN2, + RXCHECKINGCRC => RXCHECKINGCRC, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXCRCERR => RXCRCERR, + RXDATA(15 downto 0) => RXDATA, + RXDATA(31 downto 16) => OPEN16, + RXDISPERR(1 downto 0) => RXDISPERR, + RXDISPERR(3 downto 2) => OPEN2, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(3 downto 2) => OPEN2, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(1 downto 0) => RXRUNDISP, + RXRUNDISP(3 downto 2) => OPEN2, + TXBUFERR => TXBUFERR, + TXKERR(1 downto 0) => TXKERR, + TXKERR(3 downto 2) => OPEN2, + TXN => TXN, + TXP => TXP, + TXRUNDISP(1 downto 0) => TXRUNDISP, + TXRUNDISP(3 downto 2) => OPEN2, + BREFCLK => BREFCLK, + BREFCLK2 => BREFCLK2, + CHBONDI => CHBONDI, + CONFIGENABLE => CONFIGENABLE, + CONFIGIN => CONFIGIN, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKSEL => REFCLKSEL, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(3 downto 2) => z2, + TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(3 downto 2) => z2, + TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(3 downto 2) => z2, + TXCHARISK(1 downto 0) => TXCHARISK, + TXCHARISK(3 downto 2) => z2, + TXDATA(15 downto 0) => TXDATA, + TXDATA(31 downto 16) => z16, + TXFORCECRCERR => TXFORCECRCERR, + TXINHIBIT => TXINHIBIT, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT_INFINIBAND_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_infiniband_4.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Gigabit Transceiver for INFINIBAND I/O Standard 4 Byte Data +-- /___/ /\ Filename : GT_INFINIBAND_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:11 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT_INFINIBAND_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT_INFINIBAND_4 is +generic ( + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + LANE_ID : bit_vector := "00000000000"; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT_INFINIBAND_4; + +-- Architecture body -- + +architecture GT_INFINIBAND_4_V of GT_INFINIBAND_4 is + + +begin +-- GT Instatiation (port map, generic map) +GT_inst : GT + generic map ( + ALIGN_COMMA_MSB => FALSE, + CHAN_BOND_LIMIT => 16, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_OFFSET => 8, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00110111100", + CHAN_BOND_SEQ_1_2 => LANE_ID, + CHAN_BOND_SEQ_1_3 => "00001001010", + CHAN_BOND_SEQ_1_4 => "00001001010", + CHAN_BOND_SEQ_2_1 => "00110111100", + CHAN_BOND_SEQ_2_2 => LANE_ID, + CHAN_BOND_SEQ_2_3 => "00001000101", + CHAN_BOND_SEQ_2_4 => "00001000101", + CHAN_BOND_SEQ_2_USE => TRUE, + CHAN_BOND_SEQ_LEN => 4, + CHAN_BOND_WAIT => 8, + CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, + CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, + CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, + CLK_COR_SEQ_1_1 => "00100011100", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_USE => FALSE, + CLK_COR_SEQ_LEN => 1, + CLK_CORRECT_USE => TRUE, + COMMA_10B_MASK => "1111111000", + CRC_END_OF_PKT => "K29_7", + CRC_FORMAT => "INFINIBAND", + CRC_START_OF_PKT => "K27_7", + DEC_MCOMMA_DETECT => TRUE, + DEC_PCOMMA_DETECT => TRUE, + DEC_VALID_COMMA_ONLY => TRUE, + MCOMMA_10B_VALUE => "1100000000", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0011111000", + PCOMMA_DETECT => TRUE, + REF_CLK_V_SEL => REF_CLK_V_SEL, + RX_BUFFER_USE => TRUE, + RX_CRC_USE => RX_CRC_USE, + RX_DATA_WIDTH => 4, + RX_DECODE_USE => TRUE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SERDES_10B => SERDES_10B, + TERMINATION_IMP => TERMINATION_IMP, + TX_BUFFER_USE => TRUE, + TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, + TX_CRC_USE => TX_CRC_USE, + TX_DATA_WIDTH => 4, + TX_DIFF_CTRL => TX_DIFF_CTRL, + TX_PREEMPHASIS => TX_PREEMPHASIS +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + CONFIGOUT => CONFIGOUT, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA => RXCHARISCOMMA, + RXCHARISK => RXCHARISK, + RXCHECKINGCRC => RXCHECKINGCRC, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXCRCERR => RXCRCERR, + RXDATA => RXDATA, + RXDISPERR => RXDISPERR, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE => RXNOTINTABLE, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP => RXRUNDISP, + TXBUFERR => TXBUFERR, + TXKERR => TXKERR, + TXN => TXN, + TXP => TXP, + TXRUNDISP => TXRUNDISP, + BREFCLK => BREFCLK, + BREFCLK2 => BREFCLK2, + CHBONDI => CHBONDI, + CONFIGENABLE => CONFIGENABLE, + CONFIGIN => CONFIGIN, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKSEL => REFCLKSEL, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B => TXBYPASS8B10B, + TXCHARDISPMODE => TXCHARDISPMODE, + TXCHARDISPVAL => TXCHARDISPVAL, + TXCHARISK => TXCHARISK, + TXDATA => TXDATA, + TXFORCECRCERR => TXFORCECRCERR, + TXINHIBIT => TXINHIBIT, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT_INFINIBAND_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt.vhd,v 1.5 2006/03/16 00:57:41 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Gigabit Transceiver for High-Speed I/O Simulation Model +-- /___/ /\ Filename : GT.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:07 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT is +generic ( + in_delay : time := 0 ps; + out_delay : VitalDelayType01 := (100 ps, 100 ps); + + ALIGN_COMMA_MSB : boolean := FALSE; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_OFFSET : integer := 8; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 1; + CHAN_BOND_WAIT : integer := 8; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + CLK_COR_SEQ_1_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 1; + CLK_CORRECT_USE : boolean := TRUE; + COMMA_10B_MASK : bit_vector := "1111111000"; + CRC_END_OF_PKT : string := "K29_7"; + CRC_FORMAT : string := "USER_MODE"; + CRC_START_OF_PKT : string := "K27_7"; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + MCOMMA_10B_VALUE : bit_vector := "1100000000"; + MCOMMA_DETECT : boolean := TRUE; + PCOMMA_10B_VALUE : bit_vector := "0011111000"; + PCOMMA_DETECT : boolean := TRUE; + REF_CLK_V_SEL : integer := 0; + RX_BUFFER_USE : boolean := TRUE; + RX_CRC_USE : boolean := FALSE; + RX_DATA_WIDTH : integer := 2; + RX_DECODE_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_BUFFER_USE : boolean := TRUE; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DATA_WIDTH : integer := 2; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT; + +-- Architecture body -- + +architecture GT_V of GT is + + component GT_SWIFT_BUS + port ( + TX_CRC_FORCE_VALUE : in std_logic_vector(7 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXP : in std_ulogic; + RXN : in std_ulogic; + GSR : in std_ulogic; + TXP : out std_ulogic; + TXN : out std_ulogic; + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + CONFIGOUT : out std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + CRC_END_OF_PKT : in std_logic_vector(7 downto 0); + CRC_FORMAT : in std_logic_vector(1 downto 0); + CRC_START_OF_PKT : in std_logic_vector(7 downto 0); + CHAN_BOND_LIMIT : in std_logic_vector(4 downto 0); + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXUSRCLK : in std_ulogic; + TXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXUSRCLK2 : in std_ulogic; + RXRESET : in std_ulogic; + TXRESET : in std_ulogic; + POWERDOWN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + RX_LOSS_OF_SYNC_FSM : in std_ulogic; + RX_LOS_INVALID_INCR : in std_logic_vector(2 downto 0); + RX_LOS_THRESHOLD : in std_logic_vector(2 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXPOLARITY : in std_ulogic; + TXINHIBIT : in std_ulogic; + ENCHANSYNC : in std_ulogic; + RXPOLARITY : in std_ulogic; + CHBONDI : in std_logic_vector(3 downto 0); + RXRECCLK : out std_ulogic; + TXBUFERR : out std_ulogic; + TXFORCECRCERR : in std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + TXKERR : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXCOMMADET : out std_ulogic; + RXCHECKINGCRC : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXRUNDISP : out std_logic_vector(3 downto 0); + RXBUFSTATUS : out std_logic_vector(1 downto 0); + CHBONDO : out std_logic_vector(3 downto 0); + CHBONDDONE : out std_ulogic; + TX_PREEMPHASIS : in std_logic_vector(1 downto 0); + TX_DIFF_CTRL : in std_logic_vector(2 downto 0); + TERMINATION_IMP : in std_ulogic; + SERDES_10B : in std_ulogic; + ALIGN_COMMA_MSB : in std_ulogic; + PCOMMA_DETECT : in std_ulogic; + MCOMMA_DETECT : in std_ulogic; + PCOMMA_10B_VALUE : in std_logic_vector(0 to 9); + MCOMMA_10B_VALUE : in std_logic_vector(0 to 9); + COMMA_10B_MASK : in std_logic_vector(0 to 9); + DEC_PCOMMA_DETECT : in std_ulogic; + DEC_MCOMMA_DETECT : in std_ulogic; + DEC_VALID_COMMA_ONLY : in std_ulogic; + RX_DECODE_USE : in std_ulogic; + RX_BUFFER_USE : in std_ulogic; + TX_BUFFER_USE : in std_ulogic; + CLK_CORRECT_USE : in std_ulogic; + CLK_COR_SEQ_LEN : in std_logic_vector(1 downto 0); + CLK_COR_INSERT_IDLE_FLAG : in std_ulogic; + CLK_COR_KEEP_IDLE : in std_ulogic; + CLK_COR_REPEAT_WAIT : in std_logic_vector(4 downto 0); + CLK_COR_SEQ_1_1 : in std_logic_vector(10 downto 0); + CLK_COR_SEQ_1_2 : in std_logic_vector(10 downto 0); + CLK_COR_SEQ_1_3 : in std_logic_vector(10 downto 0); + CLK_COR_SEQ_1_4 : in std_logic_vector(10 downto 0); + CLK_COR_SEQ_2_USE : in std_ulogic; + CLK_COR_SEQ_2_1 : in std_logic_vector(10 downto 0); + CLK_COR_SEQ_2_2 : in std_logic_vector(10 downto 0); + CLK_COR_SEQ_2_3 : in std_logic_vector(10 downto 0); + CLK_COR_SEQ_2_4 : in std_logic_vector(10 downto 0); + CHAN_BOND_MODE : in std_logic_vector(1 downto 0); + CHAN_BOND_SEQ_LEN : in std_logic_vector(1 downto 0); + CHAN_BOND_SEQ_1_1 : in std_logic_vector(10 downto 0); + CHAN_BOND_SEQ_1_2 : in std_logic_vector(10 downto 0); + CHAN_BOND_SEQ_1_3 : in std_logic_vector(10 downto 0); + CHAN_BOND_SEQ_1_4 : in std_logic_vector(10 downto 0); + CHAN_BOND_SEQ_2_USE : in std_ulogic; + CHAN_BOND_SEQ_2_1 : in std_logic_vector(10 downto 0); + CHAN_BOND_SEQ_2_2 : in std_logic_vector(10 downto 0); + CHAN_BOND_SEQ_2_3 : in std_logic_vector(10 downto 0); + CHAN_BOND_SEQ_2_4 : in std_logic_vector(10 downto 0); + CHAN_BOND_WAIT : in std_logic_vector(3 downto 0); + CHAN_BOND_OFFSET : in std_logic_vector(3 downto 0); + TX_CRC_USE : in std_ulogic; + RX_CRC_USE : in std_ulogic; + CHAN_BOND_ONE_SHOT : in std_ulogic; + RX_DATA_WIDTH : in std_logic_vector(1 downto 0); + TX_DATA_WIDTH : in std_logic_vector(1 downto 0); + BREFCLK : in std_ulogic; + BREFCLK2 : in std_ulogic; + REF_CLK_V_SEL : in std_ulogic + ); + end component; +-- Attribute-to-Cell mapping signals + signal ALIGN_COMMA_MSB_BINARY : std_ulogic; + signal CHAN_BOND_LIMIT_BINARY : std_logic_vector(4 downto 0); + signal CHAN_BOND_MODE_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_OFFSET_BINARY : std_logic_vector(3 downto 0); + signal CHAN_BOND_ONE_SHOT_BINARY : std_ulogic; + signal CHAN_BOND_SEQ_1_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1); + signal CHAN_BOND_SEQ_1_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2); + signal CHAN_BOND_SEQ_1_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3); + signal CHAN_BOND_SEQ_1_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4); + signal CHAN_BOND_SEQ_2_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1); + signal CHAN_BOND_SEQ_2_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2); + signal CHAN_BOND_SEQ_2_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3); + signal CHAN_BOND_SEQ_2_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4); + signal CHAN_BOND_SEQ_2_USE_BINARY : std_ulogic; + signal CHAN_BOND_SEQ_LEN_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_WAIT_BINARY : std_logic_vector(3 downto 0); + signal CLK_COR_INSERT_IDLE_FLAG_BINARY : std_ulogic; + signal CLK_COR_KEEP_IDLE_BINARY : std_ulogic; + signal CLK_COR_REPEAT_WAIT_BINARY : std_logic_vector(4 downto 0); + signal CLK_COR_SEQ_1_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1); + signal CLK_COR_SEQ_1_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2); + signal CLK_COR_SEQ_1_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3); + signal CLK_COR_SEQ_1_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4); + signal CLK_COR_SEQ_2_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1); + signal CLK_COR_SEQ_2_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2); + signal CLK_COR_SEQ_2_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3); + signal CLK_COR_SEQ_2_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4); + signal CLK_COR_SEQ_2_USE_BINARY : std_ulogic; + signal CLK_COR_SEQ_LEN_BINARY : std_logic_vector(1 downto 0); + signal CLK_CORRECT_USE_BINARY : std_ulogic; + signal COMMA_10B_MASK_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(COMMA_10B_MASK); + signal CRC_END_OF_PKT_BINARY : std_logic_vector(7 downto 0); + signal CRC_FORMAT_BINARY : std_logic_vector(1 downto 0); + signal CRC_START_OF_PKT_BINARY : std_logic_vector(7 downto 0); + signal DEC_MCOMMA_DETECT_BINARY : std_ulogic; + signal DEC_PCOMMA_DETECT_BINARY : std_ulogic; + signal DEC_VALID_COMMA_ONLY_BINARY : std_ulogic; + signal MCOMMA_10B_VALUE_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(MCOMMA_10B_VALUE); + signal MCOMMA_DETECT_BINARY : std_ulogic; + signal PCOMMA_10B_VALUE_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(PCOMMA_10B_VALUE); + signal PCOMMA_DETECT_BINARY : std_ulogic; + signal REF_CLK_V_SEL_BINARY : std_ulogic; + signal RX_BUFFER_USE_BINARY : std_ulogic; + signal RX_CRC_USE_BINARY : std_ulogic; + signal RX_DATA_WIDTH_BINARY : std_logic_vector(1 downto 0); + signal RX_DECODE_USE_BINARY : std_ulogic; + signal RX_LOS_INVALID_INCR_BINARY : std_logic_vector(2 downto 0); + signal RX_LOS_THRESHOLD_BINARY : std_logic_vector(2 downto 0); + signal RX_LOSS_OF_SYNC_FSM_BINARY : std_ulogic; + signal SERDES_10B_BINARY : std_ulogic; + signal TERMINATION_IMP_BINARY : std_ulogic; + signal TX_BUFFER_USE_BINARY : std_ulogic; + signal TX_CRC_FORCE_VALUE_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(TX_CRC_FORCE_VALUE); + signal TX_CRC_USE_BINARY : std_ulogic; + signal TX_DATA_WIDTH_BINARY : std_logic_vector(1 downto 0); + signal TX_DIFF_CTRL_BINARY : std_logic_vector(2 downto 0); + signal TX_PREEMPHASIS_BINARY : std_logic_vector(1 downto 0); + +-- Input/Output Pin signals + signal CHBONDDONE_out : std_ulogic; + signal CHBONDO_out : std_logic_vector(3 downto 0); + signal CONFIGOUT_out : std_ulogic; + signal RXBUFSTATUS_out : std_logic_vector(1 downto 0); + signal RXCHARISCOMMA_out : std_logic_vector(3 downto 0); + signal RXCHARISK_out : std_logic_vector(3 downto 0); + signal RXCHECKINGCRC_out : std_ulogic; + signal RXCLKCORCNT_out : std_logic_vector(2 downto 0); + signal RXCOMMADET_out : std_ulogic; + signal RXCRCERR_out : std_ulogic; + signal RXDATA_out : std_logic_vector(31 downto 0); + signal RXDISPERR_out : std_logic_vector(3 downto 0); + signal RXLOSSOFSYNC_out : std_logic_vector(1 downto 0); + signal RXNOTINTABLE_out : std_logic_vector(3 downto 0); + signal RXREALIGN_out : std_ulogic; + signal RXRECCLK_out : std_ulogic; + signal RXRUNDISP_out : std_logic_vector(3 downto 0); + signal TXBUFERR_out : std_ulogic; + signal TXKERR_out : std_logic_vector(3 downto 0); + signal TXN_out : std_ulogic; + signal TXP_out : std_ulogic; + signal TXRUNDISP_out : std_logic_vector(3 downto 0); + + signal BREFCLK_ipd : std_ulogic; + signal BREFCLK2_ipd : std_ulogic; + signal CHBONDI_ipd : std_logic_vector(3 downto 0); + signal CONFIGENABLE_ipd : std_ulogic; + signal CONFIGIN_ipd : std_ulogic; + signal ENCHANSYNC_ipd : std_ulogic; + signal ENMCOMMAALIGN_ipd : std_ulogic; + signal ENPCOMMAALIGN_ipd : std_ulogic; + signal LOOPBACK_ipd : std_logic_vector(1 downto 0); + signal POWERDOWN_ipd : std_ulogic; + signal REFCLK_ipd : std_ulogic; + signal REFCLK2_ipd : std_ulogic; + signal REFCLKSEL_ipd : std_ulogic; + signal RXN_ipd : std_ulogic; + signal RXP_ipd : std_ulogic; + signal RXPOLARITY_ipd : std_ulogic; + signal RXRESET_ipd : std_ulogic; + signal RXUSRCLK_ipd : std_ulogic; + signal RXUSRCLK2_ipd : std_ulogic; + signal TXBYPASS8B10B_ipd : std_logic_vector(3 downto 0); + signal TXCHARDISPMODE_ipd : std_logic_vector(3 downto 0); + signal TXCHARDISPVAL_ipd : std_logic_vector(3 downto 0); + signal TXCHARISK_ipd : std_logic_vector(3 downto 0); + signal TXDATA_ipd : std_logic_vector(31 downto 0); + signal TXFORCECRCERR_ipd : std_ulogic; + signal TXINHIBIT_ipd : std_ulogic; + signal TXPOLARITY_ipd : std_ulogic; + signal TXRESET_ipd : std_ulogic; + signal TXUSRCLK_ipd : std_ulogic; + signal TXUSRCLK2_ipd : std_ulogic; + + +begin + +BREFCLK_ipd <= BREFCLK after in_delay; +BREFCLK2_ipd <= BREFCLK2 after in_delay; +CHBONDI_ipd <= CHBONDI after in_delay; +CONFIGENABLE_ipd <= CONFIGENABLE after in_delay; +CONFIGIN_ipd <= CONFIGIN after in_delay; +ENCHANSYNC_ipd <= ENCHANSYNC after in_delay; +ENMCOMMAALIGN_ipd <= ENMCOMMAALIGN after in_delay; +ENPCOMMAALIGN_ipd <= ENPCOMMAALIGN after in_delay; +LOOPBACK_ipd <= LOOPBACK after in_delay; +POWERDOWN_ipd <= POWERDOWN after in_delay; +REFCLK_ipd <= REFCLK after in_delay; +REFCLK2_ipd <= REFCLK2 after in_delay; +REFCLKSEL_ipd <= REFCLKSEL after in_delay; +RXN_ipd <= RXN after in_delay; +RXP_ipd <= RXP after in_delay; +RXPOLARITY_ipd <= RXPOLARITY after in_delay; +RXRESET_ipd <= RXRESET after in_delay; +RXUSRCLK_ipd <= RXUSRCLK after in_delay; +RXUSRCLK2_ipd <= RXUSRCLK2 after in_delay; +TXBYPASS8B10B_ipd <= TXBYPASS8B10B after in_delay; +TXCHARDISPMODE_ipd <= TXCHARDISPMODE after in_delay; +TXCHARDISPVAL_ipd <= TXCHARDISPVAL after in_delay; +TXCHARISK_ipd <= TXCHARISK after in_delay; +TXDATA_ipd <= TXDATA after in_delay; +TXFORCECRCERR_ipd <= TXFORCECRCERR after in_delay; +TXINHIBIT_ipd <= TXINHIBIT after in_delay; +TXPOLARITY_ipd <= TXPOLARITY after in_delay; +TXRESET_ipd <= TXRESET after in_delay; +TXUSRCLK_ipd <= TXUSRCLK after in_delay; +TXUSRCLK2_ipd <= TXUSRCLK2 after in_delay; + + gt_swift_bw_1 : GT_SWIFT_BUS + port map ( + ALIGN_COMMA_MSB => ALIGN_COMMA_MSB_BINARY, + BREFCLK => BREFCLK_ipd, + BREFCLK2 => BREFCLK2_ipd, + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT_BINARY, + CHAN_BOND_MODE => CHAN_BOND_MODE_BINARY, + CHAN_BOND_OFFSET => CHAN_BOND_OFFSET_BINARY, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT_BINARY, + CHAN_BOND_SEQ_1_1 => CHAN_BOND_SEQ_1_1_BINARY, + CHAN_BOND_SEQ_1_2 => CHAN_BOND_SEQ_1_2_BINARY, + CHAN_BOND_SEQ_1_3 => CHAN_BOND_SEQ_1_3_BINARY, + CHAN_BOND_SEQ_1_4 => CHAN_BOND_SEQ_1_4_BINARY, + CHAN_BOND_SEQ_2_1 => CHAN_BOND_SEQ_2_1_BINARY, + CHAN_BOND_SEQ_2_2 => CHAN_BOND_SEQ_2_2_BINARY, + CHAN_BOND_SEQ_2_3 => CHAN_BOND_SEQ_2_3_BINARY, + CHAN_BOND_SEQ_2_4 => CHAN_BOND_SEQ_2_4_BINARY, + CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE_BINARY, + CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN_BINARY, + CHAN_BOND_WAIT => CHAN_BOND_WAIT_BINARY, + CHBONDDONE => CHBONDDONE_out, + CHBONDI => CHBONDI_ipd, + CHBONDO => CHBONDO_out, + CLK_CORRECT_USE => CLK_CORRECT_USE_BINARY, + CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG_BINARY, + CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE_BINARY, + CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT_BINARY, + CLK_COR_SEQ_1_1 => CLK_COR_SEQ_1_1_BINARY, + CLK_COR_SEQ_1_2 => CLK_COR_SEQ_1_2_BINARY, + CLK_COR_SEQ_1_3 => CLK_COR_SEQ_1_3_BINARY, + CLK_COR_SEQ_1_4 => CLK_COR_SEQ_1_4_BINARY, + CLK_COR_SEQ_2_1 => CLK_COR_SEQ_2_1_BINARY, + CLK_COR_SEQ_2_2 => CLK_COR_SEQ_2_2_BINARY, + CLK_COR_SEQ_2_3 => CLK_COR_SEQ_2_3_BINARY, + CLK_COR_SEQ_2_4 => CLK_COR_SEQ_2_4_BINARY, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE_BINARY, + CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN_BINARY, + COMMA_10B_MASK => COMMA_10B_MASK_BINARY, + CONFIGENABLE => CONFIGENABLE_ipd, + CONFIGIN => CONFIGIN_ipd, + CONFIGOUT => CONFIGOUT_out, + CRC_END_OF_PKT => CRC_END_OF_PKT_BINARY, + CRC_FORMAT => CRC_FORMAT_BINARY, + CRC_START_OF_PKT => CRC_START_OF_PKT_BINARY, + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT_BINARY, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT_BINARY, + DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY_BINARY, + ENCHANSYNC => ENCHANSYNC_ipd, + ENMCOMMAALIGN => ENMCOMMAALIGN_ipd, + ENPCOMMAALIGN => ENPCOMMAALIGN_ipd, + GSR => GSR, + LOOPBACK => LOOPBACK_ipd, + MCOMMA_10B_VALUE => MCOMMA_10B_VALUE_BINARY, + MCOMMA_DETECT => MCOMMA_DETECT_BINARY, + PCOMMA_10B_VALUE => PCOMMA_10B_VALUE_BINARY, + PCOMMA_DETECT => PCOMMA_DETECT_BINARY, + POWERDOWN => POWERDOWN_ipd, + REFCLK => REFCLK_ipd, + REFCLK2 => REFCLK2_ipd, + REFCLKSEL => REFCLKSEL_ipd, + REF_CLK_V_SEL => REF_CLK_V_SEL_BINARY, + RXBUFSTATUS => RXBUFSTATUS_out, + RXCHARISCOMMA => RXCHARISCOMMA_out, + RXCHARISK => RXCHARISK_out, + RXCHECKINGCRC => RXCHECKINGCRC_out, + RXCLKCORCNT => RXCLKCORCNT_out, + RXCOMMADET => RXCOMMADET_out, + RXCRCERR => RXCRCERR_out, + RXDATA => RXDATA_out, + RXDISPERR => RXDISPERR_out, + RXLOSSOFSYNC => RXLOSSOFSYNC_out, + RXN => RXN_ipd, + RXNOTINTABLE => RXNOTINTABLE_out, + RXP => RXP_ipd, + RXPOLARITY => RXPOLARITY_ipd, + RXREALIGN => RXREALIGN_out, + RXRECCLK => RXRECCLK_out, + RXRESET => RXRESET_ipd, + RXRUNDISP => RXRUNDISP_out, + RXUSRCLK => RXUSRCLK_ipd, + RXUSRCLK2 => RXUSRCLK2_ipd, + RX_BUFFER_USE => RX_BUFFER_USE_BINARY, + RX_CRC_USE => RX_CRC_USE_BINARY, + RX_DATA_WIDTH => RX_DATA_WIDTH_BINARY, + RX_DECODE_USE => RX_DECODE_USE_BINARY, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM_BINARY, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR_BINARY, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD_BINARY, + SERDES_10B => SERDES_10B_BINARY, + TERMINATION_IMP => TERMINATION_IMP_BINARY, + TXBUFERR => TXBUFERR_out, + TXBYPASS8B10B => TXBYPASS8B10B_ipd, + TXCHARDISPMODE => TXCHARDISPMODE_ipd, + TXCHARDISPVAL => TXCHARDISPVAL_ipd, + TXCHARISK => TXCHARISK_ipd, + TXDATA => TXDATA_ipd, + TXFORCECRCERR => TXFORCECRCERR_ipd, + TXINHIBIT => TXINHIBIT_ipd, + TXKERR => TXKERR_out, + TXN => TXN_out, + TXP => TXP_out, + TXPOLARITY => TXPOLARITY_ipd, + TXRESET => TXRESET_ipd, + TXRUNDISP => TXRUNDISP_out, + TXUSRCLK => TXUSRCLK_ipd, + TXUSRCLK2 => TXUSRCLK2_ipd, + TX_BUFFER_USE => TX_BUFFER_USE_BINARY, + TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE_BINARY, + TX_CRC_USE => TX_CRC_USE_BINARY, + TX_DATA_WIDTH => TX_DATA_WIDTH_BINARY, + TX_DIFF_CTRL => TX_DIFF_CTRL_BINARY, + TX_PREEMPHASIS => TX_PREEMPHASIS_BINARY + + ); + + INIPROC : process + begin + case ALIGN_COMMA_MSB is + when FALSE => ALIGN_COMMA_MSB_BINARY <= '0'; + when TRUE => ALIGN_COMMA_MSB_BINARY <= '1'; + when others => assert FALSE report "Error : ALIGN_COMMA_MSB is neither TRUE nor FALSE." severity warning; + end case; + case CHAN_BOND_LIMIT is + when 1 => CHAN_BOND_LIMIT_BINARY <= "00001"; + when 2 => CHAN_BOND_LIMIT_BINARY <= "00010"; + when 3 => CHAN_BOND_LIMIT_BINARY <= "00011"; + when 4 => CHAN_BOND_LIMIT_BINARY <= "00100"; + when 5 => CHAN_BOND_LIMIT_BINARY <= "00101"; + when 6 => CHAN_BOND_LIMIT_BINARY <= "00110"; + when 7 => CHAN_BOND_LIMIT_BINARY <= "00111"; + when 8 => CHAN_BOND_LIMIT_BINARY <= "01000"; + when 9 => CHAN_BOND_LIMIT_BINARY <= "01001"; + when 10 => CHAN_BOND_LIMIT_BINARY <= "01010"; + when 11 => CHAN_BOND_LIMIT_BINARY <= "01011"; + when 12 => CHAN_BOND_LIMIT_BINARY <= "01100"; + when 13 => CHAN_BOND_LIMIT_BINARY <= "01101"; + when 14 => CHAN_BOND_LIMIT_BINARY <= "01110"; + when 15 => CHAN_BOND_LIMIT_BINARY <= "01111"; + when 16 => CHAN_BOND_LIMIT_BINARY <= "10000"; + when 17 => CHAN_BOND_LIMIT_BINARY <= "10001"; + when 18 => CHAN_BOND_LIMIT_BINARY <= "10010"; + when 19 => CHAN_BOND_LIMIT_BINARY <= "10011"; + when 20 => CHAN_BOND_LIMIT_BINARY <= "10100"; + when 21 => CHAN_BOND_LIMIT_BINARY <= "10101"; + when 22 => CHAN_BOND_LIMIT_BINARY <= "10110"; + when 23 => CHAN_BOND_LIMIT_BINARY <= "10111"; + when 24 => CHAN_BOND_LIMIT_BINARY <= "11000"; + when 25 => CHAN_BOND_LIMIT_BINARY <= "11001"; + when 26 => CHAN_BOND_LIMIT_BINARY <= "11010"; + when 27 => CHAN_BOND_LIMIT_BINARY <= "11011"; + when 28 => CHAN_BOND_LIMIT_BINARY <= "11100"; + when 29 => CHAN_BOND_LIMIT_BINARY <= "11101"; + when 30 => CHAN_BOND_LIMIT_BINARY <= "11110"; + when 31 => CHAN_BOND_LIMIT_BINARY <= "11111"; + when others => assert FALSE report "Error : CHAN_BOND_LIMIT is not in range 1...31." severity warning; + end case; +-- case CHAN_BOND_MODE is + if((CHAN_BOND_MODE = "OFF") or (CHAN_BOND_MODE = "off")) then + CHAN_BOND_MODE_BINARY <= "00"; + elsif((CHAN_BOND_MODE = "MASTER") or (CHAN_BOND_MODE = "master")) then + CHAN_BOND_MODE_BINARY <= "01"; + elsif((CHAN_BOND_MODE = "SLAVE_1_HOP") or (CHAN_BOND_MODE = "slave_1_hop")) then + CHAN_BOND_MODE_BINARY <= "10"; + elsif((CHAN_BOND_MODE = "SLAVE_2_HOPS") or (CHAN_BOND_MODE = "slave_2_hops")) then + CHAN_BOND_MODE_BINARY <= "11"; + else + assert FALSE report "Error : CHAN_BOND_MODE = is not OFF, MASTER, SLAVE_1_HOP, SLAVE_2_HOPS." severity warning; + end if; +-- end case; + case CHAN_BOND_OFFSET is + when 0 => CHAN_BOND_OFFSET_BINARY <= "0000"; + when 1 => CHAN_BOND_OFFSET_BINARY <= "0001"; + when 2 => CHAN_BOND_OFFSET_BINARY <= "0010"; + when 3 => CHAN_BOND_OFFSET_BINARY <= "0011"; + when 4 => CHAN_BOND_OFFSET_BINARY <= "0100"; + when 5 => CHAN_BOND_OFFSET_BINARY <= "0101"; + when 6 => CHAN_BOND_OFFSET_BINARY <= "0110"; + when 7 => CHAN_BOND_OFFSET_BINARY <= "0111"; + when 8 => CHAN_BOND_OFFSET_BINARY <= "1000"; + when 9 => CHAN_BOND_OFFSET_BINARY <= "1001"; + when 10 => CHAN_BOND_OFFSET_BINARY <= "1010"; + when 11 => CHAN_BOND_OFFSET_BINARY <= "1011"; + when 12 => CHAN_BOND_OFFSET_BINARY <= "1100"; + when 13 => CHAN_BOND_OFFSET_BINARY <= "1101"; + when 14 => CHAN_BOND_OFFSET_BINARY <= "1110"; + when 15 => CHAN_BOND_OFFSET_BINARY <= "1111"; + when others => assert FALSE report "Error : CHAN_BOND_OFFSET is not in range 0...15." severity warning; + end case; + case CHAN_BOND_ONE_SHOT is + when FALSE => CHAN_BOND_ONE_SHOT_BINARY <= '0'; + when TRUE => CHAN_BOND_ONE_SHOT_BINARY <= '1'; + when others => assert FALSE report "Error : CHAN_BOND_ONE_SHOT is neither TRUE nor FALSE." severity warning; + end case; + case CHAN_BOND_SEQ_2_USE is + when FALSE => CHAN_BOND_SEQ_2_USE_BINARY <= '0'; + when TRUE => CHAN_BOND_SEQ_2_USE_BINARY <= '1'; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_2_USE is neither TRUE nor FALSE." severity warning; + end case; + case CHAN_BOND_SEQ_LEN is + when 1 => CHAN_BOND_SEQ_LEN_BINARY <= "01"; + when 2 => CHAN_BOND_SEQ_LEN_BINARY <= "10"; + when 3 => CHAN_BOND_SEQ_LEN_BINARY <= "11"; + when 4 => CHAN_BOND_SEQ_LEN_BINARY <= "00"; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_LEN is not in range 1...4." severity warning; + end case; + case CHAN_BOND_WAIT is + when 1 => CHAN_BOND_WAIT_BINARY <= "0001"; + when 2 => CHAN_BOND_WAIT_BINARY <= "0010"; + when 3 => CHAN_BOND_WAIT_BINARY <= "0011"; + when 4 => CHAN_BOND_WAIT_BINARY <= "0100"; + when 5 => CHAN_BOND_WAIT_BINARY <= "0101"; + when 6 => CHAN_BOND_WAIT_BINARY <= "0110"; + when 7 => CHAN_BOND_WAIT_BINARY <= "0111"; + when 8 => CHAN_BOND_WAIT_BINARY <= "1000"; + when 9 => CHAN_BOND_WAIT_BINARY <= "1001"; + when 10 => CHAN_BOND_WAIT_BINARY <= "1010"; + when 11 => CHAN_BOND_WAIT_BINARY <= "1011"; + when 12 => CHAN_BOND_WAIT_BINARY <= "1100"; + when 13 => CHAN_BOND_WAIT_BINARY <= "1101"; + when 14 => CHAN_BOND_WAIT_BINARY <= "1110"; + when 15 => CHAN_BOND_WAIT_BINARY <= "1111"; + when others => assert FALSE report "Error : CHAN_BOND_WAIT is not in range 1...15." severity warning; + end case; + case CLK_COR_INSERT_IDLE_FLAG is + when FALSE => CLK_COR_INSERT_IDLE_FLAG_BINARY <= '0'; + when TRUE => CLK_COR_INSERT_IDLE_FLAG_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_INSERT_IDLE_FLAG is neither TRUE nor FALSE." severity warning; + end case; + case CLK_COR_KEEP_IDLE is + when FALSE => CLK_COR_KEEP_IDLE_BINARY <= '0'; + when TRUE => CLK_COR_KEEP_IDLE_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_KEEP_IDLE is neither TRUE nor FALSE." severity warning; + end case; + case CLK_COR_REPEAT_WAIT is + when 0 => CLK_COR_REPEAT_WAIT_BINARY <= "00000"; + when 1 => CLK_COR_REPEAT_WAIT_BINARY <= "00001"; + when 2 => CLK_COR_REPEAT_WAIT_BINARY <= "00010"; + when 3 => CLK_COR_REPEAT_WAIT_BINARY <= "00011"; + when 4 => CLK_COR_REPEAT_WAIT_BINARY <= "00100"; + when 5 => CLK_COR_REPEAT_WAIT_BINARY <= "00101"; + when 6 => CLK_COR_REPEAT_WAIT_BINARY <= "00110"; + when 7 => CLK_COR_REPEAT_WAIT_BINARY <= "00111"; + when 8 => CLK_COR_REPEAT_WAIT_BINARY <= "01000"; + when 9 => CLK_COR_REPEAT_WAIT_BINARY <= "01001"; + when 10 => CLK_COR_REPEAT_WAIT_BINARY <= "01010"; + when 11 => CLK_COR_REPEAT_WAIT_BINARY <= "01011"; + when 12 => CLK_COR_REPEAT_WAIT_BINARY <= "01100"; + when 13 => CLK_COR_REPEAT_WAIT_BINARY <= "01101"; + when 14 => CLK_COR_REPEAT_WAIT_BINARY <= "01110"; + when 15 => CLK_COR_REPEAT_WAIT_BINARY <= "01111"; + when 16 => CLK_COR_REPEAT_WAIT_BINARY <= "10000"; + when 17 => CLK_COR_REPEAT_WAIT_BINARY <= "10001"; + when 18 => CLK_COR_REPEAT_WAIT_BINARY <= "10010"; + when 19 => CLK_COR_REPEAT_WAIT_BINARY <= "10011"; + when 20 => CLK_COR_REPEAT_WAIT_BINARY <= "10100"; + when 21 => CLK_COR_REPEAT_WAIT_BINARY <= "10101"; + when 22 => CLK_COR_REPEAT_WAIT_BINARY <= "10110"; + when 23 => CLK_COR_REPEAT_WAIT_BINARY <= "10111"; + when 24 => CLK_COR_REPEAT_WAIT_BINARY <= "11000"; + when 25 => CLK_COR_REPEAT_WAIT_BINARY <= "11001"; + when 26 => CLK_COR_REPEAT_WAIT_BINARY <= "11010"; + when 27 => CLK_COR_REPEAT_WAIT_BINARY <= "11011"; + when 28 => CLK_COR_REPEAT_WAIT_BINARY <= "11100"; + when 29 => CLK_COR_REPEAT_WAIT_BINARY <= "11101"; + when 30 => CLK_COR_REPEAT_WAIT_BINARY <= "11110"; + when 31 => CLK_COR_REPEAT_WAIT_BINARY <= "11111"; + when others => assert FALSE report "Error : CLK_COR_REPEAT_WAIT is not in range 0...31." severity warning; + end case; + case CLK_COR_SEQ_2_USE is + when FALSE => CLK_COR_SEQ_2_USE_BINARY <= '0'; + when TRUE => CLK_COR_SEQ_2_USE_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_SEQ_2_USE is neither TRUE nor FALSE." severity warning; + end case; + case CLK_COR_SEQ_LEN is + when 1 => CLK_COR_SEQ_LEN_BINARY <= "01"; + when 2 => CLK_COR_SEQ_LEN_BINARY <= "10"; + when 3 => CLK_COR_SEQ_LEN_BINARY <= "11"; + when 4 => CLK_COR_SEQ_LEN_BINARY <= "00"; + when others => assert FALSE report "Error : CLK_COR_SEQ_LEN is not in range 1...4." severity warning; + end case; + case CLK_CORRECT_USE is + when FALSE => CLK_CORRECT_USE_BINARY <= '0'; + when TRUE => CLK_CORRECT_USE_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_CORRECT_USE is neither TRUE nor FALSE." severity warning; + end case; +-- case CRC_END_OF_PKT is + if((CRC_END_OF_PKT = "K28_0") or (CRC_END_OF_PKT = "k28_0")) then + CRC_END_OF_PKT_BINARY <= "00011100"; + elsif((CRC_END_OF_PKT = "K28_1") or (CRC_END_OF_PKT = "k28_1")) then + CRC_END_OF_PKT_BINARY <= "00111100"; + elsif((CRC_END_OF_PKT = "K28_2") or (CRC_END_OF_PKT = "k28_2")) then + CRC_END_OF_PKT_BINARY <= "01011100"; + elsif((CRC_END_OF_PKT = "K28_3") or (CRC_END_OF_PKT = "k28_3")) then + CRC_END_OF_PKT_BINARY <= "01111100"; + elsif((CRC_END_OF_PKT = "K28_4") or (CRC_END_OF_PKT = "k28_4")) then + CRC_END_OF_PKT_BINARY <= "10011100"; + elsif((CRC_END_OF_PKT = "K28_5") or (CRC_END_OF_PKT = "k28_5")) then + CRC_END_OF_PKT_BINARY <= "10111100"; + elsif((CRC_END_OF_PKT = "K28_6") or (CRC_END_OF_PKT = "k28_6")) then + CRC_END_OF_PKT_BINARY <= "11011100"; + elsif((CRC_END_OF_PKT = "K28_7") or (CRC_END_OF_PKT = "k28_7")) then + CRC_END_OF_PKT_BINARY <= "11111100"; + elsif((CRC_END_OF_PKT = "K23_7") or (CRC_END_OF_PKT = "k23_7")) then + CRC_END_OF_PKT_BINARY <= "11110111"; + elsif((CRC_END_OF_PKT = "K27_7") or (CRC_END_OF_PKT = "k27_7")) then + CRC_END_OF_PKT_BINARY <= "11111011"; + elsif((CRC_END_OF_PKT = "K29_7") or (CRC_END_OF_PKT = "k29_7")) then + CRC_END_OF_PKT_BINARY <= "11111101"; + elsif((CRC_END_OF_PKT = "K30_7") or (CRC_END_OF_PKT = "k30_7")) then + CRC_END_OF_PKT_BINARY <= "11111110"; + else + assert FALSE report "Error : CRC_END_OF_PKT = is not K28_0, K28_1, K28_2, K28_3, K28_4, K28_5, K28_6, K28_7, K23_7, K27_7, K29_7, K30_7." severity warning; + end if; +-- end case; +-- case CRC_FORMAT is + if((CRC_FORMAT = "USER_MODE") or (CRC_FORMAT = "user_mode")) then + CRC_FORMAT_BINARY <= "00"; + elsif((CRC_FORMAT = "ETHERNET") or (CRC_FORMAT = "ethernet")) then + CRC_FORMAT_BINARY <= "01"; + elsif((CRC_FORMAT = "INFINIBAND") or (CRC_FORMAT = "infiniband")) then + CRC_FORMAT_BINARY <= "10"; + elsif((CRC_FORMAT = "FIBRE_CHAN") or (CRC_FORMAT = "fibre_chan")) then + CRC_FORMAT_BINARY <= "11"; + else + assert FALSE report "Error : CRC_FORMAT = is not USER_MODE, ETHERNET, INFINIBAND, FIBRE_CHAN." severity warning; + end if; +-- end case; +-- case CRC_START_OF_PKT is + if((CRC_START_OF_PKT = "K28_0") or (CRC_START_OF_PKT = "k28_0")) then + CRC_START_OF_PKT_BINARY <= "00011100"; + elsif((CRC_START_OF_PKT = "K28_1") or (CRC_START_OF_PKT = "k28_1")) then + CRC_START_OF_PKT_BINARY <= "00111100"; + elsif((CRC_START_OF_PKT = "K28_2") or (CRC_START_OF_PKT = "k28_2")) then + CRC_START_OF_PKT_BINARY <= "01011100"; + elsif((CRC_START_OF_PKT = "K28_3") or (CRC_START_OF_PKT = "k28_3")) then + CRC_START_OF_PKT_BINARY <= "01111100"; + elsif((CRC_START_OF_PKT = "K28_4") or (CRC_START_OF_PKT = "k28_4")) then + CRC_START_OF_PKT_BINARY <= "10011100"; + elsif((CRC_START_OF_PKT = "K28_5") or (CRC_START_OF_PKT = "k28_5")) then + CRC_START_OF_PKT_BINARY <= "10111100"; + elsif((CRC_START_OF_PKT = "K28_6") or (CRC_START_OF_PKT = "k28_6")) then + CRC_START_OF_PKT_BINARY <= "11011100"; + elsif((CRC_START_OF_PKT = "K28_7") or (CRC_START_OF_PKT = "k28_7")) then + CRC_START_OF_PKT_BINARY <= "11111100"; + elsif((CRC_START_OF_PKT = "K23_7") or (CRC_START_OF_PKT = "k23_7")) then + CRC_START_OF_PKT_BINARY <= "11110111"; + elsif((CRC_START_OF_PKT = "K27_7") or (CRC_START_OF_PKT = "k27_7")) then + CRC_START_OF_PKT_BINARY <= "11111011"; + elsif((CRC_START_OF_PKT = "K29_7") or (CRC_START_OF_PKT = "k29_7")) then + CRC_START_OF_PKT_BINARY <= "11111101"; + elsif((CRC_START_OF_PKT = "K30_7") or (CRC_START_OF_PKT = "k30_7")) then + CRC_START_OF_PKT_BINARY <= "11111110"; + else + assert FALSE report "Error : CRC_START_OF_PKT = is not K28_0, K28_1, K28_2, K28_3, K28_4, K28_5, K28_6, K28_7, K23_7, K27_7, K29_7, K30_7." severity warning; + end if; +-- end case; + case DEC_MCOMMA_DETECT is + when FALSE => DEC_MCOMMA_DETECT_BINARY <= '0'; + when TRUE => DEC_MCOMMA_DETECT_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_MCOMMA_DETECT is neither TRUE nor FALSE." severity warning; + end case; + case DEC_PCOMMA_DETECT is + when FALSE => DEC_PCOMMA_DETECT_BINARY <= '0'; + when TRUE => DEC_PCOMMA_DETECT_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_PCOMMA_DETECT is neither TRUE nor FALSE." severity warning; + end case; + case DEC_VALID_COMMA_ONLY is + when FALSE => DEC_VALID_COMMA_ONLY_BINARY <= '0'; + when TRUE => DEC_VALID_COMMA_ONLY_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_VALID_COMMA_ONLY is neither TRUE nor FALSE." severity warning; + end case; + case MCOMMA_DETECT is + when FALSE => MCOMMA_DETECT_BINARY <= '0'; + when TRUE => MCOMMA_DETECT_BINARY <= '1'; + when others => assert FALSE report "Error : MCOMMA_DETECT is neither TRUE nor FALSE." severity warning; + end case; + case PCOMMA_DETECT is + when FALSE => PCOMMA_DETECT_BINARY <= '0'; + when TRUE => PCOMMA_DETECT_BINARY <= '1'; + when others => assert FALSE report "Error : PCOMMA_DETECT is neither TRUE nor FALSE." severity warning; + end case; + case REF_CLK_V_SEL is + when 0 => REF_CLK_V_SEL_BINARY <= '0'; + when 1 => REF_CLK_V_SEL_BINARY <= '1'; + when others => assert FALSE report "Error : REF_CLK_V_SEL is not in 0, 1." severity warning; + end case; + case RX_BUFFER_USE is + when FALSE => RX_BUFFER_USE_BINARY <= '0'; + when TRUE => RX_BUFFER_USE_BINARY <= '1'; + when others => assert FALSE report "Error : RX_BUFFER_USE is neither TRUE nor FALSE." severity warning; + end case; + case RX_CRC_USE is + when FALSE => RX_CRC_USE_BINARY <= '0'; + when TRUE => RX_CRC_USE_BINARY <= '1'; + when others => assert FALSE report "Error : RX_CRC_USE is neither TRUE nor FALSE." severity warning; + end case; + case RX_DATA_WIDTH is + when 1 => RX_DATA_WIDTH_BINARY <= "01"; + when 2 => RX_DATA_WIDTH_BINARY <= "10"; + when 4 => RX_DATA_WIDTH_BINARY <= "00"; + when others => assert FALSE report "Error : RX_DATA_WIDTH is not in 1, 2, 4." severity warning; + end case; + case RX_DECODE_USE is + when FALSE => RX_DECODE_USE_BINARY <= '0'; + when TRUE => RX_DECODE_USE_BINARY <= '1'; + when others => assert FALSE report "Error : RX_DECODE_USE is neither TRUE nor FALSE." severity warning; + end case; + case RX_LOS_INVALID_INCR is + when 1 => RX_LOS_INVALID_INCR_BINARY <= "000"; + when 2 => RX_LOS_INVALID_INCR_BINARY <= "001"; + when 4 => RX_LOS_INVALID_INCR_BINARY <= "010"; + when 8 => RX_LOS_INVALID_INCR_BINARY <= "011"; + when 16 => RX_LOS_INVALID_INCR_BINARY <= "100"; + when 32 => RX_LOS_INVALID_INCR_BINARY <= "101"; + when 64 => RX_LOS_INVALID_INCR_BINARY <= "110"; + when 128 => RX_LOS_INVALID_INCR_BINARY <= "111"; + when others => assert FALSE report "Error : RX_LOS_INVALID_INCR is not in 1, 2, 4, 8, 16, 32, 64, 128." severity warning; + end case; + case RX_LOS_THRESHOLD is + when 4 => RX_LOS_THRESHOLD_BINARY <= "000"; + when 8 => RX_LOS_THRESHOLD_BINARY <= "001"; + when 16 => RX_LOS_THRESHOLD_BINARY <= "010"; + when 32 => RX_LOS_THRESHOLD_BINARY <= "011"; + when 64 => RX_LOS_THRESHOLD_BINARY <= "100"; + when 128 => RX_LOS_THRESHOLD_BINARY <= "101"; + when 256 => RX_LOS_THRESHOLD_BINARY <= "110"; + when 512 => RX_LOS_THRESHOLD_BINARY <= "111"; + when others => assert FALSE report "Error : RX_LOS_THRESHOLD is not in 4, 8, 16, 32, 64, 128, 256, 512." severity warning; + end case; + case RX_LOSS_OF_SYNC_FSM is + when FALSE => RX_LOSS_OF_SYNC_FSM_BINARY <= '0'; + when TRUE => RX_LOSS_OF_SYNC_FSM_BINARY <= '1'; + when others => assert FALSE report "Error : RX_LOSS_OF_SYNC_FSM is neither TRUE nor FALSE." severity warning; + end case; + case SERDES_10B is + when FALSE => SERDES_10B_BINARY <= '0'; + when TRUE => SERDES_10B_BINARY <= '1'; + when others => assert FALSE report "Error : SERDES_10B is neither TRUE nor FALSE." severity warning; + end case; + case TERMINATION_IMP is + when 50 => TERMINATION_IMP_BINARY <= '0'; + when 75 => TERMINATION_IMP_BINARY <= '1'; + when others => assert FALSE report "Error : TERMINATION_IMP is not in 50, 75." severity warning; + end case; + case TX_BUFFER_USE is + when FALSE => TX_BUFFER_USE_BINARY <= '0'; + when TRUE => TX_BUFFER_USE_BINARY <= '1'; + when others => assert FALSE report "Error : TX_BUFFER_USE is neither TRUE nor FALSE." severity warning; + end case; + case TX_CRC_USE is + when FALSE => TX_CRC_USE_BINARY <= '0'; + when TRUE => TX_CRC_USE_BINARY <= '1'; + when others => assert FALSE report "Error : TX_CRC_USE is neither TRUE nor FALSE." severity warning; + end case; + case TX_DATA_WIDTH is + when 1 => TX_DATA_WIDTH_BINARY <= "01"; + when 2 => TX_DATA_WIDTH_BINARY <= "10"; + when 4 => TX_DATA_WIDTH_BINARY <= "00"; + when others => assert FALSE report "Error : TX_DATA_WIDTH is not in 1, 2, 4." severity warning; + end case; + case TX_DIFF_CTRL is + when 400 => TX_DIFF_CTRL_BINARY <= "010"; + when 500 => TX_DIFF_CTRL_BINARY <= "000"; + when 600 => TX_DIFF_CTRL_BINARY <= "001"; + when 700 => TX_DIFF_CTRL_BINARY <= "011"; + when 800 => TX_DIFF_CTRL_BINARY <= "110"; + when others => assert FALSE report "Error : TX_DIFF_CTRL is not in 400, 500, 600, 700, 800." severity warning; + end case; + case TX_PREEMPHASIS is + when 0 => TX_PREEMPHASIS_BINARY <= "00"; + when 1 => TX_PREEMPHASIS_BINARY <= "01"; + when 2 => TX_PREEMPHASIS_BINARY <= "10"; + when 3 => TX_PREEMPHASIS_BINARY <= "11"; + when others => assert FALSE report "Error : TX_PREEMPHASIS is not in 0, 1, 2, 3." severity warning; + end case; + wait; + end process INIPROC; + + TIMING : process + +-- Pin timing violations (clock input pins) + +-- Pin Timing Violations (all input pins) + +-- Output Pin glitch declaration + variable CHBONDDONE_GlitchData : VitalGlitchDataType; + variable CHBONDO0_GlitchData : VitalGlitchDataType; + variable CHBONDO1_GlitchData : VitalGlitchDataType; + variable CHBONDO2_GlitchData : VitalGlitchDataType; + variable CHBONDO3_GlitchData : VitalGlitchDataType; + variable CONFIGOUT_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS0_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS1_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA0_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA1_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA2_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA3_GlitchData : VitalGlitchDataType; + variable RXCHARISK0_GlitchData : VitalGlitchDataType; + variable RXCHARISK1_GlitchData : VitalGlitchDataType; + variable RXCHARISK2_GlitchData : VitalGlitchDataType; + variable RXCHARISK3_GlitchData : VitalGlitchDataType; + variable RXCHECKINGCRC_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT0_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT1_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT2_GlitchData : VitalGlitchDataType; + variable RXCOMMADET_GlitchData : VitalGlitchDataType; + variable RXCRCERR_GlitchData : VitalGlitchDataType; + variable RXDATA0_GlitchData : VitalGlitchDataType; + variable RXDATA1_GlitchData : VitalGlitchDataType; + variable RXDATA2_GlitchData : VitalGlitchDataType; + variable RXDATA3_GlitchData : VitalGlitchDataType; + variable RXDATA4_GlitchData : VitalGlitchDataType; + variable RXDATA5_GlitchData : VitalGlitchDataType; + variable RXDATA6_GlitchData : VitalGlitchDataType; + variable RXDATA7_GlitchData : VitalGlitchDataType; + variable RXDATA8_GlitchData : VitalGlitchDataType; + variable RXDATA9_GlitchData : VitalGlitchDataType; + variable RXDATA10_GlitchData : VitalGlitchDataType; + variable RXDATA11_GlitchData : VitalGlitchDataType; + variable RXDATA12_GlitchData : VitalGlitchDataType; + variable RXDATA13_GlitchData : VitalGlitchDataType; + variable RXDATA14_GlitchData : VitalGlitchDataType; + variable RXDATA15_GlitchData : VitalGlitchDataType; + variable RXDATA16_GlitchData : VitalGlitchDataType; + variable RXDATA17_GlitchData : VitalGlitchDataType; + variable RXDATA18_GlitchData : VitalGlitchDataType; + variable RXDATA19_GlitchData : VitalGlitchDataType; + variable RXDATA20_GlitchData : VitalGlitchDataType; + variable RXDATA21_GlitchData : VitalGlitchDataType; + variable RXDATA22_GlitchData : VitalGlitchDataType; + variable RXDATA23_GlitchData : VitalGlitchDataType; + variable RXDATA24_GlitchData : VitalGlitchDataType; + variable RXDATA25_GlitchData : VitalGlitchDataType; + variable RXDATA26_GlitchData : VitalGlitchDataType; + variable RXDATA27_GlitchData : VitalGlitchDataType; + variable RXDATA28_GlitchData : VitalGlitchDataType; + variable RXDATA29_GlitchData : VitalGlitchDataType; + variable RXDATA30_GlitchData : VitalGlitchDataType; + variable RXDATA31_GlitchData : VitalGlitchDataType; + variable RXDISPERR0_GlitchData : VitalGlitchDataType; + variable RXDISPERR1_GlitchData : VitalGlitchDataType; + variable RXDISPERR2_GlitchData : VitalGlitchDataType; + variable RXDISPERR3_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC0_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC1_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE0_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE1_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE2_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE3_GlitchData : VitalGlitchDataType; + variable RXREALIGN_GlitchData : VitalGlitchDataType; +-- variable RXRECCLK_GlitchData : VitalGlitchDataType; + variable RXRUNDISP0_GlitchData : VitalGlitchDataType; + variable RXRUNDISP1_GlitchData : VitalGlitchDataType; + variable RXRUNDISP2_GlitchData : VitalGlitchDataType; + variable RXRUNDISP3_GlitchData : VitalGlitchDataType; + variable TXBUFERR_GlitchData : VitalGlitchDataType; + variable TXKERR0_GlitchData : VitalGlitchDataType; + variable TXKERR1_GlitchData : VitalGlitchDataType; + variable TXKERR2_GlitchData : VitalGlitchDataType; + variable TXKERR3_GlitchData : VitalGlitchDataType; +-- variable TXN_GlitchData : VitalGlitchDataType; +-- variable TXP_GlitchData : VitalGlitchDataType; + variable TXRUNDISP0_GlitchData : VitalGlitchDataType; + variable TXRUNDISP1_GlitchData : VitalGlitchDataType; + variable TXRUNDISP2_GlitchData : VitalGlitchDataType; + variable TXRUNDISP3_GlitchData : VitalGlitchDataType; +begin + +-- Setup/Hold Check Violations (all input pins) + + +-- End of (TimingChecksOn) + +-- Output-to-Clock path delay + VitalPathDelay01 + ( + OutSignal => CHBONDDONE, + GlitchData => CHBONDDONE_GlitchData, + OutSignalName => "CHBONDDONE", + OutTemp => CHBONDDONE_OUT, + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CHBONDO(0), + GlitchData => CHBONDO0_GlitchData, + OutSignalName => "CHBONDO(0)", + OutTemp => CHBONDO_OUT(0), + Paths => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CHBONDO(1), + GlitchData => CHBONDO1_GlitchData, + OutSignalName => "CHBONDO(1)", + OutTemp => CHBONDO_OUT(1), + Paths => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CHBONDO(2), + GlitchData => CHBONDO2_GlitchData, + OutSignalName => "CHBONDO(2)", + OutTemp => CHBONDO_OUT(2), + Paths => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CHBONDO(3), + GlitchData => CHBONDO3_GlitchData, + OutSignalName => "CHBONDO(3)", + OutTemp => CHBONDO_OUT(3), + Paths => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CONFIGOUT, + GlitchData => CONFIGOUT_GlitchData, + OutSignalName => "CONFIGOUT", + OutTemp => CONFIGOUT_OUT, + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS(0), + GlitchData => RXBUFSTATUS0_GlitchData, + OutSignalName => "RXBUFSTATUS(0)", + OutTemp => RXBUFSTATUS_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS(1), + GlitchData => RXBUFSTATUS1_GlitchData, + OutSignalName => "RXBUFSTATUS(1)", + OutTemp => RXBUFSTATUS_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(0), + GlitchData => RXCHARISCOMMA0_GlitchData, + OutSignalName => "RXCHARISCOMMA(0)", + OutTemp => RXCHARISCOMMA_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(1), + GlitchData => RXCHARISCOMMA1_GlitchData, + OutSignalName => "RXCHARISCOMMA(1)", + OutTemp => RXCHARISCOMMA_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(2), + GlitchData => RXCHARISCOMMA2_GlitchData, + OutSignalName => "RXCHARISCOMMA(2)", + OutTemp => RXCHARISCOMMA_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(3), + GlitchData => RXCHARISCOMMA3_GlitchData, + OutSignalName => "RXCHARISCOMMA(3)", + OutTemp => RXCHARISCOMMA_OUT(3), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(0), + GlitchData => RXCHARISK0_GlitchData, + OutSignalName => "RXCHARISK(0)", + OutTemp => RXCHARISK_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(1), + GlitchData => RXCHARISK1_GlitchData, + OutSignalName => "RXCHARISK(1)", + OutTemp => RXCHARISK_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(2), + GlitchData => RXCHARISK2_GlitchData, + OutSignalName => "RXCHARISK(2)", + OutTemp => RXCHARISK_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(3), + GlitchData => RXCHARISK3_GlitchData, + OutSignalName => "RXCHARISK(3)", + OutTemp => RXCHARISK_OUT(3), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHECKINGCRC, + GlitchData => RXCHECKINGCRC_GlitchData, + OutSignalName => "RXCHECKINGCRC", + OutTemp => RXCHECKINGCRC_OUT, + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT(0), + GlitchData => RXCLKCORCNT0_GlitchData, + OutSignalName => "RXCLKCORCNT(0)", + OutTemp => RXCLKCORCNT_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT(1), + GlitchData => RXCLKCORCNT1_GlitchData, + OutSignalName => "RXCLKCORCNT(1)", + OutTemp => RXCLKCORCNT_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT(2), + GlitchData => RXCLKCORCNT2_GlitchData, + OutSignalName => "RXCLKCORCNT(2)", + OutTemp => RXCLKCORCNT_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCOMMADET, + GlitchData => RXCOMMADET_GlitchData, + OutSignalName => "RXCOMMADET", + OutTemp => RXCOMMADET_OUT, + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCERR, + GlitchData => RXCRCERR_GlitchData, + OutSignalName => "RXCRCERR", + OutTemp => RXCRCERR_OUT, + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(0), + GlitchData => RXDATA0_GlitchData, + OutSignalName => "RXDATA(0)", + OutTemp => RXDATA_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(1), + GlitchData => RXDATA1_GlitchData, + OutSignalName => "RXDATA(1)", + OutTemp => RXDATA_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(2), + GlitchData => RXDATA2_GlitchData, + OutSignalName => "RXDATA(2)", + OutTemp => RXDATA_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(3), + GlitchData => RXDATA3_GlitchData, + OutSignalName => "RXDATA(3)", + OutTemp => RXDATA_OUT(3), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(4), + GlitchData => RXDATA4_GlitchData, + OutSignalName => "RXDATA(4)", + OutTemp => RXDATA_OUT(4), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(5), + GlitchData => RXDATA5_GlitchData, + OutSignalName => "RXDATA(5)", + OutTemp => RXDATA_OUT(5), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(6), + GlitchData => RXDATA6_GlitchData, + OutSignalName => "RXDATA(6)", + OutTemp => RXDATA_OUT(6), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(7), + GlitchData => RXDATA7_GlitchData, + OutSignalName => "RXDATA(7)", + OutTemp => RXDATA_OUT(7), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(8), + GlitchData => RXDATA8_GlitchData, + OutSignalName => "RXDATA(8)", + OutTemp => RXDATA_OUT(8), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(9), + GlitchData => RXDATA9_GlitchData, + OutSignalName => "RXDATA(9)", + OutTemp => RXDATA_OUT(9), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(10), + GlitchData => RXDATA10_GlitchData, + OutSignalName => "RXDATA(10)", + OutTemp => RXDATA_OUT(10), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(11), + GlitchData => RXDATA11_GlitchData, + OutSignalName => "RXDATA(11)", + OutTemp => RXDATA_OUT(11), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(12), + GlitchData => RXDATA12_GlitchData, + OutSignalName => "RXDATA(12)", + OutTemp => RXDATA_OUT(12), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(13), + GlitchData => RXDATA13_GlitchData, + OutSignalName => "RXDATA(13)", + OutTemp => RXDATA_OUT(13), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(14), + GlitchData => RXDATA14_GlitchData, + OutSignalName => "RXDATA(14)", + OutTemp => RXDATA_OUT(14), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(15), + GlitchData => RXDATA15_GlitchData, + OutSignalName => "RXDATA(15)", + OutTemp => RXDATA_OUT(15), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(16), + GlitchData => RXDATA16_GlitchData, + OutSignalName => "RXDATA(16)", + OutTemp => RXDATA_OUT(16), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(17), + GlitchData => RXDATA17_GlitchData, + OutSignalName => "RXDATA(17)", + OutTemp => RXDATA_OUT(17), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(18), + GlitchData => RXDATA18_GlitchData, + OutSignalName => "RXDATA(18)", + OutTemp => RXDATA_OUT(18), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(19), + GlitchData => RXDATA19_GlitchData, + OutSignalName => "RXDATA(19)", + OutTemp => RXDATA_OUT(19), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(20), + GlitchData => RXDATA20_GlitchData, + OutSignalName => "RXDATA(20)", + OutTemp => RXDATA_OUT(20), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(21), + GlitchData => RXDATA21_GlitchData, + OutSignalName => "RXDATA(21)", + OutTemp => RXDATA_OUT(21), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(22), + GlitchData => RXDATA22_GlitchData, + OutSignalName => "RXDATA(22)", + OutTemp => RXDATA_OUT(22), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(23), + GlitchData => RXDATA23_GlitchData, + OutSignalName => "RXDATA(23)", + OutTemp => RXDATA_OUT(23), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(24), + GlitchData => RXDATA24_GlitchData, + OutSignalName => "RXDATA(24)", + OutTemp => RXDATA_OUT(24), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(25), + GlitchData => RXDATA25_GlitchData, + OutSignalName => "RXDATA(25)", + OutTemp => RXDATA_OUT(25), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(26), + GlitchData => RXDATA26_GlitchData, + OutSignalName => "RXDATA(26)", + OutTemp => RXDATA_OUT(26), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(27), + GlitchData => RXDATA27_GlitchData, + OutSignalName => "RXDATA(27)", + OutTemp => RXDATA_OUT(27), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(28), + GlitchData => RXDATA28_GlitchData, + OutSignalName => "RXDATA(28)", + OutTemp => RXDATA_OUT(28), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(29), + GlitchData => RXDATA29_GlitchData, + OutSignalName => "RXDATA(29)", + OutTemp => RXDATA_OUT(29), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(30), + GlitchData => RXDATA30_GlitchData, + OutSignalName => "RXDATA(30)", + OutTemp => RXDATA_OUT(30), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(31), + GlitchData => RXDATA31_GlitchData, + OutSignalName => "RXDATA(31)", + OutTemp => RXDATA_OUT(31), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(0), + GlitchData => RXDISPERR0_GlitchData, + OutSignalName => "RXDISPERR(0)", + OutTemp => RXDISPERR_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(1), + GlitchData => RXDISPERR1_GlitchData, + OutSignalName => "RXDISPERR(1)", + OutTemp => RXDISPERR_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(2), + GlitchData => RXDISPERR2_GlitchData, + OutSignalName => "RXDISPERR(2)", + OutTemp => RXDISPERR_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(3), + GlitchData => RXDISPERR3_GlitchData, + OutSignalName => "RXDISPERR(3)", + OutTemp => RXDISPERR_OUT(3), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC(0), + GlitchData => RXLOSSOFSYNC0_GlitchData, + OutSignalName => "RXLOSSOFSYNC(0)", + OutTemp => RXLOSSOFSYNC_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC(1), + GlitchData => RXLOSSOFSYNC1_GlitchData, + OutSignalName => "RXLOSSOFSYNC(1)", + OutTemp => RXLOSSOFSYNC_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(0), + GlitchData => RXNOTINTABLE0_GlitchData, + OutSignalName => "RXNOTINTABLE(0)", + OutTemp => RXNOTINTABLE_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(1), + GlitchData => RXNOTINTABLE1_GlitchData, + OutSignalName => "RXNOTINTABLE(1)", + OutTemp => RXNOTINTABLE_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(2), + GlitchData => RXNOTINTABLE2_GlitchData, + OutSignalName => "RXNOTINTABLE(2)", + OutTemp => RXNOTINTABLE_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(3), + GlitchData => RXNOTINTABLE3_GlitchData, + OutSignalName => "RXNOTINTABLE(3)", + OutTemp => RXNOTINTABLE_OUT(3), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXREALIGN, + GlitchData => RXREALIGN_GlitchData, + OutSignalName => "RXREALIGN", + OutTemp => RXREALIGN_OUT, + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(0), + GlitchData => RXRUNDISP0_GlitchData, + OutSignalName => "RXRUNDISP(0)", + OutTemp => RXRUNDISP_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(1), + GlitchData => RXRUNDISP1_GlitchData, + OutSignalName => "RXRUNDISP(1)", + OutTemp => RXRUNDISP_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(2), + GlitchData => RXRUNDISP2_GlitchData, + OutSignalName => "RXRUNDISP(2)", + OutTemp => RXRUNDISP_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(3), + GlitchData => RXRUNDISP3_GlitchData, + OutSignalName => "RXRUNDISP(3)", + OutTemp => RXRUNDISP_OUT(3), + Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXBUFERR, + GlitchData => TXBUFERR_GlitchData, + OutSignalName => "TXBUFERR", + OutTemp => TXBUFERR_OUT, + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(0), + GlitchData => TXKERR0_GlitchData, + OutSignalName => "TXKERR(0)", + OutTemp => TXKERR_OUT(0), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(1), + GlitchData => TXKERR1_GlitchData, + OutSignalName => "TXKERR(1)", + OutTemp => TXKERR_OUT(1), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(2), + GlitchData => TXKERR2_GlitchData, + OutSignalName => "TXKERR(2)", + OutTemp => TXKERR_OUT(2), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(3), + GlitchData => TXKERR3_GlitchData, + OutSignalName => "TXKERR(3)", + OutTemp => TXKERR_OUT(3), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(0), + GlitchData => TXRUNDISP0_GlitchData, + OutSignalName => "TXRUNDISP(0)", + OutTemp => TXRUNDISP_OUT(0), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(1), + GlitchData => TXRUNDISP1_GlitchData, + OutSignalName => "TXRUNDISP(1)", + OutTemp => TXRUNDISP_OUT(1), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(2), + GlitchData => TXRUNDISP2_GlitchData, + OutSignalName => "TXRUNDISP(2)", + OutTemp => TXRUNDISP_OUT(2), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(3), + GlitchData => TXRUNDISP3_GlitchData, + OutSignalName => "TXRUNDISP(3)", + OutTemp => TXRUNDISP_OUT(3), + Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING + ); + +-- Wait signal (input/output pins) + wait on + CHBONDDONE_OUT, + CHBONDO_OUT, + CONFIGOUT_OUT, + RXBUFSTATUS_OUT, + RXCHARISCOMMA_OUT, + RXCHARISK_OUT, + RXCHECKINGCRC_OUT, + RXCLKCORCNT_OUT, + RXCOMMADET_OUT, + RXCRCERR_OUT, + RXDATA_OUT, + RXDISPERR_OUT, + RXLOSSOFSYNC_OUT, + RXNOTINTABLE_OUT, + RXREALIGN_OUT, +-- RXRECCLK_OUT, + RXRUNDISP_OUT, + TXBUFERR_OUT, + TXKERR_OUT, +-- TXN_OUT, +-- TXP_OUT, + TXRUNDISP_OUT, + BREFCLK_ipd, + BREFCLK2_ipd, + CHBONDI_ipd, + CONFIGENABLE_ipd, + CONFIGIN_ipd, + ENCHANSYNC_ipd, + ENMCOMMAALIGN_ipd, + ENPCOMMAALIGN_ipd, + LOOPBACK_ipd, + POWERDOWN_ipd, + REFCLK_ipd, + REFCLK2_ipd, + REFCLKSEL_ipd, + RXN_ipd, + RXP_ipd, + RXPOLARITY_ipd, + RXRESET_ipd, + RXUSRCLK_ipd, + RXUSRCLK2_ipd, + TXBYPASS8B10B_ipd, + TXCHARDISPMODE_ipd, + TXCHARDISPVAL_ipd, + TXCHARISK_ipd, + TXDATA_ipd, + TXFORCECRCERR_ipd, + TXINHIBIT_ipd, + TXPOLARITY_ipd, + TXRESET_ipd, + TXUSRCLK_ipd, + TXUSRCLK2_ipd; + + end process TIMING; + + TXN <= TXN_OUT; + TXP <= TXP_OUT; + RXRECCLK <= RXRECCLK_OUT; + +end GT_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_xaui_1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Gigabit Transceiver for XAUI I/O Standard 1 Byte Data +-- /___/ /\ Filename : GT_XAUI_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:11 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT_XAUI_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT_XAUI_1 is +generic ( + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + CRC_END_OF_PKT : string := "K29_7"; + CRC_FORMAT : string := "USER_MODE"; + CRC_START_OF_PKT : string := "K27_7"; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT_XAUI_1; + +-- Architecture body -- + +architecture GT_XAUI_1_V of GT_XAUI_1 is + +signal OPEN3 : std_logic_vector(2 downto 0); +signal OPEN24 : std_logic_vector(23 downto 0); +signal z3 : std_logic_vector(2 downto 0) := "000"; +signal z24 : std_logic_vector(23 downto 0) := "000000000000000000000000"; + +begin +-- GT Instatiation (port map, generic map) +GT_inst : GT + generic map ( + ALIGN_COMMA_MSB => FALSE, + CHAN_BOND_LIMIT => 16, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_OFFSET => 8, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00101111100", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_USE => FALSE, + CHAN_BOND_SEQ_LEN => 1, + CHAN_BOND_WAIT => 8, + CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, + CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, + CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, + CLK_COR_SEQ_1_1 => "00100011100", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_USE => FALSE, + CLK_COR_SEQ_LEN => 1, + CLK_CORRECT_USE => TRUE, + COMMA_10B_MASK => "1111111000", + CRC_END_OF_PKT => CRC_END_OF_PKT, + CRC_FORMAT => CRC_FORMAT, + CRC_START_OF_PKT => CRC_START_OF_PKT, + DEC_MCOMMA_DETECT => TRUE, + DEC_PCOMMA_DETECT => TRUE, + DEC_VALID_COMMA_ONLY => TRUE, + MCOMMA_10B_VALUE => "1100000000", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0011111000", + PCOMMA_DETECT => TRUE, + REF_CLK_V_SEL => REF_CLK_V_SEL, + RX_BUFFER_USE => TRUE, + RX_CRC_USE => RX_CRC_USE, + RX_DATA_WIDTH => 1, + RX_DECODE_USE => TRUE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SERDES_10B => SERDES_10B, + TERMINATION_IMP => TERMINATION_IMP, + TX_BUFFER_USE => TRUE, + TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, + TX_CRC_USE => TX_CRC_USE, + TX_DATA_WIDTH => 1, + TX_DIFF_CTRL => TX_DIFF_CTRL, + TX_PREEMPHASIS => TX_PREEMPHASIS +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + CONFIGOUT => CONFIGOUT, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(3 downto 1) => OPEN3, + RXCHARISK(0 downto 0) => RXCHARISK, + RXCHARISK(3 downto 1) => OPEN3, + RXCHECKINGCRC => RXCHECKINGCRC, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXCRCERR => RXCRCERR, + RXDATA(7 downto 0) => RXDATA, + RXDATA(31 downto 8) => OPEN24, + RXDISPERR(0 downto 0) => RXDISPERR, + RXDISPERR(3 downto 1) => OPEN3, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(3 downto 1) => OPEN3, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(0 downto 0) => RXRUNDISP, + RXRUNDISP(3 downto 1) => OPEN3, + TXBUFERR => TXBUFERR, + TXKERR(0 downto 0) => TXKERR, + TXKERR(3 downto 1) => OPEN3, + TXN => TXN, + TXP => TXP, + TXRUNDISP(0 downto 0) => TXRUNDISP, + TXRUNDISP(3 downto 1) => OPEN3, + BREFCLK => BREFCLK, + BREFCLK2 => BREFCLK2, + CHBONDI => CHBONDI, + CONFIGENABLE => CONFIGENABLE, + CONFIGIN => CONFIGIN, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKSEL => REFCLKSEL, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(3 downto 1) => z3, + TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(3 downto 1) => z3, + TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(3 downto 1) => z3, + TXCHARISK(0 downto 0) => TXCHARISK, + TXCHARISK(3 downto 1) => z3, + TXDATA(7 downto 0) => TXDATA, + TXDATA(31 downto 8) => z24, + TXFORCECRCERR => TXFORCECRCERR, + TXINHIBIT => TXINHIBIT, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT_XAUI_1_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_xaui_2.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Gigabit Transceiver for XAUI I/O Standard 2 Byte Data +-- /___/ /\ Filename : GT_XAUI_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:11 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT_XAUI_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT_XAUI_2 is +generic ( + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + CRC_END_OF_PKT : string := "K29_7"; + CRC_FORMAT : string := "USER_MODE"; + CRC_START_OF_PKT : string := "K27_7"; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT_XAUI_2; + +-- Architecture body -- + +architecture GT_XAUI_2_V of GT_XAUI_2 is + +signal OPEN2 : std_logic_vector(1 downto 0); +signal OPEN16 : std_logic_vector(15 downto 0); +signal z2 : std_logic_vector(1 downto 0) := "00"; +signal z16 : std_logic_vector(15 downto 0) := "0000000000000000"; + +begin +-- GT Instatiation (port map, generic map) +GT_inst : GT + generic map ( + ALIGN_COMMA_MSB => FALSE, + CHAN_BOND_LIMIT => 16, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_OFFSET => 8, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00101111100", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_USE => FALSE, + CHAN_BOND_SEQ_LEN => 1, + CHAN_BOND_WAIT => 8, + CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, + CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, + CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, + CLK_COR_SEQ_1_1 => "00100011100", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_USE => FALSE, + CLK_COR_SEQ_LEN => 1, + CLK_CORRECT_USE => TRUE, + COMMA_10B_MASK => "1111111000", + CRC_END_OF_PKT => CRC_END_OF_PKT, + CRC_FORMAT => CRC_FORMAT, + CRC_START_OF_PKT => CRC_START_OF_PKT, + DEC_MCOMMA_DETECT => TRUE, + DEC_PCOMMA_DETECT => TRUE, + DEC_VALID_COMMA_ONLY => TRUE, + MCOMMA_10B_VALUE => "1100000000", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0011111000", + PCOMMA_DETECT => TRUE, + REF_CLK_V_SEL => REF_CLK_V_SEL, + RX_BUFFER_USE => TRUE, + RX_CRC_USE => RX_CRC_USE, + RX_DATA_WIDTH => 2, + RX_DECODE_USE => TRUE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SERDES_10B => SERDES_10B, + TERMINATION_IMP => TERMINATION_IMP, + TX_BUFFER_USE => TRUE, + TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, + TX_CRC_USE => TX_CRC_USE, + TX_DATA_WIDTH => 2, + TX_DIFF_CTRL => TX_DIFF_CTRL, + TX_PREEMPHASIS => TX_PREEMPHASIS +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + CONFIGOUT => CONFIGOUT, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, + RXCHARISCOMMA(3 downto 2) => OPEN2, + RXCHARISK(1 downto 0) => RXCHARISK, + RXCHARISK(3 downto 2) => OPEN2, + RXCHECKINGCRC => RXCHECKINGCRC, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXCRCERR => RXCRCERR, + RXDATA(15 downto 0) => RXDATA, + RXDATA(31 downto 16) => OPEN16, + RXDISPERR(1 downto 0) => RXDISPERR, + RXDISPERR(3 downto 2) => OPEN2, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, + RXNOTINTABLE(3 downto 2) => OPEN2, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP(1 downto 0) => RXRUNDISP, + RXRUNDISP(3 downto 2) => OPEN2, + TXBUFERR => TXBUFERR, + TXKERR(1 downto 0) => TXKERR, + TXKERR(3 downto 2) => OPEN2, + TXN => TXN, + TXP => TXP, + TXRUNDISP(1 downto 0) => TXRUNDISP, + TXRUNDISP(3 downto 2) => OPEN2, + BREFCLK => BREFCLK, + BREFCLK2 => BREFCLK2, + CHBONDI => CHBONDI, + CONFIGENABLE => CONFIGENABLE, + CONFIGIN => CONFIGIN, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKSEL => REFCLKSEL, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, + TXBYPASS8B10B(3 downto 2) => z2, + TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, + TXCHARDISPMODE(3 downto 2) => z2, + TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, + TXCHARDISPVAL(3 downto 2) => z2, + TXCHARISK(1 downto 0) => TXCHARISK, + TXCHARISK(3 downto 2) => z2, + TXDATA(15 downto 0) => TXDATA, + TXDATA(31 downto 16) => z16, + TXFORCECRCERR => TXFORCECRCERR, + TXINHIBIT => TXINHIBIT, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT_XAUI_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_xaui_4.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Gigabit Transceiver for XAUI I/O Standard 4 Byte Data +-- /___/ /\ Filename : GT_XAUI_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:11 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT_XAUI_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT_XAUI_4 is +generic ( + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + CRC_END_OF_PKT : string := "K29_7"; + CRC_FORMAT : string := "USER_MODE"; + CRC_START_OF_PKT : string := "K27_7"; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + + + ); + +port ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT_XAUI_4; + +-- Architecture body -- + +architecture GT_XAUI_4_V of GT_XAUI_4 is + + +begin +-- GT Instatiation (port map, generic map) +GT_inst : GT + generic map ( + ALIGN_COMMA_MSB => FALSE, + CHAN_BOND_LIMIT => 16, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_OFFSET => 8, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_1_1 => "00101111100", + CHAN_BOND_SEQ_1_2 => "00000000000", + CHAN_BOND_SEQ_1_3 => "00000000000", + CHAN_BOND_SEQ_1_4 => "00000000000", + CHAN_BOND_SEQ_2_1 => "00000000000", + CHAN_BOND_SEQ_2_2 => "00000000000", + CHAN_BOND_SEQ_2_3 => "00000000000", + CHAN_BOND_SEQ_2_4 => "00000000000", + CHAN_BOND_SEQ_2_USE => FALSE, + CHAN_BOND_SEQ_LEN => 1, + CHAN_BOND_WAIT => 8, + CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, + CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, + CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, + CLK_COR_SEQ_1_1 => "00100011100", + CLK_COR_SEQ_1_2 => "00000000000", + CLK_COR_SEQ_1_3 => "00000000000", + CLK_COR_SEQ_1_4 => "00000000000", + CLK_COR_SEQ_2_1 => "00000000000", + CLK_COR_SEQ_2_2 => "00000000000", + CLK_COR_SEQ_2_3 => "00000000000", + CLK_COR_SEQ_2_4 => "00000000000", + CLK_COR_SEQ_2_USE => FALSE, + CLK_COR_SEQ_LEN => 1, + CLK_CORRECT_USE => TRUE, + COMMA_10B_MASK => "1111111000", + CRC_END_OF_PKT => CRC_END_OF_PKT, + CRC_FORMAT => CRC_FORMAT, + CRC_START_OF_PKT => CRC_START_OF_PKT, + DEC_MCOMMA_DETECT => TRUE, + DEC_PCOMMA_DETECT => TRUE, + DEC_VALID_COMMA_ONLY => TRUE, + MCOMMA_10B_VALUE => "1100000000", + MCOMMA_DETECT => TRUE, + PCOMMA_10B_VALUE => "0011111000", + PCOMMA_DETECT => TRUE, + REF_CLK_V_SEL => REF_CLK_V_SEL, + RX_BUFFER_USE => TRUE, + RX_CRC_USE => RX_CRC_USE, + RX_DATA_WIDTH => 4, + RX_DECODE_USE => TRUE, + RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, + RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, + RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, + SERDES_10B => SERDES_10B, + TERMINATION_IMP => TERMINATION_IMP, + TX_BUFFER_USE => TRUE, + TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, + TX_CRC_USE => TX_CRC_USE, + TX_DATA_WIDTH => 4, + TX_DIFF_CTRL => TX_DIFF_CTRL, + TX_PREEMPHASIS => TX_PREEMPHASIS +) +port map ( + CHBONDDONE => CHBONDDONE, + CHBONDO => CHBONDO, + CONFIGOUT => CONFIGOUT, + RXBUFSTATUS => RXBUFSTATUS, + RXCHARISCOMMA => RXCHARISCOMMA, + RXCHARISK => RXCHARISK, + RXCHECKINGCRC => RXCHECKINGCRC, + RXCLKCORCNT => RXCLKCORCNT, + RXCOMMADET => RXCOMMADET, + RXCRCERR => RXCRCERR, + RXDATA => RXDATA, + RXDISPERR => RXDISPERR, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE => RXNOTINTABLE, + RXREALIGN => RXREALIGN, + RXRECCLK => RXRECCLK, + RXRUNDISP => RXRUNDISP, + TXBUFERR => TXBUFERR, + TXKERR => TXKERR, + TXN => TXN, + TXP => TXP, + TXRUNDISP => TXRUNDISP, + BREFCLK => BREFCLK, + BREFCLK2 => BREFCLK2, + CHBONDI => CHBONDI, + CONFIGENABLE => CONFIGENABLE, + CONFIGIN => CONFIGIN, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + POWERDOWN => POWERDOWN, + REFCLK => REFCLK, + REFCLK2 => REFCLK2, + REFCLKSEL => REFCLKSEL, + RXN => RXN, + RXP => RXP, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B => TXBYPASS8B10B, + TXCHARDISPMODE => TXCHARDISPMODE, + TXCHARDISPVAL => TXCHARDISPVAL, + TXCHARISK => TXCHARISK, + TXDATA => TXDATA, + TXFORCECRCERR => TXFORCECRCERR, + TXINHIBIT => TXINHIBIT, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2 + +); + +end GT_XAUI_4_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/jtagppc.vhd,v 1.5 2004/09/09 23:33:00 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / JTAG Primitive for Power PC +-- /___/ /\ Filename : JTAGPPC.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:12 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL JTAGPPC ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity JTAGPPC is + port ( + TCK : out std_ulogic; + TDIPPC : out std_ulogic; + TMS : out std_ulogic; + + TDOPPC : in std_ulogic; + TDOTSPPC : in std_ulogic + ); +end JTAGPPC; + +architecture JTAGPPC_v of JTAGPPC is + begin + TCK <= '1'; + TDIPPC <= '1'; + TMS <= '1'; +end JTAGPPC_v; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/ppc405.vhd,v 1.9 2006/03/16 00:57:42 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Power PC Core +-- /___/ /\ Filename : PPC405.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:12 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FPGA_startup is + + port ( + bus_reset : out std_ulogic; + ghigh_b : out std_ulogic; + done : out std_ulogic; + gsr : out std_ulogic; + gwe : out std_ulogic; + gts_b : out std_ulogic; + + shutdown : in std_ulogic; + cclk : in std_ulogic; + por : in std_ulogic + ); +end FPGA_startup; + +architecture FPGA_startup_v of FPGA_startup is + signal count_changed : boolean := false; +begin +set_output:process(cclk, por) + variable abus_reset : std_ulogic := '0'; + variable aghigh_b : std_ulogic := '0'; + variable agsr : std_ulogic := '0'; + variable adone : std_ulogic := '0'; + variable agwe : std_ulogic := '0'; + variable agts_b : std_ulogic := '0'; + variable count : integer := 0; + variable count_last_value : integer := 0; + +begin + if (((cclk'event) and (cclk = '1') and (cclk'last_value = '0')) or ((por'event) and (por = '1') and (por'last_value = '0')))then + + count_last_value := count; + if (por = '1') then + count := 0; + elsif ((shutdown ='1') and (count > 0)) then + count := count - 1; + elsif ((shutdown ='0') and (count < 255)) then + count := count + 1; + end if; + if(count_last_value /= count) then + count_changed <= true; + end if; + + + if (por = '1') then + bus_reset <= '0'; + ghigh_b <= '0'; + gsr <= '0'; + done <= '0'; + gwe <= '0'; + gts_b <= '0'; + + else + + bus_reset <= abus_reset; + ghigh_b <= aghigh_b; + gsr <= agsr; + done <= adone; + gwe <= agwe; + gts_b <= agts_b; + + end if; + end if; + if(count_last_value /= count) then + abus_reset := '1'; + aghigh_b := '0'; + agsr := '0'; + adone := '0'; + agwe := '0'; + agts_b := '0'; + if (count >= 04) then + abus_reset := '0'; + end if; + if ((count = 33) or (count = 34)) then + agsr := '1'; + end if; + if (count > 38) then + aghigh_b := '1'; + end if; + if (count > 49) then + adone := '1'; + end if; + if (count > 50) then + agwe := '1'; + end if; + if (count > 51) then + agts_b := '1'; + end if; + end if; +end process set_output; + + +end FPGA_startup_v; +----- CELL PPC405 ----- +------------------------------------------------------------------------------- +-- Model for power pc (for simulation only) +------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity PPC405 is + +generic ( + + + + PPCUSER : std_logic_vector(0 to 3) := "0000" +) ; + port ( + C405CPMCORESLEEPREQ : out std_ulogic; + C405CPMMSRCE : out std_ulogic; + C405CPMMSREE : out std_ulogic; + C405CPMTIMERIRQ : out std_ulogic; + C405CPMTIMERRESETREQ : out std_ulogic; + C405DBGMSRWE : out std_ulogic; + C405DBGSTOPACK : out std_ulogic; + C405DBGWBCOMPLETE : out std_ulogic; + C405DBGWBFULL : out std_ulogic; + C405DBGWBIAR : out std_logic_vector(0 TO 29); + C405DCRABUS : out std_logic_vector(0 TO 9); + C405DCRDBUSOUT : out std_logic_vector(0 TO 31); + C405DCRREAD : out std_ulogic; + C405DCRWRITE : out std_ulogic; + C405JTGCAPTUREDR : out std_ulogic; + C405JTGEXTEST : out std_ulogic; + C405JTGPGMOUT : out std_ulogic; + C405JTGSHIFTDR : out std_ulogic; + C405JTGTDO : out std_ulogic; + C405JTGTDOEN : out std_ulogic; + C405JTGUPDATEDR : out std_ulogic; + C405PLBDCUABORT : out std_ulogic; + C405PLBDCUABUS : out std_logic_vector(0 TO 31); + C405PLBDCUBE : out std_logic_vector(0 TO 7); + C405PLBDCUCACHEABLE : out std_ulogic; + C405PLBDCUGUARDED : out std_ulogic; + C405PLBDCUPRIORITY : out std_logic_vector(0 TO 1); + C405PLBDCUREQUEST : out std_ulogic; + C405PLBDCURNW : out std_ulogic; + C405PLBDCUSIZE2 : out std_ulogic; + C405PLBDCUU0ATTR : out std_ulogic; + C405PLBDCUWRDBUS : out std_logic_vector(0 TO 63); + C405PLBDCUWRITETHRU : out std_ulogic; + C405PLBICUABORT : out std_ulogic; + C405PLBICUABUS : out std_logic_vector(0 TO 29); + C405PLBICUCACHEABLE : out std_ulogic; + C405PLBICUPRIORITY : out std_logic_vector(0 TO 1); + C405PLBICUREQUEST : out std_ulogic; + C405PLBICUSIZE : out std_logic_vector(2 TO 3); + C405PLBICUU0ATTR : out std_ulogic; + C405RSTCHIPRESETREQ : out std_ulogic; + C405RSTCORERESETREQ : out std_ulogic; + C405RSTSYSRESETREQ : out std_ulogic; + C405TRCCYCLE : out std_ulogic; + C405TRCEVENEXECUTIONSTATUS : out std_logic_vector(0 TO 1); + C405TRCODDEXECUTIONSTATUS : out std_logic_vector(0 TO 1); + C405TRCTRACESTATUS : out std_logic_vector(0 TO 3); + C405TRCTRIGGEREVENTOUT : out std_ulogic; + C405TRCTRIGGEREVENTTYPE : out std_logic_vector(0 TO 10); + C405XXXMACHINECHECK : out std_ulogic; + DSOCMBRAMABUS : out std_logic_vector(8 TO 29); + DSOCMBRAMBYTEWRITE : out std_logic_vector(0 TO 3); + DSOCMBRAMEN : out std_ulogic; + DSOCMBRAMWRDBUS : out std_logic_vector(0 TO 31); + DSOCMBUSY : out std_ulogic; + ISOCMBRAMEN : out std_ulogic; + ISOCMBRAMEVENWRITEEN : out std_ulogic; + ISOCMBRAMODDWRITEEN : out std_ulogic; + ISOCMBRAMRDABUS : out std_logic_vector(8 TO 28); + ISOCMBRAMWRABUS : out std_logic_vector(8 TO 28); + ISOCMBRAMWRDBUS : out std_logic_vector(0 TO 31); + + BRAMDSOCMCLK : in std_ulogic; + BRAMDSOCMRDDBUS : in std_logic_vector(0 TO 31); + BRAMISOCMCLK : in std_ulogic; + BRAMISOCMRDDBUS : in std_logic_vector(0 TO 63); + CPMC405CLOCK : in std_ulogic; + CPMC405CORECLKINACTIVE : in std_ulogic; + CPMC405CPUCLKEN : in std_ulogic; + CPMC405JTAGCLKEN : in std_ulogic; + CPMC405TIMERCLKEN : in std_ulogic; + CPMC405TIMERTICK : in std_ulogic; + DBGC405DEBUGHALT : in std_ulogic; + DBGC405EXTBUSHOLDACK : in std_ulogic; + DBGC405UNCONDDEBUGEVENT : in std_ulogic; + DCRC405ACK : in std_ulogic; + DCRC405DBUSIN : in std_logic_vector(0 TO 31); + DSARCVALUE : in std_logic_vector(0 TO 7); + DSCNTLVALUE : in std_logic_vector(0 TO 7); + EICC405CRITINPUTIRQ : in std_ulogic; + EICC405EXTINPUTIRQ : in std_ulogic; + ISARCVALUE : in std_logic_vector(0 TO 7); + ISCNTLVALUE : in std_logic_vector(0 TO 7); + JTGC405BNDSCANTDO : in std_ulogic; + JTGC405TCK : in std_ulogic; + JTGC405TDI : in std_ulogic; + JTGC405TMS : in std_ulogic; + JTGC405TRSTNEG : in std_ulogic; + MCBCPUCLKEN : in std_ulogic; + MCBJTAGEN : in std_ulogic; + MCBTIMEREN : in std_ulogic; + MCPPCRST : in std_ulogic; + PLBC405DCUADDRACK : in std_ulogic; + PLBC405DCUBUSY : in std_ulogic; + PLBC405DCUERR : in std_ulogic; + PLBC405DCURDDACK : in std_ulogic; + PLBC405DCURDDBUS : in std_logic_vector(0 TO 63); + PLBC405DCURDWDADDR : in std_logic_vector(1 TO 3); + PLBC405DCUSSIZE1 : in std_ulogic; + PLBC405DCUWRDACK : in std_ulogic; + PLBC405ICUADDRACK : in std_ulogic; + PLBC405ICUBUSY : in std_ulogic; + PLBC405ICUERR : in std_ulogic; + PLBC405ICURDDACK : in std_ulogic; + PLBC405ICURDDBUS : in std_logic_vector(0 TO 63); + PLBC405ICURDWDADDR : in std_logic_vector(1 TO 3); + PLBC405ICUSSIZE1 : in std_ulogic; + PLBCLK : in std_ulogic; + RSTC405RESETCHIP : in std_ulogic; + RSTC405RESETCORE : in std_ulogic; + RSTC405RESETSYS : in std_ulogic; + TIEC405DETERMINISTICMULT : in std_ulogic; + TIEC405DISOPERANDFWD : in std_ulogic; + TIEC405MMUEN : in std_ulogic; + TIEDSOCMDCRADDR : in std_logic_vector(0 TO 7); + TIEISOCMDCRADDR : in std_logic_vector(0 TO 7); + TRCC405TRACEDISABLE : in std_ulogic; + TRCC405TRIGGEREVENTIN : in std_ulogic +); +end PPC405; + +-- architecture body -- + + +architecture PPC405_v of PPC405 is + + component PPC405_SWIFT_BUS + port ( + BUS_CLK : in std_ulogic; + BUS_RESET : in std_ulogic; + GWE : in std_ulogic; + GHIGHB : in std_ulogic; + GSR : in std_ulogic; + CPMC405CPUCLKEN : in std_ulogic; + CPMC405JTAGCLKEN : in std_ulogic; + CPMC405TIMERCLKEN : in std_ulogic; + C405JTGPGMOUT : out std_ulogic; + MCBCPUCLKEN : in std_ulogic; + MCBJTAGEN : in std_ulogic; + MCBTIMEREN : in std_ulogic; + MCPPCRST : in std_ulogic; + C405TRCODDEXECUTIONSTATUS : out std_logic_vector(0 TO 1); + C405TRCEVENEXECUTIONSTATUS : out std_logic_vector(0 TO 1); + CPMC405CLOCK : in std_ulogic; + CPMC405CORECLKINACTIVE : in std_ulogic; + PLBCLK : in std_ulogic; + CPMC405TIMERTICK : in std_ulogic; + C405CPMMSREE : out std_ulogic; + C405CPMMSRCE : out std_ulogic; + C405CPMTIMERIRQ : out std_ulogic; + C405CPMTIMERRESETREQ : out std_ulogic; + C405CPMCORESLEEPREQ : out std_ulogic; + TIEC405DISOPERANDFWD : in std_ulogic; + TIEC405DETERMINISTICMULT : in std_ulogic; + TIEC405MMUEN : in std_ulogic; + TIEC405PVR : in std_logic_vector(28 TO 31); + C405XXXMACHINECHECK : out std_ulogic; + C405RSTCHIPRESETREQ : out std_ulogic; + C405RSTCORERESETREQ : out std_ulogic; + C405RSTSYSRESETREQ : out std_ulogic; + RSTC405RESETCHIP : in std_ulogic; + RSTC405RESETCORE : in std_ulogic; + RSTC405RESETSYS : in std_ulogic; + C405PLBICUREQUEST : out std_ulogic; + C405PLBICUPRIORITY : out std_logic_vector(0 TO 1); + C405PLBICUCACHEABLE : out std_ulogic; + C405PLBICUABUS : out std_logic_vector(0 TO 29); + C405PLBICUSIZE : out std_logic_vector(2 TO 3); + C405PLBICUABORT : out std_ulogic; + C405PLBICUU0ATTR : out std_ulogic; + PLBC405ICUADDRACK : in std_ulogic; + PLBC405ICUBUSY : in std_ulogic; + PLBC405ICUERR : in std_ulogic; + PLBC405ICURDDACK : in std_ulogic; + PLBC405ICURDDBUS : in std_logic_vector(0 TO 63); + PLBC405ICUSSIZE1 : in std_ulogic; + PLBC405ICURDWDADDR : in std_logic_vector(1 TO 3); + C405PLBDCUREQUEST : out std_ulogic; + C405PLBDCURNW : out std_ulogic; + C405PLBDCUABUS : out std_logic_vector(0 TO 31); + C405PLBDCUBE : out std_logic_vector(0 TO 7); + C405PLBDCUCACHEABLE : out std_ulogic; + C405PLBDCUGUARDED : out std_ulogic; + C405PLBDCUPRIORITY : out std_logic_vector(0 TO 1); + C405PLBDCUSIZE2 : out std_ulogic; + C405PLBDCUABORT : out std_ulogic; + C405PLBDCUWRDBUS : out std_logic_vector(0 TO 63); + C405PLBDCUU0ATTR : out std_ulogic; + C405PLBDCUWRITETHRU : out std_ulogic; + PLBC405DCUADDRACK : in std_ulogic; + PLBC405DCUBUSY : in std_ulogic; + PLBC405DCUERR : in std_ulogic; + PLBC405DCURDDACK : in std_ulogic; + PLBC405DCURDDBUS : in std_logic_vector(0 TO 63); + PLBC405DCURDWDADDR : in std_logic_vector(1 TO 3); + PLBC405DCUSSIZE1 : in std_ulogic; + PLBC405DCUWRDACK : in std_ulogic; + ISOCMBRAMRDABUS : out std_logic_vector(8 TO 28); + ISOCMBRAMWRABUS : out std_logic_vector(8 TO 28); + ISOCMBRAMEN : out std_ulogic; + ISOCMBRAMODDWRITEEN : out std_ulogic; + ISOCMBRAMEVENWRITEEN : out std_ulogic; + ISOCMBRAMWRDBUS : out std_logic_vector(0 TO 31); + BRAMISOCMRDDBUS : in std_logic_vector(0 TO 63); + TIEISOCMDCRADDR : in std_logic_vector(0 TO 7); + ISARCVALUE : in std_logic_vector(0 TO 7); + ISCNTLVALUE : in std_logic_vector(0 TO 7); + BRAMISOCMCLK : in std_ulogic; + DSOCMBRAMABUS : out std_logic_vector(8 TO 29); + DSOCMBRAMBYTEWRITE : out std_logic_vector(0 TO 3); + DSOCMBRAMEN : out std_ulogic; + DSOCMBRAMWRDBUS : out std_logic_vector(0 TO 31); + BRAMDSOCMRDDBUS : in std_logic_vector(0 TO 31); + DSOCMBUSY : out std_ulogic; + TIEDSOCMDCRADDR : in std_logic_vector(0 TO 7); + DSARCVALUE : in std_logic_vector(0 TO 7); + DSCNTLVALUE : in std_logic_vector(0 TO 7); + BRAMDSOCMCLK : in std_ulogic; + C405DCRREAD : out std_ulogic; + C405DCRWRITE : out std_ulogic; + C405DCRABUS : out std_logic_vector(0 TO 9); + C405DCRDBUSOUT : out std_logic_vector(0 TO 31); + DCRC405ACK : in std_ulogic; + DCRC405DBUSIN : in std_logic_vector(0 TO 31); + EICC405EXTINPUTIRQ : in std_ulogic; + EICC405CRITINPUTIRQ : in std_ulogic; + JTGC405BNDSCANTDO : in std_ulogic; + JTGC405TCK : in std_ulogic; + JTGC405TDI : in std_ulogic; + JTGC405TMS : in std_ulogic; + JTGC405TRSTNEG : in std_ulogic; + C405JTGTDO : out std_ulogic; + C405JTGTDOEN : out std_ulogic; + C405JTGEXTEST : out std_ulogic; + C405JTGCAPTUREDR : out std_ulogic; + C405JTGSHIFTDR : out std_ulogic; + C405JTGUPDATEDR : out std_ulogic; + DBGC405DEBUGHALT : in std_ulogic; + DBGC405UNCONDDEBUGEVENT : in std_ulogic; + DBGC405EXTBUSHOLDACK : in std_ulogic; + C405DBGMSRWE : out std_ulogic; + C405DBGSTOPACK : out std_ulogic; + C405DBGWBCOMPLETE : out std_ulogic; + C405DBGWBFULL : out std_ulogic; + C405DBGWBIAR : out std_logic_vector(0 TO 29); + C405TRCTRIGGEREVENTOUT : out std_ulogic; + C405TRCTRIGGEREVENTTYPE : out std_logic_vector(0 TO 10); + C405TRCCYCLE : out std_ulogic; + C405TRCTRACESTATUS : out std_logic_vector(0 TO 3); + TRCC405TRACEDISABLE : in std_ulogic; + TRCC405TRIGGEREVENTIN : in std_ulogic + ); + end component; +component FPGA_STARTUP + port ( + bus_reset : out std_ulogic; + ghigh_b : out std_ulogic; + done : out std_ulogic; + gsr : out std_ulogic; + gwe : out std_ulogic; + gts_b : out std_ulogic; + + shutdown : in std_ulogic; + cclk : in std_ulogic; + por : in std_ulogic + ); +end component; + + constant in_delay : time := 1 ps; + constant out_delay : VitalDelayType01 := (100 ps, 100 ps); + + signal TIEC405PVR_ipd : std_logic_vector(31 downto 28); + signal BRAMDSOCMCLK_ipd : std_ulogic; + signal BRAMDSOCMRDDBUS_ipd : std_logic_vector(0 TO 31); + signal BRAMISOCMCLK_ipd : std_ulogic; + signal BRAMISOCMRDDBUS_ipd : std_logic_vector(0 TO 63); + signal CPMC405CLOCK_ipd : std_ulogic; + signal CPMC405CORECLKINACTIVE_ipd : std_ulogic; + signal CPMC405CPUCLKEN_ipd : std_ulogic; + signal CPMC405JTAGCLKEN_ipd : std_ulogic; + signal CPMC405TIMERCLKEN_ipd : std_ulogic; + signal CPMC405TIMERTICK_ipd : std_ulogic; + signal DBGC405DEBUGHALT_ipd : std_ulogic; + signal DBGC405EXTBUSHOLDACK_ipd : std_ulogic; + signal DBGC405UNCONDDEBUGEVENT_ipd : std_ulogic; + signal DCRC405ACK_ipd : std_ulogic; + signal DCRC405DBUSIN_ipd : std_logic_vector(0 TO 31); + signal DSARCVALUE_ipd : std_logic_vector(0 TO 7); + signal DSCNTLVALUE_ipd : std_logic_vector(0 TO 7); + signal EICC405CRITINPUTIRQ_ipd : std_ulogic; + signal EICC405EXTINPUTIRQ_ipd : std_ulogic; + signal ISARCVALUE_ipd : std_logic_vector(0 TO 7); + signal ISCNTLVALUE_ipd : std_logic_vector(0 TO 7); + signal JTGC405BNDSCANTDO_ipd : std_ulogic; + signal JTGC405TCK_ipd : std_ulogic; + signal JTGC405TDI_ipd : std_ulogic; + signal JTGC405TMS_ipd : std_ulogic; + signal JTGC405TRSTNEG_ipd : std_ulogic; + signal MCBCPUCLKEN_ipd : std_ulogic; + signal MCBJTAGEN_ipd : std_ulogic; + signal MCBTIMEREN_ipd : std_ulogic; + signal MCPPCRST_ipd : std_ulogic; + signal PLBC405DCUADDRACK_ipd : std_ulogic; + signal PLBC405DCUBUSY_ipd : std_ulogic; + signal PLBC405DCUERR_ipd : std_ulogic; + signal PLBC405DCURDDACK_ipd : std_ulogic; + signal PLBC405DCURDDBUS_ipd : std_logic_vector(0 TO 63); + signal PLBC405DCURDWDADDR_ipd : std_logic_vector(1 TO 3); + signal PLBC405DCUSSIZE1_ipd : std_ulogic; + signal PLBC405DCUWRDACK_ipd : std_ulogic; + signal PLBC405ICUADDRACK_ipd : std_ulogic; + signal PLBC405ICUBUSY_ipd : std_ulogic; + signal PLBC405ICUERR_ipd : std_ulogic; + signal PLBC405ICURDDACK_ipd : std_ulogic; + signal PLBC405ICURDDBUS_ipd : std_logic_vector(0 TO 63); + signal PLBC405ICURDWDADDR_ipd : std_logic_vector(1 TO 3); + signal PLBC405ICUSSIZE1_ipd : std_ulogic; + signal PLBCLK_ipd : std_ulogic; + signal RSTC405RESETCHIP_ipd : std_ulogic; + signal RSTC405RESETCORE_ipd : std_ulogic; + signal RSTC405RESETSYS_ipd : std_ulogic; + signal TIEC405DETERMINISTICMULT_ipd : std_ulogic; + signal TIEC405DISOPERANDFWD_ipd : std_ulogic; + signal TIEC405MMUEN_ipd : std_ulogic; + signal TIEDSOCMDCRADDR_ipd : std_logic_vector(0 TO 7); + signal TIEISOCMDCRADDR_ipd : std_logic_vector(0 TO 7); + signal TRCC405TRACEDISABLE_ipd : std_ulogic; + signal TRCC405TRIGGEREVENTIN_ipd : std_ulogic; + + signal TIEC405PVR_ipd_1 : std_logic_vector(31 downto 28); + signal BRAMDSOCMCLK_ipd_1 : std_ulogic; + signal BRAMDSOCMRDDBUS_ipd_1 : std_logic_vector(0 TO 31); + signal BRAMISOCMCLK_ipd_1 : std_ulogic; + signal BRAMISOCMRDDBUS_ipd_1 : std_logic_vector(0 TO 63); + signal CPMC405CLOCK_ipd_1 : std_ulogic; + signal CPMC405CORECLKINACTIVE_ipd_1 : std_ulogic; + signal CPMC405CPUCLKEN_ipd_1 : std_ulogic; + signal CPMC405JTAGCLKEN_ipd_1 : std_ulogic; + signal CPMC405TIMERCLKEN_ipd_1 : std_ulogic; + signal CPMC405TIMERTICK_ipd_1 : std_ulogic; + signal DBGC405DEBUGHALT_ipd_1 : std_ulogic; + signal DBGC405EXTBUSHOLDACK_ipd_1 : std_ulogic; + signal DBGC405UNCONDDEBUGEVENT_ipd_1 : std_ulogic; + signal DCRC405ACK_ipd_1 : std_ulogic; + signal DCRC405DBUSIN_ipd_1 : std_logic_vector(0 TO 31); + signal DSARCVALUE_ipd_1 : std_logic_vector(0 TO 7); + signal DSCNTLVALUE_ipd_1 : std_logic_vector(0 TO 7); + signal EICC405CRITINPUTIRQ_ipd_1 : std_ulogic; + signal EICC405EXTINPUTIRQ_ipd_1 : std_ulogic; + signal ISARCVALUE_ipd_1 : std_logic_vector(0 TO 7); + signal ISCNTLVALUE_ipd_1 : std_logic_vector(0 TO 7); + signal JTGC405BNDSCANTDO_ipd_1 : std_ulogic; + signal JTGC405TCK_ipd_1 : std_ulogic; + signal JTGC405TDI_ipd_1 : std_ulogic; + signal JTGC405TMS_ipd_1 : std_ulogic; + signal JTGC405TRSTNEG_ipd_1 : std_ulogic; + signal MCBCPUCLKEN_ipd_1 : std_ulogic; + signal MCBJTAGEN_ipd_1 : std_ulogic; + signal MCBTIMEREN_ipd_1 : std_ulogic; + signal MCPPCRST_ipd_1 : std_ulogic; + signal PLBC405DCUADDRACK_ipd_1 : std_ulogic; + signal PLBC405DCUBUSY_ipd_1 : std_ulogic; + signal PLBC405DCUERR_ipd_1 : std_ulogic; + signal PLBC405DCURDDACK_ipd_1 : std_ulogic; + signal PLBC405DCURDDBUS_ipd_1 : std_logic_vector(0 TO 63); + signal PLBC405DCURDWDADDR_ipd_1 : std_logic_vector(1 TO 3); + signal PLBC405DCUSSIZE1_ipd_1 : std_ulogic; + signal PLBC405DCUWRDACK_ipd_1 : std_ulogic; + signal PLBC405ICUADDRACK_ipd_1 : std_ulogic; + signal PLBC405ICUBUSY_ipd_1 : std_ulogic; + signal PLBC405ICUERR_ipd_1 : std_ulogic; + signal PLBC405ICURDDACK_ipd_1 : std_ulogic; + signal PLBC405ICURDDBUS_ipd_1 : std_logic_vector(0 TO 63); + signal PLBC405ICURDWDADDR_ipd_1 : std_logic_vector(1 TO 3); + signal PLBC405ICUSSIZE1_ipd_1 : std_ulogic; + signal PLBCLK_ipd_1 : std_ulogic; + signal RSTC405RESETCHIP_ipd_1 : std_ulogic; + signal RSTC405RESETCORE_ipd_1 : std_ulogic; + signal RSTC405RESETSYS_ipd_1 : std_ulogic; + signal TIEC405DETERMINISTICMULT_ipd_1 : std_ulogic; + signal TIEC405DISOPERANDFWD_ipd_1 : std_ulogic; + signal TIEC405MMUEN_ipd_1 : std_ulogic; + signal TIEDSOCMDCRADDR_ipd_1 : std_logic_vector(0 TO 7); + signal TIEISOCMDCRADDR_ipd_1 : std_logic_vector(0 TO 7); + signal TRCC405TRACEDISABLE_ipd_1 : std_ulogic; + signal TRCC405TRIGGEREVENTIN_ipd_1 : std_ulogic; + + signal C405CPMCORESLEEPREQ_OUT : std_ulogic; + signal C405CPMMSRCE_OUT : std_ulogic; + signal C405CPMMSREE_OUT : std_ulogic; + signal C405CPMTIMERIRQ_OUT : std_ulogic; + signal C405CPMTIMERRESETREQ_OUT : std_ulogic; + signal C405DBGMSRWE_OUT : std_ulogic; + signal C405DBGSTOPACK_OUT : std_ulogic; + signal C405DBGWBCOMPLETE_OUT : std_ulogic; + signal C405DBGWBFULL_OUT : std_ulogic; + signal C405DBGWBIAR_OUT : std_logic_vector(0 TO 29); + signal C405DCRABUS_OUT : std_logic_vector(0 TO 9); + signal C405DCRDBUSOUT_OUT : std_logic_vector(0 TO 31); + signal C405DCRREAD_OUT : std_ulogic; + signal C405DCRWRITE_OUT : std_ulogic; + signal C405JTGCAPTUREDR_OUT : std_ulogic; + signal C405JTGEXTEST_OUT : std_ulogic; + signal C405JTGPGMOUT_OUT : std_ulogic; + signal C405JTGSHIFTDR_OUT : std_ulogic; + signal C405JTGTDO_OUT : std_ulogic; + signal C405JTGTDOEN_OUT : std_ulogic; + signal C405JTGUPDATEDR_OUT : std_ulogic; + signal C405PLBDCUABORT_OUT : std_ulogic; + signal C405PLBDCUABUS_OUT : std_logic_vector(0 TO 31); + signal C405PLBDCUBE_OUT : std_logic_vector(0 TO 7); + signal C405PLBDCUCACHEABLE_OUT : std_ulogic; + signal C405PLBDCUGUARDED_OUT : std_ulogic; + signal C405PLBDCUPRIORITY_OUT : std_logic_vector(0 TO 1); + signal C405PLBDCUREQUEST_OUT : std_ulogic; + signal C405PLBDCURNW_OUT : std_ulogic; + signal C405PLBDCUSIZE2_OUT : std_ulogic; + signal C405PLBDCUU0ATTR_OUT : std_ulogic; + signal C405PLBDCUWRDBUS_OUT : std_logic_vector(0 TO 63); + signal C405PLBDCUWRITETHRU_OUT : std_ulogic; + signal C405PLBICUABORT_OUT : std_ulogic; + signal C405PLBICUABUS_OUT : std_logic_vector(0 TO 29); + signal C405PLBICUCACHEABLE_OUT : std_ulogic; + signal C405PLBICUPRIORITY_OUT : std_logic_vector(0 TO 1); + signal C405PLBICUREQUEST_OUT : std_ulogic; + signal C405PLBICUSIZE_OUT : std_logic_vector(2 TO 3); + signal C405PLBICUU0ATTR_OUT : std_ulogic; + signal C405RSTCHIPRESETREQ_OUT : std_ulogic; + signal C405RSTCORERESETREQ_OUT : std_ulogic; + signal C405RSTSYSRESETREQ_OUT : std_ulogic; + signal C405TRCCYCLE_OUT : std_ulogic; + signal C405TRCEVENEXECUTIONSTATUS_OUT : std_logic_vector(0 TO 1); + signal C405TRCODDEXECUTIONSTATUS_OUT : std_logic_vector(0 TO 1); + signal C405TRCTRACESTATUS_OUT : std_logic_vector(0 TO 3); + signal C405TRCTRIGGEREVENTOUT_OUT : std_ulogic; + signal C405TRCTRIGGEREVENTTYPE_OUT : std_logic_vector(0 TO 10); + signal C405XXXMACHINECHECK_OUT : std_ulogic; + signal DSOCMBRAMABUS_OUT : std_logic_vector(8 TO 29); + signal DSOCMBRAMBYTEWRITE_OUT : std_logic_vector(0 TO 3); + signal DSOCMBRAMEN_OUT : std_ulogic; + signal DSOCMBRAMWRDBUS_OUT : std_logic_vector(0 TO 31); + signal DSOCMBUSY_OUT : std_ulogic; + signal ISOCMBRAMEN_OUT : std_ulogic; + signal ISOCMBRAMEVENWRITEEN_OUT : std_ulogic; + signal ISOCMBRAMODDWRITEEN_OUT : std_ulogic; + signal ISOCMBRAMRDABUS_OUT : std_logic_vector(8 TO 28); + signal ISOCMBRAMWRABUS_OUT : std_logic_vector(8 TO 28); + signal ISOCMBRAMWRDBUS_OUT : std_logic_vector(0 TO 31); + + + signal FPGA_CCLK : std_ulogic := '0'; + signal FPGA_POR : std_ulogic := '1'; + signal FPGA_BUS_RESET : std_ulogic := '0'; + signal FPGA_GWE : std_ulogic := '0'; + signal FPGA_GHIGHB : std_ulogic := '0'; + signal FPGA_GSR : std_ulogic := '0'; + signal GSR_OR : std_ulogic := '0'; + signal GSR : std_ulogic := '0'; + signal FPGA_SHUTDOWN : std_ulogic := '0'; + + signal FPGA_CCLK_delay : std_ulogic := '0'; + signal FPGA_BUS_RESET_delay : std_ulogic := '0'; + signal GSR_delay : std_ulogic := '0'; + signal FPGA_GWE_delay : std_ulogic := '0'; + signal FPGA_GHIGHB_delay : std_ulogic := '0'; + signal ppcuser_binary : std_logic_vector(0 to 3) := PPCUSER; + + + + +begin + + +BRAMDSOCMCLK_ipd <= BRAMDSOCMCLK after 0 ps; +BRAMDSOCMRDDBUS_ipd <= BRAMDSOCMRDDBUS after 0 ps; +BRAMISOCMCLK_ipd <= BRAMISOCMCLK after 0 ps; +BRAMISOCMRDDBUS_ipd <= BRAMISOCMRDDBUS after 0 ps; +CPMC405CLOCK_ipd <= CPMC405CLOCK after 0 ps; +CPMC405CORECLKINACTIVE_ipd <= CPMC405CORECLKINACTIVE after 0 ps; +CPMC405CPUCLKEN_ipd <= CPMC405CPUCLKEN after 0 ps; +CPMC405JTAGCLKEN_ipd <= CPMC405JTAGCLKEN after 0 ps; +CPMC405TIMERCLKEN_ipd <= CPMC405TIMERCLKEN after 0 ps; +CPMC405TIMERTICK_ipd <= CPMC405TIMERTICK after 0 ps; +DBGC405DEBUGHALT_ipd <= DBGC405DEBUGHALT after 0 ps; +DBGC405EXTBUSHOLDACK_ipd <= DBGC405EXTBUSHOLDACK after 0 ps; +DBGC405UNCONDDEBUGEVENT_ipd <= DBGC405UNCONDDEBUGEVENT after 0 ps; +DCRC405ACK_ipd <= DCRC405ACK after 0 ps; +DCRC405DBUSIN_ipd <= DCRC405DBUSIN after 0 ps; +DSARCVALUE_ipd <= DSARCVALUE after 0 ps; +DSCNTLVALUE_ipd <= DSCNTLVALUE after 0 ps; +EICC405CRITINPUTIRQ_ipd <= EICC405CRITINPUTIRQ after 0 ps; +EICC405EXTINPUTIRQ_ipd <= EICC405EXTINPUTIRQ after 0 ps; +ISARCVALUE_ipd <= ISARCVALUE after 0 ps; +ISCNTLVALUE_ipd <= ISCNTLVALUE after 0 ps; +JTGC405BNDSCANTDO_ipd <= JTGC405BNDSCANTDO after 0 ps; +JTGC405TCK_ipd <= JTGC405TCK after 0 ps; +JTGC405TDI_ipd <= JTGC405TDI after 0 ps; +JTGC405TMS_ipd <= JTGC405TMS after 0 ps; +JTGC405TRSTNEG_ipd <= JTGC405TRSTNEG after 0 ps; +MCBCPUCLKEN_ipd <= MCBCPUCLKEN after 0 ps; +MCBJTAGEN_ipd <= MCBJTAGEN after 0 ps; +MCBTIMEREN_ipd <= MCBTIMEREN after 0 ps; +MCPPCRST_ipd <= MCPPCRST after 0 ps; +PLBC405DCUADDRACK_ipd <= PLBC405DCUADDRACK after 0 ps; +PLBC405DCUBUSY_ipd <= PLBC405DCUBUSY after 0 ps; +PLBC405DCUERR_ipd <= PLBC405DCUERR after 0 ps; +PLBC405DCURDDACK_ipd <= PLBC405DCURDDACK after 0 ps; +PLBC405DCURDDBUS_ipd <= PLBC405DCURDDBUS after 0 ps; +PLBC405DCURDWDADDR_ipd <= PLBC405DCURDWDADDR after 0 ps; +PLBC405DCUSSIZE1_ipd <= PLBC405DCUSSIZE1 after 0 ps; +PLBC405DCUWRDACK_ipd <= PLBC405DCUWRDACK after 0 ps; +PLBC405ICUADDRACK_ipd <= PLBC405ICUADDRACK after 0 ps; +PLBC405ICUBUSY_ipd <= PLBC405ICUBUSY after 0 ps; +PLBC405ICUERR_ipd <= PLBC405ICUERR after 0 ps; +PLBC405ICURDDACK_ipd <= PLBC405ICURDDACK after 0 ps; +PLBC405ICURDDBUS_ipd <= PLBC405ICURDDBUS after 0 ps; +PLBC405ICURDWDADDR_ipd <= PLBC405ICURDWDADDR after 0 ps; +PLBC405ICUSSIZE1_ipd <= PLBC405ICUSSIZE1 after 0 ps; +PLBCLK_ipd <= PLBCLK after 0 ps; +RSTC405RESETCHIP_ipd <= RSTC405RESETCHIP after 0 ps; +RSTC405RESETCORE_ipd <= RSTC405RESETCORE after 0 ps; +RSTC405RESETSYS_ipd <= RSTC405RESETSYS after 0 ps; +TIEC405DETERMINISTICMULT_ipd <= TIEC405DETERMINISTICMULT after 0 ps; +TIEC405DISOPERANDFWD_ipd <= TIEC405DISOPERANDFWD after 0 ps; +TIEC405MMUEN_ipd <= TIEC405MMUEN after 0 ps; +TIEDSOCMDCRADDR_ipd <= TIEDSOCMDCRADDR after 0 ps; +TIEISOCMDCRADDR_ipd <= TIEISOCMDCRADDR after 0 ps; +TRCC405TRACEDISABLE_ipd <= TRCC405TRACEDISABLE after 0 ps; +TRCC405TRIGGEREVENTIN_ipd <= TRCC405TRIGGEREVENTIN after 0 ps; + +BRAMDSOCMCLK_ipd_1 <= BRAMDSOCMCLK_ipd after in_delay; +BRAMDSOCMRDDBUS_ipd_1 <= BRAMDSOCMRDDBUS_ipd after in_delay; +BRAMISOCMCLK_ipd_1 <= BRAMISOCMCLK_ipd after in_delay; +BRAMISOCMRDDBUS_ipd_1 <= BRAMISOCMRDDBUS_ipd after in_delay; +CPMC405CLOCK_ipd_1 <= CPMC405CLOCK_ipd after in_delay; +CPMC405CORECLKINACTIVE_ipd_1 <= CPMC405CORECLKINACTIVE_ipd after in_delay; +CPMC405CPUCLKEN_ipd_1 <= CPMC405CPUCLKEN_ipd after in_delay; +CPMC405JTAGCLKEN_ipd_1 <= CPMC405JTAGCLKEN_ipd after in_delay; +CPMC405TIMERCLKEN_ipd_1 <= CPMC405TIMERCLKEN_ipd after in_delay; +CPMC405TIMERTICK_ipd_1 <= CPMC405TIMERTICK_ipd after in_delay; +DBGC405DEBUGHALT_ipd_1 <= DBGC405DEBUGHALT_ipd after in_delay; +DBGC405EXTBUSHOLDACK_ipd_1 <= DBGC405EXTBUSHOLDACK_ipd after in_delay; +DBGC405UNCONDDEBUGEVENT_ipd_1 <= DBGC405UNCONDDEBUGEVENT_ipd after in_delay; +DCRC405ACK_ipd_1 <= DCRC405ACK_ipd after in_delay; +DCRC405DBUSIN_ipd_1 <= DCRC405DBUSIN_ipd after in_delay; +DSARCVALUE_ipd_1 <= DSARCVALUE_ipd after in_delay; +DSCNTLVALUE_ipd_1 <= DSCNTLVALUE_ipd after in_delay; +EICC405CRITINPUTIRQ_ipd_1 <= EICC405CRITINPUTIRQ_ipd after in_delay; +EICC405EXTINPUTIRQ_ipd_1 <= EICC405EXTINPUTIRQ_ipd after in_delay; +ISARCVALUE_ipd_1 <= ISARCVALUE_ipd after in_delay; +ISCNTLVALUE_ipd_1 <= ISCNTLVALUE_ipd after in_delay; +JTGC405BNDSCANTDO_ipd_1 <= JTGC405BNDSCANTDO_ipd after in_delay; +JTGC405TCK_ipd_1 <= JTGC405TCK_ipd after in_delay; +JTGC405TDI_ipd_1 <= JTGC405TDI_ipd after in_delay; +JTGC405TMS_ipd_1 <= JTGC405TMS_ipd after in_delay; +JTGC405TRSTNEG_ipd_1 <= JTGC405TRSTNEG_ipd after in_delay; +MCBCPUCLKEN_ipd_1 <= MCBCPUCLKEN_ipd after in_delay; +MCBJTAGEN_ipd_1 <= MCBJTAGEN_ipd after in_delay; +MCBTIMEREN_ipd_1 <= MCBTIMEREN_ipd after in_delay; +MCPPCRST_ipd_1 <= MCPPCRST_ipd after in_delay; +PLBC405DCUADDRACK_ipd_1 <= PLBC405DCUADDRACK_ipd after in_delay; +PLBC405DCUBUSY_ipd_1 <= PLBC405DCUBUSY_ipd after in_delay; +PLBC405DCUERR_ipd_1 <= PLBC405DCUERR_ipd after in_delay; +PLBC405DCURDDACK_ipd_1 <= PLBC405DCURDDACK_ipd after in_delay; +PLBC405DCURDDBUS_ipd_1 <= PLBC405DCURDDBUS_ipd after in_delay; +PLBC405DCURDWDADDR_ipd_1 <= PLBC405DCURDWDADDR_ipd after in_delay; +PLBC405DCUSSIZE1_ipd_1 <= PLBC405DCUSSIZE1_ipd after in_delay; +PLBC405DCUWRDACK_ipd_1 <= PLBC405DCUWRDACK_ipd after in_delay; +PLBC405ICUADDRACK_ipd_1 <= PLBC405ICUADDRACK_ipd after in_delay; +PLBC405ICUBUSY_ipd_1 <= PLBC405ICUBUSY_ipd after in_delay; +PLBC405ICUERR_ipd_1 <= PLBC405ICUERR_ipd after in_delay; +PLBC405ICURDDACK_ipd_1 <= PLBC405ICURDDACK_ipd after in_delay; +PLBC405ICURDDBUS_ipd_1 <= PLBC405ICURDDBUS_ipd after in_delay; +PLBC405ICURDWDADDR_ipd_1 <= PLBC405ICURDWDADDR_ipd after in_delay; +PLBC405ICUSSIZE1_ipd_1 <= PLBC405ICUSSIZE1_ipd after in_delay; +PLBCLK_ipd_1 <= PLBCLK_ipd after in_delay; +RSTC405RESETCHIP_ipd_1 <= RSTC405RESETCHIP_ipd after in_delay; +RSTC405RESETCORE_ipd_1 <= RSTC405RESETCORE_ipd after in_delay; +RSTC405RESETSYS_ipd_1 <= RSTC405RESETSYS_ipd after in_delay; +TIEC405DETERMINISTICMULT_ipd_1 <= TIEC405DETERMINISTICMULT_ipd after in_delay; +TIEC405DISOPERANDFWD_ipd_1 <= TIEC405DISOPERANDFWD_ipd after in_delay; +TIEC405MMUEN_ipd_1 <= TIEC405MMUEN_ipd after in_delay; +TIEDSOCMDCRADDR_ipd_1 <= TIEDSOCMDCRADDR_ipd after in_delay; +TIEISOCMDCRADDR_ipd_1 <= TIEISOCMDCRADDR_ipd after in_delay; +TRCC405TRACEDISABLE_ipd_1 <= TRCC405TRACEDISABLE_ipd after in_delay; +TRCC405TRIGGEREVENTIN_ipd_1 <= TRCC405TRIGGEREVENTIN_ipd after in_delay; + +IPPC405_SWIFT : PPC405_SWIFT_BUS + port map ( + BUS_CLK => FPGA_CCLK, + BUS_RESET => FPGA_BUS_RESET_delay, + GSR => GSR_delay , + GWE => FPGA_GWE_delay, + GHIGHB => FPGA_GHIGHB_delay, + CPMC405CPUCLKEN => CPMC405CPUCLKEN_ipd_1 , + CPMC405JTAGCLKEN => CPMC405JTAGCLKEN_ipd_1 , + CPMC405TIMERCLKEN => CPMC405TIMERCLKEN_ipd_1 , + C405JTGPGMOUT => C405JTGPGMOUT_OUT , + MCBCPUCLKEN => MCBCPUCLKEN_ipd_1 , + MCBJTAGEN => MCBJTAGEN_ipd_1 , + MCBTIMEREN => MCBTIMEREN_ipd_1 , + MCPPCRST => MCPPCRST_ipd_1 , + C405TRCODDEXECUTIONSTATUS => C405TRCODDEXECUTIONSTATUS_OUT , + C405TRCEVENEXECUTIONSTATUS => C405TRCEVENEXECUTIONSTATUS_OUT , + CPMC405CLOCK => CPMC405CLOCK , + CPMC405CORECLKINACTIVE => CPMC405CORECLKINACTIVE_ipd_1 , + PLBCLK => PLBCLK , + CPMC405TIMERTICK => CPMC405TIMERTICK_ipd_1 , + C405CPMMSREE => C405CPMMSREE_OUT , + C405CPMMSRCE => C405CPMMSRCE_OUT , + C405CPMTIMERIRQ => C405CPMTIMERIRQ_OUT , + C405CPMTIMERRESETREQ => C405CPMTIMERRESETREQ_OUT , + C405CPMCORESLEEPREQ => C405CPMCORESLEEPREQ_OUT , + TIEC405DISOPERANDFWD => TIEC405DISOPERANDFWD_ipd_1 , + TIEC405DETERMINISTICMULT => TIEC405DETERMINISTICMULT_ipd_1 , + TIEC405MMUEN => TIEC405MMUEN_ipd_1 , + TIEC405PVR => ppcuser_binary , + C405XXXMACHINECHECK => C405XXXMACHINECHECK_OUT , + C405RSTCHIPRESETREQ => C405RSTCHIPRESETREQ_OUT , + C405RSTCORERESETREQ => C405RSTCORERESETREQ_OUT , + C405RSTSYSRESETREQ => C405RSTSYSRESETREQ_OUT , + RSTC405RESETCHIP => RSTC405RESETCHIP_ipd_1 , + RSTC405RESETCORE => RSTC405RESETCORE_ipd_1 , + RSTC405RESETSYS => RSTC405RESETSYS_ipd_1 , + C405PLBICUREQUEST => C405PLBICUREQUEST_OUT , + C405PLBICUPRIORITY => C405PLBICUPRIORITY_OUT , + C405PLBICUCACHEABLE => C405PLBICUCACHEABLE_OUT , + C405PLBICUABUS => C405PLBICUABUS_OUT , + C405PLBICUSIZE => C405PLBICUSIZE_OUT , + C405PLBICUABORT => C405PLBICUABORT_OUT , + C405PLBICUU0ATTR => C405PLBICUU0ATTR_OUT , + PLBC405ICUADDRACK => PLBC405ICUADDRACK_ipd_1 , + PLBC405ICUBUSY => PLBC405ICUBUSY_ipd_1 , + PLBC405ICUERR => PLBC405ICUERR_ipd_1 , + PLBC405ICURDDACK => PLBC405ICURDDACK_ipd_1 , + PLBC405ICURDDBUS => PLBC405ICURDDBUS_ipd_1 , + PLBC405ICUSSIZE1 => PLBC405ICUSSIZE1_ipd_1 , + PLBC405ICURDWDADDR => PLBC405ICURDWDADDR_ipd_1 , + C405PLBDCUREQUEST => C405PLBDCUREQUEST_OUT , + C405PLBDCURNW => C405PLBDCURNW_OUT , + C405PLBDCUABUS => C405PLBDCUABUS_OUT , + C405PLBDCUBE => C405PLBDCUBE_OUT , + C405PLBDCUCACHEABLE => C405PLBDCUCACHEABLE_OUT , + C405PLBDCUGUARDED => C405PLBDCUGUARDED_OUT , + C405PLBDCUPRIORITY => C405PLBDCUPRIORITY_OUT , + C405PLBDCUSIZE2 => C405PLBDCUSIZE2_OUT , + C405PLBDCUABORT => C405PLBDCUABORT_OUT , + C405PLBDCUWRDBUS => C405PLBDCUWRDBUS_OUT , + C405PLBDCUU0ATTR => C405PLBDCUU0ATTR_OUT , + C405PLBDCUWRITETHRU => C405PLBDCUWRITETHRU_OUT , + PLBC405DCUADDRACK => PLBC405DCUADDRACK_ipd_1 , + PLBC405DCUBUSY => PLBC405DCUBUSY_ipd_1 , + PLBC405DCUERR => PLBC405DCUERR_ipd_1 , + PLBC405DCURDDACK => PLBC405DCURDDACK_ipd_1 , + PLBC405DCURDDBUS => PLBC405DCURDDBUS_ipd_1 , + PLBC405DCURDWDADDR => PLBC405DCURDWDADDR_ipd_1 , + PLBC405DCUSSIZE1 => PLBC405DCUSSIZE1_ipd_1 , + PLBC405DCUWRDACK => PLBC405DCUWRDACK_ipd_1 , + ISOCMBRAMRDABUS => ISOCMBRAMRDABUS_OUT , + ISOCMBRAMWRABUS => ISOCMBRAMWRABUS_OUT , + ISOCMBRAMEN => ISOCMBRAMEN_OUT , + ISOCMBRAMODDWRITEEN => ISOCMBRAMODDWRITEEN_OUT , + ISOCMBRAMEVENWRITEEN => ISOCMBRAMEVENWRITEEN_OUT , + ISOCMBRAMWRDBUS => ISOCMBRAMWRDBUS_OUT , + BRAMISOCMRDDBUS => BRAMISOCMRDDBUS_ipd_1 , + TIEISOCMDCRADDR => TIEISOCMDCRADDR_ipd_1 , + ISARCVALUE => ISARCVALUE_ipd_1 , + ISCNTLVALUE => ISCNTLVALUE_ipd_1 , + BRAMISOCMCLK => BRAMISOCMCLK , + DSOCMBRAMABUS => DSOCMBRAMABUS_OUT , + DSOCMBRAMBYTEWRITE => DSOCMBRAMBYTEWRITE_OUT , + DSOCMBRAMEN => DSOCMBRAMEN_OUT , + DSOCMBRAMWRDBUS => DSOCMBRAMWRDBUS_OUT , + BRAMDSOCMRDDBUS => BRAMDSOCMRDDBUS_ipd_1 , + DSOCMBUSY => DSOCMBUSY_OUT , + TIEDSOCMDCRADDR => TIEDSOCMDCRADDR_ipd_1 , + DSARCVALUE => DSARCVALUE_ipd_1 , + DSCNTLVALUE => DSCNTLVALUE_ipd_1 , + BRAMDSOCMCLK => BRAMDSOCMCLK , + C405DCRREAD => C405DCRREAD_OUT , + C405DCRWRITE => C405DCRWRITE_OUT , + C405DCRABUS => C405DCRABUS_OUT , + C405DCRDBUSOUT => C405DCRDBUSOUT_OUT , + DCRC405ACK => DCRC405ACK_ipd_1 , + DCRC405DBUSIN => DCRC405DBUSIN_ipd_1 , + EICC405EXTINPUTIRQ => EICC405EXTINPUTIRQ_ipd_1 , + EICC405CRITINPUTIRQ => EICC405CRITINPUTIRQ_ipd_1 , + JTGC405BNDSCANTDO => JTGC405BNDSCANTDO_ipd_1 , + JTGC405TCK => JTGC405TCK_ipd_1 , + JTGC405TDI => JTGC405TDI_ipd_1 , + JTGC405TMS => JTGC405TMS_ipd_1 , + JTGC405TRSTNEG => JTGC405TRSTNEG_ipd_1 , + C405JTGTDO => C405JTGTDO_OUT , + C405JTGTDOEN => C405JTGTDOEN_OUT , + C405JTGEXTEST => C405JTGEXTEST_OUT , + C405JTGCAPTUREDR => C405JTGCAPTUREDR_OUT , + C405JTGSHIFTDR => C405JTGSHIFTDR_OUT , + C405JTGUPDATEDR => C405JTGUPDATEDR_OUT , + DBGC405DEBUGHALT => DBGC405DEBUGHALT_ipd_1 , + DBGC405UNCONDDEBUGEVENT => DBGC405UNCONDDEBUGEVENT_ipd_1 , + DBGC405EXTBUSHOLDACK => DBGC405EXTBUSHOLDACK_ipd_1 , + C405DBGMSRWE => C405DBGMSRWE_OUT , + C405DBGSTOPACK => C405DBGSTOPACK_OUT , + C405DBGWBCOMPLETE => C405DBGWBCOMPLETE_OUT , + C405DBGWBFULL => C405DBGWBFULL_OUT , + C405DBGWBIAR => C405DBGWBIAR_OUT , + C405TRCTRIGGEREVENTOUT => C405TRCTRIGGEREVENTOUT_OUT , + C405TRCTRIGGEREVENTTYPE => C405TRCTRIGGEREVENTTYPE_OUT , + C405TRCCYCLE => C405TRCCYCLE_OUT , + C405TRCTRACESTATUS => C405TRCTRACESTATUS_OUT , + TRCC405TRACEDISABLE => TRCC405TRACEDISABLE_ipd_1 , + TRCC405TRIGGEREVENTIN => TRCC405TRIGGEREVENTIN_ipd_1 +); + + + + + FPGA_CCLK <= NOT(FPGA_CCLK) after 5000 ps; + FPGA_POR <= '0' after 100 ps; + GSR_OR <= FPGA_GSR or GSR; + + +start_blk : FPGA_startup + port map ( + bus_reset => FPGA_BUS_RESET, + ghigh_b => FPGA_GHIGHB, + gsr => FPGA_GSR, + gwe => FPGA_GWE, + shutdown => FPGA_SHUTDOWN, + + cclk => FPGA_CCLK, + por => FPGA_POR); + + + FPGA_BUS_RESET_delay <= FPGA_BUS_RESET after 10 ps ; + GSR_delay <= GSR_OR after 10 ps; + FPGA_GWE_delay <= FPGA_GWE after 10 ps; + FPGA_GHIGHB_delay <= FPGA_GHIGHB after 10 ps; + +TIMING : process + + +VARIABLE DSOCMBRAMABUS8_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS9_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS10_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS11_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS12_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS13_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS14_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS15_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS16_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS17_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS18_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS19_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS20_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS21_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS22_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS23_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS24_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS25_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS26_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS27_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS28_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMABUS29_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMBYTEWRITE0_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMBYTEWRITE1_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMBYTEWRITE2_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMBYTEWRITE3_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMEN_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS0_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS1_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS2_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS3_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS4_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS5_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS6_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS7_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS8_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS9_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS10_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS11_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS12_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS13_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS14_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS15_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS16_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS17_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS18_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS19_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS20_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS21_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS22_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS23_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS24_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS25_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS26_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS27_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS28_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS29_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS30_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBRAMWRDBUS31_GlitchData: VitalGlitchDataType; + +VARIABLE ISOCMBRAMEN_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMEVENWRITEEN_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMODDWRITEEN_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS8_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS9_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS10_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS11_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS12_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS13_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS14_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS15_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS16_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS17_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS18_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS19_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS20_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS21_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS22_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS23_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS24_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS25_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS26_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS27_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMRDABUS28_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS8_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS9_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS10_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS11_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS12_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS13_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS14_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS15_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS16_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS17_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS18_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS19_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS20_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS21_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS22_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS23_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS24_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS25_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS26_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS27_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRABUS28_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS0_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS1_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS2_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS3_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS4_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS5_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS6_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS7_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS8_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS9_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS10_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS11_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS12_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS13_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS14_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS15_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS16_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS17_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS18_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS19_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS20_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS21_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS22_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS23_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS24_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS25_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS26_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS27_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS28_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS29_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS30_GlitchData: VitalGlitchDataType; +VARIABLE ISOCMBRAMWRDBUS31_GlitchData: VitalGlitchDataType; + +VARIABLE C405CPMCORESLEEPREQ_GlitchData: VitalGlitchDataType; +VARIABLE C405CPMMSRCE_GlitchData: VitalGlitchDataType; +VARIABLE C405CPMMSREE_GlitchData: VitalGlitchDataType; +VARIABLE C405CPMTIMERIRQ_GlitchData: VitalGlitchDataType; +VARIABLE C405CPMTIMERRESETREQ_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGMSRWE_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGSTOPACK_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBCOMPLETE_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBFULL_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR0_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR1_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR2_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR3_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR4_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR5_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR6_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR7_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR8_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR9_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR10_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR11_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR12_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR13_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR14_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR15_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR16_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR17_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR18_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR19_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR20_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR21_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR22_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR23_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR24_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR25_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR26_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR27_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR28_GlitchData: VitalGlitchDataType; +VARIABLE C405DBGWBIAR29_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRABUS0_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRABUS1_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRABUS2_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRABUS3_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRABUS4_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRABUS5_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRABUS6_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRABUS7_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRABUS8_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRABUS9_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT0_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT1_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT2_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT3_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT4_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT5_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT6_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT7_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT8_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT9_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT10_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT11_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT12_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT13_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT14_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT15_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT16_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT17_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT18_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT19_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT20_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT21_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT22_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT23_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT24_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT25_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT26_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT27_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT28_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT29_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT30_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRDBUSOUT31_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRREAD_GlitchData: VitalGlitchDataType; +VARIABLE C405DCRWRITE_GlitchData: VitalGlitchDataType; +VARIABLE C405JTGPGMOUT_GlitchData: VitalGlitchDataType; +VARIABLE C405RSTCHIPRESETREQ_GlitchData: VitalGlitchDataType; +VARIABLE C405RSTCORERESETREQ_GlitchData: VitalGlitchDataType; +VARIABLE C405RSTSYSRESETREQ_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCCYCLE_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCEVENEXECUTIONSTATUS0_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCEVENEXECUTIONSTATUS1_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCODDEXECUTIONSTATUS0_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCODDEXECUTIONSTATUS1_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCTRACESTATUS0_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCTRACESTATUS1_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCTRACESTATUS2_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCTRACESTATUS3_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCTRIGGEREVENTOUT_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCTRIGGEREVENTTYPE0_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCTRIGGEREVENTTYPE1_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCTRIGGEREVENTTYPE2_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCTRIGGEREVENTTYPE3_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCTRIGGEREVENTTYPE4_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCTRIGGEREVENTTYPE5_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCTRIGGEREVENTTYPE6_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCTRIGGEREVENTTYPE7_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCTRIGGEREVENTTYPE8_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCTRIGGEREVENTTYPE9_GlitchData: VitalGlitchDataType; +VARIABLE C405TRCTRIGGEREVENTTYPE10_GlitchData: VitalGlitchDataType; +VARIABLE C405XXXMACHINECHECK_GlitchData: VitalGlitchDataType; +VARIABLE DSOCMBUSY_GlitchData: VitalGlitchDataType; + + +VARIABLE C405JTGCAPTUREDR_GlitchData: VitalGlitchDataType; +VARIABLE C405JTGEXTEST_GlitchData: VitalGlitchDataType; +VARIABLE C405JTGSHIFTDR_GlitchData: VitalGlitchDataType; +VARIABLE C405JTGTDO_GlitchData: VitalGlitchDataType; +VARIABLE C405JTGTDOEN_GlitchData: VitalGlitchDataType; +VARIABLE C405JTGUPDATEDR_GlitchData: VitalGlitchDataType; +VARIABLE Tviol_CPMC405CORECLKINACTIVE_jtgc405tck_posedge: STD_ULOGIC := '0'; +VARIABLE Tmkr_CPMC405CORECLKINACTIVE_jtgc405tck_posedge: VitalTimingDataType := VitalTimingDataInit; +VARIABLE Tviol_DBGC405EXTBUSHOLDACK_jtgc405tck_posedge: STD_ULOGIC := '0'; +VARIABLE Tmkr_DBGC405EXTBUSHOLDACK_jtgc405tck_posedge: VitalTimingDataType := VitalTimingDataInit; +VARIABLE Tviol_JTGC405BNDSCANTDO_jtgc405tck_posedge: STD_ULOGIC := '0'; +VARIABLE Tmkr_JTGC405BNDSCANTDO_jtgc405tck_posedge: VitalTimingDataType := VitalTimingDataInit; +VARIABLE Tviol_JTGC405TDI_jtgc405tck_posedge: STD_ULOGIC := '0'; +VARIABLE Tmkr_JTGC405TDI_jtgc405tck_posedge: VitalTimingDataType := VitalTimingDataInit; +VARIABLE Tviol_JTGC405TMS_jtgc405tck_posedge: STD_ULOGIC := '0'; +VARIABLE Tmkr_JTGC405TMS_jtgc405tck_posedge: VitalTimingDataType := VitalTimingDataInit; +VARIABLE C405PLBDCUABORT_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS0_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS1_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS2_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS3_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS4_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS5_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS6_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS7_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS8_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS9_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS10_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS11_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS12_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS13_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS14_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS15_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS16_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS17_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS18_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS19_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS20_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS21_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS22_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS23_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS24_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS25_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS26_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS27_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS28_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS29_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS30_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUABUS31_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUBE0_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUBE1_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUBE2_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUBE3_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUBE4_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUBE5_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUBE6_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUBE7_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUCACHEABLE_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUGUARDED_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUPRIORITY0_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUPRIORITY1_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUREQUEST_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCURNW_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUSIZE2_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUU0ATTR_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS0_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS1_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS2_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS3_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS4_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS5_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS6_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS7_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS8_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS9_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS10_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS11_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS12_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS13_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS14_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS15_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS16_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS17_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS18_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS19_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS20_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS21_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS22_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS23_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS24_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS25_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS26_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS27_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS28_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS29_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS30_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS31_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS32_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS33_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS34_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS35_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS36_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS37_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS38_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS39_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS40_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS41_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS42_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS43_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS44_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS45_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS46_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS47_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS48_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS49_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS50_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS51_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS52_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS53_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS54_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS55_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS56_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS57_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS58_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS59_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS60_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS61_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS62_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRDBUS63_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBDCUWRITETHRU_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABORT_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS0_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS1_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS2_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS3_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS4_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS5_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS6_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS7_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS8_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS9_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS10_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS11_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS12_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS13_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS14_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS15_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS16_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS17_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS18_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS19_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS20_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS21_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS22_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS23_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS24_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS25_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS26_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS27_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS28_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUABUS29_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUCACHEABLE_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUPRIORITY0_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUPRIORITY1_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUREQUEST_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUSIZE2_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUSIZE3_GlitchData: VitalGlitchDataType; +VARIABLE C405PLBICUU0ATTR_GlitchData: VitalGlitchDataType; + +begin + +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(8), + GlitchData => DSOCMBRAMABUS8_GlitchData, + OutSignalName => "DSOCMBRAMABUS(8)", + OutTemp => DSOCMBRAMABUS_OUT(8), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(9), + GlitchData => DSOCMBRAMABUS9_GlitchData, + OutSignalName => "DSOCMBRAMABUS(9)", + OutTemp => DSOCMBRAMABUS_OUT(9), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(10), + GlitchData => DSOCMBRAMABUS10_GlitchData, + OutSignalName => "DSOCMBRAMABUS(10)", + OutTemp => DSOCMBRAMABUS_OUT(10), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(11), + GlitchData => DSOCMBRAMABUS11_GlitchData, + OutSignalName => "DSOCMBRAMABUS(11)", + OutTemp => DSOCMBRAMABUS_OUT(11), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(12), + GlitchData => DSOCMBRAMABUS12_GlitchData, + OutSignalName => "DSOCMBRAMABUS(12)", + OutTemp => DSOCMBRAMABUS_OUT(12), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(13), + GlitchData => DSOCMBRAMABUS13_GlitchData, + OutSignalName => "DSOCMBRAMABUS(13)", + OutTemp => DSOCMBRAMABUS_OUT(13), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(14), + GlitchData => DSOCMBRAMABUS14_GlitchData, + OutSignalName => "DSOCMBRAMABUS(14)", + OutTemp => DSOCMBRAMABUS_OUT(14), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(15), + GlitchData => DSOCMBRAMABUS15_GlitchData, + OutSignalName => "DSOCMBRAMABUS(15)", + OutTemp => DSOCMBRAMABUS_OUT(15), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(16), + GlitchData => DSOCMBRAMABUS16_GlitchData, + OutSignalName => "DSOCMBRAMABUS(16)", + OutTemp => DSOCMBRAMABUS_OUT(16), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(17), + GlitchData => DSOCMBRAMABUS17_GlitchData, + OutSignalName => "DSOCMBRAMABUS(17)", + OutTemp => DSOCMBRAMABUS_OUT(17), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(18), + GlitchData => DSOCMBRAMABUS18_GlitchData, + OutSignalName => "DSOCMBRAMABUS(18)", + OutTemp => DSOCMBRAMABUS_OUT(18), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(19), + GlitchData => DSOCMBRAMABUS19_GlitchData, + OutSignalName => "DSOCMBRAMABUS(19)", + OutTemp => DSOCMBRAMABUS_OUT(19), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(20), + GlitchData => DSOCMBRAMABUS20_GlitchData, + OutSignalName => "DSOCMBRAMABUS(20)", + OutTemp => DSOCMBRAMABUS_OUT(20), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(21), + GlitchData => DSOCMBRAMABUS21_GlitchData, + OutSignalName => "DSOCMBRAMABUS(21)", + OutTemp => DSOCMBRAMABUS_OUT(21), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(22), + GlitchData => DSOCMBRAMABUS22_GlitchData, + OutSignalName => "DSOCMBRAMABUS(22)", + OutTemp => DSOCMBRAMABUS_OUT(22), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(23), + GlitchData => DSOCMBRAMABUS23_GlitchData, + OutSignalName => "DSOCMBRAMABUS(23)", + OutTemp => DSOCMBRAMABUS_OUT(23), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(24), + GlitchData => DSOCMBRAMABUS24_GlitchData, + OutSignalName => "DSOCMBRAMABUS(24)", + OutTemp => DSOCMBRAMABUS_OUT(24), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(25), + GlitchData => DSOCMBRAMABUS25_GlitchData, + OutSignalName => "DSOCMBRAMABUS(25)", + OutTemp => DSOCMBRAMABUS_OUT(25), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(26), + GlitchData => DSOCMBRAMABUS26_GlitchData, + OutSignalName => "DSOCMBRAMABUS(26)", + OutTemp => DSOCMBRAMABUS_OUT(26), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(27), + GlitchData => DSOCMBRAMABUS27_GlitchData, + OutSignalName => "DSOCMBRAMABUS(27)", + OutTemp => DSOCMBRAMABUS_OUT(27), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(28), + GlitchData => DSOCMBRAMABUS28_GlitchData, + OutSignalName => "DSOCMBRAMABUS(28)", + OutTemp => DSOCMBRAMABUS_OUT(28), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMABUS(29), + GlitchData => DSOCMBRAMABUS29_GlitchData, + OutSignalName => "DSOCMBRAMABUS(29)", + OutTemp => DSOCMBRAMABUS_OUT(29), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMBYTEWRITE(0), + GlitchData => DSOCMBRAMBYTEWRITE0_GlitchData, + OutSignalName => "DSOCMBRAMBYTEWRITE(0)", + OutTemp => DSOCMBRAMBYTEWRITE_OUT(0), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMBYTEWRITE(1), + GlitchData => DSOCMBRAMBYTEWRITE1_GlitchData, + OutSignalName => "DSOCMBRAMBYTEWRITE(1)", + OutTemp => DSOCMBRAMBYTEWRITE_OUT(1), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMBYTEWRITE(2), + GlitchData => DSOCMBRAMBYTEWRITE2_GlitchData, + OutSignalName => "DSOCMBRAMBYTEWRITE(2)", + OutTemp => DSOCMBRAMBYTEWRITE_OUT(2), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMBYTEWRITE(3), + GlitchData => DSOCMBRAMBYTEWRITE3_GlitchData, + OutSignalName => "DSOCMBRAMBYTEWRITE(3)", + OutTemp => DSOCMBRAMBYTEWRITE_OUT(3), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMEN, + GlitchData => DSOCMBRAMEN_GlitchData, + OutSignalName => "DSOCMBRAMEN", + OutTemp => DSOCMBRAMEN_OUT, + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(0), + GlitchData => DSOCMBRAMWRDBUS0_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(0)", + OutTemp => DSOCMBRAMWRDBUS_OUT(0), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(1), + GlitchData => DSOCMBRAMWRDBUS1_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(1)", + OutTemp => DSOCMBRAMWRDBUS_OUT(1), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(2), + GlitchData => DSOCMBRAMWRDBUS2_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(2)", + OutTemp => DSOCMBRAMWRDBUS_OUT(2), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(3), + GlitchData => DSOCMBRAMWRDBUS3_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(3)", + OutTemp => DSOCMBRAMWRDBUS_OUT(3), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(4), + GlitchData => DSOCMBRAMWRDBUS4_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(4)", + OutTemp => DSOCMBRAMWRDBUS_OUT(4), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(5), + GlitchData => DSOCMBRAMWRDBUS5_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(5)", + OutTemp => DSOCMBRAMWRDBUS_OUT(5), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(6), + GlitchData => DSOCMBRAMWRDBUS6_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(6)", + OutTemp => DSOCMBRAMWRDBUS_OUT(6), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(7), + GlitchData => DSOCMBRAMWRDBUS7_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(7)", + OutTemp => DSOCMBRAMWRDBUS_OUT(7), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(8), + GlitchData => DSOCMBRAMWRDBUS8_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(8)", + OutTemp => DSOCMBRAMWRDBUS_OUT(8), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(9), + GlitchData => DSOCMBRAMWRDBUS9_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(9)", + OutTemp => DSOCMBRAMWRDBUS_OUT(9), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(10), + GlitchData => DSOCMBRAMWRDBUS10_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(10)", + OutTemp => DSOCMBRAMWRDBUS_OUT(10), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(11), + GlitchData => DSOCMBRAMWRDBUS11_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(11)", + OutTemp => DSOCMBRAMWRDBUS_OUT(11), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(12), + GlitchData => DSOCMBRAMWRDBUS12_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(12)", + OutTemp => DSOCMBRAMWRDBUS_OUT(12), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(13), + GlitchData => DSOCMBRAMWRDBUS13_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(13)", + OutTemp => DSOCMBRAMWRDBUS_OUT(13), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(14), + GlitchData => DSOCMBRAMWRDBUS14_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(14)", + OutTemp => DSOCMBRAMWRDBUS_OUT(14), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(15), + GlitchData => DSOCMBRAMWRDBUS15_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(15)", + OutTemp => DSOCMBRAMWRDBUS_OUT(15), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(16), + GlitchData => DSOCMBRAMWRDBUS16_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(16)", + OutTemp => DSOCMBRAMWRDBUS_OUT(16), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(17), + GlitchData => DSOCMBRAMWRDBUS17_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(17)", + OutTemp => DSOCMBRAMWRDBUS_OUT(17), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(18), + GlitchData => DSOCMBRAMWRDBUS18_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(18)", + OutTemp => DSOCMBRAMWRDBUS_OUT(18), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(19), + GlitchData => DSOCMBRAMWRDBUS19_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(19)", + OutTemp => DSOCMBRAMWRDBUS_OUT(19), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(20), + GlitchData => DSOCMBRAMWRDBUS20_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(20)", + OutTemp => DSOCMBRAMWRDBUS_OUT(20), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(21), + GlitchData => DSOCMBRAMWRDBUS21_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(21)", + OutTemp => DSOCMBRAMWRDBUS_OUT(21), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(22), + GlitchData => DSOCMBRAMWRDBUS22_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(22)", + OutTemp => DSOCMBRAMWRDBUS_OUT(22), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(23), + GlitchData => DSOCMBRAMWRDBUS23_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(23)", + OutTemp => DSOCMBRAMWRDBUS_OUT(23), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(24), + GlitchData => DSOCMBRAMWRDBUS24_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(24)", + OutTemp => DSOCMBRAMWRDBUS_OUT(24), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(25), + GlitchData => DSOCMBRAMWRDBUS25_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(25)", + OutTemp => DSOCMBRAMWRDBUS_OUT(25), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(26), + GlitchData => DSOCMBRAMWRDBUS26_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(26)", + OutTemp => DSOCMBRAMWRDBUS_OUT(26), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(27), + GlitchData => DSOCMBRAMWRDBUS27_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(27)", + OutTemp => DSOCMBRAMWRDBUS_OUT(27), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(28), + GlitchData => DSOCMBRAMWRDBUS28_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(28)", + OutTemp => DSOCMBRAMWRDBUS_OUT(28), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(29), + GlitchData => DSOCMBRAMWRDBUS29_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(29)", + OutTemp => DSOCMBRAMWRDBUS_OUT(29), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(30), + GlitchData => DSOCMBRAMWRDBUS30_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(30)", + OutTemp => DSOCMBRAMWRDBUS_OUT(30), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBRAMWRDBUS(31), + GlitchData => DSOCMBRAMWRDBUS31_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(31)", + OutTemp => DSOCMBRAMWRDBUS_OUT(31), + Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMEN, + GlitchData => ISOCMBRAMEN_GlitchData, + OutSignalName => "ISOCMBRAMEN", + OutTemp => ISOCMBRAMEN_OUT, + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMEVENWRITEEN, + GlitchData => ISOCMBRAMEVENWRITEEN_GlitchData, + OutSignalName => "ISOCMBRAMEVENWRITEEN", + OutTemp => ISOCMBRAMEVENWRITEEN_OUT, + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMODDWRITEEN, + GlitchData => ISOCMBRAMODDWRITEEN_GlitchData, + OutSignalName => "ISOCMBRAMODDWRITEEN", + OutTemp => ISOCMBRAMODDWRITEEN_OUT, + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(8), + GlitchData => ISOCMBRAMRDABUS8_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(8)", + OutTemp => ISOCMBRAMRDABUS_OUT(8), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(9), + GlitchData => ISOCMBRAMRDABUS9_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(9)", + OutTemp => ISOCMBRAMRDABUS_OUT(9), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(10), + GlitchData => ISOCMBRAMRDABUS10_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(10)", + OutTemp => ISOCMBRAMRDABUS_OUT(10), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(11), + GlitchData => ISOCMBRAMRDABUS11_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(11)", + OutTemp => ISOCMBRAMRDABUS_OUT(11), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(12), + GlitchData => ISOCMBRAMRDABUS12_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(12)", + OutTemp => ISOCMBRAMRDABUS_OUT(12), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(13), + GlitchData => ISOCMBRAMRDABUS13_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(13)", + OutTemp => ISOCMBRAMRDABUS_OUT(13), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(14), + GlitchData => ISOCMBRAMRDABUS14_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(14)", + OutTemp => ISOCMBRAMRDABUS_OUT(14), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(15), + GlitchData => ISOCMBRAMRDABUS15_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(15)", + OutTemp => ISOCMBRAMRDABUS_OUT(15), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(16), + GlitchData => ISOCMBRAMRDABUS16_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(16)", + OutTemp => ISOCMBRAMRDABUS_OUT(16), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(17), + GlitchData => ISOCMBRAMRDABUS17_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(17)", + OutTemp => ISOCMBRAMRDABUS_OUT(17), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(18), + GlitchData => ISOCMBRAMRDABUS18_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(18)", + OutTemp => ISOCMBRAMRDABUS_OUT(18), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(19), + GlitchData => ISOCMBRAMRDABUS19_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(19)", + OutTemp => ISOCMBRAMRDABUS_OUT(19), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(20), + GlitchData => ISOCMBRAMRDABUS20_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(20)", + OutTemp => ISOCMBRAMRDABUS_OUT(20), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(21), + GlitchData => ISOCMBRAMRDABUS21_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(21)", + OutTemp => ISOCMBRAMRDABUS_OUT(21), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(22), + GlitchData => ISOCMBRAMRDABUS22_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(22)", + OutTemp => ISOCMBRAMRDABUS_OUT(22), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(23), + GlitchData => ISOCMBRAMRDABUS23_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(23)", + OutTemp => ISOCMBRAMRDABUS_OUT(23), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(24), + GlitchData => ISOCMBRAMRDABUS24_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(24)", + OutTemp => ISOCMBRAMRDABUS_OUT(24), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(25), + GlitchData => ISOCMBRAMRDABUS25_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(25)", + OutTemp => ISOCMBRAMRDABUS_OUT(25), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(26), + GlitchData => ISOCMBRAMRDABUS26_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(26)", + OutTemp => ISOCMBRAMRDABUS_OUT(26), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(27), + GlitchData => ISOCMBRAMRDABUS27_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(27)", + OutTemp => ISOCMBRAMRDABUS_OUT(27), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMRDABUS(28), + GlitchData => ISOCMBRAMRDABUS28_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(28)", + OutTemp => ISOCMBRAMRDABUS_OUT(28), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(8), + GlitchData => ISOCMBRAMWRABUS8_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(8)", + OutTemp => ISOCMBRAMWRABUS_OUT(8), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(9), + GlitchData => ISOCMBRAMWRABUS9_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(9)", + OutTemp => ISOCMBRAMWRABUS_OUT(9), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(10), + GlitchData => ISOCMBRAMWRABUS10_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(10)", + OutTemp => ISOCMBRAMWRABUS_OUT(10), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(11), + GlitchData => ISOCMBRAMWRABUS11_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(11)", + OutTemp => ISOCMBRAMWRABUS_OUT(11), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(12), + GlitchData => ISOCMBRAMWRABUS12_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(12)", + OutTemp => ISOCMBRAMWRABUS_OUT(12), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(13), + GlitchData => ISOCMBRAMWRABUS13_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(13)", + OutTemp => ISOCMBRAMWRABUS_OUT(13), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(14), + GlitchData => ISOCMBRAMWRABUS14_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(14)", + OutTemp => ISOCMBRAMWRABUS_OUT(14), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(15), + GlitchData => ISOCMBRAMWRABUS15_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(15)", + OutTemp => ISOCMBRAMWRABUS_OUT(15), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(16), + GlitchData => ISOCMBRAMWRABUS16_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(16)", + OutTemp => ISOCMBRAMWRABUS_OUT(16), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(17), + GlitchData => ISOCMBRAMWRABUS17_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(17)", + OutTemp => ISOCMBRAMWRABUS_OUT(17), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(18), + GlitchData => ISOCMBRAMWRABUS18_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(18)", + OutTemp => ISOCMBRAMWRABUS_OUT(18), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(19), + GlitchData => ISOCMBRAMWRABUS19_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(19)", + OutTemp => ISOCMBRAMWRABUS_OUT(19), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(20), + GlitchData => ISOCMBRAMWRABUS20_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(20)", + OutTemp => ISOCMBRAMWRABUS_OUT(20), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(21), + GlitchData => ISOCMBRAMWRABUS21_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(21)", + OutTemp => ISOCMBRAMWRABUS_OUT(21), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(22), + GlitchData => ISOCMBRAMWRABUS22_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(22)", + OutTemp => ISOCMBRAMWRABUS_OUT(22), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(23), + GlitchData => ISOCMBRAMWRABUS23_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(23)", + OutTemp => ISOCMBRAMWRABUS_OUT(23), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(24), + GlitchData => ISOCMBRAMWRABUS24_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(24)", + OutTemp => ISOCMBRAMWRABUS_OUT(24), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(25), + GlitchData => ISOCMBRAMWRABUS25_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(25)", + OutTemp => ISOCMBRAMWRABUS_OUT(25), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(26), + GlitchData => ISOCMBRAMWRABUS26_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(26)", + OutTemp => ISOCMBRAMWRABUS_OUT(26), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(27), + GlitchData => ISOCMBRAMWRABUS27_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(27)", + OutTemp => ISOCMBRAMWRABUS_OUT(27), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRABUS(28), + GlitchData => ISOCMBRAMWRABUS28_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(28)", + OutTemp => ISOCMBRAMWRABUS_OUT(28), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(0), + GlitchData => ISOCMBRAMWRDBUS0_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(0)", + OutTemp => ISOCMBRAMWRDBUS_OUT(0), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(1), + GlitchData => ISOCMBRAMWRDBUS1_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(1)", + OutTemp => ISOCMBRAMWRDBUS_OUT(1), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(2), + GlitchData => ISOCMBRAMWRDBUS2_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(2)", + OutTemp => ISOCMBRAMWRDBUS_OUT(2), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(3), + GlitchData => ISOCMBRAMWRDBUS3_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(3)", + OutTemp => ISOCMBRAMWRDBUS_OUT(3), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(4), + GlitchData => ISOCMBRAMWRDBUS4_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(4)", + OutTemp => ISOCMBRAMWRDBUS_OUT(4), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(5), + GlitchData => ISOCMBRAMWRDBUS5_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(5)", + OutTemp => ISOCMBRAMWRDBUS_OUT(5), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(6), + GlitchData => ISOCMBRAMWRDBUS6_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(6)", + OutTemp => ISOCMBRAMWRDBUS_OUT(6), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(7), + GlitchData => ISOCMBRAMWRDBUS7_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(7)", + OutTemp => ISOCMBRAMWRDBUS_OUT(7), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(8), + GlitchData => ISOCMBRAMWRDBUS8_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(8)", + OutTemp => ISOCMBRAMWRDBUS_OUT(8), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(9), + GlitchData => ISOCMBRAMWRDBUS9_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(9)", + OutTemp => ISOCMBRAMWRDBUS_OUT(9), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(10), + GlitchData => ISOCMBRAMWRDBUS10_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(10)", + OutTemp => ISOCMBRAMWRDBUS_OUT(10), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(11), + GlitchData => ISOCMBRAMWRDBUS11_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(11)", + OutTemp => ISOCMBRAMWRDBUS_OUT(11), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(12), + GlitchData => ISOCMBRAMWRDBUS12_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(12)", + OutTemp => ISOCMBRAMWRDBUS_OUT(12), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(13), + GlitchData => ISOCMBRAMWRDBUS13_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(13)", + OutTemp => ISOCMBRAMWRDBUS_OUT(13), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(14), + GlitchData => ISOCMBRAMWRDBUS14_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(14)", + OutTemp => ISOCMBRAMWRDBUS_OUT(14), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(15), + GlitchData => ISOCMBRAMWRDBUS15_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(15)", + OutTemp => ISOCMBRAMWRDBUS_OUT(15), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(16), + GlitchData => ISOCMBRAMWRDBUS16_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(16)", + OutTemp => ISOCMBRAMWRDBUS_OUT(16), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(17), + GlitchData => ISOCMBRAMWRDBUS17_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(17)", + OutTemp => ISOCMBRAMWRDBUS_OUT(17), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(18), + GlitchData => ISOCMBRAMWRDBUS18_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(18)", + OutTemp => ISOCMBRAMWRDBUS_OUT(18), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(19), + GlitchData => ISOCMBRAMWRDBUS19_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(19)", + OutTemp => ISOCMBRAMWRDBUS_OUT(19), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(20), + GlitchData => ISOCMBRAMWRDBUS20_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(20)", + OutTemp => ISOCMBRAMWRDBUS_OUT(20), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(21), + GlitchData => ISOCMBRAMWRDBUS21_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(21)", + OutTemp => ISOCMBRAMWRDBUS_OUT(21), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(22), + GlitchData => ISOCMBRAMWRDBUS22_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(22)", + OutTemp => ISOCMBRAMWRDBUS_OUT(22), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(23), + GlitchData => ISOCMBRAMWRDBUS23_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(23)", + OutTemp => ISOCMBRAMWRDBUS_OUT(23), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(24), + GlitchData => ISOCMBRAMWRDBUS24_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(24)", + OutTemp => ISOCMBRAMWRDBUS_OUT(24), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(25), + GlitchData => ISOCMBRAMWRDBUS25_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(25)", + OutTemp => ISOCMBRAMWRDBUS_OUT(25), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(26), + GlitchData => ISOCMBRAMWRDBUS26_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(26)", + OutTemp => ISOCMBRAMWRDBUS_OUT(26), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(27), + GlitchData => ISOCMBRAMWRDBUS27_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(27)", + OutTemp => ISOCMBRAMWRDBUS_OUT(27), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(28), + GlitchData => ISOCMBRAMWRDBUS28_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(28)", + OutTemp => ISOCMBRAMWRDBUS_OUT(28), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(29), + GlitchData => ISOCMBRAMWRDBUS29_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(29)", + OutTemp => ISOCMBRAMWRDBUS_OUT(29), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(30), + GlitchData => ISOCMBRAMWRDBUS30_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(30)", + OutTemp => ISOCMBRAMWRDBUS_OUT(30), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => ISOCMBRAMWRDBUS(31), + GlitchData => ISOCMBRAMWRDBUS31_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(31)", + OutTemp => ISOCMBRAMWRDBUS_OUT(31), + Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405CPMCORESLEEPREQ, + GlitchData => C405CPMCORESLEEPREQ_GlitchData, + OutSignalName => "C405CPMCORESLEEPREQ", + OutTemp => C405CPMCORESLEEPREQ_OUT, + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405CPMMSRCE, + GlitchData => C405CPMMSRCE_GlitchData, + OutSignalName => "C405CPMMSRCE", + OutTemp => C405CPMMSRCE_OUT, + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405CPMMSREE, + GlitchData => C405CPMMSREE_GlitchData, + OutSignalName => "C405CPMMSREE", + OutTemp => C405CPMMSREE_OUT, + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405CPMTIMERIRQ, + GlitchData => C405CPMTIMERIRQ_GlitchData, + OutSignalName => "C405CPMTIMERIRQ", + OutTemp => C405CPMTIMERIRQ_OUT, + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405CPMTIMERRESETREQ, + GlitchData => C405CPMTIMERRESETREQ_GlitchData, + OutSignalName => "C405CPMTIMERRESETREQ", + OutTemp => C405CPMTIMERRESETREQ_OUT, + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGMSRWE, + GlitchData => C405DBGMSRWE_GlitchData, + OutSignalName => "C405DBGMSRWE", + OutTemp => C405DBGMSRWE_OUT, + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGSTOPACK, + GlitchData => C405DBGSTOPACK_GlitchData, + OutSignalName => "C405DBGSTOPACK", + OutTemp => C405DBGSTOPACK_OUT, + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBCOMPLETE, + GlitchData => C405DBGWBCOMPLETE_GlitchData, + OutSignalName => "C405DBGWBCOMPLETE", + OutTemp => C405DBGWBCOMPLETE_OUT, + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBFULL, + GlitchData => C405DBGWBFULL_GlitchData, + OutSignalName => "C405DBGWBFULL", + OutTemp => C405DBGWBFULL_OUT, + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(0), + GlitchData => C405DBGWBIAR0_GlitchData, + OutSignalName => "C405DBGWBIAR(0)", + OutTemp => C405DBGWBIAR_OUT(0), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(1), + GlitchData => C405DBGWBIAR1_GlitchData, + OutSignalName => "C405DBGWBIAR(1)", + OutTemp => C405DBGWBIAR_OUT(1), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(2), + GlitchData => C405DBGWBIAR2_GlitchData, + OutSignalName => "C405DBGWBIAR(2)", + OutTemp => C405DBGWBIAR_OUT(2), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(3), + GlitchData => C405DBGWBIAR3_GlitchData, + OutSignalName => "C405DBGWBIAR(3)", + OutTemp => C405DBGWBIAR_OUT(3), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(4), + GlitchData => C405DBGWBIAR4_GlitchData, + OutSignalName => "C405DBGWBIAR(4)", + OutTemp => C405DBGWBIAR_OUT(4), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(5), + GlitchData => C405DBGWBIAR5_GlitchData, + OutSignalName => "C405DBGWBIAR(5)", + OutTemp => C405DBGWBIAR_OUT(5), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(6), + GlitchData => C405DBGWBIAR6_GlitchData, + OutSignalName => "C405DBGWBIAR(6)", + OutTemp => C405DBGWBIAR_OUT(6), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(7), + GlitchData => C405DBGWBIAR7_GlitchData, + OutSignalName => "C405DBGWBIAR(7)", + OutTemp => C405DBGWBIAR_OUT(7), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(8), + GlitchData => C405DBGWBIAR8_GlitchData, + OutSignalName => "C405DBGWBIAR(8)", + OutTemp => C405DBGWBIAR_OUT(8), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(9), + GlitchData => C405DBGWBIAR9_GlitchData, + OutSignalName => "C405DBGWBIAR(9)", + OutTemp => C405DBGWBIAR_OUT(9), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(10), + GlitchData => C405DBGWBIAR10_GlitchData, + OutSignalName => "C405DBGWBIAR(10)", + OutTemp => C405DBGWBIAR_OUT(10), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(11), + GlitchData => C405DBGWBIAR11_GlitchData, + OutSignalName => "C405DBGWBIAR(11)", + OutTemp => C405DBGWBIAR_OUT(11), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(12), + GlitchData => C405DBGWBIAR12_GlitchData, + OutSignalName => "C405DBGWBIAR(12)", + OutTemp => C405DBGWBIAR_OUT(12), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(13), + GlitchData => C405DBGWBIAR13_GlitchData, + OutSignalName => "C405DBGWBIAR(13)", + OutTemp => C405DBGWBIAR_OUT(13), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(14), + GlitchData => C405DBGWBIAR14_GlitchData, + OutSignalName => "C405DBGWBIAR(14)", + OutTemp => C405DBGWBIAR_OUT(14), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(15), + GlitchData => C405DBGWBIAR15_GlitchData, + OutSignalName => "C405DBGWBIAR(15)", + OutTemp => C405DBGWBIAR_OUT(15), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(16), + GlitchData => C405DBGWBIAR16_GlitchData, + OutSignalName => "C405DBGWBIAR(16)", + OutTemp => C405DBGWBIAR_OUT(16), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(17), + GlitchData => C405DBGWBIAR17_GlitchData, + OutSignalName => "C405DBGWBIAR(17)", + OutTemp => C405DBGWBIAR_OUT(17), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(18), + GlitchData => C405DBGWBIAR18_GlitchData, + OutSignalName => "C405DBGWBIAR(18)", + OutTemp => C405DBGWBIAR_OUT(18), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(19), + GlitchData => C405DBGWBIAR19_GlitchData, + OutSignalName => "C405DBGWBIAR(19)", + OutTemp => C405DBGWBIAR_OUT(19), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(20), + GlitchData => C405DBGWBIAR20_GlitchData, + OutSignalName => "C405DBGWBIAR(20)", + OutTemp => C405DBGWBIAR_OUT(20), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(21), + GlitchData => C405DBGWBIAR21_GlitchData, + OutSignalName => "C405DBGWBIAR(21)", + OutTemp => C405DBGWBIAR_OUT(21), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(22), + GlitchData => C405DBGWBIAR22_GlitchData, + OutSignalName => "C405DBGWBIAR(22)", + OutTemp => C405DBGWBIAR_OUT(22), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(23), + GlitchData => C405DBGWBIAR23_GlitchData, + OutSignalName => "C405DBGWBIAR(23)", + OutTemp => C405DBGWBIAR_OUT(23), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(24), + GlitchData => C405DBGWBIAR24_GlitchData, + OutSignalName => "C405DBGWBIAR(24)", + OutTemp => C405DBGWBIAR_OUT(24), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(25), + GlitchData => C405DBGWBIAR25_GlitchData, + OutSignalName => "C405DBGWBIAR(25)", + OutTemp => C405DBGWBIAR_OUT(25), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(26), + GlitchData => C405DBGWBIAR26_GlitchData, + OutSignalName => "C405DBGWBIAR(26)", + OutTemp => C405DBGWBIAR_OUT(26), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(27), + GlitchData => C405DBGWBIAR27_GlitchData, + OutSignalName => "C405DBGWBIAR(27)", + OutTemp => C405DBGWBIAR_OUT(27), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(28), + GlitchData => C405DBGWBIAR28_GlitchData, + OutSignalName => "C405DBGWBIAR(28)", + OutTemp => C405DBGWBIAR_OUT(28), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DBGWBIAR(29), + GlitchData => C405DBGWBIAR29_GlitchData, + OutSignalName => "C405DBGWBIAR(29)", + OutTemp => C405DBGWBIAR_OUT(29), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRABUS(0), + GlitchData => C405DCRABUS0_GlitchData, + OutSignalName => "C405DCRABUS(0)", + OutTemp => C405DCRABUS_OUT(0), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRABUS(1), + GlitchData => C405DCRABUS1_GlitchData, + OutSignalName => "C405DCRABUS(1)", + OutTemp => C405DCRABUS_OUT(1), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRABUS(2), + GlitchData => C405DCRABUS2_GlitchData, + OutSignalName => "C405DCRABUS(2)", + OutTemp => C405DCRABUS_OUT(2), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRABUS(3), + GlitchData => C405DCRABUS3_GlitchData, + OutSignalName => "C405DCRABUS(3)", + OutTemp => C405DCRABUS_OUT(3), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRABUS(4), + GlitchData => C405DCRABUS4_GlitchData, + OutSignalName => "C405DCRABUS(4)", + OutTemp => C405DCRABUS_OUT(4), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRABUS(5), + GlitchData => C405DCRABUS5_GlitchData, + OutSignalName => "C405DCRABUS(5)", + OutTemp => C405DCRABUS_OUT(5), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRABUS(6), + GlitchData => C405DCRABUS6_GlitchData, + OutSignalName => "C405DCRABUS(6)", + OutTemp => C405DCRABUS_OUT(6), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRABUS(7), + GlitchData => C405DCRABUS7_GlitchData, + OutSignalName => "C405DCRABUS(7)", + OutTemp => C405DCRABUS_OUT(7), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRABUS(8), + GlitchData => C405DCRABUS8_GlitchData, + OutSignalName => "C405DCRABUS(8)", + OutTemp => C405DCRABUS_OUT(8), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRABUS(9), + GlitchData => C405DCRABUS9_GlitchData, + OutSignalName => "C405DCRABUS(9)", + OutTemp => C405DCRABUS_OUT(9), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(0), + GlitchData => C405DCRDBUSOUT0_GlitchData, + OutSignalName => "C405DCRDBUSOUT(0)", + OutTemp => C405DCRDBUSOUT_OUT(0), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(1), + GlitchData => C405DCRDBUSOUT1_GlitchData, + OutSignalName => "C405DCRDBUSOUT(1)", + OutTemp => C405DCRDBUSOUT_OUT(1), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(2), + GlitchData => C405DCRDBUSOUT2_GlitchData, + OutSignalName => "C405DCRDBUSOUT(2)", + OutTemp => C405DCRDBUSOUT_OUT(2), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(3), + GlitchData => C405DCRDBUSOUT3_GlitchData, + OutSignalName => "C405DCRDBUSOUT(3)", + OutTemp => C405DCRDBUSOUT_OUT(3), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(4), + GlitchData => C405DCRDBUSOUT4_GlitchData, + OutSignalName => "C405DCRDBUSOUT(4)", + OutTemp => C405DCRDBUSOUT_OUT(4), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(5), + GlitchData => C405DCRDBUSOUT5_GlitchData, + OutSignalName => "C405DCRDBUSOUT(5)", + OutTemp => C405DCRDBUSOUT_OUT(5), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(6), + GlitchData => C405DCRDBUSOUT6_GlitchData, + OutSignalName => "C405DCRDBUSOUT(6)", + OutTemp => C405DCRDBUSOUT_OUT(6), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(7), + GlitchData => C405DCRDBUSOUT7_GlitchData, + OutSignalName => "C405DCRDBUSOUT(7)", + OutTemp => C405DCRDBUSOUT_OUT(7), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(8), + GlitchData => C405DCRDBUSOUT8_GlitchData, + OutSignalName => "C405DCRDBUSOUT(8)", + OutTemp => C405DCRDBUSOUT_OUT(8), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(9), + GlitchData => C405DCRDBUSOUT9_GlitchData, + OutSignalName => "C405DCRDBUSOUT(9)", + OutTemp => C405DCRDBUSOUT_OUT(9), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(10), + GlitchData => C405DCRDBUSOUT10_GlitchData, + OutSignalName => "C405DCRDBUSOUT(10)", + OutTemp => C405DCRDBUSOUT_OUT(10), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(11), + GlitchData => C405DCRDBUSOUT11_GlitchData, + OutSignalName => "C405DCRDBUSOUT(11)", + OutTemp => C405DCRDBUSOUT_OUT(11), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(12), + GlitchData => C405DCRDBUSOUT12_GlitchData, + OutSignalName => "C405DCRDBUSOUT(12)", + OutTemp => C405DCRDBUSOUT_OUT(12), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(13), + GlitchData => C405DCRDBUSOUT13_GlitchData, + OutSignalName => "C405DCRDBUSOUT(13)", + OutTemp => C405DCRDBUSOUT_OUT(13), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(14), + GlitchData => C405DCRDBUSOUT14_GlitchData, + OutSignalName => "C405DCRDBUSOUT(14)", + OutTemp => C405DCRDBUSOUT_OUT(14), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(15), + GlitchData => C405DCRDBUSOUT15_GlitchData, + OutSignalName => "C405DCRDBUSOUT(15)", + OutTemp => C405DCRDBUSOUT_OUT(15), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(16), + GlitchData => C405DCRDBUSOUT16_GlitchData, + OutSignalName => "C405DCRDBUSOUT(16)", + OutTemp => C405DCRDBUSOUT_OUT(16), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(17), + GlitchData => C405DCRDBUSOUT17_GlitchData, + OutSignalName => "C405DCRDBUSOUT(17)", + OutTemp => C405DCRDBUSOUT_OUT(17), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(18), + GlitchData => C405DCRDBUSOUT18_GlitchData, + OutSignalName => "C405DCRDBUSOUT(18)", + OutTemp => C405DCRDBUSOUT_OUT(18), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(19), + GlitchData => C405DCRDBUSOUT19_GlitchData, + OutSignalName => "C405DCRDBUSOUT(19)", + OutTemp => C405DCRDBUSOUT_OUT(19), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(20), + GlitchData => C405DCRDBUSOUT20_GlitchData, + OutSignalName => "C405DCRDBUSOUT(20)", + OutTemp => C405DCRDBUSOUT_OUT(20), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(21), + GlitchData => C405DCRDBUSOUT21_GlitchData, + OutSignalName => "C405DCRDBUSOUT(21)", + OutTemp => C405DCRDBUSOUT_OUT(21), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(22), + GlitchData => C405DCRDBUSOUT22_GlitchData, + OutSignalName => "C405DCRDBUSOUT(22)", + OutTemp => C405DCRDBUSOUT_OUT(22), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(23), + GlitchData => C405DCRDBUSOUT23_GlitchData, + OutSignalName => "C405DCRDBUSOUT(23)", + OutTemp => C405DCRDBUSOUT_OUT(23), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(24), + GlitchData => C405DCRDBUSOUT24_GlitchData, + OutSignalName => "C405DCRDBUSOUT(24)", + OutTemp => C405DCRDBUSOUT_OUT(24), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(25), + GlitchData => C405DCRDBUSOUT25_GlitchData, + OutSignalName => "C405DCRDBUSOUT(25)", + OutTemp => C405DCRDBUSOUT_OUT(25), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(26), + GlitchData => C405DCRDBUSOUT26_GlitchData, + OutSignalName => "C405DCRDBUSOUT(26)", + OutTemp => C405DCRDBUSOUT_OUT(26), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(27), + GlitchData => C405DCRDBUSOUT27_GlitchData, + OutSignalName => "C405DCRDBUSOUT(27)", + OutTemp => C405DCRDBUSOUT_OUT(27), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(28), + GlitchData => C405DCRDBUSOUT28_GlitchData, + OutSignalName => "C405DCRDBUSOUT(28)", + OutTemp => C405DCRDBUSOUT_OUT(28), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(29), + GlitchData => C405DCRDBUSOUT29_GlitchData, + OutSignalName => "C405DCRDBUSOUT(29)", + OutTemp => C405DCRDBUSOUT_OUT(29), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(30), + GlitchData => C405DCRDBUSOUT30_GlitchData, + OutSignalName => "C405DCRDBUSOUT(30)", + OutTemp => C405DCRDBUSOUT_OUT(30), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRDBUSOUT(31), + GlitchData => C405DCRDBUSOUT31_GlitchData, + OutSignalName => "C405DCRDBUSOUT(31)", + OutTemp => C405DCRDBUSOUT_OUT(31), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRREAD, + GlitchData => C405DCRREAD_GlitchData, + OutSignalName => "C405DCRREAD", + OutTemp => C405DCRREAD_OUT, + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405DCRWRITE, + GlitchData => C405DCRWRITE_GlitchData, + OutSignalName => "C405DCRWRITE", + OutTemp => C405DCRWRITE_OUT, + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405JTGPGMOUT, + GlitchData => C405JTGPGMOUT_GlitchData, + OutSignalName => "C405JTGPGMOUT", + OutTemp => C405JTGPGMOUT_OUT, + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405RSTCHIPRESETREQ, + GlitchData => C405RSTCHIPRESETREQ_GlitchData, + OutSignalName => "C405RSTCHIPRESETREQ", + OutTemp => C405RSTCHIPRESETREQ_OUT, + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405RSTCORERESETREQ, + GlitchData => C405RSTCORERESETREQ_GlitchData, + OutSignalName => "C405RSTCORERESETREQ", + OutTemp => C405RSTCORERESETREQ_OUT, + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405RSTSYSRESETREQ, + GlitchData => C405RSTSYSRESETREQ_GlitchData, + OutSignalName => "C405RSTSYSRESETREQ", + OutTemp => C405RSTSYSRESETREQ_OUT, + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCCYCLE, + GlitchData => C405TRCCYCLE_GlitchData, + OutSignalName => "C405TRCCYCLE", + OutTemp => C405TRCCYCLE_OUT, + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCEVENEXECUTIONSTATUS(0), + GlitchData => C405TRCEVENEXECUTIONSTATUS0_GlitchData, + OutSignalName => "C405TRCEVENEXECUTIONSTATUS(0)", + OutTemp => C405TRCEVENEXECUTIONSTATUS_OUT(0), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCEVENEXECUTIONSTATUS(1), + GlitchData => C405TRCEVENEXECUTIONSTATUS1_GlitchData, + OutSignalName => "C405TRCEVENEXECUTIONSTATUS(1)", + OutTemp => C405TRCEVENEXECUTIONSTATUS_OUT(1), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCODDEXECUTIONSTATUS(0), + GlitchData => C405TRCODDEXECUTIONSTATUS0_GlitchData, + OutSignalName => "C405TRCODDEXECUTIONSTATUS(0)", + OutTemp => C405TRCODDEXECUTIONSTATUS_OUT(0), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCODDEXECUTIONSTATUS(1), + GlitchData => C405TRCODDEXECUTIONSTATUS1_GlitchData, + OutSignalName => "C405TRCODDEXECUTIONSTATUS(1)", + OutTemp => C405TRCODDEXECUTIONSTATUS_OUT(1), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCTRACESTATUS(0), + GlitchData => C405TRCTRACESTATUS0_GlitchData, + OutSignalName => "C405TRCTRACESTATUS(0)", + OutTemp => C405TRCTRACESTATUS_OUT(0), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCTRACESTATUS(1), + GlitchData => C405TRCTRACESTATUS1_GlitchData, + OutSignalName => "C405TRCTRACESTATUS(1)", + OutTemp => C405TRCTRACESTATUS_OUT(1), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCTRACESTATUS(2), + GlitchData => C405TRCTRACESTATUS2_GlitchData, + OutSignalName => "C405TRCTRACESTATUS(2)", + OutTemp => C405TRCTRACESTATUS_OUT(2), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCTRACESTATUS(3), + GlitchData => C405TRCTRACESTATUS3_GlitchData, + OutSignalName => "C405TRCTRACESTATUS(3)", + OutTemp => C405TRCTRACESTATUS_OUT(3), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCTRIGGEREVENTOUT, + GlitchData => C405TRCTRIGGEREVENTOUT_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTOUT", + OutTemp => C405TRCTRIGGEREVENTOUT_OUT, + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCTRIGGEREVENTTYPE(0), + GlitchData => C405TRCTRIGGEREVENTTYPE0_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(0)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(0), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCTRIGGEREVENTTYPE(1), + GlitchData => C405TRCTRIGGEREVENTTYPE1_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(1)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(1), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCTRIGGEREVENTTYPE(2), + GlitchData => C405TRCTRIGGEREVENTTYPE2_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(2)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(2), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCTRIGGEREVENTTYPE(3), + GlitchData => C405TRCTRIGGEREVENTTYPE3_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(3)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(3), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCTRIGGEREVENTTYPE(4), + GlitchData => C405TRCTRIGGEREVENTTYPE4_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(4)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(4), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCTRIGGEREVENTTYPE(5), + GlitchData => C405TRCTRIGGEREVENTTYPE5_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(5)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(5), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCTRIGGEREVENTTYPE(6), + GlitchData => C405TRCTRIGGEREVENTTYPE6_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(6)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(6), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCTRIGGEREVENTTYPE(7), + GlitchData => C405TRCTRIGGEREVENTTYPE7_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(7)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(7), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCTRIGGEREVENTTYPE(8), + GlitchData => C405TRCTRIGGEREVENTTYPE8_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(8)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(8), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCTRIGGEREVENTTYPE(9), + GlitchData => C405TRCTRIGGEREVENTTYPE9_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(9)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(9), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405TRCTRIGGEREVENTTYPE(10), + GlitchData => C405TRCTRIGGEREVENTTYPE10_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(10)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(10), + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405XXXMACHINECHECK, + GlitchData => C405XXXMACHINECHECK_GlitchData, + OutSignalName => "C405XXXMACHINECHECK", + OutTemp => C405XXXMACHINECHECK_OUT, + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => DSOCMBUSY, + GlitchData => DSOCMBUSY_GlitchData, + OutSignalName => "DSOCMBUSY", + OutTemp => DSOCMBUSY_OUT, + Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405JTGCAPTUREDR, + GlitchData => C405JTGCAPTUREDR_GlitchData, + OutSignalName => "C405JTGCAPTUREDR", + OutTemp => C405JTGCAPTUREDR_OUT, + Paths => (0 => (jtgc405tck_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405JTGEXTEST, + GlitchData => C405JTGEXTEST_GlitchData, + OutSignalName => "C405JTGEXTEST", + OutTemp => C405JTGEXTEST_OUT, + Paths => (0 => (jtgc405tck_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405JTGSHIFTDR, + GlitchData => C405JTGSHIFTDR_GlitchData, + OutSignalName => "C405JTGSHIFTDR", + OutTemp => C405JTGSHIFTDR_OUT, + Paths => (0 => (jtgc405tck_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405JTGTDO, + GlitchData => C405JTGTDO_GlitchData, + OutSignalName => "C405JTGTDO", + OutTemp => C405JTGTDO_OUT, + Paths => (0 => (jtgc405tck_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405JTGTDOEN, + GlitchData => C405JTGTDOEN_GlitchData, + OutSignalName => "C405JTGTDOEN", + OutTemp => C405JTGTDOEN_OUT, + Paths => (0 => (jtgc405tck_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405JTGUPDATEDR, + GlitchData => C405JTGUPDATEDR_GlitchData, + OutSignalName => "C405JTGUPDATEDR", + OutTemp => C405JTGUPDATEDR_OUT, + Paths => (0 => (jtgc405tck_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABORT, + GlitchData => C405PLBDCUABORT_GlitchData, + OutSignalName => "C405PLBDCUABORT", + OutTemp => C405PLBDCUABORT_OUT, + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(0), + GlitchData => C405PLBDCUABUS0_GlitchData, + OutSignalName => "C405PLBDCUABUS(0)", + OutTemp => C405PLBDCUABUS_OUT(0), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(1), + GlitchData => C405PLBDCUABUS1_GlitchData, + OutSignalName => "C405PLBDCUABUS(1)", + OutTemp => C405PLBDCUABUS_OUT(1), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(2), + GlitchData => C405PLBDCUABUS2_GlitchData, + OutSignalName => "C405PLBDCUABUS(2)", + OutTemp => C405PLBDCUABUS_OUT(2), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(3), + GlitchData => C405PLBDCUABUS3_GlitchData, + OutSignalName => "C405PLBDCUABUS(3)", + OutTemp => C405PLBDCUABUS_OUT(3), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(4), + GlitchData => C405PLBDCUABUS4_GlitchData, + OutSignalName => "C405PLBDCUABUS(4)", + OutTemp => C405PLBDCUABUS_OUT(4), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(5), + GlitchData => C405PLBDCUABUS5_GlitchData, + OutSignalName => "C405PLBDCUABUS(5)", + OutTemp => C405PLBDCUABUS_OUT(5), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(6), + GlitchData => C405PLBDCUABUS6_GlitchData, + OutSignalName => "C405PLBDCUABUS(6)", + OutTemp => C405PLBDCUABUS_OUT(6), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(7), + GlitchData => C405PLBDCUABUS7_GlitchData, + OutSignalName => "C405PLBDCUABUS(7)", + OutTemp => C405PLBDCUABUS_OUT(7), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(8), + GlitchData => C405PLBDCUABUS8_GlitchData, + OutSignalName => "C405PLBDCUABUS(8)", + OutTemp => C405PLBDCUABUS_OUT(8), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(9), + GlitchData => C405PLBDCUABUS9_GlitchData, + OutSignalName => "C405PLBDCUABUS(9)", + OutTemp => C405PLBDCUABUS_OUT(9), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(10), + GlitchData => C405PLBDCUABUS10_GlitchData, + OutSignalName => "C405PLBDCUABUS(10)", + OutTemp => C405PLBDCUABUS_OUT(10), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(11), + GlitchData => C405PLBDCUABUS11_GlitchData, + OutSignalName => "C405PLBDCUABUS(11)", + OutTemp => C405PLBDCUABUS_OUT(11), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(12), + GlitchData => C405PLBDCUABUS12_GlitchData, + OutSignalName => "C405PLBDCUABUS(12)", + OutTemp => C405PLBDCUABUS_OUT(12), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(13), + GlitchData => C405PLBDCUABUS13_GlitchData, + OutSignalName => "C405PLBDCUABUS(13)", + OutTemp => C405PLBDCUABUS_OUT(13), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(14), + GlitchData => C405PLBDCUABUS14_GlitchData, + OutSignalName => "C405PLBDCUABUS(14)", + OutTemp => C405PLBDCUABUS_OUT(14), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(15), + GlitchData => C405PLBDCUABUS15_GlitchData, + OutSignalName => "C405PLBDCUABUS(15)", + OutTemp => C405PLBDCUABUS_OUT(15), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(16), + GlitchData => C405PLBDCUABUS16_GlitchData, + OutSignalName => "C405PLBDCUABUS(16)", + OutTemp => C405PLBDCUABUS_OUT(16), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(17), + GlitchData => C405PLBDCUABUS17_GlitchData, + OutSignalName => "C405PLBDCUABUS(17)", + OutTemp => C405PLBDCUABUS_OUT(17), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(18), + GlitchData => C405PLBDCUABUS18_GlitchData, + OutSignalName => "C405PLBDCUABUS(18)", + OutTemp => C405PLBDCUABUS_OUT(18), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(19), + GlitchData => C405PLBDCUABUS19_GlitchData, + OutSignalName => "C405PLBDCUABUS(19)", + OutTemp => C405PLBDCUABUS_OUT(19), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(20), + GlitchData => C405PLBDCUABUS20_GlitchData, + OutSignalName => "C405PLBDCUABUS(20)", + OutTemp => C405PLBDCUABUS_OUT(20), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(21), + GlitchData => C405PLBDCUABUS21_GlitchData, + OutSignalName => "C405PLBDCUABUS(21)", + OutTemp => C405PLBDCUABUS_OUT(21), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(22), + GlitchData => C405PLBDCUABUS22_GlitchData, + OutSignalName => "C405PLBDCUABUS(22)", + OutTemp => C405PLBDCUABUS_OUT(22), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(23), + GlitchData => C405PLBDCUABUS23_GlitchData, + OutSignalName => "C405PLBDCUABUS(23)", + OutTemp => C405PLBDCUABUS_OUT(23), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(24), + GlitchData => C405PLBDCUABUS24_GlitchData, + OutSignalName => "C405PLBDCUABUS(24)", + OutTemp => C405PLBDCUABUS_OUT(24), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(25), + GlitchData => C405PLBDCUABUS25_GlitchData, + OutSignalName => "C405PLBDCUABUS(25)", + OutTemp => C405PLBDCUABUS_OUT(25), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(26), + GlitchData => C405PLBDCUABUS26_GlitchData, + OutSignalName => "C405PLBDCUABUS(26)", + OutTemp => C405PLBDCUABUS_OUT(26), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(27), + GlitchData => C405PLBDCUABUS27_GlitchData, + OutSignalName => "C405PLBDCUABUS(27)", + OutTemp => C405PLBDCUABUS_OUT(27), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(28), + GlitchData => C405PLBDCUABUS28_GlitchData, + OutSignalName => "C405PLBDCUABUS(28)", + OutTemp => C405PLBDCUABUS_OUT(28), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(29), + GlitchData => C405PLBDCUABUS29_GlitchData, + OutSignalName => "C405PLBDCUABUS(29)", + OutTemp => C405PLBDCUABUS_OUT(29), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(30), + GlitchData => C405PLBDCUABUS30_GlitchData, + OutSignalName => "C405PLBDCUABUS(30)", + OutTemp => C405PLBDCUABUS_OUT(30), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUABUS(31), + GlitchData => C405PLBDCUABUS31_GlitchData, + OutSignalName => "C405PLBDCUABUS(31)", + OutTemp => C405PLBDCUABUS_OUT(31), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUBE(0), + GlitchData => C405PLBDCUBE0_GlitchData, + OutSignalName => "C405PLBDCUBE(0)", + OutTemp => C405PLBDCUBE_OUT(0), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUBE(1), + GlitchData => C405PLBDCUBE1_GlitchData, + OutSignalName => "C405PLBDCUBE(1)", + OutTemp => C405PLBDCUBE_OUT(1), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUBE(2), + GlitchData => C405PLBDCUBE2_GlitchData, + OutSignalName => "C405PLBDCUBE(2)", + OutTemp => C405PLBDCUBE_OUT(2), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUBE(3), + GlitchData => C405PLBDCUBE3_GlitchData, + OutSignalName => "C405PLBDCUBE(3)", + OutTemp => C405PLBDCUBE_OUT(3), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUBE(4), + GlitchData => C405PLBDCUBE4_GlitchData, + OutSignalName => "C405PLBDCUBE(4)", + OutTemp => C405PLBDCUBE_OUT(4), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUBE(5), + GlitchData => C405PLBDCUBE5_GlitchData, + OutSignalName => "C405PLBDCUBE(5)", + OutTemp => C405PLBDCUBE_OUT(5), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUBE(6), + GlitchData => C405PLBDCUBE6_GlitchData, + OutSignalName => "C405PLBDCUBE(6)", + OutTemp => C405PLBDCUBE_OUT(6), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUBE(7), + GlitchData => C405PLBDCUBE7_GlitchData, + OutSignalName => "C405PLBDCUBE(7)", + OutTemp => C405PLBDCUBE_OUT(7), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUCACHEABLE, + GlitchData => C405PLBDCUCACHEABLE_GlitchData, + OutSignalName => "C405PLBDCUCACHEABLE", + OutTemp => C405PLBDCUCACHEABLE_OUT, + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUGUARDED, + GlitchData => C405PLBDCUGUARDED_GlitchData, + OutSignalName => "C405PLBDCUGUARDED", + OutTemp => C405PLBDCUGUARDED_OUT, + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUPRIORITY(0), + GlitchData => C405PLBDCUPRIORITY0_GlitchData, + OutSignalName => "C405PLBDCUPRIORITY(0)", + OutTemp => C405PLBDCUPRIORITY_OUT(0), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUPRIORITY(1), + GlitchData => C405PLBDCUPRIORITY1_GlitchData, + OutSignalName => "C405PLBDCUPRIORITY(1)", + OutTemp => C405PLBDCUPRIORITY_OUT(1), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUREQUEST, + GlitchData => C405PLBDCUREQUEST_GlitchData, + OutSignalName => "C405PLBDCUREQUEST", + OutTemp => C405PLBDCUREQUEST_OUT, + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCURNW, + GlitchData => C405PLBDCURNW_GlitchData, + OutSignalName => "C405PLBDCURNW", + OutTemp => C405PLBDCURNW_OUT, + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUSIZE2, + GlitchData => C405PLBDCUSIZE2_GlitchData, + OutSignalName => "C405PLBDCUSIZE2", + OutTemp => C405PLBDCUSIZE2_OUT, + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUU0ATTR, + GlitchData => C405PLBDCUU0ATTR_GlitchData, + OutSignalName => "C405PLBDCUU0ATTR", + OutTemp => C405PLBDCUU0ATTR_OUT, + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(0), + GlitchData => C405PLBDCUWRDBUS0_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(0)", + OutTemp => C405PLBDCUWRDBUS_OUT(0), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(1), + GlitchData => C405PLBDCUWRDBUS1_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(1)", + OutTemp => C405PLBDCUWRDBUS_OUT(1), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(2), + GlitchData => C405PLBDCUWRDBUS2_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(2)", + OutTemp => C405PLBDCUWRDBUS_OUT(2), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(3), + GlitchData => C405PLBDCUWRDBUS3_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(3)", + OutTemp => C405PLBDCUWRDBUS_OUT(3), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(4), + GlitchData => C405PLBDCUWRDBUS4_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(4)", + OutTemp => C405PLBDCUWRDBUS_OUT(4), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(5), + GlitchData => C405PLBDCUWRDBUS5_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(5)", + OutTemp => C405PLBDCUWRDBUS_OUT(5), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(6), + GlitchData => C405PLBDCUWRDBUS6_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(6)", + OutTemp => C405PLBDCUWRDBUS_OUT(6), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(7), + GlitchData => C405PLBDCUWRDBUS7_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(7)", + OutTemp => C405PLBDCUWRDBUS_OUT(7), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(8), + GlitchData => C405PLBDCUWRDBUS8_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(8)", + OutTemp => C405PLBDCUWRDBUS_OUT(8), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(9), + GlitchData => C405PLBDCUWRDBUS9_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(9)", + OutTemp => C405PLBDCUWRDBUS_OUT(9), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(10), + GlitchData => C405PLBDCUWRDBUS10_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(10)", + OutTemp => C405PLBDCUWRDBUS_OUT(10), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(11), + GlitchData => C405PLBDCUWRDBUS11_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(11)", + OutTemp => C405PLBDCUWRDBUS_OUT(11), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(12), + GlitchData => C405PLBDCUWRDBUS12_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(12)", + OutTemp => C405PLBDCUWRDBUS_OUT(12), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(13), + GlitchData => C405PLBDCUWRDBUS13_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(13)", + OutTemp => C405PLBDCUWRDBUS_OUT(13), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(14), + GlitchData => C405PLBDCUWRDBUS14_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(14)", + OutTemp => C405PLBDCUWRDBUS_OUT(14), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(15), + GlitchData => C405PLBDCUWRDBUS15_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(15)", + OutTemp => C405PLBDCUWRDBUS_OUT(15), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(16), + GlitchData => C405PLBDCUWRDBUS16_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(16)", + OutTemp => C405PLBDCUWRDBUS_OUT(16), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(17), + GlitchData => C405PLBDCUWRDBUS17_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(17)", + OutTemp => C405PLBDCUWRDBUS_OUT(17), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(18), + GlitchData => C405PLBDCUWRDBUS18_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(18)", + OutTemp => C405PLBDCUWRDBUS_OUT(18), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(19), + GlitchData => C405PLBDCUWRDBUS19_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(19)", + OutTemp => C405PLBDCUWRDBUS_OUT(19), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(20), + GlitchData => C405PLBDCUWRDBUS20_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(20)", + OutTemp => C405PLBDCUWRDBUS_OUT(20), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(21), + GlitchData => C405PLBDCUWRDBUS21_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(21)", + OutTemp => C405PLBDCUWRDBUS_OUT(21), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(22), + GlitchData => C405PLBDCUWRDBUS22_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(22)", + OutTemp => C405PLBDCUWRDBUS_OUT(22), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(23), + GlitchData => C405PLBDCUWRDBUS23_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(23)", + OutTemp => C405PLBDCUWRDBUS_OUT(23), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(24), + GlitchData => C405PLBDCUWRDBUS24_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(24)", + OutTemp => C405PLBDCUWRDBUS_OUT(24), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(25), + GlitchData => C405PLBDCUWRDBUS25_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(25)", + OutTemp => C405PLBDCUWRDBUS_OUT(25), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(26), + GlitchData => C405PLBDCUWRDBUS26_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(26)", + OutTemp => C405PLBDCUWRDBUS_OUT(26), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(27), + GlitchData => C405PLBDCUWRDBUS27_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(27)", + OutTemp => C405PLBDCUWRDBUS_OUT(27), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(28), + GlitchData => C405PLBDCUWRDBUS28_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(28)", + OutTemp => C405PLBDCUWRDBUS_OUT(28), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(29), + GlitchData => C405PLBDCUWRDBUS29_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(29)", + OutTemp => C405PLBDCUWRDBUS_OUT(29), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(30), + GlitchData => C405PLBDCUWRDBUS30_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(30)", + OutTemp => C405PLBDCUWRDBUS_OUT(30), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(31), + GlitchData => C405PLBDCUWRDBUS31_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(31)", + OutTemp => C405PLBDCUWRDBUS_OUT(31), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(32), + GlitchData => C405PLBDCUWRDBUS32_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(32)", + OutTemp => C405PLBDCUWRDBUS_OUT(32), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(33), + GlitchData => C405PLBDCUWRDBUS33_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(33)", + OutTemp => C405PLBDCUWRDBUS_OUT(33), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(34), + GlitchData => C405PLBDCUWRDBUS34_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(34)", + OutTemp => C405PLBDCUWRDBUS_OUT(34), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(35), + GlitchData => C405PLBDCUWRDBUS35_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(35)", + OutTemp => C405PLBDCUWRDBUS_OUT(35), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(36), + GlitchData => C405PLBDCUWRDBUS36_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(36)", + OutTemp => C405PLBDCUWRDBUS_OUT(36), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(37), + GlitchData => C405PLBDCUWRDBUS37_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(37)", + OutTemp => C405PLBDCUWRDBUS_OUT(37), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(38), + GlitchData => C405PLBDCUWRDBUS38_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(38)", + OutTemp => C405PLBDCUWRDBUS_OUT(38), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(39), + GlitchData => C405PLBDCUWRDBUS39_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(39)", + OutTemp => C405PLBDCUWRDBUS_OUT(39), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(40), + GlitchData => C405PLBDCUWRDBUS40_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(40)", + OutTemp => C405PLBDCUWRDBUS_OUT(40), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(41), + GlitchData => C405PLBDCUWRDBUS41_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(41)", + OutTemp => C405PLBDCUWRDBUS_OUT(41), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(42), + GlitchData => C405PLBDCUWRDBUS42_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(42)", + OutTemp => C405PLBDCUWRDBUS_OUT(42), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(43), + GlitchData => C405PLBDCUWRDBUS43_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(43)", + OutTemp => C405PLBDCUWRDBUS_OUT(43), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(44), + GlitchData => C405PLBDCUWRDBUS44_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(44)", + OutTemp => C405PLBDCUWRDBUS_OUT(44), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(45), + GlitchData => C405PLBDCUWRDBUS45_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(45)", + OutTemp => C405PLBDCUWRDBUS_OUT(45), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(46), + GlitchData => C405PLBDCUWRDBUS46_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(46)", + OutTemp => C405PLBDCUWRDBUS_OUT(46), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(47), + GlitchData => C405PLBDCUWRDBUS47_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(47)", + OutTemp => C405PLBDCUWRDBUS_OUT(47), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(48), + GlitchData => C405PLBDCUWRDBUS48_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(48)", + OutTemp => C405PLBDCUWRDBUS_OUT(48), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(49), + GlitchData => C405PLBDCUWRDBUS49_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(49)", + OutTemp => C405PLBDCUWRDBUS_OUT(49), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(50), + GlitchData => C405PLBDCUWRDBUS50_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(50)", + OutTemp => C405PLBDCUWRDBUS_OUT(50), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(51), + GlitchData => C405PLBDCUWRDBUS51_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(51)", + OutTemp => C405PLBDCUWRDBUS_OUT(51), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(52), + GlitchData => C405PLBDCUWRDBUS52_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(52)", + OutTemp => C405PLBDCUWRDBUS_OUT(52), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(53), + GlitchData => C405PLBDCUWRDBUS53_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(53)", + OutTemp => C405PLBDCUWRDBUS_OUT(53), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(54), + GlitchData => C405PLBDCUWRDBUS54_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(54)", + OutTemp => C405PLBDCUWRDBUS_OUT(54), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(55), + GlitchData => C405PLBDCUWRDBUS55_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(55)", + OutTemp => C405PLBDCUWRDBUS_OUT(55), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(56), + GlitchData => C405PLBDCUWRDBUS56_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(56)", + OutTemp => C405PLBDCUWRDBUS_OUT(56), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(57), + GlitchData => C405PLBDCUWRDBUS57_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(57)", + OutTemp => C405PLBDCUWRDBUS_OUT(57), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(58), + GlitchData => C405PLBDCUWRDBUS58_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(58)", + OutTemp => C405PLBDCUWRDBUS_OUT(58), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(59), + GlitchData => C405PLBDCUWRDBUS59_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(59)", + OutTemp => C405PLBDCUWRDBUS_OUT(59), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(60), + GlitchData => C405PLBDCUWRDBUS60_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(60)", + OutTemp => C405PLBDCUWRDBUS_OUT(60), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(61), + GlitchData => C405PLBDCUWRDBUS61_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(61)", + OutTemp => C405PLBDCUWRDBUS_OUT(61), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(62), + GlitchData => C405PLBDCUWRDBUS62_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(62)", + OutTemp => C405PLBDCUWRDBUS_OUT(62), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRDBUS(63), + GlitchData => C405PLBDCUWRDBUS63_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(63)", + OutTemp => C405PLBDCUWRDBUS_OUT(63), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBDCUWRITETHRU, + GlitchData => C405PLBDCUWRITETHRU_GlitchData, + OutSignalName => "C405PLBDCUWRITETHRU", + OutTemp => C405PLBDCUWRITETHRU_OUT, + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABORT, + GlitchData => C405PLBICUABORT_GlitchData, + OutSignalName => "C405PLBICUABORT", + OutTemp => C405PLBICUABORT_OUT, + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(0), + GlitchData => C405PLBICUABUS0_GlitchData, + OutSignalName => "C405PLBICUABUS(0)", + OutTemp => C405PLBICUABUS_OUT(0), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(1), + GlitchData => C405PLBICUABUS1_GlitchData, + OutSignalName => "C405PLBICUABUS(1)", + OutTemp => C405PLBICUABUS_OUT(1), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(2), + GlitchData => C405PLBICUABUS2_GlitchData, + OutSignalName => "C405PLBICUABUS(2)", + OutTemp => C405PLBICUABUS_OUT(2), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(3), + GlitchData => C405PLBICUABUS3_GlitchData, + OutSignalName => "C405PLBICUABUS(3)", + OutTemp => C405PLBICUABUS_OUT(3), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(4), + GlitchData => C405PLBICUABUS4_GlitchData, + OutSignalName => "C405PLBICUABUS(4)", + OutTemp => C405PLBICUABUS_OUT(4), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(5), + GlitchData => C405PLBICUABUS5_GlitchData, + OutSignalName => "C405PLBICUABUS(5)", + OutTemp => C405PLBICUABUS_OUT(5), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(6), + GlitchData => C405PLBICUABUS6_GlitchData, + OutSignalName => "C405PLBICUABUS(6)", + OutTemp => C405PLBICUABUS_OUT(6), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(7), + GlitchData => C405PLBICUABUS7_GlitchData, + OutSignalName => "C405PLBICUABUS(7)", + OutTemp => C405PLBICUABUS_OUT(7), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(8), + GlitchData => C405PLBICUABUS8_GlitchData, + OutSignalName => "C405PLBICUABUS(8)", + OutTemp => C405PLBICUABUS_OUT(8), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(9), + GlitchData => C405PLBICUABUS9_GlitchData, + OutSignalName => "C405PLBICUABUS(9)", + OutTemp => C405PLBICUABUS_OUT(9), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(10), + GlitchData => C405PLBICUABUS10_GlitchData, + OutSignalName => "C405PLBICUABUS(10)", + OutTemp => C405PLBICUABUS_OUT(10), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(11), + GlitchData => C405PLBICUABUS11_GlitchData, + OutSignalName => "C405PLBICUABUS(11)", + OutTemp => C405PLBICUABUS_OUT(11), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(12), + GlitchData => C405PLBICUABUS12_GlitchData, + OutSignalName => "C405PLBICUABUS(12)", + OutTemp => C405PLBICUABUS_OUT(12), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(13), + GlitchData => C405PLBICUABUS13_GlitchData, + OutSignalName => "C405PLBICUABUS(13)", + OutTemp => C405PLBICUABUS_OUT(13), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(14), + GlitchData => C405PLBICUABUS14_GlitchData, + OutSignalName => "C405PLBICUABUS(14)", + OutTemp => C405PLBICUABUS_OUT(14), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(15), + GlitchData => C405PLBICUABUS15_GlitchData, + OutSignalName => "C405PLBICUABUS(15)", + OutTemp => C405PLBICUABUS_OUT(15), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(16), + GlitchData => C405PLBICUABUS16_GlitchData, + OutSignalName => "C405PLBICUABUS(16)", + OutTemp => C405PLBICUABUS_OUT(16), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(17), + GlitchData => C405PLBICUABUS17_GlitchData, + OutSignalName => "C405PLBICUABUS(17)", + OutTemp => C405PLBICUABUS_OUT(17), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(18), + GlitchData => C405PLBICUABUS18_GlitchData, + OutSignalName => "C405PLBICUABUS(18)", + OutTemp => C405PLBICUABUS_OUT(18), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(19), + GlitchData => C405PLBICUABUS19_GlitchData, + OutSignalName => "C405PLBICUABUS(19)", + OutTemp => C405PLBICUABUS_OUT(19), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(20), + GlitchData => C405PLBICUABUS20_GlitchData, + OutSignalName => "C405PLBICUABUS(20)", + OutTemp => C405PLBICUABUS_OUT(20), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(21), + GlitchData => C405PLBICUABUS21_GlitchData, + OutSignalName => "C405PLBICUABUS(21)", + OutTemp => C405PLBICUABUS_OUT(21), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(22), + GlitchData => C405PLBICUABUS22_GlitchData, + OutSignalName => "C405PLBICUABUS(22)", + OutTemp => C405PLBICUABUS_OUT(22), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(23), + GlitchData => C405PLBICUABUS23_GlitchData, + OutSignalName => "C405PLBICUABUS(23)", + OutTemp => C405PLBICUABUS_OUT(23), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(24), + GlitchData => C405PLBICUABUS24_GlitchData, + OutSignalName => "C405PLBICUABUS(24)", + OutTemp => C405PLBICUABUS_OUT(24), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(25), + GlitchData => C405PLBICUABUS25_GlitchData, + OutSignalName => "C405PLBICUABUS(25)", + OutTemp => C405PLBICUABUS_OUT(25), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(26), + GlitchData => C405PLBICUABUS26_GlitchData, + OutSignalName => "C405PLBICUABUS(26)", + OutTemp => C405PLBICUABUS_OUT(26), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(27), + GlitchData => C405PLBICUABUS27_GlitchData, + OutSignalName => "C405PLBICUABUS(27)", + OutTemp => C405PLBICUABUS_OUT(27), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(28), + GlitchData => C405PLBICUABUS28_GlitchData, + OutSignalName => "C405PLBICUABUS(28)", + OutTemp => C405PLBICUABUS_OUT(28), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUABUS(29), + GlitchData => C405PLBICUABUS29_GlitchData, + OutSignalName => "C405PLBICUABUS(29)", + OutTemp => C405PLBICUABUS_OUT(29), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUCACHEABLE, + GlitchData => C405PLBICUCACHEABLE_GlitchData, + OutSignalName => "C405PLBICUCACHEABLE", + OutTemp => C405PLBICUCACHEABLE_OUT, + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUPRIORITY(0), + GlitchData => C405PLBICUPRIORITY0_GlitchData, + OutSignalName => "C405PLBICUPRIORITY(0)", + OutTemp => C405PLBICUPRIORITY_OUT(0), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUPRIORITY(1), + GlitchData => C405PLBICUPRIORITY1_GlitchData, + OutSignalName => "C405PLBICUPRIORITY(1)", + OutTemp => C405PLBICUPRIORITY_OUT(1), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUREQUEST, + GlitchData => C405PLBICUREQUEST_GlitchData, + OutSignalName => "C405PLBICUREQUEST", + OutTemp => C405PLBICUREQUEST_OUT, + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUSIZE(2), + GlitchData => C405PLBICUSIZE2_GlitchData, + OutSignalName => "C405PLBICUSIZE(2)", + OutTemp => C405PLBICUSIZE_OUT(2), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUSIZE(3), + GlitchData => C405PLBICUSIZE3_GlitchData, + OutSignalName => "C405PLBICUSIZE(3)", + OutTemp => C405PLBICUSIZE_OUT(3), + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); +VitalPathDelay01 ( + OutSignal => C405PLBICUU0ATTR, + GlitchData => C405PLBICUU0ATTR_GlitchData, + OutSignalName => "C405PLBICUU0ATTR", + OutTemp => C405PLBICUU0ATTR_OUT, + Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), + Mode => VitalTransport, + Xon => False, + MsgOn => False, + MsgSeverity => WARNING); + +wait on BRAMDSOCMCLK_ipd , BRAMDSOCMRDDBUS_ipd , + BRAMISOCMCLK_ipd , BRAMISOCMRDDBUS_ipd , + CPMC405CLOCK_ipd , CPMC405CORECLKINACTIVE_ipd , + CPMC405CPUCLKEN_ipd , CPMC405JTAGCLKEN_ipd , + CPMC405TIMERCLKEN_ipd , CPMC405TIMERTICK_ipd , + DBGC405DEBUGHALT_ipd , DBGC405EXTBUSHOLDACK_ipd , + DBGC405UNCONDDEBUGEVENT_ipd , DCRC405ACK_ipd , + DCRC405DBUSIN_ipd , DSARCVALUE_ipd , + DSCNTLVALUE_ipd , EICC405CRITINPUTIRQ_ipd , + EICC405EXTINPUTIRQ_ipd , ISARCVALUE_ipd , + ISCNTLVALUE_ipd , JTGC405BNDSCANTDO_ipd , + JTGC405TCK_ipd , JTGC405TDI_ipd , + JTGC405TMS_ipd , JTGC405TRSTNEG_ipd , + MCBCPUCLKEN_ipd , MCBJTAGEN_ipd , + MCBTIMEREN_ipd , MCPPCRST_ipd , + PLBC405DCUADDRACK_ipd , PLBC405DCUBUSY_ipd , + PLBC405DCUERR_ipd , PLBC405DCURDDACK_ipd , + PLBC405DCURDDBUS_ipd , PLBC405DCURDWDADDR_ipd , + PLBC405DCUSSIZE1_ipd , PLBC405DCUWRDACK_ipd , + PLBC405ICUADDRACK_ipd , PLBC405ICUBUSY_ipd , + PLBC405ICUERR_ipd , PLBC405ICURDDACK_ipd , + PLBC405ICURDDBUS_ipd , PLBC405ICURDWDADDR_ipd , + PLBC405ICUSSIZE1_ipd , PLBCLK_ipd , + RSTC405RESETCHIP_ipd , RSTC405RESETCORE_ipd , + RSTC405RESETSYS_ipd , TIEC405DETERMINISTICMULT_ipd , + TIEC405DISOPERANDFWD_ipd , TIEC405MMUEN_ipd , + TIEDSOCMDCRADDR_ipd , TIEISOCMDCRADDR_ipd , + TRCC405TRACEDISABLE_ipd , TRCC405TRIGGEREVENTIN_ipd , + C405CPMCORESLEEPREQ_OUT , C405CPMMSRCE_OUT , + C405CPMMSREE_OUT , C405CPMTIMERIRQ_OUT , + C405CPMTIMERRESETREQ_OUT , C405DBGMSRWE_OUT , + C405DBGSTOPACK_OUT , C405DBGWBCOMPLETE_OUT , + C405DBGWBFULL_OUT , C405DBGWBIAR_OUT , + C405DCRABUS_OUT , C405DCRDBUSOUT_OUT , + C405DCRREAD_OUT , C405DCRWRITE_OUT , + C405JTGCAPTUREDR_OUT , C405JTGEXTEST_OUT , + C405JTGPGMOUT_OUT , C405JTGSHIFTDR_OUT , + C405JTGTDO_OUT , C405JTGTDOEN_OUT , + C405JTGUPDATEDR_OUT , C405PLBDCUABORT_OUT , + C405PLBDCUABUS_OUT , C405PLBDCUBE_OUT , + C405PLBDCUCACHEABLE_OUT , C405PLBDCUGUARDED_OUT , + C405PLBDCUPRIORITY_OUT , C405PLBDCUREQUEST_OUT , + C405PLBDCURNW_OUT , C405PLBDCUSIZE2_OUT , + C405PLBDCUU0ATTR_OUT , C405PLBDCUWRDBUS_OUT , + C405PLBDCUWRITETHRU_OUT , C405PLBICUABORT_OUT , + C405PLBICUABUS_OUT , C405PLBICUCACHEABLE_OUT , + C405PLBICUPRIORITY_OUT , C405PLBICUREQUEST_OUT , + C405PLBICUSIZE_OUT , C405PLBICUU0ATTR_OUT , + C405RSTCHIPRESETREQ_OUT , C405RSTCORERESETREQ_OUT , + C405RSTSYSRESETREQ_OUT , C405TRCCYCLE_OUT , + C405TRCEVENEXECUTIONSTATUS_OUT , C405TRCODDEXECUTIONSTATUS_OUT , + C405TRCTRACESTATUS_OUT , C405TRCTRIGGEREVENTOUT_OUT , + C405TRCTRIGGEREVENTTYPE_OUT , C405XXXMACHINECHECK_OUT , + DSOCMBRAMABUS_OUT , DSOCMBRAMBYTEWRITE_OUT , + DSOCMBRAMEN_OUT , DSOCMBRAMWRDBUS_OUT , + DSOCMBUSY_OUT , ISOCMBRAMEN_OUT , + ISOCMBRAMEVENWRITEEN_OUT , ISOCMBRAMODDWRITEEN_OUT , + ISOCMBRAMRDABUS_OUT , ISOCMBRAMWRABUS_OUT , + ISOCMBRAMWRDBUS_OUT ; + +end process TIMING; + +end PPC405_v; + + + + +----- CELL EMAC ----- +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Ethernet Media Access Controller +-- /___/ /\ Filename : EMAC.vhd +-- \ \ / \ Timestamp : Fri Jun 18 10:57:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 10/04/05 - Fixed CR#217767. Fixed connectivity for three output ports EMACDCRACK, EMACDCRDBUS and DCRHOSTDONEIR +-- 12/07/07 - Fixed CR#455025. Added delays for 16 bit client mode +-- 02/04/08 - Fixed CR#460680. Changed delay to 125ps +-- End Revision + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity EMAC is +generic ( + IN_DELAY : time := 0 ps; + OUT_DELAY : VitalDelayType01 := (100 ps, 100 ps) + + +-- clk-to-output path delays + + ); + +port ( + DCRHOSTDONEIR : out std_ulogic; + EMAC0CLIENTANINTERRUPT : out std_ulogic; + EMAC0CLIENTRXBADFRAME : out std_ulogic; + EMAC0CLIENTRXCLIENTCLKOUT : out std_ulogic; + EMAC0CLIENTRXD : out std_logic_vector(15 downto 0); + EMAC0CLIENTRXDVLD : out std_ulogic; + EMAC0CLIENTRXDVLDMSW : out std_ulogic; + EMAC0CLIENTRXDVREG6 : out std_ulogic; + EMAC0CLIENTRXFRAMEDROP : out std_ulogic; + EMAC0CLIENTRXGOODFRAME : out std_ulogic; + EMAC0CLIENTRXSTATS : out std_logic_vector(6 downto 0); + EMAC0CLIENTRXSTATSBYTEVLD : out std_ulogic; + EMAC0CLIENTRXSTATSVLD : out std_ulogic; + EMAC0CLIENTTXACK : out std_ulogic; + EMAC0CLIENTTXCLIENTCLKOUT : out std_ulogic; + EMAC0CLIENTTXCOLLISION : out std_ulogic; + EMAC0CLIENTTXGMIIMIICLKOUT : out std_ulogic; + EMAC0CLIENTTXRETRANSMIT : out std_ulogic; + EMAC0CLIENTTXSTATS : out std_ulogic; + EMAC0CLIENTTXSTATSBYTEVLD : out std_ulogic; + EMAC0CLIENTTXSTATSVLD : out std_ulogic; + EMAC0PHYENCOMMAALIGN : out std_ulogic; + EMAC0PHYLOOPBACKMSB : out std_ulogic; + EMAC0PHYMCLKOUT : out std_ulogic; + EMAC0PHYMDOUT : out std_ulogic; + EMAC0PHYMDTRI : out std_ulogic; + EMAC0PHYMGTRXRESET : out std_ulogic; + EMAC0PHYMGTTXRESET : out std_ulogic; + EMAC0PHYPOWERDOWN : out std_ulogic; + EMAC0PHYSYNCACQSTATUS : out std_ulogic; + EMAC0PHYTXCHARDISPMODE : out std_ulogic; + EMAC0PHYTXCHARDISPVAL : out std_ulogic; + EMAC0PHYTXCHARISK : out std_ulogic; + EMAC0PHYTXCLK : out std_ulogic; + EMAC0PHYTXD : out std_logic_vector(7 downto 0); + EMAC0PHYTXEN : out std_ulogic; + EMAC0PHYTXER : out std_ulogic; + EMAC1CLIENTANINTERRUPT : out std_ulogic; + EMAC1CLIENTRXBADFRAME : out std_ulogic; + EMAC1CLIENTRXCLIENTCLKOUT : out std_ulogic; + EMAC1CLIENTRXD : out std_logic_vector(15 downto 0); + EMAC1CLIENTRXDVLD : out std_ulogic; + EMAC1CLIENTRXDVLDMSW : out std_ulogic; + EMAC1CLIENTRXDVREG6 : out std_ulogic; + EMAC1CLIENTRXFRAMEDROP : out std_ulogic; + EMAC1CLIENTRXGOODFRAME : out std_ulogic; + EMAC1CLIENTRXSTATS : out std_logic_vector(6 downto 0); + EMAC1CLIENTRXSTATSBYTEVLD : out std_ulogic; + EMAC1CLIENTRXSTATSVLD : out std_ulogic; + EMAC1CLIENTTXACK : out std_ulogic; + EMAC1CLIENTTXCLIENTCLKOUT : out std_ulogic; + EMAC1CLIENTTXCOLLISION : out std_ulogic; + EMAC1CLIENTTXGMIIMIICLKOUT : out std_ulogic; + EMAC1CLIENTTXRETRANSMIT : out std_ulogic; + EMAC1CLIENTTXSTATS : out std_ulogic; + EMAC1CLIENTTXSTATSBYTEVLD : out std_ulogic; + EMAC1CLIENTTXSTATSVLD : out std_ulogic; + EMAC1PHYENCOMMAALIGN : out std_ulogic; + EMAC1PHYLOOPBACKMSB : out std_ulogic; + EMAC1PHYMCLKOUT : out std_ulogic; + EMAC1PHYMDOUT : out std_ulogic; + EMAC1PHYMDTRI : out std_ulogic; + EMAC1PHYMGTRXRESET : out std_ulogic; + EMAC1PHYMGTTXRESET : out std_ulogic; + EMAC1PHYPOWERDOWN : out std_ulogic; + EMAC1PHYSYNCACQSTATUS : out std_ulogic; + EMAC1PHYTXCHARDISPMODE : out std_ulogic; + EMAC1PHYTXCHARDISPVAL : out std_ulogic; + EMAC1PHYTXCHARISK : out std_ulogic; + EMAC1PHYTXCLK : out std_ulogic; + EMAC1PHYTXD : out std_logic_vector(7 downto 0); + EMAC1PHYTXEN : out std_ulogic; + EMAC1PHYTXER : out std_ulogic; + EMACDCRACK : out std_ulogic; + EMACDCRDBUS : out std_logic_vector(0 to 31); + HOSTMIIMRDY : out std_ulogic; + HOSTRDDATA : out std_logic_vector(31 downto 0); + + CLIENTEMAC0DCMLOCKED : in std_ulogic; + CLIENTEMAC0PAUSEREQ : in std_ulogic; + CLIENTEMAC0PAUSEVAL : in std_logic_vector(15 downto 0); + CLIENTEMAC0RXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC0TXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC0TXD : in std_logic_vector(15 downto 0); + CLIENTEMAC0TXDVLD : in std_ulogic; + CLIENTEMAC0TXDVLDMSW : in std_ulogic; + CLIENTEMAC0TXFIRSTBYTE : in std_ulogic; + CLIENTEMAC0TXGMIIMIICLKIN : in std_ulogic; + CLIENTEMAC0TXIFGDELAY : in std_logic_vector(7 downto 0); + CLIENTEMAC0TXUNDERRUN : in std_ulogic; + CLIENTEMAC1DCMLOCKED : in std_ulogic; + CLIENTEMAC1PAUSEREQ : in std_ulogic; + CLIENTEMAC1PAUSEVAL : in std_logic_vector(15 downto 0); + CLIENTEMAC1RXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC1TXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC1TXD : in std_logic_vector(15 downto 0); + CLIENTEMAC1TXDVLD : in std_ulogic; + CLIENTEMAC1TXDVLDMSW : in std_ulogic; + CLIENTEMAC1TXFIRSTBYTE : in std_ulogic; + CLIENTEMAC1TXGMIIMIICLKIN : in std_ulogic; + CLIENTEMAC1TXIFGDELAY : in std_logic_vector(7 downto 0); + CLIENTEMAC1TXUNDERRUN : in std_ulogic; + DCREMACABUS : in std_logic_vector(8 to 9); + DCREMACCLK : in std_ulogic; + DCREMACDBUS : in std_logic_vector(0 to 31); + DCREMACENABLE : in std_ulogic; + DCREMACREAD : in std_ulogic; + DCREMACWRITE : in std_ulogic; + HOSTADDR : in std_logic_vector(9 downto 0); + HOSTCLK : in std_ulogic; + HOSTEMAC1SEL : in std_ulogic; + HOSTMIIMSEL : in std_ulogic; + HOSTOPCODE : in std_logic_vector(1 downto 0); + HOSTREQ : in std_ulogic; + HOSTWRDATA : in std_logic_vector(31 downto 0); + PHYEMAC0COL : in std_ulogic; + PHYEMAC0CRS : in std_ulogic; + PHYEMAC0GTXCLK : in std_ulogic; + PHYEMAC0MCLKIN : in std_ulogic; + PHYEMAC0MDIN : in std_ulogic; + PHYEMAC0MIITXCLK : in std_ulogic; + PHYEMAC0PHYAD : in std_logic_vector(4 downto 0); + PHYEMAC0RXBUFERR : in std_ulogic; + PHYEMAC0RXBUFSTATUS : in std_logic_vector(1 downto 0); + PHYEMAC0RXCHARISCOMMA : in std_ulogic; + PHYEMAC0RXCHARISK : in std_ulogic; + PHYEMAC0RXCHECKINGCRC : in std_ulogic; + PHYEMAC0RXCLK : in std_ulogic; + PHYEMAC0RXCLKCORCNT : in std_logic_vector(2 downto 0); + PHYEMAC0RXCOMMADET : in std_ulogic; + PHYEMAC0RXD : in std_logic_vector(7 downto 0); + PHYEMAC0RXDISPERR : in std_ulogic; + PHYEMAC0RXDV : in std_ulogic; + PHYEMAC0RXER : in std_ulogic; + PHYEMAC0RXLOSSOFSYNC : in std_logic_vector(1 downto 0); + PHYEMAC0RXNOTINTABLE : in std_ulogic; + PHYEMAC0RXRUNDISP : in std_ulogic; + PHYEMAC0SIGNALDET : in std_ulogic; + PHYEMAC0TXBUFERR : in std_ulogic; + PHYEMAC1COL : in std_ulogic; + PHYEMAC1CRS : in std_ulogic; + PHYEMAC1GTXCLK : in std_ulogic; + PHYEMAC1MCLKIN : in std_ulogic; + PHYEMAC1MDIN : in std_ulogic; + PHYEMAC1MIITXCLK : in std_ulogic; + PHYEMAC1PHYAD : in std_logic_vector(4 downto 0); + PHYEMAC1RXBUFERR : in std_ulogic; + PHYEMAC1RXBUFSTATUS : in std_logic_vector(1 downto 0); + PHYEMAC1RXCHARISCOMMA : in std_ulogic; + PHYEMAC1RXCHARISK : in std_ulogic; + PHYEMAC1RXCHECKINGCRC : in std_ulogic; + PHYEMAC1RXCLK : in std_ulogic; + PHYEMAC1RXCLKCORCNT : in std_logic_vector(2 downto 0); + PHYEMAC1RXCOMMADET : in std_ulogic; + PHYEMAC1RXD : in std_logic_vector(7 downto 0); + PHYEMAC1RXDISPERR : in std_ulogic; + PHYEMAC1RXDV : in std_ulogic; + PHYEMAC1RXER : in std_ulogic; + PHYEMAC1RXLOSSOFSYNC : in std_logic_vector(1 downto 0); + PHYEMAC1RXNOTINTABLE : in std_ulogic; + PHYEMAC1RXRUNDISP : in std_ulogic; + PHYEMAC1SIGNALDET : in std_ulogic; + PHYEMAC1TXBUFERR : in std_ulogic; + RESET : in std_ulogic; + TIEEMAC0CONFIGVEC : in std_logic_vector(79 downto 0); + TIEEMAC0UNICASTADDR : in std_logic_vector(47 downto 0); + TIEEMAC1CONFIGVEC : in std_logic_vector(79 downto 0); + TIEEMAC1UNICASTADDR : in std_logic_vector(47 downto 0) + ); +end EMAC; + +-- Architecture body -- + +architecture EMAC_V of EMAC is + + component EMAC_SWIFT_BUS + port ( + DCRHOSTDONEIR : out std_ulogic; + EMAC0CLIENTANINTERRUPT : out std_ulogic; + EMAC0CLIENTRXBADFRAME : out std_ulogic; + EMAC0CLIENTRXCLIENTCLKOUT : out std_ulogic; + EMAC0CLIENTRXD : out std_logic_vector(15 downto 0); + EMAC0CLIENTRXDVLD : out std_ulogic; + EMAC0CLIENTRXDVLDMSW : out std_ulogic; + EMAC0CLIENTRXDVREG6 : out std_ulogic; + EMAC0CLIENTRXFRAMEDROP : out std_ulogic; + EMAC0CLIENTRXGOODFRAME : out std_ulogic; + EMAC0CLIENTRXSTATS : out std_logic_vector(6 downto 0); + EMAC0CLIENTRXSTATSBYTEVLD : out std_ulogic; + EMAC0CLIENTRXSTATSVLD : out std_ulogic; + EMAC0CLIENTTXACK : out std_ulogic; + EMAC0CLIENTTXCLIENTCLKOUT : out std_ulogic; + EMAC0CLIENTTXCOLLISION : out std_ulogic; + EMAC0CLIENTTXGMIIMIICLKOUT : out std_ulogic; + EMAC0CLIENTTXRETRANSMIT : out std_ulogic; + EMAC0CLIENTTXSTATS : out std_ulogic; + EMAC0CLIENTTXSTATSBYTEVLD : out std_ulogic; + EMAC0CLIENTTXSTATSVLD : out std_ulogic; + EMAC0PHYENCOMMAALIGN : out std_ulogic; + EMAC0PHYLOOPBACKMSB : out std_ulogic; + EMAC0PHYMCLKOUT : out std_ulogic; + EMAC0PHYMDOUT : out std_ulogic; + EMAC0PHYMDTRI : out std_ulogic; + EMAC0PHYMGTRXRESET : out std_ulogic; + EMAC0PHYMGTTXRESET : out std_ulogic; + EMAC0PHYPOWERDOWN : out std_ulogic; + EMAC0PHYSYNCACQSTATUS : out std_ulogic; + EMAC0PHYTXCHARDISPMODE : out std_ulogic; + EMAC0PHYTXCHARDISPVAL : out std_ulogic; + EMAC0PHYTXCHARISK : out std_ulogic; + EMAC0PHYTXCLK : out std_ulogic; + EMAC0PHYTXD : out std_logic_vector(7 downto 0); + EMAC0PHYTXEN : out std_ulogic; + EMAC0PHYTXER : out std_ulogic; + EMAC1CLIENTANINTERRUPT : out std_ulogic; + EMAC1CLIENTRXBADFRAME : out std_ulogic; + EMAC1CLIENTRXCLIENTCLKOUT : out std_ulogic; + EMAC1CLIENTRXD : out std_logic_vector(15 downto 0); + EMAC1CLIENTRXDVLD : out std_ulogic; + EMAC1CLIENTRXDVLDMSW : out std_ulogic; + EMAC1CLIENTRXDVREG6 : out std_ulogic; + EMAC1CLIENTRXFRAMEDROP : out std_ulogic; + EMAC1CLIENTRXGOODFRAME : out std_ulogic; + EMAC1CLIENTRXSTATS : out std_logic_vector(6 downto 0); + EMAC1CLIENTRXSTATSBYTEVLD : out std_ulogic; + EMAC1CLIENTRXSTATSVLD : out std_ulogic; + EMAC1CLIENTTXACK : out std_ulogic; + EMAC1CLIENTTXCLIENTCLKOUT : out std_ulogic; + EMAC1CLIENTTXCOLLISION : out std_ulogic; + EMAC1CLIENTTXGMIIMIICLKOUT : out std_ulogic; + EMAC1CLIENTTXRETRANSMIT : out std_ulogic; + EMAC1CLIENTTXSTATS : out std_ulogic; + EMAC1CLIENTTXSTATSBYTEVLD : out std_ulogic; + EMAC1CLIENTTXSTATSVLD : out std_ulogic; + EMAC1PHYENCOMMAALIGN : out std_ulogic; + EMAC1PHYLOOPBACKMSB : out std_ulogic; + EMAC1PHYMCLKOUT : out std_ulogic; + EMAC1PHYMDOUT : out std_ulogic; + EMAC1PHYMDTRI : out std_ulogic; + EMAC1PHYMGTRXRESET : out std_ulogic; + EMAC1PHYMGTTXRESET : out std_ulogic; + EMAC1PHYPOWERDOWN : out std_ulogic; + EMAC1PHYSYNCACQSTATUS : out std_ulogic; + EMAC1PHYTXCHARDISPMODE : out std_ulogic; + EMAC1PHYTXCHARDISPVAL : out std_ulogic; + EMAC1PHYTXCHARISK : out std_ulogic; + EMAC1PHYTXCLK : out std_ulogic; + EMAC1PHYTXD : out std_logic_vector(7 downto 0); + EMAC1PHYTXEN : out std_ulogic; + EMAC1PHYTXER : out std_ulogic; + EMACDCRACK : out std_ulogic; + EMACDCRDBUS : out std_logic_vector(0 to 31); + HOSTMIIMRDY : out std_ulogic; + HOSTRDDATA : out std_logic_vector(31 downto 0); + + CLIENTEMAC0DCMLOCKED : in std_ulogic; + CLIENTEMAC0PAUSEREQ : in std_ulogic; + CLIENTEMAC0PAUSEVAL : in std_logic_vector(15 downto 0); + CLIENTEMAC0RXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC0TXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC0TXD : in std_logic_vector(15 downto 0); + CLIENTEMAC0TXDVLD : in std_ulogic; + CLIENTEMAC0TXDVLDMSW : in std_ulogic; + CLIENTEMAC0TXFIRSTBYTE : in std_ulogic; + CLIENTEMAC0TXGMIIMIICLKIN : in std_ulogic; + CLIENTEMAC0TXIFGDELAY : in std_logic_vector(7 downto 0); + CLIENTEMAC0TXUNDERRUN : in std_ulogic; + CLIENTEMAC1DCMLOCKED : in std_ulogic; + CLIENTEMAC1PAUSEREQ : in std_ulogic; + CLIENTEMAC1PAUSEVAL : in std_logic_vector(15 downto 0); + CLIENTEMAC1RXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC1TXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC1TXD : in std_logic_vector(15 downto 0); + CLIENTEMAC1TXDVLD : in std_ulogic; + CLIENTEMAC1TXDVLDMSW : in std_ulogic; + CLIENTEMAC1TXFIRSTBYTE : in std_ulogic; + CLIENTEMAC1TXGMIIMIICLKIN : in std_ulogic; + CLIENTEMAC1TXIFGDELAY : in std_logic_vector(7 downto 0); + CLIENTEMAC1TXUNDERRUN : in std_ulogic; + DCREMACABUS : in std_logic_vector(8 to 9); + DCREMACCLK : in std_ulogic; + DCREMACDBUS : in std_logic_vector(0 to 31); + DCREMACENABLE : in std_ulogic; + DCREMACREAD : in std_ulogic; + DCREMACWRITE : in std_ulogic; + HOSTADDR : in std_logic_vector(9 downto 0); + HOSTCLK : in std_ulogic; + HOSTEMAC1SEL : in std_ulogic; + HOSTMIIMSEL : in std_ulogic; + HOSTOPCODE : in std_logic_vector(1 downto 0); + HOSTREQ : in std_ulogic; + HOSTWRDATA : in std_logic_vector(31 downto 0); + PHYEMAC0COL : in std_ulogic; + PHYEMAC0CRS : in std_ulogic; + PHYEMAC0GTXCLK : in std_ulogic; + PHYEMAC0MCLKIN : in std_ulogic; + PHYEMAC0MDIN : in std_ulogic; + PHYEMAC0MIITXCLK : in std_ulogic; + PHYEMAC0PHYAD : in std_logic_vector(4 downto 0); + PHYEMAC0RXBUFERR : in std_ulogic; + PHYEMAC0RXBUFSTATUS : in std_logic_vector(1 downto 0); + PHYEMAC0RXCHARISCOMMA : in std_ulogic; + PHYEMAC0RXCHARISK : in std_ulogic; + PHYEMAC0RXCHECKINGCRC : in std_ulogic; + PHYEMAC0RXCLK : in std_ulogic; + PHYEMAC0RXCLKCORCNT : in std_logic_vector(2 downto 0); + PHYEMAC0RXCOMMADET : in std_ulogic; + PHYEMAC0RXD : in std_logic_vector(7 downto 0); + PHYEMAC0RXDISPERR : in std_ulogic; + PHYEMAC0RXDV : in std_ulogic; + PHYEMAC0RXER : in std_ulogic; + PHYEMAC0RXLOSSOFSYNC : in std_logic_vector(1 downto 0); + PHYEMAC0RXNOTINTABLE : in std_ulogic; + PHYEMAC0RXRUNDISP : in std_ulogic; + PHYEMAC0SIGNALDET : in std_ulogic; + PHYEMAC0TXBUFERR : in std_ulogic; + PHYEMAC1COL : in std_ulogic; + PHYEMAC1CRS : in std_ulogic; + PHYEMAC1GTXCLK : in std_ulogic; + PHYEMAC1MCLKIN : in std_ulogic; + PHYEMAC1MDIN : in std_ulogic; + PHYEMAC1MIITXCLK : in std_ulogic; + PHYEMAC1PHYAD : in std_logic_vector(4 downto 0); + PHYEMAC1RXBUFERR : in std_ulogic; + PHYEMAC1RXBUFSTATUS : in std_logic_vector(1 downto 0); + PHYEMAC1RXCHARISCOMMA : in std_ulogic; + PHYEMAC1RXCHARISK : in std_ulogic; + PHYEMAC1RXCHECKINGCRC : in std_ulogic; + PHYEMAC1RXCLK : in std_ulogic; + PHYEMAC1RXCLKCORCNT : in std_logic_vector(2 downto 0); + PHYEMAC1RXCOMMADET : in std_ulogic; + PHYEMAC1RXD : in std_logic_vector(7 downto 0); + PHYEMAC1RXDISPERR : in std_ulogic; + PHYEMAC1RXDV : in std_ulogic; + PHYEMAC1RXER : in std_ulogic; + PHYEMAC1RXLOSSOFSYNC : in std_logic_vector(1 downto 0); + PHYEMAC1RXNOTINTABLE : in std_ulogic; + PHYEMAC1RXRUNDISP : in std_ulogic; + PHYEMAC1SIGNALDET : in std_ulogic; + PHYEMAC1TXBUFERR : in std_ulogic; + RESET : in std_ulogic; + TIEEMAC0CONFIGVEC : in std_logic_vector(79 downto 0); + TIEEMAC0UNICASTADDR : in std_logic_vector(47 downto 0); + TIEEMAC1CONFIGVEC : in std_logic_vector(79 downto 0); + TIEEMAC1UNICASTADDR : in std_logic_vector(47 downto 0) + + ); + end component; + + -- CR 455025 -- Delay wrapper for 16-bit client mode + signal PHYEMAC0MIITXCLK_delay : std_ulogic; + signal CLIENTEMAC0TXD_delay : std_logic_vector(15 downto 0); + signal CLIENTEMAC0TXDVLD_delay : std_ulogic; + signal CLIENTEMAC0TXDVLDMSW_delay : std_ulogic; + signal PHYEMAC0MIITXCLK_skewed : std_ulogic; + signal CLIENTEMAC0TXD_client16_delay : std_logic_vector(15 downto 0); + signal CLIENTEMAC0TXDVLD_client16_delay : std_ulogic; + signal CLIENTEMAC0TXDVLDMSW_client16_delay : std_ulogic; + + signal PHYEMAC1MIITXCLK_delay : std_ulogic; + signal CLIENTEMAC1TXD_delay : std_logic_vector(15 downto 0); + signal CLIENTEMAC1TXDVLD_delay : std_ulogic; + signal CLIENTEMAC1TXDVLDMSW_delay : std_ulogic; + signal PHYEMAC1MIITXCLK_skewed : std_ulogic; + signal CLIENTEMAC1TXD_client16_delay : std_logic_vector(15 downto 0); + signal CLIENTEMAC1TXDVLD_client16_delay : std_ulogic; + signal CLIENTEMAC1TXDVLDMSW_client16_delay : std_ulogic; + + constant client_in_delay : time := 125 ps; + constant miitxclk_delay : time := 125 ps; + +-- Attribute-to-Cell mapping signals + +-- Input/Output Pin signals + + signal CLIENTEMAC0DCMLOCKED_ipd : std_ulogic; + signal CLIENTEMAC0PAUSEREQ_ipd : std_ulogic; + signal CLIENTEMAC0PAUSEVAL_ipd : std_logic_vector(15 downto 0); + signal CLIENTEMAC0RXCLIENTCLKIN_ipd : std_ulogic; + signal CLIENTEMAC0TXCLIENTCLKIN_ipd : std_ulogic; + signal CLIENTEMAC0TXD_ipd : std_logic_vector(15 downto 0); + signal CLIENTEMAC0TXDVLD_ipd : std_ulogic; + signal CLIENTEMAC0TXDVLDMSW_ipd : std_ulogic; + signal CLIENTEMAC0TXFIRSTBYTE_ipd : std_ulogic; + signal CLIENTEMAC0TXGMIIMIICLKIN_ipd : std_ulogic; + signal CLIENTEMAC0TXIFGDELAY_ipd : std_logic_vector(7 downto 0); + signal CLIENTEMAC0TXUNDERRUN_ipd : std_ulogic; + signal CLIENTEMAC1DCMLOCKED_ipd : std_ulogic; + signal CLIENTEMAC1PAUSEREQ_ipd : std_ulogic; + signal CLIENTEMAC1PAUSEVAL_ipd : std_logic_vector(15 downto 0); + signal CLIENTEMAC1RXCLIENTCLKIN_ipd : std_ulogic; + signal CLIENTEMAC1TXCLIENTCLKIN_ipd : std_ulogic; + signal CLIENTEMAC1TXD_ipd : std_logic_vector(15 downto 0); + signal CLIENTEMAC1TXDVLD_ipd : std_ulogic; + signal CLIENTEMAC1TXDVLDMSW_ipd : std_ulogic; + signal CLIENTEMAC1TXFIRSTBYTE_ipd : std_ulogic; + signal CLIENTEMAC1TXGMIIMIICLKIN_ipd : std_ulogic; + signal CLIENTEMAC1TXIFGDELAY_ipd : std_logic_vector(7 downto 0); + signal CLIENTEMAC1TXUNDERRUN_ipd : std_ulogic; + signal DCREMACENABLE_ipd : std_ulogic; + signal HOSTADDR_ipd : std_logic_vector(9 downto 0); + signal HOSTCLK_ipd : std_ulogic; + signal HOSTEMAC1SEL_ipd : std_ulogic; + signal HOSTMIIMSEL_ipd : std_ulogic; + signal HOSTOPCODE_ipd : std_logic_vector(1 downto 0); + signal HOSTREQ_ipd : std_ulogic; + signal HOSTWRDATA_ipd : std_logic_vector(31 downto 0); + signal PHYEMAC0COL_ipd : std_ulogic; + signal PHYEMAC0CRS_ipd : std_ulogic; + signal PHYEMAC0GTXCLK_ipd : std_ulogic; + signal PHYEMAC0MCLKIN_ipd : std_ulogic; + signal PHYEMAC0MDIN_ipd : std_ulogic; + signal PHYEMAC0MIITXCLK_ipd : std_ulogic; + signal PHYEMAC0PHYAD_ipd : std_logic_vector(4 downto 0); + signal PHYEMAC0RXBUFERR_ipd : std_ulogic; + signal PHYEMAC0RXBUFSTATUS_ipd : std_logic_vector(1 downto 0); + signal PHYEMAC0RXCHARISCOMMA_ipd : std_ulogic; + signal PHYEMAC0RXCHARISK_ipd : std_ulogic; + signal PHYEMAC0RXCHECKINGCRC_ipd : std_ulogic; + signal PHYEMAC0RXCLK_ipd : std_ulogic; + signal PHYEMAC0RXCLKCORCNT_ipd : std_logic_vector(2 downto 0); + signal PHYEMAC0RXCOMMADET_ipd : std_ulogic; + signal PHYEMAC0RXD_ipd : std_logic_vector(7 downto 0); + signal PHYEMAC0RXDISPERR_ipd : std_ulogic; + signal PHYEMAC0RXDV_ipd : std_ulogic; + signal PHYEMAC0RXER_ipd : std_ulogic; + signal PHYEMAC0RXLOSSOFSYNC_ipd : std_logic_vector(1 downto 0); + signal PHYEMAC0RXNOTINTABLE_ipd : std_ulogic; + signal PHYEMAC0RXRUNDISP_ipd : std_ulogic; + signal PHYEMAC0SIGNALDET_ipd : std_ulogic; + signal PHYEMAC0TXBUFERR_ipd : std_ulogic; + signal PHYEMAC1COL_ipd : std_ulogic; + signal PHYEMAC1CRS_ipd : std_ulogic; + signal PHYEMAC1GTXCLK_ipd : std_ulogic; + signal PHYEMAC1MCLKIN_ipd : std_ulogic; + signal PHYEMAC1MDIN_ipd : std_ulogic; + signal PHYEMAC1MIITXCLK_ipd : std_ulogic; + signal PHYEMAC1PHYAD_ipd : std_logic_vector(4 downto 0); + signal PHYEMAC1RXBUFERR_ipd : std_ulogic; + signal PHYEMAC1RXBUFSTATUS_ipd : std_logic_vector(1 downto 0); + signal PHYEMAC1RXCHARISCOMMA_ipd : std_ulogic; + signal PHYEMAC1RXCHARISK_ipd : std_ulogic; + signal PHYEMAC1RXCHECKINGCRC_ipd : std_ulogic; + signal PHYEMAC1RXCLK_ipd : std_ulogic; + signal PHYEMAC1RXCLKCORCNT_ipd : std_logic_vector(2 downto 0); + signal PHYEMAC1RXCOMMADET_ipd : std_ulogic; + signal PHYEMAC1RXD_ipd : std_logic_vector(7 downto 0); + signal PHYEMAC1RXDISPERR_ipd : std_ulogic; + signal PHYEMAC1RXDV_ipd : std_ulogic; + signal PHYEMAC1RXER_ipd : std_ulogic; + signal PHYEMAC1RXLOSSOFSYNC_ipd : std_logic_vector(1 downto 0); + signal PHYEMAC1RXNOTINTABLE_ipd : std_ulogic; + signal PHYEMAC1RXRUNDISP_ipd : std_ulogic; + signal PHYEMAC1SIGNALDET_ipd : std_ulogic; + signal PHYEMAC1TXBUFERR_ipd : std_ulogic; + signal RESET_ipd : std_ulogic; + signal TIEEMAC0CONFIGVEC_ipd : std_logic_vector(79 downto 0); + signal TIEEMAC0UNICASTADDR_ipd : std_logic_vector(47 downto 0); + signal TIEEMAC1CONFIGVEC_ipd : std_logic_vector(79 downto 0); + signal TIEEMAC1UNICASTADDR_ipd : std_logic_vector(47 downto 0); + signal DCREMACWRITE_ipd : std_ulogic; + signal DCREMACREAD_ipd : std_ulogic; + signal DCREMACDBUS_ipd : std_logic_vector(0 to 31); + signal DCREMACABUS_ipd : std_logic_vector(8 to 9); + signal DCREMACCLK_ipd : std_ulogic; + + signal DCRHOSTDONEIR_out : std_ulogic; + signal EMAC0CLIENTANINTERRUPT_out : std_ulogic; + signal EMAC0CLIENTRXBADFRAME_out : std_ulogic; + signal EMAC0CLIENTRXCLIENTCLKOUT_out : std_ulogic; + signal EMAC0CLIENTRXD_out : std_logic_vector(15 downto 0); + signal EMAC0CLIENTRXDVLD_out : std_ulogic; + signal EMAC0CLIENTRXDVLDMSW_out : std_ulogic; + signal EMAC0CLIENTRXDVREG6_out : std_ulogic; + signal EMAC0CLIENTRXFRAMEDROP_out : std_ulogic; + signal EMAC0CLIENTRXGOODFRAME_out : std_ulogic; + signal EMAC0CLIENTRXSTATS_out : std_logic_vector(6 downto 0); + signal EMAC0CLIENTRXSTATSBYTEVLD_out : std_ulogic; + signal EMAC0CLIENTRXSTATSVLD_out : std_ulogic; + signal EMAC0CLIENTTXACK_out : std_ulogic; + signal EMAC0CLIENTTXCLIENTCLKOUT_out : std_ulogic; + signal EMAC0CLIENTTXCOLLISION_out : std_ulogic; + signal EMAC0CLIENTTXGMIIMIICLKOUT_out : std_ulogic; + signal EMAC0CLIENTTXRETRANSMIT_out : std_ulogic; + signal EMAC0CLIENTTXSTATS_out : std_ulogic; + signal EMAC0CLIENTTXSTATSBYTEVLD_out : std_ulogic; + signal EMAC0CLIENTTXSTATSVLD_out : std_ulogic; + signal EMAC0PHYENCOMMAALIGN_out : std_ulogic; + signal EMAC0PHYLOOPBACKMSB_out : std_ulogic; + signal EMAC0PHYMCLKOUT_out : std_ulogic; + signal EMAC0PHYMDOUT_out : std_ulogic; + signal EMAC0PHYMDTRI_out : std_ulogic; + signal EMAC0PHYMGTRXRESET_out : std_ulogic; + signal EMAC0PHYMGTTXRESET_out : std_ulogic; + signal EMAC0PHYPOWERDOWN_out : std_ulogic; + signal EMAC0PHYSYNCACQSTATUS_out : std_ulogic; + signal EMAC0PHYTXCHARDISPMODE_out : std_ulogic; + signal EMAC0PHYTXCHARDISPVAL_out : std_ulogic; + signal EMAC0PHYTXCHARISK_out : std_ulogic; + signal EMAC0PHYTXCLK_out : std_ulogic; + signal EMAC0PHYTXD_out : std_logic_vector(7 downto 0); + signal EMAC0PHYTXEN_out : std_ulogic; + signal EMAC0PHYTXER_out : std_ulogic; + signal EMAC1CLIENTANINTERRUPT_out : std_ulogic; + signal EMAC1CLIENTRXBADFRAME_out : std_ulogic; + signal EMAC1CLIENTRXCLIENTCLKOUT_out : std_ulogic; + signal EMAC1CLIENTRXD_out : std_logic_vector(15 downto 0); + signal EMAC1CLIENTRXDVLD_out : std_ulogic; + signal EMAC1CLIENTRXDVLDMSW_out : std_ulogic; + signal EMAC1CLIENTRXDVREG6_out : std_ulogic; + signal EMAC1CLIENTRXFRAMEDROP_out : std_ulogic; + signal EMAC1CLIENTRXGOODFRAME_out : std_ulogic; + signal EMAC1CLIENTRXSTATS_out : std_logic_vector(6 downto 0); + signal EMAC1CLIENTRXSTATSBYTEVLD_out : std_ulogic; + signal EMAC1CLIENTRXSTATSVLD_out : std_ulogic; + signal EMAC1CLIENTTXACK_out : std_ulogic; + signal EMAC1CLIENTTXCLIENTCLKOUT_out : std_ulogic; + signal EMAC1CLIENTTXCOLLISION_out : std_ulogic; + signal EMAC1CLIENTTXGMIIMIICLKOUT_out : std_ulogic; + signal EMAC1CLIENTTXRETRANSMIT_out : std_ulogic; + signal EMAC1CLIENTTXSTATS_out : std_ulogic; + signal EMAC1CLIENTTXSTATSBYTEVLD_out : std_ulogic; + signal EMAC1CLIENTTXSTATSVLD_out : std_ulogic; + signal EMAC1PHYENCOMMAALIGN_out : std_ulogic; + signal EMAC1PHYLOOPBACKMSB_out : std_ulogic; + signal EMAC1PHYMCLKOUT_out : std_ulogic; + signal EMAC1PHYMDOUT_out : std_ulogic; + signal EMAC1PHYMDTRI_out : std_ulogic; + signal EMAC1PHYMGTRXRESET_out : std_ulogic; + signal EMAC1PHYMGTTXRESET_out : std_ulogic; + signal EMAC1PHYPOWERDOWN_out : std_ulogic; + signal EMAC1PHYSYNCACQSTATUS_out : std_ulogic; + signal EMAC1PHYTXCHARDISPMODE_out : std_ulogic; + signal EMAC1PHYTXCHARDISPVAL_out : std_ulogic; + signal EMAC1PHYTXCHARISK_out : std_ulogic; + signal EMAC1PHYTXCLK_out : std_ulogic; + signal EMAC1PHYTXD_out : std_logic_vector(7 downto 0); + signal EMAC1PHYTXEN_out : std_ulogic; + signal EMAC1PHYTXER_out : std_ulogic; + signal HOSTMIIMRDY_out : std_ulogic; + signal HOSTRDDATA_out : std_logic_vector(31 downto 0); + signal EMACDCRDBUS_out : std_logic_vector(0 to 31); + signal EMACDCRACK_out : std_ulogic; + + +begin + + CLIENTEMAC0DCMLOCKED_ipd <= CLIENTEMAC0DCMLOCKED after IN_DELAY; + CLIENTEMAC0PAUSEREQ_ipd <= CLIENTEMAC0PAUSEREQ after IN_DELAY; + CLIENTEMAC0PAUSEVAL_ipd <= CLIENTEMAC0PAUSEVAL after IN_DELAY; + CLIENTEMAC0RXCLIENTCLKIN_ipd <= CLIENTEMAC0RXCLIENTCLKIN after IN_DELAY; + CLIENTEMAC0TXCLIENTCLKIN_ipd <= CLIENTEMAC0TXCLIENTCLKIN after IN_DELAY; + CLIENTEMAC0TXD_ipd <= CLIENTEMAC0TXD after IN_DELAY; + CLIENTEMAC0TXDVLD_ipd <= CLIENTEMAC0TXDVLD after IN_DELAY; + CLIENTEMAC0TXDVLDMSW_ipd <= CLIENTEMAC0TXDVLDMSW after IN_DELAY; + CLIENTEMAC0TXFIRSTBYTE_ipd <= CLIENTEMAC0TXFIRSTBYTE after IN_DELAY; + CLIENTEMAC0TXGMIIMIICLKIN_ipd <= CLIENTEMAC0TXGMIIMIICLKIN after IN_DELAY; + CLIENTEMAC0TXIFGDELAY_ipd <= CLIENTEMAC0TXIFGDELAY after IN_DELAY; + CLIENTEMAC0TXUNDERRUN_ipd <= CLIENTEMAC0TXUNDERRUN after IN_DELAY; + CLIENTEMAC1DCMLOCKED_ipd <= CLIENTEMAC1DCMLOCKED after IN_DELAY; + CLIENTEMAC1PAUSEREQ_ipd <= CLIENTEMAC1PAUSEREQ after IN_DELAY; + CLIENTEMAC1PAUSEVAL_ipd <= CLIENTEMAC1PAUSEVAL after IN_DELAY; + CLIENTEMAC1RXCLIENTCLKIN_ipd <= CLIENTEMAC1RXCLIENTCLKIN after IN_DELAY; + CLIENTEMAC1TXCLIENTCLKIN_ipd <= CLIENTEMAC1TXCLIENTCLKIN after IN_DELAY; + CLIENTEMAC1TXD_ipd <= CLIENTEMAC1TXD after IN_DELAY; + CLIENTEMAC1TXDVLD_ipd <= CLIENTEMAC1TXDVLD after IN_DELAY; + CLIENTEMAC1TXDVLDMSW_ipd <= CLIENTEMAC1TXDVLDMSW after IN_DELAY; + CLIENTEMAC1TXFIRSTBYTE_ipd <= CLIENTEMAC1TXFIRSTBYTE after IN_DELAY; + CLIENTEMAC1TXGMIIMIICLKIN_ipd <= CLIENTEMAC1TXGMIIMIICLKIN after IN_DELAY; + CLIENTEMAC1TXIFGDELAY_ipd <= CLIENTEMAC1TXIFGDELAY after IN_DELAY; + CLIENTEMAC1TXUNDERRUN_ipd <= CLIENTEMAC1TXUNDERRUN after IN_DELAY; + DCREMACENABLE_ipd <= DCREMACENABLE after IN_DELAY; + HOSTADDR_ipd <= HOSTADDR after IN_DELAY; + HOSTCLK_ipd <= HOSTCLK after IN_DELAY; + HOSTEMAC1SEL_ipd <= HOSTEMAC1SEL after IN_DELAY; + HOSTMIIMSEL_ipd <= HOSTMIIMSEL after IN_DELAY; + HOSTOPCODE_ipd <= HOSTOPCODE after IN_DELAY; + HOSTREQ_ipd <= HOSTREQ after IN_DELAY; + HOSTWRDATA_ipd <= HOSTWRDATA after IN_DELAY; + PHYEMAC0COL_ipd <= PHYEMAC0COL after IN_DELAY; + PHYEMAC0CRS_ipd <= PHYEMAC0CRS after IN_DELAY; + PHYEMAC0GTXCLK_ipd <= PHYEMAC0GTXCLK after IN_DELAY; + PHYEMAC0MCLKIN_ipd <= PHYEMAC0MCLKIN after IN_DELAY; + PHYEMAC0MDIN_ipd <= PHYEMAC0MDIN after IN_DELAY; + PHYEMAC0MIITXCLK_ipd <= PHYEMAC0MIITXCLK after IN_DELAY; + PHYEMAC0PHYAD_ipd <= PHYEMAC0PHYAD after IN_DELAY; + PHYEMAC0RXBUFERR_ipd <= PHYEMAC0RXBUFERR after IN_DELAY; + PHYEMAC0RXBUFSTATUS_ipd <= PHYEMAC0RXBUFSTATUS after IN_DELAY; + PHYEMAC0RXCHARISCOMMA_ipd <= PHYEMAC0RXCHARISCOMMA after IN_DELAY; + PHYEMAC0RXCHARISK_ipd <= PHYEMAC0RXCHARISK after IN_DELAY; + PHYEMAC0RXCHECKINGCRC_ipd <= PHYEMAC0RXCHECKINGCRC after IN_DELAY; + PHYEMAC0RXCLK_ipd <= PHYEMAC0RXCLK after IN_DELAY; + PHYEMAC0RXCLKCORCNT_ipd <= PHYEMAC0RXCLKCORCNT after IN_DELAY; + PHYEMAC0RXCOMMADET_ipd <= PHYEMAC0RXCOMMADET after IN_DELAY; + PHYEMAC0RXD_ipd <= PHYEMAC0RXD after IN_DELAY; + PHYEMAC0RXDISPERR_ipd <= PHYEMAC0RXDISPERR after IN_DELAY; + PHYEMAC0RXDV_ipd <= PHYEMAC0RXDV after IN_DELAY; + PHYEMAC0RXER_ipd <= PHYEMAC0RXER after IN_DELAY; + PHYEMAC0RXLOSSOFSYNC_ipd <= PHYEMAC0RXLOSSOFSYNC after IN_DELAY; + PHYEMAC0RXNOTINTABLE_ipd <= PHYEMAC0RXNOTINTABLE after IN_DELAY; + PHYEMAC0RXRUNDISP_ipd <= PHYEMAC0RXRUNDISP after IN_DELAY; + PHYEMAC0SIGNALDET_ipd <= PHYEMAC0SIGNALDET after IN_DELAY; + PHYEMAC0TXBUFERR_ipd <= PHYEMAC0TXBUFERR after IN_DELAY; + PHYEMAC1COL_ipd <= PHYEMAC1COL after IN_DELAY; + PHYEMAC1CRS_ipd <= PHYEMAC1CRS after IN_DELAY; + PHYEMAC1GTXCLK_ipd <= PHYEMAC1GTXCLK after IN_DELAY; + PHYEMAC1MCLKIN_ipd <= PHYEMAC1MCLKIN after IN_DELAY; + PHYEMAC1MDIN_ipd <= PHYEMAC1MDIN after IN_DELAY; + PHYEMAC1MIITXCLK_ipd <= PHYEMAC1MIITXCLK after IN_DELAY; + PHYEMAC1PHYAD_ipd <= PHYEMAC1PHYAD after IN_DELAY; + PHYEMAC1RXBUFERR_ipd <= PHYEMAC1RXBUFERR after IN_DELAY; + PHYEMAC1RXBUFSTATUS_ipd <= PHYEMAC1RXBUFSTATUS after IN_DELAY; + PHYEMAC1RXCHARISCOMMA_ipd <= PHYEMAC1RXCHARISCOMMA after IN_DELAY; + PHYEMAC1RXCHARISK_ipd <= PHYEMAC1RXCHARISK after IN_DELAY; + PHYEMAC1RXCHECKINGCRC_ipd <= PHYEMAC1RXCHECKINGCRC after IN_DELAY; + PHYEMAC1RXCLK_ipd <= PHYEMAC1RXCLK after IN_DELAY; + PHYEMAC1RXCLKCORCNT_ipd <= PHYEMAC1RXCLKCORCNT after IN_DELAY; + PHYEMAC1RXCOMMADET_ipd <= PHYEMAC1RXCOMMADET after IN_DELAY; + PHYEMAC1RXD_ipd <= PHYEMAC1RXD after IN_DELAY; + PHYEMAC1RXDISPERR_ipd <= PHYEMAC1RXDISPERR after IN_DELAY; + PHYEMAC1RXDV_ipd <= PHYEMAC1RXDV after IN_DELAY; + PHYEMAC1RXER_ipd <= PHYEMAC1RXER after IN_DELAY; + PHYEMAC1RXLOSSOFSYNC_ipd <= PHYEMAC1RXLOSSOFSYNC after IN_DELAY; + PHYEMAC1RXNOTINTABLE_ipd <= PHYEMAC1RXNOTINTABLE after IN_DELAY; + PHYEMAC1RXRUNDISP_ipd <= PHYEMAC1RXRUNDISP after IN_DELAY; + PHYEMAC1SIGNALDET_ipd <= PHYEMAC1SIGNALDET after IN_DELAY; + PHYEMAC1TXBUFERR_ipd <= PHYEMAC1TXBUFERR after IN_DELAY; + RESET_ipd <= RESET after IN_DELAY; + TIEEMAC0CONFIGVEC_ipd <= TIEEMAC0CONFIGVEC after IN_DELAY; + TIEEMAC0UNICASTADDR_ipd <= TIEEMAC0UNICASTADDR after IN_DELAY; + TIEEMAC1CONFIGVEC_ipd <= TIEEMAC1CONFIGVEC after IN_DELAY; + TIEEMAC1UNICASTADDR_ipd <= TIEEMAC1UNICASTADDR after IN_DELAY; + DCREMACWRITE_ipd <= DCREMACWRITE after IN_DELAY; + DCREMACREAD_ipd <= DCREMACREAD after IN_DELAY; + DCREMACDBUS_ipd <= DCREMACDBUS after IN_DELAY; + DCREMACABUS_ipd <= DCREMACABUS after IN_DELAY; + DCREMACCLK_ipd <= DCREMACCLK after IN_DELAY; + + -- CR 455025 Delay EMAC# client input signals in 16-bit client mode + -- EMAC0 + CLIENTEMAC0TXD_delay <= CLIENTEMAC0TXD_ipd after client_in_delay; + CLIENTEMAC0TXDVLD_delay <= CLIENTEMAC0TXDVLD_ipd after client_in_delay; + CLIENTEMAC0TXDVLDMSW_delay <= CLIENTEMAC0TXDVLDMSW_ipd after client_in_delay; + + CLIENTEMAC0TXD_client16_delay <= CLIENTEMAC0TXD_delay when TIEEMAC0CONFIGVEC(66) = '1' else CLIENTEMAC0TXD_ipd; -- CONFIGVEC[66] is 16-bit Tx client + CLIENTEMAC0TXDVLD_client16_delay <= CLIENTEMAC0TXDVLD_delay when TIEEMAC0CONFIGVEC(66) = '1' else CLIENTEMAC0TXDVLD_ipd; + CLIENTEMAC0TXDVLDMSW_client16_delay <= CLIENTEMAC0TXDVLDMSW_delay when TIEEMAC0CONFIGVEC(66) = '1' else CLIENTEMAC0TXDVLDMSW_ipd; + + -- EMAC1 + CLIENTEMAC1TXD_delay <= CLIENTEMAC1TXD_ipd after client_in_delay; + CLIENTEMAC1TXDVLD_delay <= CLIENTEMAC1TXDVLD_ipd after client_in_delay; + CLIENTEMAC1TXDVLDMSW_delay <= CLIENTEMAC1TXDVLDMSW_ipd after client_in_delay; + + CLIENTEMAC1TXD_client16_delay <= CLIENTEMAC1TXD_delay when TIEEMAC1CONFIGVEC(66) = '1' else CLIENTEMAC1TXD_ipd; -- CONFIGVEC[66] is 16-bit Tx client + CLIENTEMAC1TXDVLD_client16_delay <= CLIENTEMAC1TXDVLD_delay when TIEEMAC1CONFIGVEC(66) = '1' else CLIENTEMAC1TXDVLD_ipd; + CLIENTEMAC1TXDVLDMSW_client16_delay <= CLIENTEMAC1TXDVLDMSW_delay when TIEEMAC1CONFIGVEC(66) = '1' else CLIENTEMAC1TXDVLDMSW_ipd; + + --Skew 125 MHz clock EMAC#MIITXCLK against 250 MHz clock in 16-bit client mode + PHYEMAC0MIITXCLK_delay <= PHYEMAC0MIITXCLK_ipd after miitxclk_delay; + PHYEMAC0MIITXCLK_skewed <= PHYEMAC0MIITXCLK_delay when TIEEMAC0CONFIGVEC(66) = '1' else PHYEMAC0MIITXCLK_ipd; -- In TXCLIENT16 mode + + PHYEMAC1MIITXCLK_delay <= PHYEMAC1MIITXCLK_ipd after miitxclk_delay; + PHYEMAC1MIITXCLK_skewed <= PHYEMAC1MIITXCLK_delay when TIEEMAC1CONFIGVEC(66) = '1' else PHYEMAC1MIITXCLK_ipd; -- In TXCLIENT16 mode + + + emac_swift_bw_1 : EMAC_SWIFT_BUS + port map ( + CLIENTEMAC0DCMLOCKED => CLIENTEMAC0DCMLOCKED_ipd, + CLIENTEMAC0PAUSEREQ => CLIENTEMAC0PAUSEREQ_ipd, + CLIENTEMAC0PAUSEVAL => CLIENTEMAC0PAUSEVAL_ipd, + CLIENTEMAC0RXCLIENTCLKIN => CLIENTEMAC0RXCLIENTCLKIN_ipd, + CLIENTEMAC0TXCLIENTCLKIN => CLIENTEMAC0TXCLIENTCLKIN_ipd, + CLIENTEMAC0TXD => CLIENTEMAC0TXD_client16_delay, + CLIENTEMAC0TXDVLD => CLIENTEMAC0TXDVLD_client16_delay, + CLIENTEMAC0TXDVLDMSW => CLIENTEMAC0TXDVLDMSW_client16_delay, + CLIENTEMAC0TXFIRSTBYTE => CLIENTEMAC0TXFIRSTBYTE_ipd, + CLIENTEMAC0TXGMIIMIICLKIN => CLIENTEMAC0TXGMIIMIICLKIN_ipd, + CLIENTEMAC0TXIFGDELAY => CLIENTEMAC0TXIFGDELAY_ipd, + CLIENTEMAC0TXUNDERRUN => CLIENTEMAC0TXUNDERRUN_ipd, + CLIENTEMAC1DCMLOCKED => CLIENTEMAC1DCMLOCKED_ipd, + CLIENTEMAC1PAUSEREQ => CLIENTEMAC1PAUSEREQ_ipd, + CLIENTEMAC1PAUSEVAL => CLIENTEMAC1PAUSEVAL_ipd, + CLIENTEMAC1RXCLIENTCLKIN => CLIENTEMAC1RXCLIENTCLKIN_ipd, + CLIENTEMAC1TXCLIENTCLKIN => CLIENTEMAC1TXCLIENTCLKIN_ipd, + CLIENTEMAC1TXD => CLIENTEMAC1TXD_client16_delay, + CLIENTEMAC1TXDVLD => CLIENTEMAC1TXDVLD_client16_delay, + CLIENTEMAC1TXDVLDMSW => CLIENTEMAC1TXDVLDMSW_client16_delay, + CLIENTEMAC1TXFIRSTBYTE => CLIENTEMAC1TXFIRSTBYTE_ipd, + CLIENTEMAC1TXGMIIMIICLKIN => CLIENTEMAC1TXGMIIMIICLKIN_ipd, + CLIENTEMAC1TXIFGDELAY => CLIENTEMAC1TXIFGDELAY_ipd, + CLIENTEMAC1TXUNDERRUN => CLIENTEMAC1TXUNDERRUN_ipd, + DCREMACABUS => DCREMACABUS_ipd, + DCREMACCLK => DCREMACCLK_ipd, + DCREMACDBUS => DCREMACDBUS_ipd, + DCREMACENABLE => DCREMACENABLE_ipd, + DCREMACREAD => DCREMACREAD_ipd, + DCREMACWRITE => DCREMACWRITE_ipd, + DCRHOSTDONEIR => DCRHOSTDONEIR_out, + EMAC0CLIENTANINTERRUPT => EMAC0CLIENTANINTERRUPT_out, + EMAC0CLIENTRXBADFRAME => EMAC0CLIENTRXBADFRAME_out, + EMAC0CLIENTRXCLIENTCLKOUT => EMAC0CLIENTRXCLIENTCLKOUT_out, + EMAC0CLIENTRXD => EMAC0CLIENTRXD_out, + EMAC0CLIENTRXDVLD => EMAC0CLIENTRXDVLD_out, + EMAC0CLIENTRXDVLDMSW => EMAC0CLIENTRXDVLDMSW_out, + EMAC0CLIENTRXDVREG6 => EMAC0CLIENTRXDVREG6_out, + EMAC0CLIENTRXFRAMEDROP => EMAC0CLIENTRXFRAMEDROP_out, + EMAC0CLIENTRXGOODFRAME => EMAC0CLIENTRXGOODFRAME_out, + EMAC0CLIENTRXSTATS => EMAC0CLIENTRXSTATS_out, + EMAC0CLIENTRXSTATSBYTEVLD => EMAC0CLIENTRXSTATSBYTEVLD_out, + EMAC0CLIENTRXSTATSVLD => EMAC0CLIENTRXSTATSVLD_out, + EMAC0CLIENTTXACK => EMAC0CLIENTTXACK_out, + EMAC0CLIENTTXCLIENTCLKOUT => EMAC0CLIENTTXCLIENTCLKOUT_out, + EMAC0CLIENTTXCOLLISION => EMAC0CLIENTTXCOLLISION_out, + EMAC0CLIENTTXGMIIMIICLKOUT => EMAC0CLIENTTXGMIIMIICLKOUT_out, + EMAC0CLIENTTXRETRANSMIT => EMAC0CLIENTTXRETRANSMIT_out, + EMAC0CLIENTTXSTATS => EMAC0CLIENTTXSTATS_out, + EMAC0CLIENTTXSTATSBYTEVLD => EMAC0CLIENTTXSTATSBYTEVLD_out, + EMAC0CLIENTTXSTATSVLD => EMAC0CLIENTTXSTATSVLD_out, + EMAC0PHYENCOMMAALIGN => EMAC0PHYENCOMMAALIGN_out, + EMAC0PHYLOOPBACKMSB => EMAC0PHYLOOPBACKMSB_out, + EMAC0PHYMCLKOUT => EMAC0PHYMCLKOUT_out, + EMAC0PHYMDOUT => EMAC0PHYMDOUT_out, + EMAC0PHYMDTRI => EMAC0PHYMDTRI_out, + EMAC0PHYMGTRXRESET => EMAC0PHYMGTRXRESET_out, + EMAC0PHYMGTTXRESET => EMAC0PHYMGTTXRESET_out, + EMAC0PHYPOWERDOWN => EMAC0PHYPOWERDOWN_out, + EMAC0PHYSYNCACQSTATUS => EMAC0PHYSYNCACQSTATUS_out, + EMAC0PHYTXCHARDISPMODE => EMAC0PHYTXCHARDISPMODE_out, + EMAC0PHYTXCHARDISPVAL => EMAC0PHYTXCHARDISPVAL_out, + EMAC0PHYTXCHARISK => EMAC0PHYTXCHARISK_out, + EMAC0PHYTXCLK => EMAC0PHYTXCLK_out, + EMAC0PHYTXD => EMAC0PHYTXD_out, + EMAC0PHYTXEN => EMAC0PHYTXEN_out, + EMAC0PHYTXER => EMAC0PHYTXER_out, + EMAC1CLIENTANINTERRUPT => EMAC1CLIENTANINTERRUPT_out, + EMAC1CLIENTRXBADFRAME => EMAC1CLIENTRXBADFRAME_out, + EMAC1CLIENTRXCLIENTCLKOUT => EMAC1CLIENTRXCLIENTCLKOUT_out, + EMAC1CLIENTRXD => EMAC1CLIENTRXD_out, + EMAC1CLIENTRXDVLD => EMAC1CLIENTRXDVLD_out, + EMAC1CLIENTRXDVLDMSW => EMAC1CLIENTRXDVLDMSW_out, + EMAC1CLIENTRXDVREG6 => EMAC1CLIENTRXDVREG6_out, + EMAC1CLIENTRXFRAMEDROP => EMAC1CLIENTRXFRAMEDROP_out, + EMAC1CLIENTRXGOODFRAME => EMAC1CLIENTRXGOODFRAME_out, + EMAC1CLIENTRXSTATS => EMAC1CLIENTRXSTATS_out, + EMAC1CLIENTRXSTATSBYTEVLD => EMAC1CLIENTRXSTATSBYTEVLD_out, + EMAC1CLIENTRXSTATSVLD => EMAC1CLIENTRXSTATSVLD_out, + EMAC1CLIENTTXACK => EMAC1CLIENTTXACK_out, + EMAC1CLIENTTXCLIENTCLKOUT => EMAC1CLIENTTXCLIENTCLKOUT_out, + EMAC1CLIENTTXCOLLISION => EMAC1CLIENTTXCOLLISION_out, + EMAC1CLIENTTXGMIIMIICLKOUT => EMAC1CLIENTTXGMIIMIICLKOUT_out, + EMAC1CLIENTTXRETRANSMIT => EMAC1CLIENTTXRETRANSMIT_out, + EMAC1CLIENTTXSTATS => EMAC1CLIENTTXSTATS_out, + EMAC1CLIENTTXSTATSBYTEVLD => EMAC1CLIENTTXSTATSBYTEVLD_out, + EMAC1CLIENTTXSTATSVLD => EMAC1CLIENTTXSTATSVLD_out, + EMAC1PHYENCOMMAALIGN => EMAC1PHYENCOMMAALIGN_out, + EMAC1PHYLOOPBACKMSB => EMAC1PHYLOOPBACKMSB_out, + EMAC1PHYMCLKOUT => EMAC1PHYMCLKOUT_out, + EMAC1PHYMDOUT => EMAC1PHYMDOUT_out, + EMAC1PHYMDTRI => EMAC1PHYMDTRI_out, + EMAC1PHYMGTRXRESET => EMAC1PHYMGTRXRESET_out, + EMAC1PHYMGTTXRESET => EMAC1PHYMGTTXRESET_out, + EMAC1PHYPOWERDOWN => EMAC1PHYPOWERDOWN_out, + EMAC1PHYSYNCACQSTATUS => EMAC1PHYSYNCACQSTATUS_out, + EMAC1PHYTXCHARDISPMODE => EMAC1PHYTXCHARDISPMODE_out, + EMAC1PHYTXCHARDISPVAL => EMAC1PHYTXCHARDISPVAL_out, + EMAC1PHYTXCHARISK => EMAC1PHYTXCHARISK_out, + EMAC1PHYTXCLK => EMAC1PHYTXCLK_out, + EMAC1PHYTXD => EMAC1PHYTXD_out, + EMAC1PHYTXEN => EMAC1PHYTXEN_out, + EMAC1PHYTXER => EMAC1PHYTXER_out, + EMACDCRACK => EMACDCRACK_out, + EMACDCRDBUS => EMACDCRDBUS_out, + HOSTADDR => HOSTADDR_ipd, + HOSTCLK => HOSTCLK_ipd, + HOSTEMAC1SEL => HOSTEMAC1SEL_ipd, + HOSTMIIMRDY => HOSTMIIMRDY_out, + HOSTMIIMSEL => HOSTMIIMSEL_ipd, + HOSTOPCODE => HOSTOPCODE_ipd, + HOSTRDDATA => HOSTRDDATA_out, + HOSTREQ => HOSTREQ_ipd, + HOSTWRDATA => HOSTWRDATA_ipd, + PHYEMAC0COL => PHYEMAC0COL_ipd, + PHYEMAC0CRS => PHYEMAC0CRS_ipd, + PHYEMAC0GTXCLK => PHYEMAC0GTXCLK_ipd, + PHYEMAC0MCLKIN => PHYEMAC0MCLKIN_ipd, + PHYEMAC0MDIN => PHYEMAC0MDIN_ipd, + PHYEMAC0MIITXCLK => PHYEMAC0MIITXCLK_skewed, + PHYEMAC0PHYAD => PHYEMAC0PHYAD_ipd, + PHYEMAC0RXBUFERR => PHYEMAC0RXBUFERR_ipd, + PHYEMAC0RXBUFSTATUS => PHYEMAC0RXBUFSTATUS_ipd, + PHYEMAC0RXCHARISCOMMA => PHYEMAC0RXCHARISCOMMA_ipd, + PHYEMAC0RXCHARISK => PHYEMAC0RXCHARISK_ipd, + PHYEMAC0RXCHECKINGCRC => PHYEMAC0RXCHECKINGCRC_ipd, + PHYEMAC0RXCLK => PHYEMAC0RXCLK_ipd, + PHYEMAC0RXCLKCORCNT => PHYEMAC0RXCLKCORCNT_ipd, + PHYEMAC0RXCOMMADET => PHYEMAC0RXCOMMADET_ipd, + PHYEMAC0RXD => PHYEMAC0RXD_ipd, + PHYEMAC0RXDISPERR => PHYEMAC0RXDISPERR_ipd, + PHYEMAC0RXDV => PHYEMAC0RXDV_ipd, + PHYEMAC0RXER => PHYEMAC0RXER_ipd, + PHYEMAC0RXLOSSOFSYNC => PHYEMAC0RXLOSSOFSYNC_ipd, + PHYEMAC0RXNOTINTABLE => PHYEMAC0RXNOTINTABLE_ipd, + PHYEMAC0RXRUNDISP => PHYEMAC0RXRUNDISP_ipd, + PHYEMAC0SIGNALDET => PHYEMAC0SIGNALDET_ipd, + PHYEMAC0TXBUFERR => PHYEMAC0TXBUFERR_ipd, + PHYEMAC1COL => PHYEMAC1COL_ipd, + PHYEMAC1CRS => PHYEMAC1CRS_ipd, + PHYEMAC1GTXCLK => PHYEMAC1GTXCLK_ipd, + PHYEMAC1MCLKIN => PHYEMAC1MCLKIN_ipd, + PHYEMAC1MDIN => PHYEMAC1MDIN_ipd, + PHYEMAC1MIITXCLK => PHYEMAC1MIITXCLK_skewed, + PHYEMAC1PHYAD => PHYEMAC1PHYAD_ipd, + PHYEMAC1RXBUFERR => PHYEMAC1RXBUFERR_ipd, + PHYEMAC1RXBUFSTATUS => PHYEMAC1RXBUFSTATUS_ipd, + PHYEMAC1RXCHARISCOMMA => PHYEMAC1RXCHARISCOMMA_ipd, + PHYEMAC1RXCHARISK => PHYEMAC1RXCHARISK_ipd, + PHYEMAC1RXCHECKINGCRC => PHYEMAC1RXCHECKINGCRC_ipd, + PHYEMAC1RXCLK => PHYEMAC1RXCLK_ipd, + PHYEMAC1RXCLKCORCNT => PHYEMAC1RXCLKCORCNT_ipd, + PHYEMAC1RXCOMMADET => PHYEMAC1RXCOMMADET_ipd, + PHYEMAC1RXD => PHYEMAC1RXD_ipd, + PHYEMAC1RXDISPERR => PHYEMAC1RXDISPERR_ipd, + PHYEMAC1RXDV => PHYEMAC1RXDV_ipd, + PHYEMAC1RXER => PHYEMAC1RXER_ipd, + PHYEMAC1RXLOSSOFSYNC => PHYEMAC1RXLOSSOFSYNC_ipd, + PHYEMAC1RXNOTINTABLE => PHYEMAC1RXNOTINTABLE_ipd, + PHYEMAC1RXRUNDISP => PHYEMAC1RXRUNDISP_ipd, + PHYEMAC1SIGNALDET => PHYEMAC1SIGNALDET_ipd, + PHYEMAC1TXBUFERR => PHYEMAC1TXBUFERR_ipd, + RESET => RESET_ipd, + TIEEMAC0CONFIGVEC => TIEEMAC0CONFIGVEC_ipd, + TIEEMAC0UNICASTADDR => TIEEMAC0UNICASTADDR_ipd, + TIEEMAC1CONFIGVEC => TIEEMAC1CONFIGVEC_ipd, + TIEEMAC1UNICASTADDR => TIEEMAC1UNICASTADDR_ipd + + ); + + + + TIMING : process + +-- Pin timing violations (clock input pins) + +-- Pin Timing Violations (all input pins) + +-- Output Pin glitch declaration + variable DCRHOSTDONEIR_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTANINTERRUPT_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXBADFRAME_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD0_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD1_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD2_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD3_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD4_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD5_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD6_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD7_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD8_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD9_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD10_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD11_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD12_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD13_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD14_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD15_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXDVLD_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXDVLDMSW_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXDVREG6_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXFRAMEDROP_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXGOODFRAME_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS0_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS1_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS2_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS3_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS4_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS5_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS6_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATSVLD_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXACK_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXCOLLISION_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXGMIIMIICLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXRETRANSMIT_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXSTATS_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXSTATSVLD_GlitchData : VitalGlitchDataType; + variable EMAC0PHYENCOMMAALIGN_GlitchData : VitalGlitchDataType; + variable EMAC0PHYLOOPBACKMSB_GlitchData : VitalGlitchDataType; + variable EMAC0PHYMCLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC0PHYMDOUT_GlitchData : VitalGlitchDataType; + variable EMAC0PHYMDTRI_GlitchData : VitalGlitchDataType; + variable EMAC0PHYMGTRXRESET_GlitchData : VitalGlitchDataType; + variable EMAC0PHYMGTTXRESET_GlitchData : VitalGlitchDataType; + variable EMAC0PHYPOWERDOWN_GlitchData : VitalGlitchDataType; + variable EMAC0PHYSYNCACQSTATUS_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXCHARDISPMODE_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXCHARDISPVAL_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXCHARISK_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXCLK_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD0_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD1_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD2_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD3_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD4_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD5_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD6_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD7_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXEN_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXER_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTANINTERRUPT_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXBADFRAME_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD0_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD1_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD2_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD3_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD4_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD5_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD6_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD7_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD8_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD9_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD10_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD11_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD12_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD13_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD14_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD15_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXDVLD_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXDVLDMSW_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXDVREG6_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXFRAMEDROP_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXGOODFRAME_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS0_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS1_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS2_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS3_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS4_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS5_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS6_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATSVLD_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXACK_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXCOLLISION_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXGMIIMIICLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXRETRANSMIT_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXSTATS_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXSTATSVLD_GlitchData : VitalGlitchDataType; + variable EMAC1PHYENCOMMAALIGN_GlitchData : VitalGlitchDataType; + variable EMAC1PHYLOOPBACKMSB_GlitchData : VitalGlitchDataType; + variable EMAC1PHYMCLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC1PHYMDOUT_GlitchData : VitalGlitchDataType; + variable EMAC1PHYMDTRI_GlitchData : VitalGlitchDataType; + variable EMAC1PHYMGTRXRESET_GlitchData : VitalGlitchDataType; + variable EMAC1PHYMGTTXRESET_GlitchData : VitalGlitchDataType; + variable EMAC1PHYPOWERDOWN_GlitchData : VitalGlitchDataType; + variable EMAC1PHYSYNCACQSTATUS_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXCHARDISPMODE_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXCHARDISPVAL_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXCHARISK_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXCLK_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD0_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD1_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD2_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD3_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD4_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD5_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD6_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD7_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXEN_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXER_GlitchData : VitalGlitchDataType; + variable HOSTMIIMRDY_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA0_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA1_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA2_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA3_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA4_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA5_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA6_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA7_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA8_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA9_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA10_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA11_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA12_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA13_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA14_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA15_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA16_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA17_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA18_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA19_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA20_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA21_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA22_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA23_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA24_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA25_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA26_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA27_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA28_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA29_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA30_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA31_GlitchData : VitalGlitchDataType; + variable EMACDCRACK_GlitchData : VitalGlitchDataType; +begin + + EMACDCRACK <= EMACDCRACK_out; + EMACDCRDBUS <= EMACDCRDBUS_out; + DCRHOSTDONEIR <= DCRHOSTDONEIR_out; + +-- Output-to-Clock path delay + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTANINTERRUPT, + GlitchData => EMAC0CLIENTANINTERRUPT_GlitchData, + OutSignalName => "EMAC0CLIENTANINTERRUPT", + OutTemp => EMAC0CLIENTANINTERRUPT_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXBADFRAME, + GlitchData => EMAC0CLIENTRXBADFRAME_GlitchData, + OutSignalName => "EMAC0CLIENTRXBADFRAME", + OutTemp => EMAC0CLIENTRXBADFRAME_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXCLIENTCLKOUT, + GlitchData => EMAC0CLIENTRXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC0CLIENTRXCLIENTCLKOUT", + OutTemp => EMAC0CLIENTRXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(0), + GlitchData => EMAC0CLIENTRXD0_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(0)", + OutTemp => EMAC0CLIENTRXD_OUT(0), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(1), + GlitchData => EMAC0CLIENTRXD1_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(1)", + OutTemp => EMAC0CLIENTRXD_OUT(1), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(2), + GlitchData => EMAC0CLIENTRXD2_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(2)", + OutTemp => EMAC0CLIENTRXD_OUT(2), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(3), + GlitchData => EMAC0CLIENTRXD3_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(3)", + OutTemp => EMAC0CLIENTRXD_OUT(3), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(4), + GlitchData => EMAC0CLIENTRXD4_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(4)", + OutTemp => EMAC0CLIENTRXD_OUT(4), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(5), + GlitchData => EMAC0CLIENTRXD5_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(5)", + OutTemp => EMAC0CLIENTRXD_OUT(5), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(6), + GlitchData => EMAC0CLIENTRXD6_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(6)", + OutTemp => EMAC0CLIENTRXD_OUT(6), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(7), + GlitchData => EMAC0CLIENTRXD7_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(7)", + OutTemp => EMAC0CLIENTRXD_OUT(7), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(8), + GlitchData => EMAC0CLIENTRXD8_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(8)", + OutTemp => EMAC0CLIENTRXD_OUT(8), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(9), + GlitchData => EMAC0CLIENTRXD9_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(9)", + OutTemp => EMAC0CLIENTRXD_OUT(9), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(10), + GlitchData => EMAC0CLIENTRXD10_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(10)", + OutTemp => EMAC0CLIENTRXD_OUT(10), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(11), + GlitchData => EMAC0CLIENTRXD11_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(11)", + OutTemp => EMAC0CLIENTRXD_OUT(11), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(12), + GlitchData => EMAC0CLIENTRXD12_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(12)", + OutTemp => EMAC0CLIENTRXD_OUT(12), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(13), + GlitchData => EMAC0CLIENTRXD13_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(13)", + OutTemp => EMAC0CLIENTRXD_OUT(13), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(14), + GlitchData => EMAC0CLIENTRXD14_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(14)", + OutTemp => EMAC0CLIENTRXD_OUT(14), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(15), + GlitchData => EMAC0CLIENTRXD15_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(15)", + OutTemp => EMAC0CLIENTRXD_OUT(15), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXDVLD, + GlitchData => EMAC0CLIENTRXDVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXDVLD", + OutTemp => EMAC0CLIENTRXDVLD_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXDVLDMSW, + GlitchData => EMAC0CLIENTRXDVLDMSW_GlitchData, + OutSignalName => "EMAC0CLIENTRXDVLDMSW", + OutTemp => EMAC0CLIENTRXDVLDMSW_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXDVREG6, + GlitchData => EMAC0CLIENTRXDVREG6_GlitchData, + OutSignalName => "EMAC0CLIENTRXDVREG6", + OutTemp => EMAC0CLIENTRXDVREG6_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXFRAMEDROP, + GlitchData => EMAC0CLIENTRXFRAMEDROP_GlitchData, + OutSignalName => "EMAC0CLIENTRXFRAMEDROP", + OutTemp => EMAC0CLIENTRXFRAMEDROP_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXGOODFRAME, + GlitchData => EMAC0CLIENTRXGOODFRAME_GlitchData, + OutSignalName => "EMAC0CLIENTRXGOODFRAME", + OutTemp => EMAC0CLIENTRXGOODFRAME_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(0), + GlitchData => EMAC0CLIENTRXSTATS0_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(0)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(0), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(1), + GlitchData => EMAC0CLIENTRXSTATS1_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(1)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(1), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(2), + GlitchData => EMAC0CLIENTRXSTATS2_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(2)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(2), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(3), + GlitchData => EMAC0CLIENTRXSTATS3_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(3)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(3), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(4), + GlitchData => EMAC0CLIENTRXSTATS4_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(4)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(4), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(5), + GlitchData => EMAC0CLIENTRXSTATS5_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(5)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(5), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(6), + GlitchData => EMAC0CLIENTRXSTATS6_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(6)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(6), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATSBYTEVLD, + GlitchData => EMAC0CLIENTRXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATSBYTEVLD", + OutTemp => EMAC0CLIENTRXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATSVLD, + GlitchData => EMAC0CLIENTRXSTATSVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATSVLD", + OutTemp => EMAC0CLIENTRXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXACK, + GlitchData => EMAC0CLIENTTXACK_GlitchData, + OutSignalName => "EMAC0CLIENTTXACK", + OutTemp => EMAC0CLIENTTXACK_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXCLIENTCLKOUT, + GlitchData => EMAC0CLIENTTXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC0CLIENTTXCLIENTCLKOUT", + OutTemp => EMAC0CLIENTTXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXCOLLISION, + GlitchData => EMAC0CLIENTTXCOLLISION_GlitchData, + OutSignalName => "EMAC0CLIENTTXCOLLISION", + OutTemp => EMAC0CLIENTTXCOLLISION_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXGMIIMIICLKOUT, + GlitchData => EMAC0CLIENTTXGMIIMIICLKOUT_GlitchData, + OutSignalName => "EMAC0CLIENTTXGMIIMIICLKOUT", + OutTemp => EMAC0CLIENTTXGMIIMIICLKOUT_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXRETRANSMIT, + GlitchData => EMAC0CLIENTTXRETRANSMIT_GlitchData, + OutSignalName => "EMAC0CLIENTTXRETRANSMIT", + OutTemp => EMAC0CLIENTTXRETRANSMIT_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATS, + GlitchData => EMAC0CLIENTTXSTATS_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATS", + OutTemp => EMAC0CLIENTTXSTATS_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATSBYTEVLD, + GlitchData => EMAC0CLIENTTXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATSBYTEVLD", + OutTemp => EMAC0CLIENTTXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATSVLD, + GlitchData => EMAC0CLIENTTXSTATSVLD_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATSVLD", + OutTemp => EMAC0CLIENTTXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYENCOMMAALIGN, + GlitchData => EMAC0PHYENCOMMAALIGN_GlitchData, + OutSignalName => "EMAC0PHYENCOMMAALIGN", + OutTemp => EMAC0PHYENCOMMAALIGN_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYLOOPBACKMSB, + GlitchData => EMAC0PHYLOOPBACKMSB_GlitchData, + OutSignalName => "EMAC0PHYLOOPBACKMSB", + OutTemp => EMAC0PHYLOOPBACKMSB_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMCLKOUT, + GlitchData => EMAC0PHYMCLKOUT_GlitchData, + OutSignalName => "EMAC0PHYMCLKOUT", + OutTemp => EMAC0PHYMCLKOUT_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMDOUT, + GlitchData => EMAC0PHYMDOUT_GlitchData, + OutSignalName => "EMAC0PHYMDOUT", + OutTemp => EMAC0PHYMDOUT_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMDTRI, + GlitchData => EMAC0PHYMDTRI_GlitchData, + OutSignalName => "EMAC0PHYMDTRI", + OutTemp => EMAC0PHYMDTRI_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMGTRXRESET, + GlitchData => EMAC0PHYMGTRXRESET_GlitchData, + OutSignalName => "EMAC0PHYMGTRXRESET", + OutTemp => EMAC0PHYMGTRXRESET_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMGTTXRESET, + GlitchData => EMAC0PHYMGTTXRESET_GlitchData, + OutSignalName => "EMAC0PHYMGTTXRESET", + OutTemp => EMAC0PHYMGTTXRESET_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYPOWERDOWN, + GlitchData => EMAC0PHYPOWERDOWN_GlitchData, + OutSignalName => "EMAC0PHYPOWERDOWN", + OutTemp => EMAC0PHYPOWERDOWN_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYSYNCACQSTATUS, + GlitchData => EMAC0PHYSYNCACQSTATUS_GlitchData, + OutSignalName => "EMAC0PHYSYNCACQSTATUS", + OutTemp => EMAC0PHYSYNCACQSTATUS_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARDISPMODE, + GlitchData => EMAC0PHYTXCHARDISPMODE_GlitchData, + OutSignalName => "EMAC0PHYTXCHARDISPMODE", + OutTemp => EMAC0PHYTXCHARDISPMODE_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARDISPVAL, + GlitchData => EMAC0PHYTXCHARDISPVAL_GlitchData, + OutSignalName => "EMAC0PHYTXCHARDISPVAL", + OutTemp => EMAC0PHYTXCHARDISPVAL_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARISK, + GlitchData => EMAC0PHYTXCHARISK_GlitchData, + OutSignalName => "EMAC0PHYTXCHARISK", + OutTemp => EMAC0PHYTXCHARISK_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCLK, + GlitchData => EMAC0PHYTXCLK_GlitchData, + OutSignalName => "EMAC0PHYTXCLK", + OutTemp => EMAC0PHYTXCLK_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(0), + GlitchData => EMAC0PHYTXD0_GlitchData, + OutSignalName => "EMAC0PHYTXD(0)", + OutTemp => EMAC0PHYTXD_OUT(0), + Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(1), + GlitchData => EMAC0PHYTXD1_GlitchData, + OutSignalName => "EMAC0PHYTXD(1)", + OutTemp => EMAC0PHYTXD_OUT(1), + Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(2), + GlitchData => EMAC0PHYTXD2_GlitchData, + OutSignalName => "EMAC0PHYTXD(2)", + OutTemp => EMAC0PHYTXD_OUT(2), + Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(3), + GlitchData => EMAC0PHYTXD3_GlitchData, + OutSignalName => "EMAC0PHYTXD(3)", + OutTemp => EMAC0PHYTXD_OUT(3), + Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(4), + GlitchData => EMAC0PHYTXD4_GlitchData, + OutSignalName => "EMAC0PHYTXD(4)", + OutTemp => EMAC0PHYTXD_OUT(4), + Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(5), + GlitchData => EMAC0PHYTXD5_GlitchData, + OutSignalName => "EMAC0PHYTXD(5)", + OutTemp => EMAC0PHYTXD_OUT(5), + Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(6), + GlitchData => EMAC0PHYTXD6_GlitchData, + OutSignalName => "EMAC0PHYTXD(6)", + OutTemp => EMAC0PHYTXD_OUT(6), + Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(7), + GlitchData => EMAC0PHYTXD7_GlitchData, + OutSignalName => "EMAC0PHYTXD(7)", + OutTemp => EMAC0PHYTXD_OUT(7), + Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXEN, + GlitchData => EMAC0PHYTXEN_GlitchData, + OutSignalName => "EMAC0PHYTXEN", + OutTemp => EMAC0PHYTXEN_OUT, + Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXER, + GlitchData => EMAC0PHYTXER_GlitchData, + OutSignalName => "EMAC0PHYTXER", + OutTemp => EMAC0PHYTXER_OUT, + Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTANINTERRUPT, + GlitchData => EMAC1CLIENTANINTERRUPT_GlitchData, + OutSignalName => "EMAC1CLIENTANINTERRUPT", + OutTemp => EMAC1CLIENTANINTERRUPT_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXBADFRAME, + GlitchData => EMAC1CLIENTRXBADFRAME_GlitchData, + OutSignalName => "EMAC1CLIENTRXBADFRAME", + OutTemp => EMAC1CLIENTRXBADFRAME_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXCLIENTCLKOUT, + GlitchData => EMAC1CLIENTRXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC1CLIENTRXCLIENTCLKOUT", + OutTemp => EMAC1CLIENTRXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(0), + GlitchData => EMAC1CLIENTRXD0_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(0)", + OutTemp => EMAC1CLIENTRXD_OUT(0), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(1), + GlitchData => EMAC1CLIENTRXD1_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(1)", + OutTemp => EMAC1CLIENTRXD_OUT(1), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(2), + GlitchData => EMAC1CLIENTRXD2_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(2)", + OutTemp => EMAC1CLIENTRXD_OUT(2), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(3), + GlitchData => EMAC1CLIENTRXD3_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(3)", + OutTemp => EMAC1CLIENTRXD_OUT(3), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(4), + GlitchData => EMAC1CLIENTRXD4_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(4)", + OutTemp => EMAC1CLIENTRXD_OUT(4), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(5), + GlitchData => EMAC1CLIENTRXD5_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(5)", + OutTemp => EMAC1CLIENTRXD_OUT(5), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(6), + GlitchData => EMAC1CLIENTRXD6_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(6)", + OutTemp => EMAC1CLIENTRXD_OUT(6), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(7), + GlitchData => EMAC1CLIENTRXD7_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(7)", + OutTemp => EMAC1CLIENTRXD_OUT(7), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(8), + GlitchData => EMAC1CLIENTRXD8_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(8)", + OutTemp => EMAC1CLIENTRXD_OUT(8), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(9), + GlitchData => EMAC1CLIENTRXD9_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(9)", + OutTemp => EMAC1CLIENTRXD_OUT(9), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(10), + GlitchData => EMAC1CLIENTRXD10_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(10)", + OutTemp => EMAC1CLIENTRXD_OUT(10), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(11), + GlitchData => EMAC1CLIENTRXD11_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(11)", + OutTemp => EMAC1CLIENTRXD_OUT(11), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(12), + GlitchData => EMAC1CLIENTRXD12_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(12)", + OutTemp => EMAC1CLIENTRXD_OUT(12), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(13), + GlitchData => EMAC1CLIENTRXD13_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(13)", + OutTemp => EMAC1CLIENTRXD_OUT(13), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(14), + GlitchData => EMAC1CLIENTRXD14_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(14)", + OutTemp => EMAC1CLIENTRXD_OUT(14), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(15), + GlitchData => EMAC1CLIENTRXD15_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(15)", + OutTemp => EMAC1CLIENTRXD_OUT(15), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXDVLD, + GlitchData => EMAC1CLIENTRXDVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXDVLD", + OutTemp => EMAC1CLIENTRXDVLD_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXDVLDMSW, + GlitchData => EMAC1CLIENTRXDVLDMSW_GlitchData, + OutSignalName => "EMAC1CLIENTRXDVLDMSW", + OutTemp => EMAC1CLIENTRXDVLDMSW_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXDVREG6, + GlitchData => EMAC1CLIENTRXDVREG6_GlitchData, + OutSignalName => "EMAC1CLIENTRXDVREG6", + OutTemp => EMAC1CLIENTRXDVREG6_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXFRAMEDROP, + GlitchData => EMAC1CLIENTRXFRAMEDROP_GlitchData, + OutSignalName => "EMAC1CLIENTRXFRAMEDROP", + OutTemp => EMAC1CLIENTRXFRAMEDROP_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXGOODFRAME, + GlitchData => EMAC1CLIENTRXGOODFRAME_GlitchData, + OutSignalName => "EMAC1CLIENTRXGOODFRAME", + OutTemp => EMAC1CLIENTRXGOODFRAME_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(0), + GlitchData => EMAC1CLIENTRXSTATS0_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(0)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(0), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(1), + GlitchData => EMAC1CLIENTRXSTATS1_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(1)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(1), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(2), + GlitchData => EMAC1CLIENTRXSTATS2_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(2)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(2), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(3), + GlitchData => EMAC1CLIENTRXSTATS3_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(3)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(3), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(4), + GlitchData => EMAC1CLIENTRXSTATS4_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(4)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(4), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(5), + GlitchData => EMAC1CLIENTRXSTATS5_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(5)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(5), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(6), + GlitchData => EMAC1CLIENTRXSTATS6_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(6)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(6), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATSBYTEVLD, + GlitchData => EMAC1CLIENTRXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATSBYTEVLD", + OutTemp => EMAC1CLIENTRXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATSVLD, + GlitchData => EMAC1CLIENTRXSTATSVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATSVLD", + OutTemp => EMAC1CLIENTRXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXACK, + GlitchData => EMAC1CLIENTTXACK_GlitchData, + OutSignalName => "EMAC1CLIENTTXACK", + OutTemp => EMAC1CLIENTTXACK_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXCLIENTCLKOUT, + GlitchData => EMAC1CLIENTTXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC1CLIENTTXCLIENTCLKOUT", + OutTemp => EMAC1CLIENTTXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXCOLLISION, + GlitchData => EMAC1CLIENTTXCOLLISION_GlitchData, + OutSignalName => "EMAC1CLIENTTXCOLLISION", + OutTemp => EMAC1CLIENTTXCOLLISION_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXGMIIMIICLKOUT, + GlitchData => EMAC1CLIENTTXGMIIMIICLKOUT_GlitchData, + OutSignalName => "EMAC1CLIENTTXGMIIMIICLKOUT", + OutTemp => EMAC1CLIENTTXGMIIMIICLKOUT_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXRETRANSMIT, + GlitchData => EMAC1CLIENTTXRETRANSMIT_GlitchData, + OutSignalName => "EMAC1CLIENTTXRETRANSMIT", + OutTemp => EMAC1CLIENTTXRETRANSMIT_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATS, + GlitchData => EMAC1CLIENTTXSTATS_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATS", + OutTemp => EMAC1CLIENTTXSTATS_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATSBYTEVLD, + GlitchData => EMAC1CLIENTTXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATSBYTEVLD", + OutTemp => EMAC1CLIENTTXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATSVLD, + GlitchData => EMAC1CLIENTTXSTATSVLD_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATSVLD", + OutTemp => EMAC1CLIENTTXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYENCOMMAALIGN, + GlitchData => EMAC1PHYENCOMMAALIGN_GlitchData, + OutSignalName => "EMAC1PHYENCOMMAALIGN", + OutTemp => EMAC1PHYENCOMMAALIGN_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYLOOPBACKMSB, + GlitchData => EMAC1PHYLOOPBACKMSB_GlitchData, + OutSignalName => "EMAC1PHYLOOPBACKMSB", + OutTemp => EMAC1PHYLOOPBACKMSB_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMCLKOUT, + GlitchData => EMAC1PHYMCLKOUT_GlitchData, + OutSignalName => "EMAC1PHYMCLKOUT", + OutTemp => EMAC1PHYMCLKOUT_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMDOUT, + GlitchData => EMAC1PHYMDOUT_GlitchData, + OutSignalName => "EMAC1PHYMDOUT", + OutTemp => EMAC1PHYMDOUT_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMDTRI, + GlitchData => EMAC1PHYMDTRI_GlitchData, + OutSignalName => "EMAC1PHYMDTRI", + OutTemp => EMAC1PHYMDTRI_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMGTRXRESET, + GlitchData => EMAC1PHYMGTRXRESET_GlitchData, + OutSignalName => "EMAC1PHYMGTRXRESET", + OutTemp => EMAC1PHYMGTRXRESET_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMGTTXRESET, + GlitchData => EMAC1PHYMGTTXRESET_GlitchData, + OutSignalName => "EMAC1PHYMGTTXRESET", + OutTemp => EMAC1PHYMGTTXRESET_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYPOWERDOWN, + GlitchData => EMAC1PHYPOWERDOWN_GlitchData, + OutSignalName => "EMAC1PHYPOWERDOWN", + OutTemp => EMAC1PHYPOWERDOWN_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYSYNCACQSTATUS, + GlitchData => EMAC1PHYSYNCACQSTATUS_GlitchData, + OutSignalName => "EMAC1PHYSYNCACQSTATUS", + OutTemp => EMAC1PHYSYNCACQSTATUS_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARDISPMODE, + GlitchData => EMAC1PHYTXCHARDISPMODE_GlitchData, + OutSignalName => "EMAC1PHYTXCHARDISPMODE", + OutTemp => EMAC1PHYTXCHARDISPMODE_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARDISPVAL, + GlitchData => EMAC1PHYTXCHARDISPVAL_GlitchData, + OutSignalName => "EMAC1PHYTXCHARDISPVAL", + OutTemp => EMAC1PHYTXCHARDISPVAL_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARISK, + GlitchData => EMAC1PHYTXCHARISK_GlitchData, + OutSignalName => "EMAC1PHYTXCHARISK", + OutTemp => EMAC1PHYTXCHARISK_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCLK, + GlitchData => EMAC1PHYTXCLK_GlitchData, + OutSignalName => "EMAC1PHYTXCLK", + OutTemp => EMAC1PHYTXCLK_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(0), + GlitchData => EMAC1PHYTXD0_GlitchData, + OutSignalName => "EMAC1PHYTXD(0)", + OutTemp => EMAC1PHYTXD_OUT(0), + Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(1), + GlitchData => EMAC1PHYTXD1_GlitchData, + OutSignalName => "EMAC1PHYTXD(1)", + OutTemp => EMAC1PHYTXD_OUT(1), + Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(2), + GlitchData => EMAC1PHYTXD2_GlitchData, + OutSignalName => "EMAC1PHYTXD(2)", + OutTemp => EMAC1PHYTXD_OUT(2), + Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(3), + GlitchData => EMAC1PHYTXD3_GlitchData, + OutSignalName => "EMAC1PHYTXD(3)", + OutTemp => EMAC1PHYTXD_OUT(3), + Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(4), + GlitchData => EMAC1PHYTXD4_GlitchData, + OutSignalName => "EMAC1PHYTXD(4)", + OutTemp => EMAC1PHYTXD_OUT(4), + Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(5), + GlitchData => EMAC1PHYTXD5_GlitchData, + OutSignalName => "EMAC1PHYTXD(5)", + OutTemp => EMAC1PHYTXD_OUT(5), + Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(6), + GlitchData => EMAC1PHYTXD6_GlitchData, + OutSignalName => "EMAC1PHYTXD(6)", + OutTemp => EMAC1PHYTXD_OUT(6), + Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(7), + GlitchData => EMAC1PHYTXD7_GlitchData, + OutSignalName => "EMAC1PHYTXD(7)", + OutTemp => EMAC1PHYTXD_OUT(7), + Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXEN, + GlitchData => EMAC1PHYTXEN_GlitchData, + OutSignalName => "EMAC1PHYTXEN", + OutTemp => EMAC1PHYTXEN_OUT, + Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXER, + GlitchData => EMAC1PHYTXER_GlitchData, + OutSignalName => "EMAC1PHYTXER", + OutTemp => EMAC1PHYTXER_OUT, + Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTMIIMRDY, + GlitchData => HOSTMIIMRDY_GlitchData, + OutSignalName => "HOSTMIIMRDY", + OutTemp => HOSTMIIMRDY_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(0), + GlitchData => HOSTRDDATA0_GlitchData, + OutSignalName => "HOSTRDDATA(0)", + OutTemp => HOSTRDDATA_OUT(0), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(1), + GlitchData => HOSTRDDATA1_GlitchData, + OutSignalName => "HOSTRDDATA(1)", + OutTemp => HOSTRDDATA_OUT(1), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(2), + GlitchData => HOSTRDDATA2_GlitchData, + OutSignalName => "HOSTRDDATA(2)", + OutTemp => HOSTRDDATA_OUT(2), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(3), + GlitchData => HOSTRDDATA3_GlitchData, + OutSignalName => "HOSTRDDATA(3)", + OutTemp => HOSTRDDATA_OUT(3), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(4), + GlitchData => HOSTRDDATA4_GlitchData, + OutSignalName => "HOSTRDDATA(4)", + OutTemp => HOSTRDDATA_OUT(4), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(5), + GlitchData => HOSTRDDATA5_GlitchData, + OutSignalName => "HOSTRDDATA(5)", + OutTemp => HOSTRDDATA_OUT(5), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(6), + GlitchData => HOSTRDDATA6_GlitchData, + OutSignalName => "HOSTRDDATA(6)", + OutTemp => HOSTRDDATA_OUT(6), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(7), + GlitchData => HOSTRDDATA7_GlitchData, + OutSignalName => "HOSTRDDATA(7)", + OutTemp => HOSTRDDATA_OUT(7), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(8), + GlitchData => HOSTRDDATA8_GlitchData, + OutSignalName => "HOSTRDDATA(8)", + OutTemp => HOSTRDDATA_OUT(8), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(9), + GlitchData => HOSTRDDATA9_GlitchData, + OutSignalName => "HOSTRDDATA(9)", + OutTemp => HOSTRDDATA_OUT(9), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(10), + GlitchData => HOSTRDDATA10_GlitchData, + OutSignalName => "HOSTRDDATA(10)", + OutTemp => HOSTRDDATA_OUT(10), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(11), + GlitchData => HOSTRDDATA11_GlitchData, + OutSignalName => "HOSTRDDATA(11)", + OutTemp => HOSTRDDATA_OUT(11), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(12), + GlitchData => HOSTRDDATA12_GlitchData, + OutSignalName => "HOSTRDDATA(12)", + OutTemp => HOSTRDDATA_OUT(12), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(13), + GlitchData => HOSTRDDATA13_GlitchData, + OutSignalName => "HOSTRDDATA(13)", + OutTemp => HOSTRDDATA_OUT(13), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(14), + GlitchData => HOSTRDDATA14_GlitchData, + OutSignalName => "HOSTRDDATA(14)", + OutTemp => HOSTRDDATA_OUT(14), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(15), + GlitchData => HOSTRDDATA15_GlitchData, + OutSignalName => "HOSTRDDATA(15)", + OutTemp => HOSTRDDATA_OUT(15), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(16), + GlitchData => HOSTRDDATA16_GlitchData, + OutSignalName => "HOSTRDDATA(16)", + OutTemp => HOSTRDDATA_OUT(16), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(17), + GlitchData => HOSTRDDATA17_GlitchData, + OutSignalName => "HOSTRDDATA(17)", + OutTemp => HOSTRDDATA_OUT(17), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(18), + GlitchData => HOSTRDDATA18_GlitchData, + OutSignalName => "HOSTRDDATA(18)", + OutTemp => HOSTRDDATA_OUT(18), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(19), + GlitchData => HOSTRDDATA19_GlitchData, + OutSignalName => "HOSTRDDATA(19)", + OutTemp => HOSTRDDATA_OUT(19), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(20), + GlitchData => HOSTRDDATA20_GlitchData, + OutSignalName => "HOSTRDDATA(20)", + OutTemp => HOSTRDDATA_OUT(20), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(21), + GlitchData => HOSTRDDATA21_GlitchData, + OutSignalName => "HOSTRDDATA(21)", + OutTemp => HOSTRDDATA_OUT(21), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(22), + GlitchData => HOSTRDDATA22_GlitchData, + OutSignalName => "HOSTRDDATA(22)", + OutTemp => HOSTRDDATA_OUT(22), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(23), + GlitchData => HOSTRDDATA23_GlitchData, + OutSignalName => "HOSTRDDATA(23)", + OutTemp => HOSTRDDATA_OUT(23), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(24), + GlitchData => HOSTRDDATA24_GlitchData, + OutSignalName => "HOSTRDDATA(24)", + OutTemp => HOSTRDDATA_OUT(24), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(25), + GlitchData => HOSTRDDATA25_GlitchData, + OutSignalName => "HOSTRDDATA(25)", + OutTemp => HOSTRDDATA_OUT(25), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(26), + GlitchData => HOSTRDDATA26_GlitchData, + OutSignalName => "HOSTRDDATA(26)", + OutTemp => HOSTRDDATA_OUT(26), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(27), + GlitchData => HOSTRDDATA27_GlitchData, + OutSignalName => "HOSTRDDATA(27)", + OutTemp => HOSTRDDATA_OUT(27), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(28), + GlitchData => HOSTRDDATA28_GlitchData, + OutSignalName => "HOSTRDDATA(28)", + OutTemp => HOSTRDDATA_OUT(28), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(29), + GlitchData => HOSTRDDATA29_GlitchData, + OutSignalName => "HOSTRDDATA(29)", + OutTemp => HOSTRDDATA_OUT(29), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(30), + GlitchData => HOSTRDDATA30_GlitchData, + OutSignalName => "HOSTRDDATA(30)", + OutTemp => HOSTRDDATA_OUT(30), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(31), + GlitchData => HOSTRDDATA31_GlitchData, + OutSignalName => "HOSTRDDATA(31)", + OutTemp => HOSTRDDATA_OUT(31), + Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + +-- Wait signal (input/output pins) + wait on + CLIENTEMAC0DCMLOCKED_ipd, + CLIENTEMAC0PAUSEREQ_ipd, + CLIENTEMAC0PAUSEVAL_ipd, + CLIENTEMAC0RXCLIENTCLKIN_ipd, + CLIENTEMAC0TXCLIENTCLKIN_ipd, + CLIENTEMAC0TXD_client16_delay, + CLIENTEMAC0TXDVLD_client16_delay, + CLIENTEMAC0TXDVLDMSW_client16_delay, + CLIENTEMAC0TXFIRSTBYTE_ipd, + CLIENTEMAC0TXGMIIMIICLKIN_ipd, + CLIENTEMAC0TXIFGDELAY_ipd, + CLIENTEMAC0TXUNDERRUN_ipd, + CLIENTEMAC1DCMLOCKED_ipd, + CLIENTEMAC1PAUSEREQ_ipd, + CLIENTEMAC1PAUSEVAL_ipd, + CLIENTEMAC1RXCLIENTCLKIN_ipd, + CLIENTEMAC1TXCLIENTCLKIN_ipd, + CLIENTEMAC1TXD_client16_delay, + CLIENTEMAC1TXDVLD_client16_delay, + CLIENTEMAC1TXDVLDMSW_client16_delay, + CLIENTEMAC1TXFIRSTBYTE_ipd, + CLIENTEMAC1TXGMIIMIICLKIN_ipd, + CLIENTEMAC1TXIFGDELAY_ipd, + CLIENTEMAC1TXUNDERRUN_ipd, + DCREMACENABLE_ipd, + DCRHOSTDONEIR_OUT, + EMAC0CLIENTANINTERRUPT_OUT, + EMAC0CLIENTRXBADFRAME_OUT, + EMAC0CLIENTRXCLIENTCLKOUT_OUT, + EMAC0CLIENTRXD_OUT, + EMAC0CLIENTRXDVLD_OUT, + EMAC0CLIENTRXDVLDMSW_OUT, + EMAC0CLIENTRXDVREG6_OUT, + EMAC0CLIENTRXFRAMEDROP_OUT, + EMAC0CLIENTRXGOODFRAME_OUT, + EMAC0CLIENTRXSTATS_OUT, + EMAC0CLIENTRXSTATSBYTEVLD_OUT, + EMAC0CLIENTRXSTATSVLD_OUT, + EMAC0CLIENTTXACK_OUT, + EMAC0CLIENTTXCLIENTCLKOUT_OUT, + EMAC0CLIENTTXCOLLISION_OUT, + EMAC0CLIENTTXGMIIMIICLKOUT_OUT, + EMAC0CLIENTTXRETRANSMIT_OUT, + EMAC0CLIENTTXSTATS_OUT, + EMAC0CLIENTTXSTATSBYTEVLD_OUT, + EMAC0CLIENTTXSTATSVLD_OUT, + EMAC0PHYENCOMMAALIGN_OUT, + EMAC0PHYLOOPBACKMSB_OUT, + EMAC0PHYMCLKOUT_OUT, + EMAC0PHYMDOUT_OUT, + EMAC0PHYMDTRI_OUT, + EMAC0PHYMGTRXRESET_OUT, + EMAC0PHYMGTTXRESET_OUT, + EMAC0PHYPOWERDOWN_OUT, + EMAC0PHYSYNCACQSTATUS_OUT, + EMAC0PHYTXCHARDISPMODE_OUT, + EMAC0PHYTXCHARDISPVAL_OUT, + EMAC0PHYTXCHARISK_OUT, + EMAC0PHYTXCLK_OUT, + EMAC0PHYTXD_OUT, + EMAC0PHYTXEN_OUT, + EMAC0PHYTXER_OUT, + EMAC1CLIENTANINTERRUPT_OUT, + EMAC1CLIENTRXBADFRAME_OUT, + EMAC1CLIENTRXCLIENTCLKOUT_OUT, + EMAC1CLIENTRXD_OUT, + EMAC1CLIENTRXDVLD_OUT, + EMAC1CLIENTRXDVLDMSW_OUT, + EMAC1CLIENTRXDVREG6_OUT, + EMAC1CLIENTRXFRAMEDROP_OUT, + EMAC1CLIENTRXGOODFRAME_OUT, + EMAC1CLIENTRXSTATS_OUT, + EMAC1CLIENTRXSTATSBYTEVLD_OUT, + EMAC1CLIENTRXSTATSVLD_OUT, + EMAC1CLIENTTXACK_OUT, + EMAC1CLIENTTXCLIENTCLKOUT_OUT, + EMAC1CLIENTTXCOLLISION_OUT, + EMAC1CLIENTTXGMIIMIICLKOUT_OUT, + EMAC1CLIENTTXRETRANSMIT_OUT, + EMAC1CLIENTTXSTATS_OUT, + EMAC1CLIENTTXSTATSBYTEVLD_OUT, + EMAC1CLIENTTXSTATSVLD_OUT, + EMAC1PHYENCOMMAALIGN_OUT, + EMAC1PHYLOOPBACKMSB_OUT, + EMAC1PHYMCLKOUT_OUT, + EMAC1PHYMDOUT_OUT, + EMAC1PHYMDTRI_OUT, + EMAC1PHYMGTRXRESET_OUT, + EMAC1PHYMGTTXRESET_OUT, + EMAC1PHYPOWERDOWN_OUT, + EMAC1PHYSYNCACQSTATUS_OUT, + EMAC1PHYTXCHARDISPMODE_OUT, + EMAC1PHYTXCHARDISPVAL_OUT, + EMAC1PHYTXCHARISK_OUT, + EMAC1PHYTXCLK_OUT, + EMAC1PHYTXD_OUT, + EMAC1PHYTXEN_OUT, + EMAC1PHYTXER_OUT, + HOSTADDR_ipd, + HOSTCLK_ipd, + HOSTEMAC1SEL_ipd, + HOSTMIIMRDY_OUT, + HOSTMIIMSEL_ipd, + HOSTOPCODE_ipd, + HOSTRDDATA_OUT, + HOSTREQ_ipd, + HOSTWRDATA_ipd, + PHYEMAC0COL_ipd, + PHYEMAC0CRS_ipd, + PHYEMAC0GTXCLK_ipd, + PHYEMAC0MCLKIN_ipd, + PHYEMAC0MDIN_ipd, + PHYEMAC0MIITXCLK_skewed, + PHYEMAC0PHYAD_ipd, + PHYEMAC0RXBUFERR_ipd, + PHYEMAC0RXBUFSTATUS_ipd, + PHYEMAC0RXCHARISCOMMA_ipd, + PHYEMAC0RXCHARISK_ipd, + PHYEMAC0RXCHECKINGCRC_ipd, + PHYEMAC0RXCLK_ipd, + PHYEMAC0RXCLKCORCNT_ipd, + PHYEMAC0RXCOMMADET_ipd, + PHYEMAC0RXD_ipd, + PHYEMAC0RXDISPERR_ipd, + PHYEMAC0RXDV_ipd, + PHYEMAC0RXER_ipd, + PHYEMAC0RXLOSSOFSYNC_ipd, + PHYEMAC0RXNOTINTABLE_ipd, + PHYEMAC0RXRUNDISP_ipd, + PHYEMAC0SIGNALDET_ipd, + PHYEMAC0TXBUFERR_ipd, + PHYEMAC1COL_ipd, + PHYEMAC1CRS_ipd, + PHYEMAC1GTXCLK_ipd, + PHYEMAC1MCLKIN_ipd, + PHYEMAC1MDIN_ipd, + PHYEMAC1MIITXCLK_skewed, + PHYEMAC1PHYAD_ipd, + PHYEMAC1RXBUFERR_ipd, + PHYEMAC1RXBUFSTATUS_ipd, + PHYEMAC1RXCHARISCOMMA_ipd, + PHYEMAC1RXCHARISK_ipd, + PHYEMAC1RXCHECKINGCRC_ipd, + PHYEMAC1RXCLK_ipd, + PHYEMAC1RXCLKCORCNT_ipd, + PHYEMAC1RXCOMMADET_ipd, + PHYEMAC1RXD_ipd, + PHYEMAC1RXDISPERR_ipd, + PHYEMAC1RXDV_ipd, + PHYEMAC1RXER_ipd, + PHYEMAC1RXLOSSOFSYNC_ipd, + PHYEMAC1RXNOTINTABLE_ipd, + PHYEMAC1RXRUNDISP_ipd, + PHYEMAC1SIGNALDET_ipd, + PHYEMAC1TXBUFERR_ipd, + RESET_ipd, + TIEEMAC0CONFIGVEC_ipd, + TIEEMAC0UNICASTADDR_ipd, + TIEEMAC1CONFIGVEC_ipd, + TIEEMAC1UNICASTADDR_ipd, + DCREMACWRITE_ipd, + DCREMACREAD_ipd, + DCREMACDBUS_ipd, + DCREMACABUS_ipd, + DCREMACCLK_ipd, + EMACDCRDBUS_OUT, + EMACDCRACK_OUT; + + end process TIMING; + + + +end EMAC_V; +----- CELL GT11_CUSTOM ----- +------------------------------------------------------------------------------- +-- Copyright (c) 1995-2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 11-Gigabit Transceiver for High-Speed I/O CUSTOM Simulation Model +-- /___/ /\ Filename : GT11_CUSTOM.vhd +-- \ \ / \ Timestamp : Fri Jun 18 10:57:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 05/16/05 - Changed default values for some parameters and removed two parameters. Fixed CR#207101. +-- 08/08/05 - Changed default parameter values for some parameters (CR 214282). +-- 02/28/06 - CR#226322 - Addition of new parameters and change of default values for some parameters. +-- End Revision + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT11_CUSTOM is +generic ( + ALIGN_COMMA_WORD : integer := 4; + BANDGAPSEL : boolean := FALSE; + BIASRESSEL : boolean := FALSE; + CCCB_ARBITRATOR_DISABLE : boolean := FALSE; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "NONE"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_MASK : bit_vector := "1110"; + CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "1110"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 1; + CLK_CORRECT_USE : boolean := FALSE; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 48; + CLK_COR_MIN_LAT : integer := 36; + CLK_COR_SEQ_1_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_MASK : bit_vector := "1110"; + CLK_COR_SEQ_2_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_MASK : bit_vector := "1110"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 1; + COMMA32 : boolean := FALSE; + COMMA_10B_MASK : bit_vector := X"3FF"; + CYCLE_LIMIT_SEL : bit_vector := "00"; + DCDR_FILTER : bit_vector := "010"; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + DIGRX_FWDCLK : bit_vector := "00"; + DIGRX_SYNC_MODE : boolean := FALSE; + ENABLE_DCDR : boolean := FALSE; + FDET_HYS_CAL : bit_vector := "010"; + FDET_HYS_SEL : bit_vector := "100"; + FDET_LCK_CAL : bit_vector := "100"; + FDET_LCK_SEL : bit_vector := "001"; + IREFBIASMODE : bit_vector := "11"; + LOOPCAL_WAIT : bit_vector := "00"; + MCOMMA_32B_VALUE : bit_vector := X"00000000"; + MCOMMA_DETECT : boolean := TRUE; + OPPOSITE_SELECT : boolean := FALSE; + PCOMMA_32B_VALUE : bit_vector := X"00000000"; + PCOMMA_DETECT : boolean := TRUE; + PCS_BIT_SLIP : boolean := FALSE; + PMACLKENABLE : boolean := TRUE; + PMACOREPWRENABLE : boolean := TRUE; + PMAIREFTRIM : bit_vector := "0111"; + PMAVBGCTRL : bit_vector := "00000"; + PMAVREFTRIM : bit_vector := "0111"; + PMA_BIT_SLIP : boolean := FALSE; + POWER_ENABLE : boolean := TRUE; + REPEATER : boolean := FALSE; + RXACTST : boolean := FALSE; + RXAFEEQ : bit_vector := "000000000"; + RXAFEPD : boolean := FALSE; + RXAFETST : boolean := FALSE; + RXAPD : boolean := FALSE; + RXAREGCTRL : bit_vector := "00000"; + RXASYNCDIVIDE : bit_vector := "11"; + RXBY_32 : boolean := FALSE; + RXCDRLOS : bit_vector := "000000"; + RXCLK0_FORCE_PMACLK : boolean := FALSE; + RXCLKMODE : bit_vector := "110001"; + RXCLMODE : bit_vector := "00"; + RXCMADJ : bit_vector := "01"; + RXCPSEL : boolean := TRUE; + RXCPTST : boolean := FALSE; + RXCRCCLOCKDOUBLE : boolean := FALSE; + RXCRCENABLE : boolean := FALSE; + RXCRCINITVAL : bit_vector := X"00000000"; + RXCRCINVERTGEN : boolean := FALSE; + RXCRCSAMECLOCK : boolean := FALSE; + RXCTRL1 : bit_vector := X"200"; + RXCYCLE_LIMIT_SEL : bit_vector := "00"; + RXDATA_SEL : bit_vector := "00"; + RXDCCOUPLE : boolean := FALSE; + RXDIGRESET : boolean := FALSE; + RXDIGRX : boolean := FALSE; + RXEQ : bit_vector := X"4000000000000000"; + RXFDCAL_CLOCK_DIVIDE : string := "NONE"; + RXFDET_HYS_CAL : bit_vector := "010"; + RXFDET_HYS_SEL : bit_vector := "100"; + RXFDET_LCK_CAL : bit_vector := "100"; + RXFDET_LCK_SEL : bit_vector := "001"; + RXFECONTROL1 : bit_vector := "00"; + RXFECONTROL2 : bit_vector := "000"; + RXFETUNE : bit_vector := "01"; + RXLB : boolean := FALSE; + RXLKADJ : bit_vector := "00000"; + RXLKAPD : boolean := FALSE; + RXLOOPCAL_WAIT : bit_vector := "00"; + RXLOOPFILT : bit_vector := "0111"; + RXMODE : bit_vector := "000000"; + RXOUTDIV2SEL : integer := 1; + RXPD : boolean := FALSE; + RXPDDTST : boolean := TRUE; + RXPLLNDIVSEL : integer := 8; + RXPMACLKSEL : string := "REFCLK1"; + RXRCPADJ : bit_vector := "011"; + RXRCPPD : boolean := FALSE; + RXRECCLK1_USE_SYNC : boolean := FALSE; + RXRIBADJ : bit_vector := "11"; + RXRPDPD : boolean := FALSE; + RXRSDPD : boolean := FALSE; + RXSLOWDOWN_CAL : bit_vector := "00"; + RXTUNE : bit_vector := X"0000"; + RXUSRDIVISOR : integer := 1; + RXVCODAC_INIT : bit_vector := "1010000000"; + RXVCO_CTRL_ENABLE : boolean := FALSE; + RX_BUFFER_USE : boolean := TRUE; + RX_CLOCK_DIVIDER : bit_vector := "00"; + SAMPLE_8X : boolean := FALSE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + SLOWDOWN_CAL : bit_vector := "00"; + TXABPMACLKSEL : string := "REFCLK1"; + TXAPD : boolean := FALSE; + TXAREFBIASSEL : boolean := TRUE; + TXASYNCDIVIDE : bit_vector := "11"; + TXCLK0_FORCE_PMACLK : boolean := FALSE; + TXCLKMODE : bit_vector := "1001"; + TXCLMODE : bit_vector := "00"; + TXCPSEL : boolean := TRUE; + TXCRCCLOCKDOUBLE : boolean := FALSE; + TXCRCENABLE : boolean := FALSE; + TXCRCINITVAL : bit_vector := X"00000000"; + TXCRCINVERTGEN : boolean := FALSE; + TXCRCSAMECLOCK : boolean := FALSE; + TXCTRL1 : bit_vector := X"200"; + TXDATA_SEL : bit_vector := "00"; + TXDAT_PRDRV_DAC : bit_vector := "111"; + TXDAT_TAP_DAC : bit_vector := "10110"; + TXDIGPD : boolean := FALSE; + TXFDCAL_CLOCK_DIVIDE : string := "NONE"; + TXHIGHSIGNALEN : boolean := TRUE; + TXLOOPFILT : bit_vector := "0111"; + TXLVLSHFTPD : boolean := FALSE; + TXOUTCLK1_USE_SYNC : boolean := FALSE; + TXOUTDIV2SEL : integer := 1; + TXPD : boolean := FALSE; + TXPHASESEL : boolean := FALSE; + TXPLLNDIVSEL : integer := 8; + TXPOST_PRDRV_DAC : bit_vector := "111"; + TXPOST_TAP_DAC : bit_vector := "01110"; + TXPOST_TAP_PD : boolean := TRUE; + TXPRE_PRDRV_DAC : bit_vector := "111"; + TXPRE_TAP_DAC : bit_vector := "00000"; + TXPRE_TAP_PD : boolean := TRUE; + TXSLEWRATE : boolean := FALSE; + TXTERMTRIM : bit_vector := "1100"; + TXTUNE : bit_vector := X"0000"; + TX_BUFFER_USE : boolean := TRUE; + TX_CLOCK_DIVIDER : bit_vector := "00"; + VCODAC_INIT : bit_vector := "1010000000"; + VCO_CTRL_ENABLE : boolean := FALSE; + VREFBIASMODE : bit_vector := "11" + + + ); + +port ( + CHBONDO : out std_logic_vector(4 downto 0); + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + RXBUFERR : out std_ulogic; + RXCALFAIL : out std_ulogic; + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCOUT : out std_logic_vector(31 downto 0); + RXCYCLELIMIT : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDISPERR : out std_logic_vector(7 downto 0); + RXLOCK : out std_ulogic; + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXMCLK : out std_ulogic; + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXPCSHCLKOUT : out std_ulogic; + RXREALIGN : out std_ulogic; + RXRECCLK1 : out std_ulogic; + RXRECCLK2 : out std_ulogic; + RXRUNDISP : out std_logic_vector(7 downto 0); + RXSIGDET : out std_ulogic; + RXSTATUS : out std_logic_vector(5 downto 0); + TX1N : out std_ulogic; + TX1P : out std_ulogic; + TXBUFERR : out std_ulogic; + TXCALFAIL : out std_ulogic; + TXCRCOUT : out std_logic_vector(31 downto 0); + TXCYCLELIMIT : out std_ulogic; + TXKERR : out std_logic_vector(7 downto 0); + TXLOCK : out std_ulogic; + TXOUTCLK1 : out std_ulogic; + TXOUTCLK2 : out std_ulogic; + TXPCSHCLKOUT : out std_ulogic; + TXRUNDISP : out std_logic_vector(7 downto 0); + + CHBONDI : in std_logic_vector(4 downto 0); + DADDR : in std_logic_vector(7 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + GREFCLK : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK1 : in std_ulogic; + REFCLK2 : in std_ulogic; + RX1N : in std_ulogic; + RX1P : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCLKSTABLE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXCRCCLK : in std_ulogic; + RXCRCDATAVALID : in std_ulogic; + RXCRCDATAWIDTH : in std_logic_vector(2 downto 0); + RXCRCIN : in std_logic_vector(63 downto 0); + RXCRCINIT : in std_ulogic; + RXCRCINTCLK : in std_ulogic; + RXCRCPD : in std_ulogic; + RXCRCRESET : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXPMARESET : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXSYNC : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(7 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXCLKSTABLE : in std_ulogic; + TXCRCCLK : in std_ulogic; + TXCRCDATAVALID : in std_ulogic; + TXCRCDATAWIDTH : in std_logic_vector(2 downto 0); + TXCRCIN : in std_logic_vector(63 downto 0); + TXCRCINIT : in std_ulogic; + TXCRCINTCLK : in std_ulogic; + TXCRCPD : in std_ulogic; + TXCRCRESET : in std_ulogic; + TXDATA : in std_logic_vector(63 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXENOOB : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPMARESET : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXSYNC : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT11_CUSTOM; + +-- Architecture body -- + +architecture GT11_CUSTOM_V of GT11_CUSTOM is + +signal z16 : std_logic_vector(15 downto 0) := "0000000000000000"; +signal OPEN16 : std_logic_vector(15 downto 0); + +begin + + +-- GT11 Instatiation (port map, generic map) +GT11_inst : GT11 + generic map ( + GT11_MODE => "SINGLE", + CHAN_BOND_SEQ_1_1 => CHAN_BOND_SEQ_1_1, + CHAN_BOND_SEQ_1_2 => CHAN_BOND_SEQ_1_2, + CHAN_BOND_SEQ_1_3 => CHAN_BOND_SEQ_1_3, + CHAN_BOND_SEQ_1_4 => CHAN_BOND_SEQ_1_4, + CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, + CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, + CHAN_BOND_MODE => CHAN_BOND_MODE, + CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, + CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, + CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, + RX_BUFFER_USE => RX_BUFFER_USE, + TX_BUFFER_USE => TX_BUFFER_USE, + CHAN_BOND_SEQ_2_1 => CHAN_BOND_SEQ_2_1, + CHAN_BOND_SEQ_2_2 => CHAN_BOND_SEQ_2_2, + CHAN_BOND_SEQ_2_3 => CHAN_BOND_SEQ_2_3, + CHAN_BOND_SEQ_2_4 => CHAN_BOND_SEQ_2_4, + CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, + POWER_ENABLE => POWER_ENABLE, + OPPOSITE_SELECT => OPPOSITE_SELECT, + CCCB_ARBITRATOR_DISABLE => CCCB_ARBITRATOR_DISABLE, + CLK_COR_SEQ_1_1 => CLK_COR_SEQ_1_1, + CLK_COR_SEQ_1_2 => CLK_COR_SEQ_1_2, + CLK_COR_SEQ_1_3 => CLK_COR_SEQ_1_3, + CLK_COR_SEQ_1_4 => CLK_COR_SEQ_1_4, + CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, + DIGRX_SYNC_MODE => DIGRX_SYNC_MODE, + DIGRX_FWDCLK => DIGRX_FWDCLK, + PCS_BIT_SLIP => PCS_BIT_SLIP, + CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, + TXDATA_SEL => TXDATA_SEL, + RXDATA_SEL => RXDATA_SEL, + CLK_COR_SEQ_2_1 => CLK_COR_SEQ_2_1, + CLK_COR_SEQ_2_2 => CLK_COR_SEQ_2_2, + CLK_COR_SEQ_2_3 => CLK_COR_SEQ_2_3, + CLK_COR_SEQ_2_4 => CLK_COR_SEQ_2_4, + CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, + CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, + CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, + CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, + CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, + CLK_CORRECT_USE => CLK_CORRECT_USE, + CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, + SH_CNT_MAX => SH_CNT_MAX, + SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX, + ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, + DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, + DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, + DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, + MCOMMA_DETECT => MCOMMA_DETECT, + PCOMMA_DETECT => PCOMMA_DETECT, + COMMA32 => COMMA32, + COMMA_10B_MASK => COMMA_10B_MASK, + MCOMMA_32B_VALUE => MCOMMA_32B_VALUE, + PCOMMA_32B_VALUE => PCOMMA_32B_VALUE, + RXUSRDIVISOR => RXUSRDIVISOR, + DCDR_FILTER => DCDR_FILTER, + SAMPLE_8X => SAMPLE_8X, + ENABLE_DCDR => ENABLE_DCDR, + REPEATER => REPEATER, + RXBY_32 => RXBY_32, + TXFDCAL_CLOCK_DIVIDE => TXFDCAL_CLOCK_DIVIDE, + RXFDCAL_CLOCK_DIVIDE => RXFDCAL_CLOCK_DIVIDE, + RXCYCLE_LIMIT_SEL => RXCYCLE_LIMIT_SEL, + RXVCO_CTRL_ENABLE => RXVCO_CTRL_ENABLE, + RXFDET_LCK_SEL => RXFDET_LCK_SEL, + RXFDET_HYS_SEL => RXFDET_HYS_SEL, + RXFDET_LCK_CAL => RXFDET_LCK_CAL, + RXFDET_HYS_CAL => RXFDET_HYS_CAL, + RXLOOPCAL_WAIT => RXLOOPCAL_WAIT, + RXSLOWDOWN_CAL => RXSLOWDOWN_CAL, + RXVCODAC_INIT => RXVCODAC_INIT, + CYCLE_LIMIT_SEL => CYCLE_LIMIT_SEL, + VCO_CTRL_ENABLE => VCO_CTRL_ENABLE, + FDET_LCK_SEL => FDET_LCK_SEL, + FDET_HYS_SEL => FDET_HYS_SEL, + FDET_LCK_CAL => FDET_LCK_CAL, + FDET_HYS_CAL => FDET_HYS_CAL, + LOOPCAL_WAIT => LOOPCAL_WAIT, + SLOWDOWN_CAL => SLOWDOWN_CAL, + VCODAC_INIT => VCODAC_INIT, + RXCRCCLOCKDOUBLE => RXCRCCLOCKDOUBLE, + RXCRCINVERTGEN => RXCRCINVERTGEN, + RXCRCSAMECLOCK => RXCRCSAMECLOCK, + RXCRCENABLE => RXCRCENABLE, + RXCRCINITVAL => RXCRCINITVAL, + TXCRCCLOCKDOUBLE => TXCRCCLOCKDOUBLE, + TXCRCINVERTGEN => TXCRCINVERTGEN, + TXCRCSAMECLOCK => TXCRCSAMECLOCK, + TXCRCINITVAL => TXCRCINITVAL, + TXCRCENABLE => TXCRCENABLE, + RX_CLOCK_DIVIDER => RX_CLOCK_DIVIDER, + TX_CLOCK_DIVIDER => TX_CLOCK_DIVIDER, + RXCLK0_FORCE_PMACLK => RXCLK0_FORCE_PMACLK, + TXCLK0_FORCE_PMACLK => TXCLK0_FORCE_PMACLK, + TXOUTCLK1_USE_SYNC => TXOUTCLK1_USE_SYNC, + RXRECCLK1_USE_SYNC => RXRECCLK1_USE_SYNC, + RXPMACLKSEL => RXPMACLKSEL, + TXABPMACLKSEL => TXABPMACLKSEL, + RXAREGCTRL => RXAREGCTRL, + PMAVBGCTRL => PMAVBGCTRL, + BANDGAPSEL => BANDGAPSEL, + PMAIREFTRIM => PMAIREFTRIM, + IREFBIASMODE => IREFBIASMODE, + BIASRESSEL => BIASRESSEL, + PMAVREFTRIM => PMAVREFTRIM, + VREFBIASMODE => VREFBIASMODE, + TXPHASESEL => TXPHASESEL, + PMACLKENABLE => PMACLKENABLE, + PMACOREPWRENABLE => PMACOREPWRENABLE, + RXMODE => RXMODE, + PMA_BIT_SLIP => PMA_BIT_SLIP, + RXASYNCDIVIDE => RXASYNCDIVIDE, + RXCLKMODE => RXCLKMODE, + RXLB => RXLB, + RXFETUNE => RXFETUNE, + RXRCPADJ => RXRCPADJ, + RXRIBADJ => RXRIBADJ, + RXAFEEQ => RXAFEEQ, + RXCMADJ => RXCMADJ, + RXCDRLOS => RXCDRLOS, + RXDCCOUPLE => RXDCCOUPLE, + RXLKADJ => RXLKADJ, + RXDIGRESET => RXDIGRESET, + RXFECONTROL2 => RXFECONTROL2, + RXCPTST => RXCPTST, + RXPDDTST => RXPDDTST, + RXACTST => RXACTST, + RXAFETST => RXAFETST, + RXFECONTROL1 => RXFECONTROL1, + RXLKAPD => RXLKAPD, + RXRSDPD => RXRSDPD, + RXRCPPD => RXRCPPD, + RXRPDPD => RXRPDPD, + RXAFEPD => RXAFEPD, + RXPD => RXPD, + RXEQ => RXEQ, + TXOUTDIV2SEL => TXOUTDIV2SEL, + TXPLLNDIVSEL => TXPLLNDIVSEL, + TXCLMODE => TXCLMODE, + TXLOOPFILT => TXLOOPFILT, + TXTUNE => TXTUNE, + TXCPSEL => TXCPSEL, + TXCTRL1 => TXCTRL1, + TXAPD => TXAPD, + TXLVLSHFTPD => TXLVLSHFTPD, + TXPRE_PRDRV_DAC => TXPRE_PRDRV_DAC, + TXPRE_TAP_PD => TXPRE_TAP_PD, + TXPRE_TAP_DAC => TXPRE_TAP_DAC, + TXDIGPD => TXDIGPD, + TXCLKMODE => TXCLKMODE, + TXHIGHSIGNALEN => TXHIGHSIGNALEN, + TXAREFBIASSEL => TXAREFBIASSEL, + TXTERMTRIM => TXTERMTRIM, + TXASYNCDIVIDE => TXASYNCDIVIDE, + TXSLEWRATE => TXSLEWRATE, + TXPOST_PRDRV_DAC => TXPOST_PRDRV_DAC, + TXDAT_PRDRV_DAC => TXDAT_PRDRV_DAC, + TXPOST_TAP_PD => TXPOST_TAP_PD, + TXPOST_TAP_DAC => TXPOST_TAP_DAC, + TXDAT_TAP_DAC => TXDAT_TAP_DAC, + TXPD => TXPD, + RXOUTDIV2SEL => RXOUTDIV2SEL, + RXPLLNDIVSEL => RXPLLNDIVSEL, + RXCLMODE => RXCLMODE, + RXLOOPFILT => RXLOOPFILT, + RXDIGRX => RXDIGRX, + RXTUNE => RXTUNE, + RXCPSEL => RXCPSEL, + RXCTRL1 => RXCTRL1, + RXAPD => RXAPD +) +port map ( + COMBUSIN => z16, + COMBUSOUT => OPEN16, + CHBONDO => CHBONDO, + RXSTATUS => RXSTATUS, + RXCHARISCOMMA => RXCHARISCOMMA, + RXCHARISK => RXCHARISK, + RXCOMMADET => RXCOMMADET, + RXDATA => RXDATA, + RXDISPERR => RXDISPERR, + RXLOSSOFSYNC => RXLOSSOFSYNC, + RXNOTINTABLE => RXNOTINTABLE, + RXREALIGN => RXREALIGN, + RXRUNDISP => RXRUNDISP, + RXBUFERR => RXBUFERR, + TXBUFERR => TXBUFERR, + TXKERR => TXKERR, + TXRUNDISP => TXRUNDISP, + RXRECCLK1 => RXRECCLK1, + RXRECCLK2 => RXRECCLK2, + TXOUTCLK1 => TXOUTCLK1, + TXOUTCLK2 => TXOUTCLK2, + RXLOCK => RXLOCK, + TXLOCK => TXLOCK, + RXCYCLELIMIT => RXCYCLELIMIT, + TXCYCLELIMIT => TXCYCLELIMIT, + RXCALFAIL => RXCALFAIL, + TXCALFAIL => TXCALFAIL, + RXCRCOUT => RXCRCOUT, + TXCRCOUT => TXCRCOUT, + RXSIGDET => RXSIGDET, + DRDY => DRDY, + DO => DO, + CHBONDI => CHBONDI, + ENCHANSYNC => ENCHANSYNC, + ENMCOMMAALIGN => ENMCOMMAALIGN, + ENPCOMMAALIGN => ENPCOMMAALIGN, + LOOPBACK => LOOPBACK, + POWERDOWN => POWERDOWN, + RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, + RXCOMMADETUSE => RXCOMMADETUSE, + RXDATAWIDTH => RXDATAWIDTH, + RXDEC64B66BUSE => RXDEC64B66BUSE, + RXDEC8B10BUSE => RXDEC8B10BUSE, + RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, + RXIGNOREBTF => RXIGNOREBTF, + RXINTDATAWIDTH => RXINTDATAWIDTH, + RXPOLARITY => RXPOLARITY, + RXRESET => RXRESET, + RXSLIDE => RXSLIDE, + RXUSRCLK => RXUSRCLK, + RXUSRCLK2 => RXUSRCLK2, + TXBYPASS8B10B => TXBYPASS8B10B, + TXCHARDISPMODE => TXCHARDISPMODE, + TXCHARDISPVAL => TXCHARDISPVAL, + TXCHARISK => TXCHARISK, + TXDATA => TXDATA, + TXDATAWIDTH => TXDATAWIDTH, + TXENC64B66BUSE => TXENC64B66BUSE, + TXENC8B10BUSE => TXENC8B10BUSE, + TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, + TXINHIBIT => TXINHIBIT, + TXINTDATAWIDTH => TXINTDATAWIDTH, + TXPOLARITY => TXPOLARITY, + TXRESET => TXRESET, + TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK2 => TXUSRCLK2, + RXCLKSTABLE => RXCLKSTABLE, + RXPMARESET => RXPMARESET, + TXCLKSTABLE => TXCLKSTABLE, + TXPMARESET => TXPMARESET, + RXCRCIN => RXCRCIN, + RXCRCDATAWIDTH => RXCRCDATAWIDTH, + RXCRCDATAVALID => RXCRCDATAVALID, + RXCRCINIT => RXCRCINIT, + RXCRCRESET => RXCRCRESET, + RXCRCPD => RXCRCPD, + RXCRCCLK => RXCRCCLK, + RXCRCINTCLK => RXCRCINTCLK, + TXCRCIN => TXCRCIN, + TXCRCDATAWIDTH => TXCRCDATAWIDTH, + TXCRCDATAVALID => TXCRCDATAVALID, + TXCRCINIT => TXCRCINIT, + TXCRCRESET => TXCRCRESET, + TXCRCPD => TXCRCPD, + TXCRCCLK => TXCRCCLK, + TXCRCINTCLK => TXCRCINTCLK, + TXSYNC => TXSYNC, + RXSYNC => RXSYNC, + TXENOOB => TXENOOB, + DCLK => DCLK, + DADDR => DADDR, + DEN => DEN, + DWE => DWE, + DI => DI, + RXMCLK => RXMCLK, + TX1P => TX1P, + TX1N => TX1N, + RX1P => RX1P, + RX1N => RX1N, + GREFCLK => GREFCLK, + REFCLK1 => REFCLK1, + REFCLK2 => REFCLK2, + TXPCSHCLKOUT => TXPCSHCLKOUT, + RXPCSHCLKOUT => RXPCSHCLKOUT + +); + +end GT11_CUSTOM_V; +----- CELL GT11_DUAL ----- +------------------------------------------------------------------------------- +-- Copyright (c) 1995-2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 11-Gigabit Transceiver for High-Speed I/O DUAL Simulation Model +-- /___/ /\ Filename : GT11_DUAL.vhd +-- \ \ / \ Timestamp : Fri Jun 18 10:57:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 05/16/05 - Changed default values for some parameters and removed two parameters. Fixed CR#207101. +-- 09/06/05 - Fixed CR#215006. Attribute default values update. +-- 02/28/06 - CR#226322 - Addition of new parameters and change of default values for some parameters. +-- End Revision + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT11_DUAL is +generic ( + ALIGN_COMMA_WORD_A : integer := 4; + ALIGN_COMMA_WORD_B : integer := 4; + BANDGAPSEL_A : boolean := FALSE; + BANDGAPSEL_B : boolean := FALSE; + BIASRESSEL_A : boolean := FALSE; + BIASRESSEL_B : boolean := FALSE; + CCCB_ARBITRATOR_DISABLE_A : boolean := FALSE; + CCCB_ARBITRATOR_DISABLE_B : boolean := FALSE; + CHAN_BOND_LIMIT_A : integer := 16; + CHAN_BOND_LIMIT_B : integer := 16; + CHAN_BOND_MODE_A : string := "NONE"; + CHAN_BOND_MODE_B : string := "NONE"; + CHAN_BOND_ONE_SHOT_A : boolean := FALSE; + CHAN_BOND_ONE_SHOT_B : boolean := FALSE; + CHAN_BOND_SEQ_1_1_A : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_1_B : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_2_A : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_2_B : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_3_A : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_3_B : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_4_A : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_4_B : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_MASK_A : bit_vector := "1110"; + CHAN_BOND_SEQ_1_MASK_B : bit_vector := "1110"; + CHAN_BOND_SEQ_2_1_A : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_1_B : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_2_A : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_2_B : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_3_A : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_3_B : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_4_A : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_4_B : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_MASK_A : bit_vector := "1110"; + CHAN_BOND_SEQ_2_MASK_B : bit_vector := "1110"; + CHAN_BOND_SEQ_2_USE_A : boolean := FALSE; + CHAN_BOND_SEQ_2_USE_B : boolean := FALSE; + CHAN_BOND_SEQ_LEN_A : integer := 1; + CHAN_BOND_SEQ_LEN_B : integer := 1; + CLK_CORRECT_USE_A : boolean := FALSE; + CLK_CORRECT_USE_B : boolean := FALSE; + CLK_COR_8B10B_DE_A : boolean := FALSE; + CLK_COR_8B10B_DE_B : boolean := FALSE; + CLK_COR_MAX_LAT_A : integer := 48; + CLK_COR_MAX_LAT_B : integer := 48; + CLK_COR_MIN_LAT_A : integer := 36; + CLK_COR_MIN_LAT_B : integer := 36; + CLK_COR_SEQ_1_1_A : bit_vector := "00000000000"; + CLK_COR_SEQ_1_1_B : bit_vector := "00000000000"; + CLK_COR_SEQ_1_2_A : bit_vector := "00000000000"; + CLK_COR_SEQ_1_2_B : bit_vector := "00000000000"; + CLK_COR_SEQ_1_3_A : bit_vector := "00000000000"; + CLK_COR_SEQ_1_3_B : bit_vector := "00000000000"; + CLK_COR_SEQ_1_4_A : bit_vector := "00000000000"; + CLK_COR_SEQ_1_4_B : bit_vector := "00000000000"; + CLK_COR_SEQ_1_MASK_A : bit_vector := "1110"; + CLK_COR_SEQ_1_MASK_B : bit_vector := "1110"; + CLK_COR_SEQ_2_1_A : bit_vector := "00000000000"; + CLK_COR_SEQ_2_1_B : bit_vector := "00000000000"; + CLK_COR_SEQ_2_2_A : bit_vector := "00000000000"; + CLK_COR_SEQ_2_2_B : bit_vector := "00000000000"; + CLK_COR_SEQ_2_3_A : bit_vector := "00000000000"; + CLK_COR_SEQ_2_3_B : bit_vector := "00000000000"; + CLK_COR_SEQ_2_4_A : bit_vector := "00000000000"; + CLK_COR_SEQ_2_4_B : bit_vector := "00000000000"; + CLK_COR_SEQ_2_MASK_A : bit_vector := "1110"; + CLK_COR_SEQ_2_MASK_B : bit_vector := "1110"; + CLK_COR_SEQ_2_USE_A : boolean := FALSE; + CLK_COR_SEQ_2_USE_B : boolean := FALSE; + CLK_COR_SEQ_DROP_A : boolean := FALSE; + CLK_COR_SEQ_DROP_B : boolean := FALSE; + CLK_COR_SEQ_LEN_A : integer := 1; + CLK_COR_SEQ_LEN_B : integer := 1; + COMMA32_A : boolean := FALSE; + COMMA32_B : boolean := FALSE; + COMMA_10B_MASK_A : bit_vector := X"3FF"; + COMMA_10B_MASK_B : bit_vector := X"3FF"; + CYCLE_LIMIT_SEL_A : bit_vector := "00"; + CYCLE_LIMIT_SEL_B : bit_vector := "00"; + DCDR_FILTER_A : bit_vector := "010"; + DCDR_FILTER_B : bit_vector := "010"; + DEC_MCOMMA_DETECT_A : boolean := TRUE; + DEC_MCOMMA_DETECT_B : boolean := TRUE; + DEC_PCOMMA_DETECT_A : boolean := TRUE; + DEC_PCOMMA_DETECT_B : boolean := TRUE; + DEC_VALID_COMMA_ONLY_A : boolean := TRUE; + DEC_VALID_COMMA_ONLY_B : boolean := TRUE; + DIGRX_FWDCLK_A : bit_vector := "00"; + DIGRX_FWDCLK_B : bit_vector := "00"; + DIGRX_SYNC_MODE_A : boolean := FALSE; + DIGRX_SYNC_MODE_B : boolean := FALSE; + ENABLE_DCDR_A : boolean := FALSE; + ENABLE_DCDR_B : boolean := FALSE; + FDET_HYS_CAL_A : bit_vector := "010"; + FDET_HYS_CAL_B : bit_vector := "010"; + FDET_HYS_SEL_A : bit_vector := "100"; + FDET_HYS_SEL_B : bit_vector := "100"; + FDET_LCK_CAL_A : bit_vector := "100"; + FDET_LCK_CAL_B : bit_vector := "100"; + FDET_LCK_SEL_A : bit_vector := "001"; + FDET_LCK_SEL_B : bit_vector := "001"; + IREFBIASMODE_A : bit_vector := "11"; + IREFBIASMODE_B : bit_vector := "11"; + LOOPCAL_WAIT_A : bit_vector := "00"; + LOOPCAL_WAIT_B : bit_vector := "00"; + MCOMMA_32B_VALUE_A : bit_vector := X"00000000"; + MCOMMA_32B_VALUE_B : bit_vector := X"00000000"; + MCOMMA_DETECT_A : boolean := TRUE; + MCOMMA_DETECT_B : boolean := TRUE; + OPPOSITE_SELECT_A : boolean := FALSE; + OPPOSITE_SELECT_B : boolean := FALSE; + PCOMMA_32B_VALUE_A : bit_vector := X"00000000"; + PCOMMA_32B_VALUE_B : bit_vector := X"00000000"; + PCOMMA_DETECT_A : boolean := TRUE; + PCOMMA_DETECT_B : boolean := TRUE; + PCS_BIT_SLIP_A : boolean := FALSE; + PCS_BIT_SLIP_B : boolean := FALSE; + PMACLKENABLE_A : boolean := TRUE; + PMACLKENABLE_B : boolean := TRUE; + PMACOREPWRENABLE_A : boolean := TRUE; + PMACOREPWRENABLE_B : boolean := TRUE; + PMAIREFTRIM_A : bit_vector := "0111"; + PMAIREFTRIM_B : bit_vector := "0111"; + PMAVBGCTRL_A : bit_vector := "00000"; + PMAVBGCTRL_B : bit_vector := "00000"; + PMAVREFTRIM_A : bit_vector := "0111"; + PMAVREFTRIM_B : bit_vector := "0111"; + PMA_BIT_SLIP_A : boolean := FALSE; + PMA_BIT_SLIP_B : boolean := FALSE; + POWER_ENABLE_A : boolean := TRUE; + POWER_ENABLE_B : boolean := TRUE; + REPEATER_A : boolean := FALSE; + REPEATER_B : boolean := FALSE; + RXACTST_A : boolean := FALSE; + RXACTST_B : boolean := FALSE; + RXAFEEQ_A : bit_vector := "000000000"; + RXAFEEQ_B : bit_vector := "000000000"; + RXAFEPD_A : boolean := FALSE; + RXAFEPD_B : boolean := FALSE; + RXAFETST_A : boolean := FALSE; + RXAFETST_B : boolean := FALSE; + RXAPD_A : boolean := FALSE; + RXAPD_B : boolean := FALSE; + RXAREGCTRL_A : bit_vector := "00000"; + RXAREGCTRL_B : bit_vector := "00000"; + RXASYNCDIVIDE_A : bit_vector := "11"; + RXASYNCDIVIDE_B : bit_vector := "11"; + RXBY_32_A : boolean := FALSE; + RXBY_32_B : boolean := FALSE; + RXCDRLOS_A : bit_vector := "000000"; + RXCDRLOS_B : bit_vector := "000000"; + RXCLK0_FORCE_PMACLK_A : boolean := FALSE; + RXCLK0_FORCE_PMACLK_B : boolean := FALSE; + RXCLKMODE_A : bit_vector := "110001"; + RXCLKMODE_B : bit_vector := "110001"; + RXCLMODE_A : bit_vector := "00"; + RXCLMODE_B : bit_vector := "00"; + RXCMADJ_A : bit_vector := "01"; + RXCMADJ_B : bit_vector := "01"; + RXCPSEL_A : boolean := TRUE; + RXCPSEL_B : boolean := TRUE; + RXCPTST_A : boolean := FALSE; + RXCPTST_B : boolean := FALSE; + RXCRCCLOCKDOUBLE_A : boolean := FALSE; + RXCRCCLOCKDOUBLE_B : boolean := FALSE; + RXCRCENABLE_A : boolean := FALSE; + RXCRCENABLE_B : boolean := FALSE; + RXCRCINITVAL_A : bit_vector := X"00000000"; + RXCRCINITVAL_B : bit_vector := X"00000000"; + RXCRCINVERTGEN_A : boolean := FALSE; + RXCRCINVERTGEN_B : boolean := FALSE; + RXCRCSAMECLOCK_A : boolean := FALSE; + RXCRCSAMECLOCK_B : boolean := FALSE; + RXCTRL1_A : bit_vector := X"200"; + RXCTRL1_B : bit_vector := X"200"; + RXCYCLE_LIMIT_SEL_A : bit_vector := "00"; + RXCYCLE_LIMIT_SEL_B : bit_vector := "00"; + RXDATA_SEL_A : bit_vector := "00"; + RXDATA_SEL_B : bit_vector := "00"; + RXDCCOUPLE_A : boolean := FALSE; + RXDCCOUPLE_B : boolean := FALSE; + RXDIGRESET_A : boolean := FALSE; + RXDIGRESET_B : boolean := FALSE; + RXDIGRX_A : boolean := FALSE; + RXDIGRX_B : boolean := FALSE; + RXEQ_A : bit_vector := X"4000000000000000"; + RXEQ_B : bit_vector := X"4000000000000000"; + RXFDCAL_CLOCK_DIVIDE_A : string := "NONE"; + RXFDCAL_CLOCK_DIVIDE_B : string := "NONE"; + RXFDET_HYS_CAL_A : bit_vector := "010"; + RXFDET_HYS_CAL_B : bit_vector := "010"; + RXFDET_HYS_SEL_A : bit_vector := "100"; + RXFDET_HYS_SEL_B : bit_vector := "100"; + RXFDET_LCK_CAL_A : bit_vector := "100"; + RXFDET_LCK_CAL_B : bit_vector := "100"; + RXFDET_LCK_SEL_A : bit_vector := "001"; + RXFDET_LCK_SEL_B : bit_vector := "001"; + RXFECONTROL1_A : bit_vector := "00"; + RXFECONTROL1_B : bit_vector := "00"; + RXFECONTROL2_A : bit_vector := "000"; + RXFECONTROL2_B : bit_vector := "000"; + RXFETUNE_A : bit_vector := "01"; + RXFETUNE_B : bit_vector := "01"; + RXLB_A : boolean := FALSE; + RXLB_B : boolean := FALSE; + RXLKADJ_A : bit_vector := "00000"; + RXLKADJ_B : bit_vector := "00000"; + RXLKAPD_A : boolean := FALSE; + RXLKAPD_B : boolean := FALSE; + RXLOOPCAL_WAIT_A : bit_vector := "00"; + RXLOOPCAL_WAIT_B : bit_vector := "00"; + RXLOOPFILT_A : bit_vector := "0111"; + RXLOOPFILT_B : bit_vector := "0111"; + RXMODE_A : bit_vector := "000000"; + RXMODE_B : bit_vector := "000000"; + RXOUTDIV2SEL_A : integer := 1; + RXOUTDIV2SEL_B : integer := 1; + RXPDDTST_A : boolean := TRUE; + RXPDDTST_B : boolean := TRUE; + RXPD_A : boolean := FALSE; + RXPD_B : boolean := FALSE; + RXPLLNDIVSEL_A : integer := 8; + RXPLLNDIVSEL_B : integer := 8; + RXPMACLKSEL_A : string := "REFCLK1"; + RXPMACLKSEL_B : string := "REFCLK1"; + RXRCPADJ_A : bit_vector := "011"; + RXRCPADJ_B : bit_vector := "011"; + RXRCPPD_A : boolean := FALSE; + RXRCPPD_B : boolean := FALSE; + RXRECCLK1_USE_SYNC_A : boolean := FALSE; + RXRECCLK1_USE_SYNC_B : boolean := FALSE; + RXRIBADJ_A : bit_vector := "11"; + RXRIBADJ_B : bit_vector := "11"; + RXRPDPD_A : boolean := FALSE; + RXRPDPD_B : boolean := FALSE; + RXRSDPD_A : boolean := FALSE; + RXRSDPD_B : boolean := FALSE; + RXSLOWDOWN_CAL_A : bit_vector := "00"; + RXSLOWDOWN_CAL_B : bit_vector := "00"; + RXTUNE_A : bit_vector := X"0000"; + RXTUNE_B : bit_vector := X"0000"; + RXUSRDIVISOR_A : integer := 1; + RXUSRDIVISOR_B : integer := 1; + RXVCODAC_INIT_A : bit_vector := "1010000000"; + RXVCODAC_INIT_B : bit_vector := "1010000000"; + RXVCO_CTRL_ENABLE_A : boolean := FALSE; + RXVCO_CTRL_ENABLE_B : boolean := FALSE; + RX_BUFFER_USE_A : boolean := TRUE; + RX_BUFFER_USE_B : boolean := TRUE; + RX_CLOCK_DIVIDER_A : bit_vector := "00"; + RX_CLOCK_DIVIDER_B : bit_vector := "00"; + SAMPLE_8X_A : boolean := FALSE; + SAMPLE_8X_B : boolean := FALSE; + SH_CNT_MAX_A : integer := 64; + SH_CNT_MAX_B : integer := 64; + SH_INVALID_CNT_MAX_A : integer := 16; + SH_INVALID_CNT_MAX_B : integer := 16; + SLOWDOWN_CAL_A : bit_vector := "00"; + SLOWDOWN_CAL_B : bit_vector := "00"; + TXABPMACLKSEL_A : string := "REFCLK1"; + TXABPMACLKSEL_B : string := "REFCLK1"; + TXAPD_A : boolean := FALSE; + TXAPD_B : boolean := FALSE; + TXAREFBIASSEL_A : boolean := TRUE; + TXAREFBIASSEL_B : boolean := TRUE; + TXASYNCDIVIDE_A : bit_vector := "11"; + TXASYNCDIVIDE_B : bit_vector := "11"; + TXCLK0_FORCE_PMACLK_A : boolean := FALSE; + TXCLK0_FORCE_PMACLK_B : boolean := FALSE; + TXCLKMODE_A : bit_vector := "1001"; + TXCLKMODE_B : bit_vector := "1001"; + TXCLMODE_A : bit_vector := "00"; + TXCLMODE_B : bit_vector := "00"; + TXCPSEL_A : boolean := TRUE; + TXCPSEL_B : boolean := TRUE; + TXCRCCLOCKDOUBLE_A : boolean := FALSE; + TXCRCCLOCKDOUBLE_B : boolean := FALSE; + TXCRCENABLE_A : boolean := FALSE; + TXCRCENABLE_B : boolean := FALSE; + TXCRCINITVAL_A : bit_vector := X"00000000"; + TXCRCINITVAL_B : bit_vector := X"00000000"; + TXCRCINVERTGEN_A : boolean := FALSE; + TXCRCINVERTGEN_B : boolean := FALSE; + TXCRCSAMECLOCK_A : boolean := FALSE; + TXCRCSAMECLOCK_B : boolean := FALSE; + TXCTRL1_A : bit_vector := X"200"; + TXCTRL1_B : bit_vector := X"200"; + TXDATA_SEL_A : bit_vector := "00"; + TXDATA_SEL_B : bit_vector := "00"; + TXDAT_PRDRV_DAC_A : bit_vector := "111"; + TXDAT_PRDRV_DAC_B : bit_vector := "111"; + TXDAT_TAP_DAC_A : bit_vector := "10110"; + TXDAT_TAP_DAC_B : bit_vector := "10110"; + TXDIGPD_A : boolean := FALSE; + TXDIGPD_B : boolean := FALSE; + TXFDCAL_CLOCK_DIVIDE_A : string := "NONE"; + TXFDCAL_CLOCK_DIVIDE_B : string := "NONE"; + TXHIGHSIGNALEN_A : boolean := TRUE; + TXHIGHSIGNALEN_B : boolean := TRUE; + TXLOOPFILT_A : bit_vector := "0111"; + TXLOOPFILT_B : bit_vector := "0111"; + TXLVLSHFTPD_A : boolean := FALSE; + TXLVLSHFTPD_B : boolean := FALSE; + TXOUTCLK1_USE_SYNC_A : boolean := FALSE; + TXOUTCLK1_USE_SYNC_B : boolean := FALSE; + TXOUTDIV2SEL_A : integer := 1; + TXOUTDIV2SEL_B : integer := 1; + TXPD_A : boolean := FALSE; + TXPD_B : boolean := FALSE; + TXPHASESEL_A : boolean := FALSE; + TXPHASESEL_B : boolean := FALSE; + TXPLLNDIVSEL_A : integer := 8; + TXPLLNDIVSEL_B : integer := 8; + TXPOST_PRDRV_DAC_A : bit_vector := "111"; + TXPOST_PRDRV_DAC_B : bit_vector := "111"; + TXPOST_TAP_DAC_A : bit_vector := "01110"; + TXPOST_TAP_DAC_B : bit_vector := "01110"; + TXPOST_TAP_PD_A : boolean := TRUE; + TXPOST_TAP_PD_B : boolean := TRUE; + TXPRE_PRDRV_DAC_A : bit_vector := "111"; + TXPRE_PRDRV_DAC_B : bit_vector := "111"; + TXPRE_TAP_DAC_A : bit_vector := "00000"; + TXPRE_TAP_DAC_B : bit_vector := "00000"; + TXPRE_TAP_PD_A : boolean := TRUE; + TXPRE_TAP_PD_B : boolean := TRUE; + TXSLEWRATE_A : boolean := FALSE; + TXSLEWRATE_B : boolean := FALSE; + TXTERMTRIM_A : bit_vector := "1100"; + TXTERMTRIM_B : bit_vector := "1100"; + TXTUNE_A : bit_vector := X"0000"; + TXTUNE_B : bit_vector := X"0000"; + TX_BUFFER_USE_A : boolean := TRUE; + TX_BUFFER_USE_B : boolean := TRUE; + TX_CLOCK_DIVIDER_A : bit_vector := "00"; + TX_CLOCK_DIVIDER_B : bit_vector := "00"; + VCODAC_INIT_A : bit_vector := "1010000000"; + VCODAC_INIT_B : bit_vector := "1010000000"; + VCO_CTRL_ENABLE_A : boolean := FALSE; + VCO_CTRL_ENABLE_B : boolean := FALSE; + VREFBIASMODE_A : bit_vector := "11"; + VREFBIASMODE_B : bit_vector := "11" + ); + +port ( + CHBONDOA : out std_logic_vector(4 downto 0); + CHBONDOB : out std_logic_vector(4 downto 0); + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(15 downto 0); + DRDYA : out std_ulogic; + DRDYB : out std_ulogic; + RXBUFERRA : out std_ulogic; + RXBUFERRB : out std_ulogic; + RXCALFAILA : out std_ulogic; + RXCALFAILB : out std_ulogic; + RXCHARISCOMMAA : out std_logic_vector(7 downto 0); + RXCHARISCOMMAB : out std_logic_vector(7 downto 0); + RXCHARISKA : out std_logic_vector(7 downto 0); + RXCHARISKB : out std_logic_vector(7 downto 0); + RXCOMMADETA : out std_ulogic; + RXCOMMADETB : out std_ulogic; + RXCRCOUTA : out std_logic_vector(31 downto 0); + RXCRCOUTB : out std_logic_vector(31 downto 0); + RXCYCLELIMITA : out std_ulogic; + RXCYCLELIMITB : out std_ulogic; + RXDATAA : out std_logic_vector(63 downto 0); + RXDATAB : out std_logic_vector(63 downto 0); + RXDISPERRA : out std_logic_vector(7 downto 0); + RXDISPERRB : out std_logic_vector(7 downto 0); + RXLOCKA : out std_ulogic; + RXLOCKB : out std_ulogic; + RXLOSSOFSYNCA : out std_logic_vector(1 downto 0); + RXLOSSOFSYNCB : out std_logic_vector(1 downto 0); + RXMCLKA : out std_ulogic; + RXMCLKB : out std_ulogic; + RXNOTINTABLEA : out std_logic_vector(7 downto 0); + RXNOTINTABLEB : out std_logic_vector(7 downto 0); + RXPCSHCLKOUTA : out std_ulogic; + RXPCSHCLKOUTB : out std_ulogic; + RXREALIGNA : out std_ulogic; + RXREALIGNB : out std_ulogic; + RXRECCLK1A : out std_ulogic; + RXRECCLK1B : out std_ulogic; + RXRECCLK2A : out std_ulogic; + RXRECCLK2B : out std_ulogic; + RXRUNDISPA : out std_logic_vector(7 downto 0); + RXRUNDISPB : out std_logic_vector(7 downto 0); + RXSIGDETA : out std_ulogic; + RXSIGDETB : out std_ulogic; + RXSTATUSA : out std_logic_vector(5 downto 0); + RXSTATUSB : out std_logic_vector(5 downto 0); + TX1NA : out std_ulogic; + TX1NB : out std_ulogic; + TX1PA : out std_ulogic; + TX1PB : out std_ulogic; + TXBUFERRA : out std_ulogic; + TXBUFERRB : out std_ulogic; + TXCALFAILA : out std_ulogic; + TXCALFAILB : out std_ulogic; + TXCRCOUTA : out std_logic_vector(31 downto 0); + TXCRCOUTB : out std_logic_vector(31 downto 0); + TXCYCLELIMITA : out std_ulogic; + TXCYCLELIMITB : out std_ulogic; + TXKERRA : out std_logic_vector(7 downto 0); + TXKERRB : out std_logic_vector(7 downto 0); + TXLOCKA : out std_ulogic; + TXLOCKB : out std_ulogic; + TXOUTCLK1A : out std_ulogic; + TXOUTCLK1B : out std_ulogic; + TXOUTCLK2A : out std_ulogic; + TXOUTCLK2B : out std_ulogic; + TXPCSHCLKOUTA : out std_ulogic; + TXPCSHCLKOUTB : out std_ulogic; + TXRUNDISPA : out std_logic_vector(7 downto 0); + TXRUNDISPB : out std_logic_vector(7 downto 0); + + CHBONDIA : in std_logic_vector(4 downto 0); + CHBONDIB : in std_logic_vector(4 downto 0); + DADDRA : in std_logic_vector(7 downto 0); + DADDRB : in std_logic_vector(7 downto 0); + DCLKA : in std_ulogic; + DCLKB : in std_ulogic; + DENA : in std_ulogic; + DENB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(15 downto 0); + DWEA : in std_ulogic; + DWEB : in std_ulogic; + ENCHANSYNCA : in std_ulogic; + ENCHANSYNCB : in std_ulogic; + ENMCOMMAALIGNA : in std_ulogic; + ENMCOMMAALIGNB : in std_ulogic; + ENPCOMMAALIGNA : in std_ulogic; + ENPCOMMAALIGNB : in std_ulogic; + GREFCLKA : in std_ulogic; + GREFCLKB : in std_ulogic; + LOOPBACKA : in std_logic_vector(1 downto 0); + LOOPBACKB : in std_logic_vector(1 downto 0); + POWERDOWNA : in std_ulogic; + POWERDOWNB : in std_ulogic; + REFCLK1A : in std_ulogic; + REFCLK1B : in std_ulogic; + REFCLK2A : in std_ulogic; + REFCLK2B : in std_ulogic; + RX1NA : in std_ulogic; + RX1NB : in std_ulogic; + RX1PA : in std_ulogic; + RX1PB : in std_ulogic; + RXBLOCKSYNC64B66BUSEA : in std_ulogic; + RXBLOCKSYNC64B66BUSEB : in std_ulogic; + RXCLKSTABLEA : in std_ulogic; + RXCLKSTABLEB : in std_ulogic; + RXCOMMADETUSEA : in std_ulogic; + RXCOMMADETUSEB : in std_ulogic; + RXCRCCLKA : in std_ulogic; + RXCRCCLKB : in std_ulogic; + RXCRCDATAVALIDA : in std_ulogic; + RXCRCDATAVALIDB : in std_ulogic; + RXCRCDATAWIDTHA : in std_logic_vector(2 downto 0); + RXCRCDATAWIDTHB : in std_logic_vector(2 downto 0); + RXCRCINA : in std_logic_vector(63 downto 0); + RXCRCINB : in std_logic_vector(63 downto 0); + RXCRCINITA : in std_ulogic; + RXCRCINITB : in std_ulogic; + RXCRCINTCLKA : in std_ulogic; + RXCRCINTCLKB : in std_ulogic; + RXCRCPDA : in std_ulogic; + RXCRCPDB : in std_ulogic; + RXCRCRESETA : in std_ulogic; + RXCRCRESETB : in std_ulogic; + RXDATAWIDTHA : in std_logic_vector(1 downto 0); + RXDATAWIDTHB : in std_logic_vector(1 downto 0); + RXDEC64B66BUSEA : in std_ulogic; + RXDEC64B66BUSEB : in std_ulogic; + RXDEC8B10BUSEA : in std_ulogic; + RXDEC8B10BUSEB : in std_ulogic; + RXDESCRAM64B66BUSEA : in std_ulogic; + RXDESCRAM64B66BUSEB : in std_ulogic; + RXIGNOREBTFA : in std_ulogic; + RXIGNOREBTFB : in std_ulogic; + RXINTDATAWIDTHA : in std_logic_vector(1 downto 0); + RXINTDATAWIDTHB : in std_logic_vector(1 downto 0); + RXPMARESETA : in std_ulogic; + RXPMARESETB : in std_ulogic; + RXPOLARITYA : in std_ulogic; + RXPOLARITYB : in std_ulogic; + RXRESETA : in std_ulogic; + RXRESETB : in std_ulogic; + RXSLIDEA : in std_ulogic; + RXSLIDEB : in std_ulogic; + RXSYNCA : in std_ulogic; + RXSYNCB : in std_ulogic; + RXUSRCLK2A : in std_ulogic; + RXUSRCLK2B : in std_ulogic; + RXUSRCLKA : in std_ulogic; + RXUSRCLKB : in std_ulogic; + TXBYPASS8B10BA : in std_logic_vector(7 downto 0); + TXBYPASS8B10BB : in std_logic_vector(7 downto 0); + TXCHARDISPMODEA : in std_logic_vector(7 downto 0); + TXCHARDISPMODEB : in std_logic_vector(7 downto 0); + TXCHARDISPVALA : in std_logic_vector(7 downto 0); + TXCHARDISPVALB : in std_logic_vector(7 downto 0); + TXCHARISKA : in std_logic_vector(7 downto 0); + TXCHARISKB : in std_logic_vector(7 downto 0); + TXCLKSTABLEA : in std_ulogic; + TXCLKSTABLEB : in std_ulogic; + TXCRCCLKA : in std_ulogic; + TXCRCCLKB : in std_ulogic; + TXCRCDATAVALIDA : in std_ulogic; + TXCRCDATAVALIDB : in std_ulogic; + TXCRCDATAWIDTHA : in std_logic_vector(2 downto 0); + TXCRCDATAWIDTHB : in std_logic_vector(2 downto 0); + TXCRCINA : in std_logic_vector(63 downto 0); + TXCRCINB : in std_logic_vector(63 downto 0); + TXCRCINITA : in std_ulogic; + TXCRCINITB : in std_ulogic; + TXCRCINTCLKA : in std_ulogic; + TXCRCINTCLKB : in std_ulogic; + TXCRCPDA : in std_ulogic; + TXCRCPDB : in std_ulogic; + TXCRCRESETA : in std_ulogic; + TXCRCRESETB : in std_ulogic; + TXDATAA : in std_logic_vector(63 downto 0); + TXDATAB : in std_logic_vector(63 downto 0); + TXDATAWIDTHA : in std_logic_vector(1 downto 0); + TXDATAWIDTHB : in std_logic_vector(1 downto 0); + TXENC64B66BUSEA : in std_ulogic; + TXENC64B66BUSEB : in std_ulogic; + TXENC8B10BUSEA : in std_ulogic; + TXENC8B10BUSEB : in std_ulogic; + TXENOOBA : in std_ulogic; + TXENOOBB : in std_ulogic; + TXGEARBOX64B66BUSEA : in std_ulogic; + TXGEARBOX64B66BUSEB : in std_ulogic; + TXINHIBITA : in std_ulogic; + TXINHIBITB : in std_ulogic; + TXINTDATAWIDTHA : in std_logic_vector(1 downto 0); + TXINTDATAWIDTHB : in std_logic_vector(1 downto 0); + TXPMARESETA : in std_ulogic; + TXPMARESETB : in std_ulogic; + TXPOLARITYA : in std_ulogic; + TXPOLARITYB : in std_ulogic; + TXRESETA : in std_ulogic; + TXRESETB : in std_ulogic; + TXSCRAM64B66BUSEA : in std_ulogic; + TXSCRAM64B66BUSEB : in std_ulogic; + TXSYNCA : in std_ulogic; + TXSYNCB : in std_ulogic; + TXUSRCLK2A : in std_ulogic; + TXUSRCLK2B : in std_ulogic; + TXUSRCLKA : in std_ulogic; + TXUSRCLKB : in std_ulogic + ); +end GT11_DUAL; + +architecture GT11_DUAL_V of GT11_DUAL is +signal COMBUSINA : std_logic_vector(15 downto 0); +signal COMBUSINB : std_logic_vector(15 downto 0); + + + +begin + +GT11_inst_a : GT11 + generic map ( +ALIGN_COMMA_WORD => ALIGN_COMMA_WORD_A, +BANDGAPSEL => BANDGAPSEL_A, +BIASRESSEL => BIASRESSEL_A, +CCCB_ARBITRATOR_DISABLE => CCCB_ARBITRATOR_DISABLE_A, +CHAN_BOND_LIMIT => CHAN_BOND_LIMIT_A, +CHAN_BOND_MODE => CHAN_BOND_MODE_A, +CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT_A, +CHAN_BOND_SEQ_1_1 => CHAN_BOND_SEQ_1_1_A, +CHAN_BOND_SEQ_1_2 => CHAN_BOND_SEQ_1_2_A, +CHAN_BOND_SEQ_1_3 => CHAN_BOND_SEQ_1_3_A, +CHAN_BOND_SEQ_1_4 => CHAN_BOND_SEQ_1_4_A, +CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK_A, +CHAN_BOND_SEQ_2_1 => CHAN_BOND_SEQ_2_1_A, +CHAN_BOND_SEQ_2_2 => CHAN_BOND_SEQ_2_2_A, +CHAN_BOND_SEQ_2_3 => CHAN_BOND_SEQ_2_3_A, +CHAN_BOND_SEQ_2_4 => CHAN_BOND_SEQ_2_4_A, +CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK_A, +CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE_A, +CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN_A, +CLK_CORRECT_USE => CLK_CORRECT_USE_A, +CLK_COR_8B10B_DE => CLK_COR_8B10B_DE_A, +CLK_COR_MAX_LAT => CLK_COR_MAX_LAT_A, +CLK_COR_MIN_LAT => CLK_COR_MIN_LAT_A, +CLK_COR_SEQ_1_1 => CLK_COR_SEQ_1_1_A, +CLK_COR_SEQ_1_2 => CLK_COR_SEQ_1_2_A, +CLK_COR_SEQ_1_3 => CLK_COR_SEQ_1_3_A, +CLK_COR_SEQ_1_4 => CLK_COR_SEQ_1_4_A, +CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK_A, +CLK_COR_SEQ_2_1 => CLK_COR_SEQ_2_1_A, +CLK_COR_SEQ_2_2 => CLK_COR_SEQ_2_2_A, +CLK_COR_SEQ_2_3 => CLK_COR_SEQ_2_3_A, +CLK_COR_SEQ_2_4 => CLK_COR_SEQ_2_4_A, +CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK_A, +CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE_A, +CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP_A, +CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN_A, +COMMA32 => COMMA32_A, +COMMA_10B_MASK => COMMA_10B_MASK_A, +CYCLE_LIMIT_SEL => CYCLE_LIMIT_SEL_A, +DCDR_FILTER => DCDR_FILTER_A, +DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT_A, +DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT_A, +DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY_A, +DIGRX_FWDCLK => DIGRX_FWDCLK_A, +DIGRX_SYNC_MODE => DIGRX_SYNC_MODE_A, +ENABLE_DCDR => ENABLE_DCDR_A, +FDET_HYS_CAL => FDET_HYS_CAL_A, +FDET_HYS_SEL => FDET_HYS_SEL_A, +FDET_LCK_CAL => FDET_LCK_CAL_A, +FDET_LCK_SEL => FDET_LCK_SEL_A, +GT11_MODE => "A", +IREFBIASMODE => IREFBIASMODE_A, +LOOPCAL_WAIT => LOOPCAL_WAIT_A, +MCOMMA_32B_VALUE => MCOMMA_32B_VALUE_A, +MCOMMA_DETECT => MCOMMA_DETECT_A, +OPPOSITE_SELECT => OPPOSITE_SELECT_A, +PCOMMA_32B_VALUE => PCOMMA_32B_VALUE_A, +PCOMMA_DETECT => PCOMMA_DETECT_A, +PCS_BIT_SLIP => PCS_BIT_SLIP_A, +PMACLKENABLE => PMACLKENABLE_A, +PMACOREPWRENABLE => PMACOREPWRENABLE_A, +PMAIREFTRIM => PMAIREFTRIM_A, +PMAVBGCTRL => PMAVBGCTRL_A, +PMAVREFTRIM => PMAVREFTRIM_A, +PMA_BIT_SLIP => PMA_BIT_SLIP_A, +POWER_ENABLE => POWER_ENABLE_A, +REPEATER => REPEATER_A, +RXACTST => RXACTST_A, +RXAFEEQ => RXAFEEQ_A, +RXAFEPD => RXAFEPD_A, +RXAFETST => RXAFETST_A, +RXAPD => RXAPD_A, +RXAREGCTRL => RXAREGCTRL_A, +RXASYNCDIVIDE => RXASYNCDIVIDE_A, +RXBY_32 => RXBY_32_A, +RXCDRLOS => RXCDRLOS_A, +RXCLK0_FORCE_PMACLK => RXCLK0_FORCE_PMACLK_A, +RXCLKMODE => RXCLKMODE_A, +RXCLMODE => RXCLMODE_A, +RXCMADJ => RXCMADJ_A, +RXCPSEL => RXCPSEL_A, +RXCPTST => RXCPTST_A, +RXCRCCLOCKDOUBLE => RXCRCCLOCKDOUBLE_A, +RXCRCENABLE => RXCRCENABLE_A, +RXCRCINITVAL => RXCRCINITVAL_A, +RXCRCINVERTGEN => RXCRCINVERTGEN_A, +RXCRCSAMECLOCK => RXCRCSAMECLOCK_A, +RXCTRL1 => RXCTRL1_A, +RXCYCLE_LIMIT_SEL => RXCYCLE_LIMIT_SEL_A, +RXDATA_SEL => RXDATA_SEL_A, +RXDCCOUPLE => RXDCCOUPLE_A, +RXDIGRESET => RXDIGRESET_A, +RXDIGRX => RXDIGRX_A, +RXEQ => RXEQ_A, +RXFDCAL_CLOCK_DIVIDE => RXFDCAL_CLOCK_DIVIDE_A, +RXFDET_HYS_CAL => RXFDET_HYS_CAL_A, +RXFDET_HYS_SEL => RXFDET_HYS_SEL_A, +RXFDET_LCK_CAL => RXFDET_LCK_CAL_A, +RXFDET_LCK_SEL => RXFDET_LCK_SEL_A, +RXFECONTROL1 => RXFECONTROL1_A, +RXFECONTROL2 => RXFECONTROL2_A, +RXFETUNE => RXFETUNE_A, +RXLB => RXLB_A, +RXLKADJ => RXLKADJ_A, +RXLKAPD => RXLKAPD_A, +RXLOOPCAL_WAIT => RXLOOPCAL_WAIT_A, +RXLOOPFILT => RXLOOPFILT_A, +RXMODE => RXMODE_A, +RXOUTDIV2SEL => RXOUTDIV2SEL_A, +RXPD => RXPD_A, +RXPDDTST => RXPDDTST_A, +RXPLLNDIVSEL => RXPLLNDIVSEL_A, +RXPMACLKSEL => RXPMACLKSEL_A, +RXRCPADJ => RXRCPADJ_A, +RXRCPPD => RXRCPPD_A, +RXRECCLK1_USE_SYNC => RXRECCLK1_USE_SYNC_A, +RXRIBADJ => RXRIBADJ_A, +RXRPDPD => RXRPDPD_A, +RXRSDPD => RXRSDPD_A, +RXSLOWDOWN_CAL => RXSLOWDOWN_CAL_A, +RXTUNE => RXTUNE_A, +RXUSRDIVISOR => RXUSRDIVISOR_A, +RXVCODAC_INIT => RXVCODAC_INIT_A, +RXVCO_CTRL_ENABLE => RXVCO_CTRL_ENABLE_A, +RX_BUFFER_USE => RX_BUFFER_USE_A, +RX_CLOCK_DIVIDER => RX_CLOCK_DIVIDER_A, +SAMPLE_8X => SAMPLE_8X_A, +SH_CNT_MAX => SH_CNT_MAX_A, +SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX_A, +SLOWDOWN_CAL => SLOWDOWN_CAL_A, +TXABPMACLKSEL => TXABPMACLKSEL_A, +TXAPD => TXAPD_A, +TXAREFBIASSEL => TXAREFBIASSEL_A, +TXASYNCDIVIDE => TXASYNCDIVIDE_A, +TXCLK0_FORCE_PMACLK => TXCLK0_FORCE_PMACLK_A, +TXCLKMODE => TXCLKMODE_A, +TXCLMODE => TXCLMODE_A, +TXCPSEL => TXCPSEL_A, +TXCRCCLOCKDOUBLE => TXCRCCLOCKDOUBLE_A, +TXCRCENABLE => TXCRCENABLE_A, +TXCRCINITVAL => TXCRCINITVAL_A, +TXCRCINVERTGEN => TXCRCINVERTGEN_A, +TXCRCSAMECLOCK => TXCRCSAMECLOCK_A, +TXCTRL1 => TXCTRL1_A, +TXDATA_SEL => TXDATA_SEL_A, +TXDAT_PRDRV_DAC => TXDAT_PRDRV_DAC_A, +TXDAT_TAP_DAC => TXDAT_TAP_DAC_A, +TXDIGPD => TXDIGPD_A, +TXFDCAL_CLOCK_DIVIDE => TXFDCAL_CLOCK_DIVIDE_A, +TXHIGHSIGNALEN => TXHIGHSIGNALEN_A, +TXLOOPFILT => TXLOOPFILT_A, +TXLVLSHFTPD => TXLVLSHFTPD_A, +TXOUTCLK1_USE_SYNC => TXOUTCLK1_USE_SYNC_A, +TXOUTDIV2SEL => TXOUTDIV2SEL_A, +TXPD => TXPD_A, +TXPHASESEL => TXPHASESEL_A, +TXPLLNDIVSEL => TXPLLNDIVSEL_A, +TXPOST_PRDRV_DAC => TXPOST_PRDRV_DAC_A, +TXPOST_TAP_DAC => TXPOST_TAP_DAC_A, +TXPOST_TAP_PD => TXPOST_TAP_PD_A, +TXPRE_PRDRV_DAC => TXPRE_PRDRV_DAC_A, +TXPRE_TAP_DAC => TXPRE_TAP_DAC_A, +TXPRE_TAP_PD => TXPRE_TAP_PD_A, +TXSLEWRATE => TXSLEWRATE_A, +TXTERMTRIM => TXTERMTRIM_A, +TXTUNE => TXTUNE_A, +TX_BUFFER_USE => TX_BUFFER_USE_A, +TX_CLOCK_DIVIDER => TX_CLOCK_DIVIDER_A, +VCODAC_INIT => VCODAC_INIT_A, +VCO_CTRL_ENABLE => VCO_CTRL_ENABLE_A, +VREFBIASMODE => VREFBIASMODE_A +) + +port map ( +CHBONDO => CHBONDOA, +COMBUSOUT => COMBUSINB, +DO => DOA, +DRDY => DRDYA, +RXBUFERR => RXBUFERRA, +RXCALFAIL => RXCALFAILA, +RXCHARISCOMMA => RXCHARISCOMMAA, +RXCHARISK => RXCHARISKA, +RXCOMMADET => RXCOMMADETA, +RXCRCOUT => RXCRCOUTA, +RXCYCLELIMIT => RXCYCLELIMITA, +RXDATA => RXDATAA, +RXDISPERR => RXDISPERRA, +RXLOCK => RXLOCKA, +RXLOSSOFSYNC => RXLOSSOFSYNCA, +RXMCLK => RXMCLKA, +RXNOTINTABLE => RXNOTINTABLEA, +RXPCSHCLKOUT => RXPCSHCLKOUTA, +RXREALIGN => RXREALIGNA, +RXRECCLK1 => RXRECCLK1A, +RXRECCLK2 => RXRECCLK2A, +RXRUNDISP => RXRUNDISPA, +RXSIGDET => RXSIGDETA, +RXSTATUS => RXSTATUSA, +TX1N => TX1NA, +TX1P => TX1PA, +TXBUFERR => TXBUFERRA, +TXCALFAIL => TXCALFAILA, +TXCRCOUT => TXCRCOUTA, +TXCYCLELIMIT => TXCYCLELIMITA, +TXKERR => TXKERRA, +TXLOCK => TXLOCKA, +TXOUTCLK1 => TXOUTCLK1A, +TXOUTCLK2 => TXOUTCLK2A, +TXPCSHCLKOUT => TXPCSHCLKOUTA, +TXRUNDISP => TXRUNDISPA, + +CHBONDI => CHBONDIA, +COMBUSIN => COMBUSINA, +DADDR => DADDRA, +DCLK => DCLKA, +DEN => DENA, +DI => DIA, +DWE => DWEA, +ENCHANSYNC => ENCHANSYNCA, +ENMCOMMAALIGN => ENMCOMMAALIGNA, +ENPCOMMAALIGN => ENPCOMMAALIGNA, +GREFCLK => GREFCLKA, +LOOPBACK => LOOPBACKA, +POWERDOWN => POWERDOWNA, +REFCLK1 => REFCLK1A, +REFCLK2 => REFCLK2A, +RX1N => RX1NA, +RX1P => RX1PA, +RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSEA, +RXCLKSTABLE => RXCLKSTABLEA, +RXCOMMADETUSE => RXCOMMADETUSEA, +RXCRCCLK => RXCRCCLKA, +RXCRCDATAVALID => RXCRCDATAVALIDA, +RXCRCDATAWIDTH => RXCRCDATAWIDTHA, +RXCRCIN => RXCRCINA, +RXCRCINIT => RXCRCINITA, +RXCRCINTCLK => RXCRCINTCLKA, +RXCRCPD => RXCRCPDA, +RXCRCRESET => RXCRCRESETA, +RXDATAWIDTH => RXDATAWIDTHA, +RXDEC64B66BUSE => RXDEC64B66BUSEA, +RXDEC8B10BUSE => RXDEC8B10BUSEA, +RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSEA, +RXIGNOREBTF => RXIGNOREBTFA, +RXINTDATAWIDTH => RXINTDATAWIDTHA, +RXPMARESET => RXPMARESETA, +RXPOLARITY => RXPOLARITYA, +RXRESET => RXRESETA, +RXSLIDE => RXSLIDEA, +RXSYNC => RXSYNCA, +RXUSRCLK => RXUSRCLKA, +RXUSRCLK2 => RXUSRCLK2A, +TXBYPASS8B10B => TXBYPASS8B10BA, +TXCHARDISPMODE => TXCHARDISPMODEA, +TXCHARDISPVAL => TXCHARDISPVALA, +TXCHARISK => TXCHARISKA, +TXCLKSTABLE => TXCLKSTABLEA, +TXCRCCLK => TXCRCCLKA, +TXCRCDATAVALID => TXCRCDATAVALIDA, +TXCRCDATAWIDTH => TXCRCDATAWIDTHA, +TXCRCIN => TXCRCINA, +TXCRCINIT => TXCRCINITA, +TXCRCINTCLK => TXCRCINTCLKA, +TXCRCPD => TXCRCPDA, +TXCRCRESET => TXCRCRESETA, +TXDATA => TXDATAA, +TXDATAWIDTH => TXDATAWIDTHA, +TXENC64B66BUSE => TXENC64B66BUSEA, +TXENC8B10BUSE => TXENC8B10BUSEA, +TXENOOB => TXENOOBA, +TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSEA, +TXINHIBIT => TXINHIBITA, +TXINTDATAWIDTH => TXINTDATAWIDTHA, +TXPMARESET => TXPMARESETA, +TXPOLARITY => TXPOLARITYA, +TXRESET => TXRESETA, +TXSCRAM64B66BUSE => TXSCRAM64B66BUSEA, +TXSYNC => TXSYNCA, +TXUSRCLK => TXUSRCLKA, +TXUSRCLK2 => TXUSRCLK2A +); + +GT11_inst_b : GT11 + generic map ( +ALIGN_COMMA_WORD => ALIGN_COMMA_WORD_B, +BANDGAPSEL => BANDGAPSEL_B, +BIASRESSEL => BIASRESSEL_B, +CCCB_ARBITRATOR_DISABLE => CCCB_ARBITRATOR_DISABLE_B, +CHAN_BOND_LIMIT => CHAN_BOND_LIMIT_B, +CHAN_BOND_MODE => CHAN_BOND_MODE_B, +CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT_B, +CHAN_BOND_SEQ_1_1 => CHAN_BOND_SEQ_1_1_B, +CHAN_BOND_SEQ_1_2 => CHAN_BOND_SEQ_1_2_B, +CHAN_BOND_SEQ_1_3 => CHAN_BOND_SEQ_1_3_B, +CHAN_BOND_SEQ_1_4 => CHAN_BOND_SEQ_1_4_B, +CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK_B, +CHAN_BOND_SEQ_2_1 => CHAN_BOND_SEQ_2_1_B, +CHAN_BOND_SEQ_2_2 => CHAN_BOND_SEQ_2_2_B, +CHAN_BOND_SEQ_2_3 => CHAN_BOND_SEQ_2_3_B, +CHAN_BOND_SEQ_2_4 => CHAN_BOND_SEQ_2_4_B, +CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK_B, +CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE_B, +CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN_B, +CLK_CORRECT_USE => CLK_CORRECT_USE_B, +CLK_COR_8B10B_DE => CLK_COR_8B10B_DE_B, +CLK_COR_MAX_LAT => CLK_COR_MAX_LAT_B, +CLK_COR_MIN_LAT => CLK_COR_MIN_LAT_B, +CLK_COR_SEQ_1_1 => CLK_COR_SEQ_1_1_B, +CLK_COR_SEQ_1_2 => CLK_COR_SEQ_1_2_B, +CLK_COR_SEQ_1_3 => CLK_COR_SEQ_1_3_B, +CLK_COR_SEQ_1_4 => CLK_COR_SEQ_1_4_B, +CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK_B, +CLK_COR_SEQ_2_1 => CLK_COR_SEQ_2_1_B, +CLK_COR_SEQ_2_2 => CLK_COR_SEQ_2_2_B, +CLK_COR_SEQ_2_3 => CLK_COR_SEQ_2_3_B, +CLK_COR_SEQ_2_4 => CLK_COR_SEQ_2_4_B, +CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK_B, +CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE_B, +CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP_B, +CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN_B, +COMMA32 => COMMA32_B, +COMMA_10B_MASK => COMMA_10B_MASK_B, +CYCLE_LIMIT_SEL => CYCLE_LIMIT_SEL_B, +DCDR_FILTER => DCDR_FILTER_B, +DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT_B, +DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT_B, +DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY_B, +DIGRX_FWDCLK => DIGRX_FWDCLK_B, +DIGRX_SYNC_MODE => DIGRX_SYNC_MODE_B, +ENABLE_DCDR => ENABLE_DCDR_B, +FDET_HYS_CAL => FDET_HYS_CAL_B, +FDET_HYS_SEL => FDET_HYS_SEL_B, +FDET_LCK_CAL => FDET_LCK_CAL_B, +FDET_LCK_SEL => FDET_LCK_SEL_B, +GT11_MODE => "B", +IREFBIASMODE => IREFBIASMODE_B, +LOOPCAL_WAIT => LOOPCAL_WAIT_B, +MCOMMA_32B_VALUE => MCOMMA_32B_VALUE_B, +MCOMMA_DETECT => MCOMMA_DETECT_B, +OPPOSITE_SELECT => OPPOSITE_SELECT_B, +PCOMMA_32B_VALUE => PCOMMA_32B_VALUE_B, +PCOMMA_DETECT => PCOMMA_DETECT_B, +PCS_BIT_SLIP => PCS_BIT_SLIP_B, +PMACLKENABLE => PMACLKENABLE_B, +PMACOREPWRENABLE => PMACOREPWRENABLE_B, +PMAIREFTRIM => PMAIREFTRIM_B, +PMAVBGCTRL => PMAVBGCTRL_B, +PMAVREFTRIM => PMAVREFTRIM_B, +PMA_BIT_SLIP => PMA_BIT_SLIP_B, +POWER_ENABLE => POWER_ENABLE_B, +REPEATER => REPEATER_B, +RXACTST => RXACTST_B, +RXAFEEQ => RXAFEEQ_B, +RXAFEPD => RXAFEPD_B, +RXAFETST => RXAFETST_B, +RXAPD => RXAPD_B, +RXAREGCTRL => RXAREGCTRL_B, +RXASYNCDIVIDE => RXASYNCDIVIDE_B, +RXBY_32 => RXBY_32_B, +RXCDRLOS => RXCDRLOS_B, +RXCLK0_FORCE_PMACLK => RXCLK0_FORCE_PMACLK_B, +RXCLKMODE => RXCLKMODE_B, +RXCLMODE => RXCLMODE_B, +RXCMADJ => RXCMADJ_B, +RXCPSEL => RXCPSEL_B, +RXCPTST => RXCPTST_B, +RXCRCCLOCKDOUBLE => RXCRCCLOCKDOUBLE_B, +RXCRCENABLE => RXCRCENABLE_B, +RXCRCINITVAL => RXCRCINITVAL_B, +RXCRCINVERTGEN => RXCRCINVERTGEN_B, +RXCRCSAMECLOCK => RXCRCSAMECLOCK_B, +RXCTRL1 => RXCTRL1_B, +RXCYCLE_LIMIT_SEL => RXCYCLE_LIMIT_SEL_B, +RXDATA_SEL => RXDATA_SEL_B, +RXDCCOUPLE => RXDCCOUPLE_B, +RXDIGRESET => RXDIGRESET_B, +RXDIGRX => RXDIGRX_B, +RXEQ => RXEQ_B, +RXFDCAL_CLOCK_DIVIDE => RXFDCAL_CLOCK_DIVIDE_B, +RXFDET_HYS_CAL => RXFDET_HYS_CAL_B, +RXFDET_HYS_SEL => RXFDET_HYS_SEL_B, +RXFDET_LCK_CAL => RXFDET_LCK_CAL_B, +RXFDET_LCK_SEL => RXFDET_LCK_SEL_B, +RXFECONTROL1 => RXFECONTROL1_B, +RXFECONTROL2 => RXFECONTROL2_B, +RXFETUNE => RXFETUNE_B, +RXLB => RXLB_B, +RXLKADJ => RXLKADJ_B, +RXLKAPD => RXLKAPD_B, +RXLOOPCAL_WAIT => RXLOOPCAL_WAIT_B, +RXLOOPFILT => RXLOOPFILT_B, +RXMODE => RXMODE_B, +RXOUTDIV2SEL => RXOUTDIV2SEL_B, +RXPD => RXPD_B, +RXPDDTST => RXPDDTST_B, +RXPLLNDIVSEL => RXPLLNDIVSEL_B, +RXPMACLKSEL => RXPMACLKSEL_B, +RXRCPADJ => RXRCPADJ_B, +RXRCPPD => RXRCPPD_B, +RXRECCLK1_USE_SYNC => RXRECCLK1_USE_SYNC_B, +RXRIBADJ => RXRIBADJ_B, +RXRPDPD => RXRPDPD_B, +RXRSDPD => RXRSDPD_B, +RXSLOWDOWN_CAL => RXSLOWDOWN_CAL_B, +RXTUNE => RXTUNE_B, +RXUSRDIVISOR => RXUSRDIVISOR_B, +RXVCODAC_INIT => RXVCODAC_INIT_B, +RXVCO_CTRL_ENABLE => RXVCO_CTRL_ENABLE_B, +RX_BUFFER_USE => RX_BUFFER_USE_B, +RX_CLOCK_DIVIDER => RX_CLOCK_DIVIDER_B, +SAMPLE_8X => SAMPLE_8X_B, +SH_CNT_MAX => SH_CNT_MAX_B, +SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX_B, +SLOWDOWN_CAL => SLOWDOWN_CAL_B, +TXABPMACLKSEL => TXABPMACLKSEL_B, +TXAPD => TXAPD_B, +TXAREFBIASSEL => TXAREFBIASSEL_B, +TXASYNCDIVIDE => TXASYNCDIVIDE_B, +TXCLK0_FORCE_PMACLK => TXCLK0_FORCE_PMACLK_B, +TXCLKMODE => TXCLKMODE_B, +TXCLMODE => TXCLMODE_B, +TXCPSEL => TXCPSEL_B, +TXCRCCLOCKDOUBLE => TXCRCCLOCKDOUBLE_B, +TXCRCENABLE => TXCRCENABLE_B, +TXCRCINITVAL => TXCRCINITVAL_B, +TXCRCINVERTGEN => TXCRCINVERTGEN_B, +TXCRCSAMECLOCK => TXCRCSAMECLOCK_B, +TXCTRL1 => TXCTRL1_B, +TXDATA_SEL => TXDATA_SEL_B, +TXDAT_PRDRV_DAC => TXDAT_PRDRV_DAC_B, +TXDAT_TAP_DAC => TXDAT_TAP_DAC_B, +TXDIGPD => TXDIGPD_B, +TXFDCAL_CLOCK_DIVIDE => TXFDCAL_CLOCK_DIVIDE_B, +TXHIGHSIGNALEN => TXHIGHSIGNALEN_B, +TXLOOPFILT => TXLOOPFILT_B, +TXLVLSHFTPD => TXLVLSHFTPD_B, +TXOUTCLK1_USE_SYNC => TXOUTCLK1_USE_SYNC_B, +TXOUTDIV2SEL => TXOUTDIV2SEL_B, +TXPD => TXPD_B, +TXPHASESEL => TXPHASESEL_B, +TXPLLNDIVSEL => TXPLLNDIVSEL_B, +TXPOST_PRDRV_DAC => TXPOST_PRDRV_DAC_B, +TXPOST_TAP_DAC => TXPOST_TAP_DAC_B, +TXPOST_TAP_PD => TXPOST_TAP_PD_B, +TXPRE_PRDRV_DAC => TXPRE_PRDRV_DAC_B, +TXPRE_TAP_DAC => TXPRE_TAP_DAC_B, +TXPRE_TAP_PD => TXPRE_TAP_PD_B, +TXSLEWRATE => TXSLEWRATE_B, +TXTERMTRIM => TXTERMTRIM_B, +TXTUNE => TXTUNE_B, +TX_BUFFER_USE => TX_BUFFER_USE_B, +TX_CLOCK_DIVIDER => TX_CLOCK_DIVIDER_B, +VCODAC_INIT => VCODAC_INIT_B, +VCO_CTRL_ENABLE => VCO_CTRL_ENABLE_B, +VREFBIASMODE => VREFBIASMODE_B +) + +port map ( +CHBONDO => CHBONDOB, +COMBUSOUT => COMBUSINA, +DO => DOB, +DRDY => DRDYB, +RXBUFERR => RXBUFERRB, +RXCALFAIL => RXCALFAILB, +RXCHARISCOMMA => RXCHARISCOMMAB, +RXCHARISK => RXCHARISKB, +RXCOMMADET => RXCOMMADETB, +RXCRCOUT => RXCRCOUTB, +RXCYCLELIMIT => RXCYCLELIMITB, +RXDATA => RXDATAB, +RXDISPERR => RXDISPERRB, +RXLOCK => RXLOCKB, +RXLOSSOFSYNC => RXLOSSOFSYNCB, +RXMCLK => RXMCLKB, +RXNOTINTABLE => RXNOTINTABLEB, +RXPCSHCLKOUT => RXPCSHCLKOUTB, +RXREALIGN => RXREALIGNB, +RXRECCLK1 => RXRECCLK1B, +RXRECCLK2 => RXRECCLK2B, +RXRUNDISP => RXRUNDISPB, +RXSIGDET => RXSIGDETB, +RXSTATUS => RXSTATUSB, +TX1N => TX1NB, +TX1P => TX1PB, +TXBUFERR => TXBUFERRB, +TXCALFAIL => TXCALFAILB, +TXCRCOUT => TXCRCOUTB, +TXCYCLELIMIT => TXCYCLELIMITB, +TXKERR => TXKERRB, +TXLOCK => TXLOCKB, +TXOUTCLK1 => TXOUTCLK1B, +TXOUTCLK2 => TXOUTCLK2B, +TXPCSHCLKOUT => TXPCSHCLKOUTB, +TXRUNDISP => TXRUNDISPB, + +CHBONDI => CHBONDIB, +COMBUSIN => COMBUSINB, +DADDR => DADDRB, +DCLK => DCLKB, +DEN => DENB, +DI => DIB, +DWE => DWEB, +ENCHANSYNC => ENCHANSYNCB, +ENMCOMMAALIGN => ENMCOMMAALIGNB, +ENPCOMMAALIGN => ENPCOMMAALIGNB, +GREFCLK => GREFCLKB, +LOOPBACK => LOOPBACKB, +POWERDOWN => POWERDOWNB, +REFCLK1 => REFCLK1B, +REFCLK2 => REFCLK2B, +RX1N => RX1NB, +RX1P => RX1PB, +RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSEB, +RXCLKSTABLE => RXCLKSTABLEB, +RXCOMMADETUSE => RXCOMMADETUSEB, +RXCRCCLK => RXCRCCLKB, +RXCRCDATAVALID => RXCRCDATAVALIDB, +RXCRCDATAWIDTH => RXCRCDATAWIDTHB, +RXCRCIN => RXCRCINB, +RXCRCINIT => RXCRCINITB, +RXCRCINTCLK => RXCRCINTCLKB, +RXCRCPD => RXCRCPDB, +RXCRCRESET => RXCRCRESETB, +RXDATAWIDTH => RXDATAWIDTHB, +RXDEC64B66BUSE => RXDEC64B66BUSEB, +RXDEC8B10BUSE => RXDEC8B10BUSEB, +RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSEB, +RXIGNOREBTF => RXIGNOREBTFB, +RXINTDATAWIDTH => RXINTDATAWIDTHB, +RXPMARESET => RXPMARESETB, +RXPOLARITY => RXPOLARITYB, +RXRESET => RXRESETB, +RXSLIDE => RXSLIDEB, +RXSYNC => RXSYNCB, +RXUSRCLK => RXUSRCLKB, +RXUSRCLK2 => RXUSRCLK2B, +TXBYPASS8B10B => TXBYPASS8B10BB, +TXCHARDISPMODE => TXCHARDISPMODEB, +TXCHARDISPVAL => TXCHARDISPVALB, +TXCHARISK => TXCHARISKB, +TXCLKSTABLE => TXCLKSTABLEB, +TXCRCCLK => TXCRCCLKB, +TXCRCDATAVALID => TXCRCDATAVALIDB, +TXCRCDATAWIDTH => TXCRCDATAWIDTHB, +TXCRCIN => TXCRCINB, +TXCRCINIT => TXCRCINITB, +TXCRCINTCLK => TXCRCINTCLKB, +TXCRCPD => TXCRCPDB, +TXCRCRESET => TXCRCRESETB, +TXDATA => TXDATAB, +TXDATAWIDTH => TXDATAWIDTHB, +TXENC64B66BUSE => TXENC64B66BUSEB, +TXENC8B10BUSE => TXENC8B10BUSEB, +TXENOOB => TXENOOBB, +TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSEB, +TXINHIBIT => TXINHIBITB, +TXINTDATAWIDTH => TXINTDATAWIDTHB, +TXPMARESET => TXPMARESETB, +TXPOLARITY => TXPOLARITYB, +TXRESET => TXRESETB, +TXSCRAM64B66BUSE => TXSCRAM64B66BUSEB, +TXSYNC => TXSYNCB, +TXUSRCLK => TXUSRCLKB, +TXUSRCLK2 => TXUSRCLK2B +); + +end GT11_DUAL_V; +----- CELL GT11 ----- +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 11-Gigabit Transceiver for High-Speed I/O Simulation Model +-- /___/ /\ Filename : GT11.vhd +-- \ \ / \ Timestamp : Fri Jun 18 10:57:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 05/16/05 - Changed default values for some parameters and removed two parameters. Fixed CR#207101. +-- 08/08/05 - Changed default parameter values for some parameters (CR 214282). +-- 02/28/06 - CR#226322 - Addition of new parameters and change of default values for some parameters. +-- End Revision + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GT11 is +generic ( + IN_DELAY : time := 0 ps; + OUT_DELAY : VitalDelayType01 := (100 ps, 100 ps); + ALIGN_COMMA_WORD : integer := 4; + BANDGAPSEL : boolean := FALSE; + BIASRESSEL : boolean := FALSE; + CCCB_ARBITRATOR_DISABLE : boolean := FALSE; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "NONE"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_MASK : bit_vector := "1110"; + CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "1110"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 1; + CLK_CORRECT_USE : boolean := FALSE; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 48; + CLK_COR_MIN_LAT : integer := 36; + CLK_COR_SEQ_1_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_MASK : bit_vector := "1110"; + CLK_COR_SEQ_2_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_MASK : bit_vector := "1110"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 1; + COMMA32 : boolean := FALSE; + COMMA_10B_MASK : bit_vector := X"3FF"; + CYCLE_LIMIT_SEL : bit_vector := "00"; + DCDR_FILTER : bit_vector := "010"; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + DIGRX_FWDCLK : bit_vector := "00"; + DIGRX_SYNC_MODE : boolean := FALSE; + ENABLE_DCDR : boolean := FALSE; + FDET_HYS_CAL : bit_vector := "010"; + FDET_HYS_SEL : bit_vector := "100"; + FDET_LCK_CAL : bit_vector := "100"; + FDET_LCK_SEL : bit_vector := "001"; + GT11_MODE : string := "DONT_CARE"; + IREFBIASMODE : bit_vector := "11"; + LOOPCAL_WAIT : bit_vector := "00"; + MCOMMA_32B_VALUE : bit_vector := X"00000000"; + MCOMMA_DETECT : boolean := TRUE; + OPPOSITE_SELECT : boolean := FALSE; + PCOMMA_32B_VALUE : bit_vector := X"00000000"; + PCOMMA_DETECT : boolean := TRUE; + PCS_BIT_SLIP : boolean := FALSE; + PMACLKENABLE : boolean := TRUE; + PMACOREPWRENABLE : boolean := TRUE; + PMAIREFTRIM : bit_vector := "0111"; + PMAVBGCTRL : bit_vector := "00000"; + PMAVREFTRIM : bit_vector := "0111"; + PMA_BIT_SLIP : boolean := FALSE; + POWER_ENABLE : boolean := TRUE; + REPEATER : boolean := FALSE; + RXACTST : boolean := FALSE; + RXAFEEQ : bit_vector := "000000000"; + RXAFEPD : boolean := FALSE; + RXAFETST : boolean := FALSE; + RXAPD : boolean := FALSE; + RXAREGCTRL : bit_vector := "00000"; + RXASYNCDIVIDE : bit_vector := "11"; + RXBY_32 : boolean := FALSE; + RXCDRLOS : bit_vector := "000000"; + RXCLK0_FORCE_PMACLK : boolean := FALSE; + RXCLKMODE : bit_vector := "110001"; + RXCLMODE : bit_vector := "00"; + RXCMADJ : bit_vector := "01"; + RXCPSEL : boolean := TRUE; + RXCPTST : boolean := FALSE; + RXCRCCLOCKDOUBLE : boolean := FALSE; + RXCRCENABLE : boolean := FALSE; + RXCRCINITVAL : bit_vector := X"00000000"; + RXCRCINVERTGEN : boolean := FALSE; + RXCRCSAMECLOCK : boolean := FALSE; + RXCTRL1 : bit_vector := X"200"; + RXCYCLE_LIMIT_SEL : bit_vector := "00"; + RXDATA_SEL : bit_vector := "00"; + RXDCCOUPLE : boolean := FALSE; + RXDIGRESET : boolean := FALSE; + RXDIGRX : boolean := FALSE; + RXEQ : bit_vector := X"4000000000000000"; + RXFDCAL_CLOCK_DIVIDE : string := "NONE"; + RXFDET_HYS_CAL : bit_vector := "010"; + RXFDET_HYS_SEL : bit_vector := "100"; + RXFDET_LCK_CAL : bit_vector := "100"; + RXFDET_LCK_SEL : bit_vector := "001"; + RXFECONTROL1 : bit_vector := "00"; + RXFECONTROL2 : bit_vector := "000"; + RXFETUNE : bit_vector := "01"; + RXLB : boolean := FALSE; + RXLKADJ : bit_vector := "00000"; + RXLKAPD : boolean := FALSE; + RXLOOPCAL_WAIT : bit_vector := "00"; + RXLOOPFILT : bit_vector := "0111"; + RXMODE : bit_vector := "000000"; + RXOUTDIV2SEL : integer := 1; + RXPD : boolean := FALSE; + RXPDDTST : boolean := TRUE; + RXPLLNDIVSEL : integer := 8; + RXPMACLKSEL : string := "REFCLK1"; + RXRCPADJ : bit_vector := "011"; + RXRCPPD : boolean := FALSE; + RXRECCLK1_USE_SYNC : boolean := FALSE; + RXRIBADJ : bit_vector := "11"; + RXRPDPD : boolean := FALSE; + RXRSDPD : boolean := FALSE; + RXSLOWDOWN_CAL : bit_vector := "00"; + RXTUNE : bit_vector := X"0000"; + RXUSRDIVISOR : integer := 1; + RXVCODAC_INIT : bit_vector := "1010000000"; + RXVCO_CTRL_ENABLE : boolean := FALSE; + RX_BUFFER_USE : boolean := TRUE; + RX_CLOCK_DIVIDER : bit_vector := "00"; + SAMPLE_8X : boolean := FALSE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + SLOWDOWN_CAL : bit_vector := "00"; + TXABPMACLKSEL : string := "REFCLK1"; + TXAPD : boolean := FALSE; + TXAREFBIASSEL : boolean := TRUE; + TXASYNCDIVIDE : bit_vector := "11"; + TXCLK0_FORCE_PMACLK : boolean := FALSE; + TXCLKMODE : bit_vector := "1001"; + TXCLMODE : bit_vector := "00"; + TXCPSEL : boolean := TRUE; + TXCRCCLOCKDOUBLE : boolean := FALSE; + TXCRCENABLE : boolean := FALSE; + TXCRCINITVAL : bit_vector := X"00000000"; + TXCRCINVERTGEN : boolean := FALSE; + TXCRCSAMECLOCK : boolean := FALSE; + TXCTRL1 : bit_vector := X"200"; + TXDATA_SEL : bit_vector := "00"; + TXDAT_PRDRV_DAC : bit_vector := "111"; + TXDAT_TAP_DAC : bit_vector := "10110"; + TXDIGPD : boolean := FALSE; + TXFDCAL_CLOCK_DIVIDE : string := "NONE"; + TXHIGHSIGNALEN : boolean := TRUE; + TXLOOPFILT : bit_vector := "0111"; + TXLVLSHFTPD : boolean := FALSE; + TXOUTCLK1_USE_SYNC : boolean := FALSE; + TXOUTDIV2SEL : integer := 1; + TXPD : boolean := FALSE; + TXPHASESEL : boolean := FALSE; + TXPLLNDIVSEL : integer := 8; + TXPOST_PRDRV_DAC : bit_vector := "111"; + TXPOST_TAP_DAC : bit_vector := "01110"; + TXPOST_TAP_PD : boolean := TRUE; + TXPRE_PRDRV_DAC : bit_vector := "111"; + TXPRE_TAP_DAC : bit_vector := "00000"; + TXPRE_TAP_PD : boolean := TRUE; + TXSLEWRATE : boolean := FALSE; + TXTERMTRIM : bit_vector := "1100"; + TXTUNE : bit_vector := X"0000"; + TX_BUFFER_USE : boolean := TRUE; + TX_CLOCK_DIVIDER : bit_vector := "00"; + VCODAC_INIT : bit_vector := "1010000000"; + VCO_CTRL_ENABLE : boolean := FALSE; + VREFBIASMODE : bit_vector := "11" + + +-- clk-to-output path delays + + ); + +port ( + CHBONDO : out std_logic_vector(4 downto 0); + COMBUSOUT : out std_logic_vector(15 downto 0); + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + RXBUFERR : out std_ulogic; + RXCALFAIL : out std_ulogic; + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCOUT : out std_logic_vector(31 downto 0); + RXCYCLELIMIT : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDISPERR : out std_logic_vector(7 downto 0); + RXLOCK : out std_ulogic; + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXMCLK : out std_ulogic; + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXPCSHCLKOUT : out std_ulogic; + RXREALIGN : out std_ulogic; + RXRECCLK1 : out std_ulogic; + RXRECCLK2 : out std_ulogic; + RXRUNDISP : out std_logic_vector(7 downto 0); + RXSIGDET : out std_ulogic; + RXSTATUS : out std_logic_vector(5 downto 0); + TX1N : out std_ulogic; + TX1P : out std_ulogic; + TXBUFERR : out std_ulogic; + TXCALFAIL : out std_ulogic; + TXCRCOUT : out std_logic_vector(31 downto 0); + TXCYCLELIMIT : out std_ulogic; + TXKERR : out std_logic_vector(7 downto 0); + TXLOCK : out std_ulogic; + TXOUTCLK1 : out std_ulogic; + TXOUTCLK2 : out std_ulogic; + TXPCSHCLKOUT : out std_ulogic; + TXRUNDISP : out std_logic_vector(7 downto 0); + + CHBONDI : in std_logic_vector(4 downto 0); + COMBUSIN : in std_logic_vector(15 downto 0); + DADDR : in std_logic_vector(7 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + GREFCLK : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK1 : in std_ulogic; + REFCLK2 : in std_ulogic; + RX1N : in std_ulogic; + RX1P : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCLKSTABLE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXCRCCLK : in std_ulogic; + RXCRCDATAVALID : in std_ulogic; + RXCRCDATAWIDTH : in std_logic_vector(2 downto 0); + RXCRCIN : in std_logic_vector(63 downto 0); + RXCRCINIT : in std_ulogic; + RXCRCINTCLK : in std_ulogic; + RXCRCPD : in std_ulogic; + RXCRCRESET : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXPMARESET : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXSYNC : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(7 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXCLKSTABLE : in std_ulogic; + TXCRCCLK : in std_ulogic; + TXCRCDATAVALID : in std_ulogic; + TXCRCDATAWIDTH : in std_logic_vector(2 downto 0); + TXCRCIN : in std_logic_vector(63 downto 0); + TXCRCINIT : in std_ulogic; + TXCRCINTCLK : in std_ulogic; + TXCRCPD : in std_ulogic; + TXCRCRESET : in std_ulogic; + TXDATA : in std_logic_vector(63 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXENOOB : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPMARESET : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXSYNC : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end GT11; + +-- Architecture body -- + +architecture GT11_V of GT11 is + + component GT11_SWIFT_BUS + port ( + CHBONDO : out std_logic_vector(4 downto 0); + COMBUSOUT : out std_logic_vector(15 downto 0); + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + RXBUFERR : out std_ulogic; + RXCALFAIL : out std_ulogic; + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCOUT : out std_logic_vector(31 downto 0); + RXCYCLELIMIT : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDISPERR : out std_logic_vector(7 downto 0); + RXLOCK : out std_ulogic; + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXMCLK : out std_ulogic; + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXPCSHCLKOUT : out std_ulogic; + RXREALIGN : out std_ulogic; + RXRECCLK1 : out std_ulogic; + RXRECCLK2 : out std_ulogic; + RXRUNDISP : out std_logic_vector(7 downto 0); + RXSIGDET : out std_ulogic; + RXSTATUS : out std_logic_vector(5 downto 0); + TX1N : out std_ulogic; + TX1P : out std_ulogic; + TXBUFERR : out std_ulogic; + TXCALFAIL : out std_ulogic; + TXCRCOUT : out std_logic_vector(31 downto 0); + TXCYCLELIMIT : out std_ulogic; + TXKERR : out std_logic_vector(7 downto 0); + TXLOCK : out std_ulogic; + TXOUTCLK1 : out std_ulogic; + TXOUTCLK2 : out std_ulogic; + TXPCSHCLKOUT : out std_ulogic; + TXRUNDISP : out std_logic_vector(7 downto 0); + + GT11_MODE : in std_logic_vector(1 downto 0); + + PMACFG : in std_logic_vector(63 downto 0); + PMACFG2 : in std_logic_vector(63 downto 0); + RXACLCFG : in std_logic_vector(63 downto 0); + RXAEQCFG : in std_logic_vector(63 downto 0); + RXAFECFG : in std_logic_vector(63 downto 0); + synDigCfgChnBnd1 : in std_logic_vector(63 downto 0); + synDigCfgChnBnd2 : in std_logic_vector(63 downto 0); + synDigCfgClkCor1 : in std_logic_vector(63 downto 0); + synDigCfgClkCor2 : in std_logic_vector(63 downto 0); + synDigCfgComma1 : in std_logic_vector(63 downto 0); + synDigCfgComma2 : in std_logic_vector(63 downto 0); + synDigCfgCrc : in std_logic_vector(63 downto 0); + synDigCfgMisc : in std_logic_vector(63 downto 0); + synDigCfgSynPmaFD : in std_logic_vector(63 downto 0); + TXACFG : in std_logic_vector(63 downto 0); + TXCLCFG : in std_logic_vector(63 downto 0); + + CHBONDI : in std_logic_vector(4 downto 0); + COMBUSIN : in std_logic_vector(15 downto 0); + DADDR : in std_logic_vector(7 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + GREFCLK : in std_ulogic; + GSR : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK1 : in std_ulogic; + REFCLK2 : in std_ulogic; + RX1N : in std_ulogic; + RX1P : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCLKSTABLE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXCRCCLK : in std_ulogic; + RXCRCDATAVALID : in std_ulogic; + RXCRCDATAWIDTH : in std_logic_vector(2 downto 0); + RXCRCIN : in std_logic_vector(63 downto 0); + RXCRCINIT : in std_ulogic; + RXCRCINTCLK : in std_ulogic; + RXCRCPD : in std_ulogic; + RXCRCRESET : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXPMARESET : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXSYNC : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(7 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXCLKSTABLE : in std_ulogic; + TXCRCCLK : in std_ulogic; + TXCRCDATAVALID : in std_ulogic; + TXCRCDATAWIDTH : in std_logic_vector(2 downto 0); + TXCRCIN : in std_logic_vector(63 downto 0); + TXCRCINIT : in std_ulogic; + TXCRCINTCLK : in std_ulogic; + TXCRCPD : in std_ulogic; + TXCRCRESET : in std_ulogic; + TXDATA : in std_logic_vector(63 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXENOOB : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPMARESET : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXSYNC : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + + ); + end component; + +-- Attribute-to-Cell mapping signals + signal GT11_MODE_BINARY : std_logic_vector(1 downto 0); + + +-- Input/Output Pin signals + + signal GSR_ipd : std_ulogic; + signal CHBONDI_ipd : std_logic_vector(4 downto 0); + signal ENCHANSYNC_ipd : std_ulogic; + signal ENMCOMMAALIGN_ipd : std_ulogic; + signal ENPCOMMAALIGN_ipd : std_ulogic; + signal LOOPBACK_ipd : std_logic_vector(1 downto 0); + signal POWERDOWN_ipd : std_ulogic; + signal RXBLOCKSYNC64B66BUSE_ipd : std_ulogic; + signal RXCOMMADETUSE_ipd : std_ulogic; + signal RXDATAWIDTH_ipd : std_logic_vector(1 downto 0); + signal RXDEC64B66BUSE_ipd : std_ulogic; + signal RXDEC8B10BUSE_ipd : std_ulogic; + signal RXDESCRAM64B66BUSE_ipd : std_ulogic; + signal RXIGNOREBTF_ipd : std_ulogic; + signal RXINTDATAWIDTH_ipd : std_logic_vector(1 downto 0); + signal RXPOLARITY_ipd : std_ulogic; + signal RXRESET_ipd : std_ulogic; + signal RXSLIDE_ipd : std_ulogic; + signal RXUSRCLK_ipd : std_ulogic; + signal RXUSRCLK2_ipd : std_ulogic; + signal TXBYPASS8B10B_ipd : std_logic_vector(7 downto 0); + signal TXCHARDISPMODE_ipd : std_logic_vector(7 downto 0); + signal TXCHARDISPVAL_ipd : std_logic_vector(7 downto 0); + signal TXCHARISK_ipd : std_logic_vector(7 downto 0); + signal TXDATA_ipd : std_logic_vector(63 downto 0); + signal TXDATAWIDTH_ipd : std_logic_vector(1 downto 0); + signal TXENC64B66BUSE_ipd : std_ulogic; + signal TXENC8B10BUSE_ipd : std_ulogic; + signal TXGEARBOX64B66BUSE_ipd : std_ulogic; + signal TXINHIBIT_ipd : std_ulogic; + signal TXINTDATAWIDTH_ipd : std_logic_vector(1 downto 0); + signal TXPOLARITY_ipd : std_ulogic; + signal TXRESET_ipd : std_ulogic; + signal TXSCRAM64B66BUSE_ipd : std_ulogic; + signal TXUSRCLK_ipd : std_ulogic; + signal TXUSRCLK2_ipd : std_ulogic; + signal RXCLKSTABLE_ipd : std_ulogic; + signal RXPMARESET_ipd : std_ulogic; + signal TXCLKSTABLE_ipd : std_ulogic; + signal TXPMARESET_ipd : std_ulogic; + signal RXCRCIN_ipd : std_logic_vector(63 downto 0); + signal RXCRCDATAWIDTH_ipd : std_logic_vector(2 downto 0); + signal RXCRCDATAVALID_ipd : std_ulogic; + signal RXCRCINIT_ipd : std_ulogic; + signal RXCRCRESET_ipd : std_ulogic; + signal RXCRCPD_ipd : std_ulogic; + signal RXCRCCLK_ipd : std_ulogic; + signal RXCRCINTCLK_ipd : std_ulogic; + signal TXCRCIN_ipd : std_logic_vector(63 downto 0); + signal TXCRCDATAWIDTH_ipd : std_logic_vector(2 downto 0); + signal TXCRCDATAVALID_ipd : std_ulogic; + signal TXCRCINIT_ipd : std_ulogic; + signal TXCRCRESET_ipd : std_ulogic; + signal TXCRCPD_ipd : std_ulogic; + signal TXCRCCLK_ipd : std_ulogic; + signal TXCRCINTCLK_ipd : std_ulogic; + signal TXSYNC_ipd : std_ulogic; + signal RXSYNC_ipd : std_ulogic; + signal TXENOOB_ipd : std_ulogic; + signal DCLK_ipd : std_ulogic; + signal DADDR_ipd : std_logic_vector(7 downto 0); + signal DEN_ipd : std_ulogic; + signal DWE_ipd : std_ulogic; + signal DI_ipd : std_logic_vector(15 downto 0); + signal RX1P_ipd : std_ulogic; + signal RX1N_ipd : std_ulogic; + signal GREFCLK_ipd : std_ulogic; + signal REFCLK1_ipd : std_ulogic; + signal REFCLK2_ipd : std_ulogic; + signal COMBUSIN_ipd : std_logic_vector(15 downto 0); + + signal CHBONDO_out : std_logic_vector(4 downto 0); + signal RXSTATUS_out : std_logic_vector(5 downto 0); + signal RXCHARISCOMMA_out : std_logic_vector(7 downto 0); + signal RXCHARISK_out : std_logic_vector(7 downto 0); + signal RXCOMMADET_out : std_ulogic; + signal RXDATA_out : std_logic_vector(63 downto 0); + signal RXDISPERR_out : std_logic_vector(7 downto 0); + signal RXLOSSOFSYNC_out : std_logic_vector(1 downto 0); + signal RXNOTINTABLE_out : std_logic_vector(7 downto 0); + signal RXREALIGN_out : std_ulogic; + signal RXRUNDISP_out : std_logic_vector(7 downto 0); + signal RXBUFERR_out : std_ulogic; + signal TXBUFERR_out : std_ulogic; + signal TXKERR_out : std_logic_vector(7 downto 0); + signal TXRUNDISP_out : std_logic_vector(7 downto 0); + signal RXRECCLK1_out : std_ulogic; + signal RXRECCLK2_out : std_ulogic; + signal TXOUTCLK1_out : std_ulogic; + signal TXOUTCLK2_out : std_ulogic; + signal RXLOCK_out : std_ulogic; + signal TXLOCK_out : std_ulogic; + signal RXCYCLELIMIT_out : std_ulogic; + signal TXCYCLELIMIT_out : std_ulogic; + signal RXCALFAIL_out : std_ulogic; + signal TXCALFAIL_out : std_ulogic; + signal RXCRCOUT_out : std_logic_vector(31 downto 0); + signal TXCRCOUT_out : std_logic_vector(31 downto 0); + signal RXSIGDET_out : std_ulogic; + signal DRDY_out : std_ulogic; + signal DO_out : std_logic_vector(15 downto 0); + signal RXMCLK_out : std_ulogic; + signal TX1P_out : std_ulogic; + signal TX1N_out : std_ulogic; + signal TXPCSHCLKOUT_out : std_ulogic; + signal RXPCSHCLKOUT_out : std_ulogic; + signal COMBUSOUT_out : std_logic_vector(15 downto 0); + + signal PMACFG : std_logic_vector(63 downto 0); + signal PMACFG2 : std_logic_vector(63 downto 0); + signal RXACLCFG : std_logic_vector(63 downto 0); + signal RXAEQCFG : std_logic_vector(63 downto 0); + signal RXAFECFG : std_logic_vector(63 downto 0); + signal TXACFG : std_logic_vector(63 downto 0); + signal TXCLCFG : std_logic_vector(63 downto 0); + signal synDigCfgChnBnd1 : std_logic_vector(63 downto 0); + signal synDigCfgChnBnd2 : std_logic_vector(63 downto 0); + signal synDigCfgClkCor1 : std_logic_vector(63 downto 0); + signal synDigCfgClkCor2 : std_logic_vector(63 downto 0); + signal synDigCfgComma1 : std_logic_vector(63 downto 0); + signal synDigCfgComma2 : std_logic_vector(63 downto 0); + signal synDigCfgCrc : std_logic_vector(63 downto 0); + signal synDigCfgMisc : std_logic_vector(63 downto 0); + signal synDigCfgSynPmaFD : std_logic_vector(63 downto 0); + + +begin + + GSR_ipd <= GSR; + CHBONDI_ipd <= CHBONDI after IN_DELAY; + ENCHANSYNC_ipd <= ENCHANSYNC after IN_DELAY; + ENMCOMMAALIGN_ipd <= ENMCOMMAALIGN after IN_DELAY; + ENPCOMMAALIGN_ipd <= ENPCOMMAALIGN after IN_DELAY; + LOOPBACK_ipd <= LOOPBACK after IN_DELAY; + POWERDOWN_ipd <= POWERDOWN after IN_DELAY; + RXBLOCKSYNC64B66BUSE_ipd <= RXBLOCKSYNC64B66BUSE after IN_DELAY; + RXCOMMADETUSE_ipd <= RXCOMMADETUSE after IN_DELAY; + RXDATAWIDTH_ipd <= RXDATAWIDTH after IN_DELAY; + RXDEC64B66BUSE_ipd <= RXDEC64B66BUSE after IN_DELAY; + RXDEC8B10BUSE_ipd <= RXDEC8B10BUSE after IN_DELAY; + RXDESCRAM64B66BUSE_ipd <= RXDESCRAM64B66BUSE after IN_DELAY; + RXIGNOREBTF_ipd <= RXIGNOREBTF after IN_DELAY; + RXINTDATAWIDTH_ipd <= RXINTDATAWIDTH after IN_DELAY; + RXPOLARITY_ipd <= RXPOLARITY after IN_DELAY; + RXRESET_ipd <= RXRESET after IN_DELAY; + RXSLIDE_ipd <= RXSLIDE after IN_DELAY; + RXUSRCLK_ipd <= RXUSRCLK after IN_DELAY; + RXUSRCLK2_ipd <= RXUSRCLK2 after IN_DELAY; + TXBYPASS8B10B_ipd <= TXBYPASS8B10B after IN_DELAY; + TXCHARDISPMODE_ipd <= TXCHARDISPMODE after IN_DELAY; + TXCHARDISPVAL_ipd <= TXCHARDISPVAL after IN_DELAY; + TXCHARISK_ipd <= TXCHARISK after IN_DELAY; + TXDATA_ipd <= TXDATA after IN_DELAY; + TXDATAWIDTH_ipd <= TXDATAWIDTH after IN_DELAY; + TXENC64B66BUSE_ipd <= TXENC64B66BUSE after IN_DELAY; + TXENC8B10BUSE_ipd <= TXENC8B10BUSE after IN_DELAY; + TXGEARBOX64B66BUSE_ipd <= TXGEARBOX64B66BUSE after IN_DELAY; + TXINHIBIT_ipd <= TXINHIBIT after IN_DELAY; + TXINTDATAWIDTH_ipd <= TXINTDATAWIDTH after IN_DELAY; + TXPOLARITY_ipd <= TXPOLARITY after IN_DELAY; + TXRESET_ipd <= TXRESET after IN_DELAY; + TXSCRAM64B66BUSE_ipd <= TXSCRAM64B66BUSE after IN_DELAY; + TXUSRCLK_ipd <= TXUSRCLK after IN_DELAY; + TXUSRCLK2_ipd <= TXUSRCLK2 after IN_DELAY; + RXCLKSTABLE_ipd <= RXCLKSTABLE after IN_DELAY; + RXPMARESET_ipd <= RXPMARESET after IN_DELAY; + TXCLKSTABLE_ipd <= TXCLKSTABLE after IN_DELAY; + TXPMARESET_ipd <= TXPMARESET after IN_DELAY; + RXCRCIN_ipd <= RXCRCIN after IN_DELAY; + RXCRCDATAWIDTH_ipd <= RXCRCDATAWIDTH after IN_DELAY; + RXCRCDATAVALID_ipd <= RXCRCDATAVALID after IN_DELAY; + RXCRCINIT_ipd <= RXCRCINIT after IN_DELAY; + RXCRCRESET_ipd <= RXCRCRESET after IN_DELAY; + RXCRCPD_ipd <= RXCRCPD after IN_DELAY; + RXCRCCLK_ipd <= RXCRCCLK after IN_DELAY; + RXCRCINTCLK_ipd <= RXCRCINTCLK after IN_DELAY; + TXCRCIN_ipd <= TXCRCIN after IN_DELAY; + TXCRCDATAWIDTH_ipd <= TXCRCDATAWIDTH after IN_DELAY; + TXCRCDATAVALID_ipd <= TXCRCDATAVALID after IN_DELAY; + TXCRCINIT_ipd <= TXCRCINIT after IN_DELAY; + TXCRCRESET_ipd <= TXCRCRESET after IN_DELAY; + TXCRCPD_ipd <= TXCRCPD after IN_DELAY; + TXCRCCLK_ipd <= TXCRCCLK after IN_DELAY; + TXCRCINTCLK_ipd <= TXCRCINTCLK after IN_DELAY; + TXSYNC_ipd <= TXSYNC after IN_DELAY; + RXSYNC_ipd <= RXSYNC after IN_DELAY; + TXENOOB_ipd <= TXENOOB after IN_DELAY; + DCLK_ipd <= DCLK after IN_DELAY; + DADDR_ipd <= DADDR after IN_DELAY; + DEN_ipd <= DEN after IN_DELAY; + DWE_ipd <= DWE after IN_DELAY; + DI_ipd <= DI after IN_DELAY; + RX1P_ipd <= RX1P after IN_DELAY; + RX1N_ipd <= RX1N after IN_DELAY; + GREFCLK_ipd <= GREFCLK after IN_DELAY; + REFCLK1_ipd <= REFCLK1 after IN_DELAY; + REFCLK2_ipd <= REFCLK2 after IN_DELAY; + COMBUSIN_ipd <= COMBUSIN after IN_DELAY; + + gt11_swift_bw_1 : GT11_SWIFT_BUS + port map ( +CHBONDO => CHBONDO_OUT, +COMBUSOUT => COMBUSOUT_OUT, +DO => DO_OUT, +DRDY => DRDY_OUT, +RXBUFERR => RXBUFERR_OUT, +RXCALFAIL => RXCALFAIL_OUT, +RXCHARISCOMMA => RXCHARISCOMMA_OUT, +RXCHARISK => RXCHARISK_OUT, +RXCOMMADET => RXCOMMADET_OUT, +RXCRCOUT => RXCRCOUT_OUT, +RXCYCLELIMIT => RXCYCLELIMIT_OUT, +RXDATA => RXDATA_OUT, +RXDISPERR => RXDISPERR_OUT, +RXLOCK => RXLOCK_OUT, +RXLOSSOFSYNC => RXLOSSOFSYNC_OUT, +RXMCLK => RXMCLK_OUT, +RXNOTINTABLE => RXNOTINTABLE_OUT, +RXPCSHCLKOUT => RXPCSHCLKOUT_OUT, +RXREALIGN => RXREALIGN_OUT, +RXRECCLK1 => RXRECCLK1_OUT, +RXRECCLK2 => RXRECCLK2_OUT, +RXRUNDISP => RXRUNDISP_OUT, +RXSIGDET => RXSIGDET_OUT, +RXSTATUS => RXSTATUS_OUT, +TX1N => TX1N_OUT, +TX1P => TX1P_OUT, +TXBUFERR => TXBUFERR_OUT, +TXCALFAIL => TXCALFAIL_OUT, +TXCRCOUT => TXCRCOUT_OUT, +TXCYCLELIMIT => TXCYCLELIMIT_OUT, +TXKERR => TXKERR_OUT, +TXLOCK => TXLOCK_OUT, +TXOUTCLK1 => TXOUTCLK1_OUT, +TXOUTCLK2 => TXOUTCLK2_OUT, +TXPCSHCLKOUT => TXPCSHCLKOUT_OUT, +TXRUNDISP => TXRUNDISP_OUT, + +GT11_MODE => GT11_MODE_BINARY, + +PMACFG2 => PMACFG2, +PMACFG => PMACFG, +RXACLCFG => RXACLCFG, +RXAEQCFG => RXAEQCFG, +RXAFECFG => RXAFECFG, +synDigCfgChnBnd1 => synDigCfgChnBnd1, +synDigCfgChnBnd2 => synDigCfgChnBnd2, +synDigCfgClkCor1 => synDigCfgClkCor1, +synDigCfgClkCor2 => synDigCfgClkCor2, +synDigCfgComma1 => synDigCfgComma1, +synDigCfgComma2 => synDigCfgComma2, +synDigCfgCrc => synDigCfgCrc, +synDigCfgMisc => synDigCfgMisc, +synDigCfgSynPmaFD => synDigCfgSynPmaFD, +TXACFG => TXACFG, +TXCLCFG => TXCLCFG, + +CHBONDI => CHBONDI_ipd, +COMBUSIN => COMBUSIN_ipd, +DADDR => DADDR_ipd, +DCLK => DCLK_ipd, +DEN => DEN_ipd, +DI => DI_ipd, +DWE => DWE_ipd, +ENCHANSYNC => ENCHANSYNC_ipd, +ENMCOMMAALIGN => ENMCOMMAALIGN_ipd, +ENPCOMMAALIGN => ENPCOMMAALIGN_ipd, +GREFCLK => GREFCLK_ipd, +GSR => GSR_ipd, +LOOPBACK => LOOPBACK_ipd, +POWERDOWN => POWERDOWN_ipd, +REFCLK1 => REFCLK1_ipd, +REFCLK2 => REFCLK2_ipd, +RX1N => RX1N_ipd, +RX1P => RX1P_ipd, +RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE_ipd, +RXCLKSTABLE => RXCLKSTABLE_ipd, +RXCOMMADETUSE => RXCOMMADETUSE_ipd, +RXCRCCLK => RXCRCCLK_ipd, +RXCRCDATAVALID => RXCRCDATAVALID_ipd, +RXCRCDATAWIDTH => RXCRCDATAWIDTH_ipd, +RXCRCIN => RXCRCIN_ipd, +RXCRCINIT => RXCRCINIT_ipd, +RXCRCINTCLK => RXCRCINTCLK_ipd, +RXCRCPD => RXCRCPD_ipd, +RXCRCRESET => RXCRCRESET_ipd, +RXDATAWIDTH => RXDATAWIDTH_ipd, +RXDEC8B10BUSE => RXDEC8B10BUSE_ipd, +RXDEC64B66BUSE => RXDEC64B66BUSE_ipd, +RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE_ipd, +RXIGNOREBTF => RXIGNOREBTF_ipd, +RXINTDATAWIDTH => RXINTDATAWIDTH_ipd, +RXPMARESET => RXPMARESET_ipd, +RXPOLARITY => RXPOLARITY_ipd, +RXRESET => RXRESET_ipd, +RXSLIDE => RXSLIDE_ipd, +RXSYNC => RXSYNC_ipd, +RXUSRCLK => RXUSRCLK_ipd, +RXUSRCLK2 => RXUSRCLK2_ipd, +TXBYPASS8B10B => TXBYPASS8B10B_ipd, +TXCHARDISPMODE => TXCHARDISPMODE_ipd, +TXCHARDISPVAL => TXCHARDISPVAL_ipd, +TXCHARISK => TXCHARISK_ipd, +TXCLKSTABLE => TXCLKSTABLE_ipd, +TXCRCCLK => TXCRCCLK_ipd, +TXCRCDATAVALID => TXCRCDATAVALID_ipd, +TXCRCDATAWIDTH => TXCRCDATAWIDTH_ipd, +TXCRCIN => TXCRCIN_ipd, +TXCRCINIT => TXCRCINIT_ipd, +TXCRCINTCLK => TXCRCINTCLK_ipd, +TXCRCPD => TXCRCPD_ipd, +TXCRCRESET => TXCRCRESET_ipd, +TXDATA => TXDATA_ipd, +TXDATAWIDTH => TXDATAWIDTH_ipd, +TXENC8B10BUSE => TXENC8B10BUSE_ipd, +TXENC64B66BUSE => TXENC64B66BUSE_ipd, +TXENOOB => TXENOOB_ipd, +TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE_ipd, +TXINHIBIT => TXINHIBIT_ipd, +TXINTDATAWIDTH => TXINTDATAWIDTH_ipd, +TXPMARESET => TXPMARESET_ipd, +TXPOLARITY => TXPOLARITY_ipd, +TXRESET => TXRESET_ipd, +TXSCRAM64B66BUSE => TXSCRAM64B66BUSE_ipd, +TXSYNC => TXSYNC_ipd, +TXUSRCLK => TXUSRCLK_ipd, +TXUSRCLK2 => TXUSRCLK2_ipd + ); + + INIPROC : process + variable CHAN_BOND_SEQ_1_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1); + variable CHAN_BOND_SEQ_1_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2); + variable CHAN_BOND_SEQ_1_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3); + variable CHAN_BOND_SEQ_1_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4); + variable CHAN_BOND_SEQ_1_MASK_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_MASK); + variable CHAN_BOND_LIMIT_BINARY : std_logic_vector(5 downto 0); + variable CHAN_BOND_MODE_BINARY : std_logic_vector(1 downto 0); + variable CHAN_BOND_ONE_SHOT_BINARY : std_ulogic; + variable CHAN_BOND_SEQ_2_USE_BINARY : std_ulogic; + variable CHAN_BOND_SEQ_LEN_BINARY : std_logic_vector(2 downto 0); + variable RX_BUFFER_USE_BINARY : std_ulogic; + variable TX_BUFFER_USE_BINARY : std_ulogic; + variable CHAN_BOND_SEQ_2_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1); + variable CHAN_BOND_SEQ_2_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2); + variable CHAN_BOND_SEQ_2_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3); + variable CHAN_BOND_SEQ_2_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4); + variable CHAN_BOND_SEQ_2_MASK_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_MASK); + variable POWER_ENABLE_BINARY : std_ulogic; + variable OPPOSITE_SELECT_BINARY : std_ulogic; + variable CCCB_ARBITRATOR_DISABLE_BINARY : std_ulogic; + variable CLK_COR_SEQ_1_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1); + variable CLK_COR_SEQ_1_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2); + variable CLK_COR_SEQ_1_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3); + variable CLK_COR_SEQ_1_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4); + variable CLK_COR_SEQ_1_MASK_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_MASK); + variable DIGRX_SYNC_MODE_BINARY : std_ulogic; + variable DIGRX_FWDCLK_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(DIGRX_FWDCLK); + variable PCS_BIT_SLIP_BINARY : std_ulogic; + variable CLK_COR_MIN_LAT_BINARY : std_logic_vector(5 downto 0); + variable TXDATA_SEL_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(TXDATA_SEL); + variable RXDATA_SEL_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXDATA_SEL); + variable CLK_COR_SEQ_2_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1); + variable CLK_COR_SEQ_2_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2); + variable CLK_COR_SEQ_2_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3); + variable CLK_COR_SEQ_2_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4); + variable CLK_COR_SEQ_2_MASK_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_MASK); + variable CLK_COR_MAX_LAT_BINARY : std_logic_vector(5 downto 0); + variable CLK_COR_SEQ_2_USE_BINARY : std_ulogic; + variable CLK_COR_SEQ_DROP_BINARY : std_ulogic; + variable CLK_COR_SEQ_LEN_BINARY : std_logic_vector(2 downto 0); + variable CLK_CORRECT_USE_BINARY : std_ulogic; + variable CLK_COR_8B10B_DE_BINARY : std_ulogic; + variable SH_CNT_MAX_BINARY : std_logic_vector(7 downto 0); + variable SH_INVALID_CNT_MAX_BINARY : std_logic_vector(7 downto 0); + variable ALIGN_COMMA_WORD_BINARY : std_logic_vector(1 downto 0); + variable DEC_MCOMMA_DETECT_BINARY : std_ulogic; + variable DEC_PCOMMA_DETECT_BINARY : std_ulogic; + variable DEC_VALID_COMMA_ONLY_BINARY : std_ulogic; + variable MCOMMA_DETECT_BINARY : std_ulogic; + variable PCOMMA_DETECT_BINARY : std_ulogic; + variable COMMA32_BINARY : std_ulogic; + variable COMMA_10B_MASK_BINARY : std_logic_vector(9 downto 0) := (To_StdLogicVector(COMMA_10B_MASK)(9 downto 0)); + variable MCOMMA_32B_VALUE_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(MCOMMA_32B_VALUE); + variable PCOMMA_32B_VALUE_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(PCOMMA_32B_VALUE); + variable RXUSRDIVISOR_BINARY : std_logic_vector(4 downto 0); + variable DCDR_FILTER_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(DCDR_FILTER); + variable SAMPLE_8X_BINARY : std_ulogic; + variable ENABLE_DCDR_BINARY : std_ulogic; + variable REPEATER_BINARY : std_ulogic; + variable RXBY_32_BINARY : std_ulogic; + variable TXFDCAL_CLOCK_DIVIDE_BINARY : std_logic_vector(1 downto 0); + variable RXFDCAL_CLOCK_DIVIDE_BINARY : std_logic_vector(1 downto 0); + variable RXCYCLE_LIMIT_SEL_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXCYCLE_LIMIT_SEL); + variable RXVCO_CTRL_ENABLE_BINARY : std_ulogic; + variable RXFDET_LCK_SEL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(RXFDET_LCK_SEL); + variable RXFDET_HYS_SEL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(RXFDET_HYS_SEL); + variable RXFDET_LCK_CAL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(RXFDET_LCK_CAL); + variable RXFDET_HYS_CAL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(RXFDET_HYS_CAL); + variable RXLOOPCAL_WAIT_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXLOOPCAL_WAIT); + variable RXSLOWDOWN_CAL_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXSLOWDOWN_CAL); + variable RXVCODAC_INIT_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(RXVCODAC_INIT); + variable CYCLE_LIMIT_SEL_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(CYCLE_LIMIT_SEL); + variable VCO_CTRL_ENABLE_BINARY : std_ulogic; + variable FDET_LCK_SEL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(FDET_LCK_SEL); + variable FDET_HYS_SEL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(FDET_HYS_SEL); + variable FDET_LCK_CAL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(FDET_LCK_CAL); + variable FDET_HYS_CAL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(FDET_HYS_CAL); + variable LOOPCAL_WAIT_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(LOOPCAL_WAIT); + variable SLOWDOWN_CAL_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(SLOWDOWN_CAL); + variable VCODAC_INIT_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(VCODAC_INIT); + variable RXCRCCLOCKDOUBLE_BINARY : std_ulogic; + variable RXCRCINVERTGEN_BINARY : std_ulogic; + variable RXCRCSAMECLOCK_BINARY : std_ulogic; + variable RXCRCENABLE_BINARY : std_ulogic; + variable RXCRCINITVAL_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(RXCRCINITVAL); + variable TXCRCCLOCKDOUBLE_BINARY : std_ulogic; + variable TXCRCINVERTGEN_BINARY : std_ulogic; + variable TXCRCSAMECLOCK_BINARY : std_ulogic; + variable TXCRCINITVAL_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(TXCRCINITVAL); + variable TXCRCENABLE_BINARY : std_ulogic; + variable RX_CLOCK_DIVIDER_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RX_CLOCK_DIVIDER); + variable TX_CLOCK_DIVIDER_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(TX_CLOCK_DIVIDER); + variable RXCLK0_FORCE_PMACLK_BINARY : std_ulogic; + variable TXCLK0_FORCE_PMACLK_BINARY : std_ulogic; + variable TXOUTCLK1_USE_SYNC_BINARY : std_ulogic; + variable RXRECCLK1_USE_SYNC_BINARY : std_ulogic; + variable RXPMACLKSEL_BINARY : std_logic_vector(1 downto 0); + variable TXABPMACLKSEL_BINARY : std_logic_vector(1 downto 0); + variable RXAREGCTRL_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXAREGCTRL); + variable PMAVBGCTRL_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(PMAVBGCTRL); + variable BANDGAPSEL_BINARY : std_ulogic; + variable PMAIREFTRIM_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(PMAIREFTRIM); + variable IREFBIASMODE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(IREFBIASMODE); + variable BIASRESSEL_BINARY : std_ulogic; + variable PMAVREFTRIM_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(PMAVREFTRIM); + variable VREFBIASMODE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(VREFBIASMODE); + variable TXPHASESEL_BINARY : std_ulogic; + variable PMACLKENABLE_BINARY : std_ulogic; + variable PMACOREPWRENABLE_BINARY : std_ulogic; + variable RXMODE_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(RXMODE); + variable PMA_BIT_SLIP_BINARY : std_ulogic; + variable RXASYNCDIVIDE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXASYNCDIVIDE); + variable RXCLKMODE_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(RXCLKMODE); + variable RXLB_BINARY : std_ulogic; + variable RXFETUNE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXFETUNE); + variable RXRCPADJ_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(RXRCPADJ); + variable RXRIBADJ_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXRIBADJ); + variable RXAFEEQ_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(RXAFEEQ); + variable RXCMADJ_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXCMADJ); + variable RXCDRLOS_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(RXCDRLOS); + variable RXDCCOUPLE_BINARY : std_ulogic; + variable RXLKADJ_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXLKADJ); + variable RXDIGRESET_BINARY : std_ulogic; + variable RXFECONTROL2_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(RXFECONTROL2); + variable RXCPTST_BINARY : std_ulogic; + variable RXPDDTST_BINARY : std_ulogic; + variable RXACTST_BINARY : std_ulogic; + variable RXAFETST_BINARY : std_ulogic; + variable RXFECONTROL1_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXFECONTROL1); + variable RXLKAPD_BINARY : std_ulogic; + variable RXRSDPD_BINARY : std_ulogic; + variable RXRCPPD_BINARY : std_ulogic; + variable RXRPDPD_BINARY : std_ulogic; + variable RXAFEPD_BINARY : std_ulogic; + variable RXPD_BINARY : std_ulogic; + variable RXEQ_BINARY : std_logic_vector(63 downto 0) := To_StdLogicVector(RXEQ); + variable TXOUTDIV2SEL_BINARY : std_logic_vector(3 downto 0); + variable TXPLLNDIVSEL_BINARY : std_logic_vector(3 downto 0); + variable TXCLMODE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(TXCLMODE); + variable TXLOOPFILT_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(TXLOOPFILT); + variable TXTUNE_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(TXTUNE)(12 downto 0); + variable TXCPSEL_BINARY : std_ulogic; + variable TXCTRL1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(TXCTRL1)(9 downto 0); + variable TXAPD_BINARY : std_ulogic; + variable TXLVLSHFTPD_BINARY : std_ulogic; + variable TXPRE_PRDRV_DAC_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TXPRE_PRDRV_DAC); + variable TXPRE_TAP_PD_BINARY : std_ulogic; + variable TXPRE_TAP_DAC_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TXPRE_TAP_DAC); + variable TXDIGPD_BINARY : std_ulogic; + variable TXCLKMODE_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(TXCLKMODE); + variable TXHIGHSIGNALEN_BINARY : std_ulogic; + variable TXAREFBIASSEL_BINARY : std_ulogic; + variable TXTERMTRIM_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(TXTERMTRIM); + variable TXASYNCDIVIDE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(TXASYNCDIVIDE); + variable TXSLEWRATE_BINARY : std_ulogic; + variable TXPOST_PRDRV_DAC_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TXPOST_PRDRV_DAC); + variable TXDAT_PRDRV_DAC_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TXDAT_PRDRV_DAC); + variable TXPOST_TAP_PD_BINARY : std_ulogic; + variable TXPOST_TAP_DAC_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TXPOST_TAP_DAC); + variable TXDAT_TAP_DAC_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TXDAT_TAP_DAC); + variable TXPD_BINARY : std_ulogic; + variable RXOUTDIV2SEL_BINARY : std_logic_vector(7 downto 0); + variable RXPLLNDIVSEL_BINARY : std_logic_vector(3 downto 0); + variable RXCLMODE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXCLMODE); + variable RXLOOPFILT_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RXLOOPFILT); + variable RXDIGRX_BINARY : std_ulogic; + variable RXTUNE_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(RXTUNE)(12 downto 0); + variable RXCPSEL_BINARY : std_ulogic; + variable RXCTRL1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(RXCTRL1)(9 downto 0); + variable RXAPD_BINARY : std_ulogic; + begin +-- case GT11_MODE is + if((GT11_MODE = "B") or (GT11_MODE = "b")) then + GT11_MODE_BINARY <= "00"; + elsif((GT11_MODE = "A") or (GT11_MODE = "a")) then + GT11_MODE_BINARY <= "01"; + elsif((GT11_MODE = "DONT_CARE") or (GT11_MODE = "dont_care")) then + GT11_MODE_BINARY <= "10"; + elsif((GT11_MODE = "SINGLE") or (GT11_MODE = "single")) then + GT11_MODE_BINARY <= "11"; + else + assert FALSE report "Error : GT11_MODE = is not DONT_CARE, A, B, SINGLE." severity error; + end if; +-- end case; + case CHAN_BOND_LIMIT is + when 0 => CHAN_BOND_LIMIT_BINARY := "000000"; + when 1 => CHAN_BOND_LIMIT_BINARY := "000001"; + when 2 => CHAN_BOND_LIMIT_BINARY := "000010"; + when 3 => CHAN_BOND_LIMIT_BINARY := "000011"; + when 4 => CHAN_BOND_LIMIT_BINARY := "000100"; + when 5 => CHAN_BOND_LIMIT_BINARY := "000101"; + when 6 => CHAN_BOND_LIMIT_BINARY := "000110"; + when 7 => CHAN_BOND_LIMIT_BINARY := "000111"; + when 8 => CHAN_BOND_LIMIT_BINARY := "001000"; + when 9 => CHAN_BOND_LIMIT_BINARY := "001001"; + when 10 => CHAN_BOND_LIMIT_BINARY := "001010"; + when 11 => CHAN_BOND_LIMIT_BINARY := "001011"; + when 12 => CHAN_BOND_LIMIT_BINARY := "001100"; + when 13 => CHAN_BOND_LIMIT_BINARY := "001101"; + when 14 => CHAN_BOND_LIMIT_BINARY := "001110"; + when 15 => CHAN_BOND_LIMIT_BINARY := "001111"; + when 16 => CHAN_BOND_LIMIT_BINARY := "010000"; + when 17 => CHAN_BOND_LIMIT_BINARY := "010001"; + when 18 => CHAN_BOND_LIMIT_BINARY := "010010"; + when 19 => CHAN_BOND_LIMIT_BINARY := "010011"; + when 20 => CHAN_BOND_LIMIT_BINARY := "010100"; + when 21 => CHAN_BOND_LIMIT_BINARY := "010101"; + when 22 => CHAN_BOND_LIMIT_BINARY := "010110"; + when 23 => CHAN_BOND_LIMIT_BINARY := "010111"; + when 24 => CHAN_BOND_LIMIT_BINARY := "011000"; + when 25 => CHAN_BOND_LIMIT_BINARY := "011001"; + when 26 => CHAN_BOND_LIMIT_BINARY := "011010"; + when 27 => CHAN_BOND_LIMIT_BINARY := "011011"; + when 28 => CHAN_BOND_LIMIT_BINARY := "011100"; + when 29 => CHAN_BOND_LIMIT_BINARY := "011101"; + when 30 => CHAN_BOND_LIMIT_BINARY := "011110"; + when 31 => CHAN_BOND_LIMIT_BINARY := "011111"; + when others => assert FALSE report "Error : CHAN_BOND_LIMIT is not in range 0...31." severity error; + end case; +-- case CHAN_BOND_MODE is + if((CHAN_BOND_MODE = "NONE") or (CHAN_BOND_MODE = "none")) then + CHAN_BOND_MODE_BINARY := "00"; + elsif((CHAN_BOND_MODE = "MASTER") or (CHAN_BOND_MODE = "master")) then + CHAN_BOND_MODE_BINARY := "01"; + elsif((CHAN_BOND_MODE = "SLAVE_1_HOP") or (CHAN_BOND_MODE = "slave_1_hop")) then + CHAN_BOND_MODE_BINARY := "10"; + elsif((CHAN_BOND_MODE = "SLAVE_2_HOPS") or (CHAN_BOND_MODE = "slave_2_hops")) then + CHAN_BOND_MODE_BINARY := "11"; + else + assert FALSE report "Error : CHAN_BOND_MODE = is not NONE, MASTER, SLAVE_1_HOP, SLAVE_2_HOPS." severity error; + end if; +-- end case; + case CHAN_BOND_ONE_SHOT is + when FALSE => CHAN_BOND_ONE_SHOT_BINARY := '0'; + when TRUE => CHAN_BOND_ONE_SHOT_BINARY := '1'; + when others => assert FALSE report "Error : CHAN_BOND_ONE_SHOT is neither TRUE nor FALSE." severity error; + end case; + case CHAN_BOND_SEQ_2_USE is + when FALSE => CHAN_BOND_SEQ_2_USE_BINARY := '0'; + when TRUE => CHAN_BOND_SEQ_2_USE_BINARY := '1'; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_2_USE is neither TRUE nor FALSE." severity error; + end case; + case CHAN_BOND_SEQ_LEN is + when 1 => CHAN_BOND_SEQ_LEN_BINARY := "000"; + when 2 => CHAN_BOND_SEQ_LEN_BINARY := "001"; + when 3 => CHAN_BOND_SEQ_LEN_BINARY := "010"; + when 4 => CHAN_BOND_SEQ_LEN_BINARY := "011"; + when 8 => CHAN_BOND_SEQ_LEN_BINARY := "111"; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_LEN is not in 1, 2, 3, 4, 8." severity error; + end case; + case RX_BUFFER_USE is + when FALSE => RX_BUFFER_USE_BINARY := '0'; + when TRUE => RX_BUFFER_USE_BINARY := '1'; + when others => assert FALSE report "Error : RX_BUFFER_USE is neither TRUE nor FALSE." severity error; + end case; + case TX_BUFFER_USE is + when FALSE => TX_BUFFER_USE_BINARY := '0'; + when TRUE => TX_BUFFER_USE_BINARY := '1'; + when others => assert FALSE report "Error : TX_BUFFER_USE is neither TRUE nor FALSE." severity error; + end case; + case POWER_ENABLE is + when FALSE => POWER_ENABLE_BINARY := '0'; + when TRUE => POWER_ENABLE_BINARY := '1'; + when others => assert FALSE report "Error : POWER_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case OPPOSITE_SELECT is + when FALSE => OPPOSITE_SELECT_BINARY := '0'; + when TRUE => OPPOSITE_SELECT_BINARY := '1'; + when others => assert FALSE report "Error : OPPOSITE_SELECT is neither TRUE nor FALSE." severity error; + end case; + case CCCB_ARBITRATOR_DISABLE is + when FALSE => CCCB_ARBITRATOR_DISABLE_BINARY := '0'; + when TRUE => CCCB_ARBITRATOR_DISABLE_BINARY := '1'; + when others => assert FALSE report "Error : CCCB_ARBITRATOR_DISABLE is neither TRUE nor FALSE." severity error; + end case; + case DIGRX_SYNC_MODE is + when FALSE => DIGRX_SYNC_MODE_BINARY := '0'; + when TRUE => DIGRX_SYNC_MODE_BINARY := '1'; + when others => assert FALSE report "Error : DIGRX_SYNC_MODE is neither TRUE nor FALSE." severity error; + end case; + case PCS_BIT_SLIP is + when FALSE => PCS_BIT_SLIP_BINARY := '0'; + when TRUE => PCS_BIT_SLIP_BINARY := '1'; + when others => assert FALSE report "Error : PCS_BIT_SLIP is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_MIN_LAT is + when 0 => CLK_COR_MIN_LAT_BINARY := "000000"; + when 1 => CLK_COR_MIN_LAT_BINARY := "000001"; + when 2 => CLK_COR_MIN_LAT_BINARY := "000010"; + when 3 => CLK_COR_MIN_LAT_BINARY := "000011"; + when 4 => CLK_COR_MIN_LAT_BINARY := "000100"; + when 5 => CLK_COR_MIN_LAT_BINARY := "000101"; + when 6 => CLK_COR_MIN_LAT_BINARY := "000110"; + when 7 => CLK_COR_MIN_LAT_BINARY := "000111"; + when 8 => CLK_COR_MIN_LAT_BINARY := "001000"; + when 9 => CLK_COR_MIN_LAT_BINARY := "001001"; + when 10 => CLK_COR_MIN_LAT_BINARY := "001010"; + when 11 => CLK_COR_MIN_LAT_BINARY := "001011"; + when 12 => CLK_COR_MIN_LAT_BINARY := "001100"; + when 13 => CLK_COR_MIN_LAT_BINARY := "001101"; + when 14 => CLK_COR_MIN_LAT_BINARY := "001110"; + when 15 => CLK_COR_MIN_LAT_BINARY := "001111"; + when 16 => CLK_COR_MIN_LAT_BINARY := "010000"; + when 17 => CLK_COR_MIN_LAT_BINARY := "010001"; + when 18 => CLK_COR_MIN_LAT_BINARY := "010010"; + when 19 => CLK_COR_MIN_LAT_BINARY := "010011"; + when 20 => CLK_COR_MIN_LAT_BINARY := "010100"; + when 21 => CLK_COR_MIN_LAT_BINARY := "010101"; + when 22 => CLK_COR_MIN_LAT_BINARY := "010110"; + when 23 => CLK_COR_MIN_LAT_BINARY := "010111"; + when 24 => CLK_COR_MIN_LAT_BINARY := "011000"; + when 25 => CLK_COR_MIN_LAT_BINARY := "011001"; + when 26 => CLK_COR_MIN_LAT_BINARY := "011010"; + when 27 => CLK_COR_MIN_LAT_BINARY := "011011"; + when 28 => CLK_COR_MIN_LAT_BINARY := "011100"; + when 29 => CLK_COR_MIN_LAT_BINARY := "011101"; + when 30 => CLK_COR_MIN_LAT_BINARY := "011110"; + when 31 => CLK_COR_MIN_LAT_BINARY := "011111"; + when 32 => CLK_COR_MIN_LAT_BINARY := "100000"; + when 33 => CLK_COR_MIN_LAT_BINARY := "100001"; + when 34 => CLK_COR_MIN_LAT_BINARY := "100010"; + when 35 => CLK_COR_MIN_LAT_BINARY := "100011"; + when 36 => CLK_COR_MIN_LAT_BINARY := "100100"; + when 37 => CLK_COR_MIN_LAT_BINARY := "100101"; + when 38 => CLK_COR_MIN_LAT_BINARY := "100110"; + when 39 => CLK_COR_MIN_LAT_BINARY := "100111"; + when 40 => CLK_COR_MIN_LAT_BINARY := "101000"; + when 41 => CLK_COR_MIN_LAT_BINARY := "101001"; + when 42 => CLK_COR_MIN_LAT_BINARY := "101010"; + when 43 => CLK_COR_MIN_LAT_BINARY := "101011"; + when 44 => CLK_COR_MIN_LAT_BINARY := "101100"; + when 45 => CLK_COR_MIN_LAT_BINARY := "101101"; + when 46 => CLK_COR_MIN_LAT_BINARY := "101110"; + when 47 => CLK_COR_MIN_LAT_BINARY := "101111"; + when 48 => CLK_COR_MIN_LAT_BINARY := "110000"; + when 49 => CLK_COR_MIN_LAT_BINARY := "110001"; + when 50 => CLK_COR_MIN_LAT_BINARY := "110010"; + when 51 => CLK_COR_MIN_LAT_BINARY := "110011"; + when 52 => CLK_COR_MIN_LAT_BINARY := "110100"; + when 53 => CLK_COR_MIN_LAT_BINARY := "110101"; + when 54 => CLK_COR_MIN_LAT_BINARY := "110110"; + when 55 => CLK_COR_MIN_LAT_BINARY := "110111"; + when 56 => CLK_COR_MIN_LAT_BINARY := "111000"; + when 57 => CLK_COR_MIN_LAT_BINARY := "111001"; + when 58 => CLK_COR_MIN_LAT_BINARY := "111010"; + when 59 => CLK_COR_MIN_LAT_BINARY := "111011"; + when 60 => CLK_COR_MIN_LAT_BINARY := "111100"; + when 61 => CLK_COR_MIN_LAT_BINARY := "111101"; + when 62 => CLK_COR_MIN_LAT_BINARY := "111110"; + when 63 => CLK_COR_MIN_LAT_BINARY := "111111"; + when others => assert FALSE report "Error : CLK_COR_MIN_LAT is not in range 0...63." severity error; + end case; + case CLK_COR_MAX_LAT is + when 0 => CLK_COR_MAX_LAT_BINARY := "000000"; + when 1 => CLK_COR_MAX_LAT_BINARY := "000001"; + when 2 => CLK_COR_MAX_LAT_BINARY := "000010"; + when 3 => CLK_COR_MAX_LAT_BINARY := "000011"; + when 4 => CLK_COR_MAX_LAT_BINARY := "000100"; + when 5 => CLK_COR_MAX_LAT_BINARY := "000101"; + when 6 => CLK_COR_MAX_LAT_BINARY := "000110"; + when 7 => CLK_COR_MAX_LAT_BINARY := "000111"; + when 8 => CLK_COR_MAX_LAT_BINARY := "001000"; + when 9 => CLK_COR_MAX_LAT_BINARY := "001001"; + when 10 => CLK_COR_MAX_LAT_BINARY := "001010"; + when 11 => CLK_COR_MAX_LAT_BINARY := "001011"; + when 12 => CLK_COR_MAX_LAT_BINARY := "001100"; + when 13 => CLK_COR_MAX_LAT_BINARY := "001101"; + when 14 => CLK_COR_MAX_LAT_BINARY := "001110"; + when 15 => CLK_COR_MAX_LAT_BINARY := "001111"; + when 16 => CLK_COR_MAX_LAT_BINARY := "010000"; + when 17 => CLK_COR_MAX_LAT_BINARY := "010001"; + when 18 => CLK_COR_MAX_LAT_BINARY := "010010"; + when 19 => CLK_COR_MAX_LAT_BINARY := "010011"; + when 20 => CLK_COR_MAX_LAT_BINARY := "010100"; + when 21 => CLK_COR_MAX_LAT_BINARY := "010101"; + when 22 => CLK_COR_MAX_LAT_BINARY := "010110"; + when 23 => CLK_COR_MAX_LAT_BINARY := "010111"; + when 24 => CLK_COR_MAX_LAT_BINARY := "011000"; + when 25 => CLK_COR_MAX_LAT_BINARY := "011001"; + when 26 => CLK_COR_MAX_LAT_BINARY := "011010"; + when 27 => CLK_COR_MAX_LAT_BINARY := "011011"; + when 28 => CLK_COR_MAX_LAT_BINARY := "011100"; + when 29 => CLK_COR_MAX_LAT_BINARY := "011101"; + when 30 => CLK_COR_MAX_LAT_BINARY := "011110"; + when 31 => CLK_COR_MAX_LAT_BINARY := "011111"; + when 32 => CLK_COR_MAX_LAT_BINARY := "100000"; + when 33 => CLK_COR_MAX_LAT_BINARY := "100001"; + when 34 => CLK_COR_MAX_LAT_BINARY := "100010"; + when 35 => CLK_COR_MAX_LAT_BINARY := "100011"; + when 36 => CLK_COR_MAX_LAT_BINARY := "100100"; + when 37 => CLK_COR_MAX_LAT_BINARY := "100101"; + when 38 => CLK_COR_MAX_LAT_BINARY := "100110"; + when 39 => CLK_COR_MAX_LAT_BINARY := "100111"; + when 40 => CLK_COR_MAX_LAT_BINARY := "101000"; + when 41 => CLK_COR_MAX_LAT_BINARY := "101001"; + when 42 => CLK_COR_MAX_LAT_BINARY := "101010"; + when 43 => CLK_COR_MAX_LAT_BINARY := "101011"; + when 44 => CLK_COR_MAX_LAT_BINARY := "101100"; + when 45 => CLK_COR_MAX_LAT_BINARY := "101101"; + when 46 => CLK_COR_MAX_LAT_BINARY := "101110"; + when 47 => CLK_COR_MAX_LAT_BINARY := "101111"; + when 48 => CLK_COR_MAX_LAT_BINARY := "110000"; + when 49 => CLK_COR_MAX_LAT_BINARY := "110001"; + when 50 => CLK_COR_MAX_LAT_BINARY := "110010"; + when 51 => CLK_COR_MAX_LAT_BINARY := "110011"; + when 52 => CLK_COR_MAX_LAT_BINARY := "110100"; + when 53 => CLK_COR_MAX_LAT_BINARY := "110101"; + when 54 => CLK_COR_MAX_LAT_BINARY := "110110"; + when 55 => CLK_COR_MAX_LAT_BINARY := "110111"; + when 56 => CLK_COR_MAX_LAT_BINARY := "111000"; + when 57 => CLK_COR_MAX_LAT_BINARY := "111001"; + when 58 => CLK_COR_MAX_LAT_BINARY := "111010"; + when 59 => CLK_COR_MAX_LAT_BINARY := "111011"; + when 60 => CLK_COR_MAX_LAT_BINARY := "111100"; + when 61 => CLK_COR_MAX_LAT_BINARY := "111101"; + when 62 => CLK_COR_MAX_LAT_BINARY := "111110"; + when 63 => CLK_COR_MAX_LAT_BINARY := "111111"; + when others => assert FALSE report "Error : CLK_COR_MAX_LAT is not in range 0...63." severity error; + end case; + case CLK_COR_SEQ_2_USE is + when FALSE => CLK_COR_SEQ_2_USE_BINARY := '0'; + when TRUE => CLK_COR_SEQ_2_USE_BINARY := '1'; + when others => assert FALSE report "Error : CLK_COR_SEQ_2_USE is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_SEQ_DROP is + when FALSE => CLK_COR_SEQ_DROP_BINARY := '0'; + when TRUE => CLK_COR_SEQ_DROP_BINARY := '1'; + when others => assert FALSE report "Error : CLK_COR_SEQ_DROP is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_SEQ_LEN is + when 1 => CLK_COR_SEQ_LEN_BINARY := "000"; + when 2 => CLK_COR_SEQ_LEN_BINARY := "001"; + when 3 => CLK_COR_SEQ_LEN_BINARY := "010"; + when 4 => CLK_COR_SEQ_LEN_BINARY := "011"; + when 8 => CLK_COR_SEQ_LEN_BINARY := "111"; + when others => assert FALSE report "Error : CLK_COR_SEQ_LEN is not in 1, 2, 3, 4, 8." severity error; + end case; + case CLK_CORRECT_USE is + when FALSE => CLK_CORRECT_USE_BINARY := '0'; + when TRUE => CLK_CORRECT_USE_BINARY := '1'; + when others => assert FALSE report "Error : CLK_CORRECT_USE is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_8B10B_DE is + when FALSE => CLK_COR_8B10B_DE_BINARY := '0'; + when TRUE => CLK_COR_8B10B_DE_BINARY := '1'; + when others => assert FALSE report "Error : CLK_COR_8B10B_DE is neither TRUE nor FALSE." severity error; + end case; + case SH_CNT_MAX is + when 0 => SH_CNT_MAX_BINARY := "00000000"; + when 1 => SH_CNT_MAX_BINARY := "00000001"; + when 2 => SH_CNT_MAX_BINARY := "00000010"; + when 3 => SH_CNT_MAX_BINARY := "00000011"; + when 4 => SH_CNT_MAX_BINARY := "00000100"; + when 5 => SH_CNT_MAX_BINARY := "00000101"; + when 6 => SH_CNT_MAX_BINARY := "00000110"; + when 7 => SH_CNT_MAX_BINARY := "00000111"; + when 8 => SH_CNT_MAX_BINARY := "00001000"; + when 9 => SH_CNT_MAX_BINARY := "00001001"; + when 10 => SH_CNT_MAX_BINARY := "00001010"; + when 11 => SH_CNT_MAX_BINARY := "00001011"; + when 12 => SH_CNT_MAX_BINARY := "00001100"; + when 13 => SH_CNT_MAX_BINARY := "00001101"; + when 14 => SH_CNT_MAX_BINARY := "00001110"; + when 15 => SH_CNT_MAX_BINARY := "00001111"; + when 16 => SH_CNT_MAX_BINARY := "00010000"; + when 17 => SH_CNT_MAX_BINARY := "00010001"; + when 18 => SH_CNT_MAX_BINARY := "00010010"; + when 19 => SH_CNT_MAX_BINARY := "00010011"; + when 20 => SH_CNT_MAX_BINARY := "00010100"; + when 21 => SH_CNT_MAX_BINARY := "00010101"; + when 22 => SH_CNT_MAX_BINARY := "00010110"; + when 23 => SH_CNT_MAX_BINARY := "00010111"; + when 24 => SH_CNT_MAX_BINARY := "00011000"; + when 25 => SH_CNT_MAX_BINARY := "00011001"; + when 26 => SH_CNT_MAX_BINARY := "00011010"; + when 27 => SH_CNT_MAX_BINARY := "00011011"; + when 28 => SH_CNT_MAX_BINARY := "00011100"; + when 29 => SH_CNT_MAX_BINARY := "00011101"; + when 30 => SH_CNT_MAX_BINARY := "00011110"; + when 31 => SH_CNT_MAX_BINARY := "00011111"; + when 32 => SH_CNT_MAX_BINARY := "00100000"; + when 33 => SH_CNT_MAX_BINARY := "00100001"; + when 34 => SH_CNT_MAX_BINARY := "00100010"; + when 35 => SH_CNT_MAX_BINARY := "00100011"; + when 36 => SH_CNT_MAX_BINARY := "00100100"; + when 37 => SH_CNT_MAX_BINARY := "00100101"; + when 38 => SH_CNT_MAX_BINARY := "00100110"; + when 39 => SH_CNT_MAX_BINARY := "00100111"; + when 40 => SH_CNT_MAX_BINARY := "00101000"; + when 41 => SH_CNT_MAX_BINARY := "00101001"; + when 42 => SH_CNT_MAX_BINARY := "00101010"; + when 43 => SH_CNT_MAX_BINARY := "00101011"; + when 44 => SH_CNT_MAX_BINARY := "00101100"; + when 45 => SH_CNT_MAX_BINARY := "00101101"; + when 46 => SH_CNT_MAX_BINARY := "00101110"; + when 47 => SH_CNT_MAX_BINARY := "00101111"; + when 48 => SH_CNT_MAX_BINARY := "00110000"; + when 49 => SH_CNT_MAX_BINARY := "00110001"; + when 50 => SH_CNT_MAX_BINARY := "00110010"; + when 51 => SH_CNT_MAX_BINARY := "00110011"; + when 52 => SH_CNT_MAX_BINARY := "00110100"; + when 53 => SH_CNT_MAX_BINARY := "00110101"; + when 54 => SH_CNT_MAX_BINARY := "00110110"; + when 55 => SH_CNT_MAX_BINARY := "00110111"; + when 56 => SH_CNT_MAX_BINARY := "00111000"; + when 57 => SH_CNT_MAX_BINARY := "00111001"; + when 58 => SH_CNT_MAX_BINARY := "00111010"; + when 59 => SH_CNT_MAX_BINARY := "00111011"; + when 60 => SH_CNT_MAX_BINARY := "00111100"; + when 61 => SH_CNT_MAX_BINARY := "00111101"; + when 62 => SH_CNT_MAX_BINARY := "00111110"; + when 63 => SH_CNT_MAX_BINARY := "00111111"; + when 64 => SH_CNT_MAX_BINARY := "01000000"; + when 65 => SH_CNT_MAX_BINARY := "01000001"; + when 66 => SH_CNT_MAX_BINARY := "01000010"; + when 67 => SH_CNT_MAX_BINARY := "01000011"; + when 68 => SH_CNT_MAX_BINARY := "01000100"; + when 69 => SH_CNT_MAX_BINARY := "01000101"; + when 70 => SH_CNT_MAX_BINARY := "01000110"; + when 71 => SH_CNT_MAX_BINARY := "01000111"; + when 72 => SH_CNT_MAX_BINARY := "01001000"; + when 73 => SH_CNT_MAX_BINARY := "01001001"; + when 74 => SH_CNT_MAX_BINARY := "01001010"; + when 75 => SH_CNT_MAX_BINARY := "01001011"; + when 76 => SH_CNT_MAX_BINARY := "01001100"; + when 77 => SH_CNT_MAX_BINARY := "01001101"; + when 78 => SH_CNT_MAX_BINARY := "01001110"; + when 79 => SH_CNT_MAX_BINARY := "01001111"; + when 80 => SH_CNT_MAX_BINARY := "01010000"; + when 81 => SH_CNT_MAX_BINARY := "01010001"; + when 82 => SH_CNT_MAX_BINARY := "01010010"; + when 83 => SH_CNT_MAX_BINARY := "01010011"; + when 84 => SH_CNT_MAX_BINARY := "01010100"; + when 85 => SH_CNT_MAX_BINARY := "01010101"; + when 86 => SH_CNT_MAX_BINARY := "01010110"; + when 87 => SH_CNT_MAX_BINARY := "01010111"; + when 88 => SH_CNT_MAX_BINARY := "01011000"; + when 89 => SH_CNT_MAX_BINARY := "01011001"; + when 90 => SH_CNT_MAX_BINARY := "01011010"; + when 91 => SH_CNT_MAX_BINARY := "01011011"; + when 92 => SH_CNT_MAX_BINARY := "01011100"; + when 93 => SH_CNT_MAX_BINARY := "01011101"; + when 94 => SH_CNT_MAX_BINARY := "01011110"; + when 95 => SH_CNT_MAX_BINARY := "01011111"; + when 96 => SH_CNT_MAX_BINARY := "01100000"; + when 97 => SH_CNT_MAX_BINARY := "01100001"; + when 98 => SH_CNT_MAX_BINARY := "01100010"; + when 99 => SH_CNT_MAX_BINARY := "01100011"; + when 100 => SH_CNT_MAX_BINARY := "01100100"; + when 101 => SH_CNT_MAX_BINARY := "01100101"; + when 102 => SH_CNT_MAX_BINARY := "01100110"; + when 103 => SH_CNT_MAX_BINARY := "01100111"; + when 104 => SH_CNT_MAX_BINARY := "01101000"; + when 105 => SH_CNT_MAX_BINARY := "01101001"; + when 106 => SH_CNT_MAX_BINARY := "01101010"; + when 107 => SH_CNT_MAX_BINARY := "01101011"; + when 108 => SH_CNT_MAX_BINARY := "01101100"; + when 109 => SH_CNT_MAX_BINARY := "01101101"; + when 110 => SH_CNT_MAX_BINARY := "01101110"; + when 111 => SH_CNT_MAX_BINARY := "01101111"; + when 112 => SH_CNT_MAX_BINARY := "01110000"; + when 113 => SH_CNT_MAX_BINARY := "01110001"; + when 114 => SH_CNT_MAX_BINARY := "01110010"; + when 115 => SH_CNT_MAX_BINARY := "01110011"; + when 116 => SH_CNT_MAX_BINARY := "01110100"; + when 117 => SH_CNT_MAX_BINARY := "01110101"; + when 118 => SH_CNT_MAX_BINARY := "01110110"; + when 119 => SH_CNT_MAX_BINARY := "01110111"; + when 120 => SH_CNT_MAX_BINARY := "01111000"; + when 121 => SH_CNT_MAX_BINARY := "01111001"; + when 122 => SH_CNT_MAX_BINARY := "01111010"; + when 123 => SH_CNT_MAX_BINARY := "01111011"; + when 124 => SH_CNT_MAX_BINARY := "01111100"; + when 125 => SH_CNT_MAX_BINARY := "01111101"; + when 126 => SH_CNT_MAX_BINARY := "01111110"; + when 127 => SH_CNT_MAX_BINARY := "01111111"; + when 128 => SH_CNT_MAX_BINARY := "10000000"; + when 129 => SH_CNT_MAX_BINARY := "10000001"; + when 130 => SH_CNT_MAX_BINARY := "10000010"; + when 131 => SH_CNT_MAX_BINARY := "10000011"; + when 132 => SH_CNT_MAX_BINARY := "10000100"; + when 133 => SH_CNT_MAX_BINARY := "10000101"; + when 134 => SH_CNT_MAX_BINARY := "10000110"; + when 135 => SH_CNT_MAX_BINARY := "10000111"; + when 136 => SH_CNT_MAX_BINARY := "10001000"; + when 137 => SH_CNT_MAX_BINARY := "10001001"; + when 138 => SH_CNT_MAX_BINARY := "10001010"; + when 139 => SH_CNT_MAX_BINARY := "10001011"; + when 140 => SH_CNT_MAX_BINARY := "10001100"; + when 141 => SH_CNT_MAX_BINARY := "10001101"; + when 142 => SH_CNT_MAX_BINARY := "10001110"; + when 143 => SH_CNT_MAX_BINARY := "10001111"; + when 144 => SH_CNT_MAX_BINARY := "10010000"; + when 145 => SH_CNT_MAX_BINARY := "10010001"; + when 146 => SH_CNT_MAX_BINARY := "10010010"; + when 147 => SH_CNT_MAX_BINARY := "10010011"; + when 148 => SH_CNT_MAX_BINARY := "10010100"; + when 149 => SH_CNT_MAX_BINARY := "10010101"; + when 150 => SH_CNT_MAX_BINARY := "10010110"; + when 151 => SH_CNT_MAX_BINARY := "10010111"; + when 152 => SH_CNT_MAX_BINARY := "10011000"; + when 153 => SH_CNT_MAX_BINARY := "10011001"; + when 154 => SH_CNT_MAX_BINARY := "10011010"; + when 155 => SH_CNT_MAX_BINARY := "10011011"; + when 156 => SH_CNT_MAX_BINARY := "10011100"; + when 157 => SH_CNT_MAX_BINARY := "10011101"; + when 158 => SH_CNT_MAX_BINARY := "10011110"; + when 159 => SH_CNT_MAX_BINARY := "10011111"; + when 160 => SH_CNT_MAX_BINARY := "10100000"; + when 161 => SH_CNT_MAX_BINARY := "10100001"; + when 162 => SH_CNT_MAX_BINARY := "10100010"; + when 163 => SH_CNT_MAX_BINARY := "10100011"; + when 164 => SH_CNT_MAX_BINARY := "10100100"; + when 165 => SH_CNT_MAX_BINARY := "10100101"; + when 166 => SH_CNT_MAX_BINARY := "10100110"; + when 167 => SH_CNT_MAX_BINARY := "10100111"; + when 168 => SH_CNT_MAX_BINARY := "10101000"; + when 169 => SH_CNT_MAX_BINARY := "10101001"; + when 170 => SH_CNT_MAX_BINARY := "10101010"; + when 171 => SH_CNT_MAX_BINARY := "10101011"; + when 172 => SH_CNT_MAX_BINARY := "10101100"; + when 173 => SH_CNT_MAX_BINARY := "10101101"; + when 174 => SH_CNT_MAX_BINARY := "10101110"; + when 175 => SH_CNT_MAX_BINARY := "10101111"; + when 176 => SH_CNT_MAX_BINARY := "10110000"; + when 177 => SH_CNT_MAX_BINARY := "10110001"; + when 178 => SH_CNT_MAX_BINARY := "10110010"; + when 179 => SH_CNT_MAX_BINARY := "10110011"; + when 180 => SH_CNT_MAX_BINARY := "10110100"; + when 181 => SH_CNT_MAX_BINARY := "10110101"; + when 182 => SH_CNT_MAX_BINARY := "10110110"; + when 183 => SH_CNT_MAX_BINARY := "10110111"; + when 184 => SH_CNT_MAX_BINARY := "10111000"; + when 185 => SH_CNT_MAX_BINARY := "10111001"; + when 186 => SH_CNT_MAX_BINARY := "10111010"; + when 187 => SH_CNT_MAX_BINARY := "10111011"; + when 188 => SH_CNT_MAX_BINARY := "10111100"; + when 189 => SH_CNT_MAX_BINARY := "10111101"; + when 190 => SH_CNT_MAX_BINARY := "10111110"; + when 191 => SH_CNT_MAX_BINARY := "10111111"; + when 192 => SH_CNT_MAX_BINARY := "11000000"; + when 193 => SH_CNT_MAX_BINARY := "11000001"; + when 194 => SH_CNT_MAX_BINARY := "11000010"; + when 195 => SH_CNT_MAX_BINARY := "11000011"; + when 196 => SH_CNT_MAX_BINARY := "11000100"; + when 197 => SH_CNT_MAX_BINARY := "11000101"; + when 198 => SH_CNT_MAX_BINARY := "11000110"; + when 199 => SH_CNT_MAX_BINARY := "11000111"; + when 200 => SH_CNT_MAX_BINARY := "11001000"; + when 201 => SH_CNT_MAX_BINARY := "11001001"; + when 202 => SH_CNT_MAX_BINARY := "11001010"; + when 203 => SH_CNT_MAX_BINARY := "11001011"; + when 204 => SH_CNT_MAX_BINARY := "11001100"; + when 205 => SH_CNT_MAX_BINARY := "11001101"; + when 206 => SH_CNT_MAX_BINARY := "11001110"; + when 207 => SH_CNT_MAX_BINARY := "11001111"; + when 208 => SH_CNT_MAX_BINARY := "11010000"; + when 209 => SH_CNT_MAX_BINARY := "11010001"; + when 210 => SH_CNT_MAX_BINARY := "11010010"; + when 211 => SH_CNT_MAX_BINARY := "11010011"; + when 212 => SH_CNT_MAX_BINARY := "11010100"; + when 213 => SH_CNT_MAX_BINARY := "11010101"; + when 214 => SH_CNT_MAX_BINARY := "11010110"; + when 215 => SH_CNT_MAX_BINARY := "11010111"; + when 216 => SH_CNT_MAX_BINARY := "11011000"; + when 217 => SH_CNT_MAX_BINARY := "11011001"; + when 218 => SH_CNT_MAX_BINARY := "11011010"; + when 219 => SH_CNT_MAX_BINARY := "11011011"; + when 220 => SH_CNT_MAX_BINARY := "11011100"; + when 221 => SH_CNT_MAX_BINARY := "11011101"; + when 222 => SH_CNT_MAX_BINARY := "11011110"; + when 223 => SH_CNT_MAX_BINARY := "11011111"; + when 224 => SH_CNT_MAX_BINARY := "11100000"; + when 225 => SH_CNT_MAX_BINARY := "11100001"; + when 226 => SH_CNT_MAX_BINARY := "11100010"; + when 227 => SH_CNT_MAX_BINARY := "11100011"; + when 228 => SH_CNT_MAX_BINARY := "11100100"; + when 229 => SH_CNT_MAX_BINARY := "11100101"; + when 230 => SH_CNT_MAX_BINARY := "11100110"; + when 231 => SH_CNT_MAX_BINARY := "11100111"; + when 232 => SH_CNT_MAX_BINARY := "11101000"; + when 233 => SH_CNT_MAX_BINARY := "11101001"; + when 234 => SH_CNT_MAX_BINARY := "11101010"; + when 235 => SH_CNT_MAX_BINARY := "11101011"; + when 236 => SH_CNT_MAX_BINARY := "11101100"; + when 237 => SH_CNT_MAX_BINARY := "11101101"; + when 238 => SH_CNT_MAX_BINARY := "11101110"; + when 239 => SH_CNT_MAX_BINARY := "11101111"; + when 240 => SH_CNT_MAX_BINARY := "11110000"; + when 241 => SH_CNT_MAX_BINARY := "11110001"; + when 242 => SH_CNT_MAX_BINARY := "11110010"; + when 243 => SH_CNT_MAX_BINARY := "11110011"; + when 244 => SH_CNT_MAX_BINARY := "11110100"; + when 245 => SH_CNT_MAX_BINARY := "11110101"; + when 246 => SH_CNT_MAX_BINARY := "11110110"; + when 247 => SH_CNT_MAX_BINARY := "11110111"; + when 248 => SH_CNT_MAX_BINARY := "11111000"; + when 249 => SH_CNT_MAX_BINARY := "11111001"; + when 250 => SH_CNT_MAX_BINARY := "11111010"; + when 251 => SH_CNT_MAX_BINARY := "11111011"; + when 252 => SH_CNT_MAX_BINARY := "11111100"; + when 253 => SH_CNT_MAX_BINARY := "11111101"; + when 254 => SH_CNT_MAX_BINARY := "11111110"; + when 255 => SH_CNT_MAX_BINARY := "11111111"; + when others => assert FALSE report "Error : SH_CNT_MAX is not in range 0...255." severity error; + end case; + case SH_INVALID_CNT_MAX is + when 0 => SH_INVALID_CNT_MAX_BINARY := "00000000"; + when 1 => SH_INVALID_CNT_MAX_BINARY := "00000001"; + when 2 => SH_INVALID_CNT_MAX_BINARY := "00000010"; + when 3 => SH_INVALID_CNT_MAX_BINARY := "00000011"; + when 4 => SH_INVALID_CNT_MAX_BINARY := "00000100"; + when 5 => SH_INVALID_CNT_MAX_BINARY := "00000101"; + when 6 => SH_INVALID_CNT_MAX_BINARY := "00000110"; + when 7 => SH_INVALID_CNT_MAX_BINARY := "00000111"; + when 8 => SH_INVALID_CNT_MAX_BINARY := "00001000"; + when 9 => SH_INVALID_CNT_MAX_BINARY := "00001001"; + when 10 => SH_INVALID_CNT_MAX_BINARY := "00001010"; + when 11 => SH_INVALID_CNT_MAX_BINARY := "00001011"; + when 12 => SH_INVALID_CNT_MAX_BINARY := "00001100"; + when 13 => SH_INVALID_CNT_MAX_BINARY := "00001101"; + when 14 => SH_INVALID_CNT_MAX_BINARY := "00001110"; + when 15 => SH_INVALID_CNT_MAX_BINARY := "00001111"; + when 16 => SH_INVALID_CNT_MAX_BINARY := "00010000"; + when 17 => SH_INVALID_CNT_MAX_BINARY := "00010001"; + when 18 => SH_INVALID_CNT_MAX_BINARY := "00010010"; + when 19 => SH_INVALID_CNT_MAX_BINARY := "00010011"; + when 20 => SH_INVALID_CNT_MAX_BINARY := "00010100"; + when 21 => SH_INVALID_CNT_MAX_BINARY := "00010101"; + when 22 => SH_INVALID_CNT_MAX_BINARY := "00010110"; + when 23 => SH_INVALID_CNT_MAX_BINARY := "00010111"; + when 24 => SH_INVALID_CNT_MAX_BINARY := "00011000"; + when 25 => SH_INVALID_CNT_MAX_BINARY := "00011001"; + when 26 => SH_INVALID_CNT_MAX_BINARY := "00011010"; + when 27 => SH_INVALID_CNT_MAX_BINARY := "00011011"; + when 28 => SH_INVALID_CNT_MAX_BINARY := "00011100"; + when 29 => SH_INVALID_CNT_MAX_BINARY := "00011101"; + when 30 => SH_INVALID_CNT_MAX_BINARY := "00011110"; + when 31 => SH_INVALID_CNT_MAX_BINARY := "00011111"; + when 32 => SH_INVALID_CNT_MAX_BINARY := "00100000"; + when 33 => SH_INVALID_CNT_MAX_BINARY := "00100001"; + when 34 => SH_INVALID_CNT_MAX_BINARY := "00100010"; + when 35 => SH_INVALID_CNT_MAX_BINARY := "00100011"; + when 36 => SH_INVALID_CNT_MAX_BINARY := "00100100"; + when 37 => SH_INVALID_CNT_MAX_BINARY := "00100101"; + when 38 => SH_INVALID_CNT_MAX_BINARY := "00100110"; + when 39 => SH_INVALID_CNT_MAX_BINARY := "00100111"; + when 40 => SH_INVALID_CNT_MAX_BINARY := "00101000"; + when 41 => SH_INVALID_CNT_MAX_BINARY := "00101001"; + when 42 => SH_INVALID_CNT_MAX_BINARY := "00101010"; + when 43 => SH_INVALID_CNT_MAX_BINARY := "00101011"; + when 44 => SH_INVALID_CNT_MAX_BINARY := "00101100"; + when 45 => SH_INVALID_CNT_MAX_BINARY := "00101101"; + when 46 => SH_INVALID_CNT_MAX_BINARY := "00101110"; + when 47 => SH_INVALID_CNT_MAX_BINARY := "00101111"; + when 48 => SH_INVALID_CNT_MAX_BINARY := "00110000"; + when 49 => SH_INVALID_CNT_MAX_BINARY := "00110001"; + when 50 => SH_INVALID_CNT_MAX_BINARY := "00110010"; + when 51 => SH_INVALID_CNT_MAX_BINARY := "00110011"; + when 52 => SH_INVALID_CNT_MAX_BINARY := "00110100"; + when 53 => SH_INVALID_CNT_MAX_BINARY := "00110101"; + when 54 => SH_INVALID_CNT_MAX_BINARY := "00110110"; + when 55 => SH_INVALID_CNT_MAX_BINARY := "00110111"; + when 56 => SH_INVALID_CNT_MAX_BINARY := "00111000"; + when 57 => SH_INVALID_CNT_MAX_BINARY := "00111001"; + when 58 => SH_INVALID_CNT_MAX_BINARY := "00111010"; + when 59 => SH_INVALID_CNT_MAX_BINARY := "00111011"; + when 60 => SH_INVALID_CNT_MAX_BINARY := "00111100"; + when 61 => SH_INVALID_CNT_MAX_BINARY := "00111101"; + when 62 => SH_INVALID_CNT_MAX_BINARY := "00111110"; + when 63 => SH_INVALID_CNT_MAX_BINARY := "00111111"; + when 64 => SH_INVALID_CNT_MAX_BINARY := "01000000"; + when 65 => SH_INVALID_CNT_MAX_BINARY := "01000001"; + when 66 => SH_INVALID_CNT_MAX_BINARY := "01000010"; + when 67 => SH_INVALID_CNT_MAX_BINARY := "01000011"; + when 68 => SH_INVALID_CNT_MAX_BINARY := "01000100"; + when 69 => SH_INVALID_CNT_MAX_BINARY := "01000101"; + when 70 => SH_INVALID_CNT_MAX_BINARY := "01000110"; + when 71 => SH_INVALID_CNT_MAX_BINARY := "01000111"; + when 72 => SH_INVALID_CNT_MAX_BINARY := "01001000"; + when 73 => SH_INVALID_CNT_MAX_BINARY := "01001001"; + when 74 => SH_INVALID_CNT_MAX_BINARY := "01001010"; + when 75 => SH_INVALID_CNT_MAX_BINARY := "01001011"; + when 76 => SH_INVALID_CNT_MAX_BINARY := "01001100"; + when 77 => SH_INVALID_CNT_MAX_BINARY := "01001101"; + when 78 => SH_INVALID_CNT_MAX_BINARY := "01001110"; + when 79 => SH_INVALID_CNT_MAX_BINARY := "01001111"; + when 80 => SH_INVALID_CNT_MAX_BINARY := "01010000"; + when 81 => SH_INVALID_CNT_MAX_BINARY := "01010001"; + when 82 => SH_INVALID_CNT_MAX_BINARY := "01010010"; + when 83 => SH_INVALID_CNT_MAX_BINARY := "01010011"; + when 84 => SH_INVALID_CNT_MAX_BINARY := "01010100"; + when 85 => SH_INVALID_CNT_MAX_BINARY := "01010101"; + when 86 => SH_INVALID_CNT_MAX_BINARY := "01010110"; + when 87 => SH_INVALID_CNT_MAX_BINARY := "01010111"; + when 88 => SH_INVALID_CNT_MAX_BINARY := "01011000"; + when 89 => SH_INVALID_CNT_MAX_BINARY := "01011001"; + when 90 => SH_INVALID_CNT_MAX_BINARY := "01011010"; + when 91 => SH_INVALID_CNT_MAX_BINARY := "01011011"; + when 92 => SH_INVALID_CNT_MAX_BINARY := "01011100"; + when 93 => SH_INVALID_CNT_MAX_BINARY := "01011101"; + when 94 => SH_INVALID_CNT_MAX_BINARY := "01011110"; + when 95 => SH_INVALID_CNT_MAX_BINARY := "01011111"; + when 96 => SH_INVALID_CNT_MAX_BINARY := "01100000"; + when 97 => SH_INVALID_CNT_MAX_BINARY := "01100001"; + when 98 => SH_INVALID_CNT_MAX_BINARY := "01100010"; + when 99 => SH_INVALID_CNT_MAX_BINARY := "01100011"; + when 100 => SH_INVALID_CNT_MAX_BINARY := "01100100"; + when 101 => SH_INVALID_CNT_MAX_BINARY := "01100101"; + when 102 => SH_INVALID_CNT_MAX_BINARY := "01100110"; + when 103 => SH_INVALID_CNT_MAX_BINARY := "01100111"; + when 104 => SH_INVALID_CNT_MAX_BINARY := "01101000"; + when 105 => SH_INVALID_CNT_MAX_BINARY := "01101001"; + when 106 => SH_INVALID_CNT_MAX_BINARY := "01101010"; + when 107 => SH_INVALID_CNT_MAX_BINARY := "01101011"; + when 108 => SH_INVALID_CNT_MAX_BINARY := "01101100"; + when 109 => SH_INVALID_CNT_MAX_BINARY := "01101101"; + when 110 => SH_INVALID_CNT_MAX_BINARY := "01101110"; + when 111 => SH_INVALID_CNT_MAX_BINARY := "01101111"; + when 112 => SH_INVALID_CNT_MAX_BINARY := "01110000"; + when 113 => SH_INVALID_CNT_MAX_BINARY := "01110001"; + when 114 => SH_INVALID_CNT_MAX_BINARY := "01110010"; + when 115 => SH_INVALID_CNT_MAX_BINARY := "01110011"; + when 116 => SH_INVALID_CNT_MAX_BINARY := "01110100"; + when 117 => SH_INVALID_CNT_MAX_BINARY := "01110101"; + when 118 => SH_INVALID_CNT_MAX_BINARY := "01110110"; + when 119 => SH_INVALID_CNT_MAX_BINARY := "01110111"; + when 120 => SH_INVALID_CNT_MAX_BINARY := "01111000"; + when 121 => SH_INVALID_CNT_MAX_BINARY := "01111001"; + when 122 => SH_INVALID_CNT_MAX_BINARY := "01111010"; + when 123 => SH_INVALID_CNT_MAX_BINARY := "01111011"; + when 124 => SH_INVALID_CNT_MAX_BINARY := "01111100"; + when 125 => SH_INVALID_CNT_MAX_BINARY := "01111101"; + when 126 => SH_INVALID_CNT_MAX_BINARY := "01111110"; + when 127 => SH_INVALID_CNT_MAX_BINARY := "01111111"; + when 128 => SH_INVALID_CNT_MAX_BINARY := "10000000"; + when 129 => SH_INVALID_CNT_MAX_BINARY := "10000001"; + when 130 => SH_INVALID_CNT_MAX_BINARY := "10000010"; + when 131 => SH_INVALID_CNT_MAX_BINARY := "10000011"; + when 132 => SH_INVALID_CNT_MAX_BINARY := "10000100"; + when 133 => SH_INVALID_CNT_MAX_BINARY := "10000101"; + when 134 => SH_INVALID_CNT_MAX_BINARY := "10000110"; + when 135 => SH_INVALID_CNT_MAX_BINARY := "10000111"; + when 136 => SH_INVALID_CNT_MAX_BINARY := "10001000"; + when 137 => SH_INVALID_CNT_MAX_BINARY := "10001001"; + when 138 => SH_INVALID_CNT_MAX_BINARY := "10001010"; + when 139 => SH_INVALID_CNT_MAX_BINARY := "10001011"; + when 140 => SH_INVALID_CNT_MAX_BINARY := "10001100"; + when 141 => SH_INVALID_CNT_MAX_BINARY := "10001101"; + when 142 => SH_INVALID_CNT_MAX_BINARY := "10001110"; + when 143 => SH_INVALID_CNT_MAX_BINARY := "10001111"; + when 144 => SH_INVALID_CNT_MAX_BINARY := "10010000"; + when 145 => SH_INVALID_CNT_MAX_BINARY := "10010001"; + when 146 => SH_INVALID_CNT_MAX_BINARY := "10010010"; + when 147 => SH_INVALID_CNT_MAX_BINARY := "10010011"; + when 148 => SH_INVALID_CNT_MAX_BINARY := "10010100"; + when 149 => SH_INVALID_CNT_MAX_BINARY := "10010101"; + when 150 => SH_INVALID_CNT_MAX_BINARY := "10010110"; + when 151 => SH_INVALID_CNT_MAX_BINARY := "10010111"; + when 152 => SH_INVALID_CNT_MAX_BINARY := "10011000"; + when 153 => SH_INVALID_CNT_MAX_BINARY := "10011001"; + when 154 => SH_INVALID_CNT_MAX_BINARY := "10011010"; + when 155 => SH_INVALID_CNT_MAX_BINARY := "10011011"; + when 156 => SH_INVALID_CNT_MAX_BINARY := "10011100"; + when 157 => SH_INVALID_CNT_MAX_BINARY := "10011101"; + when 158 => SH_INVALID_CNT_MAX_BINARY := "10011110"; + when 159 => SH_INVALID_CNT_MAX_BINARY := "10011111"; + when 160 => SH_INVALID_CNT_MAX_BINARY := "10100000"; + when 161 => SH_INVALID_CNT_MAX_BINARY := "10100001"; + when 162 => SH_INVALID_CNT_MAX_BINARY := "10100010"; + when 163 => SH_INVALID_CNT_MAX_BINARY := "10100011"; + when 164 => SH_INVALID_CNT_MAX_BINARY := "10100100"; + when 165 => SH_INVALID_CNT_MAX_BINARY := "10100101"; + when 166 => SH_INVALID_CNT_MAX_BINARY := "10100110"; + when 167 => SH_INVALID_CNT_MAX_BINARY := "10100111"; + when 168 => SH_INVALID_CNT_MAX_BINARY := "10101000"; + when 169 => SH_INVALID_CNT_MAX_BINARY := "10101001"; + when 170 => SH_INVALID_CNT_MAX_BINARY := "10101010"; + when 171 => SH_INVALID_CNT_MAX_BINARY := "10101011"; + when 172 => SH_INVALID_CNT_MAX_BINARY := "10101100"; + when 173 => SH_INVALID_CNT_MAX_BINARY := "10101101"; + when 174 => SH_INVALID_CNT_MAX_BINARY := "10101110"; + when 175 => SH_INVALID_CNT_MAX_BINARY := "10101111"; + when 176 => SH_INVALID_CNT_MAX_BINARY := "10110000"; + when 177 => SH_INVALID_CNT_MAX_BINARY := "10110001"; + when 178 => SH_INVALID_CNT_MAX_BINARY := "10110010"; + when 179 => SH_INVALID_CNT_MAX_BINARY := "10110011"; + when 180 => SH_INVALID_CNT_MAX_BINARY := "10110100"; + when 181 => SH_INVALID_CNT_MAX_BINARY := "10110101"; + when 182 => SH_INVALID_CNT_MAX_BINARY := "10110110"; + when 183 => SH_INVALID_CNT_MAX_BINARY := "10110111"; + when 184 => SH_INVALID_CNT_MAX_BINARY := "10111000"; + when 185 => SH_INVALID_CNT_MAX_BINARY := "10111001"; + when 186 => SH_INVALID_CNT_MAX_BINARY := "10111010"; + when 187 => SH_INVALID_CNT_MAX_BINARY := "10111011"; + when 188 => SH_INVALID_CNT_MAX_BINARY := "10111100"; + when 189 => SH_INVALID_CNT_MAX_BINARY := "10111101"; + when 190 => SH_INVALID_CNT_MAX_BINARY := "10111110"; + when 191 => SH_INVALID_CNT_MAX_BINARY := "10111111"; + when 192 => SH_INVALID_CNT_MAX_BINARY := "11000000"; + when 193 => SH_INVALID_CNT_MAX_BINARY := "11000001"; + when 194 => SH_INVALID_CNT_MAX_BINARY := "11000010"; + when 195 => SH_INVALID_CNT_MAX_BINARY := "11000011"; + when 196 => SH_INVALID_CNT_MAX_BINARY := "11000100"; + when 197 => SH_INVALID_CNT_MAX_BINARY := "11000101"; + when 198 => SH_INVALID_CNT_MAX_BINARY := "11000110"; + when 199 => SH_INVALID_CNT_MAX_BINARY := "11000111"; + when 200 => SH_INVALID_CNT_MAX_BINARY := "11001000"; + when 201 => SH_INVALID_CNT_MAX_BINARY := "11001001"; + when 202 => SH_INVALID_CNT_MAX_BINARY := "11001010"; + when 203 => SH_INVALID_CNT_MAX_BINARY := "11001011"; + when 204 => SH_INVALID_CNT_MAX_BINARY := "11001100"; + when 205 => SH_INVALID_CNT_MAX_BINARY := "11001101"; + when 206 => SH_INVALID_CNT_MAX_BINARY := "11001110"; + when 207 => SH_INVALID_CNT_MAX_BINARY := "11001111"; + when 208 => SH_INVALID_CNT_MAX_BINARY := "11010000"; + when 209 => SH_INVALID_CNT_MAX_BINARY := "11010001"; + when 210 => SH_INVALID_CNT_MAX_BINARY := "11010010"; + when 211 => SH_INVALID_CNT_MAX_BINARY := "11010011"; + when 212 => SH_INVALID_CNT_MAX_BINARY := "11010100"; + when 213 => SH_INVALID_CNT_MAX_BINARY := "11010101"; + when 214 => SH_INVALID_CNT_MAX_BINARY := "11010110"; + when 215 => SH_INVALID_CNT_MAX_BINARY := "11010111"; + when 216 => SH_INVALID_CNT_MAX_BINARY := "11011000"; + when 217 => SH_INVALID_CNT_MAX_BINARY := "11011001"; + when 218 => SH_INVALID_CNT_MAX_BINARY := "11011010"; + when 219 => SH_INVALID_CNT_MAX_BINARY := "11011011"; + when 220 => SH_INVALID_CNT_MAX_BINARY := "11011100"; + when 221 => SH_INVALID_CNT_MAX_BINARY := "11011101"; + when 222 => SH_INVALID_CNT_MAX_BINARY := "11011110"; + when 223 => SH_INVALID_CNT_MAX_BINARY := "11011111"; + when 224 => SH_INVALID_CNT_MAX_BINARY := "11100000"; + when 225 => SH_INVALID_CNT_MAX_BINARY := "11100001"; + when 226 => SH_INVALID_CNT_MAX_BINARY := "11100010"; + when 227 => SH_INVALID_CNT_MAX_BINARY := "11100011"; + when 228 => SH_INVALID_CNT_MAX_BINARY := "11100100"; + when 229 => SH_INVALID_CNT_MAX_BINARY := "11100101"; + when 230 => SH_INVALID_CNT_MAX_BINARY := "11100110"; + when 231 => SH_INVALID_CNT_MAX_BINARY := "11100111"; + when 232 => SH_INVALID_CNT_MAX_BINARY := "11101000"; + when 233 => SH_INVALID_CNT_MAX_BINARY := "11101001"; + when 234 => SH_INVALID_CNT_MAX_BINARY := "11101010"; + when 235 => SH_INVALID_CNT_MAX_BINARY := "11101011"; + when 236 => SH_INVALID_CNT_MAX_BINARY := "11101100"; + when 237 => SH_INVALID_CNT_MAX_BINARY := "11101101"; + when 238 => SH_INVALID_CNT_MAX_BINARY := "11101110"; + when 239 => SH_INVALID_CNT_MAX_BINARY := "11101111"; + when 240 => SH_INVALID_CNT_MAX_BINARY := "11110000"; + when 241 => SH_INVALID_CNT_MAX_BINARY := "11110001"; + when 242 => SH_INVALID_CNT_MAX_BINARY := "11110010"; + when 243 => SH_INVALID_CNT_MAX_BINARY := "11110011"; + when 244 => SH_INVALID_CNT_MAX_BINARY := "11110100"; + when 245 => SH_INVALID_CNT_MAX_BINARY := "11110101"; + when 246 => SH_INVALID_CNT_MAX_BINARY := "11110110"; + when 247 => SH_INVALID_CNT_MAX_BINARY := "11110111"; + when 248 => SH_INVALID_CNT_MAX_BINARY := "11111000"; + when 249 => SH_INVALID_CNT_MAX_BINARY := "11111001"; + when 250 => SH_INVALID_CNT_MAX_BINARY := "11111010"; + when 251 => SH_INVALID_CNT_MAX_BINARY := "11111011"; + when 252 => SH_INVALID_CNT_MAX_BINARY := "11111100"; + when 253 => SH_INVALID_CNT_MAX_BINARY := "11111101"; + when 254 => SH_INVALID_CNT_MAX_BINARY := "11111110"; + when 255 => SH_INVALID_CNT_MAX_BINARY := "11111111"; + when others => assert FALSE report "Error : SH_INVALID_CNT_MAX is not in range 0...255." severity error; + end case; + case ALIGN_COMMA_WORD is + when 1 => ALIGN_COMMA_WORD_BINARY := "00"; + when 2 => ALIGN_COMMA_WORD_BINARY := "01"; + when 4 => ALIGN_COMMA_WORD_BINARY := "10"; + when others => assert FALSE report "Error : ALIGN_COMMA_WORD is not in 1, 2, 4." severity error; + end case; + case DEC_MCOMMA_DETECT is + when FALSE => DEC_MCOMMA_DETECT_BINARY := '0'; + when TRUE => DEC_MCOMMA_DETECT_BINARY := '1'; + when others => assert FALSE report "Error : DEC_MCOMMA_DETECT is neither TRUE nor FALSE." severity error; + end case; + case DEC_PCOMMA_DETECT is + when FALSE => DEC_PCOMMA_DETECT_BINARY := '0'; + when TRUE => DEC_PCOMMA_DETECT_BINARY := '1'; + when others => assert FALSE report "Error : DEC_PCOMMA_DETECT is neither TRUE nor FALSE." severity error; + end case; + case DEC_VALID_COMMA_ONLY is + when FALSE => DEC_VALID_COMMA_ONLY_BINARY := '0'; + when TRUE => DEC_VALID_COMMA_ONLY_BINARY := '1'; + when others => assert FALSE report "Error : DEC_VALID_COMMA_ONLY is neither TRUE nor FALSE." severity error; + end case; + case MCOMMA_DETECT is + when FALSE => MCOMMA_DETECT_BINARY := '0'; + when TRUE => MCOMMA_DETECT_BINARY := '1'; + when others => assert FALSE report "Error : MCOMMA_DETECT is neither TRUE nor FALSE." severity error; + end case; + case PCOMMA_DETECT is + when FALSE => PCOMMA_DETECT_BINARY := '0'; + when TRUE => PCOMMA_DETECT_BINARY := '1'; + when others => assert FALSE report "Error : PCOMMA_DETECT is neither TRUE nor FALSE." severity error; + end case; + case COMMA32 is + when FALSE => COMMA32_BINARY := '0'; + when TRUE => COMMA32_BINARY := '1'; + when others => assert FALSE report "Error : COMMA32 is neither TRUE nor FALSE." severity error; + end case; + case RXUSRDIVISOR is + when 1 => RXUSRDIVISOR_BINARY := "00001"; + when 2 => RXUSRDIVISOR_BINARY := "00010"; + when 4 => RXUSRDIVISOR_BINARY := "00100"; + when 8 => RXUSRDIVISOR_BINARY := "01000"; + when 16 => RXUSRDIVISOR_BINARY := "10000"; + when others => assert FALSE report "Error : RXUSRDIVISOR is not in 1, 2, 4, 8, 16." severity error; + end case; + case SAMPLE_8X is + when FALSE => SAMPLE_8X_BINARY := '0'; + when TRUE => SAMPLE_8X_BINARY := '1'; + when others => assert FALSE report "Error : SAMPLE_8X is neither TRUE nor FALSE." severity error; + end case; + case ENABLE_DCDR is + when FALSE => ENABLE_DCDR_BINARY := '0'; + when TRUE => ENABLE_DCDR_BINARY := '1'; + when others => assert FALSE report "Error : ENABLE_DCDR is neither TRUE nor FALSE." severity error; + end case; + case REPEATER is + when FALSE => REPEATER_BINARY := '0'; + when TRUE => REPEATER_BINARY := '1'; + when others => assert FALSE report "Error : REPEATER is neither TRUE nor FALSE." severity error; + end case; + case RXBY_32 is + when FALSE => RXBY_32_BINARY := '0'; + when TRUE => RXBY_32_BINARY := '1'; + when others => assert FALSE report "Error : RXBY_32 is neither TRUE nor FALSE." severity error; + end case; +-- case TXFDCAL_CLOCK_DIVIDE is + if((TXFDCAL_CLOCK_DIVIDE = "NONE") or (TXFDCAL_CLOCK_DIVIDE = "none")) then + TXFDCAL_CLOCK_DIVIDE_BINARY := "00"; + elsif((TXFDCAL_CLOCK_DIVIDE = "TWO") or (TXFDCAL_CLOCK_DIVIDE = "two")) then + TXFDCAL_CLOCK_DIVIDE_BINARY := "01"; + elsif((TXFDCAL_CLOCK_DIVIDE = "FOUR") or (TXFDCAL_CLOCK_DIVIDE = "four")) then + TXFDCAL_CLOCK_DIVIDE_BINARY := "10"; + else + assert FALSE report "Error : TXFDCAL_CLOCK_DIVIDE = is not NONE, TWO, FOUR." severity error; + end if; +-- end case; +-- case RXFDCAL_CLOCK_DIVIDE is + if((RXFDCAL_CLOCK_DIVIDE = "NONE") or (RXFDCAL_CLOCK_DIVIDE = "none")) then + RXFDCAL_CLOCK_DIVIDE_BINARY := "00"; + elsif((RXFDCAL_CLOCK_DIVIDE = "TWO") or (RXFDCAL_CLOCK_DIVIDE = "two")) then + RXFDCAL_CLOCK_DIVIDE_BINARY := "01"; + elsif((RXFDCAL_CLOCK_DIVIDE = "FOUR") or (RXFDCAL_CLOCK_DIVIDE = "four")) then + RXFDCAL_CLOCK_DIVIDE_BINARY := "10"; + else + assert FALSE report "Error : RXFDCAL_CLOCK_DIVIDE = is not NONE, TWO, FOUR." severity error; + end if; +-- end case; + case RXVCO_CTRL_ENABLE is + when FALSE => RXVCO_CTRL_ENABLE_BINARY := '0'; + when TRUE => RXVCO_CTRL_ENABLE_BINARY := '1'; + when others => assert FALSE report "Error : RXVCO_CTRL_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case VCO_CTRL_ENABLE is + when FALSE => VCO_CTRL_ENABLE_BINARY := '0'; + when TRUE => VCO_CTRL_ENABLE_BINARY := '1'; + when others => assert FALSE report "Error : VCO_CTRL_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case RXCRCCLOCKDOUBLE is + when FALSE => RXCRCCLOCKDOUBLE_BINARY := '0'; + when TRUE => RXCRCCLOCKDOUBLE_BINARY := '1'; + when others => assert FALSE report "Error : RXCRCCLOCKDOUBLE is neither TRUE nor FALSE." severity error; + end case; + case RXCRCINVERTGEN is + when FALSE => RXCRCINVERTGEN_BINARY := '0'; + when TRUE => RXCRCINVERTGEN_BINARY := '1'; + when others => assert FALSE report "Error : RXCRCINVERTGEN is neither TRUE nor FALSE." severity error; + end case; + case RXCRCSAMECLOCK is + when FALSE => RXCRCSAMECLOCK_BINARY := '0'; + when TRUE => RXCRCSAMECLOCK_BINARY := '1'; + when others => assert FALSE report "Error : RXCRCSAMECLOCK is neither TRUE nor FALSE." severity error; + end case; + case RXCRCENABLE is + when FALSE => RXCRCENABLE_BINARY := '0'; + when TRUE => RXCRCENABLE_BINARY := '1'; + when others => assert FALSE report "Error : RXCRCENABLE is neither TRUE nor FALSE." severity error; + end case; + case TXCRCCLOCKDOUBLE is + when FALSE => TXCRCCLOCKDOUBLE_BINARY := '0'; + when TRUE => TXCRCCLOCKDOUBLE_BINARY := '1'; + when others => assert FALSE report "Error : TXCRCCLOCKDOUBLE is neither TRUE nor FALSE." severity error; + end case; + case TXCRCINVERTGEN is + when FALSE => TXCRCINVERTGEN_BINARY := '0'; + when TRUE => TXCRCINVERTGEN_BINARY := '1'; + when others => assert FALSE report "Error : TXCRCINVERTGEN is neither TRUE nor FALSE." severity error; + end case; + case TXCRCSAMECLOCK is + when FALSE => TXCRCSAMECLOCK_BINARY := '0'; + when TRUE => TXCRCSAMECLOCK_BINARY := '1'; + when others => assert FALSE report "Error : TXCRCSAMECLOCK is neither TRUE nor FALSE." severity error; + end case; + case TXCRCENABLE is + when FALSE => TXCRCENABLE_BINARY := '0'; + when TRUE => TXCRCENABLE_BINARY := '1'; + when others => assert FALSE report "Error : TXCRCENABLE is neither TRUE nor FALSE." severity error; + end case; + case RXCLK0_FORCE_PMACLK is + when FALSE => RXCLK0_FORCE_PMACLK_BINARY := '0'; + when TRUE => RXCLK0_FORCE_PMACLK_BINARY := '1'; + when others => assert FALSE report "Error : RXCLK0_FORCE_PMACLK is neither TRUE nor FALSE." severity error; + end case; + case TXCLK0_FORCE_PMACLK is + when FALSE => TXCLK0_FORCE_PMACLK_BINARY := '0'; + when TRUE => TXCLK0_FORCE_PMACLK_BINARY := '1'; + when others => assert FALSE report "Error : TXCLK0_FORCE_PMACLK is neither TRUE nor FALSE." severity error; + end case; + case TXOUTCLK1_USE_SYNC is + when FALSE => TXOUTCLK1_USE_SYNC_BINARY := '0'; + when TRUE => TXOUTCLK1_USE_SYNC_BINARY := '1'; + when others => assert FALSE report "Error : TXOUTCLK1_USE_SYNC is neither TRUE nor FALSE." severity error; + end case; + case RXRECCLK1_USE_SYNC is + when FALSE => RXRECCLK1_USE_SYNC_BINARY := '0'; + when TRUE => RXRECCLK1_USE_SYNC_BINARY := '1'; + when others => assert FALSE report "Error : RXRECCLK1_USE_SYNC is neither TRUE nor FALSE." severity error; + end case; +-- case RXPMACLKSEL is + if((RXPMACLKSEL = "REFCLK1") or (RXPMACLKSEL = "refclk1")) then + RXPMACLKSEL_BINARY := "00"; + elsif((RXPMACLKSEL = "REFCLK2") or (RXPMACLKSEL = "refclk2")) then + RXPMACLKSEL_BINARY := "01"; + elsif((RXPMACLKSEL = "GREFCLK") or (RXPMACLKSEL = "grefclk")) then + RXPMACLKSEL_BINARY := "10"; + else + assert FALSE report "Error : RXPMACLKSEL = is not REFCLK1, REFCLK2, GREFCLK." severity error; + end if; +-- end case; +-- case TXABPMACLKSEL is + if((TXABPMACLKSEL = "REFCLK1") or (TXABPMACLKSEL = "refclk1")) then + TXABPMACLKSEL_BINARY := "00"; + elsif((TXABPMACLKSEL = "REFCLK2") or (TXABPMACLKSEL = "refclk2")) then + TXABPMACLKSEL_BINARY := "01"; + elsif((TXABPMACLKSEL = "GREFCLK") or (TXABPMACLKSEL = "grefclk")) then + TXABPMACLKSEL_BINARY := "10"; + else + assert FALSE report "Error : TXABPMACLKSEL = is not REFCLK1, REFCLK2, GREFCLK." severity error; + end if; +-- end case; + case BANDGAPSEL is + when FALSE => BANDGAPSEL_BINARY := '0'; + when TRUE => BANDGAPSEL_BINARY := '1'; + when others => assert FALSE report "Error : BANDGAPSEL is neither TRUE nor FALSE." severity error; + end case; + case BIASRESSEL is + when FALSE => BIASRESSEL_BINARY := '0'; + when TRUE => BIASRESSEL_BINARY := '1'; + when others => assert FALSE report "Error : BIASRESSEL is neither TRUE nor FALSE." severity error; + end case; + case TXPHASESEL is + when FALSE => TXPHASESEL_BINARY := '0'; + when TRUE => TXPHASESEL_BINARY := '1'; + when others => assert FALSE report "Error : TXPHASESEL is neither TRUE nor FALSE." severity error; + end case; + case PMACLKENABLE is + when FALSE => PMACLKENABLE_BINARY := '0'; + when TRUE => PMACLKENABLE_BINARY := '1'; + when others => assert FALSE report "Error : PMACLKENABLE is neither TRUE nor FALSE." severity error; + end case; + case PMACOREPWRENABLE is + when FALSE => PMACOREPWRENABLE_BINARY := '0'; + when TRUE => PMACOREPWRENABLE_BINARY := '1'; + when others => assert FALSE report "Error : PMACOREPWRENABLE is neither TRUE nor FALSE." severity error; + end case; + case PMA_BIT_SLIP is + when FALSE => PMA_BIT_SLIP_BINARY := '0'; + when TRUE => PMA_BIT_SLIP_BINARY := '1'; + when others => assert FALSE report "Error : PMA_BIT_SLIP is neither TRUE nor FALSE." severity error; + end case; + case RXLB is + when FALSE => RXLB_BINARY := '0'; + when TRUE => RXLB_BINARY := '1'; + when others => assert FALSE report "Error : RXLB is neither TRUE nor FALSE." severity error; + end case; + case RXDCCOUPLE is + when FALSE => RXDCCOUPLE_BINARY := '0'; + when TRUE => RXDCCOUPLE_BINARY := '1'; + when others => assert FALSE report "Error : RXDCCOUPLE is neither TRUE nor FALSE." severity error; + end case; + case RXDIGRESET is + when FALSE => RXDIGRESET_BINARY := '0'; + when TRUE => RXDIGRESET_BINARY := '1'; + when others => assert FALSE report "Error : RXDIGRESET is neither TRUE nor FALSE." severity error; + end case; + case RXCPTST is + when FALSE => RXCPTST_BINARY := '0'; + when TRUE => RXCPTST_BINARY := '1'; + when others => assert FALSE report "Error : RXCPTST is neither TRUE nor FALSE." severity error; + end case; + case RXPDDTST is + when FALSE => RXPDDTST_BINARY := '0'; + when TRUE => RXPDDTST_BINARY := '1'; + when others => assert FALSE report "Error : RXPDDTST is neither TRUE nor FALSE." severity error; + end case; + case RXACTST is + when FALSE => RXACTST_BINARY := '0'; + when TRUE => RXACTST_BINARY := '1'; + when others => assert FALSE report "Error : RXACTST is neither TRUE nor FALSE." severity error; + end case; + case RXAFETST is + when FALSE => RXAFETST_BINARY := '0'; + when TRUE => RXAFETST_BINARY := '1'; + when others => assert FALSE report "Error : RXAFETST is neither TRUE nor FALSE." severity error; + end case; + case RXLKAPD is + when FALSE => RXLKAPD_BINARY := '0'; + when TRUE => RXLKAPD_BINARY := '1'; + when others => assert FALSE report "Error : RXLKAPD is neither TRUE nor FALSE." severity error; + end case; + case RXRSDPD is + when FALSE => RXRSDPD_BINARY := '0'; + when TRUE => RXRSDPD_BINARY := '1'; + when others => assert FALSE report "Error : RXRSDPD is neither TRUE nor FALSE." severity error; + end case; + case RXRCPPD is + when FALSE => RXRCPPD_BINARY := '0'; + when TRUE => RXRCPPD_BINARY := '1'; + when others => assert FALSE report "Error : RXRCPPD is neither TRUE nor FALSE." severity error; + end case; + case RXRPDPD is + when FALSE => RXRPDPD_BINARY := '0'; + when TRUE => RXRPDPD_BINARY := '1'; + when others => assert FALSE report "Error : RXRPDPD is neither TRUE nor FALSE." severity error; + end case; + case RXAFEPD is + when FALSE => RXAFEPD_BINARY := '0'; + when TRUE => RXAFEPD_BINARY := '1'; + when others => assert FALSE report "Error : RXAFEPD is neither TRUE nor FALSE." severity error; + end case; + case RXPD is + when FALSE => RXPD_BINARY := '0'; + when TRUE => RXPD_BINARY := '1'; + when others => assert FALSE report "Error : RXPD is neither TRUE nor FALSE." severity error; + end case; + case TXOUTDIV2SEL is + when 1 => TXOUTDIV2SEL_BINARY := "0001"; + when 2 => TXOUTDIV2SEL_BINARY := "0010"; + when 4 => TXOUTDIV2SEL_BINARY := "0011"; + when 8 => TXOUTDIV2SEL_BINARY := "0100"; + when 16 => TXOUTDIV2SEL_BINARY := "0101"; + when 32 => TXOUTDIV2SEL_BINARY := "0110"; + when others => assert FALSE report "Error : TXOUTDIV2SEL is not in 1, 2, 4, 8, 16, 32." severity error; + end case; + case TXPLLNDIVSEL is + when 8 => TXPLLNDIVSEL_BINARY := "0000"; + when 10 => TXPLLNDIVSEL_BINARY := "0010"; + when 16 => TXPLLNDIVSEL_BINARY := "0100"; + when 20 => TXPLLNDIVSEL_BINARY := "0110"; + when 32 => TXPLLNDIVSEL_BINARY := "1000"; + when 40 => TXPLLNDIVSEL_BINARY := "1010"; + when others => assert FALSE report "Error : TXPLLNDIVSEL is not in 8, 10, 16, 20, 32, 40." severity error; + end case; + case TXCPSEL is + when FALSE => TXCPSEL_BINARY := '0'; + when TRUE => TXCPSEL_BINARY := '1'; + when others => assert FALSE report "Error : TXCPSEL is neither TRUE nor FALSE." severity error; + end case; + case TXAPD is + when FALSE => TXAPD_BINARY := '0'; + when TRUE => TXAPD_BINARY := '1'; + when others => assert FALSE report "Error : TXAPD is neither TRUE nor FALSE." severity error; + end case; + case TXLVLSHFTPD is + when FALSE => TXLVLSHFTPD_BINARY := '0'; + when TRUE => TXLVLSHFTPD_BINARY := '1'; + when others => assert FALSE report "Error : TXLVLSHFTPD is neither TRUE nor FALSE." severity error; + end case; + case TXPRE_TAP_PD is + when FALSE => TXPRE_TAP_PD_BINARY := '0'; + when TRUE => TXPRE_TAP_PD_BINARY := '1'; + when others => assert FALSE report "Error : TXPRE_TAP_PD is neither TRUE nor FALSE." severity error; + end case; + case TXDIGPD is + when FALSE => TXDIGPD_BINARY := '0'; + when TRUE => TXDIGPD_BINARY := '1'; + when others => assert FALSE report "Error : TXDIGPD is neither TRUE nor FALSE." severity error; + end case; + case TXHIGHSIGNALEN is + when FALSE => TXHIGHSIGNALEN_BINARY := '0'; + when TRUE => TXHIGHSIGNALEN_BINARY := '1'; + when others => assert FALSE report "Error : TXHIGHSIGNALEN is neither TRUE nor FALSE." severity error; + end case; + case TXAREFBIASSEL is + when FALSE => TXAREFBIASSEL_BINARY := '0'; + when TRUE => TXAREFBIASSEL_BINARY := '1'; + when others => assert FALSE report "Error : TXAREFBIASSEL is neither TRUE nor FALSE." severity error; + end case; + case TXSLEWRATE is + when FALSE => TXSLEWRATE_BINARY := '0'; + when TRUE => TXSLEWRATE_BINARY := '1'; + when others => assert FALSE report "Error : TXSLEWRATE is neither TRUE nor FALSE." severity error; + end case; + case TXPOST_TAP_PD is + when FALSE => TXPOST_TAP_PD_BINARY := '0'; + when TRUE => TXPOST_TAP_PD_BINARY := '1'; + when others => assert FALSE report "Error : TXPOST_TAP_PD is neither TRUE nor FALSE." severity error; + end case; + case TXPD is + when FALSE => TXPD_BINARY := '0'; + when TRUE => TXPD_BINARY := '1'; + when others => assert FALSE report "Error : TXPD is neither TRUE nor FALSE." severity error; + end case; + case RXOUTDIV2SEL is + when 1 => RXOUTDIV2SEL_BINARY := "00010001"; + when 2 => RXOUTDIV2SEL_BINARY := "00100010"; + when 4 => RXOUTDIV2SEL_BINARY := "00110011"; + when 8 => RXOUTDIV2SEL_BINARY := "01000100"; + when 16 => RXOUTDIV2SEL_BINARY := "01010101"; + when 32 => RXOUTDIV2SEL_BINARY := "01100110"; + when others => assert FALSE report "Error : RXOUTDIV2SEL is not in 1, 2, 4, 8, 16, 32." severity error; + end case; + case RXPLLNDIVSEL is + when 8 => RXPLLNDIVSEL_BINARY := "0000"; + when 10 => RXPLLNDIVSEL_BINARY := "0010"; + when 16 => RXPLLNDIVSEL_BINARY := "0100"; + when 20 => RXPLLNDIVSEL_BINARY := "0110"; + when 32 => RXPLLNDIVSEL_BINARY := "1000"; + when 40 => RXPLLNDIVSEL_BINARY := "1010"; + when others => assert FALSE report "Error : RXPLLNDIVSEL is not in 8, 10, 16, 20, 32, 40." severity error; + end case; + case RXDIGRX is + when FALSE => RXDIGRX_BINARY := '0'; + when TRUE => RXDIGRX_BINARY := '1'; + when others => assert FALSE report "Error : RXDIGRX is neither TRUE nor FALSE." severity error; + end case; + case RXCPSEL is + when FALSE => RXCPSEL_BINARY := '0'; + when TRUE => RXCPSEL_BINARY := '1'; + when others => assert FALSE report "Error : RXCPSEL is neither TRUE nor FALSE." severity error; + end case; + case RXAPD is + when FALSE => RXAPD_BINARY := '0'; + when TRUE => RXAPD_BINARY := '1'; + when others => assert FALSE report "Error : RXAPD is neither TRUE nor FALSE." severity error; + end case; + +synDigCfgChnBnd1(63) <= '0';--RESERVED_CB1; +synDigCfgChnBnd1(62) <= TX_BUFFER_USE_BINARY; +synDigCfgChnBnd1(61) <= RX_BUFFER_USE_BINARY; +synDigCfgChnBnd1(60 downto 58) <= CHAN_BOND_SEQ_LEN_BINARY; +synDigCfgChnBnd1(57) <= CHAN_BOND_SEQ_2_USE_BINARY; +synDigCfgChnBnd1(56) <= CHAN_BOND_ONE_SHOT_BINARY; +synDigCfgChnBnd1(55 downto 54) <= CHAN_BOND_MODE_BINARY; +synDigCfgChnBnd1(53 downto 48) <= CHAN_BOND_LIMIT_BINARY; +synDigCfgChnBnd1(47 downto 44) <= CHAN_BOND_SEQ_1_MASK_BINARY; +synDigCfgChnBnd1(43 downto 33) <= CHAN_BOND_SEQ_1_4_BINARY; +synDigCfgChnBnd1(32 downto 22) <= CHAN_BOND_SEQ_1_3_BINARY; +synDigCfgChnBnd1(21 downto 11) <= CHAN_BOND_SEQ_1_2_BINARY; +synDigCfgChnBnd1(10 downto 0) <= CHAN_BOND_SEQ_1_1_BINARY; + + + +synDigCfgChnBnd2(63 downto 56) <= "00000000";-- CHAN_BOND_TUNE; +synDigCfgChnBnd2(55) <= '0'; -- unused +synDigCfgChnBnd2(54) <= '0'; -- unused +synDigCfgChnBnd2(53) <= CCCB_ARBITRATOR_DISABLE_BINARY; +synDigCfgChnBnd2(52) <= OPPOSITE_SELECT_BINARY; +synDigCfgChnBnd2(51) <= POWER_ENABLE_BINARY; +synDigCfgChnBnd2(50 downto 48) <= "000"; +synDigCfgChnBnd2(47 downto 44) <= CHAN_BOND_SEQ_2_MASK_BINARY; +synDigCfgChnBnd2(43 downto 33) <= CHAN_BOND_SEQ_2_4_BINARY; +synDigCfgChnBnd2(32 downto 22) <= CHAN_BOND_SEQ_2_3_BINARY; +synDigCfgChnBnd2(21 downto 11) <= CHAN_BOND_SEQ_2_2_BINARY; +synDigCfgChnBnd2(10 downto 0) <= CHAN_BOND_SEQ_2_1_BINARY; + + + +synDigCfgClkCor1(63 downto 62) <= RXDATA_SEL_BINARY; +synDigCfgClkCor1(61 downto 60) <= TXDATA_SEL_BINARY; +synDigCfgClkCor1(59) <= '0';--RESERVED_CCB; +synDigCfgClkCor1(58 downto 53) <= CLK_COR_MIN_LAT_BINARY; +synDigCfgClkCor1(52) <= '0';--RESERVED_CCA; +synDigCfgClkCor1(51) <= PCS_BIT_SLIP_BINARY; +synDigCfgClkCor1(50) <= DIGRX_SYNC_MODE_BINARY; +synDigCfgClkCor1(49 downto 48) <= DIGRX_FWDCLK_BINARY; +synDigCfgClkCor1(47 downto 44) <= CLK_COR_SEQ_1_MASK_BINARY; +synDigCfgClkCor1(43 downto 33) <= CLK_COR_SEQ_1_4_BINARY; +synDigCfgClkCor1(32 downto 22) <= CLK_COR_SEQ_1_3_BINARY; +synDigCfgClkCor1(21 downto 11) <= CLK_COR_SEQ_1_2_BINARY; +synDigCfgClkCor1(10 downto 0) <= CLK_COR_SEQ_1_1_BINARY; + + + +synDigCfgClkCor2(63 downto 56) <= "00000000"; --RX_LOS_THRESHOLD_BINARY; +synDigCfgClkCor2(55 downto 48) <= "00000000"; --RX_LOS_INVALID_INCR_BINARY; +synDigCfgClkCor2(47 downto 44) <= CLK_COR_SEQ_2_MASK_BINARY; +synDigCfgClkCor2(43 downto 33) <= CLK_COR_SEQ_2_4_BINARY; +synDigCfgClkCor2(32 downto 22) <= CLK_COR_SEQ_2_3_BINARY; +synDigCfgClkCor2(21 downto 11) <= CLK_COR_SEQ_2_2_BINARY; +synDigCfgClkCor2(10 downto 0) <= CLK_COR_SEQ_2_1_BINARY; + + + +synDigCfgMisc(63) <= RXRECCLK1_USE_SYNC_BINARY; +synDigCfgMisc(62) <= TXOUTCLK1_USE_SYNC_BINARY; +synDigCfgMisc(61) <= TXCLK0_FORCE_PMACLK_BINARY; +synDigCfgMisc(60) <= RXCLK0_FORCE_PMACLK_BINARY; +synDigCfgMisc(59 downto 58) <= TX_CLOCK_DIVIDER_BINARY; +synDigCfgMisc(57 downto 56) <= RX_CLOCK_DIVIDER_BINARY; +synDigCfgMisc(55) <= TXCRCENABLE_BINARY; +synDigCfgMisc(54) <= TXCRCSAMECLOCK_BINARY; +synDigCfgMisc(53) <= TXCRCINVERTGEN_BINARY; +synDigCfgMisc(52) <= TXCRCCLOCKDOUBLE_BINARY; +synDigCfgMisc(51) <= RXCRCENABLE_BINARY; +synDigCfgMisc(50) <= RXCRCSAMECLOCK_BINARY; +synDigCfgMisc(49) <= RXCRCINVERTGEN_BINARY; +synDigCfgMisc(48) <= RXCRCCLOCKDOUBLE_BINARY; +synDigCfgMisc(47 downto 46) <= RXFDCAL_CLOCK_DIVIDE_BINARY; +synDigCfgMisc(45 downto 44) <= TXFDCAL_CLOCK_DIVIDE_BINARY; +synDigCfgMisc(43) <= RXBY_32_BINARY; +synDigCfgMisc(42) <= REPEATER_BINARY; +synDigCfgMisc(41) <= ENABLE_DCDR_BINARY; +synDigCfgMisc(40) <= SAMPLE_8X_BINARY; +synDigCfgMisc(39 downto 37) <= DCDR_FILTER_BINARY; +synDigCfgMisc(36 downto 32) <= RXUSRDIVISOR_BINARY; +synDigCfgMisc(31 downto 24) <= SH_INVALID_CNT_MAX_BINARY; +synDigCfgMisc(23 downto 16) <= SH_CNT_MAX_BINARY; +synDigCfgMisc(15) <= '0';--RESERVED_M2; +synDigCfgMisc(14) <= CLK_COR_8B10B_DE_BINARY; +synDigCfgMisc(13) <= CLK_CORRECT_USE_BINARY; +synDigCfgMisc(12 downto 10) <= CLK_COR_SEQ_LEN_BINARY; +synDigCfgMisc(9) <= CLK_COR_SEQ_DROP_BINARY; +synDigCfgMisc(8) <= CLK_COR_SEQ_2_USE_BINARY; +synDigCfgMisc(7) <= '0';--TXCLK0_INVERT_PMALEAF; +synDigCfgMisc(6) <= '0';--RXCLK0_INVERT_PMALEAF; +synDigCfgMisc(5 downto 0) <= CLK_COR_MAX_LAT_BINARY; + + + +synDigCfgComma1(63 downto 42) <= "0000000000000000000000";--COMMA_32B_MASK; +synDigCfgComma1(41 downto 32) <= COMMA_10B_MASK_BINARY; +synDigCfgComma1(31 downto 8) <= "000000000000000000000000";--RESERVED_CM; +synDigCfgComma1(7) <= COMMA32_BINARY; +synDigCfgComma1(6) <= PCOMMA_DETECT_BINARY; +synDigCfgComma1(5) <= MCOMMA_DETECT_BINARY; +synDigCfgComma1(4) <= DEC_VALID_COMMA_ONLY_BINARY; +synDigCfgComma1(3) <= DEC_PCOMMA_DETECT_BINARY; +synDigCfgComma1(2) <= DEC_MCOMMA_DETECT_BINARY; +synDigCfgComma1(1 downto 0) <= ALIGN_COMMA_WORD_BINARY; + + + +synDigCfgComma2(63 downto 32) <= PCOMMA_32B_VALUE_BINARY; +synDigCfgComma2(31 downto 0) <= MCOMMA_32B_VALUE_BINARY; + + + +synDigCfgSynPmaFD(63) <= '1';-- AUTO_CAL; +synDigCfgSynPmaFD(62 downto 53) <= VCODAC_INIT_BINARY; +synDigCfgSynPmaFD(52 downto 51) <= "00";--SLOWDOWN_CAL; +synDigCfgSynPmaFD(50) <= '0';-- BYPASS_FDET; +synDigCfgSynPmaFD(49 downto 48) <= LOOPCAL_WAIT_BINARY; +synDigCfgSynPmaFD(47) <= '0';-- BYPASS_CAL; +synDigCfgSynPmaFD(46 downto 44) <= FDET_HYS_CAL_BINARY; +synDigCfgSynPmaFD(43 downto 41) <= FDET_LCK_CAL_BINARY; +synDigCfgSynPmaFD(40 downto 38) <= FDET_HYS_SEL_BINARY; +synDigCfgSynPmaFD(37 downto 35) <= FDET_LCK_SEL_BINARY; +synDigCfgSynPmaFD(34) <= VCO_CTRL_ENABLE_BINARY; +synDigCfgSynPmaFD(33 downto 32) <= CYCLE_LIMIT_SEL_BINARY; +synDigCfgSynPmaFD(31) <= '1';-- RXAUTO_CAL; +synDigCfgSynPmaFD(30 downto 21) <= RXVCODAC_INIT_BINARY; +synDigCfgSynPmaFD(20 downto 19) <= RXSLOWDOWN_CAL_BINARY; +synDigCfgSynPmaFD(18) <= '0';-- RXBYPASS_FDET; +synDigCfgSynPmaFD(17 downto 16) <= RXLOOPCAL_WAIT_BINARY; +synDigCfgSynPmaFD(15) <= '0';-- RXBYPASS_CAL; +synDigCfgSynPmaFD(14 downto 12) <= RXFDET_HYS_CAL_BINARY; +synDigCfgSynPmaFD(11 downto 9) <= RXFDET_LCK_CAL_BINARY; +synDigCfgSynPmaFD(8 downto 6) <= RXFDET_HYS_SEL_BINARY; +synDigCfgSynPmaFD(5 downto 3) <= RXFDET_LCK_SEL_BINARY; +synDigCfgSynPmaFD(2) <= RXVCO_CTRL_ENABLE_BINARY; +synDigCfgSynPmaFD(1 downto 0) <= RXCYCLE_LIMIT_SEL_BINARY; + + + +synDigCfgCrc(63 downto 32) <= TXCRCINITVAL_BINARY; +synDigCfgCrc(31 downto 0) <= RXCRCINITVAL_BINARY; + + + +PMACFG(63 downto 62) <= "00"; +PMACFG(61 downto 60) <= RXPMACLKSEL_BINARY; +PMACFG(59 downto 58) <= RXPMACLKSEL_BINARY; +PMACFG(57 downto 56) <= TXABPMACLKSEL_BINARY; +PMACFG(55 downto 48) <= "00000000"; +PMACFG(47) <= '0';-- PMATUNE; +PMACFG(46 downto 42) <= "00000";-- TXREGCTRL; +PMACFG(41 downto 37) <= RXAREGCTRL_BINARY; +PMACFG(36 downto 32) <= PMAVBGCTRL_BINARY; +PMACFG(31) <= BANDGAPSEL_BINARY; +PMACFG(30 downto 27) <= PMAIREFTRIM_BINARY; +PMACFG(26 downto 25) <= IREFBIASMODE_BINARY; +PMACFG(24) <= BIASRESSEL_BINARY; +PMACFG(23 downto 20) <= PMAVREFTRIM_BINARY; +PMACFG(19) <= '0';--VREFSELECT; +PMACFG(18 downto 17) <= VREFBIASMODE_BINARY; +PMACFG(16) <= '0';-- PMABIASPD; +PMACFG(15 downto 14) <= "00"; +PMACFG(13) <= '0'; +PMACFG(12) <= '0';-- ATBBUMPEN; +PMACFG(11) <= '0';-- NATBENABLE; +PMACFG(10 downto 5) <= "000000"; +PMACFG(4) <= TXPHASESEL_BINARY; +PMACFG(3) <= '0'; --UNUSED +PMACFG(2) <= '0';-- PMACTRL; +PMACFG(1) <= PMACLKENABLE_BINARY;--'0';-- PMACLKENABLEPD; +PMACFG(0) <= PMACOREPWRENABLE_BINARY; + +PMACFG2(63 downto 18) <= "0000000000000000000000000000000000000000000000"; +PMACFG2(17 downto 0) <= "000000000000000000"; + +RXAFECFG(63 downto 58) <= RXMODE_BINARY; +RXAFECFG(57) <= PMA_BIT_SLIP_BINARY; +RXAFECFG(56 downto 55) <= RXASYNCDIVIDE_BINARY; +RXAFECFG(54 downto 49) <= RXCLKMODE_BINARY; +RXAFECFG(48) <= RXLB_BINARY; +RXAFECFG(47 downto 46) <= RXFETUNE_BINARY; +RXAFECFG(45 downto 43) <= RXRCPADJ_BINARY;--"00";-- RXRCPADJ; +RXAFECFG(42 downto 41) <= RXRIBADJ_BINARY; +RXAFECFG(40 downto 32) <= RXAFEEQ_BINARY; +RXAFECFG(31 downto 30) <= RXCMADJ_BINARY; +RXAFECFG(29 downto 24) <= RXCDRLOS_BINARY; +RXAFECFG(23) <= '0'; +RXAFECFG(22) <= RXDCCOUPLE_BINARY; +RXAFECFG(21) <= '0'; +RXAFECFG(20 downto 16) <= RXLKADJ_BINARY; +RXAFECFG(15) <= RXDIGRESET_BINARY; +RXAFECFG(14 downto 12) <= RXFECONTROL2_BINARY; +RXAFECFG(11) <= RXCPTST_BINARY; +RXAFECFG(10) <= RXPDDTST_BINARY; +RXAFECFG(9) <= RXACTST_BINARY; +RXAFECFG(8) <= RXAFETST_BINARY; +RXAFECFG(7 downto 6) <= RXFECONTROL1_BINARY; +RXAFECFG(5) <= RXLKAPD_BINARY; +RXAFECFG(4) <= RXRSDPD_BINARY; +RXAFECFG(3) <= RXRCPPD_BINARY; +RXAFECFG(2) <= RXRPDPD_BINARY; +RXAFECFG(1) <= RXAFEPD_BINARY; +RXAFECFG(0) <= RXPD_BINARY; + + + +RXAEQCFG(63 downto 0) <= RXEQ_BINARY; + + + +TXCLCFG(63 downto 60) <= TXOUTDIV2SEL_BINARY; +TXCLCFG(59 downto 56) <= TXPLLNDIVSEL_BINARY; +TXCLCFG(55 downto 54) <= TXCLMODE_BINARY; +TXCLCFG(53 downto 50) <= TXLOOPFILT_BINARY; +TXCLCFG(49) <= '0';-- UNUSED; +TXCLCFG(48) <= '0';-- UNUSED; +TXCLCFG(47 downto 35) <= TXTUNE_BINARY; +TXCLCFG(34) <= '0';-- UNUSED; +TXCLCFG(33) <= '0';-- --UNUSED; +TXCLCFG(32) <= TXCPSEL_BINARY; +TXCLCFG(31) <= '0'; --TXDACTST +TXCLCFG(30 downto 27) <= TXOUTDIV2SEL_BINARY; +TXCLCFG(26 downto 17) <= TXCTRL1_BINARY; +TXCLCFG(16) <= '0';-- TXQPPD; +TXCLCFG(15) <= '0';-- TXCMFPD; +TXCLCFG(14) <= '0';-- TXVCOPD; +TXCLCFG(13) <= '0';-- TXADCADJPD; +TXCLCFG(12) <= '0';-- TXDIVPD; +TXCLCFG(11) <= '0';-- TXBIASPD; +TXCLCFG(10) <= '0';-- TXDIVBUFPD; +TXCLCFG(9) <= '0';-- TXVCOBUFPD; +TXCLCFG(8) <= TXAPD_BINARY; +TXCLCFG(7) <= '0';-- TXAPTST; +TXCLCFG(6) <= '0';-- TXCMFTST; +TXCLCFG(5) <= '0';-- TXFILTTST; +TXCLCFG(4) <= '0';-- TXDIVTST; +TXCLCFG(3) <= '0';-- TXPFDTST; +TXCLCFG(2) <= '0';-- TXVCOBUFTST; +TXCLCFG(1) <= '0';-- TXDIVBUFTST; +TXCLCFG(0) <= '0';-- TXVCOTST; + + + +TXACFG(63 downto 60) <= "0000"; +TXACFG(59) <= TXLVLSHFTPD_BINARY; +TXACFG(58 downto 56) <= TXPRE_PRDRV_DAC_BINARY; +TXACFG(55) <= TXPRE_TAP_PD_BINARY; +TXACFG(54 downto 53) <= TXPRE_TAP_DAC_BINARY(4 downto 3); +TXACFG(52) <= TXDIGPD_BINARY; +TXACFG(51 downto 48) <= TXCLKMODE_BINARY; +TXACFG(47 downto 45) <= TXPRE_TAP_DAC_BINARY(2 downto 0); +TXACFG(44) <= '0'; +TXACFG(43) <= TXHIGHSIGNALEN_BINARY; +TXACFG(42) <= TXAREFBIASSEL_BINARY; +TXACFG(41 downto 38) <= TXTERMTRIM_BINARY; +TXACFG(37) <= TXASYNCDIVIDE_BINARY(1); +TXACFG(36) <= TXSLEWRATE_BINARY; +TXACFG(35 downto 33) <= TXPOST_PRDRV_DAC_BINARY; +TXACFG(32 downto 30) <= TXDAT_PRDRV_DAC_BINARY; +TXACFG(29) <= TXASYNCDIVIDE_BINARY(0); +TXACFG(28) <= TXPOST_TAP_PD_BINARY; +TXACFG(27 downto 23) <= TXPOST_TAP_DAC_BINARY; +TXACFG(22 downto 21) <= "00";-- TXTUNE1; +TXACFG(20 downto 16) <= TXDAT_TAP_DAC_BINARY; +TXACFG(15 downto 1) <= "000000000000000";-- TXDIG_TST; +TXACFG(0) <= TXPD_BINARY; + + + +RXACLCFG(63 downto 60) <= RXOUTDIV2SEL_BINARY(7 downto 4); +RXACLCFG(59 downto 56) <= RXPLLNDIVSEL_BINARY; +RXACLCFG(55 downto 54) <= RXCLMODE_BINARY; +RXACLCFG(53 downto 50) <= RXLOOPFILT_BINARY; +RXACLCFG(49) <= RXDIGRX_BINARY; +RXACLCFG(48) <= '0';-- RXPFDTX; +RXACLCFG(47 downto 35) <= RXTUNE_BINARY; +RXACLCFG(34) <= '0';-- RXSLOSEL; +RXACLCFG(33) <= '0';-- RXDACSEL; +RXACLCFG(32) <= RXCPSEL_BINARY; +RXACLCFG(31) <= '0';-- RXDACTST; +RXACLCFG(30 downto 27) <= RXOUTDIV2SEL_BINARY(3 downto 0); +RXACLCFG(26 downto 17) <= RXCTRL1_BINARY; +RXACLCFG(16) <= '0';-- RXQPPD; +RXACLCFG(15) <= '1';-- RXCMFPD; +RXACLCFG(14) <= '0';-- RXVCOPD; +RXACLCFG(13) <= '0';-- RXADCADJPD; +RXACLCFG(12) <= '0';-- RXDIVPD; +RXACLCFG(11) <= '0';-- RXBIASPD; +RXACLCFG(10) <= '0';-- RXVCOBUFPD; +RXACLCFG(9) <= '0';-- RXDIVBUFPD; +RXACLCFG(8) <= RXAPD_BINARY; +RXACLCFG(7) <= '0';-- RXAPTST; +RXACLCFG(6) <= '0';-- RXCMFTST; +RXACLCFG(5) <= '0';-- RXFILTTST; +RXACLCFG(4) <= '0';-- RXDIVTST; +RXACLCFG(3) <= '0';-- RXPFDTST; +RXACLCFG(2) <= '0';-- RXVCOBUFTST; +RXACLCFG(1) <= '0';-- RXDIVBUFTST; +RXACLCFG(0) <= '0';-- RXVCOTST + wait; + end process INIPROC; + + TIMING : process + +-- Pin timing violations (clock input pins) + +-- Pin Timing Violations (all input pins) + +-- Output Pin glitch declaration + variable CHBONDO0_GlitchData : VitalGlitchDataType; + variable CHBONDO1_GlitchData : VitalGlitchDataType; + variable CHBONDO2_GlitchData : VitalGlitchDataType; + variable CHBONDO3_GlitchData : VitalGlitchDataType; + variable CHBONDO4_GlitchData : VitalGlitchDataType; + variable RXSTATUS0_GlitchData : VitalGlitchDataType; + variable RXSTATUS1_GlitchData : VitalGlitchDataType; + variable RXSTATUS2_GlitchData : VitalGlitchDataType; + variable RXSTATUS3_GlitchData : VitalGlitchDataType; + variable RXSTATUS4_GlitchData : VitalGlitchDataType; + variable RXSTATUS5_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA0_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA1_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA2_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA3_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA4_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA5_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA6_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA7_GlitchData : VitalGlitchDataType; + variable RXCHARISK0_GlitchData : VitalGlitchDataType; + variable RXCHARISK1_GlitchData : VitalGlitchDataType; + variable RXCHARISK2_GlitchData : VitalGlitchDataType; + variable RXCHARISK3_GlitchData : VitalGlitchDataType; + variable RXCHARISK4_GlitchData : VitalGlitchDataType; + variable RXCHARISK5_GlitchData : VitalGlitchDataType; + variable RXCHARISK6_GlitchData : VitalGlitchDataType; + variable RXCHARISK7_GlitchData : VitalGlitchDataType; + variable RXCOMMADET_GlitchData : VitalGlitchDataType; + variable RXDATA0_GlitchData : VitalGlitchDataType; + variable RXDATA1_GlitchData : VitalGlitchDataType; + variable RXDATA2_GlitchData : VitalGlitchDataType; + variable RXDATA3_GlitchData : VitalGlitchDataType; + variable RXDATA4_GlitchData : VitalGlitchDataType; + variable RXDATA5_GlitchData : VitalGlitchDataType; + variable RXDATA6_GlitchData : VitalGlitchDataType; + variable RXDATA7_GlitchData : VitalGlitchDataType; + variable RXDATA8_GlitchData : VitalGlitchDataType; + variable RXDATA9_GlitchData : VitalGlitchDataType; + variable RXDATA10_GlitchData : VitalGlitchDataType; + variable RXDATA11_GlitchData : VitalGlitchDataType; + variable RXDATA12_GlitchData : VitalGlitchDataType; + variable RXDATA13_GlitchData : VitalGlitchDataType; + variable RXDATA14_GlitchData : VitalGlitchDataType; + variable RXDATA15_GlitchData : VitalGlitchDataType; + variable RXDATA16_GlitchData : VitalGlitchDataType; + variable RXDATA17_GlitchData : VitalGlitchDataType; + variable RXDATA18_GlitchData : VitalGlitchDataType; + variable RXDATA19_GlitchData : VitalGlitchDataType; + variable RXDATA20_GlitchData : VitalGlitchDataType; + variable RXDATA21_GlitchData : VitalGlitchDataType; + variable RXDATA22_GlitchData : VitalGlitchDataType; + variable RXDATA23_GlitchData : VitalGlitchDataType; + variable RXDATA24_GlitchData : VitalGlitchDataType; + variable RXDATA25_GlitchData : VitalGlitchDataType; + variable RXDATA26_GlitchData : VitalGlitchDataType; + variable RXDATA27_GlitchData : VitalGlitchDataType; + variable RXDATA28_GlitchData : VitalGlitchDataType; + variable RXDATA29_GlitchData : VitalGlitchDataType; + variable RXDATA30_GlitchData : VitalGlitchDataType; + variable RXDATA31_GlitchData : VitalGlitchDataType; + variable RXDATA32_GlitchData : VitalGlitchDataType; + variable RXDATA33_GlitchData : VitalGlitchDataType; + variable RXDATA34_GlitchData : VitalGlitchDataType; + variable RXDATA35_GlitchData : VitalGlitchDataType; + variable RXDATA36_GlitchData : VitalGlitchDataType; + variable RXDATA37_GlitchData : VitalGlitchDataType; + variable RXDATA38_GlitchData : VitalGlitchDataType; + variable RXDATA39_GlitchData : VitalGlitchDataType; + variable RXDATA40_GlitchData : VitalGlitchDataType; + variable RXDATA41_GlitchData : VitalGlitchDataType; + variable RXDATA42_GlitchData : VitalGlitchDataType; + variable RXDATA43_GlitchData : VitalGlitchDataType; + variable RXDATA44_GlitchData : VitalGlitchDataType; + variable RXDATA45_GlitchData : VitalGlitchDataType; + variable RXDATA46_GlitchData : VitalGlitchDataType; + variable RXDATA47_GlitchData : VitalGlitchDataType; + variable RXDATA48_GlitchData : VitalGlitchDataType; + variable RXDATA49_GlitchData : VitalGlitchDataType; + variable RXDATA50_GlitchData : VitalGlitchDataType; + variable RXDATA51_GlitchData : VitalGlitchDataType; + variable RXDATA52_GlitchData : VitalGlitchDataType; + variable RXDATA53_GlitchData : VitalGlitchDataType; + variable RXDATA54_GlitchData : VitalGlitchDataType; + variable RXDATA55_GlitchData : VitalGlitchDataType; + variable RXDATA56_GlitchData : VitalGlitchDataType; + variable RXDATA57_GlitchData : VitalGlitchDataType; + variable RXDATA58_GlitchData : VitalGlitchDataType; + variable RXDATA59_GlitchData : VitalGlitchDataType; + variable RXDATA60_GlitchData : VitalGlitchDataType; + variable RXDATA61_GlitchData : VitalGlitchDataType; + variable RXDATA62_GlitchData : VitalGlitchDataType; + variable RXDATA63_GlitchData : VitalGlitchDataType; + variable RXDISPERR0_GlitchData : VitalGlitchDataType; + variable RXDISPERR1_GlitchData : VitalGlitchDataType; + variable RXDISPERR2_GlitchData : VitalGlitchDataType; + variable RXDISPERR3_GlitchData : VitalGlitchDataType; + variable RXDISPERR4_GlitchData : VitalGlitchDataType; + variable RXDISPERR5_GlitchData : VitalGlitchDataType; + variable RXDISPERR6_GlitchData : VitalGlitchDataType; + variable RXDISPERR7_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC0_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC1_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE0_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE1_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE2_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE3_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE4_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE5_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE6_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE7_GlitchData : VitalGlitchDataType; + variable RXREALIGN_GlitchData : VitalGlitchDataType; + variable RXRUNDISP0_GlitchData : VitalGlitchDataType; + variable RXRUNDISP1_GlitchData : VitalGlitchDataType; + variable RXRUNDISP2_GlitchData : VitalGlitchDataType; + variable RXRUNDISP3_GlitchData : VitalGlitchDataType; + variable RXRUNDISP4_GlitchData : VitalGlitchDataType; + variable RXRUNDISP5_GlitchData : VitalGlitchDataType; + variable RXRUNDISP6_GlitchData : VitalGlitchDataType; + variable RXRUNDISP7_GlitchData : VitalGlitchDataType; + variable RXBUFERR_GlitchData : VitalGlitchDataType; + variable TXBUFERR_GlitchData : VitalGlitchDataType; + variable TXKERR0_GlitchData : VitalGlitchDataType; + variable TXKERR1_GlitchData : VitalGlitchDataType; + variable TXKERR2_GlitchData : VitalGlitchDataType; + variable TXKERR3_GlitchData : VitalGlitchDataType; + variable TXKERR4_GlitchData : VitalGlitchDataType; + variable TXKERR5_GlitchData : VitalGlitchDataType; + variable TXKERR6_GlitchData : VitalGlitchDataType; + variable TXKERR7_GlitchData : VitalGlitchDataType; + variable TXRUNDISP0_GlitchData : VitalGlitchDataType; + variable TXRUNDISP1_GlitchData : VitalGlitchDataType; + variable TXRUNDISP2_GlitchData : VitalGlitchDataType; + variable TXRUNDISP3_GlitchData : VitalGlitchDataType; + variable TXRUNDISP4_GlitchData : VitalGlitchDataType; + variable TXRUNDISP5_GlitchData : VitalGlitchDataType; + variable TXRUNDISP6_GlitchData : VitalGlitchDataType; + variable TXRUNDISP7_GlitchData : VitalGlitchDataType; + variable RXRECCLK1_GlitchData : VitalGlitchDataType; + variable RXRECCLK2_GlitchData : VitalGlitchDataType; + variable TXOUTCLK1_GlitchData : VitalGlitchDataType; + variable TXOUTCLK2_GlitchData : VitalGlitchDataType; + variable RXLOCK_GlitchData : VitalGlitchDataType; + variable TXLOCK_GlitchData : VitalGlitchDataType; + variable RXCYCLELIMIT_GlitchData : VitalGlitchDataType; + variable TXCYCLELIMIT_GlitchData : VitalGlitchDataType; + variable RXCALFAIL_GlitchData : VitalGlitchDataType; + variable TXCALFAIL_GlitchData : VitalGlitchDataType; + variable RXCRCOUT0_GlitchData : VitalGlitchDataType; + variable RXCRCOUT1_GlitchData : VitalGlitchDataType; + variable RXCRCOUT2_GlitchData : VitalGlitchDataType; + variable RXCRCOUT3_GlitchData : VitalGlitchDataType; + variable RXCRCOUT4_GlitchData : VitalGlitchDataType; + variable RXCRCOUT5_GlitchData : VitalGlitchDataType; + variable RXCRCOUT6_GlitchData : VitalGlitchDataType; + variable RXCRCOUT7_GlitchData : VitalGlitchDataType; + variable RXCRCOUT8_GlitchData : VitalGlitchDataType; + variable RXCRCOUT9_GlitchData : VitalGlitchDataType; + variable RXCRCOUT10_GlitchData : VitalGlitchDataType; + variable RXCRCOUT11_GlitchData : VitalGlitchDataType; + variable RXCRCOUT12_GlitchData : VitalGlitchDataType; + variable RXCRCOUT13_GlitchData : VitalGlitchDataType; + variable RXCRCOUT14_GlitchData : VitalGlitchDataType; + variable RXCRCOUT15_GlitchData : VitalGlitchDataType; + variable RXCRCOUT16_GlitchData : VitalGlitchDataType; + variable RXCRCOUT17_GlitchData : VitalGlitchDataType; + variable RXCRCOUT18_GlitchData : VitalGlitchDataType; + variable RXCRCOUT19_GlitchData : VitalGlitchDataType; + variable RXCRCOUT20_GlitchData : VitalGlitchDataType; + variable RXCRCOUT21_GlitchData : VitalGlitchDataType; + variable RXCRCOUT22_GlitchData : VitalGlitchDataType; + variable RXCRCOUT23_GlitchData : VitalGlitchDataType; + variable RXCRCOUT24_GlitchData : VitalGlitchDataType; + variable RXCRCOUT25_GlitchData : VitalGlitchDataType; + variable RXCRCOUT26_GlitchData : VitalGlitchDataType; + variable RXCRCOUT27_GlitchData : VitalGlitchDataType; + variable RXCRCOUT28_GlitchData : VitalGlitchDataType; + variable RXCRCOUT29_GlitchData : VitalGlitchDataType; + variable RXCRCOUT30_GlitchData : VitalGlitchDataType; + variable RXCRCOUT31_GlitchData : VitalGlitchDataType; + variable TXCRCOUT0_GlitchData : VitalGlitchDataType; + variable TXCRCOUT1_GlitchData : VitalGlitchDataType; + variable TXCRCOUT2_GlitchData : VitalGlitchDataType; + variable TXCRCOUT3_GlitchData : VitalGlitchDataType; + variable TXCRCOUT4_GlitchData : VitalGlitchDataType; + variable TXCRCOUT5_GlitchData : VitalGlitchDataType; + variable TXCRCOUT6_GlitchData : VitalGlitchDataType; + variable TXCRCOUT7_GlitchData : VitalGlitchDataType; + variable TXCRCOUT8_GlitchData : VitalGlitchDataType; + variable TXCRCOUT9_GlitchData : VitalGlitchDataType; + variable TXCRCOUT10_GlitchData : VitalGlitchDataType; + variable TXCRCOUT11_GlitchData : VitalGlitchDataType; + variable TXCRCOUT12_GlitchData : VitalGlitchDataType; + variable TXCRCOUT13_GlitchData : VitalGlitchDataType; + variable TXCRCOUT14_GlitchData : VitalGlitchDataType; + variable TXCRCOUT15_GlitchData : VitalGlitchDataType; + variable TXCRCOUT16_GlitchData : VitalGlitchDataType; + variable TXCRCOUT17_GlitchData : VitalGlitchDataType; + variable TXCRCOUT18_GlitchData : VitalGlitchDataType; + variable TXCRCOUT19_GlitchData : VitalGlitchDataType; + variable TXCRCOUT20_GlitchData : VitalGlitchDataType; + variable TXCRCOUT21_GlitchData : VitalGlitchDataType; + variable TXCRCOUT22_GlitchData : VitalGlitchDataType; + variable TXCRCOUT23_GlitchData : VitalGlitchDataType; + variable TXCRCOUT24_GlitchData : VitalGlitchDataType; + variable TXCRCOUT25_GlitchData : VitalGlitchDataType; + variable TXCRCOUT26_GlitchData : VitalGlitchDataType; + variable TXCRCOUT27_GlitchData : VitalGlitchDataType; + variable TXCRCOUT28_GlitchData : VitalGlitchDataType; + variable TXCRCOUT29_GlitchData : VitalGlitchDataType; + variable TXCRCOUT30_GlitchData : VitalGlitchDataType; + variable TXCRCOUT31_GlitchData : VitalGlitchDataType; + variable RXSIGDET_GlitchData : VitalGlitchDataType; + variable DRDY_GlitchData : VitalGlitchDataType; + variable DO0_GlitchData : VitalGlitchDataType; + variable DO1_GlitchData : VitalGlitchDataType; + variable DO2_GlitchData : VitalGlitchDataType; + variable DO3_GlitchData : VitalGlitchDataType; + variable DO4_GlitchData : VitalGlitchDataType; + variable DO5_GlitchData : VitalGlitchDataType; + variable DO6_GlitchData : VitalGlitchDataType; + variable DO7_GlitchData : VitalGlitchDataType; + variable DO8_GlitchData : VitalGlitchDataType; + variable DO9_GlitchData : VitalGlitchDataType; + variable DO10_GlitchData : VitalGlitchDataType; + variable DO11_GlitchData : VitalGlitchDataType; + variable DO12_GlitchData : VitalGlitchDataType; + variable DO13_GlitchData : VitalGlitchDataType; + variable DO14_GlitchData : VitalGlitchDataType; + variable DO15_GlitchData : VitalGlitchDataType; + variable RXMCLK_GlitchData : VitalGlitchDataType; + variable TX1P_GlitchData : VitalGlitchDataType; + variable TX1N_GlitchData : VitalGlitchDataType; + variable TXPCSHCLKOUT_GlitchData : VitalGlitchDataType; + variable RXPCSHCLKOUT_GlitchData : VitalGlitchDataType; + variable COMBUSOUT0_GlitchData : VitalGlitchDataType; + variable COMBUSOUT1_GlitchData : VitalGlitchDataType; + variable COMBUSOUT2_GlitchData : VitalGlitchDataType; + variable COMBUSOUT3_GlitchData : VitalGlitchDataType; + variable COMBUSOUT4_GlitchData : VitalGlitchDataType; + variable COMBUSOUT5_GlitchData : VitalGlitchDataType; + variable COMBUSOUT6_GlitchData : VitalGlitchDataType; + variable COMBUSOUT7_GlitchData : VitalGlitchDataType; + variable COMBUSOUT8_GlitchData : VitalGlitchDataType; + variable COMBUSOUT9_GlitchData : VitalGlitchDataType; + variable COMBUSOUT10_GlitchData : VitalGlitchDataType; + variable COMBUSOUT11_GlitchData : VitalGlitchDataType; + variable COMBUSOUT12_GlitchData : VitalGlitchDataType; + variable COMBUSOUT13_GlitchData : VitalGlitchDataType; + variable COMBUSOUT14_GlitchData : VitalGlitchDataType; + variable COMBUSOUT15_GlitchData : VitalGlitchDataType; +begin + +-- Output-to-Clock path delay + VitalPathDelay01 + ( + OutSignal => CHBONDO(0), + GlitchData => CHBONDO0_GlitchData, + OutSignalName => "CHBONDO(0)", + OutTemp => CHBONDO_OUT(0), + Paths => (0 => (RXUSRCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CHBONDO(1), + GlitchData => CHBONDO1_GlitchData, + OutSignalName => "CHBONDO(1)", + OutTemp => CHBONDO_OUT(1), + Paths => (0 => (RXUSRCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CHBONDO(2), + GlitchData => CHBONDO2_GlitchData, + OutSignalName => "CHBONDO(2)", + OutTemp => CHBONDO_OUT(2), + Paths => (0 => (RXUSRCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CHBONDO(3), + GlitchData => CHBONDO3_GlitchData, + OutSignalName => "CHBONDO(3)", + OutTemp => CHBONDO_OUT(3), + Paths => (0 => (RXUSRCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CHBONDO(4), + GlitchData => CHBONDO4_GlitchData, + OutSignalName => "CHBONDO(4)", + OutTemp => CHBONDO_OUT(4), + Paths => (0 => (RXUSRCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS(0), + GlitchData => RXSTATUS0_GlitchData, + OutSignalName => "RXSTATUS(0)", + OutTemp => RXSTATUS_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS(1), + GlitchData => RXSTATUS1_GlitchData, + OutSignalName => "RXSTATUS(1)", + OutTemp => RXSTATUS_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS(2), + GlitchData => RXSTATUS2_GlitchData, + OutSignalName => "RXSTATUS(2)", + OutTemp => RXSTATUS_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS(3), + GlitchData => RXSTATUS3_GlitchData, + OutSignalName => "RXSTATUS(3)", + OutTemp => RXSTATUS_OUT(3), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS(4), + GlitchData => RXSTATUS4_GlitchData, + OutSignalName => "RXSTATUS(4)", + OutTemp => RXSTATUS_OUT(4), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS(5), + GlitchData => RXSTATUS5_GlitchData, + OutSignalName => "RXSTATUS(5)", + OutTemp => RXSTATUS_OUT(5), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(0), + GlitchData => RXCHARISCOMMA0_GlitchData, + OutSignalName => "RXCHARISCOMMA(0)", + OutTemp => RXCHARISCOMMA_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(1), + GlitchData => RXCHARISCOMMA1_GlitchData, + OutSignalName => "RXCHARISCOMMA(1)", + OutTemp => RXCHARISCOMMA_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(2), + GlitchData => RXCHARISCOMMA2_GlitchData, + OutSignalName => "RXCHARISCOMMA(2)", + OutTemp => RXCHARISCOMMA_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(3), + GlitchData => RXCHARISCOMMA3_GlitchData, + OutSignalName => "RXCHARISCOMMA(3)", + OutTemp => RXCHARISCOMMA_OUT(3), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(4), + GlitchData => RXCHARISCOMMA4_GlitchData, + OutSignalName => "RXCHARISCOMMA(4)", + OutTemp => RXCHARISCOMMA_OUT(4), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(5), + GlitchData => RXCHARISCOMMA5_GlitchData, + OutSignalName => "RXCHARISCOMMA(5)", + OutTemp => RXCHARISCOMMA_OUT(5), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(6), + GlitchData => RXCHARISCOMMA6_GlitchData, + OutSignalName => "RXCHARISCOMMA(6)", + OutTemp => RXCHARISCOMMA_OUT(6), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA(7), + GlitchData => RXCHARISCOMMA7_GlitchData, + OutSignalName => "RXCHARISCOMMA(7)", + OutTemp => RXCHARISCOMMA_OUT(7), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(0), + GlitchData => RXCHARISK0_GlitchData, + OutSignalName => "RXCHARISK(0)", + OutTemp => RXCHARISK_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(1), + GlitchData => RXCHARISK1_GlitchData, + OutSignalName => "RXCHARISK(1)", + OutTemp => RXCHARISK_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(2), + GlitchData => RXCHARISK2_GlitchData, + OutSignalName => "RXCHARISK(2)", + OutTemp => RXCHARISK_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(3), + GlitchData => RXCHARISK3_GlitchData, + OutSignalName => "RXCHARISK(3)", + OutTemp => RXCHARISK_OUT(3), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(4), + GlitchData => RXCHARISK4_GlitchData, + OutSignalName => "RXCHARISK(4)", + OutTemp => RXCHARISK_OUT(4), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(5), + GlitchData => RXCHARISK5_GlitchData, + OutSignalName => "RXCHARISK(5)", + OutTemp => RXCHARISK_OUT(5), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(6), + GlitchData => RXCHARISK6_GlitchData, + OutSignalName => "RXCHARISK(6)", + OutTemp => RXCHARISK_OUT(6), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK(7), + GlitchData => RXCHARISK7_GlitchData, + OutSignalName => "RXCHARISK(7)", + OutTemp => RXCHARISK_OUT(7), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCOMMADET, + GlitchData => RXCOMMADET_GlitchData, + OutSignalName => "RXCOMMADET", + OutTemp => RXCOMMADET_OUT, + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(0), + GlitchData => RXDATA0_GlitchData, + OutSignalName => "RXDATA(0)", + OutTemp => RXDATA_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(1), + GlitchData => RXDATA1_GlitchData, + OutSignalName => "RXDATA(1)", + OutTemp => RXDATA_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(2), + GlitchData => RXDATA2_GlitchData, + OutSignalName => "RXDATA(2)", + OutTemp => RXDATA_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(3), + GlitchData => RXDATA3_GlitchData, + OutSignalName => "RXDATA(3)", + OutTemp => RXDATA_OUT(3), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(4), + GlitchData => RXDATA4_GlitchData, + OutSignalName => "RXDATA(4)", + OutTemp => RXDATA_OUT(4), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(5), + GlitchData => RXDATA5_GlitchData, + OutSignalName => "RXDATA(5)", + OutTemp => RXDATA_OUT(5), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(6), + GlitchData => RXDATA6_GlitchData, + OutSignalName => "RXDATA(6)", + OutTemp => RXDATA_OUT(6), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(7), + GlitchData => RXDATA7_GlitchData, + OutSignalName => "RXDATA(7)", + OutTemp => RXDATA_OUT(7), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(8), + GlitchData => RXDATA8_GlitchData, + OutSignalName => "RXDATA(8)", + OutTemp => RXDATA_OUT(8), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(9), + GlitchData => RXDATA9_GlitchData, + OutSignalName => "RXDATA(9)", + OutTemp => RXDATA_OUT(9), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(10), + GlitchData => RXDATA10_GlitchData, + OutSignalName => "RXDATA(10)", + OutTemp => RXDATA_OUT(10), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(11), + GlitchData => RXDATA11_GlitchData, + OutSignalName => "RXDATA(11)", + OutTemp => RXDATA_OUT(11), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(12), + GlitchData => RXDATA12_GlitchData, + OutSignalName => "RXDATA(12)", + OutTemp => RXDATA_OUT(12), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(13), + GlitchData => RXDATA13_GlitchData, + OutSignalName => "RXDATA(13)", + OutTemp => RXDATA_OUT(13), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(14), + GlitchData => RXDATA14_GlitchData, + OutSignalName => "RXDATA(14)", + OutTemp => RXDATA_OUT(14), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(15), + GlitchData => RXDATA15_GlitchData, + OutSignalName => "RXDATA(15)", + OutTemp => RXDATA_OUT(15), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(16), + GlitchData => RXDATA16_GlitchData, + OutSignalName => "RXDATA(16)", + OutTemp => RXDATA_OUT(16), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(17), + GlitchData => RXDATA17_GlitchData, + OutSignalName => "RXDATA(17)", + OutTemp => RXDATA_OUT(17), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(18), + GlitchData => RXDATA18_GlitchData, + OutSignalName => "RXDATA(18)", + OutTemp => RXDATA_OUT(18), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(19), + GlitchData => RXDATA19_GlitchData, + OutSignalName => "RXDATA(19)", + OutTemp => RXDATA_OUT(19), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(20), + GlitchData => RXDATA20_GlitchData, + OutSignalName => "RXDATA(20)", + OutTemp => RXDATA_OUT(20), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(21), + GlitchData => RXDATA21_GlitchData, + OutSignalName => "RXDATA(21)", + OutTemp => RXDATA_OUT(21), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(22), + GlitchData => RXDATA22_GlitchData, + OutSignalName => "RXDATA(22)", + OutTemp => RXDATA_OUT(22), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(23), + GlitchData => RXDATA23_GlitchData, + OutSignalName => "RXDATA(23)", + OutTemp => RXDATA_OUT(23), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(24), + GlitchData => RXDATA24_GlitchData, + OutSignalName => "RXDATA(24)", + OutTemp => RXDATA_OUT(24), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(25), + GlitchData => RXDATA25_GlitchData, + OutSignalName => "RXDATA(25)", + OutTemp => RXDATA_OUT(25), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(26), + GlitchData => RXDATA26_GlitchData, + OutSignalName => "RXDATA(26)", + OutTemp => RXDATA_OUT(26), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(27), + GlitchData => RXDATA27_GlitchData, + OutSignalName => "RXDATA(27)", + OutTemp => RXDATA_OUT(27), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(28), + GlitchData => RXDATA28_GlitchData, + OutSignalName => "RXDATA(28)", + OutTemp => RXDATA_OUT(28), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(29), + GlitchData => RXDATA29_GlitchData, + OutSignalName => "RXDATA(29)", + OutTemp => RXDATA_OUT(29), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(30), + GlitchData => RXDATA30_GlitchData, + OutSignalName => "RXDATA(30)", + OutTemp => RXDATA_OUT(30), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(31), + GlitchData => RXDATA31_GlitchData, + OutSignalName => "RXDATA(31)", + OutTemp => RXDATA_OUT(31), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(32), + GlitchData => RXDATA32_GlitchData, + OutSignalName => "RXDATA(32)", + OutTemp => RXDATA_OUT(32), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(33), + GlitchData => RXDATA33_GlitchData, + OutSignalName => "RXDATA(33)", + OutTemp => RXDATA_OUT(33), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(34), + GlitchData => RXDATA34_GlitchData, + OutSignalName => "RXDATA(34)", + OutTemp => RXDATA_OUT(34), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(35), + GlitchData => RXDATA35_GlitchData, + OutSignalName => "RXDATA(35)", + OutTemp => RXDATA_OUT(35), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(36), + GlitchData => RXDATA36_GlitchData, + OutSignalName => "RXDATA(36)", + OutTemp => RXDATA_OUT(36), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(37), + GlitchData => RXDATA37_GlitchData, + OutSignalName => "RXDATA(37)", + OutTemp => RXDATA_OUT(37), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(38), + GlitchData => RXDATA38_GlitchData, + OutSignalName => "RXDATA(38)", + OutTemp => RXDATA_OUT(38), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(39), + GlitchData => RXDATA39_GlitchData, + OutSignalName => "RXDATA(39)", + OutTemp => RXDATA_OUT(39), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(40), + GlitchData => RXDATA40_GlitchData, + OutSignalName => "RXDATA(40)", + OutTemp => RXDATA_OUT(40), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(41), + GlitchData => RXDATA41_GlitchData, + OutSignalName => "RXDATA(41)", + OutTemp => RXDATA_OUT(41), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(42), + GlitchData => RXDATA42_GlitchData, + OutSignalName => "RXDATA(42)", + OutTemp => RXDATA_OUT(42), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(43), + GlitchData => RXDATA43_GlitchData, + OutSignalName => "RXDATA(43)", + OutTemp => RXDATA_OUT(43), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(44), + GlitchData => RXDATA44_GlitchData, + OutSignalName => "RXDATA(44)", + OutTemp => RXDATA_OUT(44), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(45), + GlitchData => RXDATA45_GlitchData, + OutSignalName => "RXDATA(45)", + OutTemp => RXDATA_OUT(45), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(46), + GlitchData => RXDATA46_GlitchData, + OutSignalName => "RXDATA(46)", + OutTemp => RXDATA_OUT(46), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(47), + GlitchData => RXDATA47_GlitchData, + OutSignalName => "RXDATA(47)", + OutTemp => RXDATA_OUT(47), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(48), + GlitchData => RXDATA48_GlitchData, + OutSignalName => "RXDATA(48)", + OutTemp => RXDATA_OUT(48), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(49), + GlitchData => RXDATA49_GlitchData, + OutSignalName => "RXDATA(49)", + OutTemp => RXDATA_OUT(49), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(50), + GlitchData => RXDATA50_GlitchData, + OutSignalName => "RXDATA(50)", + OutTemp => RXDATA_OUT(50), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(51), + GlitchData => RXDATA51_GlitchData, + OutSignalName => "RXDATA(51)", + OutTemp => RXDATA_OUT(51), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(52), + GlitchData => RXDATA52_GlitchData, + OutSignalName => "RXDATA(52)", + OutTemp => RXDATA_OUT(52), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(53), + GlitchData => RXDATA53_GlitchData, + OutSignalName => "RXDATA(53)", + OutTemp => RXDATA_OUT(53), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(54), + GlitchData => RXDATA54_GlitchData, + OutSignalName => "RXDATA(54)", + OutTemp => RXDATA_OUT(54), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(55), + GlitchData => RXDATA55_GlitchData, + OutSignalName => "RXDATA(55)", + OutTemp => RXDATA_OUT(55), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(56), + GlitchData => RXDATA56_GlitchData, + OutSignalName => "RXDATA(56)", + OutTemp => RXDATA_OUT(56), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(57), + GlitchData => RXDATA57_GlitchData, + OutSignalName => "RXDATA(57)", + OutTemp => RXDATA_OUT(57), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(58), + GlitchData => RXDATA58_GlitchData, + OutSignalName => "RXDATA(58)", + OutTemp => RXDATA_OUT(58), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(59), + GlitchData => RXDATA59_GlitchData, + OutSignalName => "RXDATA(59)", + OutTemp => RXDATA_OUT(59), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(60), + GlitchData => RXDATA60_GlitchData, + OutSignalName => "RXDATA(60)", + OutTemp => RXDATA_OUT(60), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(61), + GlitchData => RXDATA61_GlitchData, + OutSignalName => "RXDATA(61)", + OutTemp => RXDATA_OUT(61), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(62), + GlitchData => RXDATA62_GlitchData, + OutSignalName => "RXDATA(62)", + OutTemp => RXDATA_OUT(62), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA(63), + GlitchData => RXDATA63_GlitchData, + OutSignalName => "RXDATA(63)", + OutTemp => RXDATA_OUT(63), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(0), + GlitchData => RXDISPERR0_GlitchData, + OutSignalName => "RXDISPERR(0)", + OutTemp => RXDISPERR_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(1), + GlitchData => RXDISPERR1_GlitchData, + OutSignalName => "RXDISPERR(1)", + OutTemp => RXDISPERR_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(2), + GlitchData => RXDISPERR2_GlitchData, + OutSignalName => "RXDISPERR(2)", + OutTemp => RXDISPERR_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(3), + GlitchData => RXDISPERR3_GlitchData, + OutSignalName => "RXDISPERR(3)", + OutTemp => RXDISPERR_OUT(3), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(4), + GlitchData => RXDISPERR4_GlitchData, + OutSignalName => "RXDISPERR(4)", + OutTemp => RXDISPERR_OUT(4), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(5), + GlitchData => RXDISPERR5_GlitchData, + OutSignalName => "RXDISPERR(5)", + OutTemp => RXDISPERR_OUT(5), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(6), + GlitchData => RXDISPERR6_GlitchData, + OutSignalName => "RXDISPERR(6)", + OutTemp => RXDISPERR_OUT(6), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR(7), + GlitchData => RXDISPERR7_GlitchData, + OutSignalName => "RXDISPERR(7)", + OutTemp => RXDISPERR_OUT(7), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC(0), + GlitchData => RXLOSSOFSYNC0_GlitchData, + OutSignalName => "RXLOSSOFSYNC(0)", + OutTemp => RXLOSSOFSYNC_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC(1), + GlitchData => RXLOSSOFSYNC1_GlitchData, + OutSignalName => "RXLOSSOFSYNC(1)", + OutTemp => RXLOSSOFSYNC_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(0), + GlitchData => RXNOTINTABLE0_GlitchData, + OutSignalName => "RXNOTINTABLE(0)", + OutTemp => RXNOTINTABLE_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(1), + GlitchData => RXNOTINTABLE1_GlitchData, + OutSignalName => "RXNOTINTABLE(1)", + OutTemp => RXNOTINTABLE_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(2), + GlitchData => RXNOTINTABLE2_GlitchData, + OutSignalName => "RXNOTINTABLE(2)", + OutTemp => RXNOTINTABLE_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(3), + GlitchData => RXNOTINTABLE3_GlitchData, + OutSignalName => "RXNOTINTABLE(3)", + OutTemp => RXNOTINTABLE_OUT(3), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(4), + GlitchData => RXNOTINTABLE4_GlitchData, + OutSignalName => "RXNOTINTABLE(4)", + OutTemp => RXNOTINTABLE_OUT(4), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(5), + GlitchData => RXNOTINTABLE5_GlitchData, + OutSignalName => "RXNOTINTABLE(5)", + OutTemp => RXNOTINTABLE_OUT(5), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(6), + GlitchData => RXNOTINTABLE6_GlitchData, + OutSignalName => "RXNOTINTABLE(6)", + OutTemp => RXNOTINTABLE_OUT(6), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE(7), + GlitchData => RXNOTINTABLE7_GlitchData, + OutSignalName => "RXNOTINTABLE(7)", + OutTemp => RXNOTINTABLE_OUT(7), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXREALIGN, + GlitchData => RXREALIGN_GlitchData, + OutSignalName => "RXREALIGN", + OutTemp => RXREALIGN_OUT, + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(0), + GlitchData => RXRUNDISP0_GlitchData, + OutSignalName => "RXRUNDISP(0)", + OutTemp => RXRUNDISP_OUT(0), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(1), + GlitchData => RXRUNDISP1_GlitchData, + OutSignalName => "RXRUNDISP(1)", + OutTemp => RXRUNDISP_OUT(1), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(2), + GlitchData => RXRUNDISP2_GlitchData, + OutSignalName => "RXRUNDISP(2)", + OutTemp => RXRUNDISP_OUT(2), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(3), + GlitchData => RXRUNDISP3_GlitchData, + OutSignalName => "RXRUNDISP(3)", + OutTemp => RXRUNDISP_OUT(3), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(4), + GlitchData => RXRUNDISP4_GlitchData, + OutSignalName => "RXRUNDISP(4)", + OutTemp => RXRUNDISP_OUT(4), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(5), + GlitchData => RXRUNDISP5_GlitchData, + OutSignalName => "RXRUNDISP(5)", + OutTemp => RXRUNDISP_OUT(5), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(6), + GlitchData => RXRUNDISP6_GlitchData, + OutSignalName => "RXRUNDISP(6)", + OutTemp => RXRUNDISP_OUT(6), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP(7), + GlitchData => RXRUNDISP7_GlitchData, + OutSignalName => "RXRUNDISP(7)", + OutTemp => RXRUNDISP_OUT(7), + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFERR, + GlitchData => RXBUFERR_GlitchData, + OutSignalName => "RXBUFERR", + OutTemp => RXBUFERR_OUT, + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXBUFERR, + GlitchData => TXBUFERR_GlitchData, + OutSignalName => "TXBUFERR", + OutTemp => TXBUFERR_OUT, + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(0), + GlitchData => TXKERR0_GlitchData, + OutSignalName => "TXKERR(0)", + OutTemp => TXKERR_OUT(0), + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(1), + GlitchData => TXKERR1_GlitchData, + OutSignalName => "TXKERR(1)", + OutTemp => TXKERR_OUT(1), + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(2), + GlitchData => TXKERR2_GlitchData, + OutSignalName => "TXKERR(2)", + OutTemp => TXKERR_OUT(2), + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(3), + GlitchData => TXKERR3_GlitchData, + OutSignalName => "TXKERR(3)", + OutTemp => TXKERR_OUT(3), + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(4), + GlitchData => TXKERR4_GlitchData, + OutSignalName => "TXKERR(4)", + OutTemp => TXKERR_OUT(4), + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(5), + GlitchData => TXKERR5_GlitchData, + OutSignalName => "TXKERR(5)", + OutTemp => TXKERR_OUT(5), + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(6), + GlitchData => TXKERR6_GlitchData, + OutSignalName => "TXKERR(6)", + OutTemp => TXKERR_OUT(6), + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR(7), + GlitchData => TXKERR7_GlitchData, + OutSignalName => "TXKERR(7)", + OutTemp => TXKERR_OUT(7), + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(0), + GlitchData => TXRUNDISP0_GlitchData, + OutSignalName => "TXRUNDISP(0)", + OutTemp => TXRUNDISP_OUT(0), + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(1), + GlitchData => TXRUNDISP1_GlitchData, + OutSignalName => "TXRUNDISP(1)", + OutTemp => TXRUNDISP_OUT(1), + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(2), + GlitchData => TXRUNDISP2_GlitchData, + OutSignalName => "TXRUNDISP(2)", + OutTemp => TXRUNDISP_OUT(2), + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(3), + GlitchData => TXRUNDISP3_GlitchData, + OutSignalName => "TXRUNDISP(3)", + OutTemp => TXRUNDISP_OUT(3), + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(4), + GlitchData => TXRUNDISP4_GlitchData, + OutSignalName => "TXRUNDISP(4)", + OutTemp => TXRUNDISP_OUT(4), + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(5), + GlitchData => TXRUNDISP5_GlitchData, + OutSignalName => "TXRUNDISP(5)", + OutTemp => TXRUNDISP_OUT(5), + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(6), + GlitchData => TXRUNDISP6_GlitchData, + OutSignalName => "TXRUNDISP(6)", + OutTemp => TXRUNDISP_OUT(6), + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP(7), + GlitchData => TXRUNDISP7_GlitchData, + OutSignalName => "TXRUNDISP(7)", + OutTemp => TXRUNDISP_OUT(7), + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOCK, + GlitchData => RXLOCK_GlitchData, + OutSignalName => "RXLOCK", + OutTemp => RXLOCK_OUT, + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXLOCK, + GlitchData => TXLOCK_GlitchData, + OutSignalName => "TXLOCK", + OutTemp => TXLOCK_OUT, + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCYCLELIMIT, + GlitchData => RXCYCLELIMIT_GlitchData, + OutSignalName => "RXCYCLELIMIT", + OutTemp => RXCYCLELIMIT_OUT, + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCYCLELIMIT, + GlitchData => TXCYCLELIMIT_GlitchData, + OutSignalName => "TXCYCLELIMIT", + OutTemp => TXCYCLELIMIT_OUT, + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCALFAIL, + GlitchData => RXCALFAIL_GlitchData, + OutSignalName => "RXCALFAIL", + OutTemp => RXCALFAIL_OUT, + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCALFAIL, + GlitchData => TXCALFAIL_GlitchData, + OutSignalName => "TXCALFAIL", + OutTemp => TXCALFAIL_OUT, + Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(0), + GlitchData => RXCRCOUT0_GlitchData, + OutSignalName => "RXCRCOUT(0)", + OutTemp => RXCRCOUT_OUT(0), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(1), + GlitchData => RXCRCOUT1_GlitchData, + OutSignalName => "RXCRCOUT(1)", + OutTemp => RXCRCOUT_OUT(1), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(2), + GlitchData => RXCRCOUT2_GlitchData, + OutSignalName => "RXCRCOUT(2)", + OutTemp => RXCRCOUT_OUT(2), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(3), + GlitchData => RXCRCOUT3_GlitchData, + OutSignalName => "RXCRCOUT(3)", + OutTemp => RXCRCOUT_OUT(3), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(4), + GlitchData => RXCRCOUT4_GlitchData, + OutSignalName => "RXCRCOUT(4)", + OutTemp => RXCRCOUT_OUT(4), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(5), + GlitchData => RXCRCOUT5_GlitchData, + OutSignalName => "RXCRCOUT(5)", + OutTemp => RXCRCOUT_OUT(5), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(6), + GlitchData => RXCRCOUT6_GlitchData, + OutSignalName => "RXCRCOUT(6)", + OutTemp => RXCRCOUT_OUT(6), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(7), + GlitchData => RXCRCOUT7_GlitchData, + OutSignalName => "RXCRCOUT(7)", + OutTemp => RXCRCOUT_OUT(7), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(8), + GlitchData => RXCRCOUT8_GlitchData, + OutSignalName => "RXCRCOUT(8)", + OutTemp => RXCRCOUT_OUT(8), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(9), + GlitchData => RXCRCOUT9_GlitchData, + OutSignalName => "RXCRCOUT(9)", + OutTemp => RXCRCOUT_OUT(9), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(10), + GlitchData => RXCRCOUT10_GlitchData, + OutSignalName => "RXCRCOUT(10)", + OutTemp => RXCRCOUT_OUT(10), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(11), + GlitchData => RXCRCOUT11_GlitchData, + OutSignalName => "RXCRCOUT(11)", + OutTemp => RXCRCOUT_OUT(11), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(12), + GlitchData => RXCRCOUT12_GlitchData, + OutSignalName => "RXCRCOUT(12)", + OutTemp => RXCRCOUT_OUT(12), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(13), + GlitchData => RXCRCOUT13_GlitchData, + OutSignalName => "RXCRCOUT(13)", + OutTemp => RXCRCOUT_OUT(13), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(14), + GlitchData => RXCRCOUT14_GlitchData, + OutSignalName => "RXCRCOUT(14)", + OutTemp => RXCRCOUT_OUT(14), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(15), + GlitchData => RXCRCOUT15_GlitchData, + OutSignalName => "RXCRCOUT(15)", + OutTemp => RXCRCOUT_OUT(15), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(16), + GlitchData => RXCRCOUT16_GlitchData, + OutSignalName => "RXCRCOUT(16)", + OutTemp => RXCRCOUT_OUT(16), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(17), + GlitchData => RXCRCOUT17_GlitchData, + OutSignalName => "RXCRCOUT(17)", + OutTemp => RXCRCOUT_OUT(17), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(18), + GlitchData => RXCRCOUT18_GlitchData, + OutSignalName => "RXCRCOUT(18)", + OutTemp => RXCRCOUT_OUT(18), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(19), + GlitchData => RXCRCOUT19_GlitchData, + OutSignalName => "RXCRCOUT(19)", + OutTemp => RXCRCOUT_OUT(19), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(20), + GlitchData => RXCRCOUT20_GlitchData, + OutSignalName => "RXCRCOUT(20)", + OutTemp => RXCRCOUT_OUT(20), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(21), + GlitchData => RXCRCOUT21_GlitchData, + OutSignalName => "RXCRCOUT(21)", + OutTemp => RXCRCOUT_OUT(21), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(22), + GlitchData => RXCRCOUT22_GlitchData, + OutSignalName => "RXCRCOUT(22)", + OutTemp => RXCRCOUT_OUT(22), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(23), + GlitchData => RXCRCOUT23_GlitchData, + OutSignalName => "RXCRCOUT(23)", + OutTemp => RXCRCOUT_OUT(23), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(24), + GlitchData => RXCRCOUT24_GlitchData, + OutSignalName => "RXCRCOUT(24)", + OutTemp => RXCRCOUT_OUT(24), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(25), + GlitchData => RXCRCOUT25_GlitchData, + OutSignalName => "RXCRCOUT(25)", + OutTemp => RXCRCOUT_OUT(25), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(26), + GlitchData => RXCRCOUT26_GlitchData, + OutSignalName => "RXCRCOUT(26)", + OutTemp => RXCRCOUT_OUT(26), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(27), + GlitchData => RXCRCOUT27_GlitchData, + OutSignalName => "RXCRCOUT(27)", + OutTemp => RXCRCOUT_OUT(27), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(28), + GlitchData => RXCRCOUT28_GlitchData, + OutSignalName => "RXCRCOUT(28)", + OutTemp => RXCRCOUT_OUT(28), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(29), + GlitchData => RXCRCOUT29_GlitchData, + OutSignalName => "RXCRCOUT(29)", + OutTemp => RXCRCOUT_OUT(29), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(30), + GlitchData => RXCRCOUT30_GlitchData, + OutSignalName => "RXCRCOUT(30)", + OutTemp => RXCRCOUT_OUT(30), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCRCOUT(31), + GlitchData => RXCRCOUT31_GlitchData, + OutSignalName => "RXCRCOUT(31)", + OutTemp => RXCRCOUT_OUT(31), + Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(0), + GlitchData => TXCRCOUT0_GlitchData, + OutSignalName => "TXCRCOUT(0)", + OutTemp => TXCRCOUT_OUT(0), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(1), + GlitchData => TXCRCOUT1_GlitchData, + OutSignalName => "TXCRCOUT(1)", + OutTemp => TXCRCOUT_OUT(1), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(2), + GlitchData => TXCRCOUT2_GlitchData, + OutSignalName => "TXCRCOUT(2)", + OutTemp => TXCRCOUT_OUT(2), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(3), + GlitchData => TXCRCOUT3_GlitchData, + OutSignalName => "TXCRCOUT(3)", + OutTemp => TXCRCOUT_OUT(3), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(4), + GlitchData => TXCRCOUT4_GlitchData, + OutSignalName => "TXCRCOUT(4)", + OutTemp => TXCRCOUT_OUT(4), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(5), + GlitchData => TXCRCOUT5_GlitchData, + OutSignalName => "TXCRCOUT(5)", + OutTemp => TXCRCOUT_OUT(5), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(6), + GlitchData => TXCRCOUT6_GlitchData, + OutSignalName => "TXCRCOUT(6)", + OutTemp => TXCRCOUT_OUT(6), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(7), + GlitchData => TXCRCOUT7_GlitchData, + OutSignalName => "TXCRCOUT(7)", + OutTemp => TXCRCOUT_OUT(7), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(8), + GlitchData => TXCRCOUT8_GlitchData, + OutSignalName => "TXCRCOUT(8)", + OutTemp => TXCRCOUT_OUT(8), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(9), + GlitchData => TXCRCOUT9_GlitchData, + OutSignalName => "TXCRCOUT(9)", + OutTemp => TXCRCOUT_OUT(9), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(10), + GlitchData => TXCRCOUT10_GlitchData, + OutSignalName => "TXCRCOUT(10)", + OutTemp => TXCRCOUT_OUT(10), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(11), + GlitchData => TXCRCOUT11_GlitchData, + OutSignalName => "TXCRCOUT(11)", + OutTemp => TXCRCOUT_OUT(11), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(12), + GlitchData => TXCRCOUT12_GlitchData, + OutSignalName => "TXCRCOUT(12)", + OutTemp => TXCRCOUT_OUT(12), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(13), + GlitchData => TXCRCOUT13_GlitchData, + OutSignalName => "TXCRCOUT(13)", + OutTemp => TXCRCOUT_OUT(13), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(14), + GlitchData => TXCRCOUT14_GlitchData, + OutSignalName => "TXCRCOUT(14)", + OutTemp => TXCRCOUT_OUT(14), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(15), + GlitchData => TXCRCOUT15_GlitchData, + OutSignalName => "TXCRCOUT(15)", + OutTemp => TXCRCOUT_OUT(15), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(16), + GlitchData => TXCRCOUT16_GlitchData, + OutSignalName => "TXCRCOUT(16)", + OutTemp => TXCRCOUT_OUT(16), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(17), + GlitchData => TXCRCOUT17_GlitchData, + OutSignalName => "TXCRCOUT(17)", + OutTemp => TXCRCOUT_OUT(17), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(18), + GlitchData => TXCRCOUT18_GlitchData, + OutSignalName => "TXCRCOUT(18)", + OutTemp => TXCRCOUT_OUT(18), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(19), + GlitchData => TXCRCOUT19_GlitchData, + OutSignalName => "TXCRCOUT(19)", + OutTemp => TXCRCOUT_OUT(19), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(20), + GlitchData => TXCRCOUT20_GlitchData, + OutSignalName => "TXCRCOUT(20)", + OutTemp => TXCRCOUT_OUT(20), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(21), + GlitchData => TXCRCOUT21_GlitchData, + OutSignalName => "TXCRCOUT(21)", + OutTemp => TXCRCOUT_OUT(21), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(22), + GlitchData => TXCRCOUT22_GlitchData, + OutSignalName => "TXCRCOUT(22)", + OutTemp => TXCRCOUT_OUT(22), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(23), + GlitchData => TXCRCOUT23_GlitchData, + OutSignalName => "TXCRCOUT(23)", + OutTemp => TXCRCOUT_OUT(23), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(24), + GlitchData => TXCRCOUT24_GlitchData, + OutSignalName => "TXCRCOUT(24)", + OutTemp => TXCRCOUT_OUT(24), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(25), + GlitchData => TXCRCOUT25_GlitchData, + OutSignalName => "TXCRCOUT(25)", + OutTemp => TXCRCOUT_OUT(25), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(26), + GlitchData => TXCRCOUT26_GlitchData, + OutSignalName => "TXCRCOUT(26)", + OutTemp => TXCRCOUT_OUT(26), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(27), + GlitchData => TXCRCOUT27_GlitchData, + OutSignalName => "TXCRCOUT(27)", + OutTemp => TXCRCOUT_OUT(27), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(28), + GlitchData => TXCRCOUT28_GlitchData, + OutSignalName => "TXCRCOUT(28)", + OutTemp => TXCRCOUT_OUT(28), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(29), + GlitchData => TXCRCOUT29_GlitchData, + OutSignalName => "TXCRCOUT(29)", + OutTemp => TXCRCOUT_OUT(29), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(30), + GlitchData => TXCRCOUT30_GlitchData, + OutSignalName => "TXCRCOUT(30)", + OutTemp => TXCRCOUT_OUT(30), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXCRCOUT(31), + GlitchData => TXCRCOUT31_GlitchData, + OutSignalName => "TXCRCOUT(31)", + OutTemp => TXCRCOUT_OUT(31), + Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSIGDET, + GlitchData => RXSIGDET_GlitchData, + OutSignalName => "RXSIGDET", + OutTemp => RXSIGDET_OUT, + Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DRDY, + GlitchData => DRDY_GlitchData, + OutSignalName => "DRDY", + OutTemp => DRDY_OUT, + Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(0), + GlitchData => DO0_GlitchData, + OutSignalName => "DO(0)", + OutTemp => DO_OUT(0), + Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(1), + GlitchData => DO1_GlitchData, + OutSignalName => "DO(1)", + OutTemp => DO_OUT(1), + Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(2), + GlitchData => DO2_GlitchData, + OutSignalName => "DO(2)", + OutTemp => DO_OUT(2), + Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(3), + GlitchData => DO3_GlitchData, + OutSignalName => "DO(3)", + OutTemp => DO_OUT(3), + Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(4), + GlitchData => DO4_GlitchData, + OutSignalName => "DO(4)", + OutTemp => DO_OUT(4), + Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(5), + GlitchData => DO5_GlitchData, + OutSignalName => "DO(5)", + OutTemp => DO_OUT(5), + Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(6), + GlitchData => DO6_GlitchData, + OutSignalName => "DO(6)", + OutTemp => DO_OUT(6), + Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(7), + GlitchData => DO7_GlitchData, + OutSignalName => "DO(7)", + OutTemp => DO_OUT(7), + Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(8), + GlitchData => DO8_GlitchData, + OutSignalName => "DO(8)", + OutTemp => DO_OUT(8), + Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(9), + GlitchData => DO9_GlitchData, + OutSignalName => "DO(9)", + OutTemp => DO_OUT(9), + Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(10), + GlitchData => DO10_GlitchData, + OutSignalName => "DO(10)", + OutTemp => DO_OUT(10), + Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(11), + GlitchData => DO11_GlitchData, + OutSignalName => "DO(11)", + OutTemp => DO_OUT(11), + Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(12), + GlitchData => DO12_GlitchData, + OutSignalName => "DO(12)", + OutTemp => DO_OUT(12), + Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(13), + GlitchData => DO13_GlitchData, + OutSignalName => "DO(13)", + OutTemp => DO_OUT(13), + Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(14), + GlitchData => DO14_GlitchData, + OutSignalName => "DO(14)", + OutTemp => DO_OUT(14), + Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(15), + GlitchData => DO15_GlitchData, + OutSignalName => "DO(15)", + OutTemp => DO_OUT(15), + Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + +-- Wait signal (input/output pins) + wait on + CHBONDO_OUT, + RXSTATUS_OUT, + RXCHARISCOMMA_OUT, + RXCHARISK_OUT, + RXCOMMADET_OUT, + RXDATA_OUT, + RXDISPERR_OUT, + RXLOSSOFSYNC_OUT, + RXNOTINTABLE_OUT, + RXREALIGN_OUT, + RXRUNDISP_OUT, + RXBUFERR_OUT, + TXBUFERR_OUT, + TXKERR_OUT, + TXRUNDISP_OUT, + RXLOCK_OUT, + TXLOCK_OUT, + RXCYCLELIMIT_OUT, + TXCYCLELIMIT_OUT, + RXCALFAIL_OUT, + TXCALFAIL_OUT, + RXCRCOUT_OUT, + TXCRCOUT_OUT, + RXSIGDET_OUT, + DRDY_OUT, + DO_OUT, + CHBONDI_ipd, + ENCHANSYNC_ipd, + ENMCOMMAALIGN_ipd, + ENPCOMMAALIGN_ipd, + LOOPBACK_ipd, + POWERDOWN_ipd, + RXBLOCKSYNC64B66BUSE_ipd, + RXCOMMADETUSE_ipd, + RXDATAWIDTH_ipd, + RXDEC64B66BUSE_ipd, + RXDEC8B10BUSE_ipd, + RXDESCRAM64B66BUSE_ipd, + RXIGNOREBTF_ipd, + RXINTDATAWIDTH_ipd, + RXPOLARITY_ipd, + RXRESET_ipd, + RXSLIDE_ipd, + RXUSRCLK_ipd, + RXUSRCLK2_ipd, + TXBYPASS8B10B_ipd, + TXCHARDISPMODE_ipd, + TXCHARDISPVAL_ipd, + TXCHARISK_ipd, + TXDATA_ipd, + TXDATAWIDTH_ipd, + TXENC64B66BUSE_ipd, + TXENC8B10BUSE_ipd, + TXGEARBOX64B66BUSE_ipd, + TXINHIBIT_ipd, + TXINTDATAWIDTH_ipd, + TXPOLARITY_ipd, + TXRESET_ipd, + TXSCRAM64B66BUSE_ipd, + TXUSRCLK_ipd, + TXUSRCLK2_ipd, + RXCLKSTABLE_ipd, + RXPMARESET_ipd, + TXCLKSTABLE_ipd, + TXPMARESET_ipd, + RXCRCIN_ipd, + RXCRCDATAWIDTH_ipd, + RXCRCDATAVALID_ipd, + RXCRCINIT_ipd, + RXCRCRESET_ipd, + RXCRCPD_ipd, + RXCRCCLK_ipd, + RXCRCINTCLK_ipd, + TXCRCIN_ipd, + TXCRCDATAWIDTH_ipd, + TXCRCDATAVALID_ipd, + TXCRCINIT_ipd, + TXCRCRESET_ipd, + TXCRCPD_ipd, + TXCRCCLK_ipd, + TXCRCINTCLK_ipd, + TXSYNC_ipd, + RXSYNC_ipd, + TXENOOB_ipd, + DCLK_ipd, + DADDR_ipd, + DEN_ipd, + DWE_ipd, + DI_ipd, + RX1P_ipd, + RX1N_ipd, + GREFCLK_ipd, + REFCLK1_ipd, + REFCLK2_ipd, + COMBUSIN_ipd; + + + end process TIMING; +RXPCSHCLKOUT <= RXPCSHCLKOUT_OUT; +TXPCSHCLKOUT <= TXPCSHCLKOUT_OUT; +RXMCLK <= RXMCLK_OUT; +RXRECCLK1 <= RXRECCLK1_OUT; +RXRECCLK2 <= RXRECCLK2_OUT; +TXOUTCLK1 <= TXOUTCLK1_OUT; +TXOUTCLK2 <= TXOUTCLK2_OUT; +TX1N <= TX1N_OUT; +TX1P <= TX1P_OUT; +COMBUSOUT <= COMBUSOUT_OUT; +end GT11_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/SMODEL/Attic/ppc405_adv.vhd,v 1.13 2007/09/13 23:04:05 vandanad Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Power PC Core +-- /___/ /\ Filename : PPC405_ADV.vhd +-- \ \ / \ Timestamp : Fri Jun 18 10:57:02 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + + + +------------------------------------------------------------------------------- +-- Model for fpga_startup_virtex4 (for simulation only) +------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity fpga_startup_virtex4 is + + port ( + bus_reset : out std_ulogic; + ghigh_b : out std_ulogic; + done : out std_ulogic; + gsr : out std_ulogic; + gwe : out std_ulogic; + gts_b : out std_ulogic; + + shutdown : in std_ulogic; + cclk : in std_ulogic; + por : in std_ulogic + ); +end fpga_startup_virtex4; + +architecture fpga_startup_virtex4_v of fpga_startup_virtex4 is + signal count_changed : boolean := false; +begin +set_output:process(cclk, por) + variable abus_reset : std_ulogic := '0'; + variable aghigh_b : std_ulogic := '0'; + variable agsr : std_ulogic := '0'; + variable adone : std_ulogic := '0'; + variable agwe : std_ulogic := '0'; + variable agts_b : std_ulogic := '0'; + variable count : integer := 0; + variable count_last_value : integer := 0; + +begin + if (((cclk'event) and (cclk = '1') and (cclk'last_value = '0')) or ((por'event) and (por = '1') and (por'last_value = '0')))then + + count_last_value := count; + if (por = '1') then + count := 0; + elsif ((shutdown ='1') and (count > 0)) then + count := count - 1; + elsif ((shutdown ='0') and (count < 255)) then + count := count + 1; + end if; + if(count_last_value /= count) then + count_changed <= true; + end if; + + + if (por = '1') then + bus_reset <= '0'; + ghigh_b <= '0'; + gsr <= '0'; + done <= '0'; + gwe <= '0'; + gts_b <= '0'; + + else + + bus_reset <= abus_reset; + ghigh_b <= aghigh_b; + gsr <= agsr; + done <= adone; + gwe <= agwe; + gts_b <= agts_b; + + end if; + end if; + if(count_last_value /= count) then + abus_reset := '1'; + aghigh_b := '0'; + agsr := '0'; + adone := '0'; + agwe := '0'; + agts_b := '0'; + if (count >= 02) then + abus_reset := '0'; + end if; + if ((count = 23) or (count = 24)) then + agsr := '1'; + end if; + if (count > 39) then + aghigh_b := '1'; + end if; + if (count > 49) then + adone := '1'; + end if; + + if ((count = 51) or (count = 52)) then + agsr := '1'; + end if; + if (count > 54) then + agwe := '1'; + end if; + if (count > 55) then + agts_b := '1'; + end if; + end if; +end process set_output; + + +end fpga_startup_virtex4_v; + +----- CELL PPC405_ADV ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity PPC405_ADV is +generic ( + in_delay : time := 1 ps; + out_delay : VitalDelayType01 := (100 ps, 100 ps) +-- clk-to-output path delays + ); +port ( + APUFCMDECODED : out std_ulogic; + APUFCMDECUDI : out std_logic_vector(0 to 2); + APUFCMDECUDIVALID : out std_ulogic; + APUFCMENDIAN : out std_ulogic; + APUFCMFLUSH : out std_ulogic; + APUFCMINSTRUCTION : out std_logic_vector(0 to 31); + APUFCMINSTRVALID : out std_ulogic; + APUFCMLOADBYTEEN : out std_logic_vector(0 to 3); + APUFCMLOADDATA : out std_logic_vector(0 to 31); + APUFCMLOADDVALID : out std_ulogic; + APUFCMOPERANDVALID : out std_ulogic; + APUFCMRADATA : out std_logic_vector(0 to 31); + APUFCMRBDATA : out std_logic_vector(0 to 31); + APUFCMWRITEBACKOK : out std_ulogic; + APUFCMXERCA : out std_ulogic; + C405CPMCORESLEEPREQ : out std_ulogic; + C405CPMMSRCE : out std_ulogic; + C405CPMMSREE : out std_ulogic; + C405CPMTIMERIRQ : out std_ulogic; + C405CPMTIMERRESETREQ : out std_ulogic; + C405DBGLOADDATAONAPUDBUS : out std_ulogic; + C405DBGMSRWE : out std_ulogic; + C405DBGSTOPACK : out std_ulogic; + C405DBGWBCOMPLETE : out std_ulogic; + C405DBGWBFULL : out std_ulogic; + C405DBGWBIAR : out std_logic_vector(0 to 29); + C405JTGCAPTUREDR : out std_ulogic; + C405JTGEXTEST : out std_ulogic; + C405JTGPGMOUT : out std_ulogic; + C405JTGSHIFTDR : out std_ulogic; + C405JTGTDO : out std_ulogic; + C405JTGTDOEN : out std_ulogic; + C405JTGUPDATEDR : out std_ulogic; + C405PLBDCUABORT : out std_ulogic; + C405PLBDCUABUS : out std_logic_vector(0 to 31); + C405PLBDCUBE : out std_logic_vector(0 to 7); + C405PLBDCUCACHEABLE : out std_ulogic; + C405PLBDCUGUARDED : out std_ulogic; + C405PLBDCUPRIORITY : out std_logic_vector(0 to 1); + C405PLBDCUREQUEST : out std_ulogic; + C405PLBDCURNW : out std_ulogic; + C405PLBDCUSIZE2 : out std_ulogic; + C405PLBDCUU0ATTR : out std_ulogic; + C405PLBDCUWRDBUS : out std_logic_vector(0 to 63); + C405PLBDCUWRITETHRU : out std_ulogic; + C405PLBICUABORT : out std_ulogic; + C405PLBICUABUS : out std_logic_vector(0 to 29); + C405PLBICUCACHEABLE : out std_ulogic; + C405PLBICUPRIORITY : out std_logic_vector(0 to 1); + C405PLBICUREQUEST : out std_ulogic; + C405PLBICUSIZE : out std_logic_vector(2 to 3); + C405PLBICUU0ATTR : out std_ulogic; + C405RSTCHIPRESETREQ : out std_ulogic; + C405RSTCORERESETREQ : out std_ulogic; + C405RSTSYSRESETREQ : out std_ulogic; + C405TRCCYCLE : out std_ulogic; + C405TRCEVENEXECUTIONSTATUS : out std_logic_vector(0 to 1); + C405TRCODDEXECUTIONSTATUS : out std_logic_vector(0 to 1); + C405TRCTRACESTATUS : out std_logic_vector(0 to 3); + C405TRCTRIGGEREVENTOUT : out std_ulogic; + C405TRCTRIGGEREVENTTYPE : out std_logic_vector(0 to 10); + C405XXXMACHINECHECK : out std_ulogic; + DCREMACABUS : out std_logic_vector(8 to 9); + DCREMACCLK : out std_ulogic; + DCREMACDBUS : out std_logic_vector(0 to 31); + DCREMACENABLER : out std_ulogic; + DCREMACREAD : out std_ulogic; + DCREMACWRITE : out std_ulogic; + DSOCMBRAMABUS : out std_logic_vector(8 to 29); + DSOCMBRAMBYTEWRITE : out std_logic_vector(0 to 3); + DSOCMBRAMEN : out std_ulogic; + DSOCMBRAMWRDBUS : out std_logic_vector(0 to 31); + DSOCMBUSY : out std_ulogic; + DSOCMRDADDRVALID : out std_ulogic; + DSOCMWRADDRVALID : out std_ulogic; + EXTDCRABUS : out std_logic_vector(0 to 9); + EXTDCRDBUSOUT : out std_logic_vector(0 to 31); + EXTDCRREAD : out std_ulogic; + EXTDCRWRITE : out std_ulogic; + ISOCMBRAMEN : out std_ulogic; + ISOCMBRAMEVENWRITEEN : out std_ulogic; + ISOCMBRAMODDWRITEEN : out std_ulogic; + ISOCMBRAMRDABUS : out std_logic_vector(8 to 28); + ISOCMBRAMWRABUS : out std_logic_vector(8 to 28); + ISOCMBRAMWRDBUS : out std_logic_vector(0 to 31); + ISOCMDCRBRAMEVENEN : out std_ulogic; + ISOCMDCRBRAMODDEN : out std_ulogic; + ISOCMDCRBRAMRDSELECT : out std_ulogic; + + BRAMDSOCMCLK : in std_ulogic; + BRAMDSOCMRDDBUS : in std_logic_vector(0 to 31); + BRAMISOCMCLK : in std_ulogic; + BRAMISOCMDCRRDDBUS : in std_logic_vector(0 to 31); + BRAMISOCMRDDBUS : in std_logic_vector(0 to 63); + CPMC405CLOCK : in std_ulogic; + CPMC405CORECLKINACTIVE : in std_ulogic; + CPMC405CPUCLKEN : in std_ulogic; + CPMC405JTAGCLKEN : in std_ulogic; + CPMC405SYNCBYPASS : in std_ulogic; + CPMC405TIMERCLKEN : in std_ulogic; + CPMC405TIMERTICK : in std_ulogic; + CPMDCRCLK : in std_ulogic; + CPMFCMCLK : in std_ulogic; + DBGC405DEBUGHALT : in std_ulogic; + DBGC405EXTBUSHOLDACK : in std_ulogic; + DBGC405UNCONDDEBUGEVENT : in std_ulogic; + DSARCVALUE : in std_logic_vector(0 to 7); + DSCNTLVALUE : in std_logic_vector(0 to 7); + DSOCMRWCOMPLETE : in std_ulogic; + EICC405CRITINPUTIRQ : in std_ulogic; + EICC405EXTINPUTIRQ : in std_ulogic; + EMACDCRACK : in std_ulogic; + EMACDCRDBUS : in std_logic_vector(0 to 31); + EXTDCRACK : in std_ulogic; + EXTDCRDBUSIN : in std_logic_vector(0 to 31); + FCMAPUCR : in std_logic_vector(0 to 3); + FCMAPUDCDCREN : in std_ulogic; + FCMAPUDCDFORCEALIGN : in std_ulogic; + FCMAPUDCDFORCEBESTEERING : in std_ulogic; + FCMAPUDCDFPUOP : in std_ulogic; + FCMAPUDCDGPRWRITE : in std_ulogic; + FCMAPUDCDLDSTBYTE : in std_ulogic; + FCMAPUDCDLDSTDW : in std_ulogic; + FCMAPUDCDLDSTHW : in std_ulogic; + FCMAPUDCDLDSTQW : in std_ulogic; + FCMAPUDCDLDSTWD : in std_ulogic; + FCMAPUDCDLOAD : in std_ulogic; + FCMAPUDCDPRIVOP : in std_ulogic; + FCMAPUDCDRAEN : in std_ulogic; + FCMAPUDCDRBEN : in std_ulogic; + FCMAPUDCDSTORE : in std_ulogic; + FCMAPUDCDTRAPBE : in std_ulogic; + FCMAPUDCDTRAPLE : in std_ulogic; + FCMAPUDCDUPDATE : in std_ulogic; + FCMAPUDCDXERCAEN : in std_ulogic; + FCMAPUDCDXEROVEN : in std_ulogic; + FCMAPUDECODEBUSY : in std_ulogic; + FCMAPUDONE : in std_ulogic; + FCMAPUEXCEPTION : in std_ulogic; + FCMAPUEXEBLOCKINGMCO : in std_ulogic; + FCMAPUEXECRFIELD : in std_logic_vector(0 to 2); + FCMAPUEXENONBLOCKINGMCO : in std_ulogic; + FCMAPUINSTRACK : in std_ulogic; + FCMAPULOADWAIT : in std_ulogic; + FCMAPURESULT : in std_logic_vector(0 to 31); + FCMAPURESULTVALID : in std_ulogic; + FCMAPUSLEEPNOTREADY : in std_ulogic; + FCMAPUXERCA : in std_ulogic; + FCMAPUXEROV : in std_ulogic; + ISARCVALUE : in std_logic_vector(0 to 7); + ISCNTLVALUE : in std_logic_vector(0 to 7); + JTGC405BNDSCANTDO : in std_ulogic; + JTGC405TCK : in std_ulogic; + JTGC405TDI : in std_ulogic; + JTGC405TMS : in std_ulogic; + JTGC405TRSTNEG : in std_ulogic; + MCBCPUCLKEN : in std_ulogic; + MCBJTAGEN : in std_ulogic; + MCBTIMEREN : in std_ulogic; + MCPPCRST : in std_ulogic; + PLBC405DCUADDRACK : in std_ulogic; + PLBC405DCUBUSY : in std_ulogic; + PLBC405DCUERR : in std_ulogic; + PLBC405DCURDDACK : in std_ulogic; + PLBC405DCURDDBUS : in std_logic_vector(0 to 63); + PLBC405DCURDWDADDR : in std_logic_vector(1 to 3); + PLBC405DCUSSIZE1 : in std_ulogic; + PLBC405DCUWRDACK : in std_ulogic; + PLBC405ICUADDRACK : in std_ulogic; + PLBC405ICUBUSY : in std_ulogic; + PLBC405ICUERR : in std_ulogic; + PLBC405ICURDDACK : in std_ulogic; + PLBC405ICURDDBUS : in std_logic_vector(0 to 63); + PLBC405ICURDWDADDR : in std_logic_vector(1 to 3); + PLBC405ICUSSIZE1 : in std_ulogic; + PLBCLK : in std_ulogic; + RSTC405RESETCHIP : in std_ulogic; + RSTC405RESETCORE : in std_ulogic; + RSTC405RESETSYS : in std_ulogic; + TIEAPUCONTROL : in std_logic_vector(0 to 15); + TIEAPUUDI1 : in std_logic_vector(0 to 23); + TIEAPUUDI2 : in std_logic_vector(0 to 23); + TIEAPUUDI3 : in std_logic_vector(0 to 23); + TIEAPUUDI4 : in std_logic_vector(0 to 23); + TIEAPUUDI5 : in std_logic_vector(0 to 23); + TIEAPUUDI6 : in std_logic_vector(0 to 23); + TIEAPUUDI7 : in std_logic_vector(0 to 23); + TIEAPUUDI8 : in std_logic_vector(0 to 23); + TIEC405DETERMINISTICMULT : in std_ulogic; + TIEC405DISOPERANDFWD : in std_ulogic; + TIEC405MMUEN : in std_ulogic; + TIEDCRADDR : in std_logic_vector(0 to 5); + TIEPVRBIT10 : in std_ulogic; + TIEPVRBIT11 : in std_ulogic; + TIEPVRBIT28 : in std_ulogic; + TIEPVRBIT29 : in std_ulogic; + TIEPVRBIT30 : in std_ulogic; + TIEPVRBIT31 : in std_ulogic; + TIEPVRBIT8 : in std_ulogic; + TIEPVRBIT9 : in std_ulogic; + TRCC405TRACEDISABLE : in std_ulogic; + TRCC405TRIGGEREVENTIN : in std_ulogic + ); +end PPC405_ADV; + +architecture PPC405_ADV_V of PPC405_ADV is + component PPC405_ADV_SWIFT_BUS + port ( CFG_MCLK : in std_logic; + BUS_RESET : in std_logic; + GSR : in std_logic; + GWE : in std_logic; + GHIGHB : in std_logic; + CPMC405CPUCLKEN : in std_logic; + CPMC405JTAGCLKEN : in std_logic; + CPMC405TIMERCLKEN : in std_logic; + C405JTGPGMOUT : out std_logic; + MCBCPUCLKEN : in std_logic; + MCBJTAGEN : in std_logic; + MCBTIMEREN : in std_logic; + MCPPCRST : in std_logic; + C405TRCODDEXECUTIONSTATUS : out std_logic_vector(0 to 1); + C405TRCEVENEXECUTIONSTATUS : out std_logic_vector(0 to 1); + CPMC405CLOCK : in std_logic; + CPMC405CORECLKINACTIVE : in std_logic; + PLBCLK : in std_logic; + CPMFCMCLK : in std_logic; + CPMDCRCLK : in std_logic; + CPMC405SYNCBYPASS : in std_logic; + CPMC405TIMERTICK : in std_logic; + C405CPMMSREE : out std_logic; + C405CPMMSRCE : out std_logic; + C405CPMTIMERIRQ : out std_logic; + C405CPMTIMERRESETREQ : out std_logic; + C405CPMCORESLEEPREQ : out std_logic; + TIEC405DISOPERANDFWD : in std_logic; + TIEC405DETERMINISTICMULT : in std_logic; + TIEC405MMUEN : in std_logic; + TIEPVRBIT8 : in std_logic; + TIEPVRBIT9 : in std_logic; + TIEPVRBIT10 : in std_logic; + TIEPVRBIT11 : in std_logic; + TIEPVRBIT28 : in std_logic; + TIEPVRBIT29 : in std_logic; + TIEPVRBIT30 : in std_logic; + TIEPVRBIT31 : in std_logic; + C405XXXMACHINECHECK : out std_logic; + DCREMACENABLER : out std_logic; + DCREMACCLK : out std_logic; + DCREMACWRITE : out std_logic; + DCREMACREAD : out std_logic; + DCREMACDBUS : out std_logic_vector(0 to 31); + DCREMACABUS : out std_logic_vector(8 to 9); + EMACDCRDBUS : in std_logic_vector(0 to 31); + EMACDCRACK : in std_logic; + C405RSTCHIPRESETREQ : out std_logic; + C405RSTCORERESETREQ : out std_logic; + C405RSTSYSRESETREQ : out std_logic; + RSTC405RESETCHIP : in std_logic; + RSTC405RESETCORE : in std_logic; + RSTC405RESETSYS : in std_logic; + C405PLBICUREQUEST : out std_logic; + C405PLBICUPRIORITY : out std_logic_vector(0 to 1); + C405PLBICUCACHEABLE : out std_logic; + C405PLBICUABUS : out std_logic_vector(0 to 29); + C405PLBICUSIZE : out std_logic_vector(2 to 3); + C405PLBICUABORT : out std_logic; + C405PLBICUU0ATTR : out std_logic; + PLBC405ICUADDRACK : in std_logic; + PLBC405ICUBUSY : in std_logic; + PLBC405ICUERR : in std_logic; + PLBC405ICURDDACK : in std_logic; + PLBC405ICURDDBUS :in std_logic_vector(0 to 63); + PLBC405ICUSSIZE1 : in std_logic; + PLBC405ICURDWDADDR : in std_logic_vector(1 to 3); + C405PLBDCUREQUEST : out std_logic; + C405PLBDCURNW : out std_logic; + C405PLBDCUABUS : out std_logic_vector(0 to 31); + C405PLBDCUBE : out std_logic_vector(0 to 7); + C405PLBDCUCACHEABLE : out std_logic; + C405PLBDCUGUARDED : out std_logic; + C405PLBDCUPRIORITY : out std_logic_vector(0 to 1); + C405PLBDCUSIZE2 : out std_logic; + C405PLBDCUABORT : out std_logic; + C405PLBDCUWRDBUS : out std_logic_vector(0 to 63); + C405PLBDCUU0ATTR : out std_logic; + C405PLBDCUWRITETHRU : out std_logic; + PLBC405DCUADDRACK : in std_logic; + PLBC405DCUBUSY : in std_logic; + PLBC405DCUERR : in std_logic; + PLBC405DCURDDACK : in std_logic; + PLBC405DCURDDBUS : in std_logic_vector(0 to 63); + PLBC405DCURDWDADDR : in std_logic_vector(1 to 3); + PLBC405DCUSSIZE1 : in std_logic; + PLBC405DCUWRDACK : in std_logic; + ISOCMBRAMRDABUS : out std_logic_vector(8 to 28); + ISOCMBRAMWRABUS : out std_logic_vector(8 to 28); + ISOCMBRAMEN : out std_logic; + ISOCMBRAMODDWRITEEN : out std_logic; + ISOCMBRAMEVENWRITEEN : out std_logic; + ISOCMBRAMWRDBUS : out std_logic_vector(0 to 31); + ISOCMDCRBRAMEVENEN : out std_logic; + ISOCMDCRBRAMODDEN : out std_logic; + ISOCMDCRBRAMRDSELECT : out std_logic; + BRAMISOCMDCRRDDBUS : in std_logic_vector(0 to 31); + BRAMISOCMRDDBUS : in std_logic_vector(0 to 63); + ISARCVALUE : in std_logic_vector(0 to 7); + ISCNTLVALUE : in std_logic_vector(0 to 7); + BRAMISOCMCLK : in std_logic; + DSOCMBRAMABUS : out std_logic_vector(8 to 29); + DSOCMBRAMBYTEWRITE : out std_logic_vector(0 to 3); + DSOCMBRAMEN : out std_logic; + DSOCMBRAMWRDBUS : out std_logic_vector(0 to 31); + BRAMDSOCMRDDBUS : in std_logic_vector(0 to 31); + DSOCMRWCOMPLETE : in std_logic; + DSOCMBUSY : out std_logic; + DSOCMWRADDRVALID : out std_logic; + DSOCMRDADDRVALID : out std_logic; + TIEDCRADDR : in std_logic_vector(0 to 5); + DSARCVALUE : in std_logic_vector(0 to 7); + DSCNTLVALUE : in std_logic_vector(0 to 7); + BRAMDSOCMCLK : in std_logic; + EXTDCRREAD : out std_logic; + EXTDCRWRITE : out std_logic; + EXTDCRABUS : out std_logic_vector(0 to 9); + EXTDCRDBUSOUT : out std_logic_vector(0 to 31); + EXTDCRACK : in std_logic; + EXTDCRDBUSIN : in std_logic_vector(0 to 31); + EICC405EXTINPUTIRQ : in std_logic; + EICC405CRITINPUTIRQ : in std_logic; + JTGC405BNDSCANTDO : in std_logic; + JTGC405TCK : in std_logic; + JTGC405TDI : in std_logic; + JTGC405TMS : in std_logic; + JTGC405TRSTNEG : in std_logic; + C405JTGTDO : out std_logic; + C405JTGTDOEN : out std_logic; + C405JTGEXTEST : out std_logic; + C405JTGCAPTUREDR : out std_logic; + C405JTGSHIFTDR : out std_logic; + C405JTGUPDATEDR : out std_logic; + DBGC405DEBUGHALT : in std_logic; + DBGC405UNCONDDEBUGEVENT : in std_logic; + DBGC405EXTBUSHOLDACK : in std_logic; + C405DBGMSRWE : out std_logic; + C405DBGSTOPACK : out std_logic; + C405DBGWBCOMPLETE : out std_logic; + C405DBGWBFULL : out std_logic; + C405DBGWBIAR : out std_logic_vector(0 to 29); + C405TRCTRIGGEREVENTOUT : out std_logic; + C405TRCTRIGGEREVENTTYPE : out std_logic_vector(0 to 10); + C405TRCCYCLE : out std_logic; + C405TRCTRACESTATUS : out std_logic_vector(0 to 3); + TRCC405TRACEDISABLE : in std_logic; + TRCC405TRIGGEREVENTIN : in std_logic; + C405DBGLOADDATAONAPUDBUS : out std_logic; + APUFCMINSTRUCTION : out std_logic_vector(0 to 31); + APUFCMRADATA : out std_logic_vector(0 to 31); + APUFCMRBDATA : out std_logic_vector(0 to 31); + APUFCMINSTRVALID : out std_logic; + APUFCMLOADDATA : out std_logic_vector(0 to 31); + APUFCMOPERANDVALID : out std_logic; + APUFCMLOADDVALID : out std_logic; + APUFCMFLUSH : out std_logic; + APUFCMWRITEBACKOK : out std_logic; + APUFCMLOADBYTEEN : out std_logic_vector(0 to 3); + APUFCMENDIAN : out std_logic; + APUFCMXERCA : out std_logic; + APUFCMDECODED : out std_logic; + APUFCMDECUDI : out std_logic_vector(0 to 2); + APUFCMDECUDIVALID : out std_logic; + FCMAPUDONE : in std_logic; + FCMAPURESULT : in std_logic_vector(0 to 31); + FCMAPURESULTVALID : in std_logic; + FCMAPUINSTRACK : in std_logic; + FCMAPUEXCEPTION : in std_logic; + FCMAPUXERCA : in std_logic; + FCMAPUXEROV : in std_logic; + FCMAPUCR : in std_logic_vector(0 to 3); + FCMAPUDCDFPUOP : in std_logic; + FCMAPUDCDGPRWRITE : in std_logic; + FCMAPUDCDRAEN : in std_logic; + FCMAPUDCDRBEN : in std_logic; + FCMAPUDCDLOAD : in std_logic; + FCMAPUDCDSTORE : in std_logic; + FCMAPUDCDXERCAEN : in std_logic; + FCMAPUDCDXEROVEN : in std_logic; + FCMAPUDCDPRIVOP : in std_logic; + FCMAPUDCDCREN : in std_logic; + FCMAPUEXECRFIELD : in std_logic_vector(0 to 2); + FCMAPUDCDUPDATE : in std_logic; + FCMAPUDCDFORCEALIGN : in std_logic; + FCMAPUDCDFORCEBESTEERING : in std_logic; + FCMAPUDCDLDSTBYTE : in std_logic; + FCMAPUDCDLDSTHW : in std_logic; + FCMAPUDCDLDSTWD : in std_logic; + FCMAPUDCDLDSTDW : in std_logic; + FCMAPUDCDLDSTQW : in std_logic; + FCMAPUDCDTRAPBE : in std_logic; + FCMAPUDCDTRAPLE : in std_logic; + FCMAPUEXEBLOCKINGMCO : in std_logic; + FCMAPUEXENONBLOCKINGMCO : in std_logic; + FCMAPUSLEEPNOTREADY : in std_logic; + FCMAPULOADWAIT : in std_logic; + FCMAPUDECODEBUSY : in std_logic; + TIEAPUCONTROL : in std_logic_vector(0 to 15); + TIEAPUUDI1 : in std_logic_vector(0 to 23); + TIEAPUUDI2 : in std_logic_vector(0 to 23); + TIEAPUUDI3 : in std_logic_vector(0 to 23); + TIEAPUUDI4 : in std_logic_vector(0 to 23); + TIEAPUUDI5 : in std_logic_vector(0 to 23); + TIEAPUUDI6 : in std_logic_vector(0 to 23); + TIEAPUUDI7 : in std_logic_vector(0 to 23); + TIEAPUUDI8 : in std_logic_vector(0 to 23) + ); + end component; +----- component fpga_startup_virtex4 ----- +component fpga_startup_virtex4 + port ( + bus_reset : out std_ulogic; + done : out std_ulogic; + ghigh_b : out std_ulogic; + gsr : out std_ulogic; + gts_b : out std_ulogic; + gwe : out std_ulogic; + + cclk : in std_ulogic; + por : in std_ulogic; + shutdown : in std_ulogic + ); +end component; + + + + signal APUFCMDECODED_out : std_ulogic; + signal APUFCMDECUDI_out : std_logic_vector(0 to 2); + signal APUFCMDECUDIVALID_out : std_ulogic; + signal APUFCMENDIAN_out : std_ulogic; + signal APUFCMFLUSH_out : std_ulogic; + signal APUFCMINSTRUCTION_out : std_logic_vector(0 to 31); + signal APUFCMINSTRVALID_out : std_ulogic; + signal APUFCMLOADBYTEEN_out : std_logic_vector(0 to 3); + signal APUFCMLOADDATA_out : std_logic_vector(0 to 31); + signal APUFCMLOADDVALID_out : std_ulogic; + signal APUFCMOPERANDVALID_out : std_ulogic; + signal APUFCMRADATA_out : std_logic_vector(0 to 31); + signal APUFCMRBDATA_out : std_logic_vector(0 to 31); + signal APUFCMWRITEBACKOK_out : std_ulogic; + signal APUFCMXERCA_out : std_ulogic; + signal C405CPMCORESLEEPREQ_out : std_ulogic; + signal C405CPMMSRCE_out : std_ulogic; + signal C405CPMMSREE_out : std_ulogic; + signal C405CPMTIMERIRQ_out : std_ulogic; + signal C405CPMTIMERRESETREQ_out : std_ulogic; + signal C405DBGLOADDATAONAPUDBUS_out : std_ulogic; + signal C405DBGMSRWE_out : std_ulogic; + signal C405DBGSTOPACK_out : std_ulogic; + signal C405DBGWBCOMPLETE_out : std_ulogic; + signal C405DBGWBFULL_out : std_ulogic; + signal C405DBGWBIAR_out : std_logic_vector(0 to 29); + signal C405JTGCAPTUREDR_out : std_ulogic; + signal C405JTGEXTEST_out : std_ulogic; + signal C405JTGPGMOUT_out : std_ulogic; + signal C405JTGSHIFTDR_out : std_ulogic; + signal C405JTGTDO_out : std_ulogic; + signal C405JTGTDOEN_out : std_ulogic; + signal C405JTGUPDATEDR_out : std_ulogic; + signal C405PLBDCUABORT_out : std_ulogic; + signal C405PLBDCUABUS_out : std_logic_vector(0 to 31); + signal C405PLBDCUBE_out : std_logic_vector(0 to 7); + signal C405PLBDCUCACHEABLE_out : std_ulogic; + signal C405PLBDCUGUARDED_out : std_ulogic; + signal C405PLBDCUPRIORITY_out : std_logic_vector(0 to 1); + signal C405PLBDCUREQUEST_out : std_ulogic; + signal C405PLBDCURNW_out : std_ulogic; + signal C405PLBDCUSIZE2_out : std_ulogic; + signal C405PLBDCUU0ATTR_out : std_ulogic; + signal C405PLBDCUWRDBUS_out : std_logic_vector(0 to 63); + signal C405PLBDCUWRITETHRU_out : std_ulogic; + signal C405PLBICUABORT_out : std_ulogic; + signal C405PLBICUABUS_out : std_logic_vector(0 to 29); + signal C405PLBICUCACHEABLE_out : std_ulogic; + signal C405PLBICUPRIORITY_out : std_logic_vector(0 to 1); + signal C405PLBICUREQUEST_out : std_ulogic; + signal C405PLBICUSIZE_out : std_logic_vector(2 to 3); + signal C405PLBICUU0ATTR_out : std_ulogic; + signal C405RSTCHIPRESETREQ_out : std_ulogic; + signal C405RSTCORERESETREQ_out : std_ulogic; + signal C405RSTSYSRESETREQ_out : std_ulogic; + signal C405TRCCYCLE_out : std_ulogic; + signal C405TRCEVENEXECUTIONSTATUS_out : std_logic_vector(0 to 1); + signal C405TRCODDEXECUTIONSTATUS_out : std_logic_vector(0 to 1); + signal C405TRCTRACESTATUS_out : std_logic_vector(0 to 3); + signal C405TRCTRIGGEREVENTOUT_out : std_ulogic; + signal C405TRCTRIGGEREVENTTYPE_out : std_logic_vector(0 to 10); + signal C405XXXMACHINECHECK_out : std_ulogic; + signal DCREMACENABLER_out : std_ulogic; + signal DSOCMBRAMABUS_out : std_logic_vector(8 to 29); + signal DSOCMBRAMBYTEWRITE_out : std_logic_vector(0 to 3); + signal DSOCMBRAMEN_out : std_ulogic; + signal DSOCMBRAMWRDBUS_out : std_logic_vector(0 to 31); + signal DSOCMBUSY_out : std_ulogic; + signal DSOCMRDADDRVALID_out : std_ulogic; + signal DSOCMWRADDRVALID_out : std_ulogic; + signal EXTDCRABUS_out : std_logic_vector(0 to 9); + signal EXTDCRDBUSOUT_out : std_logic_vector(0 to 31); + signal EXTDCRREAD_out : std_ulogic; + signal EXTDCRWRITE_out : std_ulogic; + signal ISOCMBRAMEN_out : std_ulogic; + signal ISOCMBRAMEVENWRITEEN_out : std_ulogic; + signal ISOCMBRAMODDWRITEEN_out : std_ulogic; + signal ISOCMBRAMRDABUS_out : std_logic_vector(8 to 28); + signal ISOCMBRAMWRABUS_out : std_logic_vector(8 to 28); + signal ISOCMBRAMWRDBUS_out : std_logic_vector(0 to 31); + signal ISOCMDCRBRAMEVENEN_out : std_ulogic; + signal ISOCMDCRBRAMODDEN_out : std_ulogic; + signal ISOCMDCRBRAMRDSELECT_out : std_ulogic; + signal DCREMACWRITE_out : std_ulogic; + signal DCREMACREAD_out : std_ulogic; + signal DCREMACDBUS_out : std_logic_vector(0 to 31); + signal DCREMACABUS_out : std_logic_vector(8 to 9); + signal DCREMACCLK_out : std_ulogic; + + signal GSR_ipd : std_ulogic; + signal BRAMDSOCMCLK_ipd : std_ulogic; + signal BRAMDSOCMRDDBUS_ipd : std_logic_vector(0 to 31); + signal BRAMISOCMCLK_ipd : std_ulogic; + signal BRAMISOCMDCRRDDBUS_ipd : std_logic_vector(0 to 31); + signal BRAMISOCMRDDBUS_ipd : std_logic_vector(0 to 63); + signal CPMC405CLOCK_ipd : std_ulogic; + signal CPMC405CORECLKINACTIVE_ipd : std_ulogic; + signal CPMC405CPUCLKEN_ipd : std_ulogic; + signal CPMC405JTAGCLKEN_ipd : std_ulogic; + signal CPMC405SYNCBYPASS_ipd : std_ulogic; + signal CPMC405TIMERCLKEN_ipd : std_ulogic; + signal CPMC405TIMERTICK_ipd : std_ulogic; + signal CPMDCRCLK_ipd : std_ulogic; + signal CPMFCMCLK_ipd : std_ulogic; + signal DBGC405DEBUGHALT_ipd : std_ulogic; + signal DBGC405EXTBUSHOLDACK_ipd : std_ulogic; + signal DBGC405UNCONDDEBUGEVENT_ipd : std_ulogic; + signal DSARCVALUE_ipd : std_logic_vector(0 to 7); + signal DSCNTLVALUE_ipd : std_logic_vector(0 to 7); + signal DSOCMRWCOMPLETE_ipd : std_ulogic; + signal EICC405CRITINPUTIRQ_ipd : std_ulogic; + signal EICC405EXTINPUTIRQ_ipd : std_ulogic; + signal EXTDCRACK_ipd : std_ulogic; + signal EXTDCRDBUSIN_ipd : std_logic_vector(0 to 31); + signal FCMAPUCR_ipd : std_logic_vector(0 to 3); + signal FCMAPUDCDCREN_ipd : std_ulogic; + signal FCMAPUDCDFORCEALIGN_ipd : std_ulogic; + signal FCMAPUDCDFORCEBESTEERING_ipd : std_ulogic; + signal FCMAPUDCDFPUOP_ipd : std_ulogic; + signal FCMAPUDCDGPRWRITE_ipd : std_ulogic; + signal FCMAPUDCDLDSTBYTE_ipd : std_ulogic; + signal FCMAPUDCDLDSTDW_ipd : std_ulogic; + signal FCMAPUDCDLDSTHW_ipd : std_ulogic; + signal FCMAPUDCDLDSTQW_ipd : std_ulogic; + signal FCMAPUDCDLDSTWD_ipd : std_ulogic; + signal FCMAPUDCDLOAD_ipd : std_ulogic; + signal FCMAPUDCDPRIVOP_ipd : std_ulogic; + signal FCMAPUDCDRAEN_ipd : std_ulogic; + signal FCMAPUDCDRBEN_ipd : std_ulogic; + signal FCMAPUDCDSTORE_ipd : std_ulogic; + signal FCMAPUDCDTRAPBE_ipd : std_ulogic; + signal FCMAPUDCDTRAPLE_ipd : std_ulogic; + signal FCMAPUDCDUPDATE_ipd : std_ulogic; + signal FCMAPUDCDXERCAEN_ipd : std_ulogic; + signal FCMAPUDCDXEROVEN_ipd : std_ulogic; + signal FCMAPUDECODEBUSY_ipd : std_ulogic; + signal FCMAPUDONE_ipd : std_ulogic; + signal FCMAPUEXCEPTION_ipd : std_ulogic; + signal FCMAPUEXEBLOCKINGMCO_ipd : std_ulogic; + signal FCMAPUEXECRFIELD_ipd : std_logic_vector(0 to 2); + signal FCMAPUEXENONBLOCKINGMCO_ipd : std_ulogic; + signal FCMAPUINSTRACK_ipd : std_ulogic; + signal FCMAPULOADWAIT_ipd : std_ulogic; + signal FCMAPURESULT_ipd : std_logic_vector(0 to 31); + signal FCMAPURESULTVALID_ipd : std_ulogic; + signal FCMAPUSLEEPNOTREADY_ipd : std_ulogic; + signal FCMAPUXERCA_ipd : std_ulogic; + signal FCMAPUXEROV_ipd : std_ulogic; + signal ISARCVALUE_ipd : std_logic_vector(0 to 7); + signal ISCNTLVALUE_ipd : std_logic_vector(0 to 7); + signal JTGC405BNDSCANTDO_ipd : std_ulogic; + signal JTGC405TCK_ipd : std_ulogic; + signal JTGC405TDI_ipd : std_ulogic; + signal JTGC405TMS_ipd : std_ulogic; + signal JTGC405TRSTNEG_ipd : std_ulogic; + signal MCBCPUCLKEN_ipd : std_ulogic; + signal MCBJTAGEN_ipd : std_ulogic; + signal MCBTIMEREN_ipd : std_ulogic; + signal MCPPCRST_ipd : std_ulogic; + signal PLBC405DCUADDRACK_ipd : std_ulogic; + signal PLBC405DCUBUSY_ipd : std_ulogic; + signal PLBC405DCUERR_ipd : std_ulogic; + signal PLBC405DCURDDACK_ipd : std_ulogic; + signal PLBC405DCURDDBUS_ipd : std_logic_vector(0 to 63); + signal PLBC405DCURDWDADDR_ipd : std_logic_vector(1 to 3); + signal PLBC405DCUSSIZE1_ipd : std_ulogic; + signal PLBC405DCUWRDACK_ipd : std_ulogic; + signal PLBC405ICUADDRACK_ipd : std_ulogic; + signal PLBC405ICUBUSY_ipd : std_ulogic; + signal PLBC405ICUERR_ipd : std_ulogic; + signal PLBC405ICURDDACK_ipd : std_ulogic; + signal PLBC405ICURDDBUS_ipd : std_logic_vector(0 to 63); + signal PLBC405ICURDWDADDR_ipd : std_logic_vector(1 to 3); + signal PLBC405ICUSSIZE1_ipd : std_ulogic; + signal PLBCLK_ipd : std_ulogic; + signal RSTC405RESETCHIP_ipd : std_ulogic; + signal RSTC405RESETCORE_ipd : std_ulogic; + signal RSTC405RESETSYS_ipd : std_ulogic; + signal TIEAPUCONTROL_ipd : std_logic_vector(0 to 15); + signal TIEAPUUDI1_ipd : std_logic_vector(0 to 23); + signal TIEAPUUDI2_ipd : std_logic_vector(0 to 23); + signal TIEAPUUDI3_ipd : std_logic_vector(0 to 23); + signal TIEAPUUDI4_ipd : std_logic_vector(0 to 23); + signal TIEAPUUDI5_ipd : std_logic_vector(0 to 23); + signal TIEAPUUDI6_ipd : std_logic_vector(0 to 23); + signal TIEAPUUDI7_ipd : std_logic_vector(0 to 23); + signal TIEAPUUDI8_ipd : std_logic_vector(0 to 23); + signal TIEC405DETERMINISTICMULT_ipd : std_ulogic; + signal TIEC405DISOPERANDFWD_ipd : std_ulogic; + signal TIEC405MMUEN_ipd : std_ulogic; + signal TIEDCRADDR_ipd : std_logic_vector(0 to 5); + signal TIEPVRBIT10_ipd : std_ulogic; + signal TIEPVRBIT11_ipd : std_ulogic; + signal TIEPVRBIT28_ipd : std_ulogic; + signal TIEPVRBIT29_ipd : std_ulogic; + signal TIEPVRBIT30_ipd : std_ulogic; + signal TIEPVRBIT31_ipd : std_ulogic; + signal TIEPVRBIT8_ipd : std_ulogic; + signal TIEPVRBIT9_ipd : std_ulogic; + signal TRCC405TRACEDISABLE_ipd : std_ulogic; + signal TRCC405TRIGGEREVENTIN_ipd : std_ulogic; + signal EMACDCRDBUS_ipd : std_logic_vector(0 to 31); + signal EMACDCRACK_ipd : std_ulogic; + + signal GSR_ipd_1 : std_ulogic; + signal BRAMDSOCMCLK_ipd_1 : std_ulogic; + signal BRAMDSOCMRDDBUS_ipd_1 : std_logic_vector(0 to 31); + signal BRAMISOCMCLK_ipd_1 : std_ulogic; + signal BRAMISOCMDCRRDDBUS_ipd_1 : std_logic_vector(0 to 31); + signal BRAMISOCMRDDBUS_ipd_1 : std_logic_vector(0 to 63); + signal CPMC405CLOCK_ipd_1 : std_ulogic; + signal CPMC405CORECLKINACTIVE_ipd_1 : std_ulogic; + signal CPMC405CPUCLKEN_ipd_1 : std_ulogic; + signal CPMC405JTAGCLKEN_ipd_1 : std_ulogic; + signal CPMC405SYNCBYPASS_ipd_1 : std_ulogic; + signal CPMC405TIMERCLKEN_ipd_1 : std_ulogic; + signal CPMC405TIMERTICK_ipd_1 : std_ulogic; + signal CPMDCRCLK_ipd_1 : std_ulogic; + signal CPMFCMCLK_ipd_1 : std_ulogic; + signal DBGC405DEBUGHALT_ipd_1 : std_ulogic; + signal DBGC405EXTBUSHOLDACK_ipd_1 : std_ulogic; + signal DBGC405UNCONDDEBUGEVENT_ipd_1 : std_ulogic; + signal DSARCVALUE_ipd_1 : std_logic_vector(0 to 7); + signal DSCNTLVALUE_ipd_1 : std_logic_vector(0 to 7); + signal DSOCMRWCOMPLETE_ipd_1 : std_ulogic; + signal EICC405CRITINPUTIRQ_ipd_1 : std_ulogic; + signal EICC405EXTINPUTIRQ_ipd_1 : std_ulogic; + signal EXTDCRACK_ipd_1 : std_ulogic; + signal EXTDCRDBUSIN_ipd_1 : std_logic_vector(0 to 31); + signal FCMAPUCR_ipd_1 : std_logic_vector(0 to 3); + signal FCMAPUDCDCREN_ipd_1 : std_ulogic; + signal FCMAPUDCDFORCEALIGN_ipd_1 : std_ulogic; + signal FCMAPUDCDFORCEBESTEERING_ipd_1 : std_ulogic; + signal FCMAPUDCDFPUOP_ipd_1 : std_ulogic; + signal FCMAPUDCDGPRWRITE_ipd_1 : std_ulogic; + signal FCMAPUDCDLDSTBYTE_ipd_1 : std_ulogic; + signal FCMAPUDCDLDSTDW_ipd_1 : std_ulogic; + signal FCMAPUDCDLDSTHW_ipd_1 : std_ulogic; + signal FCMAPUDCDLDSTQW_ipd_1 : std_ulogic; + signal FCMAPUDCDLDSTWD_ipd_1 : std_ulogic; + signal FCMAPUDCDLOAD_ipd_1 : std_ulogic; + signal FCMAPUDCDPRIVOP_ipd_1 : std_ulogic; + signal FCMAPUDCDRAEN_ipd_1 : std_ulogic; + signal FCMAPUDCDRBEN_ipd_1 : std_ulogic; + signal FCMAPUDCDSTORE_ipd_1 : std_ulogic; + signal FCMAPUDCDTRAPBE_ipd_1 : std_ulogic; + signal FCMAPUDCDTRAPLE_ipd_1 : std_ulogic; + signal FCMAPUDCDUPDATE_ipd_1 : std_ulogic; + signal FCMAPUDCDXERCAEN_ipd_1 : std_ulogic; + signal FCMAPUDCDXEROVEN_ipd_1 : std_ulogic; + signal FCMAPUDECODEBUSY_ipd_1 : std_ulogic; + signal FCMAPUDONE_ipd_1 : std_ulogic; + signal FCMAPUEXCEPTION_ipd_1 : std_ulogic; + signal FCMAPUEXEBLOCKINGMCO_ipd_1 : std_ulogic; + signal FCMAPUEXECRFIELD_ipd_1 : std_logic_vector(0 to 2); + signal FCMAPUEXENONBLOCKINGMCO_ipd_1 : std_ulogic; + signal FCMAPUINSTRACK_ipd_1 : std_ulogic; + signal FCMAPULOADWAIT_ipd_1 : std_ulogic; + signal FCMAPURESULT_ipd_1 : std_logic_vector(0 to 31); + signal FCMAPURESULTVALID_ipd_1 : std_ulogic; + signal FCMAPUSLEEPNOTREADY_ipd_1 : std_ulogic; + signal FCMAPUXERCA_ipd_1 : std_ulogic; + signal FCMAPUXEROV_ipd_1 : std_ulogic; + signal ISARCVALUE_ipd_1 : std_logic_vector(0 to 7); + signal ISCNTLVALUE_ipd_1 : std_logic_vector(0 to 7); + signal JTGC405BNDSCANTDO_ipd_1 : std_ulogic; + signal JTGC405TCK_ipd_1 : std_ulogic; + signal JTGC405TDI_ipd_1 : std_ulogic; + signal JTGC405TMS_ipd_1 : std_ulogic; + signal JTGC405TRSTNEG_ipd_1 : std_ulogic; + signal MCBCPUCLKEN_ipd_1 : std_ulogic; + signal MCBJTAGEN_ipd_1 : std_ulogic; + signal MCBTIMEREN_ipd_1 : std_ulogic; + signal MCPPCRST_ipd_1 : std_ulogic; + signal PLBC405DCUADDRACK_ipd_1 : std_ulogic; + signal PLBC405DCUBUSY_ipd_1 : std_ulogic; + signal PLBC405DCUERR_ipd_1 : std_ulogic; + signal PLBC405DCURDDACK_ipd_1 : std_ulogic; + signal PLBC405DCURDDBUS_ipd_1 : std_logic_vector(0 to 63); + signal PLBC405DCURDWDADDR_ipd_1 : std_logic_vector(1 to 3); + signal PLBC405DCUSSIZE1_ipd_1 : std_ulogic; + signal PLBC405DCUWRDACK_ipd_1 : std_ulogic; + signal PLBC405ICUADDRACK_ipd_1 : std_ulogic; + signal PLBC405ICUBUSY_ipd_1 : std_ulogic; + signal PLBC405ICUERR_ipd_1 : std_ulogic; + signal PLBC405ICURDDACK_ipd_1 : std_ulogic; + signal PLBC405ICURDDBUS_ipd_1 : std_logic_vector(0 to 63); + signal PLBC405ICURDWDADDR_ipd_1 : std_logic_vector(1 to 3); + signal PLBC405ICUSSIZE1_ipd_1 : std_ulogic; + signal PLBCLK_ipd_1 : std_ulogic; + signal RSTC405RESETCHIP_ipd_1 : std_ulogic; + signal RSTC405RESETCORE_ipd_1 : std_ulogic; + signal RSTC405RESETSYS_ipd_1 : std_ulogic; + signal TIEAPUCONTROL_ipd_1 : std_logic_vector(0 to 15); + signal TIEAPUUDI1_ipd_1 : std_logic_vector(0 to 23); + signal TIEAPUUDI2_ipd_1 : std_logic_vector(0 to 23); + signal TIEAPUUDI3_ipd_1 : std_logic_vector(0 to 23); + signal TIEAPUUDI4_ipd_1 : std_logic_vector(0 to 23); + signal TIEAPUUDI5_ipd_1 : std_logic_vector(0 to 23); + signal TIEAPUUDI6_ipd_1 : std_logic_vector(0 to 23); + signal TIEAPUUDI7_ipd_1 : std_logic_vector(0 to 23); + signal TIEAPUUDI8_ipd_1 : std_logic_vector(0 to 23); + signal TIEC405DETERMINISTICMULT_ipd_1 : std_ulogic; + signal TIEC405DISOPERANDFWD_ipd_1 : std_ulogic; + signal TIEC405MMUEN_ipd_1 : std_ulogic; + signal TIEDCRADDR_ipd_1 : std_logic_vector(0 to 5); + signal TIEPVRBIT10_ipd_1 : std_ulogic; + signal TIEPVRBIT11_ipd_1 : std_ulogic; + signal TIEPVRBIT28_ipd_1 : std_ulogic; + signal TIEPVRBIT29_ipd_1 : std_ulogic; + signal TIEPVRBIT30_ipd_1 : std_ulogic; + signal TIEPVRBIT31_ipd_1 : std_ulogic; + signal TIEPVRBIT8_ipd_1 : std_ulogic; + signal TIEPVRBIT9_ipd_1 : std_ulogic; + signal TRCC405TRACEDISABLE_ipd_1 : std_ulogic; + signal TRCC405TRIGGEREVENTIN_ipd_1 : std_ulogic; + signal EMACDCRDBUS_ipd_1 : std_logic_vector(0 to 31); + signal EMACDCRACK_ipd_1 : std_ulogic; + + signal open_sig : std_ulogic; + signal VCC_sig : std_ulogic := '1'; + signal GND_sig : std_ulogic := '0'; + + signal FPGA_CCLK : std_ulogic := '0'; + signal FPGA_POR : std_ulogic := '1'; + signal FPGA_BUS_RESET : std_ulogic := '0'; + signal FPGA_GWE : std_ulogic := '0'; + signal FPGA_GHIGHB : std_ulogic := '0'; + signal FPGA_GSR : std_ulogic := '0'; + signal GSR_OR : std_ulogic := '0'; + signal GSR : std_ulogic := '0'; + signal FPGA_SHUTDOWN : std_ulogic := '0'; + + signal FPGA_CCLK_delay : std_ulogic := '0'; + signal FPGA_BUS_RESET_delay : std_ulogic := '0'; + signal GSR_delay : std_ulogic := '0'; + signal FPGA_GWE_delay : std_ulogic := '0'; + signal FPGA_GHIGHB_delay : std_ulogic := '0'; + signal FPGA_CCLK_reg : std_ulogic := '0'; + +-- signal ppcuser_binary : std_logic_vector(0 to 3) := PPCUSER; + + +begin + BRAMDSOCMCLK_ipd <= BRAMDSOCMCLK; + BRAMDSOCMRDDBUS_ipd <= BRAMDSOCMRDDBUS after 0 ps; + BRAMISOCMCLK_ipd <= BRAMISOCMCLK; + BRAMISOCMDCRRDDBUS_ipd <= BRAMISOCMDCRRDDBUS after 0 ps; + BRAMISOCMRDDBUS_ipd <= BRAMISOCMRDDBUS after 0 ps; + CPMC405CLOCK_ipd <= CPMC405CLOCK; + CPMC405CORECLKINACTIVE_ipd <= CPMC405CORECLKINACTIVE after 0 ps; + CPMC405CPUCLKEN_ipd <= CPMC405CPUCLKEN after 0 ps; + CPMC405JTAGCLKEN_ipd <= CPMC405JTAGCLKEN after 0 ps; + CPMC405SYNCBYPASS_ipd <= CPMC405SYNCBYPASS after 0 ps; + CPMC405TIMERCLKEN_ipd <= CPMC405TIMERCLKEN after 0 ps; + CPMC405TIMERTICK_ipd <= CPMC405TIMERTICK after 0 ps; + CPMDCRCLK_ipd <= CPMDCRCLK; + CPMFCMCLK_ipd <= CPMFCMCLK; + DBGC405DEBUGHALT_ipd <= DBGC405DEBUGHALT after 0 ps; + DBGC405EXTBUSHOLDACK_ipd <= DBGC405EXTBUSHOLDACK after 0 ps; + DBGC405UNCONDDEBUGEVENT_ipd <= DBGC405UNCONDDEBUGEVENT after 0 ps; + DSARCVALUE_ipd <= DSARCVALUE after 0 ps; + DSCNTLVALUE_ipd <= DSCNTLVALUE after 0 ps; + DSOCMRWCOMPLETE_ipd <= DSOCMRWCOMPLETE after 0 ps; + EICC405CRITINPUTIRQ_ipd <= EICC405CRITINPUTIRQ after 0 ps; + EICC405EXTINPUTIRQ_ipd <= EICC405EXTINPUTIRQ after 0 ps; + EMACDCRACK_ipd <= EMACDCRACK after 0 ps; + EMACDCRDBUS_ipd <= EMACDCRDBUS after 0 ps; + EXTDCRACK_ipd <= EXTDCRACK after 0 ps; + EXTDCRDBUSIN_ipd <= EXTDCRDBUSIN after 0 ps; + FCMAPUCR_ipd <= FCMAPUCR after 0 ps; + FCMAPUDCDCREN_ipd <= FCMAPUDCDCREN after 0 ps; + FCMAPUDCDFORCEALIGN_ipd <= FCMAPUDCDFORCEALIGN after 0 ps; + FCMAPUDCDFORCEBESTEERING_ipd <= FCMAPUDCDFORCEBESTEERING after 0 ps; + FCMAPUDCDFPUOP_ipd <= FCMAPUDCDFPUOP after 0 ps; + FCMAPUDCDGPRWRITE_ipd <= FCMAPUDCDGPRWRITE after 0 ps; + FCMAPUDCDLDSTBYTE_ipd <= FCMAPUDCDLDSTBYTE after 0 ps; + FCMAPUDCDLDSTDW_ipd <= FCMAPUDCDLDSTDW after 0 ps; + FCMAPUDCDLDSTHW_ipd <= FCMAPUDCDLDSTHW after 0 ps; + FCMAPUDCDLDSTQW_ipd <= FCMAPUDCDLDSTQW after 0 ps; + FCMAPUDCDLDSTWD_ipd <= FCMAPUDCDLDSTWD after 0 ps; + FCMAPUDCDLOAD_ipd <= FCMAPUDCDLOAD after 0 ps; + FCMAPUDCDPRIVOP_ipd <= FCMAPUDCDPRIVOP after 0 ps; + FCMAPUDCDRAEN_ipd <= FCMAPUDCDRAEN after 0 ps; + FCMAPUDCDRBEN_ipd <= FCMAPUDCDRBEN after 0 ps; + FCMAPUDCDSTORE_ipd <= FCMAPUDCDSTORE after 0 ps; + FCMAPUDCDTRAPBE_ipd <= FCMAPUDCDTRAPBE after 0 ps; + FCMAPUDCDTRAPLE_ipd <= FCMAPUDCDTRAPLE after 0 ps; + FCMAPUDCDUPDATE_ipd <= FCMAPUDCDUPDATE after 0 ps; + FCMAPUDCDXERCAEN_ipd <= FCMAPUDCDXERCAEN after 0 ps; + FCMAPUDCDXEROVEN_ipd <= FCMAPUDCDXEROVEN after 0 ps; + FCMAPUDECODEBUSY_ipd <= FCMAPUDECODEBUSY after 0 ps; + FCMAPUDONE_ipd <= FCMAPUDONE after 0 ps; + FCMAPUEXCEPTION_ipd <= FCMAPUEXCEPTION after 0 ps; + FCMAPUEXEBLOCKINGMCO_ipd <= FCMAPUEXEBLOCKINGMCO after 0 ps; + FCMAPUEXECRFIELD_ipd <= FCMAPUEXECRFIELD after 0 ps; + FCMAPUEXENONBLOCKINGMCO_ipd <= FCMAPUEXENONBLOCKINGMCO after 0 ps; + FCMAPUINSTRACK_ipd <= FCMAPUINSTRACK after 0 ps; + FCMAPULOADWAIT_ipd <= FCMAPULOADWAIT after 0 ps; + FCMAPURESULT_ipd <= FCMAPURESULT after 0 ps; + FCMAPURESULTVALID_ipd <= FCMAPURESULTVALID after 0 ps; + FCMAPUSLEEPNOTREADY_ipd <= FCMAPUSLEEPNOTREADY after 0 ps; + FCMAPUXERCA_ipd <= FCMAPUXERCA after 0 ps; + FCMAPUXEROV_ipd <= FCMAPUXEROV after 0 ps; + ISARCVALUE_ipd <= ISARCVALUE after 0 ps; + ISCNTLVALUE_ipd <= ISCNTLVALUE after 0 ps; + JTGC405BNDSCANTDO_ipd <= JTGC405BNDSCANTDO after 0 ps; + JTGC405TCK_ipd <= JTGC405TCK; + JTGC405TDI_ipd <= JTGC405TDI after 0 ps; + JTGC405TMS_ipd <= JTGC405TMS after 0 ps; + JTGC405TRSTNEG_ipd <= JTGC405TRSTNEG after 0 ps; + MCBCPUCLKEN_ipd <= MCBCPUCLKEN after 0 ps; + MCBJTAGEN_ipd <= MCBJTAGEN after 0 ps; + MCBTIMEREN_ipd <= MCBTIMEREN after 0 ps; + MCPPCRST_ipd <= MCPPCRST after 0 ps; + PLBC405DCUADDRACK_ipd <= PLBC405DCUADDRACK after 0 ps; + PLBC405DCUBUSY_ipd <= PLBC405DCUBUSY after 0 ps; + PLBC405DCUERR_ipd <= PLBC405DCUERR after 0 ps; + PLBC405DCURDDACK_ipd <= PLBC405DCURDDACK after 0 ps; + PLBC405DCURDDBUS_ipd <= PLBC405DCURDDBUS after 0 ps; + PLBC405DCURDWDADDR_ipd <= PLBC405DCURDWDADDR after 0 ps; + PLBC405DCUSSIZE1_ipd <= PLBC405DCUSSIZE1 after 0 ps; + PLBC405DCUWRDACK_ipd <= PLBC405DCUWRDACK after 0 ps; + PLBC405ICUADDRACK_ipd <= PLBC405ICUADDRACK after 0 ps; + PLBC405ICUBUSY_ipd <= PLBC405ICUBUSY after 0 ps; + PLBC405ICUERR_ipd <= PLBC405ICUERR after 0 ps; + PLBC405ICURDDACK_ipd <= PLBC405ICURDDACK after 0 ps; + PLBC405ICURDDBUS_ipd <= PLBC405ICURDDBUS after 0 ps; + PLBC405ICURDWDADDR_ipd <= PLBC405ICURDWDADDR after 0 ps; + PLBC405ICUSSIZE1_ipd <= PLBC405ICUSSIZE1 after 0 ps; + PLBCLK_ipd <= PLBCLK; + RSTC405RESETCHIP_ipd <= RSTC405RESETCHIP after 0 ps; + RSTC405RESETCORE_ipd <= RSTC405RESETCORE after 0 ps; + RSTC405RESETSYS_ipd <= RSTC405RESETSYS after 0 ps; + TIEAPUCONTROL_ipd <= TIEAPUCONTROL after 0 ps; + TIEAPUUDI1_ipd <= TIEAPUUDI1 after 0 ps; + TIEAPUUDI2_ipd <= TIEAPUUDI2 after 0 ps; + TIEAPUUDI3_ipd <= TIEAPUUDI3 after 0 ps; + TIEAPUUDI4_ipd <= TIEAPUUDI4 after 0 ps; + TIEAPUUDI5_ipd <= TIEAPUUDI5 after 0 ps; + TIEAPUUDI6_ipd <= TIEAPUUDI6 after 0 ps; + TIEAPUUDI7_ipd <= TIEAPUUDI7 after 0 ps; + TIEAPUUDI8_ipd <= TIEAPUUDI8 after 0 ps; + TIEC405DETERMINISTICMULT_ipd <= TIEC405DETERMINISTICMULT after 0 ps; + TIEC405DISOPERANDFWD_ipd <= TIEC405DISOPERANDFWD after 0 ps; + TIEC405MMUEN_ipd <= TIEC405MMUEN after 0 ps; + TIEDCRADDR_ipd <= TIEDCRADDR after 0 ps; + TIEPVRBIT10_ipd <= TIEPVRBIT10 after 0 ps; + TIEPVRBIT11_ipd <= TIEPVRBIT11 after 0 ps; + TIEPVRBIT28_ipd <= TIEPVRBIT28 after 0 ps; + TIEPVRBIT29_ipd <= TIEPVRBIT29 after 0 ps; + TIEPVRBIT30_ipd <= TIEPVRBIT30 after 0 ps; + TIEPVRBIT31_ipd <= TIEPVRBIT31 after 0 ps; + TIEPVRBIT8_ipd <= TIEPVRBIT8 after 0 ps; + TIEPVRBIT9_ipd <= TIEPVRBIT9 after 0 ps; + TRCC405TRACEDISABLE_ipd <= TRCC405TRACEDISABLE after 0 ps; + TRCC405TRIGGEREVENTIN_ipd <= TRCC405TRIGGEREVENTIN after 0 ps; + + BRAMDSOCMCLK_ipd_1 <= BRAMDSOCMCLK_ipd; + BRAMDSOCMRDDBUS_ipd_1 <= BRAMDSOCMRDDBUS_ipd after in_delay; + BRAMISOCMCLK_ipd_1 <= BRAMISOCMCLK_ipd; + BRAMISOCMDCRRDDBUS_ipd_1 <= BRAMISOCMDCRRDDBUS_ipd after in_delay; + BRAMISOCMRDDBUS_ipd_1 <= BRAMISOCMRDDBUS_ipd after in_delay; + CPMC405CLOCK_ipd_1 <= CPMC405CLOCK_ipd; + CPMC405CORECLKINACTIVE_ipd_1 <= CPMC405CORECLKINACTIVE_ipd after in_delay; + CPMC405CPUCLKEN_ipd_1 <= CPMC405CPUCLKEN_ipd after in_delay; + CPMC405JTAGCLKEN_ipd_1 <= CPMC405JTAGCLKEN_ipd after in_delay; + CPMC405SYNCBYPASS_ipd_1 <= CPMC405SYNCBYPASS_ipd after in_delay; + CPMC405TIMERCLKEN_ipd_1 <= CPMC405TIMERCLKEN_ipd after in_delay; + CPMC405TIMERTICK_ipd_1 <= CPMC405TIMERTICK_ipd after in_delay; + CPMDCRCLK_ipd_1 <= CPMDCRCLK_ipd; + CPMFCMCLK_ipd_1 <= CPMFCMCLK_ipd; + DBGC405DEBUGHALT_ipd_1 <= DBGC405DEBUGHALT_ipd after in_delay; + DBGC405EXTBUSHOLDACK_ipd_1 <= DBGC405EXTBUSHOLDACK_ipd after in_delay; + DBGC405UNCONDDEBUGEVENT_ipd_1 <= DBGC405UNCONDDEBUGEVENT_ipd after in_delay; + DSARCVALUE_ipd_1 <= DSARCVALUE_ipd after in_delay; + DSCNTLVALUE_ipd_1 <= DSCNTLVALUE_ipd after in_delay; + DSOCMRWCOMPLETE_ipd_1 <= DSOCMRWCOMPLETE_ipd after in_delay; + EICC405CRITINPUTIRQ_ipd_1 <= EICC405CRITINPUTIRQ_ipd after in_delay; + EICC405EXTINPUTIRQ_ipd_1 <= EICC405EXTINPUTIRQ_ipd after in_delay; + EMACDCRACK_ipd_1 <= EMACDCRACK_ipd after in_delay; + EMACDCRDBUS_ipd_1 <= EMACDCRDBUS_ipd after in_delay; + EXTDCRACK_ipd_1 <= EXTDCRACK_ipd after in_delay; + EXTDCRDBUSIN_ipd_1 <= EXTDCRDBUSIN_ipd after in_delay; + FCMAPUCR_ipd_1 <= FCMAPUCR_ipd after in_delay; + FCMAPUDCDCREN_ipd_1 <= FCMAPUDCDCREN_ipd after in_delay; + FCMAPUDCDFORCEALIGN_ipd_1 <= FCMAPUDCDFORCEALIGN_ipd after in_delay; + FCMAPUDCDFORCEBESTEERING_ipd_1 <= FCMAPUDCDFORCEBESTEERING_ipd after in_delay; + FCMAPUDCDFPUOP_ipd_1 <= FCMAPUDCDFPUOP_ipd after in_delay; + FCMAPUDCDGPRWRITE_ipd_1 <= FCMAPUDCDGPRWRITE_ipd after in_delay; + FCMAPUDCDLDSTBYTE_ipd_1 <= FCMAPUDCDLDSTBYTE_ipd after in_delay; + FCMAPUDCDLDSTDW_ipd_1 <= FCMAPUDCDLDSTDW_ipd after in_delay; + FCMAPUDCDLDSTHW_ipd_1 <= FCMAPUDCDLDSTHW_ipd after in_delay; + FCMAPUDCDLDSTQW_ipd_1 <= FCMAPUDCDLDSTQW_ipd after in_delay; + FCMAPUDCDLDSTWD_ipd_1 <= FCMAPUDCDLDSTWD_ipd after in_delay; + FCMAPUDCDLOAD_ipd_1 <= FCMAPUDCDLOAD_ipd after in_delay; + FCMAPUDCDPRIVOP_ipd_1 <= FCMAPUDCDPRIVOP_ipd after in_delay; + FCMAPUDCDRAEN_ipd_1 <= FCMAPUDCDRAEN_ipd after in_delay; + FCMAPUDCDRBEN_ipd_1 <= FCMAPUDCDRBEN_ipd after in_delay; + FCMAPUDCDSTORE_ipd_1 <= FCMAPUDCDSTORE_ipd after in_delay; + FCMAPUDCDTRAPBE_ipd_1 <= FCMAPUDCDTRAPBE_ipd after in_delay; + FCMAPUDCDTRAPLE_ipd_1 <= FCMAPUDCDTRAPLE_ipd after in_delay; + FCMAPUDCDUPDATE_ipd_1 <= FCMAPUDCDUPDATE_ipd after in_delay; + FCMAPUDCDXERCAEN_ipd_1 <= FCMAPUDCDXERCAEN_ipd after in_delay; + FCMAPUDCDXEROVEN_ipd_1 <= FCMAPUDCDXEROVEN_ipd after in_delay; + FCMAPUDECODEBUSY_ipd_1 <= FCMAPUDECODEBUSY_ipd after in_delay; + FCMAPUDONE_ipd_1 <= FCMAPUDONE_ipd after in_delay; + FCMAPUEXCEPTION_ipd_1 <= FCMAPUEXCEPTION_ipd after in_delay; + FCMAPUEXEBLOCKINGMCO_ipd_1 <= FCMAPUEXEBLOCKINGMCO_ipd after in_delay; + FCMAPUEXECRFIELD_ipd_1 <= FCMAPUEXECRFIELD_ipd after in_delay; + FCMAPUEXENONBLOCKINGMCO_ipd_1 <= FCMAPUEXENONBLOCKINGMCO_ipd after in_delay; + FCMAPUINSTRACK_ipd_1 <= FCMAPUINSTRACK_ipd after in_delay; + FCMAPULOADWAIT_ipd_1 <= FCMAPULOADWAIT_ipd after in_delay; + FCMAPURESULT_ipd_1 <= FCMAPURESULT_ipd after in_delay; + FCMAPURESULTVALID_ipd_1 <= FCMAPURESULTVALID_ipd after in_delay; + FCMAPUSLEEPNOTREADY_ipd_1 <= FCMAPUSLEEPNOTREADY_ipd after in_delay; + FCMAPUXERCA_ipd_1 <= FCMAPUXERCA_ipd after in_delay; + FCMAPUXEROV_ipd_1 <= FCMAPUXEROV_ipd after in_delay; + ISARCVALUE_ipd_1 <= ISARCVALUE_ipd after in_delay; + ISCNTLVALUE_ipd_1 <= ISCNTLVALUE_ipd after in_delay; + JTGC405BNDSCANTDO_ipd_1 <= JTGC405BNDSCANTDO_ipd after in_delay; + JTGC405TCK_ipd_1 <= JTGC405TCK_ipd; + JTGC405TDI_ipd_1 <= JTGC405TDI_ipd after in_delay; + JTGC405TMS_ipd_1 <= JTGC405TMS_ipd after in_delay; + JTGC405TRSTNEG_ipd_1 <= JTGC405TRSTNEG_ipd after in_delay; + MCBCPUCLKEN_ipd_1 <= MCBCPUCLKEN_ipd after in_delay; + MCBJTAGEN_ipd_1 <= MCBJTAGEN_ipd after in_delay; + MCBTIMEREN_ipd_1 <= MCBTIMEREN_ipd after in_delay; + MCPPCRST_ipd_1 <= MCPPCRST_ipd after in_delay; + PLBC405DCUADDRACK_ipd_1 <= PLBC405DCUADDRACK_ipd after in_delay; + PLBC405DCUBUSY_ipd_1 <= PLBC405DCUBUSY_ipd after in_delay; + PLBC405DCUERR_ipd_1 <= PLBC405DCUERR_ipd after in_delay; + PLBC405DCURDDACK_ipd_1 <= PLBC405DCURDDACK_ipd after in_delay; + PLBC405DCURDDBUS_ipd_1 <= PLBC405DCURDDBUS_ipd after in_delay; + PLBC405DCURDWDADDR_ipd_1 <= PLBC405DCURDWDADDR_ipd after in_delay; + PLBC405DCUSSIZE1_ipd_1 <= PLBC405DCUSSIZE1_ipd after in_delay; + PLBC405DCUWRDACK_ipd_1 <= PLBC405DCUWRDACK_ipd after in_delay; + PLBC405ICUADDRACK_ipd_1 <= PLBC405ICUADDRACK_ipd after in_delay; + PLBC405ICUBUSY_ipd_1 <= PLBC405ICUBUSY_ipd after in_delay; + PLBC405ICUERR_ipd_1 <= PLBC405ICUERR_ipd after in_delay; + PLBC405ICURDDACK_ipd_1 <= PLBC405ICURDDACK_ipd after in_delay; + PLBC405ICURDDBUS_ipd_1 <= PLBC405ICURDDBUS_ipd after in_delay; + PLBC405ICURDWDADDR_ipd_1 <= PLBC405ICURDWDADDR_ipd after in_delay; + PLBC405ICUSSIZE1_ipd_1 <= PLBC405ICUSSIZE1_ipd after in_delay; + PLBCLK_ipd_1 <= PLBCLK_ipd; + RSTC405RESETCHIP_ipd_1 <= RSTC405RESETCHIP_ipd after in_delay; + RSTC405RESETCORE_ipd_1 <= RSTC405RESETCORE_ipd after in_delay; + RSTC405RESETSYS_ipd_1 <= RSTC405RESETSYS_ipd after in_delay; + TIEAPUCONTROL_ipd_1 <= TIEAPUCONTROL_ipd after in_delay; + TIEAPUUDI1_ipd_1 <= TIEAPUUDI1_ipd after in_delay; + TIEAPUUDI2_ipd_1 <= TIEAPUUDI2_ipd after in_delay; + TIEAPUUDI3_ipd_1 <= TIEAPUUDI3_ipd after in_delay; + TIEAPUUDI4_ipd_1 <= TIEAPUUDI4_ipd after in_delay; + TIEAPUUDI5_ipd_1 <= TIEAPUUDI5_ipd after in_delay; + TIEAPUUDI6_ipd_1 <= TIEAPUUDI6_ipd after in_delay; + TIEAPUUDI7_ipd_1 <= TIEAPUUDI7_ipd after in_delay; + TIEAPUUDI8_ipd_1 <= TIEAPUUDI8_ipd after in_delay; + TIEC405DETERMINISTICMULT_ipd_1 <= TIEC405DETERMINISTICMULT_ipd after in_delay; + TIEC405DISOPERANDFWD_ipd_1 <= TIEC405DISOPERANDFWD_ipd after in_delay; + TIEC405MMUEN_ipd_1 <= TIEC405MMUEN_ipd after in_delay; + TIEDCRADDR_ipd_1 <= TIEDCRADDR_ipd after in_delay; + TIEPVRBIT10_ipd_1 <= TIEPVRBIT10_ipd after in_delay; + TIEPVRBIT11_ipd_1 <= TIEPVRBIT11_ipd after in_delay; + TIEPVRBIT28_ipd_1 <= TIEPVRBIT28_ipd after in_delay; + TIEPVRBIT29_ipd_1 <= TIEPVRBIT29_ipd after in_delay; + TIEPVRBIT30_ipd_1 <= TIEPVRBIT30_ipd after in_delay; + TIEPVRBIT31_ipd_1 <= TIEPVRBIT31_ipd after in_delay; + TIEPVRBIT8_ipd_1 <= TIEPVRBIT8_ipd after in_delay; + TIEPVRBIT9_ipd_1 <= TIEPVRBIT9_ipd after in_delay; + TRCC405TRACEDISABLE_ipd_1 <= TRCC405TRACEDISABLE_ipd after in_delay; + TRCC405TRIGGEREVENTIN_ipd_1 <= TRCC405TRIGGEREVENTIN_ipd after in_delay; + + ppc405_adv_swift_bw_1 : PPC405_ADV_SWIFT_BUS + port map ( + CFG_MCLK => FPGA_CCLK, + BUS_RESET => FPGA_BUS_RESET_delay, + GSR => GSR_delay, + GWE => FPGA_GWE_delay, + GHIGHB => FPGA_GHIGHB_delay, + + CPMC405CPUCLKEN => CPMC405CPUCLKEN_ipd_1, + CPMC405JTAGCLKEN => CPMC405JTAGCLKEN_ipd_1, + CPMC405TIMERCLKEN => CPMC405TIMERCLKEN_ipd_1, + C405JTGPGMOUT => C405JTGPGMOUT_out, + MCBCPUCLKEN => MCBCPUCLKEN_ipd_1, + MCBJTAGEN => MCBJTAGEN_ipd_1, + MCBTIMEREN => MCBTIMEREN_ipd_1, + MCPPCRST => MCPPCRST_ipd_1, + C405TRCODDEXECUTIONSTATUS => C405TRCODDEXECUTIONSTATUS_out, + C405TRCEVENEXECUTIONSTATUS => C405TRCEVENEXECUTIONSTATUS_out, + CPMC405CLOCK => CPMC405CLOCK_ipd_1, + CPMC405CORECLKINACTIVE => CPMC405CORECLKINACTIVE_ipd_1, + PLBCLK => PLBCLK_ipd_1, + CPMFCMCLK => CPMFCMCLK_ipd_1, + CPMDCRCLK => CPMDCRCLK_ipd_1, + CPMC405SYNCBYPASS => CPMC405SYNCBYPASS_ipd_1, + CPMC405TIMERTICK => CPMC405TIMERTICK_ipd_1, + C405CPMMSREE => C405CPMMSREE_out, + C405CPMMSRCE => C405CPMMSRCE_out, + C405CPMTIMERIRQ => C405CPMTIMERIRQ_out, + C405CPMTIMERRESETREQ => C405CPMTIMERRESETREQ_out, + C405CPMCORESLEEPREQ => C405CPMCORESLEEPREQ_out, + TIEC405DISOPERANDFWD => TIEC405DISOPERANDFWD_ipd_1, + TIEC405DETERMINISTICMULT => TIEC405DETERMINISTICMULT_ipd_1, + TIEC405MMUEN => TIEC405MMUEN_ipd_1, + TIEPVRBIT8 => TIEPVRBIT8_ipd_1, + TIEPVRBIT9 => TIEPVRBIT9_ipd_1, + TIEPVRBIT10 => TIEPVRBIT10_ipd_1, + TIEPVRBIT11 => TIEPVRBIT11_ipd_1, + TIEPVRBIT28 => TIEPVRBIT28_ipd_1, + TIEPVRBIT29 => TIEPVRBIT29_ipd_1, + TIEPVRBIT30 => TIEPVRBIT30_ipd_1, + TIEPVRBIT31 => TIEPVRBIT31_ipd_1, + C405XXXMACHINECHECK => C405XXXMACHINECHECK_out, + DCREMACENABLER => DCREMACENABLER_out, + DCREMACCLK => DCREMACCLK_out, + DCREMACWRITE => DCREMACWRITE_out, + DCREMACREAD => DCREMACREAD_out, + DCREMACDBUS => DCREMACDBUS_out, + DCREMACABUS => DCREMACABUS_out, + EMACDCRDBUS => EMACDCRDBUS_ipd_1, + EMACDCRACK => EMACDCRACK_ipd_1, + C405RSTCHIPRESETREQ => C405RSTCHIPRESETREQ_out, + C405RSTCORERESETREQ => C405RSTCORERESETREQ_out, + C405RSTSYSRESETREQ => C405RSTSYSRESETREQ_out, + RSTC405RESETCHIP => RSTC405RESETCHIP_ipd_1, + RSTC405RESETCORE => RSTC405RESETCORE_ipd_1, + RSTC405RESETSYS => RSTC405RESETSYS_ipd_1, + C405PLBICUREQUEST => C405PLBICUREQUEST_out, + C405PLBICUPRIORITY => C405PLBICUPRIORITY_out, + C405PLBICUCACHEABLE => C405PLBICUCACHEABLE_out, + C405PLBICUABUS => C405PLBICUABUS_out, + C405PLBICUSIZE => C405PLBICUSIZE_out, + C405PLBICUABORT => C405PLBICUABORT_out, + C405PLBICUU0ATTR => C405PLBICUU0ATTR_out, + PLBC405ICUADDRACK => PLBC405ICUADDRACK_ipd_1, + PLBC405ICUBUSY => PLBC405ICUBUSY_ipd_1, + PLBC405ICUERR => PLBC405ICUERR_ipd_1, + PLBC405ICURDDACK => PLBC405ICURDDACK_ipd_1, + PLBC405ICURDDBUS => PLBC405ICURDDBUS_ipd_1, + PLBC405ICUSSIZE1 => PLBC405ICUSSIZE1_ipd_1, + PLBC405ICURDWDADDR => PLBC405ICURDWDADDR_ipd_1, + C405PLBDCUREQUEST => C405PLBDCUREQUEST_out, + C405PLBDCURNW => C405PLBDCURNW_out, + C405PLBDCUABUS => C405PLBDCUABUS_out, + C405PLBDCUBE => C405PLBDCUBE_out, + C405PLBDCUCACHEABLE => C405PLBDCUCACHEABLE_out, + C405PLBDCUGUARDED => C405PLBDCUGUARDED_out, + C405PLBDCUPRIORITY => C405PLBDCUPRIORITY_out, + C405PLBDCUSIZE2 => C405PLBDCUSIZE2_out, + C405PLBDCUABORT => C405PLBDCUABORT_out, + C405PLBDCUWRDBUS => C405PLBDCUWRDBUS_out, + C405PLBDCUU0ATTR => C405PLBDCUU0ATTR_out, + C405PLBDCUWRITETHRU => C405PLBDCUWRITETHRU_out, + PLBC405DCUADDRACK => PLBC405DCUADDRACK_ipd_1, + PLBC405DCUBUSY => PLBC405DCUBUSY_ipd_1, + PLBC405DCUERR => PLBC405DCUERR_ipd_1, + PLBC405DCURDDACK => PLBC405DCURDDACK_ipd_1, + PLBC405DCURDDBUS => PLBC405DCURDDBUS_ipd_1, + PLBC405DCURDWDADDR => PLBC405DCURDWDADDR_ipd_1, + PLBC405DCUSSIZE1 => PLBC405DCUSSIZE1_ipd_1, + PLBC405DCUWRDACK => PLBC405DCUWRDACK_ipd_1, + ISOCMBRAMRDABUS => ISOCMBRAMRDABUS_out, + ISOCMBRAMWRABUS => ISOCMBRAMWRABUS_out, + ISOCMBRAMEN => ISOCMBRAMEN_out, + ISOCMBRAMODDWRITEEN => ISOCMBRAMODDWRITEEN_out, + ISOCMBRAMEVENWRITEEN => ISOCMBRAMEVENWRITEEN_out, + ISOCMBRAMWRDBUS => ISOCMBRAMWRDBUS_out, + ISOCMDCRBRAMEVENEN => ISOCMDCRBRAMEVENEN_out, + ISOCMDCRBRAMODDEN => ISOCMDCRBRAMODDEN_out, + ISOCMDCRBRAMRDSELECT => ISOCMDCRBRAMRDSELECT_out, + BRAMISOCMDCRRDDBUS => BRAMISOCMDCRRDDBUS_ipd_1, + BRAMISOCMRDDBUS => BRAMISOCMRDDBUS_ipd_1, + ISARCVALUE => ISARCVALUE_ipd_1, + ISCNTLVALUE => ISCNTLVALUE_ipd_1, + BRAMISOCMCLK => BRAMISOCMCLK_ipd_1, + DSOCMBRAMABUS => DSOCMBRAMABUS_out, + DSOCMBRAMBYTEWRITE => DSOCMBRAMBYTEWRITE_out, + DSOCMBRAMEN => DSOCMBRAMEN_out, + DSOCMBRAMWRDBUS => DSOCMBRAMWRDBUS_out, + BRAMDSOCMRDDBUS => BRAMDSOCMRDDBUS_ipd_1, + DSOCMRWCOMPLETE => DSOCMRWCOMPLETE_ipd_1, + DSOCMBUSY => DSOCMBUSY_out, + DSOCMWRADDRVALID => DSOCMWRADDRVALID_out, + DSOCMRDADDRVALID => DSOCMRDADDRVALID_out, + TIEDCRADDR => TIEDCRADDR_ipd_1, + DSARCVALUE => DSARCVALUE_ipd_1, + DSCNTLVALUE => DSCNTLVALUE_ipd_1, + BRAMDSOCMCLK => BRAMDSOCMCLK_ipd_1, + EXTDCRREAD => EXTDCRREAD_out, + EXTDCRWRITE => EXTDCRWRITE_out, + EXTDCRABUS => EXTDCRABUS_out, + EXTDCRDBUSOUT => EXTDCRDBUSOUT_out, + EXTDCRACK => EXTDCRACK_ipd_1, + EXTDCRDBUSIN => EXTDCRDBUSIN_ipd_1, + EICC405EXTINPUTIRQ => EICC405EXTINPUTIRQ_ipd_1, + EICC405CRITINPUTIRQ => EICC405CRITINPUTIRQ_ipd_1, + JTGC405BNDSCANTDO => JTGC405BNDSCANTDO_ipd_1, + JTGC405TCK => JTGC405TCK_ipd_1, + JTGC405TDI => JTGC405TDI_ipd_1, + JTGC405TMS => JTGC405TMS, + JTGC405TRSTNEG => JTGC405TRSTNEG_ipd_1, + C405JTGTDO => C405JTGTDO_out, + C405JTGTDOEN => C405JTGTDOEN_out, + C405JTGEXTEST => C405JTGEXTEST_out, + C405JTGCAPTUREDR => C405JTGCAPTUREDR_out, + C405JTGSHIFTDR => C405JTGSHIFTDR_out, + C405JTGUPDATEDR => C405JTGUPDATEDR_out, + DBGC405DEBUGHALT => DBGC405DEBUGHALT_ipd_1, + DBGC405UNCONDDEBUGEVENT => DBGC405UNCONDDEBUGEVENT_ipd_1, + DBGC405EXTBUSHOLDACK => DBGC405EXTBUSHOLDACK_ipd_1, + C405DBGMSRWE => C405DBGMSRWE_out, + C405DBGSTOPACK => C405DBGSTOPACK_out, + C405DBGWBCOMPLETE => C405DBGWBCOMPLETE_out, + C405DBGWBFULL => C405DBGWBFULL_out, + C405DBGWBIAR => C405DBGWBIAR_out, + C405TRCTRIGGEREVENTOUT => C405TRCTRIGGEREVENTOUT_out, + C405TRCTRIGGEREVENTTYPE => C405TRCTRIGGEREVENTTYPE_out, + C405TRCCYCLE => C405TRCCYCLE_out, + C405TRCTRACESTATUS => C405TRCTRACESTATUS_out, + TRCC405TRACEDISABLE => TRCC405TRACEDISABLE_ipd_1, + TRCC405TRIGGEREVENTIN => TRCC405TRIGGEREVENTIN_ipd_1, + C405DBGLOADDATAONAPUDBUS => C405DBGLOADDATAONAPUDBUS_out, + APUFCMINSTRUCTION => APUFCMINSTRUCTION_out, + APUFCMRADATA => APUFCMRADATA_out, + APUFCMRBDATA => APUFCMRBDATA_out, + APUFCMINSTRVALID => APUFCMINSTRVALID_out, + APUFCMLOADDATA => APUFCMLOADDATA_out, + APUFCMOPERANDVALID => APUFCMOPERANDVALID_out, + APUFCMLOADDVALID => APUFCMLOADDVALID_out, + APUFCMFLUSH => APUFCMFLUSH_out, + APUFCMWRITEBACKOK => APUFCMWRITEBACKOK_out, + APUFCMLOADBYTEEN => APUFCMLOADBYTEEN_out, + APUFCMENDIAN => APUFCMENDIAN_out, + APUFCMXERCA => APUFCMXERCA_out, + APUFCMDECODED => APUFCMDECODED_out, + APUFCMDECUDI => APUFCMDECUDI_out, + APUFCMDECUDIVALID => APUFCMDECUDIVALID_out, + FCMAPUDONE => FCMAPUDONE_ipd_1, + FCMAPURESULT => FCMAPURESULT_ipd_1, + FCMAPURESULTVALID => FCMAPURESULTVALID_ipd_1, + FCMAPUINSTRACK => FCMAPUINSTRACK_ipd_1, + FCMAPUEXCEPTION => FCMAPUEXCEPTION_ipd_1, + FCMAPUXERCA => FCMAPUXERCA_ipd_1, + FCMAPUXEROV => FCMAPUXEROV_ipd_1, + FCMAPUCR => FCMAPUCR_ipd_1, + FCMAPUDCDFPUOP => FCMAPUDCDFPUOP_ipd_1, + FCMAPUDCDGPRWRITE => FCMAPUDCDGPRWRITE_ipd_1, + FCMAPUDCDRAEN => FCMAPUDCDRAEN_ipd_1, + FCMAPUDCDRBEN => FCMAPUDCDRBEN_ipd_1, + FCMAPUDCDLOAD => FCMAPUDCDLOAD_ipd_1, + FCMAPUDCDSTORE => FCMAPUDCDSTORE_ipd_1, + FCMAPUDCDXERCAEN => FCMAPUDCDXERCAEN_ipd_1, + FCMAPUDCDXEROVEN => FCMAPUDCDXEROVEN_ipd_1, + FCMAPUDCDPRIVOP => FCMAPUDCDPRIVOP_ipd_1, + FCMAPUDCDCREN => FCMAPUDCDCREN_ipd_1, + FCMAPUEXECRFIELD => FCMAPUEXECRFIELD_ipd_1, + FCMAPUDCDUPDATE => FCMAPUDCDUPDATE_ipd_1, + FCMAPUDCDFORCEALIGN => FCMAPUDCDFORCEALIGN_ipd_1, + FCMAPUDCDFORCEBESTEERING => FCMAPUDCDFORCEBESTEERING_ipd_1, + FCMAPUDCDLDSTBYTE => FCMAPUDCDLDSTBYTE_ipd_1, + FCMAPUDCDLDSTHW => FCMAPUDCDLDSTHW_ipd_1, + FCMAPUDCDLDSTWD => FCMAPUDCDLDSTWD_ipd_1, + FCMAPUDCDLDSTDW => FCMAPUDCDLDSTDW_ipd_1, + FCMAPUDCDLDSTQW => FCMAPUDCDLDSTQW_ipd_1, + FCMAPUDCDTRAPBE => FCMAPUDCDTRAPBE_ipd_1, + FCMAPUDCDTRAPLE => FCMAPUDCDTRAPLE_ipd_1, + FCMAPUEXEBLOCKINGMCO => FCMAPUEXEBLOCKINGMCO_ipd_1, + FCMAPUEXENONBLOCKINGMCO => FCMAPUEXENONBLOCKINGMCO_ipd_1, + FCMAPUSLEEPNOTREADY => FCMAPUSLEEPNOTREADY_ipd_1, + FCMAPULOADWAIT => FCMAPULOADWAIT_ipd_1, + FCMAPUDECODEBUSY => FCMAPUDECODEBUSY_ipd_1, + TIEAPUCONTROL => TIEAPUCONTROL_ipd_1, + TIEAPUUDI1 => TIEAPUUDI1_ipd_1, + TIEAPUUDI2 => TIEAPUUDI2_ipd_1, + TIEAPUUDI3 => TIEAPUUDI3_ipd_1, + TIEAPUUDI4 => TIEAPUUDI4_ipd_1, + TIEAPUUDI5 => TIEAPUUDI5_ipd_1, + TIEAPUUDI6 => TIEAPUUDI6_ipd_1, + TIEAPUUDI7 => TIEAPUUDI7_ipd_1, + TIEAPUUDI8 => TIEAPUUDI8_ipd_1 + + ); + +start_blk : fpga_startup_virtex4 + + port map ( + bus_reset => FPGA_BUS_RESET, + ghigh_b => FPGA_GHIGHB, + gsr => FPGA_GSR, + gwe => FPGA_GWE, + shutdown => FPGA_SHUTDOWN, + + cclk => FPGA_CCLK, + por => FPGA_POR); + + GSR_OR <= FPGA_GSR or GSR; + FPGA_POR <= '0' after 1000 ps; + FPGA_CCLK <= NOT(FPGA_CCLK) after 5000 ps; + + FPGA_BUS_RESET_delay <= FPGA_BUS_RESET after 10 ps ; + GSR_delay <= GSR_OR after 10 ps; + FPGA_GWE_delay <= FPGA_GWE after 10 ps; + FPGA_GHIGHB_delay <= FPGA_GHIGHB after 10 ps; + + + TIMING : process + variable APUFCMDECODED_GlitchData : VitalGlitchDataType; + variable APUFCMDECUDI0_GlitchData : VitalGlitchDataType; + variable APUFCMDECUDI1_GlitchData : VitalGlitchDataType; + variable APUFCMDECUDI2_GlitchData : VitalGlitchDataType; + variable APUFCMDECUDIVALID_GlitchData : VitalGlitchDataType; + variable APUFCMENDIAN_GlitchData : VitalGlitchDataType; + variable APUFCMFLUSH_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION0_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION1_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION2_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION3_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION4_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION5_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION6_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION7_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION8_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION9_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION10_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION11_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION12_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION13_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION14_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION15_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION16_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION17_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION18_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION19_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION20_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION21_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION22_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION23_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION24_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION25_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION26_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION27_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION28_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION29_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION30_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION31_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRVALID_GlitchData : VitalGlitchDataType; + variable APUFCMLOADBYTEEN0_GlitchData : VitalGlitchDataType; + variable APUFCMLOADBYTEEN1_GlitchData : VitalGlitchDataType; + variable APUFCMLOADBYTEEN2_GlitchData : VitalGlitchDataType; + variable APUFCMLOADBYTEEN3_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA0_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA1_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA2_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA3_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA4_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA5_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA6_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA7_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA8_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA9_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA10_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA11_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA12_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA13_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA14_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA15_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA16_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA17_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA18_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA19_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA20_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA21_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA22_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA23_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA24_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA25_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA26_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA27_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA28_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA29_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA30_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA31_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDVALID_GlitchData : VitalGlitchDataType; + variable APUFCMOPERANDVALID_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA0_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA1_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA2_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA3_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA4_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA5_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA6_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA7_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA8_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA9_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA10_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA11_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA12_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA13_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA14_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA15_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA16_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA17_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA18_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA19_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA20_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA21_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA22_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA23_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA24_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA25_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA26_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA27_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA28_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA29_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA30_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA31_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA0_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA1_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA2_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA3_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA4_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA5_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA6_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA7_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA8_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA9_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA10_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA11_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA12_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA13_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA14_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA15_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA16_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA17_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA18_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA19_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA20_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA21_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA22_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA23_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA24_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA25_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA26_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA27_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA28_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA29_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA30_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA31_GlitchData : VitalGlitchDataType; + variable APUFCMWRITEBACKOK_GlitchData : VitalGlitchDataType; + variable APUFCMXERCA_GlitchData : VitalGlitchDataType; + variable C405CPMCORESLEEPREQ_GlitchData : VitalGlitchDataType; + variable C405CPMMSRCE_GlitchData : VitalGlitchDataType; + variable C405CPMMSREE_GlitchData : VitalGlitchDataType; + variable C405CPMTIMERIRQ_GlitchData : VitalGlitchDataType; + variable C405CPMTIMERRESETREQ_GlitchData : VitalGlitchDataType; + variable C405DBGLOADDATAONAPUDBUS_GlitchData : VitalGlitchDataType; + variable C405DBGMSRWE_GlitchData : VitalGlitchDataType; + variable C405DBGSTOPACK_GlitchData : VitalGlitchDataType; + variable C405DBGWBCOMPLETE_GlitchData : VitalGlitchDataType; + variable C405DBGWBFULL_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR0_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR1_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR2_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR3_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR4_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR5_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR6_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR7_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR8_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR9_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR10_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR11_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR12_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR13_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR14_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR15_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR16_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR17_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR18_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR19_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR20_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR21_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR22_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR23_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR24_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR25_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR26_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR27_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR28_GlitchData : VitalGlitchDataType; + variable C405DBGWBIAR29_GlitchData : VitalGlitchDataType; + variable C405JTGCAPTUREDR_GlitchData : VitalGlitchDataType; + variable C405JTGEXTEST_GlitchData : VitalGlitchDataType; + variable C405JTGPGMOUT_GlitchData : VitalGlitchDataType; + variable C405JTGSHIFTDR_GlitchData : VitalGlitchDataType; + variable C405JTGTDO_GlitchData : VitalGlitchDataType; + variable C405JTGTDOEN_GlitchData : VitalGlitchDataType; + variable C405JTGUPDATEDR_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABORT_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS0_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS1_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS2_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS3_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS4_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS5_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS6_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS7_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS8_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS9_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS10_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS11_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS12_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS13_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS14_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS15_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS16_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS17_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS18_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS19_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS20_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS21_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS22_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS23_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS24_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS25_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS26_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS27_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS28_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS29_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS30_GlitchData : VitalGlitchDataType; + variable C405PLBDCUABUS31_GlitchData : VitalGlitchDataType; + variable C405PLBDCUBE0_GlitchData : VitalGlitchDataType; + variable C405PLBDCUBE1_GlitchData : VitalGlitchDataType; + variable C405PLBDCUBE2_GlitchData : VitalGlitchDataType; + variable C405PLBDCUBE3_GlitchData : VitalGlitchDataType; + variable C405PLBDCUBE4_GlitchData : VitalGlitchDataType; + variable C405PLBDCUBE5_GlitchData : VitalGlitchDataType; + variable C405PLBDCUBE6_GlitchData : VitalGlitchDataType; + variable C405PLBDCUBE7_GlitchData : VitalGlitchDataType; + variable C405PLBDCUCACHEABLE_GlitchData : VitalGlitchDataType; + variable C405PLBDCUGUARDED_GlitchData : VitalGlitchDataType; + variable C405PLBDCUPRIORITY0_GlitchData : VitalGlitchDataType; + variable C405PLBDCUPRIORITY1_GlitchData : VitalGlitchDataType; + variable C405PLBDCUREQUEST_GlitchData : VitalGlitchDataType; + variable C405PLBDCURNW_GlitchData : VitalGlitchDataType; + variable C405PLBDCUSIZE2_GlitchData : VitalGlitchDataType; + variable C405PLBDCUU0ATTR_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS0_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS1_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS2_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS3_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS4_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS5_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS6_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS7_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS8_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS9_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS10_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS11_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS12_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS13_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS14_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS15_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS16_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS17_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS18_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS19_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS20_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS21_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS22_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS23_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS24_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS25_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS26_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS27_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS28_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS29_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS30_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS31_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS32_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS33_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS34_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS35_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS36_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS37_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS38_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS39_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS40_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS41_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS42_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS43_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS44_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS45_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS46_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS47_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS48_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS49_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS50_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS51_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS52_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS53_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS54_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS55_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS56_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS57_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS58_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS59_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS60_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS61_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS62_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRDBUS63_GlitchData : VitalGlitchDataType; + variable C405PLBDCUWRITETHRU_GlitchData : VitalGlitchDataType; + variable C405PLBICUABORT_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS0_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS1_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS2_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS3_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS4_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS5_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS6_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS7_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS8_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS9_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS10_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS11_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS12_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS13_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS14_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS15_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS16_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS17_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS18_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS19_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS20_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS21_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS22_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS23_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS24_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS25_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS26_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS27_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS28_GlitchData : VitalGlitchDataType; + variable C405PLBICUABUS29_GlitchData : VitalGlitchDataType; + variable C405PLBICUCACHEABLE_GlitchData : VitalGlitchDataType; + variable C405PLBICUPRIORITY0_GlitchData : VitalGlitchDataType; + variable C405PLBICUPRIORITY1_GlitchData : VitalGlitchDataType; + variable C405PLBICUREQUEST_GlitchData : VitalGlitchDataType; + variable C405PLBICUSIZE2_GlitchData : VitalGlitchDataType; + variable C405PLBICUSIZE3_GlitchData : VitalGlitchDataType; + variable C405PLBICUU0ATTR_GlitchData : VitalGlitchDataType; + variable C405RSTCHIPRESETREQ_GlitchData : VitalGlitchDataType; + variable C405RSTCORERESETREQ_GlitchData : VitalGlitchDataType; + variable C405RSTSYSRESETREQ_GlitchData : VitalGlitchDataType; + variable C405TRCCYCLE_GlitchData : VitalGlitchDataType; + variable C405TRCEVENEXECUTIONSTATUS0_GlitchData : VitalGlitchDataType; + variable C405TRCEVENEXECUTIONSTATUS1_GlitchData : VitalGlitchDataType; + variable C405TRCODDEXECUTIONSTATUS0_GlitchData : VitalGlitchDataType; + variable C405TRCODDEXECUTIONSTATUS1_GlitchData : VitalGlitchDataType; + variable C405TRCTRACESTATUS0_GlitchData : VitalGlitchDataType; + variable C405TRCTRACESTATUS1_GlitchData : VitalGlitchDataType; + variable C405TRCTRACESTATUS2_GlitchData : VitalGlitchDataType; + variable C405TRCTRACESTATUS3_GlitchData : VitalGlitchDataType; + variable C405TRCTRIGGEREVENTOUT_GlitchData : VitalGlitchDataType; + variable C405TRCTRIGGEREVENTTYPE0_GlitchData : VitalGlitchDataType; + variable C405TRCTRIGGEREVENTTYPE1_GlitchData : VitalGlitchDataType; + variable C405TRCTRIGGEREVENTTYPE2_GlitchData : VitalGlitchDataType; + variable C405TRCTRIGGEREVENTTYPE3_GlitchData : VitalGlitchDataType; + variable C405TRCTRIGGEREVENTTYPE4_GlitchData : VitalGlitchDataType; + variable C405TRCTRIGGEREVENTTYPE5_GlitchData : VitalGlitchDataType; + variable C405TRCTRIGGEREVENTTYPE6_GlitchData : VitalGlitchDataType; + variable C405TRCTRIGGEREVENTTYPE7_GlitchData : VitalGlitchDataType; + variable C405TRCTRIGGEREVENTTYPE8_GlitchData : VitalGlitchDataType; + variable C405TRCTRIGGEREVENTTYPE9_GlitchData : VitalGlitchDataType; + variable C405TRCTRIGGEREVENTTYPE10_GlitchData : VitalGlitchDataType; + variable C405XXXMACHINECHECK_GlitchData : VitalGlitchDataType; + variable DCREMACENABLER_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS8_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS9_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS10_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS11_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS12_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS13_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS14_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS15_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS16_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS17_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS18_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS19_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS20_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS21_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS22_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS23_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS24_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS25_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS26_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS27_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS28_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMABUS29_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMBYTEWRITE0_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMBYTEWRITE1_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMBYTEWRITE2_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMBYTEWRITE3_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMEN_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS0_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS1_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS2_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS3_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS4_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS5_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS6_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS7_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS8_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS9_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS10_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS11_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS12_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS13_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS14_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS15_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS16_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS17_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS18_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS19_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS20_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS21_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS22_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS23_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS24_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS25_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS26_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS27_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS28_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS29_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS30_GlitchData : VitalGlitchDataType; + variable DSOCMBRAMWRDBUS31_GlitchData : VitalGlitchDataType; + variable DSOCMBUSY_GlitchData : VitalGlitchDataType; + variable DSOCMRDADDRVALID_GlitchData : VitalGlitchDataType; + variable DSOCMWRADDRVALID_GlitchData : VitalGlitchDataType; + variable EXTDCRABUS0_GlitchData : VitalGlitchDataType; + variable EXTDCRABUS1_GlitchData : VitalGlitchDataType; + variable EXTDCRABUS2_GlitchData : VitalGlitchDataType; + variable EXTDCRABUS3_GlitchData : VitalGlitchDataType; + variable EXTDCRABUS4_GlitchData : VitalGlitchDataType; + variable EXTDCRABUS5_GlitchData : VitalGlitchDataType; + variable EXTDCRABUS6_GlitchData : VitalGlitchDataType; + variable EXTDCRABUS7_GlitchData : VitalGlitchDataType; + variable EXTDCRABUS8_GlitchData : VitalGlitchDataType; + variable EXTDCRABUS9_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT0_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT1_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT2_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT3_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT4_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT5_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT6_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT7_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT8_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT9_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT10_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT11_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT12_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT13_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT14_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT15_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT16_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT17_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT18_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT19_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT20_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT21_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT22_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT23_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT24_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT25_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT26_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT27_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT28_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT29_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT30_GlitchData : VitalGlitchDataType; + variable EXTDCRDBUSOUT31_GlitchData : VitalGlitchDataType; + variable EXTDCRREAD_GlitchData : VitalGlitchDataType; + variable EXTDCRWRITE_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMEN_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMEVENWRITEEN_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMODDWRITEEN_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS8_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS9_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS10_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS11_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS12_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS13_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS14_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS15_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS16_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS17_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS18_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS19_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS20_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS21_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS22_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS23_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS24_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS25_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS26_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS27_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMRDABUS28_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS8_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS9_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS10_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS11_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS12_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS13_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS14_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS15_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS16_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS17_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS18_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS19_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS20_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS21_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS22_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS23_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS24_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS25_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS26_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS27_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRABUS28_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS0_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS1_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS2_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS3_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS4_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS5_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS6_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS7_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS8_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS9_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS10_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS11_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS12_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS13_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS14_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS15_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS16_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS17_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS18_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS19_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS20_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS21_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS22_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS23_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS24_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS25_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS26_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS27_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS28_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS29_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS30_GlitchData : VitalGlitchDataType; + variable ISOCMBRAMWRDBUS31_GlitchData : VitalGlitchDataType; + variable ISOCMDCRBRAMEVENEN_GlitchData : VitalGlitchDataType; + variable ISOCMDCRBRAMODDEN_GlitchData : VitalGlitchDataType; + variable ISOCMDCRBRAMRDSELECT_GlitchData : VitalGlitchDataType; + variable DCREMACWRITE_GlitchData : VitalGlitchDataType; + variable DCREMACREAD_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS0_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS1_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS2_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS3_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS4_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS5_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS6_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS7_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS8_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS9_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS10_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS11_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS12_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS13_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS14_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS15_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS16_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS17_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS18_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS19_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS20_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS21_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS22_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS23_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS24_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS25_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS26_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS27_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS28_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS29_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS30_GlitchData : VitalGlitchDataType; + variable DCREMACDBUS31_GlitchData : VitalGlitchDataType; + variable DCREMACABUS8_GlitchData : VitalGlitchDataType; + variable DCREMACABUS9_GlitchData : VitalGlitchDataType; + variable DCREMACCLK_GlitchData : VitalGlitchDataType; +begin + + +-- Output-to-Clock path delay + VitalPathDelay01 + ( + OutSignal => APUFCMDECODED, + GlitchData => APUFCMDECODED_GlitchData, + OutSignalName => "APUFCMDECODED", + OutTemp => APUFCMDECODED_OUT, + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECUDIVALID, + GlitchData => APUFCMDECUDIVALID_GlitchData, + OutSignalName => "APUFCMDECUDIVALID", + OutTemp => APUFCMDECUDIVALID_OUT, + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMENDIAN, + GlitchData => APUFCMENDIAN_GlitchData, + OutSignalName => "APUFCMENDIAN", + OutTemp => APUFCMENDIAN_OUT, + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMFLUSH, + GlitchData => APUFCMFLUSH_GlitchData, + OutSignalName => "APUFCMFLUSH", + OutTemp => APUFCMFLUSH_OUT, + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRVALID, + GlitchData => APUFCMINSTRVALID_GlitchData, + OutSignalName => "APUFCMINSTRVALID", + OutTemp => APUFCMINSTRVALID_OUT, + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDVALID, + GlitchData => APUFCMLOADDVALID_GlitchData, + OutSignalName => "APUFCMLOADDVALID", + OutTemp => APUFCMLOADDVALID_OUT, + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMOPERANDVALID, + GlitchData => APUFCMOPERANDVALID_GlitchData, + OutSignalName => "APUFCMOPERANDVALID", + OutTemp => APUFCMOPERANDVALID_OUT, + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMWRITEBACKOK, + GlitchData => APUFCMWRITEBACKOK_GlitchData, + OutSignalName => "APUFCMWRITEBACKOK", + OutTemp => APUFCMWRITEBACKOK_OUT, + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMXERCA, + GlitchData => APUFCMXERCA_GlitchData, + OutSignalName => "APUFCMXERCA", + OutTemp => APUFCMXERCA_OUT, + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405CPMCORESLEEPREQ, + GlitchData => C405CPMCORESLEEPREQ_GlitchData, + OutSignalName => "C405CPMCORESLEEPREQ", + OutTemp => C405CPMCORESLEEPREQ_OUT, + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405CPMMSRCE, + GlitchData => C405CPMMSRCE_GlitchData, + OutSignalName => "C405CPMMSRCE", + OutTemp => C405CPMMSRCE_OUT, + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405CPMMSREE, + GlitchData => C405CPMMSREE_GlitchData, + OutSignalName => "C405CPMMSREE", + OutTemp => C405CPMMSREE_OUT, + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405CPMTIMERIRQ, + GlitchData => C405CPMTIMERIRQ_GlitchData, + OutSignalName => "C405CPMTIMERIRQ", + OutTemp => C405CPMTIMERIRQ_OUT, + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405CPMTIMERRESETREQ, + GlitchData => C405CPMTIMERRESETREQ_GlitchData, + OutSignalName => "C405CPMTIMERRESETREQ", + OutTemp => C405CPMTIMERRESETREQ_OUT, + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGLOADDATAONAPUDBUS, + GlitchData => C405DBGLOADDATAONAPUDBUS_GlitchData, + OutSignalName => "C405DBGLOADDATAONAPUDBUS", + OutTemp => C405DBGLOADDATAONAPUDBUS_OUT, + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGMSRWE, + GlitchData => C405DBGMSRWE_GlitchData, + OutSignalName => "C405DBGMSRWE", + OutTemp => C405DBGMSRWE_OUT, + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGSTOPACK, + GlitchData => C405DBGSTOPACK_GlitchData, + OutSignalName => "C405DBGSTOPACK", + OutTemp => C405DBGSTOPACK_OUT, + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBCOMPLETE, + GlitchData => C405DBGWBCOMPLETE_GlitchData, + OutSignalName => "C405DBGWBCOMPLETE", + OutTemp => C405DBGWBCOMPLETE_OUT, + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBFULL, + GlitchData => C405DBGWBFULL_GlitchData, + OutSignalName => "C405DBGWBFULL", + OutTemp => C405DBGWBFULL_OUT, + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405JTGCAPTUREDR, + GlitchData => C405JTGCAPTUREDR_GlitchData, + OutSignalName => "C405JTGCAPTUREDR", + OutTemp => C405JTGCAPTUREDR_OUT, + Paths => (0 => (JTGC405TCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405JTGEXTEST, + GlitchData => C405JTGEXTEST_GlitchData, + OutSignalName => "C405JTGEXTEST", + OutTemp => C405JTGEXTEST_OUT, + Paths => (0 => (JTGC405TCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405JTGPGMOUT, + GlitchData => C405JTGPGMOUT_GlitchData, + OutSignalName => "C405JTGPGMOUT", + OutTemp => C405JTGPGMOUT_OUT, + Paths => (0 => (JTGC405TCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405JTGSHIFTDR, + GlitchData => C405JTGSHIFTDR_GlitchData, + OutSignalName => "C405JTGSHIFTDR", + OutTemp => C405JTGSHIFTDR_OUT, + Paths => (0 => (JTGC405TCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405JTGTDO, + GlitchData => C405JTGTDO_GlitchData, + OutSignalName => "C405JTGTDO", + OutTemp => C405JTGTDO_OUT, + Paths => (0 => (JTGC405TCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405JTGTDOEN, + GlitchData => C405JTGTDOEN_GlitchData, + OutSignalName => "C405JTGTDOEN", + OutTemp => C405JTGTDOEN_OUT, + Paths => (0 => (JTGC405TCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405JTGUPDATEDR, + GlitchData => C405JTGUPDATEDR_GlitchData, + OutSignalName => "C405JTGUPDATEDR", + OutTemp => C405JTGUPDATEDR_OUT, + Paths => (0 => (JTGC405TCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABORT, + GlitchData => C405PLBDCUABORT_GlitchData, + OutSignalName => "C405PLBDCUABORT", + OutTemp => C405PLBDCUABORT_OUT, + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUCACHEABLE, + GlitchData => C405PLBDCUCACHEABLE_GlitchData, + OutSignalName => "C405PLBDCUCACHEABLE", + OutTemp => C405PLBDCUCACHEABLE_OUT, + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUGUARDED, + GlitchData => C405PLBDCUGUARDED_GlitchData, + OutSignalName => "C405PLBDCUGUARDED", + OutTemp => C405PLBDCUGUARDED_OUT, + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUREQUEST, + GlitchData => C405PLBDCUREQUEST_GlitchData, + OutSignalName => "C405PLBDCUREQUEST", + OutTemp => C405PLBDCUREQUEST_OUT, + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCURNW, + GlitchData => C405PLBDCURNW_GlitchData, + OutSignalName => "C405PLBDCURNW", + OutTemp => C405PLBDCURNW_OUT, + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUSIZE2, + GlitchData => C405PLBDCUSIZE2_GlitchData, + OutSignalName => "C405PLBDCUSIZE2", + OutTemp => C405PLBDCUSIZE2_OUT, + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUU0ATTR, + GlitchData => C405PLBDCUU0ATTR_GlitchData, + OutSignalName => "C405PLBDCUU0ATTR", + OutTemp => C405PLBDCUU0ATTR_OUT, + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRITETHRU, + GlitchData => C405PLBDCUWRITETHRU_GlitchData, + OutSignalName => "C405PLBDCUWRITETHRU", + OutTemp => C405PLBDCUWRITETHRU_OUT, + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABORT, + GlitchData => C405PLBICUABORT_GlitchData, + OutSignalName => "C405PLBICUABORT", + OutTemp => C405PLBICUABORT_OUT, + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUCACHEABLE, + GlitchData => C405PLBICUCACHEABLE_GlitchData, + OutSignalName => "C405PLBICUCACHEABLE", + OutTemp => C405PLBICUCACHEABLE_OUT, + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUREQUEST, + GlitchData => C405PLBICUREQUEST_GlitchData, + OutSignalName => "C405PLBICUREQUEST", + OutTemp => C405PLBICUREQUEST_OUT, + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUU0ATTR, + GlitchData => C405PLBICUU0ATTR_GlitchData, + OutSignalName => "C405PLBICUU0ATTR", + OutTemp => C405PLBICUU0ATTR_OUT, + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405RSTCHIPRESETREQ, + GlitchData => C405RSTCHIPRESETREQ_GlitchData, + OutSignalName => "C405RSTCHIPRESETREQ", + OutTemp => C405RSTCHIPRESETREQ_OUT, + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405RSTCORERESETREQ, + GlitchData => C405RSTCORERESETREQ_GlitchData, + OutSignalName => "C405RSTCORERESETREQ", + OutTemp => C405RSTCORERESETREQ_OUT, + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405RSTSYSRESETREQ, + GlitchData => C405RSTSYSRESETREQ_GlitchData, + OutSignalName => "C405RSTSYSRESETREQ", + OutTemp => C405RSTSYSRESETREQ_OUT, + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCCYCLE, + GlitchData => C405TRCCYCLE_GlitchData, + OutSignalName => "C405TRCCYCLE", + OutTemp => C405TRCCYCLE_OUT, + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCTRIGGEREVENTOUT, + GlitchData => C405TRCTRIGGEREVENTOUT_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTOUT", + OutTemp => C405TRCTRIGGEREVENTOUT_OUT, + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405XXXMACHINECHECK, + GlitchData => C405XXXMACHINECHECK_GlitchData, + OutSignalName => "C405XXXMACHINECHECK", + OutTemp => C405XXXMACHINECHECK_OUT, + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMEN, + GlitchData => DSOCMBRAMEN_GlitchData, + OutSignalName => "DSOCMBRAMEN", + OutTemp => DSOCMBRAMEN_OUT, + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBUSY, + GlitchData => DSOCMBUSY_GlitchData, + OutSignalName => "DSOCMBUSY", + OutTemp => DSOCMBUSY_OUT, + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMRDADDRVALID, + GlitchData => DSOCMRDADDRVALID_GlitchData, + OutSignalName => "DSOCMRDADDRVALID", + OutTemp => DSOCMRDADDRVALID_OUT, + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMWRADDRVALID, + GlitchData => DSOCMWRADDRVALID_GlitchData, + OutSignalName => "DSOCMWRADDRVALID", + OutTemp => DSOCMWRADDRVALID_OUT, + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRREAD, + GlitchData => EXTDCRREAD_GlitchData, + OutSignalName => "EXTDCRREAD", + OutTemp => EXTDCRREAD_OUT, + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRWRITE, + GlitchData => EXTDCRWRITE_GlitchData, + OutSignalName => "EXTDCRWRITE", + OutTemp => EXTDCRWRITE_OUT, + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMEN, + GlitchData => ISOCMBRAMEN_GlitchData, + OutSignalName => "ISOCMBRAMEN", + OutTemp => ISOCMBRAMEN_OUT, + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMEVENWRITEEN, + GlitchData => ISOCMBRAMEVENWRITEEN_GlitchData, + OutSignalName => "ISOCMBRAMEVENWRITEEN", + OutTemp => ISOCMBRAMEVENWRITEEN_OUT, + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMODDWRITEEN, + GlitchData => ISOCMBRAMODDWRITEEN_GlitchData, + OutSignalName => "ISOCMBRAMODDWRITEEN", + OutTemp => ISOCMBRAMODDWRITEEN_OUT, + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMDCRBRAMEVENEN, + GlitchData => ISOCMDCRBRAMEVENEN_GlitchData, + OutSignalName => "ISOCMDCRBRAMEVENEN", + OutTemp => ISOCMDCRBRAMEVENEN_OUT, + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMDCRBRAMODDEN, + GlitchData => ISOCMDCRBRAMODDEN_GlitchData, + OutSignalName => "ISOCMDCRBRAMODDEN", + OutTemp => ISOCMDCRBRAMODDEN_OUT, + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMDCRBRAMRDSELECT, + GlitchData => ISOCMDCRBRAMRDSELECT_GlitchData, + OutSignalName => "ISOCMDCRBRAMRDSELECT", + OutTemp => ISOCMDCRBRAMRDSELECT_OUT, + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + +----- bused outputs + VitalPathDelay01 + ( + OutSignal => APUFCMDECUDI(0), + GlitchData => APUFCMDECUDI0_GlitchData, + OutSignalName => "APUFCMDECUDI(0)", + OutTemp => APUFCMDECUDI_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECUDI(1), + GlitchData => APUFCMDECUDI1_GlitchData, + OutSignalName => "APUFCMDECUDI(1)", + OutTemp => APUFCMDECUDI_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECUDI(2), + GlitchData => APUFCMDECUDI2_GlitchData, + OutSignalName => "APUFCMDECUDI(2)", + OutTemp => APUFCMDECUDI_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(0), + GlitchData => APUFCMINSTRUCTION0_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(0)", + OutTemp => APUFCMINSTRUCTION_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(1), + GlitchData => APUFCMINSTRUCTION1_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(1)", + OutTemp => APUFCMINSTRUCTION_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(2), + GlitchData => APUFCMINSTRUCTION2_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(2)", + OutTemp => APUFCMINSTRUCTION_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(3), + GlitchData => APUFCMINSTRUCTION3_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(3)", + OutTemp => APUFCMINSTRUCTION_OUT(3), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(4), + GlitchData => APUFCMINSTRUCTION4_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(4)", + OutTemp => APUFCMINSTRUCTION_OUT(4), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(5), + GlitchData => APUFCMINSTRUCTION5_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(5)", + OutTemp => APUFCMINSTRUCTION_OUT(5), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(6), + GlitchData => APUFCMINSTRUCTION6_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(6)", + OutTemp => APUFCMINSTRUCTION_OUT(6), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(7), + GlitchData => APUFCMINSTRUCTION7_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(7)", + OutTemp => APUFCMINSTRUCTION_OUT(7), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(8), + GlitchData => APUFCMINSTRUCTION8_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(8)", + OutTemp => APUFCMINSTRUCTION_OUT(8), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(9), + GlitchData => APUFCMINSTRUCTION9_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(9)", + OutTemp => APUFCMINSTRUCTION_OUT(9), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(10), + GlitchData => APUFCMINSTRUCTION10_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(10)", + OutTemp => APUFCMINSTRUCTION_OUT(10), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(11), + GlitchData => APUFCMINSTRUCTION11_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(11)", + OutTemp => APUFCMINSTRUCTION_OUT(11), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(12), + GlitchData => APUFCMINSTRUCTION12_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(12)", + OutTemp => APUFCMINSTRUCTION_OUT(12), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(13), + GlitchData => APUFCMINSTRUCTION13_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(13)", + OutTemp => APUFCMINSTRUCTION_OUT(13), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(14), + GlitchData => APUFCMINSTRUCTION14_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(14)", + OutTemp => APUFCMINSTRUCTION_OUT(14), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(15), + GlitchData => APUFCMINSTRUCTION15_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(15)", + OutTemp => APUFCMINSTRUCTION_OUT(15), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(16), + GlitchData => APUFCMINSTRUCTION16_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(16)", + OutTemp => APUFCMINSTRUCTION_OUT(16), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(17), + GlitchData => APUFCMINSTRUCTION17_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(17)", + OutTemp => APUFCMINSTRUCTION_OUT(17), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(18), + GlitchData => APUFCMINSTRUCTION18_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(18)", + OutTemp => APUFCMINSTRUCTION_OUT(18), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(19), + GlitchData => APUFCMINSTRUCTION19_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(19)", + OutTemp => APUFCMINSTRUCTION_OUT(19), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(20), + GlitchData => APUFCMINSTRUCTION20_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(20)", + OutTemp => APUFCMINSTRUCTION_OUT(20), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(21), + GlitchData => APUFCMINSTRUCTION21_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(21)", + OutTemp => APUFCMINSTRUCTION_OUT(21), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(22), + GlitchData => APUFCMINSTRUCTION22_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(22)", + OutTemp => APUFCMINSTRUCTION_OUT(22), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(23), + GlitchData => APUFCMINSTRUCTION23_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(23)", + OutTemp => APUFCMINSTRUCTION_OUT(23), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(24), + GlitchData => APUFCMINSTRUCTION24_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(24)", + OutTemp => APUFCMINSTRUCTION_OUT(24), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(25), + GlitchData => APUFCMINSTRUCTION25_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(25)", + OutTemp => APUFCMINSTRUCTION_OUT(25), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(26), + GlitchData => APUFCMINSTRUCTION26_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(26)", + OutTemp => APUFCMINSTRUCTION_OUT(26), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(27), + GlitchData => APUFCMINSTRUCTION27_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(27)", + OutTemp => APUFCMINSTRUCTION_OUT(27), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(28), + GlitchData => APUFCMINSTRUCTION28_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(28)", + OutTemp => APUFCMINSTRUCTION_OUT(28), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(29), + GlitchData => APUFCMINSTRUCTION29_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(29)", + OutTemp => APUFCMINSTRUCTION_OUT(29), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(30), + GlitchData => APUFCMINSTRUCTION30_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(30)", + OutTemp => APUFCMINSTRUCTION_OUT(30), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(31), + GlitchData => APUFCMINSTRUCTION31_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(31)", + OutTemp => APUFCMINSTRUCTION_OUT(31), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADBYTEEN(0), + GlitchData => APUFCMLOADBYTEEN0_GlitchData, + OutSignalName => "APUFCMLOADBYTEEN(0)", + OutTemp => APUFCMLOADBYTEEN_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADBYTEEN(1), + GlitchData => APUFCMLOADBYTEEN1_GlitchData, + OutSignalName => "APUFCMLOADBYTEEN(1)", + OutTemp => APUFCMLOADBYTEEN_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADBYTEEN(2), + GlitchData => APUFCMLOADBYTEEN2_GlitchData, + OutSignalName => "APUFCMLOADBYTEEN(2)", + OutTemp => APUFCMLOADBYTEEN_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADBYTEEN(3), + GlitchData => APUFCMLOADBYTEEN3_GlitchData, + OutSignalName => "APUFCMLOADBYTEEN(3)", + OutTemp => APUFCMLOADBYTEEN_OUT(3), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(0), + GlitchData => APUFCMLOADDATA0_GlitchData, + OutSignalName => "APUFCMLOADDATA(0)", + OutTemp => APUFCMLOADDATA_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(1), + GlitchData => APUFCMLOADDATA1_GlitchData, + OutSignalName => "APUFCMLOADDATA(1)", + OutTemp => APUFCMLOADDATA_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(2), + GlitchData => APUFCMLOADDATA2_GlitchData, + OutSignalName => "APUFCMLOADDATA(2)", + OutTemp => APUFCMLOADDATA_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(3), + GlitchData => APUFCMLOADDATA3_GlitchData, + OutSignalName => "APUFCMLOADDATA(3)", + OutTemp => APUFCMLOADDATA_OUT(3), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(4), + GlitchData => APUFCMLOADDATA4_GlitchData, + OutSignalName => "APUFCMLOADDATA(4)", + OutTemp => APUFCMLOADDATA_OUT(4), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(5), + GlitchData => APUFCMLOADDATA5_GlitchData, + OutSignalName => "APUFCMLOADDATA(5)", + OutTemp => APUFCMLOADDATA_OUT(5), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(6), + GlitchData => APUFCMLOADDATA6_GlitchData, + OutSignalName => "APUFCMLOADDATA(6)", + OutTemp => APUFCMLOADDATA_OUT(6), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(7), + GlitchData => APUFCMLOADDATA7_GlitchData, + OutSignalName => "APUFCMLOADDATA(7)", + OutTemp => APUFCMLOADDATA_OUT(7), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(8), + GlitchData => APUFCMLOADDATA8_GlitchData, + OutSignalName => "APUFCMLOADDATA(8)", + OutTemp => APUFCMLOADDATA_OUT(8), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(9), + GlitchData => APUFCMLOADDATA9_GlitchData, + OutSignalName => "APUFCMLOADDATA(9)", + OutTemp => APUFCMLOADDATA_OUT(9), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(10), + GlitchData => APUFCMLOADDATA10_GlitchData, + OutSignalName => "APUFCMLOADDATA(10)", + OutTemp => APUFCMLOADDATA_OUT(10), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(11), + GlitchData => APUFCMLOADDATA11_GlitchData, + OutSignalName => "APUFCMLOADDATA(11)", + OutTemp => APUFCMLOADDATA_OUT(11), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(12), + GlitchData => APUFCMLOADDATA12_GlitchData, + OutSignalName => "APUFCMLOADDATA(12)", + OutTemp => APUFCMLOADDATA_OUT(12), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(13), + GlitchData => APUFCMLOADDATA13_GlitchData, + OutSignalName => "APUFCMLOADDATA(13)", + OutTemp => APUFCMLOADDATA_OUT(13), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(14), + GlitchData => APUFCMLOADDATA14_GlitchData, + OutSignalName => "APUFCMLOADDATA(14)", + OutTemp => APUFCMLOADDATA_OUT(14), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(15), + GlitchData => APUFCMLOADDATA15_GlitchData, + OutSignalName => "APUFCMLOADDATA(15)", + OutTemp => APUFCMLOADDATA_OUT(15), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(16), + GlitchData => APUFCMLOADDATA16_GlitchData, + OutSignalName => "APUFCMLOADDATA(16)", + OutTemp => APUFCMLOADDATA_OUT(16), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(17), + GlitchData => APUFCMLOADDATA17_GlitchData, + OutSignalName => "APUFCMLOADDATA(17)", + OutTemp => APUFCMLOADDATA_OUT(17), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(18), + GlitchData => APUFCMLOADDATA18_GlitchData, + OutSignalName => "APUFCMLOADDATA(18)", + OutTemp => APUFCMLOADDATA_OUT(18), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(19), + GlitchData => APUFCMLOADDATA19_GlitchData, + OutSignalName => "APUFCMLOADDATA(19)", + OutTemp => APUFCMLOADDATA_OUT(19), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(20), + GlitchData => APUFCMLOADDATA20_GlitchData, + OutSignalName => "APUFCMLOADDATA(20)", + OutTemp => APUFCMLOADDATA_OUT(20), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(21), + GlitchData => APUFCMLOADDATA21_GlitchData, + OutSignalName => "APUFCMLOADDATA(21)", + OutTemp => APUFCMLOADDATA_OUT(21), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(22), + GlitchData => APUFCMLOADDATA22_GlitchData, + OutSignalName => "APUFCMLOADDATA(22)", + OutTemp => APUFCMLOADDATA_OUT(22), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(23), + GlitchData => APUFCMLOADDATA23_GlitchData, + OutSignalName => "APUFCMLOADDATA(23)", + OutTemp => APUFCMLOADDATA_OUT(23), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(24), + GlitchData => APUFCMLOADDATA24_GlitchData, + OutSignalName => "APUFCMLOADDATA(24)", + OutTemp => APUFCMLOADDATA_OUT(24), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(25), + GlitchData => APUFCMLOADDATA25_GlitchData, + OutSignalName => "APUFCMLOADDATA(25)", + OutTemp => APUFCMLOADDATA_OUT(25), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(26), + GlitchData => APUFCMLOADDATA26_GlitchData, + OutSignalName => "APUFCMLOADDATA(26)", + OutTemp => APUFCMLOADDATA_OUT(26), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(27), + GlitchData => APUFCMLOADDATA27_GlitchData, + OutSignalName => "APUFCMLOADDATA(27)", + OutTemp => APUFCMLOADDATA_OUT(27), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(28), + GlitchData => APUFCMLOADDATA28_GlitchData, + OutSignalName => "APUFCMLOADDATA(28)", + OutTemp => APUFCMLOADDATA_OUT(28), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(29), + GlitchData => APUFCMLOADDATA29_GlitchData, + OutSignalName => "APUFCMLOADDATA(29)", + OutTemp => APUFCMLOADDATA_OUT(29), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(30), + GlitchData => APUFCMLOADDATA30_GlitchData, + OutSignalName => "APUFCMLOADDATA(30)", + OutTemp => APUFCMLOADDATA_OUT(30), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(31), + GlitchData => APUFCMLOADDATA31_GlitchData, + OutSignalName => "APUFCMLOADDATA(31)", + OutTemp => APUFCMLOADDATA_OUT(31), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(0), + GlitchData => APUFCMRADATA0_GlitchData, + OutSignalName => "APUFCMRADATA(0)", + OutTemp => APUFCMRADATA_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(1), + GlitchData => APUFCMRADATA1_GlitchData, + OutSignalName => "APUFCMRADATA(1)", + OutTemp => APUFCMRADATA_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(2), + GlitchData => APUFCMRADATA2_GlitchData, + OutSignalName => "APUFCMRADATA(2)", + OutTemp => APUFCMRADATA_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(3), + GlitchData => APUFCMRADATA3_GlitchData, + OutSignalName => "APUFCMRADATA(3)", + OutTemp => APUFCMRADATA_OUT(3), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(4), + GlitchData => APUFCMRADATA4_GlitchData, + OutSignalName => "APUFCMRADATA(4)", + OutTemp => APUFCMRADATA_OUT(4), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(5), + GlitchData => APUFCMRADATA5_GlitchData, + OutSignalName => "APUFCMRADATA(5)", + OutTemp => APUFCMRADATA_OUT(5), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(6), + GlitchData => APUFCMRADATA6_GlitchData, + OutSignalName => "APUFCMRADATA(6)", + OutTemp => APUFCMRADATA_OUT(6), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(7), + GlitchData => APUFCMRADATA7_GlitchData, + OutSignalName => "APUFCMRADATA(7)", + OutTemp => APUFCMRADATA_OUT(7), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(8), + GlitchData => APUFCMRADATA8_GlitchData, + OutSignalName => "APUFCMRADATA(8)", + OutTemp => APUFCMRADATA_OUT(8), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(9), + GlitchData => APUFCMRADATA9_GlitchData, + OutSignalName => "APUFCMRADATA(9)", + OutTemp => APUFCMRADATA_OUT(9), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(10), + GlitchData => APUFCMRADATA10_GlitchData, + OutSignalName => "APUFCMRADATA(10)", + OutTemp => APUFCMRADATA_OUT(10), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(11), + GlitchData => APUFCMRADATA11_GlitchData, + OutSignalName => "APUFCMRADATA(11)", + OutTemp => APUFCMRADATA_OUT(11), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(12), + GlitchData => APUFCMRADATA12_GlitchData, + OutSignalName => "APUFCMRADATA(12)", + OutTemp => APUFCMRADATA_OUT(12), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(13), + GlitchData => APUFCMRADATA13_GlitchData, + OutSignalName => "APUFCMRADATA(13)", + OutTemp => APUFCMRADATA_OUT(13), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(14), + GlitchData => APUFCMRADATA14_GlitchData, + OutSignalName => "APUFCMRADATA(14)", + OutTemp => APUFCMRADATA_OUT(14), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(15), + GlitchData => APUFCMRADATA15_GlitchData, + OutSignalName => "APUFCMRADATA(15)", + OutTemp => APUFCMRADATA_OUT(15), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(16), + GlitchData => APUFCMRADATA16_GlitchData, + OutSignalName => "APUFCMRADATA(16)", + OutTemp => APUFCMRADATA_OUT(16), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(17), + GlitchData => APUFCMRADATA17_GlitchData, + OutSignalName => "APUFCMRADATA(17)", + OutTemp => APUFCMRADATA_OUT(17), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(18), + GlitchData => APUFCMRADATA18_GlitchData, + OutSignalName => "APUFCMRADATA(18)", + OutTemp => APUFCMRADATA_OUT(18), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(19), + GlitchData => APUFCMRADATA19_GlitchData, + OutSignalName => "APUFCMRADATA(19)", + OutTemp => APUFCMRADATA_OUT(19), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(20), + GlitchData => APUFCMRADATA20_GlitchData, + OutSignalName => "APUFCMRADATA(20)", + OutTemp => APUFCMRADATA_OUT(20), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(21), + GlitchData => APUFCMRADATA21_GlitchData, + OutSignalName => "APUFCMRADATA(21)", + OutTemp => APUFCMRADATA_OUT(21), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(22), + GlitchData => APUFCMRADATA22_GlitchData, + OutSignalName => "APUFCMRADATA(22)", + OutTemp => APUFCMRADATA_OUT(22), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(23), + GlitchData => APUFCMRADATA23_GlitchData, + OutSignalName => "APUFCMRADATA(23)", + OutTemp => APUFCMRADATA_OUT(23), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(24), + GlitchData => APUFCMRADATA24_GlitchData, + OutSignalName => "APUFCMRADATA(24)", + OutTemp => APUFCMRADATA_OUT(24), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(25), + GlitchData => APUFCMRADATA25_GlitchData, + OutSignalName => "APUFCMRADATA(25)", + OutTemp => APUFCMRADATA_OUT(25), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(26), + GlitchData => APUFCMRADATA26_GlitchData, + OutSignalName => "APUFCMRADATA(26)", + OutTemp => APUFCMRADATA_OUT(26), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(27), + GlitchData => APUFCMRADATA27_GlitchData, + OutSignalName => "APUFCMRADATA(27)", + OutTemp => APUFCMRADATA_OUT(27), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(28), + GlitchData => APUFCMRADATA28_GlitchData, + OutSignalName => "APUFCMRADATA(28)", + OutTemp => APUFCMRADATA_OUT(28), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(29), + GlitchData => APUFCMRADATA29_GlitchData, + OutSignalName => "APUFCMRADATA(29)", + OutTemp => APUFCMRADATA_OUT(29), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(30), + GlitchData => APUFCMRADATA30_GlitchData, + OutSignalName => "APUFCMRADATA(30)", + OutTemp => APUFCMRADATA_OUT(30), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(31), + GlitchData => APUFCMRADATA31_GlitchData, + OutSignalName => "APUFCMRADATA(31)", + OutTemp => APUFCMRADATA_OUT(31), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(0), + GlitchData => APUFCMRBDATA0_GlitchData, + OutSignalName => "APUFCMRBDATA(0)", + OutTemp => APUFCMRBDATA_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(1), + GlitchData => APUFCMRBDATA1_GlitchData, + OutSignalName => "APUFCMRBDATA(1)", + OutTemp => APUFCMRBDATA_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(2), + GlitchData => APUFCMRBDATA2_GlitchData, + OutSignalName => "APUFCMRBDATA(2)", + OutTemp => APUFCMRBDATA_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(3), + GlitchData => APUFCMRBDATA3_GlitchData, + OutSignalName => "APUFCMRBDATA(3)", + OutTemp => APUFCMRBDATA_OUT(3), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(4), + GlitchData => APUFCMRBDATA4_GlitchData, + OutSignalName => "APUFCMRBDATA(4)", + OutTemp => APUFCMRBDATA_OUT(4), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(5), + GlitchData => APUFCMRBDATA5_GlitchData, + OutSignalName => "APUFCMRBDATA(5)", + OutTemp => APUFCMRBDATA_OUT(5), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(6), + GlitchData => APUFCMRBDATA6_GlitchData, + OutSignalName => "APUFCMRBDATA(6)", + OutTemp => APUFCMRBDATA_OUT(6), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(7), + GlitchData => APUFCMRBDATA7_GlitchData, + OutSignalName => "APUFCMRBDATA(7)", + OutTemp => APUFCMRBDATA_OUT(7), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(8), + GlitchData => APUFCMRBDATA8_GlitchData, + OutSignalName => "APUFCMRBDATA(8)", + OutTemp => APUFCMRBDATA_OUT(8), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(9), + GlitchData => APUFCMRBDATA9_GlitchData, + OutSignalName => "APUFCMRBDATA(9)", + OutTemp => APUFCMRBDATA_OUT(9), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(10), + GlitchData => APUFCMRBDATA10_GlitchData, + OutSignalName => "APUFCMRBDATA(10)", + OutTemp => APUFCMRBDATA_OUT(10), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(11), + GlitchData => APUFCMRBDATA11_GlitchData, + OutSignalName => "APUFCMRBDATA(11)", + OutTemp => APUFCMRBDATA_OUT(11), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(12), + GlitchData => APUFCMRBDATA12_GlitchData, + OutSignalName => "APUFCMRBDATA(12)", + OutTemp => APUFCMRBDATA_OUT(12), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(13), + GlitchData => APUFCMRBDATA13_GlitchData, + OutSignalName => "APUFCMRBDATA(13)", + OutTemp => APUFCMRBDATA_OUT(13), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(14), + GlitchData => APUFCMRBDATA14_GlitchData, + OutSignalName => "APUFCMRBDATA(14)", + OutTemp => APUFCMRBDATA_OUT(14), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(15), + GlitchData => APUFCMRBDATA15_GlitchData, + OutSignalName => "APUFCMRBDATA(15)", + OutTemp => APUFCMRBDATA_OUT(15), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(16), + GlitchData => APUFCMRBDATA16_GlitchData, + OutSignalName => "APUFCMRBDATA(16)", + OutTemp => APUFCMRBDATA_OUT(16), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(17), + GlitchData => APUFCMRBDATA17_GlitchData, + OutSignalName => "APUFCMRBDATA(17)", + OutTemp => APUFCMRBDATA_OUT(17), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(18), + GlitchData => APUFCMRBDATA18_GlitchData, + OutSignalName => "APUFCMRBDATA(18)", + OutTemp => APUFCMRBDATA_OUT(18), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(19), + GlitchData => APUFCMRBDATA19_GlitchData, + OutSignalName => "APUFCMRBDATA(19)", + OutTemp => APUFCMRBDATA_OUT(19), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(20), + GlitchData => APUFCMRBDATA20_GlitchData, + OutSignalName => "APUFCMRBDATA(20)", + OutTemp => APUFCMRBDATA_OUT(20), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(21), + GlitchData => APUFCMRBDATA21_GlitchData, + OutSignalName => "APUFCMRBDATA(21)", + OutTemp => APUFCMRBDATA_OUT(21), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(22), + GlitchData => APUFCMRBDATA22_GlitchData, + OutSignalName => "APUFCMRBDATA(22)", + OutTemp => APUFCMRBDATA_OUT(22), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(23), + GlitchData => APUFCMRBDATA23_GlitchData, + OutSignalName => "APUFCMRBDATA(23)", + OutTemp => APUFCMRBDATA_OUT(23), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(24), + GlitchData => APUFCMRBDATA24_GlitchData, + OutSignalName => "APUFCMRBDATA(24)", + OutTemp => APUFCMRBDATA_OUT(24), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(25), + GlitchData => APUFCMRBDATA25_GlitchData, + OutSignalName => "APUFCMRBDATA(25)", + OutTemp => APUFCMRBDATA_OUT(25), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(26), + GlitchData => APUFCMRBDATA26_GlitchData, + OutSignalName => "APUFCMRBDATA(26)", + OutTemp => APUFCMRBDATA_OUT(26), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(27), + GlitchData => APUFCMRBDATA27_GlitchData, + OutSignalName => "APUFCMRBDATA(27)", + OutTemp => APUFCMRBDATA_OUT(27), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(28), + GlitchData => APUFCMRBDATA28_GlitchData, + OutSignalName => "APUFCMRBDATA(28)", + OutTemp => APUFCMRBDATA_OUT(28), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(29), + GlitchData => APUFCMRBDATA29_GlitchData, + OutSignalName => "APUFCMRBDATA(29)", + OutTemp => APUFCMRBDATA_OUT(29), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(30), + GlitchData => APUFCMRBDATA30_GlitchData, + OutSignalName => "APUFCMRBDATA(30)", + OutTemp => APUFCMRBDATA_OUT(30), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(31), + GlitchData => APUFCMRBDATA31_GlitchData, + OutSignalName => "APUFCMRBDATA(31)", + OutTemp => APUFCMRBDATA_OUT(31), + Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(0), + GlitchData => C405DBGWBIAR0_GlitchData, + OutSignalName => "C405DBGWBIAR(0)", + OutTemp => C405DBGWBIAR_OUT(0), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(1), + GlitchData => C405DBGWBIAR1_GlitchData, + OutSignalName => "C405DBGWBIAR(1)", + OutTemp => C405DBGWBIAR_OUT(1), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(2), + GlitchData => C405DBGWBIAR2_GlitchData, + OutSignalName => "C405DBGWBIAR(2)", + OutTemp => C405DBGWBIAR_OUT(2), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(3), + GlitchData => C405DBGWBIAR3_GlitchData, + OutSignalName => "C405DBGWBIAR(3)", + OutTemp => C405DBGWBIAR_OUT(3), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(4), + GlitchData => C405DBGWBIAR4_GlitchData, + OutSignalName => "C405DBGWBIAR(4)", + OutTemp => C405DBGWBIAR_OUT(4), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(5), + GlitchData => C405DBGWBIAR5_GlitchData, + OutSignalName => "C405DBGWBIAR(5)", + OutTemp => C405DBGWBIAR_OUT(5), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(6), + GlitchData => C405DBGWBIAR6_GlitchData, + OutSignalName => "C405DBGWBIAR(6)", + OutTemp => C405DBGWBIAR_OUT(6), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(7), + GlitchData => C405DBGWBIAR7_GlitchData, + OutSignalName => "C405DBGWBIAR(7)", + OutTemp => C405DBGWBIAR_OUT(7), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(8), + GlitchData => C405DBGWBIAR8_GlitchData, + OutSignalName => "C405DBGWBIAR(8)", + OutTemp => C405DBGWBIAR_OUT(8), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(9), + GlitchData => C405DBGWBIAR9_GlitchData, + OutSignalName => "C405DBGWBIAR(9)", + OutTemp => C405DBGWBIAR_OUT(9), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(10), + GlitchData => C405DBGWBIAR10_GlitchData, + OutSignalName => "C405DBGWBIAR(10)", + OutTemp => C405DBGWBIAR_OUT(10), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(11), + GlitchData => C405DBGWBIAR11_GlitchData, + OutSignalName => "C405DBGWBIAR(11)", + OutTemp => C405DBGWBIAR_OUT(11), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(12), + GlitchData => C405DBGWBIAR12_GlitchData, + OutSignalName => "C405DBGWBIAR(12)", + OutTemp => C405DBGWBIAR_OUT(12), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(13), + GlitchData => C405DBGWBIAR13_GlitchData, + OutSignalName => "C405DBGWBIAR(13)", + OutTemp => C405DBGWBIAR_OUT(13), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(14), + GlitchData => C405DBGWBIAR14_GlitchData, + OutSignalName => "C405DBGWBIAR(14)", + OutTemp => C405DBGWBIAR_OUT(14), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(15), + GlitchData => C405DBGWBIAR15_GlitchData, + OutSignalName => "C405DBGWBIAR(15)", + OutTemp => C405DBGWBIAR_OUT(15), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(16), + GlitchData => C405DBGWBIAR16_GlitchData, + OutSignalName => "C405DBGWBIAR(16)", + OutTemp => C405DBGWBIAR_OUT(16), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(17), + GlitchData => C405DBGWBIAR17_GlitchData, + OutSignalName => "C405DBGWBIAR(17)", + OutTemp => C405DBGWBIAR_OUT(17), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(18), + GlitchData => C405DBGWBIAR18_GlitchData, + OutSignalName => "C405DBGWBIAR(18)", + OutTemp => C405DBGWBIAR_OUT(18), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(19), + GlitchData => C405DBGWBIAR19_GlitchData, + OutSignalName => "C405DBGWBIAR(19)", + OutTemp => C405DBGWBIAR_OUT(19), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(20), + GlitchData => C405DBGWBIAR20_GlitchData, + OutSignalName => "C405DBGWBIAR(20)", + OutTemp => C405DBGWBIAR_OUT(20), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(21), + GlitchData => C405DBGWBIAR21_GlitchData, + OutSignalName => "C405DBGWBIAR(21)", + OutTemp => C405DBGWBIAR_OUT(21), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(22), + GlitchData => C405DBGWBIAR22_GlitchData, + OutSignalName => "C405DBGWBIAR(22)", + OutTemp => C405DBGWBIAR_OUT(22), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(23), + GlitchData => C405DBGWBIAR23_GlitchData, + OutSignalName => "C405DBGWBIAR(23)", + OutTemp => C405DBGWBIAR_OUT(23), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(24), + GlitchData => C405DBGWBIAR24_GlitchData, + OutSignalName => "C405DBGWBIAR(24)", + OutTemp => C405DBGWBIAR_OUT(24), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(25), + GlitchData => C405DBGWBIAR25_GlitchData, + OutSignalName => "C405DBGWBIAR(25)", + OutTemp => C405DBGWBIAR_OUT(25), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(26), + GlitchData => C405DBGWBIAR26_GlitchData, + OutSignalName => "C405DBGWBIAR(26)", + OutTemp => C405DBGWBIAR_OUT(26), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(27), + GlitchData => C405DBGWBIAR27_GlitchData, + OutSignalName => "C405DBGWBIAR(27)", + OutTemp => C405DBGWBIAR_OUT(27), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(28), + GlitchData => C405DBGWBIAR28_GlitchData, + OutSignalName => "C405DBGWBIAR(28)", + OutTemp => C405DBGWBIAR_OUT(28), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405DBGWBIAR(29), + GlitchData => C405DBGWBIAR29_GlitchData, + OutSignalName => "C405DBGWBIAR(29)", + OutTemp => C405DBGWBIAR_OUT(29), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(0), + GlitchData => C405PLBDCUABUS0_GlitchData, + OutSignalName => "C405PLBDCUABUS(0)", + OutTemp => C405PLBDCUABUS_OUT(0), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(1), + GlitchData => C405PLBDCUABUS1_GlitchData, + OutSignalName => "C405PLBDCUABUS(1)", + OutTemp => C405PLBDCUABUS_OUT(1), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(2), + GlitchData => C405PLBDCUABUS2_GlitchData, + OutSignalName => "C405PLBDCUABUS(2)", + OutTemp => C405PLBDCUABUS_OUT(2), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(3), + GlitchData => C405PLBDCUABUS3_GlitchData, + OutSignalName => "C405PLBDCUABUS(3)", + OutTemp => C405PLBDCUABUS_OUT(3), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(4), + GlitchData => C405PLBDCUABUS4_GlitchData, + OutSignalName => "C405PLBDCUABUS(4)", + OutTemp => C405PLBDCUABUS_OUT(4), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(5), + GlitchData => C405PLBDCUABUS5_GlitchData, + OutSignalName => "C405PLBDCUABUS(5)", + OutTemp => C405PLBDCUABUS_OUT(5), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(6), + GlitchData => C405PLBDCUABUS6_GlitchData, + OutSignalName => "C405PLBDCUABUS(6)", + OutTemp => C405PLBDCUABUS_OUT(6), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(7), + GlitchData => C405PLBDCUABUS7_GlitchData, + OutSignalName => "C405PLBDCUABUS(7)", + OutTemp => C405PLBDCUABUS_OUT(7), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(8), + GlitchData => C405PLBDCUABUS8_GlitchData, + OutSignalName => "C405PLBDCUABUS(8)", + OutTemp => C405PLBDCUABUS_OUT(8), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(9), + GlitchData => C405PLBDCUABUS9_GlitchData, + OutSignalName => "C405PLBDCUABUS(9)", + OutTemp => C405PLBDCUABUS_OUT(9), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(10), + GlitchData => C405PLBDCUABUS10_GlitchData, + OutSignalName => "C405PLBDCUABUS(10)", + OutTemp => C405PLBDCUABUS_OUT(10), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(11), + GlitchData => C405PLBDCUABUS11_GlitchData, + OutSignalName => "C405PLBDCUABUS(11)", + OutTemp => C405PLBDCUABUS_OUT(11), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(12), + GlitchData => C405PLBDCUABUS12_GlitchData, + OutSignalName => "C405PLBDCUABUS(12)", + OutTemp => C405PLBDCUABUS_OUT(12), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(13), + GlitchData => C405PLBDCUABUS13_GlitchData, + OutSignalName => "C405PLBDCUABUS(13)", + OutTemp => C405PLBDCUABUS_OUT(13), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(14), + GlitchData => C405PLBDCUABUS14_GlitchData, + OutSignalName => "C405PLBDCUABUS(14)", + OutTemp => C405PLBDCUABUS_OUT(14), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(15), + GlitchData => C405PLBDCUABUS15_GlitchData, + OutSignalName => "C405PLBDCUABUS(15)", + OutTemp => C405PLBDCUABUS_OUT(15), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(16), + GlitchData => C405PLBDCUABUS16_GlitchData, + OutSignalName => "C405PLBDCUABUS(16)", + OutTemp => C405PLBDCUABUS_OUT(16), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(17), + GlitchData => C405PLBDCUABUS17_GlitchData, + OutSignalName => "C405PLBDCUABUS(17)", + OutTemp => C405PLBDCUABUS_OUT(17), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(18), + GlitchData => C405PLBDCUABUS18_GlitchData, + OutSignalName => "C405PLBDCUABUS(18)", + OutTemp => C405PLBDCUABUS_OUT(18), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(19), + GlitchData => C405PLBDCUABUS19_GlitchData, + OutSignalName => "C405PLBDCUABUS(19)", + OutTemp => C405PLBDCUABUS_OUT(19), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(20), + GlitchData => C405PLBDCUABUS20_GlitchData, + OutSignalName => "C405PLBDCUABUS(20)", + OutTemp => C405PLBDCUABUS_OUT(20), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(21), + GlitchData => C405PLBDCUABUS21_GlitchData, + OutSignalName => "C405PLBDCUABUS(21)", + OutTemp => C405PLBDCUABUS_OUT(21), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(22), + GlitchData => C405PLBDCUABUS22_GlitchData, + OutSignalName => "C405PLBDCUABUS(22)", + OutTemp => C405PLBDCUABUS_OUT(22), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(23), + GlitchData => C405PLBDCUABUS23_GlitchData, + OutSignalName => "C405PLBDCUABUS(23)", + OutTemp => C405PLBDCUABUS_OUT(23), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(24), + GlitchData => C405PLBDCUABUS24_GlitchData, + OutSignalName => "C405PLBDCUABUS(24)", + OutTemp => C405PLBDCUABUS_OUT(24), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(25), + GlitchData => C405PLBDCUABUS25_GlitchData, + OutSignalName => "C405PLBDCUABUS(25)", + OutTemp => C405PLBDCUABUS_OUT(25), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(26), + GlitchData => C405PLBDCUABUS26_GlitchData, + OutSignalName => "C405PLBDCUABUS(26)", + OutTemp => C405PLBDCUABUS_OUT(26), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(27), + GlitchData => C405PLBDCUABUS27_GlitchData, + OutSignalName => "C405PLBDCUABUS(27)", + OutTemp => C405PLBDCUABUS_OUT(27), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(28), + GlitchData => C405PLBDCUABUS28_GlitchData, + OutSignalName => "C405PLBDCUABUS(28)", + OutTemp => C405PLBDCUABUS_OUT(28), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(29), + GlitchData => C405PLBDCUABUS29_GlitchData, + OutSignalName => "C405PLBDCUABUS(29)", + OutTemp => C405PLBDCUABUS_OUT(29), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(30), + GlitchData => C405PLBDCUABUS30_GlitchData, + OutSignalName => "C405PLBDCUABUS(30)", + OutTemp => C405PLBDCUABUS_OUT(30), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUABUS(31), + GlitchData => C405PLBDCUABUS31_GlitchData, + OutSignalName => "C405PLBDCUABUS(31)", + OutTemp => C405PLBDCUABUS_OUT(31), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUBE(0), + GlitchData => C405PLBDCUBE0_GlitchData, + OutSignalName => "C405PLBDCUBE(0)", + OutTemp => C405PLBDCUBE_OUT(0), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUBE(1), + GlitchData => C405PLBDCUBE1_GlitchData, + OutSignalName => "C405PLBDCUBE(1)", + OutTemp => C405PLBDCUBE_OUT(1), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUBE(2), + GlitchData => C405PLBDCUBE2_GlitchData, + OutSignalName => "C405PLBDCUBE(2)", + OutTemp => C405PLBDCUBE_OUT(2), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUBE(3), + GlitchData => C405PLBDCUBE3_GlitchData, + OutSignalName => "C405PLBDCUBE(3)", + OutTemp => C405PLBDCUBE_OUT(3), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUBE(4), + GlitchData => C405PLBDCUBE4_GlitchData, + OutSignalName => "C405PLBDCUBE(4)", + OutTemp => C405PLBDCUBE_OUT(4), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUBE(5), + GlitchData => C405PLBDCUBE5_GlitchData, + OutSignalName => "C405PLBDCUBE(5)", + OutTemp => C405PLBDCUBE_OUT(5), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUBE(6), + GlitchData => C405PLBDCUBE6_GlitchData, + OutSignalName => "C405PLBDCUBE(6)", + OutTemp => C405PLBDCUBE_OUT(6), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUBE(7), + GlitchData => C405PLBDCUBE7_GlitchData, + OutSignalName => "C405PLBDCUBE(7)", + OutTemp => C405PLBDCUBE_OUT(7), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUPRIORITY(0), + GlitchData => C405PLBDCUPRIORITY0_GlitchData, + OutSignalName => "C405PLBDCUPRIORITY(0)", + OutTemp => C405PLBDCUPRIORITY_OUT(0), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUPRIORITY(1), + GlitchData => C405PLBDCUPRIORITY1_GlitchData, + OutSignalName => "C405PLBDCUPRIORITY(1)", + OutTemp => C405PLBDCUPRIORITY_OUT(1), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(0), + GlitchData => C405PLBDCUWRDBUS0_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(0)", + OutTemp => C405PLBDCUWRDBUS_OUT(0), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(1), + GlitchData => C405PLBDCUWRDBUS1_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(1)", + OutTemp => C405PLBDCUWRDBUS_OUT(1), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(2), + GlitchData => C405PLBDCUWRDBUS2_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(2)", + OutTemp => C405PLBDCUWRDBUS_OUT(2), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(3), + GlitchData => C405PLBDCUWRDBUS3_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(3)", + OutTemp => C405PLBDCUWRDBUS_OUT(3), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(4), + GlitchData => C405PLBDCUWRDBUS4_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(4)", + OutTemp => C405PLBDCUWRDBUS_OUT(4), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(5), + GlitchData => C405PLBDCUWRDBUS5_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(5)", + OutTemp => C405PLBDCUWRDBUS_OUT(5), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(6), + GlitchData => C405PLBDCUWRDBUS6_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(6)", + OutTemp => C405PLBDCUWRDBUS_OUT(6), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(7), + GlitchData => C405PLBDCUWRDBUS7_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(7)", + OutTemp => C405PLBDCUWRDBUS_OUT(7), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(8), + GlitchData => C405PLBDCUWRDBUS8_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(8)", + OutTemp => C405PLBDCUWRDBUS_OUT(8), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(9), + GlitchData => C405PLBDCUWRDBUS9_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(9)", + OutTemp => C405PLBDCUWRDBUS_OUT(9), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(10), + GlitchData => C405PLBDCUWRDBUS10_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(10)", + OutTemp => C405PLBDCUWRDBUS_OUT(10), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(11), + GlitchData => C405PLBDCUWRDBUS11_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(11)", + OutTemp => C405PLBDCUWRDBUS_OUT(11), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(12), + GlitchData => C405PLBDCUWRDBUS12_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(12)", + OutTemp => C405PLBDCUWRDBUS_OUT(12), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(13), + GlitchData => C405PLBDCUWRDBUS13_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(13)", + OutTemp => C405PLBDCUWRDBUS_OUT(13), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(14), + GlitchData => C405PLBDCUWRDBUS14_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(14)", + OutTemp => C405PLBDCUWRDBUS_OUT(14), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(15), + GlitchData => C405PLBDCUWRDBUS15_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(15)", + OutTemp => C405PLBDCUWRDBUS_OUT(15), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(16), + GlitchData => C405PLBDCUWRDBUS16_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(16)", + OutTemp => C405PLBDCUWRDBUS_OUT(16), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(17), + GlitchData => C405PLBDCUWRDBUS17_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(17)", + OutTemp => C405PLBDCUWRDBUS_OUT(17), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(18), + GlitchData => C405PLBDCUWRDBUS18_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(18)", + OutTemp => C405PLBDCUWRDBUS_OUT(18), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(19), + GlitchData => C405PLBDCUWRDBUS19_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(19)", + OutTemp => C405PLBDCUWRDBUS_OUT(19), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(20), + GlitchData => C405PLBDCUWRDBUS20_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(20)", + OutTemp => C405PLBDCUWRDBUS_OUT(20), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(21), + GlitchData => C405PLBDCUWRDBUS21_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(21)", + OutTemp => C405PLBDCUWRDBUS_OUT(21), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(22), + GlitchData => C405PLBDCUWRDBUS22_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(22)", + OutTemp => C405PLBDCUWRDBUS_OUT(22), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(23), + GlitchData => C405PLBDCUWRDBUS23_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(23)", + OutTemp => C405PLBDCUWRDBUS_OUT(23), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(24), + GlitchData => C405PLBDCUWRDBUS24_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(24)", + OutTemp => C405PLBDCUWRDBUS_OUT(24), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(25), + GlitchData => C405PLBDCUWRDBUS25_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(25)", + OutTemp => C405PLBDCUWRDBUS_OUT(25), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(26), + GlitchData => C405PLBDCUWRDBUS26_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(26)", + OutTemp => C405PLBDCUWRDBUS_OUT(26), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(27), + GlitchData => C405PLBDCUWRDBUS27_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(27)", + OutTemp => C405PLBDCUWRDBUS_OUT(27), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(28), + GlitchData => C405PLBDCUWRDBUS28_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(28)", + OutTemp => C405PLBDCUWRDBUS_OUT(28), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(29), + GlitchData => C405PLBDCUWRDBUS29_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(29)", + OutTemp => C405PLBDCUWRDBUS_OUT(29), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(30), + GlitchData => C405PLBDCUWRDBUS30_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(30)", + OutTemp => C405PLBDCUWRDBUS_OUT(30), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(31), + GlitchData => C405PLBDCUWRDBUS31_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(31)", + OutTemp => C405PLBDCUWRDBUS_OUT(31), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(32), + GlitchData => C405PLBDCUWRDBUS32_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(32)", + OutTemp => C405PLBDCUWRDBUS_OUT(32), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(33), + GlitchData => C405PLBDCUWRDBUS33_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(33)", + OutTemp => C405PLBDCUWRDBUS_OUT(33), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(34), + GlitchData => C405PLBDCUWRDBUS34_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(34)", + OutTemp => C405PLBDCUWRDBUS_OUT(34), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(35), + GlitchData => C405PLBDCUWRDBUS35_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(35)", + OutTemp => C405PLBDCUWRDBUS_OUT(35), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(36), + GlitchData => C405PLBDCUWRDBUS36_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(36)", + OutTemp => C405PLBDCUWRDBUS_OUT(36), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(37), + GlitchData => C405PLBDCUWRDBUS37_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(37)", + OutTemp => C405PLBDCUWRDBUS_OUT(37), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(38), + GlitchData => C405PLBDCUWRDBUS38_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(38)", + OutTemp => C405PLBDCUWRDBUS_OUT(38), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(39), + GlitchData => C405PLBDCUWRDBUS39_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(39)", + OutTemp => C405PLBDCUWRDBUS_OUT(39), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(40), + GlitchData => C405PLBDCUWRDBUS40_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(40)", + OutTemp => C405PLBDCUWRDBUS_OUT(40), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(41), + GlitchData => C405PLBDCUWRDBUS41_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(41)", + OutTemp => C405PLBDCUWRDBUS_OUT(41), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(42), + GlitchData => C405PLBDCUWRDBUS42_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(42)", + OutTemp => C405PLBDCUWRDBUS_OUT(42), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(43), + GlitchData => C405PLBDCUWRDBUS43_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(43)", + OutTemp => C405PLBDCUWRDBUS_OUT(43), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(44), + GlitchData => C405PLBDCUWRDBUS44_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(44)", + OutTemp => C405PLBDCUWRDBUS_OUT(44), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(45), + GlitchData => C405PLBDCUWRDBUS45_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(45)", + OutTemp => C405PLBDCUWRDBUS_OUT(45), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(46), + GlitchData => C405PLBDCUWRDBUS46_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(46)", + OutTemp => C405PLBDCUWRDBUS_OUT(46), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(47), + GlitchData => C405PLBDCUWRDBUS47_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(47)", + OutTemp => C405PLBDCUWRDBUS_OUT(47), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(48), + GlitchData => C405PLBDCUWRDBUS48_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(48)", + OutTemp => C405PLBDCUWRDBUS_OUT(48), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(49), + GlitchData => C405PLBDCUWRDBUS49_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(49)", + OutTemp => C405PLBDCUWRDBUS_OUT(49), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(50), + GlitchData => C405PLBDCUWRDBUS50_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(50)", + OutTemp => C405PLBDCUWRDBUS_OUT(50), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(51), + GlitchData => C405PLBDCUWRDBUS51_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(51)", + OutTemp => C405PLBDCUWRDBUS_OUT(51), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(52), + GlitchData => C405PLBDCUWRDBUS52_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(52)", + OutTemp => C405PLBDCUWRDBUS_OUT(52), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(53), + GlitchData => C405PLBDCUWRDBUS53_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(53)", + OutTemp => C405PLBDCUWRDBUS_OUT(53), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(54), + GlitchData => C405PLBDCUWRDBUS54_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(54)", + OutTemp => C405PLBDCUWRDBUS_OUT(54), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(55), + GlitchData => C405PLBDCUWRDBUS55_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(55)", + OutTemp => C405PLBDCUWRDBUS_OUT(55), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(56), + GlitchData => C405PLBDCUWRDBUS56_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(56)", + OutTemp => C405PLBDCUWRDBUS_OUT(56), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(57), + GlitchData => C405PLBDCUWRDBUS57_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(57)", + OutTemp => C405PLBDCUWRDBUS_OUT(57), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(58), + GlitchData => C405PLBDCUWRDBUS58_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(58)", + OutTemp => C405PLBDCUWRDBUS_OUT(58), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(59), + GlitchData => C405PLBDCUWRDBUS59_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(59)", + OutTemp => C405PLBDCUWRDBUS_OUT(59), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(60), + GlitchData => C405PLBDCUWRDBUS60_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(60)", + OutTemp => C405PLBDCUWRDBUS_OUT(60), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(61), + GlitchData => C405PLBDCUWRDBUS61_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(61)", + OutTemp => C405PLBDCUWRDBUS_OUT(61), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(62), + GlitchData => C405PLBDCUWRDBUS62_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(62)", + OutTemp => C405PLBDCUWRDBUS_OUT(62), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBDCUWRDBUS(63), + GlitchData => C405PLBDCUWRDBUS63_GlitchData, + OutSignalName => "C405PLBDCUWRDBUS(63)", + OutTemp => C405PLBDCUWRDBUS_OUT(63), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(0), + GlitchData => C405PLBICUABUS0_GlitchData, + OutSignalName => "C405PLBICUABUS(0)", + OutTemp => C405PLBICUABUS_OUT(0), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(1), + GlitchData => C405PLBICUABUS1_GlitchData, + OutSignalName => "C405PLBICUABUS(1)", + OutTemp => C405PLBICUABUS_OUT(1), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(2), + GlitchData => C405PLBICUABUS2_GlitchData, + OutSignalName => "C405PLBICUABUS(2)", + OutTemp => C405PLBICUABUS_OUT(2), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(3), + GlitchData => C405PLBICUABUS3_GlitchData, + OutSignalName => "C405PLBICUABUS(3)", + OutTemp => C405PLBICUABUS_OUT(3), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(4), + GlitchData => C405PLBICUABUS4_GlitchData, + OutSignalName => "C405PLBICUABUS(4)", + OutTemp => C405PLBICUABUS_OUT(4), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(5), + GlitchData => C405PLBICUABUS5_GlitchData, + OutSignalName => "C405PLBICUABUS(5)", + OutTemp => C405PLBICUABUS_OUT(5), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(6), + GlitchData => C405PLBICUABUS6_GlitchData, + OutSignalName => "C405PLBICUABUS(6)", + OutTemp => C405PLBICUABUS_OUT(6), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(7), + GlitchData => C405PLBICUABUS7_GlitchData, + OutSignalName => "C405PLBICUABUS(7)", + OutTemp => C405PLBICUABUS_OUT(7), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(8), + GlitchData => C405PLBICUABUS8_GlitchData, + OutSignalName => "C405PLBICUABUS(8)", + OutTemp => C405PLBICUABUS_OUT(8), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(9), + GlitchData => C405PLBICUABUS9_GlitchData, + OutSignalName => "C405PLBICUABUS(9)", + OutTemp => C405PLBICUABUS_OUT(9), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(10), + GlitchData => C405PLBICUABUS10_GlitchData, + OutSignalName => "C405PLBICUABUS(10)", + OutTemp => C405PLBICUABUS_OUT(10), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(11), + GlitchData => C405PLBICUABUS11_GlitchData, + OutSignalName => "C405PLBICUABUS(11)", + OutTemp => C405PLBICUABUS_OUT(11), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(12), + GlitchData => C405PLBICUABUS12_GlitchData, + OutSignalName => "C405PLBICUABUS(12)", + OutTemp => C405PLBICUABUS_OUT(12), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(13), + GlitchData => C405PLBICUABUS13_GlitchData, + OutSignalName => "C405PLBICUABUS(13)", + OutTemp => C405PLBICUABUS_OUT(13), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(14), + GlitchData => C405PLBICUABUS14_GlitchData, + OutSignalName => "C405PLBICUABUS(14)", + OutTemp => C405PLBICUABUS_OUT(14), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(15), + GlitchData => C405PLBICUABUS15_GlitchData, + OutSignalName => "C405PLBICUABUS(15)", + OutTemp => C405PLBICUABUS_OUT(15), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(16), + GlitchData => C405PLBICUABUS16_GlitchData, + OutSignalName => "C405PLBICUABUS(16)", + OutTemp => C405PLBICUABUS_OUT(16), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(17), + GlitchData => C405PLBICUABUS17_GlitchData, + OutSignalName => "C405PLBICUABUS(17)", + OutTemp => C405PLBICUABUS_OUT(17), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(18), + GlitchData => C405PLBICUABUS18_GlitchData, + OutSignalName => "C405PLBICUABUS(18)", + OutTemp => C405PLBICUABUS_OUT(18), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(19), + GlitchData => C405PLBICUABUS19_GlitchData, + OutSignalName => "C405PLBICUABUS(19)", + OutTemp => C405PLBICUABUS_OUT(19), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(20), + GlitchData => C405PLBICUABUS20_GlitchData, + OutSignalName => "C405PLBICUABUS(20)", + OutTemp => C405PLBICUABUS_OUT(20), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(21), + GlitchData => C405PLBICUABUS21_GlitchData, + OutSignalName => "C405PLBICUABUS(21)", + OutTemp => C405PLBICUABUS_OUT(21), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(22), + GlitchData => C405PLBICUABUS22_GlitchData, + OutSignalName => "C405PLBICUABUS(22)", + OutTemp => C405PLBICUABUS_OUT(22), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(23), + GlitchData => C405PLBICUABUS23_GlitchData, + OutSignalName => "C405PLBICUABUS(23)", + OutTemp => C405PLBICUABUS_OUT(23), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(24), + GlitchData => C405PLBICUABUS24_GlitchData, + OutSignalName => "C405PLBICUABUS(24)", + OutTemp => C405PLBICUABUS_OUT(24), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(25), + GlitchData => C405PLBICUABUS25_GlitchData, + OutSignalName => "C405PLBICUABUS(25)", + OutTemp => C405PLBICUABUS_OUT(25), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(26), + GlitchData => C405PLBICUABUS26_GlitchData, + OutSignalName => "C405PLBICUABUS(26)", + OutTemp => C405PLBICUABUS_OUT(26), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(27), + GlitchData => C405PLBICUABUS27_GlitchData, + OutSignalName => "C405PLBICUABUS(27)", + OutTemp => C405PLBICUABUS_OUT(27), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(28), + GlitchData => C405PLBICUABUS28_GlitchData, + OutSignalName => "C405PLBICUABUS(28)", + OutTemp => C405PLBICUABUS_OUT(28), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUABUS(29), + GlitchData => C405PLBICUABUS29_GlitchData, + OutSignalName => "C405PLBICUABUS(29)", + OutTemp => C405PLBICUABUS_OUT(29), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUPRIORITY(0), + GlitchData => C405PLBICUPRIORITY0_GlitchData, + OutSignalName => "C405PLBICUPRIORITY(0)", + OutTemp => C405PLBICUPRIORITY_OUT(0), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUPRIORITY(1), + GlitchData => C405PLBICUPRIORITY1_GlitchData, + OutSignalName => "C405PLBICUPRIORITY(1)", + OutTemp => C405PLBICUPRIORITY_OUT(1), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUSIZE(2), + GlitchData => C405PLBICUSIZE2_GlitchData, + OutSignalName => "C405PLBICUSIZE(2)", + OutTemp => C405PLBICUSIZE_OUT(2), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405PLBICUSIZE(3), + GlitchData => C405PLBICUSIZE3_GlitchData, + OutSignalName => "C405PLBICUSIZE(3)", + OutTemp => C405PLBICUSIZE_OUT(3), + Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCEVENEXECUTIONSTATUS(0), + GlitchData => C405TRCEVENEXECUTIONSTATUS0_GlitchData, + OutSignalName => "C405TRCEVENEXECUTIONSTATUS(0)", + OutTemp => C405TRCEVENEXECUTIONSTATUS_OUT(0), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCEVENEXECUTIONSTATUS(1), + GlitchData => C405TRCEVENEXECUTIONSTATUS1_GlitchData, + OutSignalName => "C405TRCEVENEXECUTIONSTATUS(1)", + OutTemp => C405TRCEVENEXECUTIONSTATUS_OUT(1), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCODDEXECUTIONSTATUS(0), + GlitchData => C405TRCODDEXECUTIONSTATUS0_GlitchData, + OutSignalName => "C405TRCODDEXECUTIONSTATUS(0)", + OutTemp => C405TRCODDEXECUTIONSTATUS_OUT(0), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCODDEXECUTIONSTATUS(1), + GlitchData => C405TRCODDEXECUTIONSTATUS1_GlitchData, + OutSignalName => "C405TRCODDEXECUTIONSTATUS(1)", + OutTemp => C405TRCODDEXECUTIONSTATUS_OUT(1), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCTRACESTATUS(0), + GlitchData => C405TRCTRACESTATUS0_GlitchData, + OutSignalName => "C405TRCTRACESTATUS(0)", + OutTemp => C405TRCTRACESTATUS_OUT(0), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCTRACESTATUS(1), + GlitchData => C405TRCTRACESTATUS1_GlitchData, + OutSignalName => "C405TRCTRACESTATUS(1)", + OutTemp => C405TRCTRACESTATUS_OUT(1), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCTRACESTATUS(2), + GlitchData => C405TRCTRACESTATUS2_GlitchData, + OutSignalName => "C405TRCTRACESTATUS(2)", + OutTemp => C405TRCTRACESTATUS_OUT(2), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCTRACESTATUS(3), + GlitchData => C405TRCTRACESTATUS3_GlitchData, + OutSignalName => "C405TRCTRACESTATUS(3)", + OutTemp => C405TRCTRACESTATUS_OUT(3), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCTRIGGEREVENTTYPE(0), + GlitchData => C405TRCTRIGGEREVENTTYPE0_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(0)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(0), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCTRIGGEREVENTTYPE(1), + GlitchData => C405TRCTRIGGEREVENTTYPE1_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(1)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(1), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCTRIGGEREVENTTYPE(2), + GlitchData => C405TRCTRIGGEREVENTTYPE2_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(2)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(2), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCTRIGGEREVENTTYPE(3), + GlitchData => C405TRCTRIGGEREVENTTYPE3_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(3)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(3), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCTRIGGEREVENTTYPE(4), + GlitchData => C405TRCTRIGGEREVENTTYPE4_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(4)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(4), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCTRIGGEREVENTTYPE(5), + GlitchData => C405TRCTRIGGEREVENTTYPE5_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(5)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(5), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCTRIGGEREVENTTYPE(6), + GlitchData => C405TRCTRIGGEREVENTTYPE6_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(6)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(6), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCTRIGGEREVENTTYPE(7), + GlitchData => C405TRCTRIGGEREVENTTYPE7_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(7)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(7), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCTRIGGEREVENTTYPE(8), + GlitchData => C405TRCTRIGGEREVENTTYPE8_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(8)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(8), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCTRIGGEREVENTTYPE(9), + GlitchData => C405TRCTRIGGEREVENTTYPE9_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(9)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(9), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C405TRCTRIGGEREVENTTYPE(10), + GlitchData => C405TRCTRIGGEREVENTTYPE10_GlitchData, + OutSignalName => "C405TRCTRIGGEREVENTTYPE(10)", + OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(10), + Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(8), + GlitchData => DSOCMBRAMABUS8_GlitchData, + OutSignalName => "DSOCMBRAMABUS(8)", + OutTemp => DSOCMBRAMABUS_OUT(8), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(9), + GlitchData => DSOCMBRAMABUS9_GlitchData, + OutSignalName => "DSOCMBRAMABUS(9)", + OutTemp => DSOCMBRAMABUS_OUT(9), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(10), + GlitchData => DSOCMBRAMABUS10_GlitchData, + OutSignalName => "DSOCMBRAMABUS(10)", + OutTemp => DSOCMBRAMABUS_OUT(10), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(11), + GlitchData => DSOCMBRAMABUS11_GlitchData, + OutSignalName => "DSOCMBRAMABUS(11)", + OutTemp => DSOCMBRAMABUS_OUT(11), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(12), + GlitchData => DSOCMBRAMABUS12_GlitchData, + OutSignalName => "DSOCMBRAMABUS(12)", + OutTemp => DSOCMBRAMABUS_OUT(12), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(13), + GlitchData => DSOCMBRAMABUS13_GlitchData, + OutSignalName => "DSOCMBRAMABUS(13)", + OutTemp => DSOCMBRAMABUS_OUT(13), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(14), + GlitchData => DSOCMBRAMABUS14_GlitchData, + OutSignalName => "DSOCMBRAMABUS(14)", + OutTemp => DSOCMBRAMABUS_OUT(14), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(15), + GlitchData => DSOCMBRAMABUS15_GlitchData, + OutSignalName => "DSOCMBRAMABUS(15)", + OutTemp => DSOCMBRAMABUS_OUT(15), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(16), + GlitchData => DSOCMBRAMABUS16_GlitchData, + OutSignalName => "DSOCMBRAMABUS(16)", + OutTemp => DSOCMBRAMABUS_OUT(16), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(17), + GlitchData => DSOCMBRAMABUS17_GlitchData, + OutSignalName => "DSOCMBRAMABUS(17)", + OutTemp => DSOCMBRAMABUS_OUT(17), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(18), + GlitchData => DSOCMBRAMABUS18_GlitchData, + OutSignalName => "DSOCMBRAMABUS(18)", + OutTemp => DSOCMBRAMABUS_OUT(18), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(19), + GlitchData => DSOCMBRAMABUS19_GlitchData, + OutSignalName => "DSOCMBRAMABUS(19)", + OutTemp => DSOCMBRAMABUS_OUT(19), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(20), + GlitchData => DSOCMBRAMABUS20_GlitchData, + OutSignalName => "DSOCMBRAMABUS(20)", + OutTemp => DSOCMBRAMABUS_OUT(20), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(21), + GlitchData => DSOCMBRAMABUS21_GlitchData, + OutSignalName => "DSOCMBRAMABUS(21)", + OutTemp => DSOCMBRAMABUS_OUT(21), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(22), + GlitchData => DSOCMBRAMABUS22_GlitchData, + OutSignalName => "DSOCMBRAMABUS(22)", + OutTemp => DSOCMBRAMABUS_OUT(22), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(23), + GlitchData => DSOCMBRAMABUS23_GlitchData, + OutSignalName => "DSOCMBRAMABUS(23)", + OutTemp => DSOCMBRAMABUS_OUT(23), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(24), + GlitchData => DSOCMBRAMABUS24_GlitchData, + OutSignalName => "DSOCMBRAMABUS(24)", + OutTemp => DSOCMBRAMABUS_OUT(24), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(25), + GlitchData => DSOCMBRAMABUS25_GlitchData, + OutSignalName => "DSOCMBRAMABUS(25)", + OutTemp => DSOCMBRAMABUS_OUT(25), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(26), + GlitchData => DSOCMBRAMABUS26_GlitchData, + OutSignalName => "DSOCMBRAMABUS(26)", + OutTemp => DSOCMBRAMABUS_OUT(26), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(27), + GlitchData => DSOCMBRAMABUS27_GlitchData, + OutSignalName => "DSOCMBRAMABUS(27)", + OutTemp => DSOCMBRAMABUS_OUT(27), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(28), + GlitchData => DSOCMBRAMABUS28_GlitchData, + OutSignalName => "DSOCMBRAMABUS(28)", + OutTemp => DSOCMBRAMABUS_OUT(28), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMABUS(29), + GlitchData => DSOCMBRAMABUS29_GlitchData, + OutSignalName => "DSOCMBRAMABUS(29)", + OutTemp => DSOCMBRAMABUS_OUT(29), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMBYTEWRITE(0), + GlitchData => DSOCMBRAMBYTEWRITE0_GlitchData, + OutSignalName => "DSOCMBRAMBYTEWRITE(0)", + OutTemp => DSOCMBRAMBYTEWRITE_OUT(0), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMBYTEWRITE(1), + GlitchData => DSOCMBRAMBYTEWRITE1_GlitchData, + OutSignalName => "DSOCMBRAMBYTEWRITE(1)", + OutTemp => DSOCMBRAMBYTEWRITE_OUT(1), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMBYTEWRITE(2), + GlitchData => DSOCMBRAMBYTEWRITE2_GlitchData, + OutSignalName => "DSOCMBRAMBYTEWRITE(2)", + OutTemp => DSOCMBRAMBYTEWRITE_OUT(2), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMBYTEWRITE(3), + GlitchData => DSOCMBRAMBYTEWRITE3_GlitchData, + OutSignalName => "DSOCMBRAMBYTEWRITE(3)", + OutTemp => DSOCMBRAMBYTEWRITE_OUT(3), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(0), + GlitchData => DSOCMBRAMWRDBUS0_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(0)", + OutTemp => DSOCMBRAMWRDBUS_OUT(0), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(1), + GlitchData => DSOCMBRAMWRDBUS1_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(1)", + OutTemp => DSOCMBRAMWRDBUS_OUT(1), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(2), + GlitchData => DSOCMBRAMWRDBUS2_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(2)", + OutTemp => DSOCMBRAMWRDBUS_OUT(2), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(3), + GlitchData => DSOCMBRAMWRDBUS3_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(3)", + OutTemp => DSOCMBRAMWRDBUS_OUT(3), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(4), + GlitchData => DSOCMBRAMWRDBUS4_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(4)", + OutTemp => DSOCMBRAMWRDBUS_OUT(4), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(5), + GlitchData => DSOCMBRAMWRDBUS5_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(5)", + OutTemp => DSOCMBRAMWRDBUS_OUT(5), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(6), + GlitchData => DSOCMBRAMWRDBUS6_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(6)", + OutTemp => DSOCMBRAMWRDBUS_OUT(6), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(7), + GlitchData => DSOCMBRAMWRDBUS7_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(7)", + OutTemp => DSOCMBRAMWRDBUS_OUT(7), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(8), + GlitchData => DSOCMBRAMWRDBUS8_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(8)", + OutTemp => DSOCMBRAMWRDBUS_OUT(8), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(9), + GlitchData => DSOCMBRAMWRDBUS9_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(9)", + OutTemp => DSOCMBRAMWRDBUS_OUT(9), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(10), + GlitchData => DSOCMBRAMWRDBUS10_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(10)", + OutTemp => DSOCMBRAMWRDBUS_OUT(10), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(11), + GlitchData => DSOCMBRAMWRDBUS11_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(11)", + OutTemp => DSOCMBRAMWRDBUS_OUT(11), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(12), + GlitchData => DSOCMBRAMWRDBUS12_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(12)", + OutTemp => DSOCMBRAMWRDBUS_OUT(12), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(13), + GlitchData => DSOCMBRAMWRDBUS13_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(13)", + OutTemp => DSOCMBRAMWRDBUS_OUT(13), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(14), + GlitchData => DSOCMBRAMWRDBUS14_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(14)", + OutTemp => DSOCMBRAMWRDBUS_OUT(14), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(15), + GlitchData => DSOCMBRAMWRDBUS15_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(15)", + OutTemp => DSOCMBRAMWRDBUS_OUT(15), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(16), + GlitchData => DSOCMBRAMWRDBUS16_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(16)", + OutTemp => DSOCMBRAMWRDBUS_OUT(16), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(17), + GlitchData => DSOCMBRAMWRDBUS17_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(17)", + OutTemp => DSOCMBRAMWRDBUS_OUT(17), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(18), + GlitchData => DSOCMBRAMWRDBUS18_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(18)", + OutTemp => DSOCMBRAMWRDBUS_OUT(18), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(19), + GlitchData => DSOCMBRAMWRDBUS19_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(19)", + OutTemp => DSOCMBRAMWRDBUS_OUT(19), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(20), + GlitchData => DSOCMBRAMWRDBUS20_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(20)", + OutTemp => DSOCMBRAMWRDBUS_OUT(20), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(21), + GlitchData => DSOCMBRAMWRDBUS21_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(21)", + OutTemp => DSOCMBRAMWRDBUS_OUT(21), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(22), + GlitchData => DSOCMBRAMWRDBUS22_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(22)", + OutTemp => DSOCMBRAMWRDBUS_OUT(22), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(23), + GlitchData => DSOCMBRAMWRDBUS23_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(23)", + OutTemp => DSOCMBRAMWRDBUS_OUT(23), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(24), + GlitchData => DSOCMBRAMWRDBUS24_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(24)", + OutTemp => DSOCMBRAMWRDBUS_OUT(24), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(25), + GlitchData => DSOCMBRAMWRDBUS25_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(25)", + OutTemp => DSOCMBRAMWRDBUS_OUT(25), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(26), + GlitchData => DSOCMBRAMWRDBUS26_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(26)", + OutTemp => DSOCMBRAMWRDBUS_OUT(26), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(27), + GlitchData => DSOCMBRAMWRDBUS27_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(27)", + OutTemp => DSOCMBRAMWRDBUS_OUT(27), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(28), + GlitchData => DSOCMBRAMWRDBUS28_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(28)", + OutTemp => DSOCMBRAMWRDBUS_OUT(28), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(29), + GlitchData => DSOCMBRAMWRDBUS29_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(29)", + OutTemp => DSOCMBRAMWRDBUS_OUT(29), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(30), + GlitchData => DSOCMBRAMWRDBUS30_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(30)", + OutTemp => DSOCMBRAMWRDBUS_OUT(30), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DSOCMBRAMWRDBUS(31), + GlitchData => DSOCMBRAMWRDBUS31_GlitchData, + OutSignalName => "DSOCMBRAMWRDBUS(31)", + OutTemp => DSOCMBRAMWRDBUS_OUT(31), + Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRABUS(0), + GlitchData => EXTDCRABUS0_GlitchData, + OutSignalName => "EXTDCRABUS(0)", + OutTemp => EXTDCRABUS_OUT(0), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRABUS(1), + GlitchData => EXTDCRABUS1_GlitchData, + OutSignalName => "EXTDCRABUS(1)", + OutTemp => EXTDCRABUS_OUT(1), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRABUS(2), + GlitchData => EXTDCRABUS2_GlitchData, + OutSignalName => "EXTDCRABUS(2)", + OutTemp => EXTDCRABUS_OUT(2), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRABUS(3), + GlitchData => EXTDCRABUS3_GlitchData, + OutSignalName => "EXTDCRABUS(3)", + OutTemp => EXTDCRABUS_OUT(3), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRABUS(4), + GlitchData => EXTDCRABUS4_GlitchData, + OutSignalName => "EXTDCRABUS(4)", + OutTemp => EXTDCRABUS_OUT(4), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRABUS(5), + GlitchData => EXTDCRABUS5_GlitchData, + OutSignalName => "EXTDCRABUS(5)", + OutTemp => EXTDCRABUS_OUT(5), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRABUS(6), + GlitchData => EXTDCRABUS6_GlitchData, + OutSignalName => "EXTDCRABUS(6)", + OutTemp => EXTDCRABUS_OUT(6), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRABUS(7), + GlitchData => EXTDCRABUS7_GlitchData, + OutSignalName => "EXTDCRABUS(7)", + OutTemp => EXTDCRABUS_OUT(7), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRABUS(8), + GlitchData => EXTDCRABUS8_GlitchData, + OutSignalName => "EXTDCRABUS(8)", + OutTemp => EXTDCRABUS_OUT(8), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRABUS(9), + GlitchData => EXTDCRABUS9_GlitchData, + OutSignalName => "EXTDCRABUS(9)", + OutTemp => EXTDCRABUS_OUT(9), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(0), + GlitchData => EXTDCRDBUSOUT0_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(0)", + OutTemp => EXTDCRDBUSOUT_OUT(0), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(1), + GlitchData => EXTDCRDBUSOUT1_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(1)", + OutTemp => EXTDCRDBUSOUT_OUT(1), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(2), + GlitchData => EXTDCRDBUSOUT2_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(2)", + OutTemp => EXTDCRDBUSOUT_OUT(2), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(3), + GlitchData => EXTDCRDBUSOUT3_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(3)", + OutTemp => EXTDCRDBUSOUT_OUT(3), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(4), + GlitchData => EXTDCRDBUSOUT4_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(4)", + OutTemp => EXTDCRDBUSOUT_OUT(4), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(5), + GlitchData => EXTDCRDBUSOUT5_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(5)", + OutTemp => EXTDCRDBUSOUT_OUT(5), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(6), + GlitchData => EXTDCRDBUSOUT6_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(6)", + OutTemp => EXTDCRDBUSOUT_OUT(6), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(7), + GlitchData => EXTDCRDBUSOUT7_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(7)", + OutTemp => EXTDCRDBUSOUT_OUT(7), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(8), + GlitchData => EXTDCRDBUSOUT8_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(8)", + OutTemp => EXTDCRDBUSOUT_OUT(8), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(9), + GlitchData => EXTDCRDBUSOUT9_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(9)", + OutTemp => EXTDCRDBUSOUT_OUT(9), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(10), + GlitchData => EXTDCRDBUSOUT10_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(10)", + OutTemp => EXTDCRDBUSOUT_OUT(10), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(11), + GlitchData => EXTDCRDBUSOUT11_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(11)", + OutTemp => EXTDCRDBUSOUT_OUT(11), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(12), + GlitchData => EXTDCRDBUSOUT12_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(12)", + OutTemp => EXTDCRDBUSOUT_OUT(12), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(13), + GlitchData => EXTDCRDBUSOUT13_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(13)", + OutTemp => EXTDCRDBUSOUT_OUT(13), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(14), + GlitchData => EXTDCRDBUSOUT14_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(14)", + OutTemp => EXTDCRDBUSOUT_OUT(14), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(15), + GlitchData => EXTDCRDBUSOUT15_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(15)", + OutTemp => EXTDCRDBUSOUT_OUT(15), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(16), + GlitchData => EXTDCRDBUSOUT16_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(16)", + OutTemp => EXTDCRDBUSOUT_OUT(16), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(17), + GlitchData => EXTDCRDBUSOUT17_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(17)", + OutTemp => EXTDCRDBUSOUT_OUT(17), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(18), + GlitchData => EXTDCRDBUSOUT18_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(18)", + OutTemp => EXTDCRDBUSOUT_OUT(18), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(19), + GlitchData => EXTDCRDBUSOUT19_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(19)", + OutTemp => EXTDCRDBUSOUT_OUT(19), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(20), + GlitchData => EXTDCRDBUSOUT20_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(20)", + OutTemp => EXTDCRDBUSOUT_OUT(20), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(21), + GlitchData => EXTDCRDBUSOUT21_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(21)", + OutTemp => EXTDCRDBUSOUT_OUT(21), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(22), + GlitchData => EXTDCRDBUSOUT22_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(22)", + OutTemp => EXTDCRDBUSOUT_OUT(22), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(23), + GlitchData => EXTDCRDBUSOUT23_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(23)", + OutTemp => EXTDCRDBUSOUT_OUT(23), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(24), + GlitchData => EXTDCRDBUSOUT24_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(24)", + OutTemp => EXTDCRDBUSOUT_OUT(24), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(25), + GlitchData => EXTDCRDBUSOUT25_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(25)", + OutTemp => EXTDCRDBUSOUT_OUT(25), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(26), + GlitchData => EXTDCRDBUSOUT26_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(26)", + OutTemp => EXTDCRDBUSOUT_OUT(26), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(27), + GlitchData => EXTDCRDBUSOUT27_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(27)", + OutTemp => EXTDCRDBUSOUT_OUT(27), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(28), + GlitchData => EXTDCRDBUSOUT28_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(28)", + OutTemp => EXTDCRDBUSOUT_OUT(28), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(29), + GlitchData => EXTDCRDBUSOUT29_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(29)", + OutTemp => EXTDCRDBUSOUT_OUT(29), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(30), + GlitchData => EXTDCRDBUSOUT30_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(30)", + OutTemp => EXTDCRDBUSOUT_OUT(30), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EXTDCRDBUSOUT(31), + GlitchData => EXTDCRDBUSOUT31_GlitchData, + OutSignalName => "EXTDCRDBUSOUT(31)", + OutTemp => EXTDCRDBUSOUT_OUT(31), + Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(8), + GlitchData => ISOCMBRAMRDABUS8_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(8)", + OutTemp => ISOCMBRAMRDABUS_OUT(8), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(9), + GlitchData => ISOCMBRAMRDABUS9_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(9)", + OutTemp => ISOCMBRAMRDABUS_OUT(9), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(10), + GlitchData => ISOCMBRAMRDABUS10_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(10)", + OutTemp => ISOCMBRAMRDABUS_OUT(10), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(11), + GlitchData => ISOCMBRAMRDABUS11_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(11)", + OutTemp => ISOCMBRAMRDABUS_OUT(11), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(12), + GlitchData => ISOCMBRAMRDABUS12_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(12)", + OutTemp => ISOCMBRAMRDABUS_OUT(12), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(13), + GlitchData => ISOCMBRAMRDABUS13_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(13)", + OutTemp => ISOCMBRAMRDABUS_OUT(13), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(14), + GlitchData => ISOCMBRAMRDABUS14_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(14)", + OutTemp => ISOCMBRAMRDABUS_OUT(14), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(15), + GlitchData => ISOCMBRAMRDABUS15_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(15)", + OutTemp => ISOCMBRAMRDABUS_OUT(15), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(16), + GlitchData => ISOCMBRAMRDABUS16_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(16)", + OutTemp => ISOCMBRAMRDABUS_OUT(16), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(17), + GlitchData => ISOCMBRAMRDABUS17_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(17)", + OutTemp => ISOCMBRAMRDABUS_OUT(17), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(18), + GlitchData => ISOCMBRAMRDABUS18_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(18)", + OutTemp => ISOCMBRAMRDABUS_OUT(18), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(19), + GlitchData => ISOCMBRAMRDABUS19_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(19)", + OutTemp => ISOCMBRAMRDABUS_OUT(19), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(20), + GlitchData => ISOCMBRAMRDABUS20_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(20)", + OutTemp => ISOCMBRAMRDABUS_OUT(20), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(21), + GlitchData => ISOCMBRAMRDABUS21_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(21)", + OutTemp => ISOCMBRAMRDABUS_OUT(21), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(22), + GlitchData => ISOCMBRAMRDABUS22_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(22)", + OutTemp => ISOCMBRAMRDABUS_OUT(22), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(23), + GlitchData => ISOCMBRAMRDABUS23_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(23)", + OutTemp => ISOCMBRAMRDABUS_OUT(23), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(24), + GlitchData => ISOCMBRAMRDABUS24_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(24)", + OutTemp => ISOCMBRAMRDABUS_OUT(24), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(25), + GlitchData => ISOCMBRAMRDABUS25_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(25)", + OutTemp => ISOCMBRAMRDABUS_OUT(25), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(26), + GlitchData => ISOCMBRAMRDABUS26_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(26)", + OutTemp => ISOCMBRAMRDABUS_OUT(26), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(27), + GlitchData => ISOCMBRAMRDABUS27_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(27)", + OutTemp => ISOCMBRAMRDABUS_OUT(27), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMRDABUS(28), + GlitchData => ISOCMBRAMRDABUS28_GlitchData, + OutSignalName => "ISOCMBRAMRDABUS(28)", + OutTemp => ISOCMBRAMRDABUS_OUT(28), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(8), + GlitchData => ISOCMBRAMWRABUS8_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(8)", + OutTemp => ISOCMBRAMWRABUS_OUT(8), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(9), + GlitchData => ISOCMBRAMWRABUS9_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(9)", + OutTemp => ISOCMBRAMWRABUS_OUT(9), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(10), + GlitchData => ISOCMBRAMWRABUS10_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(10)", + OutTemp => ISOCMBRAMWRABUS_OUT(10), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(11), + GlitchData => ISOCMBRAMWRABUS11_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(11)", + OutTemp => ISOCMBRAMWRABUS_OUT(11), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(12), + GlitchData => ISOCMBRAMWRABUS12_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(12)", + OutTemp => ISOCMBRAMWRABUS_OUT(12), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(13), + GlitchData => ISOCMBRAMWRABUS13_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(13)", + OutTemp => ISOCMBRAMWRABUS_OUT(13), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(14), + GlitchData => ISOCMBRAMWRABUS14_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(14)", + OutTemp => ISOCMBRAMWRABUS_OUT(14), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(15), + GlitchData => ISOCMBRAMWRABUS15_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(15)", + OutTemp => ISOCMBRAMWRABUS_OUT(15), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(16), + GlitchData => ISOCMBRAMWRABUS16_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(16)", + OutTemp => ISOCMBRAMWRABUS_OUT(16), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(17), + GlitchData => ISOCMBRAMWRABUS17_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(17)", + OutTemp => ISOCMBRAMWRABUS_OUT(17), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(18), + GlitchData => ISOCMBRAMWRABUS18_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(18)", + OutTemp => ISOCMBRAMWRABUS_OUT(18), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(19), + GlitchData => ISOCMBRAMWRABUS19_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(19)", + OutTemp => ISOCMBRAMWRABUS_OUT(19), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(20), + GlitchData => ISOCMBRAMWRABUS20_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(20)", + OutTemp => ISOCMBRAMWRABUS_OUT(20), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(21), + GlitchData => ISOCMBRAMWRABUS21_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(21)", + OutTemp => ISOCMBRAMWRABUS_OUT(21), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(22), + GlitchData => ISOCMBRAMWRABUS22_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(22)", + OutTemp => ISOCMBRAMWRABUS_OUT(22), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(23), + GlitchData => ISOCMBRAMWRABUS23_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(23)", + OutTemp => ISOCMBRAMWRABUS_OUT(23), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(24), + GlitchData => ISOCMBRAMWRABUS24_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(24)", + OutTemp => ISOCMBRAMWRABUS_OUT(24), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(25), + GlitchData => ISOCMBRAMWRABUS25_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(25)", + OutTemp => ISOCMBRAMWRABUS_OUT(25), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(26), + GlitchData => ISOCMBRAMWRABUS26_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(26)", + OutTemp => ISOCMBRAMWRABUS_OUT(26), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(27), + GlitchData => ISOCMBRAMWRABUS27_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(27)", + OutTemp => ISOCMBRAMWRABUS_OUT(27), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRABUS(28), + GlitchData => ISOCMBRAMWRABUS28_GlitchData, + OutSignalName => "ISOCMBRAMWRABUS(28)", + OutTemp => ISOCMBRAMWRABUS_OUT(28), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(0), + GlitchData => ISOCMBRAMWRDBUS0_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(0)", + OutTemp => ISOCMBRAMWRDBUS_OUT(0), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(1), + GlitchData => ISOCMBRAMWRDBUS1_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(1)", + OutTemp => ISOCMBRAMWRDBUS_OUT(1), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(2), + GlitchData => ISOCMBRAMWRDBUS2_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(2)", + OutTemp => ISOCMBRAMWRDBUS_OUT(2), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(3), + GlitchData => ISOCMBRAMWRDBUS3_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(3)", + OutTemp => ISOCMBRAMWRDBUS_OUT(3), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(4), + GlitchData => ISOCMBRAMWRDBUS4_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(4)", + OutTemp => ISOCMBRAMWRDBUS_OUT(4), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(5), + GlitchData => ISOCMBRAMWRDBUS5_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(5)", + OutTemp => ISOCMBRAMWRDBUS_OUT(5), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(6), + GlitchData => ISOCMBRAMWRDBUS6_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(6)", + OutTemp => ISOCMBRAMWRDBUS_OUT(6), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(7), + GlitchData => ISOCMBRAMWRDBUS7_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(7)", + OutTemp => ISOCMBRAMWRDBUS_OUT(7), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(8), + GlitchData => ISOCMBRAMWRDBUS8_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(8)", + OutTemp => ISOCMBRAMWRDBUS_OUT(8), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(9), + GlitchData => ISOCMBRAMWRDBUS9_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(9)", + OutTemp => ISOCMBRAMWRDBUS_OUT(9), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(10), + GlitchData => ISOCMBRAMWRDBUS10_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(10)", + OutTemp => ISOCMBRAMWRDBUS_OUT(10), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(11), + GlitchData => ISOCMBRAMWRDBUS11_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(11)", + OutTemp => ISOCMBRAMWRDBUS_OUT(11), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(12), + GlitchData => ISOCMBRAMWRDBUS12_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(12)", + OutTemp => ISOCMBRAMWRDBUS_OUT(12), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(13), + GlitchData => ISOCMBRAMWRDBUS13_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(13)", + OutTemp => ISOCMBRAMWRDBUS_OUT(13), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(14), + GlitchData => ISOCMBRAMWRDBUS14_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(14)", + OutTemp => ISOCMBRAMWRDBUS_OUT(14), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(15), + GlitchData => ISOCMBRAMWRDBUS15_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(15)", + OutTemp => ISOCMBRAMWRDBUS_OUT(15), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(16), + GlitchData => ISOCMBRAMWRDBUS16_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(16)", + OutTemp => ISOCMBRAMWRDBUS_OUT(16), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(17), + GlitchData => ISOCMBRAMWRDBUS17_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(17)", + OutTemp => ISOCMBRAMWRDBUS_OUT(17), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(18), + GlitchData => ISOCMBRAMWRDBUS18_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(18)", + OutTemp => ISOCMBRAMWRDBUS_OUT(18), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(19), + GlitchData => ISOCMBRAMWRDBUS19_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(19)", + OutTemp => ISOCMBRAMWRDBUS_OUT(19), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(20), + GlitchData => ISOCMBRAMWRDBUS20_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(20)", + OutTemp => ISOCMBRAMWRDBUS_OUT(20), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(21), + GlitchData => ISOCMBRAMWRDBUS21_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(21)", + OutTemp => ISOCMBRAMWRDBUS_OUT(21), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(22), + GlitchData => ISOCMBRAMWRDBUS22_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(22)", + OutTemp => ISOCMBRAMWRDBUS_OUT(22), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(23), + GlitchData => ISOCMBRAMWRDBUS23_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(23)", + OutTemp => ISOCMBRAMWRDBUS_OUT(23), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(24), + GlitchData => ISOCMBRAMWRDBUS24_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(24)", + OutTemp => ISOCMBRAMWRDBUS_OUT(24), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(25), + GlitchData => ISOCMBRAMWRDBUS25_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(25)", + OutTemp => ISOCMBRAMWRDBUS_OUT(25), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(26), + GlitchData => ISOCMBRAMWRDBUS26_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(26)", + OutTemp => ISOCMBRAMWRDBUS_OUT(26), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(27), + GlitchData => ISOCMBRAMWRDBUS27_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(27)", + OutTemp => ISOCMBRAMWRDBUS_OUT(27), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(28), + GlitchData => ISOCMBRAMWRDBUS28_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(28)", + OutTemp => ISOCMBRAMWRDBUS_OUT(28), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(29), + GlitchData => ISOCMBRAMWRDBUS29_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(29)", + OutTemp => ISOCMBRAMWRDBUS_OUT(29), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(30), + GlitchData => ISOCMBRAMWRDBUS30_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(30)", + OutTemp => ISOCMBRAMWRDBUS_OUT(30), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => ISOCMBRAMWRDBUS(31), + GlitchData => ISOCMBRAMWRDBUS31_GlitchData, + OutSignalName => "ISOCMBRAMWRDBUS(31)", + OutTemp => ISOCMBRAMWRDBUS_OUT(31), + Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), + DefaultDelay => OUT_DELAY, + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + +-- Wait signal (input/output pins) + wait on + APUFCMDECODED_OUT, + APUFCMDECUDI_OUT, + APUFCMDECUDIVALID_OUT, + APUFCMENDIAN_OUT, + APUFCMFLUSH_OUT, + APUFCMINSTRUCTION_OUT, + APUFCMINSTRVALID_OUT, + APUFCMLOADBYTEEN_OUT, + APUFCMLOADDATA_OUT, + APUFCMLOADDVALID_OUT, + APUFCMOPERANDVALID_OUT, + APUFCMRADATA_OUT, + APUFCMRBDATA_OUT, + APUFCMWRITEBACKOK_OUT, + APUFCMXERCA_OUT, + BRAMDSOCMCLK_ipd_1, + BRAMDSOCMRDDBUS_ipd_1, + BRAMISOCMCLK_ipd_1, + BRAMISOCMDCRRDDBUS_ipd_1, + BRAMISOCMRDDBUS_ipd_1, + C405CPMCORESLEEPREQ_OUT, + C405CPMMSRCE_OUT, + C405CPMMSREE_OUT, + C405CPMTIMERIRQ_OUT, + C405CPMTIMERRESETREQ_OUT, + C405DBGLOADDATAONAPUDBUS_OUT, + C405DBGMSRWE_OUT, + C405DBGSTOPACK_OUT, + C405DBGWBCOMPLETE_OUT, + C405DBGWBFULL_OUT, + C405DBGWBIAR_OUT, + C405JTGCAPTUREDR_OUT, + C405JTGEXTEST_OUT, + C405JTGPGMOUT_OUT, + C405JTGSHIFTDR_OUT, + C405JTGTDO_OUT, + C405JTGTDOEN_OUT, + C405JTGUPDATEDR_OUT, + C405PLBDCUABORT_OUT, + C405PLBDCUABUS_OUT, + C405PLBDCUBE_OUT, + C405PLBDCUCACHEABLE_OUT, + C405PLBDCUGUARDED_OUT, + C405PLBDCUPRIORITY_OUT, + C405PLBDCUREQUEST_OUT, + C405PLBDCURNW_OUT, + C405PLBDCUSIZE2_OUT, + C405PLBDCUU0ATTR_OUT, + C405PLBDCUWRDBUS_OUT, + C405PLBDCUWRITETHRU_OUT, + C405PLBICUABORT_OUT, + C405PLBICUABUS_OUT, + C405PLBICUCACHEABLE_OUT, + C405PLBICUPRIORITY_OUT, + C405PLBICUREQUEST_OUT, + C405PLBICUSIZE_OUT, + C405PLBICUU0ATTR_OUT, + C405RSTCHIPRESETREQ_OUT, + C405RSTCORERESETREQ_OUT, + C405RSTSYSRESETREQ_OUT, + C405TRCCYCLE_OUT, + C405TRCEVENEXECUTIONSTATUS_OUT, + C405TRCODDEXECUTIONSTATUS_OUT, + C405TRCTRACESTATUS_OUT, + C405TRCTRIGGEREVENTOUT_OUT, + C405TRCTRIGGEREVENTTYPE_OUT, + C405XXXMACHINECHECK_OUT, + CPMC405CLOCK_ipd_1, + CPMC405CORECLKINACTIVE_ipd_1, + CPMC405CPUCLKEN_ipd_1, + CPMC405JTAGCLKEN_ipd_1, + CPMC405SYNCBYPASS_ipd_1, + CPMC405TIMERCLKEN_ipd_1, + CPMC405TIMERTICK_ipd_1, + CPMDCRCLK_ipd_1, + CPMFCMCLK_ipd_1, + DBGC405DEBUGHALT_ipd_1, + DBGC405EXTBUSHOLDACK_ipd_1, + DBGC405UNCONDDEBUGEVENT_ipd_1, + DCREMACENABLER_OUT, + DSARCVALUE_ipd_1, + DSCNTLVALUE_ipd_1, + DSOCMBRAMABUS_OUT, + DSOCMBRAMBYTEWRITE_OUT, + DSOCMBRAMEN_OUT, + DSOCMBRAMWRDBUS_OUT, + DSOCMBUSY_OUT, + DSOCMRDADDRVALID_OUT, + DSOCMRWCOMPLETE_ipd_1, + DSOCMWRADDRVALID_OUT, + EICC405CRITINPUTIRQ_ipd_1, + EICC405EXTINPUTIRQ_ipd_1, + EXTDCRABUS_OUT, + EXTDCRACK_ipd_1, + EXTDCRDBUSIN_ipd_1, + EXTDCRDBUSOUT_OUT, + EXTDCRREAD_OUT, + EXTDCRWRITE_OUT, + FCMAPUCR_ipd_1, + FCMAPUDCDCREN_ipd_1, + FCMAPUDCDFORCEALIGN_ipd_1, + FCMAPUDCDFORCEBESTEERING_ipd_1, + FCMAPUDCDFPUOP_ipd_1, + FCMAPUDCDGPRWRITE_ipd_1, + FCMAPUDCDLDSTBYTE_ipd_1, + FCMAPUDCDLDSTDW_ipd_1, + FCMAPUDCDLDSTHW_ipd_1, + FCMAPUDCDLDSTQW_ipd_1, + FCMAPUDCDLDSTWD_ipd_1, + FCMAPUDCDLOAD_ipd_1, + FCMAPUDCDPRIVOP_ipd_1, + FCMAPUDCDRAEN_ipd_1, + FCMAPUDCDRBEN_ipd_1, + FCMAPUDCDSTORE_ipd_1, + FCMAPUDCDTRAPBE_ipd_1, + FCMAPUDCDTRAPLE_ipd_1, + FCMAPUDCDUPDATE_ipd_1, + FCMAPUDCDXERCAEN_ipd_1, + FCMAPUDCDXEROVEN_ipd_1, + FCMAPUDECODEBUSY_ipd_1, + FCMAPUDONE_ipd_1, + FCMAPUEXCEPTION_ipd_1, + FCMAPUEXEBLOCKINGMCO_ipd_1, + FCMAPUEXECRFIELD_ipd_1, + FCMAPUEXENONBLOCKINGMCO_ipd_1, + FCMAPUINSTRACK_ipd_1, + FCMAPULOADWAIT_ipd_1, + FCMAPURESULT_ipd_1, + FCMAPURESULTVALID_ipd_1, + FCMAPUSLEEPNOTREADY_ipd_1, + FCMAPUXERCA_ipd_1, + FCMAPUXEROV_ipd_1, + ISARCVALUE_ipd_1, + ISCNTLVALUE_ipd_1, + ISOCMBRAMEN_OUT, + ISOCMBRAMEVENWRITEEN_OUT, + ISOCMBRAMODDWRITEEN_OUT, + ISOCMBRAMRDABUS_OUT, + ISOCMBRAMWRABUS_OUT, + ISOCMBRAMWRDBUS_OUT, + ISOCMDCRBRAMEVENEN_OUT, + ISOCMDCRBRAMODDEN_OUT, + ISOCMDCRBRAMRDSELECT_OUT, + JTGC405BNDSCANTDO_ipd_1, + JTGC405TCK_ipd_1, + JTGC405TDI_ipd_1, + JTGC405TMS_ipd_1, + JTGC405TRSTNEG_ipd_1, + MCBCPUCLKEN_ipd_1, + MCBJTAGEN_ipd_1, + MCBTIMEREN_ipd_1, + MCPPCRST_ipd_1, + PLBC405DCUADDRACK_ipd_1, + PLBC405DCUBUSY_ipd_1, + PLBC405DCUERR_ipd_1, + PLBC405DCURDDACK_ipd_1, + PLBC405DCURDDBUS_ipd_1, + PLBC405DCURDWDADDR_ipd_1, + PLBC405DCUSSIZE1_ipd_1, + PLBC405DCUWRDACK_ipd_1, + PLBC405ICUADDRACK_ipd_1, + PLBC405ICUBUSY_ipd_1, + PLBC405ICUERR_ipd_1, + PLBC405ICURDDACK_ipd_1, + PLBC405ICURDDBUS_ipd_1, + PLBC405ICURDWDADDR_ipd_1, + PLBC405ICUSSIZE1_ipd_1, + PLBCLK_ipd_1, + RSTC405RESETCHIP_ipd_1, + RSTC405RESETCORE_ipd_1, + RSTC405RESETSYS_ipd_1, + TIEAPUCONTROL_ipd_1, + TIEAPUUDI1_ipd_1, + TIEAPUUDI2_ipd_1, + TIEAPUUDI3_ipd_1, + TIEAPUUDI4_ipd_1, + TIEAPUUDI5_ipd_1, + TIEAPUUDI6_ipd_1, + TIEAPUUDI7_ipd_1, + TIEAPUUDI8_ipd_1, + TIEC405DETERMINISTICMULT_ipd_1, + TIEC405DISOPERANDFWD_ipd_1, + TIEC405MMUEN_ipd_1, + TIEDCRADDR_ipd_1, + TIEPVRBIT10_ipd_1, + TIEPVRBIT11_ipd_1, + TIEPVRBIT28_ipd_1, + TIEPVRBIT29_ipd_1, + TIEPVRBIT30_ipd_1, + TIEPVRBIT31_ipd_1, + TIEPVRBIT8_ipd_1, + TIEPVRBIT9_ipd_1, + TRCC405TRACEDISABLE_ipd_1, + TRCC405TRIGGEREVENTIN_ipd_1, + DCREMACWRITE_OUT, + DCREMACREAD_OUT, + DCREMACDBUS_OUT, + DCREMACABUS_OUT, + DCREMACCLK_OUT, + EMACDCRDBUS_ipd_1, + EMACDCRACK_ipd_1; + + end process TIMING; +--C405PLBICUSIZE <= C405PLBICUSIZE_OUT after OUT_DELAY(tr01); +DCREMACABUS <= DCREMACABUS_OUT; +DCREMACCLK <= DCREMACCLK_OUT; +DCREMACDBUS <= DCREMACDBUS_OUT; +DCREMACENABLER <= DCREMACENABLER_OUT; +DCREMACREAD <= DCREMACREAD_OUT; +DCREMACWRITE <= DCREMACWRITE_OUT; +--DSOCMBRAMABUS <= DSOCMBRAMABUS_OUT after OUT_DELAY(tr01); +--ISOCMBRAMRDABUS <= ISOCMBRAMRDABUS_OUT after OUT_DELAY(tr01); +--ISOCMBRAMWRABUS <= ISOCMBRAMWRABUS_OUT after OUT_DELAY(tr01); +end PPC405_ADV_V; + + diff --git a/Common/sim/xilinx/libsrc/unisims/unisim_VCOMP.vhd b/Common/sim/xilinx/libsrc/unisims/unisim_VCOMP.vhd new file mode 100644 index 0000000..8dcf1a4 --- /dev/null +++ b/Common/sim/xilinx/libsrc/unisims/unisim_VCOMP.vhd @@ -0,0 +1,28337 @@ +--************************************************************** +-- Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. +-- File Name : unisim_VCOMP_pre.vhd +-- Library : unisim +-- Release : 10.1 +-- Entity Count : 1112 +-- Generated by : gencomp +--************************************************************** + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +package VCOMPONENTS is +attribute BOX_TYPE : string; + + +-- synopsys translate_off + +----------------------------------------- +----------- FPGA Globals -------------- +----------------------------------------- +signal GSR : std_logic := '0'; +signal GTS : std_logic := '0'; + +----------------------------------------- +----------- CPLD Globals -------------- +----------------------------------------- +signal PRLD : std_logic := '0'; + +----------------------------------------- +----------- JTAG Globals -------------- +----------------------------------------- +signal JTAG_TDO_GLBL : std_logic; +signal JTAG_TDI_GLBL : std_logic := '0'; +signal JTAG_TMS_GLBL : std_logic := '0'; +signal JTAG_TCK_GLBL : std_logic := '0'; +signal JTAG_TRST_GLBL : std_logic := '0'; + +signal JTAG_CAPTURE_GLBL : std_logic := '0'; +signal JTAG_RESET_GLBL : std_logic := '1'; +signal JTAG_SHIFT_GLBL : std_logic := '1'; +signal JTAG_UPDATE_GLBL : std_logic := '0'; + +signal JTAG_SEL1_GLBL : std_logic := '0'; +signal JTAG_SEL2_GLBL : std_logic := '0'; +signal JTAG_SEL3_GLBL : std_logic := '0'; +signal JTAG_SEL4_GLBL : std_logic := '0'; + +signal JTAG_USER_TDO1_GLBL : std_logic := 'Z'; +signal JTAG_USER_TDO2_GLBL : std_logic := 'Z'; +signal JTAG_USER_TDO3_GLBL : std_logic := 'Z'; +signal JTAG_USER_TDO4_GLBL : std_logic := 'Z'; + +-- synopsys translate_on + +-- START COMPONENT +----- component AND2B1 ----- +component AND2B1 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND2B1 : component is "PRIMITIVE"; + +----- component AND2B2 ----- +component AND2B2 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND2B2 : component is "PRIMITIVE"; + +----- component AND2 ----- +component AND2 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND2 : component is "PRIMITIVE"; + +----- component AND3B1 ----- +component AND3B1 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND3B1 : component is "PRIMITIVE"; + +----- component AND3B2 ----- +component AND3B2 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND3B2 : component is "PRIMITIVE"; + +----- component AND3B3 ----- +component AND3B3 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND3B3 : component is "PRIMITIVE"; + +----- component AND3 ----- +component AND3 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND3 : component is "PRIMITIVE"; + +----- component AND4B1 ----- +component AND4B1 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND4B1 : component is "PRIMITIVE"; + +----- component AND4B2 ----- +component AND4B2 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND4B2 : component is "PRIMITIVE"; + +----- component AND4B3 ----- +component AND4B3 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND4B3 : component is "PRIMITIVE"; + +----- component AND4B4 ----- +component AND4B4 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND4B4 : component is "PRIMITIVE"; + +----- component AND4 ----- +component AND4 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND4 : component is "PRIMITIVE"; + +----- component AND5B1 ----- +component AND5B1 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND5B1 : component is "PRIMITIVE"; + +----- component AND5B2 ----- +component AND5B2 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND5B2 : component is "PRIMITIVE"; + +----- component AND5B3 ----- +component AND5B3 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND5B3 : component is "PRIMITIVE"; + +----- component AND5B4 ----- +component AND5B4 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND5B4 : component is "PRIMITIVE"; + +----- component AND5B5 ----- +component AND5B5 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND5B5 : component is "PRIMITIVE"; + +----- component AND5 ----- +component AND5 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND5 : component is "PRIMITIVE"; + +----- component AND6 ----- +component AND6 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND6 : component is "PRIMITIVE"; + +----- component AND7 ----- +component AND7 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic; + I6 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND7 : component is "PRIMITIVE"; + +----- component AND8 ----- +component AND8 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic; + I6 : in std_ulogic; + I7 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + AND8 : component is "PRIMITIVE"; + +----- component BSCAN_FPGACORE ----- +component BSCAN_FPGACORE + port + ( + CAPTURE : out std_ulogic := 'H'; + DRCK1 : out std_ulogic := 'H'; + DRCK2 : out std_ulogic := 'H'; + RESET : out std_ulogic := 'H'; + SEL1 : out std_ulogic := 'L'; + SEL2 : out std_ulogic := 'L'; + SHIFT : out std_ulogic := 'L'; + TDI : out std_ulogic := 'L'; + UPDATE : out std_ulogic := 'L'; + TDO1 : in std_ulogic := 'X'; + TDO2 : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + BSCAN_FPGACORE : component is "PRIMITIVE"; + +----- component BSCAN_SPARTAN2 ----- +component BSCAN_SPARTAN2 + port + ( + DRCK1 : out std_ulogic := 'H'; + DRCK2 : out std_ulogic := 'H'; + RESET : out std_ulogic := 'H'; + SEL1 : out std_ulogic := 'L'; + SEL2 : out std_ulogic := 'L'; + SHIFT : out std_ulogic := 'L'; + TDI : out std_ulogic := 'L'; + UPDATE : out std_ulogic := 'L'; + TDO1 : in std_ulogic := 'X'; + TDO2 : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + BSCAN_SPARTAN2 : component is "PRIMITIVE"; + +----- component BSCAN_SPARTAN3A ----- +component BSCAN_SPARTAN3A + port + ( + CAPTURE : out std_ulogic := 'H'; + DRCK1 : out std_ulogic := 'L'; + DRCK2 : out std_ulogic := 'L'; + RESET : out std_ulogic := 'L'; + SEL1 : out std_ulogic := 'L'; + SEL2 : out std_ulogic := 'L'; + SHIFT : out std_ulogic := 'L'; + TCK : out std_ulogic := 'L'; + TDI : out std_ulogic := 'L'; + TMS : out std_ulogic := 'L'; + UPDATE : out std_ulogic := 'L'; + TDO1 : in std_ulogic := 'X'; + TDO2 : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + BSCAN_SPARTAN3A : component is "PRIMITIVE"; + +----- component BSCAN_SPARTAN3 ----- +component BSCAN_SPARTAN3 + port + ( + CAPTURE : out std_ulogic := 'H'; + DRCK1 : out std_ulogic := 'L'; + DRCK2 : out std_ulogic := 'L'; + RESET : out std_ulogic := 'L'; + SEL1 : out std_ulogic := 'L'; + SEL2 : out std_ulogic := 'L'; + SHIFT : out std_ulogic := 'L'; + TDI : out std_ulogic := 'L'; + UPDATE : out std_ulogic := 'L'; + TDO1 : in std_ulogic := 'X'; + TDO2 : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + BSCAN_SPARTAN3 : component is "PRIMITIVE"; + +----- component BSCAN_VIRTEX2 ----- +component BSCAN_VIRTEX2 + port + ( + CAPTURE : out std_ulogic := 'H'; + DRCK1 : out std_ulogic := 'H'; + DRCK2 : out std_ulogic := 'H'; + RESET : out std_ulogic := 'H'; + SEL1 : out std_ulogic := 'L'; + SEL2 : out std_ulogic := 'L'; + SHIFT : out std_ulogic := 'L'; + TDI : out std_ulogic := 'L'; + UPDATE : out std_ulogic := 'L'; + TDO1 : in std_ulogic := 'X'; + TDO2 : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + BSCAN_VIRTEX2 : component is "PRIMITIVE"; + +----- component BSCAN_VIRTEX4 ----- +component BSCAN_VIRTEX4 + generic + ( + JTAG_CHAIN : integer := 1 + ); + port + ( + CAPTURE : out std_ulogic := 'H'; + DRCK : out std_ulogic := 'H'; + RESET : out std_ulogic := 'H'; + SEL : out std_ulogic := 'L'; + SHIFT : out std_ulogic := 'L'; + TDI : out std_ulogic := 'L'; + UPDATE : out std_ulogic := 'L'; + TDO : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + BSCAN_VIRTEX4 : component is "PRIMITIVE"; + +----- component BSCAN_VIRTEX5 ----- +component BSCAN_VIRTEX5 + generic + ( + JTAG_CHAIN : integer := 1 + ); + port + ( + CAPTURE : out std_ulogic := 'H'; + DRCK : out std_ulogic := 'H'; + RESET : out std_ulogic := 'H'; + SEL : out std_ulogic := 'L'; + SHIFT : out std_ulogic := 'L'; + TDI : out std_ulogic := 'L'; + UPDATE : out std_ulogic := 'L'; + TDO : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + BSCAN_VIRTEX5 : component is "PRIMITIVE"; + +----- component BSCAN_VIRTEX ----- +component BSCAN_VIRTEX + port + ( + DRCK1 : out std_ulogic := 'H'; + DRCK2 : out std_ulogic := 'H'; + RESET : out std_ulogic := 'H'; + SEL1 : out std_ulogic := 'L'; + SEL2 : out std_ulogic := 'L'; + SHIFT : out std_ulogic := 'L'; + TDI : out std_ulogic := 'L'; + UPDATE : out std_ulogic := 'L'; + TDO1 : in std_ulogic := 'X'; + TDO2 : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + BSCAN_VIRTEX : component is "PRIMITIVE"; + +----- component BUFCF ----- +component BUFCF + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + BUFCF : component is "PRIMITIVE"; + +----- component BUFE ----- +component BUFE + port + ( + O : out std_ulogic; + E : in std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + BUFE : component is "PRIMITIVE"; + +----- component BUFFOE ----- +component BUFFOE + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + BUFFOE : component is "PRIMITIVE"; + +----- component BUFGCE_1 ----- +component BUFGCE_1 + port + ( + O : out STD_ULOGIC; + CE : in STD_ULOGIC; + I : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + BUFGCE_1 : component is "PRIMITIVE"; + +----- component BUFGCE ----- +component BUFGCE + port + ( + O : out STD_ULOGIC; + CE : in STD_ULOGIC; + I : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + BUFGCE : component is "PRIMITIVE"; + +----- component BUFGCTRL ----- +component BUFGCTRL + generic + ( + INIT_OUT : integer := 0; + PRESELECT_I0 : boolean := false; + PRESELECT_I1 : boolean := false + ); + port + ( + O : out std_ulogic; + CE0 : in std_ulogic; + CE1 : in std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + IGNORE0 : in std_ulogic; + IGNORE1 : in std_ulogic; + S0 : in std_ulogic; + S1 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + BUFGCTRL : component is "PRIMITIVE"; + +----- component BUFGDLL ----- +component BUFGDLL + generic + ( + DUTY_CYCLE_CORRECTION : boolean := true + ); + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + BUFGDLL : component is "PRIMITIVE"; + +----- component BUFGMUX_1 ----- +component BUFGMUX_1 + port + ( + O : out std_ulogic; + I0 : in std_ulogic := '1'; + I1 : in std_ulogic := '1'; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + BUFGMUX_1 : component is "PRIMITIVE"; + +----- component BUFGMUX_CTRL ----- +component BUFGMUX_CTRL + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + BUFGMUX_CTRL : component is "PRIMITIVE"; + +----- component BUFGMUX ----- +component BUFGMUX + port + ( + O : out std_ulogic; + I0 : in std_ulogic := '0'; + I1 : in std_ulogic := '0'; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + BUFGMUX : component is "PRIMITIVE"; + +----- component BUFGMUX_VIRTEX4 ----- +component BUFGMUX_VIRTEX4 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + BUFGMUX_VIRTEX4 : component is "PRIMITIVE"; + +----- component BUFGP ----- +component BUFGP + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + BUFGP : component is "PRIMITIVE"; + +----- component BUFGSR ----- +component BUFGSR + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + BUFGSR : component is "PRIMITIVE"; + +----- component BUFGTS ----- +component BUFGTS + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + BUFGTS : component is "PRIMITIVE"; + +----- component BUFG ----- +component BUFG + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + BUFG : component is "PRIMITIVE"; + +----- component BUFIO ----- +component BUFIO + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + BUFIO : component is "PRIMITIVE"; + +----- component BUFR ----- +component BUFR + generic + ( + BUFR_DIVIDE : string := "BYPASS"; + SIM_DEVICE : string := "VIRTEX4" + ); + port + ( + O : out std_ulogic; + CE : in std_ulogic; + CLR : in std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + BUFR : component is "PRIMITIVE"; + +----- component BUFT ----- +component BUFT + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + BUFT : component is "PRIMITIVE"; + +----- component BUF ----- +component BUF + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + BUF : component is "PRIMITIVE"; + +----- component CAPTURE_FPGACORE ----- +component CAPTURE_FPGACORE + generic + ( + ONESHOT : boolean := false + ); + port + ( + CAP : in std_ulogic; + CLK : in std_ulogic + ); +end component; +attribute BOX_TYPE of + CAPTURE_FPGACORE : component is "PRIMITIVE"; + +----- component CAPTURE_SPARTAN2 ----- +component CAPTURE_SPARTAN2 + generic + ( + ONESHOT : boolean := false + ); + port + ( + CAP : in std_ulogic; + CLK : in std_ulogic + ); +end component; +attribute BOX_TYPE of + CAPTURE_SPARTAN2 : component is "PRIMITIVE"; + +----- component CAPTURE_SPARTAN3A ----- +component CAPTURE_SPARTAN3A + generic + ( + ONESHOT : boolean := true + ); + port + ( + CAP : in std_ulogic; + CLK : in std_ulogic + ); +end component; +attribute BOX_TYPE of + CAPTURE_SPARTAN3A : component is "PRIMITIVE"; + +----- component CAPTURE_SPARTAN3 ----- +component CAPTURE_SPARTAN3 + generic + ( + ONESHOT : boolean := false + ); + port + ( + CAP : in std_ulogic; + CLK : in std_ulogic + ); +end component; +attribute BOX_TYPE of + CAPTURE_SPARTAN3 : component is "PRIMITIVE"; + +----- component CAPTURE_VIRTEX2 ----- +component CAPTURE_VIRTEX2 + generic + ( + ONESHOT : boolean := false + ); + port + ( + CAP : in std_ulogic; + CLK : in std_ulogic + ); +end component; +attribute BOX_TYPE of + CAPTURE_VIRTEX2 : component is "PRIMITIVE"; + +----- component CAPTURE_VIRTEX4 ----- +component CAPTURE_VIRTEX4 + generic + ( + ONESHOT : boolean := true + ); + port + ( + CAP : in std_ulogic; + CLK : in std_ulogic + ); +end component; +attribute BOX_TYPE of + CAPTURE_VIRTEX4 : component is "PRIMITIVE"; + +----- component CAPTURE_VIRTEX5 ----- +component CAPTURE_VIRTEX5 + generic + ( + ONESHOT : boolean := true + ); + port + ( + CAP : in std_ulogic; + CLK : in std_ulogic + ); +end component; +attribute BOX_TYPE of + CAPTURE_VIRTEX5 : component is "PRIMITIVE"; + +----- component CAPTURE_VIRTEX ----- +component CAPTURE_VIRTEX + generic + ( + ONESHOT : boolean := false + ); + port + ( + CAP : in std_ulogic; + CLK : in std_ulogic + ); +end component; +attribute BOX_TYPE of + CAPTURE_VIRTEX : component is "PRIMITIVE"; + +----- component CARRY4 ----- +component CARRY4 + port + ( + CO : out std_logic_vector(3 downto 0); + O : out std_logic_vector(3 downto 0); + CI : in std_ulogic; + CYINIT : in std_ulogic; + DI : in std_logic_vector(3 downto 0); + S : in std_logic_vector(3 downto 0) + ); +end component; +attribute BOX_TYPE of + CARRY4 : component is "PRIMITIVE"; + +----- component CFGLUT5 ----- +component CFGLUT5 + generic + ( + INIT : bit_vector := X"00000000" + ); + port + ( + CDO : out STD_ULOGIC; + O5 : out STD_ULOGIC; + O6 : out STD_ULOGIC; + CDI : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC; + I3 : in STD_ULOGIC; + I4 : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + CFGLUT5 : component is "PRIMITIVE"; + +----- component CLK_DIV10RSD ----- +component CLK_DIV10RSD + generic + ( + DIVIDE_BY : integer := 10; + DIVIDER_DELAY : integer := 1 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV10RSD : component is "PRIMITIVE"; + +----- component CLK_DIV10R ----- +component CLK_DIV10R + generic + ( + DIVIDE_BY : integer := 10 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV10R : component is "PRIMITIVE"; + +----- component CLK_DIV10SD ----- +component CLK_DIV10SD + generic + ( + DIVIDE_BY : integer := 10; + DIVIDER_DELAY : integer := 1 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV10SD : component is "PRIMITIVE"; + +----- component CLK_DIV10 ----- +component CLK_DIV10 + generic + ( + DIVIDE_BY : integer := 10 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV10 : component is "PRIMITIVE"; + +----- component CLK_DIV12RSD ----- +component CLK_DIV12RSD + generic + ( + DIVIDE_BY : integer := 12; + DIVIDER_DELAY : integer := 1 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV12RSD : component is "PRIMITIVE"; + +----- component CLK_DIV12R ----- +component CLK_DIV12R + generic + ( + DIVIDE_BY : integer := 12 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV12R : component is "PRIMITIVE"; + +----- component CLK_DIV12SD ----- +component CLK_DIV12SD + generic + ( + DIVIDE_BY : integer := 12; + DIVIDER_DELAY : integer := 1 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV12SD : component is "PRIMITIVE"; + +----- component CLK_DIV12 ----- +component CLK_DIV12 + generic + ( + DIVIDE_BY : integer := 12 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV12 : component is "PRIMITIVE"; + +----- component CLK_DIV14RSD ----- +component CLK_DIV14RSD + generic + ( + DIVIDE_BY : integer := 14; + DIVIDER_DELAY : integer := 1 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV14RSD : component is "PRIMITIVE"; + +----- component CLK_DIV14R ----- +component CLK_DIV14R + generic + ( + DIVIDE_BY : integer := 14 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV14R : component is "PRIMITIVE"; + +----- component CLK_DIV14SD ----- +component CLK_DIV14SD + generic + ( + DIVIDE_BY : integer := 14; + DIVIDER_DELAY : integer := 1 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV14SD : component is "PRIMITIVE"; + +----- component CLK_DIV14 ----- +component CLK_DIV14 + generic + ( + DIVIDE_BY : integer := 14 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV14 : component is "PRIMITIVE"; + +----- component CLK_DIV16RSD ----- +component CLK_DIV16RSD + generic + ( + DIVIDE_BY : integer := 16; + DIVIDER_DELAY : integer := 1 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV16RSD : component is "PRIMITIVE"; + +----- component CLK_DIV16R ----- +component CLK_DIV16R + generic + ( + DIVIDE_BY : integer := 16 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV16R : component is "PRIMITIVE"; + +----- component CLK_DIV16SD ----- +component CLK_DIV16SD + generic + ( + DIVIDE_BY : integer := 16; + DIVIDER_DELAY : integer := 1 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV16SD : component is "PRIMITIVE"; + +----- component CLK_DIV16 ----- +component CLK_DIV16 + generic + ( + DIVIDE_BY : integer := 16 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV16 : component is "PRIMITIVE"; + +----- component CLK_DIV2RSD ----- +component CLK_DIV2RSD + generic + ( + DIVIDE_BY : integer := 2; + DIVIDER_DELAY : integer := 1 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV2RSD : component is "PRIMITIVE"; + +----- component CLK_DIV2R ----- +component CLK_DIV2R + generic + ( + DIVIDE_BY : integer := 2 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV2R : component is "PRIMITIVE"; + +----- component CLK_DIV2SD ----- +component CLK_DIV2SD + generic + ( + DIVIDE_BY : integer := 2; + DIVIDER_DELAY : integer := 1 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV2SD : component is "PRIMITIVE"; + +----- component CLK_DIV2 ----- +component CLK_DIV2 + generic + ( + DIVIDE_BY : integer := 2 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV2 : component is "PRIMITIVE"; + +----- component CLK_DIV4RSD ----- +component CLK_DIV4RSD + generic + ( + DIVIDE_BY : integer := 4; + DIVIDER_DELAY : integer := 1 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV4RSD : component is "PRIMITIVE"; + +----- component CLK_DIV4R ----- +component CLK_DIV4R + generic + ( + DIVIDE_BY : integer := 4 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV4R : component is "PRIMITIVE"; + +----- component CLK_DIV4SD ----- +component CLK_DIV4SD + generic + ( + DIVIDE_BY : integer := 4; + DIVIDER_DELAY : integer := 1 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV4SD : component is "PRIMITIVE"; + +----- component CLK_DIV4 ----- +component CLK_DIV4 + generic + ( + DIVIDE_BY : integer := 4 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV4 : component is "PRIMITIVE"; + +----- component CLK_DIV6RSD ----- +component CLK_DIV6RSD + generic + ( + DIVIDE_BY : integer := 6; + DIVIDER_DELAY : integer := 1 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV6RSD : component is "PRIMITIVE"; + +----- component CLK_DIV6R ----- +component CLK_DIV6R + generic + ( + DIVIDE_BY : integer := 6 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV6R : component is "PRIMITIVE"; + +----- component CLK_DIV6SD ----- +component CLK_DIV6SD + generic + ( + DIVIDE_BY : integer := 6; + DIVIDER_DELAY : integer := 1 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV6SD : component is "PRIMITIVE"; + +----- component CLK_DIV6 ----- +component CLK_DIV6 + generic + ( + DIVIDE_BY : integer := 6 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV6 : component is "PRIMITIVE"; + +----- component CLK_DIV8RSD ----- +component CLK_DIV8RSD + generic + ( + DIVIDE_BY : integer := 8; + DIVIDER_DELAY : integer := 1 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV8RSD : component is "PRIMITIVE"; + +----- component CLK_DIV8R ----- +component CLK_DIV8R + generic + ( + DIVIDE_BY : integer := 8 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV8R : component is "PRIMITIVE"; + +----- component CLK_DIV8SD ----- +component CLK_DIV8SD + generic + ( + DIVIDE_BY : integer := 8; + DIVIDER_DELAY : integer := 1 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV8SD : component is "PRIMITIVE"; + +----- component CLK_DIV8 ----- +component CLK_DIV8 + generic + ( + DIVIDE_BY : integer := 8 + ); + port + ( + CLKDV : out std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLK_DIV8 : component is "PRIMITIVE"; + +----- component CLKDLLE ----- +component CLKDLLE + generic + ( + CLKDV_DIVIDE : real := 2.0; + DUTY_CYCLE_CORRECTION : boolean := true; + FACTORY_JF : bit_vector := X"C080"; + STARTUP_WAIT : boolean := false --non-simulatable + ); + port + ( + CLK0 : out std_ulogic := '0'; + CLK180 : out std_ulogic := '0'; + CLK270 : out std_ulogic := '0'; + CLK2X : out std_ulogic := '0'; + CLK2X180 : out std_ulogic := '0'; + CLK90 : out std_ulogic := '0'; + CLKDV : out std_ulogic := '0'; + LOCKED : out std_ulogic := '0'; + CLKFB : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0'; + RST : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLKDLLE : component is "PRIMITIVE"; + +----- component CLKDLLHF ----- +component CLKDLLHF + generic + ( + CLKDV_DIVIDE : real := 2.0; + DUTY_CYCLE_CORRECTION : boolean := true; + FACTORY_JF : bit_vector := X"FFF0"; + STARTUP_WAIT : boolean := false --non-simulatable + ); + port + ( + CLK0 : out std_ulogic := '0'; + CLK180 : out std_ulogic := '0'; + CLKDV : out std_ulogic := '0'; + LOCKED : out std_ulogic := '0'; + CLKFB : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0'; + RST : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLKDLLHF : component is "PRIMITIVE"; + +----- component CLKDLL ----- +component CLKDLL + generic + ( + CLKDV_DIVIDE : real := 2.0; + DUTY_CYCLE_CORRECTION : boolean := true; + FACTORY_JF : bit_vector := X"C080"; + STARTUP_WAIT : boolean := false --non-simulatable + ); + port + ( + CLK0 : out std_ulogic := '0'; + CLK180 : out std_ulogic := '0'; + CLK270 : out std_ulogic := '0'; + CLK2X : out std_ulogic := '0'; + CLK90 : out std_ulogic := '0'; + CLKDV : out std_ulogic := '0'; + LOCKED : out std_ulogic := '0'; + CLKFB : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0'; + RST : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + CLKDLL : component is "PRIMITIVE"; + +----- component CONFIG ----- +component CONFIG +end component; +attribute BOX_TYPE of + CONFIG : component is "PRIMITIVE"; + +----- component CRC32 ----- +component CRC32 + generic + ( + CRC_INIT : bit_vector := X"FFFFFFFF" + ); + port + ( + CRCOUT : out std_logic_vector(31 downto 0); + CRCCLK : in std_ulogic; + CRCDATAVALID : in std_ulogic; + CRCDATAWIDTH : in std_logic_vector(2 downto 0); + CRCIN : in std_logic_vector(31 downto 0); + CRCRESET : in std_ulogic + ); +end component; +attribute BOX_TYPE of + CRC32 : component is "PRIMITIVE"; + +----- component CRC64 ----- +component CRC64 + generic + ( + CRC_INIT : bit_vector := X"FFFFFFFF" + ); + port + ( + CRCOUT : out std_logic_vector(31 downto 0); + CRCCLK : in std_ulogic; + CRCDATAVALID : in std_ulogic; + CRCDATAWIDTH : in std_logic_vector(2 downto 0); + CRCIN : in std_logic_vector(63 downto 0); + CRCRESET : in std_ulogic + ); +end component; +attribute BOX_TYPE of + CRC64 : component is "PRIMITIVE"; + +----- component DCC_FPGACORE ----- +component DCC_FPGACORE + generic + ( + DEVICE_SIZE : integer := 10 + ); + port + ( + BCLK : out std_ulogic; + DONEOUT : out std_ulogic; + DOUT0 : out std_ulogic; + DOUT1 : out std_ulogic; + DOUT2 : out std_ulogic; + DOUT3 : out std_ulogic; + DOUT4 : out std_ulogic; + DOUT5 : out std_ulogic; + DOUT6 : out std_ulogic; + DOUT7 : out std_ulogic; + GSR : out std_ulogic; + GTS : out std_ulogic; + GWE : out std_ulogic; + INITBOUT : out std_ulogic; + TDO : out std_ulogic; + CCLK : in std_ulogic; + CSB : in std_ulogic; + DIN0 : in std_ulogic; + DIN1 : in std_ulogic; + DIN2 : in std_ulogic; + DIN3 : in std_ulogic; + DIN4 : in std_ulogic; + DIN5 : in std_ulogic; + DIN6 : in std_ulogic; + DIN7 : in std_ulogic; + DONEIN : in std_ulogic; + LBISTISOLATEB : in std_ulogic; + M0 : in std_ulogic; + M1 : in std_ulogic; + M2 : in std_ulogic; + PROGB : in std_ulogic; + TCK : in std_ulogic; + TDI : in std_ulogic; + TMS : in std_ulogic; + WRITEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + DCC_FPGACORE : component is "PRIMITIVE"; + +----- component DCIRESET ----- +component DCIRESET + port + ( + LOCKED : out std_ulogic; + RST : in std_ulogic + ); +end component; +attribute BOX_TYPE of + DCIRESET : component is "PRIMITIVE"; + +----- component DCM_ADV ----- +component DCM_ADV + generic + ( + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := false; + CLKIN_PERIOD : real := 10.0; + CLKOUT_PHASE_SHIFT : string := "NONE"; + CLK_FEEDBACK : string := "1X"; + DCM_AUTOCALIBRATION : boolean := true; + DCM_PERFORMANCE_MODE : string := "MAX_SPEED"; + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DUTY_CYCLE_CORRECTION : boolean := true; + FACTORY_JF : bit_vector := X"F0F0"; + PHASE_SHIFT : integer := 0; + SIM_DEVICE : string := "VIRTEX4"; + STARTUP_WAIT : boolean := false --non-simulatable + ); + port + ( + CLK0 : out std_ulogic := '0'; + CLK180 : out std_ulogic := '0'; + CLK270 : out std_ulogic := '0'; + CLK2X : out std_ulogic := '0'; + CLK2X180 : out std_ulogic := '0'; + CLK90 : out std_ulogic := '0'; + CLKDV : out std_ulogic := '0'; + CLKFX : out std_ulogic := '0'; + CLKFX180 : out std_ulogic := '0'; + DO : out std_logic_vector(15 downto 0) := "0000000000000000"; + DRDY : out std_ulogic := '0'; + LOCKED : out std_ulogic := '0'; + PSDONE : out std_ulogic := '0'; + CLKFB : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0'; + DADDR : in std_logic_vector(6 downto 0) := "0000000"; + DCLK : in std_ulogic := '0'; + DEN : in std_ulogic := '0'; + DI : in std_logic_vector(15 downto 0) := "0000000000000000"; + DWE : in std_ulogic := '0'; + PSCLK : in std_ulogic := '0'; + PSEN : in std_ulogic := '0'; + PSINCDEC : in std_ulogic := '0'; + RST : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + DCM_ADV : component is "PRIMITIVE"; + +----- component DCM_BASE ----- +component DCM_BASE + generic + ( + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := FALSE; + CLKIN_PERIOD : real := 10.0; + CLKOUT_PHASE_SHIFT : string := "NONE"; + CLK_FEEDBACK : string := "1X"; + DCM_AUTOCALIBRATION : boolean := TRUE; + DCM_PERFORMANCE_MODE : string := "MAX_SPEED"; + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DUTY_CYCLE_CORRECTION : boolean := TRUE; + FACTORY_JF : bit_vector := X"F0F0"; + PHASE_SHIFT : integer := 0; + STARTUP_WAIT : boolean := false + ); + port + ( + CLK0 : out std_ulogic; + CLK180 : out std_ulogic; + CLK270 : out std_ulogic; + CLK2X : out std_ulogic; + CLK2X180 : out std_ulogic; + CLK90 : out std_ulogic; + CLKDV : out std_ulogic; + CLKFX : out std_ulogic; + CLKFX180 : out std_ulogic; + LOCKED : out std_ulogic; + CLKFB : in std_ulogic; + CLKIN : in std_ulogic; + RST : in std_ulogic + ); +end component; +attribute BOX_TYPE of + DCM_BASE : component is "PRIMITIVE"; + +----- component DCM_PS ----- +component DCM_PS + generic + ( + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := FALSE; + CLKIN_PERIOD : real := 10.0; + CLKOUT_PHASE_SHIFT : string := "NONE"; + CLK_FEEDBACK : string := "1X"; + DCM_AUTOCALIBRATION : boolean := TRUE; + DCM_PERFORMANCE_MODE : string := "MAX_SPEED"; + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DUTY_CYCLE_CORRECTION : boolean := TRUE; + FACTORY_JF : bit_vector := X"F0F0"; + PHASE_SHIFT : integer := 0; + STARTUP_WAIT : boolean := FALSE + ); + port + ( + CLK0 : out std_ulogic; + CLK180 : out std_ulogic; + CLK270 : out std_ulogic; + CLK2X : out std_ulogic; + CLK2X180 : out std_ulogic; + CLK90 : out std_ulogic; + CLKDV : out std_ulogic; + CLKFX : out std_ulogic; + CLKFX180 : out std_ulogic; + DO : out std_logic_vector(15 downto 0); + LOCKED : out std_ulogic; + PSDONE : out std_ulogic; + CLKFB : in std_ulogic; + CLKIN : in std_ulogic; + PSCLK : in std_ulogic; + PSEN : in std_ulogic; + PSINCDEC : in std_ulogic; + RST : in std_ulogic + ); +end component; +attribute BOX_TYPE of + DCM_PS : component is "PRIMITIVE"; + +----- component DCM_SP ----- +component DCM_SP + generic + ( + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := false; + CLKIN_PERIOD : real := 10.0; + CLKOUT_PHASE_SHIFT : string := "NONE"; + CLK_FEEDBACK : string := "1X"; + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DSS_MODE : string := "NONE"; + DUTY_CYCLE_CORRECTION : boolean := true; + FACTORY_JF : bit_vector := X"C080"; + PHASE_SHIFT : integer := 0; + STARTUP_WAIT : boolean := false --non-simulatable + ); + port + ( + CLK0 : out std_ulogic := '0'; + CLK180 : out std_ulogic := '0'; + CLK270 : out std_ulogic := '0'; + CLK2X : out std_ulogic := '0'; + CLK2X180 : out std_ulogic := '0'; + CLK90 : out std_ulogic := '0'; + CLKDV : out std_ulogic := '0'; + CLKFX : out std_ulogic := '0'; + CLKFX180 : out std_ulogic := '0'; + LOCKED : out std_ulogic := '0'; + PSDONE : out std_ulogic := '0'; + STATUS : out std_logic_vector(7 downto 0) := "00000000"; + CLKFB : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0'; + DSSEN : in std_ulogic := '0'; + PSCLK : in std_ulogic := '0'; + PSEN : in std_ulogic := '0'; + PSINCDEC : in std_ulogic := '0'; + RST : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + DCM_SP : component is "PRIMITIVE"; + +----- component DCM ----- +component DCM + generic + ( + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := false; + CLKIN_PERIOD : real := 10.0; + CLKOUT_PHASE_SHIFT : string := "NONE"; + CLK_FEEDBACK : string := "1X"; + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DSS_MODE : string := "NONE"; + DUTY_CYCLE_CORRECTION : boolean := true; + FACTORY_JF : bit_vector := X"C080"; + PHASE_SHIFT : integer := 0; + SIM_MODE : string := "SAFE"; + STARTUP_WAIT : boolean := false --non-simulatable + ); + port + ( + CLK0 : out std_ulogic := '0'; + CLK180 : out std_ulogic := '0'; + CLK270 : out std_ulogic := '0'; + CLK2X : out std_ulogic := '0'; + CLK2X180 : out std_ulogic := '0'; + CLK90 : out std_ulogic := '0'; + CLKDV : out std_ulogic := '0'; + CLKFX : out std_ulogic := '0'; + CLKFX180 : out std_ulogic := '0'; + LOCKED : out std_ulogic := '0'; + PSDONE : out std_ulogic := '0'; + STATUS : out std_logic_vector(7 downto 0) := "00000000"; + CLKFB : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0'; + DSSEN : in std_ulogic := '0'; + PSCLK : in std_ulogic := '0'; + PSEN : in std_ulogic := '0'; + PSINCDEC : in std_ulogic := '0'; + RST : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + DCM : component is "PRIMITIVE"; + +----- component DNA_PORT ----- +component DNA_PORT + generic + ( + SIM_DNA_VALUE : bit_vector := X"000000000000000" + ); + port + ( + DOUT : out std_ulogic; + CLK : in std_ulogic; + DIN : in std_ulogic; + READ : in std_ulogic; + SHIFT : in std_ulogic + ); +end component; +attribute BOX_TYPE of + DNA_PORT : component is "PRIMITIVE"; + +----- component DSP48A ----- +component DSP48A + generic + ( + A0REG : integer := 0; + A1REG : integer := 1; + B0REG : integer := 0; + B1REG : integer := 1; + CARRYINREG : integer := 1; + CARRYINSEL : string := "CARRYIN"; + CREG : integer := 1; + DREG : integer := 1; + MREG : integer := 1; + OPMODEREG : integer := 1; + PREG : integer := 1; + RSTTYPE : string := "SYNC" + ); + port + ( + BCOUT : out std_logic_vector(17 downto 0); + CARRYOUT : out std_ulogic; + P : out std_logic_vector(47 downto 0); + PCOUT : out std_logic_vector(47 downto 0); + A : in std_logic_vector(17 downto 0); + B : in std_logic_vector(17 downto 0); + C : in std_logic_vector(47 downto 0); + CARRYIN : in std_ulogic; + CEA : in std_ulogic; + CEB : in std_ulogic; + CEC : in std_ulogic; + CECARRYIN : in std_ulogic; + CED : in std_ulogic; + CEM : in std_ulogic; + CEOPMODE : in std_ulogic; + CEP : in std_ulogic; + CLK : in std_ulogic; + D : in std_logic_vector(17 downto 0); + OPMODE : in std_logic_vector(7 downto 0); + PCIN : in std_logic_vector(47 downto 0); + RSTA : in std_ulogic; + RSTB : in std_ulogic; + RSTC : in std_ulogic; + RSTCARRYIN : in std_ulogic; + RSTD : in std_ulogic; + RSTM : in std_ulogic; + RSTOPMODE : in std_ulogic; + RSTP : in std_ulogic + ); +end component; +attribute BOX_TYPE of + DSP48A : component is "PRIMITIVE"; + +----- component DSP48E ----- +component DSP48E + generic + ( + SIM_MODE : string := "SAFE"; + ACASCREG : integer := 1; + ALUMODEREG : integer := 1; + AREG : integer := 1; + AUTORESET_PATTERN_DETECT : boolean := FALSE; + AUTORESET_PATTERN_DETECT_OPTINV : string := "MATCH"; + A_INPUT : string := "DIRECT"; + BCASCREG : integer := 1; + BREG : integer := 1; + B_INPUT : string := "DIRECT"; + CARRYINREG : integer := 1; + CARRYINSELREG : integer := 1; + CREG : integer := 1; + MASK : bit_vector := X"3FFFFFFFFFFF"; + MREG : integer := 1; + MULTCARRYINREG : integer := 1; + OPMODEREG : integer := 1; + PATTERN : bit_vector := X"000000000000"; + PREG : integer := 1; + SEL_MASK : string := "MASK"; + SEL_PATTERN : string := "PATTERN"; + SEL_ROUNDING_MASK : string := "SEL_MASK"; + USE_MULT : string := "MULT_S"; + USE_PATTERN_DETECT : string := "NO_PATDET"; + USE_SIMD : string := "ONE48" + ); + port + ( + ACOUT : out std_logic_vector(29 downto 0); + BCOUT : out std_logic_vector(17 downto 0); + CARRYCASCOUT : out std_ulogic; + CARRYOUT : out std_logic_vector(3 downto 0); + MULTSIGNOUT : out std_ulogic; + OVERFLOW : out std_ulogic; + P : out std_logic_vector(47 downto 0); + PATTERNBDETECT : out std_ulogic; + PATTERNDETECT : out std_ulogic; + PCOUT : out std_logic_vector(47 downto 0); + UNDERFLOW : out std_ulogic; + A : in std_logic_vector(29 downto 0); + ACIN : in std_logic_vector(29 downto 0); + ALUMODE : in std_logic_vector(3 downto 0); + B : in std_logic_vector(17 downto 0); + BCIN : in std_logic_vector(17 downto 0); + C : in std_logic_vector(47 downto 0); + CARRYCASCIN : in std_ulogic; + CARRYIN : in std_ulogic; + CARRYINSEL : in std_logic_vector(2 downto 0); + CEA1 : in std_ulogic; + CEA2 : in std_ulogic; + CEALUMODE : in std_ulogic; + CEB1 : in std_ulogic; + CEB2 : in std_ulogic; + CEC : in std_ulogic; + CECARRYIN : in std_ulogic; + CECTRL : in std_ulogic; + CEM : in std_ulogic; + CEMULTCARRYIN : in std_ulogic; + CEP : in std_ulogic; + CLK : in std_ulogic; + MULTSIGNIN : in std_ulogic; + OPMODE : in std_logic_vector(6 downto 0); + PCIN : in std_logic_vector(47 downto 0); + RSTA : in std_ulogic; + RSTALLCARRYIN : in std_ulogic; + RSTALUMODE : in std_ulogic; + RSTB : in std_ulogic; + RSTC : in std_ulogic; + RSTCTRL : in std_ulogic; + RSTM : in std_ulogic; + RSTP : in std_ulogic + ); +end component; +attribute BOX_TYPE of + DSP48E : component is "PRIMITIVE"; + +----- component DSP48 ----- +component DSP48 + generic + ( + AREG : integer := 1; + B_INPUT : string := "DIRECT"; + BREG : integer := 1; + CARRYINREG : integer := 1; + CARRYINSELREG : integer := 1; + CREG : integer := 1; + LEGACY_MODE : string := "MULT18X18S"; + MREG : integer := 1; + OPMODEREG : integer := 1; + PREG : integer := 1; + SUBTRACTREG : integer := 1 + ); + port + ( + BCOUT : out std_logic_vector(17 downto 0); + P : out std_logic_vector(47 downto 0); + PCOUT : out std_logic_vector(47 downto 0); + A : in std_logic_vector(17 downto 0); + B : in std_logic_vector(17 downto 0); + BCIN : in std_logic_vector(17 downto 0); + C : in std_logic_vector(47 downto 0); + CARRYIN : in std_ulogic; + CARRYINSEL : in std_logic_vector(1 downto 0); + CEA : in std_ulogic; + CEB : in std_ulogic; + CEC : in std_ulogic; + CECARRYIN : in std_ulogic; + CECINSUB : in std_ulogic; + CECTRL : in std_ulogic; + CEM : in std_ulogic; + CEP : in std_ulogic; + CLK : in std_ulogic; + OPMODE : in std_logic_vector(6 downto 0); + PCIN : in std_logic_vector(47 downto 0); + RSTA : in std_ulogic; + RSTB : in std_ulogic; + RSTC : in std_ulogic; + RSTCARRYIN : in std_ulogic; + RSTCTRL : in std_ulogic; + RSTM : in std_ulogic; + RSTP : in std_ulogic; + SUBTRACT : in std_ulogic + ); +end component; +attribute BOX_TYPE of + DSP48 : component is "PRIMITIVE"; + +----- component EMAC ----- +component EMAC + generic + ( + IN_DELAY : time := 0 ps + ); + port + ( + DCRHOSTDONEIR : out std_ulogic; + EMAC0CLIENTANINTERRUPT : out std_ulogic; + EMAC0CLIENTRXBADFRAME : out std_ulogic; + EMAC0CLIENTRXCLIENTCLKOUT : out std_ulogic; + EMAC0CLIENTRXD : out std_logic_vector(15 downto 0); + EMAC0CLIENTRXDVLD : out std_ulogic; + EMAC0CLIENTRXDVLDMSW : out std_ulogic; + EMAC0CLIENTRXDVREG6 : out std_ulogic; + EMAC0CLIENTRXFRAMEDROP : out std_ulogic; + EMAC0CLIENTRXGOODFRAME : out std_ulogic; + EMAC0CLIENTRXSTATS : out std_logic_vector(6 downto 0); + EMAC0CLIENTRXSTATSBYTEVLD : out std_ulogic; + EMAC0CLIENTRXSTATSVLD : out std_ulogic; + EMAC0CLIENTTXACK : out std_ulogic; + EMAC0CLIENTTXCLIENTCLKOUT : out std_ulogic; + EMAC0CLIENTTXCOLLISION : out std_ulogic; + EMAC0CLIENTTXGMIIMIICLKOUT : out std_ulogic; + EMAC0CLIENTTXRETRANSMIT : out std_ulogic; + EMAC0CLIENTTXSTATS : out std_ulogic; + EMAC0CLIENTTXSTATSBYTEVLD : out std_ulogic; + EMAC0CLIENTTXSTATSVLD : out std_ulogic; + EMAC0PHYENCOMMAALIGN : out std_ulogic; + EMAC0PHYLOOPBACKMSB : out std_ulogic; + EMAC0PHYMCLKOUT : out std_ulogic; + EMAC0PHYMDOUT : out std_ulogic; + EMAC0PHYMDTRI : out std_ulogic; + EMAC0PHYMGTRXRESET : out std_ulogic; + EMAC0PHYMGTTXRESET : out std_ulogic; + EMAC0PHYPOWERDOWN : out std_ulogic; + EMAC0PHYSYNCACQSTATUS : out std_ulogic; + EMAC0PHYTXCHARDISPMODE : out std_ulogic; + EMAC0PHYTXCHARDISPVAL : out std_ulogic; + EMAC0PHYTXCHARISK : out std_ulogic; + EMAC0PHYTXCLK : out std_ulogic; + EMAC0PHYTXD : out std_logic_vector(7 downto 0); + EMAC0PHYTXEN : out std_ulogic; + EMAC0PHYTXER : out std_ulogic; + EMAC1CLIENTANINTERRUPT : out std_ulogic; + EMAC1CLIENTRXBADFRAME : out std_ulogic; + EMAC1CLIENTRXCLIENTCLKOUT : out std_ulogic; + EMAC1CLIENTRXD : out std_logic_vector(15 downto 0); + EMAC1CLIENTRXDVLD : out std_ulogic; + EMAC1CLIENTRXDVLDMSW : out std_ulogic; + EMAC1CLIENTRXDVREG6 : out std_ulogic; + EMAC1CLIENTRXFRAMEDROP : out std_ulogic; + EMAC1CLIENTRXGOODFRAME : out std_ulogic; + EMAC1CLIENTRXSTATS : out std_logic_vector(6 downto 0); + EMAC1CLIENTRXSTATSBYTEVLD : out std_ulogic; + EMAC1CLIENTRXSTATSVLD : out std_ulogic; + EMAC1CLIENTTXACK : out std_ulogic; + EMAC1CLIENTTXCLIENTCLKOUT : out std_ulogic; + EMAC1CLIENTTXCOLLISION : out std_ulogic; + EMAC1CLIENTTXGMIIMIICLKOUT : out std_ulogic; + EMAC1CLIENTTXRETRANSMIT : out std_ulogic; + EMAC1CLIENTTXSTATS : out std_ulogic; + EMAC1CLIENTTXSTATSBYTEVLD : out std_ulogic; + EMAC1CLIENTTXSTATSVLD : out std_ulogic; + EMAC1PHYENCOMMAALIGN : out std_ulogic; + EMAC1PHYLOOPBACKMSB : out std_ulogic; + EMAC1PHYMCLKOUT : out std_ulogic; + EMAC1PHYMDOUT : out std_ulogic; + EMAC1PHYMDTRI : out std_ulogic; + EMAC1PHYMGTRXRESET : out std_ulogic; + EMAC1PHYMGTTXRESET : out std_ulogic; + EMAC1PHYPOWERDOWN : out std_ulogic; + EMAC1PHYSYNCACQSTATUS : out std_ulogic; + EMAC1PHYTXCHARDISPMODE : out std_ulogic; + EMAC1PHYTXCHARDISPVAL : out std_ulogic; + EMAC1PHYTXCHARISK : out std_ulogic; + EMAC1PHYTXCLK : out std_ulogic; + EMAC1PHYTXD : out std_logic_vector(7 downto 0); + EMAC1PHYTXEN : out std_ulogic; + EMAC1PHYTXER : out std_ulogic; + EMACDCRACK : out std_ulogic; + EMACDCRDBUS : out std_logic_vector(0 to 31); + HOSTMIIMRDY : out std_ulogic; + HOSTRDDATA : out std_logic_vector(31 downto 0); + CLIENTEMAC0DCMLOCKED : in std_ulogic; + CLIENTEMAC0PAUSEREQ : in std_ulogic; + CLIENTEMAC0PAUSEVAL : in std_logic_vector(15 downto 0); + CLIENTEMAC0RXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC0TXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC0TXD : in std_logic_vector(15 downto 0); + CLIENTEMAC0TXDVLD : in std_ulogic; + CLIENTEMAC0TXDVLDMSW : in std_ulogic; + CLIENTEMAC0TXFIRSTBYTE : in std_ulogic; + CLIENTEMAC0TXGMIIMIICLKIN : in std_ulogic; + CLIENTEMAC0TXIFGDELAY : in std_logic_vector(7 downto 0); + CLIENTEMAC0TXUNDERRUN : in std_ulogic; + CLIENTEMAC1DCMLOCKED : in std_ulogic; + CLIENTEMAC1PAUSEREQ : in std_ulogic; + CLIENTEMAC1PAUSEVAL : in std_logic_vector(15 downto 0); + CLIENTEMAC1RXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC1TXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC1TXD : in std_logic_vector(15 downto 0); + CLIENTEMAC1TXDVLD : in std_ulogic; + CLIENTEMAC1TXDVLDMSW : in std_ulogic; + CLIENTEMAC1TXFIRSTBYTE : in std_ulogic; + CLIENTEMAC1TXGMIIMIICLKIN : in std_ulogic; + CLIENTEMAC1TXIFGDELAY : in std_logic_vector(7 downto 0); + CLIENTEMAC1TXUNDERRUN : in std_ulogic; + DCREMACABUS : in std_logic_vector(8 to 9); + DCREMACCLK : in std_ulogic; + DCREMACDBUS : in std_logic_vector(0 to 31); + DCREMACENABLE : in std_ulogic; + DCREMACREAD : in std_ulogic; + DCREMACWRITE : in std_ulogic; + HOSTADDR : in std_logic_vector(9 downto 0); + HOSTCLK : in std_ulogic; + HOSTEMAC1SEL : in std_ulogic; + HOSTMIIMSEL : in std_ulogic; + HOSTOPCODE : in std_logic_vector(1 downto 0); + HOSTREQ : in std_ulogic; + HOSTWRDATA : in std_logic_vector(31 downto 0); + PHYEMAC0COL : in std_ulogic; + PHYEMAC0CRS : in std_ulogic; + PHYEMAC0GTXCLK : in std_ulogic; + PHYEMAC0MCLKIN : in std_ulogic; + PHYEMAC0MDIN : in std_ulogic; + PHYEMAC0MIITXCLK : in std_ulogic; + PHYEMAC0PHYAD : in std_logic_vector(4 downto 0); + PHYEMAC0RXBUFERR : in std_ulogic; + PHYEMAC0RXBUFSTATUS : in std_logic_vector(1 downto 0); + PHYEMAC0RXCHARISCOMMA : in std_ulogic; + PHYEMAC0RXCHARISK : in std_ulogic; + PHYEMAC0RXCHECKINGCRC : in std_ulogic; + PHYEMAC0RXCLK : in std_ulogic; + PHYEMAC0RXCLKCORCNT : in std_logic_vector(2 downto 0); + PHYEMAC0RXCOMMADET : in std_ulogic; + PHYEMAC0RXD : in std_logic_vector(7 downto 0); + PHYEMAC0RXDISPERR : in std_ulogic; + PHYEMAC0RXDV : in std_ulogic; + PHYEMAC0RXER : in std_ulogic; + PHYEMAC0RXLOSSOFSYNC : in std_logic_vector(1 downto 0); + PHYEMAC0RXNOTINTABLE : in std_ulogic; + PHYEMAC0RXRUNDISP : in std_ulogic; + PHYEMAC0SIGNALDET : in std_ulogic; + PHYEMAC0TXBUFERR : in std_ulogic; + PHYEMAC1COL : in std_ulogic; + PHYEMAC1CRS : in std_ulogic; + PHYEMAC1GTXCLK : in std_ulogic; + PHYEMAC1MCLKIN : in std_ulogic; + PHYEMAC1MDIN : in std_ulogic; + PHYEMAC1MIITXCLK : in std_ulogic; + PHYEMAC1PHYAD : in std_logic_vector(4 downto 0); + PHYEMAC1RXBUFERR : in std_ulogic; + PHYEMAC1RXBUFSTATUS : in std_logic_vector(1 downto 0); + PHYEMAC1RXCHARISCOMMA : in std_ulogic; + PHYEMAC1RXCHARISK : in std_ulogic; + PHYEMAC1RXCHECKINGCRC : in std_ulogic; + PHYEMAC1RXCLK : in std_ulogic; + PHYEMAC1RXCLKCORCNT : in std_logic_vector(2 downto 0); + PHYEMAC1RXCOMMADET : in std_ulogic; + PHYEMAC1RXD : in std_logic_vector(7 downto 0); + PHYEMAC1RXDISPERR : in std_ulogic; + PHYEMAC1RXDV : in std_ulogic; + PHYEMAC1RXER : in std_ulogic; + PHYEMAC1RXLOSSOFSYNC : in std_logic_vector(1 downto 0); + PHYEMAC1RXNOTINTABLE : in std_ulogic; + PHYEMAC1RXRUNDISP : in std_ulogic; + PHYEMAC1SIGNALDET : in std_ulogic; + PHYEMAC1TXBUFERR : in std_ulogic; + RESET : in std_ulogic; + TIEEMAC0CONFIGVEC : in std_logic_vector(79 downto 0); + TIEEMAC0UNICASTADDR : in std_logic_vector(47 downto 0); + TIEEMAC1CONFIGVEC : in std_logic_vector(79 downto 0); + TIEEMAC1UNICASTADDR : in std_logic_vector(47 downto 0) + ); +end component; +attribute BOX_TYPE of + EMAC : component is "PRIMITIVE"; + +----- component FD_1 ----- +component FD_1 + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + D : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FD_1 : component is "PRIMITIVE"; + +----- component FDC_1 ----- +component FDC_1 + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDC_1 : component is "PRIMITIVE"; + +----- component FDCE_1 ----- +component FDCE_1 + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDCE_1 : component is "PRIMITIVE"; + +----- component FDCE ----- +component FDCE + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDCE : component is "PRIMITIVE"; + +----- component FDCP_1 ----- +component FDCP_1 + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDCP_1 : component is "PRIMITIVE"; + +----- component FDCPE_1 ----- +component FDCPE_1 + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDCPE_1 : component is "PRIMITIVE"; + +----- component FDCPE ----- +component FDCPE + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDCPE : component is "PRIMITIVE"; + +----- component FDCP ----- +component FDCP + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDCP : component is "PRIMITIVE"; + +----- component FDCPX1 ----- +component FDCPX1 + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDCPX1 : component is "PRIMITIVE"; + +----- component FDC ----- +component FDC + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDC : component is "PRIMITIVE"; + +----- component FDDCE ----- +component FDDCE + port + ( + Q : out STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLR : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + FDDCE : component is "PRIMITIVE"; + +----- component FDDCPE ----- +component FDDCPE + port + ( + Q : out STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLR : in STD_ULOGIC; + D : in STD_ULOGIC; + PRE : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + FDDCPE : component is "PRIMITIVE"; + +----- component FDDCP ----- +component FDDCP + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out STD_ULOGIC; + C : in STD_ULOGIC; + CLR : in STD_ULOGIC; + D : in STD_ULOGIC; + PRE : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + FDDCP : component is "PRIMITIVE"; + +----- component FDDC ----- +component FDDC + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out STD_ULOGIC; + C : in STD_ULOGIC; + CLR : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + FDDC : component is "PRIMITIVE"; + +----- component FDDPE ----- +component FDDPE + port + ( + Q : out STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC; + D : in STD_ULOGIC; + PRE : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + FDDPE : component is "PRIMITIVE"; + +----- component FDDP ----- +component FDDP + generic + ( + INIT : bit := '1' + ); + port + ( + Q : out STD_ULOGIC; + C : in STD_ULOGIC; + D : in STD_ULOGIC; + PRE : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + FDDP : component is "PRIMITIVE"; + +----- component FDDRCPE ----- +component FDDRCPE + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + CLR : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDDRCPE : component is "PRIMITIVE"; + +----- component FDDRRSE ----- +component FDDRRSE + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDDRRSE : component is "PRIMITIVE"; + +----- component FDD ----- +component FDD + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out STD_ULOGIC; + C : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + FDD : component is "PRIMITIVE"; + +----- component FDE_1 ----- +component FDE_1 + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDE_1 : component is "PRIMITIVE"; + +----- component FDE ----- +component FDE + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDE : component is "PRIMITIVE"; + +----- component FDP_1 ----- +component FDP_1 + generic + ( + INIT : bit := '1' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDP_1 : component is "PRIMITIVE"; + +----- component FDPE_1 ----- +component FDPE_1 + generic + ( + INIT : bit := '1' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDPE_1 : component is "PRIMITIVE"; + +----- component FDPE ----- +component FDPE + generic + ( + INIT : bit := '1' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDPE : component is "PRIMITIVE"; + +----- component FDP ----- +component FDP + generic + ( + INIT : bit := '1' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDP : component is "PRIMITIVE"; + +----- component FDR_1 ----- +component FDR_1 + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out STD_ULOGIC; + C : in STD_ULOGIC; + D : in STD_ULOGIC; + R : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + FDR_1 : component is "PRIMITIVE"; + +----- component FDRE_1 ----- +component FDRE_1 + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDRE_1 : component is "PRIMITIVE"; + +----- component FDRE ----- +component FDRE + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDRE : component is "PRIMITIVE"; + +----- component FDRS_1 ----- +component FDRS_1 + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDRS_1 : component is "PRIMITIVE"; + +----- component FDRSE_1 ----- +component FDRSE_1 + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDRSE_1 : component is "PRIMITIVE"; + +----- component FDRSE ----- +component FDRSE + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDRSE : component is "PRIMITIVE"; + +----- component FDRS ----- +component FDRS + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDRS : component is "PRIMITIVE"; + +----- component FDR ----- +component FDR + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDR : component is "PRIMITIVE"; + +----- component FDS_1 ----- +component FDS_1 + generic + ( + INIT : bit := '1' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + D : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDS_1 : component is "PRIMITIVE"; + +----- component FDSE_1 ----- +component FDSE_1 + generic + ( + INIT : bit := '1' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDSE_1 : component is "PRIMITIVE"; + +----- component FDSE ----- +component FDSE + generic + ( + INIT : bit := '1' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDSE : component is "PRIMITIVE"; + +----- component FDS ----- +component FDS + generic + ( + INIT : bit := '1' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + D : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FDS : component is "PRIMITIVE"; + +----- component FD ----- +component FD + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + D : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FD : component is "PRIMITIVE"; + +----- component FIFO16 ----- +component FIFO16 + generic + ( + ALMOST_FULL_OFFSET : bit_vector := X"080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"080"; + DATA_WIDTH : integer := 36; + FIRST_WORD_FALL_THROUGH : boolean := false + ); + port + ( + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DO : out std_logic_vector (31 downto 0); + DOP : out std_logic_vector (3 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (11 downto 0); + RDERR : out std_ulogic; + WRCOUNT : out std_logic_vector (11 downto 0); + WRERR : out std_ulogic; + DI : in std_logic_vector (31 downto 0); + DIP : in std_logic_vector (3 downto 0); + RDCLK : in std_ulogic; + RDEN : in std_ulogic; + RST : in std_ulogic; + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FIFO16 : component is "PRIMITIVE"; + +----- component FIFO18_36 ----- +component FIFO18_36 + generic + ( + ALMOST_FULL_OFFSET : bit_vector := X"080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"080"; + DO_REG : integer := 1; + EN_SYN : boolean := FALSE; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + SIM_MODE : string := "SAFE" + ); + port + ( + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DO : out std_logic_vector (31 downto 0); + DOP : out std_logic_vector (3 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (8 downto 0); + RDERR : out std_ulogic; + WRCOUNT : out std_logic_vector (8 downto 0); + WRERR : out std_ulogic; + DI : in std_logic_vector (31 downto 0); + DIP : in std_logic_vector (3 downto 0); + RDCLK : in std_ulogic; + RDEN : in std_ulogic; + RST : in std_ulogic; + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FIFO18_36 : component is "PRIMITIVE"; + +----- component FIFO18 ----- +component FIFO18 + generic + ( + ALMOST_FULL_OFFSET : bit_vector := X"080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"080"; + DATA_WIDTH : integer := 4; + DO_REG : integer := 1; + EN_SYN : boolean := FALSE; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + SIM_MODE : string := "SAFE" + ); + port + ( + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DO : out std_logic_vector (15 downto 0); + DOP : out std_logic_vector (1 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (11 downto 0); + RDERR : out std_ulogic; + WRCOUNT : out std_logic_vector (11 downto 0); + WRERR : out std_ulogic; + DI : in std_logic_vector (15 downto 0); + DIP : in std_logic_vector (1 downto 0); + RDCLK : in std_ulogic; + RDEN : in std_ulogic; + RST : in std_ulogic; + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FIFO18 : component is "PRIMITIVE"; + +----- component FIFO36_72_EXP ----- +component FIFO36_72_EXP + generic + ( + ALMOST_FULL_OFFSET : bit_vector := X"080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"080"; + DO_REG : integer := 1; + EN_ECC_READ : boolean := FALSE; + EN_ECC_WRITE : boolean := FALSE; + EN_SYN : boolean := FALSE; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + SIM_MODE : string := "SAFE" + ); + port + ( + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DBITERR : out std_ulogic; + DO : out std_logic_vector (63 downto 0); + DOP : out std_logic_vector (7 downto 0); + ECCPARITY : out std_logic_vector (7 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (12 downto 0); + RDERR : out std_ulogic; + SBITERR : out std_ulogic; + WRCOUNT : out std_logic_vector (12 downto 0); + WRERR : out std_ulogic; + DI : in std_logic_vector (63 downto 0); + DIP : in std_logic_vector (7 downto 0); + RDCLKL : in std_ulogic; + RDCLKU : in std_ulogic; + RDEN : in std_ulogic; + RDRCLKL : in std_ulogic; + RDRCLKU : in std_ulogic; + RST : in std_ulogic; + WRCLKL : in std_ulogic; + WRCLKU : in std_ulogic; + WREN : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FIFO36_72_EXP : component is "PRIMITIVE"; + +----- component FIFO36_72 ----- +component FIFO36_72 + generic + ( + ALMOST_FULL_OFFSET : bit_vector := X"080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"080"; + DO_REG : integer := 1; + EN_ECC_READ : boolean := FALSE; + EN_ECC_WRITE : boolean := FALSE; + EN_SYN : boolean := FALSE; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + SIM_MODE : string := "SAFE" + ); + port + ( + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DBITERR : out std_ulogic; + DO : out std_logic_vector (63 downto 0); + DOP : out std_logic_vector (7 downto 0); + ECCPARITY : out std_logic_vector (7 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (8 downto 0); + RDERR : out std_ulogic; + SBITERR : out std_ulogic; + WRCOUNT : out std_logic_vector (8 downto 0); + WRERR : out std_ulogic; + DI : in std_logic_vector (63 downto 0); + DIP : in std_logic_vector (7 downto 0); + RDCLK : in std_ulogic; + RDEN : in std_ulogic; + RST : in std_ulogic; + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FIFO36_72 : component is "PRIMITIVE"; + +----- component FIFO36_EXP ----- +component FIFO36_EXP + generic + ( + ALMOST_EMPTY_OFFSET : bit_vector := X"0080"; + ALMOST_FULL_OFFSET : bit_vector := X"0080"; + DATA_WIDTH : integer := 4; + DO_REG : integer := 1; + EN_SYN : boolean := FALSE; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + SIM_MODE : string := "SAFE" + ); + port + ( + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DO : out std_logic_vector (31 downto 0); + DOP : out std_logic_vector (3 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (12 downto 0); + RDERR : out std_ulogic; + WRCOUNT : out std_logic_vector (12 downto 0); + WRERR : out std_ulogic; + DI : in std_logic_vector (31 downto 0); + DIP : in std_logic_vector (3 downto 0); + RDCLKL : in std_ulogic; + RDCLKU : in std_ulogic; + RDEN : in std_ulogic; + RDRCLKL : in std_ulogic; + RDRCLKU : in std_ulogic; + RST : in std_ulogic; + WRCLKL : in std_ulogic; + WRCLKU : in std_ulogic; + WREN : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FIFO36_EXP : component is "PRIMITIVE"; + +----- component FIFO36 ----- +component FIFO36 + generic + ( + ALMOST_FULL_OFFSET : bit_vector := X"0080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"0080"; + DATA_WIDTH : integer := 4; + DO_REG : integer := 1; + EN_SYN : boolean := FALSE; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + SIM_MODE : string := "SAFE" + ); + port + ( + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DO : out std_logic_vector (31 downto 0); + DOP : out std_logic_vector (3 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (12 downto 0); + RDERR : out std_ulogic; + WRCOUNT : out std_logic_vector (12 downto 0); + WRERR : out std_ulogic; + DI : in std_logic_vector (31 downto 0); + DIP : in std_logic_vector (3 downto 0); + RDCLK : in std_ulogic; + RDEN : in std_ulogic; + RST : in std_ulogic; + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FIFO36 : component is "PRIMITIVE"; + +----- component FMAP ----- +component FMAP + port + ( + O : in std_ulogic := 'X'; + I1 : in std_ulogic := 'X'; + I2 : in std_ulogic := 'X'; + I3 : in std_ulogic := 'X'; + I4 : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + FMAP : component is "PRIMITIVE"; + +----- component FRAME_ECC_VIRTEX4 ----- +component FRAME_ECC_VIRTEX4 + port + ( + ERROR : out std_ulogic; + SYNDROME : out std_logic_vector(11 downto 0); + SYNDROMEVALID : out std_ulogic + ); +end component; +attribute BOX_TYPE of + FRAME_ECC_VIRTEX4 : component is "PRIMITIVE"; + +----- component FRAME_ECC_VIRTEX5 ----- +component FRAME_ECC_VIRTEX5 + port + ( + CRCERROR : out std_ulogic; + ECCERROR : out std_ulogic; + SYNDROME : out std_logic_vector(11 downto 0); + SYNDROMEVALID : out std_ulogic + ); +end component; +attribute BOX_TYPE of + FRAME_ECC_VIRTEX5 : component is "PRIMITIVE"; + +----- component FTCP ----- +component FTCP + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CLR : in std_ulogic; + PRE : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FTCP : component is "PRIMITIVE"; + +----- component FTC ----- +component FTC + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CLR : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FTC : component is "PRIMITIVE"; + +----- component FTP ----- +component FTP + port + ( + Q : out std_ulogic; + C : in std_ulogic; + PRE : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + FTP : component is "PRIMITIVE"; + +----- component GND ----- +component GND + port + ( + G : out std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + GND : component is "PRIMITIVE"; + +----- component GT10_10GE_4 ----- +component GT10_10GE_4 + generic + ( + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := TRUE; + CHAN_BOND_64B66B_SV : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := TRUE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_CORRECT_USE : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_10GE_4 : component is "PRIMITIVE"; + +----- component GT10_10GE_8 ----- +component GT10_10GE_8 + generic + ( + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := TRUE; + CHAN_BOND_64B66B_SV : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := TRUE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_CORRECT_USE : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDISPERR : out std_logic_vector(7 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(7 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(7 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(7 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(7 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXDATA : in std_logic_vector(63 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_10GE_8 : component is "PRIMITIVE"; + +----- component GT10_10GFC_4 ----- +component GT10_10GFC_4 + generic + ( + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := TRUE; + CHAN_BOND_64B66B_SV : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := TRUE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_CORRECT_USE : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_10GFC_4 : component is "PRIMITIVE"; + +----- component GT10_10GFC_8 ----- +component GT10_10GFC_8 + generic + ( + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := TRUE; + CHAN_BOND_64B66B_SV : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := TRUE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_CORRECT_USE : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDISPERR : out std_logic_vector(7 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(7 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(7 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(7 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(7 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXDATA : in std_logic_vector(63 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_10GFC_8 : component is "PRIMITIVE"; + +----- component GT10_AURORA_1 ----- +component GT10_AURORA_1 + generic + ( + ALIGN_COMMA_WORD : integer := 1; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_CORRECT_USE : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00fc0db00b0f32263068090104a628"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_AURORA_1 : component is "PRIMITIVE"; + +----- component GT10_AURORA_2 ----- +component GT10_AURORA_2 + generic + ( + ALIGN_COMMA_WORD : integer := 1; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_CORRECT_USE : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00fc0db00b0f32663068090105a628"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_AURORA_2 : component is "PRIMITIVE"; + +----- component GT10_AURORA_4 ----- +component GT10_AURORA_4 + generic + ( + ALIGN_COMMA_WORD : integer := 1; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_CORRECT_USE : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd500b0132663068090105a628"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_AURORA_4 : component is "PRIMITIVE"; + +----- component GT10_AURORAX_4 ----- +component GT10_AURORAX_4 + generic + ( + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_64B66B_SV : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_CORRECT_USE : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_AURORAX_4 : component is "PRIMITIVE"; + +----- component GT10_AURORAX_8 ----- +component GT10_AURORAX_8 + generic + ( + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_64B66B_SV : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_CORRECT_USE : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDISPERR : out std_logic_vector(7 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(7 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(7 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(7 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(7 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXDATA : in std_logic_vector(63 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_AURORAX_8 : component is "PRIMITIVE"; + +----- component GT10_CUSTOM ----- +component GT10_CUSTOM + generic + ( + ALIGN_COMMA_WORD : integer := 1; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 1; + CHAN_BOND_64B66B_SV : boolean := FALSE; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 1; + CLK_CORRECT_USE : boolean := TRUE; + COMMA_10B_MASK : bit_vector := "0001111111"; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + MCOMMA_10B_VALUE : bit_vector := "1010000011"; + MCOMMA_DETECT : boolean := TRUE; + PCOMMA_10B_VALUE : bit_vector := "0101111100"; + PCOMMA_DETECT : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED : string := "0_32"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDISPERR : out std_logic_vector(7 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(7 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(7 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(7 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(7 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXDATA : in std_logic_vector(63 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_CUSTOM : component is "PRIMITIVE"; + +----- component GT10_INFINIBAND_1 ----- +component GT10_INFINIBAND_1 + generic + ( + ALIGN_COMMA_WORD : integer := 2; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_LEN : integer := 2; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 2; + CLK_CORRECT_USE : boolean := TRUE; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + LANE_ID : bit_vector := "00000000000"; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd500b0132263068090104a620"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_INFINIBAND_1 : component is "PRIMITIVE"; + +----- component GT10_INFINIBAND_2 ----- +component GT10_INFINIBAND_2 + generic + ( + ALIGN_COMMA_WORD : integer := 2; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_LEN : integer := 2; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 2; + CLK_CORRECT_USE : boolean := TRUE; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + LANE_ID : bit_vector := "00000000000"; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00fc0d300b0f32663068090105a620"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_INFINIBAND_2 : component is "PRIMITIVE"; + +----- component GT10_INFINIBAND_4 ----- +component GT10_INFINIBAND_4 + generic + ( + ALIGN_COMMA_WORD : integer := 2; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_LEN : integer := 2; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 2; + CLK_CORRECT_USE : boolean := TRUE; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + LANE_ID : bit_vector := "00000000000"; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd500b0132663068090105a620"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_INFINIBAND_4 : component is "PRIMITIVE"; + +----- component GT10_OC192_4 ----- +component GT10_OC192_4 + generic + ( + ALIGN_COMMA_WORD : integer := 1; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + MCOMMA_10B_VALUE : bit_vector := "0010101010"; + MCOMMA_DETECT : boolean := TRUE; + PCOMMA_10B_VALUE : bit_vector := "0010101010"; + PCOMMA_DETECT : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504c00208c9050d0068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLKBSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_OC192_4 : component is "PRIMITIVE"; + +----- component GT10_OC192_8 ----- +component GT10_OC192_8 + generic + ( + ALIGN_COMMA_WORD : integer := 1; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + MCOMMA_10B_VALUE : bit_vector := "0010101010"; + MCOMMA_DETECT : boolean := TRUE; + PCOMMA_10B_VALUE : bit_vector := "0010101010"; + PCOMMA_DETECT : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504c00208c9050d0068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDISPERR : out std_logic_vector(7 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(7 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(7 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(7 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLKBSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(7 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXDATA : in std_logic_vector(63 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_OC192_8 : component is "PRIMITIVE"; + +----- component GT10_OC48_1 ----- +component GT10_OC48_1 + generic + ( + ALIGN_COMMA_WORD : integer := 1; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + MCOMMA_10B_VALUE : bit_vector := "0010101010"; + MCOMMA_DETECT : boolean := TRUE; + PCOMMA_10B_VALUE : bit_vector := "0010101010"; + PCOMMA_DETECT : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd500b01300830680901040820"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_OC48_1 : component is "PRIMITIVE"; + +----- component GT10_OC48_2 ----- +component GT10_OC48_2 + generic + ( + ALIGN_COMMA_WORD : integer := 1; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + MCOMMA_10B_VALUE : bit_vector := "0010101010"; + MCOMMA_DETECT : boolean := TRUE; + PCOMMA_10B_VALUE : bit_vector := "0010101010"; + PCOMMA_DETECT : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00fc0d300b0f304830680901050820"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_OC48_2 : component is "PRIMITIVE"; + +----- component GT10_OC48_4 ----- +component GT10_OC48_4 + generic + ( + ALIGN_COMMA_WORD : integer := 1; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + MCOMMA_10B_VALUE : bit_vector := "0010101010"; + MCOMMA_DETECT : boolean := TRUE; + PCOMMA_10B_VALUE : bit_vector := "0010101010"; + PCOMMA_DETECT : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd500b01304830680901050820"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_OC48_4 : component is "PRIMITIVE"; + +----- component GT10_PCI_EXPRESS_1 ----- +component GT10_PCI_EXPRESS_1 + generic + ( + ALIGN_COMMA_WORD : integer := 2; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 2; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 2; + CLK_CORRECT_USE : boolean := TRUE; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd500b0132263068090104a620"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_PCI_EXPRESS_1 : component is "PRIMITIVE"; + +----- component GT10_PCI_EXPRESS_2 ----- +component GT10_PCI_EXPRESS_2 + generic + ( + ALIGN_COMMA_WORD : integer := 2; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 2; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 2; + CLK_CORRECT_USE : boolean := TRUE; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00fc0d300b0f32663068090105a620"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_PCI_EXPRESS_2 : component is "PRIMITIVE"; + +----- component GT10_PCI_EXPRESS_4 ----- +component GT10_PCI_EXPRESS_4 + generic + ( + ALIGN_COMMA_WORD : integer := 2; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 2; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 2; + CLK_CORRECT_USE : boolean := TRUE; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd500b0132663068090105a620"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_PCI_EXPRESS_4 : component is "PRIMITIVE"; + +----- component GT10 ----- +component GT10 + generic + ( + ALIGN_COMMA_WORD : integer := 1; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 1; + CHAN_BOND_64B66B_SV : boolean := FALSE; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 1; + CLK_CORRECT_USE : boolean := TRUE; + COMMA_10B_MASK : bit_vector := "0001111111"; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + MCOMMA_10B_VALUE : bit_vector := "1010000011"; + MCOMMA_DETECT : boolean := TRUE; + PCOMMA_10B_VALUE : bit_vector := "0101111100"; + PCOMMA_DETECT : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED : string := "0_32"; + PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDISPERR : out std_logic_vector(7 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(7 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(7 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(7 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(7 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXDATA : in std_logic_vector(63 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10 : component is "PRIMITIVE"; + +----- component GT10_XAUI_1 ----- +component GT10_XAUI_1 + generic + ( + ALIGN_COMMA_WORD : integer := 2; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 2; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 2; + CLK_CORRECT_USE : boolean := TRUE; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00fc0db00b0f32263068090104a628"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_XAUI_1 : component is "PRIMITIVE"; + +----- component GT10_XAUI_2 ----- +component GT10_XAUI_2 + generic + ( + ALIGN_COMMA_WORD : integer := 2; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 2; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 2; + CLK_CORRECT_USE : boolean := TRUE; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00fc0db00b0f32663068090105a628"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_XAUI_2 : component is "PRIMITIVE"; + +----- component GT10_XAUI_4 ----- +component GT10_XAUI_4 + generic + ( + ALIGN_COMMA_WORD : integer := 2; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 2; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 36; + CLK_COR_MIN_LAT : integer := 28; + CLK_COR_SEQ_1_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_MASK : bit_vector := "0000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 2; + CLK_CORRECT_USE : boolean := TRUE; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + PMA_PWR_CNTRL : bit_vector := "11111111"; + PMA_SPEED_HEX : bit_vector := X"00ffcd500b0132663068090105a628"; + PMA_SPEED_USE : string := "PMA_SPEED"; + RX_BUFFER_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + TX_BUFFER_USE : boolean := TRUE + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(4 downto 0); + PMARXLOCK : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXOUTCLK : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + BREFCLKNIN : in std_ulogic; + BREFCLKPIN : in std_ulogic; + CHBONDI : in std_logic_vector(4 downto 0); + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + PMAINIT : in std_ulogic; + PMAREGADDR : in std_logic_vector(5 downto 0); + PMAREGDATAIN : in std_logic_vector(7 downto 0); + PMAREGRW : in std_ulogic; + PMAREGSTROBE : in std_ulogic; + PMARXLOCKSEL : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKBSEL : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT10_XAUI_4 : component is "PRIMITIVE"; + +----- component GT11CLK_MGT ----- +component GT11CLK_MGT + generic + ( + SYNCLK1OUTEN : string := "ENABLE"; + SYNCLK2OUTEN : string := "DISABLE" + ); + port + ( + SYNCLK1OUT : out std_ulogic; + SYNCLK2OUT : out std_ulogic; + MGTCLKN : in std_ulogic; + MGTCLKP : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT11CLK_MGT : component is "PRIMITIVE"; + +----- component GT11CLK ----- +component GT11CLK + generic + ( + REFCLKSEL : string := "MGTCLK"; + SYNCLK1OUTEN : string := "ENABLE"; + SYNCLK2OUTEN : string := "DISABLE" + ); + port + ( + SYNCLK1OUT : out std_ulogic; + SYNCLK2OUT : out std_ulogic; + MGTCLKN : in std_ulogic; + MGTCLKP : in std_ulogic; + REFCLK : in std_ulogic; + RXBCLK : in std_ulogic; + SYNCLK1IN : in std_ulogic; + SYNCLK2IN : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT11CLK : component is "PRIMITIVE"; + +----- component GT11_CUSTOM ----- +component GT11_CUSTOM + generic + ( + ALIGN_COMMA_WORD : integer := 4; + BANDGAPSEL : boolean := FALSE; + BIASRESSEL : boolean := FALSE; + CCCB_ARBITRATOR_DISABLE : boolean := FALSE; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "NONE"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_MASK : bit_vector := "1110"; + CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "1110"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 1; + CLK_CORRECT_USE : boolean := FALSE; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 48; + CLK_COR_MIN_LAT : integer := 36; + CLK_COR_SEQ_1_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_MASK : bit_vector := "1110"; + CLK_COR_SEQ_2_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_MASK : bit_vector := "1110"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 1; + COMMA32 : boolean := FALSE; + COMMA_10B_MASK : bit_vector := X"3FF"; + CYCLE_LIMIT_SEL : bit_vector := "00"; + DCDR_FILTER : bit_vector := "010"; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + DIGRX_FWDCLK : bit_vector := "00"; + DIGRX_SYNC_MODE : boolean := FALSE; + ENABLE_DCDR : boolean := FALSE; + FDET_HYS_CAL : bit_vector := "010"; + FDET_HYS_SEL : bit_vector := "100"; + FDET_LCK_CAL : bit_vector := "100"; + FDET_LCK_SEL : bit_vector := "001"; + IREFBIASMODE : bit_vector := "11"; + LOOPCAL_WAIT : bit_vector := "00"; + MCOMMA_32B_VALUE : bit_vector := X"00000000"; + MCOMMA_DETECT : boolean := TRUE; + OPPOSITE_SELECT : boolean := FALSE; + PCOMMA_32B_VALUE : bit_vector := X"00000000"; + PCOMMA_DETECT : boolean := TRUE; + PCS_BIT_SLIP : boolean := FALSE; + PMACLKENABLE : boolean := TRUE; + PMACOREPWRENABLE : boolean := TRUE; + PMAIREFTRIM : bit_vector := "0111"; + PMAVBGCTRL : bit_vector := "00000"; + PMAVREFTRIM : bit_vector := "0111"; + PMA_BIT_SLIP : boolean := FALSE; + POWER_ENABLE : boolean := TRUE; + REPEATER : boolean := FALSE; + RXACTST : boolean := FALSE; + RXAFEEQ : bit_vector := "000000000"; + RXAFEPD : boolean := FALSE; + RXAFETST : boolean := FALSE; + RXAPD : boolean := FALSE; + RXAREGCTRL : bit_vector := "00000"; + RXASYNCDIVIDE : bit_vector := "11"; + RXBY_32 : boolean := FALSE; + RXCDRLOS : bit_vector := "000000"; + RXCLK0_FORCE_PMACLK : boolean := FALSE; + RXCLKMODE : bit_vector := "110001"; + RXCLMODE : bit_vector := "00"; + RXCMADJ : bit_vector := "01"; + RXCPSEL : boolean := TRUE; + RXCPTST : boolean := FALSE; + RXCRCCLOCKDOUBLE : boolean := FALSE; + RXCRCENABLE : boolean := FALSE; + RXCRCINITVAL : bit_vector := X"00000000"; + RXCRCINVERTGEN : boolean := FALSE; + RXCRCSAMECLOCK : boolean := FALSE; + RXCTRL1 : bit_vector := X"200"; + RXCYCLE_LIMIT_SEL : bit_vector := "00"; + RXDATA_SEL : bit_vector := "00"; + RXDCCOUPLE : boolean := FALSE; + RXDIGRESET : boolean := FALSE; + RXDIGRX : boolean := FALSE; + RXEQ : bit_vector := X"4000000000000000"; + RXFDCAL_CLOCK_DIVIDE : string := "NONE"; + RXFDET_HYS_CAL : bit_vector := "010"; + RXFDET_HYS_SEL : bit_vector := "100"; + RXFDET_LCK_CAL : bit_vector := "100"; + RXFDET_LCK_SEL : bit_vector := "001"; + RXFECONTROL1 : bit_vector := "00"; + RXFECONTROL2 : bit_vector := "000"; + RXFETUNE : bit_vector := "01"; + RXLB : boolean := FALSE; + RXLKADJ : bit_vector := "00000"; + RXLKAPD : boolean := FALSE; + RXLOOPCAL_WAIT : bit_vector := "00"; + RXLOOPFILT : bit_vector := "0111"; + RXMODE : bit_vector := "000000"; + RXOUTDIV2SEL : integer := 1; + RXPD : boolean := FALSE; + RXPDDTST : boolean := TRUE; + RXPLLNDIVSEL : integer := 8; + RXPMACLKSEL : string := "REFCLK1"; + RXRCPADJ : bit_vector := "011"; + RXRCPPD : boolean := FALSE; + RXRECCLK1_USE_SYNC : boolean := FALSE; + RXRIBADJ : bit_vector := "11"; + RXRPDPD : boolean := FALSE; + RXRSDPD : boolean := FALSE; + RXSLOWDOWN_CAL : bit_vector := "00"; + RXTUNE : bit_vector := X"0000"; + RXUSRDIVISOR : integer := 1; + RXVCODAC_INIT : bit_vector := "1010000000"; + RXVCO_CTRL_ENABLE : boolean := FALSE; + RX_BUFFER_USE : boolean := TRUE; + RX_CLOCK_DIVIDER : bit_vector := "00"; + SAMPLE_8X : boolean := FALSE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + SLOWDOWN_CAL : bit_vector := "00"; + TXABPMACLKSEL : string := "REFCLK1"; + TXAPD : boolean := FALSE; + TXAREFBIASSEL : boolean := TRUE; + TXASYNCDIVIDE : bit_vector := "11"; + TXCLK0_FORCE_PMACLK : boolean := FALSE; + TXCLKMODE : bit_vector := "1001"; + TXCLMODE : bit_vector := "00"; + TXCPSEL : boolean := TRUE; + TXCRCCLOCKDOUBLE : boolean := FALSE; + TXCRCENABLE : boolean := FALSE; + TXCRCINITVAL : bit_vector := X"00000000"; + TXCRCINVERTGEN : boolean := FALSE; + TXCRCSAMECLOCK : boolean := FALSE; + TXCTRL1 : bit_vector := X"200"; + TXDATA_SEL : bit_vector := "00"; + TXDAT_PRDRV_DAC : bit_vector := "111"; + TXDAT_TAP_DAC : bit_vector := "10110"; + TXDIGPD : boolean := FALSE; + TXFDCAL_CLOCK_DIVIDE : string := "NONE"; + TXHIGHSIGNALEN : boolean := TRUE; + TXLOOPFILT : bit_vector := "0111"; + TXLVLSHFTPD : boolean := FALSE; + TXOUTCLK1_USE_SYNC : boolean := FALSE; + TXOUTDIV2SEL : integer := 1; + TXPD : boolean := FALSE; + TXPHASESEL : boolean := FALSE; + TXPLLNDIVSEL : integer := 8; + TXPOST_PRDRV_DAC : bit_vector := "111"; + TXPOST_TAP_DAC : bit_vector := "01110"; + TXPOST_TAP_PD : boolean := TRUE; + TXPRE_PRDRV_DAC : bit_vector := "111"; + TXPRE_TAP_DAC : bit_vector := "00000"; + TXPRE_TAP_PD : boolean := TRUE; + TXSLEWRATE : boolean := FALSE; + TXTERMTRIM : bit_vector := "1100"; + TXTUNE : bit_vector := X"0000"; + TX_BUFFER_USE : boolean := TRUE; + TX_CLOCK_DIVIDER : bit_vector := "00"; + VCODAC_INIT : bit_vector := "1010000000"; + VCO_CTRL_ENABLE : boolean := FALSE; + VREFBIASMODE : bit_vector := "11" + ); + port + ( + CHBONDO : out std_logic_vector(4 downto 0); + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + RXBUFERR : out std_ulogic; + RXCALFAIL : out std_ulogic; + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCOUT : out std_logic_vector(31 downto 0); + RXCYCLELIMIT : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDISPERR : out std_logic_vector(7 downto 0); + RXLOCK : out std_ulogic; + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXMCLK : out std_ulogic; + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXPCSHCLKOUT : out std_ulogic; + RXREALIGN : out std_ulogic; + RXRECCLK1 : out std_ulogic; + RXRECCLK2 : out std_ulogic; + RXRUNDISP : out std_logic_vector(7 downto 0); + RXSIGDET : out std_ulogic; + RXSTATUS : out std_logic_vector(5 downto 0); + TX1N : out std_ulogic; + TX1P : out std_ulogic; + TXBUFERR : out std_ulogic; + TXCALFAIL : out std_ulogic; + TXCRCOUT : out std_logic_vector(31 downto 0); + TXCYCLELIMIT : out std_ulogic; + TXKERR : out std_logic_vector(7 downto 0); + TXLOCK : out std_ulogic; + TXOUTCLK1 : out std_ulogic; + TXOUTCLK2 : out std_ulogic; + TXPCSHCLKOUT : out std_ulogic; + TXRUNDISP : out std_logic_vector(7 downto 0); + CHBONDI : in std_logic_vector(4 downto 0); + DADDR : in std_logic_vector(7 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + GREFCLK : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK1 : in std_ulogic; + REFCLK2 : in std_ulogic; + RX1N : in std_ulogic; + RX1P : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCLKSTABLE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXCRCCLK : in std_ulogic; + RXCRCDATAVALID : in std_ulogic; + RXCRCDATAWIDTH : in std_logic_vector(2 downto 0); + RXCRCIN : in std_logic_vector(63 downto 0); + RXCRCINIT : in std_ulogic; + RXCRCINTCLK : in std_ulogic; + RXCRCPD : in std_ulogic; + RXCRCRESET : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXPMARESET : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXSYNC : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(7 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXCLKSTABLE : in std_ulogic; + TXCRCCLK : in std_ulogic; + TXCRCDATAVALID : in std_ulogic; + TXCRCDATAWIDTH : in std_logic_vector(2 downto 0); + TXCRCIN : in std_logic_vector(63 downto 0); + TXCRCINIT : in std_ulogic; + TXCRCINTCLK : in std_ulogic; + TXCRCPD : in std_ulogic; + TXCRCRESET : in std_ulogic; + TXDATA : in std_logic_vector(63 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXENOOB : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPMARESET : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXSYNC : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT11_CUSTOM : component is "PRIMITIVE"; + +----- component GT11_DUAL ----- +component GT11_DUAL + generic + ( + ALIGN_COMMA_WORD_A : integer := 4; + ALIGN_COMMA_WORD_B : integer := 4; + BANDGAPSEL_A : boolean := FALSE; + BANDGAPSEL_B : boolean := FALSE; + BIASRESSEL_A : boolean := FALSE; + BIASRESSEL_B : boolean := FALSE; + CCCB_ARBITRATOR_DISABLE_A : boolean := FALSE; + CCCB_ARBITRATOR_DISABLE_B : boolean := FALSE; + CHAN_BOND_LIMIT_A : integer := 16; + CHAN_BOND_LIMIT_B : integer := 16; + CHAN_BOND_MODE_A : string := "NONE"; + CHAN_BOND_MODE_B : string := "NONE"; + CHAN_BOND_ONE_SHOT_A : boolean := FALSE; + CHAN_BOND_ONE_SHOT_B : boolean := FALSE; + CHAN_BOND_SEQ_1_1_A : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_1_B : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_2_A : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_2_B : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_3_A : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_3_B : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_4_A : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_4_B : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_MASK_A : bit_vector := "1110"; + CHAN_BOND_SEQ_1_MASK_B : bit_vector := "1110"; + CHAN_BOND_SEQ_2_1_A : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_1_B : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_2_A : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_2_B : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_3_A : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_3_B : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_4_A : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_4_B : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_MASK_A : bit_vector := "1110"; + CHAN_BOND_SEQ_2_MASK_B : bit_vector := "1110"; + CHAN_BOND_SEQ_2_USE_A : boolean := FALSE; + CHAN_BOND_SEQ_2_USE_B : boolean := FALSE; + CHAN_BOND_SEQ_LEN_A : integer := 1; + CHAN_BOND_SEQ_LEN_B : integer := 1; + CLK_CORRECT_USE_A : boolean := FALSE; + CLK_CORRECT_USE_B : boolean := FALSE; + CLK_COR_8B10B_DE_A : boolean := FALSE; + CLK_COR_8B10B_DE_B : boolean := FALSE; + CLK_COR_MAX_LAT_A : integer := 48; + CLK_COR_MAX_LAT_B : integer := 48; + CLK_COR_MIN_LAT_A : integer := 36; + CLK_COR_MIN_LAT_B : integer := 36; + CLK_COR_SEQ_1_1_A : bit_vector := "00000000000"; + CLK_COR_SEQ_1_1_B : bit_vector := "00000000000"; + CLK_COR_SEQ_1_2_A : bit_vector := "00000000000"; + CLK_COR_SEQ_1_2_B : bit_vector := "00000000000"; + CLK_COR_SEQ_1_3_A : bit_vector := "00000000000"; + CLK_COR_SEQ_1_3_B : bit_vector := "00000000000"; + CLK_COR_SEQ_1_4_A : bit_vector := "00000000000"; + CLK_COR_SEQ_1_4_B : bit_vector := "00000000000"; + CLK_COR_SEQ_1_MASK_A : bit_vector := "1110"; + CLK_COR_SEQ_1_MASK_B : bit_vector := "1110"; + CLK_COR_SEQ_2_1_A : bit_vector := "00000000000"; + CLK_COR_SEQ_2_1_B : bit_vector := "00000000000"; + CLK_COR_SEQ_2_2_A : bit_vector := "00000000000"; + CLK_COR_SEQ_2_2_B : bit_vector := "00000000000"; + CLK_COR_SEQ_2_3_A : bit_vector := "00000000000"; + CLK_COR_SEQ_2_3_B : bit_vector := "00000000000"; + CLK_COR_SEQ_2_4_A : bit_vector := "00000000000"; + CLK_COR_SEQ_2_4_B : bit_vector := "00000000000"; + CLK_COR_SEQ_2_MASK_A : bit_vector := "1110"; + CLK_COR_SEQ_2_MASK_B : bit_vector := "1110"; + CLK_COR_SEQ_2_USE_A : boolean := FALSE; + CLK_COR_SEQ_2_USE_B : boolean := FALSE; + CLK_COR_SEQ_DROP_A : boolean := FALSE; + CLK_COR_SEQ_DROP_B : boolean := FALSE; + CLK_COR_SEQ_LEN_A : integer := 1; + CLK_COR_SEQ_LEN_B : integer := 1; + COMMA32_A : boolean := FALSE; + COMMA32_B : boolean := FALSE; + COMMA_10B_MASK_A : bit_vector := X"3FF"; + COMMA_10B_MASK_B : bit_vector := X"3FF"; + CYCLE_LIMIT_SEL_A : bit_vector := "00"; + CYCLE_LIMIT_SEL_B : bit_vector := "00"; + DCDR_FILTER_A : bit_vector := "010"; + DCDR_FILTER_B : bit_vector := "010"; + DEC_MCOMMA_DETECT_A : boolean := TRUE; + DEC_MCOMMA_DETECT_B : boolean := TRUE; + DEC_PCOMMA_DETECT_A : boolean := TRUE; + DEC_PCOMMA_DETECT_B : boolean := TRUE; + DEC_VALID_COMMA_ONLY_A : boolean := TRUE; + DEC_VALID_COMMA_ONLY_B : boolean := TRUE; + DIGRX_FWDCLK_A : bit_vector := "00"; + DIGRX_FWDCLK_B : bit_vector := "00"; + DIGRX_SYNC_MODE_A : boolean := FALSE; + DIGRX_SYNC_MODE_B : boolean := FALSE; + ENABLE_DCDR_A : boolean := FALSE; + ENABLE_DCDR_B : boolean := FALSE; + FDET_HYS_CAL_A : bit_vector := "010"; + FDET_HYS_CAL_B : bit_vector := "010"; + FDET_HYS_SEL_A : bit_vector := "100"; + FDET_HYS_SEL_B : bit_vector := "100"; + FDET_LCK_CAL_A : bit_vector := "100"; + FDET_LCK_CAL_B : bit_vector := "100"; + FDET_LCK_SEL_A : bit_vector := "001"; + FDET_LCK_SEL_B : bit_vector := "001"; + IREFBIASMODE_A : bit_vector := "11"; + IREFBIASMODE_B : bit_vector := "11"; + LOOPCAL_WAIT_A : bit_vector := "00"; + LOOPCAL_WAIT_B : bit_vector := "00"; + MCOMMA_32B_VALUE_A : bit_vector := X"00000000"; + MCOMMA_32B_VALUE_B : bit_vector := X"00000000"; + MCOMMA_DETECT_A : boolean := TRUE; + MCOMMA_DETECT_B : boolean := TRUE; + OPPOSITE_SELECT_A : boolean := FALSE; + OPPOSITE_SELECT_B : boolean := FALSE; + PCOMMA_32B_VALUE_A : bit_vector := X"00000000"; + PCOMMA_32B_VALUE_B : bit_vector := X"00000000"; + PCOMMA_DETECT_A : boolean := TRUE; + PCOMMA_DETECT_B : boolean := TRUE; + PCS_BIT_SLIP_A : boolean := FALSE; + PCS_BIT_SLIP_B : boolean := FALSE; + PMACLKENABLE_A : boolean := TRUE; + PMACLKENABLE_B : boolean := TRUE; + PMACOREPWRENABLE_A : boolean := TRUE; + PMACOREPWRENABLE_B : boolean := TRUE; + PMAIREFTRIM_A : bit_vector := "0111"; + PMAIREFTRIM_B : bit_vector := "0111"; + PMAVBGCTRL_A : bit_vector := "00000"; + PMAVBGCTRL_B : bit_vector := "00000"; + PMAVREFTRIM_A : bit_vector := "0111"; + PMAVREFTRIM_B : bit_vector := "0111"; + PMA_BIT_SLIP_A : boolean := FALSE; + PMA_BIT_SLIP_B : boolean := FALSE; + POWER_ENABLE_A : boolean := TRUE; + POWER_ENABLE_B : boolean := TRUE; + REPEATER_A : boolean := FALSE; + REPEATER_B : boolean := FALSE; + RXACTST_A : boolean := FALSE; + RXACTST_B : boolean := FALSE; + RXAFEEQ_A : bit_vector := "000000000"; + RXAFEEQ_B : bit_vector := "000000000"; + RXAFEPD_A : boolean := FALSE; + RXAFEPD_B : boolean := FALSE; + RXAFETST_A : boolean := FALSE; + RXAFETST_B : boolean := FALSE; + RXAPD_A : boolean := FALSE; + RXAPD_B : boolean := FALSE; + RXAREGCTRL_A : bit_vector := "00000"; + RXAREGCTRL_B : bit_vector := "00000"; + RXASYNCDIVIDE_A : bit_vector := "11"; + RXASYNCDIVIDE_B : bit_vector := "11"; + RXBY_32_A : boolean := FALSE; + RXBY_32_B : boolean := FALSE; + RXCDRLOS_A : bit_vector := "000000"; + RXCDRLOS_B : bit_vector := "000000"; + RXCLK0_FORCE_PMACLK_A : boolean := FALSE; + RXCLK0_FORCE_PMACLK_B : boolean := FALSE; + RXCLKMODE_A : bit_vector := "110001"; + RXCLKMODE_B : bit_vector := "110001"; + RXCLMODE_A : bit_vector := "00"; + RXCLMODE_B : bit_vector := "00"; + RXCMADJ_A : bit_vector := "01"; + RXCMADJ_B : bit_vector := "01"; + RXCPSEL_A : boolean := TRUE; + RXCPSEL_B : boolean := TRUE; + RXCPTST_A : boolean := FALSE; + RXCPTST_B : boolean := FALSE; + RXCRCCLOCKDOUBLE_A : boolean := FALSE; + RXCRCCLOCKDOUBLE_B : boolean := FALSE; + RXCRCENABLE_A : boolean := FALSE; + RXCRCENABLE_B : boolean := FALSE; + RXCRCINITVAL_A : bit_vector := X"00000000"; + RXCRCINITVAL_B : bit_vector := X"00000000"; + RXCRCINVERTGEN_A : boolean := FALSE; + RXCRCINVERTGEN_B : boolean := FALSE; + RXCRCSAMECLOCK_A : boolean := FALSE; + RXCRCSAMECLOCK_B : boolean := FALSE; + RXCTRL1_A : bit_vector := X"200"; + RXCTRL1_B : bit_vector := X"200"; + RXCYCLE_LIMIT_SEL_A : bit_vector := "00"; + RXCYCLE_LIMIT_SEL_B : bit_vector := "00"; + RXDATA_SEL_A : bit_vector := "00"; + RXDATA_SEL_B : bit_vector := "00"; + RXDCCOUPLE_A : boolean := FALSE; + RXDCCOUPLE_B : boolean := FALSE; + RXDIGRESET_A : boolean := FALSE; + RXDIGRESET_B : boolean := FALSE; + RXDIGRX_A : boolean := FALSE; + RXDIGRX_B : boolean := FALSE; + RXEQ_A : bit_vector := X"4000000000000000"; + RXEQ_B : bit_vector := X"4000000000000000"; + RXFDCAL_CLOCK_DIVIDE_A : string := "NONE"; + RXFDCAL_CLOCK_DIVIDE_B : string := "NONE"; + RXFDET_HYS_CAL_A : bit_vector := "010"; + RXFDET_HYS_CAL_B : bit_vector := "010"; + RXFDET_HYS_SEL_A : bit_vector := "100"; + RXFDET_HYS_SEL_B : bit_vector := "100"; + RXFDET_LCK_CAL_A : bit_vector := "100"; + RXFDET_LCK_CAL_B : bit_vector := "100"; + RXFDET_LCK_SEL_A : bit_vector := "001"; + RXFDET_LCK_SEL_B : bit_vector := "001"; + RXFECONTROL1_A : bit_vector := "00"; + RXFECONTROL1_B : bit_vector := "00"; + RXFECONTROL2_A : bit_vector := "000"; + RXFECONTROL2_B : bit_vector := "000"; + RXFETUNE_A : bit_vector := "01"; + RXFETUNE_B : bit_vector := "01"; + RXLB_A : boolean := FALSE; + RXLB_B : boolean := FALSE; + RXLKADJ_A : bit_vector := "00000"; + RXLKADJ_B : bit_vector := "00000"; + RXLKAPD_A : boolean := FALSE; + RXLKAPD_B : boolean := FALSE; + RXLOOPCAL_WAIT_A : bit_vector := "00"; + RXLOOPCAL_WAIT_B : bit_vector := "00"; + RXLOOPFILT_A : bit_vector := "0111"; + RXLOOPFILT_B : bit_vector := "0111"; + RXMODE_A : bit_vector := "000000"; + RXMODE_B : bit_vector := "000000"; + RXOUTDIV2SEL_A : integer := 1; + RXOUTDIV2SEL_B : integer := 1; + RXPDDTST_A : boolean := TRUE; + RXPDDTST_B : boolean := TRUE; + RXPD_A : boolean := FALSE; + RXPD_B : boolean := FALSE; + RXPLLNDIVSEL_A : integer := 8; + RXPLLNDIVSEL_B : integer := 8; + RXPMACLKSEL_A : string := "REFCLK1"; + RXPMACLKSEL_B : string := "REFCLK1"; + RXRCPADJ_A : bit_vector := "011"; + RXRCPADJ_B : bit_vector := "011"; + RXRCPPD_A : boolean := FALSE; + RXRCPPD_B : boolean := FALSE; + RXRECCLK1_USE_SYNC_A : boolean := FALSE; + RXRECCLK1_USE_SYNC_B : boolean := FALSE; + RXRIBADJ_A : bit_vector := "11"; + RXRIBADJ_B : bit_vector := "11"; + RXRPDPD_A : boolean := FALSE; + RXRPDPD_B : boolean := FALSE; + RXRSDPD_A : boolean := FALSE; + RXRSDPD_B : boolean := FALSE; + RXSLOWDOWN_CAL_A : bit_vector := "00"; + RXSLOWDOWN_CAL_B : bit_vector := "00"; + RXTUNE_A : bit_vector := X"0000"; + RXTUNE_B : bit_vector := X"0000"; + RXUSRDIVISOR_A : integer := 1; + RXUSRDIVISOR_B : integer := 1; + RXVCODAC_INIT_A : bit_vector := "1010000000"; + RXVCODAC_INIT_B : bit_vector := "1010000000"; + RXVCO_CTRL_ENABLE_A : boolean := FALSE; + RXVCO_CTRL_ENABLE_B : boolean := FALSE; + RX_BUFFER_USE_A : boolean := TRUE; + RX_BUFFER_USE_B : boolean := TRUE; + RX_CLOCK_DIVIDER_A : bit_vector := "00"; + RX_CLOCK_DIVIDER_B : bit_vector := "00"; + SAMPLE_8X_A : boolean := FALSE; + SAMPLE_8X_B : boolean := FALSE; + SH_CNT_MAX_A : integer := 64; + SH_CNT_MAX_B : integer := 64; + SH_INVALID_CNT_MAX_A : integer := 16; + SH_INVALID_CNT_MAX_B : integer := 16; + SLOWDOWN_CAL_A : bit_vector := "00"; + SLOWDOWN_CAL_B : bit_vector := "00"; + TXABPMACLKSEL_A : string := "REFCLK1"; + TXABPMACLKSEL_B : string := "REFCLK1"; + TXAPD_A : boolean := FALSE; + TXAPD_B : boolean := FALSE; + TXAREFBIASSEL_A : boolean := TRUE; + TXAREFBIASSEL_B : boolean := TRUE; + TXASYNCDIVIDE_A : bit_vector := "11"; + TXASYNCDIVIDE_B : bit_vector := "11"; + TXCLK0_FORCE_PMACLK_A : boolean := FALSE; + TXCLK0_FORCE_PMACLK_B : boolean := FALSE; + TXCLKMODE_A : bit_vector := "1001"; + TXCLKMODE_B : bit_vector := "1001"; + TXCLMODE_A : bit_vector := "00"; + TXCLMODE_B : bit_vector := "00"; + TXCPSEL_A : boolean := TRUE; + TXCPSEL_B : boolean := TRUE; + TXCRCCLOCKDOUBLE_A : boolean := FALSE; + TXCRCCLOCKDOUBLE_B : boolean := FALSE; + TXCRCENABLE_A : boolean := FALSE; + TXCRCENABLE_B : boolean := FALSE; + TXCRCINITVAL_A : bit_vector := X"00000000"; + TXCRCINITVAL_B : bit_vector := X"00000000"; + TXCRCINVERTGEN_A : boolean := FALSE; + TXCRCINVERTGEN_B : boolean := FALSE; + TXCRCSAMECLOCK_A : boolean := FALSE; + TXCRCSAMECLOCK_B : boolean := FALSE; + TXCTRL1_A : bit_vector := X"200"; + TXCTRL1_B : bit_vector := X"200"; + TXDATA_SEL_A : bit_vector := "00"; + TXDATA_SEL_B : bit_vector := "00"; + TXDAT_PRDRV_DAC_A : bit_vector := "111"; + TXDAT_PRDRV_DAC_B : bit_vector := "111"; + TXDAT_TAP_DAC_A : bit_vector := "10110"; + TXDAT_TAP_DAC_B : bit_vector := "10110"; + TXDIGPD_A : boolean := FALSE; + TXDIGPD_B : boolean := FALSE; + TXFDCAL_CLOCK_DIVIDE_A : string := "NONE"; + TXFDCAL_CLOCK_DIVIDE_B : string := "NONE"; + TXHIGHSIGNALEN_A : boolean := TRUE; + TXHIGHSIGNALEN_B : boolean := TRUE; + TXLOOPFILT_A : bit_vector := "0111"; + TXLOOPFILT_B : bit_vector := "0111"; + TXLVLSHFTPD_A : boolean := FALSE; + TXLVLSHFTPD_B : boolean := FALSE; + TXOUTCLK1_USE_SYNC_A : boolean := FALSE; + TXOUTCLK1_USE_SYNC_B : boolean := FALSE; + TXOUTDIV2SEL_A : integer := 1; + TXOUTDIV2SEL_B : integer := 1; + TXPD_A : boolean := FALSE; + TXPD_B : boolean := FALSE; + TXPHASESEL_A : boolean := FALSE; + TXPHASESEL_B : boolean := FALSE; + TXPLLNDIVSEL_A : integer := 8; + TXPLLNDIVSEL_B : integer := 8; + TXPOST_PRDRV_DAC_A : bit_vector := "111"; + TXPOST_PRDRV_DAC_B : bit_vector := "111"; + TXPOST_TAP_DAC_A : bit_vector := "01110"; + TXPOST_TAP_DAC_B : bit_vector := "01110"; + TXPOST_TAP_PD_A : boolean := TRUE; + TXPOST_TAP_PD_B : boolean := TRUE; + TXPRE_PRDRV_DAC_A : bit_vector := "111"; + TXPRE_PRDRV_DAC_B : bit_vector := "111"; + TXPRE_TAP_DAC_A : bit_vector := "00000"; + TXPRE_TAP_DAC_B : bit_vector := "00000"; + TXPRE_TAP_PD_A : boolean := TRUE; + TXPRE_TAP_PD_B : boolean := TRUE; + TXSLEWRATE_A : boolean := FALSE; + TXSLEWRATE_B : boolean := FALSE; + TXTERMTRIM_A : bit_vector := "1100"; + TXTERMTRIM_B : bit_vector := "1100"; + TXTUNE_A : bit_vector := X"0000"; + TXTUNE_B : bit_vector := X"0000"; + TX_BUFFER_USE_A : boolean := TRUE; + TX_BUFFER_USE_B : boolean := TRUE; + TX_CLOCK_DIVIDER_A : bit_vector := "00"; + TX_CLOCK_DIVIDER_B : bit_vector := "00"; + VCODAC_INIT_A : bit_vector := "1010000000"; + VCODAC_INIT_B : bit_vector := "1010000000"; + VCO_CTRL_ENABLE_A : boolean := FALSE; + VCO_CTRL_ENABLE_B : boolean := FALSE; + VREFBIASMODE_A : bit_vector := "11"; + VREFBIASMODE_B : bit_vector := "11" + ); + port + ( + CHBONDOA : out std_logic_vector(4 downto 0); + CHBONDOB : out std_logic_vector(4 downto 0); + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(15 downto 0); + DRDYA : out std_ulogic; + DRDYB : out std_ulogic; + RXBUFERRA : out std_ulogic; + RXBUFERRB : out std_ulogic; + RXCALFAILA : out std_ulogic; + RXCALFAILB : out std_ulogic; + RXCHARISCOMMAA : out std_logic_vector(7 downto 0); + RXCHARISCOMMAB : out std_logic_vector(7 downto 0); + RXCHARISKA : out std_logic_vector(7 downto 0); + RXCHARISKB : out std_logic_vector(7 downto 0); + RXCOMMADETA : out std_ulogic; + RXCOMMADETB : out std_ulogic; + RXCRCOUTA : out std_logic_vector(31 downto 0); + RXCRCOUTB : out std_logic_vector(31 downto 0); + RXCYCLELIMITA : out std_ulogic; + RXCYCLELIMITB : out std_ulogic; + RXDATAA : out std_logic_vector(63 downto 0); + RXDATAB : out std_logic_vector(63 downto 0); + RXDISPERRA : out std_logic_vector(7 downto 0); + RXDISPERRB : out std_logic_vector(7 downto 0); + RXLOCKA : out std_ulogic; + RXLOCKB : out std_ulogic; + RXLOSSOFSYNCA : out std_logic_vector(1 downto 0); + RXLOSSOFSYNCB : out std_logic_vector(1 downto 0); + RXMCLKA : out std_ulogic; + RXMCLKB : out std_ulogic; + RXNOTINTABLEA : out std_logic_vector(7 downto 0); + RXNOTINTABLEB : out std_logic_vector(7 downto 0); + RXPCSHCLKOUTA : out std_ulogic; + RXPCSHCLKOUTB : out std_ulogic; + RXREALIGNA : out std_ulogic; + RXREALIGNB : out std_ulogic; + RXRECCLK1A : out std_ulogic; + RXRECCLK1B : out std_ulogic; + RXRECCLK2A : out std_ulogic; + RXRECCLK2B : out std_ulogic; + RXRUNDISPA : out std_logic_vector(7 downto 0); + RXRUNDISPB : out std_logic_vector(7 downto 0); + RXSIGDETA : out std_ulogic; + RXSIGDETB : out std_ulogic; + RXSTATUSA : out std_logic_vector(5 downto 0); + RXSTATUSB : out std_logic_vector(5 downto 0); + TX1NA : out std_ulogic; + TX1NB : out std_ulogic; + TX1PA : out std_ulogic; + TX1PB : out std_ulogic; + TXBUFERRA : out std_ulogic; + TXBUFERRB : out std_ulogic; + TXCALFAILA : out std_ulogic; + TXCALFAILB : out std_ulogic; + TXCRCOUTA : out std_logic_vector(31 downto 0); + TXCRCOUTB : out std_logic_vector(31 downto 0); + TXCYCLELIMITA : out std_ulogic; + TXCYCLELIMITB : out std_ulogic; + TXKERRA : out std_logic_vector(7 downto 0); + TXKERRB : out std_logic_vector(7 downto 0); + TXLOCKA : out std_ulogic; + TXLOCKB : out std_ulogic; + TXOUTCLK1A : out std_ulogic; + TXOUTCLK1B : out std_ulogic; + TXOUTCLK2A : out std_ulogic; + TXOUTCLK2B : out std_ulogic; + TXPCSHCLKOUTA : out std_ulogic; + TXPCSHCLKOUTB : out std_ulogic; + TXRUNDISPA : out std_logic_vector(7 downto 0); + TXRUNDISPB : out std_logic_vector(7 downto 0); + CHBONDIA : in std_logic_vector(4 downto 0); + CHBONDIB : in std_logic_vector(4 downto 0); + DADDRA : in std_logic_vector(7 downto 0); + DADDRB : in std_logic_vector(7 downto 0); + DCLKA : in std_ulogic; + DCLKB : in std_ulogic; + DENA : in std_ulogic; + DENB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(15 downto 0); + DWEA : in std_ulogic; + DWEB : in std_ulogic; + ENCHANSYNCA : in std_ulogic; + ENCHANSYNCB : in std_ulogic; + ENMCOMMAALIGNA : in std_ulogic; + ENMCOMMAALIGNB : in std_ulogic; + ENPCOMMAALIGNA : in std_ulogic; + ENPCOMMAALIGNB : in std_ulogic; + GREFCLKA : in std_ulogic; + GREFCLKB : in std_ulogic; + LOOPBACKA : in std_logic_vector(1 downto 0); + LOOPBACKB : in std_logic_vector(1 downto 0); + POWERDOWNA : in std_ulogic; + POWERDOWNB : in std_ulogic; + REFCLK1A : in std_ulogic; + REFCLK1B : in std_ulogic; + REFCLK2A : in std_ulogic; + REFCLK2B : in std_ulogic; + RX1NA : in std_ulogic; + RX1NB : in std_ulogic; + RX1PA : in std_ulogic; + RX1PB : in std_ulogic; + RXBLOCKSYNC64B66BUSEA : in std_ulogic; + RXBLOCKSYNC64B66BUSEB : in std_ulogic; + RXCLKSTABLEA : in std_ulogic; + RXCLKSTABLEB : in std_ulogic; + RXCOMMADETUSEA : in std_ulogic; + RXCOMMADETUSEB : in std_ulogic; + RXCRCCLKA : in std_ulogic; + RXCRCCLKB : in std_ulogic; + RXCRCDATAVALIDA : in std_ulogic; + RXCRCDATAVALIDB : in std_ulogic; + RXCRCDATAWIDTHA : in std_logic_vector(2 downto 0); + RXCRCDATAWIDTHB : in std_logic_vector(2 downto 0); + RXCRCINA : in std_logic_vector(63 downto 0); + RXCRCINB : in std_logic_vector(63 downto 0); + RXCRCINITA : in std_ulogic; + RXCRCINITB : in std_ulogic; + RXCRCINTCLKA : in std_ulogic; + RXCRCINTCLKB : in std_ulogic; + RXCRCPDA : in std_ulogic; + RXCRCPDB : in std_ulogic; + RXCRCRESETA : in std_ulogic; + RXCRCRESETB : in std_ulogic; + RXDATAWIDTHA : in std_logic_vector(1 downto 0); + RXDATAWIDTHB : in std_logic_vector(1 downto 0); + RXDEC64B66BUSEA : in std_ulogic; + RXDEC64B66BUSEB : in std_ulogic; + RXDEC8B10BUSEA : in std_ulogic; + RXDEC8B10BUSEB : in std_ulogic; + RXDESCRAM64B66BUSEA : in std_ulogic; + RXDESCRAM64B66BUSEB : in std_ulogic; + RXIGNOREBTFA : in std_ulogic; + RXIGNOREBTFB : in std_ulogic; + RXINTDATAWIDTHA : in std_logic_vector(1 downto 0); + RXINTDATAWIDTHB : in std_logic_vector(1 downto 0); + RXPMARESETA : in std_ulogic; + RXPMARESETB : in std_ulogic; + RXPOLARITYA : in std_ulogic; + RXPOLARITYB : in std_ulogic; + RXRESETA : in std_ulogic; + RXRESETB : in std_ulogic; + RXSLIDEA : in std_ulogic; + RXSLIDEB : in std_ulogic; + RXSYNCA : in std_ulogic; + RXSYNCB : in std_ulogic; + RXUSRCLK2A : in std_ulogic; + RXUSRCLK2B : in std_ulogic; + RXUSRCLKA : in std_ulogic; + RXUSRCLKB : in std_ulogic; + TXBYPASS8B10BA : in std_logic_vector(7 downto 0); + TXBYPASS8B10BB : in std_logic_vector(7 downto 0); + TXCHARDISPMODEA : in std_logic_vector(7 downto 0); + TXCHARDISPMODEB : in std_logic_vector(7 downto 0); + TXCHARDISPVALA : in std_logic_vector(7 downto 0); + TXCHARDISPVALB : in std_logic_vector(7 downto 0); + TXCHARISKA : in std_logic_vector(7 downto 0); + TXCHARISKB : in std_logic_vector(7 downto 0); + TXCLKSTABLEA : in std_ulogic; + TXCLKSTABLEB : in std_ulogic; + TXCRCCLKA : in std_ulogic; + TXCRCCLKB : in std_ulogic; + TXCRCDATAVALIDA : in std_ulogic; + TXCRCDATAVALIDB : in std_ulogic; + TXCRCDATAWIDTHA : in std_logic_vector(2 downto 0); + TXCRCDATAWIDTHB : in std_logic_vector(2 downto 0); + TXCRCINA : in std_logic_vector(63 downto 0); + TXCRCINB : in std_logic_vector(63 downto 0); + TXCRCINITA : in std_ulogic; + TXCRCINITB : in std_ulogic; + TXCRCINTCLKA : in std_ulogic; + TXCRCINTCLKB : in std_ulogic; + TXCRCPDA : in std_ulogic; + TXCRCPDB : in std_ulogic; + TXCRCRESETA : in std_ulogic; + TXCRCRESETB : in std_ulogic; + TXDATAA : in std_logic_vector(63 downto 0); + TXDATAB : in std_logic_vector(63 downto 0); + TXDATAWIDTHA : in std_logic_vector(1 downto 0); + TXDATAWIDTHB : in std_logic_vector(1 downto 0); + TXENC64B66BUSEA : in std_ulogic; + TXENC64B66BUSEB : in std_ulogic; + TXENC8B10BUSEA : in std_ulogic; + TXENC8B10BUSEB : in std_ulogic; + TXENOOBA : in std_ulogic; + TXENOOBB : in std_ulogic; + TXGEARBOX64B66BUSEA : in std_ulogic; + TXGEARBOX64B66BUSEB : in std_ulogic; + TXINHIBITA : in std_ulogic; + TXINHIBITB : in std_ulogic; + TXINTDATAWIDTHA : in std_logic_vector(1 downto 0); + TXINTDATAWIDTHB : in std_logic_vector(1 downto 0); + TXPMARESETA : in std_ulogic; + TXPMARESETB : in std_ulogic; + TXPOLARITYA : in std_ulogic; + TXPOLARITYB : in std_ulogic; + TXRESETA : in std_ulogic; + TXRESETB : in std_ulogic; + TXSCRAM64B66BUSEA : in std_ulogic; + TXSCRAM64B66BUSEB : in std_ulogic; + TXSYNCA : in std_ulogic; + TXSYNCB : in std_ulogic; + TXUSRCLK2A : in std_ulogic; + TXUSRCLK2B : in std_ulogic; + TXUSRCLKA : in std_ulogic; + TXUSRCLKB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT11_DUAL : component is "PRIMITIVE"; + +----- component GT11 ----- +component GT11 + generic + ( + IN_DELAY : time := 0 ps; + ALIGN_COMMA_WORD : integer := 4; + BANDGAPSEL : boolean := FALSE; + BIASRESSEL : boolean := FALSE; + CCCB_ARBITRATOR_DISABLE : boolean := FALSE; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "NONE"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_MASK : bit_vector := "1110"; + CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_MASK : bit_vector := "1110"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 1; + CLK_CORRECT_USE : boolean := FALSE; + CLK_COR_8B10B_DE : boolean := FALSE; + CLK_COR_MAX_LAT : integer := 48; + CLK_COR_MIN_LAT : integer := 36; + CLK_COR_SEQ_1_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_MASK : bit_vector := "1110"; + CLK_COR_SEQ_2_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_MASK : bit_vector := "1110"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_DROP : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 1; + COMMA32 : boolean := FALSE; + COMMA_10B_MASK : bit_vector := X"3FF"; + CYCLE_LIMIT_SEL : bit_vector := "00"; + DCDR_FILTER : bit_vector := "010"; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + DIGRX_FWDCLK : bit_vector := "00"; + DIGRX_SYNC_MODE : boolean := FALSE; + ENABLE_DCDR : boolean := FALSE; + FDET_HYS_CAL : bit_vector := "010"; + FDET_HYS_SEL : bit_vector := "100"; + FDET_LCK_CAL : bit_vector := "100"; + FDET_LCK_SEL : bit_vector := "001"; + GT11_MODE : string := "DONT_CARE"; + IREFBIASMODE : bit_vector := "11"; + LOOPCAL_WAIT : bit_vector := "00"; + MCOMMA_32B_VALUE : bit_vector := X"00000000"; + MCOMMA_DETECT : boolean := TRUE; + OPPOSITE_SELECT : boolean := FALSE; + PCOMMA_32B_VALUE : bit_vector := X"00000000"; + PCOMMA_DETECT : boolean := TRUE; + PCS_BIT_SLIP : boolean := FALSE; + PMACLKENABLE : boolean := TRUE; + PMACOREPWRENABLE : boolean := TRUE; + PMAIREFTRIM : bit_vector := "0111"; + PMAVBGCTRL : bit_vector := "00000"; + PMAVREFTRIM : bit_vector := "0111"; + PMA_BIT_SLIP : boolean := FALSE; + POWER_ENABLE : boolean := TRUE; + REPEATER : boolean := FALSE; + RXACTST : boolean := FALSE; + RXAFEEQ : bit_vector := "000000000"; + RXAFEPD : boolean := FALSE; + RXAFETST : boolean := FALSE; + RXAPD : boolean := FALSE; + RXAREGCTRL : bit_vector := "00000"; + RXASYNCDIVIDE : bit_vector := "11"; + RXBY_32 : boolean := FALSE; + RXCDRLOS : bit_vector := "000000"; + RXCLK0_FORCE_PMACLK : boolean := FALSE; + RXCLKMODE : bit_vector := "110001"; + RXCLMODE : bit_vector := "00"; + RXCMADJ : bit_vector := "01"; + RXCPSEL : boolean := TRUE; + RXCPTST : boolean := FALSE; + RXCRCCLOCKDOUBLE : boolean := FALSE; + RXCRCENABLE : boolean := FALSE; + RXCRCINITVAL : bit_vector := X"00000000"; + RXCRCINVERTGEN : boolean := FALSE; + RXCRCSAMECLOCK : boolean := FALSE; + RXCTRL1 : bit_vector := X"200"; + RXCYCLE_LIMIT_SEL : bit_vector := "00"; + RXDATA_SEL : bit_vector := "00"; + RXDCCOUPLE : boolean := FALSE; + RXDIGRESET : boolean := FALSE; + RXDIGRX : boolean := FALSE; + RXEQ : bit_vector := X"4000000000000000"; + RXFDCAL_CLOCK_DIVIDE : string := "NONE"; + RXFDET_HYS_CAL : bit_vector := "010"; + RXFDET_HYS_SEL : bit_vector := "100"; + RXFDET_LCK_CAL : bit_vector := "100"; + RXFDET_LCK_SEL : bit_vector := "001"; + RXFECONTROL1 : bit_vector := "00"; + RXFECONTROL2 : bit_vector := "000"; + RXFETUNE : bit_vector := "01"; + RXLB : boolean := FALSE; + RXLKADJ : bit_vector := "00000"; + RXLKAPD : boolean := FALSE; + RXLOOPCAL_WAIT : bit_vector := "00"; + RXLOOPFILT : bit_vector := "0111"; + RXMODE : bit_vector := "000000"; + RXOUTDIV2SEL : integer := 1; + RXPD : boolean := FALSE; + RXPDDTST : boolean := TRUE; + RXPLLNDIVSEL : integer := 8; + RXPMACLKSEL : string := "REFCLK1"; + RXRCPADJ : bit_vector := "011"; + RXRCPPD : boolean := FALSE; + RXRECCLK1_USE_SYNC : boolean := FALSE; + RXRIBADJ : bit_vector := "11"; + RXRPDPD : boolean := FALSE; + RXRSDPD : boolean := FALSE; + RXSLOWDOWN_CAL : bit_vector := "00"; + RXTUNE : bit_vector := X"0000"; + RXUSRDIVISOR : integer := 1; + RXVCODAC_INIT : bit_vector := "1010000000"; + RXVCO_CTRL_ENABLE : boolean := FALSE; + RX_BUFFER_USE : boolean := TRUE; + RX_CLOCK_DIVIDER : bit_vector := "00"; + SAMPLE_8X : boolean := FALSE; + SH_CNT_MAX : integer := 64; + SH_INVALID_CNT_MAX : integer := 16; + SLOWDOWN_CAL : bit_vector := "00"; + TXABPMACLKSEL : string := "REFCLK1"; + TXAPD : boolean := FALSE; + TXAREFBIASSEL : boolean := TRUE; + TXASYNCDIVIDE : bit_vector := "11"; + TXCLK0_FORCE_PMACLK : boolean := FALSE; + TXCLKMODE : bit_vector := "1001"; + TXCLMODE : bit_vector := "00"; + TXCPSEL : boolean := TRUE; + TXCRCCLOCKDOUBLE : boolean := FALSE; + TXCRCENABLE : boolean := FALSE; + TXCRCINITVAL : bit_vector := X"00000000"; + TXCRCINVERTGEN : boolean := FALSE; + TXCRCSAMECLOCK : boolean := FALSE; + TXCTRL1 : bit_vector := X"200"; + TXDATA_SEL : bit_vector := "00"; + TXDAT_PRDRV_DAC : bit_vector := "111"; + TXDAT_TAP_DAC : bit_vector := "10110"; + TXDIGPD : boolean := FALSE; + TXFDCAL_CLOCK_DIVIDE : string := "NONE"; + TXHIGHSIGNALEN : boolean := TRUE; + TXLOOPFILT : bit_vector := "0111"; + TXLVLSHFTPD : boolean := FALSE; + TXOUTCLK1_USE_SYNC : boolean := FALSE; + TXOUTDIV2SEL : integer := 1; + TXPD : boolean := FALSE; + TXPHASESEL : boolean := FALSE; + TXPLLNDIVSEL : integer := 8; + TXPOST_PRDRV_DAC : bit_vector := "111"; + TXPOST_TAP_DAC : bit_vector := "01110"; + TXPOST_TAP_PD : boolean := TRUE; + TXPRE_PRDRV_DAC : bit_vector := "111"; + TXPRE_TAP_DAC : bit_vector := "00000"; + TXPRE_TAP_PD : boolean := TRUE; + TXSLEWRATE : boolean := FALSE; + TXTERMTRIM : bit_vector := "1100"; + TXTUNE : bit_vector := X"0000"; + TX_BUFFER_USE : boolean := TRUE; + TX_CLOCK_DIVIDER : bit_vector := "00"; + VCODAC_INIT : bit_vector := "1010000000"; + VCO_CTRL_ENABLE : boolean := FALSE; + VREFBIASMODE : bit_vector := "11" + ); + port + ( + CHBONDO : out std_logic_vector(4 downto 0); + COMBUSOUT : out std_logic_vector(15 downto 0); + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + RXBUFERR : out std_ulogic; + RXCALFAIL : out std_ulogic; + RXCHARISCOMMA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic_vector(7 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCOUT : out std_logic_vector(31 downto 0); + RXCYCLELIMIT : out std_ulogic; + RXDATA : out std_logic_vector(63 downto 0); + RXDISPERR : out std_logic_vector(7 downto 0); + RXLOCK : out std_ulogic; + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXMCLK : out std_ulogic; + RXNOTINTABLE : out std_logic_vector(7 downto 0); + RXPCSHCLKOUT : out std_ulogic; + RXREALIGN : out std_ulogic; + RXRECCLK1 : out std_ulogic; + RXRECCLK2 : out std_ulogic; + RXRUNDISP : out std_logic_vector(7 downto 0); + RXSIGDET : out std_ulogic; + RXSTATUS : out std_logic_vector(5 downto 0); + TX1N : out std_ulogic; + TX1P : out std_ulogic; + TXBUFERR : out std_ulogic; + TXCALFAIL : out std_ulogic; + TXCRCOUT : out std_logic_vector(31 downto 0); + TXCYCLELIMIT : out std_ulogic; + TXKERR : out std_logic_vector(7 downto 0); + TXLOCK : out std_ulogic; + TXOUTCLK1 : out std_ulogic; + TXOUTCLK2 : out std_ulogic; + TXPCSHCLKOUT : out std_ulogic; + TXRUNDISP : out std_logic_vector(7 downto 0); + CHBONDI : in std_logic_vector(4 downto 0); + COMBUSIN : in std_logic_vector(15 downto 0); + DADDR : in std_logic_vector(7 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + GREFCLK : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK1 : in std_ulogic; + REFCLK2 : in std_ulogic; + RX1N : in std_ulogic; + RX1P : in std_ulogic; + RXBLOCKSYNC64B66BUSE : in std_ulogic; + RXCLKSTABLE : in std_ulogic; + RXCOMMADETUSE : in std_ulogic; + RXCRCCLK : in std_ulogic; + RXCRCDATAVALID : in std_ulogic; + RXCRCDATAWIDTH : in std_logic_vector(2 downto 0); + RXCRCIN : in std_logic_vector(63 downto 0); + RXCRCINIT : in std_ulogic; + RXCRCINTCLK : in std_ulogic; + RXCRCPD : in std_ulogic; + RXCRCRESET : in std_ulogic; + RXDATAWIDTH : in std_logic_vector(1 downto 0); + RXDEC64B66BUSE : in std_ulogic; + RXDEC8B10BUSE : in std_ulogic; + RXDESCRAM64B66BUSE : in std_ulogic; + RXIGNOREBTF : in std_ulogic; + RXINTDATAWIDTH : in std_logic_vector(1 downto 0); + RXPMARESET : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXSLIDE : in std_ulogic; + RXSYNC : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(7 downto 0); + TXCHARDISPMODE : in std_logic_vector(7 downto 0); + TXCHARDISPVAL : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic_vector(7 downto 0); + TXCLKSTABLE : in std_ulogic; + TXCRCCLK : in std_ulogic; + TXCRCDATAVALID : in std_ulogic; + TXCRCDATAWIDTH : in std_logic_vector(2 downto 0); + TXCRCIN : in std_logic_vector(63 downto 0); + TXCRCINIT : in std_ulogic; + TXCRCINTCLK : in std_ulogic; + TXCRCPD : in std_ulogic; + TXCRCRESET : in std_ulogic; + TXDATA : in std_logic_vector(63 downto 0); + TXDATAWIDTH : in std_logic_vector(1 downto 0); + TXENC64B66BUSE : in std_ulogic; + TXENC8B10BUSE : in std_ulogic; + TXENOOB : in std_ulogic; + TXGEARBOX64B66BUSE : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXINTDATAWIDTH : in std_logic_vector(1 downto 0); + TXPMARESET : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXSCRAM64B66BUSE : in std_ulogic; + TXSYNC : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT11 : component is "PRIMITIVE"; + +----- component GT_AURORA_1 ----- +component GT_AURORA_1 + generic + ( + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT_AURORA_1 : component is "PRIMITIVE"; + +----- component GT_AURORA_2 ----- +component GT_AURORA_2 + generic + ( + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT_AURORA_2 : component is "PRIMITIVE"; + +----- component GT_AURORA_4 ----- +component GT_AURORA_4 + generic + ( + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT_AURORA_4 : component is "PRIMITIVE"; + +----- component GT_CUSTOM ----- +component GT_CUSTOM + generic + ( + ALIGN_COMMA_MSB : boolean := FALSE; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_OFFSET : integer := 8; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 1; + CHAN_BOND_WAIT : integer := 8; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + CLK_COR_SEQ_1_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 1; + CLK_CORRECT_USE : boolean := TRUE; + COMMA_10B_MASK : bit_vector := "1111111000"; + CRC_END_OF_PKT : string := "K29_7"; + CRC_FORMAT : string := "USER_MODE"; + CRC_START_OF_PKT : string := "K27_7"; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + MCOMMA_10B_VALUE : bit_vector := "1100000000"; + MCOMMA_DETECT : boolean := TRUE; + PCOMMA_10B_VALUE : bit_vector := "0011111000"; + PCOMMA_DETECT : boolean := TRUE; + REF_CLK_V_SEL : integer := 0; + RX_BUFFER_USE : boolean := TRUE; + RX_CRC_USE : boolean := FALSE; + RX_DATA_WIDTH : integer := 2; + RX_DECODE_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_BUFFER_USE : boolean := TRUE; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DATA_WIDTH : integer := 2; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT_CUSTOM : component is "PRIMITIVE"; + +----- component GT_ETHERNET_1 ----- +component GT_ETHERNET_1 + generic + ( + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + ); + port + ( + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT_ETHERNET_1 : component is "PRIMITIVE"; + +----- component GT_ETHERNET_2 ----- +component GT_ETHERNET_2 + generic + ( + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + ); + port + ( + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT_ETHERNET_2 : component is "PRIMITIVE"; + +----- component GT_ETHERNET_4 ----- +component GT_ETHERNET_4 + generic + ( + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + ); + port + ( + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT_ETHERNET_4 : component is "PRIMITIVE"; + +----- component GT_FIBRE_CHAN_1 ----- +component GT_FIBRE_CHAN_1 + generic + ( + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 2; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + ); + port + ( + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT_FIBRE_CHAN_1 : component is "PRIMITIVE"; + +----- component GT_FIBRE_CHAN_2 ----- +component GT_FIBRE_CHAN_2 + generic + ( + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 2; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + ); + port + ( + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT_FIBRE_CHAN_2 : component is "PRIMITIVE"; + +----- component GT_FIBRE_CHAN_4 ----- +component GT_FIBRE_CHAN_4 + generic + ( + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 2; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + ); + port + ( + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT_FIBRE_CHAN_4 : component is "PRIMITIVE"; + +----- component GT_INFINIBAND_1 ----- +component GT_INFINIBAND_1 + generic + ( + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + LANE_ID : bit_vector := "00000000000"; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT_INFINIBAND_1 : component is "PRIMITIVE"; + +----- component GT_INFINIBAND_2 ----- +component GT_INFINIBAND_2 + generic + ( + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + LANE_ID : bit_vector := "00000000000"; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT_INFINIBAND_2 : component is "PRIMITIVE"; + +----- component GT_INFINIBAND_4 ----- +component GT_INFINIBAND_4 + generic + ( + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + LANE_ID : bit_vector := "00000000000"; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT_INFINIBAND_4 : component is "PRIMITIVE"; + +----- component GTP_DUAL ----- +component GTP_DUAL + generic + ( + AC_CAP_DIS_0 : boolean := TRUE; + AC_CAP_DIS_1 : boolean := TRUE; + ALIGN_COMMA_WORD_0 : integer := 1; + ALIGN_COMMA_WORD_1 : integer := 1; + CHAN_BOND_1_MAX_SKEW_0 : integer := 7; + CHAN_BOND_1_MAX_SKEW_1 : integer := 7; + CHAN_BOND_2_MAX_SKEW_0 : integer := 1; + CHAN_BOND_2_MAX_SKEW_1 : integer := 1; + CHAN_BOND_LEVEL_0 : integer := 0; + CHAN_BOND_LEVEL_1 : integer := 0; + CHAN_BOND_MODE_0 : string := "OFF"; + CHAN_BOND_MODE_1 : string := "OFF"; + CHAN_BOND_SEQ_1_1_0 : bit_vector := "0001001010"; + CHAN_BOND_SEQ_1_1_1 : bit_vector := "0001001010"; + CHAN_BOND_SEQ_1_2_0 : bit_vector := "0001001010"; + CHAN_BOND_SEQ_1_2_1 : bit_vector := "0001001010"; + CHAN_BOND_SEQ_1_3_0 : bit_vector := "0001001010"; + CHAN_BOND_SEQ_1_3_1 : bit_vector := "0001001010"; + CHAN_BOND_SEQ_1_4_0 : bit_vector := "0110111100"; + CHAN_BOND_SEQ_1_4_1 : bit_vector := "0110111100"; + CHAN_BOND_SEQ_1_ENABLE_0 : bit_vector := "1111"; + CHAN_BOND_SEQ_1_ENABLE_1 : bit_vector := "1111"; + CHAN_BOND_SEQ_2_1_0 : bit_vector := "0110111100"; + CHAN_BOND_SEQ_2_1_1 : bit_vector := "0110111100"; + CHAN_BOND_SEQ_2_2_0 : bit_vector := "0100111100"; + CHAN_BOND_SEQ_2_2_1 : bit_vector := "0100111100"; + CHAN_BOND_SEQ_2_3_0 : bit_vector := "0100111100"; + CHAN_BOND_SEQ_2_3_1 : bit_vector := "0100111100"; + CHAN_BOND_SEQ_2_4_0 : bit_vector := "0100111100"; + CHAN_BOND_SEQ_2_4_1 : bit_vector := "0100111100"; + CHAN_BOND_SEQ_2_ENABLE_0 : bit_vector := "1111"; + CHAN_BOND_SEQ_2_ENABLE_1 : bit_vector := "1111"; + CHAN_BOND_SEQ_2_USE_0 : boolean := TRUE; + CHAN_BOND_SEQ_2_USE_1 : boolean := TRUE; + CHAN_BOND_SEQ_LEN_0 : integer := 4; + CHAN_BOND_SEQ_LEN_1 : integer := 4; + CLK25_DIVIDER : integer := 4; + CLKINDC_B : boolean := TRUE; + CLK_CORRECT_USE_0 : boolean := TRUE; + CLK_CORRECT_USE_1 : boolean := TRUE; + CLK_COR_ADJ_LEN_0 : integer := 1; + CLK_COR_ADJ_LEN_1 : integer := 1; + CLK_COR_DET_LEN_0 : integer := 1; + CLK_COR_DET_LEN_1 : integer := 1; + CLK_COR_INSERT_IDLE_FLAG_0 : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG_1 : boolean := FALSE; + CLK_COR_KEEP_IDLE_0 : boolean := FALSE; + CLK_COR_KEEP_IDLE_1 : boolean := FALSE; + CLK_COR_MAX_LAT_0 : integer := 18; + CLK_COR_MAX_LAT_1 : integer := 18; + CLK_COR_MIN_LAT_0 : integer := 16; + CLK_COR_MIN_LAT_1 : integer := 16; + CLK_COR_PRECEDENCE_0 : boolean := TRUE; + CLK_COR_PRECEDENCE_1 : boolean := TRUE; + CLK_COR_REPEAT_WAIT_0 : integer := 5; + CLK_COR_REPEAT_WAIT_1 : integer := 5; + CLK_COR_SEQ_1_1_0 : bit_vector := "0100011100"; + CLK_COR_SEQ_1_1_1 : bit_vector := "0100011100"; + CLK_COR_SEQ_1_2_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_2_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_3_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_3_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_4_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_4_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_ENABLE_0 : bit_vector := "1111"; + CLK_COR_SEQ_1_ENABLE_1 : bit_vector := "1111"; + CLK_COR_SEQ_2_1_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_1_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_2_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_2_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_3_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_3_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_4_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_4_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_ENABLE_0 : bit_vector := "1111"; + CLK_COR_SEQ_2_ENABLE_1 : bit_vector := "1111"; + CLK_COR_SEQ_2_USE_0 : boolean := FALSE; + CLK_COR_SEQ_2_USE_1 : boolean := FALSE; + COMMA_10B_ENABLE_0 : bit_vector := "1111111111"; + COMMA_10B_ENABLE_1 : bit_vector := "1111111111"; + COMMA_DOUBLE_0 : boolean := FALSE; + COMMA_DOUBLE_1 : boolean := FALSE; + COM_BURST_VAL_0 : bit_vector := "1111"; + COM_BURST_VAL_1 : bit_vector := "1111"; + DEC_MCOMMA_DETECT_0 : boolean := TRUE; + DEC_MCOMMA_DETECT_1 : boolean := TRUE; + DEC_PCOMMA_DETECT_0 : boolean := TRUE; + DEC_PCOMMA_DETECT_1 : boolean := TRUE; + DEC_VALID_COMMA_ONLY_0 : boolean := TRUE; + DEC_VALID_COMMA_ONLY_1 : boolean := TRUE; + MCOMMA_10B_VALUE_0 : bit_vector := "1010000011"; + MCOMMA_10B_VALUE_1 : bit_vector := "1010000011"; + MCOMMA_DETECT_0 : boolean := TRUE; + MCOMMA_DETECT_1 : boolean := TRUE; + OOBDETECT_THRESHOLD_0 : bit_vector := "001"; + OOBDETECT_THRESHOLD_1 : bit_vector := "001"; + OOB_CLK_DIVIDER : integer := 4; + OVERSAMPLE_MODE : boolean := FALSE; + PCI_EXPRESS_MODE_0 : boolean := TRUE; + PCI_EXPRESS_MODE_1 : boolean := TRUE; + PCOMMA_10B_VALUE_0 : bit_vector := "0101111100"; + PCOMMA_10B_VALUE_1 : bit_vector := "0101111100"; + PCOMMA_DETECT_0 : boolean := TRUE; + PCOMMA_DETECT_1 : boolean := TRUE; + PCS_COM_CFG : bit_vector := X"1680a0e"; + PLL_DIVSEL_FB : integer := 5; + PLL_DIVSEL_REF : integer := 2; + PLL_RXDIVSEL_OUT_0 : integer := 1; + PLL_RXDIVSEL_OUT_1 : integer := 1; + PLL_SATA_0 : boolean := FALSE; + PLL_SATA_1 : boolean := FALSE; + PLL_TXDIVSEL_COMM_OUT : integer := 1; + PLL_TXDIVSEL_OUT_0 : integer := 1; + PLL_TXDIVSEL_OUT_1 : integer := 1; + PMA_CDR_SCAN_0 : bit_vector := X"6c07640"; + PMA_CDR_SCAN_1 : bit_vector := X"6c07640"; + PMA_RX_CFG_0 : bit_vector := X"09f0089"; + PMA_RX_CFG_1 : bit_vector := X"09f0089"; + PRBS_ERR_THRESHOLD_0 : bit_vector := X"00000001"; + PRBS_ERR_THRESHOLD_1 : bit_vector := X"00000001"; + RCV_TERM_GND_0 : boolean := TRUE; + RCV_TERM_GND_1 : boolean := TRUE; + RCV_TERM_MID_0 : boolean := FALSE; + RCV_TERM_MID_1 : boolean := FALSE; + RCV_TERM_VTTRX_0 : boolean := FALSE; + RCV_TERM_VTTRX_1 : boolean := FALSE; + RX_BUFFER_USE_0 : boolean := TRUE; + RX_BUFFER_USE_1 : boolean := TRUE; + RX_DECODE_SEQ_MATCH_0 : boolean := TRUE; + RX_DECODE_SEQ_MATCH_1 : boolean := TRUE; + RX_LOSS_OF_SYNC_FSM_0 : boolean := FALSE; + RX_LOSS_OF_SYNC_FSM_1 : boolean := FALSE; + RX_LOS_INVALID_INCR_0 : integer := 8; + RX_LOS_INVALID_INCR_1 : integer := 8; + RX_LOS_THRESHOLD_0 : integer := 128; + RX_LOS_THRESHOLD_1 : integer := 128; + RX_SLIDE_MODE_0 : string := "PCS"; + RX_SLIDE_MODE_1 : string := "PCS"; + RX_STATUS_FMT_0 : string := "PCIE"; + RX_STATUS_FMT_1 : string := "PCIE"; + RX_XCLK_SEL_0 : string := "RXREC"; + RX_XCLK_SEL_1 : string := "RXREC"; + SATA_BURST_VAL_0 : bit_vector := "100"; + SATA_BURST_VAL_1 : bit_vector := "100"; + SATA_IDLE_VAL_0 : bit_vector := "011"; + SATA_IDLE_VAL_1 : bit_vector := "011"; + SATA_MAX_BURST_0 : integer := 7; + SATA_MAX_BURST_1 : integer := 7; + SATA_MAX_INIT_0 : integer := 22; + SATA_MAX_INIT_1 : integer := 22; + SATA_MAX_WAKE_0 : integer := 7; + SATA_MAX_WAKE_1 : integer := 7; + SATA_MIN_BURST_0 : integer := 4; + SATA_MIN_BURST_1 : integer := 4; + SATA_MIN_INIT_0 : integer := 12; + SATA_MIN_INIT_1 : integer := 12; + SATA_MIN_WAKE_0 : integer := 4; + SATA_MIN_WAKE_1 : integer := 4; + SIM_GTPRESET_SPEEDUP : integer := 0; + SIM_MODE : string := "FAST"; + SIM_PLL_PERDIV2 : bit_vector := X"190"; + SIM_RECEIVER_DETECT_PASS0 : boolean := FALSE; + SIM_RECEIVER_DETECT_PASS1 : boolean := FALSE; + TERMINATION_CTRL : bit_vector := "10100"; + TERMINATION_IMP_0 : integer := 50; + TERMINATION_IMP_1 : integer := 50; + TERMINATION_OVRD : boolean := FALSE; + TRANS_TIME_FROM_P2_0 : bit_vector := X"003c"; + TRANS_TIME_FROM_P2_1 : bit_vector := X"003c"; + TRANS_TIME_NON_P2_0 : bit_vector := X"0019"; + TRANS_TIME_NON_P2_1 : bit_vector := X"0019"; + TRANS_TIME_TO_P2_0 : bit_vector := X"0064"; + TRANS_TIME_TO_P2_1 : bit_vector := X"0064"; + TXRX_INVERT_0 : bit_vector := "00000"; + TXRX_INVERT_1 : bit_vector := "00000"; + TX_BUFFER_USE_0 : boolean := TRUE; + TX_BUFFER_USE_1 : boolean := TRUE; + TX_DIFF_BOOST_0 : boolean := TRUE; + TX_DIFF_BOOST_1 : boolean := TRUE; + TX_SYNC_FILTERB : integer := 1; + TX_XCLK_SEL_0 : string := "TXUSR"; + TX_XCLK_SEL_1 : string := "TXUSR" + ); + port + ( + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + PHYSTATUS0 : out std_ulogic; + PHYSTATUS1 : out std_ulogic; + PLLLKDET : out std_ulogic; + REFCLKOUT : out std_ulogic; + RESETDONE0 : out std_ulogic; + RESETDONE1 : out std_ulogic; + RXBUFSTATUS0 : out std_logic_vector(2 downto 0); + RXBUFSTATUS1 : out std_logic_vector(2 downto 0); + RXBYTEISALIGNED0 : out std_ulogic; + RXBYTEISALIGNED1 : out std_ulogic; + RXBYTEREALIGN0 : out std_ulogic; + RXBYTEREALIGN1 : out std_ulogic; + RXCHANBONDSEQ0 : out std_ulogic; + RXCHANBONDSEQ1 : out std_ulogic; + RXCHANISALIGNED0 : out std_ulogic; + RXCHANISALIGNED1 : out std_ulogic; + RXCHANREALIGN0 : out std_ulogic; + RXCHANREALIGN1 : out std_ulogic; + RXCHARISCOMMA0 : out std_logic_vector(1 downto 0); + RXCHARISCOMMA1 : out std_logic_vector(1 downto 0); + RXCHARISK0 : out std_logic_vector(1 downto 0); + RXCHARISK1 : out std_logic_vector(1 downto 0); + RXCHBONDO0 : out std_logic_vector(2 downto 0); + RXCHBONDO1 : out std_logic_vector(2 downto 0); + RXCLKCORCNT0 : out std_logic_vector(2 downto 0); + RXCLKCORCNT1 : out std_logic_vector(2 downto 0); + RXCOMMADET0 : out std_ulogic; + RXCOMMADET1 : out std_ulogic; + RXDATA0 : out std_logic_vector(15 downto 0); + RXDATA1 : out std_logic_vector(15 downto 0); + RXDISPERR0 : out std_logic_vector(1 downto 0); + RXDISPERR1 : out std_logic_vector(1 downto 0); + RXELECIDLE0 : out std_ulogic; + RXELECIDLE1 : out std_ulogic; + RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); + RXNOTINTABLE0 : out std_logic_vector(1 downto 0); + RXNOTINTABLE1 : out std_logic_vector(1 downto 0); + RXOVERSAMPLEERR0 : out std_ulogic; + RXOVERSAMPLEERR1 : out std_ulogic; + RXPRBSERR0 : out std_ulogic; + RXPRBSERR1 : out std_ulogic; + RXRECCLK0 : out std_ulogic; + RXRECCLK1 : out std_ulogic; + RXRUNDISP0 : out std_logic_vector(1 downto 0); + RXRUNDISP1 : out std_logic_vector(1 downto 0); + RXSTATUS0 : out std_logic_vector(2 downto 0); + RXSTATUS1 : out std_logic_vector(2 downto 0); + RXVALID0 : out std_ulogic; + RXVALID1 : out std_ulogic; + TXBUFSTATUS0 : out std_logic_vector(1 downto 0); + TXBUFSTATUS1 : out std_logic_vector(1 downto 0); + TXKERR0 : out std_logic_vector(1 downto 0); + TXKERR1 : out std_logic_vector(1 downto 0); + TXN0 : out std_ulogic; + TXN1 : out std_ulogic; + TXOUTCLK0 : out std_ulogic; + TXOUTCLK1 : out std_ulogic; + TXP0 : out std_ulogic; + TXP1 : out std_ulogic; + TXRUNDISP0 : out std_logic_vector(1 downto 0); + TXRUNDISP1 : out std_logic_vector(1 downto 0); + CLKIN : in std_ulogic; + DADDR : in std_logic_vector(6 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + GTPRESET : in std_ulogic; + GTPTEST : in std_logic_vector(3 downto 0); + INTDATAWIDTH : in std_ulogic; + LOOPBACK0 : in std_logic_vector(2 downto 0); + LOOPBACK1 : in std_logic_vector(2 downto 0); + PLLLKDETEN : in std_ulogic; + PLLPOWERDOWN : in std_ulogic; + PRBSCNTRESET0 : in std_ulogic; + PRBSCNTRESET1 : in std_ulogic; + REFCLKPWRDNB : in std_ulogic; + RXBUFRESET0 : in std_ulogic; + RXBUFRESET1 : in std_ulogic; + RXCDRRESET0 : in std_ulogic; + RXCDRRESET1 : in std_ulogic; + RXCHBONDI0 : in std_logic_vector(2 downto 0); + RXCHBONDI1 : in std_logic_vector(2 downto 0); + RXCOMMADETUSE0 : in std_ulogic; + RXCOMMADETUSE1 : in std_ulogic; + RXDATAWIDTH0 : in std_ulogic; + RXDATAWIDTH1 : in std_ulogic; + RXDEC8B10BUSE0 : in std_ulogic; + RXDEC8B10BUSE1 : in std_ulogic; + RXELECIDLERESET0 : in std_ulogic; + RXELECIDLERESET1 : in std_ulogic; + RXENCHANSYNC0 : in std_ulogic; + RXENCHANSYNC1 : in std_ulogic; + RXENELECIDLERESETB : in std_ulogic; + RXENEQB0 : in std_ulogic; + RXENEQB1 : in std_ulogic; + RXENMCOMMAALIGN0 : in std_ulogic; + RXENMCOMMAALIGN1 : in std_ulogic; + RXENPCOMMAALIGN0 : in std_ulogic; + RXENPCOMMAALIGN1 : in std_ulogic; + RXENPRBSTST0 : in std_logic_vector(1 downto 0); + RXENPRBSTST1 : in std_logic_vector(1 downto 0); + RXENSAMPLEALIGN0 : in std_ulogic; + RXENSAMPLEALIGN1 : in std_ulogic; + RXEQMIX0 : in std_logic_vector(1 downto 0); + RXEQMIX1 : in std_logic_vector(1 downto 0); + RXEQPOLE0 : in std_logic_vector(3 downto 0); + RXEQPOLE1 : in std_logic_vector(3 downto 0); + RXN0 : in std_ulogic; + RXN1 : in std_ulogic; + RXP0 : in std_ulogic; + RXP1 : in std_ulogic; + RXPMASETPHASE0 : in std_ulogic; + RXPMASETPHASE1 : in std_ulogic; + RXPOLARITY0 : in std_ulogic; + RXPOLARITY1 : in std_ulogic; + RXPOWERDOWN0 : in std_logic_vector(1 downto 0); + RXPOWERDOWN1 : in std_logic_vector(1 downto 0); + RXRESET0 : in std_ulogic; + RXRESET1 : in std_ulogic; + RXSLIDE0 : in std_ulogic; + RXSLIDE1 : in std_ulogic; + RXUSRCLK0 : in std_ulogic; + RXUSRCLK1 : in std_ulogic; + RXUSRCLK20 : in std_ulogic; + RXUSRCLK21 : in std_ulogic; + TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXBYPASS8B10B0 : in std_logic_vector(1 downto 0); + TXBYPASS8B10B1 : in std_logic_vector(1 downto 0); + TXCHARDISPMODE0 : in std_logic_vector(1 downto 0); + TXCHARDISPMODE1 : in std_logic_vector(1 downto 0); + TXCHARDISPVAL0 : in std_logic_vector(1 downto 0); + TXCHARDISPVAL1 : in std_logic_vector(1 downto 0); + TXCHARISK0 : in std_logic_vector(1 downto 0); + TXCHARISK1 : in std_logic_vector(1 downto 0); + TXCOMSTART0 : in std_ulogic; + TXCOMSTART1 : in std_ulogic; + TXCOMTYPE0 : in std_ulogic; + TXCOMTYPE1 : in std_ulogic; + TXDATA0 : in std_logic_vector(15 downto 0); + TXDATA1 : in std_logic_vector(15 downto 0); + TXDATAWIDTH0 : in std_ulogic; + TXDATAWIDTH1 : in std_ulogic; + TXDETECTRX0 : in std_ulogic; + TXDETECTRX1 : in std_ulogic; + TXDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXELECIDLE0 : in std_ulogic; + TXELECIDLE1 : in std_ulogic; + TXENC8B10BUSE0 : in std_ulogic; + TXENC8B10BUSE1 : in std_ulogic; + TXENPMAPHASEALIGN : in std_ulogic; + TXENPRBSTST0 : in std_logic_vector(1 downto 0); + TXENPRBSTST1 : in std_logic_vector(1 downto 0); + TXINHIBIT0 : in std_ulogic; + TXINHIBIT1 : in std_ulogic; + TXPMASETPHASE : in std_ulogic; + TXPOLARITY0 : in std_ulogic; + TXPOLARITY1 : in std_ulogic; + TXPOWERDOWN0 : in std_logic_vector(1 downto 0); + TXPOWERDOWN1 : in std_logic_vector(1 downto 0); + TXPREEMPHASIS0 : in std_logic_vector(2 downto 0); + TXPREEMPHASIS1 : in std_logic_vector(2 downto 0); + TXRESET0 : in std_ulogic; + TXRESET1 : in std_ulogic; + TXUSRCLK0 : in std_ulogic; + TXUSRCLK1 : in std_ulogic; + TXUSRCLK20 : in std_ulogic; + TXUSRCLK21 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GTP_DUAL : component is "PRIMITIVE"; + +----- component GT ----- +component GT + generic + ( + ALIGN_COMMA_MSB : boolean := FALSE; + CHAN_BOND_LIMIT : integer := 16; + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_OFFSET : integer := 8; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000"; + CHAN_BOND_SEQ_2_USE : boolean := FALSE; + CHAN_BOND_SEQ_LEN : integer := 1; + CHAN_BOND_WAIT : integer := 8; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + CLK_COR_SEQ_1_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_1_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_1 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_2 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_3 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_4 : bit_vector := "00000000000"; + CLK_COR_SEQ_2_USE : boolean := FALSE; + CLK_COR_SEQ_LEN : integer := 1; + CLK_CORRECT_USE : boolean := TRUE; + COMMA_10B_MASK : bit_vector := "1111111000"; + CRC_END_OF_PKT : string := "K29_7"; + CRC_FORMAT : string := "USER_MODE"; + CRC_START_OF_PKT : string := "K27_7"; + DEC_MCOMMA_DETECT : boolean := TRUE; + DEC_PCOMMA_DETECT : boolean := TRUE; + DEC_VALID_COMMA_ONLY : boolean := TRUE; + MCOMMA_10B_VALUE : bit_vector := "1100000000"; + MCOMMA_DETECT : boolean := TRUE; + PCOMMA_10B_VALUE : bit_vector := "0011111000"; + PCOMMA_DETECT : boolean := TRUE; + REF_CLK_V_SEL : integer := 0; + RX_BUFFER_USE : boolean := TRUE; + RX_CRC_USE : boolean := FALSE; + RX_DATA_WIDTH : integer := 2; + RX_DECODE_USE : boolean := TRUE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_BUFFER_USE : boolean := TRUE; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DATA_WIDTH : integer := 2; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT : component is "PRIMITIVE"; + +----- component GT_XAUI_1 ----- +component GT_XAUI_1 + generic + ( + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + CRC_END_OF_PKT : string := "K29_7"; + CRC_FORMAT : string := "USER_MODE"; + CRC_START_OF_PKT : string := "K27_7"; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(0 downto 0); + RXCHARISK : out std_logic_vector(0 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(7 downto 0); + RXDISPERR : out std_logic_vector(0 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(0 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(0 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(0 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(0 downto 0); + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(0 downto 0); + TXCHARDISPMODE : in std_logic_vector(0 downto 0); + TXCHARDISPVAL : in std_logic_vector(0 downto 0); + TXCHARISK : in std_logic_vector(0 downto 0); + TXDATA : in std_logic_vector(7 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT_XAUI_1 : component is "PRIMITIVE"; + +----- component GT_XAUI_2 ----- +component GT_XAUI_2 + generic + ( + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + CRC_END_OF_PKT : string := "K29_7"; + CRC_FORMAT : string := "USER_MODE"; + CRC_START_OF_PKT : string := "K27_7"; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(1 downto 0); + RXCHARISK : out std_logic_vector(1 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(15 downto 0); + RXDISPERR : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(1 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(1 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(1 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(1 downto 0); + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(1 downto 0); + TXCHARDISPMODE : in std_logic_vector(1 downto 0); + TXCHARDISPVAL : in std_logic_vector(1 downto 0); + TXCHARISK : in std_logic_vector(1 downto 0); + TXDATA : in std_logic_vector(15 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT_XAUI_2 : component is "PRIMITIVE"; + +----- component GT_XAUI_4 ----- +component GT_XAUI_4 + generic + ( + CHAN_BOND_MODE : string := "OFF"; + CHAN_BOND_ONE_SHOT : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; + CLK_COR_KEEP_IDLE : boolean := FALSE; + CLK_COR_REPEAT_WAIT : integer := 1; + CRC_END_OF_PKT : string := "K29_7"; + CRC_FORMAT : string := "USER_MODE"; + CRC_START_OF_PKT : string := "K27_7"; + REF_CLK_V_SEL : integer := 0; + RX_CRC_USE : boolean := FALSE; + RX_LOS_INVALID_INCR : integer := 1; + RX_LOS_THRESHOLD : integer := 4; + RX_LOSS_OF_SYNC_FSM : boolean := TRUE; + SERDES_10B : boolean := FALSE; + TERMINATION_IMP : integer := 50; + TX_CRC_FORCE_VALUE : bit_vector := "11010110"; + TX_CRC_USE : boolean := FALSE; + TX_DIFF_CTRL : integer := 500; + TX_PREEMPHASIS : integer := 0 + ); + port + ( + CHBONDDONE : out std_ulogic; + CHBONDO : out std_logic_vector(3 downto 0); + CONFIGOUT : out std_ulogic; + RXBUFSTATUS : out std_logic_vector(1 downto 0); + RXCHARISCOMMA : out std_logic_vector(3 downto 0); + RXCHARISK : out std_logic_vector(3 downto 0); + RXCHECKINGCRC : out std_ulogic; + RXCLKCORCNT : out std_logic_vector(2 downto 0); + RXCOMMADET : out std_ulogic; + RXCRCERR : out std_ulogic; + RXDATA : out std_logic_vector(31 downto 0); + RXDISPERR : out std_logic_vector(3 downto 0); + RXLOSSOFSYNC : out std_logic_vector(1 downto 0); + RXNOTINTABLE : out std_logic_vector(3 downto 0); + RXREALIGN : out std_ulogic; + RXRECCLK : out std_ulogic; + RXRUNDISP : out std_logic_vector(3 downto 0); + TXBUFERR : out std_ulogic; + TXKERR : out std_logic_vector(3 downto 0); + TXN : out std_ulogic; + TXP : out std_ulogic; + TXRUNDISP : out std_logic_vector(3 downto 0); + BREFCLK : in std_ulogic := 'X'; + BREFCLK2 : in std_ulogic := 'X'; + CHBONDI : in std_logic_vector(3 downto 0); + CONFIGENABLE : in std_ulogic; + CONFIGIN : in std_ulogic; + ENCHANSYNC : in std_ulogic; + ENMCOMMAALIGN : in std_ulogic; + ENPCOMMAALIGN : in std_ulogic; + LOOPBACK : in std_logic_vector(1 downto 0); + POWERDOWN : in std_ulogic; + REFCLK : in std_ulogic; + REFCLK2 : in std_ulogic; + REFCLKSEL : in std_ulogic; + RXN : in std_ulogic; + RXP : in std_ulogic; + RXPOLARITY : in std_ulogic; + RXRESET : in std_ulogic; + RXUSRCLK : in std_ulogic; + RXUSRCLK2 : in std_ulogic; + TXBYPASS8B10B : in std_logic_vector(3 downto 0); + TXCHARDISPMODE : in std_logic_vector(3 downto 0); + TXCHARDISPVAL : in std_logic_vector(3 downto 0); + TXCHARISK : in std_logic_vector(3 downto 0); + TXDATA : in std_logic_vector(31 downto 0); + TXFORCECRCERR : in std_ulogic; + TXINHIBIT : in std_ulogic; + TXPOLARITY : in std_ulogic; + TXRESET : in std_ulogic; + TXUSRCLK : in std_ulogic; + TXUSRCLK2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GT_XAUI_4 : component is "PRIMITIVE"; + +----- component GTX_DUAL ----- +component GTX_DUAL + generic + ( + AC_CAP_DIS_0 : boolean := TRUE; + AC_CAP_DIS_1 : boolean := TRUE; + ALIGN_COMMA_WORD_0 : integer := 1; + ALIGN_COMMA_WORD_1 : integer := 1; + CB2_INH_CC_PERIOD_0 : integer := 8; + CB2_INH_CC_PERIOD_1 : integer := 8; + CDR_PH_ADJ_TIME : bit_vector := "01010"; + CHAN_BOND_1_MAX_SKEW_0 : integer := 7; + CHAN_BOND_1_MAX_SKEW_1 : integer := 7; + CHAN_BOND_2_MAX_SKEW_0 : integer := 7; + CHAN_BOND_2_MAX_SKEW_1 : integer := 7; + CHAN_BOND_KEEP_ALIGN_0 : boolean := FALSE; + CHAN_BOND_KEEP_ALIGN_1 : boolean := FALSE; + CHAN_BOND_LEVEL_0 : integer := 0; + CHAN_BOND_LEVEL_1 : integer := 0; + CHAN_BOND_MODE_0 : string := "OFF"; + CHAN_BOND_MODE_1 : string := "OFF"; + CHAN_BOND_SEQ_1_1_0 : bit_vector := "0101111100"; + CHAN_BOND_SEQ_1_1_1 : bit_vector := "0101111100"; + CHAN_BOND_SEQ_1_2_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_2_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_3_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_3_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_4_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_4_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_ENABLE_0 : bit_vector := "0001"; + CHAN_BOND_SEQ_1_ENABLE_1 : bit_vector := "0001"; + CHAN_BOND_SEQ_2_1_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_1_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_2_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_2_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_3_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_3_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_4_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_4_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_ENABLE_0 : bit_vector := "0000"; + CHAN_BOND_SEQ_2_ENABLE_1 : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE_0 : boolean := FALSE; + CHAN_BOND_SEQ_2_USE_1 : boolean := FALSE; + CHAN_BOND_SEQ_LEN_0 : integer := 1; + CHAN_BOND_SEQ_LEN_1 : integer := 1; + CLK25_DIVIDER : integer := 10; + CLKINDC_B : boolean := TRUE; + CLKRCV_TRST : boolean := TRUE; + CLK_CORRECT_USE_0 : boolean := TRUE; + CLK_CORRECT_USE_1 : boolean := TRUE; + CLK_COR_ADJ_LEN_0 : integer := 1; + CLK_COR_ADJ_LEN_1 : integer := 1; + CLK_COR_DET_LEN_0 : integer := 1; + CLK_COR_DET_LEN_1 : integer := 1; + CLK_COR_INSERT_IDLE_FLAG_0 : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG_1 : boolean := FALSE; + CLK_COR_KEEP_IDLE_0 : boolean := FALSE; + CLK_COR_KEEP_IDLE_1 : boolean := FALSE; + CLK_COR_MAX_LAT_0 : integer := 20; + CLK_COR_MAX_LAT_1 : integer := 20; + CLK_COR_MIN_LAT_0 : integer := 18; + CLK_COR_MIN_LAT_1 : integer := 18; + CLK_COR_PRECEDENCE_0 : boolean := TRUE; + CLK_COR_PRECEDENCE_1 : boolean := TRUE; + CLK_COR_REPEAT_WAIT_0 : integer := 0; + CLK_COR_REPEAT_WAIT_1 : integer := 0; + CLK_COR_SEQ_1_1_0 : bit_vector := "0100011100"; + CLK_COR_SEQ_1_1_1 : bit_vector := "0100011100"; + CLK_COR_SEQ_1_2_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_2_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_3_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_3_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_4_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_4_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_ENABLE_0 : bit_vector := "0001"; + CLK_COR_SEQ_1_ENABLE_1 : bit_vector := "0001"; + CLK_COR_SEQ_2_1_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_1_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_2_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_2_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_3_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_3_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_4_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_4_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_ENABLE_0 : bit_vector := "0000"; + CLK_COR_SEQ_2_ENABLE_1 : bit_vector := "0000"; + CLK_COR_SEQ_2_USE_0 : boolean := FALSE; + CLK_COR_SEQ_2_USE_1 : boolean := FALSE; + CM_TRIM_0 : bit_vector := "10"; + CM_TRIM_1 : bit_vector := "10"; + COMMA_10B_ENABLE_0 : bit_vector := "0001111111"; + COMMA_10B_ENABLE_1 : bit_vector := "0001111111"; + COMMA_DOUBLE_0 : boolean := FALSE; + COMMA_DOUBLE_1 : boolean := FALSE; + COM_BURST_VAL_0 : bit_vector := "1111"; + COM_BURST_VAL_1 : bit_vector := "1111"; + DEC_MCOMMA_DETECT_0 : boolean := TRUE; + DEC_MCOMMA_DETECT_1 : boolean := TRUE; + DEC_PCOMMA_DETECT_0 : boolean := TRUE; + DEC_PCOMMA_DETECT_1 : boolean := TRUE; + DEC_VALID_COMMA_ONLY_0 : boolean := TRUE; + DEC_VALID_COMMA_ONLY_1 : boolean := TRUE; + DFE_CAL_TIME : bit_vector := "00110"; + DFE_CFG_0 : bit_vector := "1101111011"; + DFE_CFG_1 : bit_vector := "1101111011"; + GEARBOX_ENDEC_0 : bit_vector := "000"; + GEARBOX_ENDEC_1 : bit_vector := "000"; + MCOMMA_10B_VALUE_0 : bit_vector := "1010000011"; + MCOMMA_10B_VALUE_1 : bit_vector := "1010000011"; + MCOMMA_DETECT_0 : boolean := TRUE; + MCOMMA_DETECT_1 : boolean := TRUE; + OOBDETECT_THRESHOLD_0 : bit_vector := "110"; + OOBDETECT_THRESHOLD_1 : bit_vector := "110"; + OOB_CLK_DIVIDER : integer := 6; + OVERSAMPLE_MODE : boolean := FALSE; + PCI_EXPRESS_MODE_0 : boolean := FALSE; + PCI_EXPRESS_MODE_1 : boolean := FALSE; + PCOMMA_10B_VALUE_0 : bit_vector := "0101111100"; + PCOMMA_10B_VALUE_1 : bit_vector := "0101111100"; + PCOMMA_DETECT_0 : boolean := TRUE; + PCOMMA_DETECT_1 : boolean := TRUE; + PLL_COM_CFG : bit_vector := X"21680a"; + PLL_CP_CFG : bit_vector := X"00"; + PLL_DIVSEL_FB : integer := 2; + PLL_DIVSEL_REF : integer := 1; + PLL_FB_DCCEN : boolean := FALSE; + PLL_LKDET_CFG : bit_vector := "101"; + PLL_RXDIVSEL_OUT_0 : integer := 1; + PLL_RXDIVSEL_OUT_1 : integer := 1; + PLL_SATA_0 : boolean := FALSE; + PLL_SATA_1 : boolean := FALSE; + PLL_TDCC_CFG : bit_vector := "000"; + PLL_TXDIVSEL_OUT_0 : integer := 1; + PLL_TXDIVSEL_OUT_1 : integer := 1; + PMA_CDR_SCAN_0 : bit_vector := X"6404035"; + PMA_CDR_SCAN_1 : bit_vector := X"6404035"; + PMA_COM_CFG : bit_vector := X"000000000000000000"; + PMA_RXSYNC_CFG_0 : bit_vector := X"00"; + PMA_RXSYNC_CFG_1 : bit_vector := X"00"; + PMA_RX_CFG_0 : bit_vector := X"0f44089"; + PMA_RX_CFG_1 : bit_vector := X"0f44089"; + PMA_TX_CFG_0 : bit_vector := X"80082"; + PMA_TX_CFG_1 : bit_vector := X"80082"; + PRBS_ERR_THRESHOLD_0 : bit_vector := X"00000001"; + PRBS_ERR_THRESHOLD_1 : bit_vector := X"00000001"; + RCV_TERM_GND_0 : boolean := FALSE; + RCV_TERM_GND_1 : boolean := FALSE; + RCV_TERM_VTTRX_0 : boolean := FALSE; + RCV_TERM_VTTRX_1 : boolean := FALSE; + RXGEARBOX_USE_0 : boolean := FALSE; + RXGEARBOX_USE_1 : boolean := FALSE; + RX_BUFFER_USE_0 : boolean := TRUE; + RX_BUFFER_USE_1 : boolean := TRUE; + RX_DECODE_SEQ_MATCH_0 : boolean := TRUE; + RX_DECODE_SEQ_MATCH_1 : boolean := TRUE; + RX_EN_IDLE_HOLD_CDR : boolean := FALSE; + RX_EN_IDLE_HOLD_DFE_0 : boolean := TRUE; + RX_EN_IDLE_HOLD_DFE_1 : boolean := TRUE; + RX_EN_IDLE_RESET_BUF_0 : boolean := TRUE; + RX_EN_IDLE_RESET_BUF_1 : boolean := TRUE; + RX_EN_IDLE_RESET_FR : boolean := TRUE; + RX_EN_IDLE_RESET_PH : boolean := TRUE; + RX_IDLE_HI_CNT_0 : bit_vector := "1000"; + RX_IDLE_HI_CNT_1 : bit_vector := "1000"; + RX_IDLE_LO_CNT_0 : bit_vector := "0000"; + RX_IDLE_LO_CNT_1 : bit_vector := "0000"; + RX_LOSS_OF_SYNC_FSM_0 : boolean := FALSE; + RX_LOSS_OF_SYNC_FSM_1 : boolean := FALSE; + RX_LOS_INVALID_INCR_0 : integer := 1; + RX_LOS_INVALID_INCR_1 : integer := 1; + RX_LOS_THRESHOLD_0 : integer := 4; + RX_LOS_THRESHOLD_1 : integer := 4; + RX_SLIDE_MODE_0 : string := "PCS"; + RX_SLIDE_MODE_1 : string := "PCS"; + RX_STATUS_FMT_0 : string := "PCIE"; + RX_STATUS_FMT_1 : string := "PCIE"; + RX_XCLK_SEL_0 : string := "RXREC"; + RX_XCLK_SEL_1 : string := "RXREC"; + SATA_BURST_VAL_0 : bit_vector := "100"; + SATA_BURST_VAL_1 : bit_vector := "100"; + SATA_IDLE_VAL_0 : bit_vector := "100"; + SATA_IDLE_VAL_1 : bit_vector := "100"; + SATA_MAX_BURST_0 : integer := 7; + SATA_MAX_BURST_1 : integer := 7; + SATA_MAX_INIT_0 : integer := 22; + SATA_MAX_INIT_1 : integer := 22; + SATA_MAX_WAKE_0 : integer := 7; + SATA_MAX_WAKE_1 : integer := 7; + SATA_MIN_BURST_0 : integer := 4; + SATA_MIN_BURST_1 : integer := 4; + SATA_MIN_INIT_0 : integer := 12; + SATA_MIN_INIT_1 : integer := 12; + SATA_MIN_WAKE_0 : integer := 4; + SATA_MIN_WAKE_1 : integer := 4; + SIM_GTXRESET_SPEEDUP : integer := 1; + SIM_MODE : string := "FAST"; + SIM_PLL_PERDIV2 : bit_vector := X"140"; + SIM_RECEIVER_DETECT_PASS_0 : boolean := TRUE; + SIM_RECEIVER_DETECT_PASS_1 : boolean := TRUE; + TERMINATION_CTRL : bit_vector := "10100"; + TERMINATION_IMP_0 : integer := 50; + TERMINATION_IMP_1 : integer := 50; + TERMINATION_OVRD : boolean := FALSE; + TRANS_TIME_FROM_P2_0 : bit_vector := X"03c"; + TRANS_TIME_FROM_P2_1 : bit_vector := X"03c"; + TRANS_TIME_NON_P2_0 : bit_vector := X"19"; + TRANS_TIME_NON_P2_1 : bit_vector := X"19"; + TRANS_TIME_TO_P2_0 : bit_vector := X"064"; + TRANS_TIME_TO_P2_1 : bit_vector := X"064"; + TXGEARBOX_USE_0 : boolean := FALSE; + TXGEARBOX_USE_1 : boolean := FALSE; + TXRX_INVERT_0 : bit_vector := "011"; + TXRX_INVERT_1 : bit_vector := "011"; + TX_BUFFER_USE_0 : boolean := TRUE; + TX_BUFFER_USE_1 : boolean := TRUE; + TX_DETECT_RX_CFG_0 : bit_vector := X"1832"; + TX_DETECT_RX_CFG_1 : bit_vector := X"1832"; + TX_IDLE_DELAY_0 : bit_vector := "010"; + TX_IDLE_DELAY_1 : bit_vector := "010"; + TX_XCLK_SEL_0 : string := "TXOUT"; + TX_XCLK_SEL_1 : string := "TXOUT" + ); + port + ( + DFECLKDLYADJMONITOR0 : out std_logic_vector(5 downto 0); + DFECLKDLYADJMONITOR1 : out std_logic_vector(5 downto 0); + DFEEYEDACMONITOR0 : out std_logic_vector(4 downto 0); + DFEEYEDACMONITOR1 : out std_logic_vector(4 downto 0); + DFESENSCAL0 : out std_logic_vector(2 downto 0); + DFESENSCAL1 : out std_logic_vector(2 downto 0); + DFETAP1MONITOR0 : out std_logic_vector(4 downto 0); + DFETAP1MONITOR1 : out std_logic_vector(4 downto 0); + DFETAP2MONITOR0 : out std_logic_vector(4 downto 0); + DFETAP2MONITOR1 : out std_logic_vector(4 downto 0); + DFETAP3MONITOR0 : out std_logic_vector(3 downto 0); + DFETAP3MONITOR1 : out std_logic_vector(3 downto 0); + DFETAP4MONITOR0 : out std_logic_vector(3 downto 0); + DFETAP4MONITOR1 : out std_logic_vector(3 downto 0); + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + PHYSTATUS0 : out std_ulogic; + PHYSTATUS1 : out std_ulogic; + PLLLKDET : out std_ulogic; + REFCLKOUT : out std_ulogic; + RESETDONE0 : out std_ulogic; + RESETDONE1 : out std_ulogic; + RXBUFSTATUS0 : out std_logic_vector(2 downto 0); + RXBUFSTATUS1 : out std_logic_vector(2 downto 0); + RXBYTEISALIGNED0 : out std_ulogic; + RXBYTEISALIGNED1 : out std_ulogic; + RXBYTEREALIGN0 : out std_ulogic; + RXBYTEREALIGN1 : out std_ulogic; + RXCHANBONDSEQ0 : out std_ulogic; + RXCHANBONDSEQ1 : out std_ulogic; + RXCHANISALIGNED0 : out std_ulogic; + RXCHANISALIGNED1 : out std_ulogic; + RXCHANREALIGN0 : out std_ulogic; + RXCHANREALIGN1 : out std_ulogic; + RXCHARISCOMMA0 : out std_logic_vector(3 downto 0); + RXCHARISCOMMA1 : out std_logic_vector(3 downto 0); + RXCHARISK0 : out std_logic_vector(3 downto 0); + RXCHARISK1 : out std_logic_vector(3 downto 0); + RXCHBONDO0 : out std_logic_vector(3 downto 0); + RXCHBONDO1 : out std_logic_vector(3 downto 0); + RXCLKCORCNT0 : out std_logic_vector(2 downto 0); + RXCLKCORCNT1 : out std_logic_vector(2 downto 0); + RXCOMMADET0 : out std_ulogic; + RXCOMMADET1 : out std_ulogic; + RXDATA0 : out std_logic_vector(31 downto 0); + RXDATA1 : out std_logic_vector(31 downto 0); + RXDATAVALID0 : out std_ulogic; + RXDATAVALID1 : out std_ulogic; + RXDISPERR0 : out std_logic_vector(3 downto 0); + RXDISPERR1 : out std_logic_vector(3 downto 0); + RXELECIDLE0 : out std_ulogic; + RXELECIDLE1 : out std_ulogic; + RXHEADER0 : out std_logic_vector(2 downto 0); + RXHEADER1 : out std_logic_vector(2 downto 0); + RXHEADERVALID0 : out std_ulogic; + RXHEADERVALID1 : out std_ulogic; + RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); + RXNOTINTABLE0 : out std_logic_vector(3 downto 0); + RXNOTINTABLE1 : out std_logic_vector(3 downto 0); + RXOVERSAMPLEERR0 : out std_ulogic; + RXOVERSAMPLEERR1 : out std_ulogic; + RXPRBSERR0 : out std_ulogic; + RXPRBSERR1 : out std_ulogic; + RXRECCLK0 : out std_ulogic; + RXRECCLK1 : out std_ulogic; + RXRUNDISP0 : out std_logic_vector(3 downto 0); + RXRUNDISP1 : out std_logic_vector(3 downto 0); + RXSTARTOFSEQ0 : out std_ulogic; + RXSTARTOFSEQ1 : out std_ulogic; + RXSTATUS0 : out std_logic_vector(2 downto 0); + RXSTATUS1 : out std_logic_vector(2 downto 0); + RXVALID0 : out std_ulogic; + RXVALID1 : out std_ulogic; + TXBUFSTATUS0 : out std_logic_vector(1 downto 0); + TXBUFSTATUS1 : out std_logic_vector(1 downto 0); + TXGEARBOXREADY0 : out std_ulogic; + TXGEARBOXREADY1 : out std_ulogic; + TXKERR0 : out std_logic_vector(3 downto 0); + TXKERR1 : out std_logic_vector(3 downto 0); + TXN0 : out std_ulogic; + TXN1 : out std_ulogic; + TXOUTCLK0 : out std_ulogic; + TXOUTCLK1 : out std_ulogic; + TXP0 : out std_ulogic; + TXP1 : out std_ulogic; + TXRUNDISP0 : out std_logic_vector(3 downto 0); + TXRUNDISP1 : out std_logic_vector(3 downto 0); + CLKIN : in std_ulogic; + DADDR : in std_logic_vector(6 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DFECLKDLYADJ0 : in std_logic_vector(5 downto 0); + DFECLKDLYADJ1 : in std_logic_vector(5 downto 0); + DFETAP10 : in std_logic_vector(4 downto 0); + DFETAP11 : in std_logic_vector(4 downto 0); + DFETAP20 : in std_logic_vector(4 downto 0); + DFETAP21 : in std_logic_vector(4 downto 0); + DFETAP30 : in std_logic_vector(3 downto 0); + DFETAP31 : in std_logic_vector(3 downto 0); + DFETAP40 : in std_logic_vector(3 downto 0); + DFETAP41 : in std_logic_vector(3 downto 0); + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + GTXRESET : in std_ulogic; + GTXTEST : in std_logic_vector(13 downto 0); + INTDATAWIDTH : in std_ulogic; + LOOPBACK0 : in std_logic_vector(2 downto 0); + LOOPBACK1 : in std_logic_vector(2 downto 0); + PLLLKDETEN : in std_ulogic; + PLLPOWERDOWN : in std_ulogic; + PRBSCNTRESET0 : in std_ulogic; + PRBSCNTRESET1 : in std_ulogic; + REFCLKPWRDNB : in std_ulogic; + RXBUFRESET0 : in std_ulogic; + RXBUFRESET1 : in std_ulogic; + RXCDRRESET0 : in std_ulogic; + RXCDRRESET1 : in std_ulogic; + RXCHBONDI0 : in std_logic_vector(3 downto 0); + RXCHBONDI1 : in std_logic_vector(3 downto 0); + RXCOMMADETUSE0 : in std_ulogic; + RXCOMMADETUSE1 : in std_ulogic; + RXDATAWIDTH0 : in std_logic_vector(1 downto 0); + RXDATAWIDTH1 : in std_logic_vector(1 downto 0); + RXDEC8B10BUSE0 : in std_ulogic; + RXDEC8B10BUSE1 : in std_ulogic; + RXENCHANSYNC0 : in std_ulogic; + RXENCHANSYNC1 : in std_ulogic; + RXENEQB0 : in std_ulogic; + RXENEQB1 : in std_ulogic; + RXENMCOMMAALIGN0 : in std_ulogic; + RXENMCOMMAALIGN1 : in std_ulogic; + RXENPCOMMAALIGN0 : in std_ulogic; + RXENPCOMMAALIGN1 : in std_ulogic; + RXENPMAPHASEALIGN0 : in std_ulogic; + RXENPMAPHASEALIGN1 : in std_ulogic; + RXENPRBSTST0 : in std_logic_vector(1 downto 0); + RXENPRBSTST1 : in std_logic_vector(1 downto 0); + RXENSAMPLEALIGN0 : in std_ulogic; + RXENSAMPLEALIGN1 : in std_ulogic; + RXEQMIX0 : in std_logic_vector(1 downto 0); + RXEQMIX1 : in std_logic_vector(1 downto 0); + RXEQPOLE0 : in std_logic_vector(3 downto 0); + RXEQPOLE1 : in std_logic_vector(3 downto 0); + RXGEARBOXSLIP0 : in std_ulogic; + RXGEARBOXSLIP1 : in std_ulogic; + RXN0 : in std_ulogic; + RXN1 : in std_ulogic; + RXP0 : in std_ulogic; + RXP1 : in std_ulogic; + RXPMASETPHASE0 : in std_ulogic; + RXPMASETPHASE1 : in std_ulogic; + RXPOLARITY0 : in std_ulogic; + RXPOLARITY1 : in std_ulogic; + RXPOWERDOWN0 : in std_logic_vector(1 downto 0); + RXPOWERDOWN1 : in std_logic_vector(1 downto 0); + RXRESET0 : in std_ulogic; + RXRESET1 : in std_ulogic; + RXSLIDE0 : in std_ulogic; + RXSLIDE1 : in std_ulogic; + RXUSRCLK0 : in std_ulogic; + RXUSRCLK1 : in std_ulogic; + RXUSRCLK20 : in std_ulogic; + RXUSRCLK21 : in std_ulogic; + TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXBYPASS8B10B0 : in std_logic_vector(3 downto 0); + TXBYPASS8B10B1 : in std_logic_vector(3 downto 0); + TXCHARDISPMODE0 : in std_logic_vector(3 downto 0); + TXCHARDISPMODE1 : in std_logic_vector(3 downto 0); + TXCHARDISPVAL0 : in std_logic_vector(3 downto 0); + TXCHARDISPVAL1 : in std_logic_vector(3 downto 0); + TXCHARISK0 : in std_logic_vector(3 downto 0); + TXCHARISK1 : in std_logic_vector(3 downto 0); + TXCOMSTART0 : in std_ulogic; + TXCOMSTART1 : in std_ulogic; + TXCOMTYPE0 : in std_ulogic; + TXCOMTYPE1 : in std_ulogic; + TXDATA0 : in std_logic_vector(31 downto 0); + TXDATA1 : in std_logic_vector(31 downto 0); + TXDATAWIDTH0 : in std_logic_vector(1 downto 0); + TXDATAWIDTH1 : in std_logic_vector(1 downto 0); + TXDETECTRX0 : in std_ulogic; + TXDETECTRX1 : in std_ulogic; + TXDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXELECIDLE0 : in std_ulogic; + TXELECIDLE1 : in std_ulogic; + TXENC8B10BUSE0 : in std_ulogic; + TXENC8B10BUSE1 : in std_ulogic; + TXENPMAPHASEALIGN0 : in std_ulogic; + TXENPMAPHASEALIGN1 : in std_ulogic; + TXENPRBSTST0 : in std_logic_vector(1 downto 0); + TXENPRBSTST1 : in std_logic_vector(1 downto 0); + TXHEADER0 : in std_logic_vector(2 downto 0); + TXHEADER1 : in std_logic_vector(2 downto 0); + TXINHIBIT0 : in std_ulogic; + TXINHIBIT1 : in std_ulogic; + TXPMASETPHASE0 : in std_ulogic; + TXPMASETPHASE1 : in std_ulogic; + TXPOLARITY0 : in std_ulogic; + TXPOLARITY1 : in std_ulogic; + TXPOWERDOWN0 : in std_logic_vector(1 downto 0); + TXPOWERDOWN1 : in std_logic_vector(1 downto 0); + TXPREEMPHASIS0 : in std_logic_vector(3 downto 0); + TXPREEMPHASIS1 : in std_logic_vector(3 downto 0); + TXRESET0 : in std_ulogic; + TXRESET1 : in std_ulogic; + TXSEQUENCE0 : in std_logic_vector(6 downto 0); + TXSEQUENCE1 : in std_logic_vector(6 downto 0); + TXSTARTSEQ0 : in std_ulogic; + TXSTARTSEQ1 : in std_ulogic; + TXUSRCLK0 : in std_ulogic; + TXUSRCLK1 : in std_ulogic; + TXUSRCLK20 : in std_ulogic; + TXUSRCLK21 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + GTX_DUAL : component is "PRIMITIVE"; + +----- component IBUF_AGP ----- +component IBUF_AGP + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_AGP : component is "PRIMITIVE"; + +----- component IBUF_CTT ----- +component IBUF_CTT + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_CTT : component is "PRIMITIVE"; + +----- component IBUF_DLY_ADJ ----- +component IBUF_DLY_ADJ + generic + ( + DELAY_OFFSET : string := "OFF"; + IOSTANDARD : string := "DEFAULT" + ); + port + ( + O : out std_ulogic; + I : in std_ulogic; + S : in std_logic_vector (2 downto 0) + ); +end component; +attribute BOX_TYPE of + IBUF_DLY_ADJ : component is "PRIMITIVE"; + +----- component IBUFDS_BLVDS_25 ----- +component IBUFDS_BLVDS_25 + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFDS_BLVDS_25 : component is "PRIMITIVE"; + +----- component IBUFDS_DIFF_OUT ----- +component IBUFDS_DIFF_OUT + generic + ( + IOSTANDARD : string := "LVDS_25" + ); + port + ( + O : out STD_ULOGIC; + OB : out STD_ULOGIC; + I : in STD_ULOGIC; + IB : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + IBUFDS_DIFF_OUT : component is "PRIMITIVE"; + +----- component IBUFDS_DLY_ADJ ----- +component IBUFDS_DLY_ADJ + generic + ( + DELAY_OFFSET : string := "OFF"; + DIFF_TERM : boolean := FALSE; + IOSTANDARD : string := "DEFAULT" + ); + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic; + S : in std_logic_vector (2 downto 0) + ); +end component; +attribute BOX_TYPE of + IBUFDS_DLY_ADJ : component is "PRIMITIVE"; + +----- component IBUFDS_LDT_25 ----- +component IBUFDS_LDT_25 + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFDS_LDT_25 : component is "PRIMITIVE"; + +----- component IBUFDS_LVDS_25_DCI ----- +component IBUFDS_LVDS_25_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFDS_LVDS_25_DCI : component is "PRIMITIVE"; + +----- component IBUFDS_LVDS_25 ----- +component IBUFDS_LVDS_25 + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFDS_LVDS_25 : component is "PRIMITIVE"; + +----- component IBUFDS_LVDS_33_DCI ----- +component IBUFDS_LVDS_33_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFDS_LVDS_33_DCI : component is "PRIMITIVE"; + +----- component IBUFDS_LVDS_33 ----- +component IBUFDS_LVDS_33 + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFDS_LVDS_33 : component is "PRIMITIVE"; + +----- component IBUFDS_LVDSEXT_25_DCI ----- +component IBUFDS_LVDSEXT_25_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFDS_LVDSEXT_25_DCI : component is "PRIMITIVE"; + +----- component IBUFDS_LVDSEXT_25 ----- +component IBUFDS_LVDSEXT_25 + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFDS_LVDSEXT_25 : component is "PRIMITIVE"; + +----- component IBUFDS_LVDSEXT_33_DCI ----- +component IBUFDS_LVDSEXT_33_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFDS_LVDSEXT_33_DCI : component is "PRIMITIVE"; + +----- component IBUFDS_LVDSEXT_33 ----- +component IBUFDS_LVDSEXT_33 + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFDS_LVDSEXT_33 : component is "PRIMITIVE"; + +----- component IBUFDS_LVPECL_25 ----- +component IBUFDS_LVPECL_25 + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFDS_LVPECL_25 : component is "PRIMITIVE"; + +----- component IBUFDS_LVPECL_33 ----- +component IBUFDS_LVPECL_33 + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFDS_LVPECL_33 : component is "PRIMITIVE"; + +----- component IBUFDS_ULVDS_25 ----- +component IBUFDS_ULVDS_25 + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFDS_ULVDS_25 : component is "PRIMITIVE"; + +----- component IBUFDS ----- +component IBUFDS + generic + ( + CAPACITANCE : string := "DONT_CARE"; + DIFF_TERM : boolean := FALSE; + IBUF_DELAY_VALUE : string := "0"; + IFD_DELAY_VALUE : string := "AUTO"; + IOSTANDARD : string := "DEFAULT" + ); + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFDS : component is "PRIMITIVE"; + +----- component IBUFG_AGP ----- +component IBUFG_AGP + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_AGP : component is "PRIMITIVE"; + +----- component IBUFG_CTT ----- +component IBUFG_CTT + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_CTT : component is "PRIMITIVE"; + +----- component IBUFGDS_BLVDS_25 ----- +component IBUFGDS_BLVDS_25 + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFGDS_BLVDS_25 : component is "PRIMITIVE"; + +----- component IBUFGDS_DIFF_OUT ----- +component IBUFGDS_DIFF_OUT + generic + ( + IOSTANDARD : string := "LVDS_25" + ); + port + ( + O : out STD_ULOGIC; + OB : out STD_ULOGIC; + I : in STD_ULOGIC; + IB : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + IBUFGDS_DIFF_OUT : component is "PRIMITIVE"; + +----- component IBUFGDS_LDT_25 ----- +component IBUFGDS_LDT_25 + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFGDS_LDT_25 : component is "PRIMITIVE"; + +----- component IBUFGDS_LVDS_25_DCI ----- +component IBUFGDS_LVDS_25_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFGDS_LVDS_25_DCI : component is "PRIMITIVE"; + +----- component IBUFGDS_LVDS_25 ----- +component IBUFGDS_LVDS_25 + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFGDS_LVDS_25 : component is "PRIMITIVE"; + +----- component IBUFGDS_LVDS_33_DCI ----- +component IBUFGDS_LVDS_33_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFGDS_LVDS_33_DCI : component is "PRIMITIVE"; + +----- component IBUFGDS_LVDS_33 ----- +component IBUFGDS_LVDS_33 + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFGDS_LVDS_33 : component is "PRIMITIVE"; + +----- component IBUFGDS_LVDSEXT_25_DCI ----- +component IBUFGDS_LVDSEXT_25_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFGDS_LVDSEXT_25_DCI : component is "PRIMITIVE"; + +----- component IBUFGDS_LVDSEXT_25 ----- +component IBUFGDS_LVDSEXT_25 + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFGDS_LVDSEXT_25 : component is "PRIMITIVE"; + +----- component IBUFGDS_LVDSEXT_33_DCI ----- +component IBUFGDS_LVDSEXT_33_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFGDS_LVDSEXT_33_DCI : component is "PRIMITIVE"; + +----- component IBUFGDS_LVDSEXT_33 ----- +component IBUFGDS_LVDSEXT_33 + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFGDS_LVDSEXT_33 : component is "PRIMITIVE"; + +----- component IBUFGDS_LVPECL_25 ----- +component IBUFGDS_LVPECL_25 + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFGDS_LVPECL_25 : component is "PRIMITIVE"; + +----- component IBUFGDS_LVPECL_33 ----- +component IBUFGDS_LVPECL_33 + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFGDS_LVPECL_33 : component is "PRIMITIVE"; + +----- component IBUFGDS_ULVDS_25 ----- +component IBUFGDS_ULVDS_25 + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFGDS_ULVDS_25 : component is "PRIMITIVE"; + +----- component IBUFGDS ----- +component IBUFGDS + generic + ( + CAPACITANCE : string := "DONT_CARE"; + DIFF_TERM : boolean := FALSE; + IBUF_DELAY_VALUE : string := "0"; + IOSTANDARD : string := "DEFAULT" + ); + port + ( + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFGDS : component is "PRIMITIVE"; + +----- component IBUFG_GTL_DCI ----- +component IBUFG_GTL_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_GTL_DCI : component is "PRIMITIVE"; + +----- component IBUFG_GTLP_DCI ----- +component IBUFG_GTLP_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_GTLP_DCI : component is "PRIMITIVE"; + +----- component IBUFG_GTLP ----- +component IBUFG_GTLP + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_GTLP : component is "PRIMITIVE"; + +----- component IBUFG_GTL ----- +component IBUFG_GTL + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_GTL : component is "PRIMITIVE"; + +----- component IBUFG_HSTL_I_18 ----- +component IBUFG_HSTL_I_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_HSTL_I_18 : component is "PRIMITIVE"; + +----- component IBUFG_HSTL_I_DCI_18 ----- +component IBUFG_HSTL_I_DCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_HSTL_I_DCI_18 : component is "PRIMITIVE"; + +----- component IBUFG_HSTL_I_DCI ----- +component IBUFG_HSTL_I_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_HSTL_I_DCI : component is "PRIMITIVE"; + +----- component IBUFG_HSTL_II_18 ----- +component IBUFG_HSTL_II_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_HSTL_II_18 : component is "PRIMITIVE"; + +----- component IBUFG_HSTL_II_DCI_18 ----- +component IBUFG_HSTL_II_DCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_HSTL_II_DCI_18 : component is "PRIMITIVE"; + +----- component IBUFG_HSTL_II_DCI ----- +component IBUFG_HSTL_II_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_HSTL_II_DCI : component is "PRIMITIVE"; + +----- component IBUFG_HSTL_III_18 ----- +component IBUFG_HSTL_III_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_HSTL_III_18 : component is "PRIMITIVE"; + +----- component IBUFG_HSTL_III_DCI_18 ----- +component IBUFG_HSTL_III_DCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_HSTL_III_DCI_18 : component is "PRIMITIVE"; + +----- component IBUFG_HSTL_III_DCI ----- +component IBUFG_HSTL_III_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_HSTL_III_DCI : component is "PRIMITIVE"; + +----- component IBUFG_HSTL_III ----- +component IBUFG_HSTL_III + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_HSTL_III : component is "PRIMITIVE"; + +----- component IBUFG_HSTL_II ----- +component IBUFG_HSTL_II + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_HSTL_II : component is "PRIMITIVE"; + +----- component IBUFG_HSTL_IV_18 ----- +component IBUFG_HSTL_IV_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_HSTL_IV_18 : component is "PRIMITIVE"; + +----- component IBUFG_HSTL_IV_DCI_18 ----- +component IBUFG_HSTL_IV_DCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_HSTL_IV_DCI_18 : component is "PRIMITIVE"; + +----- component IBUFG_HSTL_IV_DCI ----- +component IBUFG_HSTL_IV_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_HSTL_IV_DCI : component is "PRIMITIVE"; + +----- component IBUFG_HSTL_I ----- +component IBUFG_HSTL_I + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_HSTL_I : component is "PRIMITIVE"; + +----- component IBUFG_HSTL_IV ----- +component IBUFG_HSTL_IV + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_HSTL_IV : component is "PRIMITIVE"; + +----- component IBUFG_LVCMOS12 ----- +component IBUFG_LVCMOS12 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_LVCMOS12 : component is "PRIMITIVE"; + +----- component IBUFG_LVCMOS15 ----- +component IBUFG_LVCMOS15 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_LVCMOS15 : component is "PRIMITIVE"; + +----- component IBUFG_LVCMOS18 ----- +component IBUFG_LVCMOS18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_LVCMOS18 : component is "PRIMITIVE"; + +----- component IBUFG_LVCMOS25 ----- +component IBUFG_LVCMOS25 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_LVCMOS25 : component is "PRIMITIVE"; + +----- component IBUFG_LVCMOS2 ----- +component IBUFG_LVCMOS2 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_LVCMOS2 : component is "PRIMITIVE"; + +----- component IBUFG_LVCMOS33 ----- +component IBUFG_LVCMOS33 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_LVCMOS33 : component is "PRIMITIVE"; + +----- component IBUFG_LVDCI_15 ----- +component IBUFG_LVDCI_15 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_LVDCI_15 : component is "PRIMITIVE"; + +----- component IBUFG_LVDCI_18 ----- +component IBUFG_LVDCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_LVDCI_18 : component is "PRIMITIVE"; + +----- component IBUFG_LVDCI_25 ----- +component IBUFG_LVDCI_25 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_LVDCI_25 : component is "PRIMITIVE"; + +----- component IBUFG_LVDCI_33 ----- +component IBUFG_LVDCI_33 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_LVDCI_33 : component is "PRIMITIVE"; + +----- component IBUFG_LVDCI_DV2_15 ----- +component IBUFG_LVDCI_DV2_15 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_LVDCI_DV2_15 : component is "PRIMITIVE"; + +----- component IBUFG_LVDCI_DV2_18 ----- +component IBUFG_LVDCI_DV2_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_LVDCI_DV2_18 : component is "PRIMITIVE"; + +----- component IBUFG_LVDCI_DV2_25 ----- +component IBUFG_LVDCI_DV2_25 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_LVDCI_DV2_25 : component is "PRIMITIVE"; + +----- component IBUFG_LVDCI_DV2_33 ----- +component IBUFG_LVDCI_DV2_33 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_LVDCI_DV2_33 : component is "PRIMITIVE"; + +----- component IBUFG_LVDS ----- +component IBUFG_LVDS + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_LVDS : component is "PRIMITIVE"; + +----- component IBUFG_LVPECL ----- +component IBUFG_LVPECL + port + ( + O : out STD_ULOGIC; + I : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + IBUFG_LVPECL : component is "PRIMITIVE"; + +----- component IBUFG_LVTTL ----- +component IBUFG_LVTTL + port + ( + O : out STD_ULOGIC; + I : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + IBUFG_LVTTL : component is "PRIMITIVE"; + +----- component IBUFG_PCI33_3 ----- +component IBUFG_PCI33_3 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_PCI33_3 : component is "PRIMITIVE"; + +----- component IBUFG_PCI33_5 ----- +component IBUFG_PCI33_5 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_PCI33_5 : component is "PRIMITIVE"; + +----- component IBUFG_PCI66_3 ----- +component IBUFG_PCI66_3 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_PCI66_3 : component is "PRIMITIVE"; + +----- component IBUFG_PCIX66_3 ----- +component IBUFG_PCIX66_3 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_PCIX66_3 : component is "PRIMITIVE"; + +----- component IBUFG_PCIX ----- +component IBUFG_PCIX + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_PCIX : component is "PRIMITIVE"; + +----- component IBUFG_SSTL18_I_DCI ----- +component IBUFG_SSTL18_I_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_SSTL18_I_DCI : component is "PRIMITIVE"; + +----- component IBUFG_SSTL18_II_DCI ----- +component IBUFG_SSTL18_II_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_SSTL18_II_DCI : component is "PRIMITIVE"; + +----- component IBUFG_SSTL18_II ----- +component IBUFG_SSTL18_II + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_SSTL18_II : component is "PRIMITIVE"; + +----- component IBUFG_SSTL18_I ----- +component IBUFG_SSTL18_I + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_SSTL18_I : component is "PRIMITIVE"; + +----- component IBUFG_SSTL2_I_DCI ----- +component IBUFG_SSTL2_I_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_SSTL2_I_DCI : component is "PRIMITIVE"; + +----- component IBUFG_SSTL2_II_DCI ----- +component IBUFG_SSTL2_II_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_SSTL2_II_DCI : component is "PRIMITIVE"; + +----- component IBUFG_SSTL2_II ----- +component IBUFG_SSTL2_II + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_SSTL2_II : component is "PRIMITIVE"; + +----- component IBUFG_SSTL2_I ----- +component IBUFG_SSTL2_I + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_SSTL2_I : component is "PRIMITIVE"; + +----- component IBUFG_SSTL3_I_DCI ----- +component IBUFG_SSTL3_I_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_SSTL3_I_DCI : component is "PRIMITIVE"; + +----- component IBUFG_SSTL3_II_DCI ----- +component IBUFG_SSTL3_II_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_SSTL3_II_DCI : component is "PRIMITIVE"; + +----- component IBUFG_SSTL3_II ----- +component IBUFG_SSTL3_II + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_SSTL3_II : component is "PRIMITIVE"; + +----- component IBUFG_SSTL3_I ----- +component IBUFG_SSTL3_I + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG_SSTL3_I : component is "PRIMITIVE"; + +----- component IBUF_GTL_DCI ----- +component IBUF_GTL_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_GTL_DCI : component is "PRIMITIVE"; + +----- component IBUF_GTLP_DCI ----- +component IBUF_GTLP_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_GTLP_DCI : component is "PRIMITIVE"; + +----- component IBUF_GTLP ----- +component IBUF_GTLP + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_GTLP : component is "PRIMITIVE"; + +----- component IBUF_GTL ----- +component IBUF_GTL + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_GTL : component is "PRIMITIVE"; + +----- component IBUFG ----- +component IBUFG + generic + ( + CAPACITANCE : string := "DONT_CARE"; + IBUF_DELAY_VALUE : string := "0"; + IOSTANDARD : string := "DEFAULT" + ); + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUFG : component is "PRIMITIVE"; + +----- component IBUF_HSTL_I_18 ----- +component IBUF_HSTL_I_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_HSTL_I_18 : component is "PRIMITIVE"; + +----- component IBUF_HSTL_I_DCI_18 ----- +component IBUF_HSTL_I_DCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_HSTL_I_DCI_18 : component is "PRIMITIVE"; + +----- component IBUF_HSTL_I_DCI ----- +component IBUF_HSTL_I_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_HSTL_I_DCI : component is "PRIMITIVE"; + +----- component IBUF_HSTL_II_18 ----- +component IBUF_HSTL_II_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_HSTL_II_18 : component is "PRIMITIVE"; + +----- component IBUF_HSTL_II_DCI_18 ----- +component IBUF_HSTL_II_DCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_HSTL_II_DCI_18 : component is "PRIMITIVE"; + +----- component IBUF_HSTL_II_DCI ----- +component IBUF_HSTL_II_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_HSTL_II_DCI : component is "PRIMITIVE"; + +----- component IBUF_HSTL_III_18 ----- +component IBUF_HSTL_III_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_HSTL_III_18 : component is "PRIMITIVE"; + +----- component IBUF_HSTL_III_DCI_18 ----- +component IBUF_HSTL_III_DCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_HSTL_III_DCI_18 : component is "PRIMITIVE"; + +----- component IBUF_HSTL_III_DCI ----- +component IBUF_HSTL_III_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_HSTL_III_DCI : component is "PRIMITIVE"; + +----- component IBUF_HSTL_III ----- +component IBUF_HSTL_III + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_HSTL_III : component is "PRIMITIVE"; + +----- component IBUF_HSTL_II ----- +component IBUF_HSTL_II + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_HSTL_II : component is "PRIMITIVE"; + +----- component IBUF_HSTL_IV_18 ----- +component IBUF_HSTL_IV_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_HSTL_IV_18 : component is "PRIMITIVE"; + +----- component IBUF_HSTL_IV_DCI_18 ----- +component IBUF_HSTL_IV_DCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_HSTL_IV_DCI_18 : component is "PRIMITIVE"; + +----- component IBUF_HSTL_IV_DCI ----- +component IBUF_HSTL_IV_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_HSTL_IV_DCI : component is "PRIMITIVE"; + +----- component IBUF_HSTL_I ----- +component IBUF_HSTL_I + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_HSTL_I : component is "PRIMITIVE"; + +----- component IBUF_HSTL_IV ----- +component IBUF_HSTL_IV + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_HSTL_IV : component is "PRIMITIVE"; + +----- component IBUF_LVCMOS12 ----- +component IBUF_LVCMOS12 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_LVCMOS12 : component is "PRIMITIVE"; + +----- component IBUF_LVCMOS15 ----- +component IBUF_LVCMOS15 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_LVCMOS15 : component is "PRIMITIVE"; + +----- component IBUF_LVCMOS18 ----- +component IBUF_LVCMOS18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_LVCMOS18 : component is "PRIMITIVE"; + +----- component IBUF_LVCMOS25 ----- +component IBUF_LVCMOS25 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_LVCMOS25 : component is "PRIMITIVE"; + +----- component IBUF_LVCMOS2 ----- +component IBUF_LVCMOS2 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_LVCMOS2 : component is "PRIMITIVE"; + +----- component IBUF_LVCMOS33 ----- +component IBUF_LVCMOS33 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_LVCMOS33 : component is "PRIMITIVE"; + +----- component IBUF_LVDCI_15 ----- +component IBUF_LVDCI_15 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_LVDCI_15 : component is "PRIMITIVE"; + +----- component IBUF_LVDCI_18 ----- +component IBUF_LVDCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_LVDCI_18 : component is "PRIMITIVE"; + +----- component IBUF_LVDCI_25 ----- +component IBUF_LVDCI_25 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_LVDCI_25 : component is "PRIMITIVE"; + +----- component IBUF_LVDCI_33 ----- +component IBUF_LVDCI_33 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_LVDCI_33 : component is "PRIMITIVE"; + +----- component IBUF_LVDCI_DV2_15 ----- +component IBUF_LVDCI_DV2_15 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_LVDCI_DV2_15 : component is "PRIMITIVE"; + +----- component IBUF_LVDCI_DV2_18 ----- +component IBUF_LVDCI_DV2_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_LVDCI_DV2_18 : component is "PRIMITIVE"; + +----- component IBUF_LVDCI_DV2_25 ----- +component IBUF_LVDCI_DV2_25 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_LVDCI_DV2_25 : component is "PRIMITIVE"; + +----- component IBUF_LVDCI_DV2_33 ----- +component IBUF_LVDCI_DV2_33 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_LVDCI_DV2_33 : component is "PRIMITIVE"; + +----- component IBUF_LVDS ----- +component IBUF_LVDS + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_LVDS : component is "PRIMITIVE"; + +----- component IBUF_LVPECL ----- +component IBUF_LVPECL + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_LVPECL : component is "PRIMITIVE"; + +----- component IBUF_LVTTL ----- +component IBUF_LVTTL + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_LVTTL : component is "PRIMITIVE"; + +----- component IBUF_PCI33_3 ----- +component IBUF_PCI33_3 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_PCI33_3 : component is "PRIMITIVE"; + +----- component IBUF_PCI33_5 ----- +component IBUF_PCI33_5 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_PCI33_5 : component is "PRIMITIVE"; + +----- component IBUF_PCI66_3 ----- +component IBUF_PCI66_3 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_PCI66_3 : component is "PRIMITIVE"; + +----- component IBUF_PCIX66_3 ----- +component IBUF_PCIX66_3 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_PCIX66_3 : component is "PRIMITIVE"; + +----- component IBUF_PCIX ----- +component IBUF_PCIX + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_PCIX : component is "PRIMITIVE"; + +----- component IBUF_SSTL18_I_DCI ----- +component IBUF_SSTL18_I_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_SSTL18_I_DCI : component is "PRIMITIVE"; + +----- component IBUF_SSTL18_II_DCI ----- +component IBUF_SSTL18_II_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_SSTL18_II_DCI : component is "PRIMITIVE"; + +----- component IBUF_SSTL18_II ----- +component IBUF_SSTL18_II + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_SSTL18_II : component is "PRIMITIVE"; + +----- component IBUF_SSTL18_I ----- +component IBUF_SSTL18_I + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_SSTL18_I : component is "PRIMITIVE"; + +----- component IBUF_SSTL2_I_DCI ----- +component IBUF_SSTL2_I_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_SSTL2_I_DCI : component is "PRIMITIVE"; + +----- component IBUF_SSTL2_II_DCI ----- +component IBUF_SSTL2_II_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_SSTL2_II_DCI : component is "PRIMITIVE"; + +----- component IBUF_SSTL2_II ----- +component IBUF_SSTL2_II + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_SSTL2_II : component is "PRIMITIVE"; + +----- component IBUF_SSTL2_I ----- +component IBUF_SSTL2_I + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_SSTL2_I : component is "PRIMITIVE"; + +----- component IBUF_SSTL3_I_DCI ----- +component IBUF_SSTL3_I_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_SSTL3_I_DCI : component is "PRIMITIVE"; + +----- component IBUF_SSTL3_II_DCI ----- +component IBUF_SSTL3_II_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_SSTL3_II_DCI : component is "PRIMITIVE"; + +----- component IBUF_SSTL3_II ----- +component IBUF_SSTL3_II + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_SSTL3_II : component is "PRIMITIVE"; + +----- component IBUF_SSTL3_I ----- +component IBUF_SSTL3_I + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF_SSTL3_I : component is "PRIMITIVE"; + +----- component IBUF ----- +component IBUF + generic + ( + CAPACITANCE : string := "DONT_CARE"; + IBUF_DELAY_VALUE : string := "0"; + IFD_DELAY_VALUE : string := "AUTO"; + IOSTANDARD : string := "DEFAULT" + ); + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IBUF : component is "PRIMITIVE"; + +----- component ICAP_SPARTAN3A ----- +component ICAP_SPARTAN3A + port + ( + BUSY : out std_ulogic; + O : out std_logic_vector(7 downto 0); + CE : in std_ulogic; + CLK : in std_ulogic; + I : in std_logic_vector(7 downto 0); + WRITE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + ICAP_SPARTAN3A : component is "PRIMITIVE"; + +----- component ICAP_VIRTEX2 ----- +component ICAP_VIRTEX2 + port + ( + BUSY : out std_ulogic; + O : out std_logic_vector(7 downto 0); + CE : in std_ulogic; + CLK : in std_ulogic; + I : in std_logic_vector(7 downto 0); + WRITE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + ICAP_VIRTEX2 : component is "PRIMITIVE"; + +----- component ICAP_VIRTEX4 ----- +component ICAP_VIRTEX4 + generic + ( + ICAP_WIDTH : string := "X8" + ); + port + ( + BUSY : out std_ulogic; + O : out std_logic_vector(31 downto 0); + CE : in std_ulogic; + CLK : in std_ulogic; + I : in std_logic_vector(31 downto 0); + WRITE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + ICAP_VIRTEX4 : component is "PRIMITIVE"; + +----- component ICAP_VIRTEX5 ----- +component ICAP_VIRTEX5 + generic + ( + ICAP_WIDTH : string := "X8" + ); + port + ( + BUSY : out std_ulogic; + O : out std_logic_vector(31 downto 0); + CE : in std_ulogic; + CLK : in std_ulogic; + I : in std_logic_vector(31 downto 0); + WRITE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + ICAP_VIRTEX5 : component is "PRIMITIVE"; + +----- component IDDR_2CLK ----- +component IDDR_2CLK + generic + ( + DDR_CLK_EDGE : string := "OPPOSITE_EDGE"; + INIT_Q1 : bit := '0'; + INIT_Q2 : bit := '0'; + SRTYPE : string := "SYNC" + ); + port + ( + Q1 : out std_ulogic; + Q2 : out std_ulogic; + C : in std_ulogic; + CB : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IDDR_2CLK : component is "PRIMITIVE"; + +----- component IDDR2 ----- +component IDDR2 + generic + ( + DDR_ALIGNMENT : string := "NONE"; + INIT_Q0 : bit := '0'; + INIT_Q1 : bit := '0'; + SRTYPE : string := "SYNC" + ); + port + ( + Q0 : out std_ulogic; + Q1 : out std_ulogic; + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IDDR2 : component is "PRIMITIVE"; + +----- component IDDR ----- +component IDDR + generic + ( + DDR_CLK_EDGE : string := "OPPOSITE_EDGE"; + INIT_Q1 : bit := '0'; + INIT_Q2 : bit := '0'; + SRTYPE : string := "SYNC" + ); + port + ( + Q1 : out std_ulogic; + Q2 : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IDDR : component is "PRIMITIVE"; + +----- component IDELAYCTRL ----- +component IDELAYCTRL + port + ( + RDY : out std_ulogic; + REFCLK : in std_ulogic; + RST : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IDELAYCTRL : component is "PRIMITIVE"; + +----- component IDELAY ----- +component IDELAY + generic + ( + IOBDELAY_TYPE : string := "DEFAULT"; + IOBDELAY_VALUE : integer := 0 + ); + port + ( + O : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + I : in std_ulogic; + INC : in std_ulogic; + RST : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IDELAY : component is "PRIMITIVE"; + +----- component IFDDRCPE ----- +component IFDDRCPE + port + ( + Q0 : out std_ulogic; + Q1 : out std_ulogic; + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IFDDRCPE : component is "PRIMITIVE"; + +----- component IFDDRRSE ----- +component IFDDRRSE + port + ( + Q0 : out std_ulogic; + Q1 : out std_ulogic; + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IFDDRRSE : component is "PRIMITIVE"; + +----- component ILD ----- +component ILD + port + ( + Q : out std_ulogic; + D : in std_ulogic; + G : in std_ulogic + ); +end component; +attribute BOX_TYPE of + ILD : component is "PRIMITIVE"; + +----- component INV ----- +component INV + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + INV : component is "PRIMITIVE"; + +----- component IOBUF_AGP ----- +component IOBUF_AGP + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_AGP : component is "PRIMITIVE"; + +----- component IOBUF_CTT ----- +component IOBUF_CTT + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_CTT : component is "PRIMITIVE"; + +----- component IOBUFDS_BLVDS_25 ----- +component IOBUFDS_BLVDS_25 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + IOB : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUFDS_BLVDS_25 : component is "PRIMITIVE"; + +----- component IOBUFDS ----- +component IOBUFDS + generic + ( + CAPACITANCE : string := "DONT_CARE"; + IBUF_DELAY_VALUE : string := "0"; + IFD_DELAY_VALUE : string := "AUTO"; + IOSTANDARD : string := "DEFAULT" + ); + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + IOB : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUFDS : component is "PRIMITIVE"; + +----- component IOBUFE_F ----- +component IOBUFE_F + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + E : in std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUFE_F : component is "PRIMITIVE"; + +----- component IOBUFE_S ----- +component IOBUFE_S + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + E : in std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUFE_S : component is "PRIMITIVE"; + +----- component IOBUFE ----- +component IOBUFE + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + E : in std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUFE : component is "PRIMITIVE"; + +----- component IOBUF_F_12 ----- +component IOBUF_F_12 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_F_12 : component is "PRIMITIVE"; + +----- component IOBUF_F_16 ----- +component IOBUF_F_16 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_F_16 : component is "PRIMITIVE"; + +----- component IOBUF_F_24 ----- +component IOBUF_F_24 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_F_24 : component is "PRIMITIVE"; + +----- component IOBUF_F_2 ----- +component IOBUF_F_2 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_F_2 : component is "PRIMITIVE"; + +----- component IOBUF_F_4 ----- +component IOBUF_F_4 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_F_4 : component is "PRIMITIVE"; + +----- component IOBUF_F_6 ----- +component IOBUF_F_6 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_F_6 : component is "PRIMITIVE"; + +----- component IOBUF_F_8 ----- +component IOBUF_F_8 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_F_8 : component is "PRIMITIVE"; + +----- component IOBUF_GTL_DCI ----- +component IOBUF_GTL_DCI + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_GTL_DCI : component is "PRIMITIVE"; + +----- component IOBUF_GTLP_DCI ----- +component IOBUF_GTLP_DCI + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_GTLP_DCI : component is "PRIMITIVE"; + +----- component IOBUF_GTLP ----- +component IOBUF_GTLP + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_GTLP : component is "PRIMITIVE"; + +----- component IOBUF_GTL ----- +component IOBUF_GTL + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_GTL : component is "PRIMITIVE"; + +----- component IOBUF_HSTL_I_18 ----- +component IOBUF_HSTL_I_18 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_HSTL_I_18 : component is "PRIMITIVE"; + +----- component IOBUF_HSTL_II_18 ----- +component IOBUF_HSTL_II_18 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_HSTL_II_18 : component is "PRIMITIVE"; + +----- component IOBUF_HSTL_II_DCI_18 ----- +component IOBUF_HSTL_II_DCI_18 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_HSTL_II_DCI_18 : component is "PRIMITIVE"; + +----- component IOBUF_HSTL_II_DCI ----- +component IOBUF_HSTL_II_DCI + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_HSTL_II_DCI : component is "PRIMITIVE"; + +----- component IOBUF_HSTL_III_18 ----- +component IOBUF_HSTL_III_18 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_HSTL_III_18 : component is "PRIMITIVE"; + +----- component IOBUF_HSTL_III ----- +component IOBUF_HSTL_III + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_HSTL_III : component is "PRIMITIVE"; + +----- component IOBUF_HSTL_II ----- +component IOBUF_HSTL_II + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_HSTL_II : component is "PRIMITIVE"; + +----- component IOBUF_HSTL_IV_18 ----- +component IOBUF_HSTL_IV_18 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_HSTL_IV_18 : component is "PRIMITIVE"; + +----- component IOBUF_HSTL_IV_DCI_18 ----- +component IOBUF_HSTL_IV_DCI_18 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_HSTL_IV_DCI_18 : component is "PRIMITIVE"; + +----- component IOBUF_HSTL_IV_DCI ----- +component IOBUF_HSTL_IV_DCI + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_HSTL_IV_DCI : component is "PRIMITIVE"; + +----- component IOBUF_HSTL_I ----- +component IOBUF_HSTL_I + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_HSTL_I : component is "PRIMITIVE"; + +----- component IOBUF_HSTL_IV ----- +component IOBUF_HSTL_IV + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_HSTL_IV : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS12_F_2 ----- +component IOBUF_LVCMOS12_F_2 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS12_F_2 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS12_F_4 ----- +component IOBUF_LVCMOS12_F_4 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS12_F_4 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS12_F_6 ----- +component IOBUF_LVCMOS12_F_6 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS12_F_6 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS12_F_8 ----- +component IOBUF_LVCMOS12_F_8 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS12_F_8 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS12_S_2 ----- +component IOBUF_LVCMOS12_S_2 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS12_S_2 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS12_S_4 ----- +component IOBUF_LVCMOS12_S_4 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS12_S_4 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS12_S_6 ----- +component IOBUF_LVCMOS12_S_6 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS12_S_6 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS12_S_8 ----- +component IOBUF_LVCMOS12_S_8 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS12_S_8 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS12 ----- +component IOBUF_LVCMOS12 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS12 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS15_F_12 ----- +component IOBUF_LVCMOS15_F_12 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS15_F_12 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS15_F_16 ----- +component IOBUF_LVCMOS15_F_16 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS15_F_16 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS15_F_2 ----- +component IOBUF_LVCMOS15_F_2 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS15_F_2 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS15_F_4 ----- +component IOBUF_LVCMOS15_F_4 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS15_F_4 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS15_F_6 ----- +component IOBUF_LVCMOS15_F_6 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS15_F_6 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS15_F_8 ----- +component IOBUF_LVCMOS15_F_8 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS15_F_8 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS15_S_12 ----- +component IOBUF_LVCMOS15_S_12 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS15_S_12 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS15_S_16 ----- +component IOBUF_LVCMOS15_S_16 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS15_S_16 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS15_S_2 ----- +component IOBUF_LVCMOS15_S_2 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS15_S_2 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS15_S_4 ----- +component IOBUF_LVCMOS15_S_4 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS15_S_4 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS15_S_6 ----- +component IOBUF_LVCMOS15_S_6 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS15_S_6 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS15_S_8 ----- +component IOBUF_LVCMOS15_S_8 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS15_S_8 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS15 ----- +component IOBUF_LVCMOS15 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS15 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS18_F_12 ----- +component IOBUF_LVCMOS18_F_12 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS18_F_12 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS18_F_16 ----- +component IOBUF_LVCMOS18_F_16 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS18_F_16 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS18_F_2 ----- +component IOBUF_LVCMOS18_F_2 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS18_F_2 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS18_F_4 ----- +component IOBUF_LVCMOS18_F_4 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS18_F_4 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS18_F_6 ----- +component IOBUF_LVCMOS18_F_6 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS18_F_6 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS18_F_8 ----- +component IOBUF_LVCMOS18_F_8 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS18_F_8 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS18_S_12 ----- +component IOBUF_LVCMOS18_S_12 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS18_S_12 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS18_S_16 ----- +component IOBUF_LVCMOS18_S_16 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS18_S_16 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS18_S_2 ----- +component IOBUF_LVCMOS18_S_2 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS18_S_2 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS18_S_4 ----- +component IOBUF_LVCMOS18_S_4 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS18_S_4 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS18_S_6 ----- +component IOBUF_LVCMOS18_S_6 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS18_S_6 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS18_S_8 ----- +component IOBUF_LVCMOS18_S_8 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS18_S_8 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS18 ----- +component IOBUF_LVCMOS18 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS18 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS25_F_12 ----- +component IOBUF_LVCMOS25_F_12 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS25_F_12 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS25_F_16 ----- +component IOBUF_LVCMOS25_F_16 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS25_F_16 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS25_F_24 ----- +component IOBUF_LVCMOS25_F_24 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS25_F_24 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS25_F_2 ----- +component IOBUF_LVCMOS25_F_2 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS25_F_2 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS25_F_4 ----- +component IOBUF_LVCMOS25_F_4 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS25_F_4 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS25_F_6 ----- +component IOBUF_LVCMOS25_F_6 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS25_F_6 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS25_F_8 ----- +component IOBUF_LVCMOS25_F_8 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS25_F_8 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS25_S_12 ----- +component IOBUF_LVCMOS25_S_12 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS25_S_12 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS25_S_16 ----- +component IOBUF_LVCMOS25_S_16 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS25_S_16 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS25_S_24 ----- +component IOBUF_LVCMOS25_S_24 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS25_S_24 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS25_S_2 ----- +component IOBUF_LVCMOS25_S_2 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS25_S_2 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS25_S_4 ----- +component IOBUF_LVCMOS25_S_4 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS25_S_4 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS25_S_6 ----- +component IOBUF_LVCMOS25_S_6 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS25_S_6 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS25_S_8 ----- +component IOBUF_LVCMOS25_S_8 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS25_S_8 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS25 ----- +component IOBUF_LVCMOS25 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS25 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS2 ----- +component IOBUF_LVCMOS2 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS2 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS33_F_12 ----- +component IOBUF_LVCMOS33_F_12 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS33_F_12 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS33_F_16 ----- +component IOBUF_LVCMOS33_F_16 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS33_F_16 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS33_F_24 ----- +component IOBUF_LVCMOS33_F_24 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS33_F_24 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS33_F_2 ----- +component IOBUF_LVCMOS33_F_2 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS33_F_2 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS33_F_4 ----- +component IOBUF_LVCMOS33_F_4 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS33_F_4 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS33_F_6 ----- +component IOBUF_LVCMOS33_F_6 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS33_F_6 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS33_F_8 ----- +component IOBUF_LVCMOS33_F_8 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS33_F_8 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS33_S_12 ----- +component IOBUF_LVCMOS33_S_12 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS33_S_12 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS33_S_16 ----- +component IOBUF_LVCMOS33_S_16 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS33_S_16 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS33_S_24 ----- +component IOBUF_LVCMOS33_S_24 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS33_S_24 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS33_S_2 ----- +component IOBUF_LVCMOS33_S_2 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS33_S_2 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS33_S_4 ----- +component IOBUF_LVCMOS33_S_4 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS33_S_4 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS33_S_6 ----- +component IOBUF_LVCMOS33_S_6 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS33_S_6 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS33_S_8 ----- +component IOBUF_LVCMOS33_S_8 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS33_S_8 : component is "PRIMITIVE"; + +----- component IOBUF_LVCMOS33 ----- +component IOBUF_LVCMOS33 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVCMOS33 : component is "PRIMITIVE"; + +----- component IOBUF_LVDCI_15 ----- +component IOBUF_LVDCI_15 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVDCI_15 : component is "PRIMITIVE"; + +----- component IOBUF_LVDCI_18 ----- +component IOBUF_LVDCI_18 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVDCI_18 : component is "PRIMITIVE"; + +----- component IOBUF_LVDCI_25 ----- +component IOBUF_LVDCI_25 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVDCI_25 : component is "PRIMITIVE"; + +----- component IOBUF_LVDCI_33 ----- +component IOBUF_LVDCI_33 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVDCI_33 : component is "PRIMITIVE"; + +----- component IOBUF_LVDCI_DV2_15 ----- +component IOBUF_LVDCI_DV2_15 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVDCI_DV2_15 : component is "PRIMITIVE"; + +----- component IOBUF_LVDCI_DV2_18 ----- +component IOBUF_LVDCI_DV2_18 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVDCI_DV2_18 : component is "PRIMITIVE"; + +----- component IOBUF_LVDCI_DV2_25 ----- +component IOBUF_LVDCI_DV2_25 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVDCI_DV2_25 : component is "PRIMITIVE"; + +----- component IOBUF_LVDCI_DV2_33 ----- +component IOBUF_LVDCI_DV2_33 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVDCI_DV2_33 : component is "PRIMITIVE"; + +----- component IOBUF_LVDS ----- +component IOBUF_LVDS + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVDS : component is "PRIMITIVE"; + +----- component IOBUF_LVPECL ----- +component IOBUF_LVPECL + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVPECL : component is "PRIMITIVE"; + +----- component IOBUF_LVTTL_F_12 ----- +component IOBUF_LVTTL_F_12 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVTTL_F_12 : component is "PRIMITIVE"; + +----- component IOBUF_LVTTL_F_16 ----- +component IOBUF_LVTTL_F_16 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVTTL_F_16 : component is "PRIMITIVE"; + +----- component IOBUF_LVTTL_F_24 ----- +component IOBUF_LVTTL_F_24 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVTTL_F_24 : component is "PRIMITIVE"; + +----- component IOBUF_LVTTL_F_2 ----- +component IOBUF_LVTTL_F_2 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVTTL_F_2 : component is "PRIMITIVE"; + +----- component IOBUF_LVTTL_F_4 ----- +component IOBUF_LVTTL_F_4 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVTTL_F_4 : component is "PRIMITIVE"; + +----- component IOBUF_LVTTL_F_6 ----- +component IOBUF_LVTTL_F_6 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVTTL_F_6 : component is "PRIMITIVE"; + +----- component IOBUF_LVTTL_F_8 ----- +component IOBUF_LVTTL_F_8 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVTTL_F_8 : component is "PRIMITIVE"; + +----- component IOBUF_LVTTL_S_12 ----- +component IOBUF_LVTTL_S_12 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVTTL_S_12 : component is "PRIMITIVE"; + +----- component IOBUF_LVTTL_S_16 ----- +component IOBUF_LVTTL_S_16 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVTTL_S_16 : component is "PRIMITIVE"; + +----- component IOBUF_LVTTL_S_24 ----- +component IOBUF_LVTTL_S_24 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVTTL_S_24 : component is "PRIMITIVE"; + +----- component IOBUF_LVTTL_S_2 ----- +component IOBUF_LVTTL_S_2 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVTTL_S_2 : component is "PRIMITIVE"; + +----- component IOBUF_LVTTL_S_4 ----- +component IOBUF_LVTTL_S_4 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVTTL_S_4 : component is "PRIMITIVE"; + +----- component IOBUF_LVTTL_S_6 ----- +component IOBUF_LVTTL_S_6 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVTTL_S_6 : component is "PRIMITIVE"; + +----- component IOBUF_LVTTL_S_8 ----- +component IOBUF_LVTTL_S_8 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVTTL_S_8 : component is "PRIMITIVE"; + +----- component IOBUF_LVTTL ----- +component IOBUF_LVTTL + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_LVTTL : component is "PRIMITIVE"; + +----- component IOBUF_PCI33_3 ----- +component IOBUF_PCI33_3 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_PCI33_3 : component is "PRIMITIVE"; + +----- component IOBUF_PCI33_5 ----- +component IOBUF_PCI33_5 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_PCI33_5 : component is "PRIMITIVE"; + +----- component IOBUF_PCI66_3 ----- +component IOBUF_PCI66_3 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_PCI66_3 : component is "PRIMITIVE"; + +----- component IOBUF_PCIX66_3 ----- +component IOBUF_PCIX66_3 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_PCIX66_3 : component is "PRIMITIVE"; + +----- component IOBUF_PCIX ----- +component IOBUF_PCIX + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_PCIX : component is "PRIMITIVE"; + +----- component IOBUF_S_12 ----- +component IOBUF_S_12 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_S_12 : component is "PRIMITIVE"; + +----- component IOBUF_S_16 ----- +component IOBUF_S_16 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_S_16 : component is "PRIMITIVE"; + +----- component IOBUF_S_24 ----- +component IOBUF_S_24 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_S_24 : component is "PRIMITIVE"; + +----- component IOBUF_S_2 ----- +component IOBUF_S_2 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_S_2 : component is "PRIMITIVE"; + +----- component IOBUF_S_4 ----- +component IOBUF_S_4 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_S_4 : component is "PRIMITIVE"; + +----- component IOBUF_S_6 ----- +component IOBUF_S_6 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_S_6 : component is "PRIMITIVE"; + +----- component IOBUF_S_8 ----- +component IOBUF_S_8 + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_S_8 : component is "PRIMITIVE"; + +----- component IOBUF_SSTL18_II_DCI ----- +component IOBUF_SSTL18_II_DCI + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_SSTL18_II_DCI : component is "PRIMITIVE"; + +----- component IOBUF_SSTL18_II ----- +component IOBUF_SSTL18_II + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_SSTL18_II : component is "PRIMITIVE"; + +----- component IOBUF_SSTL18_I ----- +component IOBUF_SSTL18_I + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_SSTL18_I : component is "PRIMITIVE"; + +----- component IOBUF_SSTL2_II_DCI ----- +component IOBUF_SSTL2_II_DCI + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_SSTL2_II_DCI : component is "PRIMITIVE"; + +----- component IOBUF_SSTL2_II ----- +component IOBUF_SSTL2_II + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_SSTL2_II : component is "PRIMITIVE"; + +----- component IOBUF_SSTL2_I ----- +component IOBUF_SSTL2_I + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_SSTL2_I : component is "PRIMITIVE"; + +----- component IOBUF_SSTL3_II_DCI ----- +component IOBUF_SSTL3_II_DCI + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_SSTL3_II_DCI : component is "PRIMITIVE"; + +----- component IOBUF_SSTL3_II ----- +component IOBUF_SSTL3_II + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_SSTL3_II : component is "PRIMITIVE"; + +----- component IOBUF_SSTL3_I ----- +component IOBUF_SSTL3_I + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF_SSTL3_I : component is "PRIMITIVE"; + +----- component IOBUF ----- +component IOBUF + generic + ( + CAPACITANCE : string := "DONT_CARE"; + DRIVE : integer := 12; + IBUF_DELAY_VALUE : string := "0"; + IFD_DELAY_VALUE : string := "AUTO"; + IOSTANDARD : string := "DEFAULT"; + SLEW : string := "SLOW" + ); + port + ( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IOBUF : component is "PRIMITIVE"; + +----- component IODELAY ----- +component IODELAY + generic + ( + DELAY_SRC : string := "I"; + HIGH_PERFORMANCE_MODE : boolean := true; + IDELAY_TYPE : string := "DEFAULT"; + IDELAY_VALUE : integer := 0; + ODELAY_VALUE : integer := 0; + REFCLK_FREQUENCY : real := 200.0; + SIGNAL_PATTERN : string := "DATA" + ); + port + ( + DATAOUT : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + DATAIN : in std_ulogic; + IDATAIN : in std_ulogic; + INC : in std_ulogic; + ODATAIN : in std_ulogic; + RST : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + IODELAY : component is "PRIMITIVE"; + +----- component ISERDES_NODELAY ----- +component ISERDES_NODELAY + generic + ( + BITSLIP_ENABLE : boolean := false; + DATA_RATE : string := "DDR"; + DATA_WIDTH : integer := 4; + INIT_Q1 : bit := '0'; + INIT_Q2 : bit := '0'; + INIT_Q3 : bit := '0'; + INIT_Q4 : bit := '0'; + INTERFACE_TYPE : string := "MEMORY"; + NUM_CE : integer := 2; + SERDES_MODE : string := "MASTER" + ); + port + ( + Q1 : out std_ulogic; + Q2 : out std_ulogic; + Q3 : out std_ulogic; + Q4 : out std_ulogic; + Q5 : out std_ulogic; + Q6 : out std_ulogic; + SHIFTOUT1 : out std_ulogic; + SHIFTOUT2 : out std_ulogic; + BITSLIP : in std_ulogic; + CE1 : in std_ulogic; + CE2 : in std_ulogic; + CLK : in std_ulogic; + CLKB : in std_ulogic; + CLKDIV : in std_ulogic; + D : in std_ulogic; + OCLK : in std_ulogic; + RST : in std_ulogic; + SHIFTIN1 : in std_ulogic; + SHIFTIN2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + ISERDES_NODELAY : component is "PRIMITIVE"; + +----- component ISERDES ----- +component ISERDES + generic + ( + BITSLIP_ENABLE : boolean := false; + DATA_RATE : string := "DDR"; + DATA_WIDTH : integer := 4; + INIT_Q1 : bit := '0'; + INIT_Q2 : bit := '0'; + INIT_Q3 : bit := '0'; + INIT_Q4 : bit := '0'; + INTERFACE_TYPE : string := "MEMORY"; + IOBDELAY : string := "NONE"; + IOBDELAY_TYPE : string := "DEFAULT"; + IOBDELAY_VALUE : integer := 0; + NUM_CE : integer := 2; + SERDES_MODE : string := "MASTER"; + SRVAL_Q1 : bit := '0'; + SRVAL_Q2 : bit := '0'; + SRVAL_Q3 : bit := '0'; + SRVAL_Q4 : bit := '0' + ); + port + ( + O : out std_ulogic; + Q1 : out std_ulogic; + Q2 : out std_ulogic; + Q3 : out std_ulogic; + Q4 : out std_ulogic; + Q5 : out std_ulogic; + Q6 : out std_ulogic; + SHIFTOUT1 : out std_ulogic; + SHIFTOUT2 : out std_ulogic; + BITSLIP : in std_ulogic; + CE1 : in std_ulogic; + CE2 : in std_ulogic; + CLK : in std_ulogic; + CLKDIV : in std_ulogic; + D : in std_ulogic; + DLYCE : in std_ulogic; + DLYINC : in std_ulogic; + DLYRST : in std_ulogic; + OCLK : in std_ulogic; + REV : in std_ulogic; + SHIFTIN1 : in std_ulogic; + SHIFTIN2 : in std_ulogic; + SR : in std_ulogic + ); +end component; +attribute BOX_TYPE of + ISERDES : component is "PRIMITIVE"; + +----- component JTAGPPC440 ----- +component JTAGPPC440 + port + ( + TCK : out std_ulogic; + TDIPPC : out std_ulogic; + TMS : out std_ulogic; + TDOPPC : in std_ulogic + ); +end component; +attribute BOX_TYPE of + JTAGPPC440 : component is "PRIMITIVE"; + +----- component JTAGPPC ----- +component JTAGPPC + port + ( + TCK : out std_ulogic; + TDIPPC : out std_ulogic; + TMS : out std_ulogic; + TDOPPC : in std_ulogic; + TDOTSPPC : in std_ulogic + ); +end component; +attribute BOX_TYPE of + JTAGPPC : component is "PRIMITIVE"; + +----- component JTAG_SIM_SPARTAN3A ----- +component JTAG_SIM_SPARTAN3A + generic + ( + PART_NAME : string := "3S200A" + ); + port + ( + TDO : out std_ulogic; + TCK : in std_ulogic; + TDI : in std_ulogic; + TMS : in std_ulogic + ); +end component; +attribute BOX_TYPE of + JTAG_SIM_SPARTAN3A : component is "PRIMITIVE"; + +----- component JTAG_SIM_VIRTEX4 ----- +component JTAG_SIM_VIRTEX4 + generic + ( + PART_NAME : string := "LX15" + ); + port + ( + TDO : out std_ulogic; + TCK : in std_ulogic; + TDI : in std_ulogic; + TMS : in std_ulogic + ); +end component; +attribute BOX_TYPE of + JTAG_SIM_VIRTEX4 : component is "PRIMITIVE"; + +----- component JTAG_SIM_VIRTEX5 ----- +component JTAG_SIM_VIRTEX5 + generic + ( + PART_NAME : string := "LX50" + ); + port + ( + TDO : out std_ulogic; + TCK : in std_ulogic; + TDI : in std_ulogic; + TMS : in std_ulogic + ); +end component; +attribute BOX_TYPE of + JTAG_SIM_VIRTEX5 : component is "PRIMITIVE"; + +----- component KEEPER ----- +component KEEPER + port + ( + O : inout std_ulogic := 'W' + ); +end component; +attribute BOX_TYPE of + KEEPER : component is "PRIMITIVE"; + +----- component KEEP ----- +component KEEP + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + KEEP : component is "PRIMITIVE"; + +----- component KEY_CLEAR ----- +component KEY_CLEAR + port + ( + KEYCLEARB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + KEY_CLEAR : component is "PRIMITIVE"; + +----- component LD_1 ----- +component LD_1 + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic := '0'; + D : in std_ulogic; + G : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LD_1 : component is "PRIMITIVE"; + +----- component LDC_1 ----- +component LDC_1 + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + G : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LDC_1 : component is "PRIMITIVE"; + +----- component LDCE_1 ----- +component LDCE_1 + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + G : in std_ulogic; + GE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LDCE_1 : component is "PRIMITIVE"; + +----- component LDCE ----- +component LDCE + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + G : in std_ulogic; + GE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LDCE : component is "PRIMITIVE"; + +----- component LDCP_1 ----- +component LDCP_1 + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + G : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LDCP_1 : component is "PRIMITIVE"; + +----- component LDCPE_1 ----- +component LDCPE_1 + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + G : in std_ulogic; + GE : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LDCPE_1 : component is "PRIMITIVE"; + +----- component LDCPE ----- +component LDCPE + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + G : in std_ulogic; + GE : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LDCPE : component is "PRIMITIVE"; + +----- component LDCP ----- +component LDCP + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + G : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LDCP : component is "PRIMITIVE"; + +----- component LDC ----- +component LDC + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + G : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LDC : component is "PRIMITIVE"; + +----- component LDE_1 ----- +component LDE_1 + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic := '0'; + D : in std_ulogic; + G : in std_ulogic; + GE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LDE_1 : component is "PRIMITIVE"; + +----- component LDE ----- +component LDE + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic := '0'; + D : in std_ulogic; + G : in std_ulogic; + GE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LDE : component is "PRIMITIVE"; + +----- component LDG ----- +component LDG + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + G : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + LDG : component is "PRIMITIVE"; + +----- component LDP_1 ----- +component LDP_1 + generic + ( + INIT : bit := '1' + ); + port + ( + Q : out std_ulogic; + D : in std_ulogic; + G : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LDP_1 : component is "PRIMITIVE"; + +----- component LDPE_1 ----- +component LDPE_1 + generic + ( + INIT : bit := '1' + ); + port + ( + Q : out std_ulogic; + D : in std_ulogic; + G : in std_ulogic; + GE : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LDPE_1 : component is "PRIMITIVE"; + +----- component LDPE ----- +component LDPE + generic + ( + INIT : bit := '1' + ); + port + ( + Q : out std_ulogic; + D : in std_ulogic; + G : in std_ulogic; + GE : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LDPE : component is "PRIMITIVE"; + +----- component LDP ----- +component LDP + generic + ( + INIT : bit := '1' + ); + port + ( + Q : out std_ulogic; + D : in std_ulogic; + G : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LDP : component is "PRIMITIVE"; + +----- component LD ----- +component LD + generic + ( + INIT : bit := '0' + ); + port + ( + Q : out std_ulogic := '0'; + D : in std_ulogic; + G : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LD : component is "PRIMITIVE"; + +----- component LUT1_D ----- +component LUT1_D + generic + ( + INIT : bit_vector := X"0" + ); + port + ( + LO : out std_ulogic; + O : out std_ulogic; + I0 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LUT1_D : component is "PRIMITIVE"; + +----- component LUT1_L ----- +component LUT1_L + generic + ( + INIT : bit_vector := X"0" + ); + port + ( + LO : out std_ulogic; + I0 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LUT1_L : component is "PRIMITIVE"; + +----- component LUT1 ----- +component LUT1 + generic + ( + INIT : bit_vector := X"0" + ); + port + ( + O : out std_ulogic; + I0 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LUT1 : component is "PRIMITIVE"; + +----- component LUT2_D ----- +component LUT2_D + generic + ( + INIT : bit_vector := X"0" + ); + port + ( + LO : out std_ulogic; + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LUT2_D : component is "PRIMITIVE"; + +----- component LUT2_L ----- +component LUT2_L + generic + ( + INIT : bit_vector := X"0" + ); + port + ( + LO : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LUT2_L : component is "PRIMITIVE"; + +----- component LUT2 ----- +component LUT2 + generic + ( + INIT : bit_vector := X"0" + ); + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LUT2 : component is "PRIMITIVE"; + +----- component LUT3_D ----- +component LUT3_D + generic + ( + INIT : bit_vector := X"00" + ); + port + ( + LO : out std_ulogic; + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LUT3_D : component is "PRIMITIVE"; + +----- component LUT3_L ----- +component LUT3_L + generic + ( + INIT : bit_vector := X"00" + ); + port + ( + LO : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LUT3_L : component is "PRIMITIVE"; + +----- component LUT3 ----- +component LUT3 + generic + ( + INIT : bit_vector := X"00" + ); + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LUT3 : component is "PRIMITIVE"; + +----- component LUT4_D ----- +component LUT4_D + generic + ( + INIT : bit_vector := X"0000" + ); + port + ( + LO : out std_ulogic; + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LUT4_D : component is "PRIMITIVE"; + +----- component LUT4_L ----- +component LUT4_L + generic + ( + INIT : bit_vector := X"0000" + ); + port + ( + LO : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LUT4_L : component is "PRIMITIVE"; + +----- component LUT4 ----- +component LUT4 + generic + ( + INIT : bit_vector := X"0000" + ); + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LUT4 : component is "PRIMITIVE"; + +----- component LUT5_D ----- +component LUT5_D + generic + ( + INIT : bit_vector := X"00000000" + ); + port + ( + LO : out std_ulogic; + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LUT5_D : component is "PRIMITIVE"; + +----- component LUT5_L ----- +component LUT5_L + generic + ( + INIT : bit_vector := X"00000000" + ); + port + ( + LO : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LUT5_L : component is "PRIMITIVE"; + +----- component LUT5 ----- +component LUT5 + generic + ( + INIT : bit_vector := X"00000000" + ); + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LUT5 : component is "PRIMITIVE"; + +----- component LUT6_2 ----- +component LUT6_2 + generic + ( + INIT : bit_vector := X"0000000000000000" + ); + port + ( + O5 : out std_ulogic; + O6 : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LUT6_2 : component is "PRIMITIVE"; + +----- component LUT6_D ----- +component LUT6_D + generic + ( + INIT : bit_vector := X"0000000000000000" + ); + port + ( + LO : out std_ulogic; + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LUT6_D : component is "PRIMITIVE"; + +----- component LUT6_L ----- +component LUT6_L + generic + ( + INIT : bit_vector := X"0000000000000000" + ); + port + ( + LO : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LUT6_L : component is "PRIMITIVE"; + +----- component LUT6 ----- +component LUT6 + generic + ( + INIT : bit_vector := X"0000000000000000" + ); + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + LUT6 : component is "PRIMITIVE"; + +----- component MERGE ----- +component MERGE + port + ( + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MERGE : component is "PRIMITIVE"; + +----- component MIN_OFF ----- +component MIN_OFF + port + ( + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MIN_OFF : component is "PRIMITIVE"; + +----- component MULT18X18SIO ----- +component MULT18X18SIO + generic + ( + AREG : integer := 1; + BREG : integer := 1; + B_INPUT : string := "DIRECT"; + PREG : integer := 1 + ); + port + ( + BCOUT : out std_logic_vector (17 downto 0); + P : out std_logic_vector (35 downto 0); + A : in std_logic_vector (17 downto 0); + B : in std_logic_vector (17 downto 0); + BCIN : in std_logic_vector (17 downto 0); + CEA : in std_ulogic; + CEB : in std_ulogic; + CEP : in std_ulogic; + CLK : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + RSTP : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MULT18X18SIO : component is "PRIMITIVE"; + +----- component MULT18X18S ----- +component MULT18X18S + port + ( + P : out std_logic_vector (35 downto 0); + A : in std_logic_vector (17 downto 0); + B : in std_logic_vector (17 downto 0); + C : in std_ulogic; + CE : in std_ulogic; + R : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MULT18X18S : component is "PRIMITIVE"; + +----- component MULT18X18 ----- +component MULT18X18 + port + ( + P : out std_logic_vector (35 downto 0); + A : in std_logic_vector (17 downto 0); + B : in std_logic_vector (17 downto 0) + ); +end component; +attribute BOX_TYPE of + MULT18X18 : component is "PRIMITIVE"; + +----- component MULT_AND ----- +component MULT_AND + port + ( + LO : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MULT_AND : component is "PRIMITIVE"; + +----- component MUXCY_D ----- +component MUXCY_D + port + ( + LO : out std_ulogic; + O : out std_ulogic; + CI : in std_ulogic; + DI : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MUXCY_D : component is "PRIMITIVE"; + +----- component MUXCY_L ----- +component MUXCY_L + port + ( + LO : out std_ulogic; + CI : in std_ulogic; + DI : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MUXCY_L : component is "PRIMITIVE"; + +----- component MUXCY ----- +component MUXCY + port + ( + O : out std_ulogic; + CI : in std_ulogic; + DI : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MUXCY : component is "PRIMITIVE"; + +----- component MUXF5_D ----- +component MUXF5_D + port + ( + LO : out std_ulogic; + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MUXF5_D : component is "PRIMITIVE"; + +----- component MUXF5_L ----- +component MUXF5_L + port + ( + LO : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MUXF5_L : component is "PRIMITIVE"; + +----- component MUXF5 ----- +component MUXF5 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MUXF5 : component is "PRIMITIVE"; + +----- component MUXF6_D ----- +component MUXF6_D + port + ( + LO : out std_ulogic; + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MUXF6_D : component is "PRIMITIVE"; + +----- component MUXF6_L ----- +component MUXF6_L + port + ( + LO : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MUXF6_L : component is "PRIMITIVE"; + +----- component MUXF6 ----- +component MUXF6 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MUXF6 : component is "PRIMITIVE"; + +----- component MUXF7_D ----- +component MUXF7_D + port + ( + LO : out std_ulogic; + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MUXF7_D : component is "PRIMITIVE"; + +----- component MUXF7_L ----- +component MUXF7_L + port + ( + LO : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MUXF7_L : component is "PRIMITIVE"; + +----- component MUXF7 ----- +component MUXF7 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MUXF7 : component is "PRIMITIVE"; + +----- component MUXF8_D ----- +component MUXF8_D + port + ( + LO : out std_ulogic; + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MUXF8_D : component is "PRIMITIVE"; + +----- component MUXF8_L ----- +component MUXF8_L + port + ( + LO : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MUXF8_L : component is "PRIMITIVE"; + +----- component MUXF8 ----- +component MUXF8 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + MUXF8 : component is "PRIMITIVE"; + +----- component NAND2B1 ----- +component NAND2B1 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NAND2B1 : component is "PRIMITIVE"; + +----- component NAND2B2 ----- +component NAND2B2 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NAND2B2 : component is "PRIMITIVE"; + +----- component NAND2 ----- +component NAND2 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NAND2 : component is "PRIMITIVE"; + +----- component NAND3B1 ----- +component NAND3B1 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NAND3B1 : component is "PRIMITIVE"; + +----- component NAND3B2 ----- +component NAND3B2 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NAND3B2 : component is "PRIMITIVE"; + +----- component NAND3B3 ----- +component NAND3B3 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NAND3B3 : component is "PRIMITIVE"; + +----- component NAND3 ----- +component NAND3 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NAND3 : component is "PRIMITIVE"; + +----- component NAND4B1 ----- +component NAND4B1 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NAND4B1 : component is "PRIMITIVE"; + +----- component NAND4B2 ----- +component NAND4B2 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NAND4B2 : component is "PRIMITIVE"; + +----- component NAND4B3 ----- +component NAND4B3 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NAND4B3 : component is "PRIMITIVE"; + +----- component NAND4B4 ----- +component NAND4B4 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NAND4B4 : component is "PRIMITIVE"; + +----- component NAND4 ----- +component NAND4 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NAND4 : component is "PRIMITIVE"; + +----- component NAND5B1 ----- +component NAND5B1 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NAND5B1 : component is "PRIMITIVE"; + +----- component NAND5B2 ----- +component NAND5B2 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NAND5B2 : component is "PRIMITIVE"; + +----- component NAND5B3 ----- +component NAND5B3 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NAND5B3 : component is "PRIMITIVE"; + +----- component NAND5B4 ----- +component NAND5B4 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NAND5B4 : component is "PRIMITIVE"; + +----- component NAND5B5 ----- +component NAND5B5 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NAND5B5 : component is "PRIMITIVE"; + +----- component NAND5 ----- +component NAND5 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NAND5 : component is "PRIMITIVE"; + +----- component NOR2B1 ----- +component NOR2B1 + port + ( + O : out STD_ULOGIC; + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + NOR2B1 : component is "PRIMITIVE"; + +----- component NOR2B2 ----- +component NOR2B2 + port + ( + O : out STD_ULOGIC; + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + NOR2B2 : component is "PRIMITIVE"; + +----- component NOR2 ----- +component NOR2 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NOR2 : component is "PRIMITIVE"; + +----- component NOR3B1 ----- +component NOR3B1 + port + ( + O : out STD_ULOGIC; + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + NOR3B1 : component is "PRIMITIVE"; + +----- component NOR3B2 ----- +component NOR3B2 + port + ( + O : out STD_ULOGIC; + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + NOR3B2 : component is "PRIMITIVE"; + +----- component NOR3B3 ----- +component NOR3B3 + port + ( + O : out STD_ULOGIC; + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + NOR3B3 : component is "PRIMITIVE"; + +----- component NOR3 ----- +component NOR3 + port + ( + O : out STD_ULOGIC; + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + NOR3 : component is "PRIMITIVE"; + +----- component NOR4B1 ----- +component NOR4B1 + port + ( + O : out STD_ULOGIC; + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC; + I3 : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + NOR4B1 : component is "PRIMITIVE"; + +----- component NOR4B2 ----- +component NOR4B2 + port + ( + O : out STD_ULOGIC; + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC; + I3 : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + NOR4B2 : component is "PRIMITIVE"; + +----- component NOR4B3 ----- +component NOR4B3 + port + ( + O : out STD_ULOGIC; + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC; + I3 : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + NOR4B3 : component is "PRIMITIVE"; + +----- component NOR4B4 ----- +component NOR4B4 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NOR4B4 : component is "PRIMITIVE"; + +----- component NOR4 ----- +component NOR4 + port + ( + O : out STD_ULOGIC; + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC; + I3 : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + NOR4 : component is "PRIMITIVE"; + +----- component NOR5B1 ----- +component NOR5B1 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NOR5B1 : component is "PRIMITIVE"; + +----- component NOR5B2 ----- +component NOR5B2 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NOR5B2 : component is "PRIMITIVE"; + +----- component NOR5B3 ----- +component NOR5B3 + port + ( + O : out STD_ULOGIC; + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC; + I3 : in STD_ULOGIC; + I4 : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + NOR5B3 : component is "PRIMITIVE"; + +----- component NOR5B4 ----- +component NOR5B4 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NOR5B4 : component is "PRIMITIVE"; + +----- component NOR5B5 ----- +component NOR5B5 + port + ( + O : out STD_ULOGIC; + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC; + I3 : in STD_ULOGIC; + I4 : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + NOR5B5 : component is "PRIMITIVE"; + +----- component NOR5 ----- +component NOR5 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + NOR5 : component is "PRIMITIVE"; + +----- component OBUF_AGP ----- +component OBUF_AGP + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_AGP : component is "PRIMITIVE"; + +----- component OBUF_CTT ----- +component OBUF_CTT + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_CTT : component is "PRIMITIVE"; + +----- component OBUFDS_BLVDS_25 ----- +component OBUFDS_BLVDS_25 + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFDS_BLVDS_25 : component is "PRIMITIVE"; + +----- component OBUFDS_LDT_25 ----- +component OBUFDS_LDT_25 + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFDS_LDT_25 : component is "PRIMITIVE"; + +----- component OBUFDS_LVDS_25 ----- +component OBUFDS_LVDS_25 + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFDS_LVDS_25 : component is "PRIMITIVE"; + +----- component OBUFDS_LVDS_33 ----- +component OBUFDS_LVDS_33 + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFDS_LVDS_33 : component is "PRIMITIVE"; + +----- component OBUFDS_LVDSEXT_25 ----- +component OBUFDS_LVDSEXT_25 + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFDS_LVDSEXT_25 : component is "PRIMITIVE"; + +----- component OBUFDS_LVDSEXT_33 ----- +component OBUFDS_LVDSEXT_33 + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFDS_LVDSEXT_33 : component is "PRIMITIVE"; + +----- component OBUFDS_LVPECL_25 ----- +component OBUFDS_LVPECL_25 + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFDS_LVPECL_25 : component is "PRIMITIVE"; + +----- component OBUFDS_LVPECL_33 ----- +component OBUFDS_LVPECL_33 + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFDS_LVPECL_33 : component is "PRIMITIVE"; + +----- component OBUFDS_ULVDS_25 ----- +component OBUFDS_ULVDS_25 + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFDS_ULVDS_25 : component is "PRIMITIVE"; + +----- component OBUFDS ----- +component OBUFDS + generic + ( + CAPACITANCE : string := "DONT_CARE"; + IOSTANDARD : string := "DEFAULT" + ); + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFDS : component is "PRIMITIVE"; + +----- component OBUFE ----- +component OBUFE + port + ( + O : out std_ulogic; + I : in std_ulogic; + E : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFE : component is "PRIMITIVE"; + +----- component OBUF_F_12 ----- +component OBUF_F_12 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_F_12 : component is "PRIMITIVE"; + +----- component OBUF_F_16 ----- +component OBUF_F_16 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_F_16 : component is "PRIMITIVE"; + +----- component OBUF_F_24 ----- +component OBUF_F_24 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_F_24 : component is "PRIMITIVE"; + +----- component OBUF_F_2 ----- +component OBUF_F_2 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_F_2 : component is "PRIMITIVE"; + +----- component OBUF_F_4 ----- +component OBUF_F_4 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_F_4 : component is "PRIMITIVE"; + +----- component OBUF_F_6 ----- +component OBUF_F_6 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_F_6 : component is "PRIMITIVE"; + +----- component OBUF_F_8 ----- +component OBUF_F_8 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_F_8 : component is "PRIMITIVE"; + +----- component OBUF_GTL_DCI ----- +component OBUF_GTL_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_GTL_DCI : component is "PRIMITIVE"; + +----- component OBUF_GTLP_DCI ----- +component OBUF_GTLP_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_GTLP_DCI : component is "PRIMITIVE"; + +----- component OBUF_GTLP ----- +component OBUF_GTLP + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_GTLP : component is "PRIMITIVE"; + +----- component OBUF_GTL ----- +component OBUF_GTL + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_GTL : component is "PRIMITIVE"; + +----- component OBUF_HSTL_I_18 ----- +component OBUF_HSTL_I_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_HSTL_I_18 : component is "PRIMITIVE"; + +----- component OBUF_HSTL_I_DCI_18 ----- +component OBUF_HSTL_I_DCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_HSTL_I_DCI_18 : component is "PRIMITIVE"; + +----- component OBUF_HSTL_I_DCI ----- +component OBUF_HSTL_I_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_HSTL_I_DCI : component is "PRIMITIVE"; + +----- component OBUF_HSTL_II_18 ----- +component OBUF_HSTL_II_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_HSTL_II_18 : component is "PRIMITIVE"; + +----- component OBUF_HSTL_II_DCI_18 ----- +component OBUF_HSTL_II_DCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_HSTL_II_DCI_18 : component is "PRIMITIVE"; + +----- component OBUF_HSTL_II_DCI ----- +component OBUF_HSTL_II_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_HSTL_II_DCI : component is "PRIMITIVE"; + +----- component OBUF_HSTL_III_18 ----- +component OBUF_HSTL_III_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_HSTL_III_18 : component is "PRIMITIVE"; + +----- component OBUF_HSTL_III_DCI_18 ----- +component OBUF_HSTL_III_DCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_HSTL_III_DCI_18 : component is "PRIMITIVE"; + +----- component OBUF_HSTL_III_DCI ----- +component OBUF_HSTL_III_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_HSTL_III_DCI : component is "PRIMITIVE"; + +----- component OBUF_HSTL_III ----- +component OBUF_HSTL_III + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_HSTL_III : component is "PRIMITIVE"; + +----- component OBUF_HSTL_II ----- +component OBUF_HSTL_II + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_HSTL_II : component is "PRIMITIVE"; + +----- component OBUF_HSTL_IV_18 ----- +component OBUF_HSTL_IV_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_HSTL_IV_18 : component is "PRIMITIVE"; + +----- component OBUF_HSTL_IV_DCI_18 ----- +component OBUF_HSTL_IV_DCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_HSTL_IV_DCI_18 : component is "PRIMITIVE"; + +----- component OBUF_HSTL_IV_DCI ----- +component OBUF_HSTL_IV_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_HSTL_IV_DCI : component is "PRIMITIVE"; + +----- component OBUF_HSTL_I ----- +component OBUF_HSTL_I + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_HSTL_I : component is "PRIMITIVE"; + +----- component OBUF_HSTL_IV ----- +component OBUF_HSTL_IV + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_HSTL_IV : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS12_F_2 ----- +component OBUF_LVCMOS12_F_2 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS12_F_2 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS12_F_4 ----- +component OBUF_LVCMOS12_F_4 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS12_F_4 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS12_F_6 ----- +component OBUF_LVCMOS12_F_6 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS12_F_6 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS12_F_8 ----- +component OBUF_LVCMOS12_F_8 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS12_F_8 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS12_S_2 ----- +component OBUF_LVCMOS12_S_2 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS12_S_2 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS12_S_4 ----- +component OBUF_LVCMOS12_S_4 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS12_S_4 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS12_S_6 ----- +component OBUF_LVCMOS12_S_6 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS12_S_6 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS12_S_8 ----- +component OBUF_LVCMOS12_S_8 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS12_S_8 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS12 ----- +component OBUF_LVCMOS12 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS12 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS15_F_12 ----- +component OBUF_LVCMOS15_F_12 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS15_F_12 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS15_F_16 ----- +component OBUF_LVCMOS15_F_16 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS15_F_16 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS15_F_2 ----- +component OBUF_LVCMOS15_F_2 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS15_F_2 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS15_F_4 ----- +component OBUF_LVCMOS15_F_4 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS15_F_4 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS15_F_6 ----- +component OBUF_LVCMOS15_F_6 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS15_F_6 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS15_F_8 ----- +component OBUF_LVCMOS15_F_8 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS15_F_8 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS15_S_12 ----- +component OBUF_LVCMOS15_S_12 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS15_S_12 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS15_S_16 ----- +component OBUF_LVCMOS15_S_16 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS15_S_16 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS15_S_2 ----- +component OBUF_LVCMOS15_S_2 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS15_S_2 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS15_S_4 ----- +component OBUF_LVCMOS15_S_4 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS15_S_4 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS15_S_6 ----- +component OBUF_LVCMOS15_S_6 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS15_S_6 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS15_S_8 ----- +component OBUF_LVCMOS15_S_8 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS15_S_8 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS15 ----- +component OBUF_LVCMOS15 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS15 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS18_F_12 ----- +component OBUF_LVCMOS18_F_12 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS18_F_12 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS18_F_16 ----- +component OBUF_LVCMOS18_F_16 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS18_F_16 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS18_F_2 ----- +component OBUF_LVCMOS18_F_2 + port + ( + O : out STD_ULOGIC; + I : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS18_F_2 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS18_F_4 ----- +component OBUF_LVCMOS18_F_4 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS18_F_4 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS18_F_6 ----- +component OBUF_LVCMOS18_F_6 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS18_F_6 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS18_F_8 ----- +component OBUF_LVCMOS18_F_8 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS18_F_8 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS18_S_12 ----- +component OBUF_LVCMOS18_S_12 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS18_S_12 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS18_S_16 ----- +component OBUF_LVCMOS18_S_16 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS18_S_16 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS18_S_2 ----- +component OBUF_LVCMOS18_S_2 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS18_S_2 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS18_S_4 ----- +component OBUF_LVCMOS18_S_4 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS18_S_4 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS18_S_6 ----- +component OBUF_LVCMOS18_S_6 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS18_S_6 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS18_S_8 ----- +component OBUF_LVCMOS18_S_8 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS18_S_8 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS18 ----- +component OBUF_LVCMOS18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS18 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS25_F_12 ----- +component OBUF_LVCMOS25_F_12 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS25_F_12 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS25_F_16 ----- +component OBUF_LVCMOS25_F_16 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS25_F_16 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS25_F_24 ----- +component OBUF_LVCMOS25_F_24 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS25_F_24 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS25_F_2 ----- +component OBUF_LVCMOS25_F_2 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS25_F_2 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS25_F_4 ----- +component OBUF_LVCMOS25_F_4 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS25_F_4 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS25_F_6 ----- +component OBUF_LVCMOS25_F_6 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS25_F_6 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS25_F_8 ----- +component OBUF_LVCMOS25_F_8 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS25_F_8 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS25_S_12 ----- +component OBUF_LVCMOS25_S_12 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS25_S_12 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS25_S_16 ----- +component OBUF_LVCMOS25_S_16 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS25_S_16 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS25_S_24 ----- +component OBUF_LVCMOS25_S_24 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS25_S_24 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS25_S_2 ----- +component OBUF_LVCMOS25_S_2 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS25_S_2 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS25_S_4 ----- +component OBUF_LVCMOS25_S_4 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS25_S_4 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS25_S_6 ----- +component OBUF_LVCMOS25_S_6 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS25_S_6 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS25_S_8 ----- +component OBUF_LVCMOS25_S_8 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS25_S_8 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS25 ----- +component OBUF_LVCMOS25 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS25 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS2 ----- +component OBUF_LVCMOS2 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS2 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS33_F_12 ----- +component OBUF_LVCMOS33_F_12 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS33_F_12 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS33_F_16 ----- +component OBUF_LVCMOS33_F_16 + port + ( + O : out STD_ULOGIC; + I : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS33_F_16 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS33_F_24 ----- +component OBUF_LVCMOS33_F_24 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS33_F_24 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS33_F_2 ----- +component OBUF_LVCMOS33_F_2 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS33_F_2 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS33_F_4 ----- +component OBUF_LVCMOS33_F_4 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS33_F_4 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS33_F_6 ----- +component OBUF_LVCMOS33_F_6 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS33_F_6 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS33_F_8 ----- +component OBUF_LVCMOS33_F_8 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS33_F_8 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS33_S_12 ----- +component OBUF_LVCMOS33_S_12 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS33_S_12 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS33_S_16 ----- +component OBUF_LVCMOS33_S_16 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS33_S_16 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS33_S_24 ----- +component OBUF_LVCMOS33_S_24 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS33_S_24 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS33_S_2 ----- +component OBUF_LVCMOS33_S_2 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS33_S_2 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS33_S_4 ----- +component OBUF_LVCMOS33_S_4 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS33_S_4 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS33_S_6 ----- +component OBUF_LVCMOS33_S_6 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS33_S_6 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS33_S_8 ----- +component OBUF_LVCMOS33_S_8 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS33_S_8 : component is "PRIMITIVE"; + +----- component OBUF_LVCMOS33 ----- +component OBUF_LVCMOS33 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVCMOS33 : component is "PRIMITIVE"; + +----- component OBUF_LVDCI_15 ----- +component OBUF_LVDCI_15 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVDCI_15 : component is "PRIMITIVE"; + +----- component OBUF_LVDCI_18 ----- +component OBUF_LVDCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVDCI_18 : component is "PRIMITIVE"; + +----- component OBUF_LVDCI_25 ----- +component OBUF_LVDCI_25 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVDCI_25 : component is "PRIMITIVE"; + +----- component OBUF_LVDCI_33 ----- +component OBUF_LVDCI_33 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVDCI_33 : component is "PRIMITIVE"; + +----- component OBUF_LVDCI_DV2_15 ----- +component OBUF_LVDCI_DV2_15 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVDCI_DV2_15 : component is "PRIMITIVE"; + +----- component OBUF_LVDCI_DV2_18 ----- +component OBUF_LVDCI_DV2_18 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVDCI_DV2_18 : component is "PRIMITIVE"; + +----- component OBUF_LVDCI_DV2_25 ----- +component OBUF_LVDCI_DV2_25 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVDCI_DV2_25 : component is "PRIMITIVE"; + +----- component OBUF_LVDCI_DV2_33 ----- +component OBUF_LVDCI_DV2_33 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVDCI_DV2_33 : component is "PRIMITIVE"; + +----- component OBUF_LVDS ----- +component OBUF_LVDS + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVDS : component is "PRIMITIVE"; + +----- component OBUF_LVPECL ----- +component OBUF_LVPECL + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVPECL : component is "PRIMITIVE"; + +----- component OBUF_LVTTL_F_12 ----- +component OBUF_LVTTL_F_12 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVTTL_F_12 : component is "PRIMITIVE"; + +----- component OBUF_LVTTL_F_16 ----- +component OBUF_LVTTL_F_16 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVTTL_F_16 : component is "PRIMITIVE"; + +----- component OBUF_LVTTL_F_24 ----- +component OBUF_LVTTL_F_24 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVTTL_F_24 : component is "PRIMITIVE"; + +----- component OBUF_LVTTL_F_2 ----- +component OBUF_LVTTL_F_2 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVTTL_F_2 : component is "PRIMITIVE"; + +----- component OBUF_LVTTL_F_4 ----- +component OBUF_LVTTL_F_4 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVTTL_F_4 : component is "PRIMITIVE"; + +----- component OBUF_LVTTL_F_6 ----- +component OBUF_LVTTL_F_6 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVTTL_F_6 : component is "PRIMITIVE"; + +----- component OBUF_LVTTL_F_8 ----- +component OBUF_LVTTL_F_8 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVTTL_F_8 : component is "PRIMITIVE"; + +----- component OBUF_LVTTL_S_12 ----- +component OBUF_LVTTL_S_12 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVTTL_S_12 : component is "PRIMITIVE"; + +----- component OBUF_LVTTL_S_16 ----- +component OBUF_LVTTL_S_16 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVTTL_S_16 : component is "PRIMITIVE"; + +----- component OBUF_LVTTL_S_24 ----- +component OBUF_LVTTL_S_24 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVTTL_S_24 : component is "PRIMITIVE"; + +----- component OBUF_LVTTL_S_2 ----- +component OBUF_LVTTL_S_2 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVTTL_S_2 : component is "PRIMITIVE"; + +----- component OBUF_LVTTL_S_4 ----- +component OBUF_LVTTL_S_4 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVTTL_S_4 : component is "PRIMITIVE"; + +----- component OBUF_LVTTL_S_6 ----- +component OBUF_LVTTL_S_6 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVTTL_S_6 : component is "PRIMITIVE"; + +----- component OBUF_LVTTL_S_8 ----- +component OBUF_LVTTL_S_8 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVTTL_S_8 : component is "PRIMITIVE"; + +----- component OBUF_LVTTL ----- +component OBUF_LVTTL + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_LVTTL : component is "PRIMITIVE"; + +----- component OBUF_PCI33_3 ----- +component OBUF_PCI33_3 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_PCI33_3 : component is "PRIMITIVE"; + +----- component OBUF_PCI33_5 ----- +component OBUF_PCI33_5 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_PCI33_5 : component is "PRIMITIVE"; + +----- component OBUF_PCI66_3 ----- +component OBUF_PCI66_3 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_PCI66_3 : component is "PRIMITIVE"; + +----- component OBUF_PCIX66_3 ----- +component OBUF_PCIX66_3 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_PCIX66_3 : component is "PRIMITIVE"; + +----- component OBUF_PCIX ----- +component OBUF_PCIX + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_PCIX : component is "PRIMITIVE"; + +----- component OBUF_S_12 ----- +component OBUF_S_12 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_S_12 : component is "PRIMITIVE"; + +----- component OBUF_S_16 ----- +component OBUF_S_16 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_S_16 : component is "PRIMITIVE"; + +----- component OBUF_S_24 ----- +component OBUF_S_24 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_S_24 : component is "PRIMITIVE"; + +----- component OBUF_S_2 ----- +component OBUF_S_2 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_S_2 : component is "PRIMITIVE"; + +----- component OBUF_S_4 ----- +component OBUF_S_4 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_S_4 : component is "PRIMITIVE"; + +----- component OBUF_S_6 ----- +component OBUF_S_6 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_S_6 : component is "PRIMITIVE"; + +----- component OBUF_S_8 ----- +component OBUF_S_8 + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_S_8 : component is "PRIMITIVE"; + +----- component OBUF_SSTL18_I_DCI ----- +component OBUF_SSTL18_I_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_SSTL18_I_DCI : component is "PRIMITIVE"; + +----- component OBUF_SSTL18_II_DCI ----- +component OBUF_SSTL18_II_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_SSTL18_II_DCI : component is "PRIMITIVE"; + +----- component OBUF_SSTL18_II ----- +component OBUF_SSTL18_II + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_SSTL18_II : component is "PRIMITIVE"; + +----- component OBUF_SSTL18_I ----- +component OBUF_SSTL18_I + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_SSTL18_I : component is "PRIMITIVE"; + +----- component OBUF_SSTL2_I_DCI ----- +component OBUF_SSTL2_I_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_SSTL2_I_DCI : component is "PRIMITIVE"; + +----- component OBUF_SSTL2_II_DCI ----- +component OBUF_SSTL2_II_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_SSTL2_II_DCI : component is "PRIMITIVE"; + +----- component OBUF_SSTL2_II ----- +component OBUF_SSTL2_II + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_SSTL2_II : component is "PRIMITIVE"; + +----- component OBUF_SSTL2_I ----- +component OBUF_SSTL2_I + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_SSTL2_I : component is "PRIMITIVE"; + +----- component OBUF_SSTL3_I_DCI ----- +component OBUF_SSTL3_I_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_SSTL3_I_DCI : component is "PRIMITIVE"; + +----- component OBUF_SSTL3_II_DCI ----- +component OBUF_SSTL3_II_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_SSTL3_II_DCI : component is "PRIMITIVE"; + +----- component OBUF_SSTL3_II ----- +component OBUF_SSTL3_II + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_SSTL3_II : component is "PRIMITIVE"; + +----- component OBUF_SSTL3_I ----- +component OBUF_SSTL3_I + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF_SSTL3_I : component is "PRIMITIVE"; + +----- component OBUFT_AGP ----- +component OBUFT_AGP + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_AGP : component is "PRIMITIVE"; + +----- component OBUFT_CTT ----- +component OBUFT_CTT + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_CTT : component is "PRIMITIVE"; + +----- component OBUFTDS_BLVDS_25 ----- +component OBUFTDS_BLVDS_25 + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFTDS_BLVDS_25 : component is "PRIMITIVE"; + +----- component OBUFTDS_LDT_25 ----- +component OBUFTDS_LDT_25 + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFTDS_LDT_25 : component is "PRIMITIVE"; + +----- component OBUFTDS_LVDS_25 ----- +component OBUFTDS_LVDS_25 + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFTDS_LVDS_25 : component is "PRIMITIVE"; + +----- component OBUFTDS_LVDS_33 ----- +component OBUFTDS_LVDS_33 + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFTDS_LVDS_33 : component is "PRIMITIVE"; + +----- component OBUFTDS_LVDSEXT_25 ----- +component OBUFTDS_LVDSEXT_25 + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFTDS_LVDSEXT_25 : component is "PRIMITIVE"; + +----- component OBUFTDS_LVDSEXT_33 ----- +component OBUFTDS_LVDSEXT_33 + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFTDS_LVDSEXT_33 : component is "PRIMITIVE"; + +----- component OBUFTDS_LVPECL_25 ----- +component OBUFTDS_LVPECL_25 + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFTDS_LVPECL_25 : component is "PRIMITIVE"; + +----- component OBUFTDS_LVPECL_33 ----- +component OBUFTDS_LVPECL_33 + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFTDS_LVPECL_33 : component is "PRIMITIVE"; + +----- component OBUFTDS_ULVDS_25 ----- +component OBUFTDS_ULVDS_25 + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFTDS_ULVDS_25 : component is "PRIMITIVE"; + +----- component OBUFTDS ----- +component OBUFTDS + generic + ( + CAPACITANCE : string := "DONT_CARE"; + IOSTANDARD : string := "DEFAULT" + ); + port + ( + O : out std_ulogic; + OB : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFTDS : component is "PRIMITIVE"; + +----- component OBUFT_F_12 ----- +component OBUFT_F_12 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_F_12 : component is "PRIMITIVE"; + +----- component OBUFT_F_16 ----- +component OBUFT_F_16 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_F_16 : component is "PRIMITIVE"; + +----- component OBUFT_F_24 ----- +component OBUFT_F_24 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_F_24 : component is "PRIMITIVE"; + +----- component OBUFT_F_2 ----- +component OBUFT_F_2 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_F_2 : component is "PRIMITIVE"; + +----- component OBUFT_F_4 ----- +component OBUFT_F_4 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_F_4 : component is "PRIMITIVE"; + +----- component OBUFT_F_6 ----- +component OBUFT_F_6 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_F_6 : component is "PRIMITIVE"; + +----- component OBUFT_F_8 ----- +component OBUFT_F_8 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_F_8 : component is "PRIMITIVE"; + +----- component OBUFT_GTL_DCI ----- +component OBUFT_GTL_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_GTL_DCI : component is "PRIMITIVE"; + +----- component OBUFT_GTLP_DCI ----- +component OBUFT_GTLP_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_GTLP_DCI : component is "PRIMITIVE"; + +----- component OBUFT_GTLP ----- +component OBUFT_GTLP + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_GTLP : component is "PRIMITIVE"; + +----- component OBUFT_GTL ----- +component OBUFT_GTL + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_GTL : component is "PRIMITIVE"; + +----- component OBUFT_HSTL_I_18 ----- +component OBUFT_HSTL_I_18 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_HSTL_I_18 : component is "PRIMITIVE"; + +----- component OBUFT_HSTL_I_DCI_18 ----- +component OBUFT_HSTL_I_DCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_HSTL_I_DCI_18 : component is "PRIMITIVE"; + +----- component OBUFT_HSTL_I_DCI ----- +component OBUFT_HSTL_I_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_HSTL_I_DCI : component is "PRIMITIVE"; + +----- component OBUFT_HSTL_II_18 ----- +component OBUFT_HSTL_II_18 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_HSTL_II_18 : component is "PRIMITIVE"; + +----- component OBUFT_HSTL_II_DCI_18 ----- +component OBUFT_HSTL_II_DCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_HSTL_II_DCI_18 : component is "PRIMITIVE"; + +----- component OBUFT_HSTL_II_DCI ----- +component OBUFT_HSTL_II_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_HSTL_II_DCI : component is "PRIMITIVE"; + +----- component OBUFT_HSTL_III_18 ----- +component OBUFT_HSTL_III_18 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_HSTL_III_18 : component is "PRIMITIVE"; + +----- component OBUFT_HSTL_III_DCI_18 ----- +component OBUFT_HSTL_III_DCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_HSTL_III_DCI_18 : component is "PRIMITIVE"; + +----- component OBUFT_HSTL_III_DCI ----- +component OBUFT_HSTL_III_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_HSTL_III_DCI : component is "PRIMITIVE"; + +----- component OBUFT_HSTL_III ----- +component OBUFT_HSTL_III + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_HSTL_III : component is "PRIMITIVE"; + +----- component OBUFT_HSTL_II ----- +component OBUFT_HSTL_II + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_HSTL_II : component is "PRIMITIVE"; + +----- component OBUFT_HSTL_IV_18 ----- +component OBUFT_HSTL_IV_18 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_HSTL_IV_18 : component is "PRIMITIVE"; + +----- component OBUFT_HSTL_IV_DCI_18 ----- +component OBUFT_HSTL_IV_DCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_HSTL_IV_DCI_18 : component is "PRIMITIVE"; + +----- component OBUFT_HSTL_IV_DCI ----- +component OBUFT_HSTL_IV_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_HSTL_IV_DCI : component is "PRIMITIVE"; + +----- component OBUFT_HSTL_I ----- +component OBUFT_HSTL_I + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_HSTL_I : component is "PRIMITIVE"; + +----- component OBUFT_HSTL_IV ----- +component OBUFT_HSTL_IV + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_HSTL_IV : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS12_F_2 ----- +component OBUFT_LVCMOS12_F_2 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS12_F_2 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS12_F_4 ----- +component OBUFT_LVCMOS12_F_4 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS12_F_4 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS12_F_6 ----- +component OBUFT_LVCMOS12_F_6 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS12_F_6 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS12_F_8 ----- +component OBUFT_LVCMOS12_F_8 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS12_F_8 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS12_S_2 ----- +component OBUFT_LVCMOS12_S_2 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS12_S_2 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS12_S_4 ----- +component OBUFT_LVCMOS12_S_4 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS12_S_4 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS12_S_6 ----- +component OBUFT_LVCMOS12_S_6 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS12_S_6 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS12_S_8 ----- +component OBUFT_LVCMOS12_S_8 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS12_S_8 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS12 ----- +component OBUFT_LVCMOS12 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS12 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS15_F_12 ----- +component OBUFT_LVCMOS15_F_12 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS15_F_12 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS15_F_16 ----- +component OBUFT_LVCMOS15_F_16 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS15_F_16 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS15_F_2 ----- +component OBUFT_LVCMOS15_F_2 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS15_F_2 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS15_F_4 ----- +component OBUFT_LVCMOS15_F_4 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS15_F_4 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS15_F_6 ----- +component OBUFT_LVCMOS15_F_6 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS15_F_6 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS15_F_8 ----- +component OBUFT_LVCMOS15_F_8 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS15_F_8 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS15_S_12 ----- +component OBUFT_LVCMOS15_S_12 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS15_S_12 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS15_S_16 ----- +component OBUFT_LVCMOS15_S_16 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS15_S_16 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS15_S_2 ----- +component OBUFT_LVCMOS15_S_2 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS15_S_2 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS15_S_4 ----- +component OBUFT_LVCMOS15_S_4 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS15_S_4 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS15_S_6 ----- +component OBUFT_LVCMOS15_S_6 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS15_S_6 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS15_S_8 ----- +component OBUFT_LVCMOS15_S_8 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS15_S_8 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS15 ----- +component OBUFT_LVCMOS15 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS15 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS18_F_12 ----- +component OBUFT_LVCMOS18_F_12 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS18_F_12 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS18_F_16 ----- +component OBUFT_LVCMOS18_F_16 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS18_F_16 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS18_F_2 ----- +component OBUFT_LVCMOS18_F_2 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS18_F_2 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS18_F_4 ----- +component OBUFT_LVCMOS18_F_4 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS18_F_4 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS18_F_6 ----- +component OBUFT_LVCMOS18_F_6 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS18_F_6 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS18_F_8 ----- +component OBUFT_LVCMOS18_F_8 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS18_F_8 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS18_S_12 ----- +component OBUFT_LVCMOS18_S_12 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS18_S_12 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS18_S_16 ----- +component OBUFT_LVCMOS18_S_16 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS18_S_16 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS18_S_2 ----- +component OBUFT_LVCMOS18_S_2 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS18_S_2 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS18_S_4 ----- +component OBUFT_LVCMOS18_S_4 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS18_S_4 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS18_S_6 ----- +component OBUFT_LVCMOS18_S_6 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS18_S_6 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS18_S_8 ----- +component OBUFT_LVCMOS18_S_8 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS18_S_8 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS18 ----- +component OBUFT_LVCMOS18 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS18 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS25_F_12 ----- +component OBUFT_LVCMOS25_F_12 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS25_F_12 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS25_F_16 ----- +component OBUFT_LVCMOS25_F_16 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS25_F_16 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS25_F_24 ----- +component OBUFT_LVCMOS25_F_24 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS25_F_24 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS25_F_2 ----- +component OBUFT_LVCMOS25_F_2 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS25_F_2 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS25_F_4 ----- +component OBUFT_LVCMOS25_F_4 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS25_F_4 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS25_F_6 ----- +component OBUFT_LVCMOS25_F_6 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS25_F_6 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS25_F_8 ----- +component OBUFT_LVCMOS25_F_8 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS25_F_8 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS25_S_12 ----- +component OBUFT_LVCMOS25_S_12 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS25_S_12 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS25_S_16 ----- +component OBUFT_LVCMOS25_S_16 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS25_S_16 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS25_S_24 ----- +component OBUFT_LVCMOS25_S_24 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS25_S_24 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS25_S_2 ----- +component OBUFT_LVCMOS25_S_2 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS25_S_2 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS25_S_4 ----- +component OBUFT_LVCMOS25_S_4 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS25_S_4 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS25_S_6 ----- +component OBUFT_LVCMOS25_S_6 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS25_S_6 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS25_S_8 ----- +component OBUFT_LVCMOS25_S_8 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS25_S_8 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS25 ----- +component OBUFT_LVCMOS25 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS25 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS2 ----- +component OBUFT_LVCMOS2 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS2 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS33_F_12 ----- +component OBUFT_LVCMOS33_F_12 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS33_F_12 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS33_F_16 ----- +component OBUFT_LVCMOS33_F_16 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS33_F_16 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS33_F_24 ----- +component OBUFT_LVCMOS33_F_24 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS33_F_24 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS33_F_2 ----- +component OBUFT_LVCMOS33_F_2 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS33_F_2 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS33_F_4 ----- +component OBUFT_LVCMOS33_F_4 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS33_F_4 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS33_F_6 ----- +component OBUFT_LVCMOS33_F_6 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS33_F_6 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS33_F_8 ----- +component OBUFT_LVCMOS33_F_8 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS33_F_8 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS33_S_12 ----- +component OBUFT_LVCMOS33_S_12 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS33_S_12 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS33_S_16 ----- +component OBUFT_LVCMOS33_S_16 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS33_S_16 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS33_S_24 ----- +component OBUFT_LVCMOS33_S_24 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS33_S_24 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS33_S_2 ----- +component OBUFT_LVCMOS33_S_2 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS33_S_2 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS33_S_4 ----- +component OBUFT_LVCMOS33_S_4 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS33_S_4 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS33_S_6 ----- +component OBUFT_LVCMOS33_S_6 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS33_S_6 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS33_S_8 ----- +component OBUFT_LVCMOS33_S_8 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS33_S_8 : component is "PRIMITIVE"; + +----- component OBUFT_LVCMOS33 ----- +component OBUFT_LVCMOS33 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVCMOS33 : component is "PRIMITIVE"; + +----- component OBUFT_LVDCI_15 ----- +component OBUFT_LVDCI_15 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVDCI_15 : component is "PRIMITIVE"; + +----- component OBUFT_LVDCI_18 ----- +component OBUFT_LVDCI_18 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVDCI_18 : component is "PRIMITIVE"; + +----- component OBUFT_LVDCI_25 ----- +component OBUFT_LVDCI_25 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVDCI_25 : component is "PRIMITIVE"; + +----- component OBUFT_LVDCI_33 ----- +component OBUFT_LVDCI_33 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVDCI_33 : component is "PRIMITIVE"; + +----- component OBUFT_LVDCI_DV2_15 ----- +component OBUFT_LVDCI_DV2_15 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVDCI_DV2_15 : component is "PRIMITIVE"; + +----- component OBUFT_LVDCI_DV2_18 ----- +component OBUFT_LVDCI_DV2_18 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVDCI_DV2_18 : component is "PRIMITIVE"; + +----- component OBUFT_LVDCI_DV2_25 ----- +component OBUFT_LVDCI_DV2_25 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVDCI_DV2_25 : component is "PRIMITIVE"; + +----- component OBUFT_LVDCI_DV2_33 ----- +component OBUFT_LVDCI_DV2_33 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVDCI_DV2_33 : component is "PRIMITIVE"; + +----- component OBUFT_LVDS ----- +component OBUFT_LVDS + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVDS : component is "PRIMITIVE"; + +----- component OBUFT_LVPECL ----- +component OBUFT_LVPECL + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVPECL : component is "PRIMITIVE"; + +----- component OBUFT_LVTTL_F_12 ----- +component OBUFT_LVTTL_F_12 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVTTL_F_12 : component is "PRIMITIVE"; + +----- component OBUFT_LVTTL_F_16 ----- +component OBUFT_LVTTL_F_16 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVTTL_F_16 : component is "PRIMITIVE"; + +----- component OBUFT_LVTTL_F_24 ----- +component OBUFT_LVTTL_F_24 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVTTL_F_24 : component is "PRIMITIVE"; + +----- component OBUFT_LVTTL_F_2 ----- +component OBUFT_LVTTL_F_2 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVTTL_F_2 : component is "PRIMITIVE"; + +----- component OBUFT_LVTTL_F_4 ----- +component OBUFT_LVTTL_F_4 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVTTL_F_4 : component is "PRIMITIVE"; + +----- component OBUFT_LVTTL_F_6 ----- +component OBUFT_LVTTL_F_6 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVTTL_F_6 : component is "PRIMITIVE"; + +----- component OBUFT_LVTTL_F_8 ----- +component OBUFT_LVTTL_F_8 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVTTL_F_8 : component is "PRIMITIVE"; + +----- component OBUFT_LVTTL_S_12 ----- +component OBUFT_LVTTL_S_12 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVTTL_S_12 : component is "PRIMITIVE"; + +----- component OBUFT_LVTTL_S_16 ----- +component OBUFT_LVTTL_S_16 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVTTL_S_16 : component is "PRIMITIVE"; + +----- component OBUFT_LVTTL_S_24 ----- +component OBUFT_LVTTL_S_24 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVTTL_S_24 : component is "PRIMITIVE"; + +----- component OBUFT_LVTTL_S_2 ----- +component OBUFT_LVTTL_S_2 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVTTL_S_2 : component is "PRIMITIVE"; + +----- component OBUFT_LVTTL_S_4 ----- +component OBUFT_LVTTL_S_4 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVTTL_S_4 : component is "PRIMITIVE"; + +----- component OBUFT_LVTTL_S_6 ----- +component OBUFT_LVTTL_S_6 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVTTL_S_6 : component is "PRIMITIVE"; + +----- component OBUFT_LVTTL_S_8 ----- +component OBUFT_LVTTL_S_8 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVTTL_S_8 : component is "PRIMITIVE"; + +----- component OBUFT_LVTTL ----- +component OBUFT_LVTTL + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_LVTTL : component is "PRIMITIVE"; + +----- component OBUFT_PCI33_3 ----- +component OBUFT_PCI33_3 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_PCI33_3 : component is "PRIMITIVE"; + +----- component OBUFT_PCI33_5 ----- +component OBUFT_PCI33_5 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_PCI33_5 : component is "PRIMITIVE"; + +----- component OBUFT_PCI66_3 ----- +component OBUFT_PCI66_3 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_PCI66_3 : component is "PRIMITIVE"; + +----- component OBUFT_PCIX66_3 ----- +component OBUFT_PCIX66_3 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_PCIX66_3 : component is "PRIMITIVE"; + +----- component OBUFT_PCIX ----- +component OBUFT_PCIX + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_PCIX : component is "PRIMITIVE"; + +----- component OBUFT_S_12 ----- +component OBUFT_S_12 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_S_12 : component is "PRIMITIVE"; + +----- component OBUFT_S_16 ----- +component OBUFT_S_16 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_S_16 : component is "PRIMITIVE"; + +----- component OBUFT_S_24 ----- +component OBUFT_S_24 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_S_24 : component is "PRIMITIVE"; + +----- component OBUFT_S_2 ----- +component OBUFT_S_2 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_S_2 : component is "PRIMITIVE"; + +----- component OBUFT_S_4 ----- +component OBUFT_S_4 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_S_4 : component is "PRIMITIVE"; + +----- component OBUFT_S_6 ----- +component OBUFT_S_6 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_S_6 : component is "PRIMITIVE"; + +----- component OBUFT_S_8 ----- +component OBUFT_S_8 + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_S_8 : component is "PRIMITIVE"; + +----- component OBUFT_SSTL18_I_DCI ----- +component OBUFT_SSTL18_I_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_SSTL18_I_DCI : component is "PRIMITIVE"; + +----- component OBUFT_SSTL18_II_DCI ----- +component OBUFT_SSTL18_II_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_SSTL18_II_DCI : component is "PRIMITIVE"; + +----- component OBUFT_SSTL18_II ----- +component OBUFT_SSTL18_II + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_SSTL18_II : component is "PRIMITIVE"; + +----- component OBUFT_SSTL18_I ----- +component OBUFT_SSTL18_I + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_SSTL18_I : component is "PRIMITIVE"; + +----- component OBUFT_SSTL2_I_DCI ----- +component OBUFT_SSTL2_I_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_SSTL2_I_DCI : component is "PRIMITIVE"; + +----- component OBUFT_SSTL2_II_DCI ----- +component OBUFT_SSTL2_II_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_SSTL2_II_DCI : component is "PRIMITIVE"; + +----- component OBUFT_SSTL2_II ----- +component OBUFT_SSTL2_II + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_SSTL2_II : component is "PRIMITIVE"; + +----- component OBUFT_SSTL2_I ----- +component OBUFT_SSTL2_I + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_SSTL2_I : component is "PRIMITIVE"; + +----- component OBUFT_SSTL3_I_DCI ----- +component OBUFT_SSTL3_I_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_SSTL3_I_DCI : component is "PRIMITIVE"; + +----- component OBUFT_SSTL3_II_DCI ----- +component OBUFT_SSTL3_II_DCI + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_SSTL3_II_DCI : component is "PRIMITIVE"; + +----- component OBUFT_SSTL3_II ----- +component OBUFT_SSTL3_II + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_SSTL3_II : component is "PRIMITIVE"; + +----- component OBUFT_SSTL3_I ----- +component OBUFT_SSTL3_I + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT_SSTL3_I : component is "PRIMITIVE"; + +----- component OBUFT ----- +component OBUFT + generic + ( + CAPACITANCE : string := "DONT_CARE"; + DRIVE : integer := 12; + IOSTANDARD : string := "DEFAULT"; + SLEW : string := "SLOW" + ); + port + ( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUFT : component is "PRIMITIVE"; + +----- component OBUF ----- +component OBUF + generic + ( + CAPACITANCE : string := "DONT_CARE"; + DRIVE : integer := 12; + IOSTANDARD : string := "DEFAULT"; + SLEW : string := "SLOW" + ); + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OBUF : component is "PRIMITIVE"; + +----- component ODDR2 ----- +component ODDR2 + generic + ( + DDR_ALIGNMENT : string := "NONE"; + INIT : bit := '0'; + SRTYPE : string := "SYNC" + ); + port + ( + Q : out std_ulogic; + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + ODDR2 : component is "PRIMITIVE"; + +----- component ODDR ----- +component ODDR + generic + ( + DDR_CLK_EDGE : string := "OPPOSITE_EDGE"; + INIT : bit := '0'; + SRTYPE : string := "SYNC" + ); + port + ( + Q : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + D1 : in std_ulogic; + D2 : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + ODDR : component is "PRIMITIVE"; + +----- component OFDDRCPE ----- +component OFDDRCPE + port + ( + Q : out std_ulogic; + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + CLR : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + PRE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OFDDRCPE : component is "PRIMITIVE"; + +----- component OFDDRRSE ----- +component OFDDRRSE + port + ( + Q : out std_ulogic; + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OFDDRRSE : component is "PRIMITIVE"; + +----- component OFDDRTCPE ----- +component OFDDRTCPE + port + ( + O : out std_ulogic; + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + CLR : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + PRE : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OFDDRTCPE : component is "PRIMITIVE"; + +----- component OFDDRTRSE ----- +component OFDDRTRSE + port + ( + O : out std_ulogic; + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic; + T : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OFDDRTRSE : component is "PRIMITIVE"; + +----- component OPT_OFF ----- +component OPT_OFF + port + ( + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OPT_OFF : component is "PRIMITIVE"; + +----- component OPT_UIM ----- +component OPT_UIM + port + ( + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OPT_UIM : component is "PRIMITIVE"; + +----- component OR2B1 ----- +component OR2B1 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR2B1 : component is "PRIMITIVE"; + +----- component OR2B2 ----- +component OR2B2 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR2B2 : component is "PRIMITIVE"; + +----- component OR2 ----- +component OR2 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR2 : component is "PRIMITIVE"; + +----- component OR3B1 ----- +component OR3B1 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR3B1 : component is "PRIMITIVE"; + +----- component OR3B2 ----- +component OR3B2 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR3B2 : component is "PRIMITIVE"; + +----- component OR3B3 ----- +component OR3B3 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR3B3 : component is "PRIMITIVE"; + +----- component OR3 ----- +component OR3 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR3 : component is "PRIMITIVE"; + +----- component OR4B1 ----- +component OR4B1 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR4B1 : component is "PRIMITIVE"; + +----- component OR4B2 ----- +component OR4B2 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR4B2 : component is "PRIMITIVE"; + +----- component OR4B3 ----- +component OR4B3 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR4B3 : component is "PRIMITIVE"; + +----- component OR4B4 ----- +component OR4B4 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR4B4 : component is "PRIMITIVE"; + +----- component OR4 ----- +component OR4 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR4 : component is "PRIMITIVE"; + +----- component OR5B1 ----- +component OR5B1 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR5B1 : component is "PRIMITIVE"; + +----- component OR5B2 ----- +component OR5B2 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR5B2 : component is "PRIMITIVE"; + +----- component OR5B3 ----- +component OR5B3 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR5B3 : component is "PRIMITIVE"; + +----- component OR5B4 ----- +component OR5B4 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR5B4 : component is "PRIMITIVE"; + +----- component OR5B5 ----- +component OR5B5 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR5B5 : component is "PRIMITIVE"; + +----- component OR5 ----- +component OR5 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR5 : component is "PRIMITIVE"; + +----- component OR6 ----- +component OR6 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR6 : component is "PRIMITIVE"; + +----- component OR7 ----- +component OR7 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic; + I6 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR7 : component is "PRIMITIVE"; + +----- component OR8 ----- +component OR8 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic; + I6 : in std_ulogic; + I7 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OR8 : component is "PRIMITIVE"; + +----- component ORCY ----- +component ORCY + port + ( + O : out std_ulogic; + CI : in std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + ORCY : component is "PRIMITIVE"; + +----- component OSERDES ----- +component OSERDES + generic + ( + DATA_RATE_OQ : string := "DDR"; + DATA_RATE_TQ : string := "DDR"; + DATA_WIDTH : integer := 4; + INIT_OQ : bit := '0'; + INIT_TQ : bit := '0'; + SERDES_MODE : string := "MASTER"; + SRVAL_OQ : bit := '0'; + SRVAL_TQ : bit := '0'; + TRISTATE_WIDTH : integer := 4 + ); + port + ( + OQ : out std_ulogic; + SHIFTOUT1 : out std_ulogic; + SHIFTOUT2 : out std_ulogic; + TQ : out std_ulogic; + CLK : in std_ulogic; + CLKDIV : in std_ulogic; + D1 : in std_ulogic; + D2 : in std_ulogic; + D3 : in std_ulogic; + D4 : in std_ulogic; + D5 : in std_ulogic; + D6 : in std_ulogic; + OCE : in std_ulogic; + REV : in std_ulogic; + SHIFTIN1 : in std_ulogic; + SHIFTIN2 : in std_ulogic; + SR : in std_ulogic; + T1 : in std_ulogic; + T2 : in std_ulogic; + T3 : in std_ulogic; + T4 : in std_ulogic; + TCE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + OSERDES : component is "PRIMITIVE"; + +----- component PCIE_EP ----- +component PCIE_EP + generic + ( + ACTIVELANESIN : bit_vector := X"01"; + AERBASEPTR : bit_vector := X"110"; + AERCAPABILITYNEXTPTR : bit_vector := X"138"; + BAR0ADDRWIDTH : integer := 0; + BAR0EXIST : boolean := TRUE; + BAR0IOMEMN : integer := 0; + BAR0MASKWIDTH : bit_vector := X"14"; + BAR0PREFETCHABLE : boolean := TRUE; + BAR1ADDRWIDTH : integer := 0; + BAR1EXIST : boolean := FALSE; + BAR1IOMEMN : integer := 0; + BAR1MASKWIDTH : bit_vector := X"00"; + BAR1PREFETCHABLE : boolean := FALSE; + BAR2ADDRWIDTH : integer := 0; + BAR2EXIST : boolean := FALSE; + BAR2IOMEMN : integer := 0; + BAR2MASKWIDTH : bit_vector := X"00"; + BAR2PREFETCHABLE : boolean := FALSE; + BAR3ADDRWIDTH : integer := 0; + BAR3EXIST : boolean := FALSE; + BAR3IOMEMN : integer := 0; + BAR3MASKWIDTH : bit_vector := X"00"; + BAR3PREFETCHABLE : boolean := FALSE; + BAR4ADDRWIDTH : integer := 0; + BAR4EXIST : boolean := FALSE; + BAR4IOMEMN : integer := 0; + BAR4MASKWIDTH : bit_vector := X"00"; + BAR4PREFETCHABLE : boolean := FALSE; + BAR5EXIST : boolean := FALSE; + BAR5IOMEMN : integer := 0; + BAR5MASKWIDTH : bit_vector := X"00"; + BAR5PREFETCHABLE : boolean := FALSE; + CAPABILITIESPOINTER : bit_vector := X"40"; + CARDBUSCISPOINTER : bit_vector := X"00000000"; + CLASSCODE : bit_vector := X"058000"; + CLKDIVIDED : boolean := FALSE; + DEVICECAPABILITYENDPOINTL0SLATENCY : bit_vector := X"0"; + DEVICECAPABILITYENDPOINTL1LATENCY : bit_vector := X"0"; + DEVICEID : bit_vector := X"5050"; + DEVICESERIALNUMBER : bit_vector := X"E000000001000A35"; + DSNBASEPTR : bit_vector := X"148"; + DSNCAPABILITYNEXTPTR : bit_vector := X"154"; + INFINITECOMPLETIONS : boolean := TRUE; + INTERRUPTPIN : bit_vector := X"00"; + L0SEXITLATENCY : integer := 7; + L0SEXITLATENCYCOMCLK : integer := 7; + L1EXITLATENCY : integer := 7; + L1EXITLATENCYCOMCLK : integer := 7; + LINKCAPABILITYASPMSUPPORT : bit_vector := X"1"; + LINKCAPABILITYMAXLINKWIDTH : bit_vector := X"01"; + LINKSTATUSSLOTCLOCKCONFIG : boolean := FALSE; + LOWPRIORITYVCCOUNT : integer := 0; + MSIBASEPTR : bit_vector := X"048"; + MSICAPABILITYMULTIMSGCAP : bit_vector := X"0"; + MSICAPABILITYNEXTPTR : bit_vector := X"60"; + PBBASEPTR : bit_vector := X"138"; + PBCAPABILITYDW0BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW0DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW0PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW0PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW0POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW0TYPE : bit_vector := X"0"; + PBCAPABILITYDW1BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW1DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW1PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW1PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW1POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW1TYPE : bit_vector := X"0"; + PBCAPABILITYDW2BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW2DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW2PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW2PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW2POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW2TYPE : bit_vector := X"0"; + PBCAPABILITYDW3BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW3DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW3PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW3PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW3POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW3TYPE : bit_vector := X"0"; + PBCAPABILITYNEXTPTR : bit_vector := X"148"; + PBCAPABILITYSYSTEMALLOCATED : boolean := FALSE; + PCIECAPABILITYNEXTPTR : bit_vector := X"00"; + PMBASEPTR : bit_vector := X"040"; + PMCAPABILITYAUXCURRENT : bit_vector := X"0"; + PMCAPABILITYD1SUPPORT : boolean := FALSE; + PMCAPABILITYD2SUPPORT : boolean := FALSE; + PMCAPABILITYDSI : boolean := TRUE; + PMCAPABILITYNEXTPTR : bit_vector := X"60"; + PMCAPABILITYPMESUPPORT : bit_vector := X"00"; + PMDATA0 : bit_vector := X"00"; + PMDATA1 : bit_vector := X"00"; + PMDATA2 : bit_vector := X"00"; + PMDATA3 : bit_vector := X"00"; + PMDATA4 : bit_vector := X"00"; + PMDATA5 : bit_vector := X"00"; + PMDATA6 : bit_vector := X"00"; + PMDATA7 : bit_vector := X"00"; + PMDATASCALE0 : integer := 0; + PMDATASCALE1 : integer := 0; + PMDATASCALE2 : integer := 0; + PMDATASCALE3 : integer := 0; + PMDATASCALE4 : integer := 0; + PMDATASCALE5 : integer := 0; + PMDATASCALE6 : integer := 0; + PMDATASCALE7 : integer := 0; + PORTVCCAPABILITYEXTENDEDVCCOUNT : bit_vector := X"0"; + PORTVCCAPABILITYVCARBCAP : bit_vector := X"00"; + PORTVCCAPABILITYVCARBTABLEOFFSET : bit_vector := X"00"; + RESETMODE : boolean := FALSE; + RETRYRAMREADLATENCY : integer := 3; + RETRYRAMSIZE : bit_vector := X"009"; + RETRYRAMWRITELATENCY : integer := 1; + REVISIONID : bit_vector := X"00"; + SUBSYSTEMID : bit_vector := X"5050"; + SUBSYSTEMVENDORID : bit_vector := X"10EE"; + TLRAMREADLATENCY : integer := 3; + TLRAMWRITELATENCY : integer := 1; + TXTSNFTS : integer := 255; + TXTSNFTSCOMCLK : integer := 255; + VC0RXFIFOBASEC : bit_vector := X"0098"; + VC0RXFIFOBASENP : bit_vector := X"0080"; + VC0RXFIFOBASEP : bit_vector := X"0000"; + VC0RXFIFOLIMITC : bit_vector := X"0117"; + VC0RXFIFOLIMITNP : bit_vector := X"0097"; + VC0RXFIFOLIMITP : bit_vector := X"007f"; + VC0TOTALCREDITSCD : bit_vector := X"000"; + VC0TOTALCREDITSCH : bit_vector := X"00"; + VC0TOTALCREDITSNPH : bit_vector := X"08"; + VC0TOTALCREDITSPD : bit_vector := X"034"; + VC0TOTALCREDITSPH : bit_vector := X"08"; + VC0TXFIFOBASEC : bit_vector := X"0098"; + VC0TXFIFOBASENP : bit_vector := X"0080"; + VC0TXFIFOBASEP : bit_vector := X"0000"; + VC0TXFIFOLIMITC : bit_vector := X"0117"; + VC0TXFIFOLIMITNP : bit_vector := X"0097"; + VC0TXFIFOLIMITP : bit_vector := X"007f"; + VC1RXFIFOBASEC : bit_vector := X"0118"; + VC1RXFIFOBASENP : bit_vector := X"0118"; + VC1RXFIFOBASEP : bit_vector := X"0118"; + VC1RXFIFOLIMITC : bit_vector := X"0118"; + VC1RXFIFOLIMITNP : bit_vector := X"0118"; + VC1RXFIFOLIMITP : bit_vector := X"0118"; + VC1TOTALCREDITSCD : bit_vector := X"000"; + VC1TOTALCREDITSCH : bit_vector := X"00"; + VC1TOTALCREDITSNPH : bit_vector := X"00"; + VC1TOTALCREDITSPD : bit_vector := X"000"; + VC1TOTALCREDITSPH : bit_vector := X"00"; + VC1TXFIFOBASEC : bit_vector := X"0118"; + VC1TXFIFOBASENP : bit_vector := X"0118"; + VC1TXFIFOBASEP : bit_vector := X"0118"; + VC1TXFIFOLIMITC : bit_vector := X"0118"; + VC1TXFIFOLIMITNP : bit_vector := X"0118"; + VC1TXFIFOLIMITP : bit_vector := X"0118"; + VCBASEPTR : bit_vector := X"154"; + VCCAPABILITYNEXTPTR : bit_vector := X"000"; + VENDORID : bit_vector := X"10EE"; + XPBASEPTR : bit_vector := X"60"; + XPDEVICEPORTTYPE : bit_vector := X"0"; + XPMAXPAYLOAD : integer := 0 + ); + port + ( + BUSMASTERENABLE : out std_ulogic; + CRMDOHOTRESETN : out std_ulogic; + CRMPWRSOFTRESETN : out std_ulogic; + DLLTXPMDLLPOUTSTANDING : out std_ulogic; + INTERRUPTDISABLE : out std_ulogic; + IOSPACEENABLE : out std_ulogic; + L0CFGLOOPBACKACK : out std_ulogic; + L0COMPLETERID : out std_logic_vector(12 downto 0); + L0DLLERRORVECTOR : out std_logic_vector(6 downto 0); + L0DLLRXACKOUTSTANDING : out std_ulogic; + L0DLLTXNONFCOUTSTANDING : out std_ulogic; + L0DLLTXOUTSTANDING : out std_ulogic; + L0DLLVCSTATUS : out std_logic_vector(7 downto 0); + L0DLUPDOWN : out std_logic_vector(7 downto 0); + L0FIRSTCFGWRITEOCCURRED : out std_ulogic; + L0LTSSMSTATE : out std_logic_vector(3 downto 0); + L0MACENTEREDL0 : out std_ulogic; + L0MACLINKTRAINING : out std_ulogic; + L0MACLINKUP : out std_ulogic; + L0MACNEGOTIATEDLINKWIDTH : out std_logic_vector(3 downto 0); + L0MACNEWSTATEACK : out std_ulogic; + L0MACRXL0SSTATE : out std_ulogic; + L0MSIENABLE0 : out std_ulogic; + L0MULTIMSGEN0 : out std_logic_vector(2 downto 0); + L0PMEACK : out std_ulogic; + L0PMEEN : out std_ulogic; + L0PMEREQOUT : out std_ulogic; + L0PWRL1STATE : out std_ulogic; + L0PWRL23READYSTATE : out std_ulogic; + L0PWRSTATE0 : out std_logic_vector(1 downto 0); + L0PWRTURNOFFREQ : out std_ulogic; + L0PWRTXL0SSTATE : out std_ulogic; + L0RXDLLPM : out std_ulogic; + L0RXDLLPMTYPE : out std_logic_vector(2 downto 0); + L0RXMACLINKERROR : out std_logic_vector(1 downto 0); + L0STATSCFGOTHERRECEIVED : out std_ulogic; + L0STATSCFGOTHERTRANSMITTED : out std_ulogic; + L0STATSCFGRECEIVED : out std_ulogic; + L0STATSCFGTRANSMITTED : out std_ulogic; + L0STATSDLLPRECEIVED : out std_ulogic; + L0STATSDLLPTRANSMITTED : out std_ulogic; + L0STATSOSRECEIVED : out std_ulogic; + L0STATSOSTRANSMITTED : out std_ulogic; + L0STATSTLPRECEIVED : out std_ulogic; + L0STATSTLPTRANSMITTED : out std_ulogic; + L0UNLOCKRECEIVED : out std_ulogic; + LLKRXCHCOMPLETIONAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHNONPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXDATA : out std_logic_vector(63 downto 0); + LLKRXEOFN : out std_ulogic; + LLKRXEOPN : out std_ulogic; + LLKRXPREFERREDTYPE : out std_logic_vector(15 downto 0); + LLKRXSOFN : out std_ulogic; + LLKRXSOPN : out std_ulogic; + LLKRXSRCLASTREQN : out std_ulogic; + LLKRXSRCRDYN : out std_ulogic; + LLKRXVALIDN : out std_logic_vector(1 downto 0); + LLKTCSTATUS : out std_logic_vector(7 downto 0); + LLKTXCHANSPACE : out std_logic_vector(9 downto 0); + LLKTXCHCOMPLETIONREADYN : out std_logic_vector(7 downto 0); + LLKTXCHNONPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCHPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCONFIGREADYN : out std_ulogic; + LLKTXDSTRDYN : out std_ulogic; + MAXPAYLOADSIZE : out std_logic_vector(2 downto 0); + MAXREADREQUESTSIZE : out std_logic_vector(2 downto 0); + MEMSPACEENABLE : out std_ulogic; + MGMTPSO : out std_logic_vector(16 downto 0); + MGMTRDATA : out std_logic_vector(31 downto 0); + MGMTSTATSCREDIT : out std_logic_vector(11 downto 0); + MIMDLLBRADD : out std_logic_vector(11 downto 0); + MIMDLLBREN : out std_ulogic; + MIMDLLBWADD : out std_logic_vector(11 downto 0); + MIMDLLBWDATA : out std_logic_vector(63 downto 0); + MIMDLLBWEN : out std_ulogic; + MIMRXBRADD : out std_logic_vector(12 downto 0); + MIMRXBREN : out std_ulogic; + MIMRXBWADD : out std_logic_vector(12 downto 0); + MIMRXBWDATA : out std_logic_vector(63 downto 0); + MIMRXBWEN : out std_ulogic; + MIMTXBRADD : out std_logic_vector(12 downto 0); + MIMTXBREN : out std_ulogic; + MIMTXBWADD : out std_logic_vector(12 downto 0); + MIMTXBWDATA : out std_logic_vector(63 downto 0); + MIMTXBWEN : out std_ulogic; + PARITYERRORRESPONSE : out std_ulogic; + PIPEDESKEWLANESL0 : out std_ulogic; + PIPEDESKEWLANESL1 : out std_ulogic; + PIPEDESKEWLANESL2 : out std_ulogic; + PIPEDESKEWLANESL3 : out std_ulogic; + PIPEDESKEWLANESL4 : out std_ulogic; + PIPEDESKEWLANESL5 : out std_ulogic; + PIPEDESKEWLANESL6 : out std_ulogic; + PIPEDESKEWLANESL7 : out std_ulogic; + PIPEPOWERDOWNL0 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL1 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL2 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL3 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL4 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL5 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL6 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL7 : out std_logic_vector(1 downto 0); + PIPERESETL0 : out std_ulogic; + PIPERESETL1 : out std_ulogic; + PIPERESETL2 : out std_ulogic; + PIPERESETL3 : out std_ulogic; + PIPERESETL4 : out std_ulogic; + PIPERESETL5 : out std_ulogic; + PIPERESETL6 : out std_ulogic; + PIPERESETL7 : out std_ulogic; + PIPERXPOLARITYL0 : out std_ulogic; + PIPERXPOLARITYL1 : out std_ulogic; + PIPERXPOLARITYL2 : out std_ulogic; + PIPERXPOLARITYL3 : out std_ulogic; + PIPERXPOLARITYL4 : out std_ulogic; + PIPERXPOLARITYL5 : out std_ulogic; + PIPERXPOLARITYL6 : out std_ulogic; + PIPERXPOLARITYL7 : out std_ulogic; + PIPETXCOMPLIANCEL0 : out std_ulogic; + PIPETXCOMPLIANCEL1 : out std_ulogic; + PIPETXCOMPLIANCEL2 : out std_ulogic; + PIPETXCOMPLIANCEL3 : out std_ulogic; + PIPETXCOMPLIANCEL4 : out std_ulogic; + PIPETXCOMPLIANCEL5 : out std_ulogic; + PIPETXCOMPLIANCEL6 : out std_ulogic; + PIPETXCOMPLIANCEL7 : out std_ulogic; + PIPETXDATAKL0 : out std_ulogic; + PIPETXDATAKL1 : out std_ulogic; + PIPETXDATAKL2 : out std_ulogic; + PIPETXDATAKL3 : out std_ulogic; + PIPETXDATAKL4 : out std_ulogic; + PIPETXDATAKL5 : out std_ulogic; + PIPETXDATAKL6 : out std_ulogic; + PIPETXDATAKL7 : out std_ulogic; + PIPETXDATAL0 : out std_logic_vector(7 downto 0); + PIPETXDATAL1 : out std_logic_vector(7 downto 0); + PIPETXDATAL2 : out std_logic_vector(7 downto 0); + PIPETXDATAL3 : out std_logic_vector(7 downto 0); + PIPETXDATAL4 : out std_logic_vector(7 downto 0); + PIPETXDATAL5 : out std_logic_vector(7 downto 0); + PIPETXDATAL6 : out std_logic_vector(7 downto 0); + PIPETXDATAL7 : out std_logic_vector(7 downto 0); + PIPETXDETECTRXLOOPBACKL0 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL1 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL2 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL3 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL4 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL5 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL6 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL7 : out std_ulogic; + PIPETXELECIDLEL0 : out std_ulogic; + PIPETXELECIDLEL1 : out std_ulogic; + PIPETXELECIDLEL2 : out std_ulogic; + PIPETXELECIDLEL3 : out std_ulogic; + PIPETXELECIDLEL4 : out std_ulogic; + PIPETXELECIDLEL5 : out std_ulogic; + PIPETXELECIDLEL6 : out std_ulogic; + PIPETXELECIDLEL7 : out std_ulogic; + SERRENABLE : out std_ulogic; + URREPORTINGENABLE : out std_ulogic; + AUXPOWER : in std_ulogic; + COMPLIANCEAVOID : in std_ulogic; + CRMCORECLK : in std_ulogic; + CRMCORECLKDLO : in std_ulogic; + CRMCORECLKRXO : in std_ulogic; + CRMCORECLKTXO : in std_ulogic; + CRMLINKRSTN : in std_ulogic; + CRMMACRSTN : in std_ulogic; + CRMMGMTRSTN : in std_ulogic; + CRMNVRSTN : in std_ulogic; + CRMURSTN : in std_ulogic; + CRMUSERCFGRSTN : in std_ulogic; + CRMUSERCLK : in std_ulogic; + CRMUSERCLKRXO : in std_ulogic; + CRMUSERCLKTXO : in std_ulogic; + L0CFGDISABLESCRAMBLE : in std_ulogic; + L0CFGLOOPBACKMASTER : in std_ulogic; + L0LEGACYINTFUNCT0 : in std_ulogic; + L0MSIREQUEST0 : in std_logic_vector(3 downto 0); + L0PACKETHEADERFROMUSER : in std_logic_vector(127 downto 0); + L0PMEREQIN : in std_ulogic; + L0SETCOMPLETERABORTERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTCORRERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTUNCORRERROR : in std_ulogic; + L0SETDETECTEDCORRERROR : in std_ulogic; + L0SETDETECTEDFATALERROR : in std_ulogic; + L0SETDETECTEDNONFATALERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONCORRERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTOTHERERROR : in std_ulogic; + L0SETUSERDETECTEDPARITYERROR : in std_ulogic; + L0SETUSERMASTERDATAPARITY : in std_ulogic; + L0SETUSERRECEIVEDMASTERABORT : in std_ulogic; + L0SETUSERRECEIVEDTARGETABORT : in std_ulogic; + L0SETUSERSIGNALLEDTARGETABORT : in std_ulogic; + L0SETUSERSYSTEMERROR : in std_ulogic; + L0TRANSACTIONSPENDING : in std_ulogic; + LLKRXCHFIFO : in std_logic_vector(1 downto 0); + LLKRXCHTC : in std_logic_vector(2 downto 0); + LLKRXDSTCONTREQN : in std_ulogic; + LLKRXDSTREQN : in std_ulogic; + LLKTXCHFIFO : in std_logic_vector(1 downto 0); + LLKTXCHTC : in std_logic_vector(2 downto 0); + LLKTXDATA : in std_logic_vector(63 downto 0); + LLKTXENABLEN : in std_logic_vector(1 downto 0); + LLKTXEOFN : in std_ulogic; + LLKTXEOPN : in std_ulogic; + LLKTXSOFN : in std_ulogic; + LLKTXSOPN : in std_ulogic; + LLKTXSRCDSCN : in std_ulogic; + LLKTXSRCRDYN : in std_ulogic; + MGMTADDR : in std_logic_vector(10 downto 0); + MGMTBWREN : in std_logic_vector(3 downto 0); + MGMTRDEN : in std_ulogic; + MGMTSTATSCREDITSEL : in std_logic_vector(6 downto 0); + MGMTWDATA : in std_logic_vector(31 downto 0); + MGMTWREN : in std_ulogic; + MIMDLLBRDATA : in std_logic_vector(63 downto 0); + MIMRXBRDATA : in std_logic_vector(63 downto 0); + MIMTXBRDATA : in std_logic_vector(63 downto 0); + PIPEPHYSTATUSL0 : in std_ulogic; + PIPEPHYSTATUSL1 : in std_ulogic; + PIPEPHYSTATUSL2 : in std_ulogic; + PIPEPHYSTATUSL3 : in std_ulogic; + PIPEPHYSTATUSL4 : in std_ulogic; + PIPEPHYSTATUSL5 : in std_ulogic; + PIPEPHYSTATUSL6 : in std_ulogic; + PIPEPHYSTATUSL7 : in std_ulogic; + PIPERXCHANISALIGNEDL0 : in std_ulogic; + PIPERXCHANISALIGNEDL1 : in std_ulogic; + PIPERXCHANISALIGNEDL2 : in std_ulogic; + PIPERXCHANISALIGNEDL3 : in std_ulogic; + PIPERXCHANISALIGNEDL4 : in std_ulogic; + PIPERXCHANISALIGNEDL5 : in std_ulogic; + PIPERXCHANISALIGNEDL6 : in std_ulogic; + PIPERXCHANISALIGNEDL7 : in std_ulogic; + PIPERXDATAKL0 : in std_ulogic; + PIPERXDATAKL1 : in std_ulogic; + PIPERXDATAKL2 : in std_ulogic; + PIPERXDATAKL3 : in std_ulogic; + PIPERXDATAKL4 : in std_ulogic; + PIPERXDATAKL5 : in std_ulogic; + PIPERXDATAKL6 : in std_ulogic; + PIPERXDATAKL7 : in std_ulogic; + PIPERXDATAL0 : in std_logic_vector(7 downto 0); + PIPERXDATAL1 : in std_logic_vector(7 downto 0); + PIPERXDATAL2 : in std_logic_vector(7 downto 0); + PIPERXDATAL3 : in std_logic_vector(7 downto 0); + PIPERXDATAL4 : in std_logic_vector(7 downto 0); + PIPERXDATAL5 : in std_logic_vector(7 downto 0); + PIPERXDATAL6 : in std_logic_vector(7 downto 0); + PIPERXDATAL7 : in std_logic_vector(7 downto 0); + PIPERXELECIDLEL0 : in std_ulogic; + PIPERXELECIDLEL1 : in std_ulogic; + PIPERXELECIDLEL2 : in std_ulogic; + PIPERXELECIDLEL3 : in std_ulogic; + PIPERXELECIDLEL4 : in std_ulogic; + PIPERXELECIDLEL5 : in std_ulogic; + PIPERXELECIDLEL6 : in std_ulogic; + PIPERXELECIDLEL7 : in std_ulogic; + PIPERXSTATUSL0 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL1 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL2 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL3 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL4 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL5 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL6 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL7 : in std_logic_vector(2 downto 0); + PIPERXVALIDL0 : in std_ulogic; + PIPERXVALIDL1 : in std_ulogic; + PIPERXVALIDL2 : in std_ulogic; + PIPERXVALIDL3 : in std_ulogic; + PIPERXVALIDL4 : in std_ulogic; + PIPERXVALIDL5 : in std_ulogic; + PIPERXVALIDL6 : in std_ulogic; + PIPERXVALIDL7 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + PCIE_EP : component is "PRIMITIVE"; + +----- component PCIE_INTERNAL_1_1 ----- +component PCIE_INTERNAL_1_1 + generic + ( + ACTIVELANESIN : bit_vector := X"01"; + AERBASEPTR : bit_vector := X"110"; + AERCAPABILITYECRCCHECKCAPABLE : boolean := FALSE; + AERCAPABILITYECRCGENCAPABLE : boolean := FALSE; + AERCAPABILITYNEXTPTR : bit_vector := X"138"; + BAR0ADDRWIDTH : integer := 0; + BAR0EXIST : boolean := TRUE; + BAR0IOMEMN : integer := 0; + BAR0MASKWIDTH : bit_vector := X"14"; + BAR0PREFETCHABLE : boolean := TRUE; + BAR1ADDRWIDTH : integer := 0; + BAR1EXIST : boolean := FALSE; + BAR1IOMEMN : integer := 0; + BAR1MASKWIDTH : bit_vector := X"00"; + BAR1PREFETCHABLE : boolean := FALSE; + BAR2ADDRWIDTH : integer := 0; + BAR2EXIST : boolean := FALSE; + BAR2IOMEMN : integer := 0; + BAR2MASKWIDTH : bit_vector := X"00"; + BAR2PREFETCHABLE : boolean := FALSE; + BAR3ADDRWIDTH : integer := 0; + BAR3EXIST : boolean := FALSE; + BAR3IOMEMN : integer := 0; + BAR3MASKWIDTH : bit_vector := X"00"; + BAR3PREFETCHABLE : boolean := FALSE; + BAR4ADDRWIDTH : integer := 0; + BAR4EXIST : boolean := FALSE; + BAR4IOMEMN : integer := 0; + BAR4MASKWIDTH : bit_vector := X"00"; + BAR4PREFETCHABLE : boolean := FALSE; + BAR5EXIST : boolean := FALSE; + BAR5IOMEMN : integer := 0; + BAR5MASKWIDTH : bit_vector := X"00"; + BAR5PREFETCHABLE : boolean := FALSE; + CAPABILITIESPOINTER : bit_vector := X"40"; + CARDBUSCISPOINTER : bit_vector := X"00000000"; + CLASSCODE : bit_vector := X"058000"; + CLKDIVIDED : boolean := FALSE; + CONFIGROUTING : bit_vector := X"1"; + DEVICECAPABILITYENDPOINTL0SLATENCY : bit_vector := X"0"; + DEVICECAPABILITYENDPOINTL1LATENCY : bit_vector := X"0"; + DEVICEID : bit_vector := X"5050"; + DEVICESERIALNUMBER : bit_vector := X"E000000001000A35"; + DSNBASEPTR : bit_vector := X"148"; + DSNCAPABILITYNEXTPTR : bit_vector := X"154"; + DUALCOREENABLE : boolean := FALSE; + DUALCORESLAVE : boolean := FALSE; + DUALROLECFGCNTRLROOTEPN : integer := 0; + EXTCFGCAPPTR : bit_vector := X"00"; + EXTCFGXPCAPPTR : bit_vector := X"000"; + HEADERTYPE : bit_vector := X"00"; + INFINITECOMPLETIONS : boolean := TRUE; + INTERRUPTPIN : bit_vector := X"00"; + ISSWITCH : boolean := FALSE; + L0SEXITLATENCY : integer := 7; + L0SEXITLATENCYCOMCLK : integer := 7; + L1EXITLATENCY : integer := 7; + L1EXITLATENCYCOMCLK : integer := 7; + LINKCAPABILITYASPMSUPPORT : bit_vector := X"1"; + LINKCAPABILITYMAXLINKWIDTH : bit_vector := X"01"; + LINKSTATUSSLOTCLOCKCONFIG : boolean := FALSE; + LLKBYPASS : boolean := FALSE; + LOWPRIORITYVCCOUNT : integer := 0; + MSIBASEPTR : bit_vector := X"048"; + MSICAPABILITYMULTIMSGCAP : bit_vector := X"0"; + MSICAPABILITYNEXTPTR : bit_vector := X"60"; + PBBASEPTR : bit_vector := X"138"; + PBCAPABILITYDW0BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW0DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW0PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW0PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW0POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW0TYPE : bit_vector := X"0"; + PBCAPABILITYDW1BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW1DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW1PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW1PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW1POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW1TYPE : bit_vector := X"0"; + PBCAPABILITYDW2BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW2DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW2PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW2PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW2POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW2TYPE : bit_vector := X"0"; + PBCAPABILITYDW3BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW3DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW3PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW3PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW3POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW3TYPE : bit_vector := X"0"; + PBCAPABILITYNEXTPTR : bit_vector := X"148"; + PBCAPABILITYSYSTEMALLOCATED : boolean := FALSE; + PCIECAPABILITYINTMSGNUM : bit_vector := X"00"; + PCIECAPABILITYNEXTPTR : bit_vector := X"00"; + PCIECAPABILITYSLOTIMPL : boolean := FALSE; + PCIEREVISION : integer := 1; + PMBASEPTR : bit_vector := X"040"; + PMCAPABILITYAUXCURRENT : bit_vector := X"0"; + PMCAPABILITYD1SUPPORT : boolean := FALSE; + PMCAPABILITYD2SUPPORT : boolean := FALSE; + PMCAPABILITYDSI : boolean := TRUE; + PMCAPABILITYNEXTPTR : bit_vector := X"60"; + PMCAPABILITYPMESUPPORT : bit_vector := X"00"; + PMDATA0 : bit_vector := X"00"; + PMDATA1 : bit_vector := X"00"; + PMDATA2 : bit_vector := X"00"; + PMDATA3 : bit_vector := X"00"; + PMDATA4 : bit_vector := X"00"; + PMDATA5 : bit_vector := X"00"; + PMDATA6 : bit_vector := X"00"; + PMDATA7 : bit_vector := X"00"; + PMDATA8 : bit_vector := X"00"; + PMDATASCALE0 : integer := 0; + PMDATASCALE1 : integer := 0; + PMDATASCALE2 : integer := 0; + PMDATASCALE3 : integer := 0; + PMDATASCALE4 : integer := 0; + PMDATASCALE5 : integer := 0; + PMDATASCALE6 : integer := 0; + PMDATASCALE7 : integer := 0; + PMDATASCALE8 : integer := 0; + PMSTATUSCONTROLDATASCALE : bit_vector := X"0"; + PORTVCCAPABILITYEXTENDEDVCCOUNT : bit_vector := X"0"; + PORTVCCAPABILITYVCARBCAP : bit_vector := X"00"; + PORTVCCAPABILITYVCARBTABLEOFFSET : bit_vector := X"00"; + RAMSHARETXRX : boolean := FALSE; + RESETMODE : boolean := FALSE; + RETRYRAMREADLATENCY : integer := 3; + RETRYRAMSIZE : bit_vector := X"009"; + RETRYRAMWIDTH : integer := 0; + RETRYRAMWRITELATENCY : integer := 1; + RETRYREADADDRPIPE : boolean := FALSE; + RETRYREADDATAPIPE : boolean := FALSE; + RETRYWRITEPIPE : boolean := FALSE; + REVISIONID : bit_vector := X"00"; + RXREADADDRPIPE : boolean := FALSE; + RXREADDATAPIPE : boolean := FALSE; + RXWRITEPIPE : boolean := FALSE; + SELECTASMODE : boolean := FALSE; + SELECTDLLIF : boolean := FALSE; + SLOTCAPABILITYATTBUTTONPRESENT : boolean := FALSE; + SLOTCAPABILITYATTINDICATORPRESENT : boolean := FALSE; + SLOTCAPABILITYHOTPLUGCAPABLE : boolean := FALSE; + SLOTCAPABILITYHOTPLUGSURPRISE : boolean := FALSE; + SLOTCAPABILITYMSLSENSORPRESENT : boolean := FALSE; + SLOTCAPABILITYPHYSICALSLOTNUM : bit_vector := X"0000"; + SLOTCAPABILITYPOWERCONTROLLERPRESENT : boolean := FALSE; + SLOTCAPABILITYPOWERINDICATORPRESENT : boolean := FALSE; + SLOTCAPABILITYSLOTPOWERLIMITSCALE : bit_vector := X"0"; + SLOTCAPABILITYSLOTPOWERLIMITVALUE : bit_vector := X"00"; + SLOTIMPLEMENTED : boolean := FALSE; + SUBSYSTEMID : bit_vector := X"5050"; + SUBSYSTEMVENDORID : bit_vector := X"10EE"; + TLRAMREADLATENCY : integer := 3; + TLRAMWIDTH : integer := 0; + TLRAMWRITELATENCY : integer := 1; + TXREADADDRPIPE : boolean := FALSE; + TXREADDATAPIPE : boolean := FALSE; + TXTSNFTS : integer := 255; + TXTSNFTSCOMCLK : integer := 255; + TXWRITEPIPE : boolean := FALSE; + UPSTREAMFACING : boolean := TRUE; + VC0RXFIFOBASEC : bit_vector := X"0098"; + VC0RXFIFOBASENP : bit_vector := X"0080"; + VC0RXFIFOBASEP : bit_vector := X"0000"; + VC0RXFIFOLIMITC : bit_vector := X"0117"; + VC0RXFIFOLIMITNP : bit_vector := X"0097"; + VC0RXFIFOLIMITP : bit_vector := X"007f"; + VC0TOTALCREDITSCD : bit_vector := X"000"; + VC0TOTALCREDITSCH : bit_vector := X"00"; + VC0TOTALCREDITSNPH : bit_vector := X"08"; + VC0TOTALCREDITSPD : bit_vector := X"034"; + VC0TOTALCREDITSPH : bit_vector := X"08"; + VC0TXFIFOBASEC : bit_vector := X"0098"; + VC0TXFIFOBASENP : bit_vector := X"0080"; + VC0TXFIFOBASEP : bit_vector := X"0000"; + VC0TXFIFOLIMITC : bit_vector := X"0117"; + VC0TXFIFOLIMITNP : bit_vector := X"0097"; + VC0TXFIFOLIMITP : bit_vector := X"007f"; + VC1RXFIFOBASEC : bit_vector := X"0118"; + VC1RXFIFOBASENP : bit_vector := X"0118"; + VC1RXFIFOBASEP : bit_vector := X"0118"; + VC1RXFIFOLIMITC : bit_vector := X"0118"; + VC1RXFIFOLIMITNP : bit_vector := X"0118"; + VC1RXFIFOLIMITP : bit_vector := X"0118"; + VC1TOTALCREDITSCD : bit_vector := X"000"; + VC1TOTALCREDITSCH : bit_vector := X"00"; + VC1TOTALCREDITSNPH : bit_vector := X"00"; + VC1TOTALCREDITSPD : bit_vector := X"000"; + VC1TOTALCREDITSPH : bit_vector := X"00"; + VC1TXFIFOBASEC : bit_vector := X"0118"; + VC1TXFIFOBASENP : bit_vector := X"0118"; + VC1TXFIFOBASEP : bit_vector := X"0118"; + VC1TXFIFOLIMITC : bit_vector := X"0118"; + VC1TXFIFOLIMITNP : bit_vector := X"0118"; + VC1TXFIFOLIMITP : bit_vector := X"0118"; + VCBASEPTR : bit_vector := X"154"; + VCCAPABILITYNEXTPTR : bit_vector := X"000"; + VENDORID : bit_vector := X"10EE"; + XLINKSUPPORTED : boolean := FALSE; + XPBASEPTR : bit_vector := X"60"; + XPDEVICEPORTTYPE : bit_vector := X"0"; + XPMAXPAYLOAD : integer := 0; + XPRCBCONTROL : integer := 0 + ); + port + ( + BUSMASTERENABLE : out std_ulogic; + CRMDOHOTRESETN : out std_ulogic; + CRMPWRSOFTRESETN : out std_ulogic; + CRMRXHOTRESETN : out std_ulogic; + DLLTXPMDLLPOUTSTANDING : out std_ulogic; + INTERRUPTDISABLE : out std_ulogic; + IOSPACEENABLE : out std_ulogic; + L0ASAUTONOMOUSINITCOMPLETED : out std_ulogic; + L0ATTENTIONINDICATORCONTROL : out std_logic_vector(1 downto 0); + L0CFGLOOPBACKACK : out std_ulogic; + L0COMPLETERID : out std_logic_vector(12 downto 0); + L0CORRERRMSGRCVD : out std_ulogic; + L0DLLASRXSTATE : out std_logic_vector(1 downto 0); + L0DLLASTXSTATE : out std_ulogic; + L0DLLERRORVECTOR : out std_logic_vector(6 downto 0); + L0DLLRXACKOUTSTANDING : out std_ulogic; + L0DLLTXNONFCOUTSTANDING : out std_ulogic; + L0DLLTXOUTSTANDING : out std_ulogic; + L0DLLVCSTATUS : out std_logic_vector(7 downto 0); + L0DLUPDOWN : out std_logic_vector(7 downto 0); + L0ERRMSGREQID : out std_logic_vector(15 downto 0); + L0FATALERRMSGRCVD : out std_ulogic; + L0FIRSTCFGWRITEOCCURRED : out std_ulogic; + L0FWDCORRERROUT : out std_ulogic; + L0FWDFATALERROUT : out std_ulogic; + L0FWDNONFATALERROUT : out std_ulogic; + L0LTSSMSTATE : out std_logic_vector(3 downto 0); + L0MACENTEREDL0 : out std_ulogic; + L0MACLINKTRAINING : out std_ulogic; + L0MACLINKUP : out std_ulogic; + L0MACNEGOTIATEDLINKWIDTH : out std_logic_vector(3 downto 0); + L0MACNEWSTATEACK : out std_ulogic; + L0MACRXL0SSTATE : out std_ulogic; + L0MACUPSTREAMDOWNSTREAM : out std_ulogic; + L0MCFOUND : out std_logic_vector(2 downto 0); + L0MSIENABLE0 : out std_ulogic; + L0MULTIMSGEN0 : out std_logic_vector(2 downto 0); + L0NONFATALERRMSGRCVD : out std_ulogic; + L0PMEACK : out std_ulogic; + L0PMEEN : out std_ulogic; + L0PMEREQOUT : out std_ulogic; + L0POWERCONTROLLERCONTROL : out std_ulogic; + L0POWERINDICATORCONTROL : out std_logic_vector(1 downto 0); + L0PWRINHIBITTRANSFERS : out std_ulogic; + L0PWRL1STATE : out std_ulogic; + L0PWRL23READYDEVICE : out std_ulogic; + L0PWRL23READYSTATE : out std_ulogic; + L0PWRSTATE0 : out std_logic_vector(1 downto 0); + L0PWRTURNOFFREQ : out std_ulogic; + L0PWRTXL0SSTATE : out std_ulogic; + L0RECEIVEDASSERTINTALEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTBLEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTCLEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTDLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTALEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTBLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTCLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTDLEGACYINT : out std_ulogic; + L0RXBEACON : out std_ulogic; + L0RXDLLFCCMPLMCCRED : out std_logic_vector(23 downto 0); + L0RXDLLFCCMPLMCUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLFCNPOSTBYPCRED : out std_logic_vector(19 downto 0); + L0RXDLLFCNPOSTBYPUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLFCPOSTORDCRED : out std_logic_vector(23 downto 0); + L0RXDLLFCPOSTORDUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLPM : out std_ulogic; + L0RXDLLPMTYPE : out std_logic_vector(2 downto 0); + L0RXDLLSBFCDATA : out std_logic_vector(18 downto 0); + L0RXDLLSBFCUPDATE : out std_ulogic; + L0RXDLLTLPECRCOK : out std_ulogic; + L0RXDLLTLPEND : out std_logic_vector(1 downto 0); + L0RXMACLINKERROR : out std_logic_vector(1 downto 0); + L0STATSCFGOTHERRECEIVED : out std_ulogic; + L0STATSCFGOTHERTRANSMITTED : out std_ulogic; + L0STATSCFGRECEIVED : out std_ulogic; + L0STATSCFGTRANSMITTED : out std_ulogic; + L0STATSDLLPRECEIVED : out std_ulogic; + L0STATSDLLPTRANSMITTED : out std_ulogic; + L0STATSOSRECEIVED : out std_ulogic; + L0STATSOSTRANSMITTED : out std_ulogic; + L0STATSTLPRECEIVED : out std_ulogic; + L0STATSTLPTRANSMITTED : out std_ulogic; + L0TOGGLEELECTROMECHANICALINTERLOCK : out std_ulogic; + L0TRANSFORMEDVC : out std_logic_vector(2 downto 0); + L0TXDLLFCCMPLMCUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLFCNPOSTBYPUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLFCPOSTORDUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLPMUPDATED : out std_ulogic; + L0TXDLLSBFCUPDATED : out std_ulogic; + L0UCBYPFOUND : out std_logic_vector(3 downto 0); + L0UCORDFOUND : out std_logic_vector(3 downto 0); + L0UNLOCKRECEIVED : out std_ulogic; + LLKRX4DWHEADERN : out std_ulogic; + LLKRXCHCOMPLETIONAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHCOMPLETIONPARTIALN : out std_logic_vector(7 downto 0); + LLKRXCHCONFIGAVAILABLEN : out std_ulogic; + LLKRXCHCONFIGPARTIALN : out std_ulogic; + LLKRXCHNONPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHNONPOSTEDPARTIALN : out std_logic_vector(7 downto 0); + LLKRXCHPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHPOSTEDPARTIALN : out std_logic_vector(7 downto 0); + LLKRXDATA : out std_logic_vector(63 downto 0); + LLKRXECRCBADN : out std_ulogic; + LLKRXEOFN : out std_ulogic; + LLKRXEOPN : out std_ulogic; + LLKRXPREFERREDTYPE : out std_logic_vector(15 downto 0); + LLKRXSOFN : out std_ulogic; + LLKRXSOPN : out std_ulogic; + LLKRXSRCDSCN : out std_ulogic; + LLKRXSRCLASTREQN : out std_ulogic; + LLKRXSRCRDYN : out std_ulogic; + LLKRXVALIDN : out std_logic_vector(1 downto 0); + LLKTCSTATUS : out std_logic_vector(7 downto 0); + LLKTXCHANSPACE : out std_logic_vector(9 downto 0); + LLKTXCHCOMPLETIONREADYN : out std_logic_vector(7 downto 0); + LLKTXCHNONPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCHPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCONFIGREADYN : out std_ulogic; + LLKTXDSTRDYN : out std_ulogic; + MAXPAYLOADSIZE : out std_logic_vector(2 downto 0); + MAXREADREQUESTSIZE : out std_logic_vector(2 downto 0); + MEMSPACEENABLE : out std_ulogic; + MGMTPSO : out std_logic_vector(16 downto 0); + MGMTRDATA : out std_logic_vector(31 downto 0); + MGMTSTATSCREDIT : out std_logic_vector(11 downto 0); + MIMDLLBRADD : out std_logic_vector(11 downto 0); + MIMDLLBREN : out std_ulogic; + MIMDLLBWADD : out std_logic_vector(11 downto 0); + MIMDLLBWDATA : out std_logic_vector(63 downto 0); + MIMDLLBWEN : out std_ulogic; + MIMRXBRADD : out std_logic_vector(12 downto 0); + MIMRXBREN : out std_ulogic; + MIMRXBWADD : out std_logic_vector(12 downto 0); + MIMRXBWDATA : out std_logic_vector(63 downto 0); + MIMRXBWEN : out std_ulogic; + MIMTXBRADD : out std_logic_vector(12 downto 0); + MIMTXBREN : out std_ulogic; + MIMTXBWADD : out std_logic_vector(12 downto 0); + MIMTXBWDATA : out std_logic_vector(63 downto 0); + MIMTXBWEN : out std_ulogic; + PARITYERRORRESPONSE : out std_ulogic; + PIPEDESKEWLANESL0 : out std_ulogic; + PIPEDESKEWLANESL1 : out std_ulogic; + PIPEDESKEWLANESL2 : out std_ulogic; + PIPEDESKEWLANESL3 : out std_ulogic; + PIPEDESKEWLANESL4 : out std_ulogic; + PIPEDESKEWLANESL5 : out std_ulogic; + PIPEDESKEWLANESL6 : out std_ulogic; + PIPEDESKEWLANESL7 : out std_ulogic; + PIPEPOWERDOWNL0 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL1 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL2 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL3 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL4 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL5 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL6 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL7 : out std_logic_vector(1 downto 0); + PIPERESETL0 : out std_ulogic; + PIPERESETL1 : out std_ulogic; + PIPERESETL2 : out std_ulogic; + PIPERESETL3 : out std_ulogic; + PIPERESETL4 : out std_ulogic; + PIPERESETL5 : out std_ulogic; + PIPERESETL6 : out std_ulogic; + PIPERESETL7 : out std_ulogic; + PIPERXPOLARITYL0 : out std_ulogic; + PIPERXPOLARITYL1 : out std_ulogic; + PIPERXPOLARITYL2 : out std_ulogic; + PIPERXPOLARITYL3 : out std_ulogic; + PIPERXPOLARITYL4 : out std_ulogic; + PIPERXPOLARITYL5 : out std_ulogic; + PIPERXPOLARITYL6 : out std_ulogic; + PIPERXPOLARITYL7 : out std_ulogic; + PIPETXCOMPLIANCEL0 : out std_ulogic; + PIPETXCOMPLIANCEL1 : out std_ulogic; + PIPETXCOMPLIANCEL2 : out std_ulogic; + PIPETXCOMPLIANCEL3 : out std_ulogic; + PIPETXCOMPLIANCEL4 : out std_ulogic; + PIPETXCOMPLIANCEL5 : out std_ulogic; + PIPETXCOMPLIANCEL6 : out std_ulogic; + PIPETXCOMPLIANCEL7 : out std_ulogic; + PIPETXDATAKL0 : out std_ulogic; + PIPETXDATAKL1 : out std_ulogic; + PIPETXDATAKL2 : out std_ulogic; + PIPETXDATAKL3 : out std_ulogic; + PIPETXDATAKL4 : out std_ulogic; + PIPETXDATAKL5 : out std_ulogic; + PIPETXDATAKL6 : out std_ulogic; + PIPETXDATAKL7 : out std_ulogic; + PIPETXDATAL0 : out std_logic_vector(7 downto 0); + PIPETXDATAL1 : out std_logic_vector(7 downto 0); + PIPETXDATAL2 : out std_logic_vector(7 downto 0); + PIPETXDATAL3 : out std_logic_vector(7 downto 0); + PIPETXDATAL4 : out std_logic_vector(7 downto 0); + PIPETXDATAL5 : out std_logic_vector(7 downto 0); + PIPETXDATAL6 : out std_logic_vector(7 downto 0); + PIPETXDATAL7 : out std_logic_vector(7 downto 0); + PIPETXDETECTRXLOOPBACKL0 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL1 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL2 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL3 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL4 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL5 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL6 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL7 : out std_ulogic; + PIPETXELECIDLEL0 : out std_ulogic; + PIPETXELECIDLEL1 : out std_ulogic; + PIPETXELECIDLEL2 : out std_ulogic; + PIPETXELECIDLEL3 : out std_ulogic; + PIPETXELECIDLEL4 : out std_ulogic; + PIPETXELECIDLEL5 : out std_ulogic; + PIPETXELECIDLEL6 : out std_ulogic; + PIPETXELECIDLEL7 : out std_ulogic; + SERRENABLE : out std_ulogic; + URREPORTINGENABLE : out std_ulogic; + AUXPOWER : in std_ulogic; + CFGNEGOTIATEDLINKWIDTH : in std_logic_vector(5 downto 0); + COMPLIANCEAVOID : in std_ulogic; + CRMCFGBRIDGEHOTRESET : in std_ulogic; + CRMCORECLK : in std_ulogic; + CRMCORECLKDLO : in std_ulogic; + CRMCORECLKRXO : in std_ulogic; + CRMCORECLKTXO : in std_ulogic; + CRMLINKRSTN : in std_ulogic; + CRMMACRSTN : in std_ulogic; + CRMMGMTRSTN : in std_ulogic; + CRMNVRSTN : in std_ulogic; + CRMTXHOTRESETN : in std_ulogic; + CRMURSTN : in std_ulogic; + CRMUSERCFGRSTN : in std_ulogic; + CRMUSERCLK : in std_ulogic; + CRMUSERCLKRXO : in std_ulogic; + CRMUSERCLKTXO : in std_ulogic; + CROSSLINKSEED : in std_ulogic; + L0ACKNAKTIMERADJUSTMENT : in std_logic_vector(11 downto 0); + L0ALLDOWNPORTSINL1 : in std_ulogic; + L0ALLDOWNRXPORTSINL0S : in std_ulogic; + L0ASE : in std_ulogic; + L0ASPORTCOUNT : in std_logic_vector(7 downto 0); + L0ASTURNPOOLBITSCONSUMED : in std_logic_vector(2 downto 0); + L0ATTENTIONBUTTONPRESSED : in std_ulogic; + L0CFGASSPANTREEOWNEDSTATE : in std_ulogic; + L0CFGASSTATECHANGECMD : in std_logic_vector(3 downto 0); + L0CFGDISABLESCRAMBLE : in std_ulogic; + L0CFGEXTENDEDSYNC : in std_ulogic; + L0CFGL0SENTRYENABLE : in std_ulogic; + L0CFGL0SENTRYSUP : in std_ulogic; + L0CFGL0SEXITLAT : in std_logic_vector(2 downto 0); + L0CFGLINKDISABLE : in std_ulogic; + L0CFGLOOPBACKMASTER : in std_ulogic; + L0CFGNEGOTIATEDMAXP : in std_logic_vector(2 downto 0); + L0CFGVCENABLE : in std_logic_vector(7 downto 0); + L0CFGVCID : in std_logic_vector(23 downto 0); + L0DLLHOLDLINKUP : in std_ulogic; + L0ELECTROMECHANICALINTERLOCKENGAGED : in std_ulogic; + L0FWDASSERTINTALEGACYINT : in std_ulogic; + L0FWDASSERTINTBLEGACYINT : in std_ulogic; + L0FWDASSERTINTCLEGACYINT : in std_ulogic; + L0FWDASSERTINTDLEGACYINT : in std_ulogic; + L0FWDCORRERRIN : in std_ulogic; + L0FWDDEASSERTINTALEGACYINT : in std_ulogic; + L0FWDDEASSERTINTBLEGACYINT : in std_ulogic; + L0FWDDEASSERTINTCLEGACYINT : in std_ulogic; + L0FWDDEASSERTINTDLEGACYINT : in std_ulogic; + L0FWDFATALERRIN : in std_ulogic; + L0FWDNONFATALERRIN : in std_ulogic; + L0LEGACYINTFUNCT0 : in std_ulogic; + L0MRLSENSORCLOSEDN : in std_ulogic; + L0MSIREQUEST0 : in std_logic_vector(3 downto 0); + L0PACKETHEADERFROMUSER : in std_logic_vector(127 downto 0); + L0PMEREQIN : in std_ulogic; + L0PORTNUMBER : in std_logic_vector(7 downto 0); + L0POWERFAULTDETECTED : in std_ulogic; + L0PRESENCEDETECTSLOTEMPTYN : in std_ulogic; + L0PWRNEWSTATEREQ : in std_ulogic; + L0PWRNEXTLINKSTATE : in std_logic_vector(1 downto 0); + L0REPLAYTIMERADJUSTMENT : in std_logic_vector(11 downto 0); + L0ROOTTURNOFFREQ : in std_ulogic; + L0RXTLTLPNONINITIALIZEDVC : in std_logic_vector(7 downto 0); + L0SENDUNLOCKMESSAGE : in std_ulogic; + L0SETCOMPLETERABORTERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTCORRERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTUNCORRERROR : in std_ulogic; + L0SETDETECTEDCORRERROR : in std_ulogic; + L0SETDETECTEDFATALERROR : in std_ulogic; + L0SETDETECTEDNONFATALERROR : in std_ulogic; + L0SETLINKDETECTEDPARITYERROR : in std_ulogic; + L0SETLINKMASTERDATAPARITY : in std_ulogic; + L0SETLINKRECEIVEDMASTERABORT : in std_ulogic; + L0SETLINKRECEIVEDTARGETABORT : in std_ulogic; + L0SETLINKSIGNALLEDTARGETABORT : in std_ulogic; + L0SETLINKSYSTEMERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONCORRERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTOTHERERROR : in std_ulogic; + L0SETUSERDETECTEDPARITYERROR : in std_ulogic; + L0SETUSERMASTERDATAPARITY : in std_ulogic; + L0SETUSERRECEIVEDMASTERABORT : in std_ulogic; + L0SETUSERRECEIVEDTARGETABORT : in std_ulogic; + L0SETUSERSIGNALLEDTARGETABORT : in std_ulogic; + L0SETUSERSYSTEMERROR : in std_ulogic; + L0TLASFCCREDSTARVATION : in std_ulogic; + L0TLLINKRETRAIN : in std_ulogic; + L0TRANSACTIONSPENDING : in std_ulogic; + L0TXBEACON : in std_ulogic; + L0TXCFGPM : in std_ulogic; + L0TXCFGPMTYPE : in std_logic_vector(2 downto 0); + L0TXTLFCCMPLMCCRED : in std_logic_vector(159 downto 0); + L0TXTLFCCMPLMCUPDATE : in std_logic_vector(15 downto 0); + L0TXTLFCNPOSTBYPCRED : in std_logic_vector(191 downto 0); + L0TXTLFCNPOSTBYPUPDATE : in std_logic_vector(15 downto 0); + L0TXTLFCPOSTORDCRED : in std_logic_vector(159 downto 0); + L0TXTLFCPOSTORDUPDATE : in std_logic_vector(15 downto 0); + L0TXTLSBFCDATA : in std_logic_vector(18 downto 0); + L0TXTLSBFCUPDATE : in std_ulogic; + L0TXTLTLPDATA : in std_logic_vector(63 downto 0); + L0TXTLTLPEDB : in std_ulogic; + L0TXTLTLPENABLE : in std_logic_vector(1 downto 0); + L0TXTLTLPEND : in std_logic_vector(1 downto 0); + L0TXTLTLPLATENCY : in std_logic_vector(3 downto 0); + L0TXTLTLPREQ : in std_ulogic; + L0TXTLTLPREQEND : in std_ulogic; + L0TXTLTLPWIDTH : in std_ulogic; + L0UPSTREAMRXPORTINL0S : in std_ulogic; + L0VC0PREVIEWEXPAND : in std_ulogic; + L0WAKEN : in std_ulogic; + LLKRXCHFIFO : in std_logic_vector(1 downto 0); + LLKRXCHTC : in std_logic_vector(2 downto 0); + LLKRXDSTCONTREQN : in std_ulogic; + LLKRXDSTREQN : in std_ulogic; + LLKTX4DWHEADERN : in std_ulogic; + LLKTXCHFIFO : in std_logic_vector(1 downto 0); + LLKTXCHTC : in std_logic_vector(2 downto 0); + LLKTXCOMPLETEN : in std_ulogic; + LLKTXCREATEECRCN : in std_ulogic; + LLKTXDATA : in std_logic_vector(63 downto 0); + LLKTXENABLEN : in std_logic_vector(1 downto 0); + LLKTXEOFN : in std_ulogic; + LLKTXEOPN : in std_ulogic; + LLKTXSOFN : in std_ulogic; + LLKTXSOPN : in std_ulogic; + LLKTXSRCDSCN : in std_ulogic; + LLKTXSRCRDYN : in std_ulogic; + MAINPOWER : in std_ulogic; + MGMTADDR : in std_logic_vector(10 downto 0); + MGMTBWREN : in std_logic_vector(3 downto 0); + MGMTRDEN : in std_ulogic; + MGMTSTATSCREDITSEL : in std_logic_vector(6 downto 0); + MGMTWDATA : in std_logic_vector(31 downto 0); + MGMTWREN : in std_ulogic; + MIMDLLBRDATA : in std_logic_vector(63 downto 0); + MIMRXBRDATA : in std_logic_vector(63 downto 0); + MIMTXBRDATA : in std_logic_vector(63 downto 0); + PIPEPHYSTATUSL0 : in std_ulogic; + PIPEPHYSTATUSL1 : in std_ulogic; + PIPEPHYSTATUSL2 : in std_ulogic; + PIPEPHYSTATUSL3 : in std_ulogic; + PIPEPHYSTATUSL4 : in std_ulogic; + PIPEPHYSTATUSL5 : in std_ulogic; + PIPEPHYSTATUSL6 : in std_ulogic; + PIPEPHYSTATUSL7 : in std_ulogic; + PIPERXCHANISALIGNEDL0 : in std_ulogic; + PIPERXCHANISALIGNEDL1 : in std_ulogic; + PIPERXCHANISALIGNEDL2 : in std_ulogic; + PIPERXCHANISALIGNEDL3 : in std_ulogic; + PIPERXCHANISALIGNEDL4 : in std_ulogic; + PIPERXCHANISALIGNEDL5 : in std_ulogic; + PIPERXCHANISALIGNEDL6 : in std_ulogic; + PIPERXCHANISALIGNEDL7 : in std_ulogic; + PIPERXDATAKL0 : in std_ulogic; + PIPERXDATAKL1 : in std_ulogic; + PIPERXDATAKL2 : in std_ulogic; + PIPERXDATAKL3 : in std_ulogic; + PIPERXDATAKL4 : in std_ulogic; + PIPERXDATAKL5 : in std_ulogic; + PIPERXDATAKL6 : in std_ulogic; + PIPERXDATAKL7 : in std_ulogic; + PIPERXDATAL0 : in std_logic_vector(7 downto 0); + PIPERXDATAL1 : in std_logic_vector(7 downto 0); + PIPERXDATAL2 : in std_logic_vector(7 downto 0); + PIPERXDATAL3 : in std_logic_vector(7 downto 0); + PIPERXDATAL4 : in std_logic_vector(7 downto 0); + PIPERXDATAL5 : in std_logic_vector(7 downto 0); + PIPERXDATAL6 : in std_logic_vector(7 downto 0); + PIPERXDATAL7 : in std_logic_vector(7 downto 0); + PIPERXELECIDLEL0 : in std_ulogic; + PIPERXELECIDLEL1 : in std_ulogic; + PIPERXELECIDLEL2 : in std_ulogic; + PIPERXELECIDLEL3 : in std_ulogic; + PIPERXELECIDLEL4 : in std_ulogic; + PIPERXELECIDLEL5 : in std_ulogic; + PIPERXELECIDLEL6 : in std_ulogic; + PIPERXELECIDLEL7 : in std_ulogic; + PIPERXSTATUSL0 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL1 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL2 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL3 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL4 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL5 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL6 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL7 : in std_logic_vector(2 downto 0); + PIPERXVALIDL0 : in std_ulogic; + PIPERXVALIDL1 : in std_ulogic; + PIPERXVALIDL2 : in std_ulogic; + PIPERXVALIDL3 : in std_ulogic; + PIPERXVALIDL4 : in std_ulogic; + PIPERXVALIDL5 : in std_ulogic; + PIPERXVALIDL6 : in std_ulogic; + PIPERXVALIDL7 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + PCIE_INTERNAL_1_1 : component is "PRIMITIVE"; + +----- component PLL_ADV ----- +component PLL_ADV + generic + ( + BANDWIDTH : string := "OPTIMIZED"; + CLKFBOUT_DESKEW_ADJUST : string := "NONE"; + CLKFBOUT_MULT : integer := 1; + CLKFBOUT_PHASE : real := 0.0; + CLKIN1_PERIOD : real := 0.000; + CLKIN2_PERIOD : real := 0.000; + CLKOUT0_DESKEW_ADJUST : string := "NONE"; + CLKOUT0_DIVIDE : integer := 1; + CLKOUT0_DUTY_CYCLE : real := 0.5; + CLKOUT0_PHASE : real := 0.0; + CLKOUT1_DESKEW_ADJUST : string := "NONE"; + CLKOUT1_DIVIDE : integer := 1; + CLKOUT1_DUTY_CYCLE : real := 0.5; + CLKOUT1_PHASE : real := 0.0; + CLKOUT2_DESKEW_ADJUST : string := "NONE"; + CLKOUT2_DIVIDE : integer := 1; + CLKOUT2_DUTY_CYCLE : real := 0.5; + CLKOUT2_PHASE : real := 0.0; + CLKOUT3_DESKEW_ADJUST : string := "NONE"; + CLKOUT3_DIVIDE : integer := 1; + CLKOUT3_DUTY_CYCLE : real := 0.5; + CLKOUT3_PHASE : real := 0.0; + CLKOUT4_DESKEW_ADJUST : string := "NONE"; + CLKOUT4_DIVIDE : integer := 1; + CLKOUT4_DUTY_CYCLE : real := 0.5; + CLKOUT4_PHASE : real := 0.0; + CLKOUT5_DESKEW_ADJUST : string := "NONE"; + CLKOUT5_DIVIDE : integer := 1; + CLKOUT5_DUTY_CYCLE : real := 0.5; + CLKOUT5_PHASE : real := 0.0; + COMPENSATION : string := "SYSTEM_SYNCHRONOUS"; + DIVCLK_DIVIDE : integer := 1; + EN_REL : boolean := FALSE; + PLL_PMCD_MODE : boolean := FALSE; + REF_JITTER : real := 0.100; + RESET_ON_LOSS_OF_LOCK : boolean := FALSE; + RST_DEASSERT_CLK : string := "CLKIN1" + ); + port + ( + CLKFBDCM : out std_ulogic := '0'; + CLKFBOUT : out std_ulogic := '0'; + CLKOUT0 : out std_ulogic := '0'; + CLKOUT1 : out std_ulogic := '0'; + CLKOUT2 : out std_ulogic := '0'; + CLKOUT3 : out std_ulogic := '0'; + CLKOUT4 : out std_ulogic := '0'; + CLKOUT5 : out std_ulogic := '0'; + CLKOUTDCM0 : out std_ulogic := '0'; + CLKOUTDCM1 : out std_ulogic := '0'; + CLKOUTDCM2 : out std_ulogic := '0'; + CLKOUTDCM3 : out std_ulogic := '0'; + CLKOUTDCM4 : out std_ulogic := '0'; + CLKOUTDCM5 : out std_ulogic := '0'; + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic := '0'; + LOCKED : out std_ulogic := '0'; + CLKFBIN : in std_ulogic; + CLKIN1 : in std_ulogic; + CLKIN2 : in std_ulogic; + CLKINSEL : in std_ulogic; + DADDR : in std_logic_vector(4 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + REL : in std_ulogic; + RST : in std_ulogic + ); +end component; +attribute BOX_TYPE of + PLL_ADV : component is "PRIMITIVE"; + +----- component PLL_BASE ----- +component PLL_BASE + generic + ( + BANDWIDTH : string := "OPTIMIZED"; + CLKFBOUT_MULT : integer := 1; + CLKFBOUT_PHASE : real := 0.0; + CLKIN_PERIOD : real := 0.000; + CLKOUT0_DIVIDE : integer := 1; + CLKOUT0_DUTY_CYCLE : real := 0.5; + CLKOUT0_PHASE : real := 0.0; + CLKOUT1_DIVIDE : integer := 1; + CLKOUT1_DUTY_CYCLE : real := 0.5; + CLKOUT1_PHASE : real := 0.0; + CLKOUT2_DIVIDE : integer := 1; + CLKOUT2_DUTY_CYCLE : real := 0.5; + CLKOUT2_PHASE : real := 0.0; + CLKOUT3_DIVIDE : integer := 1; + CLKOUT3_DUTY_CYCLE : real := 0.5; + CLKOUT3_PHASE : real := 0.0; + CLKOUT4_DIVIDE : integer := 1; + CLKOUT4_DUTY_CYCLE : real := 0.5; + CLKOUT4_PHASE : real := 0.0; + CLKOUT5_DIVIDE : integer := 1; + CLKOUT5_DUTY_CYCLE : real := 0.5; + CLKOUT5_PHASE : real := 0.0; + COMPENSATION : string := "SYSTEM_SYNCHRONOUS"; + DIVCLK_DIVIDE : integer := 1; + REF_JITTER : real := 0.100; + RESET_ON_LOSS_OF_LOCK : boolean := FALSE + ); + port + ( + CLKFBOUT : out std_ulogic; + CLKOUT0 : out std_ulogic; + CLKOUT1 : out std_ulogic; + CLKOUT2 : out std_ulogic; + CLKOUT3 : out std_ulogic; + CLKOUT4 : out std_ulogic; + CLKOUT5 : out std_ulogic; + LOCKED : out std_ulogic; + CLKFBIN : in std_ulogic; + CLKIN : in std_ulogic; + RST : in std_ulogic + ); +end component; +attribute BOX_TYPE of + PLL_BASE : component is "PRIMITIVE"; + +----- component PMCD ----- +component PMCD + generic + ( + EN_REL : boolean := FALSE; + RST_DEASSERT_CLK : string := "CLKA" + ); + port + ( + CLKA1 : out std_ulogic; + CLKA1D2 : out std_ulogic; + CLKA1D4 : out std_ulogic; + CLKA1D8 : out std_ulogic; + CLKB1 : out std_ulogic; + CLKC1 : out std_ulogic; + CLKD1 : out std_ulogic; + CLKA : in std_ulogic; + CLKB : in std_ulogic; + CLKC : in std_ulogic; + CLKD : in std_ulogic; + REL : in std_ulogic; + RST : in std_ulogic + ); +end component; +attribute BOX_TYPE of + PMCD : component is "PRIMITIVE"; + +----- component PPC405_ADV ----- +component PPC405_ADV + port + ( + APUFCMDECODED : out std_ulogic; + APUFCMDECUDI : out std_logic_vector(0 to 2); + APUFCMDECUDIVALID : out std_ulogic; + APUFCMENDIAN : out std_ulogic; + APUFCMFLUSH : out std_ulogic; + APUFCMINSTRUCTION : out std_logic_vector(0 to 31); + APUFCMINSTRVALID : out std_ulogic; + APUFCMLOADBYTEEN : out std_logic_vector(0 to 3); + APUFCMLOADDATA : out std_logic_vector(0 to 31); + APUFCMLOADDVALID : out std_ulogic; + APUFCMOPERANDVALID : out std_ulogic; + APUFCMRADATA : out std_logic_vector(0 to 31); + APUFCMRBDATA : out std_logic_vector(0 to 31); + APUFCMWRITEBACKOK : out std_ulogic; + APUFCMXERCA : out std_ulogic; + C405CPMCORESLEEPREQ : out std_ulogic; + C405CPMMSRCE : out std_ulogic; + C405CPMMSREE : out std_ulogic; + C405CPMTIMERIRQ : out std_ulogic; + C405CPMTIMERRESETREQ : out std_ulogic; + C405DBGLOADDATAONAPUDBUS : out std_ulogic; + C405DBGMSRWE : out std_ulogic; + C405DBGSTOPACK : out std_ulogic; + C405DBGWBCOMPLETE : out std_ulogic; + C405DBGWBFULL : out std_ulogic; + C405DBGWBIAR : out std_logic_vector(0 to 29); + C405JTGCAPTUREDR : out std_ulogic; + C405JTGEXTEST : out std_ulogic; + C405JTGPGMOUT : out std_ulogic; + C405JTGSHIFTDR : out std_ulogic; + C405JTGTDO : out std_ulogic; + C405JTGTDOEN : out std_ulogic; + C405JTGUPDATEDR : out std_ulogic; + C405PLBDCUABORT : out std_ulogic; + C405PLBDCUABUS : out std_logic_vector(0 to 31); + C405PLBDCUBE : out std_logic_vector(0 to 7); + C405PLBDCUCACHEABLE : out std_ulogic; + C405PLBDCUGUARDED : out std_ulogic; + C405PLBDCUPRIORITY : out std_logic_vector(0 to 1); + C405PLBDCUREQUEST : out std_ulogic; + C405PLBDCURNW : out std_ulogic; + C405PLBDCUSIZE2 : out std_ulogic; + C405PLBDCUU0ATTR : out std_ulogic; + C405PLBDCUWRDBUS : out std_logic_vector(0 to 63); + C405PLBDCUWRITETHRU : out std_ulogic; + C405PLBICUABORT : out std_ulogic; + C405PLBICUABUS : out std_logic_vector(0 to 29); + C405PLBICUCACHEABLE : out std_ulogic; + C405PLBICUPRIORITY : out std_logic_vector(0 to 1); + C405PLBICUREQUEST : out std_ulogic; + C405PLBICUSIZE : out std_logic_vector(2 to 3); + C405PLBICUU0ATTR : out std_ulogic; + C405RSTCHIPRESETREQ : out std_ulogic; + C405RSTCORERESETREQ : out std_ulogic; + C405RSTSYSRESETREQ : out std_ulogic; + C405TRCCYCLE : out std_ulogic; + C405TRCEVENEXECUTIONSTATUS : out std_logic_vector(0 to 1); + C405TRCODDEXECUTIONSTATUS : out std_logic_vector(0 to 1); + C405TRCTRACESTATUS : out std_logic_vector(0 to 3); + C405TRCTRIGGEREVENTOUT : out std_ulogic; + C405TRCTRIGGEREVENTTYPE : out std_logic_vector(0 to 10); + C405XXXMACHINECHECK : out std_ulogic; + DCREMACABUS : out std_logic_vector(8 to 9); + DCREMACCLK : out std_ulogic; + DCREMACDBUS : out std_logic_vector(0 to 31); + DCREMACENABLER : out std_ulogic; + DCREMACREAD : out std_ulogic; + DCREMACWRITE : out std_ulogic; + DSOCMBRAMABUS : out std_logic_vector(8 to 29); + DSOCMBRAMBYTEWRITE : out std_logic_vector(0 to 3); + DSOCMBRAMEN : out std_ulogic; + DSOCMBRAMWRDBUS : out std_logic_vector(0 to 31); + DSOCMBUSY : out std_ulogic; + DSOCMRDADDRVALID : out std_ulogic; + DSOCMWRADDRVALID : out std_ulogic; + EXTDCRABUS : out std_logic_vector(0 to 9); + EXTDCRDBUSOUT : out std_logic_vector(0 to 31); + EXTDCRREAD : out std_ulogic; + EXTDCRWRITE : out std_ulogic; + ISOCMBRAMEN : out std_ulogic; + ISOCMBRAMEVENWRITEEN : out std_ulogic; + ISOCMBRAMODDWRITEEN : out std_ulogic; + ISOCMBRAMRDABUS : out std_logic_vector(8 to 28); + ISOCMBRAMWRABUS : out std_logic_vector(8 to 28); + ISOCMBRAMWRDBUS : out std_logic_vector(0 to 31); + ISOCMDCRBRAMEVENEN : out std_ulogic; + ISOCMDCRBRAMODDEN : out std_ulogic; + ISOCMDCRBRAMRDSELECT : out std_ulogic; + BRAMDSOCMCLK : in std_ulogic; + BRAMDSOCMRDDBUS : in std_logic_vector(0 to 31); + BRAMISOCMCLK : in std_ulogic; + BRAMISOCMDCRRDDBUS : in std_logic_vector(0 to 31); + BRAMISOCMRDDBUS : in std_logic_vector(0 to 63); + CPMC405CLOCK : in std_ulogic; + CPMC405CORECLKINACTIVE : in std_ulogic; + CPMC405CPUCLKEN : in std_ulogic; + CPMC405JTAGCLKEN : in std_ulogic; + CPMC405SYNCBYPASS : in std_ulogic; + CPMC405TIMERCLKEN : in std_ulogic; + CPMC405TIMERTICK : in std_ulogic; + CPMDCRCLK : in std_ulogic; + CPMFCMCLK : in std_ulogic; + DBGC405DEBUGHALT : in std_ulogic; + DBGC405EXTBUSHOLDACK : in std_ulogic; + DBGC405UNCONDDEBUGEVENT : in std_ulogic; + DSARCVALUE : in std_logic_vector(0 to 7); + DSCNTLVALUE : in std_logic_vector(0 to 7); + DSOCMRWCOMPLETE : in std_ulogic; + EICC405CRITINPUTIRQ : in std_ulogic; + EICC405EXTINPUTIRQ : in std_ulogic; + EMACDCRACK : in std_ulogic; + EMACDCRDBUS : in std_logic_vector(0 to 31); + EXTDCRACK : in std_ulogic; + EXTDCRDBUSIN : in std_logic_vector(0 to 31); + FCMAPUCR : in std_logic_vector(0 to 3); + FCMAPUDCDCREN : in std_ulogic; + FCMAPUDCDFORCEALIGN : in std_ulogic; + FCMAPUDCDFORCEBESTEERING : in std_ulogic; + FCMAPUDCDFPUOP : in std_ulogic; + FCMAPUDCDGPRWRITE : in std_ulogic; + FCMAPUDCDLDSTBYTE : in std_ulogic; + FCMAPUDCDLDSTDW : in std_ulogic; + FCMAPUDCDLDSTHW : in std_ulogic; + FCMAPUDCDLDSTQW : in std_ulogic; + FCMAPUDCDLDSTWD : in std_ulogic; + FCMAPUDCDLOAD : in std_ulogic; + FCMAPUDCDPRIVOP : in std_ulogic; + FCMAPUDCDRAEN : in std_ulogic; + FCMAPUDCDRBEN : in std_ulogic; + FCMAPUDCDSTORE : in std_ulogic; + FCMAPUDCDTRAPBE : in std_ulogic; + FCMAPUDCDTRAPLE : in std_ulogic; + FCMAPUDCDUPDATE : in std_ulogic; + FCMAPUDCDXERCAEN : in std_ulogic; + FCMAPUDCDXEROVEN : in std_ulogic; + FCMAPUDECODEBUSY : in std_ulogic; + FCMAPUDONE : in std_ulogic; + FCMAPUEXCEPTION : in std_ulogic; + FCMAPUEXEBLOCKINGMCO : in std_ulogic; + FCMAPUEXECRFIELD : in std_logic_vector(0 to 2); + FCMAPUEXENONBLOCKINGMCO : in std_ulogic; + FCMAPUINSTRACK : in std_ulogic; + FCMAPULOADWAIT : in std_ulogic; + FCMAPURESULT : in std_logic_vector(0 to 31); + FCMAPURESULTVALID : in std_ulogic; + FCMAPUSLEEPNOTREADY : in std_ulogic; + FCMAPUXERCA : in std_ulogic; + FCMAPUXEROV : in std_ulogic; + ISARCVALUE : in std_logic_vector(0 to 7); + ISCNTLVALUE : in std_logic_vector(0 to 7); + JTGC405BNDSCANTDO : in std_ulogic; + JTGC405TCK : in std_ulogic; + JTGC405TDI : in std_ulogic; + JTGC405TMS : in std_ulogic; + JTGC405TRSTNEG : in std_ulogic; + MCBCPUCLKEN : in std_ulogic; + MCBJTAGEN : in std_ulogic; + MCBTIMEREN : in std_ulogic; + MCPPCRST : in std_ulogic; + PLBC405DCUADDRACK : in std_ulogic; + PLBC405DCUBUSY : in std_ulogic; + PLBC405DCUERR : in std_ulogic; + PLBC405DCURDDACK : in std_ulogic; + PLBC405DCURDDBUS : in std_logic_vector(0 to 63); + PLBC405DCURDWDADDR : in std_logic_vector(1 to 3); + PLBC405DCUSSIZE1 : in std_ulogic; + PLBC405DCUWRDACK : in std_ulogic; + PLBC405ICUADDRACK : in std_ulogic; + PLBC405ICUBUSY : in std_ulogic; + PLBC405ICUERR : in std_ulogic; + PLBC405ICURDDACK : in std_ulogic; + PLBC405ICURDDBUS : in std_logic_vector(0 to 63); + PLBC405ICURDWDADDR : in std_logic_vector(1 to 3); + PLBC405ICUSSIZE1 : in std_ulogic; + PLBCLK : in std_ulogic; + RSTC405RESETCHIP : in std_ulogic; + RSTC405RESETCORE : in std_ulogic; + RSTC405RESETSYS : in std_ulogic; + TIEAPUCONTROL : in std_logic_vector(0 to 15); + TIEAPUUDI1 : in std_logic_vector(0 to 23); + TIEAPUUDI2 : in std_logic_vector(0 to 23); + TIEAPUUDI3 : in std_logic_vector(0 to 23); + TIEAPUUDI4 : in std_logic_vector(0 to 23); + TIEAPUUDI5 : in std_logic_vector(0 to 23); + TIEAPUUDI6 : in std_logic_vector(0 to 23); + TIEAPUUDI7 : in std_logic_vector(0 to 23); + TIEAPUUDI8 : in std_logic_vector(0 to 23); + TIEC405DETERMINISTICMULT : in std_ulogic; + TIEC405DISOPERANDFWD : in std_ulogic; + TIEC405MMUEN : in std_ulogic; + TIEDCRADDR : in std_logic_vector(0 to 5); + TIEPVRBIT10 : in std_ulogic; + TIEPVRBIT11 : in std_ulogic; + TIEPVRBIT28 : in std_ulogic; + TIEPVRBIT29 : in std_ulogic; + TIEPVRBIT30 : in std_ulogic; + TIEPVRBIT31 : in std_ulogic; + TIEPVRBIT8 : in std_ulogic; + TIEPVRBIT9 : in std_ulogic; + TRCC405TRACEDISABLE : in std_ulogic; + TRCC405TRIGGEREVENTIN : in std_ulogic + ); +end component; +attribute BOX_TYPE of + PPC405_ADV : component is "PRIMITIVE"; + +----- component PPC405 ----- +component PPC405 + generic + ( + PPCUSER : std_logic_vector(0 to 3) := "0000" + ); + port + ( + C405CPMCORESLEEPREQ : out std_ulogic; + C405CPMMSRCE : out std_ulogic; + C405CPMMSREE : out std_ulogic; + C405CPMTIMERIRQ : out std_ulogic; + C405CPMTIMERRESETREQ : out std_ulogic; + C405DBGMSRWE : out std_ulogic; + C405DBGSTOPACK : out std_ulogic; + C405DBGWBCOMPLETE : out std_ulogic; + C405DBGWBFULL : out std_ulogic; + C405DBGWBIAR : out std_logic_vector(0 TO 29); + C405DCRABUS : out std_logic_vector(0 TO 9); + C405DCRDBUSOUT : out std_logic_vector(0 TO 31); + C405DCRREAD : out std_ulogic; + C405DCRWRITE : out std_ulogic; + C405JTGCAPTUREDR : out std_ulogic; + C405JTGEXTEST : out std_ulogic; + C405JTGPGMOUT : out std_ulogic; + C405JTGSHIFTDR : out std_ulogic; + C405JTGTDO : out std_ulogic; + C405JTGTDOEN : out std_ulogic; + C405JTGUPDATEDR : out std_ulogic; + C405PLBDCUABORT : out std_ulogic; + C405PLBDCUABUS : out std_logic_vector(0 TO 31); + C405PLBDCUBE : out std_logic_vector(0 TO 7); + C405PLBDCUCACHEABLE : out std_ulogic; + C405PLBDCUGUARDED : out std_ulogic; + C405PLBDCUPRIORITY : out std_logic_vector(0 TO 1); + C405PLBDCUREQUEST : out std_ulogic; + C405PLBDCURNW : out std_ulogic; + C405PLBDCUSIZE2 : out std_ulogic; + C405PLBDCUU0ATTR : out std_ulogic; + C405PLBDCUWRDBUS : out std_logic_vector(0 TO 63); + C405PLBDCUWRITETHRU : out std_ulogic; + C405PLBICUABORT : out std_ulogic; + C405PLBICUABUS : out std_logic_vector(0 TO 29); + C405PLBICUCACHEABLE : out std_ulogic; + C405PLBICUPRIORITY : out std_logic_vector(0 TO 1); + C405PLBICUREQUEST : out std_ulogic; + C405PLBICUSIZE : out std_logic_vector(2 TO 3); + C405PLBICUU0ATTR : out std_ulogic; + C405RSTCHIPRESETREQ : out std_ulogic; + C405RSTCORERESETREQ : out std_ulogic; + C405RSTSYSRESETREQ : out std_ulogic; + C405TRCCYCLE : out std_ulogic; + C405TRCEVENEXECUTIONSTATUS : out std_logic_vector(0 TO 1); + C405TRCODDEXECUTIONSTATUS : out std_logic_vector(0 TO 1); + C405TRCTRACESTATUS : out std_logic_vector(0 TO 3); + C405TRCTRIGGEREVENTOUT : out std_ulogic; + C405TRCTRIGGEREVENTTYPE : out std_logic_vector(0 TO 10); + C405XXXMACHINECHECK : out std_ulogic; + DSOCMBRAMABUS : out std_logic_vector(8 TO 29); + DSOCMBRAMBYTEWRITE : out std_logic_vector(0 TO 3); + DSOCMBRAMEN : out std_ulogic; + DSOCMBRAMWRDBUS : out std_logic_vector(0 TO 31); + DSOCMBUSY : out std_ulogic; + ISOCMBRAMEN : out std_ulogic; + ISOCMBRAMEVENWRITEEN : out std_ulogic; + ISOCMBRAMODDWRITEEN : out std_ulogic; + ISOCMBRAMRDABUS : out std_logic_vector(8 TO 28); + ISOCMBRAMWRABUS : out std_logic_vector(8 TO 28); + ISOCMBRAMWRDBUS : out std_logic_vector(0 TO 31); + BRAMDSOCMCLK : in std_ulogic; + BRAMDSOCMRDDBUS : in std_logic_vector(0 TO 31); + BRAMISOCMCLK : in std_ulogic; + BRAMISOCMRDDBUS : in std_logic_vector(0 TO 63); + CPMC405CLOCK : in std_ulogic; + CPMC405CORECLKINACTIVE : in std_ulogic; + CPMC405CPUCLKEN : in std_ulogic; + CPMC405JTAGCLKEN : in std_ulogic; + CPMC405TIMERCLKEN : in std_ulogic; + CPMC405TIMERTICK : in std_ulogic; + DBGC405DEBUGHALT : in std_ulogic; + DBGC405EXTBUSHOLDACK : in std_ulogic; + DBGC405UNCONDDEBUGEVENT : in std_ulogic; + DCRC405ACK : in std_ulogic; + DCRC405DBUSIN : in std_logic_vector(0 TO 31); + DSARCVALUE : in std_logic_vector(0 TO 7); + DSCNTLVALUE : in std_logic_vector(0 TO 7); + EICC405CRITINPUTIRQ : in std_ulogic; + EICC405EXTINPUTIRQ : in std_ulogic; + ISARCVALUE : in std_logic_vector(0 TO 7); + ISCNTLVALUE : in std_logic_vector(0 TO 7); + JTGC405BNDSCANTDO : in std_ulogic; + JTGC405TCK : in std_ulogic; + JTGC405TDI : in std_ulogic; + JTGC405TMS : in std_ulogic; + JTGC405TRSTNEG : in std_ulogic; + MCBCPUCLKEN : in std_ulogic; + MCBJTAGEN : in std_ulogic; + MCBTIMEREN : in std_ulogic; + MCPPCRST : in std_ulogic; + PLBC405DCUADDRACK : in std_ulogic; + PLBC405DCUBUSY : in std_ulogic; + PLBC405DCUERR : in std_ulogic; + PLBC405DCURDDACK : in std_ulogic; + PLBC405DCURDDBUS : in std_logic_vector(0 TO 63); + PLBC405DCURDWDADDR : in std_logic_vector(1 TO 3); + PLBC405DCUSSIZE1 : in std_ulogic; + PLBC405DCUWRDACK : in std_ulogic; + PLBC405ICUADDRACK : in std_ulogic; + PLBC405ICUBUSY : in std_ulogic; + PLBC405ICUERR : in std_ulogic; + PLBC405ICURDDACK : in std_ulogic; + PLBC405ICURDDBUS : in std_logic_vector(0 TO 63); + PLBC405ICURDWDADDR : in std_logic_vector(1 TO 3); + PLBC405ICUSSIZE1 : in std_ulogic; + PLBCLK : in std_ulogic; + RSTC405RESETCHIP : in std_ulogic; + RSTC405RESETCORE : in std_ulogic; + RSTC405RESETSYS : in std_ulogic; + TIEC405DETERMINISTICMULT : in std_ulogic; + TIEC405DISOPERANDFWD : in std_ulogic; + TIEC405MMUEN : in std_ulogic; + TIEDSOCMDCRADDR : in std_logic_vector(0 TO 7); + TIEISOCMDCRADDR : in std_logic_vector(0 TO 7); + TRCC405TRACEDISABLE : in std_ulogic; + TRCC405TRIGGEREVENTIN : in std_ulogic + ); +end component; +attribute BOX_TYPE of + PPC405 : component is "PRIMITIVE"; + +----- component PPC440 ----- +component PPC440 + generic + ( + APU_CONTROL : bit_vector := X"02000"; + APU_UDI0 : bit_vector := X"000000"; + APU_UDI1 : bit_vector := X"000000"; + APU_UDI10 : bit_vector := X"000000"; + APU_UDI11 : bit_vector := X"000000"; + APU_UDI12 : bit_vector := X"000000"; + APU_UDI13 : bit_vector := X"000000"; + APU_UDI14 : bit_vector := X"000000"; + APU_UDI15 : bit_vector := X"000000"; + APU_UDI2 : bit_vector := X"000000"; + APU_UDI3 : bit_vector := X"000000"; + APU_UDI4 : bit_vector := X"000000"; + APU_UDI5 : bit_vector := X"000000"; + APU_UDI6 : bit_vector := X"000000"; + APU_UDI7 : bit_vector := X"000000"; + APU_UDI8 : bit_vector := X"000000"; + APU_UDI9 : bit_vector := X"000000"; + CLOCK_DELAY : boolean := FALSE; + DCR_AUTOLOCK_ENABLE : boolean := TRUE; + DMA0_CONTROL : bit_vector := X"00"; + DMA0_RXCHANNELCTRL : bit_vector := X"01010000"; + DMA0_RXIRQTIMER : bit_vector := X"3FF"; + DMA0_TXCHANNELCTRL : bit_vector := X"01010000"; + DMA0_TXIRQTIMER : bit_vector := X"3FF"; + DMA1_CONTROL : bit_vector := X"00"; + DMA1_RXCHANNELCTRL : bit_vector := X"01010000"; + DMA1_RXIRQTIMER : bit_vector := X"3FF"; + DMA1_TXCHANNELCTRL : bit_vector := X"01010000"; + DMA1_TXIRQTIMER : bit_vector := X"3FF"; + DMA2_CONTROL : bit_vector := X"00"; + DMA2_RXCHANNELCTRL : bit_vector := X"01010000"; + DMA2_RXIRQTIMER : bit_vector := X"3FF"; + DMA2_TXCHANNELCTRL : bit_vector := X"01010000"; + DMA2_TXIRQTIMER : bit_vector := X"3FF"; + DMA3_CONTROL : bit_vector := X"00"; + DMA3_RXCHANNELCTRL : bit_vector := X"01010000"; + DMA3_RXIRQTIMER : bit_vector := X"3FF"; + DMA3_TXCHANNELCTRL : bit_vector := X"01010000"; + DMA3_TXIRQTIMER : bit_vector := X"3FF"; + INTERCONNECT_IMASK : bit_vector := X"FFFFFFFF"; + INTERCONNECT_TMPL_SEL : bit_vector := X"3FFFFFFF"; + MI_ARBCONFIG : bit_vector := X"00432010"; + MI_BANKCONFLICT_MASK : bit_vector := X"00000000"; + MI_CONTROL : bit_vector := X"0000008F"; + MI_ROWCONFLICT_MASK : bit_vector := X"00000000"; + PPCDM_ASYNCMODE : boolean := FALSE; + PPCDS_ASYNCMODE : boolean := FALSE; + PPCM_ARBCONFIG : bit_vector := X"00432010"; + PPCM_CONTROL : bit_vector := X"8000009F"; + PPCM_COUNTER : bit_vector := X"00000500"; + PPCS0_ADDRMAP_TMPL0 : bit_vector := X"FFFFFFFF"; + PPCS0_ADDRMAP_TMPL1 : bit_vector := X"FFFFFFFF"; + PPCS0_ADDRMAP_TMPL2 : bit_vector := X"FFFFFFFF"; + PPCS0_ADDRMAP_TMPL3 : bit_vector := X"FFFFFFFF"; + PPCS0_CONTROL : bit_vector := X"8033336C"; + PPCS0_WIDTH_128N64 : boolean := TRUE; + PPCS1_ADDRMAP_TMPL0 : bit_vector := X"FFFFFFFF"; + PPCS1_ADDRMAP_TMPL1 : bit_vector := X"FFFFFFFF"; + PPCS1_ADDRMAP_TMPL2 : bit_vector := X"FFFFFFFF"; + PPCS1_ADDRMAP_TMPL3 : bit_vector := X"FFFFFFFF"; + PPCS1_CONTROL : bit_vector := X"8033336C"; + PPCS1_WIDTH_128N64 : boolean := TRUE; + XBAR_ADDRMAP_TMPL0 : bit_vector := X"FFFF0000"; + XBAR_ADDRMAP_TMPL1 : bit_vector := X"00000000"; + XBAR_ADDRMAP_TMPL2 : bit_vector := X"00000000"; + XBAR_ADDRMAP_TMPL3 : bit_vector := X"00000000" + ); + port + ( + APUFCMDECFPUOP : out std_ulogic; + APUFCMDECLDSTXFERSIZE : out std_logic_vector(0 to 2); + APUFCMDECLOAD : out std_ulogic; + APUFCMDECNONAUTON : out std_ulogic; + APUFCMDECSTORE : out std_ulogic; + APUFCMDECUDI : out std_logic_vector(0 to 3); + APUFCMDECUDIVALID : out std_ulogic; + APUFCMENDIAN : out std_ulogic; + APUFCMFLUSH : out std_ulogic; + APUFCMINSTRUCTION : out std_logic_vector(0 to 31); + APUFCMINSTRVALID : out std_ulogic; + APUFCMLOADBYTEADDR : out std_logic_vector(0 to 3); + APUFCMLOADDATA : out std_logic_vector(0 to 127); + APUFCMLOADDVALID : out std_ulogic; + APUFCMMSRFE0 : out std_ulogic; + APUFCMMSRFE1 : out std_ulogic; + APUFCMNEXTINSTRREADY : out std_ulogic; + APUFCMOPERANDVALID : out std_ulogic; + APUFCMRADATA : out std_logic_vector(0 to 31); + APUFCMRBDATA : out std_logic_vector(0 to 31); + APUFCMWRITEBACKOK : out std_ulogic; + C440CPMCORESLEEPREQ : out std_ulogic; + C440CPMDECIRPTREQ : out std_ulogic; + C440CPMFITIRPTREQ : out std_ulogic; + C440CPMMSRCE : out std_ulogic; + C440CPMMSREE : out std_ulogic; + C440CPMTIMERRESETREQ : out std_ulogic; + C440CPMWDIRPTREQ : out std_ulogic; + C440DBGSYSTEMCONTROL : out std_logic_vector(0 to 7); + C440JTGTDO : out std_ulogic; + C440JTGTDOEN : out std_ulogic; + C440MACHINECHECK : out std_ulogic; + C440RSTCHIPRESETREQ : out std_ulogic; + C440RSTCORERESETREQ : out std_ulogic; + C440RSTSYSTEMRESETREQ : out std_ulogic; + C440TRCBRANCHSTATUS : out std_logic_vector(0 to 2); + C440TRCCYCLE : out std_ulogic; + C440TRCEXECUTIONSTATUS : out std_logic_vector(0 to 4); + C440TRCTRACESTATUS : out std_logic_vector(0 to 6); + C440TRCTRIGGEREVENTOUT : out std_ulogic; + C440TRCTRIGGEREVENTTYPE : out std_logic_vector(0 to 13); + DMA0LLRSTENGINEACK : out std_ulogic; + DMA0LLRXDSTRDYN : out std_ulogic; + DMA0LLTXD : out std_logic_vector(0 to 31); + DMA0LLTXEOFN : out std_ulogic; + DMA0LLTXEOPN : out std_ulogic; + DMA0LLTXREM : out std_logic_vector(0 to 3); + DMA0LLTXSOFN : out std_ulogic; + DMA0LLTXSOPN : out std_ulogic; + DMA0LLTXSRCRDYN : out std_ulogic; + DMA0RXIRQ : out std_ulogic; + DMA0TXIRQ : out std_ulogic; + DMA1LLRSTENGINEACK : out std_ulogic; + DMA1LLRXDSTRDYN : out std_ulogic; + DMA1LLTXD : out std_logic_vector(0 to 31); + DMA1LLTXEOFN : out std_ulogic; + DMA1LLTXEOPN : out std_ulogic; + DMA1LLTXREM : out std_logic_vector(0 to 3); + DMA1LLTXSOFN : out std_ulogic; + DMA1LLTXSOPN : out std_ulogic; + DMA1LLTXSRCRDYN : out std_ulogic; + DMA1RXIRQ : out std_ulogic; + DMA1TXIRQ : out std_ulogic; + DMA2LLRSTENGINEACK : out std_ulogic; + DMA2LLRXDSTRDYN : out std_ulogic; + DMA2LLTXD : out std_logic_vector(0 to 31); + DMA2LLTXEOFN : out std_ulogic; + DMA2LLTXEOPN : out std_ulogic; + DMA2LLTXREM : out std_logic_vector(0 to 3); + DMA2LLTXSOFN : out std_ulogic; + DMA2LLTXSOPN : out std_ulogic; + DMA2LLTXSRCRDYN : out std_ulogic; + DMA2RXIRQ : out std_ulogic; + DMA2TXIRQ : out std_ulogic; + DMA3LLRSTENGINEACK : out std_ulogic; + DMA3LLRXDSTRDYN : out std_ulogic; + DMA3LLTXD : out std_logic_vector(0 to 31); + DMA3LLTXEOFN : out std_ulogic; + DMA3LLTXEOPN : out std_ulogic; + DMA3LLTXREM : out std_logic_vector(0 to 3); + DMA3LLTXSOFN : out std_ulogic; + DMA3LLTXSOPN : out std_ulogic; + DMA3LLTXSRCRDYN : out std_ulogic; + DMA3RXIRQ : out std_ulogic; + DMA3TXIRQ : out std_ulogic; + MIMCADDRESS : out std_logic_vector(0 to 35); + MIMCADDRESSVALID : out std_ulogic; + MIMCBANKCONFLICT : out std_ulogic; + MIMCBYTEENABLE : out std_logic_vector(0 to 15); + MIMCREADNOTWRITE : out std_ulogic; + MIMCROWCONFLICT : out std_ulogic; + MIMCWRITEDATA : out std_logic_vector(0 to 127); + MIMCWRITEDATAVALID : out std_ulogic; + PPCCPMINTERCONNECTBUSY : out std_ulogic; + PPCDMDCRABUS : out std_logic_vector(0 to 9); + PPCDMDCRDBUSOUT : out std_logic_vector(0 to 31); + PPCDMDCRREAD : out std_ulogic; + PPCDMDCRUABUS : out std_logic_vector(20 to 21); + PPCDMDCRWRITE : out std_ulogic; + PPCDSDCRACK : out std_ulogic; + PPCDSDCRDBUSIN : out std_logic_vector(0 to 31); + PPCDSDCRTIMEOUTWAIT : out std_ulogic; + PPCEICINTERCONNECTIRQ : out std_ulogic; + PPCMPLBABORT : out std_ulogic; + PPCMPLBABUS : out std_logic_vector(0 to 31); + PPCMPLBBE : out std_logic_vector(0 to 15); + PPCMPLBBUSLOCK : out std_ulogic; + PPCMPLBLOCKERR : out std_ulogic; + PPCMPLBPRIORITY : out std_logic_vector(0 to 1); + PPCMPLBRDBURST : out std_ulogic; + PPCMPLBREQUEST : out std_ulogic; + PPCMPLBRNW : out std_ulogic; + PPCMPLBSIZE : out std_logic_vector(0 to 3); + PPCMPLBTATTRIBUTE : out std_logic_vector(0 to 15); + PPCMPLBTYPE : out std_logic_vector(0 to 2); + PPCMPLBUABUS : out std_logic_vector(28 to 31); + PPCMPLBWRBURST : out std_ulogic; + PPCMPLBWRDBUS : out std_logic_vector(0 to 127); + PPCS0PLBADDRACK : out std_ulogic; + PPCS0PLBMBUSY : out std_logic_vector(0 to 3); + PPCS0PLBMIRQ : out std_logic_vector(0 to 3); + PPCS0PLBMRDERR : out std_logic_vector(0 to 3); + PPCS0PLBMWRERR : out std_logic_vector(0 to 3); + PPCS0PLBRDBTERM : out std_ulogic; + PPCS0PLBRDCOMP : out std_ulogic; + PPCS0PLBRDDACK : out std_ulogic; + PPCS0PLBRDDBUS : out std_logic_vector(0 to 127); + PPCS0PLBRDWDADDR : out std_logic_vector(0 to 3); + PPCS0PLBREARBITRATE : out std_ulogic; + PPCS0PLBSSIZE : out std_logic_vector(0 to 1); + PPCS0PLBWAIT : out std_ulogic; + PPCS0PLBWRBTERM : out std_ulogic; + PPCS0PLBWRCOMP : out std_ulogic; + PPCS0PLBWRDACK : out std_ulogic; + PPCS1PLBADDRACK : out std_ulogic; + PPCS1PLBMBUSY : out std_logic_vector(0 to 3); + PPCS1PLBMIRQ : out std_logic_vector(0 to 3); + PPCS1PLBMRDERR : out std_logic_vector(0 to 3); + PPCS1PLBMWRERR : out std_logic_vector(0 to 3); + PPCS1PLBRDBTERM : out std_ulogic; + PPCS1PLBRDCOMP : out std_ulogic; + PPCS1PLBRDDACK : out std_ulogic; + PPCS1PLBRDDBUS : out std_logic_vector(0 to 127); + PPCS1PLBRDWDADDR : out std_logic_vector(0 to 3); + PPCS1PLBREARBITRATE : out std_ulogic; + PPCS1PLBSSIZE : out std_logic_vector(0 to 1); + PPCS1PLBWAIT : out std_ulogic; + PPCS1PLBWRBTERM : out std_ulogic; + PPCS1PLBWRCOMP : out std_ulogic; + PPCS1PLBWRDACK : out std_ulogic; + CPMC440CLK : in std_ulogic; + CPMC440CLKEN : in std_ulogic; + CPMC440CORECLOCKINACTIVE : in std_ulogic; + CPMC440TIMERCLOCK : in std_ulogic; + CPMDCRCLK : in std_ulogic; + CPMDMA0LLCLK : in std_ulogic; + CPMDMA1LLCLK : in std_ulogic; + CPMDMA2LLCLK : in std_ulogic; + CPMDMA3LLCLK : in std_ulogic; + CPMFCMCLK : in std_ulogic; + CPMINTERCONNECTCLK : in std_ulogic; + CPMINTERCONNECTCLKEN : in std_ulogic; + CPMINTERCONNECTCLKNTO1 : in std_ulogic; + CPMMCCLK : in std_ulogic; + CPMPPCMPLBCLK : in std_ulogic; + CPMPPCS0PLBCLK : in std_ulogic; + CPMPPCS1PLBCLK : in std_ulogic; + DBGC440DEBUGHALT : in std_ulogic; + DBGC440SYSTEMSTATUS : in std_logic_vector(0 to 4); + DBGC440UNCONDDEBUGEVENT : in std_ulogic; + DCRPPCDMACK : in std_ulogic; + DCRPPCDMDBUSIN : in std_logic_vector(0 to 31); + DCRPPCDMTIMEOUTWAIT : in std_ulogic; + DCRPPCDSABUS : in std_logic_vector(0 to 9); + DCRPPCDSDBUSOUT : in std_logic_vector(0 to 31); + DCRPPCDSREAD : in std_ulogic; + DCRPPCDSWRITE : in std_ulogic; + EICC440CRITIRQ : in std_ulogic; + EICC440EXTIRQ : in std_ulogic; + FCMAPUCONFIRMINSTR : in std_ulogic; + FCMAPUCR : in std_logic_vector(0 to 3); + FCMAPUDONE : in std_ulogic; + FCMAPUEXCEPTION : in std_ulogic; + FCMAPUFPSCRFEX : in std_ulogic; + FCMAPURESULT : in std_logic_vector(0 to 31); + FCMAPURESULTVALID : in std_ulogic; + FCMAPUSLEEPNOTREADY : in std_ulogic; + FCMAPUSTOREDATA : in std_logic_vector(0 to 127); + JTGC440TCK : in std_ulogic; + JTGC440TDI : in std_ulogic; + JTGC440TMS : in std_ulogic; + JTGC440TRSTNEG : in std_ulogic; + LLDMA0RSTENGINEREQ : in std_ulogic; + LLDMA0RXD : in std_logic_vector(0 to 31); + LLDMA0RXEOFN : in std_ulogic; + LLDMA0RXEOPN : in std_ulogic; + LLDMA0RXREM : in std_logic_vector(0 to 3); + LLDMA0RXSOFN : in std_ulogic; + LLDMA0RXSOPN : in std_ulogic; + LLDMA0RXSRCRDYN : in std_ulogic; + LLDMA0TXDSTRDYN : in std_ulogic; + LLDMA1RSTENGINEREQ : in std_ulogic; + LLDMA1RXD : in std_logic_vector(0 to 31); + LLDMA1RXEOFN : in std_ulogic; + LLDMA1RXEOPN : in std_ulogic; + LLDMA1RXREM : in std_logic_vector(0 to 3); + LLDMA1RXSOFN : in std_ulogic; + LLDMA1RXSOPN : in std_ulogic; + LLDMA1RXSRCRDYN : in std_ulogic; + LLDMA1TXDSTRDYN : in std_ulogic; + LLDMA2RSTENGINEREQ : in std_ulogic; + LLDMA2RXD : in std_logic_vector(0 to 31); + LLDMA2RXEOFN : in std_ulogic; + LLDMA2RXEOPN : in std_ulogic; + LLDMA2RXREM : in std_logic_vector(0 to 3); + LLDMA2RXSOFN : in std_ulogic; + LLDMA2RXSOPN : in std_ulogic; + LLDMA2RXSRCRDYN : in std_ulogic; + LLDMA2TXDSTRDYN : in std_ulogic; + LLDMA3RSTENGINEREQ : in std_ulogic; + LLDMA3RXD : in std_logic_vector(0 to 31); + LLDMA3RXEOFN : in std_ulogic; + LLDMA3RXEOPN : in std_ulogic; + LLDMA3RXREM : in std_logic_vector(0 to 3); + LLDMA3RXSOFN : in std_ulogic; + LLDMA3RXSOPN : in std_ulogic; + LLDMA3RXSRCRDYN : in std_ulogic; + LLDMA3TXDSTRDYN : in std_ulogic; + MCMIADDRREADYTOACCEPT : in std_ulogic; + MCMIREADDATA : in std_logic_vector(0 to 127); + MCMIREADDATAERR : in std_ulogic; + MCMIREADDATAVALID : in std_ulogic; + PLBPPCMADDRACK : in std_ulogic; + PLBPPCMMBUSY : in std_ulogic; + PLBPPCMMIRQ : in std_ulogic; + PLBPPCMMRDERR : in std_ulogic; + PLBPPCMMWRERR : in std_ulogic; + PLBPPCMRDBTERM : in std_ulogic; + PLBPPCMRDDACK : in std_ulogic; + PLBPPCMRDDBUS : in std_logic_vector(0 to 127); + PLBPPCMRDPENDPRI : in std_logic_vector(0 to 1); + PLBPPCMRDPENDREQ : in std_ulogic; + PLBPPCMRDWDADDR : in std_logic_vector(0 to 3); + PLBPPCMREARBITRATE : in std_ulogic; + PLBPPCMREQPRI : in std_logic_vector(0 to 1); + PLBPPCMSSIZE : in std_logic_vector(0 to 1); + PLBPPCMTIMEOUT : in std_ulogic; + PLBPPCMWRBTERM : in std_ulogic; + PLBPPCMWRDACK : in std_ulogic; + PLBPPCMWRPENDPRI : in std_logic_vector(0 to 1); + PLBPPCMWRPENDREQ : in std_ulogic; + PLBPPCS0ABORT : in std_ulogic; + PLBPPCS0ABUS : in std_logic_vector(0 to 31); + PLBPPCS0BE : in std_logic_vector(0 to 15); + PLBPPCS0BUSLOCK : in std_ulogic; + PLBPPCS0LOCKERR : in std_ulogic; + PLBPPCS0MASTERID : in std_logic_vector(0 to 1); + PLBPPCS0MSIZE : in std_logic_vector(0 to 1); + PLBPPCS0PAVALID : in std_ulogic; + PLBPPCS0RDBURST : in std_ulogic; + PLBPPCS0RDPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS0RDPENDREQ : in std_ulogic; + PLBPPCS0RDPRIM : in std_ulogic; + PLBPPCS0REQPRI : in std_logic_vector(0 to 1); + PLBPPCS0RNW : in std_ulogic; + PLBPPCS0SAVALID : in std_ulogic; + PLBPPCS0SIZE : in std_logic_vector(0 to 3); + PLBPPCS0TATTRIBUTE : in std_logic_vector(0 to 15); + PLBPPCS0TYPE : in std_logic_vector(0 to 2); + PLBPPCS0UABUS : in std_logic_vector(28 to 31); + PLBPPCS0WRBURST : in std_ulogic; + PLBPPCS0WRDBUS : in std_logic_vector(0 to 127); + PLBPPCS0WRPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS0WRPENDREQ : in std_ulogic; + PLBPPCS0WRPRIM : in std_ulogic; + PLBPPCS1ABORT : in std_ulogic; + PLBPPCS1ABUS : in std_logic_vector(0 to 31); + PLBPPCS1BE : in std_logic_vector(0 to 15); + PLBPPCS1BUSLOCK : in std_ulogic; + PLBPPCS1LOCKERR : in std_ulogic; + PLBPPCS1MASTERID : in std_logic_vector(0 to 1); + PLBPPCS1MSIZE : in std_logic_vector(0 to 1); + PLBPPCS1PAVALID : in std_ulogic; + PLBPPCS1RDBURST : in std_ulogic; + PLBPPCS1RDPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS1RDPENDREQ : in std_ulogic; + PLBPPCS1RDPRIM : in std_ulogic; + PLBPPCS1REQPRI : in std_logic_vector(0 to 1); + PLBPPCS1RNW : in std_ulogic; + PLBPPCS1SAVALID : in std_ulogic; + PLBPPCS1SIZE : in std_logic_vector(0 to 3); + PLBPPCS1TATTRIBUTE : in std_logic_vector(0 to 15); + PLBPPCS1TYPE : in std_logic_vector(0 to 2); + PLBPPCS1UABUS : in std_logic_vector(28 to 31); + PLBPPCS1WRBURST : in std_ulogic; + PLBPPCS1WRDBUS : in std_logic_vector(0 to 127); + PLBPPCS1WRPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS1WRPENDREQ : in std_ulogic; + PLBPPCS1WRPRIM : in std_ulogic; + RSTC440RESETCHIP : in std_ulogic; + RSTC440RESETCORE : in std_ulogic; + RSTC440RESETSYSTEM : in std_ulogic; + TIEC440DCURDLDCACHEPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCURDNONCACHEPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCURDTOUCHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCURDURGENTPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCUWRFLUSHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCUWRSTOREPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCUWRURGENTPLBPRIO : in std_logic_vector(0 to 1); + TIEC440ENDIANRESET : in std_ulogic; + TIEC440ERPNRESET : in std_logic_vector(0 to 3); + TIEC440ICURDFETCHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440ICURDSPECPLBPRIO : in std_logic_vector(0 to 1); + TIEC440ICURDTOUCHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440PIR : in std_logic_vector(28 to 31); + TIEC440PVR : in std_logic_vector(28 to 31); + TIEC440USERRESET : in std_logic_vector(0 to 3); + TIEDCRBASEADDR : in std_logic_vector(0 to 1); + TRCC440TRACEDISABLE : in std_ulogic; + TRCC440TRIGGEREVENTIN : in std_ulogic + ); +end component; +attribute BOX_TYPE of + PPC440 : component is "PRIMITIVE"; + +----- component PULLDOWN ----- +component PULLDOWN + port + ( + O : out std_ulogic := 'L' + ); +end component; +attribute BOX_TYPE of + PULLDOWN : component is "PRIMITIVE"; + +----- component PULLUP ----- +component PULLUP + port + ( + O : out std_ulogic := 'H' + ); +end component; +attribute BOX_TYPE of + PULLUP : component is "PRIMITIVE"; + +----- component RAM128X1D ----- +component RAM128X1D + generic + ( + INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000" + ); + port + ( + DPO : out std_ulogic; + SPO : out std_ulogic; + A : in std_logic_vector(6 downto 0); + D : in std_ulogic; + DPRA : in std_logic_vector(6 downto 0); + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM128X1D : component is "PRIMITIVE"; + +----- component RAM128X1S_1 ----- +component RAM128X1S_1 + generic + ( + INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000" + ); + port + ( + O : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic; + A6 : in std_ulogic; + D : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM128X1S_1 : component is "PRIMITIVE"; + +----- component RAM128X1S ----- +component RAM128X1S + generic + ( + INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000" + ); + port + ( + O : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic; + A6 : in std_ulogic; + D : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM128X1S : component is "PRIMITIVE"; + +----- component RAM16X1D_1 ----- +component RAM16X1D_1 + generic + ( + INIT : bit_vector(15 downto 0) := X"0000" + ); + port + ( + DPO : out std_ulogic; + SPO : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + D : in std_ulogic; + DPRA0 : in std_ulogic; + DPRA1 : in std_ulogic; + DPRA2 : in std_ulogic; + DPRA3 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM16X1D_1 : component is "PRIMITIVE"; + +----- component RAM16X1D ----- +component RAM16X1D + generic + ( + INIT : bit_vector(15 downto 0) := X"0000" + ); + port + ( + DPO : out std_ulogic; + SPO : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + D : in std_ulogic; + DPRA0 : in std_ulogic; + DPRA1 : in std_ulogic; + DPRA2 : in std_ulogic; + DPRA3 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM16X1D : component is "PRIMITIVE"; + +----- component RAM16X1S_1 ----- +component RAM16X1S_1 + generic + ( + INIT : bit_vector(15 downto 0) := X"0000" + ); + port + ( + O : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + D : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM16X1S_1 : component is "PRIMITIVE"; + +----- component RAM16X1S ----- +component RAM16X1S + generic + ( + INIT : bit_vector(15 downto 0) := X"0000" + ); + port + ( + O : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + D : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM16X1S : component is "PRIMITIVE"; + +----- component RAM16X2S ----- +component RAM16X2S + generic + ( + INIT_00 : bit_vector(15 downto 0) := X"0000"; + INIT_01 : bit_vector(15 downto 0) := X"0000" + ); + port + ( + O0 : out std_ulogic; + O1 : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM16X2S : component is "PRIMITIVE"; + +----- component RAM16X4S ----- +component RAM16X4S + generic + ( + INIT_00 : bit_vector(15 downto 0) := X"0000"; + INIT_01 : bit_vector(15 downto 0) := X"0000"; + INIT_02 : bit_vector(15 downto 0) := X"0000"; + INIT_03 : bit_vector(15 downto 0) := X"0000" + ); + port + ( + O0 : out std_ulogic; + O1 : out std_ulogic; + O2 : out std_ulogic; + O3 : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + D2 : in std_ulogic; + D3 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM16X4S : component is "PRIMITIVE"; + +----- component RAM16X8S ----- +component RAM16X8S + generic + ( + INIT_00 : bit_vector(15 downto 0) := X"0000"; + INIT_01 : bit_vector(15 downto 0) := X"0000"; + INIT_02 : bit_vector(15 downto 0) := X"0000"; + INIT_03 : bit_vector(15 downto 0) := X"0000"; + INIT_04 : bit_vector(15 downto 0) := X"0000"; + INIT_05 : bit_vector(15 downto 0) := X"0000"; + INIT_06 : bit_vector(15 downto 0) := X"0000"; + INIT_07 : bit_vector(15 downto 0) := X"0000" + ); + port + ( + O : out std_logic_vector ( 7 downto 0); + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + D : in std_logic_vector ( 7 downto 0); + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM16X8S : component is "PRIMITIVE"; + +----- component RAM256X1S ----- +component RAM256X1S + generic + ( + INIT : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + O : out std_ulogic; + A : in std_logic_vector(7 downto 0); + D : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM256X1S : component is "PRIMITIVE"; + +----- component RAM32M ----- +component RAM32M + generic + ( + INIT_A : bit_vector(63 downto 0) := X"0000000000000000"; + INIT_B : bit_vector(63 downto 0) := X"0000000000000000"; + INIT_C : bit_vector(63 downto 0) := X"0000000000000000"; + INIT_D : bit_vector(63 downto 0) := X"0000000000000000" + ); + port + ( + DOA : out std_logic_vector (1 downto 0); + DOB : out std_logic_vector (1 downto 0); + DOC : out std_logic_vector (1 downto 0); + DOD : out std_logic_vector (1 downto 0); + ADDRA : in std_logic_vector(4 downto 0); + ADDRB : in std_logic_vector(4 downto 0); + ADDRC : in std_logic_vector(4 downto 0); + ADDRD : in std_logic_vector(4 downto 0); + DIA : in std_logic_vector (1 downto 0); + DIB : in std_logic_vector (1 downto 0); + DIC : in std_logic_vector (1 downto 0); + DID : in std_logic_vector (1 downto 0); + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM32M : component is "PRIMITIVE"; + +----- component RAM32X1D_1 ----- +component RAM32X1D_1 + generic + ( + INIT : bit_vector(31 downto 0) := X"00000000" + ); + port + ( + DPO : out std_ulogic; + SPO : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + D : in std_ulogic; + DPRA0 : in std_ulogic; + DPRA1 : in std_ulogic; + DPRA2 : in std_ulogic; + DPRA3 : in std_ulogic; + DPRA4 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM32X1D_1 : component is "PRIMITIVE"; + +----- component RAM32X1D ----- +component RAM32X1D + generic + ( + INIT : bit_vector(31 downto 0) := X"00000000" + ); + port + ( + DPO : out std_ulogic; + SPO : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + D : in std_ulogic; + DPRA0 : in std_ulogic; + DPRA1 : in std_ulogic; + DPRA2 : in std_ulogic; + DPRA3 : in std_ulogic; + DPRA4 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM32X1D : component is "PRIMITIVE"; + +----- component RAM32X1S_1 ----- +component RAM32X1S_1 + generic + ( + INIT : bit_vector(31 downto 0) := X"00000000" + ); + port + ( + O : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + D : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM32X1S_1 : component is "PRIMITIVE"; + +----- component RAM32X1S ----- +component RAM32X1S + generic + ( + INIT : bit_vector(31 downto 0) := X"00000000" + ); + port + ( + O : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + D : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM32X1S : component is "PRIMITIVE"; + +----- component RAM32X2S ----- +component RAM32X2S + generic + ( + INIT_00 : bit_vector(31 downto 0) := X"00000000"; + INIT_01 : bit_vector(31 downto 0) := X"00000000" + ); + port + ( + O0 : out std_ulogic; + O1 : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM32X2S : component is "PRIMITIVE"; + +----- component RAM32X4S ----- +component RAM32X4S + generic + ( + INIT_00 : bit_vector(31 downto 0) := X"00000000"; + INIT_01 : bit_vector(31 downto 0) := X"00000000"; + INIT_02 : bit_vector(31 downto 0) := X"00000000"; + INIT_03 : bit_vector(31 downto 0) := X"00000000" + ); + port + ( + O0 : out std_ulogic; + O1 : out std_ulogic; + O2 : out std_ulogic; + O3 : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + D2 : in std_ulogic; + D3 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM32X4S : component is "PRIMITIVE"; + +----- component RAM32X8S ----- +component RAM32X8S + generic + ( + INIT_00 : bit_vector(31 downto 0) := X"00000000"; + INIT_01 : bit_vector(31 downto 0) := X"00000000"; + INIT_02 : bit_vector(31 downto 0) := X"00000000"; + INIT_03 : bit_vector(31 downto 0) := X"00000000"; + INIT_04 : bit_vector(31 downto 0) := X"00000000"; + INIT_05 : bit_vector(31 downto 0) := X"00000000"; + INIT_06 : bit_vector(31 downto 0) := X"00000000"; + INIT_07 : bit_vector(31 downto 0) := X"00000000" + ); + port + ( + O : out std_logic_vector ( 7 downto 0); + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + D : in std_logic_vector ( 7 downto 0); + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM32X8S : component is "PRIMITIVE"; + +----- component RAM64M ----- +component RAM64M + generic + ( + INIT_A : bit_vector(63 downto 0) := X"0000000000000000"; + INIT_B : bit_vector(63 downto 0) := X"0000000000000000"; + INIT_C : bit_vector(63 downto 0) := X"0000000000000000"; + INIT_D : bit_vector(63 downto 0) := X"0000000000000000" + ); + port + ( + DOA : out std_ulogic; + DOB : out std_ulogic; + DOC : out std_ulogic; + DOD : out std_ulogic; + ADDRA : in std_logic_vector(5 downto 0); + ADDRB : in std_logic_vector(5 downto 0); + ADDRC : in std_logic_vector(5 downto 0); + ADDRD : in std_logic_vector(5 downto 0); + DIA : in std_ulogic; + DIB : in std_ulogic; + DIC : in std_ulogic; + DID : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM64M : component is "PRIMITIVE"; + +----- component RAM64X1D_1 ----- +component RAM64X1D_1 + generic + ( + INIT : bit_vector(63 downto 0) := X"0000000000000000" + ); + port + ( + DPO : out std_ulogic; + SPO : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic; + D : in std_ulogic; + DPRA0 : in std_ulogic; + DPRA1 : in std_ulogic; + DPRA2 : in std_ulogic; + DPRA3 : in std_ulogic; + DPRA4 : in std_ulogic; + DPRA5 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM64X1D_1 : component is "PRIMITIVE"; + +----- component RAM64X1D ----- +component RAM64X1D + generic + ( + INIT : bit_vector(63 downto 0) := X"0000000000000000" + ); + port + ( + DPO : out std_ulogic; + SPO : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic; + D : in std_ulogic; + DPRA0 : in std_ulogic; + DPRA1 : in std_ulogic; + DPRA2 : in std_ulogic; + DPRA3 : in std_ulogic; + DPRA4 : in std_ulogic; + DPRA5 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM64X1D : component is "PRIMITIVE"; + +----- component RAM64X1S_1 ----- +component RAM64X1S_1 + generic + ( + INIT : bit_vector(63 downto 0) := X"0000000000000000" + ); + port + ( + O : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic; + D : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM64X1S_1 : component is "PRIMITIVE"; + +----- component RAM64X1S ----- +component RAM64X1S + generic + ( + INIT : bit_vector(63 downto 0) := X"0000000000000000" + ); + port + ( + O : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic; + D : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM64X1S : component is "PRIMITIVE"; + +----- component RAM64X2S ----- +component RAM64X2S + generic + ( + INIT_00 : bit_vector(63 downto 0) := X"0000000000000000"; + INIT_01 : bit_vector(63 downto 0) := X"0000000000000000" + ); + port + ( + O0 : out std_ulogic; + O1 : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAM64X2S : component is "PRIMITIVE"; + +----- component RAMB16BWER ----- +component RAMB16BWER + generic + ( + DATA_WIDTH_A : integer := 0; + DATA_WIDTH_B : integer := 0; + DOA_REG : integer := 0; + DOB_REG : integer := 0; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + RSTTYPE : string := "SYNC"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector (31 downto 0); + DOB : out std_logic_vector (31 downto 0); + DOPA : out std_logic_vector (3 downto 0); + DOPB : out std_logic_vector (3 downto 0); + ADDRA : in std_logic_vector (13 downto 0); + ADDRB : in std_logic_vector (13 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector (31 downto 0); + DIB : in std_logic_vector (31 downto 0); + DIPA : in std_logic_vector (3 downto 0); + DIPB : in std_logic_vector (3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + WEA : in std_logic_vector (3 downto 0); + WEB : in std_logic_vector (3 downto 0) + ); +end component; +attribute BOX_TYPE of + RAMB16BWER : component is "PRIMITIVE"; + +----- component RAMB16BWE_S18_S18 ----- +component RAMB16BWE_S18_S18 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"00000"; + INIT_B : bit_vector := X"00000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"00000"; + SRVAL_B : bit_vector := X"00000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPA : out std_logic_vector(1 downto 0); + DOPB : out std_logic_vector(1 downto 0); + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPA : in std_logic_vector(1 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(1 downto 0); + WEB : in std_logic_vector(1 downto 0) + ); +end component; +attribute BOX_TYPE of + RAMB16BWE_S18_S18 : component is "PRIMITIVE"; + +----- component RAMB16BWE_S18_S9 ----- +component RAMB16BWE_S18_S9 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"00000"; + INIT_B : bit_vector := X"000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"00000"; + SRVAL_B : bit_vector := X"000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPA : out std_logic_vector(1 downto 0); + DOPB : out std_logic_vector(0 downto 0); + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPA : in std_logic_vector(1 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(1 downto 0); + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16BWE_S18_S9 : component is "PRIMITIVE"; + +----- component RAMB16BWE_S18 ----- +component RAMB16BWE_S18 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT : bit_vector := X"00000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SRVAL : bit_vector := X"00000"; + WRITE_MODE : string := "WRITE_FIRST" + ); + port + ( + DO : out std_logic_vector(15 downto 0); + DOP : out std_logic_vector(1 downto 0); + ADDR : in std_logic_vector(9 downto 0); + CLK : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DIP : in std_logic_vector(1 downto 0); + EN : in std_ulogic; + SSR : in std_ulogic; + WE : in std_logic_vector(1 downto 0) + ); +end component; +attribute BOX_TYPE of + RAMB16BWE_S18 : component is "PRIMITIVE"; + +----- component RAMB16BWE_S36_S18 ----- +component RAMB16BWE_S36_S18 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"00000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"00000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(1 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(3 downto 0); + WEB : in std_logic_vector(1 downto 0) + ); +end component; +attribute BOX_TYPE of + RAMB16BWE_S36_S18 : component is "PRIMITIVE"; + +----- component RAMB16BWE_S36_S36 ----- +component RAMB16BWE_S36_S36 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(3 downto 0); + WEB : in std_logic_vector(3 downto 0) + ); +end component; +attribute BOX_TYPE of + RAMB16BWE_S36_S36 : component is "PRIMITIVE"; + +----- component RAMB16BWE_S36_S9 ----- +component RAMB16BWE_S36_S9 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(0 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(3 downto 0); + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16BWE_S36_S9 : component is "PRIMITIVE"; + +----- component RAMB16BWE_S36 ----- +component RAMB16BWE_S36 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT : bit_vector := X"000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SRVAL : bit_vector := X"000000000"; + WRITE_MODE : string := "WRITE_FIRST" + ); + port + ( + DO : out std_logic_vector(31 downto 0); + DOP : out std_logic_vector(3 downto 0); + ADDR : in std_logic_vector(8 downto 0); + CLK : in std_ulogic; + DI : in std_logic_vector(31 downto 0); + DIP : in std_logic_vector(3 downto 0); + EN : in std_ulogic; + SSR : in std_ulogic; + WE : in std_logic_vector(3 downto 0) + ); +end component; +attribute BOX_TYPE of + RAMB16BWE_S36 : component is "PRIMITIVE"; + +----- component RAMB16BWE ----- +component RAMB16BWE + generic + ( + DATA_WIDTH_A : integer := 0; + DATA_WIDTH_B : integer := 0; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector (31 downto 0); + DOB : out std_logic_vector (31 downto 0); + DOPA : out std_logic_vector (3 downto 0); + DOPB : out std_logic_vector (3 downto 0); + ADDRA : in std_logic_vector (13 downto 0); + ADDRB : in std_logic_vector (13 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector (31 downto 0); + DIB : in std_logic_vector (31 downto 0); + DIPA : in std_logic_vector (3 downto 0); + DIPB : in std_logic_vector (3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector (3 downto 0); + WEB : in std_logic_vector (3 downto 0) + ); +end component; +attribute BOX_TYPE of + RAMB16BWE : component is "PRIMITIVE"; + +----- component RAMB16_S18_S18 ----- +component RAMB16_S18_S18 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"00000"; + INIT_B : bit_vector := X"00000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"00000"; + SRVAL_B : bit_vector := X"00000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPA : out std_logic_vector(1 downto 0); + DOPB : out std_logic_vector(1 downto 0); + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPA : in std_logic_vector(1 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S18_S18 : component is "PRIMITIVE"; + +----- component RAMB16_S18_S36 ----- +component RAMB16_S18_S36 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"00000"; + INIT_B : bit_vector := X"000000000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"00000"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(1 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(1 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S18_S36 : component is "PRIMITIVE"; + +----- component RAMB16_S18 ----- +component RAMB16_S18 + generic + ( + INIT : bit_vector := X"00000"; + SRVAL : bit_vector := X"00000"; + WRITE_MODE : string := "WRITE_FIRST"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + DO : out std_logic_vector (15 downto 0); + DOP : out std_logic_vector (1 downto 0); + ADDR : in std_logic_vector (9 downto 0); + CLK : in std_ulogic; + DI : in std_logic_vector (15 downto 0); + DIP : in std_logic_vector (1 downto 0); + EN : in std_ulogic; + SSR : in std_ulogic; + WE : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S18 : component is "PRIMITIVE"; + +----- component RAMB16_S1_S18 ----- +component RAMB16_S1_S18 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"00000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"00000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPB : out std_logic_vector(1 downto 0); + ADDRA : in std_logic_vector(13 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S1_S18 : component is "PRIMITIVE"; + +----- component RAMB16_S1_S1 ----- +component RAMB16_S1_S1 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"0"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"0"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(0 downto 0); + ADDRA : in std_logic_vector(13 downto 0); + ADDRB : in std_logic_vector(13 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S1_S1 : component is "PRIMITIVE"; + +----- component RAMB16_S1_S2 ----- +component RAMB16_S1_S2 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"0"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"0"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(1 downto 0); + ADDRA : in std_logic_vector(13 downto 0); + ADDRB : in std_logic_vector(12 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S1_S2 : component is "PRIMITIVE"; + +----- component RAMB16_S1_S36 ----- +component RAMB16_S1_S36 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"000000000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(13 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S1_S36 : component is "PRIMITIVE"; + +----- component RAMB16_S1_S4 ----- +component RAMB16_S1_S4 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"0"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"0"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(13 downto 0); + ADDRB : in std_logic_vector(11 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S1_S4 : component is "PRIMITIVE"; + +----- component RAMB16_S1_S9 ----- +component RAMB16_S1_S9 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPB : out std_logic_vector(0 downto 0); + ADDRA : in std_logic_vector(13 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S1_S9 : component is "PRIMITIVE"; + +----- component RAMB16_S1 ----- +component RAMB16_S1 + generic + ( + INIT : bit_vector := X"0"; + SRVAL : bit_vector := X"0"; + WRITE_MODE : string := "WRITE_FIRST"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + DO : out STD_LOGIC_VECTOR (0 downto 0); + ADDR : in STD_LOGIC_VECTOR (13 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (0 downto 0); + EN : in STD_ULOGIC; + SSR : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + RAMB16_S1 : component is "PRIMITIVE"; + +----- component RAMB16_S2_S18 ----- +component RAMB16_S2_S18 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"00000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"00000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(1 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPB : out std_logic_vector(1 downto 0); + ADDRA : in std_logic_vector(12 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(1 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S2_S18 : component is "PRIMITIVE"; + +----- component RAMB16_S2_S2 ----- +component RAMB16_S2_S2 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"0"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"0"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(1 downto 0); + DOB : out std_logic_vector(1 downto 0); + ADDRA : in std_logic_vector(12 downto 0); + ADDRB : in std_logic_vector(12 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(1 downto 0); + DIB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S2_S2 : component is "PRIMITIVE"; + +----- component RAMB16_S2_S36 ----- +component RAMB16_S2_S36 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"000000000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(1 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(12 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(1 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S2_S36 : component is "PRIMITIVE"; + +----- component RAMB16_S2_S4 ----- +component RAMB16_S2_S4 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"0"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"0"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(1 downto 0); + DOB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(12 downto 0); + ADDRB : in std_logic_vector(11 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(1 downto 0); + DIB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S2_S4 : component is "PRIMITIVE"; + +----- component RAMB16_S2_S9 ----- +component RAMB16_S2_S9 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(1 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPB : out std_logic_vector(0 downto 0); + ADDRA : in std_logic_vector(12 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(1 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S2_S9 : component is "PRIMITIVE"; + +----- component RAMB16_S2 ----- +component RAMB16_S2 + generic + ( + INIT : bit_vector := X"0"; + SRVAL : bit_vector := X"0"; + WRITE_MODE : string := "WRITE_FIRST"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + DO : out STD_LOGIC_VECTOR (1 downto 0); + ADDR : in STD_LOGIC_VECTOR (12 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (1 downto 0); + EN : in STD_ULOGIC; + SSR : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + RAMB16_S2 : component is "PRIMITIVE"; + +----- component RAMB16_S36_S36 ----- +component RAMB16_S36_S36 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S36_S36 : component is "PRIMITIVE"; + +----- component RAMB16_S36 ----- +component RAMB16_S36 + generic + ( + INIT : bit_vector := X"000000000"; + SRVAL : bit_vector := X"000000000"; + WRITE_MODE : string := "WRITE_FIRST"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + DO : out STD_LOGIC_VECTOR (31 downto 0); + DOP : out STD_LOGIC_VECTOR (3 downto 0); + ADDR : in STD_LOGIC_VECTOR (8 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (31 downto 0); + DIP : in STD_LOGIC_VECTOR (3 downto 0); + EN : in STD_ULOGIC; + SSR : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + RAMB16_S36 : component is "PRIMITIVE"; + +----- component RAMB16_S4_S18 ----- +component RAMB16_S4_S18 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"00000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"00000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(3 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPB : out std_logic_vector(1 downto 0); + ADDRA : in std_logic_vector(11 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(3 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S4_S18 : component is "PRIMITIVE"; + +----- component RAMB16_S4_S36 ----- +component RAMB16_S4_S36 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"000000000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(3 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(11 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(3 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S4_S36 : component is "PRIMITIVE"; + +----- component RAMB16_S4_S4 ----- +component RAMB16_S4_S4 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"0"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"0"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(3 downto 0); + DOB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(11 downto 0); + ADDRB : in std_logic_vector(11 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(3 downto 0); + DIB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S4_S4 : component is "PRIMITIVE"; + +----- component RAMB16_S4_S9 ----- +component RAMB16_S4_S9 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(3 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPB : out std_logic_vector(0 downto 0); + ADDRA : in std_logic_vector(11 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(3 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S4_S9 : component is "PRIMITIVE"; + +----- component RAMB16_S4 ----- +component RAMB16_S4 + generic + ( + INIT : bit_vector := X"0"; + SRVAL : bit_vector := X"0"; + WRITE_MODE : string := "WRITE_FIRST"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + DO : out STD_LOGIC_VECTOR (3 downto 0); + ADDR : in STD_LOGIC_VECTOR (11 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (3 downto 0); + EN : in STD_ULOGIC; + SSR : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + RAMB16_S4 : component is "PRIMITIVE"; + +----- component RAMB16_S9_S18 ----- +component RAMB16_S9_S18 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000"; + INIT_B : bit_vector := X"00000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"000"; + SRVAL_B : bit_vector := X"00000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(7 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPA : out std_logic_vector(0 downto 0); + DOPB : out std_logic_vector(1 downto 0); + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(7 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPA : in std_logic_vector(0 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S9_S18 : component is "PRIMITIVE"; + +----- component RAMB16_S9_S36 ----- +component RAMB16_S9_S36 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000"; + INIT_B : bit_vector := X"000000000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"000"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(7 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(0 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(7 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(0 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S9_S36 : component is "PRIMITIVE"; + +----- component RAMB16_S9_S9 ----- +component RAMB16_S9_S9 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000"; + INIT_B : bit_vector := X"000"; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"000"; + SRVAL_B : bit_vector := X"000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + port + ( + DOA : out std_logic_vector(7 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPA : out std_logic_vector(0 downto 0); + DOPB : out std_logic_vector(0 downto 0); + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(7 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPA : in std_logic_vector(0 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB16_S9_S9 : component is "PRIMITIVE"; + +----- component RAMB16_S9 ----- +component RAMB16_S9 + generic + ( + INIT : bit_vector := X"000"; + SRVAL : bit_vector := X"000"; + WRITE_MODE : string := "WRITE_FIRST"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + DO : out STD_LOGIC_VECTOR (7 downto 0); + DOP : out STD_LOGIC_VECTOR (0 downto 0); + ADDR : in STD_LOGIC_VECTOR (10 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (7 downto 0); + DIP : in STD_LOGIC_VECTOR (0 downto 0); + EN : in STD_ULOGIC; + SSR : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + RAMB16_S9 : component is "PRIMITIVE"; + +----- component RAMB16 ----- +component RAMB16 + generic + ( + DOA_REG : integer := 0; + DOB_REG : integer := 0; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + INIT_FILE : string := "NONE"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INVERT_CLK_DOA_REG : boolean := false; + INVERT_CLK_DOB_REG : boolean := false; + RAM_EXTENSION_A : string := "NONE"; + RAM_EXTENSION_B : string := "NONE"; + READ_WIDTH_A : integer := 0; + READ_WIDTH_B : integer := 0; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST"; + WRITE_WIDTH_A : integer := 0; + WRITE_WIDTH_B : integer := 0 + ); + port + ( + CASCADEOUTA : out std_ulogic; + CASCADEOUTB : out std_ulogic; + DOA : out std_logic_vector (31 downto 0); + DOB : out std_logic_vector (31 downto 0); + DOPA : out std_logic_vector (3 downto 0); + DOPB : out std_logic_vector (3 downto 0); + ADDRA : in std_logic_vector (14 downto 0); + ADDRB : in std_logic_vector (14 downto 0); + CASCADEINA : in std_ulogic; + CASCADEINB : in std_ulogic; + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector (31 downto 0); + DIB : in std_logic_vector (31 downto 0); + DIPA : in std_logic_vector (3 downto 0); + DIPB : in std_logic_vector (3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector (3 downto 0); + WEB : in std_logic_vector (3 downto 0) + ); +end component; +attribute BOX_TYPE of + RAMB16 : component is "PRIMITIVE"; + +----- component RAMB18SDP ----- +component RAMB18SDP + generic + ( + DO_REG : integer := 0; + INIT : bit_vector := X"000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_FILE : string := "NONE"; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL : bit_vector := X"000000000" + ); + port + ( + DO : out std_logic_vector(31 downto 0); + DOP : out std_logic_vector(3 downto 0); + DI : in std_logic_vector(31 downto 0); + DIP : in std_logic_vector(3 downto 0); + RDADDR : in std_logic_vector(8 downto 0); + RDCLK : in std_ulogic; + RDEN : in std_ulogic; + REGCE : in std_ulogic; + SSR : in std_ulogic; + WE : in std_logic_vector(3 downto 0); + WRADDR : in std_logic_vector(8 downto 0); + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB18SDP : component is "PRIMITIVE"; + +----- component RAMB18 ----- +component RAMB18 + generic + ( + DOA_REG : integer := 0; + DOB_REG : integer := 0; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"00000"; + INIT_B : bit_vector := X"00000"; + INIT_FILE : string := "NONE"; + READ_WIDTH_A : integer := 0; + READ_WIDTH_B : integer := 0; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL_A : bit_vector := X"00000"; + SRVAL_B : bit_vector := X"00000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST"; + WRITE_WIDTH_A : integer := 0; + WRITE_WIDTH_B : integer := 0 + ); + port + ( + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPA : out std_logic_vector(1 downto 0); + DOPB : out std_logic_vector(1 downto 0); + ADDRA : in std_logic_vector(13 downto 0); + ADDRB : in std_logic_vector(13 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPA : in std_logic_vector(1 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(1 downto 0); + WEB : in std_logic_vector(1 downto 0) + ); +end component; +attribute BOX_TYPE of + RAMB18 : component is "PRIMITIVE"; + +----- component RAMB32_S64_ECC ----- +component RAMB32_S64_ECC + generic + ( + DO_REG : integer := 0; + SIM_COLLISION_CHECK : string := "ALL" + ); + port + ( + DO : out std_logic_vector(63 downto 0); + STATUS : out std_logic_vector(1 downto 0); + DI : in std_logic_vector(63 downto 0); + RDADDR : in std_logic_vector(8 downto 0); + RDCLK : in std_ulogic; + RDEN : in std_ulogic; + SSR : in std_ulogic; + WRADDR : in std_logic_vector(8 downto 0); + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB32_S64_ECC : component is "PRIMITIVE"; + +----- component RAMB36_EXP ----- +component RAMB36_EXP + generic + ( + DOA_REG : integer := 0; + DOB_REG : integer := 0; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + INIT_FILE : string := "NONE"; + RAM_EXTENSION_A : string := "NONE"; + RAM_EXTENSION_B : string := "NONE"; + READ_WIDTH_A : integer := 0; + READ_WIDTH_B : integer := 0; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST"; + WRITE_WIDTH_A : integer := 0; + WRITE_WIDTH_B : integer := 0 + ); + port + ( + CASCADEOUTLATA : out std_ulogic; + CASCADEOUTLATB : out std_ulogic; + CASCADEOUTREGA : out std_ulogic; + CASCADEOUTREGB : out std_ulogic; + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRAL : in std_logic_vector(15 downto 0); + ADDRAU : in std_logic_vector(14 downto 0); + ADDRBL : in std_logic_vector(15 downto 0); + ADDRBU : in std_logic_vector(14 downto 0); + CASCADEINLATA : in std_ulogic; + CASCADEINLATB : in std_ulogic; + CASCADEINREGA : in std_ulogic; + CASCADEINREGB : in std_ulogic; + CLKAL : in std_ulogic; + CLKAU : in std_ulogic; + CLKBL : in std_ulogic; + CLKBU : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENAL : in std_ulogic; + ENAU : in std_ulogic; + ENBL : in std_ulogic; + ENBU : in std_ulogic; + REGCEAL : in std_ulogic; + REGCEAU : in std_ulogic; + REGCEBL : in std_ulogic; + REGCEBU : in std_ulogic; + REGCLKAL : in std_ulogic; + REGCLKAU : in std_ulogic; + REGCLKBL : in std_ulogic; + REGCLKBU : in std_ulogic; + SSRAL : in std_ulogic; + SSRAU : in std_ulogic; + SSRBL : in std_ulogic; + SSRBU : in std_ulogic; + WEAL : in std_logic_vector(3 downto 0); + WEAU : in std_logic_vector(3 downto 0); + WEBL : in std_logic_vector(7 downto 0); + WEBU : in std_logic_vector(7 downto 0) + ); +end component; +attribute BOX_TYPE of + RAMB36_EXP : component is "PRIMITIVE"; + +----- component RAMB36SDP_EXP ----- +component RAMB36SDP_EXP + generic + ( + DO_REG : integer := 0; + EN_ECC_READ : boolean := FALSE; + EN_ECC_SCRUB : boolean := FALSE; + EN_ECC_WRITE : boolean := FALSE; + INIT : bit_vector := X"000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_FILE : string := "NONE"; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL : bit_vector := X"000000000000000000" + ); + port + ( + DBITERR : out std_ulogic; + DO : out std_logic_vector(63 downto 0); + DOP : out std_logic_vector(7 downto 0); + ECCPARITY : out std_logic_vector(7 downto 0); + SBITERR : out std_ulogic; + DI : in std_logic_vector(63 downto 0); + DIP : in std_logic_vector(7 downto 0); + RDADDRL : in std_logic_vector(15 downto 0); + RDADDRU : in std_logic_vector(14 downto 0); + RDCLKL : in std_ulogic; + RDCLKU : in std_ulogic; + RDENU : in std_ulogic; + RDENL : in std_ulogic; + RDRCLKL : in std_ulogic; + RDRCLKU : in std_ulogic; + REGCEL : in std_ulogic; + REGCEU : in std_ulogic; + SSRL : in std_ulogic; + SSRU : in std_ulogic; + WEL : in std_logic_vector(7 downto 0); + WEU : in std_logic_vector(7 downto 0); + WRADDRL : in std_logic_vector(15 downto 0); + WRADDRU : in std_logic_vector(14 downto 0); + WRCLKL : in std_ulogic; + WRCLKU : in std_ulogic; + WRENL : in std_ulogic; + WRENU : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB36SDP_EXP : component is "PRIMITIVE"; + +----- component RAMB36SDP ----- +component RAMB36SDP + generic + ( + DO_REG : integer := 0; + EN_ECC_READ : boolean := FALSE; + EN_ECC_SCRUB : boolean := FALSE; + EN_ECC_WRITE : boolean := FALSE; + INIT : bit_vector := X"000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_FILE : string := "NONE"; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL : bit_vector := X"000000000000000000" + ); + port + ( + DBITERR : out std_ulogic; + DO : out std_logic_vector(63 downto 0); + DOP : out std_logic_vector(7 downto 0); + ECCPARITY : out std_logic_vector(7 downto 0); + SBITERR : out std_ulogic; + DI : in std_logic_vector(63 downto 0); + DIP : in std_logic_vector(7 downto 0); + RDADDR : in std_logic_vector(8 downto 0); + RDCLK : in std_ulogic; + RDEN : in std_ulogic; + REGCE : in std_ulogic; + SSR : in std_ulogic; + WE : in std_logic_vector(7 downto 0); + WRADDR : in std_logic_vector(8 downto 0); + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB36SDP : component is "PRIMITIVE"; + +----- component RAMB36 ----- +component RAMB36 + generic + ( + DOA_REG : integer := 0; + DOB_REG : integer := 0; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + INIT_FILE : string := "NONE"; + RAM_EXTENSION_A : string := "NONE"; + RAM_EXTENSION_B : string := "NONE"; + READ_WIDTH_A : integer := 0; + READ_WIDTH_B : integer := 0; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST"; + WRITE_WIDTH_A : integer := 0; + WRITE_WIDTH_B : integer := 0 + ); + port + ( + CASCADEOUTLATA : out std_ulogic; + CASCADEOUTLATB : out std_ulogic; + CASCADEOUTREGA : out std_ulogic; + CASCADEOUTREGB : out std_ulogic; + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(15 downto 0); + ADDRB : in std_logic_vector(15 downto 0); + CASCADEINLATA : in std_ulogic; + CASCADEINLATB : in std_ulogic; + CASCADEINREGA : in std_ulogic; + CASCADEINREGB : in std_ulogic; + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(3 downto 0); + WEB : in std_logic_vector(3 downto 0) + ); +end component; +attribute BOX_TYPE of + RAMB36 : component is "PRIMITIVE"; + +----- component RAMB4_S16_S16 ----- +component RAMB4_S16_S16 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL" + ); + port + ( + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(15 downto 0); + ADDRA : in std_logic_vector(7 downto 0); + ADDRB : in std_logic_vector(7 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(15 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB4_S16_S16 : component is "PRIMITIVE"; + +----- component RAMB4_S16 ----- +component RAMB4_S16 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + DO : out STD_LOGIC_VECTOR (15 downto 0); + ADDR : in STD_LOGIC_VECTOR (7 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (15 downto 0); + EN : in STD_ULOGIC; + RST : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + RAMB4_S16 : component is "PRIMITIVE"; + +----- component RAMB4_S1_S16 ----- +component RAMB4_S1_S16 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL" + ); + port + ( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(15 downto 0); + ADDRA : in std_logic_vector(11 downto 0); + ADDRB : in std_logic_vector(7 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(15 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB4_S1_S16 : component is "PRIMITIVE"; + +----- component RAMB4_S1_S1 ----- +component RAMB4_S1_S1 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL" + ); + port + ( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(0 downto 0); + ADDRA : in std_logic_vector(11 downto 0); + ADDRB : in std_logic_vector(11 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB4_S1_S1 : component is "PRIMITIVE"; + +----- component RAMB4_S1_S2 ----- +component RAMB4_S1_S2 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL" + ); + port + ( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(1 downto 0); + ADDRA : in std_logic_vector(11 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB4_S1_S2 : component is "PRIMITIVE"; + +----- component RAMB4_S1_S4 ----- +component RAMB4_S1_S4 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL" + ); + port + ( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(11 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB4_S1_S4 : component is "PRIMITIVE"; + +----- component RAMB4_S1_S8 ----- +component RAMB4_S1_S8 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL" + ); + port + ( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(7 downto 0); + ADDRA : in std_logic_vector(11 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(7 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB4_S1_S8 : component is "PRIMITIVE"; + +----- component RAMB4_S1 ----- +component RAMB4_S1 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + DO : out STD_LOGIC_VECTOR (0 downto 0); + ADDR : in STD_LOGIC_VECTOR (11 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (0 downto 0); + EN : in STD_ULOGIC; + RST : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + RAMB4_S1 : component is "PRIMITIVE"; + +----- component RAMB4_S2_S16 ----- +component RAMB4_S2_S16 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL" + ); + port + ( + DOA : out std_logic_vector(1 downto 0); + DOB : out std_logic_vector(15 downto 0); + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(7 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(1 downto 0); + DIB : in std_logic_vector(15 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB4_S2_S16 : component is "PRIMITIVE"; + +----- component RAMB4_S2_S2 ----- +component RAMB4_S2_S2 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL" + ); + port + ( + DOA : out std_logic_vector(1 downto 0); + DOB : out std_logic_vector(1 downto 0); + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(1 downto 0); + DIB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB4_S2_S2 : component is "PRIMITIVE"; + +----- component RAMB4_S2_S4 ----- +component RAMB4_S2_S4 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL" + ); + port + ( + DOA : out std_logic_vector(1 downto 0); + DOB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(1 downto 0); + DIB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB4_S2_S4 : component is "PRIMITIVE"; + +----- component RAMB4_S2_S8 ----- +component RAMB4_S2_S8 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL" + ); + port + ( + DOA : out std_logic_vector(1 downto 0); + DOB : out std_logic_vector(7 downto 0); + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(1 downto 0); + DIB : in std_logic_vector(7 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB4_S2_S8 : component is "PRIMITIVE"; + +----- component RAMB4_S2 ----- +component RAMB4_S2 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + DO : out STD_LOGIC_VECTOR (1 downto 0); + ADDR : in STD_LOGIC_VECTOR (10 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (1 downto 0); + EN : in STD_ULOGIC; + RST : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + RAMB4_S2 : component is "PRIMITIVE"; + +----- component RAMB4_S4_S16 ----- +component RAMB4_S4_S16 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL" + ); + port + ( + DOA : out std_logic_vector(3 downto 0); + DOB : out std_logic_vector(15 downto 0); + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(7 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(3 downto 0); + DIB : in std_logic_vector(15 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB4_S4_S16 : component is "PRIMITIVE"; + +----- component RAMB4_S4_S4 ----- +component RAMB4_S4_S4 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL" + ); + port + ( + DOA : out std_logic_vector(3 downto 0); + DOB : out std_logic_vector(3 downto 0); + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(3 downto 0); + DIB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB4_S4_S4 : component is "PRIMITIVE"; + +----- component RAMB4_S4_S8 ----- +component RAMB4_S4_S8 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL" + ); + port + ( + DOA : out std_logic_vector(3 downto 0); + DOB : out std_logic_vector(7 downto 0); + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(3 downto 0); + DIB : in std_logic_vector(7 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB4_S4_S8 : component is "PRIMITIVE"; + +----- component RAMB4_S4 ----- +component RAMB4_S4 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + DO : out STD_LOGIC_VECTOR (3 downto 0); + ADDR : in STD_LOGIC_VECTOR (9 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (3 downto 0); + EN : in STD_ULOGIC; + RST : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + RAMB4_S4 : component is "PRIMITIVE"; + +----- component RAMB4_S8_S16 ----- +component RAMB4_S8_S16 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL" + ); + port + ( + DOA : out std_logic_vector(7 downto 0); + DOB : out std_logic_vector(15 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(7 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(7 downto 0); + DIB : in std_logic_vector(15 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB4_S8_S16 : component is "PRIMITIVE"; + +----- component RAMB4_S8_S8 ----- +component RAMB4_S8_S8 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + SIM_COLLISION_CHECK : string := "ALL" + ); + port + ( + DOA : out std_logic_vector(7 downto 0); + DOB : out std_logic_vector(7 downto 0); + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(7 downto 0); + DIB : in std_logic_vector(7 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); +end component; +attribute BOX_TYPE of + RAMB4_S8_S8 : component is "PRIMITIVE"; + +----- component RAMB4_S8 ----- +component RAMB4_S8 + generic + ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + DO : out STD_LOGIC_VECTOR (7 downto 0); + ADDR : in STD_LOGIC_VECTOR (8 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (7 downto 0); + EN : in STD_ULOGIC; + RST : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + RAMB4_S8 : component is "PRIMITIVE"; + +----- component ROCBUF ----- +component ROCBUF + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + ROCBUF : component is "PRIMITIVE"; + +----- component ROC ----- +component ROC + generic + ( + WIDTH : time := 100 ns + ); + port + ( + O : out std_ulogic := '1' + ); +end component; +attribute BOX_TYPE of + ROC : component is "PRIMITIVE"; + +----- component ROM128X1 ----- +component ROM128X1 + generic + ( + INIT : bit_vector := X"00000000000000000000000000000000" + ); + port + ( + O : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic; + A6 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + ROM128X1 : component is "PRIMITIVE"; + +----- component ROM16X1 ----- +component ROM16X1 + generic + ( + INIT : bit_vector := X"0000" + ); + port + ( + O : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + ROM16X1 : component is "PRIMITIVE"; + +----- component ROM256X1 ----- +component ROM256X1 + generic + ( + INIT : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + O : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic; + A6 : in std_ulogic; + A7 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + ROM256X1 : component is "PRIMITIVE"; + +----- component ROM32X1 ----- +component ROM32X1 + generic + ( + INIT : bit_vector := X"00000000" + ); + port + ( + O : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + ROM32X1 : component is "PRIMITIVE"; + +----- component ROM64X1 ----- +component ROM64X1 + generic + ( + INIT : bit_vector := X"0000000000000000" + ); + port + ( + O : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + ROM64X1 : component is "PRIMITIVE"; + +----- component SIM_CONFIG_S3A ----- +component SIM_CONFIG_S3A + generic + ( + DEVICE_ID : bit_vector := X"00000000" + ); + port + ( + CSOB : out std_ulogic := '1'; + DONE : inout std_ulogic; + CCLK : in std_ulogic := '0'; + D : inout std_logic_vector(7 downto 0); + DCMLOCK : in std_ulogic := '0'; + CSIB : in std_ulogic := '0'; + INITB : inout std_ulogic := 'H'; + M : in std_logic_vector(2 downto 0) := "000"; + PROGB : in std_ulogic := '0'; + RDWRB : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + SIM_CONFIG_S3A : component is "PRIMITIVE"; + +----- component SIM_CONFIG_V5 ----- +component SIM_CONFIG_V5 + generic + ( + DEVICE_ID : bit_vector := X"00000000" + ); + port + ( + BUSY : out std_ulogic := '0'; + CSOB : out std_ulogic := '1'; + DONE : inout std_ulogic := '0'; + CCLK : in std_ulogic := '0'; + CSB : in std_ulogic := '0'; + D : inout std_logic_vector(31 downto 0); + DCMLOCK : in std_ulogic := '0'; + INITB : inout std_ulogic := 'H'; + M : in std_logic_vector(2 downto 0) := "000"; + PROGB : in std_ulogic := '0'; + RDWRB : in std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + SIM_CONFIG_V5 : component is "PRIMITIVE"; + +----- component SPI_ACCESS ----- +component SPI_ACCESS + generic + ( + SIM_DELAY_TYPE : string := "SCALED"; + SIM_DEVICE : string := "3S1400AN"; + SIM_FACTORY_ID : bit_vector := X"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + SIM_USER_ID : bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; + SIM_MEM_FILE : string := "NONE" + ); + port + ( + MISO : out std_ulogic; + CLK : in std_ulogic; + CSB : in std_ulogic; + MOSI : in std_ulogic + ); +end component; +attribute BOX_TYPE of + SPI_ACCESS : component is "PRIMITIVE"; + +----- component SRL16_1 ----- +component SRL16_1 + generic + ( + INIT : bit_vector := X"0000" + ); + port + ( + Q : out STD_ULOGIC; + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + CLK : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + SRL16_1 : component is "PRIMITIVE"; + +----- component SRL16E_1 ----- +component SRL16E_1 + generic + ( + INIT : bit_vector := X"0000" + ); + port + ( + Q : out STD_ULOGIC; + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + SRL16E_1 : component is "PRIMITIVE"; + +----- component SRL16E ----- +component SRL16E + generic + ( + INIT : bit_vector := X"0000" + ); + port + ( + Q : out STD_ULOGIC; + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + SRL16E : component is "PRIMITIVE"; + +----- component SRL16 ----- +component SRL16 + generic + ( + INIT : bit_vector := X"0000" + ); + port + ( + Q : out STD_ULOGIC; + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + CLK : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + SRL16 : component is "PRIMITIVE"; + +----- component SRLC16_1 ----- +component SRLC16_1 + generic + ( + INIT : bit_vector := X"0000" + ); + port + ( + Q : out STD_ULOGIC; + Q15 : out STD_ULOGIC; + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + CLK : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + SRLC16_1 : component is "PRIMITIVE"; + +----- component SRLC16E_1 ----- +component SRLC16E_1 + generic + ( + INIT : bit_vector := X"0000" + ); + port + ( + Q : out STD_ULOGIC; + Q15 : out STD_ULOGIC; + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + SRLC16E_1 : component is "PRIMITIVE"; + +----- component SRLC16E ----- +component SRLC16E + generic + ( + INIT : bit_vector := X"0000" + ); + port + ( + Q : out STD_ULOGIC; + Q15 : out STD_ULOGIC; + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + SRLC16E : component is "PRIMITIVE"; + +----- component SRLC16 ----- +component SRLC16 + generic + ( + INIT : bit_vector := X"0000" + ); + port + ( + Q : out STD_ULOGIC; + Q15 : out STD_ULOGIC; + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + CLK : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + SRLC16 : component is "PRIMITIVE"; + +----- component SRLC32E ----- +component SRLC32E + generic + ( + INIT : bit_vector := X"00000000" + ); + port + ( + Q : out STD_ULOGIC; + Q31 : out STD_ULOGIC; + A : in STD_LOGIC_VECTOR (4 downto 0); + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end component; +attribute BOX_TYPE of + SRLC32E : component is "PRIMITIVE"; + +----- component STARTBUF_FPGACORE ----- +component STARTBUF_FPGACORE + port + ( + GSROUT : out std_ulogic; + CLKIN : in std_ulogic := 'X'; + GSRIN : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + STARTBUF_FPGACORE : component is "PRIMITIVE"; + +----- component STARTBUF_SPARTAN2 ----- +component STARTBUF_SPARTAN2 + port + ( + GSROUT : out std_ulogic; + GTSOUT : out std_ulogic; + CLKIN : in std_ulogic := 'X'; + GSRIN : in std_ulogic := 'X'; + GTSIN : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + STARTBUF_SPARTAN2 : component is "PRIMITIVE"; + +----- component STARTBUF_SPARTAN3 ----- +component STARTBUF_SPARTAN3 + port + ( + GSROUT : out std_ulogic; + GTSOUT : out std_ulogic; + CLKIN : in std_ulogic := 'X'; + GSRIN : in std_ulogic := 'X'; + GTSIN : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + STARTBUF_SPARTAN3 : component is "PRIMITIVE"; + +----- component STARTBUF_VIRTEX2 ----- +component STARTBUF_VIRTEX2 + port + ( + GSROUT : out std_ulogic; + GTSOUT : out std_ulogic; + CLKIN : in std_ulogic := 'X'; + GSRIN : in std_ulogic := 'X'; + GTSIN : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + STARTBUF_VIRTEX2 : component is "PRIMITIVE"; + +----- component STARTBUF_VIRTEX4 ----- +component STARTBUF_VIRTEX4 + port + ( + EOSOUT : out std_ulogic; + GSROUT : out std_ulogic; + GTSOUT : out std_ulogic; + CLKIN : in std_ulogic := 'X'; + GSRIN : in std_ulogic := 'X'; + GTSIN : in std_ulogic := 'X'; + USRCCLKOIN : in std_ulogic := 'X'; + USRCCLKTSIN : in std_ulogic := 'X'; + USRDONEOIN : in std_ulogic := 'X'; + USRDONETSIN : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + STARTBUF_VIRTEX4 : component is "PRIMITIVE"; + +----- component STARTBUF_VIRTEX ----- +component STARTBUF_VIRTEX + port + ( + GSROUT : out std_ulogic; + GTSOUT : out std_ulogic; + CLKIN : in std_ulogic := 'X'; + GSRIN : in std_ulogic := 'X'; + GTSIN : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + STARTBUF_VIRTEX : component is "PRIMITIVE"; + +----- component STARTUP_FPGACORE ----- +component STARTUP_FPGACORE + port + ( + CLK : in std_ulogic := 'X'; + GSR : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + STARTUP_FPGACORE : component is "PRIMITIVE"; + +----- component STARTUP_SPARTAN2 ----- +component STARTUP_SPARTAN2 + port + ( + CLK : in std_ulogic := 'X'; + GSR : in std_ulogic := 'X'; + GTS : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + STARTUP_SPARTAN2 : component is "PRIMITIVE"; + +----- component STARTUP_SPARTAN3A ----- +component STARTUP_SPARTAN3A + port + ( + CLK : in std_ulogic := 'X'; + GSR : in std_ulogic := 'X'; + GTS : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + STARTUP_SPARTAN3A : component is "PRIMITIVE"; + +----- component STARTUP_SPARTAN3E ----- +component STARTUP_SPARTAN3E + port + ( + CLK : in std_ulogic := 'X'; + GSR : in std_ulogic := 'X'; + GTS : in std_ulogic := 'X'; + MBT : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + STARTUP_SPARTAN3E : component is "PRIMITIVE"; + +----- component STARTUP_SPARTAN3 ----- +component STARTUP_SPARTAN3 + port + ( + CLK : in std_ulogic := 'X'; + GSR : in std_ulogic := 'X'; + GTS : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + STARTUP_SPARTAN3 : component is "PRIMITIVE"; + +----- component STARTUP_VIRTEX2 ----- +component STARTUP_VIRTEX2 + port + ( + CLK : in std_ulogic := 'X'; + GSR : in std_ulogic := 'X'; + GTS : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + STARTUP_VIRTEX2 : component is "PRIMITIVE"; + +----- component STARTUP_VIRTEX4 ----- +component STARTUP_VIRTEX4 + port + ( + EOS : out std_ulogic; + CLK : in std_ulogic := 'X'; + GSR : in std_ulogic := 'X'; + GTS : in std_ulogic := 'X'; + USRCCLKO : in std_ulogic := 'X'; + USRCCLKTS : in std_ulogic := 'X'; + USRDONEO : in std_ulogic := 'X'; + USRDONETS : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + STARTUP_VIRTEX4 : component is "PRIMITIVE"; + +----- component STARTUP_VIRTEX5 ----- +component STARTUP_VIRTEX5 + port + ( + CFGCLK : out std_ulogic; + CFGMCLK : out std_ulogic; + DINSPI : out std_ulogic; + EOS : out std_ulogic; + TCKSPI : out std_ulogic; + CLK : in std_ulogic := 'X'; + GSR : in std_ulogic := 'X'; + GTS : in std_ulogic := 'X'; + USRCCLKO : in std_ulogic := 'X'; + USRCCLKTS : in std_ulogic := 'X'; + USRDONEO : in std_ulogic := 'X'; + USRDONETS : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + STARTUP_VIRTEX5 : component is "PRIMITIVE"; + +----- component STARTUP_VIRTEX ----- +component STARTUP_VIRTEX + port + ( + CLK : in std_ulogic := 'X'; + GSR : in std_ulogic := 'X'; + GTS : in std_ulogic := 'X' + ); +end component; +attribute BOX_TYPE of + STARTUP_VIRTEX : component is "PRIMITIVE"; + +----- component SYSMON ----- +component SYSMON + generic + ( + INIT_40 : bit_vector := X"0000"; + INIT_41 : bit_vector := X"0000"; + INIT_42 : bit_vector := X"0800"; + INIT_43 : bit_vector := X"0000"; + INIT_44 : bit_vector := X"0000"; + INIT_45 : bit_vector := X"0000"; + INIT_46 : bit_vector := X"0000"; + INIT_47 : bit_vector := X"0000"; + INIT_48 : bit_vector := X"0000"; + INIT_49 : bit_vector := X"0000"; + INIT_4A : bit_vector := X"0000"; + INIT_4B : bit_vector := X"0000"; + INIT_4C : bit_vector := X"0000"; + INIT_4D : bit_vector := X"0000"; + INIT_4E : bit_vector := X"0000"; + INIT_4F : bit_vector := X"0000"; + INIT_50 : bit_vector := X"0000"; + INIT_51 : bit_vector := X"0000"; + INIT_52 : bit_vector := X"0000"; + INIT_53 : bit_vector := X"0000"; + INIT_54 : bit_vector := X"0000"; + INIT_55 : bit_vector := X"0000"; + INIT_56 : bit_vector := X"0000"; + INIT_57 : bit_vector := X"0000"; + SIM_MONITOR_FILE : string := "design.txt" + ); + port + ( + ALM : out std_logic_vector(2 downto 0); + BUSY : out std_ulogic; + CHANNEL : out std_logic_vector(4 downto 0); + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + EOC : out std_ulogic; + EOS : out std_ulogic; + JTAGBUSY : out std_ulogic; + JTAGLOCKED : out std_ulogic; + JTAGMODIFIED : out std_ulogic; + OT : out std_ulogic; + CONVST : in std_ulogic; + CONVSTCLK : in std_ulogic; + DADDR : in std_logic_vector(6 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + RESET : in std_ulogic; + VAUXN : in std_logic_vector(15 downto 0); + VAUXP : in std_logic_vector(15 downto 0); + VN : in std_ulogic; + VP : in std_ulogic + ); +end component; +attribute BOX_TYPE of + SYSMON : component is "PRIMITIVE"; + +----- component TBLOCK ----- +component TBLOCK +end component; +attribute BOX_TYPE of + TBLOCK : component is "PRIMITIVE"; + +----- component TEMAC ----- +component TEMAC + generic + ( + EMAC0_1000BASEX_ENABLE : boolean := FALSE; + EMAC0_ADDRFILTER_ENABLE : boolean := FALSE; + EMAC0_BYTEPHY : boolean := FALSE; + EMAC0_CONFIGVEC_79 : boolean := FALSE; + EMAC0_DCRBASEADDR : bit_vector := X"00"; + EMAC0_GTLOOPBACK : boolean := FALSE; + EMAC0_HOST_ENABLE : boolean := FALSE; + EMAC0_LINKTIMERVAL : bit_vector := X"000"; + EMAC0_LTCHECK_DISABLE : boolean := FALSE; + EMAC0_MDIO_ENABLE : boolean := FALSE; + EMAC0_PAUSEADDR : bit_vector := X"000000000000"; + EMAC0_PHYINITAUTONEG_ENABLE : boolean := FALSE; + EMAC0_PHYISOLATE : boolean := FALSE; + EMAC0_PHYLOOPBACKMSB : boolean := FALSE; + EMAC0_PHYPOWERDOWN : boolean := FALSE; + EMAC0_PHYRESET : boolean := FALSE; + EMAC0_RGMII_ENABLE : boolean := FALSE; + EMAC0_RX16BITCLIENT_ENABLE : boolean := FALSE; + EMAC0_RXFLOWCTRL_ENABLE : boolean := FALSE; + EMAC0_RXHALFDUPLEX : boolean := FALSE; + EMAC0_RXINBANDFCS_ENABLE : boolean := FALSE; + EMAC0_RXJUMBOFRAME_ENABLE : boolean := FALSE; + EMAC0_RXRESET : boolean := FALSE; + EMAC0_RXVLAN_ENABLE : boolean := FALSE; + EMAC0_RX_ENABLE : boolean := FALSE; + EMAC0_SGMII_ENABLE : boolean := FALSE; + EMAC0_SPEED_LSB : boolean := FALSE; + EMAC0_SPEED_MSB : boolean := FALSE; + EMAC0_TX16BITCLIENT_ENABLE : boolean := FALSE; + EMAC0_TXFLOWCTRL_ENABLE : boolean := FALSE; + EMAC0_TXHALFDUPLEX : boolean := FALSE; + EMAC0_TXIFGADJUST_ENABLE : boolean := FALSE; + EMAC0_TXINBANDFCS_ENABLE : boolean := FALSE; + EMAC0_TXJUMBOFRAME_ENABLE : boolean := FALSE; + EMAC0_TXRESET : boolean := FALSE; + EMAC0_TXVLAN_ENABLE : boolean := FALSE; + EMAC0_TX_ENABLE : boolean := FALSE; + EMAC0_UNICASTADDR : bit_vector := X"000000000000"; + EMAC0_UNIDIRECTION_ENABLE : boolean := FALSE; + EMAC0_USECLKEN : boolean := FALSE; + EMAC1_1000BASEX_ENABLE : boolean := FALSE; + EMAC1_ADDRFILTER_ENABLE : boolean := FALSE; + EMAC1_BYTEPHY : boolean := FALSE; + EMAC1_CONFIGVEC_79 : boolean := FALSE; + EMAC1_DCRBASEADDR : bit_vector := X"00"; + EMAC1_GTLOOPBACK : boolean := FALSE; + EMAC1_HOST_ENABLE : boolean := FALSE; + EMAC1_LINKTIMERVAL : bit_vector := X"000"; + EMAC1_LTCHECK_DISABLE : boolean := FALSE; + EMAC1_MDIO_ENABLE : boolean := FALSE; + EMAC1_PAUSEADDR : bit_vector := X"000000000000"; + EMAC1_PHYINITAUTONEG_ENABLE : boolean := FALSE; + EMAC1_PHYISOLATE : boolean := FALSE; + EMAC1_PHYLOOPBACKMSB : boolean := FALSE; + EMAC1_PHYPOWERDOWN : boolean := FALSE; + EMAC1_PHYRESET : boolean := FALSE; + EMAC1_RGMII_ENABLE : boolean := FALSE; + EMAC1_RX16BITCLIENT_ENABLE : boolean := FALSE; + EMAC1_RXFLOWCTRL_ENABLE : boolean := FALSE; + EMAC1_RXHALFDUPLEX : boolean := FALSE; + EMAC1_RXINBANDFCS_ENABLE : boolean := FALSE; + EMAC1_RXJUMBOFRAME_ENABLE : boolean := FALSE; + EMAC1_RXRESET : boolean := FALSE; + EMAC1_RXVLAN_ENABLE : boolean := FALSE; + EMAC1_RX_ENABLE : boolean := FALSE; + EMAC1_SGMII_ENABLE : boolean := FALSE; + EMAC1_SPEED_LSB : boolean := FALSE; + EMAC1_SPEED_MSB : boolean := FALSE; + EMAC1_TX16BITCLIENT_ENABLE : boolean := FALSE; + EMAC1_TXFLOWCTRL_ENABLE : boolean := FALSE; + EMAC1_TXHALFDUPLEX : boolean := FALSE; + EMAC1_TXIFGADJUST_ENABLE : boolean := FALSE; + EMAC1_TXINBANDFCS_ENABLE : boolean := FALSE; + EMAC1_TXJUMBOFRAME_ENABLE : boolean := FALSE; + EMAC1_TXRESET : boolean := FALSE; + EMAC1_TXVLAN_ENABLE : boolean := FALSE; + EMAC1_TX_ENABLE : boolean := FALSE; + EMAC1_UNICASTADDR : bit_vector := X"000000000000"; + EMAC1_UNIDIRECTION_ENABLE : boolean := FALSE; + EMAC1_USECLKEN : boolean := FALSE + ); + port + ( + DCRHOSTDONEIR : out std_ulogic; + EMAC0CLIENTANINTERRUPT : out std_ulogic; + EMAC0CLIENTRXBADFRAME : out std_ulogic; + EMAC0CLIENTRXCLIENTCLKOUT : out std_ulogic; + EMAC0CLIENTRXD : out std_logic_vector(15 downto 0); + EMAC0CLIENTRXDVLD : out std_ulogic; + EMAC0CLIENTRXDVLDMSW : out std_ulogic; + EMAC0CLIENTRXFRAMEDROP : out std_ulogic; + EMAC0CLIENTRXGOODFRAME : out std_ulogic; + EMAC0CLIENTRXSTATS : out std_logic_vector(6 downto 0); + EMAC0CLIENTRXSTATSBYTEVLD : out std_ulogic; + EMAC0CLIENTRXSTATSVLD : out std_ulogic; + EMAC0CLIENTTXACK : out std_ulogic; + EMAC0CLIENTTXCLIENTCLKOUT : out std_ulogic; + EMAC0CLIENTTXCOLLISION : out std_ulogic; + EMAC0CLIENTTXRETRANSMIT : out std_ulogic; + EMAC0CLIENTTXSTATS : out std_ulogic; + EMAC0CLIENTTXSTATSBYTEVLD : out std_ulogic; + EMAC0CLIENTTXSTATSVLD : out std_ulogic; + EMAC0PHYENCOMMAALIGN : out std_ulogic; + EMAC0PHYLOOPBACKMSB : out std_ulogic; + EMAC0PHYMCLKOUT : out std_ulogic; + EMAC0PHYMDOUT : out std_ulogic; + EMAC0PHYMDTRI : out std_ulogic; + EMAC0PHYMGTRXRESET : out std_ulogic; + EMAC0PHYMGTTXRESET : out std_ulogic; + EMAC0PHYPOWERDOWN : out std_ulogic; + EMAC0PHYSYNCACQSTATUS : out std_ulogic; + EMAC0PHYTXCHARDISPMODE : out std_ulogic; + EMAC0PHYTXCHARDISPVAL : out std_ulogic; + EMAC0PHYTXCHARISK : out std_ulogic; + EMAC0PHYTXCLK : out std_ulogic; + EMAC0PHYTXD : out std_logic_vector(7 downto 0); + EMAC0PHYTXEN : out std_ulogic; + EMAC0PHYTXER : out std_ulogic; + EMAC0PHYTXGMIIMIICLKOUT : out std_ulogic; + EMAC0SPEEDIS10100 : out std_ulogic; + EMAC1CLIENTANINTERRUPT : out std_ulogic; + EMAC1CLIENTRXBADFRAME : out std_ulogic; + EMAC1CLIENTRXCLIENTCLKOUT : out std_ulogic; + EMAC1CLIENTRXD : out std_logic_vector(15 downto 0); + EMAC1CLIENTRXDVLD : out std_ulogic; + EMAC1CLIENTRXDVLDMSW : out std_ulogic; + EMAC1CLIENTRXFRAMEDROP : out std_ulogic; + EMAC1CLIENTRXGOODFRAME : out std_ulogic; + EMAC1CLIENTRXSTATS : out std_logic_vector(6 downto 0); + EMAC1CLIENTRXSTATSBYTEVLD : out std_ulogic; + EMAC1CLIENTRXSTATSVLD : out std_ulogic; + EMAC1CLIENTTXACK : out std_ulogic; + EMAC1CLIENTTXCLIENTCLKOUT : out std_ulogic; + EMAC1CLIENTTXCOLLISION : out std_ulogic; + EMAC1CLIENTTXRETRANSMIT : out std_ulogic; + EMAC1CLIENTTXSTATS : out std_ulogic; + EMAC1CLIENTTXSTATSBYTEVLD : out std_ulogic; + EMAC1CLIENTTXSTATSVLD : out std_ulogic; + EMAC1PHYENCOMMAALIGN : out std_ulogic; + EMAC1PHYLOOPBACKMSB : out std_ulogic; + EMAC1PHYMCLKOUT : out std_ulogic; + EMAC1PHYMDOUT : out std_ulogic; + EMAC1PHYMDTRI : out std_ulogic; + EMAC1PHYMGTRXRESET : out std_ulogic; + EMAC1PHYMGTTXRESET : out std_ulogic; + EMAC1PHYPOWERDOWN : out std_ulogic; + EMAC1PHYSYNCACQSTATUS : out std_ulogic; + EMAC1PHYTXCHARDISPMODE : out std_ulogic; + EMAC1PHYTXCHARDISPVAL : out std_ulogic; + EMAC1PHYTXCHARISK : out std_ulogic; + EMAC1PHYTXCLK : out std_ulogic; + EMAC1PHYTXD : out std_logic_vector(7 downto 0); + EMAC1PHYTXEN : out std_ulogic; + EMAC1PHYTXER : out std_ulogic; + EMAC1PHYTXGMIIMIICLKOUT : out std_ulogic; + EMAC1SPEEDIS10100 : out std_ulogic; + EMACDCRACK : out std_ulogic; + EMACDCRDBUS : out std_logic_vector(0 to 31); + HOSTMIIMRDY : out std_ulogic; + HOSTRDDATA : out std_logic_vector(31 downto 0); + CLIENTEMAC0DCMLOCKED : in std_ulogic; + CLIENTEMAC0PAUSEREQ : in std_ulogic; + CLIENTEMAC0PAUSEVAL : in std_logic_vector(15 downto 0); + CLIENTEMAC0RXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC0TXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC0TXD : in std_logic_vector(15 downto 0); + CLIENTEMAC0TXDVLD : in std_ulogic; + CLIENTEMAC0TXDVLDMSW : in std_ulogic; + CLIENTEMAC0TXFIRSTBYTE : in std_ulogic; + CLIENTEMAC0TXIFGDELAY : in std_logic_vector(7 downto 0); + CLIENTEMAC0TXUNDERRUN : in std_ulogic; + CLIENTEMAC1DCMLOCKED : in std_ulogic; + CLIENTEMAC1PAUSEREQ : in std_ulogic; + CLIENTEMAC1PAUSEVAL : in std_logic_vector(15 downto 0); + CLIENTEMAC1RXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC1TXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC1TXD : in std_logic_vector(15 downto 0); + CLIENTEMAC1TXDVLD : in std_ulogic; + CLIENTEMAC1TXDVLDMSW : in std_ulogic; + CLIENTEMAC1TXFIRSTBYTE : in std_ulogic; + CLIENTEMAC1TXIFGDELAY : in std_logic_vector(7 downto 0); + CLIENTEMAC1TXUNDERRUN : in std_ulogic; + DCREMACABUS : in std_logic_vector(0 to 9); + DCREMACCLK : in std_ulogic; + DCREMACDBUS : in std_logic_vector(0 to 31); + DCREMACENABLE : in std_ulogic; + DCREMACREAD : in std_ulogic; + DCREMACWRITE : in std_ulogic; + HOSTADDR : in std_logic_vector(9 downto 0); + HOSTCLK : in std_ulogic; + HOSTEMAC1SEL : in std_ulogic; + HOSTMIIMSEL : in std_ulogic; + HOSTOPCODE : in std_logic_vector(1 downto 0); + HOSTREQ : in std_ulogic; + HOSTWRDATA : in std_logic_vector(31 downto 0); + PHYEMAC0COL : in std_ulogic; + PHYEMAC0CRS : in std_ulogic; + PHYEMAC0GTXCLK : in std_ulogic; + PHYEMAC0MCLKIN : in std_ulogic; + PHYEMAC0MDIN : in std_ulogic; + PHYEMAC0MIITXCLK : in std_ulogic; + PHYEMAC0PHYAD : in std_logic_vector(4 downto 0); + PHYEMAC0RXBUFERR : in std_ulogic; + PHYEMAC0RXBUFSTATUS : in std_logic_vector(1 downto 0); + PHYEMAC0RXCHARISCOMMA : in std_ulogic; + PHYEMAC0RXCHARISK : in std_ulogic; + PHYEMAC0RXCHECKINGCRC : in std_ulogic; + PHYEMAC0RXCLK : in std_ulogic; + PHYEMAC0RXCLKCORCNT : in std_logic_vector(2 downto 0); + PHYEMAC0RXCOMMADET : in std_ulogic; + PHYEMAC0RXD : in std_logic_vector(7 downto 0); + PHYEMAC0RXDISPERR : in std_ulogic; + PHYEMAC0RXDV : in std_ulogic; + PHYEMAC0RXER : in std_ulogic; + PHYEMAC0RXLOSSOFSYNC : in std_logic_vector(1 downto 0); + PHYEMAC0RXNOTINTABLE : in std_ulogic; + PHYEMAC0RXRUNDISP : in std_ulogic; + PHYEMAC0SIGNALDET : in std_ulogic; + PHYEMAC0TXBUFERR : in std_ulogic; + PHYEMAC0TXGMIIMIICLKIN : in std_ulogic; + PHYEMAC1COL : in std_ulogic; + PHYEMAC1CRS : in std_ulogic; + PHYEMAC1GTXCLK : in std_ulogic; + PHYEMAC1MCLKIN : in std_ulogic; + PHYEMAC1MDIN : in std_ulogic; + PHYEMAC1MIITXCLK : in std_ulogic; + PHYEMAC1PHYAD : in std_logic_vector(4 downto 0); + PHYEMAC1RXBUFERR : in std_ulogic; + PHYEMAC1RXBUFSTATUS : in std_logic_vector(1 downto 0); + PHYEMAC1RXCHARISCOMMA : in std_ulogic; + PHYEMAC1RXCHARISK : in std_ulogic; + PHYEMAC1RXCHECKINGCRC : in std_ulogic; + PHYEMAC1RXCLK : in std_ulogic; + PHYEMAC1RXCLKCORCNT : in std_logic_vector(2 downto 0); + PHYEMAC1RXCOMMADET : in std_ulogic; + PHYEMAC1RXD : in std_logic_vector(7 downto 0); + PHYEMAC1RXDISPERR : in std_ulogic; + PHYEMAC1RXDV : in std_ulogic; + PHYEMAC1RXER : in std_ulogic; + PHYEMAC1RXLOSSOFSYNC : in std_logic_vector(1 downto 0); + PHYEMAC1RXNOTINTABLE : in std_ulogic; + PHYEMAC1RXRUNDISP : in std_ulogic; + PHYEMAC1SIGNALDET : in std_ulogic; + PHYEMAC1TXBUFERR : in std_ulogic; + PHYEMAC1TXGMIIMIICLKIN : in std_ulogic; + RESET : in std_ulogic + ); +end component; +attribute BOX_TYPE of + TEMAC : component is "PRIMITIVE"; + +----- component TIMEGRP ----- +component TIMEGRP +end component; +attribute BOX_TYPE of + TIMEGRP : component is "PRIMITIVE"; + +----- component TIMESPEC ----- +component TIMESPEC +end component; +attribute BOX_TYPE of + TIMESPEC : component is "PRIMITIVE"; + +----- component TOCBUF ----- +component TOCBUF + port + ( + O : out std_ulogic; + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + TOCBUF : component is "PRIMITIVE"; + +----- component TOC ----- +component TOC + generic + ( + WIDTH : time := 100 ns + ); + port + ( + O : out std_ulogic := '0' + ); +end component; +attribute BOX_TYPE of + TOC : component is "PRIMITIVE"; + +----- component USR_ACCESS_VIRTEX4 ----- +component USR_ACCESS_VIRTEX4 + port + ( + DATA : out std_logic_vector(31 downto 0); + DATAVALID : out std_ulogic + ); +end component; +attribute BOX_TYPE of + USR_ACCESS_VIRTEX4 : component is "PRIMITIVE"; + +----- component USR_ACCESS_VIRTEX5 ----- +component USR_ACCESS_VIRTEX5 + port + ( + CFGCLK : out std_ulogic; + DATA : out std_logic_vector(31 downto 0); + DATAVALID : out std_ulogic + ); +end component; +attribute BOX_TYPE of + USR_ACCESS_VIRTEX5 : component is "PRIMITIVE"; + +----- component VCC ----- +component VCC + port + ( + P : out std_ulogic := '1' + ); +end component; +attribute BOX_TYPE of + VCC : component is "PRIMITIVE"; + +----- component WIREAND ----- +component WIREAND + port + ( + I : in std_ulogic + ); +end component; +attribute BOX_TYPE of + WIREAND : component is "PRIMITIVE"; + +----- component XNOR2 ----- +component XNOR2 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + XNOR2 : component is "PRIMITIVE"; + +----- component XNOR3 ----- +component XNOR3 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + XNOR3 : component is "PRIMITIVE"; + +----- component XNOR4 ----- +component XNOR4 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + XNOR4 : component is "PRIMITIVE"; + +----- component XNOR5 ----- +component XNOR5 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + XNOR5 : component is "PRIMITIVE"; + +----- component XOR2 ----- +component XOR2 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + XOR2 : component is "PRIMITIVE"; + +----- component XOR3 ----- +component XOR3 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + XOR3 : component is "PRIMITIVE"; + +----- component XOR4 ----- +component XOR4 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + XOR4 : component is "PRIMITIVE"; + +----- component XOR5 ----- +component XOR5 + port + ( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end component; +attribute BOX_TYPE of + XOR5 : component is "PRIMITIVE"; + +----- component XORCY_D ----- +component XORCY_D + port + ( + LO : out std_ulogic; + O : out std_ulogic; + CI : in std_ulogic; + LI : in std_ulogic + ); +end component; +attribute BOX_TYPE of + XORCY_D : component is "PRIMITIVE"; + +----- component XORCY_L ----- +component XORCY_L + port + ( + LO : out std_ulogic; + CI : in std_ulogic; + LI : in std_ulogic + ); +end component; +attribute BOX_TYPE of + XORCY_L : component is "PRIMITIVE"; + +----- component XORCY ----- +component XORCY + port + ( + O : out std_ulogic; + CI : in std_ulogic; + LI : in std_ulogic + ); +end component; +attribute BOX_TYPE of + XORCY : component is "PRIMITIVE"; + +-- END COMPONENT + +end VCOMPONENTS; diff --git a/Common/sim/xilinx/libsrc/unisims/unisim_VITAL.vhd b/Common/sim/xilinx/libsrc/unisims/unisim_VITAL.vhd new file mode 100644 index 0000000..956305e --- /dev/null +++ b/Common/sim/xilinx/libsrc/unisims/unisim_VITAL.vhd @@ -0,0 +1,196520 @@ +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and2.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-input AND Gate +-- /___/ /\ Filename : AND2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:12 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND2 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end AND2; + +architecture AND2_V of AND2 is +begin + O <= I0 and I1; +end AND2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and2b1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-input AND Gate +-- /___/ /\ Filename : AND2B1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:12 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND2B1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND2B1 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end AND2B1; + +architecture AND2B1_V of AND2B1 is +begin + O <= (not I0) and I1; +end AND2B1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and2b2.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-input AND Gate +-- /___/ /\ Filename : AND2B2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:12 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND2B2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND2B2 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end AND2B2; + +architecture AND2B2_V of AND2B2 is +begin + O <= (not I0) and (not I1); +end AND2B2_V; + + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and3.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input AND Gate +-- /___/ /\ Filename : AND3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:12 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND3 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end AND3; + +architecture AND3_V of AND3 is +begin + O <= I0 and I1 and I2; +end AND3_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and3b1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input AND Gate +-- /___/ /\ Filename : AND3B1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:12 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND3B1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND3B1 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end AND3B1; + +architecture AND3B1_V of AND3B1 is +begin + O <= (not I0) and I1 and I2; +end AND3B1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and3b2.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input AND Gate +-- /___/ /\ Filename : AND3B2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:13 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND3B2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND3B2 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end AND3B2; + +architecture AND3B2_V of AND3B2 is +begin + O <= (not I0) and (not I1) and I2; +end AND3B2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and3b3.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input AND Gate +-- /___/ /\ Filename : AND3B3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:13 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND3B3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND3B3 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end AND3B3; + +architecture AND3B3_V of AND3B3 is +begin + O <= (not I0) and (not I1) and (not I2); +end AND3B3_V; + + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and4.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input AND Gate +-- /___/ /\ Filename : AND4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:13 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND4 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end AND4; + +architecture AND4_V of AND4 is +begin + O <= I0 and I1 and I2 and I3; +end AND4_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and4b1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input AND Gate +-- /___/ /\ Filename : AND4B1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:13 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND4B1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND4B1 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end AND4B1; + +architecture AND4B1_V of AND4B1 is +begin + O <= (not I0) and I1 and I2 and I3; +end AND4B1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and4b2.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input AND Gate +-- /___/ /\ Filename : AND4B2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:13 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND4B2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND4B2 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end AND4B2; + +architecture AND4B2_V of AND4B2 is +begin + O <= (not I1) and (not I0) and I2 and I3; +end AND4B2_V; + + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and4b3.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input AND Gate +-- /___/ /\ Filename : AND4B3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:13 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND4B3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND4B3 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end AND4B3; + +architecture AND4B3_V of AND4B3 is +begin + O <= (not I1) and (not I0) and (not I2) and I3; +end AND4B3_V; + + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and4b4.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input AND Gate +-- /___/ /\ Filename : AND4B4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:13 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND4B4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND4B4 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end AND4B4; + +architecture AND4B4_V of AND4B4 is +begin + O <= (not I1) and (not I0) and (not I2) and (not I3); +end AND4B4_V; + + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and5.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input AND Gate +-- /___/ /\ Filename : AND5.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:13 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND5 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end AND5; + +architecture AND5_V of AND5 is +begin + O <= I0 and I1 and I2 and I3 and I4; +end AND5_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and5b1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input AND Gate +-- /___/ /\ Filename : AND5B1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:13 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND5B1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND5B1 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end AND5B1; + +architecture AND5B1_V of AND5B1 is +begin + O <= (not I0) and I1 and I2 and I3 and I4; +end AND5B1_V; + + + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and5b2.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input AND Gate +-- /___/ /\ Filename : AND5B2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:14 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND5B2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND5B2 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end AND5B2; + +architecture AND5B2_V of AND5B2 is +begin + O <= (not I0) and (not I1) and I2 and I3 and I4; +end AND5B2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and5b3.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input AND Gate +-- /___/ /\ Filename : AND5B3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:14 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND5B3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND5B3 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end AND5B3; + +architecture AND5B3_V of AND5B3 is +begin + O <= (not I0) and (not I1) and (not I2) and I3 and I4; +end AND5B3_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and5b4.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input AND Gate +-- /___/ /\ Filename : AND5B4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:14 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND5B4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND5B4 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end AND5B4; + +architecture AND5B4_V of AND5B4 is +begin + O <= (not I0) and (not I1) and (not I2) and (not I3) and I4; +end AND5B4_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/and5b5.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input AND Gate +-- /___/ /\ Filename : AND5B5.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:14 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND5B5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND5B5 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end AND5B5; + +architecture AND5B5_V of AND5B5 is +begin + O <= (not I0) and (not I1) and (not I2) and (not I3) and (not I4); +end AND5B5_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bscan_fpgacore.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Boundary Scan Logic Control Circuit for FPGACORE +-- /___/ /\ Filename : BSCAN_FPGACORE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:14 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BSCAN_FPGACORE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity BSCAN_FPGACORE is + port( + CAPTURE : out std_ulogic := 'H'; + DRCK1 : out std_ulogic := 'H'; + DRCK2 : out std_ulogic := 'H'; + RESET : out std_ulogic := 'H'; + SEL1 : out std_ulogic := 'L'; + SEL2 : out std_ulogic := 'L'; + SHIFT : out std_ulogic := 'L'; + TDI : out std_ulogic := 'L'; + UPDATE : out std_ulogic := 'L'; + + TDO1 : in std_ulogic := 'X'; + TDO2 : in std_ulogic := 'X' + ); +end BSCAN_FPGACORE; + +architecture BSCAN_FPGACORE_V of BSCAN_FPGACORE is +begin + CAPTURE <= 'H'; + RESET <= 'H'; + UPDATE <= 'L'; + SHIFT <= 'L'; + DRCK1 <= 'H'; + DRCK2 <= 'H'; + SEL1 <= 'L'; + SEL2 <= 'L'; + TDI <= 'L'; +end BSCAN_FPGACORE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bscan_spartan2.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Boundary Scan Logic Control Circuit for SPARTAN2 +-- /___/ /\ Filename : BSCAN_SPARTAN2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:14 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BSCAN_SPARTAN2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity BSCAN_SPARTAN2 is + port( + DRCK1 : out std_ulogic := 'H'; + DRCK2 : out std_ulogic := 'H'; + RESET : out std_ulogic := 'H'; + SEL1 : out std_ulogic := 'L'; + SEL2 : out std_ulogic := 'L'; + SHIFT : out std_ulogic := 'L'; + TDI : out std_ulogic := 'L'; + UPDATE : out std_ulogic := 'L'; + + TDO1 : in std_ulogic := 'X'; + TDO2 : in std_ulogic := 'X' + ); +end BSCAN_SPARTAN2; + +architecture BSCAN_SPARTAN2_V of BSCAN_SPARTAN2 is +begin + RESET <= 'H'; + UPDATE <= 'L'; + SHIFT <= 'L'; + DRCK1 <= 'H'; + DRCK2 <= 'H'; + SEL1 <= 'L'; + SEL2 <= 'L'; + TDI <= 'L'; +end BSCAN_SPARTAN2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bscan_spartan3.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Boundary Scan Logic Control Circuit for SPARTAN3 +-- /___/ /\ Filename : BSCAN_SPARTAN3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:14 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BSCAN_SPARTAN3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity BSCAN_SPARTAN3 is + port( + CAPTURE : out std_ulogic := 'H'; + DRCK1 : out std_ulogic := 'L'; + DRCK2 : out std_ulogic := 'L'; + RESET : out std_ulogic := 'L'; + SEL1 : out std_ulogic := 'L'; + SEL2 : out std_ulogic := 'L'; + SHIFT : out std_ulogic := 'L'; + TDI : out std_ulogic := 'L'; + UPDATE : out std_ulogic := 'L'; + + TDO1 : in std_ulogic := 'X'; + TDO2 : in std_ulogic := 'X' + ); +end BSCAN_SPARTAN3; + +architecture BSCAN_SPARTAN3_V of BSCAN_SPARTAN3 is +begin + CAPTURE <= 'H'; + RESET <= 'L'; + UPDATE <= 'L'; + SHIFT <= 'L'; + DRCK1 <= 'L'; + DRCK2 <= 'L'; + SEL1 <= 'L'; + SEL2 <= 'L'; + TDI <= 'L'; +end BSCAN_SPARTAN3_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bscan_virtex.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Boundary Scan Logic Control Circuit for VIRTEX +-- /___/ /\ Filename : BSCAN_VIRTEX.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:15 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BSCAN_VIRTEX ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity BSCAN_VIRTEX is + port( + DRCK1 : out std_ulogic := 'H'; + DRCK2 : out std_ulogic := 'H'; + RESET : out std_ulogic := 'H'; + SEL1 : out std_ulogic := 'L'; + SEL2 : out std_ulogic := 'L'; + SHIFT : out std_ulogic := 'L'; + TDI : out std_ulogic := 'L'; + UPDATE : out std_ulogic := 'L'; + + TDO1 : in std_ulogic := 'X'; + TDO2 : in std_ulogic := 'X' + ); +end BSCAN_VIRTEX; + +architecture BSCAN_VIRTEX_V of BSCAN_VIRTEX is +begin + RESET <= 'H'; + UPDATE <= 'L'; + SHIFT <= 'L'; + DRCK1 <= 'H'; + DRCK2 <= 'H'; + SEL1 <= 'L'; + SEL2 <= 'L'; + TDI <= 'L'; +end BSCAN_VIRTEX_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bscan_virtex2.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Boundary Scan Logic Control Circuit for VIRTEX2 +-- /___/ /\ Filename : BSCAN_VIRTEX2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:15 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BSCAN_VIRTEX2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity BSCAN_VIRTEX2 is + port( + CAPTURE : out std_ulogic := 'H'; + DRCK1 : out std_ulogic := 'H'; + DRCK2 : out std_ulogic := 'H'; + RESET : out std_ulogic := 'H'; + SEL1 : out std_ulogic := 'L'; + SEL2 : out std_ulogic := 'L'; + SHIFT : out std_ulogic := 'L'; + TDI : out std_ulogic := 'L'; + UPDATE : out std_ulogic := 'L'; + + TDO1 : in std_ulogic := 'X'; + TDO2 : in std_ulogic := 'X' + ); +end BSCAN_VIRTEX2; + +architecture BSCAN_VIRTEX2_V of BSCAN_VIRTEX2 is +begin + CAPTURE <= 'H'; + RESET <= 'H'; + UPDATE <= 'L'; + SHIFT <= 'L'; + DRCK1 <= 'H'; + DRCK2 <= 'H'; + SEL1 <= 'L'; + SEL2 <= 'L'; + TDI <= 'L'; +end BSCAN_VIRTEX2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/buf.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / General Purpose Buffer +-- /___/ /\ Filename : BUF.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:15 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BUF ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity BUF is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end BUF; + +architecture BUF_V of BUF is +begin + O <= TO_X01(I); +end BUF_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bufcf.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Fast Connect Buffer +-- /___/ /\ Filename : BUFCF.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:15 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BUFCF ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity BUFCF is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end BUFCF; + +architecture BUFCF_V of BUFCF is +begin + O <= TO_X01(I); +end BUFCF_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bufe.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Internal 3-State Buffer with Active High Enable +-- /___/ /\ Filename : BUFE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:15 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BUFE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity BUFE is + port( + O : out std_ulogic; + + E : in std_ulogic; + I : in std_ulogic + ); +end BUFE; + +architecture BUFE_V of BUFE is +begin + VITALBehavior : process(E, I) + begin + if ((E = '0') or (E = 'L')) then + O <= 'Z'; + elsif ((E = '1') or (E = 'H')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (E = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end BUFE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bufg.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Buffer +-- /___/ /\ Filename : BUFG.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:15 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BUFG ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity BUFG is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end BUFG; + +architecture BUFG_V of BUFG is +begin + O <= TO_X01(I); +end BUFG_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bufgce.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Mux Buffer with Clock Enable and Output State 0 +-- /___/ /\ Filename : BUFGCE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:15 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BUFGCE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VCOMPONENTS.all; + +entity BUFGCE is + port( + O : out STD_ULOGIC; + + CE: in STD_ULOGIC; + I : in STD_ULOGIC + ); +end BUFGCE; + +architecture BUFGCE_V of BUFGCE is + + signal NCE : STD_ULOGIC := 'X'; + signal GND : STD_ULOGIC := '0'; + +begin + B1 : BUFGMUX + port map ( + I0 => I, + I1 => GND, + O =>O, + s =>NCE); + + I1 : INV + port map ( + I => CE, + O => NCE); + +end BUFGCE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bufgce_1.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Mux Buffer with Clock Enable and Output State 1 +-- /___/ /\ Filename : BUFGCE_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:15 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BUFGCE_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VCOMPONENTS.all; + +entity BUFGCE_1 is + port( + O : out STD_ULOGIC; + + CE: in STD_ULOGIC; + I : in STD_ULOGIC + ); +end BUFGCE_1; +architecture BUFGCE_1_V of BUFGCE_1 is + + signal NCE : STD_ULOGIC := 'X'; + signal VCC : STD_ULOGIC := '1'; + +begin + B1 : BUFGMUX_1 + port map ( + I0 => I, + I1 => VCC, + O => O, + s => NCE); + + I1 : INV + port map ( + I => CE, + O => NCE); + +end BUFGCE_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bufgdll.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Clock Delay Locked Loop Buffer +-- /___/ /\ Filename : BUFGDLL.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:16 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BUFGDLL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VCOMPONENTS.all; + +entity BUFGDLL is + generic( + DUTY_CYCLE_CORRECTION : boolean := true + ); + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end BUFGDLL; + +architecture BUFGDLL_V of BUFGDLL is + + signal clkin_int, clkout : std_ulogic; + signal clk0_out, clk180_out, clk270_out, clk90_out : std_ulogic; + signal clk2x_out, clkdv_out, locked_out : std_ulogic := '0'; + signal gnd : std_ulogic := '0'; +begin + IBUFG_inst : IBUFG + port map ( + O => clkin_int, + + I => I + ); + + CLKDLL_inst : CLKDLL + generic map ( + DUTY_CYCLE_CORRECTION => DUTY_CYCLE_CORRECTION + ) + + port map( + CLK0 => clk0_out, + CLK180 => clk180_out, + CLK270 => clk270_out, + CLK2X => clk2x_out, + CLK90 => clk90_out, + CLKDV => clkdv_out, + LOCKED => locked_out, + + CLKFB => clkout, + CLKIN => clkin_int, + RST => gnd + ); + + BUFG_inst : BUFG + port map ( + O => clkout, + + I => clk0_out + ); + + O <= clkout; +end BUFGDLL_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bufgmux.vhd,v 1.6.228.1 2008/02/29 00:12:09 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Mux Buffer with Output State 0 +-- /___/ /\ Filename : BUFGMUX.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:16 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 02/07/08 - Recoding same as verilog model. (CR467336) +-- End Revision + + +----- CELL BUFGMUX ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity BUFGMUX is + port( + O : out std_ulogic; + + I0 : in std_ulogic := '0'; + I1 : in std_ulogic := '0'; + S : in std_ulogic + ); + +end BUFGMUX; + +architecture BUFGMUX_V of BUFGMUX is + signal q0 : std_ulogic := '1'; + signal q0_enable : std_ulogic := '1'; + signal q1 : std_ulogic := '0'; + signal q1_enable : std_ulogic := '0'; +begin + + O <= I0 when (q0 = '1') else I1 when (q1 = '1') else 'X' when ( q0 = 'X' or q1 = 'X') else 'L'; + + q0_p : process(I0, S, q0_enable) + begin + if (I0 /= '1') then + q0 <= (not S) and q0_enable; + end if; + end process; + + q1_p : process(I1, S, q1_enable) + begin + if (I1 /= '1') then + q1 <= S and q1_enable; + end if; + end process; + + q0_en_p : process(q1, I0) + begin + if (q1 = '1') then + q0_enable <= '0'; + elsif (I0 /= '0') then + q0_enable <= not q1; + end if; + end process; + + q1_en_p : process(q0, I1) + begin + if (q0 = '1') then + q1_enable <= '0'; + elsif (I1 /= '0') then + q1_enable <= not q0; + end if; + end process; + +end BUFGMUX_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bufgmux_1.vhd,v 1.6.228.1 2008/02/29 00:15:22 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Mux Buffer with Output State 1 +-- /___/ /\ Filename : BUFGMUX_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:16 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 02/07/08 - Recoding same as verilog model. (CR467336) +-- End Revision + +----- CELL BUFGMUX_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity BUFGMUX_1 is + port( + O : out std_ulogic; + + I0 : in std_ulogic := '1'; + I1 : in std_ulogic := '1'; + S : in std_ulogic + ); +end BUFGMUX_1; + +architecture BUFGMUX_1_V of BUFGMUX_1 is + signal q0 : std_ulogic := '1'; + signal q0_enable : std_ulogic := '1'; + signal q1 : std_ulogic := '0'; + signal q1_enable : std_ulogic := '0'; +begin + + O <= I0 when (q0 = '1') else I1 when (q1 = '1') else 'X' when ( q0 = 'X' or q1 = 'X') else 'H'; + + q0_p : process(I0, S, q0_enable) + begin + if (I0 /= '0') then + q0 <= (not S) and q0_enable; + end if; + end process; + + q1_p : process(I1, S, q1_enable) + begin + if (I1 /= '0') then + q1 <= S and q1_enable; + end if; + end process; + + q0_en_p : process(q1, I0) + begin + if (q1 = '1') then + q0_enable <= '0'; + elsif (I0 /= '1') then + q0_enable <= not q1; + end if; + end process; + + q1_en_p : process(q0, I1) + begin + if (q0 = '1') then + q1_enable <= '0'; + elsif (I1 /= '1') then + q1_enable <= not q0; + end if; + end process; + + +end BUFGMUX_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/bufgp.vhd,v 1.5 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Primary Global Buffer for Driving Clocks or Long Lines +-- /___/ /\ Filename : BUFGP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:16 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BUFGP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity BUFGP is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end BUFGP; + +architecture BUFGP_V of BUFGP is +begin + O <= TO_X01(I); +end BUFGP_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/buft.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Internal 3-State Buffers with Active Low Enable +-- /___/ /\ Filename : BUFT.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:16 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BUFT ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity BUFT is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); +end BUFT; + +architecture BUFT_V of BUFT is +begin + VITALBehavior : process(I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end BUFT_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/capture_fpgacore.vhd,v 1.8 2006/01/10 08:24:56 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Register State Capture for Bitstream Readback for FPGACORE +-- /___/ /\ Filename : CAPTURE_FPGACORE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:16 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 07/23/05 - Added ONESHOT to all CAPUTURE comps; CR # 212645 +-- 01/10/06 - made ONESHOT false; CR # 220151 +-- End Revision + + +----- CELL CAPTURE_FPGACORE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CAPTURE_FPGACORE is + generic( + ONESHOT : boolean := false + ); + port( + CAP : in std_ulogic; + CLK : in std_ulogic + ); +end CAPTURE_FPGACORE; + +architecture CAPTURE_FPGACORE_V of CAPTURE_FPGACORE is +begin +end CAPTURE_FPGACORE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/capture_spartan2.vhd,v 1.8 2006/01/10 08:24:56 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Register State Capture for Bitstream Readback for SPARTAN2 +-- /___/ /\ Filename : CAPTURE_SPARTAN2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:16 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 07/23/05 - Added ONESHOT to all CAPUTURE comps; CR # 212645 +-- 01/10/06 - made ONESHOT false; CR # 220151 +-- End Revision + +----- CELL CAPTURE_SPARTAN2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CAPTURE_SPARTAN2 is + generic( + ONESHOT : boolean := false + ); + port( + CAP : in std_ulogic; + CLK : in std_ulogic + ); +end CAPTURE_SPARTAN2; + +architecture CAPTURE_SPARTAN2_V of CAPTURE_SPARTAN2 is +begin +end CAPTURE_SPARTAN2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/capture_spartan3.vhd,v 1.8 2006/01/10 08:24:56 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Register State Capture for Bitstream Readback for SPARTAN3 +-- /___/ /\ Filename : CAPTURE_SPARTAN3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:17 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 07/23/05 - Added ONESHOT to all CAPUTURE comps; CR # 212645 +-- 01/10/06 - made ONESHOT false; CR # 220151 +-- End Revision + +----- CELL CAPTURE_SPARTAN3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CAPTURE_SPARTAN3 is + generic( + ONESHOT : boolean := false + ); + port( + CAP : in std_ulogic; + CLK : in std_ulogic + ); +end CAPTURE_SPARTAN3; + +architecture CAPTURE_SPARTAN3_V of CAPTURE_SPARTAN3 is +begin +end CAPTURE_SPARTAN3_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/capture_virtex.vhd,v 1.8 2006/01/10 08:24:56 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Register State Capture for Bitstream Readback for VIRTEX +-- /___/ /\ Filename : CAPTURE_VIRTEX.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:17 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 07/23/05 - Added ONESHOT to all CAPUTURE comps; CR # 212645 +-- 01/10/06 - made ONESHOT false; CR # 220151 +-- End Revision + + +----- CELL CAPTURE_VIRTEX ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CAPTURE_VIRTEX is + generic( + ONESHOT : boolean := false + ); + port( + CAP : in std_ulogic; + CLK : in std_ulogic + ); +end CAPTURE_VIRTEX; + +architecture CAPTURE_VIRTEX_V of CAPTURE_VIRTEX is +begin +end CAPTURE_VIRTEX_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/capture_virtex2.vhd,v 1.8 2006/01/10 08:24:56 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Register State Capture for Bitstream Readback for VIRTEX2 +-- /___/ /\ Filename : CAPTURE_VIRTEX2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:17 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 07/23/05 - Added ONESHOT to all CAPUTURE comps; CR # 212645 +-- 01/10/06 - made ONESHOT false; CR # 220151 +-- End Revision + + +----- CELL CAPTURE_VIRTEX2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CAPTURE_VIRTEX2 is + generic( + ONESHOT : boolean := false + ); + port( + CAP : in std_ulogic; + CLK : in std_ulogic + ); +end CAPTURE_VIRTEX2; + +architecture CAPTURE_VIRTEX2_V of CAPTURE_VIRTEX2 is +begin +end CAPTURE_VIRTEX2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/clkdll.vhd,v 1.15 2007/06/01 23:01:22 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Clock Delay Locked Loop +-- /___/ /\ Filename : CLKDLL.vhd +-- \ \ / \ Timestamp : Fri Jun 18 10:55:21 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 05/09/05 - Change RST check from 3 clkin cycles to 2 ns (CR200477). +-- 05/25/06 - Remove GSR (232012). +-- 05/10/07 - Remove vital timing. +-- End Revision + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library STD; +use STD.TEXTIO.all; + + + +entity clkdll_maximum_period_check is + generic ( + clock_name : string := ""; + maximum_period : time); + port( + clock : in std_ulogic; + rst : in std_ulogic + ); +end clkdll_maximum_period_check; + +architecture clkdll_maximum_period_check_V of clkdll_maximum_period_check is +begin + + MAX_PERIOD_CHECKER : process + variable clock_edge_previous : time := 0 ps; + variable clock_edge_current : time := 0 ps; + variable clock_period : time := 0 ps; + variable Message : line; + begin + if (rising_edge(clock)) then + clock_edge_previous := clock_edge_current; + clock_edge_current := NOW; + + if (clock_edge_previous > 0 ps) then + clock_period := clock_edge_current - clock_edge_previous; + end if; + + if ((clock_period > maximum_period) and (rst = '0')) then + Write ( Message, string'(" Error : Input Clock Period of")); + Write ( Message, clock_period/1000.0 ); + Write ( Message, string'(" on the ") ); + Write ( Message, clock_name ); + Write ( Message, string'(" port ") ); + Write ( Message, string'(" of CLKDLL ") ); + Write ( Message, string'(" exceeds allotted value of ") ); + Write ( Message, maximum_period/1000.0 ); + Write ( Message, string'(" at simulation time ") ); + Write ( Message, clock_edge_current/1000.0 ); + Write ( Message, '.' & LF ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + end if; + end if; + wait on clock; + end process MAX_PERIOD_CHECKER; +end clkdll_maximum_period_check_V; + +----- CELL CLKDLL ----- +library IEEE; +use IEEE.std_logic_1164.all; + +library STD; +use STD.TEXTIO.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + + +entity CLKDLL is + generic ( + CLKDV_DIVIDE : real := 2.0; + DUTY_CYCLE_CORRECTION : boolean := true; + FACTORY_JF : bit_vector := X"C080"; --non-simulatable + STARTUP_WAIT : boolean := false --non-simulatable + ); + + port ( + CLK0 : out std_ulogic := '0'; + CLK180 : out std_ulogic := '0'; + CLK270 : out std_ulogic := '0'; + CLK2X : out std_ulogic := '0'; + CLK90 : out std_ulogic := '0'; + CLKDV : out std_ulogic := '0'; + LOCKED : out std_ulogic := '0'; + + CLKFB : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0'; + RST : in std_ulogic := '0' + ); + +end CLKDLL; + +architecture CLKDLL_V of CLKDLL is + + component clkdll_maximum_period_check + generic ( + clock_name : string := ""; + maximum_period : time); + port( + clock : in std_ulogic; + rst : in std_ulogic + ); + end component; + + constant MAXPERCLKIN : time := 40000 ps; + constant SIM_CLKIN_CYCLE_JITTER : time := 300 ps; + constant SIM_CLKIN_PERIOD_JITTER : time := 1000 ps; + + signal CLKFB_ipd, CLKIN_ipd, RST_ipd : std_ulogic; + signal clk0_out : std_ulogic; + signal clk2x_out, clkdv_out, locked_out : std_ulogic := '0'; + + signal clkfb_type : integer; + signal divide_type : integer; + signal clk1x_type : integer; + + signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0'; + signal lock_out : std_logic_vector(1 downto 0) := "00"; + + signal lock_fb : std_ulogic := '0'; + signal fb_delay_found : std_ulogic := '0'; + + signal clkin_ps : std_ulogic; + signal clkin_fb, clkin_fb0, clkin_fb1, clkin_fb2 : std_ulogic; + type real_array_usr is array (2 downto 0) of time; + signal clkin_period_real : real_array_usr := (0.000 ns, 0.000 ns, 0.000 ns); + signal period : time := 0 ps; + signal period_orig : time := 0 ps; + signal period_ps : time := 0 ps; + signal clkout_delay : time := 0 ps; + signal fb_delay : time := 0 ps; + signal period_dv_high, period_dv_low : time := 0 ps; + signal cycle_jitter, period_jitter : time := 0 ps; + + signal clkin_window, clkfb_window : std_ulogic := '0'; + signal clkin_5050 : std_ulogic := '0'; + signal rst_reg : std_logic_vector(2 downto 0) := "000"; + + signal clkin_period_real0_temp : time := 0 ps; + signal ps_lock_temp : std_ulogic := '0'; + + signal clk0_temp : std_ulogic := '0'; + signal clk2x_temp : std_ulogic := '0'; + + signal no_stop : boolean := false; + +begin + INITPROC : process + begin + detect_resolution + (model_name => "CLKDLL" + ); + if (CLKDV_DIVIDE = 1.5) then + divide_type <= 3; + elsif (CLKDV_DIVIDE = 2.0) then + divide_type <= 4; + elsif (CLKDV_DIVIDE = 2.5) then + divide_type <= 5; + elsif (CLKDV_DIVIDE = 3.0) then + divide_type <= 6; + elsif (CLKDV_DIVIDE = 4.0) then + divide_type <= 8; + elsif (CLKDV_DIVIDE = 5.0) then + divide_type <= 10; + elsif (CLKDV_DIVIDE = 8.0) then + divide_type <= 16; + elsif (CLKDV_DIVIDE = 16.0) then + divide_type <= 32; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLKDV_DIVIDE", + EntityName => "CLKDLL", + GenericValue => CLKDV_DIVIDE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + clkfb_type <= 2; + + period_jitter <= SIM_CLKIN_PERIOD_JITTER; + cycle_jitter <= SIM_CLKIN_CYCLE_JITTER; + + case DUTY_CYCLE_CORRECTION is + when false => clk1x_type <= 0; + when true => clk1x_type <= 1; + when others => + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "DUTY_CYCLE_CORRECTION", + EntityName => "CLKDLL", + GenericValue => DUTY_CYCLE_CORRECTION, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end case; + + case STARTUP_WAIT is + when false => null; + when true => null; + when others => + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "STARTUP_WAIT", + EntityName => "CLKDLL", + GenericValue => STARTUP_WAIT, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end case; + wait; + end process INITPROC; + +-- +-- input wire delays +-- + + CLKIN_ipd <= CLKIN; + CLKFB_ipd <= CLKFB; + RST_ipd <= RST; + + + i_max_clkin : clkdll_maximum_period_check + generic map ( + clock_name => "CLKIN", + maximum_period => MAXPERCLKIN) + + port map ( + clock => clkin_ipd, + rst => rst_ipd); + + assign_clkin_ps : process + begin + if (rst_ipd = '0') then + clkin_ps <= clkin_ipd; + elsif (rst_ipd = '1') then + clkin_ps <= '0'; + wait until (falling_edge(rst_reg(2))); + end if; + wait on clkin_ipd, rst_ipd; + end process assign_clkin_ps; + + clkin_fb0 <= transport (clkin_ps and lock_fb) after period_ps/4; + clkin_fb1 <= transport clkin_fb0 after period_ps/4; + clkin_fb2 <= transport clkin_fb1 after period_ps/4; + clkin_fb <= transport clkin_fb2 after period_ps/4; + + determine_period_ps : process + variable clkin_ps_edge_previous : time := 0 ps; + variable clkin_ps_edge_current : time := 0 ps; + begin + if (rst_ipd'event) then + clkin_ps_edge_previous := 0 ps; + clkin_ps_edge_current := 0 ps; + period_ps <= 0 ps; + else + if (rising_edge(clkin_ps)) then + clkin_ps_edge_previous := clkin_ps_edge_current; + clkin_ps_edge_current := NOW; + wait for 0 ps; + if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then + period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; + elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then + period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; + end if; + end if; + end if; + wait on clkin_ps, rst_ipd; + end process determine_period_ps; + + assign_lock_fb : process + begin + if (rising_edge(clkin_ps)) then + lock_fb <= lock_period; + end if; + wait on clkin_ps; + end process assign_lock_fb; + + calculate_clkout_delay : process + begin + if (rst_ipd'event) then + clkout_delay <= 0 ps; + elsif (period'event or fb_delay'event) then + clkout_delay <= period - fb_delay; + end if; + wait on period, fb_delay, rst_ipd; + end process calculate_clkout_delay; + +-- +--generate master reset signal +-- + + gen_master_rst : process + begin + if (rising_edge(clkin_ipd)) then + rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_ipd; + rst_reg(1) <= rst_reg(0) and rst_ipd; + rst_reg(0) <= rst_ipd; + end if; + wait on clkin_ipd; + end process gen_master_rst; + + check_rst_width : process + variable Message : line; + variable rst_tmp1, rst_tmp2 : time := 0 ps; + begin + if ((rising_edge(rst_ipd)) or (falling_edge(rst_ipd))) then + if (rst_ipd = '1') then + rst_tmp1 := NOW; + elsif (rst_ipd = '1') then + rst_tmp2 := NOW - rst_tmp1; + end if; + if ((rst_tmp2 < 2000 ps) and (rst_tmp2 /= 0 ps)) then + Write ( Message, string'(" Error : RST ")); + Write ( Message, string'(" must be asserted atleast for 2 ns. ")); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + end if; + wait on rst_ipd; + end process check_rst_width; + +-- +--determine clock period +-- + determine_clock_period : process + variable clkin_edge_previous : time := 0 ps; + variable clkin_edge_current : time := 0 ps; + begin + if (rst_ipd'event) then + clkin_period_real(0) <= 0 ps; + clkin_period_real(1) <= 0 ps; + clkin_period_real(2) <= 0 ps; + elsif (rising_edge(clkin_ps)) then + clkin_edge_previous := clkin_edge_current; + clkin_edge_current := NOW; + clkin_period_real(2) <= clkin_period_real(1); + clkin_period_real(1) <= clkin_period_real(0); + if (clkin_edge_previous /= 0 ps) then + clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous; + end if; + end if; + if (no_stop'event) then + clkin_period_real(0) <= clkin_period_real0_temp; + end if; + wait on clkin_ps, no_stop, rst_ipd; + end process determine_clock_period; + + evaluate_clock_period : process + variable clock_stopped : std_ulogic := '1'; + variable Message : line; + begin + if (rst_ipd'event) then + lock_period <= '0'; + clock_stopped := '1'; + clkin_period_real0_temp <= 0 ps; + else + if (falling_edge(clkin_ps)) then + if (lock_period = '0') then + if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then + lock_period <= '1'; + period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3; + period <= clkin_period_real(0); + end if; + elsif (lock_period = '1') then + if (100000000 ps < clkin_period_real(0)/1000) then + Write ( Message, string'(" Error : CLKIN stopped toggling ")); + Write ( Message, string'(" exceeds ")); + Write ( Message, string'(" 10000 ")); + Write ( Message, string'(" Current CLKIN Period = ")); + Write ( Message, string'(" clkin_period(0) / 10000.0 ")); + Write ( Message, string'(" ns ")); + assert false report Message.all severity warning; + DEALLOCATE (Message); + lock_period <= '0'; + wait until (falling_edge(rst_reg(2))); + elsif ((period_orig * 2 < clkin_period_real(0)) and (clock_stopped = '0')) then + clkin_period_real0_temp <= clkin_period_real(1); + no_stop <= not no_stop; + clock_stopped := '1'; + elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then + Write ( Message, string'(" Error : Input Clock Period Jitter ")); + Write ( Message, string'(" exceeds ")); + Write ( Message, period_jitter / 1000.0 ); + Write ( Message, string'(" Locked CLKIN Period = ")); + Write ( Message, period_orig / 1000.0 ); + Write ( Message, string'(" Current CLKIN Period = ")); + Write ( Message, clkin_period_real(0) / 1000.0 ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + lock_period <= '0'; + wait until (falling_edge(rst_reg(2))); + elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then + Write ( Message, string'(" Error : Input Clock Cycle Jitter ")); + Write ( Message, string'(" exceeds ")); + Write ( Message, cycle_jitter / 1000.0 ); + Write ( Message, string'(" Previous CLKIN Period = ")); + Write ( Message, clkin_period_real(1) / 1000.0 ); + Write ( Message, string'(" Current CLKIN Period = ")); + Write ( Message, clkin_period_real(0) / 1000.0 ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + lock_period <= '0'; + wait until (falling_edge(rst_reg(2))); + else + period <= clkin_period_real(0); + clock_stopped := '0'; + end if; + end if; + end if; + end if; + wait on clkin_ps, rst_ipd; + end process evaluate_clock_period; + +-- +--determine clock delay +-- + + determine_clock_delay : process + variable delay_edge : time := 0 ps; + variable temp1 : integer := 0; + variable temp2 : integer := 0; + variable temp : integer := 0; + variable delay_edge_current : time := 0 ps; + begin + if (rst_ipd'event) then + fb_delay <= 0 ps; + fb_delay_found <= '0'; + else + if (rising_edge(lock_period)) then + if ((lock_period = '1') and (clkfb_type /= 0)) then + if (clkfb_type = 1) then + wait until ((rising_edge(clk0_temp)) or (rst_ipd'event)); + delay_edge := NOW; + elsif (clkfb_type = 2) then + wait until ((rising_edge(clk2x_temp)) or (rst_ipd'event)); + delay_edge := NOW; + end if; + wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event)); + temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps); + temp2 := (period_orig * 1)/ (1 ps); + temp := temp1 mod temp2; + fb_delay <= temp * 1 ps; + end if; + end if; + fb_delay_found <= '1'; + end if; + wait on lock_period, rst_ipd; + end process determine_clock_delay; +-- +-- determine feedback lock +-- + GEN_CLKFB_WINDOW : process + begin + if (rst_ipd'event) then + clkfb_window <= '0'; + else + if (rising_edge(CLKFB_ipd)) then + wait for 0 ps; + clkfb_window <= '1'; + wait for cycle_jitter; + clkfb_window <= '0'; + end if; + end if; + wait on clkfb_ipd, rst_ipd; + end process GEN_CLKFB_WINDOW; + + GEN_CLKIN_WINDOW : process + begin + if (rst_ipd'event) then + clkin_window <= '0'; + else + if (rising_edge(clkin_fb)) then + wait for 0 ps; + clkin_window <= '1'; + wait for cycle_jitter; + clkin_window <= '0'; + end if; + end if; + wait on clkin_fb, rst_ipd; + end process GEN_CLKIN_WINDOW; + + set_reset_lock_clkin : process + begin + if (rst_ipd'event) then + lock_clkin <= '0'; + else + if (rising_edge(clkin_fb)) then + wait for 1 ps; + if ((clkfb_window = '1') and (fb_delay_found = '1')) then + lock_clkin <= '1'; + else + lock_clkin <= '0'; + end if; + end if; + end if; + wait on clkin_fb, rst_ipd; + end process set_reset_lock_clkin; + + set_reset_lock_clkfb : process + begin + if (rst_ipd'event) then + lock_clkfb <= '0'; + else + if (rising_edge(clkfb_ipd)) then + wait for 1 ps; + if ((clkin_window = '1') and (fb_delay_found = '1')) then + lock_clkfb <= '1'; + else + lock_clkfb <= '0'; + end if; + end if; + end if; + wait on clkfb_ipd, rst_ipd; + end process set_reset_lock_clkfb; + + assign_lock_delay : process + begin + if (rst_ipd'event) then + lock_delay <= '0'; + else + if (falling_edge(clkin_fb)) then + lock_delay <= lock_clkin or lock_clkfb; + end if; + end if; + wait on clkin_fb, rst_ipd; + end process; + +-- +--generate lock signal +-- + + generate_lock : process + begin + if (rst_ipd'event) then + lock_out <= "00"; + locked_out <= '0'; + else + if (rising_edge(clkin_ps)) then + if (clkfb_type = 0) then + lock_out(0) <= lock_period; + else + lock_out(0) <= lock_period and lock_delay and lock_fb; + end if; + lock_out(1) <= lock_out(0); + locked_out <= lock_out(1); + + end if; + end if; + wait on clkin_ps, rst_ipd; + end process generate_lock; + +-- +--generate the clk1x_out +-- + + gen_clk1x : process + begin + if (rst_ipd'event) then + clkin_5050 <= '0'; + else + if (rising_edge(clkin_ps)) then + clkin_5050 <= '1'; + wait for (period/2); + clkin_5050 <= '0'; + end if; + end if; + wait on clkin_ps, rst_ipd; + end process gen_clk1x; + + clk0_out <= clkin_5050 when (clk1x_type = 1) else clkin_ps; + +-- +--generate the clk2x_out +-- + + gen_clk2x : process + begin + + if (rising_edge(clkin_ps)) then + clk2x_out <= '1'; + wait for (period / 4); + clk2x_out <= '0'; + if (lock_out(0) = '1') then + wait for (period / 4); + clk2x_out <= '1'; + wait for (period / 4); + clk2x_out <= '0'; + else + wait for (period / 2); + end if; + end if; + wait on clkin_ps; + end process gen_clk2x; + +-- +--generate the clkdv_out +-- + + determine_clkdv_period : process + begin + if (period'event) then +-- period_dv_high <= (period / 2) * (divide_type / 2); +-- period_dv_low <= (period / 2) * (divide_type / 2 + divide_type mod 2); + period_dv_high <= (period * divide_type) / 4; + period_dv_low <= (period * divide_type) / 4; + end if; + wait on period; + end process determine_clkdv_period; + + + gen_clkdv : process + begin + if (rising_edge(clkin_ps)) then + if (lock_out(0) = '1') then + clkdv_out <= '1'; + wait for (period_dv_high); + clkdv_out <= '0'; + wait for (period_dv_low); + clkdv_out <= '1'; + wait for (period_dv_high); + clkdv_out <= '0'; + wait for (period_dv_low - period/2); + end if; + end if; + wait on clkin_ps; + end process gen_clkdv; + + +-- +--generate all output signal +-- + schedule_outputs : process + begin + if (CLK0_out'event) then + CLK0 <= transport CLK0_out after clkout_delay; + clk0_temp <= transport CLK0_out after clkout_delay; + CLK90 <= transport clk0_out after (clkout_delay + period / 4); + CLK180 <= transport clk0_out after (clkout_delay + period / 2); + CLK270 <= transport clk0_out after (clkout_delay + (3 * period) / 4); + end if; + + if (clk2x_out'event) then + CLK2X <= transport clk2x_out after clkout_delay; + clk2x_temp <= transport clk2x_out after clkout_delay; + end if; + + if (clkdv_out'event) then + CLKDV <= transport clkdv_out after clkout_delay; + end if; + + LOCKED <= locked_out after 100 ps; + wait on clk0_out, clk2x_out, clkdv_out, locked_out; + end process schedule_outputs; + +end CLKDLL_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/clkdlle.vhd,v 1.15 2007/06/01 23:01:22 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Clock Delay Locked Loop for Virtex-E +-- /___/ /\ Filename : CLKDLLE.vhd +-- \ \ / \ Timestamp : Fri Jun 18 10:55:21 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 05/09/05 - Change RST check from 3 clkin cycles to 2 ns (CR200477). +-- 05/25/06 - Remove GSR (232012). +-- 05/10/07 - Remove Vital timing. +-- End Revision + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library STD; +use STD.TEXTIO.all; + + + +entity clkdlle_maximum_period_check is + generic ( + clock_name : string := ""; + maximum_period : time); + port( + clock : in std_ulogic; + rst : in std_ulogic + ); +end clkdlle_maximum_period_check; + +architecture clkdlle_maximum_period_check_V of clkdlle_maximum_period_check is +begin + + MAX_PERIOD_CHECKER : process + variable clock_edge_previous : time := 0 ps; + variable clock_edge_current : time := 0 ps; + variable clock_period : time := 0 ps; + variable Message : line; + begin + if (rising_edge(clock)) then + clock_edge_previous := clock_edge_current; + clock_edge_current := NOW; + + if (clock_edge_previous > 0 ps) then + clock_period := clock_edge_current - clock_edge_previous; + end if; + + if ((clock_period > maximum_period) and (rst = '0')) then + Write ( Message, string'(" Error : Input Clock Period of")); + Write ( Message, clock_period/1000.0 ); + Write ( Message, string'(" on the ") ); + Write ( Message, clock_name ); + Write ( Message, string'(" port ") ); + Write ( Message, string'(" of CLKDLLE ") ); + Write ( Message, string'(" exceeds allotted value of ") ); + Write ( Message, maximum_period/1000.0 ); + Write ( Message, string'(" at simulation time ") ); + Write ( Message, clock_edge_current/1000.0 ); + Write ( Message, '.' & LF ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + end if; + end if; + wait on clock; + end process MAX_PERIOD_CHECKER; +end clkdlle_maximum_period_check_V; + +----- CELL CLKDLLE ----- +library IEEE; +use IEEE.std_logic_1164.all; + +library STD; +use STD.TEXTIO.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity CLKDLLE is + generic ( + + CLKDV_DIVIDE : real := 2.0; + DUTY_CYCLE_CORRECTION : boolean := true; + FACTORY_JF : bit_vector := X"C080"; --non-simulatable + STARTUP_WAIT : boolean := false --non-simulatable + ); + + port ( + CLK0 : out std_ulogic := '0'; + CLK180 : out std_ulogic := '0'; + CLK270 : out std_ulogic := '0'; + CLK2X : out std_ulogic := '0'; + CLK2X180 : out std_ulogic := '0'; + CLK90 : out std_ulogic := '0'; + CLKDV : out std_ulogic := '0'; + LOCKED : out std_ulogic := '0'; + + CLKFB : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0'; + RST : in std_ulogic := '0' + ); + +end CLKDLLE; + +architecture CLKDLLE_V of CLKDLLE is + + component clkdlle_maximum_period_check + generic ( + clock_name : string := ""; + maximum_period : time); + port( + clock : in std_ulogic; + rst : in std_ulogic + ); + end component; + + constant MAXPERCLKIN : time := 40000 ps; + constant SIM_CLKIN_CYCLE_JITTER : time := 300 ps; + constant SIM_CLKIN_PERIOD_JITTER : time := 1000 ps; + + signal CLKFB_ipd, CLKIN_ipd, RST_ipd : std_ulogic; + signal clk0_out : std_ulogic; + signal clk2x_out, clkdv_out, locked_out : std_ulogic := '0'; + + signal clkfb_type : integer; + signal divide_type : integer; + signal clk1x_type : integer; + + signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0'; + signal lock_out : std_logic_vector(1 downto 0) := "00"; + + signal lock_fb : std_ulogic := '0'; + signal fb_delay_found : std_ulogic := '0'; + + signal clkin_ps : std_ulogic; + signal clkin_fb, clkin_fb0, clkin_fb1, clkin_fb2 : std_ulogic; + type real_array_usr is array (2 downto 0) of time; + signal clkin_period_real : real_array_usr := (0.000 ns, 0.000 ns, 0.000 ns); + signal period : time := 0 ps; + signal period_orig : time := 0 ps; + signal period_ps : time := 0 ps; + signal clkout_delay : time := 0 ps; + signal fb_delay : time := 0 ps; + signal period_dv_high, period_dv_low : time := 0 ps; + signal cycle_jitter, period_jitter : time := 0 ps; + + signal clkin_window, clkfb_window : std_ulogic := '0'; + signal clkin_5050 : std_ulogic := '0'; + signal rst_reg : std_logic_vector(2 downto 0) := "000"; + + signal clkin_period_real0_temp : time := 0 ps; + signal ps_lock_temp : std_ulogic := '0'; + + signal clk0_temp : std_ulogic := '0'; + signal clk2x_temp : std_ulogic := '0'; + + signal no_stop : boolean := false; + +begin + INITPROC : process + begin + detect_resolution + (model_name => "CLKDLLE" + ); + if (CLKDV_DIVIDE = 1.5) then + divide_type <= 3; + elsif (CLKDV_DIVIDE = 2.0) then + divide_type <= 4; + elsif (CLKDV_DIVIDE = 2.5) then + divide_type <= 5; + elsif (CLKDV_DIVIDE = 3.0) then + divide_type <= 6; + elsif (CLKDV_DIVIDE = 3.5) then + divide_type <= 7; + elsif (CLKDV_DIVIDE = 4.0) then + divide_type <= 8; + elsif (CLKDV_DIVIDE = 4.5) then + divide_type <= 9; + elsif (CLKDV_DIVIDE = 5.0) then + divide_type <= 10; + elsif (CLKDV_DIVIDE = 5.5) then + divide_type <= 11; + elsif (CLKDV_DIVIDE = 6.0) then + divide_type <= 12; + elsif (CLKDV_DIVIDE = 6.5) then + divide_type <= 13; + elsif (CLKDV_DIVIDE = 7.0) then + divide_type <= 14; + elsif (CLKDV_DIVIDE = 7.5) then + divide_type <= 15; + elsif (CLKDV_DIVIDE = 8.0) then + divide_type <= 16; + elsif (CLKDV_DIVIDE = 9.0) then + divide_type <= 18; + elsif (CLKDV_DIVIDE = 10.0) then + divide_type <= 20; + elsif (CLKDV_DIVIDE = 11.0) then + divide_type <= 22; + elsif (CLKDV_DIVIDE = 12.0) then + divide_type <= 24; + elsif (CLKDV_DIVIDE = 13.0) then + divide_type <= 26; + elsif (CLKDV_DIVIDE = 14.0) then + divide_type <= 28; + elsif (CLKDV_DIVIDE = 15.0) then + divide_type <= 30; + elsif (CLKDV_DIVIDE = 16.0) then + divide_type <= 32; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLKDV_DIVIDE", + EntityName => "CLKDLLE", + GenericValue => CLKDV_DIVIDE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + clkfb_type <= 2; + + period_jitter <= SIM_CLKIN_PERIOD_JITTER; + cycle_jitter <= SIM_CLKIN_CYCLE_JITTER; + + case DUTY_CYCLE_CORRECTION is + when false => clk1x_type <= 0; + when true => clk1x_type <= 1; + when others => + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "DUTY_CYCLE_CORRECTION", + EntityName => "CLKDLLE", + GenericValue => DUTY_CYCLE_CORRECTION, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end case; + + case STARTUP_WAIT is + when false => null; + when true => null; + when others => + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "STARTUP_WAIT", + EntityName => "CLKDLLE", + GenericValue => STARTUP_WAIT, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end case; + wait; + end process INITPROC; + +-- +-- input wire delays +-- + + CLKIN_ipd <= CLKIN; + CLKFB_ipd <= CLKFB; + RST_ipd <= RST; + + i_max_clkin : clkdlle_maximum_period_check + generic map ( + clock_name => "CLKIN", + maximum_period => MAXPERCLKIN) + + port map ( + clock => clkin_ipd, + rst => rst_ipd); + + assign_clkin_ps : process + begin + if (rst_ipd = '0') then + clkin_ps <= clkin_ipd; + elsif (rst_ipd = '1') then + clkin_ps <= '0'; + wait until (falling_edge(rst_reg(2))); + end if; + wait on clkin_ipd, rst_ipd; + end process assign_clkin_ps; + + clkin_fb0 <= transport (clkin_ps and lock_fb) after period_ps/4; + clkin_fb1 <= transport clkin_fb0 after period_ps/4; + clkin_fb2 <= transport clkin_fb1 after period_ps/4; + clkin_fb <= transport clkin_fb2 after period_ps/4; + + determine_period_ps : process + variable clkin_ps_edge_previous : time := 0 ps; + variable clkin_ps_edge_current : time := 0 ps; + begin + if (rst_ipd'event) then + clkin_ps_edge_previous := 0 ps; + clkin_ps_edge_current := 0 ps; + period_ps <= 0 ps; + else + if (rising_edge(clkin_ps)) then + clkin_ps_edge_previous := clkin_ps_edge_current; + clkin_ps_edge_current := NOW; + wait for 0 ps; + if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then + period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; + elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then + period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; + end if; + end if; + end if; + wait on clkin_ps, rst_ipd; + end process determine_period_ps; + + assign_lock_fb : process + begin + if (rising_edge(clkin_ps)) then + lock_fb <= lock_period; + end if; + wait on clkin_ps; + end process assign_lock_fb; + + calculate_clkout_delay : process + begin + if (rst_ipd'event) then + clkout_delay <= 0 ps; + elsif (period'event or fb_delay'event) then + clkout_delay <= period - fb_delay; + end if; + wait on period, fb_delay, rst_ipd; + end process calculate_clkout_delay; + +-- +--generate master reset signal +-- + + gen_master_rst : process + begin + if (rising_edge(clkin_ipd)) then + rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_ipd; + rst_reg(1) <= rst_reg(0) and rst_ipd; + rst_reg(0) <= rst_ipd; + end if; + wait on clkin_ipd; + end process gen_master_rst; + + check_rst_width : process + variable Message : line; + variable rst_tmp1, rst_tmp2 : time := 0 ps; + begin + if ((rising_edge(rst_ipd)) or (falling_edge(rst_ipd))) then + if (rst_ipd = '1') then + rst_tmp1 := NOW; + elsif (rst_ipd = '1') then + rst_tmp2 := NOW - rst_tmp1; + end if; + if ((rst_tmp2 < 2000 ps) and (rst_tmp2 /= 0 ps)) then + Write ( Message, string'(" Error : RST ")); + Write ( Message, string'(" must be asserted atleast for 2 ns. ")); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + end if; + wait on rst_ipd; + end process check_rst_width; + +-- +--determine clock period +-- + determine_clock_period : process + variable clkin_edge_previous : time := 0 ps; + variable clkin_edge_current : time := 0 ps; + begin + if (rst_ipd'event) then + clkin_period_real(0) <= 0 ps; + clkin_period_real(1) <= 0 ps; + clkin_period_real(2) <= 0 ps; + elsif (rising_edge(clkin_ps)) then + clkin_edge_previous := clkin_edge_current; + clkin_edge_current := NOW; + clkin_period_real(2) <= clkin_period_real(1); + clkin_period_real(1) <= clkin_period_real(0); + if (clkin_edge_previous /= 0 ps) then + clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous; + end if; + end if; + if (no_stop'event) then + clkin_period_real(0) <= clkin_period_real0_temp; + end if; + wait on clkin_ps, no_stop, rst_ipd; + end process determine_clock_period; + + evaluate_clock_period : process + variable clock_stopped : std_ulogic := '1'; + variable Message : line; + begin + if (rst_ipd'event) then + lock_period <= '0'; + clock_stopped := '1'; + clkin_period_real0_temp <= 0 ps; + else + if (falling_edge(clkin_ps)) then + if (lock_period = '0') then + if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then + lock_period <= '1'; + period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3; + period <= clkin_period_real(0); + end if; + elsif (lock_period = '1') then + if (100000000 ps < clkin_period_real(0)/1000) then + Write ( Message, string'(" Error : CLKIN stopped toggling ")); + Write ( Message, string'(" exceeds ")); + Write ( Message, string'(" 10000 ")); + Write ( Message, string'(" Current CLKIN Period = ")); + Write ( Message, string'(" clkin_period(0) / 10000.0 ")); + Write ( Message, string'(" ns ")); + assert false report Message.all severity warning; + DEALLOCATE (Message); + lock_period <= '0'; + wait until (falling_edge(rst_reg(2))); + elsif ((period_orig * 2 < clkin_period_real(0)) and (clock_stopped = '0')) then + clkin_period_real0_temp <= clkin_period_real(1); + no_stop <= not no_stop; + clock_stopped := '1'; + elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then + Write ( Message, string'(" Error : Input Clock Period Jitter ")); + Write ( Message, string'(" exceeds ")); + Write ( Message, period_jitter / 1000.0 ); + Write ( Message, string'(" Locked CLKIN Period = ")); + Write ( Message, period_orig / 1000.0 ); + Write ( Message, string'(" Current CLKIN Period = ")); + Write ( Message, clkin_period_real(0) / 1000.0 ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + lock_period <= '0'; + wait until (falling_edge(rst_reg(2))); + elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then + Write ( Message, string'(" Error : Input Clock Cycle Jitter ")); + Write ( Message, string'(" exceeds ")); + Write ( Message, cycle_jitter / 1000.0 ); + Write ( Message, string'(" Previous CLKIN Period = ")); + Write ( Message, clkin_period_real(1) / 1000.0 ); + Write ( Message, string'(" Current CLKIN Period = ")); + Write ( Message, clkin_period_real(0) / 1000.0 ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + lock_period <= '0'; + wait until (falling_edge(rst_reg(2))); + end if; + else + period <= clkin_period_real(0); + clock_stopped := '0'; + end if; + end if; + end if; + wait on clkin_ps, rst_ipd; + end process evaluate_clock_period; + +-- +--determine clock delay +-- + + determine_clock_delay : process + variable delay_edge : time := 0 ps; + variable temp1 : integer := 0; + variable temp2 : integer := 0; + variable temp : integer := 0; + variable delay_edge_current : time := 0 ps; + begin + if (rst_ipd'event) then + fb_delay <= 0 ps; + fb_delay_found <= '0'; + else + if (rising_edge(lock_period)) then + if ((lock_period = '1') and (clkfb_type /= 0)) then + if (clkfb_type = 1) then + wait until ((rising_edge(clk0_temp)) or (rst_ipd'event)); + delay_edge := NOW; + elsif (clkfb_type = 2) then + wait until ((rising_edge(clk2x_temp)) or (rst_ipd'event)); + delay_edge := NOW; + end if; + wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event)); + temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps); + temp2 := (period_orig * 1)/ (1 ps); + temp := temp1 mod temp2; + fb_delay <= temp * 1 ps; + end if; + end if; + fb_delay_found <= '1'; + end if; + wait on lock_period, rst_ipd; + end process determine_clock_delay; +-- +-- determine feedback lock +-- + GEN_CLKFB_WINDOW : process + begin + if (rst_ipd'event) then + clkfb_window <= '0'; + else + if (rising_edge(CLKFB_ipd)) then + wait for 0 ps; + clkfb_window <= '1'; + wait for cycle_jitter; + clkfb_window <= '0'; + end if; + end if; + wait on clkfb_ipd, rst_ipd; + end process GEN_CLKFB_WINDOW; + + GEN_CLKIN_WINDOW : process + begin + if (rst_ipd'event) then + clkin_window <= '0'; + else + if (rising_edge(clkin_fb)) then + wait for 0 ps; + clkin_window <= '1'; + wait for cycle_jitter; + clkin_window <= '0'; + end if; + end if; + wait on clkin_fb, rst_ipd; + end process GEN_CLKIN_WINDOW; + + set_reset_lock_clkin : process + begin + if (rst_ipd'event) then + lock_clkin <= '0'; + else + if (rising_edge(clkin_fb)) then + wait for 1 ps; + if ((clkfb_window = '1') and (fb_delay_found = '1')) then + lock_clkin <= '1'; + else + lock_clkin <= '0'; + end if; + end if; + end if; + wait on clkin_fb, rst_ipd; + end process set_reset_lock_clkin; + + set_reset_lock_clkfb : process + begin + if (rst_ipd'event) then + lock_clkfb <= '0'; + else + if (rising_edge(clkfb_ipd)) then + wait for 1 ps; + if ((clkin_window = '1') and (fb_delay_found = '1')) then + lock_clkfb <= '1'; + else + lock_clkfb <= '0'; + end if; + end if; + end if; + wait on clkfb_ipd, rst_ipd; + end process set_reset_lock_clkfb; + + assign_lock_delay : process + begin + if (rst_ipd'event) then + lock_delay <= '0'; + else + if (falling_edge(clkin_fb)) then + lock_delay <= lock_clkin or lock_clkfb; + end if; + end if; + wait on clkin_fb, rst_ipd; + end process; + +-- +--generate lock signal +-- + + generate_lock : process + begin + if (rst_ipd'event) then + lock_out <= "00"; + locked_out <= '0'; + else + if (rising_edge(clkin_ps)) then + if (clkfb_type = 0) then + lock_out(0) <= lock_period; + else + lock_out(0) <= lock_period and lock_delay and lock_fb; + end if; + lock_out(1) <= lock_out(0); + locked_out <= lock_out(1); + + end if; + end if; + wait on clkin_ps, rst_ipd; + end process generate_lock; + +-- +--generate the clk1x_out +-- + + gen_clk1x : process + begin + if (rst_ipd'event) then + clkin_5050 <= '0'; + else + if (rising_edge(clkin_ps)) then + clkin_5050 <= '1'; + wait for (period/2); + clkin_5050 <= '0'; + end if; + end if; + wait on clkin_ps, rst_ipd; + end process gen_clk1x; + + clk0_out <= clkin_5050 when (clk1x_type = 1) else clkin_ps; + +-- +--generate the clk2x_out +-- + + gen_clk2x : process + begin + + if (rising_edge(clkin_ps)) then + clk2x_out <= '1'; + wait for (period / 4); + clk2x_out <= '0'; + if (lock_out(0) = '1') then + wait for (period / 4); + clk2x_out <= '1'; + wait for (period / 4); + clk2x_out <= '0'; + else + wait for (period / 2); + end if; + end if; + wait on clkin_ps; + end process gen_clk2x; + +-- +--generate the clkdv_out +-- + + determine_clkdv_period : process + begin + if (period'event) then +-- period_dv_high <= (period / 2) * (divide_type / 2); +-- period_dv_low <= (period / 2) * (divide_type / 2 + divide_type mod 2); + period_dv_high <= (period * divide_type)/4; + period_dv_low <= (period * divide_type)/4; + end if; + wait on period; + end process determine_clkdv_period; + + + gen_clkdv : process + begin + if (rising_edge(clkin_ps)) then + if (lock_out(0) = '1') then + clkdv_out <= '1'; + wait for (period_dv_high); + clkdv_out <= '0'; + wait for (period_dv_low); + clkdv_out <= '1'; + wait for (period_dv_high); + clkdv_out <= '0'; + wait for (period_dv_low - period/2); + end if; + end if; + wait on clkin_ps; + end process gen_clkdv; + + +-- +--generate all output signal +-- + schedule_outputs : process + begin + if (CLK0_out'event) then + CLK0 <= transport CLK0_out after clkout_delay; + clk0_temp <= transport CLK0_out after clkout_delay; + CLK90 <= transport clk0_out after (clkout_delay + period / 4); + CLK180 <= transport clk0_out after (clkout_delay + period / 2); + CLK270 <= transport clk0_out after (clkout_delay + (3 * period) / 4); + end if; + + if (clk2x_out'event) then + CLK2X <= transport clk2x_out after clkout_delay; + clk2x_temp <= transport clk2x_out after clkout_delay; + CLK2X180 <= transport clk2x_out after (clkout_delay + period/4); + end if; + + if (clkdv_out'event) then + CLKDV <= transport clkdv_out after clkout_delay; + end if; + + LOCKED <= locked_out after 100 ps; + wait on clk0_out, clk2x_out, clkdv_out, locked_out; + end process schedule_outputs; + +end CLKDLLE_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/clkdllhf.vhd,v 1.14 2007/06/01 23:01:22 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / High Frequency Clcok Delay Locked Loop +-- /___/ /\ Filename : CLKDLLHF.vhd +-- \ \ / \ Timestamp : Fri Jun 18 10:55:21 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 05/09/05 - Change RST check from 3 clkin cycles to 2 ns (CR200477). +-- 05/25/06 - Remove GSR (232012). +-- 05/10/07 - Remove vital timing. +-- End Revision + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library STD; +use STD.TEXTIO.all; + + + +entity clkdllhf_maximum_period_check is + generic ( + clock_name : string := ""; + maximum_period : time); + port( + clock : in std_ulogic; + rst : in std_ulogic + ); +end clkdllhf_maximum_period_check; + +architecture clkdllhf_maximum_period_check_V of clkdllhf_maximum_period_check is +begin + + MAX_PERIOD_CHECKER : process + variable clock_edge_previous : time := 0 ps; + variable clock_edge_current : time := 0 ps; + variable clock_period : time := 0 ps; + variable Message : line; + begin + if (rising_edge(clock)) then + clock_edge_previous := clock_edge_current; + clock_edge_current := NOW; + + if (clock_edge_previous > 0 ps) then + clock_period := clock_edge_current - clock_edge_previous; + end if; + + if ((clock_period > maximum_period) and (rst = '0')) then + Write ( Message, string'(" Error : Input Clock Period of")); + Write ( Message, clock_period/1000.0 ); + Write ( Message, string'(" on the ") ); + Write ( Message, clock_name ); + Write ( Message, string'(" port ") ); + Write ( Message, string'(" of CLKDLLHF ") ); + Write ( Message, string'(" exceeds allotted value of ") ); + Write ( Message, maximum_period/1000.0 ); + Write ( Message, string'(" at simulation time ") ); + Write ( Message, clock_edge_current/1000.0 ); + Write ( Message, '.' & LF ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + end if; + end if; + wait on clock; + end process MAX_PERIOD_CHECKER; +end clkdllhf_maximum_period_check_V; + +----- CELL CLKDLLHF ----- +library IEEE; +use IEEE.std_logic_1164.all; + +library STD; +use STD.TEXTIO.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity CLKDLLHF is + generic ( + CLKDV_DIVIDE : real := 2.0; + DUTY_CYCLE_CORRECTION : boolean := true; + FACTORY_JF : bit_vector := X"FFF0"; --non-simulatable + STARTUP_WAIT : boolean := false --non-simulatable + ); + + port ( + CLK0 : out std_ulogic := '0'; + CLK180 : out std_ulogic := '0'; + CLKDV : out std_ulogic := '0'; + LOCKED : out std_ulogic := '0'; + + CLKFB : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0'; + RST : in std_ulogic := '0' + ); + +end CLKDLLHF; + +architecture CLKDLLHF_V of CLKDLLHF is + + component clkdllhf_maximum_period_check + generic ( + clock_name : string := ""; + maximum_period : time); + port( + clock : in std_ulogic; + rst : in std_ulogic + ); + end component; + + constant MAXPERCLKIN : time := 40000 ps; + constant SIM_CLKIN_CYCLE_JITTER : time := 300 ps; + constant SIM_CLKIN_PERIOD_JITTER : time := 1000 ps; + + signal CLKFB_ipd, CLKIN_ipd, RST_ipd : std_ulogic; + signal clk0_out : std_ulogic; + signal clkdv_out, locked_out : std_ulogic := '0'; + + signal clkfb_type : integer; + signal divide_type : integer; + signal clk1x_type : integer; + + signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0'; + signal lock_out : std_logic_vector(1 downto 0) := "00"; + + signal lock_fb : std_ulogic := '0'; + signal fb_delay_found : std_ulogic := '0'; + + signal clkin_ps : std_ulogic; + signal clkin_fb, clkin_fb0, clkin_fb1, clkin_fb2 : std_ulogic; + type real_array_usr is array (2 downto 0) of time; + signal clkin_period_real : real_array_usr := (0.000 ns, 0.000 ns, 0.000 ns); + signal period : time := 0 ps; + signal period_orig : time := 0 ps; + signal period_ps : time := 0 ps; + signal clkout_delay : time := 0 ps; + signal fb_delay : time := 0 ps; + signal period_dv_high, period_dv_low : time := 0 ps; + signal cycle_jitter, period_jitter : time := 0 ps; + + signal clkin_window, clkfb_window : std_ulogic := '0'; + signal clkin_5050 : std_ulogic := '0'; + signal rst_reg : std_logic_vector(2 downto 0) := "000"; + + signal clkin_period_real0_temp : time := 0 ps; + signal ps_lock_temp : std_ulogic := '0'; + + signal clk0_temp : std_ulogic := '0'; + signal clk2X_temp : std_ulogic := '0'; + + signal no_stop : boolean := false; + +begin + INITPROC : process + begin + detect_resolution + (model_name => "CLKDLLHF" + ); + + if (CLKDV_DIVIDE = 1.5) then + divide_type <= 3; + elsif (CLKDV_DIVIDE = 2.0) then + divide_type <= 4; + elsif (CLKDV_DIVIDE = 2.5) then + divide_type <= 5; + elsif (CLKDV_DIVIDE = 3.0) then + divide_type <= 6; + elsif (CLKDV_DIVIDE = 4.0) then + divide_type <= 8; + elsif (CLKDV_DIVIDE = 5.0) then + divide_type <= 10; + elsif (CLKDV_DIVIDE = 8.0) then + divide_type <= 16; + elsif (CLKDV_DIVIDE = 16.0) then + divide_type <= 32; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLKDV_DIVIDE", + EntityName => "CLKDLLHF", + GenericValue => CLKDV_DIVIDE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + clkfb_type <= 1; + + period_jitter <= SIM_CLKIN_PERIOD_JITTER; + cycle_jitter <= SIM_CLKIN_CYCLE_JITTER; + + case DUTY_CYCLE_CORRECTION is + when false => clk1x_type <= 0; + when true => clk1x_type <= 1; + when others => + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "DUTY_CYCLE_CORRECTION", + EntityName => "CLKDLLHF", + GenericValue => DUTY_CYCLE_CORRECTION, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end case; + + case STARTUP_WAIT is + when false => null; + when true => null; + when others => + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "STARTUP_WAIT", + EntityName => "CLKDLLHF", + GenericValue => STARTUP_WAIT, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end case; + wait; + end process INITPROC; + +-- +-- input wire delays +-- + + CLKIN_ipd<= CLKIN; + CLKFB_ipd <= CLKFB; + RST_ipd <= RST; + + + i_max_clkin : clkdllhf_maximum_period_check + generic map ( + clock_name => "CLKIN", + maximum_period => MAXPERCLKIN) + + port map ( + clock => clkin_ipd, + rst => rst_ipd); + + assign_clkin_ps : process + begin + if (rst_ipd = '0') then + clkin_ps <= clkin_ipd; + elsif (rst_ipd = '1') then + clkin_ps <= '0'; + wait until (falling_edge(rst_reg(2))); + end if; + wait on clkin_ipd, rst_ipd; + end process assign_clkin_ps; + + clkin_fb0 <= transport (clkin_ps and lock_fb) after period_ps/4; + clkin_fb1 <= transport clkin_fb0 after period_ps/4; + clkin_fb2 <= transport clkin_fb1 after period_ps/4; + clkin_fb <= transport clkin_fb2 after period_ps/4; + + determine_period_ps : process + variable clkin_ps_edge_previous : time := 0 ps; + variable clkin_ps_edge_current : time := 0 ps; + begin + if (rst_ipd'event) then + clkin_ps_edge_previous := 0 ps; + clkin_ps_edge_current := 0 ps; + period_ps <= 0 ps; + else + if (rising_edge(clkin_ps)) then + clkin_ps_edge_previous := clkin_ps_edge_current; + clkin_ps_edge_current := NOW; + wait for 0 ps; + if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then + period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; + elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then + period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; + end if; + end if; + end if; + wait on clkin_ps, rst_ipd; + end process determine_period_ps; + + assign_lock_fb : process + begin + if (rising_edge(clkin_ps)) then + lock_fb <= lock_period; + end if; + wait on clkin_ps; + end process assign_lock_fb; + + calculate_clkout_delay : process + begin + if (rst_ipd'event) then + clkout_delay <= 0 ps; + elsif (period'event or fb_delay'event) then + clkout_delay <= period - fb_delay; + end if; + wait on period, fb_delay, rst_ipd; + end process calculate_clkout_delay; + +-- +--generate master reset signal +-- + + gen_master_rst : process + begin + if (rising_edge(clkin_ipd)) then + rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_ipd; + rst_reg(1) <= rst_reg(0) and rst_ipd; + rst_reg(0) <= rst_ipd; + end if; + wait on clkin_ipd; + end process gen_master_rst; + + check_rst_width : process + variable Message : line; + variable rst_tmp1, rst_tmp2 : time := 0 ps; + begin + if ((rising_edge(rst_ipd)) or (falling_edge(rst_ipd))) then + if (rst_ipd = '1') then + rst_tmp1 := NOW; + elsif (rst_ipd = '1') then + rst_tmp2 := NOW - rst_tmp1; + end if; + if ((rst_tmp2 < 2000 ps) and (rst_tmp2 /= 0 ps)) then + Write ( Message, string'(" Error : RST ")); + Write ( Message, string'(" must be asserted atleast for 2 ns. ")); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + end if; + wait on rst_ipd; + end process check_rst_width; + +-- +--determine clock period +-- + determine_clock_period : process + variable clkin_edge_previous : time := 0 ps; + variable clkin_edge_current : time := 0 ps; + begin + if (rst_ipd'event) then + clkin_period_real(0) <= 0 ps; + clkin_period_real(1) <= 0 ps; + clkin_period_real(2) <= 0 ps; + elsif (rising_edge(clkin_ps)) then + clkin_edge_previous := clkin_edge_current; + clkin_edge_current := NOW; + clkin_period_real(2) <= clkin_period_real(1); + clkin_period_real(1) <= clkin_period_real(0); + if (clkin_edge_previous /= 0 ps) then + clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous; + end if; + end if; + if (no_stop'event) then + clkin_period_real(0) <= clkin_period_real0_temp; + end if; + wait on clkin_ps, no_stop, rst_ipd; + end process determine_clock_period; + + evaluate_clock_period : process + variable clock_stopped : std_ulogic := '1'; + variable Message : line; + begin + if (rst_ipd'event) then + lock_period <= '0'; + clock_stopped := '1'; + clkin_period_real0_temp <= 0 ps; + else + if (falling_edge(clkin_ps)) then + if (lock_period = '0') then + if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then + lock_period <= '1'; + period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3; + period <= clkin_period_real(0); + end if; + elsif (lock_period = '1') then + if (100000000 ps < clkin_period_real(0)/1000) then + Write ( Message, string'(" Error : CLKIN stopped toggling ")); + Write ( Message, string'(" exceeds ")); + Write ( Message, string'(" 10000 ")); + Write ( Message, string'(" Current CLKIN Period = ")); + Write ( Message, string'(" clkin_period(0) / 10000.0 ")); + Write ( Message, string'(" ns ")); + assert false report Message.all severity warning; + DEALLOCATE (Message); + lock_period <= '0'; + wait until (falling_edge(rst_reg(2))); + elsif ((period_orig * 2 < clkin_period_real(0)) and (clock_stopped = '0')) then + clkin_period_real0_temp <= clkin_period_real(1); + no_stop <= not no_stop; + clock_stopped := '1'; + elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then + Write ( Message, string'(" Error : Input Clock Period Jitter ")); + Write ( Message, string'(" exceeds ")); + Write ( Message, period_jitter / 1000.0 ); + Write ( Message, string'(" Locked CLKIN Period = ")); + Write ( Message, period_orig / 1000.0 ); + Write ( Message, string'(" Current CLKIN Period = ")); + Write ( Message, clkin_period_real(0) / 1000.0 ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + lock_period <= '0'; + wait until (falling_edge(rst_reg(2))); + elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then + Write ( Message, string'(" Error : Input Clock Cycle Jitter ")); + Write ( Message, string'(" exceeds ")); + Write ( Message, cycle_jitter / 1000.0 ); + Write ( Message, string'(" Previous CLKIN Period = ")); + Write ( Message, clkin_period_real(1) / 1000.0 ); + Write ( Message, string'(" Current CLKIN Period = ")); + Write ( Message, clkin_period_real(0) / 1000.0 ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + lock_period <= '0'; + wait until (falling_edge(rst_reg(2))); + end if; + else + period <= clkin_period_real(0); + clock_stopped := '0'; + end if; + end if; + end if; + wait on clkin_ps, rst_ipd; + end process evaluate_clock_period; + + determine_clock_delay : process + variable delay_edge : time := 0 ps; + variable temp1 : integer := 0; + variable temp2 : integer := 0; + variable temp : integer := 0; + variable delay_edge_current : time := 0 ps; + begin + if (rst_ipd'event) then + fb_delay <= 0 ps; + fb_delay_found <= '0'; + else + if (rising_edge(lock_period)) then + if ((lock_period = '1') and (clkfb_type /= 0)) then + if (clkfb_type = 1) then + wait until ((rising_edge(clk0_temp)) or (rst_ipd'event)); + delay_edge := NOW; + elsif (clkfb_type = 2) then + wait until ((rising_edge(clk2x_temp)) or (rst_ipd'event)); + delay_edge := NOW; + end if; + wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event)); + temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps); + temp2 := (period_orig * 1)/ (1 ps); + temp := temp1 mod temp2; + fb_delay <= temp * 1 ps; + end if; + end if; + fb_delay_found <= '1'; + end if; + wait on lock_period, rst_ipd; + end process determine_clock_delay; +-- +-- determine feedback lock +-- + GEN_CLKFB_WINDOW : process + begin + if (rst_ipd'event) then + clkfb_window <= '0'; + else + if (rising_edge(CLKFB_ipd)) then + wait for 0 ps; + clkfb_window <= '1'; + wait for cycle_jitter; + clkfb_window <= '0'; + end if; + end if; + wait on clkfb_ipd, rst_ipd; + end process GEN_CLKFB_WINDOW; + + GEN_CLKIN_WINDOW : process + begin + if (rst_ipd'event) then + clkin_window <= '0'; + else + if (rising_edge(clkin_fb)) then + wait for 0 ps; + clkin_window <= '1'; + wait for cycle_jitter; + clkin_window <= '0'; + end if; + end if; + wait on clkin_fb, rst_ipd; + end process GEN_CLKIN_WINDOW; + + set_reset_lock_clkin : process + begin + if (rst_ipd'event) then + lock_clkin <= '0'; + else + if (rising_edge(clkin_fb)) then + wait for 1 ps; + if ((clkfb_window = '1') and (fb_delay_found = '1')) then + lock_clkin <= '1'; + else + lock_clkin <= '0'; + end if; + end if; + end if; + wait on clkin_fb, rst_ipd; + end process set_reset_lock_clkin; + + set_reset_lock_clkfb : process + begin + if (rst_ipd'event) then + lock_clkfb <= '0'; + else + if (rising_edge(clkfb_ipd)) then + wait for 1 ps; + if ((clkin_window = '1') and (fb_delay_found = '1')) then + lock_clkfb <= '1'; + else + lock_clkfb <= '0'; + end if; + end if; + end if; + wait on clkfb_ipd, rst_ipd; + end process set_reset_lock_clkfb; + + assign_lock_delay : process + begin + if (rst_ipd'event) then + lock_delay <= '0'; + else + if (falling_edge(clkin_fb)) then + lock_delay <= lock_clkin or lock_clkfb; + end if; + end if; + wait on clkin_fb, rst_ipd; + end process; + +-- +--generate lock signal +-- + + generate_lock : process + begin + if (rst_ipd'event) then + lock_out <= "00"; + locked_out <= '0'; + else + if (rising_edge(clkin_ps)) then + if (clkfb_type = 0) then + lock_out(0) <= lock_period; + else + lock_out(0) <= lock_period and lock_delay and lock_fb; + end if; + lock_out(1) <= lock_out(0); + locked_out <= lock_out(1); + + end if; + end if; + wait on clkin_ps, rst_ipd; + end process generate_lock; + +-- +--generate the clk1x_out +-- + + gen_clk1x : process + begin + if (rst_ipd'event) then + clkin_5050 <= '0'; + else + if (rising_edge(clkin_ps)) then + clkin_5050 <= '1'; + wait for (period/2); + clkin_5050 <= '0'; + end if; + end if; + wait on clkin_ps, rst_ipd; + end process gen_clk1x; + + clk0_out <= clkin_5050 when (clk1x_type = 1) else clkin_ps; + +-- +--generate the clkdv_out +-- + + determine_clkdv_period : process + begin + if (period'event) then + period_dv_high <= (period / 2) * (divide_type / 2); + period_dv_low <= (period / 2) * (divide_type / 2 + divide_type mod 2); + end if; + wait on period; + end process determine_clkdv_period; + + + gen_clkdv : process + begin + if (rising_edge(clkin_ps)) then + if (lock_out(0) = '1') then + clkdv_out <= '1'; + wait for (period_dv_high); + clkdv_out <= '0'; + wait for (period_dv_low); + clkdv_out <= '1'; + wait for (period_dv_high); + clkdv_out <= '0'; + wait for (period_dv_low - period/2); + end if; + end if; + wait on clkin_ps; + end process gen_clkdv; + + +-- +--generate all output signal +-- + schedule_outputs : process + begin + if (CLK0_out'event) then + CLK0 <= transport CLK0_out after clkout_delay; + clk0_temp <= transport CLK0_out after clkout_delay; + CLK180 <= transport clk0_out after (clkout_delay + period / 2); + end if; + + + if (clkdv_out'event) then + CLKDV <= transport clkdv_out after clkout_delay; + end if; + + LOCKED <= locked_out after 100 ps; + wait on clk0_out, clkdv_out, locked_out; + end process schedule_outputs; + +end CLKDLLHF_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/config.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / +-- /___/ /\ Filename : CONFIG.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:21 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CONFIG ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CONFIG is +end CONFIG; + +architecture CONFIG_V of CONFIG is +begin +end CONFIG_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/dcm.vhd,v 1.28.16.2 2008/03/18 22:25:55 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Digital Clock Manager +-- /___/ /\ Filename : DCM.vhd +-- \ \ / \ Timestamp : Fri Jun 18 10:57:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 05/11/05 - Add clkin alignment check control to remove the glitch when +-- clkin stopped. (CR207409). +-- 05/25/05 - Seperate clock_second_pos and neg to another process due to +-- wait caused unreset. Set fb_delay_found after fb_delay computed. +-- Enable clkfb_div after lock_fb high (CR 208771) +-- 06/03/05 - Use after instead wait for clk0_out(CR209283). +-- Update error message (CR 209076). +-- 07/06/05 - Add lock_fb_dly to alignment check. (CR210755). +-- Use counter to generate clkdv_out to align with clk0_out. (CR211465). +-- 07/25/05 - Set CLKIN_PERIOD default to 10.0ns to (CR 213190). +-- 08/30/05 - Change reset for CLK270, CLK180 (CR 213641). +-- 09/08/05 - Add positive edge trig to dcm_maximum_period_check_v. (CR 216828). +-- 12/22/05 - LOCKED = x when RST less than 3 clock cycles (CR 222795) +-- 02/28/06 - Remove 1 ps in clkfx_out block to support fs resolution (CR222390) +-- 09/22/06 - Add lock_period and lock_fb to clkfb_div block (CR418722). +-- 12/19/06 - Add clkfb_div_en for clkfb2x divider (CR431210). +-- 04/06/07 - Enable the clock out in clock low time after reset in model +-- clock_divide_by_2 (CR 437471). +-- 06/11/07 - Add SIM_MODE and fast unisim model (SLIB_M2.1) +-- 08/29/07 - Change delay of lock_fb_dly to 0.75*period, same as verilog (CR447628). +-- 02/21/08 - Align clk2x to both clk0 pos and neg edges. (CR467858). +-- 03/01/08 - Disable alignment of clkfb and clkin_fb check when ps_lock high (CR468893). +-- End Revision + + +----- dcm_clock_divide_by_2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity dcm_clock_divide_by_2 is + port( + clock_out : out std_ulogic := '0'; + + clock : in std_ulogic; + clock_type : in integer; + rst : in std_ulogic + ); +end dcm_clock_divide_by_2; + +architecture dcm_clock_divide_by_2_V of dcm_clock_divide_by_2 is + signal clock_div2 : std_ulogic := '0'; + signal rst_reg : std_logic_vector(2 downto 0); + signal clk_src : std_ulogic; +begin + + CLKIN_DIVIDER : process + begin + if (rising_edge(clock)) then + clock_div2 <= not clock_div2; + end if; + wait on clock; + end process CLKIN_DIVIDER; + + gen_reset : process + begin + if (rising_edge(clock)) then + rst_reg(0) <= rst; + rst_reg(1) <= rst_reg(0) and rst; + rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst; + end if; + wait on clock; + end process gen_reset; + + clk_src <= clock_div2 when (clock_type = 1) else clock; + + assign_clkout : process + begin + if (rst = '0') then + clock_out <= clk_src; + elsif (rst = '1') then + clock_out <= '0'; + wait until falling_edge(rst_reg(2)); + if (clk_src = '1') then + wait until falling_edge(clk_src); + end if; + end if; + wait on clk_src, rst, rst_reg; + end process assign_clkout; +end dcm_clock_divide_by_2_V; + +----- dcm_maximum_period_check ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library STD; +use STD.TEXTIO.all; + +entity dcm_maximum_period_check is + generic ( +-- InstancePath : string := "*"; + + clock_name : string := ""; + maximum_period : time); + port( + clock : in std_ulogic; + rst : in std_ulogic + ); +end dcm_maximum_period_check; + +architecture dcm_maximum_period_check_V of dcm_maximum_period_check is +begin + + MAX_PERIOD_CHECKER : process + variable clock_edge_previous : time := 0 ps; + variable clock_edge_current : time := 0 ps; + variable clock_period : time := 0 ps; + variable Message : line; + begin + + if (rising_edge(clock)) then + clock_edge_previous := clock_edge_current; + clock_edge_current := NOW; + + if (clock_edge_previous > 0 ps) then + clock_period := clock_edge_current - clock_edge_previous; + end if; + + if (clock_period > maximum_period and rst = '0') then + Write ( Message, string'(" Warning : Input Clock Period of ")); + Write ( Message, clock_period ); + Write ( Message, string'(" on the ") ); + Write ( Message, clock_name ); + Write ( Message, string'(" port ") ); + Write ( Message, string'(" of DCM instance ") ); + Write ( Message, string'(" exceeds allowed value of ") ); + Write ( Message, maximum_period ); + Write ( Message, string'(" at simulation time ") ); + Write ( Message, clock_edge_current ); + Write ( Message, '.' & LF ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + end if; + end if; + wait on clock; + end process MAX_PERIOD_CHECKER; +end dcm_maximum_period_check_V; + +----- dcm_clock_lost ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity dcm_clock_lost is + port( + lost : out std_ulogic := '0'; + + clock : in std_ulogic; + enable : in boolean := false; + rst : in std_ulogic + ); +end dcm_clock_lost; + +architecture dcm_clock_lost_V of dcm_clock_lost is + signal period : time := 0 ps; + signal lost_r : std_ulogic := '0'; + signal lost_f : std_ulogic := '0'; + signal lost_sig : std_ulogic := '0'; + signal clock_negedge, clock_posedge : std_ulogic; + signal clock_low, clock_high : std_ulogic := '0'; + signal clock_second_pos, clock_second_neg : std_ulogic := '0'; +begin + determine_period : process + variable clock_edge_previous : time := 0 ps; + variable clock_edge_current : time := 0 ps; + begin + if (rst = '1') then + period <= 0 ps; + elsif (rising_edge(clock)) then + clock_edge_previous := clock_edge_current; + clock_edge_current := NOW; + if (period /= 0 ps and ((clock_edge_current - clock_edge_previous) <= (1.5 * period))) then + period <= NOW - clock_edge_previous; + elsif (period /= 0 ps and ((NOW - clock_edge_previous) > (1.5 * period))) then + period <= 0 ps; + elsif ((period = 0 ps) and (clock_edge_previous /= 0 ps) and (clock_second_pos = '1')) then + period <= NOW - clock_edge_previous; + end if; + end if; + wait on clock, rst; + end process determine_period; + + CLOCK_LOST_CHECKER : process + + begin + if (rst = '1') then + clock_low <= '0'; + clock_high <= '0'; + clock_posedge <= '0'; + clock_negedge <= '0'; + else + if (rising_edge(clock)) then + clock_low <= '0'; + clock_high <= '1'; + clock_posedge <= '0'; + clock_negedge <= '1'; + end if; + + if (falling_edge(clock)) then + clock_high <= '0'; + clock_low <= '1'; + clock_posedge <= '1'; + clock_negedge <= '0'; + end if; + end if; + + wait on clock, rst; + end process CLOCK_LOST_CHECKER; + + CLOCK_SECOND_P : process + begin + if (rst = '1') then + clock_second_pos <= '0'; + clock_second_neg <= '0'; + else + if (rising_edge(clock)) then + clock_second_pos <= '1'; + end if; + if (falling_edge(clock)) then + clock_second_neg <= '1'; + end if; + end if; + wait on clock, rst; + end process CLOCK_SECOND_P; + + SET_RESET_LOST_R : process + begin + if (rst = '1') then + lost_r <= '0'; + else + if ((enable = true) and (clock_second_pos = '1'))then + if (rising_edge(clock)) then + wait for 1 ps; + if (period /= 0 ps) then + lost_r <= '0'; + end if; + wait for (period * (9.1/10.0)); + if ((clock_low /= '1') and (clock_posedge /= '1') and (rst = '0')) then + lost_r <= '1'; + end if; + end if; + end if; + end if; + wait on clock, rst; + end process SET_RESET_LOST_R; + + SET_RESET_LOST_F : process + begin + if (rst = '1') then + lost_f <= '0'; + else + if ((enable = true) and (clock_second_neg = '1'))then + if (falling_edge(clock)) then + if (period /= 0 ps) then + lost_f <= '0'; + end if; + wait for (period * (9.1/10.0)); + if ((clock_high /= '1') and (clock_negedge /= '1') and (rst = '0')) then + lost_f <= '1'; + end if; + end if; + end if; + end if; + wait on clock, rst; + end process SET_RESET_LOST_F; + + assign_lost : process + begin + if (enable = true) then + if (lost_r'event) then + lost <= lost_r; + end if; + if (lost_f'event) then + lost <= lost_f; + end if; + end if; + wait on lost_r, lost_f; + end process assign_lost; +end dcm_clock_lost_V; + + +----- CELL DCM ----- +library IEEE; +use IEEE.std_logic_1164.all; + + + + + +library STD; +use STD.TEXTIO.all; + +library unisim; +use unisim.VPKG.all; + +entity DCM is + generic ( + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := false; + CLKIN_PERIOD : real := 10.0; --non-simulatable + CLKOUT_PHASE_SHIFT : string := "NONE"; + CLK_FEEDBACK : string := "1X"; + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; --non-simulatable + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DSS_MODE : string := "NONE"; --non-simulatable + DUTY_CYCLE_CORRECTION : boolean := true; + FACTORY_JF : bit_vector := X"C080"; --non-simulatable + PHASE_SHIFT : integer := 0; + SIM_MODE : string := "SAFE"; + STARTUP_WAIT : boolean := false --non-simulatable + ); + + port ( + CLK0 : out std_ulogic := '0'; + CLK180 : out std_ulogic := '0'; + CLK270 : out std_ulogic := '0'; + CLK2X : out std_ulogic := '0'; + CLK2X180 : out std_ulogic := '0'; + CLK90 : out std_ulogic := '0'; + CLKDV : out std_ulogic := '0'; + CLKFX : out std_ulogic := '0'; + CLKFX180 : out std_ulogic := '0'; + LOCKED : out std_ulogic := '0'; + PSDONE : out std_ulogic := '0'; + STATUS : out std_logic_vector(7 downto 0) := "00000000"; + + CLKFB : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0'; + DSSEN : in std_ulogic := '0'; + PSCLK : in std_ulogic := '0'; + PSEN : in std_ulogic := '0'; + PSINCDEC : in std_ulogic := '0'; + RST : in std_ulogic := '0' + ); + +end DCM; + +architecture DCM_V of DCM is + + component dcm_clock_divide_by_2 + port( + clock_out : out std_ulogic; + + clock : in std_ulogic; + clock_type : in integer; + rst : in std_ulogic + ); + end component; + + component dcm_maximum_period_check + generic ( +-- InstancePath : string := "*"; + + clock_name : string := ""; + maximum_period : time); + port( + clock : in std_ulogic; + rst : in std_ulogic + ); + end component; + + component dcm_clock_lost + port( + lost : out std_ulogic; + + clock : in std_ulogic; + enable : in boolean := false; + rst : in std_ulogic + ); + end component; + + signal CLKFB_ipd, CLKIN_ipd, DSSEN_ipd : std_ulogic; + signal PSCLK_ipd, PSEN_ipd, PSINCDEC_ipd, RST_ipd : std_ulogic; + signal PSCLK_dly ,PSEN_dly, PSINCDEC_dly : std_ulogic := '0'; + + signal clk0_out : std_ulogic; + signal clk2x_out, clkdv_out : std_ulogic := '0'; + signal clkfx_out, locked_out, psdone_out, ps_overflow_out, ps_lock : std_ulogic := '0'; + signal clk0_out_o : std_ulogic; + signal clk2x_out_o, clkdv_out_o : std_ulogic := '0'; + signal clkfx_out_o : std_ulogic := '0'; + signal clk180_out_o, clk90_out_o, clk270_out_o, clk2x180_out_o : std_ulogic := '0'; + signal clkfx180_out_o : std_ulogic := '0'; + signal clk0_out_ofs : std_ulogic; + signal clk2x_out_ofs, clkdv_out_ofs : std_ulogic := '0'; + signal clkfx_out_ofs : std_ulogic := '0'; + signal clk180_out_ofs, clk90_out_ofs, clk270_out_ofs, clk2x180_out_ofs : std_ulogic := '0'; + signal clkfx180_out_ofs : std_ulogic := '0'; + signal locked_out_out : std_ulogic := '0'; + signal LOCKED_sig : std_ulogic := '0'; + signal LOCKED_sig_fs : std_ulogic := '0'; + + + signal clkdv_cnt : integer := 0; + signal clkfb_type : integer; + signal divide_type : integer; + signal clkin_type : integer; + signal ps_type : integer; + signal deskew_adjust_mode : integer; + signal dfs_mode_type : integer; + signal dll_mode_type : integer; + signal clk1x_type : integer; + + + signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0'; + signal lock_out : std_logic_vector(1 downto 0) := "00"; + signal lock_out1_neg : std_ulogic := '0'; + + signal lock_fb : std_ulogic := '0'; + signal lock_fb_dly : std_ulogic := '0'; + signal lock_fb_dly_tmp : std_ulogic := '0'; + signal fb_delay_found : std_ulogic := '0'; + + signal clkin_div : std_ulogic; + signal clkin_ps : std_ulogic; + signal clkin_fb : std_ulogic; + + + signal ps_delay : time := 0 ps; + type real_array_usr is array (2 downto 0) of time; + signal clkin_period_real : real_array_usr := (0.000 ns, 0.000 ns, 0.000 ns); + signal period : time := 0 ps; + signal period_div : time := 0 ps; + signal period_orig : time := 0 ps; + signal period_ps : time := 0 ps; + signal clkout_delay : time := 0 ps; + signal fb_delay : time := 0 ps; + signal period_fx, remain_fx : time := 0 ps; + signal period_dv_high, period_dv_low : time := 0 ps; + signal cycle_jitter, period_jitter : time := 0 ps; + + signal clkin_window, clkfb_window : std_ulogic := '0'; + signal rst_reg : std_logic_vector(2 downto 0) := "000"; + signal rst_flag : std_ulogic := '0'; + signal numerator, denominator, gcd : integer := 1; + + signal clkin_lost_out : std_ulogic := '0'; + signal clkfx_lost_out : std_ulogic := '0'; + + signal remain_fx_temp : integer := 0; + + signal clkin_period_real0_temp : time := 0 ps; + signal ps_lock_reg : std_ulogic := '0'; + + signal clk0_sig : std_ulogic := '0'; + signal clk2x_sig : std_ulogic := '0'; + + signal no_stop : boolean := false; + + signal clkfx180_en : std_ulogic := '0'; + + signal status_out : std_logic_vector(7 downto 0) := "00000000"; + signal status_out_fs : std_logic_vector(7 downto 0) := "00000000"; + + signal first_time_locked : boolean := false; + + signal en_status : boolean := false; + + signal ps_overflow_out_ext : std_ulogic := '0'; + signal clkin_lost_out_ext : std_ulogic := '0'; + signal clkfx_lost_out_ext : std_ulogic := '0'; + + signal clkfb_div : std_ulogic := '0'; + signal clkfb_div_en : std_ulogic := '0'; + signal clkfb_chk : std_ulogic := '0'; + + signal lock_period_dly : std_ulogic := '0'; + signal lock_period_pulse : std_ulogic := '0'; + + signal clock_stopped : std_ulogic := '1'; + + signal clkin_chkin, clkfb_chkin : std_ulogic := '0'; + signal chk_enable, chk_rst : std_ulogic := '0'; + + signal lock_ps : std_ulogic := '0'; + signal lock_ps_dly : std_ulogic := '0'; + + constant MAXPERCLKIN : time := 1000000 ps; + constant MAXPERPSCLK : time := 100000000 ps; + constant SIM_CLKIN_CYCLE_JITTER : time := 300 ps; + constant SIM_CLKIN_PERIOD_JITTER : time := 1000 ps; + signal CLK0_out_fs : std_ulogic := '0'; + signal CLK180_out_fs : std_ulogic := '0'; + signal CLK270_out_fs : std_ulogic := '0'; + signal CLK2X_out_fs : std_ulogic := '0'; + signal CLK2X180_out_fs : std_ulogic := '0'; + signal CLK90_out_fs : std_ulogic := '0'; + signal CLKFX180_out_fs : std_ulogic := '0'; + signal CLKFX_out_fs : std_ulogic := '0'; + signal CLKDV_out_fs : std_ulogic := '0'; + signal PSDONE_out_fs : std_ulogic := '0'; + signal LOCKED_out_fs : std_ulogic := '0'; + + signal pos_shift : std_logic_vector (2 downto 0) := "000"; + signal pos_shift_st : std_logic_vector (2 downto 0) := "000"; + signal neg_shift : std_logic_vector (2 downto 0) := "000"; + signal neg_shift_st : std_logic_vector (2 downto 0) := "000"; + signal clkin_cnt : integer := 0; + signal old_clkin_cnt : integer := 0; + + signal align : std_logic := '0'; + signal clkin_divide : std_logic := '0'; + signal fbsync : std_logic := '0'; + signal clkin_error : std_logic := '0'; + signal period_updated : std_logic := '0'; + signal clkin_cnt_en : std_logic := '0'; + + signal clk_period : delay_length; + signal clkfx_period : delay_length; + signal shift_ammount : delay_length; + signal clkdv_period : delay_length; + signal start_time, delay_time : delay_length; + signal clkfx_divide_real, clkfx_multiply_real, phase_shift_real : real; + signal rst_tmp, rst_done_fx, rst_done_dv : std_logic := '0'; + signal sim_mode_type : std_logic := '0'; + +begin + sim_mode_type <= '1' when (SIM_MODE="FAST") else '0'; + CLK0 <= CLK0_out_ofs when sim_mode_type = '1' else CLK0_out_o; + CLK180 <= CLK180_out_ofs when sim_mode_type = '1' else CLK180_out_o; + CLK270 <= CLK270_out_ofs when sim_mode_type = '1' else CLK270_out_o; + CLK2X <= CLK2X_out_ofs when sim_mode_type = '1' else CLK2X_out_o; + CLK2X180 <= CLK2X180_out_ofs when sim_mode_type = '1' else CLK2X180_out_o; + CLK90 <= CLK90_out_ofs when sim_mode_type = '1' else CLK90_out_o; + CLKDV <= CLKDV_out_ofs when sim_mode_type = '1' else CLKDV_out_o; + CLKFX <= CLKFX_out_ofs when sim_mode_type = '1' else CLKFX_out_o; + CLKFX180 <= CLKFX180_out_ofs when sim_mode_type = '1' else CLKFX180_out_o; + STATUS <= status_out_fs when sim_mode_type = '1' else status_out; + LOCKED <= LOCKED_sig_fs after 100 ps when sim_mode_type = '1' else LOCKED_sig after 100 ps; + PSDONE <= PSDONE_out_fs when sim_mode_type = '1' else PSDONE_out; + LOCKED_sig <= LOCKED_sig_fs when sim_mode_type = '1' else locked_out_out; + + INITPROC : process + begin + detect_resolution + (model_name => "DCM" + ); + if (CLKDV_DIVIDE = 1.5) then + divide_type <= 3; + elsif (CLKDV_DIVIDE = 2.0) then + divide_type <= 4; + elsif (CLKDV_DIVIDE = 2.5) then + divide_type <= 5; + elsif (CLKDV_DIVIDE = 3.0) then + divide_type <= 6; + elsif (CLKDV_DIVIDE = 3.5) then + divide_type <= 7; + elsif (CLKDV_DIVIDE = 4.0) then + divide_type <= 8; + elsif (CLKDV_DIVIDE = 4.5) then + divide_type <= 9; + elsif (CLKDV_DIVIDE = 5.0) then + divide_type <= 10; + elsif (CLKDV_DIVIDE = 5.5) then + divide_type <= 11; + elsif (CLKDV_DIVIDE = 6.0) then + divide_type <= 12; + elsif (CLKDV_DIVIDE = 6.5) then + divide_type <= 13; + elsif (CLKDV_DIVIDE = 7.0) then + divide_type <= 14; + elsif (CLKDV_DIVIDE = 7.5) then + divide_type <= 15; + elsif (CLKDV_DIVIDE = 8.0) then + divide_type <= 16; + elsif (CLKDV_DIVIDE = 9.0) then + divide_type <= 18; + elsif (CLKDV_DIVIDE = 10.0) then + divide_type <= 20; + elsif (CLKDV_DIVIDE = 11.0) then + divide_type <= 22; + elsif (CLKDV_DIVIDE = 12.0) then + divide_type <= 24; + elsif (CLKDV_DIVIDE = 13.0) then + divide_type <= 26; + elsif (CLKDV_DIVIDE = 14.0) then + divide_type <= 28; + elsif (CLKDV_DIVIDE = 15.0) then + divide_type <= 30; + elsif (CLKDV_DIVIDE = 16.0) then + divide_type <= 32; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLKDV_DIVIDE", + EntityName => "DCM", +-- InstanceName => InstancePath, + GenericValue => CLKDV_DIVIDE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if ((CLKFX_DIVIDE <= 0) or (32 < CLKFX_DIVIDE)) then + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLKFX_DIVIDE", + EntityName => "DCM", +-- InstanceName => InstancePath, + GenericValue => CLKFX_DIVIDE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are 1....32", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if ((CLKFX_MULTIPLY <= 1) or (32 < CLKFX_MULTIPLY)) then + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLKFX_MULTIPLY", + EntityName => "DCM", +-- InstanceName => InstancePath, + GenericValue => CLKFX_MULTIPLY, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are 2....32", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + case CLKIN_DIVIDE_BY_2 is + when false => clkin_type <= 0; + when true => clkin_type <= 1; + when others => + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLKIN_DIVIDE_BY_2", + EntityName => "DCM", +-- InstanceName => InstancePath, + GenericValue => CLKIN_DIVIDE_BY_2, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end case; + + + if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then + ps_type <= 0; + elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then + ps_type <= 1; + elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then + ps_type <= 2; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLKOUT_PHASE_SHIFT", + EntityName => "DCM", +-- InstanceName => InstancePath, + GenericValue => CLKOUT_PHASE_SHIFT, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are NONE, FIXED or VARIABLE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if ((CLK_FEEDBACK = "none") or (CLK_FEEDBACK = "NONE")) then + clkfb_type <= 0; + elsif ((CLK_FEEDBACK = "1x") or (CLK_FEEDBACK = "1X")) then + clkfb_type <= 1; + elsif ((CLK_FEEDBACK = "2x") or (CLK_FEEDBACK = "2X")) then + clkfb_type <= 2; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLK_FEEDBACK", + EntityName => "DCM", +-- InstanceName => InstancePath, + GenericValue => CLK_FEEDBACK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are NONE, 1X or 2X", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if ((DESKEW_ADJUST = "source_synchronous") or (DESKEW_ADJUST = "SOURCE_SYNCHRONOUS")) then + DESKEW_ADJUST_mode <= 8; + elsif ((DESKEW_ADJUST = "system_synchronous") or (DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS")) then + DESKEW_ADJUST_mode <= 11; + elsif ((DESKEW_ADJUST = "0")) then + DESKEW_ADJUST_mode <= 0; + elsif ((DESKEW_ADJUST = "1")) then + DESKEW_ADJUST_mode <= 1; + elsif ((DESKEW_ADJUST = "2")) then + DESKEW_ADJUST_mode <= 2; + elsif ((DESKEW_ADJUST = "3")) then + DESKEW_ADJUST_mode <= 3; + elsif ((DESKEW_ADJUST = "4")) then + DESKEW_ADJUST_mode <= 4; + elsif ((DESKEW_ADJUST = "5")) then + DESKEW_ADJUST_mode <= 5; + elsif ((DESKEW_ADJUST = "6")) then + DESKEW_ADJUST_mode <= 6; + elsif ((DESKEW_ADJUST = "7")) then + DESKEW_ADJUST_mode <= 7; + elsif ((DESKEW_ADJUST = "8")) then + DESKEW_ADJUST_mode <= 8; + elsif ((DESKEW_ADJUST = "9")) then + DESKEW_ADJUST_mode <= 9; + elsif ((DESKEW_ADJUST = "10")) then + DESKEW_ADJUST_mode <= 10; + elsif ((DESKEW_ADJUST = "11")) then + DESKEW_ADJUST_mode <= 11; + elsif ((DESKEW_ADJUST = "12")) then + DESKEW_ADJUST_mode <= 12; + elsif ((DESKEW_ADJUST = "13")) then + DESKEW_ADJUST_mode <= 13; + elsif ((DESKEW_ADJUST = "14")) then + DESKEW_ADJUST_mode <= 14; + elsif ((DESKEW_ADJUST = "15")) then + DESKEW_ADJUST_mode <= 15; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "DESKEW_ADJUST_MODE", + EntityName => "DCM", +-- InstanceName => InstancePath, + GenericValue => DESKEW_ADJUST_MODE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 1....15", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if ((DFS_FREQUENCY_MODE = "high") or (DFS_FREQUENCY_MODE = "HIGH")) then + dfs_mode_type <= 1; + elsif ((DFS_FREQUENCY_MODE = "low") or (DFS_FREQUENCY_MODE = "LOW")) then + dfs_mode_type <= 0; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "DFS_FREQUENCY_MODE", + EntityName => "DCM", +-- InstanceName => InstancePath, + GenericValue => DFS_FREQUENCY_MODE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if ((DLL_FREQUENCY_MODE = "high") or (DLL_FREQUENCY_MODE = "HIGH")) then + dll_mode_type <= 1; + elsif ((DLL_FREQUENCY_MODE = "low") or (DLL_FREQUENCY_MODE = "LOW")) then + dll_mode_type <= 0; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "DLL_FREQUENCY_MODE", + EntityName => "DCM", +-- InstanceName => InstancePath, + GenericValue => DLL_FREQUENCY_MODE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if ((DSS_MODE = "none") or (DSS_MODE = "NONE")) then + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "DSS_MODE", + EntityName => "DCM", +-- InstanceName => InstancePath, + GenericValue => DSS_MODE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are NONE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + case DUTY_CYCLE_CORRECTION is + when false => clk1x_type <= 0; + when true => clk1x_type <= 1; + when others => + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "DUTY_CYCLE_CORRECTION", + EntityName => "DCM", +-- InstanceName => InstancePath, + GenericValue => DUTY_CYCLE_CORRECTION, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end case; + + if ((PHASE_SHIFT < -255) or (PHASE_SHIFT > 255)) then + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "PHASE_SHIFT", + EntityName => "DCM", +-- InstanceName => InstancePath, + GenericValue => PHASE_SHIFT, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are -255 ... 255", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + period_jitter <= SIM_CLKIN_PERIOD_JITTER; + cycle_jitter <= SIM_CLKIN_CYCLE_JITTER; + + case STARTUP_WAIT is + when false => null; + when true => null; + when others => + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "STARTUP_WAIT", + EntityName => "DCM", +-- InstanceName => InstancePath, + GenericValue => STARTUP_WAIT, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end case; + +-- +-- fx parameters +-- + gcd <= 1; + for i in 2 to CLKFX_MULTIPLY loop + if (((CLKFX_MULTIPLY mod i) = 0) and ((CLKFX_DIVIDE mod i) = 0)) then + gcd <= i; + end if; + end loop; + numerator <= CLKFX_MULTIPLY / gcd; + denominator <= CLKFX_DIVIDE / gcd; + wait; + end process INITPROC; + +-- +-- input wire delays +-- + +safe_model : if (SIM_MODE = "SAFE") generate + + CLKFB_ipd <= CLKFB; + CLKIN_ipd <= CLKIN; + DSSEN_ipd <= DSSEN; + PSCLK_dly <= PSCLK; + PSEN_dly <= PSEN; + PSINCDEC_dly <= PSINCDEC; + RST_ipd <= RST; + + i_clock_divide_by_2 : dcm_clock_divide_by_2 + port map ( + clock => clkin_ipd, + clock_type => clkin_type, + rst => rst_ipd, + clock_out => clkin_div); + + i_max_clkin : dcm_maximum_period_check + generic map ( + clock_name => "CLKIN", + maximum_period => MAXPERCLKIN) + + port map ( + clock => clkin_ipd, + rst => rst_ipd); + + i_max_psclk : dcm_maximum_period_check + generic map ( + clock_name => "PSCLK", + maximum_period => MAXPERPSCLK) + + port map ( + clock => psclk_dly, + rst => rst_ipd); + + i_clkin_lost : dcm_clock_lost + port map ( + lost => clkin_lost_out, + clock => clkin_ipd, + enable => first_time_locked, + rst => rst_ipd + ); + + i_clkfx_lost : dcm_clock_lost + port map ( + lost => clkfx_lost_out, + clock => clkfx_out, + enable => first_time_locked, + rst => rst_ipd + ); + + clkin_ps <= transport clkin_div after ps_delay; + + clkin_fb <= transport (clkin_ps and lock_fb); + + detect_first_time_locked : process + begin + if (first_time_locked = false) then + if (rising_edge(locked_out)) then + first_time_locked <= true; + end if; + end if; + wait on locked_out; + end process detect_first_time_locked; + + set_reset_en_status : process + begin + if (rst_ipd = '1') then + en_status <= false; + elsif (rising_edge(Locked_sig)) then + en_status <= true; + end if; + wait on rst_ipd, Locked_sig; + end process set_reset_en_status; + + gen_clkfb_div_en: process + begin + if (rst_ipd = '1') then + clkfb_div_en <= '0'; + elsif (falling_edge(clkfb_ipd)) then + if (lock_fb_dly='1' and lock_period='1' and lock_fb = '1' and clkin_ps = '0') then + clkfb_div_en <= '1'; + end if; + end if; + wait on clkfb_ipd, rst_ipd; + end process gen_clkfb_div_en; + + gen_clkfb_div: process + begin + if (rst_ipd = '1') then + clkfb_div <= '0'; + elsif (rising_edge(clkfb_ipd)) then + if (clkfb_div_en='1') then + clkfb_div <= not clkfb_div; + end if; + end if; + wait on clkfb_ipd, rst_ipd; + end process gen_clkfb_div; + + determine_clkfb_chk: process + begin + if (clkfb_type = 2) then + clkfb_chk <= clkfb_div; + else + clkfb_chk <= clkfb_ipd and lock_fb_dly; + end if; + wait on clkfb_ipd, clkfb_div; + end process determine_clkfb_chk; + + set_reset_clkin_chkin : process + begin + if ((rising_edge(clkin_fb)) or (rising_edge(chk_rst))) then + if (chk_rst = '1') then + clkin_chkin <= '0'; + else + clkin_chkin <= '1'; + end if; + end if; + wait on clkin_fb, chk_rst; + end process set_reset_clkin_chkin; + + set_reset_clkfb_chkin : process + begin + if ((rising_edge(clkfb_chk)) or (rising_edge(chk_rst))) then + if (chk_rst = '1') then + clkfb_chkin <= '0'; + else + clkfb_chkin <= '1'; + end if; + end if; + wait on clkfb_chk, chk_rst; + end process set_reset_clkfb_chkin; + + + chk_rst <= '1' when ((rst_ipd = '1') or (clock_stopped = '1')) else '0'; + + chk_enable <= '1' when ((clkin_chkin = '1') and (clkfb_chkin = '1') and (lock_ps = '1') and (lock_fb_dly = '1') and (lock_fb = '1')) else '0'; + + control_status_bits: process + begin + if ((rst_ipd = '1') or (en_status = false)) then + ps_overflow_out_ext <= '0'; + clkin_lost_out_ext <= '0'; + clkfx_lost_out_ext <= '0'; + else + ps_overflow_out_ext <= ps_overflow_out; + clkin_lost_out_ext <= clkin_lost_out; + clkfx_lost_out_ext <= clkfx_lost_out; + end if; + wait on clkfx_lost_out, clkin_lost_out, en_status, ps_overflow_out, rst_ipd; + end process control_status_bits; + + determine_period_div : process + variable clkin_div_edge_previous : time := 0 ps; + variable clkin_div_edge_current : time := 0 ps; + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + clkin_div_edge_previous := 0 ps; + clkin_div_edge_current := 0 ps; + period_div <= 0 ps; + else + if (rising_edge(clkin_div)) then + clkin_div_edge_previous := clkin_div_edge_current; + clkin_div_edge_current := NOW; + if ((clkin_div_edge_current - clkin_div_edge_previous) <= (1.5 * period_div)) then + period_div <= clkin_div_edge_current - clkin_div_edge_previous; + elsif ((period_div = 0 ps) and (clkin_div_edge_previous /= 0 ps)) then + period_div <= clkin_div_edge_current - clkin_div_edge_previous; + end if; + end if; + end if; + wait on clkin_div, rst_ipd; + end process determine_period_div; + + determine_period_ps : process + variable clkin_ps_edge_previous : time := 0 ps; + variable clkin_ps_edge_current : time := 0 ps; + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + clkin_ps_edge_previous := 0 ps; + clkin_ps_edge_current := 0 ps; + period_ps <= 0 ps; + else + if (rising_edge(clkin_ps)) then + clkin_ps_edge_previous := clkin_ps_edge_current; + clkin_ps_edge_current := NOW; + wait for 0 ps; + if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then + period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; + elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then + period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; + end if; + end if; + end if; + wait on clkin_ps, rst_ipd; + end process determine_period_ps; + + assign_lock_ps_fb : process + + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + lock_fb <= '0'; + lock_ps <= '0'; + lock_ps_dly <= '0'; + lock_fb_dly <= '0'; + lock_fb_dly_tmp <= '0'; + else + if (rising_edge(clkin_ps)) then + lock_ps <= lock_period; + lock_ps_dly <= lock_ps; + lock_fb <= lock_ps_dly; + lock_fb_dly_tmp <= lock_fb; + end if; + if (falling_edge(clkin_ps)) then +-- lock_fb_dly <= lock_fb_dly_tmp after (period/4); + lock_fb_dly <= lock_fb_dly_tmp after (period * 0.75); + end if; + end if; + wait on clkin_ps, rst_ipd; + end process assign_lock_ps_fb; + + calculate_clkout_delay : process + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + clkout_delay <= 0 ps; + elsif (fb_delay = 0 ps) then + clkout_delay <= 0 ps; + elsif (period'event or fb_delay'event) then + clkout_delay <= period - fb_delay; + end if; + wait on period, fb_delay, rst_ipd; + end process calculate_clkout_delay; + +-- +--generate master reset signal +-- + + gen_master_rst : process + begin + if (rising_edge(clkin_ipd)) then + rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_ipd; + rst_reg(1) <= rst_reg(0) and rst_ipd; + rst_reg(0) <= rst_ipd; + end if; + wait on clkin_ipd; + end process gen_master_rst; + + check_rst_width : process + variable Message : line; + begin + if (rst_ipd ='1') then + rst_flag <= '0'; + end if; + if (falling_edge(rst_ipd)) then + if ((rst_reg(2) and rst_reg(1) and rst_reg(0)) = '0') then + rst_flag <= '1'; + Write ( Message, string'(" Input Error : RST on DCM ")); + Write ( Message, string'(" must be asserted for 3 CLKIN clock cycles. ")); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + end if; + + wait on rst_ipd; + end process check_rst_width; + +-- +--phase shift parameters +-- + + determine_phase_shift : process + variable Message : line; + variable FINE_SHIFT_RANGE : time; + variable first_time : boolean := true; + variable ps_in : integer; + begin + if (first_time = true) then + if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then + ps_in := 256; + elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then + ps_in := 256 + PHASE_SHIFT; + elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then + ps_in := 256 + PHASE_SHIFT; + end if; + first_time := false; + end if; + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then + ps_in := 256; + elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then + ps_in := 256 + PHASE_SHIFT; + elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then + ps_in := 256 + PHASE_SHIFT; + else + end if; + ps_lock <= '0'; + ps_overflow_out <= '0'; + ps_delay <= 0 ps; + else + if (rising_edge (lock_period)) then + if (ps_type = 1) then + FINE_SHIFT_RANGE := 10000 ps; + elsif (ps_type = 2) then + FINE_SHIFT_RANGE := 5000 ps; + end if; + if (PHASE_SHIFT > 0) then + if (((ps_in * period_orig) / 256) > (period_orig + FINE_SHIFT_RANGE)) then + Write ( Message, string'(" Function Error : ")); +-- Write ( Message, Instancepath ); + Write ( Message, string'(" Requested Phase Shift = ")); + + Write ( Message, string'(" PHASE_SHIFT * PERIOD/256 = ")); + Write ( Message, PHASE_SHIFT); + Write ( Message, string'(" * ")); + Write ( Message, period_orig / 256); + Write ( Message, string'(" = ")); + Write ( Message, (PHASE_SHIFT) * period_orig / 256 ); + Write ( Message, string'(" This exceeds the FINE_SHIFT_RANGE of ")); + Write ( Message, FINE_SHIFT_RANGE); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + elsif (PHASE_SHIFT < 0) then + if ((period_orig > FINE_SHIFT_RANGE) and ((ps_in * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) then + Write ( Message, string'(" Function Error : ")); +-- Write ( Message, Instancepath ); + Write ( Message, string'(" Requested Phase Shift = ")); + + Write ( Message, string'(" PHASE_SHIFT * PERIOD/256 = ")); + Write ( Message, PHASE_SHIFT); + Write ( Message, string'(" * ")); + Write ( Message, period_orig / 256); + Write ( Message, string'(" = ")); + Write ( Message, (-PHASE_SHIFT) * period_orig / 256 ); + Write ( Message, string'(" This exceeds the FINE_SHIFT_RANGE of ")); + Write ( Message, FINE_SHIFT_RANGE); + + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + end if; + end if; + if (rising_edge(lock_period_pulse)) then + ps_delay <= (ps_in * period_div / 256); + end if; + if (rising_edge(PSCLK_dly)) then + if (ps_type = 2) then + if (psen_dly = '1') then + if (ps_lock = '1') then + Write ( Message, string'(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift. ")); + assert false report Message.all severity warning; + DEALLOCATE (Message); + else + if (psincdec_dly = '1') then + if (ps_in = 511) then + ps_overflow_out <= '1'; + elsif (((ps_in + 1) * period_orig / 256) > period_orig + FINE_SHIFT_RANGE) then + ps_overflow_out <= '1'; + else + ps_in := ps_in + 1; + ps_delay <= (ps_in * period_div / 256); + ps_overflow_out <= '0'; + end if; + ps_lock <= '1'; + elsif (psincdec_dly = '0') then + if (ps_in = 1) then + ps_overflow_out <= '1'; + elsif ((period_orig > FINE_SHIFT_RANGE) and (((ps_in - 1) * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) then + ps_overflow_out <= '1'; + else + ps_in := ps_in - 1; + ps_delay <= (ps_in * period_div / 256); + ps_overflow_out <= '0'; + end if; + ps_lock <= '1'; + end if; + end if; + end if; + end if; + end if; + end if; + if (ps_lock_reg'event) then + ps_lock <= ps_lock_reg; + end if; + wait on lock_period, lock_period_pulse, psclk_dly, ps_lock_reg, rst_ipd; + end process determine_phase_shift; + + determine_psdone_out : process + begin + if (rising_edge(ps_lock)) then + ps_lock_reg <= '1'; + wait until (rising_edge(clkin_ps)); + wait until (rising_edge(psclk_dly)); + wait until (rising_edge(psclk_dly)); + wait until (rising_edge(psclk_dly)); + psdone_out <= '1'; + wait until (rising_edge(psclk_dly)); + psdone_out <= '0'; + ps_lock_reg <= '0'; + end if; + wait on ps_lock; + end process determine_psdone_out; + +-- +--determine clock period +-- + determine_clock_period : process + variable clkin_edge_previous : time := 0 ps; + variable clkin_edge_current : time := 0 ps; + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + clkin_period_real(0) <= 0 ps; + clkin_period_real(1) <= 0 ps; + clkin_period_real(2) <= 0 ps; + clkin_edge_previous := 0 ps; + clkin_edge_current := 0 ps; + elsif (rising_edge(clkin_div)) then + clkin_edge_previous := clkin_edge_current; + clkin_edge_current := NOW; + clkin_period_real(2) <= clkin_period_real(1); + clkin_period_real(1) <= clkin_period_real(0); + if (clkin_edge_previous /= 0 ps) then + clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous; + end if; + end if; + if (no_stop'event) then + clkin_period_real(0) <= clkin_period_real0_temp; + end if; + wait on clkin_div, no_stop, rst_ipd; + end process determine_clock_period; + + evaluate_clock_period : process + variable Message : line; + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + lock_period <= '0'; + clock_stopped <= '1'; + clkin_period_real0_temp <= 0 ps; + else + if (falling_edge(clkin_div)) then + if (lock_period = '0') then + if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then + lock_period <= '1'; + period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3; + period <= clkin_period_real(0); + end if; + elsif (lock_period = '1') then + if (100000000 ns < clkin_period_real(0)) then + Write ( Message, string'(" Warning : CLKIN stopped toggling on ")); +-- Write ( Message, Instancepath ); + Write ( Message, string'(" exceeds ")); + Write ( Message, string'(" 100 ms ")); + Write ( Message, string'(" Current CLKIN Period = ")); + Write ( Message, clkin_period_real(0)); + assert false report Message.all severity warning; + DEALLOCATE (Message); + lock_period <= '0'; + wait until (falling_edge(rst_reg(2))); + elsif ((period_orig * 2 < clkin_period_real(0)) and (clock_stopped = '0')) then + clkin_period_real0_temp <= clkin_period_real(1); + no_stop <= not no_stop; + clock_stopped <= '1'; + elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then + Write ( Message, string'(" Warning : DCM Input Clock Period Jitter ")); +-- Write ( Message, Instancepath ); + Write ( Message, string'(" exceeds ")); + Write ( Message, period_jitter ); + Write ( Message, string'(" Locked CLKIN Period = ")); + Write ( Message, period_orig ); + Write ( Message, string'(" Current CLKIN Period = ")); + Write ( Message, clkin_period_real(0) ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + lock_period <= '0'; + wait until (falling_edge(rst_reg(2))); + elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then + Write ( Message, string'(" Warning : DCM Input Clock Cycle Jitter ")); +-- Write ( Message, Instancepath ); + Write ( Message, string'(" exceeds ")); + Write ( Message, cycle_jitter ); + Write ( Message, string'(" Previous CLKIN Period = ")); + Write ( Message, clkin_period_real(1) ); + Write ( Message, string'(" Current CLKIN Period = ")); + Write ( Message, clkin_period_real(0) ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + lock_period <= '0'; + wait until (falling_edge(rst_reg(2))); + else + period <= clkin_period_real(0); + clock_stopped <= '0'; + end if; + end if; + end if; + end if; + wait on clkin_div, rst_ipd; + end process evaluate_clock_period; + + lock_period_dly <= transport lock_period after period/2; + + lock_period_pulse <= '1' when ((lock_period = '1') and (lock_period_dly = '0')) else '0'; + +-- +--determine clock delay +-- + + determine_clock_delay : process + variable delay_edge : time := 0 ps; + variable temp1 : integer := 0; + variable temp2 : integer := 0; + variable temp : integer := 0; + variable delay_edge_current : time := 0 ps; + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + fb_delay <= 0 ps; + fb_delay_found <= '0'; + else + if (rising_edge(lock_ps_dly)) then + if ((lock_period = '1') and (clkfb_type /= 0)) then + if (clkfb_type = 1) then + wait until ((rising_edge(clk0_sig)) or (rst_ipd'event)); + delay_edge := NOW; + elsif (clkfb_type = 2) then + wait until ((rising_edge(clk2x_sig)) or (rst_ipd'event)); + delay_edge := NOW; + end if; + wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event)); + temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps); + temp2 := (period_orig * 1)/ (1 ps); + temp := temp1 mod temp2; + fb_delay <= temp * 1 ps; + fb_delay_found <= '1'; + end if; + end if; + end if; + wait on lock_ps_dly, rst_ipd; + end process determine_clock_delay; +-- +-- determine feedback lock +-- + GEN_CLKFB_WINDOW : process + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + clkfb_window <= '0'; + else + if (rising_edge(clkfb_chk)) then + wait for 0 ps; + clkfb_window <= '1'; + wait for cycle_jitter; + clkfb_window <= '0'; + end if; + end if; + wait on clkfb_chk, rst_ipd; + end process GEN_CLKFB_WINDOW; + + GEN_CLKIN_WINDOW : process + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + clkin_window <= '0'; + else + if (rising_edge(clkin_fb)) then + wait for 0 ps; + clkin_window <= '1'; + wait for cycle_jitter; + clkin_window <= '0'; + end if; + end if; + wait on clkin_fb, rst_ipd; + end process GEN_CLKIN_WINDOW; + + set_reset_lock_clkin : process + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + lock_clkin <= '0'; + else + if (rising_edge(clkin_fb)) then + wait for 1 ps; + if (((clkfb_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1'))) then + lock_clkin <= '1'; + else + if (chk_enable = '1' and ps_lock = '0') then + lock_clkin <= '0'; + end if; + end if; + end if; + end if; + wait on clkin_fb, rst_ipd; + end process set_reset_lock_clkin; + + set_reset_lock_clkfb : process + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + lock_clkfb <= '0'; + else + if (rising_edge(clkfb_chk)) then + wait for 1 ps; + if (((clkin_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1')))then + lock_clkfb <= '1'; + else + if (chk_enable = '1' and ps_lock = '0') then + lock_clkfb <= '0'; + end if; + end if; + end if; + end if; + wait on clkfb_chk, rst_ipd; + end process set_reset_lock_clkfb; + + assign_lock_delay : process + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + lock_delay <= '0'; + else + if (falling_edge(clkin_fb)) then + lock_delay <= lock_clkin or lock_clkfb; + end if; + end if; + wait on clkin_fb, rst_ipd; + end process; + +-- +--generate lock signal +-- + + generate_lock : process(clkin_ps, rst_ipd) + begin + if (rst_ipd='1') then + lock_out <= "00"; + locked_out <= '0'; + lock_out1_neg <= '0'; + elsif (rising_edge(clkin_ps)) then + if (clkfb_type = 0) then + lock_out(0) <= lock_period; + else + lock_out(0) <= lock_period and lock_delay and lock_fb; + end if; + lock_out(1) <= lock_out(0); + locked_out <= lock_out(1); + elsif (falling_edge(clkin_ps)) then + lock_out1_neg <= lock_out(1); + end if; + end process generate_lock; + +-- +--generate the clk1x_out +-- + + gen_clk1x : process( clkin_ps, rst_ipd) + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + clk0_out <= '0'; + elsif (clkin_ps'event) then + if (clkin_ps = '1' ) then + if ((clk1x_type = 1) and (lock_out(0) = '1')) then + clk0_out <= '1', '0' after period/2; + else + clk0_out <= '1'; + end if; + else + if ((clkin_ps = '0') and ((((clk1x_type = 1) and (lock_out(0) = '1')) = false) or ((lock_out(0) = '1') and (lock_out(1) = '0')))) then + clk0_out <= '0'; + end if; + end if; + end if; + end process gen_clk1x; + +-- +--generate the clk2x_out +-- + + gen_clk2x : process + begin + if (rising_edge(rst_ipd) or (rst_ipd = '1')) then + clk2x_out <= '0'; + else + if (rising_edge(clkin_ps) or falling_edge(clkin_ps)) then + clk2x_out <= '1'; + wait for (period / 4); + clk2x_out <= '0'; + end if; + end if; + wait on clkin_ps, rst_ipd; + end process gen_clk2x; + +-- +--generate the clkdv_out +-- + + gen_clkdv : process (clkin_ps, rst_ipd) + begin + if (rst_ipd='1') then + clkdv_out <= '0'; + clkdv_cnt <= 0; + elsif ((rising_edge(clkin_ps)) or (falling_edge(clkin_ps))) then + if (lock_out1_neg = '1') then + if (clkdv_cnt >= divide_type -1) then + clkdv_cnt <= 0; + else + clkdv_cnt <= clkdv_cnt + 1; + end if; + + if (clkdv_cnt < divide_type /2) then + clkdv_out <= '1'; + else + if ( ((divide_type rem (2)) > 0) and (dll_mode_type = 0)) then + clkdv_out <= '0' after (period/4); + else + clkdv_out <= '0'; + end if; + end if; + end if; + end if; + end process; + +-- +-- generate fx output signal +-- + + calculate_period_fx : process + begin + if (lock_period = '1') then + period_fx <= (period * denominator) / (numerator * 2); + remain_fx <= (((period/1 ps) * denominator) mod (numerator * 2)) * 1 ps; + end if; + wait on lock_period, period, denominator, numerator; + end process calculate_period_fx; + + generate_clkfx : process + variable temp : integer; + begin + if (rst_ipd = '1') then + clkfx_out <= '0'; + elsif (clkin_lost_out_ext = '1') then + wait until (rising_edge(rst_ipd)); + clkfx_out <= '0'; + wait until (falling_edge(rst_reg(2))); + elsif (rising_edge(clkin_ps)) then + if (lock_out(1) = '1') then + clkfx_out <= '1'; + temp := numerator * 2 - 1 - 1; + for p in 0 to temp loop + wait for (period_fx); + clkfx_out <= not clkfx_out; + end loop; + if (period_fx > (period / 2)) then + wait for (period_fx - (period / 2)); + end if; + end if; + if (clkin_lost_out_ext = '1') then + wait until (rising_edge(rst_ipd)); + clkfx_out <= '0'; + wait until (falling_edge(rst_reg(2))); + end if; + end if; + wait on clkin_lost_out_ext, clkin_ps, rst_ipd, rst_reg(2); + end process generate_clkfx; + + +-- +--generate all output signal +-- + + schedule_p1_outputs : process + begin + if (CLK0_out'event) then + if (clkfb_type /= 0) then + CLK0_out_o <= transport CLK0_out after clkout_delay; + clk0_sig <= transport CLK0_out after clkout_delay; + end if; + if ((dll_mode_type = 0) and (clkfb_type /= 0)) then + CLK90_out_o <= transport clk0_out after (clkout_delay + period / 4); + end if; + end if; + + if (CLK0_out'event or rst_ipd'event)then + if (rst_ipd = '1') then + CLK180_out_o <= '0'; + CLK270_out_o <= '0'; + elsif (CLK0_out'event) then + if (clkfb_type /= 0) then + CLK180_out_o <= transport (not clk0_out) after clkout_delay; + end if; + if ((dll_mode_type = 0) and (clkfb_type /= 0)) then + CLK270_out_o <= transport (not clk0_out) after (clkout_delay + period/4); + end if; + end if; + end if; + + if (clk2x_out'event) then + if ((dll_mode_type = 0) and (clkfb_type /= 0)) then + CLK2X_out_o <= transport clk2x_out after clkout_delay; + clk2x_sig <= transport clk2x_out after clkout_delay; + end if; + end if; + + if (CLK2X_out'event or rst_ipd'event) then + if (rst_ipd = '1') then + CLK2X180_out_o <= '0'; + elsif (CLK2X_out'event) then + if ((dll_mode_type = 0) and (clkfb_type /= 0)) then + CLK2X180_out_o <= transport (not CLK2X_out) after clkout_delay; + end if; + end if; + end if; + + if (clkdv_out'event) then + if (clkfb_type /= 0) then + CLKDV_out_o <= transport clkdv_out after clkout_delay; + end if; + end if; + + if (clkfx_out'event or rst_ipd'event) then + if (rst_ipd = '1') then + CLKFX_out_o <= '0'; + elsif (clkfx_out'event) then + CLKFX_out_o <= transport clkfx_out after clkout_delay; + end if; + end if; + + if (clkfx_out'event or (rising_edge(rst_ipd)) or first_time_locked'event or locked_out'event) then + if ((rst_ipd = '1') or (not first_time_locked)) then + CLKFX180_out_o <= '0'; + else + CLKFX180_out_o <= transport (not clkfx_out) after clkout_delay; + end if; + end if; + + wait on clk0_out, clk2x_out, clkdv_out, clkfx_out, first_time_locked, locked_out, rst_ipd; + end process; + + assign_status_out : process + begin + if (rst_ipd = '1') then + status_out(0) <= '0'; + status_out(1) <= '0'; + status_out(2) <= '0'; + elsif (ps_overflow_out_ext'event) then + status_out(0) <= ps_overflow_out_ext; + elsif (clkin_lost_out_ext'event) then + status_out(1) <= clkin_lost_out_ext; + elsif (clkfx_lost_out_ext'event) then + status_out(2) <= clkfx_lost_out_ext; + end if; + wait on clkin_lost_out_ext, clkfx_lost_out_ext, ps_overflow_out_ext, rst_ipd; + end process assign_status_out; + + locked_out_out <= 'X' when rst_flag = '1' else locked_out; + + + + +end generate; + +fast_model : if (SIM_MODE = "FAST") generate + + + CONV_P : process + variable con_line : line; + variable tmpvalue : real; + variable skipspace : character; + begin + write (con_line, CLKFX_DIVIDE); + write (con_line, string'(".0 ")); + write (con_line, CLKFX_MULTIPLY); + write (con_line, string'(".0 ")); + write (con_line, PHASE_SHIFT); + + read (con_line, tmpvalue); + clkfx_divide_real <= tmpvalue; + read (con_line, skipspace); + read (con_line, tmpvalue); + clkfx_multiply_real <= tmpvalue; + read (con_line, skipspace); + read (con_line, tmpvalue); + phase_shift_real <= tmpvalue; + wait; + end process; + + CLK0_out_ofs <= CLK0_out_fs; + CLK180_out_ofs <= CLK180_out_fs; + CLK270_out_ofs <= CLK270_out_fs; + CLK2X_out_ofs <= CLK2X_out_fs; + CLK2X180_out_ofs <= CLK2X180_out_fs; + CLK90_out_ofs <= CLK90_out_fs; + CLKDV_out_ofs <= CLKDV_out_fs; + CLKFX_out_ofs <= CLKFX_out_fs; + CLKFX180_out_ofs <= CLKFX180_out_fs; + LOCKED_sig_fs <= LOCKED_out_fs; + + feedback_dcm : process + begin + fbsync <= '0'; + wait until (RST='0'); + wait until (period_updated='1'); + wait until (rising_edge(CLKFB)); + delay_time <= NOW - start_time; + wait until (rising_edge(CLKIN)); + wait for (((12*clk_period)-(delay_time))); + fbsync <= '1'; + wait until (RST='1'); + end process; + + main_dcm : process + variable clkin_time1, clkin_time2 : time; + variable period_clkin, tmpshift : delay_length; + variable rst_tmp1 : std_ulogic := '0'; + begin + pos_shift(0) <= '0'; + neg_shift(0) <= '0'; + align <= '0'; + LOCKED_out_fs <= '0'; + period_updated <= '0'; + clkin_cnt_en <= '0'; + CLK0_out_fs <= '0'; + CLK90_out_fs <= '0'; + CLK180_out_fs <= '0'; + CLK270_out_fs <= '0'; + CLK2X_out_fs <= '0'; + CLK2X180_out_fs <= '0'; + rst_tmp1 := '1'; + rst_tmp <= rst_tmp1; + wait until (RST='0' and rst_done_fx='1' and rst_done_dv='1'); + rst_tmp <= '0'; + wait until (rising_edge(CLKIN)); + clkin_time1 := NOW; + wait until (rising_edge(CLKIN)); + clkin_time2 := NOW; + period_clkin := clkin_time2 - clkin_time1; + + clk_period <= period_clkin*0.25; + clkfx_period <= (period_clkin*clkfx_divide_real)/(2.0*clkfx_multiply_real); + shift_ammount <= ((period_clkin)/256.0); + clkdv_period <= ((period_clkin*CLKDV_DIVIDE)/2.0); + + + wait until (rising_edge(CLKIN)); + period_updated <= '1'; + start_time <= NOW; + for i in 1 to 6 loop + CLK0_out_fs <= not CLK0_out_fs; + CLK2X_out_fs <= not CLK2X_out_fs; + wait for clk_period; + CLK2X_out_fs <= not CLK2X_out_fs; + wait for clk_period; + end loop; + for i in 1 to 6 loop + CLK0_out_fs <= not CLK0_out_fs; + CLK2X_out_fs <= not CLK2X_out_fs; + wait for clk_period; + CLK2X_out_fs <= not CLK2X_out_fs; + wait for clk_period; + end loop; + if (clkfb_type /= 0) then + if (fbsync='0') then + wait until (fbsync='1'); + end if; + end if; + if (ps_type /= 0) then + if (PHASE_SHIFT > 0) then + tmpshift := (period_clkin*phase_shift_real)/256.0; + wait for tmpshift; + elsif (PHASE_SHIFT < 0) then + tmpshift :=(period_clkin)-((period_clkin*phase_shift_real)/256.0); + wait for tmpshift; + end if; + end if; + align <= '1'; + CLK0_out_fs <= not CLK0_out_fs; + CLK2X_out_fs <= not CLK2X_out_fs; + wait for (clk_period); + CLK90_out_fs <= not CLK90_out_fs; + CLK2X_out_fs <= not CLK2X_out_fs; + CLK2X180_out_fs <= not CLK2X180_out_fs; + wait for (Clk_period); + for i in 1 to 7 loop + CLK0_out_fs <= not CLK0_out_fs; + CLK180_out_fs <= not CLK180_out_fs; + CLK2X_out_fs <= not CLK2X_out_fs; + CLK2X180_out_fs <= not CLK2X180_out_fs; + wait for (clk_period); + CLK90_out_fs <= not CLK90_out_fs; + CLK2X_out_fs <= not CLK2X_out_fs; + CLK2X180_out_fs <= not CLK2X180_out_fs; + CLK270_out_fs <= not CLK270_out_fs; + wait for (clk_period); + end loop; + LOCKED_out_fs <= '1'; + clkin_cnt_en <= '1'; + while (RST = '0') loop + CLK0_out_fs <= not CLK0_out_fs; + CLK180_out_fs <= not CLK180_out_fs; + CLK2X_out_fs <= not CLK2X_out_fs; + CLK2X180_out_fs <= not CLK2X180_out_fs; + wait for (clk_period); + CLK90_out_fs <= not CLK90_out_fs; + CLK270_out_fs <= not CLK270_out_fs; + CLK2X_out_fs <= not CLK2X_out_fs; + CLK2X180_out_fs <= not CLK2X180_out_fs; + wait for (clk_period); + CLK0_out_fs <= not CLK0_out_fs; + CLK180_out_fs <= not CLK180_out_fs; + CLK2X_out_fs <= not CLK2X_out_fs; + CLK2X180_out_fs <= not CLK2X180_out_fs; + wait for (clk_period); + CLK90_out_fs <= not CLK90_out_fs; + CLK270_out_fs <= not CLK270_out_fs; + CLK2X_out_fs <= not CLK2X_out_fs; + CLK2X180_out_fs <= not CLK2X180_out_fs; + if (pos_shift_st(0)='1' and pos_shift(0)='0') then + wait for ((clk_period)+shift_ammount); + pos_shift(0) <= '1'; + elsif (neg_shift_st(0)='1' and neg_shift(0)='0') then + wait for ((clk_period)-shift_ammount); + neg_shift(0) <= '1'; + else + if (pos_shift_st(0)='0') then + pos_shift(0) <= '0'; + end if; + if (neg_shift_st(0)='0') then + neg_shift(0) <= '0'; + end if; + wait for (clk_period); + end if; + if (clkin_error='1') then + wait until (RST = '1'); + end if; + end loop; + end process; + + clkfdcm : process + begin + pos_shift(1) <= '0'; + neg_shift(1) <= '0'; + CLKFX_out_fs <= '0'; + CLKFX180_out_fs <= '0'; + rst_done_fx <= '1'; +-- wait until (RST='0'); + wait until (rst_tmp = '0'); + wait until (LOCKED_out_fs='1'); + rst_done_fx <= '0'; + CLKFX_out_fs <= '1'; + CLKFX180_out_fs <= '0'; + while (rst_tmp = '0' and RST='0') loop + wait for (clkfx_period); + CLKFX_out_fs <= not CLKFX_out_fs; + CLKFX180_out_fs <= not CLKFX180_out_fs; + if (pos_shift_st(1)='1' and pos_shift(1)='0') then + wait for ((clkfx_period) + shift_ammount); + pos_shift(1) <= '1'; + elsif (neg_shift_st(1)='1' and neg_shift(1)='0') then + wait for ((clkfx_period)-shift_ammount); + neg_shift(1) <= '1'; + else + if (pos_shift_st(1)='0') then + pos_shift(1) <= '0'; + end if; + if (neg_shift_st(1)='0') then + neg_shift(1) <= '0'; + end if; + wait for clkfx_period; + end if; + CLKFX_out_fs <= not CLKFX_out_fs; + CLKFX180_out_fs <= not CLKFX180_out_fs; + if (clkin_error='1') then + wait until (RST = '1'); + end if; + end loop; + end process; + + clkdv_dcm : process + begin + pos_shift(2) <= '0'; + neg_shift(2) <= '0'; + CLKDV_out_fs <= '0'; + rst_done_dv <= '1'; +-- wait until (RST='0'); + wait until (rst_tmp = '0'); + wait until (LOCKED_out_fs='1'); + rst_done_dv <= '0'; + CLKDV_out_fs <= not CLKDV_out_fs; + while (rst_tmp = '0' and RST = '0') loop + if (pos_shift_st(2)='1' and pos_shift(2)='0') then + wait for (clkdv_period+shift_ammount); + pos_shift(2) <= '1'; + elsif (neg_shift_st(2)='1' and neg_shift(2)='0') then + wait for (clkdv_period-shift_ammount); + neg_shift(2) <= '1'; + else + if (pos_shift_st(2)='0') then + pos_shift(2) <= '0'; + end if; + if (neg_shift_st(2)='0') then + neg_shift(2) <= '0'; + end if; + wait for (clkdv_period); + end if; + CLKDV_out_fs <= not CLKDV_out_fs; + if (clkin_error='1') then + wait until (RST='1'); + end if; + end loop; + end process; + + dps_dcm : process (PSCLK) + variable shift : integer :=0; + begin + if (PSCLK'event and PSCLK='1') then + PSDONE_out_fs <= '0'; + if (ps_type=2) then + if (PSEN = '1') then + if (pos_shift /= "000" or neg_shift /= "000") then + assert false report + "Warning : Please wait for PSDONE signal before adjusting the Phase Shift. " + severity warning; + else + if (PSINCDEC = '1' and pos_shift="000") then + pos_shift_st <= "111"; + shift := shift + 1; + if (shift >256) then + STATUS_out_fs(0) <= '1'; + else + STATUS_out_fs(0) <= '0'; + end if; + elsif (PSINCDEC = '0' and neg_shift="000") then + neg_shift_st <= "111"; + shift := shift - 1; + if (shift < -256) then + STATUS_out_fs(0) <= '1'; + else + STATUS_out_fs(0) <= '0'; + end if; + end if; + end if; + end if; + end if; + if ( pos_shift="111") then + pos_shift_st <= "000"; + PSDONE_out_fs <= '1'; + else if ( neg_shift="111") then + neg_shift_st <= "000"; + PSDONE_out_fs <= '1'; + end if; + end if; + end if; + end process; + +-- STATUS(0) <= shift(8); + + process (CLKIN) + begin + if (CLKIN'event and CLKIN = '1') then + if (RST = '1') then + clkin_cnt <= 0; + else + if (clkin_cnt_en ='1') then + if (clkin_cnt = 3) then + clkin_cnt <= 0; + else + clkin_cnt <= clkin_cnt + 1; + end if; + end if; + end if; + end if; + end process; + + + status_dcm : process + begin + if (RST='1') then + old_clkin_cnt <= 0; + clkin_error <= '0'; + else +-- elsif (CLK0_out'event and CLK0_out='1') then + wait until (rising_edge(CLK0_out)); + if (clkin_cnt_en= '1') then + clkin_error <= '0' after 1 ps ; + wait until (rising_edge(CLK0_out)); + if (clkin_cnt = old_clkin_cnt) then + assert FALSE report + "Error: This DCM simulation does not support the stopping of CLKIN. Please use the standard DCM model to properly view this behavior. All DCM outputs will be suspended until the DCM is reset." + severity error; + clkin_error <= '1'; + wait until (RST='1'); + else + old_clkin_cnt <= clkin_cnt; + end if; + end if; + end if; + end process; + + +end generate; + + + +end DCM_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/dcm_sp.vhd,v 1.10.16.5 2008/07/17 23:35:09 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Digital Clock Manager +-- /___/ /\ Filename : DCM_SP.vhd +-- \ \ / \ Timestamp : Fri Jun 18 10:57:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/06/06 - Initial version. +-- 05/09/06 - Add clkin_ps_mkup and clkin_ps_mkup_win for phase shifting (CR 229789). +-- 06/14/06 - Add period_int2 and period_int3 for multiple cycle phase shifting (CR 233283). +-- 07/21/06 - Change range of variable phase shifting to +/- integer of 20*(Period-3ns). +-- Give warning not support initial phase shifting for variable phase shifting. +-- (CR 235216). +-- 09/22/06 - Add lock_period and lock_fb to clkfb_div block (CR 418722). +-- 12/19/06 - Add clkfb_div_en for clkfb2x divider (CR431210). +-- 04/06/07 - Enable the clock out in clock low time after reset in model +-- clock_divide_by_2 (CR 437471). +-- 07/10/07 - Remove modulaton of ps_delay_md for none and fixed delay type (CR441155) +-- 08/29/07 - Change delay of lock_fb_dly to 0.75*period, same as verilog (CR447628). +-- 01/22/08 - Add () to ps_in * period_in of ps_delay_md calculation (CR466293) +-- 02/21/08 - Align clk2x to both clk0 pos and neg edges. (CR467858). +-- 03/01/08 - Disable alignment of clkfb and clkin_fb check when ps_lock high (CR468893). +-- 03/20/08 - Not check clock lost when negative edge period smaller than positive +-- edge period in dcm_adv_clock_lost module (CR469499). +-- - always generate clk2x with even duty cycle regardless CLKIN duty cycle.(CR467858). +-- - Remove -- from LOCKED <= for unisim model. (CR470138). +-- 05/13/08 - Change min input clock freq from 1.0Mhz to 0.2Mhz (CR467770) +-- 07/16/08 - remove condition for lock_out[0] when 2x feedback (CR476637). +-- End Revision + + +----- dcm_sp_clock_divide_by_2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity dcm_sp_clock_divide_by_2 is + port( + clock_out : out std_ulogic := '0'; + + clock : in std_ulogic; + clock_type : in integer; + rst : in std_ulogic + ); +end dcm_sp_clock_divide_by_2; + +architecture dcm_sp_clock_divide_by_2_V of dcm_sp_clock_divide_by_2 is + signal clock_div2 : std_ulogic := '0'; + signal rst_reg : std_logic_vector(2 downto 0); + signal clk_src : std_ulogic; +begin + + CLKIN_DIVIDER : process + begin + if (rising_edge(clock)) then + clock_div2 <= not clock_div2; + end if; + wait on clock; + end process CLKIN_DIVIDER; + + gen_reset : process + begin + if (rising_edge(clock)) then + rst_reg(0) <= rst; + rst_reg(1) <= rst_reg(0) and rst; + rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst; + end if; + wait on clock; + end process gen_reset; + + clk_src <= clock_div2 when (clock_type = 1) else clock; + + assign_clkout : process + begin + if (rst = '0') then + clock_out <= clk_src; + elsif (rst = '1') then + clock_out <= '0'; + wait until falling_edge(rst_reg(2)); + if (clk_src = '1') then + wait until falling_edge(clk_src); + end if; + end if; + wait on clk_src, rst, rst_reg; + end process assign_clkout; +end dcm_sp_clock_divide_by_2_V; + +----- dcm_sp_maximum_period_check ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library STD; +use STD.TEXTIO.all; + +entity dcm_sp_maximum_period_check is + generic ( + InstancePath : string := "*"; + + clock_name : string := ""; + maximum_period : time); + port( + clock : in std_ulogic; + rst : in std_ulogic + ); +end dcm_sp_maximum_period_check; + +architecture dcm_sp_maximum_period_check_V of dcm_sp_maximum_period_check is +begin + + MAX_PERIOD_CHECKER : process + variable clock_edge_previous : time := 0 ps; + variable clock_edge_current : time := 0 ps; + variable clock_period : time := 0 ps; + variable Message : line; + begin + + if (rising_edge(clock)) then + clock_edge_previous := clock_edge_current; + clock_edge_current := NOW; + + if (clock_edge_previous > 0 ps) then + clock_period := clock_edge_current - clock_edge_previous; + end if; + + if (clock_period > maximum_period and rst = '0') then + Write ( Message, string'(" Warning : Input Clock Period of ")); + Write ( Message, clock_period ); + Write ( Message, string'(" on the ") ); + Write ( Message, clock_name ); + Write ( Message, string'(" port ") ); + Write ( Message, string'(" of DCM_SP instance ") ); + Write ( Message, string'(" exceeds allowed value of ") ); + Write ( Message, maximum_period ); + Write ( Message, string'(" at simulation time ") ); + Write ( Message, clock_edge_current ); + Write ( Message, '.' & LF ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + end if; + end if; + wait on clock; + end process MAX_PERIOD_CHECKER; +end dcm_sp_maximum_period_check_V; + +----- dcm_sp_clock_lost ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity dcm_sp_clock_lost is + port( + lost : out std_ulogic := '0'; + + clock : in std_ulogic; + enable : in boolean := false; + rst : in std_ulogic + ); +end dcm_sp_clock_lost; + +architecture dcm_sp_clock_lost_V of dcm_sp_clock_lost is + signal period : time := 0 ps; + signal period_neg : time := 0 ps; + signal period_tmp_win : time := 0 ps; + signal period_neg_tmp_win : time := 0 ps; + signal period_chk_win : time := 0 ps; + signal lost_r : std_ulogic := '0'; + signal lost_f : std_ulogic := '0'; + signal lost_sig : std_ulogic := '0'; + signal clock_negedge, clock_posedge : integer := 0; + signal clock_low, clock_high : integer := 0; + signal clock_second_pos, clock_second_neg : integer := 0; +begin + determine_period : process(clock,rst) + variable clock_edge_previous : time := 0 ps; + variable clock_edge_current : time := 0 ps; + variable period_tmp : time := 0 ps; + begin + if (rst = '1') then + period <= 0 ps; + elsif (rising_edge(clock)) then + clock_edge_previous := clock_edge_current; + clock_edge_current := NOW; + period_tmp := clock_edge_current - clock_edge_previous; + if (period /= 0 ps and (period_tmp <= period_tmp_win)) then + period <= period_tmp; + elsif (period /= 0 ps and (period_tmp > period_tmp_win)) then + period <= 0 ps; + elsif ((period = 0 ps) and (clock_edge_previous /= 0 ps) and (clock_second_pos = 1)) then + period <= period_tmp; + end if; + end if; + end process determine_period; + + period_15_p : process(period) begin + period_tmp_win <= 1.5 * period; + period_chk_win <= (period * 9.1) / 10; + end process; + + determine_period_neg : process(clock,rst) + variable clock_edge_neg_previous : time := 0 ps; + variable clock_edge_neg_current : time := 0 ps; + variable period_neg_tmp : time := 0 ps; + begin + if (rst = '1') then + period_neg <= 0 ps; + elsif (falling_edge(clock)) then + clock_edge_neg_previous := clock_edge_neg_current; + clock_edge_neg_current := NOW; + period_neg_tmp := clock_edge_neg_current - clock_edge_neg_previous; + if (period_neg /= 0 ps and (period_neg_tmp <= period_neg_tmp_win)) then + period_neg <= period_neg_tmp; + elsif (period_neg /= 0 ps and (period_neg_tmp > period_neg_tmp_win)) then + period_neg <= 0 ps; + elsif ((period_neg = 0 ps) and (clock_edge_neg_previous /= 0 ps) and (clock_second_neg = 1)) then + period_neg <= period_neg_tmp; + end if; + end if; + end process determine_period_neg; + + period_15_neg_p : process(period_neg) begin + period_neg_tmp_win <= 1.5 * period_neg; + end process; + + + CLOCK_LOST_CHECKER : process(clock, rst) + begin + if (rst = '1') then + clock_low <= 0; + clock_high <= 0; + clock_posedge <= 0; + clock_negedge <= 0; + else + if (rising_edge(clock)) then + clock_low <= 0; + clock_high <= 1; + clock_posedge <= 0; + clock_negedge <= 1; + end if; + if (falling_edge(clock)) then + clock_high <= 0; + clock_low <= 1; + clock_posedge <= 1; + clock_negedge <= 0; + end if; + end if; + end process CLOCK_LOST_CHECKER; + + CLOCK_SECOND_P : process(clock, rst) + begin + if (rst = '1') then + clock_second_pos <= 0; + clock_second_neg <= 0; + else + if (rising_edge(clock)) then + clock_second_pos <= 1; + end if; + if (falling_edge(clock)) then + clock_second_neg <= 1; + end if; + end if; + end process CLOCK_SECOND_P; + + SET_RESET_LOST_R : process + begin + if (rst = '1') then + lost_r <= '0'; + else + if ((enable = true) and (clock_second_pos = 1))then + if (rising_edge(clock)) then + wait for 1 ps; + if (period /= 0 ps) then + lost_r <= '0'; + end if; + wait for (period_chk_win); + if ((clock_low /= 1) and (clock_posedge /= 1) and (rst = '0')) then + lost_r <= '1'; + end if; + end if; + end if; + end if; + wait on clock, rst; + end process SET_RESET_LOST_R; + + SET_RESET_LOST_F : process + begin + if (rst = '1') then + lost_f <= '0'; + else + if ((enable = true) and (clock_second_neg = 1))then + if (falling_edge(clock)) then + if (period /= 0 ps) then + lost_f <= '0'; + end if; + wait for (period_chk_win); + if ((clock_high /= 1) and (clock_negedge /= 1) and (rst = '0') and (period <= period_neg) ) then + lost_f <= '1'; + end if; + end if; + end if; + end if; + wait on clock, rst; + end process SET_RESET_LOST_F; + + assign_lost : process(lost_r, lost_f) + begin + if (enable = true) then + if (lost_r'event) then + lost <= lost_r; + end if; + if (lost_f'event) then + lost <= lost_f; + end if; + end if; + end process assign_lost; +end dcm_sp_clock_lost_V; + + +----- CELL DCM_SP ----- +library IEEE; +use IEEE.std_logic_1164.all; + + + + + +library STD; +use STD.TEXTIO.all; + +library unisim; +use unisim.VPKG.all; + +entity DCM_SP is + generic ( + TimingChecksOn : boolean := true; + InstancePath : string := "*"; + Xon : boolean := true; + MsgOn : boolean := false; + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := false; + CLKIN_PERIOD : real := 10.0; --non-simulatable + CLKOUT_PHASE_SHIFT : string := "NONE"; + CLK_FEEDBACK : string := "1X"; + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; --non-simulatable + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DSS_MODE : string := "NONE"; --non-simulatable + DUTY_CYCLE_CORRECTION : boolean := true; + FACTORY_JF : bit_vector := X"C080"; --non-simulatable + + + PHASE_SHIFT : integer := 0; + + + STARTUP_WAIT : boolean := false --non-simulatable + ); + + port ( + CLK0 : out std_ulogic := '0'; + CLK180 : out std_ulogic := '0'; + CLK270 : out std_ulogic := '0'; + CLK2X : out std_ulogic := '0'; + CLK2X180 : out std_ulogic := '0'; + CLK90 : out std_ulogic := '0'; + CLKDV : out std_ulogic := '0'; + CLKFX : out std_ulogic := '0'; + CLKFX180 : out std_ulogic := '0'; + LOCKED : out std_ulogic := '0'; + PSDONE : out std_ulogic := '0'; + STATUS : out std_logic_vector(7 downto 0) := "00000000"; + + CLKFB : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0'; + DSSEN : in std_ulogic := '0'; + PSCLK : in std_ulogic := '0'; + PSEN : in std_ulogic := '0'; + PSINCDEC : in std_ulogic := '0'; + RST : in std_ulogic := '0' + ); + + + +end DCM_SP; + +architecture DCM_SP_V of DCM_SP is + + + component dcm_sp_clock_divide_by_2 + port( + clock_out : out std_ulogic; + + clock : in std_ulogic; + clock_type : in integer; + rst : in std_ulogic + ); + end component; + + component dcm_sp_maximum_period_check + generic ( + InstancePath : string := "*"; + + clock_name : string := ""; + maximum_period : time); + port( + clock : in std_ulogic; + rst : in std_ulogic + ); + end component; + + component dcm_sp_clock_lost + port( + lost : out std_ulogic; + + clock : in std_ulogic; + enable : in boolean := false; + rst : in std_ulogic + ); + end component; + + constant MAXPERCLKIN : time := 1000000 ps; + constant MAXPERPSCLK : time := 100000000 ps; + constant SIM_CLKIN_CYCLE_JITTER : time := 300 ps; + constant SIM_CLKIN_PERIOD_JITTER : time := 1000 ps; + + signal CLKFB_ipd, CLKIN_ipd, DSSEN_ipd : std_ulogic; + signal PSCLK_ipd, PSEN_ipd, PSINCDEC_ipd, RST_ipd : std_ulogic; + signal PSCLK_dly ,PSEN_dly, PSINCDEC_dly : std_ulogic := '0'; + + signal clk0_out : std_ulogic; + signal clk2x_out, clkdv_out : std_ulogic := '0'; + signal clkfx_out, locked_out, psdone_out, ps_overflow_out, ps_lock : std_ulogic := '0'; + signal locked_out_out : std_ulogic := '0'; + signal LOCKED_sig : std_ulogic := '0'; + + signal clkdv_cnt : integer := 0; + signal clkfb_type : integer; + signal divide_type : integer; + signal clkin_type : integer; + signal ps_type : integer; + signal deskew_adjust_mode : integer; + signal dfs_mode_type : integer; + signal dll_mode_type : integer; + signal clk1x_type : integer; + + + signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0'; + signal lock_out : std_logic_vector(1 downto 0) := "00"; + signal lock_out1_neg : std_ulogic := '0'; + + signal lock_fb : std_ulogic := '0'; + signal lock_fb_dly : std_ulogic := '0'; + signal lock_fb_dly_tmp : std_ulogic := '0'; + signal fb_delay_found : std_ulogic := '0'; + + signal clkin_div : std_ulogic; + signal clkin_ps : std_ulogic; + signal clkin_ps_tmp : std_ulogic; + signal clkin_ps_mkup : std_ulogic := '0'; + signal clkin_ps_mkup_win : std_ulogic := '0'; + + signal clkin_fb : std_ulogic; + + + signal ps_delay : time := 0 ps; + signal ps_in_out : integer := 0; + signal ps_delay_init : time := 0 ps; + signal ps_delay_md : time := 0 ps; + signal ps_delay_all : time := 0 ps; + signal ps_max_range : integer := 0; + signal ps_acc : integer := 0; + signal period_int : integer := 0; + + + type real_array_usr is array (2 downto 0) of time; + signal clkin_period_real : real_array_usr := (0.000 ns, 0.000 ns, 0.000 ns); + signal period : time := 0 ps; + signal period_25 : time := 0 ps; + signal period_50 : time := 0 ps; + signal period_div : time := 0 ps; + signal period_orig : time := 0 ps; + signal period_ps : time := 0 ps; + signal clkout_delay : time := 0 ps; + signal fb_delay : time := 0 ps; + signal period_fx, remain_fx : time := 0 ps; + signal period_dv_high, period_dv_low : time := 0 ps; + signal cycle_jitter, period_jitter : time := 0 ps; + + signal clkin_window, clkfb_window : std_ulogic := '0'; + signal rst_reg : std_logic_vector(2 downto 0) := "000"; + signal rst_flag : std_ulogic := '0'; + signal numerator, denominator, gcd : integer := 1; + + signal clkin_lost_out : std_ulogic := '0'; + signal clkfx_lost_out : std_ulogic := '0'; + + signal remain_fx_temp : integer := 0; + + signal clkin_period_real0_temp : time := 0 ps; + signal ps_lock_reg : std_ulogic := '0'; + + signal clk0_sig : std_ulogic := '0'; + signal clk2x_sig : std_ulogic := '0'; + + signal no_stop : boolean := false; + + signal clkfx180_en : std_ulogic := '0'; + + signal status_out : std_logic_vector(7 downto 0) := "00000000"; + + signal first_time_locked : boolean := false; + + signal en_status : boolean := false; + + signal ps_overflow_out_ext : std_ulogic := '0'; + signal clkin_lost_out_ext : std_ulogic := '0'; + signal clkfx_lost_out_ext : std_ulogic := '0'; + + signal clkfb_div : std_ulogic := '0'; + signal clkfb_div_en : std_ulogic := '0'; + signal clkfb_chk : std_ulogic := '0'; + + signal lock_period_dly : std_ulogic := '0'; + signal lock_period_dly1 : std_ulogic := '0'; + signal lock_period_pulse : std_ulogic := '0'; + + signal clock_stopped : std_ulogic := '1'; + + signal clkin_chkin, clkfb_chkin : std_ulogic := '0'; + signal chk_enable, chk_rst : std_ulogic := '0'; + + signal lock_ps : std_ulogic := '0'; + signal lock_ps_dly : std_ulogic := '0'; + + constant PS_STEP : time := 25 ps; + +begin + INITPROC : process + begin + detect_resolution + (model_name => "DCM_SP" + ); + if (CLKDV_DIVIDE = 1.5) then + divide_type <= 3; + elsif (CLKDV_DIVIDE = 2.0) then + divide_type <= 4; + elsif (CLKDV_DIVIDE = 2.5) then + divide_type <= 5; + elsif (CLKDV_DIVIDE = 3.0) then + divide_type <= 6; + elsif (CLKDV_DIVIDE = 3.5) then + divide_type <= 7; + elsif (CLKDV_DIVIDE = 4.0) then + divide_type <= 8; + elsif (CLKDV_DIVIDE = 4.5) then + divide_type <= 9; + elsif (CLKDV_DIVIDE = 5.0) then + divide_type <= 10; + elsif (CLKDV_DIVIDE = 5.5) then + divide_type <= 11; + elsif (CLKDV_DIVIDE = 6.0) then + divide_type <= 12; + elsif (CLKDV_DIVIDE = 6.5) then + divide_type <= 13; + elsif (CLKDV_DIVIDE = 7.0) then + divide_type <= 14; + elsif (CLKDV_DIVIDE = 7.5) then + divide_type <= 15; + elsif (CLKDV_DIVIDE = 8.0) then + divide_type <= 16; + elsif (CLKDV_DIVIDE = 9.0) then + divide_type <= 18; + elsif (CLKDV_DIVIDE = 10.0) then + divide_type <= 20; + elsif (CLKDV_DIVIDE = 11.0) then + divide_type <= 22; + elsif (CLKDV_DIVIDE = 12.0) then + divide_type <= 24; + elsif (CLKDV_DIVIDE = 13.0) then + divide_type <= 26; + elsif (CLKDV_DIVIDE = 14.0) then + divide_type <= 28; + elsif (CLKDV_DIVIDE = 15.0) then + divide_type <= 30; + elsif (CLKDV_DIVIDE = 16.0) then + divide_type <= 32; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLKDV_DIVIDE", + EntityName => "DCM_SP", + InstanceName => InstancePath, + GenericValue => CLKDV_DIVIDE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if ((CLKFX_DIVIDE <= 0) or (32 < CLKFX_DIVIDE)) then + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLKFX_DIVIDE", + EntityName => "DCM_SP", + InstanceName => InstancePath, + GenericValue => CLKFX_DIVIDE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are 1....32", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if ((CLKFX_MULTIPLY <= 1) or (32 < CLKFX_MULTIPLY)) then + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLKFX_MULTIPLY", + EntityName => "DCM_SP", + InstanceName => InstancePath, + GenericValue => CLKFX_MULTIPLY, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are 2....32", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + case CLKIN_DIVIDE_BY_2 is + when false => clkin_type <= 0; + when true => clkin_type <= 1; + when others => + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLKIN_DIVIDE_BY_2", + EntityName => "DCM_SP", + InstanceName => InstancePath, + GenericValue => CLKIN_DIVIDE_BY_2, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end case; + + + if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then + ps_type <= 0; + elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then + ps_type <= 1; + elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then + ps_type <= 2; + if (PHASE_SHIFT /= 0) then + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Warning", + GenericName => "PHASE_SHIFT", + EntityName => "DCM_SP", + InstanceName => InstancePath, + GenericValue => PHASE_SHIFT, + Unit => "", + ExpectedValueMsg => "The maximum variable phase shift range is only valid when initial phase shift PHASE_SHIFT is zero", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => warning + ); + end if; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLKOUT_PHASE_SHIFT", + EntityName => "DCM_SP", + InstanceName => InstancePath, + GenericValue => CLKOUT_PHASE_SHIFT, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are NONE, FIXED or VARIABLE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if ((CLK_FEEDBACK = "none") or (CLK_FEEDBACK = "NONE")) then + clkfb_type <= 0; + elsif ((CLK_FEEDBACK = "1x") or (CLK_FEEDBACK = "1X")) then + clkfb_type <= 1; + elsif ((CLK_FEEDBACK = "2x") or (CLK_FEEDBACK = "2X")) then + clkfb_type <= 2; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLK_FEEDBACK", + EntityName => "DCM_SP", + InstanceName => InstancePath, + GenericValue => CLK_FEEDBACK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are NONE, 1X or 2X", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + + + if ((DESKEW_ADJUST = "source_synchronous") or (DESKEW_ADJUST = "SOURCE_SYNCHRONOUS")) then + DESKEW_ADJUST_mode <= 8; + elsif ((DESKEW_ADJUST = "system_synchronous") or (DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS")) then + DESKEW_ADJUST_mode <= 11; + elsif ((DESKEW_ADJUST = "0")) then + DESKEW_ADJUST_mode <= 0; + elsif ((DESKEW_ADJUST = "1")) then + DESKEW_ADJUST_mode <= 1; + elsif ((DESKEW_ADJUST = "2")) then + DESKEW_ADJUST_mode <= 2; + elsif ((DESKEW_ADJUST = "3")) then + DESKEW_ADJUST_mode <= 3; + elsif ((DESKEW_ADJUST = "4")) then + DESKEW_ADJUST_mode <= 4; + elsif ((DESKEW_ADJUST = "5")) then + DESKEW_ADJUST_mode <= 5; + elsif ((DESKEW_ADJUST = "6")) then + DESKEW_ADJUST_mode <= 6; + elsif ((DESKEW_ADJUST = "7")) then + DESKEW_ADJUST_mode <= 7; + elsif ((DESKEW_ADJUST = "8")) then + DESKEW_ADJUST_mode <= 8; + elsif ((DESKEW_ADJUST = "9")) then + DESKEW_ADJUST_mode <= 9; + elsif ((DESKEW_ADJUST = "10")) then + DESKEW_ADJUST_mode <= 10; + elsif ((DESKEW_ADJUST = "11")) then + DESKEW_ADJUST_mode <= 11; + elsif ((DESKEW_ADJUST = "12")) then + DESKEW_ADJUST_mode <= 12; + elsif ((DESKEW_ADJUST = "13")) then + DESKEW_ADJUST_mode <= 13; + elsif ((DESKEW_ADJUST = "14")) then + DESKEW_ADJUST_mode <= 14; + elsif ((DESKEW_ADJUST = "15")) then + DESKEW_ADJUST_mode <= 15; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "DESKEW_ADJUST_MODE", + EntityName => "DCM_SP", + InstanceName => InstancePath, + GenericValue => DESKEW_ADJUST_MODE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 1....15", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if ((DFS_FREQUENCY_MODE = "high") or (DFS_FREQUENCY_MODE = "HIGH")) then + dfs_mode_type <= 1; + elsif ((DFS_FREQUENCY_MODE = "low") or (DFS_FREQUENCY_MODE = "LOW")) then + dfs_mode_type <= 0; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "DFS_FREQUENCY_MODE", + EntityName => "DCM_SP", + InstanceName => InstancePath, + GenericValue => DFS_FREQUENCY_MODE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if ((DLL_FREQUENCY_MODE = "high") or (DLL_FREQUENCY_MODE = "HIGH")) then + dll_mode_type <= 1; + elsif ((DLL_FREQUENCY_MODE = "low") or (DLL_FREQUENCY_MODE = "LOW")) then + dll_mode_type <= 0; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "DLL_FREQUENCY_MODE", + EntityName => "DCM_SP", + InstanceName => InstancePath, + GenericValue => DLL_FREQUENCY_MODE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if ((DSS_MODE = "none") or (DSS_MODE = "NONE")) then + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "DSS_MODE", + EntityName => "DCM_SP", + InstanceName => InstancePath, + GenericValue => DSS_MODE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are NONE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + case DUTY_CYCLE_CORRECTION is + when false => clk1x_type <= 0; + when true => clk1x_type <= 1; + when others => + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "DUTY_CYCLE_CORRECTION", + EntityName => "DCM_SP", + InstanceName => InstancePath, + GenericValue => DUTY_CYCLE_CORRECTION, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end case; + + if ((PHASE_SHIFT < -255) or (PHASE_SHIFT > 255)) then + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "PHASE_SHIFT", + EntityName => "DCM_SP", + InstanceName => InstancePath, + GenericValue => PHASE_SHIFT, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are -255 ... 255", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + period_jitter <= SIM_CLKIN_PERIOD_JITTER; + cycle_jitter <= SIM_CLKIN_CYCLE_JITTER; + + case STARTUP_WAIT is + when false => null; + when true => null; + when others => + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "STARTUP_WAIT", + EntityName => "DCM_SP", + InstanceName => InstancePath, + GenericValue => STARTUP_WAIT, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end case; + +-- +-- fx parameters +-- + gcd <= 1; + for i in 2 to CLKFX_MULTIPLY loop + if (((CLKFX_MULTIPLY mod i) = 0) and ((CLKFX_DIVIDE mod i) = 0)) then + gcd <= i; + end if; + end loop; + numerator <= CLKFX_MULTIPLY / gcd; + denominator <= CLKFX_DIVIDE / gcd; + wait; + end process INITPROC; + +-- +-- input wire delays +-- + + + CLKFB_ipd <= CLKFB; + CLKIN_ipd <= CLKIN; + DSSEN_ipd <= DSSEN; + PSCLK_dly <= PSCLK; + PSEN_dly <= PSEN; + PSINCDEC_dly <= PSINCDEC; + RST_ipd <= RST; + + i_clock_divide_by_2 : dcm_sp_clock_divide_by_2 + port map ( + clock => clkin_ipd, + clock_type => clkin_type, + rst => rst_ipd, + clock_out => clkin_div); + + i_max_clkin : dcm_sp_maximum_period_check + generic map ( + clock_name => "CLKIN", + maximum_period => MAXPERCLKIN) + + port map ( + clock => clkin_ipd, + rst => rst_ipd); + + i_max_psclk : dcm_sp_maximum_period_check + generic map ( + clock_name => "PSCLK", + maximum_period => MAXPERPSCLK) + + port map ( + clock => psclk_dly, + rst => rst_ipd); + + i_clkin_lost : dcm_sp_clock_lost + port map ( + lost => clkin_lost_out, + clock => clkin_ipd, + enable => first_time_locked, + rst => rst_ipd + ); + + i_clkfx_lost : dcm_sp_clock_lost + port map ( + lost => clkfx_lost_out, + clock => clkfx_out, + enable => first_time_locked, + rst => rst_ipd + ); + + clkin_ps_tmp <= transport clkin_div after ps_delay_md; + + clkin_ps <= clkin_ps_mkup when clkin_ps_mkup_win = '1' else clkin_ps_tmp; + + clkin_fb <= transport (clkin_ps and lock_fb); + + + clkin_ps_tmp_p: process + variable ps_delay_last : integer := 0; + variable ps_delay_int : integer; + variable period_int2 : integer := 0; + variable period_int3 : integer := 0; + begin + if (ps_type = 2) then + ps_delay_int := (ps_delay /1 ps ) * 1; + period_int2 := 2 * period_int; + period_int3 := 3 * period_int; + + if (rising_edge(clkin_div)) then + if ((ps_delay_last > 0 and ps_delay_int <= 0 ) or + (ps_delay_last >= period_int and ps_delay_int < period_int) or + (ps_delay_last >= period_int2 and ps_delay_int < period_int2) or + (ps_delay_last >= period_int3 and ps_delay_int < period_int3)) then + clkin_ps_mkup_win <= '1'; + clkin_ps_mkup <= '1'; + wait until falling_edge(clkin_div); + clkin_ps_mkup_win <= '1'; + clkin_ps_mkup <= '0'; + else + clkin_ps_mkup_win <= '0'; + clkin_ps_mkup <= '0'; + end if; + end if; + + if (falling_edge(clkin_div)) then + if ((ps_delay_last > 0 and ps_delay_int <= 0 ) or + (ps_delay_last >= period_int and ps_delay_int < period_int) or + (ps_delay_last >= period_int2 and ps_delay_int < period_int2) or + (ps_delay_last >= period_int3 and ps_delay_int < period_int3)) then + clkin_ps_mkup <= '0'; + clkin_ps_mkup_win <= '0'; + wait until rising_edge(clkin_div); + clkin_ps_mkup <= '1'; + clkin_ps_mkup_win <= '1'; + wait until falling_edge(clkin_div); + clkin_ps_mkup <= '0'; + clkin_ps_mkup_win <= '1'; + else + clkin_ps_mkup <= '0'; + clkin_ps_mkup_win <= '0'; + end if; + end if; + ps_delay_last := ps_delay_int; + end if; + wait on clkin_div; + end process; + + detect_first_time_locked : process + begin + if (first_time_locked = false) then + if (rising_edge(locked_out)) then + first_time_locked <= true; + end if; + end if; + wait on locked_out; + end process detect_first_time_locked; + + set_reset_en_status : process + begin + if (rst_ipd = '1') then + en_status <= false; + elsif (rising_edge(Locked_sig)) then + en_status <= true; + end if; + wait on rst_ipd, Locked_sig; + end process set_reset_en_status; + + gen_clkfb_div_en: process + begin + if (rst_ipd = '1') then + clkfb_div_en <= '0'; + elsif (falling_edge(clkfb_ipd)) then + if (lock_fb_dly='1' and lock_period='1' and lock_fb = '1' and clkin_ps = '0') then + clkfb_div_en <= '1'; + end if; + end if; + wait on clkfb_ipd, rst_ipd; + end process gen_clkfb_div_en; + + gen_clkfb_div: process + begin + if (rst_ipd = '1') then + clkfb_div <= '0'; + elsif (rising_edge(clkfb_ipd)) then + if (clkfb_div_en = '1') then + clkfb_div <= not clkfb_div; + end if; + end if; + wait on clkfb_ipd, rst_ipd; + end process gen_clkfb_div; + + determine_clkfb_chk: process + begin + if (clkfb_type = 2) then + clkfb_chk <= clkfb_div; + else + clkfb_chk <= clkfb_ipd and lock_fb_dly; + end if; + wait on clkfb_ipd, clkfb_div; + end process determine_clkfb_chk; + + set_reset_clkin_chkin : process + begin + if ((rising_edge(clkin_fb)) or (rising_edge(chk_rst))) then + if (chk_rst = '1') then + clkin_chkin <= '0'; + else + clkin_chkin <= '1'; + end if; + end if; + wait on clkin_fb, chk_rst; + end process set_reset_clkin_chkin; + + set_reset_clkfb_chkin : process + begin + if ((rising_edge(clkfb_chk)) or (rising_edge(chk_rst))) then + if (chk_rst = '1') then + clkfb_chkin <= '0'; + else + clkfb_chkin <= '1'; + end if; + end if; + wait on clkfb_chk, chk_rst; + end process set_reset_clkfb_chkin; + + +-- assign_chk_rst: process +-- begin +-- if ((rst_ipd = '1') or (clock_stopped = '1')) then +-- chk_rst <= '1'; +-- else +-- chk_rst <= '0'; +-- end if; +-- wait on rst_ipd, clock_stopped; +-- end process assign_chk_rst; + + chk_rst <= '1' when ((rst_ipd = '1') or (clock_stopped = '1')) else '0'; + +-- assign_chk_enable: process +-- begin +-- if ((clkin_chkin = '1') and (clkfb_chkin = '1')) then +-- chk_enable <= '1'; +-- else +-- chk_enable <= '0'; +-- end if; +-- wait on clkin_chkin, clkfb_chkin; +-- end process assign_chk_enable; + + chk_enable <= '1' when ((clkin_chkin = '1') and (clkfb_chkin = '1') and (lock_ps = '1') and (lock_fb_dly = '1') and (lock_fb = '1')) else '0'; + + + + + control_status_bits: process + begin + if ((rst_ipd = '1') or (en_status = false)) then + ps_overflow_out_ext <= '0'; + clkin_lost_out_ext <= '0'; + clkfx_lost_out_ext <= '0'; + else + ps_overflow_out_ext <= ps_overflow_out; + clkin_lost_out_ext <= clkin_lost_out; + clkfx_lost_out_ext <= clkfx_lost_out; + end if; + wait on clkfx_lost_out, clkin_lost_out, en_status, ps_overflow_out, rst_ipd; + end process control_status_bits; + + determine_period_div : process + variable clkin_div_edge_previous : time := 0 ps; + variable clkin_div_edge_current : time := 0 ps; + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + clkin_div_edge_previous := 0 ps; + clkin_div_edge_current := 0 ps; + period_div <= 0 ps; + else + if (rising_edge(clkin_div)) then + clkin_div_edge_previous := clkin_div_edge_current; + clkin_div_edge_current := NOW; + if ((clkin_div_edge_current - clkin_div_edge_previous) <= (1.5 * period_div)) then + period_div <= clkin_div_edge_current - clkin_div_edge_previous; + elsif ((period_div = 0 ps) and (clkin_div_edge_previous /= 0 ps)) then + period_div <= clkin_div_edge_current - clkin_div_edge_previous; + end if; + end if; + end if; + wait on clkin_div, rst_ipd; + end process determine_period_div; + + period_cal_p : process(period) + variable period_25_tmp : time := 0 ps; + begin + period_25_tmp := period / 4; + period_50 <= 2 * period_25_tmp; + period_25 <= period_25_tmp; + end process; + + determine_period_ps : process + variable clkin_ps_edge_previous : time := 0 ps; + variable clkin_ps_edge_current : time := 0 ps; + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + clkin_ps_edge_previous := 0 ps; + clkin_ps_edge_current := 0 ps; + period_ps <= 0 ps; + else + if (rising_edge(clkin_ps)) then + clkin_ps_edge_previous := clkin_ps_edge_current; + clkin_ps_edge_current := NOW; + wait for 0 ps; + if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then + period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; + elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then + period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; + end if; + end if; + end if; + wait on clkin_ps, rst_ipd; + end process determine_period_ps; + + assign_lock_ps_fb : process + + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + lock_fb <= '0'; + lock_ps <= '0'; + lock_ps_dly <= '0'; + lock_fb_dly <= '0'; + lock_fb_dly_tmp <= '0'; + else + if (rising_edge(clkin_ps)) then + lock_ps <= lock_period; + lock_ps_dly <= lock_ps; + lock_fb <= lock_ps_dly; + lock_fb_dly_tmp <= lock_fb; + end if; + if (falling_edge(clkin_ps)) then +-- lock_fb_dly <= lock_fb_dly_tmp after (period/4); + lock_fb_dly <= lock_fb_dly_tmp after (period * 0.75); + end if; + end if; + wait on clkin_ps, rst_ipd; + end process assign_lock_ps_fb; + + calculate_clkout_delay : process + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + clkout_delay <= 0 ps; + elsif (fb_delay = 0 ps) then + clkout_delay <= 0 ps; + elsif (period'event or fb_delay'event) then + clkout_delay <= period - fb_delay; + end if; + wait on period, fb_delay, rst_ipd; + end process calculate_clkout_delay; + +-- +--generate master reset signal +-- + + gen_master_rst : process + begin + if (rising_edge(clkin_ipd)) then + rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_ipd; + rst_reg(1) <= rst_reg(0) and rst_ipd; + rst_reg(0) <= rst_ipd; + end if; + wait on clkin_ipd; + end process gen_master_rst; + + check_rst_width : process + variable Message : line; + begin + if (rst_ipd ='1') then + rst_flag <= '0'; + end if; + if (falling_edge(rst_ipd)) then + if ((rst_reg(2) and rst_reg(1) and rst_reg(0)) = '0') then + rst_flag <= '1'; + Write ( Message, string'(" Input Error : RST on DCM_SP ")); + Write ( Message, string'(" must be asserted for 3 CLKIN clock cycles. ")); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + end if; + + wait on rst_ipd; + end process check_rst_width; + +-- +--phase shift parameters +-- + + ps_max_range_p : process (period) + variable period_ps_tmp : integer := 0; + begin + period_int <= (period/ 1 ps ) * 1; + if (clkin_type = 1) then + period_ps_tmp := 2 * (period/ 1 ns ); + else + period_ps_tmp := (period/ 1 ns ) * 1; + end if; + if (period_ps_tmp > 3) then + ps_max_range <= 20 * (period_ps_tmp - 3); + else + ps_max_range <= 0; + end if; + end process; + + ps_delay_md_p : process (period, ps_delay, lock_period, rst_ipd) + variable tmp_value : integer; + variable tmp_value1 : integer; + variable tmp_value2 : integer; + begin + if (rst_ipd = '1') then + ps_delay_md <= 0 ps; + elsif (lock_period = '1') then + tmp_value := (ps_delay / 1 ps ) * 1; + tmp_value1 := (period / 1 ps) * 1; + tmp_value2 := tmp_value mod tmp_value1; + if (ps_type = 2) then + ps_delay_md <= period + tmp_value2 * 1 ps; + else + ps_delay_md <= period + (ps_in_out * period) / 256; + end if; + end if; + end process; + + + determine_phase_shift : process + variable Message : line; + variable first_time : boolean := true; + variable ps_in : integer; + variable ps_acc : integer := 0; + variable ps_step_int : integer := 0; + begin + if (first_time = true) then + if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then + ps_in := 256; + elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then + ps_in := 256 + PHASE_SHIFT; + elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then + ps_in := 256 + PHASE_SHIFT; + end if; + ps_step_int := (PS_STEP / 1 ps ) * 1; + first_time := false; + end if; + + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then + ps_in := 256; + elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then + ps_in := 256 + PHASE_SHIFT; + elsif ((CLKOUT_PHASE_SHIFT = "variable") or (CLKOUT_PHASE_SHIFT = "VARIABLE")) then + ps_in := 256 + PHASE_SHIFT; + else + end if; + ps_in_out <= ps_in; + ps_lock <= '0'; + ps_overflow_out <= '0'; + ps_delay <= 0 ps; + ps_acc := 0; + elsif (rising_edge(lock_period_pulse)) then + ps_delay <= (ps_in * period_div / 256); + elsif (rising_edge(PSCLK_dly)) then + if (ps_type = 2) then + if (psen_dly = '1') then + if (ps_lock = '1') then + Write ( Message, string'(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift. ")); + assert false report Message.all severity warning; + DEALLOCATE (Message); + else if (lock_ps = '1') then + if (psincdec_dly = '1') then + if (ps_acc > ps_max_range) then + ps_overflow_out <= '1'; + else + ps_delay <= ps_delay + PS_STEP; + ps_acc := ps_acc + 1; + ps_overflow_out <= '0'; + end if; + ps_lock <= '1'; + elsif (psincdec_dly = '0') then + if (ps_acc < -ps_max_range) then + ps_overflow_out <= '1'; + else + ps_delay <= ps_delay - PS_STEP; + ps_acc := ps_acc - 1; + ps_overflow_out <= '0'; + end if; + ps_lock <= '1'; + end if; + end if; + end if; + end if; + end if; + end if; + if (ps_lock_reg'event) then + ps_lock <= ps_lock_reg; + end if; + wait on lock_period_pulse, psclk_dly, ps_lock_reg, rst_ipd; + end process determine_phase_shift; + + determine_psdone_out : process + begin + if (rising_edge(ps_lock)) then + ps_lock_reg <= '1'; + wait until (rising_edge(clkin_ps)); + wait until (rising_edge(psclk_dly)); + wait until (rising_edge(psclk_dly)); + wait until (rising_edge(psclk_dly)); + psdone_out <= '1'; + wait until (rising_edge(psclk_dly)); + psdone_out <= '0'; + ps_lock_reg <= '0'; + end if; + wait on ps_lock; + end process determine_psdone_out; + +-- +--determine clock period +-- + determine_clock_period : process + variable clkin_edge_previous : time := 0 ps; + variable clkin_edge_current : time := 0 ps; + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + clkin_period_real(0) <= 0 ps; + clkin_period_real(1) <= 0 ps; + clkin_period_real(2) <= 0 ps; + clkin_edge_previous := 0 ps; + clkin_edge_current := 0 ps; + elsif (rising_edge(clkin_div)) then + clkin_edge_previous := clkin_edge_current; + clkin_edge_current := NOW; + clkin_period_real(2) <= clkin_period_real(1); + clkin_period_real(1) <= clkin_period_real(0); + if (clkin_edge_previous /= 0 ps) then + clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous; + end if; + end if; + if (no_stop'event) then + clkin_period_real(0) <= clkin_period_real0_temp; + end if; + wait on clkin_div, no_stop, rst_ipd; + end process determine_clock_period; + + evaluate_clock_period : process + variable Message : line; + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + lock_period <= '0'; + clock_stopped <= '1'; + clkin_period_real0_temp <= 0 ps; + else + if (falling_edge(clkin_div)) then + if (lock_period = '0') then + if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then + lock_period <= '1'; + period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3; + period <= clkin_period_real(0); + end if; + elsif (lock_period = '1') then + if (100000000 ns < clkin_period_real(0)) then + Write ( Message, string'(" Warning : CLKIN stopped toggling on instance ")); + Write ( Message, Instancepath ); + Write ( Message, string'(" exceeds ")); + Write ( Message, string'(" 100 ms ")); + Write ( Message, string'(" Current CLKIN Period = ")); + Write ( Message, clkin_period_real(0)); + assert false report Message.all severity warning; + DEALLOCATE (Message); + lock_period <= '0'; + wait until (falling_edge(rst_reg(2))); + elsif ((period_orig * 2 < clkin_period_real(0)) and (clock_stopped = '0')) then + clkin_period_real0_temp <= clkin_period_real(1); + no_stop <= not no_stop; + clock_stopped <= '1'; + elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then + Write ( Message, string'(" Warning : Input Clock Period Jitter on instance ")); + Write ( Message, Instancepath ); + Write ( Message, string'(" exceeds ")); + Write ( Message, period_jitter ); + Write ( Message, string'(" Locked CLKIN Period = ")); + Write ( Message, period_orig ); + Write ( Message, string'(" Current CLKIN Period = ")); + Write ( Message, clkin_period_real(0) ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + lock_period <= '0'; + wait until (falling_edge(rst_reg(2))); + elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then + Write ( Message, string'(" Warning : Input Clock Cycle Jitter on on instance ")); + Write ( Message, Instancepath ); + Write ( Message, string'(" exceeds ")); + Write ( Message, cycle_jitter ); + Write ( Message, string'(" Previous CLKIN Period = ")); + Write ( Message, clkin_period_real(1) ); + Write ( Message, string'(" Current CLKIN Period = ")); + Write ( Message, clkin_period_real(0) ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + lock_period <= '0'; + wait until (falling_edge(rst_reg(2))); + else + period <= clkin_period_real(0); + clock_stopped <= '0'; + end if; + end if; + end if; + end if; + wait on clkin_div, rst_ipd; + end process evaluate_clock_period; + + lock_period_dly1 <= transport lock_period after 1 ps; + lock_period_dly <= transport lock_period_dly1 after period_50; + + lock_period_pulse <= '1' when ((lock_period = '1') and (lock_period_dly = '0')) else '0'; + +-- +--determine clock delay +-- + + determine_clock_delay : process + variable delay_edge : time := 0 ps; + variable temp1 : integer := 0; + variable temp2 : integer := 0; + variable temp : integer := 0; + variable delay_edge_current : time := 0 ps; + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + fb_delay <= 0 ps; + fb_delay_found <= '0'; + else + if (rising_edge(lock_ps_dly)) then + if ((lock_period = '1') and (clkfb_type /= 0)) then + if (clkfb_type = 1) then + wait until ((rising_edge(clk0_sig)) or (rst_ipd'event)); + delay_edge := NOW; + elsif (clkfb_type = 2) then + wait until ((rising_edge(clk2x_sig)) or (rst_ipd'event)); + delay_edge := NOW; + end if; + wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event)); + temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps); + temp2 := (period_orig * 1)/ (1 ps); + temp := temp1 mod temp2; + fb_delay <= temp * 1 ps; + fb_delay_found <= '1'; + end if; + end if; + end if; + wait on lock_ps_dly, rst_ipd; + end process determine_clock_delay; +-- +-- determine feedback lock +-- + GEN_CLKFB_WINDOW : process + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + clkfb_window <= '0'; + else + if (rising_edge(clkfb_chk)) then + wait for 0 ps; + clkfb_window <= '1'; + wait for cycle_jitter; + clkfb_window <= '0'; + end if; + end if; + wait on clkfb_chk, rst_ipd; + end process GEN_CLKFB_WINDOW; + + GEN_CLKIN_WINDOW : process + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + clkin_window <= '0'; + else + if (rising_edge(clkin_fb)) then + wait for 0 ps; + clkin_window <= '1'; + wait for cycle_jitter; + clkin_window <= '0'; + end if; + end if; + wait on clkin_fb, rst_ipd; + end process GEN_CLKIN_WINDOW; + + set_reset_lock_clkin : process + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + lock_clkin <= '0'; + else + if (rising_edge(clkin_fb)) then + wait for 1 ps; + if (((clkfb_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1'))) then + lock_clkin <= '1'; + else + if (chk_enable = '1' and ps_lock = '0') then + lock_clkin <= '0'; + end if; + end if; + end if; + end if; + wait on clkin_fb, rst_ipd; + end process set_reset_lock_clkin; + + set_reset_lock_clkfb : process + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + lock_clkfb <= '0'; + else + if (rising_edge(clkfb_chk)) then + wait for 1 ps; + if (((clkin_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1')))then + lock_clkfb <= '1'; + else + if (chk_enable = '1' and ps_lock = '0') then + lock_clkfb <= '0'; + end if; + end if; + end if; + end if; + wait on clkfb_chk, rst_ipd; + end process set_reset_lock_clkfb; + + assign_lock_delay : process + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + lock_delay <= '0'; + else + if (falling_edge(clkin_fb)) then + lock_delay <= lock_clkin or lock_clkfb; + end if; + end if; + wait on clkin_fb, rst_ipd; + end process; + +-- +--generate lock signal +-- + + generate_lock : process(clkin_ps, rst_ipd) + begin + if (rst_ipd='1') then + lock_out <= "00"; + locked_out <= '0'; + lock_out1_neg <= '0'; + elsif (rising_edge(clkin_ps)) then +-- if (clkfb_type = 0) then + lock_out(0) <= lock_period; +-- else +-- lock_out(0) <= lock_period and lock_delay and lock_fb; +-- end if; + lock_out(1) <= lock_out(0); + locked_out <= lock_out(1); + elsif (falling_edge(clkin_ps)) then + lock_out1_neg <= lock_out(1); + end if; + end process generate_lock; + +-- +--generate the clk1x_out +-- + + gen_clk1x : process( clkin_ps, rst_ipd) + begin + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + clk0_out <= '0'; + elsif (clkin_ps'event) then + if (clkin_ps = '1' ) then + if ((clk1x_type = 1) and (lock_out(0) = '1')) then + clk0_out <= '1', '0' after period_50; + else + clk0_out <= '1'; + end if; + else + if ((clkin_ps = '0') and ((((clk1x_type = 1) and (lock_out(0) = '1')) = false) or ((lock_out(0) = '1') and (lock_out(1) = '0')))) then + clk0_out <= '0'; + end if; + end if; + end if; + end process gen_clk1x; + + + + + +-- +--generate the clk2x_out +-- + + + gen_clk2x : process + begin + if (rst_ipd='1') then + clk2x_out <= '0'; + elsif (rising_edge(clkin_ps)) then + clk2x_out <= '1'; + wait for period_25; + clk2x_out <= '0'; + if (lock_out(0) = '1') then + wait for period_25; + clk2x_out <= '1'; + wait for period_25; + clk2x_out <= '0'; + else + wait for period_50; + end if; + end if; + wait on clkin_ps, rst_ipd; + end process gen_clk2x; + +-- +--generate the clkdv_out +-- + + gen_clkdv : process (clkin_ps, rst_ipd) + begin + if (rst_ipd='1') then + clkdv_out <= '0'; + clkdv_cnt <= 0; + elsif ((rising_edge(clkin_ps)) or (falling_edge(clkin_ps))) then + if (lock_out1_neg = '1') then + if (clkdv_cnt >= divide_type -1) then + clkdv_cnt <= 0; + else + clkdv_cnt <= clkdv_cnt + 1; + end if; + + if (clkdv_cnt < divide_type /2) then + clkdv_out <= '1'; + else + if ( ((divide_type rem (2)) > 0) and (dll_mode_type = 0)) then + clkdv_out <= '0' after (period_25); + else + clkdv_out <= '0'; + end if; + end if; + end if; + end if; + end process; + +-- +-- generate fx output signal +-- + + calculate_period_fx : process + begin + if (lock_period = '1') then + period_fx <= (period * denominator) / (numerator * 2); + remain_fx <= (((period/1 ps) * denominator) mod (numerator * 2)) * 1 ps; + end if; + wait on lock_period, period, denominator, numerator; + end process calculate_period_fx; + + generate_clkfx : process + variable temp : integer; + begin + if (rst_ipd = '1') then + clkfx_out <= '0'; + elsif (clkin_lost_out_ext = '1') then + wait until (rising_edge(rst_ipd)); + clkfx_out <= '0'; + wait until (falling_edge(rst_reg(2))); + elsif (rising_edge(clkin_ps)) then + if (lock_out(1) = '1') then + clkfx_out <= '1'; + temp := numerator * 2 - 1 - 1; + for p in 0 to temp loop + wait for (period_fx); + clkfx_out <= not clkfx_out; + end loop; + if (period_fx > (period_50)) then + wait for (period_fx - (period_50)); + end if; + end if; + if (clkin_lost_out_ext = '1') then + wait until (rising_edge(rst_ipd)); + clkfx_out <= '0'; + wait until (falling_edge(rst_reg(2))); + end if; + end if; + wait on clkin_lost_out_ext, clkin_ps, rst_ipd, rst_reg(2); + end process generate_clkfx; + + +-- +--generate all output signal +-- + + schedule_p1_outputs : process + begin + if (CLK0_out'event) then + if (clkfb_type /= 0) then + CLK0 <= transport CLK0_out after clkout_delay; + clk0_sig <= transport CLK0_out after clkout_delay; + end if; + if ((dll_mode_type = 0) and (clkfb_type /= 0)) then + CLK90 <= transport clk0_out after (clkout_delay + period_25); + end if; + end if; + + if (CLK0_out'event or rst_ipd'event)then + if (rst_ipd = '1') then + CLK180 <= '0'; + CLK270 <= '0'; + elsif (CLK0_out'event) then + if (clkfb_type /= 0) then + CLK180 <= transport (not clk0_out) after clkout_delay; + end if; + if ((dll_mode_type = 0) and (clkfb_type /= 0)) then + CLK270 <= transport (not clk0_out) after (clkout_delay + period_25); + end if; + end if; + end if; + + if (clk2x_out'event) then + if ((dll_mode_type = 0) and (clkfb_type /= 0)) then + CLK2X <= transport clk2x_out after clkout_delay; + clk2x_sig <= transport clk2x_out after clkout_delay; + end if; + end if; + + if (CLK2X_out'event or rst_ipd'event) then + if (rst_ipd = '1') then + CLK2X180 <= '0'; + elsif (CLK2X_out'event) then + if ((dll_mode_type = 0) and (clkfb_type /= 0)) then + CLK2X180 <= transport (not CLK2X_out) after clkout_delay; + end if; + end if; + end if; + + + if (clkdv_out'event) then + if (clkfb_type /= 0) then + CLKDV <= transport clkdv_out after clkout_delay; + end if; + end if; + + if (clkfx_out'event or rst_ipd'event) then + if (rst_ipd = '1') then + CLKFX <= '0'; + elsif (clkfx_out'event) then + CLKFX <= transport clkfx_out after clkout_delay; + end if; + end if; + + if (clkfx_out'event or (rising_edge(rst_ipd)) or first_time_locked'event or locked_out'event) then + if ((rst_ipd = '1') or (not first_time_locked)) then + CLKFX180 <= '0'; + else + CLKFX180 <= transport (not clkfx_out) after clkout_delay; + end if; + end if; + + if (status_out(0)'event) then + status(0) <= status_out(0); + end if; + + if (status_out(1)'event) then + status(1) <= status_out(1); + end if; + + if (status_out(2)'event) then + status(2) <= status_out(2); + end if; + + wait on clk0_out, clk2x_out, clkdv_out, clkfx_out, first_time_locked, locked_out, rst_ipd, status_out; + end process; + + assign_status_out : process + begin + if (rst_ipd = '1') then + status_out(0) <= '0'; + status_out(1) <= '0'; + status_out(2) <= '0'; + elsif (ps_overflow_out_ext'event) then + status_out(0) <= ps_overflow_out_ext; + elsif (clkin_lost_out_ext'event) then + status_out(1) <= clkin_lost_out_ext; + elsif (clkfx_lost_out_ext'event) then + status_out(2) <= clkfx_lost_out_ext; + end if; + wait on clkin_lost_out_ext, clkfx_lost_out_ext, ps_overflow_out_ext, rst_ipd; + end process assign_status_out; + + locked_out_out <= 'X' when rst_flag = '1' else locked_out; + + LOCKED <= locked_out_out after 100 ps; + PSDONE <= psdone_out; + LOCKED_sig <= locked_out_out after 100 ps; + +end DCM_SP_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fd.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop +-- /___/ /\ Filename : FD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:21 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FD is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + D : in std_ulogic + ); +end FD; + +architecture FD_V of FD is +begin + + VITALBehavior : process(C) + variable FIRST_TIME : boolean := true ; + begin + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (rising_edge(C)) then + Q <= D after 100 ps; + end if; + end process; +end FD_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fd_1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Negative-Edge Clock +-- /___/ /\ Filename : FD_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:21 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FD_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FD_1 is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + D : in std_ulogic + ); +end FD_1; + +architecture FD_1_V of FD_1 is +begin + VITALBehavior : process(C) + variable FIRST_TIME : boolean := true ; + begin + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + if (falling_edge(C)) then + Q <= D after 100 ps; + end if; + end process; +end FD_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdc.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Asynchronous Clear +-- /___/ /\ Filename : FDC.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:21 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDC ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDC is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic + ); +end FDC; + +architecture FDC_V of FDC is +begin + VITALBehavior : process(CLR, C) + variable FIRST_TIME : boolean := true; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (CLR = '1') then + Q <= '0'; + elsif (rising_edge(C)) then + Q <= D after 100 ps; + end if; +end process; +end FDC_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdc_1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Asynchronous Clear and Negative-Edge Clock +-- /___/ /\ Filename : FDC_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:21 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDC_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDC_1 is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic + ); +end FDC_1; + +architecture FDC_1_V of FDC_1 is +begin + VITALBehavior : process(C, CLR) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (CLR = '1') then + Q <= '0'; + elsif (falling_edge(C)) then + Q <= D after 100 ps; + end if; + end process; +end FDC_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdce.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Asynchronous Clear and Clock Enable +-- /___/ /\ Filename : FDCE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:22 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDCE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDCE is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CE : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic + ); +end FDCE; + +architecture FDCE_V of FDCE is +begin + VITALBehavior : process(C, CLR) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (CLR = '1') then + Q <= '0'; + elsif (rising_edge(C)) then + if (CE = '1') then + Q <= D after 100 ps; + end if; + end if; + end process; +end FDCE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdce_1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Asynchronous Clear, Clock Enable and Negative-Edge Clock +-- /___/ /\ Filename : FDCE_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:22 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDCE_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDCE_1 is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CE : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic + ); +end FDCE_1; + +architecture FDCE_1_V of FDCE_1 is +begin + VITALBehavior : process(C, CLR) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (CLR = '1') then + Q <= '0'; + elsif (falling_edge(C)) then + if (CE = '1') then + Q <= D after 100 ps; + end if; + end if; + end process; +end FDCE_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdcp.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Asynchronous Clear and Preset +-- /___/ /\ Filename : FDCP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:22 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDCP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDCP is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); +end FDCP; + +architecture FDCP_V of FDCP is +begin + VITALBehavior : process(C, CLR, PRE) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (CLR = '1') then + Q <= '0'; + elsif (PRE = '1') then + Q <= '1'; + elsif (rising_edge(C)) then + Q <= D after 100 ps; + end if; + end process; +end FDCP_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdcp_1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Asynchronous Clear and Preset and Negative-Edge Clock +-- /___/ /\ Filename : FDCP_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:22 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDCP_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDCP_1 is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); + +end FDCP_1; + +architecture FDCP_1_V of FDCP_1 is +begin + VITALBehavior : process(C, CLR, PRE) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (CLR = '1') then + Q <= '0'; + elsif (PRE = '1') then + Q <= '1'; + elsif (falling_edge(C)) then + Q <= D after 100 ps; + end if; + end process; +end FDCP_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdcpe.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Asynchronous Clear and Preset and Clock Enable +-- /___/ /\ Filename : FDCPE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:22 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDCPE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDCPE is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CE : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); +end FDCPE; + +architecture FDCPE_V of FDCPE is +begin + VITALBehavior : process(C, CLR, PRE) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (CLR = '1') then + Q <= '0'; + elsif (PRE = '1') then + Q <= '1'; + elsif (rising_edge(C)) then + if (CE = '1') then + Q <= D after 100 ps; + end if; + end if; + end process; +end FDCPE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdcpe_1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Asynchronous Clear and Preset, Clock Enable and Negative-Edge Clock +-- /___/ /\ Filename : FDCPE_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:22 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDCPE_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDCPE_1 is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CE : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); +end FDCPE_1; + +architecture FDCPE_1_V of FDCPE_1 is +begin + VITALBehavior : process(C, CLR, PRE) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (CLR = '1') then + Q <= '0'; + elsif (PRE = '1') then + Q <= '1'; + elsif (falling_edge(C)) then + if (CE = '1') then + Q <= D after 100 ps; + end if; + end if; + end process; + +end FDCPE_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fddrcpe.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Dual Data Rate D Flip-Flop with Asynchronous Clear and Preset and Clock Enable +-- /___/ /\ Filename : FDDRCPE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:23 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDDRCPE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDDRCPE is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + CLR : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + PRE : in std_ulogic + ); +end FDDRCPE; + +architecture FDDRCPE_V of FDDRCPE is +begin + + VITALBehavior : process(C0, C1, CLR, PRE) + variable FIRST_TIME : boolean := true; + begin + + if (FIRST_TIME) then + Q <= TO_X01(INIT); + FIRST_TIME := false ; + end if; + + if (CLR = '1') then + Q <= '0'; + elsif (PRE = '1' ) then + Q <= '1'; + elsif ( rising_edge(C0) = true) then + if (CE = '1' ) then + Q <= D0 after 100 ps; + end if; + elsif (rising_edge(C1) = true ) then + if (CE = '1') then + Q <= D1 after 100 ps; + end if; + end if; + end process VITALBehavior; +end FDDRCPE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fddrrse.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Dual Data Rate D Flip-Flop with Synchronous Reset and Set and Clock Enable +-- /___/ /\ Filename : FDDRRSE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:23 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDDRRSE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDDRRSE is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end FDDRRSE; + +architecture FDDRRSE_V of FDDRRSE is +begin + + VITALBehavior : process(C0, C1) + variable FIRST_TIME : boolean := true; + begin + + if (FIRST_TIME) then + Q <= TO_X01(INIT); + FIRST_TIME := false ; + end if; + + if ( rising_edge(C0) = true) then + if (R = '1') then + Q <= '0' after 100 ps; + elsif (S = '1' ) then + Q <= '1' after 100 ps; + elsif (CE = '1' ) then + Q <= D0 after 100 ps; + end if; + elsif (rising_edge(C1) = true ) then + if (R = '1') then + Q <= '0' after 100 ps; + elsif (S = '1' ) then + Q <= '1' after 100 ps; + elsif (CE = '1') then + Q <= D1 after 100 ps; + end if; + end if; + end process VITALBehavior; +end FDDRRSE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fde.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Clock Enable +-- /___/ /\ Filename : FDE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:23 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDE is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic + ); +end FDE; + +architecture FDE_V of FDE is +begin + VITALBehavior : process(C) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (rising_edge(C)) then + if (CE = '1') then + Q <= D after 100 ps; + end if; + end if; + end process; +end FDE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fde_1.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Clock Enable and Negative-Edge Clock +-- /___/ /\ Filename : FDE_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:24 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDE_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDE_1 is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic + ); +end FDE_1; + +architecture FDE_1_V of FDE_1 is +begin + VITALBehavior : process(C) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (falling_edge(C)) then + if (CE = '1') then + Q <= D after 100 ps; + end if; + end if; + end process; +end FDE_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdp.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Asynchronous Preset +-- /___/ /\ Filename : FDP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:24 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDP is + generic( + INIT : bit := '1' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); +end FDP; + +architecture FDP_V of FDP is +begin + VITALBehavior : process(C, PRE) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (PRE = '1') then + Q <= '1'; + elsif (C' event and C = '1') then + Q <= D after 100 ps; + end if; + end process; +end FDP_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdp_1.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Asynchronous Preset and Negative-Edge Clock +-- /___/ /\ Filename : FDP_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:24 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDP_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDP_1 is + generic( + INIT : bit := '1' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); +end FDP_1; + +architecture FDP_1_V of FDP_1 is +begin + VITALBehavior : process(C, PRE) + variable FIRST_TIME : boolean := true ; + begin + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (PRE = '1') then + Q <= '1'; + elsif (C' event and C = '0') then + Q <= D after 100 ps; + end if; + end process; + +end FDP_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdpe.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Asynchronous Preset and Clock Enable +-- /___/ /\ Filename : FDPE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:24 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDPE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDPE is + generic( + INIT : bit := '1' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); +end FDPE; + +architecture FDPE_V of FDPE is +begin + VITALBehavior : process(C, PRE) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (PRE = '1') then + Q <= '1'; + elsif (rising_edge(C)) then + if (CE = '1') then + Q <= D after 100 ps; + end if; + end if; + end process; +end FDPE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdpe_1.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Asynchronous Preset, Clock Enable and Negative-Edge Clock +-- /___/ /\ Filename : FDPE_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:24 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDPE_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDPE_1 is + generic( + INIT : bit := '1' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); +end FDPE_1; + +architecture FDPE_1_V of FDPE_1 is +begin + VITALBehavior : process(C, PRE) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (PRE = '1') then + Q <= '1'; + elsif (falling_edge(C)) then + if (CE = '1') then + Q <= D after 100 ps; + end if; + end if; + end process; +end FDPE_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdr.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Synchronous Reset +-- /___/ /\ Filename : FDR.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:24 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDR ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDR is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic + ); +end FDR; + +architecture FDR_V of FDR is +begin + VITALBehavior : process(C) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (rising_edge(C)) then + if (R = '1') then + Q <= '0' after 100 ps; + else + Q <= D after 100 ps; + end if; + end if; + end process; +end FDR_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdr_1.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Synchronous Reset and Negative-Edge Clock +-- /___/ /\ Filename : FDR_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:24 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDR_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDR_1 is + generic( + INIT : bit := '0' +); + + port( + Q : out STD_ULOGIC; + + C : in STD_ULOGIC; + D : in STD_ULOGIC; + R : in STD_ULOGIC + ); +end FDR_1; + +architecture FDR_1_V of FDR_1 is +begin + VITALBehavior : process(C) + VARIABLE FIRST_TIME : boolean := True ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (falling_edge(C)) then + if (R = '1') then + Q <= '0' after 100 ps; + else + Q <= D after 100 ps; + end if; + end if; +end process; +end FDR_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdre.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Synchronous Reset and Clock Enable +-- /___/ /\ Filename : FDRE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:24 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDRE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDRE is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic + ); +end FDRE; + +architecture FDRE_V of FDRE is +begin + VITALBehavior : process(C) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (rising_edge(C)) then + if (R = '1') then + Q <= '0' after 100 ps; + elsif (CE = '1') then + Q <= D after 100 ps; + end if; + end if; + end process; +end FDRE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdre_1.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Synchronous Reset, Clock Enable and Negative-Edge Clock +-- /___/ /\ Filename : FDRE_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:24 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDRE_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDRE_1 is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic + ); +end FDRE_1; + +architecture FDRE_1_V of FDRE_1 is +begin + VITALBehavior : process(C) + variable FIRST_TIME : boolean := true ; + begin + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (falling_edge(C)) then + if (R = '1') then + Q <= '0' after 100 ps; + elsif (CE = '1') then + Q <= D after 100 ps; + end if; + end if; + end process; + +end FDRE_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdrs.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Synchronous Reset and Set +-- /___/ /\ Filename : FDRS.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:25 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDRS ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDRS is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end FDRS; + +architecture FDRS_V of FDRS is +begin + VITALBehavior : process(C) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (rising_edge(C)) then + if (R = '1') then + Q <= '0' after 100 ps; + elsif (S = '1') then + Q <= '1' after 100 ps; + else + Q <= D after 100 ps; + end if; + end if; + end process; +end FDRS_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdrs_1.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Synchronous Reset and Set and Negative-Edge Clock +-- /___/ /\ Filename : FDRS_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:25 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDRS_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDRS_1 is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end FDRS_1; + +architecture FDRS_1_V of FDRS_1 is +begin + VITALBehavior : process(C) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (falling_edge(C)) then + if (R = '1') then + Q <= '0' after 100 ps; + elsif (S = '1') then + Q <= '1' after 100 ps; + else + Q <= D after 100 ps; + end if; + end if; + end process; +end FDRS_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdrse.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Synchronous Reset and Set and Clock Enable +-- /___/ /\ Filename : FDRSE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:25 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDRSE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDRSE is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end FDRSE; + +architecture FDRSE_V of FDRSE is +begin + VITALBehavior : process(C) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (rising_edge(C)) then + if (R = '1') then + Q <= '0' after 100 ps; + elsif (S = '1') then + Q <= '1' after 100 ps; + elsif (CE = '1') then + Q <= D after 100 ps; + end if; + end if; + end process; +end FDRSE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdrse_1.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Synchronous Reset and Set, Clock Enable and Negative-Edge Clock +-- /___/ /\ Filename : FDRSE_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:25 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDRSE_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDRSE_1 is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end FDRSE_1; + +architecture FDRSE_1_V of FDRSE_1 is +begin + VITALBehavior : process(C) + variable FIRST_TIME : boolean := true ; + begin + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (falling_edge(C)) then + if (R = '1') then + Q <= '0' after 100 ps; + elsif (S = '1') then + Q <= '1' after 100 ps; + elsif (CE = '1') then + Q <= D after 100 ps; + end if; + end if; + end process; +end FDRSE_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fds.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Synchronous Set +-- /___/ /\ Filename : FDS.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:25 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDS ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDS is + generic( + INIT : bit := '1' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + D : in std_ulogic; + S : in std_ulogic + ); +end FDS; + +architecture FDS_V of FDS is +begin + VITALBehavior : process(C) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (rising_edge(C)) then + if (S = '1') then + Q <= '1' after 100 ps; + else + Q <= D after 100 ps; + end if; + end if; + end process; +end FDS_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fds_1.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Synchronous Set and Negative-Edge Clock +-- /___/ /\ Filename : FDS_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:25 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDS_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDS_1 is + generic( + INIT : bit := '1' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + D : in std_ulogic; + S : in std_ulogic + ); +end FDS_1; + +architecture FDS_1_V of FDS_1 is +begin + VITALBehavior : process(C) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (falling_edge(C)) then + if (S = '1') then + Q <= '1' after 100 ps; + else + Q <= D after 100 ps; + end if; + end if; + end process; +end FDS_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdse.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Synchronous Set and Clock Enable +-- /___/ /\ Filename : FDSE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:25 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDSE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDSE is + generic( + INIT : bit := '1' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + S : in std_ulogic + ); +end FDSE; + +architecture FDSE_V of FDSE is +begin + VITALBehavior : process(C) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (rising_edge(C)) then + if (S = '1') then + Q <= '1' after 100 ps; + elsif (CE = '1') then + Q <= D after 100 ps; + end if; + end if; + end process; +end FDSE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fdse_1.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Synchronous Set, Clock Enable and Negative-Edge Clock +-- /___/ /\ Filename : FDSE_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:25 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDSE_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDSE_1 is + generic( + INIT : bit := '1' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + S : in std_ulogic + ); +end FDSE_1; + +architecture FDSE_1_V of FDSE_1 is +begin + VITALBehavior : process(C) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (falling_edge(C)) then + if (S = '1') then + Q <= '1' after 100 ps; + elsif (CE = '1') then + Q <= D after 100 ps; + end if; + end if; + end process; +end FDSE_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/fmap.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / F Function Generator Partitioning Control Symbol +-- /___/ /\ Filename : FMAP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:25 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FMAP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FMAP is + port( + O : in std_ulogic := 'X'; + + I1 : in std_ulogic := 'X'; + I2 : in std_ulogic := 'X'; + I3 : in std_ulogic := 'X'; + I4 : in std_ulogic := 'X' + ); +end FMAP; + +architecture FMAP_V of FMAP is +begin +end FMAP_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/gnd.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / GND Connection +-- /___/ /\ Filename : GND.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:26 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GND ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity GND is + port( + G : out std_ulogic := '0' + ); +end GND; + +architecture GND_V of GND is +begin + + G <= '0'; +end GND_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf.vhd,v 1.10 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer +-- /___/ /\ Filename : IBUF.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:26 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +----- CELL IBUF ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +entity IBUF is + generic( + CAPACITANCE : string := "DONT_CARE"; + IBUF_DELAY_VALUE : string := "0"; + IFD_DELAY_VALUE : string := "AUTO"; + IOSTANDARD : string := "DEFAULT" + ); + + port( + O : out std_ulogic; + + I : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + IBUF : entity is true; +end IBUF; + +architecture IBUF_V of IBUF is +begin + + prcs_init : process + variable FIRST_TIME : boolean := TRUE; + begin + + If(FIRST_TIME = true) then + if((CAPACITANCE = "LOW") or + (CAPACITANCE = "NORMAL") or + (CAPACITANCE = "DONT_CARE")) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The allowed values for CAPACITANCE are LOW, NORMAL or DONT_CARE" + severity Failure; + end if; + +-- + if((IBUF_DELAY_VALUE = "0") or (IBUF_DELAY_VALUE = "1") or + (IBUF_DELAY_VALUE = "2") or (IBUF_DELAY_VALUE = "3") or + (IBUF_DELAY_VALUE = "4") or (IBUF_DELAY_VALUE = "5") or + (IBUF_DELAY_VALUE = "6") or (IBUF_DELAY_VALUE = "7") or + (IBUF_DELAY_VALUE = "8") or (IBUF_DELAY_VALUE = "9") or + (IBUF_DELAY_VALUE = "10") or (IBUF_DELAY_VALUE = "11") or + (IBUF_DELAY_VALUE = "12") or (IBUF_DELAY_VALUE = "13") or + (IBUF_DELAY_VALUE = "14") or (IBUF_DELAY_VALUE = "15") or + (IBUF_DELAY_VALUE = "16")) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The Legal values for IBUF_DELAY_VALUE are 0, 1, 2, ... , or 16. " + severity Failure; + end if; + +-- + if((IFD_DELAY_VALUE = "AUTO") or (IFD_DELAY_VALUE = "auto") or + (IFD_DELAY_VALUE = "0") or (IFD_DELAY_VALUE = "1") or + (IFD_DELAY_VALUE = "2") or (IFD_DELAY_VALUE = "3") or + (IFD_DELAY_VALUE = "4") or (IFD_DELAY_VALUE = "5") or + (IFD_DELAY_VALUE = "6") or (IFD_DELAY_VALUE = "7") or + (IFD_DELAY_VALUE = "8")) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The Legal values for IFD_DELAY_VALUE are AUTO, 0, 1, ... , or 8" + severity Failure; + end if; + + end if; + wait; + end process prcs_init; + + + O <= TO_X01(I) after 0 ps; +end IBUF_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_agp.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with AGP I/O Standard +-- /___/ /\ Filename : IBUF_AGP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:26 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_AGP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_AGP is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_AGP; + +architecture IBUF_AGP_V of IBUF_AGP is +begin + O <= TO_X01(I); +end IBUF_AGP_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_ctt.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with CTT I/O Standard +-- /___/ /\ Filename : IBUF_CTT.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:26 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_CTT ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_CTT is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_CTT; + +architecture IBUF_CTT_V of IBUF_CTT is +begin + O <= TO_X01(I); +end IBUF_CTT_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_gtl.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with GTL I/O Standard +-- /___/ /\ Filename : IBUF_GTL.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:26 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_GTL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_GTL is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_GTL; + +architecture IBUF_GTL_V of IBUF_GTL is +begin + O <= TO_X01(I); +end IBUF_GTL_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_gtl_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with GTL_DCI I/O Standard +-- /___/ /\ Filename : IBUF_GTL_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:26 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_GTL_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_GTL_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_GTL_DCI; + +architecture IBUF_GTL_DCI_V of IBUF_GTL_DCI is +begin + O <= TO_X01(I); +end IBUF_GTL_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_gtlp.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with GTLP I/O Standard +-- /___/ /\ Filename : IBUF_GTLP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:27 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_GTLP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_GTLP is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_GTLP; + +architecture IBUF_GTLP_V of IBUF_GTLP is +begin + O <= TO_X01(I); +end IBUF_GTLP_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_gtlp_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with GTLP_DCI I/O Standard +-- /___/ /\ Filename : IBUF_GTLP_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:27 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_GTLP_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_GTLP_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_GTLP_DCI; + +architecture IBUF_GTLP_DCI_V of IBUF_GTLP_DCI is +begin + O <= TO_X01(I); +end IBUF_GTLP_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_i.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with HSTL_I I/O Standard +-- /___/ /\ Filename : IBUF_HSTL_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:27 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_HSTL_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_HSTL_I is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_HSTL_I; + +architecture IBUF_HSTL_I_V of IBUF_HSTL_I is +begin + O <= TO_X01(I); +end IBUF_HSTL_I_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_i_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with HSTL_I_18 I/O Standard +-- /___/ /\ Filename : IBUF_HSTL_I_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:27 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_HSTL_I_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_HSTL_I_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_HSTL_I_18; + +architecture IBUF_HSTL_I_18_V of IBUF_HSTL_I_18 is +begin + O <= TO_X01(I); +end IBUF_HSTL_I_18_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_i_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with HSTL_I_DCI I/O Standard +-- /___/ /\ Filename : IBUF_HSTL_I_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:27 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_HSTL_I_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_HSTL_I_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_HSTL_I_DCI; + +architecture IBUF_HSTL_I_DCI_V of IBUF_HSTL_I_DCI is +begin + O <= TO_X01(I); +end IBUF_HSTL_I_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_i_dci_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with HSTL_I_DCI_18 I/O Standard +-- /___/ /\ Filename : IBUF_HSTL_I_DCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:27 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_HSTL_I_DCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_HSTL_I_DCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_HSTL_I_DCI_18; + +architecture IBUF_HSTL_I_DCI_18_V of IBUF_HSTL_I_DCI_18 is +begin + O <= TO_X01(I); +end IBUF_HSTL_I_DCI_18_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_ii.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with HSTL_II I/O Standard +-- /___/ /\ Filename : IBUF_HSTL_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:27 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_HSTL_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_HSTL_II is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_HSTL_II; + +architecture IBUF_HSTL_II_V of IBUF_HSTL_II is +begin + O <= TO_X01(I); +end IBUF_HSTL_II_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_ii_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with HSTL_II_18 I/O Standard +-- /___/ /\ Filename : IBUF_HSTL_II_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:27 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_HSTL_II_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_HSTL_II_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_HSTL_II_18; + +architecture IBUF_HSTL_II_18_V of IBUF_HSTL_II_18 is +begin + O <= TO_X01(I); +end IBUF_HSTL_II_18_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_ii_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with HSTL_II_DCI I/O Standard +-- /___/ /\ Filename : IBUF_HSTL_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:27 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_HSTL_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_HSTL_II_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_HSTL_II_DCI; + +architecture IBUF_HSTL_II_DCI_V of IBUF_HSTL_II_DCI is +begin + O <= TO_X01(I); +end IBUF_HSTL_II_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_ii_dci_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with HSTL_II_DCI_18 I/O Standard +-- /___/ /\ Filename : IBUF_HSTL_II_DCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:28 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_HSTL_II_DCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_HSTL_II_DCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_HSTL_II_DCI_18; + +architecture IBUF_HSTL_II_DCI_18_V of IBUF_HSTL_II_DCI_18 is +begin + O <= TO_X01(I); +end IBUF_HSTL_II_DCI_18_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_iii.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with HSTL_III I/O Standard +-- /___/ /\ Filename : IBUF_HSTL_III.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:28 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_HSTL_III ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_HSTL_III is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_HSTL_III; + +architecture IBUF_HSTL_III_V of IBUF_HSTL_III is +begin + O <= TO_X01(I); +end IBUF_HSTL_III_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_iii_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with HSTL_III_18 I/O Standard +-- /___/ /\ Filename : IBUF_HSTL_III_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:28 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_HSTL_III_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_HSTL_III_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_HSTL_III_18; + +architecture IBUF_HSTL_III_18_V of IBUF_HSTL_III_18 is +begin + O <= TO_X01(I); +end IBUF_HSTL_III_18_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_iii_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with HSTL_III_DCI I/O Standard +-- /___/ /\ Filename : IBUF_HSTL_III_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:28 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_HSTL_III_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_HSTL_III_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_HSTL_III_DCI; + +architecture IBUF_HSTL_III_DCI_V of IBUF_HSTL_III_DCI is +begin + O <= TO_X01(I); +end IBUF_HSTL_III_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_iii_dci_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with HSTL_III_DCI_18 I/O Standard +-- /___/ /\ Filename : IBUF_HSTL_III_DCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:28 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_HSTL_III_DCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_HSTL_III_DCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_HSTL_III_DCI_18; + +architecture IBUF_HSTL_III_DCI_18_V of IBUF_HSTL_III_DCI_18 is +begin + O <= TO_X01(I); +end IBUF_HSTL_III_DCI_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_iv.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with HSTL_IV I/O Standard +-- /___/ /\ Filename : IBUF_HSTL_IV.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:28 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_HSTL_IV ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_HSTL_IV is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_HSTL_IV; + +architecture IBUF_HSTL_IV_V of IBUF_HSTL_IV is +begin + O <= TO_X01(I); +end IBUF_HSTL_IV_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_iv_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with HSTL_IV_18 I/O Standard +-- /___/ /\ Filename : IBUF_HSTL_IV_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:28 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_HSTL_IV_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_HSTL_IV_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_HSTL_IV_18; + +architecture IBUF_HSTL_IV_18_V of IBUF_HSTL_IV_18 is +begin + O <= TO_X01(I); +end IBUF_HSTL_IV_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_iv_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with HSTL_IV_DCI I/O Standard +-- /___/ /\ Filename : IBUF_HSTL_IV_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:28 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_HSTL_IV_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_HSTL_IV_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_HSTL_IV_DCI; + +architecture IBUF_HSTL_IV_DCI_V of IBUF_HSTL_IV_DCI is +begin + O <= TO_X01(I); +end IBUF_HSTL_IV_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_hstl_iv_dci_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with HSTL_IV_DCI_18 I/O Standard +-- /___/ /\ Filename : IBUF_HSTL_IV_DCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:28 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_HSTL_IV_DCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_HSTL_IV_DCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_HSTL_IV_DCI_18; + +architecture IBUF_HSTL_IV_DCI_18_V of IBUF_HSTL_IV_DCI_18 is +begin + O <= TO_X01(I); +end IBUF_HSTL_IV_DCI_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvcmos12.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with LVCMOS12 I/O Standard +-- /___/ /\ Filename : IBUF_LVCMOS12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:28 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_LVCMOS12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_LVCMOS12 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_LVCMOS12; + +architecture IBUF_LVCMOS12_V of IBUF_LVCMOS12 is +begin + O <= TO_X01(I); +end IBUF_LVCMOS12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvcmos15.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with LVCMOS15 I/O Standard +-- /___/ /\ Filename : IBUF_LVCMOS15.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:29 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_LVCMOS15 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_LVCMOS15 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_LVCMOS15; + +architecture IBUF_LVCMOS15_V of IBUF_LVCMOS15 is +begin + O <= TO_X01(I); +end IBUF_LVCMOS15_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvcmos18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with LVCMOS18 I/O Standard +-- /___/ /\ Filename : IBUF_LVCMOS18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:29 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_LVCMOS18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_LVCMOS18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_LVCMOS18; + +architecture IBUF_LVCMOS18_V of IBUF_LVCMOS18 is +begin + O <= TO_X01(I); +end IBUF_LVCMOS18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvcmos2.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with LVCMOS2 I/O Standard +-- /___/ /\ Filename : IBUF_LVCMOS2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:29 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_LVCMOS2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_LVCMOS2 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_LVCMOS2; + +architecture IBUF_LVCMOS2_V of IBUF_LVCMOS2 is +begin + O <= TO_X01(I); +end IBUF_LVCMOS2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvcmos25.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with LVCMOS25 I/O Standard +-- /___/ /\ Filename : IBUF_LVCMOS25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:29 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_LVCMOS25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_LVCMOS25 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_LVCMOS25; + +architecture IBUF_LVCMOS25_V of IBUF_LVCMOS25 is +begin + O <= TO_X01(I); +end IBUF_LVCMOS25_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvcmos33.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with LVCMOS33 I/O Standard +-- /___/ /\ Filename : IBUF_LVCMOS33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:29 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_LVCMOS33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_LVCMOS33 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_LVCMOS33; + +architecture IBUF_LVCMOS33_V of IBUF_LVCMOS33 is +begin + O <= TO_X01(I); +end IBUF_LVCMOS33_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvdci_15.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with LVDCI_15 I/O Standard +-- /___/ /\ Filename : IBUF_LVDCI_15.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:29 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_LVDCI_15 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_LVDCI_15 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_LVDCI_15; + +architecture IBUF_LVDCI_15_V of IBUF_LVDCI_15 is +begin + O <= TO_X01(I); +end IBUF_LVDCI_15_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvdci_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with LVDCI_18 I/O Standard +-- /___/ /\ Filename : IBUF_LVDCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:29 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_LVDCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_LVDCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_LVDCI_18; + +architecture IBUF_LVDCI_18_V of IBUF_LVDCI_18 is +begin + O <= TO_X01(I); +end IBUF_LVDCI_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvdci_25.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with LVDCI_25 I/O Standard +-- /___/ /\ Filename : IBUF_LVDCI_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:29 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_LVDCI_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_LVDCI_25 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_LVDCI_25; + +architecture IBUF_LVDCI_25_V of IBUF_LVDCI_25 is +begin + O <= TO_X01(I); +end IBUF_LVDCI_25_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvdci_33.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with LVDCI_33 I/O Standard +-- /___/ /\ Filename : IBUF_LVDCI_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:29 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_LVDCI_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_LVDCI_33 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_LVDCI_33; + +architecture IBUF_LVDCI_33_V of IBUF_LVDCI_33 is +begin + O <= TO_X01(I); +end IBUF_LVDCI_33_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvdci_dv2_15.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with LVDCI_DV2_15 I/O Standard +-- /___/ /\ Filename : IBUF_LVDCI_DV2_15.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:30 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_LVDCI_DV2_15 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_LVDCI_DV2_15 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_LVDCI_DV2_15; + +architecture IBUF_LVDCI_DV2_15_V of IBUF_LVDCI_DV2_15 is +begin + O <= TO_X01(I); +end IBUF_LVDCI_DV2_15_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvdci_dv2_18.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with LVDCI_DV2_18 I/O Standard +-- /___/ /\ Filename : IBUF_LVDCI_DV2_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:30 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_LVDCI_DV2_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_LVDCI_DV2_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_LVDCI_DV2_18; + +architecture IBUF_LVDCI_DV2_18_V of IBUF_LVDCI_DV2_18 is +begin + O <= TO_X01(I); +end IBUF_LVDCI_DV2_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvdci_dv2_25.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with LVDCI_DV2_25 I/O Standard +-- /___/ /\ Filename : IBUF_LVDCI_DV2_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:30 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_LVDCI_DV2_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_LVDCI_DV2_25 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_LVDCI_DV2_25; + +architecture IBUF_LVDCI_DV2_25_V of IBUF_LVDCI_DV2_25 is +begin + O <= TO_X01(I); +end IBUF_LVDCI_DV2_25_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvdci_dv2_33.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with LVDCI_DV2_33 I/O Standard +-- /___/ /\ Filename : IBUF_LVDCI_DV2_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:30 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_LVDCI_DV2_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_LVDCI_DV2_33 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_LVDCI_DV2_33; + +architecture IBUF_LVDCI_DV2_33_V of IBUF_LVDCI_DV2_33 is +begin + O <= TO_X01(I); +end IBUF_LVDCI_DV2_33_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvds.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with LVDS I/O Standard +-- /___/ /\ Filename : IBUF_LVDS.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:30 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_LVDS ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_LVDS is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_LVDS; + +architecture IBUF_LVDS_V of IBUF_LVDS is +begin + O <= TO_X01(I); +end IBUF_LVDS_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvpecl.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with LVPECL I/O Standard +-- /___/ /\ Filename : IBUF_LVPECL.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:30 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_LVPECL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_LVPECL is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_LVPECL; + +architecture IBUF_LVPECL_V of IBUF_LVPECL is +begin + O <= TO_X01(I); +end IBUF_LVPECL_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_lvttl.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with LVTTL I/O Standard +-- /___/ /\ Filename : IBUF_LVTTL.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:30 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_LVTTL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_LVTTL is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_LVTTL; + +architecture IBUF_LVTTL_V of IBUF_LVTTL is +begin + O <= TO_X01(I); +end IBUF_LVTTL_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_pci33_3.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with PCI33_3 I/O Standard +-- /___/ /\ Filename : IBUF_PCI33_3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:30 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_PCI33_3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_PCI33_3 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_PCI33_3; + +architecture IBUF_PCI33_3_V of IBUF_PCI33_3 is +begin + O <= TO_X01(I); +end IBUF_PCI33_3_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_pci33_5.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with PCI33_5 I/O Standard +-- /___/ /\ Filename : IBUF_PCI33_5.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:30 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_PCI33_5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_PCI33_5 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_PCI33_5; + +architecture IBUF_PCI33_5_V of IBUF_PCI33_5 is +begin + O <= TO_X01(I); +end IBUF_PCI33_5_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_pci66_3.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with PCI66_3 I/O Standard +-- /___/ /\ Filename : IBUF_PCI66_3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:31 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_PCI66_3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_PCI66_3 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_PCI66_3; + +architecture IBUF_PCI66_3_V of IBUF_PCI66_3 is +begin + O <= TO_X01(I); +end IBUF_PCI66_3_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_pcix.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with PCIX I/O Standard +-- /___/ /\ Filename : IBUF_PCIX.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:31 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_PCIX ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_PCIX is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_PCIX; + +architecture IBUF_PCIX_V of IBUF_PCIX is +begin + O <= TO_X01(I); +end IBUF_PCIX_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_pcix66_3.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with PCIX66_3 I/O Standard +-- /___/ /\ Filename : IBUF_PCIX66_3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:31 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_PCIX66_3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_PCIX66_3 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_PCIX66_3; + +architecture IBUF_PCIX66_3_V of IBUF_PCIX66_3 is +begin + O <= TO_X01(I); +end IBUF_PCIX66_3_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl18_i.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with SSTL18_I I/O Standard +-- /___/ /\ Filename : IBUF_SSTL18_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:31 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_SSTL18_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_SSTL18_I is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_SSTL18_I; + +architecture IBUF_SSTL18_I_V of IBUF_SSTL18_I is +begin + O <= TO_X01(I); +end IBUF_SSTL18_I_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl18_i_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with SSTL18_I_DCI I/O Standard +-- /___/ /\ Filename : IBUF_SSTL18_I_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:31 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_SSTL18_I_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_SSTL18_I_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_SSTL18_I_DCI; + +architecture IBUF_SSTL18_I_DCI_V of IBUF_SSTL18_I_DCI is +begin + O <= TO_X01(I); +end IBUF_SSTL18_I_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl18_ii.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with SSTL18_II I/O Standard +-- /___/ /\ Filename : IBUF_SSTL18_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:31 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_SSTL18_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_SSTL18_II is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_SSTL18_II; + +architecture IBUF_SSTL18_II_V of IBUF_SSTL18_II is +begin + O <= TO_X01(I); +end IBUF_SSTL18_II_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl18_ii_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with SSTL18_II_DCI I/O Standard +-- /___/ /\ Filename : IBUF_SSTL18_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:31 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_SSTL18_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_SSTL18_II_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_SSTL18_II_DCI; + +architecture IBUF_SSTL18_II_DCI_V of IBUF_SSTL18_II_DCI is +begin + O <= TO_X01(I); +end IBUF_SSTL18_II_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl2_i.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with SSTL2_I I/O Standard +-- /___/ /\ Filename : IBUF_SSTL2_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:31 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_SSTL2_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_SSTL2_I is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_SSTL2_I; + +architecture IBUF_SSTL2_I_V of IBUF_SSTL2_I is +begin + O <= TO_X01(I); +end IBUF_SSTL2_I_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl2_i_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with SSTL2_I_DCI I/O Standard +-- /___/ /\ Filename : IBUF_SSTL2_I_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:32 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_SSTL2_I_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_SSTL2_I_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_SSTL2_I_DCI; + +architecture IBUF_SSTL2_I_DCI_V of IBUF_SSTL2_I_DCI is +begin + O <= TO_X01(I); +end IBUF_SSTL2_I_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl2_ii.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with SSTL2_II I/O Standard +-- /___/ /\ Filename : IBUF_SSTL2_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:32 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_SSTL2_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_SSTL2_II is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_SSTL2_II; + +architecture IBUF_SSTL2_II_V of IBUF_SSTL2_II is +begin + O <= TO_X01(I); +end IBUF_SSTL2_II_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl2_ii_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with SSTL2_II_DCI I/O Standard +-- /___/ /\ Filename : IBUF_SSTL2_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:32 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_SSTL2_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_SSTL2_II_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_SSTL2_II_DCI; + +architecture IBUF_SSTL2_II_DCI_V of IBUF_SSTL2_II_DCI is +begin + O <= TO_X01(I); +end IBUF_SSTL2_II_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl3_i.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with SSTL3_I I/O Standard +-- /___/ /\ Filename : IBUF_SSTL3_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:32 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_SSTL3_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_SSTL3_I is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_SSTL3_I; + +architecture IBUF_SSTL3_I_V of IBUF_SSTL3_I is +begin + O <= TO_X01(I); +end IBUF_SSTL3_I_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl3_i_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with SSTL3_I_DCI I/O Standard +-- /___/ /\ Filename : IBUF_SSTL3_I_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:32 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_SSTL3_I_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_SSTL3_I_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_SSTL3_I_DCI; + +architecture IBUF_SSTL3_I_DCI_V of IBUF_SSTL3_I_DCI is +begin + O <= TO_X01(I); +end IBUF_SSTL3_I_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl3_ii.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with SSTL3_II I/O Standard +-- /___/ /\ Filename : IBUF_SSTL3_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:32 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_SSTL3_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_SSTL3_II is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_SSTL3_II; + +architecture IBUF_SSTL3_II_V of IBUF_SSTL3_II is +begin + O <= TO_X01(I); +end IBUF_SSTL3_II_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibuf_sstl3_ii_dci.vhd,v 1.4 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Buffer with SSTL3_II_DCI I/O Standard +-- /___/ /\ Filename : IBUF_SSTL3_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:32 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUF_SSTL3_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUF_SSTL3_II_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUF_SSTL3_II_DCI; + +architecture IBUF_SSTL3_II_DCI_V of IBUF_SSTL3_II_DCI is +begin + O <= TO_X01(I); +end IBUF_SSTL3_II_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds.vhd,v 1.10 2006/07/21 20:50:05 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Buffer +-- /___/ /\ Filename : IBUFDS.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:32 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/10/06 - CR 222428 -- added H(pullup) and L(pulldown) usage +-- 07/19/06 - Add else to handle x case for o_out (CR 234718). +-- End Revision + + +----- CELL IBUFDS ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFDS is + generic( + CAPACITANCE : string := "DONT_CARE"; + DIFF_TERM : boolean := FALSE; + IBUF_DELAY_VALUE : string := "0"; + IFD_DELAY_VALUE : string := "AUTO"; + IOSTANDARD : string := "DEFAULT" + ); + + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFDS; + +architecture IBUFDS_V of IBUFDS is +begin + prcs_init : process + variable FIRST_TIME : boolean := TRUE; + begin + + If(FIRST_TIME = true) then + + if((CAPACITANCE = "LOW") or + (CAPACITANCE = "NORMAL") or + (CAPACITANCE = "DONT_CARE")) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The Legal values for CAPACITANCE are LOW, NORMAL or DONT_CARE" + severity Failure; + end if; + + if((DIFF_TERM = TRUE) or + (DIFF_TERM = FALSE)) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The Legal values for DIFF_TERM are TRUE or FALSE" + severity Failure; + end if; + +-- + if((IBUF_DELAY_VALUE = "0") or (IBUF_DELAY_VALUE = "1") or + (IBUF_DELAY_VALUE = "2") or (IBUF_DELAY_VALUE = "3") or + (IBUF_DELAY_VALUE = "4") or (IBUF_DELAY_VALUE = "5") or + (IBUF_DELAY_VALUE = "6") or (IBUF_DELAY_VALUE = "7") or + (IBUF_DELAY_VALUE = "8") or (IBUF_DELAY_VALUE = "9") or + (IBUF_DELAY_VALUE = "10") or (IBUF_DELAY_VALUE = "11") or + (IBUF_DELAY_VALUE = "12") or (IBUF_DELAY_VALUE = "13") or + (IBUF_DELAY_VALUE = "14") or (IBUF_DELAY_VALUE = "15") or + (IBUF_DELAY_VALUE = "16")) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The Legal values for IBUF_DELAY_VALUE are 0, 1, 2, ... , or 16. " + severity Failure; + end if; + +-- + if((IFD_DELAY_VALUE = "AUTO") or (IFD_DELAY_VALUE = "auto") or + (IFD_DELAY_VALUE = "0") or (IFD_DELAY_VALUE = "1") or + (IFD_DELAY_VALUE = "2") or (IFD_DELAY_VALUE = "3") or + (IFD_DELAY_VALUE = "4") or (IFD_DELAY_VALUE = "5") or + (IFD_DELAY_VALUE = "6") or (IFD_DELAY_VALUE = "7") or + (IFD_DELAY_VALUE = "8")) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The Legal values for IFD_DELAY_VALUE are AUTO, 0, 1, ... , or 8" + severity Failure; + end if; + + end if; + + wait; + end process prcs_init; + + VitalBehavior : process (I, IB) + begin +-- if ((I = '1') and (IB = '0')) then +-- O <= TO_X01(I); +-- elsif ((I = '0') and (IB = '1')) then +-- O <= TO_X01(I); +-- end if; + if ( (((I = '1') or (I = 'H')) and ((IB = '0') or (IB = 'L'))) or + (((I = '0') or (I = 'L')) and ((IB = '1') or (IB = 'H'))) ) then + O <= TO_X01(I); + elsif (I = 'Z' or I = 'X' or IB = 'Z' or IB ='X') then + O <= 'X'; + end if; + + end process; +end IBUFDS_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_blvds_25.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Buffer with BLVDS_25 I/O Standard +-- /___/ /\ Filename : IBUFDS_BLVDS_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:32 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFDS_BLVDS_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFDS_BLVDS_25 is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFDS_BLVDS_25; + +architecture IBUFDS_BLVDS_25_V of IBUFDS_BLVDS_25 is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFDS_BLVDS_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_diff_out.vhd,v 1.5 2005/07/23 00:24:21 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Buffer with Differential Outputs +-- /___/ /\ Filename : IBUFDS_DIFF_OUT.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:33 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFDS_DIFF_OUT ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFDS_DIFF_OUT is + generic( + IOSTANDARD : string := "LVDS_25" + ); + + port( + O : out STD_ULOGIC; + OB : out STD_ULOGIC; + + I : in STD_ULOGIC; + IB : in STD_ULOGIC + ); +end IBUFDS_DIFF_OUT; + +architecture IBUFDS_DIFF_OUT_V of IBUFDS_DIFF_OUT is +begin + VITALBehavior : process (I, IB) + begin + if (I /= IB ) then + O <= TO_X01(I); + OB <= TO_X01(NOT I); + end if; +end process; +end IBUFDS_DIFF_OUT_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_ldt_25.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Buffer with LDT_25 I/O Standard +-- /___/ /\ Filename : IBUFDS_LDT_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:33 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFDS_LDT_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFDS_LDT_25 is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFDS_LDT_25; + +architecture IBUFDS_LDT_25_V of IBUFDS_LDT_25 is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFDS_LDT_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvds_25.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Buffer with LVDS_25 I/O Standard +-- /___/ /\ Filename : IBUFDS_LVDS_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:33 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFDS_LVDS_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFDS_LVDS_25 is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFDS_LVDS_25; + +architecture IBUFDS_LVDS_25_V of IBUFDS_LVDS_25 is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFDS_LVDS_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvds_25_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Buffer with LVDS_25_DCI I/O Standard +-- /___/ /\ Filename : IBUFDS_LVDS_25_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:33 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFDS_LVDS_25_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFDS_LVDS_25_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFDS_LVDS_25_DCI; + +architecture IBUFDS_LVDS_25_DCI_V of IBUFDS_LVDS_25_DCI is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFDS_LVDS_25_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvds_33.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Buffer with LVDS_33 I/O Standard +-- /___/ /\ Filename : IBUFDS_LVDS_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:33 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFDS_LVDS_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFDS_LVDS_33 is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFDS_LVDS_33; + +architecture IBUFDS_LVDS_33_V of IBUFDS_LVDS_33 is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFDS_LVDS_33_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvds_33_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Buffer with LVDS_33_DCI I/O Standard +-- /___/ /\ Filename : IBUFDS_LVDS_33_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:33 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFDS_LVDS_33_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFDS_LVDS_33_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFDS_LVDS_33_DCI; + +architecture IBUFDS_LVDS_33_DCI_V of IBUFDS_LVDS_33_DCI is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFDS_LVDS_33_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvdsext_25.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Buffer with LVDSEXT_25 I/O Standard +-- /___/ /\ Filename : IBUFDS_LVDSEXT_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:33 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFDS_LVDSEXT_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFDS_LVDSEXT_25 is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFDS_LVDSEXT_25; + +architecture IBUFDS_LVDSEXT_25_V of IBUFDS_LVDSEXT_25 is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFDS_LVDSEXT_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvdsext_25_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Buffer with LVDSEXT_25_DCI I/O Standard +-- /___/ /\ Filename : IBUFDS_LVDSEXT_25_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:33 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFDS_LVDSEXT_25_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFDS_LVDSEXT_25_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFDS_LVDSEXT_25_DCI; + +architecture IBUFDS_LVDSEXT_25_DCI_V of IBUFDS_LVDSEXT_25_DCI is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFDS_LVDSEXT_25_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvdsext_33.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Buffer with LVDSEXT_33 I/O Standard +-- /___/ /\ Filename : IBUFDS_LVDSEXT_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:33 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFDS_LVDSEXT_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFDS_LVDSEXT_33 is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFDS_LVDSEXT_33; + +architecture IBUFDS_LVDSEXT_33_V of IBUFDS_LVDSEXT_33 is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFDS_LVDSEXT_33_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvdsext_33_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Buffer with LVDSEXT_33_DCI I/O Standard +-- /___/ /\ Filename : IBUFDS_LVDSEXT_33_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:33 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFDS_LVDSEXT_33_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFDS_LVDSEXT_33_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFDS_LVDSEXT_33_DCI; + +architecture IBUFDS_LVDSEXT_33_DCI_V of IBUFDS_LVDSEXT_33_DCI is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFDS_LVDSEXT_33_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvpecl_25.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Buffer with LVPECL_25 I/O Standard +-- /___/ /\ Filename : IBUFDS_LVPECL_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:34 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFDS_LVPECL_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFDS_LVPECL_25 is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFDS_LVPECL_25; + +architecture IBUFDS_LVPECL_25_V of IBUFDS_LVPECL_25 is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFDS_LVPECL_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_lvpecl_33.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Buffer with LVPECL_33 I/O Standard +-- /___/ /\ Filename : IBUFDS_LVPECL_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:34 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFDS_LVPECL_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFDS_LVPECL_33 is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFDS_LVPECL_33; + +architecture IBUFDS_LVPECL_33_V of IBUFDS_LVPECL_33 is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFDS_LVPECL_33_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufds_ulvds_25.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Buffer with ULVDS_25 I/O Standard +-- /___/ /\ Filename : IBUFDS_ULVDS_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:34 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFDS_ULVDS_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFDS_ULVDS_25 is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFDS_ULVDS_25; + +architecture IBUFDS_ULVDS_25_V of IBUFDS_ULVDS_25 is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFDS_ULVDS_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg.vhd,v 1.8 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer +-- /___/ /\ Filename : IBUFG.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:34 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG is + generic( + CAPACITANCE : string := "DONT_CARE"; + IBUF_DELAY_VALUE : string := "0"; + IOSTANDARD : string := "DEFAULT" + ); + + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG; + +architecture IBUFG_V of IBUFG is +begin + prcs_init : process + variable FIRST_TIME : boolean := TRUE; + begin + + If(FIRST_TIME = true) then + if((CAPACITANCE = "LOW") or + (CAPACITANCE = "NORMAL") or + (CAPACITANCE = "DONT_CARE")) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The Legal values for CAPACITANCE are LOW, NORMAL or DONT_CARE" + severity Failure; + end if; +-- + if((IBUF_DELAY_VALUE = "0") or (IBUF_DELAY_VALUE = "1") or + (IBUF_DELAY_VALUE = "2") or (IBUF_DELAY_VALUE = "3") or + (IBUF_DELAY_VALUE = "4") or (IBUF_DELAY_VALUE = "5") or + (IBUF_DELAY_VALUE = "6") or (IBUF_DELAY_VALUE = "7") or + (IBUF_DELAY_VALUE = "8") or (IBUF_DELAY_VALUE = "9") or + (IBUF_DELAY_VALUE = "10") or (IBUF_DELAY_VALUE = "11") or + (IBUF_DELAY_VALUE = "12") or (IBUF_DELAY_VALUE = "13") or + (IBUF_DELAY_VALUE = "14") or (IBUF_DELAY_VALUE = "15") or + (IBUF_DELAY_VALUE = "16")) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The Legal values for IBUF_DELAY_VALUE are 0, 1, 2, ... , or 16. " + severity Failure; + end if; + + end if; + wait; + end process prcs_init; + + O <= TO_X01(I); +end IBUFG_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_agp.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with AGP I/O Standard +-- /___/ /\ Filename : IBUFG_AGP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:34 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_AGP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_AGP is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_AGP; + +architecture IBUFG_AGP_V of IBUFG_AGP is +begin + O <= TO_X01(I); +end IBUFG_AGP_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_ctt.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with CTT I/O Standard +-- /___/ /\ Filename : IBUFG_CTT.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:34 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_CTT ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_CTT is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_CTT; + +architecture IBUFG_CTT_V of IBUFG_CTT is +begin + O <= TO_X01(I); +end IBUFG_CTT_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_gtl.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with GTL I/O Standard +-- /___/ /\ Filename : IBUFG_GTL.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:34 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_GTL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_GTL is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_GTL; + +architecture IBUFG_GTL_V of IBUFG_GTL is +begin + O <= TO_X01(I); +end IBUFG_GTL_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_gtl_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with GTL_DCI I/O Standard +-- /___/ /\ Filename : IBUFG_GTL_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:34 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_GTL_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_GTL_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_GTL_DCI; + +architecture IBUFG_GTL_DCI_V of IBUFG_GTL_DCI is +begin + O <= TO_X01(I); +end IBUFG_GTL_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_gtlp.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with GTLP I/O Standard +-- /___/ /\ Filename : IBUFG_GTLP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:34 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_GTLP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_GTLP is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_GTLP; + +architecture IBUFG_GTLP_V of IBUFG_GTLP is +begin + O <= TO_X01(I); +end IBUFG_GTLP_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_gtlp_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with GTLP_DCI I/O Standard +-- /___/ /\ Filename : IBUFG_GTLP_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:35 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_GTLP_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_GTLP_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_GTLP_DCI; + +architecture IBUFG_GTLP_DCI_V of IBUFG_GTLP_DCI is +begin + O <= TO_X01(I); +end IBUFG_GTLP_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_i.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with HSTL_I I/O Standard +-- /___/ /\ Filename : IBUFG_HSTL_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:35 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_HSTL_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_HSTL_I is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_HSTL_I; + +architecture IBUFG_HSTL_I_V of IBUFG_HSTL_I is +begin + O <= TO_X01(I); +end IBUFG_HSTL_I_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_i_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with HSTL_I_18 I/O Standard +-- /___/ /\ Filename : IBUFG_HSTL_I_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:35 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_HSTL_I_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_HSTL_I_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_HSTL_I_18; + +architecture IBUFG_HSTL_I_18_V of IBUFG_HSTL_I_18 is +begin + O <= TO_X01(I); +end IBUFG_HSTL_I_18_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_i_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with HSTL_I_DCI I/O Standard +-- /___/ /\ Filename : IBUFG_HSTL_I_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:35 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_HSTL_I_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_HSTL_I_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_HSTL_I_DCI; + +architecture IBUFG_HSTL_I_DCI_V of IBUFG_HSTL_I_DCI is +begin + O <= TO_X01(I); +end IBUFG_HSTL_I_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_i_dci_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with HSTL_I_DCI_18 I/O Standard +-- /___/ /\ Filename : IBUFG_HSTL_I_DCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:35 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_HSTL_I_DCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_HSTL_I_DCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_HSTL_I_DCI_18; + +architecture IBUFG_HSTL_I_DCI_18_V of IBUFG_HSTL_I_DCI_18 is +begin + O <= TO_X01(I); +end IBUFG_HSTL_I_DCI_18_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_ii.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with HSTL_II I/O Standard +-- /___/ /\ Filename : IBUFG_HSTL_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:35 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_HSTL_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_HSTL_II is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_HSTL_II; + +architecture IBUFG_HSTL_II_V of IBUFG_HSTL_II is +begin + O <= TO_X01(I); +end IBUFG_HSTL_II_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_ii_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with HSTL_II_18 I/O Standard +-- /___/ /\ Filename : IBUFG_HSTL_II_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:35 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_HSTL_II_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_HSTL_II_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_HSTL_II_18; + +architecture IBUFG_HSTL_II_18_V of IBUFG_HSTL_II_18 is +begin + O <= TO_X01(I); +end IBUFG_HSTL_II_18_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_ii_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with HSTL_II_DCI I/O Standard +-- /___/ /\ Filename : IBUFG_HSTL_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:35 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_HSTL_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_HSTL_II_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_HSTL_II_DCI; + +architecture IBUFG_HSTL_II_DCI_V of IBUFG_HSTL_II_DCI is +begin + O <= TO_X01(I); +end IBUFG_HSTL_II_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_ii_dci_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with HSTL_II_DCI_18 I/O Standard +-- /___/ /\ Filename : IBUFG_HSTL_II_DCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:35 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_HSTL_II_DCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_HSTL_II_DCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_HSTL_II_DCI_18; + +architecture IBUFG_HSTL_II_DCI_18_V of IBUFG_HSTL_II_DCI_18 is +begin + O <= TO_X01(I); +end IBUFG_HSTL_II_DCI_18_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_iii.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with HSTL_III I/O Standard +-- /___/ /\ Filename : IBUFG_HSTL_III.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:36 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_HSTL_III ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_HSTL_III is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_HSTL_III; + +architecture IBUFG_HSTL_III_V of IBUFG_HSTL_III is +begin + O <= TO_X01(I); +end IBUFG_HSTL_III_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_iii_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with HSTL_III_18 I/O Standard +-- /___/ /\ Filename : IBUFG_HSTL_III_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:36 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_HSTL_III_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_HSTL_III_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_HSTL_III_18; + +architecture IBUFG_HSTL_III_18_V of IBUFG_HSTL_III_18 is +begin + O <= TO_X01(I); +end IBUFG_HSTL_III_18_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_iii_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with HSTL_III_DCI I/O Standard +-- /___/ /\ Filename : IBUFG_HSTL_III_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:36 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_HSTL_III_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_HSTL_III_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_HSTL_III_DCI; + +architecture IBUFG_HSTL_III_DCI_V of IBUFG_HSTL_III_DCI is +begin + O <= TO_X01(I); +end IBUFG_HSTL_III_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_iii_dci_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with HSTL_III_DCI_18 I/O Standard +-- /___/ /\ Filename : IBUFG_HSTL_III_DCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:36 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_HSTL_III_DCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_HSTL_III_DCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_HSTL_III_DCI_18; + +architecture IBUFG_HSTL_III_DCI_18_V of IBUFG_HSTL_III_DCI_18 is +begin + O <= TO_X01(I); +end IBUFG_HSTL_III_DCI_18_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_iv.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with HSTL_IV I/O Standard +-- /___/ /\ Filename : IBUFG_HSTL_IV.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:36 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_HSTL_IV ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_HSTL_IV is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_HSTL_IV; + +architecture IBUFG_HSTL_IV_V of IBUFG_HSTL_IV is +begin + O <= TO_X01(I); +end IBUFG_HSTL_IV_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_iv_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with HSTL_IV_18 I/O Standard +-- /___/ /\ Filename : IBUFG_HSTL_IV_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:36 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_HSTL_IV_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_HSTL_IV_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_HSTL_IV_18; + +architecture IBUFG_HSTL_IV_18_V of IBUFG_HSTL_IV_18 is +begin + O <= TO_X01(I); +end IBUFG_HSTL_IV_18_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_iv_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with HSTL_IV_DCI I/O Standard +-- /___/ /\ Filename : IBUFG_HSTL_IV_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:36 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_HSTL_IV_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_HSTL_IV_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_HSTL_IV_DCI; + +architecture IBUFG_HSTL_IV_DCI_V of IBUFG_HSTL_IV_DCI is +begin + O <= TO_X01(I); +end IBUFG_HSTL_IV_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_hstl_iv_dci_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with HSTL_IV_DCI_18 I/O Standard +-- /___/ /\ Filename : IBUFG_HSTL_IV_DCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:36 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_HSTL_IV_DCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_HSTL_IV_DCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_HSTL_IV_DCI_18; + +architecture IBUFG_HSTL_IV_DCI_18_V of IBUFG_HSTL_IV_DCI_18 is +begin + O <= TO_X01(I); +end IBUFG_HSTL_IV_DCI_18_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvcmos12.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with LVCMOS12 I/O Standard +-- /___/ /\ Filename : IBUFG_LVCMOS12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:36 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_LVCMOS12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_LVCMOS12 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_LVCMOS12; + +architecture IBUFG_LVCMOS12_V of IBUFG_LVCMOS12 is +begin + O <= TO_X01(I); +end IBUFG_LVCMOS12_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvcmos15.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with LVCMOS15 I/O Standard +-- /___/ /\ Filename : IBUFG_LVCMOS15.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:37 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_LVCMOS15 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_LVCMOS15 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_LVCMOS15; + +architecture IBUFG_LVCMOS15_V of IBUFG_LVCMOS15 is +begin + O <= TO_X01(I); +end IBUFG_LVCMOS15_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvcmos18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with LVCMOS18 I/O Standard +-- /___/ /\ Filename : IBUFG_LVCMOS18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:37 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_LVCMOS18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_LVCMOS18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_LVCMOS18; + +architecture IBUFG_LVCMOS18_V of IBUFG_LVCMOS18 is +begin + O <= TO_X01(I); +end IBUFG_LVCMOS18_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvcmos2.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with LVCMOS2 I/O Standard +-- /___/ /\ Filename : IBUFG_LVCMOS2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:37 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_LVCMOS2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_LVCMOS2 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_LVCMOS2; + +architecture IBUFG_LVCMOS2_V of IBUFG_LVCMOS2 is +begin + O <= TO_X01(I); +end IBUFG_LVCMOS2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvcmos25.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with LVCMOS25 I/O Standard +-- /___/ /\ Filename : IBUFG_LVCMOS25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:37 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_LVCMOS25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_LVCMOS25 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_LVCMOS25; + +architecture IBUFG_LVCMOS25_V of IBUFG_LVCMOS25 is +begin + O <= TO_X01(I); +end IBUFG_LVCMOS25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvcmos33.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with LVCMOS33 I/O Standard +-- /___/ /\ Filename : IBUFG_LVCMOS33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:37 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_LVCMOS33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_LVCMOS33 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_LVCMOS33; + +architecture IBUFG_LVCMOS33_V of IBUFG_LVCMOS33 is +begin + O <= TO_X01(I); +end IBUFG_LVCMOS33_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvdci_15.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with LVDCI_15 I/O Standard +-- /___/ /\ Filename : IBUFG_LVDCI_15.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:37 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_LVDCI_15 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_LVDCI_15 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_LVDCI_15; + +architecture IBUFG_LVDCI_15_V of IBUFG_LVDCI_15 is +begin + O <= TO_X01(I); +end IBUFG_LVDCI_15_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvdci_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with LVDCI_18 I/O Standard +-- /___/ /\ Filename : IBUFG_LVDCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:37 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_LVDCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_LVDCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_LVDCI_18; + +architecture IBUFG_LVDCI_18_V of IBUFG_LVDCI_18 is +begin + O <= TO_X01(I); +end IBUFG_LVDCI_18_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvdci_25.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with LVDCI_25 I/O Standard +-- /___/ /\ Filename : IBUFG_LVDCI_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:37 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_LVDCI_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_LVDCI_25 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_LVDCI_25; + +architecture IBUFG_LVDCI_25_V of IBUFG_LVDCI_25 is +begin + O <= TO_X01(I); +end IBUFG_LVDCI_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvdci_33.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with LVDCI_33 I/O Standard +-- /___/ /\ Filename : IBUFG_LVDCI_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:37 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_LVDCI_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_LVDCI_33 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_LVDCI_33; + +architecture IBUFG_LVDCI_33_V of IBUFG_LVDCI_33 is +begin + O <= TO_X01(I); +end IBUFG_LVDCI_33_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvdci_dv2_15.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with LVDCI_DV2_15 I/O Standard +-- /___/ /\ Filename : IBUFG_LVDCI_DV2_15.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:38 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_LVDCI_DV2_15 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_LVDCI_DV2_15 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_LVDCI_DV2_15; + +architecture IBUFG_LVDCI_DV2_15_V of IBUFG_LVDCI_DV2_15 is +begin + O <= TO_X01(I); +end IBUFG_LVDCI_DV2_15_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvdci_dv2_18.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with LVDCI_DV2_18 I/O Standard +-- /___/ /\ Filename : IBUFG_LVDCI_DV2_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:38 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_LVDCI_DV2_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_LVDCI_DV2_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_LVDCI_DV2_18; + +architecture IBUFG_LVDCI_DV2_18_V of IBUFG_LVDCI_DV2_18 is +begin + O <= TO_X01(I); +end IBUFG_LVDCI_DV2_18_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvdci_dv2_25.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with LVDCI_DV2_25 I/O Standard +-- /___/ /\ Filename : IBUFG_LVDCI_DV2_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:38 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_LVDCI_DV2_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_LVDCI_DV2_25 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_LVDCI_DV2_25; + +architecture IBUFG_LVDCI_DV2_25_V of IBUFG_LVDCI_DV2_25 is +begin + O <= TO_X01(I); +end IBUFG_LVDCI_DV2_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvdci_dv2_33.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with LVDCI_DV2_33 I/O Standard +-- /___/ /\ Filename : IBUFG_LVDCI_DV2_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:38 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_LVDCI_DV2_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_LVDCI_DV2_33 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_LVDCI_DV2_33; + +architecture IBUFG_LVDCI_DV2_33_V of IBUFG_LVDCI_DV2_33 is +begin + O <= TO_X01(I); +end IBUFG_LVDCI_DV2_33_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvds.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with LVDS I/O Standard +-- /___/ /\ Filename : IBUFG_LVDS.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:38 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_LVDS ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_LVDS is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_LVDS; + +architecture IBUFG_LVDS_V of IBUFG_LVDS is +begin + O <= TO_X01(I); +end IBUFG_LVDS_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvpecl.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with LVPECL I/O Standard +-- /___/ /\ Filename : IBUFG_LVPECL.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:38 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_LVPECL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_LVPECL is + port( + O : out STD_ULOGIC; + + I : in STD_ULOGIC + ); +end IBUFG_LVPECL; + +architecture IBUFG_LVPECL_V of IBUFG_LVPECL is +begin + O <= TO_X01(I); +end IBUFG_LVPECL_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_lvttl.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with LVTTL I/O Standard +-- /___/ /\ Filename : IBUFG_LVTTL.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:38 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_LVTTL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_LVTTL is + port( + O : out STD_ULOGIC; + + I : in STD_ULOGIC + ); +end IBUFG_LVTTL; + +architecture IBUFG_LVTTL_V of IBUFG_LVTTL is +begin + O <= TO_X01(I); +end IBUFG_LVTTL_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_pci33_3.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with PCI33_3 I/O Standard +-- /___/ /\ Filename : IBUFG_PCI33_3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:38 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_PCI33_3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_PCI33_3 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_PCI33_3; + +architecture IBUFG_PCI33_3_V of IBUFG_PCI33_3 is +begin + O <= TO_X01(I); +end IBUFG_PCI33_3_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_pci33_5.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with PCI33_5 I/O Standard +-- /___/ /\ Filename : IBUFG_PCI33_5.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:38 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_PCI33_5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_PCI33_5 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_PCI33_5; + +architecture IBUFG_PCI33_5_V of IBUFG_PCI33_5 is +begin + O <= TO_X01(I); +end IBUFG_PCI33_5_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_pci66_3.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with PCI66_3 I/O Standard +-- /___/ /\ Filename : IBUFG_PCI66_3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:39 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_PCI66_3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_PCI66_3 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_PCI66_3; + +architecture IBUFG_PCI66_3_V of IBUFG_PCI66_3 is +begin + O <= TO_X01(I); +end IBUFG_PCI66_3_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_pcix.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with PCIX I/O Standard +-- /___/ /\ Filename : IBUFG_PCIX.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:39 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_PCIX ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_PCIX is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_PCIX; + +architecture IBUFG_PCIX_V of IBUFG_PCIX is +begin + O <= TO_X01(I); +end IBUFG_PCIX_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_pcix66_3.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with PCIX66_3 I/O Standard +-- /___/ /\ Filename : IBUFG_PCIX66_3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:39 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_PCIX66_3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_PCIX66_3 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_PCIX66_3; + +architecture IBUFG_PCIX66_3_V of IBUFG_PCIX66_3 is +begin + O <= TO_X01(I); +end IBUFG_PCIX66_3_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl18_i.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with SSTL18_I I/O Standard +-- /___/ /\ Filename : IBUFG_SSTL18_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:39 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_SSTL18_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_SSTL18_I is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_SSTL18_I; + +architecture IBUFG_SSTL18_I_V of IBUFG_SSTL18_I is +begin + O <= TO_X01(I); +end IBUFG_SSTL18_I_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl18_i_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with SSTL18_I_DCI I/O Standard +-- /___/ /\ Filename : IBUFG_SSTL18_I_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:39 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_SSTL18_I_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_SSTL18_I_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_SSTL18_I_DCI; + +architecture IBUFG_SSTL18_I_DCI_V of IBUFG_SSTL18_I_DCI is +begin + O <= TO_X01(I); +end IBUFG_SSTL18_I_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl18_ii.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with SSTL18_II I/O Standard +-- /___/ /\ Filename : IBUFG_SSTL18_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:39 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_SSTL18_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_SSTL18_II is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_SSTL18_II; + +architecture IBUFG_SSTL18_II_V of IBUFG_SSTL18_II is +begin + O <= TO_X01(I); +end IBUFG_SSTL18_II_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl18_ii_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with SSTL18_II_DCI I/O Standard +-- /___/ /\ Filename : IBUFG_SSTL18_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:39 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_SSTL18_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_SSTL18_II_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_SSTL18_II_DCI; + +architecture IBUFG_SSTL18_II_DCI_V of IBUFG_SSTL18_II_DCI is +begin + O <= TO_X01(I); +end IBUFG_SSTL18_II_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl2_i.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with SSTL2_I I/O Standard +-- /___/ /\ Filename : IBUFG_SSTL2_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:39 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_SSTL2_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_SSTL2_I is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_SSTL2_I; + +architecture IBUFG_SSTL2_I_V of IBUFG_SSTL2_I is +begin + O <= TO_X01(I); +end IBUFG_SSTL2_I_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl2_i_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with SSTL2_I_DCI I/O Standard +-- /___/ /\ Filename : IBUFG_SSTL2_I_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:39 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_SSTL2_I_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_SSTL2_I_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_SSTL2_I_DCI; + +architecture IBUFG_SSTL2_I_DCI_V of IBUFG_SSTL2_I_DCI is +begin + O <= TO_X01(I); +end IBUFG_SSTL2_I_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl2_ii.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with SSTL2_II I/O Standard +-- /___/ /\ Filename : IBUFG_SSTL2_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:40 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_SSTL2_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_SSTL2_II is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_SSTL2_II; + +architecture IBUFG_SSTL2_II_V of IBUFG_SSTL2_II is +begin + O <= TO_X01(I); +end IBUFG_SSTL2_II_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl2_ii_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with SSTL2_II_DCI I/O Standard +-- /___/ /\ Filename : IBUFG_SSTL2_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:40 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_SSTL2_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_SSTL2_II_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_SSTL2_II_DCI; + +architecture IBUFG_SSTL2_II_DCI_V of IBUFG_SSTL2_II_DCI is +begin + O <= TO_X01(I); +end IBUFG_SSTL2_II_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl3_i.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with SSTL3_I I/O Standard +-- /___/ /\ Filename : IBUFG_SSTL3_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:40 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_SSTL3_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_SSTL3_I is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_SSTL3_I; + +architecture IBUFG_SSTL3_I_V of IBUFG_SSTL3_I is +begin + O <= TO_X01(I); +end IBUFG_SSTL3_I_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl3_i_dci.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with SSTL3_I_DCI I/O Standard +-- /___/ /\ Filename : IBUFG_SSTL3_I_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:40 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_SSTL3_I_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_SSTL3_I_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_SSTL3_I_DCI; + +architecture IBUFG_SSTL3_I_DCI_V of IBUFG_SSTL3_I_DCI is +begin + O <= TO_X01(I); +end IBUFG_SSTL3_I_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl3_ii.vhd,v 1.5 2004/04/08 18:46:24 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with SSTL3_II I/O Standard +-- /___/ /\ Filename : IBUFG_SSTL3_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:40 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_SSTL3_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_SSTL3_II is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_SSTL3_II; + +architecture IBUFG_SSTL3_II_V of IBUFG_SSTL3_II is +begin + O <= TO_X01(I); +end IBUFG_SSTL3_II_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufg_sstl3_ii_dci.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Input Clock Buffer with SSTL3_II_DCI I/O Standard +-- /___/ /\ Filename : IBUFG_SSTL3_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:40 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFG_SSTL3_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFG_SSTL3_II_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end IBUFG_SSTL3_II_DCI; + +architecture IBUFG_SSTL3_II_DCI_V of IBUFG_SSTL3_II_DCI is +begin + O <= TO_X01(I); +end IBUFG_SSTL3_II_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds.vhd,v 1.9 2007/07/26 23:51:52 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Clock Buffer +-- /___/ /\ Filename : IBUFGDS.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:40 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 07/26/07 - Add else to handle x case for output (CR 424214). +-- End Revision + +----- CELL IBUFGDS ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFGDS is + generic( + CAPACITANCE : string := "DONT_CARE"; + DIFF_TERM : boolean := FALSE; + IBUF_DELAY_VALUE : string := "0"; + IOSTANDARD : string := "DEFAULT" + ); + + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFGDS; + +architecture IBUFGDS_V of IBUFGDS is +begin + prcs_init : process + variable FIRST_TIME : boolean := TRUE; + begin + + If(FIRST_TIME = true) then + + if((CAPACITANCE = "LOW") or + (CAPACITANCE = "NORMAL") or + (CAPACITANCE = "DONT_CARE")) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The Legal values for CAPACITANCE are LOW, NORMAL or DONT_CARE" + severity Failure; + end if; + + if((DIFF_TERM = TRUE) or + (DIFF_TERM = FALSE)) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The Legal values for DIFF_TERM are TRUE or FALSE" + severity Failure; + end if; + +-- + if((IBUF_DELAY_VALUE = "0") or (IBUF_DELAY_VALUE = "1") or + (IBUF_DELAY_VALUE = "2") or (IBUF_DELAY_VALUE = "3") or + (IBUF_DELAY_VALUE = "4") or (IBUF_DELAY_VALUE = "5") or + (IBUF_DELAY_VALUE = "6") or (IBUF_DELAY_VALUE = "7") or + (IBUF_DELAY_VALUE = "8") or (IBUF_DELAY_VALUE = "9") or + (IBUF_DELAY_VALUE = "10") or (IBUF_DELAY_VALUE = "11") or + (IBUF_DELAY_VALUE = "12") or (IBUF_DELAY_VALUE = "13") or + (IBUF_DELAY_VALUE = "14") or (IBUF_DELAY_VALUE = "15") or + (IBUF_DELAY_VALUE = "16")) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The Legal values for IBUF_DELAY_VALUE are 0, 1, 2, ... , or 16. " + severity Failure; + end if; + + end if; + wait; + end process prcs_init; + + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + elsif (I = 'Z' or I = 'X' or IB = 'Z' or IB ='X') then + O <= 'X'; + end if; + end process; +end IBUFGDS_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_blvds_25.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Clock Buffer with BLVDS_25 I/O Standard +-- /___/ /\ Filename : IBUFGDS_BLVDS_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:40 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFGDS_BLVDS_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFGDS_BLVDS_25 is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFGDS_BLVDS_25; + +architecture IBUFGDS_BLVDS_25_V of IBUFGDS_BLVDS_25 is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFGDS_BLVDS_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_diff_out.vhd,v 1.5 2005/07/23 00:24:21 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Clock Buffer with Differential Outputs +-- /___/ /\ Filename : IBUFGDS_DIFF_OUT.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:40 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFGDS_DIFF_OUT ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFGDS_DIFF_OUT is + generic( + IOSTANDARD : string := "LVDS_25" + ); + + port( + O : out STD_ULOGIC; + OB : out STD_ULOGIC; + + I : in STD_ULOGIC; + IB : in STD_ULOGIC + ); +end IBUFGDS_DIFF_OUT; + +architecture IBUFGDS_DIFF_OUT_V of IBUFGDS_DIFF_OUT is +begin + VITALBehavior : process (I, IB) + begin + if (I /= IB ) then + O <= TO_X01(I); + OB <= TO_X01(NOT I); + end if; +end process; +end IBUFGDS_DIFF_OUT_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_ldt_25.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Clock Buffer with LDT_25 I/O Standard +-- /___/ /\ Filename : IBUFGDS_LDT_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:41 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFGDS_LDT_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFGDS_LDT_25 is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFGDS_LDT_25; + +architecture IBUFGDS_LDT_25_V of IBUFGDS_LDT_25 is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFGDS_LDT_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvds_25.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Clock Buffer with LVDS_25 I/O Standard +-- /___/ /\ Filename : IBUFGDS_LVDS_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:41 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFGDS_LVDS_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFGDS_LVDS_25 is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFGDS_LVDS_25; + +architecture IBUFGDS_LVDS_25_V of IBUFGDS_LVDS_25 is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFGDS_LVDS_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvds_25_dci.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Clock Buffer with LVDS_25_DCI I/O Standard +-- /___/ /\ Filename : IBUFGDS_LVDS_25_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:41 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFGDS_LVDS_25_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFGDS_LVDS_25_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFGDS_LVDS_25_DCI; + +architecture IBUFGDS_LVDS_25_DCI_V of IBUFGDS_LVDS_25_DCI is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFGDS_LVDS_25_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvds_33.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Clock Buffer with LVDS_33 I/O Standard +-- /___/ /\ Filename : IBUFGDS_LVDS_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:41 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFGDS_LVDS_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFGDS_LVDS_33 is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFGDS_LVDS_33; + +architecture IBUFGDS_LVDS_33_V of IBUFGDS_LVDS_33 is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFGDS_LVDS_33_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvds_33_dci.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Clock Buffer with LVDS_33_DCI I/O Standard +-- /___/ /\ Filename : IBUFGDS_LVDS_33_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:41 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFGDS_LVDS_33_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFGDS_LVDS_33_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFGDS_LVDS_33_DCI; + +architecture IBUFGDS_LVDS_33_DCI_V of IBUFGDS_LVDS_33_DCI is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFGDS_LVDS_33_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvdsext_25.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Clock Buffer with LVDSEXT_25 I/O Standard +-- /___/ /\ Filename : IBUFGDS_LVDSEXT_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:41 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFGDS_LVDSEXT_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFGDS_LVDSEXT_25 is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFGDS_LVDSEXT_25; + +architecture IBUFGDS_LVDSEXT_25_V of IBUFGDS_LVDSEXT_25 is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFGDS_LVDSEXT_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvdsext_25_dci.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Clock Buffer with LVDSEXT_25_DCI I/O Standard +-- /___/ /\ Filename : IBUFGDS_LVDSEXT_25_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:41 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFGDS_LVDSEXT_25_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFGDS_LVDSEXT_25_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFGDS_LVDSEXT_25_DCI; + +architecture IBUFGDS_LVDSEXT_25_DCI_V of IBUFGDS_LVDSEXT_25_DCI is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFGDS_LVDSEXT_25_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvdsext_33.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Clock Buffer with LVDSEXT_33 I/O Standard +-- /___/ /\ Filename : IBUFGDS_LVDSEXT_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:41 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFGDS_LVDSEXT_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFGDS_LVDSEXT_33 is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFGDS_LVDSEXT_33; + +architecture IBUFGDS_LVDSEXT_33_V of IBUFGDS_LVDSEXT_33 is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFGDS_LVDSEXT_33_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvdsext_33_dci.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Clock Buffer with LVDSEXT_33_DCI I/O Standard +-- /___/ /\ Filename : IBUFGDS_LVDSEXT_33_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:41 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFGDS_LVDSEXT_33_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFGDS_LVDSEXT_33_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFGDS_LVDSEXT_33_DCI; + +architecture IBUFGDS_LVDSEXT_33_DCI_V of IBUFGDS_LVDSEXT_33_DCI is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFGDS_LVDSEXT_33_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvpecl_25.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Clock Buffer with LVPECL_25 I/O Standard +-- /___/ /\ Filename : IBUFGDS_LVPECL_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:42 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFGDS_LVPECL_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFGDS_LVPECL_25 is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFGDS_LVPECL_25; + +architecture IBUFGDS_LVPECL_25_V of IBUFGDS_LVPECL_25 is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFGDS_LVPECL_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_lvpecl_33.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Clock Buffer with LVPECL_33 I/O Standard +-- /___/ /\ Filename : IBUFGDS_LVPECL_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:42 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFGDS_LVPECL_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFGDS_LVPECL_33 is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFGDS_LVPECL_33; + +architecture IBUFGDS_LVPECL_33_V of IBUFGDS_LVPECL_33 is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFGDS_LVPECL_33_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ibufgds_ulvds_25.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Input Clock Buffer with ULVDS_25 I/O Standard +-- /___/ /\ Filename : IBUFGDS_ULVDS_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:42 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IBUFGDS_ULVDS_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IBUFGDS_ULVDS_25 is + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic + ); +end IBUFGDS_ULVDS_25; + +architecture IBUFGDS_ULVDS_25_V of IBUFGDS_ULVDS_25 is +begin + VitalBehavior : process (I, IB) + begin + if ((I = '1') and (IB = '0')) then + O <= TO_X01(I); + elsif ((I = '0') and (IB = '1')) then + O <= TO_X01(I); + end if; + end process; +end IBUFGDS_ULVDS_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/icap_virtex2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Internal Configuration Access Port for Virtex2 +-- /___/ /\ Filename : ICAP_VIRTEX2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:42 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL ICAP_VIRTEX2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity ICAP_VIRTEX2 is + port( + BUSY : out std_ulogic; + O : out std_logic_vector(7 downto 0); + + CE : in std_ulogic; + CLK : in std_ulogic; + I : in std_logic_vector(7 downto 0); + WRITE : in std_ulogic + ); +end ICAP_VIRTEX2; + +architecture ICAP_VIRTEX2_V of ICAP_VIRTEX2 is +begin +end ICAP_VIRTEX2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ifddrcpe.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Dual Data Rate Input D Flip-Flop with Asynchronous Clear and Preset and Clock Enable +-- /___/ /\ Filename : IFDDRCPE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:42 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IFDDRCPE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VCOMPONENTS.all; + +entity IFDDRCPE is + port( + Q0 : out std_ulogic; + Q1 : out std_ulogic; + + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); +end IFDDRCPE; + +architecture IFDDRCPE_V of IFDDRCPE is + signal D_in : std_ulogic := 'X'; +begin + + I1 : IBUF + port map ( + I => D, + O => D_in + ); + + F0 : FDCPE + generic map ( + INIT => '0' ) + port map ( + C => C0, + CE => CE, + CLR => CLR, + D => D_in, + PRE => PRE, + Q => Q0 + ); + + F1 : FDCPE + generic map ( + INIT => '0' ) + port map ( + C => C1, + CE => CE, + CLR => CLR, + D => D_in, + PRE => PRE, + Q => Q1 + ); +end IFDDRCPE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ifddrrse.vhd,v 1.5 2006/08/09 01:01:48 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Dual Data Rate Input D Flip-Flop with Synchronous Reset and SET and Clock Enable +-- /___/ /\ Filename : IFDDRRSE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:42 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 08/08/06 - CR 227386 fix +-- End Revision + +----- CELL IFDDRRSE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VCOMPONENTS.all; + +entity IFDDRRSE is + port( + Q0 : out std_ulogic; + Q1 : out std_ulogic; + + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end IFDDRRSE; + +architecture IFDDRRSE_V of IFDDRRSE is + signal D_in : std_ulogic := 'X'; +begin + I1 : IBUF + port map ( + I => D, + O => D_in + ); + + F0 : FDRSE + generic map ( + INIT => '0') + port map ( + C => C0, + CE => CE, + R => R, + D => D_in, + S => S, + Q => Q0 + ); + + F1 : FDRSE + generic map ( + INIT => '0') + port map ( + C => C1, + CE => CE, + R => R, + D => D_in, + S => S, + Q => Q1 + ); +end IFDDRRSE_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/inv.vhd,v 1.5 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Inverter +-- /___/ /\ Filename : INV.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:42 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL INV ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity INV is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end INV; + +architecture INV_V of INV is +begin + O <= (not TO_X01(I)); +end INV_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf.vhd,v 1.8 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer +-- /___/ /\ Filename : IOBUF.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:43 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF is + generic( + CAPACITANCE : string := "DONT_CARE"; + DRIVE : integer := 12; + IBUF_DELAY_VALUE : string := "0"; + IFD_DELAY_VALUE : string := "AUTO"; + IOSTANDARD : string := "DEFAULT"; + SLEW : string := "SLOW" + ); + + port( + O : out std_ulogic; + IO : inout std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); +end IOBUF; + +architecture IOBUF_V of IOBUF is +begin + prcs_init : process + variable FIRST_TIME : boolean := TRUE; + begin + + If(FIRST_TIME = true) then + if((CAPACITANCE = "LOW") or + (CAPACITANCE = "NORMAL") or + (CAPACITANCE = "DONT_CARE")) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The Legal values for CAPACITANCE are LOW, NORMAL or DONT_CARE" + severity Failure; + end if; +-- + if((IBUF_DELAY_VALUE = "0") or (IBUF_DELAY_VALUE = "1") or + (IBUF_DELAY_VALUE = "2") or (IBUF_DELAY_VALUE = "3") or + (IBUF_DELAY_VALUE = "4") or (IBUF_DELAY_VALUE = "5") or + (IBUF_DELAY_VALUE = "6") or (IBUF_DELAY_VALUE = "7") or + (IBUF_DELAY_VALUE = "8") or (IBUF_DELAY_VALUE = "9") or + (IBUF_DELAY_VALUE = "10") or (IBUF_DELAY_VALUE = "11") or + (IBUF_DELAY_VALUE = "12") or (IBUF_DELAY_VALUE = "13") or + (IBUF_DELAY_VALUE = "14") or (IBUF_DELAY_VALUE = "15") or + (IBUF_DELAY_VALUE = "16")) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The Legal values for IBUF_DELAY_VALUE are 0, 1, 2, ... , or 16. " + severity Failure; + end if; + +-- + if((IFD_DELAY_VALUE = "AUTO") or (IFD_DELAY_VALUE = "auto") or + (IFD_DELAY_VALUE = "0") or (IFD_DELAY_VALUE = "1") or + (IFD_DELAY_VALUE = "2") or (IFD_DELAY_VALUE = "3") or + (IFD_DELAY_VALUE = "4") or (IFD_DELAY_VALUE = "5") or + (IFD_DELAY_VALUE = "6") or (IFD_DELAY_VALUE = "7") or + (IFD_DELAY_VALUE = "8")) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The Legal values for IFD_DELAY_VALUE are AUTO, 0, 1, ... , or 8" + severity Failure; + end if; + + end if; + wait; + end process prcs_init; + + VPKGBehavior : process (IO, I, T) + + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_agp.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with AGP I/O Standard +-- /___/ /\ Filename : IOBUF_AGP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:43 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_AGP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_AGP is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); +end IOBUF_AGP; + +architecture IOBUF_AGP_V of IOBUF_AGP is + +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_AGP_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_ctt.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with CTT I/O Standard +-- /___/ /\ Filename : IOBUF_CTT.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:43 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_CTT ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_CTT is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); +end IOBUF_CTT; + +architecture IOBUF_CTT_V of IOBUF_CTT is +begin + VPKGBehavior : process (IO, I, T) + variable IO_zd : std_ulogic; + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_CTT_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_f_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with Fast Slew 12 mA Drive +-- /___/ /\ Filename : IOBUF_F_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:43 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_F_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_F_12 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_F_12; + +architecture IOBUF_F_12_V of IOBUF_F_12 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_F_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_f_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with Fast Slew 16 mA Drive +-- /___/ /\ Filename : IOBUF_F_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:43 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_F_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_F_16 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_F_16; + +architecture IOBUF_F_16_V of IOBUF_F_16 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_F_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_f_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with Fast Slew 2 mA Drive +-- /___/ /\ Filename : IOBUF_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:43 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_F_2 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_F_2; + +architecture IOBUF_F_2_V of IOBUF_F_2 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_F_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_f_24.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with Fast Slew 24 mA Drive +-- /___/ /\ Filename : IOBUF_F_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:43 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_F_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_F_24 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_F_24; + +architecture IOBUF_F_24_V of IOBUF_F_24 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_F_24_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_f_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with Fast Slew 4 mA Drive +-- /___/ /\ Filename : IOBUF_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:43 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_F_4 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_F_4; + +architecture IOBUF_F_4_V of IOBUF_F_4 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_F_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_f_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with Fast Slew 6 mA Drive +-- /___/ /\ Filename : IOBUF_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:43 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_F_6 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_F_6; + +architecture IOBUF_F_6_V of IOBUF_F_6 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_F_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_f_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with Fast Slew 8 mA Drive +-- /___/ /\ Filename : IOBUF_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:44 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_F_8 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_F_8; + +architecture IOBUF_F_8_V of IOBUF_F_8 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_F_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_gtl.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with GTL I/O Standard +-- /___/ /\ Filename : IOBUF_GTL.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:44 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_GTL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_GTL is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_GTL; + +architecture IOBUF_GTL_V of IOBUF_GTL is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_GTL_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_gtl_dci.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with GTL_DCI I/O Standard +-- /___/ /\ Filename : IOBUF_GTL_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:44 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_GTL_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_GTL_DCI is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_GTL_DCI; + +architecture IOBUF_GTL_DCI_V of IOBUF_GTL_DCI is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_GTL_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_gtlp.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with GTLP I/O Standard +-- /___/ /\ Filename : IOBUF_GTLP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:44 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_GTLP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_GTLP is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_GTLP; + +architecture IOBUF_GTLP_V of IOBUF_GTLP is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_GTLP_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_gtlp_dci.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with GTLP_DCI I/O Standard +-- /___/ /\ Filename : IOBUF_GTLP_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:44 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_GTLP_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_GTLP_DCI is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_GTLP_DCI; + +architecture IOBUF_GTLP_DCI_V of IOBUF_GTLP_DCI is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_GTLP_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_i.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with HSTL_I I/O Standard +-- /___/ /\ Filename : IOBUF_HSTL_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:44 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_HSTL_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_HSTL_I is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_HSTL_I; + +architecture IOBUF_HSTL_I_V of IOBUF_HSTL_I is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_HSTL_I_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_i_18.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with HSTL_I_18 I/O Standard +-- /___/ /\ Filename : IOBUF_HSTL_I_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:44 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_HSTL_I_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_HSTL_I_18 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_HSTL_I_18; + +architecture IOBUF_HSTL_I_18_V of IOBUF_HSTL_I_18 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_HSTL_I_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_ii.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with HSTL_II I/O Standard +-- /___/ /\ Filename : IOBUF_HSTL_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:44 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_HSTL_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_HSTL_II is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_HSTL_II; + +architecture IOBUF_HSTL_II_V of IOBUF_HSTL_II is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_HSTL_II_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_ii_18.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with HSTL_II_18 I/O Standard +-- /___/ /\ Filename : IOBUF_HSTL_II_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:44 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_HSTL_II_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_HSTL_II_18 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_HSTL_II_18; + +architecture IOBUF_HSTL_II_18_V of IOBUF_HSTL_II_18 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_HSTL_II_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_ii_dci.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with HSTL_II_DCI I/O Standard +-- /___/ /\ Filename : IOBUF_HSTL_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:45 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_HSTL_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_HSTL_II_DCI is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_HSTL_II_DCI; + +architecture IOBUF_HSTL_II_DCI_V of IOBUF_HSTL_II_DCI is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_HSTL_II_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_ii_dci_18.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with HSTL_II_DCI_18 I/O Standard +-- /___/ /\ Filename : IOBUF_HSTL_II_DCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:45 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_HSTL_II_DCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_HSTL_II_DCI_18 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_HSTL_II_DCI_18; + +architecture IOBUF_HSTL_II_DCI_18_V of IOBUF_HSTL_II_DCI_18 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_HSTL_II_DCI_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_iii.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with HSTL_III I/O Standard +-- /___/ /\ Filename : IOBUF_HSTL_III.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:45 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_HSTL_III ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_HSTL_III is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_HSTL_III; + +architecture IOBUF_HSTL_III_V of IOBUF_HSTL_III is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_HSTL_III_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_iii_18.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with HSTL_III_18 I/O Standard +-- /___/ /\ Filename : IOBUF_HSTL_III_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:45 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_HSTL_III_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_HSTL_III_18 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_HSTL_III_18; + +architecture IOBUF_HSTL_III_18_V of IOBUF_HSTL_III_18 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_HSTL_III_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_iv.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with HSTL_IV I/O Standard +-- /___/ /\ Filename : IOBUF_HSTL_IV.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:45 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_HSTL_IV ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_HSTL_IV is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_HSTL_IV; + +architecture IOBUF_HSTL_IV_V of IOBUF_HSTL_IV is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_HSTL_IV_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_iv_18.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with HSTL_IV_18 I/O Standard +-- /___/ /\ Filename : IOBUF_HSTL_IV_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:45 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_HSTL_IV_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_HSTL_IV_18 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_HSTL_IV_18; + +architecture IOBUF_HSTL_IV_18_V of IOBUF_HSTL_IV_18 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_HSTL_IV_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_iv_dci.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with HSTL_IV_DCI I/O Standard +-- /___/ /\ Filename : IOBUF_HSTL_IV_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:45 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_HSTL_IV_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_HSTL_IV_DCI is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_HSTL_IV_DCI; + +architecture IOBUF_HSTL_IV_DCI_V of IOBUF_HSTL_IV_DCI is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_HSTL_IV_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_hstl_iv_dci_18.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with HSTL_IV_DCI_18 I/O Standard +-- /___/ /\ Filename : IOBUF_HSTL_IV_DCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:45 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_HSTL_IV_DCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_HSTL_IV_DCI_18 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_HSTL_IV_DCI_18; + +architecture IOBUF_HSTL_IV_DCI_18_V of IOBUF_HSTL_IV_DCI_18 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_HSTL_IV_DCI_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS12 I/O Standard +-- /___/ /\ Filename : IOBUF_LVCMOS12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:45 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS12 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS12; + +architecture IOBUF_LVCMOS12_V of IOBUF_LVCMOS12 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos12_f_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS12 I/O Standard Fast Slew 2 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS12_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:46 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS12_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS12_F_2 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS12_F_2; + +architecture IOBUF_LVCMOS12_F_2_V of IOBUF_LVCMOS12_F_2 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS12_F_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos12_f_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS12 I/O Standard Fast Slew 4 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS12_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:46 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS12_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS12_F_4 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS12_F_4; + +architecture IOBUF_LVCMOS12_F_4_V of IOBUF_LVCMOS12_F_4 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS12_F_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos12_f_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS12 I/O Standard Fast Slew 6 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS12_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:46 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS12_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS12_F_6 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS12_F_6; + +architecture IOBUF_LVCMOS12_F_6_V of IOBUF_LVCMOS12_F_6 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS12_F_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos12_f_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS12 I/O Standard Fast Slew 8 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS12_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:46 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS12_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS12_F_8 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS12_F_8; + +architecture IOBUF_LVCMOS12_F_8_V of IOBUF_LVCMOS12_F_8 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS12_F_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos12_s_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS12 I/O Standard Slow Slew 2 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS12_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:46 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS12_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS12_S_2 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS12_S_2; + +architecture IOBUF_LVCMOS12_S_2_V of IOBUF_LVCMOS12_S_2 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS12_S_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos12_s_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS12 I/O Standard Slow Slew 4 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS12_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:46 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS12_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS12_S_4 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS12_S_4; + +architecture IOBUF_LVCMOS12_S_4_V of IOBUF_LVCMOS12_S_4 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS12_S_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos12_s_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS12 I/O Standard Slow Slew 6 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS12_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:46 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS12_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS12_S_6 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS12_S_6; + +architecture IOBUF_LVCMOS12_S_6_V of IOBUF_LVCMOS12_S_6 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS12_S_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos12_s_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS12 I/O Standard Slow Slew 8 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS12_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:46 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS12_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS12_S_8 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS12_S_8; + +architecture IOBUF_LVCMOS12_S_8_V of IOBUF_LVCMOS12_S_8 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS12_S_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS15 I/O Standard +-- /___/ /\ Filename : IOBUF_LVCMOS15.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:46 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS15 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS15 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS15; + +architecture IOBUF_LVCMOS15_V of IOBUF_LVCMOS15 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS15_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_f_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS15 I/O Standard Fast Slew 12 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS15_F_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:47 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS15_F_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS15_F_12 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS15_F_12; + +architecture IOBUF_LVCMOS15_F_12_V of IOBUF_LVCMOS15_F_12 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS15_F_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_f_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS15 I/O Standard Fast Slew 16 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS15_F_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:47 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS15_F_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS15_F_16 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS15_F_16; + +architecture IOBUF_LVCMOS15_F_16_V of IOBUF_LVCMOS15_F_16 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS15_F_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_f_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS15 I/O Standard Fast Slew 2 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS15_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:47 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS15_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS15_F_2 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS15_F_2; + +architecture IOBUF_LVCMOS15_F_2_V of IOBUF_LVCMOS15_F_2 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS15_F_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_f_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS15 I/O Standard Fast Slew 4 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS15_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:47 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS15_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS15_F_4 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS15_F_4; + +architecture IOBUF_LVCMOS15_F_4_V of IOBUF_LVCMOS15_F_4 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS15_F_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_f_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS15 I/O Standard Fast Slew 6 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS15_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:47 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS15_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS15_F_6 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS15_F_6; + +architecture IOBUF_LVCMOS15_F_6_V of IOBUF_LVCMOS15_F_6 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS15_F_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_f_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS15 I/O Standard Fast Slew 8 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS15_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:47 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS15_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS15_F_8 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS15_F_8; + +architecture IOBUF_LVCMOS15_F_8_V of IOBUF_LVCMOS15_F_8 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS15_F_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_s_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS15 I/O Standard Slow Slew 12 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS15_S_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:47 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS15_S_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS15_S_12 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS15_S_12; + +architecture IOBUF_LVCMOS15_S_12_V of IOBUF_LVCMOS15_S_12 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS15_S_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_s_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS15 I/O Standard Slow Slew 16 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS15_S_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:47 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS15_S_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS15_S_16 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS15_S_16; + +architecture IOBUF_LVCMOS15_S_16_V of IOBUF_LVCMOS15_S_16 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS15_S_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_s_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS15 I/O Standard Slow Slew 2 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS15_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:47 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS15_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS15_S_2 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS15_S_2; + +architecture IOBUF_LVCMOS15_S_2_V of IOBUF_LVCMOS15_S_2 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS15_S_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_s_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS15 I/O Standard Slow Slew 4 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS15_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:48 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS15_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS15_S_4 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS15_S_4; + +architecture IOBUF_LVCMOS15_S_4_V of IOBUF_LVCMOS15_S_4 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS15_S_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_s_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS15 I/O Standard Slow Slew 6 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS15_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:48 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS15_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS15_S_6 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS15_S_6; + +architecture IOBUF_LVCMOS15_S_6_V of IOBUF_LVCMOS15_S_6 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS15_S_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos15_s_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS15 I/O Standard Slow Slew 8 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS15_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:48 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS15_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS15_S_8 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS15_S_8; + +architecture IOBUF_LVCMOS15_S_8_V of IOBUF_LVCMOS15_S_8 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS15_S_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS18 I/O Standard +-- /___/ /\ Filename : IOBUF_LVCMOS18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:48 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS18 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS18; + +architecture IOBUF_LVCMOS18_V of IOBUF_LVCMOS18 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_f_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS18 I/O Standard Fast Slew 12 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS18_F_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:48 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS18_F_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS18_F_12 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS18_F_12; + +architecture IOBUF_LVCMOS18_F_12_V of IOBUF_LVCMOS18_F_12 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS18_F_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_f_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS18 I/O Standard Fast Slew 16 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS18_F_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:48 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS18_F_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS18_F_16 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS18_F_16; + +architecture IOBUF_LVCMOS18_F_16_V of IOBUF_LVCMOS18_F_16 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS18_F_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_f_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS18 I/O Standard Fast Slew 2 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS18_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:48 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS18_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS18_F_2 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS18_F_2; + +architecture IOBUF_LVCMOS18_F_2_V of IOBUF_LVCMOS18_F_2 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS18_F_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_f_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS18 I/O Standard Fast Slew 4 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS18_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:48 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS18_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS18_F_4 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS18_F_4; + +architecture IOBUF_LVCMOS18_F_4_V of IOBUF_LVCMOS18_F_4 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS18_F_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_f_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS18 I/O Standard Fast Slew 6 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS18_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:48 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS18_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS18_F_6 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS18_F_6; + +architecture IOBUF_LVCMOS18_F_6_V of IOBUF_LVCMOS18_F_6 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS18_F_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_f_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS18 I/O Standard Fast Slew 8 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS18_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:49 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS18_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS18_F_8 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS18_F_8; + +architecture IOBUF_LVCMOS18_F_8_V of IOBUF_LVCMOS18_F_8 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS18_F_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_s_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS18 I/O Standard Slow Slew 12 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS18_S_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:49 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS18_S_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS18_S_12 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS18_S_12; + +architecture IOBUF_LVCMOS18_S_12_V of IOBUF_LVCMOS18_S_12 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS18_S_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_s_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS18 I/O Standard Slow Slew 16 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS18_S_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:49 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS18_S_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS18_S_16 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS18_S_16; + +architecture IOBUF_LVCMOS18_S_16_V of IOBUF_LVCMOS18_S_16 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS18_S_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_s_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS18 I/O Standard Slow Slew 2 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS18_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:49 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS18_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS18_S_2 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS18_S_2; + +architecture IOBUF_LVCMOS18_S_2_V of IOBUF_LVCMOS18_S_2 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS18_S_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_s_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS18 I/O Standard Slow Slew 4 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS18_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:49 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS18_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS18_S_4 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS18_S_4; + +architecture IOBUF_LVCMOS18_S_4_V of IOBUF_LVCMOS18_S_4 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS18_S_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_s_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS18 I/O Standard Slow Slew 6 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS18_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:49 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS18_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS18_S_6 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS18_S_6; + +architecture IOBUF_LVCMOS18_S_6_V of IOBUF_LVCMOS18_S_6 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS18_S_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos18_s_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS18 I/O Standard Slow Slew 8 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS18_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:49 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS18_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS18_S_8 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS18_S_8; + +architecture IOBUF_LVCMOS18_S_8_V of IOBUF_LVCMOS18_S_8 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS18_S_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS2 I/O Standard +-- /___/ /\ Filename : IOBUF_LVCMOS2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:49 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS2 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS2; + +architecture IOBUF_LVCMOS2_V of IOBUF_LVCMOS2 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS25 I/O Standard +-- /___/ /\ Filename : IOBUF_LVCMOS25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:50 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS25 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS25; + +architecture IOBUF_LVCMOS25_V of IOBUF_LVCMOS25 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS25_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_f_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 12 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS25_F_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:50 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS25_F_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS25_F_12 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS25_F_12; + +architecture IOBUF_LVCMOS25_F_12_V of IOBUF_LVCMOS25_F_12 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS25_F_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_f_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 16 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS25_F_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:50 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS25_F_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS25_F_16 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS25_F_16; + +architecture IOBUF_LVCMOS25_F_16_V of IOBUF_LVCMOS25_F_16 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS25_F_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_f_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 2 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS25_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:50 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS25_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS25_F_2 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS25_F_2; + +architecture IOBUF_LVCMOS25_F_2_V of IOBUF_LVCMOS25_F_2 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS25_F_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_f_24.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 24 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS25_F_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:50 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS25_F_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS25_F_24 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS25_F_24; + +architecture IOBUF_LVCMOS25_F_24_V of IOBUF_LVCMOS25_F_24 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS25_F_24_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_f_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 4 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS25_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:50 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS25_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS25_F_4 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS25_F_4; + +architecture IOBUF_LVCMOS25_F_4_V of IOBUF_LVCMOS25_F_4 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS25_F_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_f_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 6 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS25_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:50 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS25_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS25_F_6 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS25_F_6; + +architecture IOBUF_LVCMOS25_F_6_V of IOBUF_LVCMOS25_F_6 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS25_F_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_f_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 8 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS25_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:51 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS25_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS25_F_8 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS25_F_8; + +architecture IOBUF_LVCMOS25_F_8_V of IOBUF_LVCMOS25_F_8 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS25_F_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_s_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 12 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS25_S_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:51 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS25_S_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS25_S_12 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS25_S_12; + +architecture IOBUF_LVCMOS25_S_12_V of IOBUF_LVCMOS25_S_12 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS25_S_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_s_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 16 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS25_S_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:51 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS25_S_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS25_S_16 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS25_S_16; + +architecture IOBUF_LVCMOS25_S_16_V of IOBUF_LVCMOS25_S_16 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS25_S_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_s_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 2 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS25_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:51 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS25_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS25_S_2 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS25_S_2; + +architecture IOBUF_LVCMOS25_S_2_V of IOBUF_LVCMOS25_S_2 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS25_S_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_s_24.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 24 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS25_S_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:51 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS25_S_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS25_S_24 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS25_S_24; + +architecture IOBUF_LVCMOS25_S_24_V of IOBUF_LVCMOS25_S_24 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS25_S_24_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_s_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 4 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS25_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:51 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS25_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS25_S_4 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS25_S_4; + +architecture IOBUF_LVCMOS25_S_4_V of IOBUF_LVCMOS25_S_4 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS25_S_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_s_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 6 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS25_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:51 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS25_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS25_S_6 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS25_S_6; + +architecture IOBUF_LVCMOS25_S_6_V of IOBUF_LVCMOS25_S_6 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS25_S_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos25_s_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 8 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS25_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:51 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS25_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS25_S_8 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS25_S_8; + +architecture IOBUF_LVCMOS25_S_8_V of IOBUF_LVCMOS25_S_8 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS25_S_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS33 I/O Standard +-- /___/ /\ Filename : IOBUF_LVCMOS33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:51 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS33 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS33; + +architecture IOBUF_LVCMOS33_V of IOBUF_LVCMOS33 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS33_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_f_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 12 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS33_F_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:52 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS33_F_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS33_F_12 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS33_F_12; + +architecture IOBUF_LVCMOS33_F_12_V of IOBUF_LVCMOS33_F_12 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS33_F_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_f_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 16 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS33_F_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:52 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS33_F_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS33_F_16 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS33_F_16; + +architecture IOBUF_LVCMOS33_F_16_V of IOBUF_LVCMOS33_F_16 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS33_F_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_f_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 2 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS33_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:52 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS33_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS33_F_2 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS33_F_2; + +architecture IOBUF_LVCMOS33_F_2_V of IOBUF_LVCMOS33_F_2 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS33_F_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_f_24.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 24 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS33_F_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:52 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS33_F_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS33_F_24 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS33_F_24; + +architecture IOBUF_LVCMOS33_F_24_V of IOBUF_LVCMOS33_F_24 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS33_F_24_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_f_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 4 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS33_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:52 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS33_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS33_F_4 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS33_F_4; + +architecture IOBUF_LVCMOS33_F_4_V of IOBUF_LVCMOS33_F_4 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS33_F_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_f_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 6 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS33_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:52 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS33_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS33_F_6 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS33_F_6; + +architecture IOBUF_LVCMOS33_F_6_V of IOBUF_LVCMOS33_F_6 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS33_F_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_f_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 8 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS33_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:52 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS33_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS33_F_8 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS33_F_8; + +architecture IOBUF_LVCMOS33_F_8_V of IOBUF_LVCMOS33_F_8 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS33_F_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_s_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 12 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS33_S_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:52 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS33_S_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS33_S_12 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS33_S_12; + +architecture IOBUF_LVCMOS33_S_12_V of IOBUF_LVCMOS33_S_12 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS33_S_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_s_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 16 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS33_S_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:52 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS33_S_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS33_S_16 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS33_S_16; + +architecture IOBUF_LVCMOS33_S_16_V of IOBUF_LVCMOS33_S_16 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS33_S_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_s_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 2 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS33_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:53 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS33_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS33_S_2 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS33_S_2; + +architecture IOBUF_LVCMOS33_S_2_V of IOBUF_LVCMOS33_S_2 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS33_S_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_s_24.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 24 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS33_S_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:53 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS33_S_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS33_S_24 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS33_S_24; + +architecture IOBUF_LVCMOS33_S_24_V of IOBUF_LVCMOS33_S_24 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS33_S_24_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_s_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 4 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS33_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:53 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS33_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS33_S_4 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS33_S_4; + +architecture IOBUF_LVCMOS33_S_4_V of IOBUF_LVCMOS33_S_4 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS33_S_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_s_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 6 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS33_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:53 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS33_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS33_S_6 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS33_S_6; + +architecture IOBUF_LVCMOS33_S_6_V of IOBUF_LVCMOS33_S_6 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS33_S_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvcmos33_s_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 8 mA Drive +-- /___/ /\ Filename : IOBUF_LVCMOS33_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:53 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVCMOS33_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVCMOS33_S_8 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVCMOS33_S_8; + +architecture IOBUF_LVCMOS33_S_8_V of IOBUF_LVCMOS33_S_8 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVCMOS33_S_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvdci_15.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVDCI_15 I/O Standard +-- /___/ /\ Filename : IOBUF_LVDCI_15.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:53 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVDCI_15 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVDCI_15 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVDCI_15; + +architecture IOBUF_LVDCI_15_V of IOBUF_LVDCI_15 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVDCI_15_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvdci_18.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVDCI_18 I/O Standard +-- /___/ /\ Filename : IOBUF_LVDCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:53 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVDCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVDCI_18 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVDCI_18; + +architecture IOBUF_LVDCI_18_V of IOBUF_LVDCI_18 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVDCI_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvdci_25.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVDCI_25 I/O Standard +-- /___/ /\ Filename : IOBUF_LVDCI_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:53 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVDCI_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVDCI_25 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVDCI_25; + +architecture IOBUF_LVDCI_25_V of IOBUF_LVDCI_25 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVDCI_25_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvdci_33.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVDCI_33 I/O Standard +-- /___/ /\ Filename : IOBUF_LVDCI_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:53 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVDCI_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVDCI_33 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVDCI_33; + +architecture IOBUF_LVDCI_33_V of IOBUF_LVDCI_33 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVDCI_33_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvdci_dv2_15.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVDCI_DV2_15 I/O Standard +-- /___/ /\ Filename : IOBUF_LVDCI_DV2_15.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:54 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVDCI_DV2_15 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVDCI_DV2_15 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVDCI_DV2_15; + +architecture IOBUF_LVDCI_DV2_15_V of IOBUF_LVDCI_DV2_15 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVDCI_DV2_15_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvdci_dv2_18.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVDCI_DV2_18 I/O Standard +-- /___/ /\ Filename : IOBUF_LVDCI_DV2_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:54 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVDCI_DV2_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVDCI_DV2_18 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVDCI_DV2_18; + +architecture IOBUF_LVDCI_DV2_18_V of IOBUF_LVDCI_DV2_18 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVDCI_DV2_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvdci_dv2_25.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVDCI_DV2_25 I/O Standard +-- /___/ /\ Filename : IOBUF_LVDCI_DV2_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:54 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVDCI_DV2_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVDCI_DV2_25 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVDCI_DV2_25; + +architecture IOBUF_LVDCI_DV2_25_V of IOBUF_LVDCI_DV2_25 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVDCI_DV2_25_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvdci_dv2_33.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVDCI_DV2_33 I/O Standard +-- /___/ /\ Filename : IOBUF_LVDCI_DV2_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:54 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVDCI_DV2_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVDCI_DV2_33 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVDCI_DV2_33; + +architecture IOBUF_LVDCI_DV2_33_V of IOBUF_LVDCI_DV2_33 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVDCI_DV2_33_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvds.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVDS I/O Standard +-- /___/ /\ Filename : IOBUF_LVDS.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:54 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVDS ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVDS is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVDS; + +architecture IOBUF_LVDS_V of IOBUF_LVDS is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVDS_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvpecl.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVPECL I/O Standard +-- /___/ /\ Filename : IOBUF_LVPECL.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:54 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVPECL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVPECL is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVPECL; + +architecture IOBUF_LVPECL_V of IOBUF_LVPECL is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVPECL_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVTTL I/O Standard +-- /___/ /\ Filename : IOBUF_LVTTL.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:54 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVTTL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVTTL is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVTTL; + +architecture IOBUF_LVTTL_V of IOBUF_LVTTL is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVTTL_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_f_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 12 mA Drive +-- /___/ /\ Filename : IOBUF_LVTTL_F_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:54 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVTTL_F_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVTTL_F_12 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVTTL_F_12; + +architecture IOBUF_LVTTL_F_12_V of IOBUF_LVTTL_F_12 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVTTL_F_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_f_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 16 mA Drive +-- /___/ /\ Filename : IOBUF_LVTTL_F_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:54 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVTTL_F_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVTTL_F_16 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVTTL_F_16; + +architecture IOBUF_LVTTL_F_16_V of IOBUF_LVTTL_F_16 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVTTL_F_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_f_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 2 mA Drive +-- /___/ /\ Filename : IOBUF_LVTTL_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:55 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVTTL_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVTTL_F_2 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVTTL_F_2; + +architecture IOBUF_LVTTL_F_2_V of IOBUF_LVTTL_F_2 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVTTL_F_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_f_24.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 24 mA Drive +-- /___/ /\ Filename : IOBUF_LVTTL_F_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:55 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVTTL_F_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVTTL_F_24 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVTTL_F_24; + +architecture IOBUF_LVTTL_F_24_V of IOBUF_LVTTL_F_24 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVTTL_F_24_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_f_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 4 mA Drive +-- /___/ /\ Filename : IOBUF_LVTTL_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:55 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVTTL_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVTTL_F_4 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVTTL_F_4; + +architecture IOBUF_LVTTL_F_4_V of IOBUF_LVTTL_F_4 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVTTL_F_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_f_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 6 mA Drive +-- /___/ /\ Filename : IOBUF_LVTTL_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:55 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVTTL_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVTTL_F_6 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVTTL_F_6; + +architecture IOBUF_LVTTL_F_6_V of IOBUF_LVTTL_F_6 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVTTL_F_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_f_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 8 mA Drive +-- /___/ /\ Filename : IOBUF_LVTTL_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:55 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVTTL_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVTTL_F_8 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVTTL_F_8; + +architecture IOBUF_LVTTL_F_8_V of IOBUF_LVTTL_F_8 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVTTL_F_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_s_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 12 mA Drive +-- /___/ /\ Filename : IOBUF_LVTTL_S_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:55 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVTTL_S_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVTTL_S_12 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVTTL_S_12; + +architecture IOBUF_LVTTL_S_12_V of IOBUF_LVTTL_S_12 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVTTL_S_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_s_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 16 mA Drive +-- /___/ /\ Filename : IOBUF_LVTTL_S_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:55 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVTTL_S_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVTTL_S_16 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVTTL_S_16; + +architecture IOBUF_LVTTL_S_16_V of IOBUF_LVTTL_S_16 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVTTL_S_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_s_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 2 mA Drive +-- /___/ /\ Filename : IOBUF_LVTTL_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:55 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVTTL_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVTTL_S_2 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVTTL_S_2; + +architecture IOBUF_LVTTL_S_2_V of IOBUF_LVTTL_S_2 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVTTL_S_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_s_24.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 24 mA Drive +-- /___/ /\ Filename : IOBUF_LVTTL_S_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVTTL_S_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVTTL_S_24 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVTTL_S_24; + +architecture IOBUF_LVTTL_S_24_V of IOBUF_LVTTL_S_24 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVTTL_S_24_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_s_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 4 mA Drive +-- /___/ /\ Filename : IOBUF_LVTTL_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVTTL_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVTTL_S_4 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVTTL_S_4; + +architecture IOBUF_LVTTL_S_4_V of IOBUF_LVTTL_S_4 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVTTL_S_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_s_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 6 mA Drive +-- /___/ /\ Filename : IOBUF_LVTTL_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVTTL_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVTTL_S_6 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVTTL_S_6; + +architecture IOBUF_LVTTL_S_6_V of IOBUF_LVTTL_S_6 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVTTL_S_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_lvttl_s_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 8 mA Drive +-- /___/ /\ Filename : IOBUF_LVTTL_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_LVTTL_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_LVTTL_S_8 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_LVTTL_S_8; + +architecture IOBUF_LVTTL_S_8_V of IOBUF_LVTTL_S_8 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_LVTTL_S_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_pci33_3.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with PCI33_3 I/O Standard +-- /___/ /\ Filename : IOBUF_PCI33_3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_PCI33_3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_PCI33_3 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_PCI33_3; + +architecture IOBUF_PCI33_3_V of IOBUF_PCI33_3 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_PCI33_3_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_pci33_5.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with PCI33_5 I/O Standard +-- /___/ /\ Filename : IOBUF_PCI33_5.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_PCI33_5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_PCI33_5 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_PCI33_5; + +architecture IOBUF_PCI33_5_V of IOBUF_PCI33_5 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_PCI33_5_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_pci66_3.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with PCI66_3 I/O Standard +-- /___/ /\ Filename : IOBUF_PCI66_3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_PCI66_3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_PCI66_3 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_PCI66_3; + +architecture IOBUF_PCI66_3_V of IOBUF_PCI66_3 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_PCI66_3_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_pcix.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with PCIX I/O Standard +-- /___/ /\ Filename : IOBUF_PCIX.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_PCIX ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_PCIX is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_PCIX; + +architecture IOBUF_PCIX_V of IOBUF_PCIX is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_PCIX_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_pcix66_3.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with PCIX66_3 I/O Standard +-- /___/ /\ Filename : IOBUF_PCIX66_3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_PCIX66_3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_PCIX66_3 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_PCIX66_3; + +architecture IOBUF_PCIX66_3_V of IOBUF_PCIX66_3 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_PCIX66_3_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_s_12.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with Slow Slew 12 mA Drive +-- /___/ /\ Filename : IOBUF_S_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:57 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_S_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_S_12 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_S_12; + +architecture IOBUF_S_12_V of IOBUF_S_12 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_S_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_s_16.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with Slow Slew 16 mA Drive +-- /___/ /\ Filename : IOBUF_S_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:57 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_S_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_S_16 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_S_16; + +architecture IOBUF_S_16_V of IOBUF_S_16 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_S_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_s_2.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with Slow Slew 2 mA Drive +-- /___/ /\ Filename : IOBUF_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:57 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_S_2 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_S_2; + +architecture IOBUF_S_2_V of IOBUF_S_2 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_S_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_s_24.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with Slow Slew 24 mA Drive +-- /___/ /\ Filename : IOBUF_S_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:57 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_S_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_S_24 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_S_24; + +architecture IOBUF_S_24_V of IOBUF_S_24 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_S_24_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_s_4.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with Slow Slew 4 mA Drive +-- /___/ /\ Filename : IOBUF_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:57 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_S_4 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_S_4; + +architecture IOBUF_S_4_V of IOBUF_S_4 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_S_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_s_6.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with Slow Slew 6 mA Drive +-- /___/ /\ Filename : IOBUF_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:57 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_S_6 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_S_6; + +architecture IOBUF_S_6_V of IOBUF_S_6 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_S_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_s_8.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with Slow Slew 8 mA Drive +-- /___/ /\ Filename : IOBUF_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:57 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_S_8 is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_S_8; + +architecture IOBUF_S_8_V of IOBUF_S_8 is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_S_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_sstl18_i.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with SSTL18_I I/O Standard +-- /___/ /\ Filename : IOBUF_SSTL18_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:57 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_SSTL18_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_SSTL18_I is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_SSTL18_I; + +architecture IOBUF_SSTL18_I_V of IOBUF_SSTL18_I is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_SSTL18_I_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_sstl18_ii.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with SSTL18_II I/O Standard +-- /___/ /\ Filename : IOBUF_SSTL18_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:57 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_SSTL18_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_SSTL18_II is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_SSTL18_II; + +architecture IOBUF_SSTL18_II_V of IOBUF_SSTL18_II is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_SSTL18_II_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_sstl18_ii_dci.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with SSTL18_II_DCI I/O Standard +-- /___/ /\ Filename : IOBUF_SSTL18_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:58 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_SSTL18_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_SSTL18_II_DCI is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_SSTL18_II_DCI; + +architecture IOBUF_SSTL18_II_DCI_V of IOBUF_SSTL18_II_DCI is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_SSTL18_II_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_sstl2_i.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with SSTL2_I I/O Standard +-- /___/ /\ Filename : IOBUF_SSTL2_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:58 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_SSTL2_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_SSTL2_I is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_SSTL2_I; + +architecture IOBUF_SSTL2_I_V of IOBUF_SSTL2_I is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_SSTL2_I_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_sstl2_ii.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with SSTL2_II I/O Standard +-- /___/ /\ Filename : IOBUF_SSTL2_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:58 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_SSTL2_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_SSTL2_II is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_SSTL2_II; + +architecture IOBUF_SSTL2_II_V of IOBUF_SSTL2_II is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_SSTL2_II_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_sstl2_ii_dci.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with SSTL2_II_DCI I/O Standard +-- /___/ /\ Filename : IOBUF_SSTL2_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:58 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_SSTL2_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_SSTL2_II_DCI is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_SSTL2_II_DCI; + +architecture IOBUF_SSTL2_II_DCI_V of IOBUF_SSTL2_II_DCI is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_SSTL2_II_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_sstl3_i.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with SSTL3_I I/O Standard +-- /___/ /\ Filename : IOBUF_SSTL3_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:58 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_SSTL3_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_SSTL3_I is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_SSTL3_I; + +architecture IOBUF_SSTL3_I_V of IOBUF_SSTL3_I is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_SSTL3_I_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_sstl3_ii.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with SSTL3_II I/O Standard +-- /___/ /\ Filename : IOBUF_SSTL3_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:58 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_SSTL3_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_SSTL3_II is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_SSTL3_II; + +architecture IOBUF_SSTL3_II_V of IOBUF_SSTL3_II is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_SSTL3_II_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobuf_sstl3_ii_dci.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer with SSTL3_II_DCI I/O Standard +-- /___/ /\ Filename : IOBUF_SSTL3_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:58 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUF_SSTL3_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUF_SSTL3_II_DCI is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end IOBUF_SSTL3_II_DCI; + +architecture IOBUF_SSTL3_II_DCI_V of IOBUF_SSTL3_II_DCI is +begin + VPKGBehavior : process (IO, I, T) + begin + O <= TO_X01(IO); + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUF_SSTL3_II_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobufds.vhd,v 1.7 2007/07/26 23:51:52 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Diffential Signaling I/O Buffer +-- /___/ /\ Filename : IOBUFDS.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:58 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 07/26/07 - Add else to handle x case for output (CR 424214). +-- End Revision + + +----- CELL IOBUFDS ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUFDS is + generic( + CAPACITANCE : string := "DONT_CARE"; + IBUF_DELAY_VALUE : string := "0"; + IFD_DELAY_VALUE : string := "AUTO"; + IOSTANDARD : string := "DEFAULT" + ); + + port( + O : out std_ulogic; + + IO : inout std_ulogic; + IOB : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); +end IOBUFDS; + +architecture IOBUFDS_V of IOBUFDS is +begin + + prcs_init : process + variable FIRST_TIME : boolean := true; + begin + + if(FIRST_TIME = true) then + if((CAPACITANCE = "LOW") or + (CAPACITANCE = "NORMAL") or + (CAPACITANCE = "DONT_CARE")) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error : The allowed values for CAPACITANCE are LOW, NORMAL or DONT_CARE" + severity failure; + end if; + end if; + +-- + if((IBUF_DELAY_VALUE = "0") or (IBUF_DELAY_VALUE = "1") or + (IBUF_DELAY_VALUE = "2") or (IBUF_DELAY_VALUE = "3") or + (IBUF_DELAY_VALUE = "4") or (IBUF_DELAY_VALUE = "5") or + (IBUF_DELAY_VALUE = "6") or (IBUF_DELAY_VALUE = "7") or + (IBUF_DELAY_VALUE = "8") or (IBUF_DELAY_VALUE = "9") or + (IBUF_DELAY_VALUE = "10") or (IBUF_DELAY_VALUE = "11") or + (IBUF_DELAY_VALUE = "12") or (IBUF_DELAY_VALUE = "13") or + (IBUF_DELAY_VALUE = "14") or (IBUF_DELAY_VALUE = "15") or + (IBUF_DELAY_VALUE = "16")) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The Legal values for IBUF_DELAY_VALUE are 0, 1, 2, ... , or 16. " + severity Failure; + end if; + +-- + if((IFD_DELAY_VALUE = "AUTO") or (IFD_DELAY_VALUE = "auto") or + (IFD_DELAY_VALUE = "0") or (IFD_DELAY_VALUE = "1") or + (IFD_DELAY_VALUE = "2") or (IFD_DELAY_VALUE = "3") or + (IFD_DELAY_VALUE = "4") or (IFD_DELAY_VALUE = "5") or + (IFD_DELAY_VALUE = "6") or (IFD_DELAY_VALUE = "7") or + (IFD_DELAY_VALUE = "8")) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The Legal values for IFD_DELAY_VALUE are AUTO, 0, 1, ... , or 8" + severity Failure; + end if; + + wait; + end process prcs_init; + + VPKGBehavior : process (IO, IOB, I, T) + begin + +-- if (IO /= IOB ) then +-- O <= TO_X01(IO); +-- else +-- O <= 'X'; +-- end if; + + if (IO = 'X' or IOB = 'X' ) then + O <= 'X'; + elsif (IO /= IOB ) then + O <= TO_X01(IO); + else + O <= 'X'; + end if; + + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + + if ((T = '1') or (T = 'H')) then + IOB <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if (((not I) = '1') or ((not I) = 'H')) then + IOB <= '1'; + elsif (((not I) = '0') or ((not I) = 'L')) then + IOB <= '0'; + elsif ((not I) = 'U') then + IOB <= 'U'; + else + IOB <= 'X'; + end if; + elsif (T = 'U') then + IOB <= 'U'; + else + IOB <= 'X'; + end if; + end process; + + +end IOBUFDS_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/iobufds_blvds_25.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Differential Signaling I/O Buffer with BLVDS_25 I/O Standard +-- /___/ /\ Filename : IOBUFDS_BLVDS_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:58 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUFDS_BLVDS_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUFDS_BLVDS_25 is + + port( + O : out std_ulogic; + + IO : inout std_ulogic; + IOB : inout std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); +end IOBUFDS_BLVDS_25; + +architecture IOBUFDS_BLVDS_25_V of IOBUFDS_BLVDS_25 is +begin + + VPKGBehavior : process (IO, IOB, I, T) + begin + if (IO /= IOB ) then + O <= TO_X01(IO); + else + O <= 'X'; + end if; + + if ((T = '1') or (T = 'H')) then + IO <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (T = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + + if ((T = '1') or (T = 'H')) then + IOB <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if (((not I) = '1') or ((not I) = 'H')) then + IOB <= '1'; + elsif (((not I) = '0') or ((not I) = 'L')) then + IOB <= '0'; + elsif ((not I) = 'U') then + IOB <= 'U'; + else + IOB <= 'X'; + end if; + elsif (T = 'U') then + IOB <= 'U'; + else + IOB <= 'X'; + end if; + end process; + +end IOBUFDS_BLVDS_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/keeper.vhd,v 1.7 2005/05/06 19:55:07 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Weak Keeper +-- /___/ /\ Filename : KEEPER.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:59 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 05/09/05 - Fixed CR#198911 + +----- CELL KEEPER ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity KEEPER is + port( + O : inout std_ulogic := 'W' + ); +end KEEPER; + +architecture KEEPER_V of KEEPER is +begin + process (O) + begin + if (O'event) then + if (O = '1') then + O <= 'H'; + elsif (O = '0') then + O <= 'L'; + elsif (O = 'X') then + O <= 'W'; + end if; + end if; + end process; +end KEEPER_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ld.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Transparent Data Latch +-- /___/ /\ Filename : LD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:59 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LD is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic := '0'; + + D : in std_ulogic; + G : in std_ulogic + ); +end LD; + +architecture LD_V of LD is +begin + VITALBehavior : process(D, G) + begin + if (G = '1') then + Q <= D after 100 ps; + end if; + end process; +end LD_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ld_1.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Transparent Data Latch with Inverted Gate +-- /___/ /\ Filename : LD_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:59 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LD_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LD_1 is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic := '0'; + + D : in std_ulogic; + G : in std_ulogic + ); +end LD_1; + +architecture LD_1_V of LD_1 is +begin + VITALBehavior : process(D, G) + begin + if (G = '0') then + Q <= D after 100 ps; + end if; + end process; +end LD_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldc.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Transparent Data Latch with Asynchronous Clear +-- /___/ /\ Filename : LDC.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:59 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LDC ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LDC is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + CLR : in std_ulogic; + D : in std_ulogic; + G : in std_ulogic + ); +end LDC; + +architecture LDC_V of LDC is +begin + VITALBehavior : process(CLR, D, G) + begin + if (CLR = '1') then + Q <= '0'; + elsif (G = '1') then + Q <= D after 100 ps; + end if; + end process; +end LDC_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldc_1.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Transparent Data Latch with Asynchronous Clear and Inverted Gate +-- /___/ /\ Filename : LDC_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:59 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LDC_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LDC_1 is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + CLR : in std_ulogic; + D : in std_ulogic; + G : in std_ulogic + ); +end LDC_1; + +architecture LDC_1_V of LDC_1 is +begin + VITALBehavior : process(CLR, D, G) + begin + if (CLR = '1') then + Q <= '0'; + elsif (G = '0') then + Q <= D after 100 ps; + end if; + end process; +end LDC_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldce.vhd,v 1.4 2004/04/08 18:46:25 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Transparent Data Latch with Asynchronous Clear and Gate Enable +-- /___/ /\ Filename : LDCE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:00 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LDCE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LDCE is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + CLR : in std_ulogic; + D : in std_ulogic; + G : in std_ulogic; + GE : in std_ulogic + ); +end LDCE; + +architecture LDCE_V of LDCE is +begin + + VITALBehavior : process(CLR, D, G, GE) + begin + if (CLR = '1') then + Q <= '0'; + elsif ((GE = '1') and (G = '1')) then + Q <= D after 100 ps; + end if; + end process; +end LDCE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldce_1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Transparent Data Latch with Asynchronous Clear, Gate Enable and Inverted Gate +-- /___/ /\ Filename : LDCE_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:00 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LDCE_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LDCE_1 is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + CLR : in std_ulogic; + D : in std_ulogic; + G : in std_ulogic; + GE : in std_ulogic + ); +end LDCE_1; + +architecture LDCE_1_V of LDCE_1 is +begin + VITALBehavior : process(CLR, D, G, GE) + begin + if (CLR = '1') then + Q <= '0'; + elsif ((GE = '1') and (G = '0')) then + Q <= D after 100 ps; + end if; + end process; +end LDCE_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldcp.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Transparent Data Latch with Asynchronous Clear and Preset +-- /___/ /\ Filename : LDCP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:00 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LDCP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LDCP is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + CLR : in std_ulogic; + D : in std_ulogic; + G : in std_ulogic; + PRE : in std_ulogic + ); +end LDCP; + +architecture LDCP_V of LDCP is +begin + VITALBehavior : process(CLR, D, G, PRE) + begin + if (CLR = '1') then + Q <= '0'; + elsif (PRE = '1') then + Q <= '1'; + elsif (G = '1') then + Q <= D after 100 ps; + end if; + end process; +end LDCP_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldcp_1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Transparent Data Latch with Asynchronous Clear and Preset and Inverted Gate +-- /___/ /\ Filename : LDCP_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:00 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LDCP_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LDCP_1 is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + CLR : in std_ulogic; + D : in std_ulogic; + G : in std_ulogic; + PRE : in std_ulogic + ); +end LDCP_1; + +architecture LDCP_1_V of LDCP_1 is +begin + VITALBehavior : process(CLR, D, G, PRE) + begin + if (CLR = '1') then + Q <= '0'; + elsif (PRE = '1') then + Q <= '1'; + elsif (G = '0') then + Q <= D after 100 ps; + end if; + end process; +end LDCP_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldcpe.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Transparent Data Latch with Asynchronous Clear and Preset and Gate Enable +-- /___/ /\ Filename : LDCPE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:00 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LDCPE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LDCPE is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + CLR : in std_ulogic; + D : in std_ulogic; + G : in std_ulogic; + GE : in std_ulogic; + PRE : in std_ulogic + ); +end LDCPE; + +architecture LDCPE_V of LDCPE is +begin + VITALBehavior : process(CLR, D, G, GE, PRE) + begin + if (CLR = '1') then + Q <= '0'; + elsif (PRE = '1') then + Q <= '1'; + elsif ((GE = '1') and (G = '1'))then + Q <= D after 100 ps; + end if; + end process; +end LDCPE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldcpe_1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Transparent Data Latch with Asynchronous Clear and Preset, Gate Enable and Inverted Gate +-- /___/ /\ Filename : LDCPE_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:00 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LDCPE_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LDCPE_1 is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + CLR : in std_ulogic; + D : in std_ulogic; + G : in std_ulogic; + GE : in std_ulogic; + PRE : in std_ulogic + ); +end LDCPE_1; + +architecture LDCPE_1_V of LDCPE_1 is +begin + VITALBehavior : process(CLR, D, G, GE, PRE) + begin + if (CLR = '1') then + Q <= '0'; + elsif (PRE = '1') then + Q <= '1'; + elsif ((GE = '1') and (G = '0')) then + Q <= D after 100 ps; + end if; + end process; +end LDCPE_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lde.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Transparent Data Latch with Gate Enable +-- /___/ /\ Filename : LDE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:00 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LDE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LDE is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic := '0'; + + D : in std_ulogic; + G : in std_ulogic; + GE : in std_ulogic + ); +end LDE; + +architecture LDE_V of LDE is +begin + VITALBehavior : process(D, G, GE) + begin + if (GE = '1' and G = '1') then + Q <= D after 100 ps; + end if; + end process; +end LDE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lde_1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Transparent Data Latch with Gate Enable and Inverted Gate +-- /___/ /\ Filename : LDE_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:00 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LDE_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LDE_1 is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic := '0'; + + D : in std_ulogic; + G : in std_ulogic; + GE : in std_ulogic + ); +end LDE_1; + +architecture LDE_1_V of LDE_1 is +begin + VITALBehavior : process(D, G, GE) + begin + if (GE = '1' and G = '0') then + Q <= D after 100 ps; + end if; + end process; +end LDE_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldp.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Transparent Data Latch with Asynchronous Preset +-- /___/ /\ Filename : LDP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LDP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LDP is + generic( + INIT : bit := '1' + ); + + port( + Q : out std_ulogic; + + D : in std_ulogic; + G : in std_ulogic; + PRE : in std_ulogic + ); +end LDP; + +architecture LDP_V of LDP is +begin + VITALBehavior : process(D, G, PRE) + begin + if (PRE = '1') then + Q <= '1'; + elsif (G = '1') then + Q <= D after 100 ps; + end if; + end process; +end LDP_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldp_1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Transparent Data Latch with Asynchronous Preset and Inverted Gate +-- /___/ /\ Filename : LDP_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LDP_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LDP_1 is + generic( + INIT : bit := '1' + ); + + port( + Q : out std_ulogic; + + D : in std_ulogic; + G : in std_ulogic; + PRE : in std_ulogic + ); +end LDP_1; + +architecture LDP_1_V of LDP_1 is +begin + VITALBehavior : process(D, G, PRE) + begin + if (PRE = '1') then + Q <= '1'; + elsif (G = '0') then + Q <= D after 100 ps; + end if; + end process; +end LDP_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldpe.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Transparent Data Latch with Asynchronous Preset and Gate Enable +-- /___/ /\ Filename : LDPE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LDPE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LDPE is + generic( + INIT : bit := '1' + ); + + port( + Q : out std_ulogic; + + D : in std_ulogic; + G : in std_ulogic; + GE : in std_ulogic; + PRE : in std_ulogic + ); +end LDPE; + +architecture LDPE_V of LDPE is +begin + VITALBehavior : process(D, G, GE, PRE) + begin + if (PRE = '1') then + Q <= '1'; + elsif ((GE = '1') and (G = '1'))then + Q <= D after 100 ps; + end if; + end process; +end LDPE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ldpe_1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Transparent Data Latch with Asynchronous Preset, Gate Enable and Inverted Gate +-- /___/ /\ Filename : LDPE_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LDPE_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LDPE_1 is + generic( + INIT : bit := '1' + ); + + port( + Q : out std_ulogic; + + D : in std_ulogic; + G : in std_ulogic; + GE : in std_ulogic; + PRE : in std_ulogic + ); +end LDPE_1; + +architecture LDPE_1_V of LDPE_1 is +begin + VITALBehavior : process(D, G, GE, PRE) + begin + if (PRE = '1') then + Q <= '1'; + elsif ((GE = '1') and (G = '0'))then + Q <= D after 100 ps; + end if; + end process; +end LDPE_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut1.vhd,v 1.6 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 1-input Look-Up-Table with General Output +-- /___/ /\ Filename : LUT1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LUT1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LUT1 is + generic( + INIT : bit_vector := X"0" + ); + + port( + O : out std_ulogic; + + I0 : in std_ulogic + ); +end LUT1; + +architecture LUT1_V of LUT1 is + +begin + VITALBehavior : process (I0) + variable INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT); + begin + if (INIT_reg(0) = INIT_reg(1)) then + O <= INIT_reg(0); + elsif (I0 = '0') then + O <= INIT_reg(0); + elsif (I0 = '1') then + O <= INIT_reg(1); + else + O <= 'X'; + end if; + end process; +end LUT1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut1_d.vhd,v 1.6 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 1-input Look-Up-Table with Dual Output +-- /___/ /\ Filename : LUT1_D.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LUT1_D ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LUT1_D is + generic( + INIT : bit_vector := X"0" + ); + + port( + LO : out std_ulogic; + O : out std_ulogic; + + I0 : in std_ulogic + ); +end LUT1_D; + +architecture LUT1_D_V of LUT1_D is +begin + VITALBehavior : process (I0) + variable INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT); + begin + if (I0 = '0') then + O <= INIT_reg(0); + LO <= INIT_reg(0); + elsif (I0 = '1') then + O <= INIT_reg(1); + LO <= INIT_reg(1); + elsif (INIT_reg(0) = INIT_reg(1)) then + O <= INIT_reg(0); + LO <= INIT_reg(0); + else + O <= 'X'; + LO <= 'X'; + end if; + end process; +end LUT1_D_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut1_l.vhd,v 1.6 2005/03/10 22:45:34 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 1-input Look-Up-Table with Local Output +-- /___/ /\ Filename : LUT1_L.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LUT1_L ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LUT1_L is + generic( + INIT : bit_vector := X"0" + ); + + port( + LO : out std_ulogic; + + I0 : in std_ulogic + ); +end LUT1_L; + +architecture LUT1_L_V of LUT1_L is +begin + VITALBehavior : process (I0) + variable INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT); + begin + if (I0 = '0') then + LO <= INIT_reg(0); + elsif (I0 = '1') then + LO <= INIT_reg(1); + elsif (INIT_reg(0) = INIT_reg(1)) then + LO <= INIT_reg(0); + else + LO <= 'X'; + end if; + end process; +end LUT1_L_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut2.vhd,v 1.9 2006/04/21 23:39:47 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-input Look-Up-Table with General Output +-- /___/ /\ Filename : LUT2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 03/15/05 - Modified to handle the address unknown case. +-- 03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842) +-- 04/13/06 - Add address declaration. (CR229735) +-- End Revision + +----- CELL LUT2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity LUT2 is + generic( + INIT : bit_vector := X"0" + ); + + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end LUT2; + +architecture LUT2_V of LUT2 is +begin + VITALBehavior : process (I0, I1) + variable INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT); + variable address : std_logic_vector(1 downto 0); + variable address_int : integer := 0; + begin + address := I1 & I0; + address_int := SLV_TO_INT(address(1 downto 0)); + + if ((I1 xor I0) = '1' or (I1 xor I0) = '0') then + O <= INIT_reg(address_int); + else + if ((INIT_reg(0) = INIT_reg(1)) and (INIT_reg(2) = INIT_reg(3)) and + (INIT_reg(0) = INIT_reg(2))) then + O <= INIT_reg(0); + elsif ((I1 = '0') and (INIT_reg(0) = INIT_reg(1))) then + O <= INIT_reg(0); + O <= INIT_reg(0); + elsif ((I1 = '1') and (INIT_reg(2) = INIT_reg(3))) then + O <= INIT_reg(2); + elsif ((I0 = '0') and (INIT_reg(0) = INIT_reg(2))) then + O <= INIT_reg(0); + elsif ((I0 = '1') and (INIT_reg(1) = INIT_reg(3))) then + O <= INIT_reg(1); + else + O <= 'X'; + end if; + end if; + end process; +end LUT2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut2_d.vhd,v 1.9 2006/04/21 23:39:47 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-input Look-Up-Table with Dual Output +-- /___/ /\ Filename : LUT2_D.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 03/15/05 - Modified to handle the address unknown case. +-- 03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842) +-- 04/13/06 - Add address declaration. (CR229735) +-- End Revision + +----- CELL LUT2_D ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity LUT2_D is + generic( + INIT : bit_vector := X"0" + ); + + port( + LO : out std_ulogic; + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end LUT2_D; + +architecture LUT2_D_V of LUT2_D is + constant INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT); +begin + VITALBehavior : process (I0, I1) + variable address : std_logic_vector(1 downto 0); + variable address_int : integer := 0; + variable tmp_o : std_ulogic; + begin + address := I1 & I0; + address_int := SLV_TO_INT(address(1 downto 0)); + + if ((I1 xor I0) = '1' or (I1 xor I0) = '0') then + tmp_o := INIT_reg(address_int); + else + if ((INIT_reg(0) = INIT_reg(1)) and (INIT_reg(2) = INIT_reg(3)) and + (INIT_reg(0) = INIT_reg(2))) then + tmp_o := INIT_reg(0); + elsif ((I1 = '0') and (INIT_reg(0) = INIT_reg(1))) then + tmp_o := INIT_reg(0); + elsif ((I1 = '1') and (INIT_reg(2) = INIT_reg(3))) then + tmp_o := INIT_reg(2); + elsif ((I0 = '0') and (INIT_reg(0) = INIT_reg(2))) then + tmp_o := INIT_reg(0); + elsif ((I0 = '1') and (INIT_reg(1) = INIT_reg(3))) then + tmp_o := INIT_reg(1); + else + tmp_o := 'X'; + end if; + end if; + O <=tmp_o; + LO <=tmp_o; + + end process; +end LUT2_D_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut2_l.vhd,v 1.9 2006/04/21 23:39:47 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-input Look-Up-Table with Local Output +-- /___/ /\ Filename : LUT2_L.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:02 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 03/15/05 - Modified to handle the address unknown case. +-- 03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842) +-- 04/13/06 - Add address declaration. (CR229735) +-- End Revision + +----- CELL LUT2_L ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity LUT2_L is + generic( + INIT : bit_vector := X"0" + ); + + port( + LO : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end LUT2_L; + +architecture LUT2_L_V of LUT2_L is +begin + VITALBehavior : process (I0, I1) + variable INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT); + variable address : std_logic_vector(1 downto 0); + variable address_int : integer := 0; + begin + address := I1 & I0; + address_int := SLV_TO_INT(address(1 downto 0)); + + if ((I1 xor I0) = '1' or (I1 xor I0) = '0') then + LO <= INIT_reg(address_int); + else + if ((INIT_reg(0) = INIT_reg(1)) and (INIT_reg(2) = INIT_reg(3)) and + (INIT_reg(0) = INIT_reg(2))) then + LO <= INIT_reg(0); + elsif ((I1 = '0') and (INIT_reg(0) = INIT_reg(1))) then + LO <= INIT_reg(0); + elsif ((I1 = '1') and (INIT_reg(2) = INIT_reg(3))) then + LO <= INIT_reg(2); + elsif ((I0 = '0') and (INIT_reg(0) = INIT_reg(2))) then + LO <= INIT_reg(0); + elsif ((I0 = '1') and (INIT_reg(1) = INIT_reg(3))) then + LO <= INIT_reg(1); + else + LO <= 'X'; + end if; + end if; + end process; +end LUT2_L_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut3.vhd,v 1.7 2006/03/11 00:58:14 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input Look-Up-Table with General Output +-- /___/ /\ Filename : LUT3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:02 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 03/15/05 - Modified to handle the address unknown case. +-- 03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842) +-- End Revision + +----- CELL LUT3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity LUT3 is + generic( + INIT : bit_vector := X"00" + ); + + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end LUT3; + +architecture LUT3_V of LUT3 is + +function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0)) + return std_logic is + variable lut4_mux4_o : std_logic; + begin + + if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then + lut4_mux4_o := d(SLV_TO_INT(s)); + elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0' + and (d(0) xor d(2)) = '0') then + lut4_mux4_o := d(0); + elsif ((s(1) = '0') and (d(0) = d(1))) then + lut4_mux4_o := d(0); + elsif ((s(1) = '1') and (d(2) = d(3))) then + lut4_mux4_o := d(2); + elsif ((s(0) = '0') and (d(0) = d(2))) then + lut4_mux4_o := d(0); + elsif ((s(0) = '1') and (d(1) = d(3))) then + lut4_mux4_o := d(1); + else + lut4_mux4_o := 'X'; + end if; + + return (lut4_mux4_o); + + end function lut4_mux4; + constant INIT_reg : std_logic_vector(7 downto 0) := To_StdLogicVector(INIT); +begin + VITALBehavior : process (I0, I1, I2) + variable I_reg : std_logic_vector(2 downto 0); + begin + + I_reg := TO_STDLOGICVECTOR( I2 & I1 & I0); + + if ((I2 xor I1 xor I0) = '1' or (I2 xor I1 xor I0) = '0') then + O <= INIT_reg(SLV_TO_INT(I_reg)); + else + O <= lut4_mux4(('0' & '0' & lut4_mux4(INIT_reg(7 downto 4), I_reg(1 downto 0)) & + lut4_mux4(INIT_reg(3 downto 0), I_reg(1 downto 0))), ('0' & I_reg(2))); + end if; + end process; +end LUT3_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut3_d.vhd,v 1.7 2006/03/11 00:58:14 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input Look-Up-Table with Dual Output +-- /___/ /\ Filename : LUT3_D.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:02 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 03/15/05 - Modified to handle the address unknown case. +-- 03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842) +-- End Revision + +----- CELL LUT3_D ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity LUT3_D is + generic( + INIT : bit_vector := X"00" + ); + + port( + LO : out std_ulogic; + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end LUT3_D; + +architecture LUT3_D_V of LUT3_D is + +function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0)) + return std_logic is + variable lut4_mux4_o : std_logic; + begin + + if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then + lut4_mux4_o := d(SLV_TO_INT(s)); + elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0' + and (d(0) xor d(2)) = '0') then + lut4_mux4_o := d(0); + elsif ((s(1) = '0') and (d(0) = d(1))) then + lut4_mux4_o := d(0); + elsif ((s(1) = '1') and (d(2) = d(3))) then + lut4_mux4_o := d(2); + elsif ((s(0) = '0') and (d(0) = d(2))) then + lut4_mux4_o := d(0); + elsif ((s(0) = '1') and (d(1) = d(3))) then + lut4_mux4_o := d(1); + else + lut4_mux4_o := 'X'; + end if; + + return (lut4_mux4_o); + + end function lut4_mux4; + + constant INIT_reg : std_logic_vector(7 downto 0) := To_StdLogicVector(INIT); +begin + + VITALBehavior : process (I0, I1, I2) + variable I_reg : std_logic_vector(2 downto 0); + variable tmp_o : std_ulogic; + begin + + I_reg := TO_STDLOGICVECTOR( I2 & I1 & I0); + + if ((I2 xor I1 xor I0) = '1' or (I2 xor I1 xor I0) = '0') then + tmp_o := INIT_reg(SLV_TO_INT(I_reg)); + else + tmp_o := lut4_mux4(('0' & '0' & lut4_mux4(INIT_reg(7 downto 4), I_reg(1 downto 0)) & + lut4_mux4(INIT_reg(3 downto 0), I_reg(1 downto 0))), ('0' & I_reg(2))); + end if; + + O <= tmp_o; + LO <= tmp_o; + + end process; +end LUT3_D_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut3_l.vhd,v 1.7 2006/03/11 00:58:14 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input Look-Up-Table with Local Output +-- /___/ /\ Filename : LUT3_L.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:02 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 03/15/05 - Modified to handle the address unknown case. +-- 03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842) +-- End Revision + +----- CELL LUT3_L ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity LUT3_L is + generic( + INIT : bit_vector := X"00" + ); + + port( + LO : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end LUT3_L; + +architecture LUT3_L_V of LUT3_L is + +function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0)) + return std_logic is + variable lut4_mux4_o : std_logic; + begin + + if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then + lut4_mux4_o := d(SLV_TO_INT(s)); + elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0' + and (d(0) xor d(2)) = '0') then + lut4_mux4_o := d(0); + elsif ((s(1) = '0') and (d(0) = d(1))) then + lut4_mux4_o := d(0); + elsif ((s(1) = '1') and (d(2) = d(3))) then + lut4_mux4_o := d(2); + elsif ((s(0) = '0') and (d(0) = d(2))) then + lut4_mux4_o := d(0); + elsif ((s(0) = '1') and (d(1) = d(3))) then + lut4_mux4_o := d(1); + else + lut4_mux4_o := 'X'; + end if; + + return (lut4_mux4_o); + + end function lut4_mux4; + + constant INIT_reg : std_logic_vector(7 downto 0) := To_StdLogicVector(INIT); +begin + VITALBehavior : process (I0, I1, I2) + variable I_reg : std_logic_vector(2 downto 0); + begin + + I_reg := TO_STDLOGICVECTOR( I2 & I1 & I0); + + if ((I2 xor I1 xor I0) = '1' or (I2 xor I1 xor I0) = '0') then + LO <= INIT_reg(SLV_TO_INT(I_reg)); + else + LO <= lut4_mux4(('0' & '0' & lut4_mux4(INIT_reg(7 downto 4), I_reg(1 downto 0)) & + lut4_mux4(INIT_reg(3 downto 0), I_reg(1 downto 0))), ('0' & I_reg(2))); + end if; + + end process; +end LUT3_L_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut4.vhd,v 1.7 2006/03/11 00:58:14 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input Look-Up-Table with General Output +-- /___/ /\ Filename : LUT4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:02 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 03/15/05 - Modified to handle the address unknown case. +-- 03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842) +-- End Revision + +----- CELL LUT4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity LUT4 is + generic( + INIT : bit_vector := X"0000" + ); + + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end LUT4; + +architecture LUT4_V of LUT4 is + +function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) ) + return std_logic is + + variable lut4_mux4_o : std_logic; + begin + + if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then + lut4_mux4_o := d(SLV_TO_INT(s)); + elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0' + and (d(0) xor d(2)) = '0') then + lut4_mux4_o := d(0); + elsif ((s(1) = '0') and (d(0) = d(1))) then + lut4_mux4_o := d(0); + elsif ((s(1) = '1') and (d(2) = d(3))) then + lut4_mux4_o := d(2); + elsif ((s(0) = '0') and (d(0) = d(2))) then + lut4_mux4_o := d(0); + elsif ((s(0) = '1') and (d(1) = d(3))) then + lut4_mux4_o := d(1); + else + lut4_mux4_o := 'X'; + end if; + + return (lut4_mux4_o); + + end function lut4_mux4; + + constant INIT_reg : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT); +begin + + lut_p : process (I0, I1, I2, I3) +-- variable INIT_reg : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT); + variable I_reg : std_logic_vector(3 downto 0); + begin + + I_reg := TO_STDLOGICVECTOR(I3 & I2 & I1 & I0); + + if ((I3 xor I2 xor I1 xor I0) = '1' or (I3 xor I2 xor I1 xor I0) = '0') then + O <= INIT_reg(SLV_TO_INT(I_reg)); + else + + O <= lut4_mux4 ( + (lut4_mux4 ( INIT_reg(15 downto 12), I_reg(1 downto 0)) & + lut4_mux4 ( INIT_reg(11 downto 8), I_reg(1 downto 0)) & + lut4_mux4 ( INIT_reg(7 downto 4), I_reg(1 downto 0)) & + lut4_mux4 ( INIT_reg(3 downto 0), I_reg(1 downto 0))), I_reg(3 downto 2)); + + end if; + end process; +end LUT4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut4_d.vhd,v 1.7 2006/03/11 00:58:14 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input Look-Up-Table with Dual Output +-- /___/ /\ Filename : LUT4_D.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:02 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 03/15/05 - Modified to handle the address unknown case. +-- 03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842) +-- End Revision + +----- CELL LUT4_D ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity LUT4_D is + generic( + INIT : bit_vector := X"0000" + ); + + port( + LO : out std_ulogic; + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end LUT4_D; + +architecture LUT4_D_V of LUT4_D is + +function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) ) + return std_logic is + + variable lut4_mux4_o : std_logic; + begin + + if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then + lut4_mux4_o := d(SLV_TO_INT(s)); + elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0' + and (d(0) xor d(2)) = '0') then + lut4_mux4_o := d(0); + elsif ((s(1) = '0') and (d(0) = d(1))) then + lut4_mux4_o := d(0); + elsif ((s(1) = '1') and (d(2) = d(3))) then + lut4_mux4_o := d(2); + elsif ((s(0) = '0') and (d(0) = d(2))) then + lut4_mux4_o := d(0); + elsif ((s(0) = '1') and (d(1) = d(3))) then + lut4_mux4_o := d(1); + else + lut4_mux4_o := 'X'; + end if; + + return (lut4_mux4_o); + + end function lut4_mux4; + + constant INIT_reg : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT); +begin + + lut_p : process (I0, I1, I2, I3) + variable I_reg : std_logic_vector(3 downto 0); + variable tmp_o : std_ulogic; + begin + + I_reg := TO_STDLOGICVECTOR(I3 & I2 & I1 & I0); + + if ((I3 xor I2 xor I1 xor I0) = '1' or (I3 xor I2 xor I1 xor I0) = '0') then + tmp_o := INIT_reg(SLV_TO_INT(I_reg)); + else + tmp_o := lut4_mux4 ( + (lut4_mux4 ( INIT_reg(15 downto 12), I_reg(1 downto 0)) & + lut4_mux4 ( INIT_reg(11 downto 8), I_reg(1 downto 0)) & + lut4_mux4 ( INIT_reg(7 downto 4), I_reg(1 downto 0)) & + lut4_mux4 ( INIT_reg(3 downto 0), I_reg(1 downto 0))), I_reg(3 downto 2)); + end if; + O <= tmp_o; + LO <= tmp_o; + + end process; +end LUT4_D_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/lut4_l.vhd,v 1.7 2006/03/11 00:58:14 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input Look-Up-Table with Local Output +-- /___/ /\ Filename : LUT4_L.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:02 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 03/15/05 - Modified to handle the address unknown case. +-- 03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842) +-- End Revision + +----- CELL LUT4_L ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity LUT4_L is + generic( + INIT : bit_vector := X"0000" + ); + + port( + LO : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end LUT4_L; + +architecture LUT4_L_V of LUT4_L is + +function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) ) + return std_logic is + + variable lut4_mux4_o : std_logic; + begin + + if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then + lut4_mux4_o := d(SLV_TO_INT(s)); + elsif ((d(0) = d(1)) and (d(2) = d(3)) and (d(0) = d(2))) then + lut4_mux4_o := d(0); + elsif ((s(1) = '0') and (d(0) = d(1))) then + lut4_mux4_o := d(0); + elsif ((s(1) = '1') and (d(2) = d(3))) then + lut4_mux4_o := d(2); + elsif ((s(0) = '0') and (d(0) = d(2))) then + lut4_mux4_o := d(0); + elsif ((s(0) = '1') and (d(1) = d(3))) then + lut4_mux4_o := d(1); + else + lut4_mux4_o := 'X'; + end if; + + return (lut4_mux4_o); + + end function lut4_mux4; + + constant INIT_reg : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT); +begin + + lut_p : process (I0, I1, I2, I3) + variable I_reg : std_logic_vector(3 downto 0); + begin + + I_reg := TO_STDLOGICVECTOR(I3 & I2 & I1 & I0); + + if ((I3 xor I2 xor I1 xor I0) = '1' or (I3 xor I2 xor I1 xor I0) = '0') then + LO <= INIT_reg(SLV_TO_INT(I_reg)); + else + LO <= lut4_mux4 ( + (lut4_mux4 ( INIT_reg(15 downto 12), I_reg(1 downto 0)) & + lut4_mux4 ( INIT_reg(11 downto 8), I_reg(1 downto 0)) & + lut4_mux4 ( INIT_reg(7 downto 4), I_reg(1 downto 0)) & + lut4_mux4 ( INIT_reg(3 downto 0), I_reg(1 downto 0))), I_reg(3 downto 2)); + end if; +end process; +end LUT4_L_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/mult18x18.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 18X18 Signed Multiplier +-- /___/ /\ Filename : MULT18X18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:03 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL MULT18X18 ----- + +library IEEE; +use IEEE.std_logic_1164.all; + +library unisim; +use unisim.Vpkg.all; + +entity MULT18X18 is + port ( + P : out std_logic_vector (35 downto 0); + + A : in std_logic_vector (17 downto 0); + B : in std_logic_vector (17 downto 0) + ); + +end MULT18X18; + +architecture MULT18X18_V of MULT18X18 is + +function INT_TO_SLV(ARG: integer; SIZE: integer) return std_logic_vector is + + variable result : std_logic_vector (SIZE-1 downto 0); + variable temp : integer := ARG; +begin + temp := ARG; + for i in 0 to SIZE-1 loop + if (temp mod 2) = 1 then + result(i) := '1'; + else + result(i) := '0'; + end if; + if temp > 0 then + temp := temp /2 ; + elsif (temp > integer'low) then + temp := (temp-1) / 2; + else + temp := temp / 2; + end if; + end loop; + return result; +end; + +function COMPLEMENT(ARG: std_logic_vector ) return std_logic_vector is + + variable RESULT : std_logic_vector (ARG'left downto 0); + variable found1 : std_ulogic := '0'; +begin + for i in 0 to ARG'left loop + if (found1 = '0') then + RESULT(i) := ARG(i); + if (ARG(i) = '1' ) then + found1 := '1'; + end if; + else + RESULT(i) := not ARG(i); + end if; + end loop; + return result; +end; + +function VECPLUS(A, B: std_logic_vector ) return std_logic_vector is + + variable carry: std_ulogic; + variable BV, sum: std_logic_vector(A'left downto 0); + +begin + + if (A(A'left) = 'X' or B(B'left) = 'X') then + sum := (others => 'X'); + return(sum); + end if; + carry := '0'; + BV := B; + + for i in 0 to A'left loop + sum(i) := A(i) xor BV(i) xor carry; + carry := (A(i) and BV(i)) or + (A(i) and carry) or + (carry and BV(i)); + end loop; + return sum; +end; + +begin + + VITALBehaviour : process (A, B) + variable O_zd,O1_zd, O2_zd : std_logic_vector( A'length+B'length-1 downto 0); + variable IA, IB1,IB2 : integer ; + variable sign : std_ulogic := '0'; + variable A_i : std_logic_vector(A'left downto 0); + variable B_i : std_logic_vector(B'left downto 0); + + begin + + if (Is_X(A) or Is_X(B) ) then + O_zd := (others => 'X'); + else + if (A(A'left) = '1' ) then + A_i := complement(A); + else + A_i := A; + end if; + + if (B(B'left) = '1') then + B_i := complement(B); + else + B_i := B; + end if; + + IA := SLV_TO_INT(A_i); + IB1 := SLV_TO_INT(B_i (17 downto 9)); + IB2 := SLV_TO_INT(B_i (8 downto 0)); + + + O1_zd := INT_TO_SLV((IA * IB1), A'length+B'length); + -- shift I1_zd 9 to the left + for j in 0 to 8 loop + O1_zd(A'length+B'length-1 downto 0) := O1_zd(A'length+B'length-2 downto 0) & '0'; + end loop; + O2_zd := INT_TO_SLV((IA * IB2), A'length+B'length); + O_zd := VECPLUS(O1_zd, O2_zd); + + sign := A(A'left) xor B(B'left); + if (sign = '1' ) then + O_zd := complement(O_zd); + end if; + end if; + P <= O_zd; + end process VITALBehaviour; + +end MULT18X18_V ; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/mult18x18s.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 18X18 Signed Registered Multiplier +-- /___/ /\ Filename : MULT18X18S.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:03 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL MULT18X18S ----- + +library IEEE; +use IEEE.std_logic_1164.all; + +library unisim; +use unisim.Vpkg.all; + +entity MULT18X18S is + + port ( + P : out std_logic_vector (35 downto 0); + + A : in std_logic_vector (17 downto 0); + B : in std_logic_vector (17 downto 0); + C : in std_ulogic; + CE : in std_ulogic; + R : in std_ulogic + ); +end MULT18X18S; + +architecture MULT18X18S_V of MULT18X18S is + + function INT_TO_SLV(ARG : integer; SIZE : integer) return std_logic_vector is + + variable result : std_logic_vector (SIZE-1 downto 0); + variable temp : integer := ARG; + begin + temp := ARG; + for i in 0 to SIZE-1 loop + if (temp mod 2) = 1 then + result(i) := '1'; + else + result(i) := '0'; + end if; + if temp > 0 then + temp := temp /2; + elsif (temp > integer'low) then + temp := (temp-1) / 2; + else + temp := temp / 2; + end if; + end loop; + return result; + end; + + function COMPLEMENT(ARG : std_logic_vector ) return std_logic_vector is + + variable RESULT : std_logic_vector (ARG'left downto 0); + variable found1 : std_ulogic := '0'; + begin + for i in 0 to ARG'left loop + if (found1 = '0') then + RESULT(i) := ARG(i); + if (ARG(i) = '1' ) then + found1 := '1'; + end if; + else + RESULT(i) := not ARG(i); + end if; + end loop; + return result; + end; + + function VECPLUS(A, B : std_logic_vector ) return std_logic_vector is + + variable carry : std_ulogic; + variable BV, sum : std_logic_vector(A'left downto 0); + + begin + + if (A(A'left) = 'X' or B(B'left) = 'X') then + sum := (others => 'X'); + return(sum); + end if; + carry := '0'; + BV := B; + + for i in 0 to A'left loop + sum(i) := A(i) xor BV(i) xor carry; + carry := (A(i) and BV(i)) or + (A(i) and carry) or + (carry and BV(i)); + end loop; + return sum; + end; + +begin + + VITALBehaviour : process (C) + variable O_zd, O1_zd, O2_zd : std_logic_vector( A'length+B'length-1 downto 0); + variable B1_zd, B2_zd : bit_vector(A'length+B'length-1 downto 0); + variable IA, IB1, Ib2 : integer; + variable sign : std_ulogic := '0'; + variable A_i : std_logic_vector(A'left downto 0); + variable B_i : std_logic_vector(B'left downto 0); + + begin + + if (rising_edge(C)) then + if (R = '1' ) then + O_zd := (others => '0'); + elsif (CE = '1' ) then + if (Is_X(A) or Is_X(B) ) then + O_zd := (others => 'X'); + else + if (A(A'left) = '1' ) then + A_i := complement(A); + else + A_i := A; + end if; + + if (B(B'left) = '1') then + B_i := complement(B); + else + B_i := B; + end if; + + IA := SLV_TO_INT(A_i); + IB1 := SLV_TO_INT(B_i (17 downto 9)); + IB2 := SLV_TO_INT(B_i (8 downto 0)); + + + O1_zd := INT_TO_SLV((IA * IB1), A'length+B'length); + for j in 0 to 8 loop + O1_zd(A'length+B'length-1 downto 0) := O1_zd(A'length+B'length-2 downto 0) & '0'; + end loop; + O2_zd := INT_TO_SLV((IA * IB2), A'length+B'length); + O_zd := VECPLUS(O1_zd, O2_zd); + + sign := A(A'left) xor B(B'left); + if (sign = '1' ) then + O_zd := complement(O_zd); + end if; + end if; + end if; + end if; + P <= O_zd after 100 ps; + end process VITALBehaviour; + +end MULT18X18S_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/mult_and.vhd,v 1.5 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Fast Multiplier AND +-- /___/ /\ Filename : MULT_AND.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:03 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL MULT_AND ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity MULT_AND is + port( + LO : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic + ); + +end MULT_AND; + +architecture MULT_AND_V of MULT_AND is +begin + VITALBehavior : process (I1, I0) + begin + LO <= (I0 and I1) after 0 ps; + end process; +end MULT_AND_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxcy.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-to-1 Multiplexer for Carry Logic with General Output +-- /___/ /\ Filename : MUXCY.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:03 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +-- 08/23/07 - Handle S= X case. CR434611 +----- CELL MUXCY ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity MUXCY is + port( + O : out std_ulogic; + + CI : in std_ulogic; + DI : in std_ulogic; + S : in std_ulogic + ); +end MUXCY; + +architecture MUXCY_V of MUXCY is +begin + VITALBehavior : process (CI, DI, S) + begin + if (S = '0') then + O <= DI; + else + O <= CI; + end if; + end process; +end MUXCY_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxcy_d.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-to-1 Multiplexer for Carry Logic with Dual Output +-- /___/ /\ Filename : MUXCY_D.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:03 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +-- 08/23/07 - Handle S= X case. CR434611 +----- CELL MUXCY_D ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity MUXCY_D is + port( + LO : out std_ulogic; + O : out std_ulogic; + + CI : in std_ulogic; + DI : in std_ulogic; + S : in std_ulogic + ); +end MUXCY_D; + +architecture MUXCY_D_V of MUXCY_D is +begin + VITALBehavior : process (CI, DI, S) + begin + if (S = '0') then + O <= DI; + LO <= DI; + else + O <= CI; + LO <= CI; + end if; + end process; +end MUXCY_D_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxcy_l.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-to-1 Multiplexer for Carry Logic with Local Output +-- /___/ /\ Filename : MUXCY_L.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:03 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +-- 08/23/07 - Handle S= X case. CR434611 +----- CELL MUXCY_L ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity MUXCY_L is + port( + LO : out std_ulogic; + + CI : in std_ulogic; + DI : in std_ulogic; + S : in std_ulogic + ); +end MUXCY_L; + +architecture MUXCY_L_V of MUXCY_L is +begin + VITALBehavior : process (CI, DI, S) + begin + if (S = '0') then + LO <= DI; + else + LO <= CI; + end if; + end process; +end MUXCY_L_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf5.vhd,v 1.6 2007/08/23 23:28:36 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-to-1 Lookup Table Multiplexer with General Output +-- /___/ /\ Filename : MUXF5.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:03 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 02/10/07 - When input same, output same for any sel value. (CR433761). +-- 08/23/07 - Handle S= X case. CR434611 + +----- CELL MUXF5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity MUXF5 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end MUXF5; + +architecture MUXF5_V of MUXF5 is +begin + VITALBehavior : process (I0, I1, S) + begin + if ( S = '1') then + O <= I1; + else + O <= I0; + end if; + end process; +end MUXF5_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf5_d.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-to-1 Lookup Table Multiplexer with Dual Output +-- /___/ /\ Filename : MUXF5_D.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:03 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +-- 08/23/07 - Handle S= X case. CR434611 +----- CELL MUXF5_D ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity MUXF5_D is + port( + LO : out std_ulogic; + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end MUXF5_D; + +architecture MUXF5_D_V of MUXF5_D is +begin + VITALBehavior : process (I0, I1, S) + begin + if (S = '0') then + O <= I0; + LO <= I0; + else + O <= I1; + LO <= I1; + end if; + end process; +end MUXF5_D_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf5_l.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-to-1 Lookup Table Multiplexer with Local Output +-- /___/ /\ Filename : MUXF5_L.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:03 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +-- 08/23/07 - Handle S= X case. CR434611 +----- CELL MUXF5_L ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity MUXF5_L is + port( + LO : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end MUXF5_L; + +architecture MUXF5_L_V of MUXF5_L is +begin + VITALBehavior : process (I0, I1, S) + begin + if (S = '0') then + LO <= I0; + else + LO <= I1; + end if; + end process; +end MUXF5_L_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf6.vhd,v 1.6 2007/08/23 23:28:36 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-to-1 Lookup Table Multiplexer with General Output +-- /___/ /\ Filename : MUXF6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:04 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +-- 08/23/07 - Handle S= X case. CR434611 +----- CELL MUXF6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity MUXF6 is + + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end MUXF6; + +architecture MUXF6_V of MUXF6 is +begin + VITALBehavior : process (I0, I1, S) + begin + if (S = '0') then + O <= I0; + else + O <= I1; + end if; + end process; +end MUXF6_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf6_d.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-to-1 Lookup Table Multiplexer with Dual Output +-- /___/ /\ Filename : MUXF6_D.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:04 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +-- 08/23/07 - Handle S= X case. CR434611 +----- CELL MUXF6_D ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity MUXF6_D is + port( + LO : out std_ulogic; + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end MUXF6_D; + +architecture MUXF6_D_V of MUXF6_D is +begin + VITALBehavior : process (I0, I1, S) + begin + if (S = '0') then + O <= I0; + LO <= I0; + else + O <= I1; + LO <= I1; + end if; + end process; +end MUXF6_D_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf6_l.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-to-1 Lookup Table Multiplexer with Local Output +-- /___/ /\ Filename : MUXF6_L.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:04 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +-- 08/23/07 - Handle S= X case. CR434611 +----- CELL MUXF6_L ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity MUXF6_L is + port( + LO : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end MUXF6_L; + +architecture MUXF6_L_V of MUXF6_L is +begin + VITALBehavior : process (I0, I1, S) + begin + if (S = '0') then + LO <= I0; + else + LO <= I1; + end if; + end process; +end MUXF6_L_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf7.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-to-1 Lookup Table Multiplexer with General Output +-- /___/ /\ Filename : MUXF7.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:04 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +-- 08/23/07 - Handle S= X case. CR434611 +----- CELL MUXF7 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity MUXF7 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end MUXF7; + +architecture MUXF7_V of MUXF7 is +begin + VITALBehavior : process (I0, I1, S) + begin + if (S = '0') then + O <= I0; + else + O <= I1; + end if; + end process; +end MUXF7_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf7_d.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-to-1 Lookup Table Multiplexer with Dual Output +-- /___/ /\ Filename : MUXF7_D.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:04 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +-- 08/23/07 - Handle S= X case. CR434611 +----- CELL MUXF7_D ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity MUXF7_D is + port( + LO : out std_ulogic; + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end MUXF7_D; + +architecture MUXF7_D_V of MUXF7_D is +begin + VITALBehavior : process (I0, I1, S) + begin + if (S = '0') then + O <= I0; + LO <= I0; + else + O <= I1; + LO <= I1; + end if; + end process; +end MUXF7_D_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf7_l.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-to-1 Lookup Table Multiplexer with Local Output +-- /___/ /\ Filename : MUXF7_L.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:04 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +-- 08/23/07 - Handle S= X case. CR434611 +----- CELL MUXF7_L ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity MUXF7_L is + port( + LO : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end MUXF7_L; + +architecture MUXF7_L_V of MUXF7_L is +begin + VITALBehavior : process (I0, I1, S) + variable LO_zd : std_ulogic; + begin + if (S = '0') then + LO <= I0; + else + LO <= I1; + end if; + end process; +end MUXF7_L_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf8.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-to-1 Lookup Table Multiplexer with General Output +-- /___/ /\ Filename : MUXF8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:04 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +-- 08/23/07 - Handle S= X case. CR434611 +----- CELL MUXF8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity MUXF8 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end MUXF8; + +architecture MUXF8_V of MUXF8 is +begin + VITALBehavior : process (I0, I1, S) + begin + if (S = '0') then + O <= I0; + else + O <= I1; + end if; + end process; +end MUXF8_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf8_d.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-to-1 Lookup Table Multiplexer with Dual Output +-- /___/ /\ Filename : MUXF8_D.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:04 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +-- 08/23/07 - Handle S= X case. CR434611 +----- CELL MUXF8_D ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity MUXF8_D is + port( + LO : out std_ulogic; + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end MUXF8_D; + +architecture MUXF8_D_V of MUXF8_D is +begin + VITALBehavior : process (I0, I1, S) + begin + if (S = '0') then + O <= I0; + LO <= I0; + else + O <= I1; + LO <= I1; + end if; + end process; +end MUXF8_D_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/muxf8_l.vhd,v 1.5 2007/08/23 23:28:36 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-to-1 Lookup Table Multiplexer with Local Output +-- /___/ /\ Filename : MUXF8_L.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:04 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +-- 08/23/07 - Handle S= X case. CR434611 +----- CELL MUXF8_L ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity MUXF8_L is + port( + LO : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); +end MUXF8_L; + +architecture MUXF8_L_V of MUXF8_L is +begin + VITALBehavior : process (I0, I1, S) + begin + if (S = '0') then + LO <= I0; + else + LO <= I1; + end if; + end process; +end MUXF8_L_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-input NAND Gate +-- /___/ /\ Filename : NAND2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:05 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NAND2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NAND2 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end NAND2; + +architecture NAND2_V of NAND2 is +begin + O <= not (I0 and I1); +end NAND2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand2b1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-input NAND Gate +-- /___/ /\ Filename : NAND2B1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:05 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NAND2B1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NAND2B1 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end NAND2B1; + +architecture NAND2B1_V of NAND2B1 is +begin + O <= not ((not I0) and I1); +end NAND2B1_V; + + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand2b2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-input NAND Gate +-- /___/ /\ Filename : NAND2B2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:05 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NAND2B2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NAND2B2 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end NAND2B2; + +architecture NAND2B2_V of NAND2B2 is +begin + O <= not ((not I0) and (not I1)); +end NAND2B2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand3.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input NAND Gate +-- /___/ /\ Filename : NAND3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:05 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NAND3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NAND3 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end NAND3; + +architecture NAND3_V of NAND3 is +begin + O <= not (I0 and I1 and I2); +end NAND3_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand3b1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input NAND Gate +-- /___/ /\ Filename : NAND3B1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:05 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NAND3B1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NAND3B1 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end NAND3B1; + +architecture NAND3B1_V of NAND3B1 is +begin + O <= not ((not I0) and I1 and I2); +end NAND3B1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand3b2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input NAND Gate +-- /___/ /\ Filename : NAND3B2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:05 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NAND3B2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NAND3B2 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end NAND3B2; + +architecture NAND3B2_V of NAND3B2 is +begin + O <= not ((not I0) and (not I1) and I2); +end NAND3B2_V; + + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand3b3.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input NAND Gate +-- /___/ /\ Filename : NAND3B3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:05 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NAND3B3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NAND3B3 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end NAND3B3; + +architecture NAND3B3_V of NAND3B3 is +begin + O <= not ((not I0) and (not I1) and (not I2)); +end NAND3B3_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand4.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input NAND Gate +-- /___/ /\ Filename : NAND4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:05 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NAND4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NAND4 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end NAND4; + +architecture NAND4_V of NAND4 is +begin + O <= not (I0 and I1 and I2 and I3); +end NAND4_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand4b1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input NAND Gate +-- /___/ /\ Filename : NAND4B1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:05 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NAND4B1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NAND4B1 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end NAND4B1; + +architecture NAND4B1_V of NAND4B1 is +begin + O <= not ((not I0) and I1 and I2 and I3); +end NAND4B1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand4b2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input NAND Gate +-- /___/ /\ Filename : NAND4B2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:06 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NAND4B2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NAND4B2 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end NAND4B2; + +architecture NAND4B2_V of NAND4B2 is +begin + O <= not ((not I0) and (not I1) and I2 and I3); +end NAND4B2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand4b3.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input NAND Gate +-- /___/ /\ Filename : NAND4B3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:06 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NAND4B3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NAND4B3 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end NAND4B3; + +architecture NAND4B3_V of NAND4B3 is +begin + O <= not ((not I0) and (not I1) and (not I2) and I3); +end NAND4B3_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand4b4.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input NAND Gate +-- /___/ /\ Filename : NAND4B4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:06 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NAND4B4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NAND4B4 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end NAND4B4; + +architecture NAND4B4_V of NAND4B4 is +begin + O <= not ((not I0) and (not I1) and (not I2) and (not I3)); +end NAND4B4_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand5.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input NAND Gate +-- /___/ /\ Filename : NAND5.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:06 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NAND5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NAND5 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end NAND5; + +architecture NAND5_V of NAND5 is +begin + O <= not (I0 and I1 and I2 and I3 and I4); +end NAND5_V; + + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand5b1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input NAND Gate +-- /___/ /\ Filename : NAND5B1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:06 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NAND5B1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NAND5B1 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end NAND5B1; + +architecture NAND5B1_V of NAND5B1 is +begin + O <= not ((not I0) and I1 and I2 and I3 and I4); +end NAND5B1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand5b2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input NAND Gate +-- /___/ /\ Filename : NAND5B2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:06 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NAND5B2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NAND5B2 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end NAND5B2; + +architecture NAND5B2_V of NAND5B2 is +begin + O <= not ((not I0) and (not I1) and I2 and I3 and I4); +end NAND5B2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand5b3.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input NAND Gate +-- /___/ /\ Filename : NAND5B3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:06 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NAND5B3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NAND5B3 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end NAND5B3; + +architecture NAND5B3_V of NAND5B3 is +begin + O <= not ((not I0) and (not I1) and (not I2) and I3 and I4); +end NAND5B3_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand5b4.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input NAND Gate +-- /___/ /\ Filename : NAND5B4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:06 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NAND5B4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NAND5B4 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end NAND5B4; + +architecture NAND5B4_V of NAND5B4 is +begin + O <= not ((not I0) and (not I1) and (not I2) and (not I3) and I4); +end NAND5B4_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nand5b5.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input NAND Gate +-- /___/ /\ Filename : NAND5B5.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:07 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NAND5B5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NAND5B5 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end NAND5B5; + +architecture NAND5B5_V of NAND5B5 is +begin + O <= not ((not I0) and (not I1) and (not I2) and (not I3) and (not I4)); +end NAND5B5_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-input NOR Gate +-- /___/ /\ Filename : NOR2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:07 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NOR2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NOR2 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end NOR2; + +architecture NOR2_V of NOR2 is +begin + O <= (not (I0 or I1)); +end NOR2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor2b1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-input NOR Gate +-- /___/ /\ Filename : NOR2B1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:07 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NOR2B1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NOR2B1 is + port( + O : out STD_ULOGIC; + + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC + ); +end NOR2B1; + +architecture NOR2B1_V of NOR2B1 is +begin + O <= (NOT ((NOT I0) OR I1)); +end NOR2B1_V; + + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor2b2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-input NOR Gate +-- /___/ /\ Filename : NOR2B2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:07 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NOR2B2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NOR2B2 is + port( + O : out STD_ULOGIC; + + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC + ); +end NOR2B2; + +architecture NOR2B2_V of NOR2B2 is +begin + O <= (NOT ((NOT I0) OR (not I1))); +end NOR2B2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor3.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input NOR Gate +-- /___/ /\ Filename : NOR3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:07 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NOR3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NOR3 is + port( + O : out STD_ULOGIC; + + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC + ); +end NOR3; + +architecture NOR3_V of NOR3 is +begin + O <= (NOT (I0 OR I1 OR I2)); +end NOR3_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor3b1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input NOR Gate +-- /___/ /\ Filename : NOR3B1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:07 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NOR3B1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NOR3B1 is + port( + O : out STD_ULOGIC; + + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC + ); +end NOR3B1; + +architecture NOR3B1_V of NOR3B1 is +begin + O <= (NOT ((NOT I0) or I1 OR I2)); +end NOR3B1_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor3b2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input NOR Gate +-- /___/ /\ Filename : NOR3B2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:07 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NOR3B2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NOR3B2 is + port( + O : out STD_ULOGIC; + + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC + ); +end NOR3B2; + +architecture NOR3B2_V of NOR3B2 is +begin + O <= (NOT ((NOT I0) or (not I1) OR I2)); +end NOR3B2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor3b3.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input NOR Gate +-- /___/ /\ Filename : NOR3B3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:07 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NOR3B3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NOR3B3 is + port( + O : out STD_ULOGIC; + + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC + ); +end NOR3B3; + +architecture NOR3B3_V of NOR3B3 is +begin + O <= (NOT ((NOT I0) or (not I1) OR (not I2))); +end NOR3B3_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor4.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input NOR Gate +-- /___/ /\ Filename : NOR4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:07 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NOR4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NOR4 is + port( + O : out STD_ULOGIC; + + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC; + I3 : in STD_ULOGIC + ); +end NOR4; + +architecture NOR4_V of NOR4 is +begin + O <= (NOT (I0 or I1 OR I2 or I3)); +end NOR4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor4b1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input NOR Gate +-- /___/ /\ Filename : NOR4B1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NOR4B1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NOR4B1 is + port( + O : out STD_ULOGIC; + + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC; + I3 : in STD_ULOGIC + ); +end NOR4B1; + +architecture NOR4B1_V of NOR4B1 is +begin + O <= (NOT ((not I0) or I1 OR I2 or I3)); +end NOR4B1_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor4b2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input NOR Gate +-- /___/ /\ Filename : NOR4B2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NOR4B2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NOR4B2 is + port( + O : out STD_ULOGIC; + + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC; + I3 : in STD_ULOGIC + ); +end NOR4B2; + +architecture NOR4B2_V of NOR4B2 is +begin + O <= (NOT ((not I0) or (not I1) OR I2 or I3)); +end NOR4B2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor4b3.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input NOR Gate +-- /___/ /\ Filename : NOR4B3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NOR4B3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NOR4B3 is + port( + O : out STD_ULOGIC; + + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC; + I3 : in STD_ULOGIC + ); +end NOR4B3; + +architecture NOR4B3_V of NOR4B3 is +begin + O <= (NOT ((not I0) or (not I1) OR (not I2) or I3)); +end NOR4B3_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor4b4.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input NOR Gate +-- /___/ /\ Filename : NOR4B4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NOR4B4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NOR4B4 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end NOR4B4; + +architecture NOR4B4_V of NOR4B4 is +begin + O <= (not ((not I0) or (not I1) or (not I2) or (not I3))); +end NOR4B4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor5.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input NOR Gate +-- /___/ /\ Filename : NOR5.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NOR5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NOR5 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end NOR5; + +architecture NOR5_V of NOR5 is +begin + O <= (not (I0 or I1 or I2 or I3 or I4)); +end NOR5_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor5b1.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input NOR Gate +-- /___/ /\ Filename : NOR5B1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NOR5B1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NOR5B1 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end NOR5B1; + +architecture NOR5B1_V of NOR5B1 is +begin + O <= (not ((not I0) or I1 or I2 or I3 or I4)); +end NOR5B1_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor5b2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input NOR Gate +-- /___/ /\ Filename : NOR5B2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NOR5B2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NOR5B2 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end NOR5B2; + +architecture NOR5B2_V of NOR5B2 is +begin + O <= (not ((not I0) or (not I1) or I2 or I3 or I4)); +end NOR5B2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor5b3.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input NOR Gate +-- /___/ /\ Filename : NOR5B3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NOR5B3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NOR5B3 is + port( + O : out STD_ULOGIC; + + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC; + I3 : in STD_ULOGIC; + I4 : in STD_ULOGIC + ); +end NOR5B3; + +architecture NOR5B3_V of NOR5B3 is +begin + O <= (NOT ((not I0) or (not I1) OR (not I2) or I3 or I4)); +end NOR5B3_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor5b4.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input NOR Gate +-- /___/ /\ Filename : NOR5B4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:08 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NOR5B4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NOR5B4 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end NOR5B4; + +architecture NOR5B4_V of NOR5B4 is +begin + O <= (not ((not I0) or (not I1) or (not I2) or (not I3) or I4)); +end NOR5B4_V; + + + + + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/nor5b5.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input NOR Gate +-- /___/ /\ Filename : NOR5B5.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:09 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL NOR5B5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity NOR5B5 is + port( + O : out STD_ULOGIC; + + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC; + I3 : in STD_ULOGIC; + I4 : in STD_ULOGIC + ); +end NOR5B5; + +architecture NOR5B5_V of NOR5B5 is +begin + O <= (NOT ((not I0) or (not I1) OR (not I2) or (not I3) or (not I4))); +end NOR5B5_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf.vhd,v 1.5 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer +-- /___/ /\ Filename : OBUF.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:09 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF is + generic( + CAPACITANCE : string := "DONT_CARE"; + DRIVE : integer := 12; + IOSTANDARD : string := "DEFAULT"; + SLEW : string := "SLOW" + ); + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF; + +architecture OBUF_V of OBUF is +begin + prcs_init : process + variable FIRST_TIME : boolean := TRUE; + begin + + If(FIRST_TIME = true) then + if((CAPACITANCE = "LOW") or + (CAPACITANCE = "NORMAL") or + (CAPACITANCE = "DONT_CARE")) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The allowed values for CAPACITANCE are LOW, NORMAL or DONT_CARE" + severity Failure; + end if; + end if; + wait; + end process prcs_init; + + O <= TO_X01(I); +end OBUF_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_agp.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with AGP I/O Standard +-- /___/ /\ Filename : OBUF_AGP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:09 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_AGP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_AGP is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_AGP; + +architecture OBUF_AGP_V of OBUF_AGP is +begin + O <= TO_X01(I); +end OBUF_AGP_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_ctt.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with CTT I/O Standard +-- /___/ /\ Filename : OBUF_CTT.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:09 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_CTT ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_CTT is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_CTT; + +architecture OBUF_CTT_V of OBUF_CTT is +begin + O <= TO_X01(I); +end OBUF_CTT_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_f_12.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with Fast Slew 12 mA Drive +-- /___/ /\ Filename : OBUF_F_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:09 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_F_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_F_12 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_F_12; + +architecture OBUF_F_12_V of OBUF_F_12 is +begin + O <= TO_X01(I); +end OBUF_F_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_f_16.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with Fast Slew 16 mA Drive +-- /___/ /\ Filename : OBUF_F_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:09 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_F_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_F_16 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_F_16; + +architecture OBUF_F_16_V of OBUF_F_16 is +begin + O <= TO_X01(I); +end OBUF_F_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_f_2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with Fast Slew 2 mA Drive +-- /___/ /\ Filename : OBUF_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:09 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_F_2 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_F_2; + +architecture OBUF_F_2_V of OBUF_F_2 is +begin + O <= TO_X01(I); +end OBUF_F_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_f_24.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with Fast Slew 24 mA Drive +-- /___/ /\ Filename : OBUF_F_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:09 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_F_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_F_24 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_F_24; + +architecture OBUF_F_24_V of OBUF_F_24 is +begin + O <= TO_X01(I); +end OBUF_F_24_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_f_4.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with Fast Slew 4 mA Drive +-- /___/ /\ Filename : OBUF_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:09 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_F_4 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_F_4; + +architecture OBUF_F_4_V of OBUF_F_4 is +begin + O <= TO_X01(I); +end OBUF_F_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_f_6.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with Fast Slew 6 mA Drive +-- /___/ /\ Filename : OBUF_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:10 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_F_6 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_F_6; + +architecture OBUF_F_6_V of OBUF_F_6 is +begin + O <= TO_X01(I); +end OBUF_F_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_f_8.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with Fast Slew 8 mA Drive +-- /___/ /\ Filename : OBUF_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:10 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_F_8 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_F_8; + +architecture OBUF_F_8_V of OBUF_F_8 is +begin + O <= TO_X01(I); +end OBUF_F_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_gtl.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with GTL I/O Standard +-- /___/ /\ Filename : OBUF_GTL.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:10 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_GTL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_GTL is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_GTL; + +architecture OBUF_GTL_V of OBUF_GTL is +begin + O <= TO_X01(I); +end OBUF_GTL_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_gtl_dci.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with GTL_DCI I/O Standard +-- /___/ /\ Filename : OBUF_GTL_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:10 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_GTL_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_GTL_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_GTL_DCI; + +architecture OBUF_GTL_DCI_V of OBUF_GTL_DCI is +begin + O <= TO_X01(I); +end OBUF_GTL_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_gtlp.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with GTLP I/O Standard +-- /___/ /\ Filename : OBUF_GTLP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:10 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_GTLP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_GTLP is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_GTLP; + +architecture OBUF_GTLP_V of OBUF_GTLP is +begin + O <= TO_X01(I); +end OBUF_GTLP_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_gtlp_dci.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with GTLP_DCI I/O Standard +-- /___/ /\ Filename : OBUF_GTLP_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:10 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_GTLP_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_GTLP_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_GTLP_DCI; + +architecture OBUF_GTLP_DCI_V of OBUF_GTLP_DCI is +begin + O <= TO_X01(I); +end OBUF_GTLP_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_i.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with HSTL_I I/O Standard +-- /___/ /\ Filename : OBUF_HSTL_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:10 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_HSTL_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_HSTL_I is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_HSTL_I; + +architecture OBUF_HSTL_I_V of OBUF_HSTL_I is +begin + O <= TO_X01(I); +end OBUF_HSTL_I_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_i_18.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with HSTL_I_18 I/O Standard +-- /___/ /\ Filename : OBUF_HSTL_I_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:10 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_HSTL_I_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_HSTL_I_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_HSTL_I_18; + +architecture OBUF_HSTL_I_18_V of OBUF_HSTL_I_18 is +begin + O <= TO_X01(I); +end OBUF_HSTL_I_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_i_dci.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with HSTL_I_DCI I/O Standard +-- /___/ /\ Filename : OBUF_HSTL_I_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:10 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_HSTL_I_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_HSTL_I_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_HSTL_I_DCI; + +architecture OBUF_HSTL_I_DCI_V of OBUF_HSTL_I_DCI is +begin + O <= TO_X01(I); +end OBUF_HSTL_I_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_i_dci_18.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with HSTL_I_DCI_18 I/O Standard +-- /___/ /\ Filename : OBUF_HSTL_I_DCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:10 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_HSTL_I_DCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_HSTL_I_DCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_HSTL_I_DCI_18; + +architecture OBUF_HSTL_I_DCI_18_V of OBUF_HSTL_I_DCI_18 is +begin + O <= TO_X01(I); +end OBUF_HSTL_I_DCI_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_ii.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with HSTL_II I/O Standard +-- /___/ /\ Filename : OBUF_HSTL_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:11 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_HSTL_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_HSTL_II is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_HSTL_II; + +architecture OBUF_HSTL_II_V of OBUF_HSTL_II is +begin + O <= TO_X01(I); +end OBUF_HSTL_II_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_ii_18.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with HSTL_II_18 I/O Standard +-- /___/ /\ Filename : OBUF_HSTL_II_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:11 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_HSTL_II_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_HSTL_II_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_HSTL_II_18; + +architecture OBUF_HSTL_II_18_V of OBUF_HSTL_II_18 is +begin + O <= TO_X01(I); +end OBUF_HSTL_II_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_ii_dci.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with HSTL_II_DCI I/O Standard +-- /___/ /\ Filename : OBUF_HSTL_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:11 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_HSTL_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_HSTL_II_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_HSTL_II_DCI; + +architecture OBUF_HSTL_II_DCI_V of OBUF_HSTL_II_DCI is +begin + O <= TO_X01(I); +end OBUF_HSTL_II_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_ii_dci_18.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with HSTL_II_DCI_18 I/O Standard +-- /___/ /\ Filename : OBUF_HSTL_II_DCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:11 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_HSTL_II_DCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_HSTL_II_DCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_HSTL_II_DCI_18; + +architecture OBUF_HSTL_II_DCI_18_V of OBUF_HSTL_II_DCI_18 is +begin + O <= TO_X01(I); +end OBUF_HSTL_II_DCI_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_iii.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with HSTL_III I/O Standard +-- /___/ /\ Filename : OBUF_HSTL_III.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:11 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_HSTL_III ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_HSTL_III is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_HSTL_III; + +architecture OBUF_HSTL_III_V of OBUF_HSTL_III is +begin + O <= TO_X01(I); +end OBUF_HSTL_III_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_iii_18.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with HSTL_III_18 I/O Standard +-- /___/ /\ Filename : OBUF_HSTL_III_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:11 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_HSTL_III_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_HSTL_III_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_HSTL_III_18; + +architecture OBUF_HSTL_III_18_V of OBUF_HSTL_III_18 is +begin + O <= TO_X01(I); +end OBUF_HSTL_III_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_iii_dci.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with HSTL_III_DCI I/O Standard +-- /___/ /\ Filename : OBUF_HSTL_III_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:11 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_HSTL_III_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_HSTL_III_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_HSTL_III_DCI; + +architecture OBUF_HSTL_III_DCI_V of OBUF_HSTL_III_DCI is +begin + O <= TO_X01(I); +end OBUF_HSTL_III_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_iii_dci_18.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with HSTL_III_DCI_18 I/O Standard +-- /___/ /\ Filename : OBUF_HSTL_III_DCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:11 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_HSTL_III_DCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_HSTL_III_DCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_HSTL_III_DCI_18; + +architecture OBUF_HSTL_III_DCI_18_V of OBUF_HSTL_III_DCI_18 is +begin + O <= TO_X01(I); +end OBUF_HSTL_III_DCI_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_iv.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with HSTL_IV I/O Standard +-- /___/ /\ Filename : OBUF_HSTL_IV.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:11 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_HSTL_IV ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_HSTL_IV is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_HSTL_IV; + +architecture OBUF_HSTL_IV_V of OBUF_HSTL_IV is +begin + O <= TO_X01(I); +end OBUF_HSTL_IV_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_iv_18.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with HSTL_IV_18 I/O Standard +-- /___/ /\ Filename : OBUF_HSTL_IV_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:12 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_HSTL_IV_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_HSTL_IV_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_HSTL_IV_18; + +architecture OBUF_HSTL_IV_18_V of OBUF_HSTL_IV_18 is +begin + O <= TO_X01(I); +end OBUF_HSTL_IV_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_iv_dci.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with HSTL_IV_DCI I/O Standard +-- /___/ /\ Filename : OBUF_HSTL_IV_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:12 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_HSTL_IV_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_HSTL_IV_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_HSTL_IV_DCI; + +architecture OBUF_HSTL_IV_DCI_V of OBUF_HSTL_IV_DCI is +begin + O <= TO_X01(I); +end OBUF_HSTL_IV_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_hstl_iv_dci_18.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with HSTL_IV_DCI_18 I/O Standard +-- /___/ /\ Filename : OBUF_HSTL_IV_DCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:12 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_HSTL_IV_DCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_HSTL_IV_DCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_HSTL_IV_DCI_18; + +architecture OBUF_HSTL_IV_DCI_18_V of OBUF_HSTL_IV_DCI_18 is +begin + O <= TO_X01(I); +end OBUF_HSTL_IV_DCI_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos12.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS12 I/O Standard +-- /___/ /\ Filename : OBUF_LVCMOS12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:12 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS12 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS12; + +architecture OBUF_LVCMOS12_V of OBUF_LVCMOS12 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos12_f_2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS12 I/O Standard Fast Slew 2 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS12_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:12 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS12_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS12_F_2 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS12_F_2; + +architecture OBUF_LVCMOS12_F_2_V of OBUF_LVCMOS12_F_2 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS12_F_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos12_f_4.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS12 I/O Standard Fast Slew 4 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS12_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:12 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS12_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS12_F_4 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS12_F_4; + +architecture OBUF_LVCMOS12_F_4_V of OBUF_LVCMOS12_F_4 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS12_F_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos12_f_6.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS12 I/O Standard Fast Slew 6 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS12_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:12 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS12_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS12_F_6 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS12_F_6; + +architecture OBUF_LVCMOS12_F_6_V of OBUF_LVCMOS12_F_6 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS12_F_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos12_f_8.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS12 I/O Standard Fast Slew 8 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS12_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:12 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS12_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS12_F_8 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS12_F_8; + +architecture OBUF_LVCMOS12_F_8_V of OBUF_LVCMOS12_F_8 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS12_F_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos12_s_2.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS12 I/O Standard Slow Slew 2 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS12_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:12 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS12_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS12_S_2 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS12_S_2; + +architecture OBUF_LVCMOS12_S_2_V of OBUF_LVCMOS12_S_2 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS12_S_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos12_s_4.vhd,v 1.4 2004/04/08 18:46:26 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS12 I/O Standard Slow Slew 4 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS12_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:13 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS12_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS12_S_4 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS12_S_4; + +architecture OBUF_LVCMOS12_S_4_V of OBUF_LVCMOS12_S_4 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS12_S_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos12_s_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS12 I/O Standard Slow Slew 6 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS12_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:13 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS12_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS12_S_6 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS12_S_6; + +architecture OBUF_LVCMOS12_S_6_V of OBUF_LVCMOS12_S_6 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS12_S_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos12_s_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS12 I/O Standard Slow Slew 8 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS12_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:13 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS12_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS12_S_8 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS12_S_8; + +architecture OBUF_LVCMOS12_S_8_V of OBUF_LVCMOS12_S_8 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS12_S_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS15 I/O Standard +-- /___/ /\ Filename : OBUF_LVCMOS15.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:13 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS15 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS15 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS15; + +architecture OBUF_LVCMOS15_V of OBUF_LVCMOS15 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS15_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_f_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS15 I/O Standard Fast Slew 12 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS15_F_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:13 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS15_F_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS15_F_12 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS15_F_12; + +architecture OBUF_LVCMOS15_F_12_V of OBUF_LVCMOS15_F_12 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS15_F_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_f_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS15 I/O Standard Fast Slew 16 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS15_F_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:13 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS15_F_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS15_F_16 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS15_F_16; + +architecture OBUF_LVCMOS15_F_16_V of OBUF_LVCMOS15_F_16 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS15_F_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_f_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS15 I/O Standard Fast Slew 2 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS15_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:13 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS15_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS15_F_2 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS15_F_2; + +architecture OBUF_LVCMOS15_F_2_V of OBUF_LVCMOS15_F_2 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS15_F_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_f_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS15 I/O Standard Fast Slew 4 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS15_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:13 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS15_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS15_F_4 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS15_F_4; + +architecture OBUF_LVCMOS15_F_4_V of OBUF_LVCMOS15_F_4 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS15_F_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_f_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS15 I/O Standard Fast Slew 6 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS15_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:13 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS15_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS15_F_6 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS15_F_6; + +architecture OBUF_LVCMOS15_F_6_V of OBUF_LVCMOS15_F_6 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS15_F_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_f_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS15 I/O Standard Fast Slew 8 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS15_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:14 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS15_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS15_F_8 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS15_F_8; + +architecture OBUF_LVCMOS15_F_8_V of OBUF_LVCMOS15_F_8 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS15_F_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_s_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS15 I/O Standard Slow Slew 12 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS15_S_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:14 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS15_S_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS15_S_12 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS15_S_12; + +architecture OBUF_LVCMOS15_S_12_V of OBUF_LVCMOS15_S_12 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS15_S_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_s_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS15 I/O Standard Slow Slew 16 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS15_S_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:14 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS15_S_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS15_S_16 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS15_S_16; + +architecture OBUF_LVCMOS15_S_16_V of OBUF_LVCMOS15_S_16 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS15_S_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_s_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS15 I/O Standard Slow Slew 2 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS15_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:14 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS15_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS15_S_2 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS15_S_2; + +architecture OBUF_LVCMOS15_S_2_V of OBUF_LVCMOS15_S_2 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS15_S_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_s_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS15 I/O Standard Slow Slew 4 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS15_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:14 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS15_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS15_S_4 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS15_S_4; + +architecture OBUF_LVCMOS15_S_4_V of OBUF_LVCMOS15_S_4 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS15_S_4_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_s_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS15 I/O Standard Slow Slew 6 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS15_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:14 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS15_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS15_S_6 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS15_S_6; + +architecture OBUF_LVCMOS15_S_6_V of OBUF_LVCMOS15_S_6 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS15_S_6_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos15_s_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS15 I/O Standard Slow Slew 8 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS15_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:14 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS15_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS15_S_8 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS15_S_8; + +architecture OBUF_LVCMOS15_S_8_V of OBUF_LVCMOS15_S_8 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS15_S_8_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS18 I/O Standard +-- /___/ /\ Filename : OBUF_LVCMOS18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:14 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS18; + +architecture OBUF_LVCMOS18_V of OBUF_LVCMOS18 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS18_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_f_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS18 I/O Standard Fast Slew 12 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS18_F_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:14 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS18_F_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS18_F_12 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS18_F_12; + +architecture OBUF_LVCMOS18_F_12_V of OBUF_LVCMOS18_F_12 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS18_F_12_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_f_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS18 I/O Standard Fast Slew 16 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS18_F_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:15 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS18_F_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS18_F_16 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS18_F_16; + +architecture OBUF_LVCMOS18_F_16_V of OBUF_LVCMOS18_F_16 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS18_F_16_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_f_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS18 I/O Standard Fast Slew 2 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS18_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:15 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS18_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS18_F_2 is + port( + O : out STD_ULOGIC; + + I : in STD_ULOGIC + ); +end OBUF_LVCMOS18_F_2; + +architecture OBUF_LVCMOS18_F_2_V of OBUF_LVCMOS18_F_2 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS18_F_2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_f_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS18 I/O Standard Fast Slew 4 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS18_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:15 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS18_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS18_F_4 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS18_F_4; + +architecture OBUF_LVCMOS18_F_4_V of OBUF_LVCMOS18_F_4 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS18_F_4_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_f_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS18 I/O Standard Fast Slew 6 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS18_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:15 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS18_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS18_F_6 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS18_F_6; + +architecture OBUF_LVCMOS18_F_6_V of OBUF_LVCMOS18_F_6 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS18_F_6_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_f_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS18 I/O Standard Fast Slew 8 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS18_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:15 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS18_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS18_F_8 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS18_F_8; + +architecture OBUF_LVCMOS18_F_8_V of OBUF_LVCMOS18_F_8 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS18_F_8_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_s_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS18 I/O Standard Slow Slew 12 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS18_S_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:15 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS18_S_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS18_S_12 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS18_S_12; + +architecture OBUF_LVCMOS18_S_12_V of OBUF_LVCMOS18_S_12 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS18_S_12_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_s_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS18 I/O Standard Slow Slew 16 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS18_S_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:15 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS18_S_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS18_S_16 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS18_S_16; + +architecture OBUF_LVCMOS18_S_16_V of OBUF_LVCMOS18_S_16 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS18_S_16_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_s_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS18 I/O Standard Slow Slew 2 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS18_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:15 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS18_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS18_S_2 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS18_S_2; + +architecture OBUF_LVCMOS18_S_2_V of OBUF_LVCMOS18_S_2 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS18_S_2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_s_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS18 I/O Standard Slow Slew 4 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS18_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:16 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS18_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS18_S_4 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS18_S_4; + +architecture OBUF_LVCMOS18_S_4_V of OBUF_LVCMOS18_S_4 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS18_S_4_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_s_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS18 I/O Standard Slow Slew 6 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS18_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:16 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS18_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS18_S_6 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS18_S_6; + +architecture OBUF_LVCMOS18_S_6_V of OBUF_LVCMOS18_S_6 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS18_S_6_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos18_s_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS18 I/O Standard Slow Slew 8 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS18_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:16 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS18_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS18_S_8 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS18_S_8; + +architecture OBUF_LVCMOS18_S_8_V of OBUF_LVCMOS18_S_8 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS18_S_8_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS2 I/O Standard +-- /___/ /\ Filename : OBUF_LVCMOS2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:16 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS2 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS2; + +architecture OBUF_LVCMOS2_V of OBUF_LVCMOS2 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS25 I/O Standard +-- /___/ /\ Filename : OBUF_LVCMOS25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:16 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS25 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS25; + +architecture OBUF_LVCMOS25_V of OBUF_LVCMOS25 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_f_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS25 I/O Standard Fast Slew 12 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS25_F_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:16 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS25_F_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS25_F_12 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS25_F_12; + +architecture OBUF_LVCMOS25_F_12_V of OBUF_LVCMOS25_F_12 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS25_F_12_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_f_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS25 I/O Standard Fast Slew 16 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS25_F_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:16 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS25_F_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS25_F_16 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS25_F_16; + +architecture OBUF_LVCMOS25_F_16_V of OBUF_LVCMOS25_F_16 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS25_F_16_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_f_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS25 I/O Standard Fast Slew 2 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS25_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:16 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS25_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS25_F_2 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS25_F_2; + +architecture OBUF_LVCMOS25_F_2_V of OBUF_LVCMOS25_F_2 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS25_F_2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_f_24.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS25 I/O Standard Fast Slew 24 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS25_F_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:16 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS25_F_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS25_F_24 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS25_F_24; + +architecture OBUF_LVCMOS25_F_24_V of OBUF_LVCMOS25_F_24 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS25_F_24_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_f_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS25 I/O Standard Fast Slew 4 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS25_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:17 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS25_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS25_F_4 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS25_F_4; + +architecture OBUF_LVCMOS25_F_4_V of OBUF_LVCMOS25_F_4 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS25_F_4_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_f_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS25 I/O Standard Fast Slew 6 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS25_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:17 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS25_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS25_F_6 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS25_F_6; + +architecture OBUF_LVCMOS25_F_6_V of OBUF_LVCMOS25_F_6 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS25_F_6_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_f_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS25 I/O Standard Fast Slew 8 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS25_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:17 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS25_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS25_F_8 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS25_F_8; + +architecture OBUF_LVCMOS25_F_8_V of OBUF_LVCMOS25_F_8 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS25_F_8_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_s_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS25 I/O Standard Slow Slew 12 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS25_S_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:17 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS25_S_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS25_S_12 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS25_S_12; + +architecture OBUF_LVCMOS25_S_12_V of OBUF_LVCMOS25_S_12 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS25_S_12_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_s_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS25 I/O Standard Slow Slew 16 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS25_S_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:17 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS25_S_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS25_S_16 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS25_S_16; + +architecture OBUF_LVCMOS25_S_16_V of OBUF_LVCMOS25_S_16 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS25_S_16_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_s_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS25 I/O Standard Slow Slew 2 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS25_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:17 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS25_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS25_S_2 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS25_S_2; + +architecture OBUF_LVCMOS25_S_2_V of OBUF_LVCMOS25_S_2 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS25_S_2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_s_24.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS25 I/O Standard Slow Slew 24 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS25_S_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:17 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS25_S_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS25_S_24 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS25_S_24; + +architecture OBUF_LVCMOS25_S_24_V of OBUF_LVCMOS25_S_24 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS25_S_24_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_s_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS25 I/O Standard Slow Slew 4 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS25_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:17 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS25_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS25_S_4 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS25_S_4; + +architecture OBUF_LVCMOS25_S_4_V of OBUF_LVCMOS25_S_4 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS25_S_4_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_s_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS25 I/O Standard Slow Slew 6 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS25_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:17 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS25_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS25_S_6 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS25_S_6; + +architecture OBUF_LVCMOS25_S_6_V of OBUF_LVCMOS25_S_6 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS25_S_6_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos25_s_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS25 I/O Standard Slow Slew 8 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS25_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:18 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS25_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS25_S_8 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS25_S_8; + +architecture OBUF_LVCMOS25_S_8_V of OBUF_LVCMOS25_S_8 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS25_S_8_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS33 I/O Standard +-- /___/ /\ Filename : OBUF_LVCMOS33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:18 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS33 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS33; + +architecture OBUF_LVCMOS33_V of OBUF_LVCMOS33 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS33_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_f_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS33 I/O Standard Fast Slew 12 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS33_F_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:18 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS33_F_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS33_F_12 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS33_F_12; + +architecture OBUF_LVCMOS33_F_12_V of OBUF_LVCMOS33_F_12 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS33_F_12_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_f_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS33 I/O Standard Fast Slew 16 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS33_F_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:18 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS33_F_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS33_F_16 is + port( + O : out STD_ULOGIC; + + I : in STD_ULOGIC + ); +end OBUF_LVCMOS33_F_16; + +architecture OBUF_LVCMOS33_F_16_V of OBUF_LVCMOS33_F_16 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS33_F_16_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_f_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS33 I/O Standard Fast Slew 2 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS33_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:18 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS33_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS33_F_2 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS33_F_2; + +architecture OBUF_LVCMOS33_F_2_V of OBUF_LVCMOS33_F_2 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS33_F_2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_f_24.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS33 I/O Standard Fast Slew 24 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS33_F_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:18 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS33_F_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS33_F_24 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS33_F_24; + +architecture OBUF_LVCMOS33_F_24_V of OBUF_LVCMOS33_F_24 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS33_F_24_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_f_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS33 I/O Standard Fast Slew 4 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS33_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:18 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS33_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS33_F_4 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS33_F_4; + +architecture OBUF_LVCMOS33_F_4_V of OBUF_LVCMOS33_F_4 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS33_F_4_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_f_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS33 I/O Standard Fast Slew 6 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS33_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:18 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS33_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS33_F_6 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS33_F_6; + +architecture OBUF_LVCMOS33_F_6_V of OBUF_LVCMOS33_F_6 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS33_F_6_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_f_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS33 I/O Standard Fast Slew 8 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS33_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:18 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS33_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS33_F_8 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS33_F_8; + +architecture OBUF_LVCMOS33_F_8_V of OBUF_LVCMOS33_F_8 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS33_F_8_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_s_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS33 I/O Standard Slow Slew 12 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS33_S_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:19 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS33_S_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS33_S_12 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS33_S_12; + +architecture OBUF_LVCMOS33_S_12_V of OBUF_LVCMOS33_S_12 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS33_S_12_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_s_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS33 I/O Standard Slow Slew 16 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS33_S_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:19 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS33_S_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS33_S_16 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS33_S_16; + +architecture OBUF_LVCMOS33_S_16_V of OBUF_LVCMOS33_S_16 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS33_S_16_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_s_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS33 I/O Standard Slow Slew 2 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS33_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:19 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS33_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS33_S_2 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS33_S_2; + +architecture OBUF_LVCMOS33_S_2_V of OBUF_LVCMOS33_S_2 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS33_S_2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_s_24.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS33 I/O Standard Slow Slew 24 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS33_S_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:19 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS33_S_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS33_S_24 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS33_S_24; + +architecture OBUF_LVCMOS33_S_24_V of OBUF_LVCMOS33_S_24 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS33_S_24_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_s_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS33 I/O Standard Slow Slew 4 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS33_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:19 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS33_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS33_S_4 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS33_S_4; + +architecture OBUF_LVCMOS33_S_4_V of OBUF_LVCMOS33_S_4 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS33_S_4_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_s_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS33 I/O Standard Slow Slew 6 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS33_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:19 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS33_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS33_S_6 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS33_S_6; + +architecture OBUF_LVCMOS33_S_6_V of OBUF_LVCMOS33_S_6 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS33_S_6_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvcmos33_s_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVCMOS33 I/O Standard Slow Slew 8 mA Drive +-- /___/ /\ Filename : OBUF_LVCMOS33_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:19 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVCMOS33_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVCMOS33_S_8 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVCMOS33_S_8; + +architecture OBUF_LVCMOS33_S_8_V of OBUF_LVCMOS33_S_8 is +begin + O <= TO_X01(I); +end OBUF_LVCMOS33_S_8_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvdci_15.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVDCI_15 I/O Standard +-- /___/ /\ Filename : OBUF_LVDCI_15.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:19 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVDCI_15 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVDCI_15 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVDCI_15; + +architecture OBUF_LVDCI_15_V of OBUF_LVDCI_15 is +begin + O <= TO_X01(I); +end OBUF_LVDCI_15_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvdci_18.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVDCI_18 I/O Standard +-- /___/ /\ Filename : OBUF_LVDCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:19 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVDCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVDCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVDCI_18; + +architecture OBUF_LVDCI_18_V of OBUF_LVDCI_18 is +begin + O <= TO_X01(I); +end OBUF_LVDCI_18_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvdci_25.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVDCI_25 I/O Standard +-- /___/ /\ Filename : OBUF_LVDCI_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:20 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVDCI_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVDCI_25 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVDCI_25; + +architecture OBUF_LVDCI_25_V of OBUF_LVDCI_25 is +begin + O <= TO_X01(I); +end OBUF_LVDCI_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvdci_33.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVDCI_33 I/O Standard +-- /___/ /\ Filename : OBUF_LVDCI_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:20 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVDCI_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVDCI_33 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVDCI_33; + +architecture OBUF_LVDCI_33_V of OBUF_LVDCI_33 is +begin + O <= TO_X01(I); +end OBUF_LVDCI_33_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvdci_dv2_15.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVDCI_DV2_15 I/O Standard +-- /___/ /\ Filename : OBUF_LVDCI_DV2_15.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:20 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVDCI_DV2_15 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVDCI_DV2_15 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVDCI_DV2_15; + +architecture OBUF_LVDCI_DV2_15_V of OBUF_LVDCI_DV2_15 is +begin + O <= TO_X01(I); +end OBUF_LVDCI_DV2_15_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvdci_dv2_18.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVDCI_DV2_18 I/O Standard +-- /___/ /\ Filename : OBUF_LVDCI_DV2_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:20 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVDCI_DV2_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVDCI_DV2_18 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVDCI_DV2_18; + +architecture OBUF_LVDCI_DV2_18_V of OBUF_LVDCI_DV2_18 is +begin + O <= TO_X01(I); +end OBUF_LVDCI_DV2_18_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvdci_dv2_25.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVDCI_DV2_25 I/O Standard +-- /___/ /\ Filename : OBUF_LVDCI_DV2_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:20 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVDCI_DV2_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVDCI_DV2_25 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVDCI_DV2_25; + +architecture OBUF_LVDCI_DV2_25_V of OBUF_LVDCI_DV2_25 is +begin + O <= TO_X01(I); +end OBUF_LVDCI_DV2_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvdci_dv2_33.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVDCI_DV2_33 I/O Standard +-- /___/ /\ Filename : OBUF_LVDCI_DV2_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:20 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVDCI_DV2_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVDCI_DV2_33 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVDCI_DV2_33; + +architecture OBUF_LVDCI_DV2_33_V of OBUF_LVDCI_DV2_33 is +begin + O <= TO_X01(I); +end OBUF_LVDCI_DV2_33_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvds.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVDS I/O Standard +-- /___/ /\ Filename : OBUF_LVDS.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:20 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVDS ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVDS is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVDS; + +architecture OBUF_LVDS_V of OBUF_LVDS is +begin + O <= TO_X01(I); +end OBUF_LVDS_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvpecl.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVPECL I/O Standard +-- /___/ /\ Filename : OBUF_LVPECL.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:20 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVPECL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVPECL is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVPECL; + +architecture OBUF_LVPECL_V of OBUF_LVPECL is +begin + O <= TO_X01(I); +end OBUF_LVPECL_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVTTL I/O Standard +-- /___/ /\ Filename : OBUF_LVTTL.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:20 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVTTL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVTTL is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVTTL; + +architecture OBUF_LVTTL_V of OBUF_LVTTL is +begin + O <= TO_X01(I); +end OBUF_LVTTL_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_f_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVTTL I/O Standard Fast Slew 12 mA Drive +-- /___/ /\ Filename : OBUF_LVTTL_F_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:21 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVTTL_F_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVTTL_F_12 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVTTL_F_12; + +architecture OBUF_LVTTL_F_12_V of OBUF_LVTTL_F_12 is +begin + O <= TO_X01(I); +end OBUF_LVTTL_F_12_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_f_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVTTL I/O Standard Fast Slew 16 mA Drive +-- /___/ /\ Filename : OBUF_LVTTL_F_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:21 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVTTL_F_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVTTL_F_16 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVTTL_F_16; + +architecture OBUF_LVTTL_F_16_V of OBUF_LVTTL_F_16 is +begin + O <= TO_X01(I); +end OBUF_LVTTL_F_16_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_f_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVTTL I/O Standard Fast Slew 2 mA Drive +-- /___/ /\ Filename : OBUF_LVTTL_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:21 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVTTL_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVTTL_F_2 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVTTL_F_2; + +architecture OBUF_LVTTL_F_2_V of OBUF_LVTTL_F_2 is +begin + O <= TO_X01(I); +end OBUF_LVTTL_F_2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_f_24.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVTTL I/O Standard Fast Slew 24 mA Drive +-- /___/ /\ Filename : OBUF_LVTTL_F_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:21 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVTTL_F_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVTTL_F_24 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVTTL_F_24; + +architecture OBUF_LVTTL_F_24_V of OBUF_LVTTL_F_24 is +begin + O <= TO_X01(I); +end OBUF_LVTTL_F_24_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_f_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVTTL I/O Standard Fast Slew 4 mA Drive +-- /___/ /\ Filename : OBUF_LVTTL_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:21 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVTTL_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVTTL_F_4 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVTTL_F_4; + +architecture OBUF_LVTTL_F_4_V of OBUF_LVTTL_F_4 is +begin + O <= TO_X01(I); +end OBUF_LVTTL_F_4_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_f_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVTTL I/O Standard Fast Slew 6 mA Drive +-- /___/ /\ Filename : OBUF_LVTTL_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:21 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVTTL_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVTTL_F_6 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVTTL_F_6; + +architecture OBUF_LVTTL_F_6_V of OBUF_LVTTL_F_6 is +begin + O <= TO_X01(I); +end OBUF_LVTTL_F_6_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_f_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVTTL I/O Standard Fast Slew 8 mA Drive +-- /___/ /\ Filename : OBUF_LVTTL_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:21 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVTTL_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVTTL_F_8 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVTTL_F_8; + +architecture OBUF_LVTTL_F_8_V of OBUF_LVTTL_F_8 is +begin + O <= TO_X01(I); +end OBUF_LVTTL_F_8_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_s_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVTTL I/O Standard Slow Slew 12 mA Drive +-- /___/ /\ Filename : OBUF_LVTTL_S_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:21 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVTTL_S_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVTTL_S_12 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVTTL_S_12; + +architecture OBUF_LVTTL_S_12_V of OBUF_LVTTL_S_12 is +begin + O <= TO_X01(I); +end OBUF_LVTTL_S_12_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_s_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVTTL I/O Standard Slow Slew 16 mA Drive +-- /___/ /\ Filename : OBUF_LVTTL_S_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:21 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVTTL_S_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVTTL_S_16 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVTTL_S_16; + +architecture OBUF_LVTTL_S_16_V of OBUF_LVTTL_S_16 is +begin + O <= TO_X01(I); +end OBUF_LVTTL_S_16_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_s_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVTTL I/O Standard Slow Slew 2 mA Drive +-- /___/ /\ Filename : OBUF_LVTTL_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:22 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVTTL_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVTTL_S_2 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVTTL_S_2; + +architecture OBUF_LVTTL_S_2_V of OBUF_LVTTL_S_2 is +begin + O <= TO_X01(I); +end OBUF_LVTTL_S_2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_s_24.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVTTL I/O Standard Slow Slew 24 mA Drive +-- /___/ /\ Filename : OBUF_LVTTL_S_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:22 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVTTL_S_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVTTL_S_24 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVTTL_S_24; + +architecture OBUF_LVTTL_S_24_V of OBUF_LVTTL_S_24 is +begin + O <= TO_X01(I); +end OBUF_LVTTL_S_24_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_s_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVTTL I/O Standard Slow Slew 4 mA Drive +-- /___/ /\ Filename : OBUF_LVTTL_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:22 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVTTL_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVTTL_S_4 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVTTL_S_4; + +architecture OBUF_LVTTL_S_4_V of OBUF_LVTTL_S_4 is +begin + O <= TO_X01(I); +end OBUF_LVTTL_S_4_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_s_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVTTL I/O Standard Slow Slew 6 mA Drive +-- /___/ /\ Filename : OBUF_LVTTL_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:22 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVTTL_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVTTL_S_6 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVTTL_S_6; + +architecture OBUF_LVTTL_S_6_V of OBUF_LVTTL_S_6 is +begin + O <= TO_X01(I); +end OBUF_LVTTL_S_6_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_lvttl_s_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with LVTTL I/O Standard Slow Slew 8 mA Drive +-- /___/ /\ Filename : OBUF_LVTTL_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:22 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_LVTTL_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_LVTTL_S_8 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_LVTTL_S_8; + +architecture OBUF_LVTTL_S_8_V of OBUF_LVTTL_S_8 is +begin + O <= TO_X01(I); +end OBUF_LVTTL_S_8_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_pci33_3.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with PCI33_3 I/O Standard +-- /___/ /\ Filename : OBUF_PCI33_3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:22 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_PCI33_3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_PCI33_3 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_PCI33_3; + +architecture OBUF_PCI33_3_V of OBUF_PCI33_3 is +begin + O <= TO_X01(I); +end OBUF_PCI33_3_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_pci33_5.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with PCI33_5 I/O Standard +-- /___/ /\ Filename : OBUF_PCI33_5.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:22 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_PCI33_5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_PCI33_5 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_PCI33_5; + +architecture OBUF_PCI33_5_V of OBUF_PCI33_5 is +begin + O <= TO_X01(I); +end OBUF_PCI33_5_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_pci66_3.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with PCI66_3 I/O Standard +-- /___/ /\ Filename : OBUF_PCI66_3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:22 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_PCI66_3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_PCI66_3 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_PCI66_3; + +architecture OBUF_PCI66_3_V of OBUF_PCI66_3 is +begin + O <= TO_X01(I); +end OBUF_PCI66_3_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_pcix.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with PCIX I/O Standard +-- /___/ /\ Filename : OBUF_PCIX.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:22 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_PCIX ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_PCIX is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_PCIX; + +architecture OBUF_PCIX_V of OBUF_PCIX is +begin + O <= TO_X01(I); +end OBUF_PCIX_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_pcix66_3.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with PCIX66_3 I/O Standard +-- /___/ /\ Filename : OBUF_PCIX66_3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:22 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_PCIX66_3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_PCIX66_3 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_PCIX66_3; + +architecture OBUF_PCIX66_3_V of OBUF_PCIX66_3 is +begin + O <= TO_X01(I); +end OBUF_PCIX66_3_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_s_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with Slow Slew 12 mA Drive +-- /___/ /\ Filename : OBUF_S_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:23 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_S_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_S_12 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_S_12; + +architecture OBUF_S_12_V of OBUF_S_12 is +begin + O <= TO_X01(I); +end OBUF_S_12_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_s_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with Slow Slew 16 mA Drive +-- /___/ /\ Filename : OBUF_S_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:23 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_S_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_S_16 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_S_16; + +architecture OBUF_S_16_V of OBUF_S_16 is +begin + O <= TO_X01(I); +end OBUF_S_16_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_s_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with Slow Slew 2 mA Drive +-- /___/ /\ Filename : OBUF_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:23 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_S_2 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_S_2; + +architecture OBUF_S_2_V of OBUF_S_2 is +begin + O <= TO_X01(I); +end OBUF_S_2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_s_24.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with Slow Slew 24 mA Drive +-- /___/ /\ Filename : OBUF_S_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:23 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_S_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_S_24 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_S_24; + +architecture OBUF_S_24_V of OBUF_S_24 is +begin + O <= TO_X01(I); +end OBUF_S_24_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_s_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with Slow Slew 4 mA Drive +-- /___/ /\ Filename : OBUF_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:23 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_S_4 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_S_4; + +architecture OBUF_S_4_V of OBUF_S_4 is +begin + O <= TO_X01(I); +end OBUF_S_4_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_s_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with Slow Slew 6 mA Drive +-- /___/ /\ Filename : OBUF_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:23 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_S_6 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_S_6; + +architecture OBUF_S_6_V of OBUF_S_6 is +begin + O <= TO_X01(I); +end OBUF_S_6_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_s_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with Slow Slew 8 mA Drive +-- /___/ /\ Filename : OBUF_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:23 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_S_8 is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_S_8; + +architecture OBUF_S_8_V of OBUF_S_8 is +begin + O <= TO_X01(I); +end OBUF_S_8_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl18_i.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with SSTL18_I I/O Standard +-- /___/ /\ Filename : OBUF_SSTL18_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:23 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_SSTL18_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_SSTL18_I is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_SSTL18_I; + +architecture OBUF_SSTL18_I_V of OBUF_SSTL18_I is +begin + O <= TO_X01(I); +end OBUF_SSTL18_I_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl18_i_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with SSTL18_I_DCI I/O Standard +-- /___/ /\ Filename : OBUF_SSTL18_I_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:23 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_SSTL18_I_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_SSTL18_I_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_SSTL18_I_DCI; + +architecture OBUF_SSTL18_I_DCI_V of OBUF_SSTL18_I_DCI is +begin + O <= TO_X01(I); +end OBUF_SSTL18_I_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl18_ii.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with SSTL18_II I/O Standard +-- /___/ /\ Filename : OBUF_SSTL18_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:24 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_SSTL18_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_SSTL18_II is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_SSTL18_II; + +architecture OBUF_SSTL18_II_V of OBUF_SSTL18_II is +begin + O <= TO_X01(I); +end OBUF_SSTL18_II_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl18_ii_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with SSTL18_II_DCI I/O Standard +-- /___/ /\ Filename : OBUF_SSTL18_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:24 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_SSTL18_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_SSTL18_II_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_SSTL18_II_DCI; + +architecture OBUF_SSTL18_II_DCI_V of OBUF_SSTL18_II_DCI is +begin + O <= TO_X01(I); +end OBUF_SSTL18_II_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl2_i.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with SSTL2_I I/O Standard +-- /___/ /\ Filename : OBUF_SSTL2_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:24 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_SSTL2_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_SSTL2_I is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_SSTL2_I; + +architecture OBUF_SSTL2_I_V of OBUF_SSTL2_I is +begin + O <= TO_X01(I); +end OBUF_SSTL2_I_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl2_i_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with SSTL2_I_DCI I/O Standard +-- /___/ /\ Filename : OBUF_SSTL2_I_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:24 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_SSTL2_I_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_SSTL2_I_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_SSTL2_I_DCI; + +architecture OBUF_SSTL2_I_DCI_V of OBUF_SSTL2_I_DCI is +begin + O <= TO_X01(I); +end OBUF_SSTL2_I_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl2_ii.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with SSTL2_II I/O Standard +-- /___/ /\ Filename : OBUF_SSTL2_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:24 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_SSTL2_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_SSTL2_II is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_SSTL2_II; + +architecture OBUF_SSTL2_II_V of OBUF_SSTL2_II is +begin + O <= TO_X01(I); +end OBUF_SSTL2_II_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl2_ii_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with SSTL2_II_DCI I/O Standard +-- /___/ /\ Filename : OBUF_SSTL2_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:24 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_SSTL2_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_SSTL2_II_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_SSTL2_II_DCI; + +architecture OBUF_SSTL2_II_DCI_V of OBUF_SSTL2_II_DCI is +begin + O <= TO_X01(I); +end OBUF_SSTL2_II_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl3_i.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with SSTL3_I I/O Standard +-- /___/ /\ Filename : OBUF_SSTL3_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:24 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_SSTL3_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_SSTL3_I is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_SSTL3_I; + +architecture OBUF_SSTL3_I_V of OBUF_SSTL3_I is +begin + O <= TO_X01(I); +end OBUF_SSTL3_I_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl3_i_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with SSTL3_I_DCI I/O Standard +-- /___/ /\ Filename : OBUF_SSTL3_I_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:24 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_SSTL3_I_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_SSTL3_I_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_SSTL3_I_DCI; + +architecture OBUF_SSTL3_I_DCI_V of OBUF_SSTL3_I_DCI is +begin + O <= TO_X01(I); +end OBUF_SSTL3_I_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl3_ii.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with SSTL3_II I/O Standard +-- /___/ /\ Filename : OBUF_SSTL3_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:24 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_SSTL3_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_SSTL3_II is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_SSTL3_II; + +architecture OBUF_SSTL3_II_V of OBUF_SSTL3_II is +begin + O <= TO_X01(I); +end OBUF_SSTL3_II_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuf_sstl3_ii_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Output Buffer with SSTL3_II_DCI I/O Standard +-- /___/ /\ Filename : OBUF_SSTL3_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:25 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUF_SSTL3_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUF_SSTL3_II_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end OBUF_SSTL3_II_DCI; + +architecture OBUF_SSTL3_II_DCI_V of OBUF_SSTL3_II_DCI is +begin + O <= TO_X01(I); +end OBUF_SSTL3_II_DCI_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds.vhd,v 1.6 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Output Buffer +-- /___/ /\ Filename : OBUFDS.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:25 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFDS ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFDS is + generic( + CAPACITANCE : string := "DONT_CARE"; + IOSTANDARD : string := "DEFAULT" + ); + + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic + ); +end OBUFDS; + +architecture OBUFDS_V of OBUFDS is +begin + VitalBehavior : process (I) + variable O_zd : std_logic; + variable OB_zd : std_logic; + begin + O_zd := TO_X01(I); + OB_zd := (not O_zd); + O <= O_zd; + OB <= OB_zd; + end process; +end OBUFDS_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds_blvds_25.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Output Buffer with BLVDS_25 I/O Standard +-- /___/ /\ Filename : OBUFDS_BLVDS_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:25 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFDS_BLVDS_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFDS_BLVDS_25 is + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic + ); +end OBUFDS_BLVDS_25; + +architecture OBUFDS_BLVDS_25_V of OBUFDS_BLVDS_25 is +begin + VITALBehavior : process (I) + variable O_zd : std_ulogic; + variable OB_zd : std_ulogic; + + begin + O_zd := TO_X01(I); + OB_zd := (not O_zd); + O <= O_zd; + OB <= OB_zd; + end process; +end OBUFDS_BLVDS_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds_ldt_25.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Output Buffer with LDT_25 I/O Standard +-- /___/ /\ Filename : OBUFDS_LDT_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:25 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFDS_LDT_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFDS_LDT_25 is + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic + ); +end OBUFDS_LDT_25; + +architecture OBUFDS_LDT_25_V of OBUFDS_LDT_25 is +begin + VITALBehavior : process (I) + variable O_zd : std_ulogic; + variable OB_zd : std_ulogic; + + begin + O_zd := TO_X01(I); + OB_zd := (not O_zd); + O <= O_zd; + OB <= OB_zd; + end process; +end OBUFDS_LDT_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds_lvds_25.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Output Buffer with LVDS_25 I/O Standard +-- /___/ /\ Filename : OBUFDS_LVDS_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:25 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFDS_LVDS_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFDS_LVDS_25 is + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic + ); +end OBUFDS_LVDS_25; + +architecture OBUFDS_LVDS_25_V of OBUFDS_LVDS_25 is +begin + VITALBehavior : process (I) + variable O_zd : std_ulogic; + variable OB_zd : std_ulogic; + + begin + O_zd := TO_X01(I); + OB_zd := (not O_zd); + O <= O_zd; + OB <= OB_zd; + end process; +end OBUFDS_LVDS_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds_lvds_33.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Output Buffer with LVDS_33 I/O Standard +-- /___/ /\ Filename : OBUFDS_LVDS_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:25 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFDS_LVDS_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFDS_LVDS_33 is + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic + ); +end OBUFDS_LVDS_33; + +architecture OBUFDS_LVDS_33_V of OBUFDS_LVDS_33 is +begin + VITALBehavior : process (I) + variable O_zd : std_ulogic; + variable OB_zd : std_ulogic; + + begin + O_zd := TO_X01(I); + OB_zd := (not O_zd); + O <= O_zd; + OB <= OB_zd; + end process; +end OBUFDS_LVDS_33_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds_lvdsext_25.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Output Buffer with LVDSEXT_25 I/O Standard +-- /___/ /\ Filename : OBUFDS_LVDSEXT_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:25 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFDS_LVDSEXT_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFDS_LVDSEXT_25 is + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic + ); +end OBUFDS_LVDSEXT_25; + +architecture OBUFDS_LVDSEXT_25_V of OBUFDS_LVDSEXT_25 is +begin + VITALBehavior : process (I) + variable O_zd : std_ulogic; + variable OB_zd : std_ulogic; + + begin + O_zd := TO_X01(I); + OB_zd := (not O_zd); + O <= O_zd; + OB <= OB_zd; + end process; +end OBUFDS_LVDSEXT_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds_lvdsext_33.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Output Buffer with LVDSEXT_33 I/O Standard +-- /___/ /\ Filename : OBUFDS_LVDSEXT_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:25 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFDS_LVDSEXT_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFDS_LVDSEXT_33 is + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic + ); +end OBUFDS_LVDSEXT_33; + +architecture OBUFDS_LVDSEXT_33_V of OBUFDS_LVDSEXT_33 is +begin + VITALBehavior : process (I) + variable O_zd : std_ulogic; + variable OB_zd : std_ulogic; + + begin + O_zd := TO_X01(I); + OB_zd := (not O_zd); + O <= O_zd; + OB <= OB_zd; + end process; +end OBUFDS_LVDSEXT_33_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds_lvpecl_25.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Output Buffer with LVPECL_25 I/O Standard +-- /___/ /\ Filename : OBUFDS_LVPECL_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:25 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFDS_LVPECL_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFDS_LVPECL_25 is + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic + ); +end OBUFDS_LVPECL_25; + +architecture OBUFDS_LVPECL_25_V of OBUFDS_LVPECL_25 is +begin + VITALBehavior : process (I) + variable O_zd : std_ulogic; + variable OB_zd : std_ulogic; + + begin + O_zd := TO_X01(I); + OB_zd := (not O_zd); + O <= O_zd; + OB <= OB_zd; + end process; +end OBUFDS_LVPECL_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds_lvpecl_33.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Output Buffer with LVPECL_33 I/O Standard +-- /___/ /\ Filename : OBUFDS_LVPECL_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:26 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFDS_LVPECL_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFDS_LVPECL_33 is + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic + ); +end OBUFDS_LVPECL_33; + +architecture OBUFDS_LVPECL_33_V of OBUFDS_LVPECL_33 is +begin + VITALBehavior : process (I) + variable O_zd : std_ulogic; + variable OB_zd : std_ulogic; + + begin + O_zd := TO_X01(I); + OB_zd := (not O_zd); + O <= O_zd; + OB <= OB_zd; + end process; +end OBUFDS_LVPECL_33_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obufds_ulvds_25.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Differential Signaling Output Buffer with ULVDS_25 I/O Standard +-- /___/ /\ Filename : OBUFDS_ULVDS_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:26 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFDS_ULVDS_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFDS_ULVDS_25 is + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic + ); +end OBUFDS_ULVDS_25; + +architecture OBUFDS_ULVDS_25_V of OBUFDS_ULVDS_25 is +begin + VITALBehavior : process (I) + variable O_zd : std_ulogic; + variable OB_zd : std_ulogic; + + begin + O_zd := TO_X01(I); + OB_zd := (not O_zd); + O <= O_zd; + OB <= OB_zd; + end process; +end OBUFDS_ULVDS_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft.vhd,v 1.5 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer +-- /___/ /\ Filename : OBUFT.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:26 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT is + generic( + CAPACITANCE : string := "DONT_CARE"; + DRIVE : integer := 12; + IOSTANDARD : string := "DEFAULT"; + SLEW : string := "SLOW" + ); + + port( + O : out std_ulogic; + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT; + +architecture OBUFT_V of OBUFT is +begin + prcs_init : process + variable FIRST_TIME : boolean := TRUE; + begin + + If(FIRST_TIME = true) then + if((CAPACITANCE = "LOW") or + (CAPACITANCE = "NORMAL") or + (CAPACITANCE = "DONT_CARE")) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The allowed values for CAPACITANCE are LOW, NORMAL or DONT_CARE" + severity Failure; + end if; + end if; + wait; + end process prcs_init; + + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_agp.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with AGP I/O Standard +-- /___/ /\ Filename : OBUFT_AGP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:26 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_AGP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_AGP is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_AGP; + +architecture OBUFT_AGP_V of OBUFT_AGP is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_AGP_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_ctt.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with CTT I/O Standard +-- /___/ /\ Filename : OBUFT_CTT.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:26 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_CTT ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_CTT is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_CTT; + +architecture OBUFT_CTT_V of OBUFT_CTT is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_CTT_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_f_12.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with Fast Slew 12 mA Drive +-- /___/ /\ Filename : OBUFT_F_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:26 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_F_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_F_12 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_F_12; + +architecture OBUFT_F_12_V of OBUFT_F_12 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_F_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_f_16.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with Fast Slew 16 mA Drive +-- /___/ /\ Filename : OBUFT_F_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:26 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_F_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_F_16 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_F_16; + +architecture OBUFT_F_16_V of OBUFT_F_16 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_F_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_f_2.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with Fast Slew 2 mA Drive +-- /___/ /\ Filename : OBUFT_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:27 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_F_2 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_F_2; + +architecture OBUFT_F_2_V of OBUFT_F_2 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_F_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_f_24.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with Fast Slew 24 mA Drive +-- /___/ /\ Filename : OBUFT_F_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:27 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_F_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_F_24 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_F_24; + +architecture OBUFT_F_24_V of OBUFT_F_24 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_F_24_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_f_4.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with Fast Slew 4 mA Drive +-- /___/ /\ Filename : OBUFT_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:27 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_F_4 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_F_4; + +architecture OBUFT_F_4_V of OBUFT_F_4 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_F_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_f_6.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with Fast Slew 6 mA Drive +-- /___/ /\ Filename : OBUFT_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:27 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_F_6 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_F_6; + +architecture OBUFT_F_6_V of OBUFT_F_6 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_F_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_f_8.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with Fast Slew 8 mA Drive +-- /___/ /\ Filename : OBUFT_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:27 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_F_8 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_F_8; + +architecture OBUFT_F_8_V of OBUFT_F_8 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_F_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_gtl.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with GTL I/O Standard +-- /___/ /\ Filename : OBUFT_GTL.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:27 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_GTL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_GTL is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_GTL; + +architecture OBUFT_GTL_V of OBUFT_GTL is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_GTL_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_gtl_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with GTL_DCI I/O Standard +-- /___/ /\ Filename : OBUFT_GTL_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:27 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_GTL_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_GTL_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_GTL_DCI; + +architecture OBUFT_GTL_DCI_V of OBUFT_GTL_DCI is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_GTL_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_gtlp.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with GTLP I/O Standard +-- /___/ /\ Filename : OBUFT_GTLP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:27 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_GTLP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_GTLP is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_GTLP; + +architecture OBUFT_GTLP_V of OBUFT_GTLP is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_GTLP_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_gtlp_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with GTLP_DCI I/O Standard +-- /___/ /\ Filename : OBUFT_GTLP_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:27 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_GTLP_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_GTLP_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_GTLP_DCI; + +architecture OBUFT_GTLP_DCI_V of OBUFT_GTLP_DCI is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_GTLP_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_i.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with HSTL_I I/O Standard +-- /___/ /\ Filename : OBUFT_HSTL_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:28 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_HSTL_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_HSTL_I is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_HSTL_I; + +architecture OBUFT_HSTL_I_V of OBUFT_HSTL_I is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_HSTL_I_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_i_18.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with HSTL_I_18 I/O Standard +-- /___/ /\ Filename : OBUFT_HSTL_I_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:28 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_HSTL_I_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_HSTL_I_18 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_HSTL_I_18; + +architecture OBUFT_HSTL_I_18_V of OBUFT_HSTL_I_18 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_HSTL_I_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_i_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with HSTL_I_DCI I/O Standard +-- /___/ /\ Filename : OBUFT_HSTL_I_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:28 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_HSTL_I_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_HSTL_I_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_HSTL_I_DCI; + +architecture OBUFT_HSTL_I_DCI_V of OBUFT_HSTL_I_DCI is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_HSTL_I_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_i_dci_18.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with HSTL_I_DCI_18 I/O Standard +-- /___/ /\ Filename : OBUFT_HSTL_I_DCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:28 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_HSTL_I_DCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_HSTL_I_DCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_HSTL_I_DCI_18; + +architecture OBUFT_HSTL_I_DCI_18_V of OBUFT_HSTL_I_DCI_18 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_HSTL_I_DCI_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_ii.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with HSTL_II I/O Standard +-- /___/ /\ Filename : OBUFT_HSTL_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:28 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_HSTL_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_HSTL_II is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_HSTL_II; + +architecture OBUFT_HSTL_II_V of OBUFT_HSTL_II is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_HSTL_II_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_ii_18.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with HSTL_II_18 I/O Standard +-- /___/ /\ Filename : OBUFT_HSTL_II_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:28 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_HSTL_II_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_HSTL_II_18 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_HSTL_II_18; + +architecture OBUFT_HSTL_II_18_V of OBUFT_HSTL_II_18 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_HSTL_II_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_ii_dci.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with HSTL_II_DCI I/O Standard +-- /___/ /\ Filename : OBUFT_HSTL_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:28 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_HSTL_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_HSTL_II_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_HSTL_II_DCI; + +architecture OBUFT_HSTL_II_DCI_V of OBUFT_HSTL_II_DCI is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_HSTL_II_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_ii_dci_18.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with HSTL_II_DCI_18 I/O Standard +-- /___/ /\ Filename : OBUFT_HSTL_II_DCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:28 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_HSTL_II_DCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_HSTL_II_DCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_HSTL_II_DCI_18; + +architecture OBUFT_HSTL_II_DCI_18_V of OBUFT_HSTL_II_DCI_18 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_HSTL_II_DCI_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_iii.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with HSTL_III I/O Standard +-- /___/ /\ Filename : OBUFT_HSTL_III.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:28 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_HSTL_III ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_HSTL_III is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_HSTL_III; + +architecture OBUFT_HSTL_III_V of OBUFT_HSTL_III is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_HSTL_III_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_iii_18.vhd,v 1.4 2004/04/08 18:46:27 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with HSTL_III_18 I/O Standard +-- /___/ /\ Filename : OBUFT_HSTL_III_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:29 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_HSTL_III_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_HSTL_III_18 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_HSTL_III_18; + +architecture OBUFT_HSTL_III_18_V of OBUFT_HSTL_III_18 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_HSTL_III_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_iii_dci.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with HSTL_III_DCI I/O Standard +-- /___/ /\ Filename : OBUFT_HSTL_III_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:29 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_HSTL_III_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_HSTL_III_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_HSTL_III_DCI; + +architecture OBUFT_HSTL_III_DCI_V of OBUFT_HSTL_III_DCI is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_HSTL_III_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_iii_dci_18.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with HSTL_III_DCI_18 I/O Standard +-- /___/ /\ Filename : OBUFT_HSTL_III_DCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:29 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_HSTL_III_DCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_HSTL_III_DCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_HSTL_III_DCI_18; + +architecture OBUFT_HSTL_III_DCI_18_V of OBUFT_HSTL_III_DCI_18 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_HSTL_III_DCI_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_iv.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with HSTL_IV I/O Standard +-- /___/ /\ Filename : OBUFT_HSTL_IV.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:29 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_HSTL_IV ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_HSTL_IV is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_HSTL_IV; + +architecture OBUFT_HSTL_IV_V of OBUFT_HSTL_IV is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_HSTL_IV_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_iv_18.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with HSTL_IV_18 I/O Standard +-- /___/ /\ Filename : OBUFT_HSTL_IV_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:29 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_HSTL_IV_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_HSTL_IV_18 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_HSTL_IV_18; + +architecture OBUFT_HSTL_IV_18_V of OBUFT_HSTL_IV_18 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_HSTL_IV_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_iv_dci.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with HSTL_IV_DCI I/O Standard +-- /___/ /\ Filename : OBUFT_HSTL_IV_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:29 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_HSTL_IV_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_HSTL_IV_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_HSTL_IV_DCI; + +architecture OBUFT_HSTL_IV_DCI_V of OBUFT_HSTL_IV_DCI is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_HSTL_IV_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_hstl_iv_dci_18.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with HSTL_IV_DCI_18 I/O Standard +-- /___/ /\ Filename : OBUFT_HSTL_IV_DCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:29 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_HSTL_IV_DCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_HSTL_IV_DCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_HSTL_IV_DCI_18; + +architecture OBUFT_HSTL_IV_DCI_18_V of OBUFT_HSTL_IV_DCI_18 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_HSTL_IV_DCI_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS12 I/O Standard +-- /___/ /\ Filename : OBUFT_LVCMOS12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:29 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS12 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS12; + +architecture OBUFT_LVCMOS12_V of OBUFT_LVCMOS12 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos12_f_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS12 I/O Standard Fast Slew 2 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS12_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:29 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS12_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS12_F_2 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS12_F_2; + +architecture OBUFT_LVCMOS12_F_2_V of OBUFT_LVCMOS12_F_2 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS12_F_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos12_f_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS12 I/O Standard Fast Slew 4 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS12_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:30 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS12_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS12_F_4 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS12_F_4; + +architecture OBUFT_LVCMOS12_F_4_V of OBUFT_LVCMOS12_F_4 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS12_F_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos12_f_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS12 I/O Standard Fast Slew 6 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS12_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:30 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS12_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS12_F_6 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS12_F_6; + +architecture OBUFT_LVCMOS12_F_6_V of OBUFT_LVCMOS12_F_6 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS12_F_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos12_f_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS12 I/O Standard Fast Slew 8 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS12_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:30 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS12_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS12_F_8 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS12_F_8; + +architecture OBUFT_LVCMOS12_F_8_V of OBUFT_LVCMOS12_F_8 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS12_F_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos12_s_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS12 I/O Standard Slow Slew 2 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS12_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:30 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS12_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS12_S_2 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS12_S_2; + +architecture OBUFT_LVCMOS12_S_2_V of OBUFT_LVCMOS12_S_2 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS12_S_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos12_s_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS12 I/O Standard Slow Slew 4 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS12_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:30 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS12_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS12_S_4 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS12_S_4; + +architecture OBUFT_LVCMOS12_S_4_V of OBUFT_LVCMOS12_S_4 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS12_S_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos12_s_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS12 I/O Standard Slow Slew 6 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS12_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:30 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS12_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS12_S_6 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS12_S_6; + +architecture OBUFT_LVCMOS12_S_6_V of OBUFT_LVCMOS12_S_6 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS12_S_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos12_s_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS12 I/O Standard Slow Slew 8 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS12_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:30 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS12_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS12_S_8 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS12_S_8; + +architecture OBUFT_LVCMOS12_S_8_V of OBUFT_LVCMOS12_S_8 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS12_S_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS15 I/O Standard +-- /___/ /\ Filename : OBUFT_LVCMOS15.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:30 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS15 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS15 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS15; + +architecture OBUFT_LVCMOS15_V of OBUFT_LVCMOS15 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS15_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_f_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS15 I/O Standard Fast Slew 12 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS15_F_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:30 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS15_F_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS15_F_12 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS15_F_12; + +architecture OBUFT_LVCMOS15_F_12_V of OBUFT_LVCMOS15_F_12 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS15_F_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_f_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS15 I/O Standard Fast Slew 16 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS15_F_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:31 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS15_F_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS15_F_16 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS15_F_16; + +architecture OBUFT_LVCMOS15_F_16_V of OBUFT_LVCMOS15_F_16 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS15_F_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_f_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS15 I/O Standard Fast Slew 2 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS15_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:31 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS15_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS15_F_2 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS15_F_2; + +architecture OBUFT_LVCMOS15_F_2_V of OBUFT_LVCMOS15_F_2 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS15_F_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_f_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS15 I/O Standard Fast Slew 4 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS15_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:31 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS15_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS15_F_4 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS15_F_4; + +architecture OBUFT_LVCMOS15_F_4_V of OBUFT_LVCMOS15_F_4 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS15_F_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_f_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS15 I/O Standard Fast Slew 6 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS15_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:31 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS15_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS15_F_6 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS15_F_6; + +architecture OBUFT_LVCMOS15_F_6_V of OBUFT_LVCMOS15_F_6 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS15_F_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_f_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS15 I/O Standard Fast Slew 8 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS15_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:31 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS15_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS15_F_8 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS15_F_8; + +architecture OBUFT_LVCMOS15_F_8_V of OBUFT_LVCMOS15_F_8 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS15_F_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_s_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS15 I/O Standard Slow Slew 12 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS15_S_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:31 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS15_S_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS15_S_12 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS15_S_12; + +architecture OBUFT_LVCMOS15_S_12_V of OBUFT_LVCMOS15_S_12 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS15_S_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_s_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS15 I/O Standard Slow Slew 16 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS15_S_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:31 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS15_S_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS15_S_16 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS15_S_16; + +architecture OBUFT_LVCMOS15_S_16_V of OBUFT_LVCMOS15_S_16 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS15_S_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_s_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS15 I/O Standard Slow Slew 2 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS15_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:31 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS15_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS15_S_2 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS15_S_2; + +architecture OBUFT_LVCMOS15_S_2_V of OBUFT_LVCMOS15_S_2 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS15_S_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_s_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS15 I/O Standard Slow Slew 4 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS15_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:31 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS15_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS15_S_4 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS15_S_4; + +architecture OBUFT_LVCMOS15_S_4_V of OBUFT_LVCMOS15_S_4 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS15_S_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_s_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS15 I/O Standard Slow Slew 6 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS15_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:32 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS15_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS15_S_6 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS15_S_6; + +architecture OBUFT_LVCMOS15_S_6_V of OBUFT_LVCMOS15_S_6 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS15_S_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos15_s_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS15 I/O Standard Slow Slew 8 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS15_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:32 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS15_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS15_S_8 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS15_S_8; + +architecture OBUFT_LVCMOS15_S_8_V of OBUFT_LVCMOS15_S_8 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS15_S_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS18 I/O Standard +-- /___/ /\ Filename : OBUFT_LVCMOS18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:32 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS18 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS18; + +architecture OBUFT_LVCMOS18_V of OBUFT_LVCMOS18 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_f_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS18 I/O Standard Fast Slew 12 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS18_F_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:32 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS18_F_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS18_F_12 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS18_F_12; + +architecture OBUFT_LVCMOS18_F_12_V of OBUFT_LVCMOS18_F_12 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS18_F_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_f_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS18 I/O Standard Fast Slew 16 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS18_F_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:32 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS18_F_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS18_F_16 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS18_F_16; + +architecture OBUFT_LVCMOS18_F_16_V of OBUFT_LVCMOS18_F_16 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS18_F_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_f_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS18 I/O Standard Fast Slew 2 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS18_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:32 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS18_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS18_F_2 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS18_F_2; + +architecture OBUFT_LVCMOS18_F_2_V of OBUFT_LVCMOS18_F_2 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS18_F_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_f_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS18 I/O Standard Fast Slew 4 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS18_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:32 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS18_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS18_F_4 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS18_F_4; + +architecture OBUFT_LVCMOS18_F_4_V of OBUFT_LVCMOS18_F_4 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS18_F_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_f_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS18 I/O Standard Fast Slew 6 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS18_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:32 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS18_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS18_F_6 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS18_F_6; + +architecture OBUFT_LVCMOS18_F_6_V of OBUFT_LVCMOS18_F_6 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS18_F_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_f_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS18 I/O Standard Fast Slew 8 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS18_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:32 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS18_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS18_F_8 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS18_F_8; + +architecture OBUFT_LVCMOS18_F_8_V of OBUFT_LVCMOS18_F_8 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS18_F_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_s_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS18 I/O Standard Slow Slew 12 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS18_S_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:33 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS18_S_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS18_S_12 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS18_S_12; + +architecture OBUFT_LVCMOS18_S_12_V of OBUFT_LVCMOS18_S_12 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS18_S_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_s_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS18 I/O Standard Slow Slew 16 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS18_S_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:33 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS18_S_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS18_S_16 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS18_S_16; + +architecture OBUFT_LVCMOS18_S_16_V of OBUFT_LVCMOS18_S_16 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS18_S_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_s_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS18 I/O Standard Slow Slew 2 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS18_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:33 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS18_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS18_S_2 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS18_S_2; + +architecture OBUFT_LVCMOS18_S_2_V of OBUFT_LVCMOS18_S_2 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS18_S_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_s_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS18 I/O Standard Slow Slew 4 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS18_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:33 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS18_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS18_S_4 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS18_S_4; + +architecture OBUFT_LVCMOS18_S_4_V of OBUFT_LVCMOS18_S_4 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS18_S_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_s_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS18 I/O Standard Slow Slew 6 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS18_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:33 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS18_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS18_S_6 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS18_S_6; + +architecture OBUFT_LVCMOS18_S_6_V of OBUFT_LVCMOS18_S_6 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS18_S_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos18_s_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS18 I/O Standard Slow Slew 8 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS18_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:33 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS18_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS18_S_8 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS18_S_8; + +architecture OBUFT_LVCMOS18_S_8_V of OBUFT_LVCMOS18_S_8 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS18_S_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS2 I/O Standard +-- /___/ /\ Filename : OBUFT_LVCMOS2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:33 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS2 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS2; + +architecture OBUFT_LVCMOS2_V of OBUFT_LVCMOS2 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS25 I/O Standard +-- /___/ /\ Filename : OBUFT_LVCMOS25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:33 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS25 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS25; + +architecture OBUFT_LVCMOS25_V of OBUFT_LVCMOS25 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS25_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_f_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 12 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS25_F_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:33 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS25_F_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS25_F_12 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS25_F_12; + +architecture OBUFT_LVCMOS25_F_12_V of OBUFT_LVCMOS25_F_12 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS25_F_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_f_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 16 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS25_F_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:34 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS25_F_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS25_F_16 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS25_F_16; + +architecture OBUFT_LVCMOS25_F_16_V of OBUFT_LVCMOS25_F_16 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS25_F_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_f_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 2 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS25_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:34 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS25_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS25_F_2 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS25_F_2; + +architecture OBUFT_LVCMOS25_F_2_V of OBUFT_LVCMOS25_F_2 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS25_F_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_f_24.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 24 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS25_F_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:34 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS25_F_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS25_F_24 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS25_F_24; + +architecture OBUFT_LVCMOS25_F_24_V of OBUFT_LVCMOS25_F_24 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS25_F_24_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_f_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 4 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS25_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:34 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS25_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS25_F_4 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS25_F_4; + +architecture OBUFT_LVCMOS25_F_4_V of OBUFT_LVCMOS25_F_4 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS25_F_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_f_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 6 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS25_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:34 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS25_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS25_F_6 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS25_F_6; + +architecture OBUFT_LVCMOS25_F_6_V of OBUFT_LVCMOS25_F_6 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS25_F_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_f_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 8 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS25_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:34 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS25_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS25_F_8 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS25_F_8; + +architecture OBUFT_LVCMOS25_F_8_V of OBUFT_LVCMOS25_F_8 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS25_F_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_s_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 12 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS25_S_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:34 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS25_S_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS25_S_12 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS25_S_12; + +architecture OBUFT_LVCMOS25_S_12_V of OBUFT_LVCMOS25_S_12 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS25_S_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_s_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 16 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS25_S_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:34 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS25_S_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS25_S_16 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS25_S_16; + +architecture OBUFT_LVCMOS25_S_16_V of OBUFT_LVCMOS25_S_16 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS25_S_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_s_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 2 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS25_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:34 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS25_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS25_S_2 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS25_S_2; + +architecture OBUFT_LVCMOS25_S_2_V of OBUFT_LVCMOS25_S_2 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS25_S_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_s_24.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 24 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS25_S_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:35 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS25_S_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS25_S_24 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS25_S_24; + +architecture OBUFT_LVCMOS25_S_24_V of OBUFT_LVCMOS25_S_24 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS25_S_24_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_s_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 4 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS25_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:35 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS25_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS25_S_4 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS25_S_4; + +architecture OBUFT_LVCMOS25_S_4_V of OBUFT_LVCMOS25_S_4 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS25_S_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_s_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 6 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS25_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:35 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS25_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS25_S_6 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS25_S_6; + +architecture OBUFT_LVCMOS25_S_6_V of OBUFT_LVCMOS25_S_6 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS25_S_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos25_s_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 8 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS25_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:35 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS25_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS25_S_8 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS25_S_8; + +architecture OBUFT_LVCMOS25_S_8_V of OBUFT_LVCMOS25_S_8 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS25_S_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS33 I/O Standard +-- /___/ /\ Filename : OBUFT_LVCMOS33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:35 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS33 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS33; + +architecture OBUFT_LVCMOS33_V of OBUFT_LVCMOS33 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS33_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_f_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 12 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS33_F_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:35 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS33_F_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS33_F_12 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS33_F_12; + +architecture OBUFT_LVCMOS33_F_12_V of OBUFT_LVCMOS33_F_12 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS33_F_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_f_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 16 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS33_F_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:35 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS33_F_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS33_F_16 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS33_F_16; + +architecture OBUFT_LVCMOS33_F_16_V of OBUFT_LVCMOS33_F_16 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS33_F_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_f_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 2 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS33_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:35 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS33_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS33_F_2 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS33_F_2; + +architecture OBUFT_LVCMOS33_F_2_V of OBUFT_LVCMOS33_F_2 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS33_F_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_f_24.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 24 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS33_F_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:35 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS33_F_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS33_F_24 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS33_F_24; + +architecture OBUFT_LVCMOS33_F_24_V of OBUFT_LVCMOS33_F_24 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS33_F_24_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_f_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 4 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS33_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:36 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS33_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS33_F_4 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS33_F_4; + +architecture OBUFT_LVCMOS33_F_4_V of OBUFT_LVCMOS33_F_4 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS33_F_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_f_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 6 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS33_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:36 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS33_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS33_F_6 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS33_F_6; + +architecture OBUFT_LVCMOS33_F_6_V of OBUFT_LVCMOS33_F_6 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS33_F_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_f_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 8 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS33_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:36 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS33_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS33_F_8 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS33_F_8; + +architecture OBUFT_LVCMOS33_F_8_V of OBUFT_LVCMOS33_F_8 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS33_F_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_s_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 12 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS33_S_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:36 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS33_S_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS33_S_12 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS33_S_12; + +architecture OBUFT_LVCMOS33_S_12_V of OBUFT_LVCMOS33_S_12 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS33_S_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_s_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 16 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS33_S_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:36 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS33_S_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS33_S_16 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS33_S_16; + +architecture OBUFT_LVCMOS33_S_16_V of OBUFT_LVCMOS33_S_16 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS33_S_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_s_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 2 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS33_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:36 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS33_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS33_S_2 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS33_S_2; + +architecture OBUFT_LVCMOS33_S_2_V of OBUFT_LVCMOS33_S_2 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS33_S_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_s_24.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 24 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS33_S_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:36 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS33_S_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS33_S_24 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS33_S_24; + +architecture OBUFT_LVCMOS33_S_24_V of OBUFT_LVCMOS33_S_24 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS33_S_24_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_s_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 4 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS33_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:36 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS33_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS33_S_4 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS33_S_4; + +architecture OBUFT_LVCMOS33_S_4_V of OBUFT_LVCMOS33_S_4 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS33_S_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_s_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 6 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS33_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:36 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS33_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS33_S_6 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS33_S_6; + +architecture OBUFT_LVCMOS33_S_6_V of OBUFT_LVCMOS33_S_6 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS33_S_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvcmos33_s_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 8 mA Drive +-- /___/ /\ Filename : OBUFT_LVCMOS33_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:37 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVCMOS33_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVCMOS33_S_8 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVCMOS33_S_8; + +architecture OBUFT_LVCMOS33_S_8_V of OBUFT_LVCMOS33_S_8 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVCMOS33_S_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvdci_15.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVDCI_15 I/O Standard +-- /___/ /\ Filename : OBUFT_LVDCI_15.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:37 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVDCI_15 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVDCI_15 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVDCI_15; + +architecture OBUFT_LVDCI_15_V of OBUFT_LVDCI_15 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVDCI_15_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvdci_18.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVDCI_18 I/O Standard +-- /___/ /\ Filename : OBUFT_LVDCI_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:37 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVDCI_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVDCI_18 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVDCI_18; + +architecture OBUFT_LVDCI_18_V of OBUFT_LVDCI_18 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVDCI_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvdci_25.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVDCI_25 I/O Standard +-- /___/ /\ Filename : OBUFT_LVDCI_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:37 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVDCI_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVDCI_25 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVDCI_25; + +architecture OBUFT_LVDCI_25_V of OBUFT_LVDCI_25 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVDCI_25_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvdci_33.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVDCI_33 I/O Standard +-- /___/ /\ Filename : OBUFT_LVDCI_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:37 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVDCI_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVDCI_33 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVDCI_33; + +architecture OBUFT_LVDCI_33_V of OBUFT_LVDCI_33 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVDCI_33_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvdci_dv2_15.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVDCI_DV2_15 I/O Standard +-- /___/ /\ Filename : OBUFT_LVDCI_DV2_15.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:37 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVDCI_DV2_15 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVDCI_DV2_15 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVDCI_DV2_15; + +architecture OBUFT_LVDCI_DV2_15_V of OBUFT_LVDCI_DV2_15 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVDCI_DV2_15_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvdci_dv2_18.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVDCI_DV2_18 I/O Standard +-- /___/ /\ Filename : OBUFT_LVDCI_DV2_18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:37 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVDCI_DV2_18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVDCI_DV2_18 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVDCI_DV2_18; + +architecture OBUFT_LVDCI_DV2_18_V of OBUFT_LVDCI_DV2_18 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVDCI_DV2_18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvdci_dv2_25.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVDCI_DV2_25 I/O Standard +-- /___/ /\ Filename : OBUFT_LVDCI_DV2_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:37 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVDCI_DV2_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVDCI_DV2_25 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVDCI_DV2_25; + +architecture OBUFT_LVDCI_DV2_25_V of OBUFT_LVDCI_DV2_25 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVDCI_DV2_25_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvdci_dv2_33.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVDCI_DV2_33 I/O Standard +-- /___/ /\ Filename : OBUFT_LVDCI_DV2_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:37 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVDCI_DV2_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVDCI_DV2_33 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVDCI_DV2_33; + +architecture OBUFT_LVDCI_DV2_33_V of OBUFT_LVDCI_DV2_33 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVDCI_DV2_33_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvds.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVDS I/O Standard +-- /___/ /\ Filename : OBUFT_LVDS.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:38 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVDS ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVDS is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVDS; + +architecture OBUFT_LVDS_V of OBUFT_LVDS is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVDS_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvpecl.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVPECL I/O Standard +-- /___/ /\ Filename : OBUFT_LVPECL.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:38 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVPECL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVPECL is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVPECL; + +architecture OBUFT_LVPECL_V of OBUFT_LVPECL is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVPECL_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVTTL I/O Standard +-- /___/ /\ Filename : OBUFT_LVTTL.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:38 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVTTL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVTTL is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVTTL; + +architecture OBUFT_LVTTL_V of OBUFT_LVTTL is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVTTL_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_f_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVTTL I/O Standard Fast Slew 12 mA Drive +-- /___/ /\ Filename : OBUFT_LVTTL_F_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:38 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVTTL_F_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVTTL_F_12 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVTTL_F_12; + +architecture OBUFT_LVTTL_F_12_V of OBUFT_LVTTL_F_12 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVTTL_F_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_f_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVTTL I/O Standard Fast Slew 16 mA Drive +-- /___/ /\ Filename : OBUFT_LVTTL_F_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:38 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVTTL_F_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVTTL_F_16 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVTTL_F_16; + +architecture OBUFT_LVTTL_F_16_V of OBUFT_LVTTL_F_16 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVTTL_F_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_f_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVTTL I/O Standard Fast Slew 2 mA Drive +-- /___/ /\ Filename : OBUFT_LVTTL_F_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:38 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVTTL_F_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVTTL_F_2 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVTTL_F_2; + +architecture OBUFT_LVTTL_F_2_V of OBUFT_LVTTL_F_2 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVTTL_F_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_f_24.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVTTL I/O Standard Fast Slew 24 mA Drive +-- /___/ /\ Filename : OBUFT_LVTTL_F_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:38 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVTTL_F_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVTTL_F_24 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVTTL_F_24; + +architecture OBUFT_LVTTL_F_24_V of OBUFT_LVTTL_F_24 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVTTL_F_24_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_f_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVTTL I/O Standard Fast Slew 4 mA Drive +-- /___/ /\ Filename : OBUFT_LVTTL_F_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:38 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVTTL_F_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVTTL_F_4 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVTTL_F_4; + +architecture OBUFT_LVTTL_F_4_V of OBUFT_LVTTL_F_4 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVTTL_F_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_f_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVTTL I/O Standard Fast Slew 6 mA Drive +-- /___/ /\ Filename : OBUFT_LVTTL_F_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:39 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVTTL_F_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVTTL_F_6 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVTTL_F_6; + +architecture OBUFT_LVTTL_F_6_V of OBUFT_LVTTL_F_6 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVTTL_F_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_f_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVTTL I/O Standard Fast Slew 8 mA Drive +-- /___/ /\ Filename : OBUFT_LVTTL_F_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:39 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVTTL_F_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVTTL_F_8 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVTTL_F_8; + +architecture OBUFT_LVTTL_F_8_V of OBUFT_LVTTL_F_8 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVTTL_F_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_s_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVTTL I/O Standard Slow Slew 12 mA Drive +-- /___/ /\ Filename : OBUFT_LVTTL_S_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:39 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVTTL_S_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVTTL_S_12 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVTTL_S_12; + +architecture OBUFT_LVTTL_S_12_V of OBUFT_LVTTL_S_12 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVTTL_S_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_s_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVTTL I/O Standard Slow Slew 16 mA Drive +-- /___/ /\ Filename : OBUFT_LVTTL_S_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:39 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVTTL_S_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVTTL_S_16 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVTTL_S_16; + +architecture OBUFT_LVTTL_S_16_V of OBUFT_LVTTL_S_16 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVTTL_S_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_s_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVTTL I/O Standard Slow Slew 2 mA Drive +-- /___/ /\ Filename : OBUFT_LVTTL_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:39 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVTTL_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVTTL_S_2 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVTTL_S_2; + +architecture OBUFT_LVTTL_S_2_V of OBUFT_LVTTL_S_2 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVTTL_S_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_s_24.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVTTL I/O Standard Slow Slew 24 mA Drive +-- /___/ /\ Filename : OBUFT_LVTTL_S_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:39 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVTTL_S_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVTTL_S_24 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVTTL_S_24; + +architecture OBUFT_LVTTL_S_24_V of OBUFT_LVTTL_S_24 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVTTL_S_24_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_s_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVTTL I/O Standard Slow Slew 4 mA Drive +-- /___/ /\ Filename : OBUFT_LVTTL_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:39 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVTTL_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVTTL_S_4 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVTTL_S_4; + +architecture OBUFT_LVTTL_S_4_V of OBUFT_LVTTL_S_4 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVTTL_S_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_s_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVTTL I/O Standard Slow Slew 6 mA Drive +-- /___/ /\ Filename : OBUFT_LVTTL_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:39 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVTTL_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVTTL_S_6 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVTTL_S_6; + +architecture OBUFT_LVTTL_S_6_V of OBUFT_LVTTL_S_6 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVTTL_S_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_lvttl_s_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with LVTTL I/O Standard Slow Slew 8 mA Drive +-- /___/ /\ Filename : OBUFT_LVTTL_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:39 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_LVTTL_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_LVTTL_S_8 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_LVTTL_S_8; + +architecture OBUFT_LVTTL_S_8_V of OBUFT_LVTTL_S_8 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_LVTTL_S_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_pci33_3.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with PCI33_3 I/O Standard +-- /___/ /\ Filename : OBUFT_PCI33_3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:40 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_PCI33_3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_PCI33_3 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_PCI33_3; + +architecture OBUFT_PCI33_3_V of OBUFT_PCI33_3 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_PCI33_3_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_pci33_5.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with PCI33_5 I/O Standard +-- /___/ /\ Filename : OBUFT_PCI33_5.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:40 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_PCI33_5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_PCI33_5 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_PCI33_5; + +architecture OBUFT_PCI33_5_V of OBUFT_PCI33_5 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_PCI33_5_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_pci66_3.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with PCI66_3 I/O Standard +-- /___/ /\ Filename : OBUFT_PCI66_3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:40 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_PCI66_3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_PCI66_3 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_PCI66_3; + +architecture OBUFT_PCI66_3_V of OBUFT_PCI66_3 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_PCI66_3_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_pcix.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with PCIX I/O Standard +-- /___/ /\ Filename : OBUFT_PCIX.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:40 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_PCIX ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_PCIX is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_PCIX; + +architecture OBUFT_PCIX_V of OBUFT_PCIX is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_PCIX_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_pcix66_3.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with PCIX66_3 I/O Standard +-- /___/ /\ Filename : OBUFT_PCIX66_3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:40 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_PCIX66_3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_PCIX66_3 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_PCIX66_3; + +architecture OBUFT_PCIX66_3_V of OBUFT_PCIX66_3 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_PCIX66_3_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_s_12.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with Slow Slew 12 mA Drive +-- /___/ /\ Filename : OBUFT_S_12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:40 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_S_12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_S_12 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_S_12; + +architecture OBUFT_S_12_V of OBUFT_S_12 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_S_12_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_s_16.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with Slow Slew 16 mA Drive +-- /___/ /\ Filename : OBUFT_S_16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:40 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_S_16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_S_16 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_S_16; + +architecture OBUFT_S_16_V of OBUFT_S_16 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_S_16_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_s_2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with Slow Slew 2 mA Drive +-- /___/ /\ Filename : OBUFT_S_2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:40 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_S_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_S_2 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_S_2; + +architecture OBUFT_S_2_V of OBUFT_S_2 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_S_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_s_24.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with Slow Slew 24 mA Drive +-- /___/ /\ Filename : OBUFT_S_24.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:41 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_S_24 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_S_24 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_S_24; + +architecture OBUFT_S_24_V of OBUFT_S_24 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_S_24_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_s_4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with Slow Slew 4 mA Drive +-- /___/ /\ Filename : OBUFT_S_4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:41 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_S_4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_S_4 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_S_4; + +architecture OBUFT_S_4_V of OBUFT_S_4 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_S_4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_s_6.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with Slow Slew 6 mA Drive +-- /___/ /\ Filename : OBUFT_S_6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:41 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_S_6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_S_6 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_S_6; + +architecture OBUFT_S_6_V of OBUFT_S_6 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_S_6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_s_8.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with Slow Slew 8 mA Drive +-- /___/ /\ Filename : OBUFT_S_8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:41 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_S_8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_S_8 is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_S_8; + +architecture OBUFT_S_8_V of OBUFT_S_8 is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_S_8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl18_i.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with SSTL18_I I/O Standard +-- /___/ /\ Filename : OBUFT_SSTL18_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:41 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_SSTL18_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_SSTL18_I is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_SSTL18_I; + +architecture OBUFT_SSTL18_I_V of OBUFT_SSTL18_I is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_SSTL18_I_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl18_i_dci.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with SSTL18_I_DCI I/O Standard +-- /___/ /\ Filename : OBUFT_SSTL18_I_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:41 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_SSTL18_I_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_SSTL18_I_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_SSTL18_I_DCI; + +architecture OBUFT_SSTL18_I_DCI_V of OBUFT_SSTL18_I_DCI is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_SSTL18_I_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl18_ii.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with SSTL18_II I/O Standard +-- /___/ /\ Filename : OBUFT_SSTL18_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:41 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_SSTL18_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_SSTL18_II is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_SSTL18_II; + +architecture OBUFT_SSTL18_II_V of OBUFT_SSTL18_II is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_SSTL18_II_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl18_ii_dci.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with SSTL18_II_DCI I/O Standard +-- /___/ /\ Filename : OBUFT_SSTL18_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:41 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_SSTL18_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_SSTL18_II_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_SSTL18_II_DCI; + +architecture OBUFT_SSTL18_II_DCI_V of OBUFT_SSTL18_II_DCI is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_SSTL18_II_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl2_i.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with SSTL2_I I/O Standard +-- /___/ /\ Filename : OBUFT_SSTL2_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:42 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_SSTL2_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_SSTL2_I is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_SSTL2_I; + +architecture OBUFT_SSTL2_I_V of OBUFT_SSTL2_I is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_SSTL2_I_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl2_i_dci.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with SSTL2_I_DCI I/O Standard +-- /___/ /\ Filename : OBUFT_SSTL2_I_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:42 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_SSTL2_I_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_SSTL2_I_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_SSTL2_I_DCI; + +architecture OBUFT_SSTL2_I_DCI_V of OBUFT_SSTL2_I_DCI is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_SSTL2_I_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl2_ii.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with SSTL2_II I/O Standard +-- /___/ /\ Filename : OBUFT_SSTL2_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:42 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_SSTL2_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_SSTL2_II is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_SSTL2_II; + +architecture OBUFT_SSTL2_II_V of OBUFT_SSTL2_II is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_SSTL2_II_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl2_ii_dci.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with SSTL2_II_DCI I/O Standard +-- /___/ /\ Filename : OBUFT_SSTL2_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:42 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_SSTL2_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_SSTL2_II_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_SSTL2_II_DCI; + +architecture OBUFT_SSTL2_II_DCI_V of OBUFT_SSTL2_II_DCI is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_SSTL2_II_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl3_i.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with SSTL3_I I/O Standard +-- /___/ /\ Filename : OBUFT_SSTL3_I.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:42 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_SSTL3_I ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_SSTL3_I is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_SSTL3_I; + +architecture OBUFT_SSTL3_I_V of OBUFT_SSTL3_I is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_SSTL3_I_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl3_i_dci.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with SSTL3_I_DCI I/O Standard +-- /___/ /\ Filename : OBUFT_SSTL3_I_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:42 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_SSTL3_I_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_SSTL3_I_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_SSTL3_I_DCI; + +architecture OBUFT_SSTL3_I_DCI_V of OBUFT_SSTL3_I_DCI is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_SSTL3_I_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl3_ii.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with SSTL3_II I/O Standard +-- /___/ /\ Filename : OBUFT_SSTL3_II.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:42 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_SSTL3_II ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_SSTL3_II is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_SSTL3_II; + +architecture OBUFT_SSTL3_II_V of OBUFT_SSTL3_II is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_SSTL3_II_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuft_sstl3_ii_dci.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer with SSTL3_II_DCI I/O Standard +-- /___/ /\ Filename : OBUFT_SSTL3_II_DCI.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:42 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFT_SSTL3_II_DCI ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFT_SSTL3_II_DCI is + port( + O : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); + +end OBUFT_SSTL3_II_DCI; + +architecture OBUFT_SSTL3_II_DCI_V of OBUFT_SSTL3_II_DCI is +begin + VITALBehavior : process (I, T) + begin + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFT_SSTL3_II_DCI_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds.vhd,v 1.5 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Differential Signaling Output Buffer +-- /___/ /\ Filename : OBUFTDS.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:42 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFTDS ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFTDS is + generic( + CAPACITANCE : string := "DONT_CARE"; + IOSTANDARD : string := "DEFAULT" + ); + + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); +end OBUFTDS; + +architecture OBUFTDS_V of OBUFTDS is +begin + prcs_init : process + variable FIRST_TIME : boolean := TRUE; + begin + + If(FIRST_TIME = true) then + if((CAPACITANCE = "LOW") or + (CAPACITANCE = "NORMAL") or + (CAPACITANCE = "DONT_CARE")) then + FIRST_TIME := false; + else + assert false + report "Attribute Syntax Error: The allowed values for CAPACITANCE are LOW, NORMAL or DONT_CARE" + severity Failure; + end if; + end if; + wait; + end process prcs_init; + + VITALBehavior : process (I, T) + begin + + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + + if ((T = '1') or (T = 'H')) then + OB <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if (((not I) = '1') or ((not I) = 'H')) then + OB <= '1'; + elsif (((not I) = '0') or ((not I) = 'L')) then + OB <= '0'; + elsif ((not I) = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + elsif (T = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + end process; +end OBUFTDS_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds_blvds_25.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Differential Signaling Output Buffer with BLVDS_25 I/O Standard +-- /___/ /\ Filename : OBUFTDS_BLVDS_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:43 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFTDS_BLVDS_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFTDS_BLVDS_25 is + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); +end OBUFTDS_BLVDS_25; + +architecture OBUFTDS_BLVDS_25_V of OBUFTDS_BLVDS_25 is +begin + VITALBehavior : process (I, T) + variable O_zd : std_ulogic; + variable OB_zd : std_ulogic; + begin + + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + + if ((T = '1') or (T = 'H')) then + OB <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if (((not I) = '1') or ((not I) = 'H')) then + OB <= '1'; + elsif (((not I) = '0') or ((not I) = 'L')) then + OB <= '0'; + elsif ((not I) = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + elsif (T = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + end process; +end OBUFTDS_BLVDS_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds_ldt_25.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Differential Signaling Output Buffer with LDT_25 I/O Standard +-- /___/ /\ Filename : OBUFTDS_LDT_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:43 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFTDS_LDT_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFTDS_LDT_25 is + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); +end OBUFTDS_LDT_25; + +architecture OBUFTDS_LDT_25_V of OBUFTDS_LDT_25 is +begin + VITALBehavior : process (I, T) + variable O_zd : std_ulogic; + variable OB_zd : std_ulogic; + begin + + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + + if ((T = '1') or (T = 'H')) then + OB <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if (((not I) = '1') or ((not I) = 'H')) then + OB <= '1'; + elsif (((not I) = '0') or ((not I) = 'L')) then + OB <= '0'; + elsif ((not I) = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + elsif (T = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + end process; +end OBUFTDS_LDT_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds_lvds_25.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Differential Signaling Output Buffer with LVDS_25 I/O Standard +-- /___/ /\ Filename : OBUFTDS_LVDS_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:43 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFTDS_LVDS_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFTDS_LVDS_25 is + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); +end OBUFTDS_LVDS_25; + +architecture OBUFTDS_LVDS_25_V of OBUFTDS_LVDS_25 is +begin + VITALBehavior : process (I, T) + variable O_zd : std_ulogic; + variable OB_zd : std_ulogic; + begin + + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + + if ((T = '1') or (T = 'H')) then + OB <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if (((not I) = '1') or ((not I) = 'H')) then + OB <= '1'; + elsif (((not I) = '0') or ((not I) = 'L')) then + OB <= '0'; + elsif ((not I) = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + elsif (T = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + end process; +end OBUFTDS_LVDS_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds_lvds_33.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Differential Signaling Output Buffer with LVDS_33 I/O Standard +-- /___/ /\ Filename : OBUFTDS_LVDS_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:43 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFTDS_LVDS_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFTDS_LVDS_33 is + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); +end OBUFTDS_LVDS_33; + +architecture OBUFTDS_LVDS_33_V of OBUFTDS_LVDS_33 is +begin + VITALBehavior : process (I, T) + begin + + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + + if ((T = '1') or (T = 'H')) then + OB <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if (((not I) = '1') or ((not I) = 'H')) then + OB <= '1'; + elsif (((not I) = '0') or ((not I) = 'L')) then + OB <= '0'; + elsif ((not I) = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + elsif (T = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + end process; +end OBUFTDS_LVDS_33_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds_lvdsext_25.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Differential Signaling Output Buffer with LVDSEXT_25 I/O Standard +-- /___/ /\ Filename : OBUFTDS_LVDSEXT_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:43 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFTDS_LVDSEXT_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFTDS_LVDSEXT_25 is + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); +end OBUFTDS_LVDSEXT_25; + +architecture OBUFTDS_LVDSEXT_25_V of OBUFTDS_LVDSEXT_25 is +begin + VITALBehavior : process (I, T) + begin + + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + + if ((T = '1') or (T = 'H')) then + OB <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if (((not I) = '1') or ((not I) = 'H')) then + OB <= '1'; + elsif (((not I) = '0') or ((not I) = 'L')) then + OB <= '0'; + elsif ((not I) = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + elsif (T = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + end process; +end OBUFTDS_LVDSEXT_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds_lvdsext_33.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Differential Signaling Output Buffer with LVDSEXT_33 I/O Standard +-- /___/ /\ Filename : OBUFTDS_LVDSEXT_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:43 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFTDS_LVDSEXT_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFTDS_LVDSEXT_33 is + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); +end OBUFTDS_LVDSEXT_33; + +architecture OBUFTDS_LVDSEXT_33_V of OBUFTDS_LVDSEXT_33 is +begin + VITALBehavior : process (I, T) + begin + + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + + if ((T = '1') or (T = 'H')) then + OB <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if (((not I) = '1') or ((not I) = 'H')) then + OB <= '1'; + elsif (((not I) = '0') or ((not I) = 'L')) then + OB <= '0'; + elsif ((not I) = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + elsif (T = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + end process; +end OBUFTDS_LVDSEXT_33_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds_lvpecl_25.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Differential Signaling Output Buffer with LVPECL_25 I/O Standard +-- /___/ /\ Filename : OBUFTDS_LVPECL_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:43 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFTDS_LVPECL_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFTDS_LVPECL_25 is + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); +end OBUFTDS_LVPECL_25; + +architecture OBUFTDS_LVPECL_25_V of OBUFTDS_LVPECL_25 is +begin + VITALBehavior : process (I, T) + begin + + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + + if ((T = '1') or (T = 'H')) then + OB <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if (((not I) = '1') or ((not I) = 'H')) then + OB <= '1'; + elsif (((not I) = '0') or ((not I) = 'L')) then + OB <= '0'; + elsif ((not I) = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + elsif (T = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + end process; +end OBUFTDS_LVPECL_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds_lvpecl_33.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Differential Signaling Output Buffer with LVPECL_33 I/O Standard +-- /___/ /\ Filename : OBUFTDS_LVPECL_33.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:43 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFTDS_LVPECL_33 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFTDS_LVPECL_33 is + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); +end OBUFTDS_LVPECL_33; + +architecture OBUFTDS_LVPECL_33_V of OBUFTDS_LVPECL_33 is +begin + VITALBehavior : process (I, T) + begin + + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + + if ((T = '1') or (T = 'H')) then + OB <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if (((not I) = '1') or ((not I) = 'H')) then + OB <= '1'; + elsif (((not I) = '0') or ((not I) = 'L')) then + OB <= '0'; + elsif ((not I) = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + elsif (T = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + end process; +end OBUFTDS_LVPECL_33_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/obuftds_ulvds_25.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Differential Signaling Output Buffer with ULVDS_25 I/O Standard +-- /___/ /\ Filename : OBUFTDS_ULVDS_25.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:43 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFTDS_ULVDS_25 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFTDS_ULVDS_25 is + port( + O : out std_ulogic; + OB : out std_ulogic; + + I : in std_ulogic; + T : in std_ulogic + ); +end OBUFTDS_ULVDS_25; + +architecture OBUFTDS_ULVDS_25_V of OBUFTDS_ULVDS_25 is +begin + VITALBehavior : process (I, T) + begin + + if ((T = '1') or (T = 'H')) then + O <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif (T = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + + if ((T = '1') or (T = 'H')) then + OB <= 'Z'; + elsif ((T = '0') or (T = 'L')) then + if (((not I) = '1') or ((not I) = 'H')) then + OB <= '1'; + elsif (((not I) = '0') or ((not I) = 'L')) then + OB <= '0'; + elsif ((not I) = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + elsif (T = 'U') then + OB <= 'U'; + else + OB <= 'X'; + end if; + end process; +end OBUFTDS_ULVDS_25_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ofddrcpe.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Dual Data Rate Output D Flip-Flop with Asynchronous Clear and Preset and Clock Enable +-- /___/ /\ Filename : OFDDRCPE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:44 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OFDDRCPE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VCOMPONENTS.all; + +entity OFDDRCPE is + port( + Q : out std_ulogic; + + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + CLR : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + PRE : in std_ulogic + ); +end OFDDRCPE; + +architecture OFDDRCPE_V of OFDDRCPE is + SIGNAL Q_out : STD_ULOGIC := 'X'; + +begin + F0 : FDDRCPE + generic map ( + INIT => '0' ) + port map ( + C0 => C0, + C1 => C1, + CE => CE, + CLR => CLR, + D0 => D0, + D1 => D1, + PRE => PRE, + Q => Q_out + ); + + O1 : OBUF + port map ( + I => Q_out, + O => Q + ); +end OFDDRCPE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ofddrrse.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Dual Data Rate Output D Flip-Flop with Synchronous Reset and Set and Clock Enable +-- /___/ /\ Filename : OFDDRRSE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:44 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OFDDRRSE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VCOMPONENTS.all; + +entity OFDDRRSE is + port( + Q : out std_ulogic; + + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end OFDDRRSE; + +architecture OFDDRRSE_V of OFDDRRSE is + + signal Q_out : std_ulogic := 'X'; + +begin + O1 : OBUF + port map ( + I => Q_out, + O => Q + ); + + F0 : FDDRRSE + generic map (INIT => '0' + ) + + port map ( + C0 => C0, + C1 => C1, + CE => CE, + R => R, + D0 => D0, + D1 => D1, + S => S, + Q => Q_out + ); +end OFDDRRSE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ofddrtcpe.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Dual Data Rate Output D Flip-Flop with 3-State Output, Asynchronous Clear and Preset and Clock Enable +-- /___/ /\ Filename : OFDDRTCPE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:44 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OFDDRTCPE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VCOMPONENTS.all; + +entity OFDDRTCPE is + port( + O : out std_ulogic; + + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + CLR : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + PRE : in std_ulogic; + T : in std_ulogic + ); +end OFDDRTCPE; + +architecture OFDDRTCPE_V of OFDDRTCPE is + + signal Q_out : std_ulogic := 'X'; + +begin + F0 : FDDRCPE + generic map ( + INIT => '0' ) + port map ( + C0 => C0, + C1 => C1, + CE => CE, + CLR => CLR, + D0 => D0, + D1 => D1, + PRE => PRE, + Q => Q_out + ); + + O1 : OBUFT + port map ( + I => Q_out, + T => T, + O => O + ); +end OFDDRTCPE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ofddrtrse.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Dual Data Rate Output D Flip-Flop with 3-State Output, Synchronous Reset and Set and Clock Enable +-- /___/ /\ Filename : OFDDRTRSE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:44 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OFDDRTRSE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VCOMPONENTS.all; + +entity OFDDRTRSE is + port( + O : out std_ulogic; + + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic; + T : in std_ulogic + ); +end OFDDRTRSE; + +architecture OFDDRTRSE_V of OFDDRTRSE is + signal Q_out : std_ulogic := 'X'; + +begin + F0 : FDDRRSE + generic map ( + INIT => '0' + ) + port map ( + C0 => C0, + C1 => C1, + CE => CE, + R => R, + D0 => D0, + D1 => D1, + S => S, + Q => Q_out + ); + + O1 : OBUFT + port map ( + I => Q_out, + T => T, + O => O + ); +end OFDDRTRSE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-input OR Gate +-- /___/ /\ Filename : OR2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:44 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR2 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end OR2; + +architecture OR2_V of OR2 is +begin + O <= (I0 or I1); +end OR2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or2b1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-input OR Gate +-- /___/ /\ Filename : OR2B1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:44 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR2B1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR2B1 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end OR2B1; + +architecture OR2B1_V of OR2B1 is +begin + O <= ((not I0) or I1); +end OR2B1_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or2b2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-input OR Gate +-- /___/ /\ Filename : OR2B2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:45 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR2B2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR2B2 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end OR2B2; + +architecture OR2B2_V of OR2B2 is +begin + O <= ((not I0) or (not I1)); +end OR2B2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or3.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input OR Gate +-- /___/ /\ Filename : OR3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:45 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR3 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end OR3; + +architecture OR3_V of OR3 is +begin + O <= (I0 or I1 or I2); +end OR3_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or3b1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input OR Gate +-- /___/ /\ Filename : OR3B1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:45 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR3B1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR3B1 is + port( + O : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end OR3B1; + +architecture OR3B1_V of OR3B1 is +begin + O <= ((not I0) or I1 or I2); +end OR3B1_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or3b2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input OR Gate +-- /___/ /\ Filename : OR3B2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:45 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR3B2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR3B2 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end OR3B2; + +architecture OR3B2_V of OR3B2 is +begin + O <= ((not I0) or (not I1) or I2); +end OR3B2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or3b3.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input OR Gate +-- /___/ /\ Filename : OR3B3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:45 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR3B3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR3B3 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end OR3B3; + +architecture OR3B3_V of OR3B3 is +begin + O <= ((not I0) or (not I1) or (not I2)); +end OR3B3_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input OR Gate +-- /___/ /\ Filename : OR4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:45 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR4 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end OR4; + +architecture OR4_V of OR4 is +begin + O <= (I0 or I1 or I2 or I3); +end OR4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or4b1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input OR Gate +-- /___/ /\ Filename : OR4B1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:45 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR4B1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR4B1 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end OR4B1; + +architecture OR4B1_V of OR4B1 is +begin + O <= ((not I0) or I1 or I2 or I3); +end OR4B1_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or4b2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input OR Gate +-- /___/ /\ Filename : OR4B2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:45 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR4B2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR4B2 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end OR4B2; + +architecture OR4B2_V of OR4B2 is +begin + O <= ((not I0) or (not I1) or I2 or I3); +end OR4B2_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or4b3.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input OR Gate +-- /___/ /\ Filename : OR4B3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:45 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR4B3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR4B3 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end OR4B3; + +architecture OR4B3_V of OR4B3 is +begin + O <= ((not I2)) or (I3) or ((not I1)) or ((not I0)); +end OR4B3_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or4b4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input OR Gate +-- /___/ /\ Filename : OR4B4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:46 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR4B4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR4B4 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end OR4B4; + +architecture OR4B4_V of OR4B4 is +begin + O <= ((not I0) or (not I1) or (not I2) or (not I3)); +end OR4B4_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or5.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input OR Gate +-- /___/ /\ Filename : OR5.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:46 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR5 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end OR5; + +architecture OR5_V of OR5 is +begin + O <= (I0 or I1 or I2 or I3 or I4); +end OR5_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or5b1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input OR Gate +-- /___/ /\ Filename : OR5B1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:46 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR5B1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR5B1 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end OR5B1; + +architecture OR5B1_V of OR5B1 is +begin + O <= ((not I0) or I1 or I2 or I3 or I4); +end OR5B1_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or5b2.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input OR Gate +-- /___/ /\ Filename : OR5B2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:46 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR5B2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR5B2 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end OR5B2; + +architecture OR5B2_V of OR5B2 is +begin + O <= ((not I0) or (not I1) or I2 or I3 or I4); +end OR5B2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or5b3.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input OR Gate +-- /___/ /\ Filename : OR5B3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:46 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR5B3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR5B3 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end OR5B3; + +architecture OR5B3_V of OR5B3 is +begin + O <= ((not I0) or (not I1) or (not I2) or I3 or I4); +end OR5B3_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or5b4.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input OR Gate +-- /___/ /\ Filename : OR5B4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:46 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR5B4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR5B4 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end OR5B4; + +architecture OR5B4_V of OR5B4 is +begin + O <= ((not I0) or (not I1) or (not I2) or (not I3) or I4); +end OR5B4_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/or5b5.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input OR Gate +-- /___/ /\ Filename : OR5B5.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:46 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR5B5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR5B5 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end OR5B5; + +architecture OR5B5_V of OR5B5 is +begin + O <= ((not I0) or (not I1) or (not I2) or (not I3) or (not I4)); +end OR5B5_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/orcy.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / OR with Carry Logic +-- /___/ /\ Filename : ORCY.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:47 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL ORCY ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity ORCY is + port( + O : out std_ulogic; + + CI : in std_ulogic; + I : in std_ulogic + ); +end ORCY; + +architecture ORCY_V of ORCY is +begin + O <= (CI or I); +end ORCY_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/pulldown.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Resistor to GND +-- /___/ /\ Filename : PULLDOWN.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:47 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL PULLDOWN ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity PULLDOWN is + port( + O : out std_ulogic := 'L' + ); +end PULLDOWN; + +architecture PULLDOWN_V of PULLDOWN is +begin + O <= 'L'; +end PULLDOWN_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/pullup.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Resistor to VCC +-- /___/ /\ Filename : PULLUP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:47 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL PULLUP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity PULLUP is + port( + O : out std_ulogic := 'H' + ); +end PULLUP; + +architecture PULLUP_V of PULLUP is +begin + O <= 'H'; +end PULLUP_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram128x1s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Synchronous RAM 128-Deep by 1-Wide +-- /___/ /\ Filename : RAM128X1S.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:47 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM128X1S ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM128X1S is + + generic ( + INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000" + ); + + port ( + O : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic; + A6 : in std_ulogic; + D : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM128X1S; + +architecture RAM128X1S_V of RAM128X1S is + signal MEM : std_logic_vector( 128 downto 0 ) := ('X' & To_StdLogicVector(INIT) ); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, A4, A5, A6, MEM) + Variable Index : integer := 128; + variable Address : std_logic_vector( 6 downto 0); + + begin + Address := (A6, A5, A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + O <= MEM(Index); + + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + Variable Index : integer := 128; + variable Address : std_logic_vector (6 downto 0); + + begin + if (rising_edge(WCLK)) then + if (WE = '1') then + Address := (A6, A5, A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + MEM(Index) <= D after 100 ps; + end if; + end if; + end process VITALWriteBehavior; +end RAM128X1S_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram128x1s_1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Synchronous RAM 128-Deep by 1-Wide +-- /___/ /\ Filename : RAM128X1S_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:47 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM128X1S_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM128X1S_1 is + + generic ( + INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000" + ); + + port ( + O : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic; + A6 : in std_ulogic; + D : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM128X1S_1; + +architecture RAM128X1S_1_V of RAM128X1S_1 is + signal MEM : std_logic_vector( 128 downto 0 ) := ('X' & To_StdLogicVector(INIT) ); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, A4, A5, A6, MEM) + Variable Index : integer := 128; + variable Address : std_logic_vector( 6 downto 0); + + begin + Address := (A6, A5, A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + O <= MEM(Index); + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + Variable Index : integer := 128; + variable Address : std_logic_vector (6 downto 0); + + begin + if (falling_edge(WCLK)) then + if (WE = '1') then + Address := (A6, A5, A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + MEM(Index) <= D after 100 ps; + end if; + end if; + end process VITALWriteBehavior; +end RAM128X1S_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram16x1d.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Dual Port Synchronous RAM 16-Deep by 1-Wide +-- /___/ /\ Filename : RAM16X1D.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:47 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM16X1D ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM16X1D is + + generic ( + INIT : bit_vector(15 downto 0) := X"0000" + ); + + port ( + DPO : out std_ulogic; + SPO : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + D : in std_ulogic; + DPRA0 : in std_ulogic; + DPRA1 : in std_ulogic; + DPRA2 : in std_ulogic; + DPRA3 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM16X1D; + +architecture RAM16X1D_V of RAM16X1D is + signal MEM : std_logic_vector( 16 downto 0 ) := ('X' & To_StdLogicVector(INIT) ); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, DPRA3, DPRA2, DPRA1, DPRA0, MEM) + Variable Index_SP : integer := 16 ; + Variable Index_DP : integer := 16 ; + + begin + Index_SP := DECODE_ADDR4(ADDRESS => (A3, A2, A1, A0)); + Index_DP := DECODE_ADDR4(ADDRESS => (DPRA3, DPRA2, DPRA1, DPRA0)); + SPO <= MEM(Index_SP); + DPO <= MEM(Index_DP); + + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + variable Index_SP : integer := 16; + variable Index_DP : integer := 16; + begin + Index_SP := DECODE_ADDR4(ADDRESS => (A3, A2, A1, A0)); + if ((WE = '1') and (wclk'event) and (wclk'last_value = '0') and (wclk = '1')) then + MEM(Index_SP) <= D after 100 ps; + end if; + end process VITALWriteBehavior; +end RAM16X1D_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram16x1d_1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Dual Port Synchronous RAM 16-Deep by 1-Wide +-- /___/ /\ Filename : RAM16X1D_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:47 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM16X1D_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM16X1D_1 is + + generic ( + INIT : bit_vector(15 downto 0) := X"0000" + ); + + port ( + DPO : out std_ulogic; + SPO : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + D : in std_ulogic; + DPRA0 : in std_ulogic; + DPRA1 : in std_ulogic; + DPRA2 : in std_ulogic; + DPRA3 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM16X1D_1; + +architecture RAM16X1D_1_V of RAM16X1D_1 is + signal MEM : std_logic_vector( 16 downto 0 ) := ('X' & To_StdLogicVector(INIT) ); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, DPRA3, DPRA2, DPRA1, DPRA0, MEM) + variable Index_SP : integer := 16; + variable Index_DP : integer := 16; + + begin + Index_SP := DECODE_ADDR4(ADDRESS => (A3, A2, A1, A0)); + Index_DP := DECODE_ADDR4(ADDRESS => (DPRA3, DPRA2, DPRA1, DPRA0)); + SPO <= MEM(Index_SP); + DPO <= MEM(Index_DP); + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + variable Index_SP : integer := 16; + variable Index_DP : integer := 16; + begin + Index_SP := DECODE_ADDR4(ADDRESS => (A3, A2, A1, A0)); + if ((WE = '1') and (wclk'event) and (wclk'last_value = '1') and (wclk = '0')) then + MEM(Index_SP) <= D after 100 ps; + end if; + + end process VITALWriteBehavior; +end RAM16X1D_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram16x1s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Synchronous RAM 16-Deep by 1-Wide +-- /___/ /\ Filename : RAM16X1S.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:47 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM16X1S ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM16X1S is + + generic ( + INIT : bit_vector(15 downto 0) := X"0000" + ); + + port ( + O : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + D : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM16X1S; + +architecture RAM16X1S_V of RAM16X1S is + signal MEM : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT)); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, MEM) + variable Index : integer := 16; + variable Address : std_logic_vector(3 downto 0); + begin + Address := (A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + O <= MEM(Index); + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + variable Index : integer := 16; + variable Address : std_logic_vector (3 downto 0); + begin + if (rising_edge(WCLK)) then + if (WE = '1') then + Address := (A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + MEM(Index) <= D after 100 ps; + end if; + end if; + end process VITALWriteBehavior; +end RAM16X1S_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram16x1s_1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Synchronous RAM 16-Deep by 1 -Wide +-- /___/ /\ Filename : RAM16X1S_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:48 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM16X1S_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM16X1S_1 is + + generic ( + INIT : bit_vector(15 downto 0) := X"0000" + ); + + port ( + O : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + D : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM16X1S_1; + +architecture RAM16X1S_1_V of RAM16X1S_1 is + signal MEM : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT)); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, MEM) + variable Index : integer := 16; + variable Address : std_logic_vector(3 downto 0); + begin + Address := (A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + O <= MEM(Index); + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + variable Index : integer := 16; + variable Address : std_logic_vector (3 downto 0); + begin + if (falling_edge(WCLK)) then + if (WE = '1') then + Address := (A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + MEM(Index) <= D after 100 ps; + end if; + end if; + end process VITALWriteBehavior; +end RAM16X1S_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram16x2s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Synchronous RAM 16-Deep by 2-Wide +-- /___/ /\ Filename : RAM16X2S.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:48 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM16X2S ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM16X2S is + + generic ( + INIT_00 : bit_vector(15 downto 0) := X"0000"; + INIT_01 : bit_vector(15 downto 0) := X"0000" + ); + + port ( + O0 : out std_ulogic; + O1 : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM16X2S; + +architecture RAM16X2S_V of RAM16X2S is + signal MEM0 : std_logic_vector( 16 downto 0 ) := ('X' & To_StdLogicVector(INIT_00) ); + signal MEM1 : std_logic_vector( 16 downto 0 ) := ('X' & To_StdLogicVector(INIT_01) ); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, MEM0, MEM1) + variable Index : integer := 16; + variable Address : std_logic_vector(3 downto 0); + + begin + Address := (A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + O0 <= MEM0(Index); + O1 <= MEM1(Index); + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + variable Index : integer := 16; + variable Address : std_logic_vector(3 downto 0); + begin + if (rising_edge(WCLK)) then + if (WE = '1') then + Address := (A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + MEM0(Index) <= D0 after 100 ps; + MEM1(Index) <= D1 after 100 ps; + end if; + end if; + end process VITALWriteBehavior; +end RAM16X2S_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram16x4s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Synchronous RAM 16-Deep by 4-Wide +-- /___/ /\ Filename : RAM16X4S.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:48 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM16X4S ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM16X4S is + + generic ( + INIT_00 : bit_vector(15 downto 0) := X"0000"; + INIT_01 : bit_vector(15 downto 0) := X"0000"; + INIT_02 : bit_vector(15 downto 0) := X"0000"; + INIT_03 : bit_vector(15 downto 0) := X"0000" + ); + + port ( + O0 : out std_ulogic; + O1 : out std_ulogic; + O2 : out std_ulogic; + O3 : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + D2 : in std_ulogic; + D3 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM16X4S; + +architecture RAM16X4S_V of RAM16X4S is + signal MEM0 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_00)); + signal MEM1 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_01)); + signal MEM2 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_02)); + signal MEM3 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_03)); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, MEM0, MEM1, MEM2, MEM3) + variable Index : integer := 16; + variable Address : std_logic_vector(3 downto 0); + begin + Address := (A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + O0 <= MEM0(Index); + O1 <= MEM1(Index); + O2 <= MEM2(Index); + O3 <= MEM3(Index); + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + variable Index : integer := 16; + variable Address : std_logic_vector(3 downto 0); + begin + if (rising_edge(WCLK)) then + if (WE = '1') then + Address := (A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + MEM0(Index) <= D0 after 100 ps; + MEM1(Index) <= D1 after 100 ps; + MEM2(Index) <= D2 after 100 ps; + MEM3(Index) <= D3 after 100 ps; + end if; + end if; + end process VITALWriteBehavior; +end RAM16X4S_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram16x8s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Synchronous RAM 16-Deep by 8-Wide +-- /___/ /\ Filename : RAM16X8S.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:48 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM16X8S ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM16X8S is + generic ( + INIT_00 : bit_vector(15 downto 0) := X"0000"; + INIT_01 : bit_vector(15 downto 0) := X"0000"; + INIT_02 : bit_vector(15 downto 0) := X"0000"; + INIT_03 : bit_vector(15 downto 0) := X"0000"; + INIT_04 : bit_vector(15 downto 0) := X"0000"; + INIT_05 : bit_vector(15 downto 0) := X"0000"; + INIT_06 : bit_vector(15 downto 0) := X"0000"; + INIT_07 : bit_vector(15 downto 0) := X"0000" + ); + + port ( + O : out std_logic_vector ( 7 downto 0); + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + D : in std_logic_vector ( 7 downto 0); + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM16X8S; + +architecture RAM16X8S_V of RAM16X8S is + signal MEM0 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_00)); + signal MEM1 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_01)); + signal MEM2 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_02)); + signal MEM3 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_03)); + signal MEM4 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_04)); + signal MEM5 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_05)); + signal MEM6 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_06)); + signal MEM7 : std_logic_vector(16 downto 0) := ('X' & To_StdLogicVector(INIT_07)); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, MEM0, MEM1, MEM2, MEM3, MEM4, MEM5, MEM6, MEM7) + variable Index : integer := 16; + variable Address : std_logic_vector(3 downto 0); + begin + Address := (A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + O(0) <= MEM0(Index); + O(1) <= MEM1(Index); + O(2) <= MEM2(Index); + O(3) <= MEM3(Index); + O(4) <= MEM4(Index); + O(5) <= MEM5(Index); + O(6) <= MEM6(Index); + O(7) <= MEM7(Index); + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + variable Index : integer := 16; + variable Address : std_logic_vector(3 downto 0); + begin + if (rising_edge(WCLK)) then + if (WE = '1') then + Address := (A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + MEM0(Index) <= D(0) after 100 ps; + MEM1(Index) <= D(1) after 100 ps; + MEM2(Index) <= D(2) after 100 ps; + MEM3(Index) <= D(3) after 100 ps; + MEM4(Index) <= D(4) after 100 ps; + MEM5(Index) <= D(5) after 100 ps; + MEM6(Index) <= D(6) after 100 ps; + MEM7(Index) <= D(7) after 100 ps; + end if; + end if; + end process VITALWriteBehavior; +end RAM16X8S_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram32x1d.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Dual Port Synchronous RAM 32-Deep by 1-Wide +-- /___/ /\ Filename : RAM32X1D.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:48 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM32X1D ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM32X1D is + + generic ( + INIT : bit_vector(31 downto 0) := X"00000000" + ); + + port ( + DPO : out std_ulogic; + SPO : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + D : in std_ulogic; + DPRA0 : in std_ulogic; + DPRA1 : in std_ulogic; + DPRA2 : in std_ulogic; + DPRA3 : in std_ulogic; + DPRA4 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM32X1D; +architecture RAM32X1D_V of RAM32X1D is + signal MEM : std_logic_vector( 32 downto 0 ) := ('X' & To_StdLogicVector(INIT) ); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, A4, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0, MEM) + Variable Index_SP : integer := 32 ; + Variable Index_DP : integer := 32 ; + variable Raddress : std_logic_vector (4 downto 0); + variable Waddress : std_logic_vector (4 downto 0); + + begin + Waddress := (A4, A3, A2, A1, A0); + Raddress := (DPRA4, DPRA3, DPRA2, DPRA1, DPRA0); + Index_SP := SLV_TO_INT(SLV => Waddress); + Index_DP := SLV_TO_INT(SLV => Raddress); + SPO <= MEM(Index_SP); + DPO <= MEM(Index_DP); + + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + variable Index_SP : integer := 32; + variable Index_DP : integer := 32; + variable Address : std_logic_vector( 4 downto 0); + + begin + Address := (A4, A3, A2, A1, A0); + Index_SP := SLV_TO_INT(SLV => Address ); + if ((WE = '1') and (wclk'event) and (wclk'last_value = '0') and (wclk = '1')) then + MEM(Index_SP) <= D after 100 ps; + end if; + end process VITALWriteBehavior; +end RAM32X1D_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram32x1d_1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Dual Port Synchronous RAM 32-Deep by 1-Wide +-- /___/ /\ Filename : RAM32X1D_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:48 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM32X1D_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM32X1D_1 is + + generic ( + INIT : bit_vector(31 downto 0) := X"00000000" + ); + + port ( + DPO : out std_ulogic; + SPO : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + D : in std_ulogic; + DPRA0 : in std_ulogic; + DPRA1 : in std_ulogic; + DPRA2 : in std_ulogic; + DPRA3 : in std_ulogic; + DPRA4 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM32X1D_1; + +architecture RAM32X1D_1_V of RAM32X1D_1 is + signal MEM : std_logic_vector( 32 downto 0 ) := ('X' & To_StdLogicVector(INIT) ); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, A4, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0, MEM) + variable Index_SP : integer := 32; + variable Index_DP : integer := 32; + variable Raddress : std_logic_vector (4 downto 0); + variable Waddress : std_logic_vector (4 downto 0); + + begin + Raddress := (A4, A3, A2, A1, A0); + Waddress := (DPRA4, DPRA3, DPRA2, DPRA1, DPRA0); + Index_SP := SLV_TO_INT(SLV => Raddress); + Index_DP := SLV_TO_INT(SLV => Waddress); + SPO <= MEM(Index_SP); + DPO <= MEM(Index_DP); + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + variable Index_SP : integer := 32; + variable Index_DP : integer := 32; + variable Address : std_logic_vector( 4 downto 0); + + begin + Address := (A4, A3, A2, A1, A0); + Index_SP := SLV_TO_INT(SLV => Address ); + if ((WE = '1') and (wclk'event) and (wclk'last_value = '1') and (wclk = '0')) then + MEM(Index_SP) <= D after 100 ps; + end if; + end process VITALWriteBehavior; +end RAM32X1D_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram32x1s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Synchronous RAM 32-Deep by 1-Wide +-- /___/ /\ Filename : RAM32X1S.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:48 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM32X1S ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM32X1S is + generic ( + INIT : bit_vector(31 downto 0) := X"00000000" + ); + + port ( + O : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + D : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM32X1S; + +architecture RAM32X1S_V of RAM32X1S is + signal MEM : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT)); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, A4, MEM) + variable Index : integer := 32; + variable Address : std_logic_vector (4 downto 0); + + begin + Address := (A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + O <= MEM(Index); + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + variable Index : integer := 32; + variable Address : std_logic_vector (4 downto 0); + + begin + if (rising_edge(WCLK)) then + if (WE = '1') then + Address := (A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + MEM(Index) <= D after 100 ps; + end if; + end if; + end process VITALWriteBehavior; +end RAM32X1S_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram32x1s_1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Synchronous RAM 32-Deep by 1-Wide +-- /___/ /\ Filename : RAM32X1S_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:48 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM32X1S_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM32X1S_1 is + generic ( + INIT : bit_vector(31 downto 0) := X"00000000" + ); + + port ( + O : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + D : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM32X1S_1; + +architecture RAM32X1S_1_V of RAM32X1S_1 is + signal MEM : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT)); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, A4, MEM) + variable Index : integer := 32; + variable Address : std_logic_vector (4 downto 0); + + begin + Address := (A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + O <= MEM(Index); + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + variable Index : integer := 32; + variable Address : std_logic_vector (4 downto 0); + + begin + if (falling_edge(WCLK)) then + if (WE = '1') then + Address := (A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + MEM(Index) <= D after 100 ps; + end if; + end if; + end process VITALWriteBehavior; +end RAM32X1S_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram32x2s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Synchronous RAM 32-Deep by 2-Wide +-- /___/ /\ Filename : RAM32X2S.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:48 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM32X2S ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM32X2S is + + generic ( + INIT_00 : bit_vector(31 downto 0) := X"00000000"; + INIT_01 : bit_vector(31 downto 0) := X"00000000" + ); + + port ( + O0 : out std_ulogic; + O1 : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM32X2S; + +architecture RAM32X2S_V of RAM32X2S is + signal MEM0 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_00)); + signal MEM1 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_01)); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, A4, MEM0, MEM1) + variable Index : integer := 32; + variable Address : std_logic_vector (4 downto 0); + + begin + Address := (A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + O0 <= MEM0(Index); + O1 <= MEM1(Index); + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + variable Index : integer := 32; + variable Address : std_logic_vector (4 downto 0); + + begin + if (rising_edge(WCLK)) then + if (WE = '1') then + Address := (A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + MEM0(Index) <= D0 after 100 ps; + MEM1(Index) <= D1 after 100 ps; + end if; + end if; + end process VITALWriteBehavior; +end RAM32X2S_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram32x4s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Synchronous RAM 32-Deep by 4-Wide +-- /___/ /\ Filename : RAM32X4S.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:49 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM32X4S ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM32X4S is + + generic ( + INIT_00 : bit_vector(31 downto 0) := X"00000000"; + INIT_01 : bit_vector(31 downto 0) := X"00000000"; + INIT_02 : bit_vector(31 downto 0) := X"00000000"; + INIT_03 : bit_vector(31 downto 0) := X"00000000" + ); + + port ( + O0 : out std_ulogic; + O1 : out std_ulogic; + O2 : out std_ulogic; + O3 : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + D2 : in std_ulogic; + D3 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM32X4S; + +architecture RAM32X4S_V of RAM32X4S is + signal MEM0 : std_logic_vector( 32 downto 0 ) := ('X' & To_StdLogicVector(INIT_00) ); + signal MEM1 : std_logic_vector( 32 downto 0 ) := ('X' & To_StdLogicVector(INIT_01) ); + signal MEM2 : std_logic_vector( 32 downto 0 ) := ('X' & To_StdLogicVector(INIT_02) ); + signal MEM3 : std_logic_vector( 32 downto 0 ) := ('X' & To_StdLogicVector(INIT_03) ); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, A4, MEM0, MEM1, MEM2, MEM3) + variable Index : integer := 32; + variable Address : std_logic_vector (4 downto 0); + + begin + Address := (A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + O0 <= MEM0(Index); + O1 <= MEM1(Index); + O2 <= MEM2(Index); + O3 <= MEM3(Index); + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + variable Index : integer := 32; + variable Address : std_logic_vector (4 downto 0); + + begin + if (rising_edge(WCLK)) then + if (WE = '1') then + Address := (A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + MEM0(Index) <= D0 after 100 ps; + MEM1(Index) <= D1 after 100 ps; + MEM2(Index) <= D2 after 100 ps; + MEM3(Index) <= D3 after 100 ps; + end if; + end if; + end process VITALWriteBehavior; +end RAM32X4S_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram32x8s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Synchronous RAM 32-Deep by 8-Wide +-- /___/ /\ Filename : RAM32X8S.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:49 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM32X8S ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM32X8S is + + generic ( + INIT_00 : bit_vector(31 downto 0) := X"00000000"; + INIT_01 : bit_vector(31 downto 0) := X"00000000"; + INIT_02 : bit_vector(31 downto 0) := X"00000000"; + INIT_03 : bit_vector(31 downto 0) := X"00000000"; + INIT_04 : bit_vector(31 downto 0) := X"00000000"; + INIT_05 : bit_vector(31 downto 0) := X"00000000"; + INIT_06 : bit_vector(31 downto 0) := X"00000000"; + INIT_07 : bit_vector(31 downto 0) := X"00000000" + ); + + port ( + O : out std_logic_vector ( 7 downto 0); + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + D : in std_logic_vector ( 7 downto 0); + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM32X8S; + +architecture RAM32X8S_V of RAM32X8S is + signal MEM0 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_00)); + signal MEM1 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_01)); + signal MEM2 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_02)); + signal MEM3 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_03)); + signal MEM4 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_04)); + signal MEM5 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_05)); + signal MEM6 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_06)); + signal MEM7 : std_logic_vector(32 downto 0) := ('X' & To_StdLogicVector(INIT_07)); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, A4, MEM0, MEM1, MEM2, MEM3, MEM4, MEM5, MEM6, MEM7) + + variable Index : integer := 32; + variable Address : std_logic_vector (4 downto 0); + + begin + Address := (A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + + O(0) <= MEM0(Index); + O(1) <= MEM1(Index); + O(2) <= MEM2(Index); + O(3) <= MEM3(Index); + O(4) <= MEM4(Index); + O(5) <= MEM5(Index); + O(6) <= MEM6(Index); + O(7) <= MEM7(Index); + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + variable Index : integer := 32; + variable Address : std_logic_vector (4 downto 0); + begin + if (rising_edge(WCLK)) then + if (WE = '1') then + Address := (A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + MEM0(Index) <= D(0) after 100 ps; + MEM1(Index) <= D(1) after 100 ps; + MEM2(Index) <= D(2) after 100 ps; + MEM3(Index) <= D(3) after 100 ps; + MEM4(Index) <= D(4) after 100 ps; + MEM5(Index) <= D(5) after 100 ps; + MEM6(Index) <= D(6) after 100 ps; + MEM7(Index) <= D(7) after 100 ps; + end if; + end if; + end process VITALWriteBehavior; +end RAM32X8S_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram64x1d.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Dual Port Synchronous RAM 64-Deep by 1-Wide +-- /___/ /\ Filename : RAM64X1D.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:49 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM64X1D ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM64X1D is + generic ( + INIT : bit_vector(63 downto 0) := X"0000000000000000" + ); + + port ( + DPO : out std_ulogic; + SPO : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic; + D : in std_ulogic; + DPRA0 : in std_ulogic; + DPRA1 : in std_ulogic; + DPRA2 : in std_ulogic; + DPRA3 : in std_ulogic; + DPRA4 : in std_ulogic; + DPRA5 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM64X1D; + +architecture RAM64X1D_V of RAM64X1D is + signal MEM : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT) ); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, A4, A5, DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0, WCLK, MEM) + variable Index_SP : integer := 64; + variable Index_DP : integer := 64; + variable Raddress : std_logic_vector (5 downto 0); + variable Waddress : std_logic_vector (5 downto 0); + + begin + Waddress := (A5, A4, A3, A2, A1, A0); + Raddress := (DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0); + Index_SP := SLV_TO_INT(SLV => Waddress); + Index_DP := SLV_TO_INT(SLV => Raddress); + SPO <= MEM(Index_SP); + DPO <= MEM(Index_DP); + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + variable Index_SP : integer := 32; + variable Index_DP : integer := 32; + variable Address : std_logic_vector( 5 downto 0); + + begin + Address := (A5, A4, A3, A2, A1, A0); + Index_SP := SLV_TO_INT(SLV => Address ); + if ((WE = '1') and (wclk'event) and (wclk'last_value = '0') and (wclk = '1')) then + MEM(Index_SP) <= D after 100 ps; + end if; + end process VITALWriteBehavior; +end RAM64X1D_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram64x1d_1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Dual Port Synchronous RAM 64-Deep by 1-Wide +-- /___/ /\ Filename : RAM64X1D_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:49 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM64X1D_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM64X1D_1 is + generic ( + INIT : bit_vector(63 downto 0) := X"0000000000000000" + ); + + port ( + DPO : out std_ulogic; + SPO : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic; + D : in std_ulogic; + DPRA0 : in std_ulogic; + DPRA1 : in std_ulogic; + DPRA2 : in std_ulogic; + DPRA3 : in std_ulogic; + DPRA4 : in std_ulogic; + DPRA5 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM64X1D_1; + +architecture RAM64X1D_1_V of RAM64X1D_1 is + signal MEM : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT) ); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, A4, A5, DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0, WCLK, MEM) + variable Index_SP : integer := 64; + variable Index_DP : integer := 64; + variable Raddress : std_logic_vector (5 downto 0); + variable Waddress : std_logic_vector (5 downto 0); + + begin + Waddress := (A5, A4, A3, A2, A1, A0); + Raddress := (DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0); + Index_SP := SLV_TO_INT(SLV => Waddress); + Index_DP := SLV_TO_INT(SLV => Raddress); + SPO <= MEM(Index_SP); + DPO <= MEM(Index_DP); + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + variable Index_SP : integer := 32; + variable Index_DP : integer := 32; + variable Address : std_logic_vector( 5 downto 0); + + begin + Address := (A5, A4, A3, A2, A1, A0); + Index_SP := SLV_TO_INT(SLV => Address ); + if ((WE = '1') and (wclk'event) and (wclk'last_value = '1') and (wclk = '0')) then + MEM(Index_SP) <= D after 100 ps; + end if; + end process VITALWriteBehavior; +end RAM64X1D_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram64x1s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Synchronous RAM 64-Deep by 1-Wide +-- /___/ /\ Filename : RAM64X1S.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:49 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM64X1S ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM64X1S is + generic ( + INIT : bit_vector(63 downto 0) := X"0000000000000000" + ); + + port ( + O : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic; + D : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM64X1S; + +architecture RAM64X1S_V of RAM64X1S is + signal MEM : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT) ); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, A4, A5, MEM) + variable Index : integer := 64; + variable Address : std_logic_vector (5 downto 0); + + begin + Address := (A5, A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + O <= MEM(Index); + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + variable Index : integer := 64; + variable Address : std_logic_vector (5 downto 0); + begin + if (rising_edge(WCLK)) then + if (WE = '1') then + Address := (A5, A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + MEM(Index) <= D after 100 ps; + end if; + end if; + end process VITALWriteBehavior; +end RAM64X1S_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram64x1s_1.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Synchronous RAM 64-Deep by 1-Wide +-- /___/ /\ Filename : RAM64X1S_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:49 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM64X1S_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM64X1S_1 is + generic ( + INIT : bit_vector(63 downto 0) := X"0000000000000000" + ); + + port ( + O : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic; + D : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM64X1S_1; + +architecture RAM64X1S_1_V of RAM64X1S_1 is + signal MEM : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT) ); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, A4, A5, MEM) + variable Index : integer := 64; + variable Address : std_logic_vector (5 downto 0); + + begin + Address := (A5, A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + O <= MEM(Index); + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + variable Index : integer := 64; + variable Address : std_logic_vector (5 downto 0); + begin + if (falling_edge(WCLK)) then + if (WE = '1') then + Address := (A5, A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + MEM(Index) <= D after 100 ps; + end if; + end if; + end process VITALWriteBehavior; +end RAM64X1S_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ram64x2s.vhd,v 1.4 2004/04/08 18:46:28 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Synchronous RAM 64-Deep by 2-Wide +-- /___/ /\ Filename : RAM64X2S.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:49 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAM64X2S ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM64X2S is + generic ( + INIT_00 : bit_vector(63 downto 0) := X"0000000000000000"; + INIT_01 : bit_vector(63 downto 0) := X"0000000000000000" + ); + + port ( + O0 : out std_ulogic; + O1 : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM64X2S; + +architecture RAM64X2S_V of RAM64X2S is + signal MEM0 : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT_00) ); + signal MEM1 : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT_01) ); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, A4, A5, MEM0, MEM1) + variable Index : integer := 32; + variable Address : std_logic_vector (5 downto 0); + begin + Address := (A5, A4, A3, A2 , A1 , A0); + Index := SLV_TO_INT(SLV => Address); + O0 <= MEM0(Index); + O1 <= MEM1(Index); + end process VITALReadBehavior; + + VITALWriteBehavior : process(WCLK) + variable Index : integer := 32; + variable Address : std_logic_vector (5 downto 0); + begin + if (rising_edge(WCLK)) then + if (WE = '1') then + Address := (A5, A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Address); + MEM0(Index) <= D0 after 100 ps; + MEM1(Index) <= D1 after 100 ps; + end if; + end if; +end process VITALWriteBehavior; +end RAM64X2S_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb16_s1.vhd,v 1.7 2005/10/07 18:35:24 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +-- /___/ /\ Filename : RAMB16_S1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:49 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 09/26/05 - Fixed CR# 216846. INIT and SRVAL attributes length check and adjustment. +-- END Revision + +----- CELL RAMB16_S1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S1 is + + generic ( + INIT : bit_vector := X"0"; + SRVAL : bit_vector := X"0"; + WRITE_MODE : string := "WRITE_FIRST"; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + + port ( + DO : out STD_LOGIC_VECTOR (0 downto 0); + + ADDR : in STD_LOGIC_VECTOR (13 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (0 downto 0); + EN : in STD_ULOGIC; + SSR : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end RAMB16_S1; + +architecture RAMB16_S1_V of RAMB16_S1 is + constant length : integer := 16384; + constant width : integer := 1; + + type Two_D_array_type is array ((length - 1) downto 0) of std_logic_vector((width - 1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + + VITALBehavior : process + variable address : integer; + variable valid_addr : boolean := FALSE; + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F & INIT_3E & INIT_3D & INIT_3C & + INIT_3B & INIT_3A & INIT_39 & INIT_38 & + INIT_37 & INIT_36 & INIT_35 & INIT_34 & + INIT_33 & INIT_32 & INIT_31 & INIT_30 & + INIT_2F & INIT_2E & INIT_2D & INIT_2C & + INIT_2B & INIT_2A & INIT_29 & INIT_28 & + INIT_27 & INIT_26 & INIT_25 & INIT_24 & + INIT_23 & INIT_22 & INIT_21 & INIT_20 & + INIT_1F & INIT_1E & INIT_1D & INIT_1C & + INIT_1B & INIT_1A & INIT_19 & INIT_18 & + INIT_17 & INIT_16 & INIT_15 & INIT_14 & + INIT_13 & INIT_12 & INIT_11 & INIT_10 & + INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(length, width, mem_slv); + + variable wr_mode : integer := 0; + variable first_time : boolean := true; + + variable INIT_reg : std_logic_vector (0 downto 0) := "0"; + variable SRVAL_reg : std_logic_vector (0 downto 0) := "0"; + begin + if (first_time) then + if ((WRITE_MODE = "write_first") or (WRITE_MODE = "WRITE_FIRST")) then + wr_mode := 0; + elsif ((WRITE_MODE = "read_first") or (WRITE_MODE = "READ_FIRST")) then + wr_mode := 1; + elsif ((WRITE_MODE = "no_change") or (WRITE_MODE = "NO_CHANGE")) then + wr_mode := 2; + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Error ", + GenericName => " WRITE_MODE ", + EntityName => "/RAMB16_S1", + GenericValue => WRITE_MODE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT'length > 1) then + INIT_reg(0 downto 0) := To_StdLogicVector(INIT)(0 downto 0); + else + INIT_reg(INIT'length-1 downto 0) := To_StdLogicVector(INIT); + end if; + DO <= INIT_reg(0 downto 0); + if (SRVAL'length > 1) then + SRVAL_reg(0 downto 0) := To_StdLogicVector(SRVAL)(0 downto 0); + else + SRVAL_reg(SRVAL'length-1 downto 0) := To_StdLogicVector(SRVAL); + end if; + first_time := false; + end if; + + valid_addr := addr_is_valid(addr); + + if (valid_addr) then + address := slv_to_int(addr); + end if; + + if (rising_edge(CLK)) then + if (EN = '1') then + if (SSR = '1') then + DO <= SRVAL_reg(0 downto 0) after 100 ps; + else + if (WE = '1') then + if (wr_mode = 0) then + DO <= DI after 100 ps; + elsif (wr_mode = 1) then + DO <= mem(address) after 100 ps; + end if; + else + if (valid_addr) then + DO <= mem(address) after 100 ps; + end if; + end if; + end if; + if (WE = '1') then + if (valid_addr) then + mem(address) := DI; + end if; + end if; + end if; + end if; + wait on CLK; + end process VITALBehavior; +end RAMB16_S1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb16_s18.vhd,v 1.10 2007/07/13 20:39:25 wloo Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +-- /___/ /\ Filename : RAMB16_S18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:50 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 09/26/05 - Fixed CR# 216846. INIT and SRVAL attributes length check and adjustment. +-- 07/09/07 - Changed generic write_mode to uppercase (CR 441954). +-- End Revision + +----- CELL RAMB16_S18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S18 is + + generic ( + INIT : bit_vector := X"00000"; + SRVAL : bit_vector := X"00000"; + WRITE_MODE : string := "WRITE_FIRST"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + + ); + + port ( + DO : out std_logic_vector (15 downto 0); + DOP : out std_logic_vector (1 downto 0); + ADDR : in std_logic_vector (9 downto 0); + CLK : in std_ulogic; + DI : in std_logic_vector (15 downto 0); + DIP : in std_logic_vector (1 downto 0); + EN : in std_ulogic; + SSR : in std_ulogic; + WE : in std_ulogic + ); +end RAMB16_S18; + +architecture RAMB16_S18_V of RAMB16_S18 is + constant length : integer := 1024; + constant width : integer := 16; + + constant parity_width : integer := 2; + + type Two_D_array_type is array ((length - 1) downto 0) of std_logic_vector((width - 1) downto 0); + type Two_D_parity_array_type is array ((length - 1) downto 0) of std_logic_vector((parity_width - 1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + + function slv_to_two_D_parity_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_parity_array_type is + variable two_D_parity_array : two_D_parity_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_parity_array(i) := intermediate; + end loop; + return two_D_parity_array; + end; +begin + + VITALBehavior : process + + variable address : integer; + variable valid_addr : boolean := FALSE; + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F & INIT_3E & INIT_3D & INIT_3C & + INIT_3B & INIT_3A & INIT_39 & INIT_38 & + INIT_37 & INIT_36 & INIT_35 & INIT_34 & + INIT_33 & INIT_32 & INIT_31 & INIT_30 & + INIT_2F & INIT_2E & INIT_2D & INIT_2C & + INIT_2B & INIT_2A & INIT_29 & INIT_28 & + INIT_27 & INIT_26 & INIT_25 & INIT_24 & + INIT_23 & INIT_22 & INIT_21 & INIT_20 & + INIT_1F & INIT_1E & INIT_1D & INIT_1C & + INIT_1B & INIT_1A & INIT_19 & INIT_18 & + INIT_17 & INIT_16 & INIT_15 & INIT_14 & + INIT_13 & INIT_12 & INIT_11 & INIT_10 & + INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + + variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07 & INITP_06 & INITP_05 & INITP_04 & + INITP_03 & INITP_02 & INITP_01 & INITP_00); + variable mem : Two_D_array_type := slv_to_two_D_array(length, width, mem_slv); + variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length, parity_width, memp_slv); + + variable wr_mode : integer := 0; + variable first_time : boolean := true; + + variable INIT_reg : std_logic_vector (17 downto 0) := "000000000000000000"; + variable SRVAL_reg : std_logic_vector (17 downto 0) := "000000000000000000"; + + begin + if (first_time) then + if ((WRITE_MODE = "write_first") or (WRITE_MODE = "WRITE_FIRST")) then + wr_mode := 0; + elsif ((WRITE_MODE = "read_first") or (WRITE_MODE = "READ_FIRST")) then + wr_mode := 1; + elsif ((WRITE_MODE = "no_change") or (WRITE_MODE = "NO_CHANGE")) then + wr_mode := 2; + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Error ", + GenericName => " WRITE_MODE ", + EntityName => "/RAMB16_S18", + GenericValue => WRITE_MODE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT'length > 18) then + INIT_reg(17 downto 0) := To_StdLogicVector(INIT)(17 downto 0); + else + INIT_reg(INIT'length-1 downto 0) := To_StdLogicVector(INIT); + end if; + + DO <= INIT_reg(15 downto 0); + DOP <= INIT_reg(17 downto 16); + + if (SRVAL'length > 18) then + SRVAL_reg(17 downto 0) := To_StdLogicVector(SRVAL)(17 downto 0); + else + SRVAL_reg(SRVAL'length-1 downto 0) := To_StdLogicVector(SRVAL); + end if; + first_time := false; + end if; + + valid_addr := addr_is_valid(addr); + + if (valid_addr) then + address := slv_to_int(addr); + end if; + + if (rising_edge(CLK)) then + if (EN = '1') then + if (SSR = '1') then + DO <= SRVAL_reg(15 downto 0) after 100 ps; + DOP <= SRVAL_reg(17 downto 16) after 100 ps; + else + if (WE = '1') then + if (wr_mode = 0) then + DO <= DI after 100 ps; + DOP <= DIP after 100 ps; + elsif (wr_mode = 1) then + DO <= mem(address) after 100 ps; + DOP <= memp(address) after 100 ps; + end if; + else + if (valid_addr) then + DO <= mem(address) after 100 ps; + DOP <= memp(address) after 100 ps; + end if; + end if; + end if; + if (WE = '1') then + if (valid_addr) then + mem(address) := DI; + memp(address) := DIP; + end if; + end if; + end if; + end if; + wait on CLK; + end process VITALBehavior; +end RAMB16_S18_V; + + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S18_S18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s18_s18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S18_S18 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(9 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPA : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(9 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPB : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKA_DOPA : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOPB : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIPA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIPA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIPA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIPA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"00000"; + INIT_B : bit_vector := X"00000"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"00000"; + SRVAL_B : bit_vector := X"00000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPA : out std_logic_vector(1 downto 0); + DOPB : out std_logic_vector(1 downto 0); + + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPA : in std_logic_vector(1 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S18_S18 : entity is true; +end ramb16_s18_s18; + +architecture RAMB16_S18_S18_V of RAMB16_S18_S18 is + attribute VITAL_LEVEL0 of + RAMB16_S18_S18_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(9 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(15 downto 0) := (others => 'X'); + signal DIPA_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(9 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(15 downto 0) := (others => 'X'); + signal DIPB_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 1024; + constant length_b : integer := 1024; + constant width_a : integer := 16; + constant width_b : integer := 16; + + constant parity_width_a : integer := 2; + constant parity_width_b : integer := 2; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + + function slv_to_two_D_parity_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_parity_array_type is + variable two_D_parity_array : two_D_parity_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_parity_array(i) := intermediate; + end loop; + return two_D_parity_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 9 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 15 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + DIPA_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIPA_ipd(i), DIPA(i), tipd_DIPA(i)); + end generate DIPA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 9 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 15 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + DIPB_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i)); + end generate DIPB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA12_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA13_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA14_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA15_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIPA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIPA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB12_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB13_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB14_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB15_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA13_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA14_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA15_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB13_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB14_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB15_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + variable DOA_GlitchData2 : VitalGlitchDataType; + variable DOA_GlitchData3 : VitalGlitchDataType; + variable DOA_GlitchData4 : VitalGlitchDataType; + variable DOA_GlitchData5 : VitalGlitchDataType; + variable DOA_GlitchData6 : VitalGlitchDataType; + variable DOA_GlitchData7 : VitalGlitchDataType; + variable DOA_GlitchData8 : VitalGlitchDataType; + variable DOA_GlitchData9 : VitalGlitchDataType; + variable DOA_GlitchData10 : VitalGlitchDataType; + variable DOA_GlitchData11 : VitalGlitchDataType; + variable DOA_GlitchData12 : VitalGlitchDataType; + variable DOA_GlitchData13 : VitalGlitchDataType; + variable DOA_GlitchData14 : VitalGlitchDataType; + variable DOA_GlitchData15 : VitalGlitchDataType; + variable DOPA_GlitchData0 : VitalGlitchDataType; + variable DOPA_GlitchData1 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOB_GlitchData8 : VitalGlitchDataType; + variable DOB_GlitchData9 : VitalGlitchDataType; + variable DOB_GlitchData10 : VitalGlitchDataType; + variable DOB_GlitchData11 : VitalGlitchDataType; + variable DOB_GlitchData12 : VitalGlitchDataType; + variable DOB_GlitchData13 : VitalGlitchDataType; + variable DOB_GlitchData14 : VitalGlitchDataType; + variable DOB_GlitchData15 : VitalGlitchDataType; + variable DOPB_GlitchData0 : VitalGlitchDataType; + variable DOPB_GlitchData1 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) & + To_StdLogicVector(INITP_06) & + To_StdLogicVector(INITP_05) & + To_StdLogicVector(INITP_04) & + To_StdLogicVector(INITP_03) & + To_StdLogicVector(INITP_02) & + To_StdLogicVector(INITP_01) & + To_StdLogicVector(INITP_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOPA_OV_LSB : integer := 0; + variable DOPA_OV_MSB : integer := 1; + variable DOPB_OV_LSB : integer := 0; + variable DOPB_OV_MSB : integer := 1; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (17 downto 0) := "000000000000000000"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (17 downto 0) := "000000000000000000"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (17 downto 0) := "000000000000000000"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (17 downto 0) := "000000000000000000"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(15 downto 0) := INI_A(15 downto 0); + variable DOB_zd : std_logic_vector(15 downto 0) := INI_B(15 downto 0); + variable DOPA_zd : std_logic_vector(1 downto 0) := INI_A(17 downto 16); + variable DOPB_zd : std_logic_vector(1 downto 0) := INI_B(17 downto 16); + + variable ADDRA_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S18_S18", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 18) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(17 downto 0) := INI_A_UNBOUND(17 downto 0); + + for I in INI_A_UNBOUND'high downto 18 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 18 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S18_S18", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 18) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S18_S18", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 18) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 18) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(17 downto 0) := INI_B_UNBOUND(17 downto 0); + + for I in INI_B_UNBOUND'high downto 18 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 18 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S18_S18", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 18) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S18_S18", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 18) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 18) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(17 downto 0) := SRVA_A_UNBOUND(17 downto 0); + + for I in SRVA_A_UNBOUND'high downto 18 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 18 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S18_S18", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 18) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S18_S18", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 18) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 18) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(17 downto 0) := SRVA_B_UNBOUND(17 downto 0); + + for I in SRVA_B_UNBOUND'high downto 18 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 18 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S18_S18", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 18) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S18_S18", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 18) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(15 downto 0) := INI_A(15 downto 0); + DOB_zd(15 downto 0) := INI_B(15 downto 0); + DOPA_zd(1 downto 0) := INI_A(17 downto 16); + DOPB_zd(1 downto 0) := INI_B(17 downto 16); + DOA <= DOA_zd; + DOPA <= DOPA_zd; + DOB <= DOB_zd; + DOPB <= DOPB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S18_S18", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S18_S18", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPA0_CLKA_posedge, + TimingData => Tmkr_DIPA0_CLKA_posedge, + TestSignal => DIPA_ipd(0), + TestSignalName => "DIPA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIPA_CLKA_negedge_posedge(0), + HoldLow => thold_DIPA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIPA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA1_CLKA_posedge, + TimingData => Tmkr_DIA1_CLKA_posedge, + TestSignal => DIA_ipd(1), + TestSignalName => "DIA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(1), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(1), + HoldLow => thold_DIA_CLKA_posedge_posedge(1), + HoldHigh => thold_DIA_CLKA_negedge_posedge(1), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA2_CLKA_posedge, + TimingData => Tmkr_DIA2_CLKA_posedge, + TestSignal => DIA_ipd(2), + TestSignalName => "DIA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(2), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(2), + HoldLow => thold_DIA_CLKA_posedge_posedge(2), + HoldHigh => thold_DIA_CLKA_negedge_posedge(2), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA3_CLKA_posedge, + TimingData => Tmkr_DIA3_CLKA_posedge, + TestSignal => DIA_ipd(3), + TestSignalName => "DIA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(3), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(3), + HoldLow => thold_DIA_CLKA_posedge_posedge(3), + HoldHigh => thold_DIA_CLKA_negedge_posedge(3), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA4_CLKA_posedge, + TimingData => Tmkr_DIA4_CLKA_posedge, + TestSignal => DIA_ipd(4), + TestSignalName => "DIA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(4), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(4), + HoldLow => thold_DIA_CLKA_posedge_posedge(4), + HoldHigh => thold_DIA_CLKA_negedge_posedge(4), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA5_CLKA_posedge, + TimingData => Tmkr_DIA5_CLKA_posedge, + TestSignal => DIA_ipd(5), + TestSignalName => "DIA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(5), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(5), + HoldLow => thold_DIA_CLKA_posedge_posedge(5), + HoldHigh => thold_DIA_CLKA_negedge_posedge(5), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA6_CLKA_posedge, + TimingData => Tmkr_DIA6_CLKA_posedge, + TestSignal => DIA_ipd(6), + TestSignalName => "DIA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(6), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(6), + HoldLow => thold_DIA_CLKA_posedge_posedge(6), + HoldHigh => thold_DIA_CLKA_negedge_posedge(6), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA7_CLKA_posedge, + TimingData => Tmkr_DIA7_CLKA_posedge, + TestSignal => DIA_ipd(7), + TestSignalName => "DIA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(7), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(7), + HoldLow => thold_DIA_CLKA_posedge_posedge(7), + HoldHigh => thold_DIA_CLKA_negedge_posedge(7), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA8_CLKA_posedge, + TimingData => Tmkr_DIA8_CLKA_posedge, + TestSignal => DIA_ipd(8), + TestSignalName => "DIA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(8), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(8), + HoldLow => thold_DIA_CLKA_posedge_posedge(8), + HoldHigh => thold_DIA_CLKA_negedge_posedge(8), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA9_CLKA_posedge, + TimingData => Tmkr_DIA9_CLKA_posedge, + TestSignal => DIA_ipd(9), + TestSignalName => "DIA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(9), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(9), + HoldLow => thold_DIA_CLKA_posedge_posedge(9), + HoldHigh => thold_DIA_CLKA_negedge_posedge(9), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA10_CLKA_posedge, + TimingData => Tmkr_DIA10_CLKA_posedge, + TestSignal => DIA_ipd(10), + TestSignalName => "DIA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(10), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(10), + HoldLow => thold_DIA_CLKA_posedge_posedge(10), + HoldHigh => thold_DIA_CLKA_negedge_posedge(10), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA11_CLKA_posedge, + TimingData => Tmkr_DIA11_CLKA_posedge, + TestSignal => DIA_ipd(11), + TestSignalName => "DIA(11)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(11), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(11), + HoldLow => thold_DIA_CLKA_posedge_posedge(11), + HoldHigh => thold_DIA_CLKA_negedge_posedge(11), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA12_CLKA_posedge, + TimingData => Tmkr_DIA12_CLKA_posedge, + TestSignal => DIA_ipd(12), + TestSignalName => "DIA(12)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(12), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(12), + HoldLow => thold_DIA_CLKA_posedge_posedge(12), + HoldHigh => thold_DIA_CLKA_negedge_posedge(12), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA13_CLKA_posedge, + TimingData => Tmkr_DIA13_CLKA_posedge, + TestSignal => DIA_ipd(13), + TestSignalName => "DIA(13)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(13), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(13), + HoldLow => thold_DIA_CLKA_posedge_posedge(13), + HoldHigh => thold_DIA_CLKA_negedge_posedge(13), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA14_CLKA_posedge, + TimingData => Tmkr_DIA14_CLKA_posedge, + TestSignal => DIA_ipd(14), + TestSignalName => "DIA(14)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(14), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(14), + HoldLow => thold_DIA_CLKA_posedge_posedge(14), + HoldHigh => thold_DIA_CLKA_negedge_posedge(14), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB0_CLKB_posedge, + TimingData => Tmkr_DIPB0_CLKB_posedge, + TestSignal => DIPB_ipd(0), + TestSignalName => "DIPB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(0), + HoldLow => thold_DIPB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB7_CLKB_posedge, + TimingData => Tmkr_DIB7_CLKB_posedge, + TestSignal => DIB_ipd(7), + TestSignalName => "DIB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(7), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(7), + HoldLow => thold_DIB_CLKB_posedge_posedge(7), + HoldHigh => thold_DIB_CLKB_negedge_posedge(7), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB8_CLKB_posedge, + TimingData => Tmkr_DIB8_CLKB_posedge, + TestSignal => DIB_ipd(8), + TestSignalName => "DIB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(8), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(8), + HoldLow => thold_DIB_CLKB_posedge_posedge(8), + HoldHigh => thold_DIB_CLKB_negedge_posedge(8), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB9_CLKB_posedge, + TimingData => Tmkr_DIB9_CLKB_posedge, + TestSignal => DIB_ipd(9), + TestSignalName => "DIB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(9), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(9), + HoldLow => thold_DIB_CLKB_posedge_posedge(9), + HoldHigh => thold_DIB_CLKB_negedge_posedge(9), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB10_CLKB_posedge, + TimingData => Tmkr_DIB10_CLKB_posedge, + TestSignal => DIB_ipd(10), + TestSignalName => "DIB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(10), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(10), + HoldLow => thold_DIB_CLKB_posedge_posedge(10), + HoldHigh => thold_DIB_CLKB_negedge_posedge(10), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB11_CLKB_posedge, + TimingData => Tmkr_DIB11_CLKB_posedge, + TestSignal => DIB_ipd(11), + TestSignalName => "DIB(11)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(11), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(11), + HoldLow => thold_DIB_CLKB_posedge_posedge(11), + HoldHigh => thold_DIB_CLKB_negedge_posedge(11), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB12_CLKB_posedge, + TimingData => Tmkr_DIB12_CLKB_posedge, + TestSignal => DIB_ipd(12), + TestSignalName => "DIB(12)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(12), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(12), + HoldLow => thold_DIB_CLKB_posedge_posedge(12), + HoldHigh => thold_DIB_CLKB_negedge_posedge(12), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB13_CLKB_posedge, + TimingData => Tmkr_DIB13_CLKB_posedge, + TestSignal => DIB_ipd(13), + TestSignalName => "DIB(13)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(13), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(13), + HoldLow => thold_DIB_CLKB_posedge_posedge(13), + HoldHigh => thold_DIB_CLKB_negedge_posedge(13), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB14_CLKB_posedge, + TimingData => Tmkr_DIB14_CLKB_posedge, + TestSignal => DIB_ipd(14), + TestSignalName => "DIB(14)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(14), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(14), + HoldLow => thold_DIB_CLKB_posedge_posedge(14), + HoldHigh => thold_DIB_CLKB_negedge_posedge(14), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S18_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_DIA2_CLKA_posedge or + Tviol_DIA3_CLKA_posedge or + Tviol_DIA4_CLKA_posedge or + Tviol_DIA5_CLKA_posedge or + Tviol_DIA6_CLKA_posedge or + Tviol_DIA7_CLKA_posedge or + Tviol_DIA8_CLKA_posedge or + Tviol_DIA9_CLKA_posedge or + Tviol_DIA10_CLKA_posedge or + Tviol_DIA11_CLKA_posedge or + Tviol_DIA12_CLKA_posedge or + Tviol_DIA13_CLKA_posedge or + Tviol_DIA14_CLKA_posedge or + Tviol_DIA15_CLKA_posedge or + Tviol_DIPA0_CLKA_posedge or + Tviol_DIPA1_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIB8_CLKB_posedge or + Tviol_DIB9_CLKB_posedge or + Tviol_DIB10_CLKB_posedge or + Tviol_DIB11_CLKB_posedge or + Tviol_DIB12_CLKB_posedge or + Tviol_DIB13_CLKB_posedge or + Tviol_DIB14_CLKB_posedge or + Tviol_DIB15_CLKB_posedge or + Tviol_DIPB0_CLKB_posedge or + Tviol_DIPB1_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + addr_overlap (address_a, address_b, parity_width_a, parity_width_b, has_overlap_p, olpp_lsb, olpp_msb, dopa_ov_lsb, dopa_ov_msb, dopb_ov_lsb, dopb_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + DOPA_zd := DIPA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S18_S18", + InstanceName => ramb16_s18_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S18_S18", + InstanceName => ramb16_s18_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S18_S18", + InstanceName => ramb16_s18_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S18_S18", + InstanceName => ramb16_s18_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S18_S18", + InstanceName => ramb16_s18_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S18_S18", + InstanceName => ramb16_s18_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S18_S18", + InstanceName => ramb16_s18_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(15 downto 0); + DOPA_zd := SRVA_A(17 downto 16); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + DOPB_zd := DIPB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S18_S18", + InstanceName => ramb16_s18_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S18_S18", + InstanceName => ramb16_s18_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S18_S18", + InstanceName => ramb16_s18_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S18_S18", + InstanceName => ramb16_s18_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S18_S18", + InstanceName => ramb16_s18_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S18_S18", + InstanceName => ramb16_s18_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S18_S18", + InstanceName => ramb16_s18_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(15 downto 0); + DOPB_zd := SRVA_B(17 downto 16); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + DOA_zd(1) := ViolationA xor DOA_zd(1); + DOA_zd(2) := ViolationA xor DOA_zd(2); + DOA_zd(3) := ViolationA xor DOA_zd(3); + DOA_zd(4) := ViolationA xor DOA_zd(4); + DOA_zd(5) := ViolationA xor DOA_zd(5); + DOA_zd(6) := ViolationA xor DOA_zd(6); + DOA_zd(7) := ViolationA xor DOA_zd(7); + DOA_zd(8) := ViolationA xor DOA_zd(8); + DOA_zd(9) := ViolationA xor DOA_zd(9); + DOA_zd(10) := ViolationA xor DOA_zd(10); + DOA_zd(11) := ViolationA xor DOA_zd(11); + DOA_zd(12) := ViolationA xor DOA_zd(12); + DOA_zd(13) := ViolationA xor DOA_zd(13); + DOA_zd(14) := ViolationA xor DOA_zd(14); + DOA_zd(15) := ViolationA xor DOA_zd(15); + DOPA_zd(0) := ViolationA xor DOPA_zd(0); + DOPA_zd(1) := ViolationA xor DOPA_zd(1); + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOB_zd(8) := ViolationB xor DOB_zd(8); + DOB_zd(9) := ViolationB xor DOB_zd(9); + DOB_zd(10) := ViolationB xor DOB_zd(10); + DOB_zd(11) := ViolationB xor DOB_zd(11); + DOB_zd(12) := ViolationB xor DOB_zd(12); + DOB_zd(13) := ViolationB xor DOB_zd(13); + DOB_zd(14) := ViolationB xor DOB_zd(14); + DOB_zd(15) := ViolationB xor DOB_zd(15); + DOPB_zd(0) := ViolationB xor DOPB_zd(0); + DOPB_zd(1) := ViolationB xor DOPB_zd(1); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(2), + GlitchData => DOA_GlitchData2, + OutSignalName => "DOA(2)", + OutTemp => DOA_zd(2), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(3), + GlitchData => DOA_GlitchData3, + OutSignalName => "DOA(3)", + OutTemp => DOA_zd(3), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(4), + GlitchData => DOA_GlitchData4, + OutSignalName => "DOA(4)", + OutTemp => DOA_zd(4), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(5), + GlitchData => DOA_GlitchData5, + OutSignalName => "DOA(5)", + OutTemp => DOA_zd(5), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(6), + GlitchData => DOA_GlitchData6, + OutSignalName => "DOA(6)", + OutTemp => DOA_zd(6), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(7), + GlitchData => DOA_GlitchData7, + OutSignalName => "DOA(7)", + OutTemp => DOA_zd(7), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(8), + GlitchData => DOA_GlitchData8, + OutSignalName => "DOA(8)", + OutTemp => DOA_zd(8), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(9), + GlitchData => DOA_GlitchData9, + OutSignalName => "DOA(9)", + OutTemp => DOA_zd(9), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(10), + GlitchData => DOA_GlitchData10, + OutSignalName => "DOA(10)", + OutTemp => DOA_zd(10), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(11), + GlitchData => DOA_GlitchData11, + OutSignalName => "DOA(11)", + OutTemp => DOA_zd(11), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(12), + GlitchData => DOA_GlitchData12, + OutSignalName => "DOA(12)", + OutTemp => DOA_zd(12), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(13), + GlitchData => DOA_GlitchData13, + OutSignalName => "DOA(13)", + OutTemp => DOA_zd(13), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(14), + GlitchData => DOA_GlitchData14, + OutSignalName => "DOA(14)", + OutTemp => DOA_zd(14), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(15), + GlitchData => DOA_GlitchData15, + OutSignalName => "DOA(15)", + OutTemp => DOA_zd(15), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPA(0), + GlitchData => DOPA_GlitchData0, + OutSignalName => "DOPA(0)", + OutTemp => DOPA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPA(1), + GlitchData => DOPA_GlitchData1, + OutSignalName => "DOPA(1)", + OutTemp => DOPA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(8), + GlitchData => DOB_GlitchData8, + OutSignalName => "DOB(8)", + OutTemp => DOB_zd(8), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(9), + GlitchData => DOB_GlitchData9, + OutSignalName => "DOB(9)", + OutTemp => DOB_zd(9), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(10), + GlitchData => DOB_GlitchData10, + OutSignalName => "DOB(10)", + OutTemp => DOB_zd(10), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(11), + GlitchData => DOB_GlitchData11, + OutSignalName => "DOB(11)", + OutTemp => DOB_zd(11), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(12), + GlitchData => DOB_GlitchData12, + OutSignalName => "DOB(12)", + OutTemp => DOB_zd(12), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(13), + GlitchData => DOB_GlitchData13, + OutSignalName => "DOB(13)", + OutTemp => DOB_zd(13), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(14), + GlitchData => DOB_GlitchData14, + OutSignalName => "DOB(14)", + OutTemp => DOB_zd(14), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(15), + GlitchData => DOB_GlitchData15, + OutSignalName => "DOB(15)", + OutTemp => DOB_zd(15), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(0), + GlitchData => DOPB_GlitchData0, + OutSignalName => "DOPB(0)", + OutTemp => DOPB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(1), + GlitchData => DOPB_GlitchData1, + OutSignalName => "DOPB(1)", + OutTemp => DOPB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPA_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S18_S18_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S18_S36.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s18_s36 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S18_S36 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(9 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPA : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(8 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPB : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKA_DOPA : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(31 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOPB : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIPA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIPA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIPA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIPA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"00000"; + INIT_B : bit_vector := X"000000000"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"00000"; + SRVAL_B : bit_vector := X"000000000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(1 downto 0); + DOPB : out std_logic_vector(3 downto 0); + + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(1 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S18_S36 : entity is true; +end ramb16_s18_s36; + +architecture RAMB16_S18_S36_V of RAMB16_S18_S36 is + attribute VITAL_LEVEL0 of + RAMB16_S18_S36_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(9 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(15 downto 0) := (others => 'X'); + signal DIPA_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(8 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(31 downto 0) := (others => 'X'); + signal DIPB_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 1024; + constant length_b : integer := 512; + constant width_a : integer := 16; + constant width_b : integer := 32; + + constant parity_width_a : integer := 2; + constant parity_width_b : integer := 4; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + + function slv_to_two_D_parity_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_parity_array_type is + variable two_D_parity_array : two_D_parity_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_parity_array(i) := intermediate; + end loop; + return two_D_parity_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 9 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 15 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + DIPA_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIPA_ipd(i), DIPA(i), tipd_DIPA(i)); + end generate DIPA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 8 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 31 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + DIPB_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i)); + end generate DIPB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA12_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA13_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA14_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA15_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIPA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIPA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB12_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB13_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB14_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB15_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB16_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB17_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB18_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB19_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB20_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB21_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB22_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB23_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB24_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB25_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB26_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB27_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB28_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB29_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB30_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB31_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA13_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA14_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA15_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB13_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB14_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB15_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB16_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB17_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB18_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB19_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB20_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB21_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB22_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB23_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB24_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB25_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB26_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB27_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB28_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB29_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB30_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB31_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + variable DOA_GlitchData2 : VitalGlitchDataType; + variable DOA_GlitchData3 : VitalGlitchDataType; + variable DOA_GlitchData4 : VitalGlitchDataType; + variable DOA_GlitchData5 : VitalGlitchDataType; + variable DOA_GlitchData6 : VitalGlitchDataType; + variable DOA_GlitchData7 : VitalGlitchDataType; + variable DOA_GlitchData8 : VitalGlitchDataType; + variable DOA_GlitchData9 : VitalGlitchDataType; + variable DOA_GlitchData10 : VitalGlitchDataType; + variable DOA_GlitchData11 : VitalGlitchDataType; + variable DOA_GlitchData12 : VitalGlitchDataType; + variable DOA_GlitchData13 : VitalGlitchDataType; + variable DOA_GlitchData14 : VitalGlitchDataType; + variable DOA_GlitchData15 : VitalGlitchDataType; + variable DOPA_GlitchData0 : VitalGlitchDataType; + variable DOPA_GlitchData1 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOB_GlitchData8 : VitalGlitchDataType; + variable DOB_GlitchData9 : VitalGlitchDataType; + variable DOB_GlitchData10 : VitalGlitchDataType; + variable DOB_GlitchData11 : VitalGlitchDataType; + variable DOB_GlitchData12 : VitalGlitchDataType; + variable DOB_GlitchData13 : VitalGlitchDataType; + variable DOB_GlitchData14 : VitalGlitchDataType; + variable DOB_GlitchData15 : VitalGlitchDataType; + variable DOB_GlitchData16 : VitalGlitchDataType; + variable DOB_GlitchData17 : VitalGlitchDataType; + variable DOB_GlitchData18 : VitalGlitchDataType; + variable DOB_GlitchData19 : VitalGlitchDataType; + variable DOB_GlitchData20 : VitalGlitchDataType; + variable DOB_GlitchData21 : VitalGlitchDataType; + variable DOB_GlitchData22 : VitalGlitchDataType; + variable DOB_GlitchData23 : VitalGlitchDataType; + variable DOB_GlitchData24 : VitalGlitchDataType; + variable DOB_GlitchData25 : VitalGlitchDataType; + variable DOB_GlitchData26 : VitalGlitchDataType; + variable DOB_GlitchData27 : VitalGlitchDataType; + variable DOB_GlitchData28 : VitalGlitchDataType; + variable DOB_GlitchData29 : VitalGlitchDataType; + variable DOB_GlitchData30 : VitalGlitchDataType; + variable DOB_GlitchData31 : VitalGlitchDataType; + variable DOPB_GlitchData0 : VitalGlitchDataType; + variable DOPB_GlitchData1 : VitalGlitchDataType; + variable DOPB_GlitchData2 : VitalGlitchDataType; + variable DOPB_GlitchData3 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) & + To_StdLogicVector(INITP_06) & + To_StdLogicVector(INITP_05) & + To_StdLogicVector(INITP_04) & + To_StdLogicVector(INITP_03) & + To_StdLogicVector(INITP_02) & + To_StdLogicVector(INITP_01) & + To_StdLogicVector(INITP_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOPA_OV_LSB : integer := 0; + variable DOPA_OV_MSB : integer := 1; + variable DOPB_OV_LSB : integer := 0; + variable DOPB_OV_MSB : integer := 3; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (17 downto 0) := "000000000000000000"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (35 downto 0) := "000000000000000000000000000000000000"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (17 downto 0) := "000000000000000000"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (35 downto 0) := "000000000000000000000000000000000000"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(15 downto 0) := INI_A(15 downto 0); + variable DOB_zd : std_logic_vector(31 downto 0) := INI_B(31 downto 0); + variable DOPA_zd : std_logic_vector(1 downto 0) := INI_A(17 downto 16); + variable DOPB_zd : std_logic_vector(3 downto 0) := INI_B(35 downto 32); + + variable ADDRA_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S18_S36", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 18) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(17 downto 0) := INI_A_UNBOUND(17 downto 0); + + for I in INI_A_UNBOUND'high downto 18 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 18 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S18_S36", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 18) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S18_S36", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 18) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 36) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(35 downto 0) := INI_B_UNBOUND(35 downto 0); + + for I in INI_B_UNBOUND'high downto 36 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 36 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S18_S36", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S18_S36", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 18) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(17 downto 0) := SRVA_A_UNBOUND(17 downto 0); + + for I in SRVA_A_UNBOUND'high downto 18 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 18 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S18_S36", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 18) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S18_S36", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 18) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 36) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(35 downto 0) := SRVA_B_UNBOUND(35 downto 0); + + for I in SRVA_B_UNBOUND'high downto 36 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 36 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S18_S36", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S18_S36", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(15 downto 0) := INI_A(15 downto 0); + DOB_zd(31 downto 0) := INI_B(31 downto 0); + DOPA_zd(1 downto 0) := INI_A(17 downto 16); + DOPB_zd(3 downto 0) := INI_B(35 downto 32); + DOA <= DOA_zd; + DOPA <= DOPA_zd; + DOB <= DOB_zd; + DOPB <= DOPB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S18_S36", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S18_S36", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPA0_CLKA_posedge, + TimingData => Tmkr_DIPA0_CLKA_posedge, + TestSignal => DIPA_ipd(0), + TestSignalName => "DIPA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIPA_CLKA_negedge_posedge(0), + HoldLow => thold_DIPA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIPA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA1_CLKA_posedge, + TimingData => Tmkr_DIA1_CLKA_posedge, + TestSignal => DIA_ipd(1), + TestSignalName => "DIA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(1), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(1), + HoldLow => thold_DIA_CLKA_posedge_posedge(1), + HoldHigh => thold_DIA_CLKA_negedge_posedge(1), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA2_CLKA_posedge, + TimingData => Tmkr_DIA2_CLKA_posedge, + TestSignal => DIA_ipd(2), + TestSignalName => "DIA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(2), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(2), + HoldLow => thold_DIA_CLKA_posedge_posedge(2), + HoldHigh => thold_DIA_CLKA_negedge_posedge(2), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA3_CLKA_posedge, + TimingData => Tmkr_DIA3_CLKA_posedge, + TestSignal => DIA_ipd(3), + TestSignalName => "DIA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(3), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(3), + HoldLow => thold_DIA_CLKA_posedge_posedge(3), + HoldHigh => thold_DIA_CLKA_negedge_posedge(3), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA4_CLKA_posedge, + TimingData => Tmkr_DIA4_CLKA_posedge, + TestSignal => DIA_ipd(4), + TestSignalName => "DIA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(4), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(4), + HoldLow => thold_DIA_CLKA_posedge_posedge(4), + HoldHigh => thold_DIA_CLKA_negedge_posedge(4), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA5_CLKA_posedge, + TimingData => Tmkr_DIA5_CLKA_posedge, + TestSignal => DIA_ipd(5), + TestSignalName => "DIA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(5), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(5), + HoldLow => thold_DIA_CLKA_posedge_posedge(5), + HoldHigh => thold_DIA_CLKA_negedge_posedge(5), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA6_CLKA_posedge, + TimingData => Tmkr_DIA6_CLKA_posedge, + TestSignal => DIA_ipd(6), + TestSignalName => "DIA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(6), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(6), + HoldLow => thold_DIA_CLKA_posedge_posedge(6), + HoldHigh => thold_DIA_CLKA_negedge_posedge(6), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA7_CLKA_posedge, + TimingData => Tmkr_DIA7_CLKA_posedge, + TestSignal => DIA_ipd(7), + TestSignalName => "DIA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(7), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(7), + HoldLow => thold_DIA_CLKA_posedge_posedge(7), + HoldHigh => thold_DIA_CLKA_negedge_posedge(7), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA8_CLKA_posedge, + TimingData => Tmkr_DIA8_CLKA_posedge, + TestSignal => DIA_ipd(8), + TestSignalName => "DIA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(8), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(8), + HoldLow => thold_DIA_CLKA_posedge_posedge(8), + HoldHigh => thold_DIA_CLKA_negedge_posedge(8), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA9_CLKA_posedge, + TimingData => Tmkr_DIA9_CLKA_posedge, + TestSignal => DIA_ipd(9), + TestSignalName => "DIA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(9), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(9), + HoldLow => thold_DIA_CLKA_posedge_posedge(9), + HoldHigh => thold_DIA_CLKA_negedge_posedge(9), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA10_CLKA_posedge, + TimingData => Tmkr_DIA10_CLKA_posedge, + TestSignal => DIA_ipd(10), + TestSignalName => "DIA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(10), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(10), + HoldLow => thold_DIA_CLKA_posedge_posedge(10), + HoldHigh => thold_DIA_CLKA_negedge_posedge(10), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA11_CLKA_posedge, + TimingData => Tmkr_DIA11_CLKA_posedge, + TestSignal => DIA_ipd(11), + TestSignalName => "DIA(11)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(11), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(11), + HoldLow => thold_DIA_CLKA_posedge_posedge(11), + HoldHigh => thold_DIA_CLKA_negedge_posedge(11), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA12_CLKA_posedge, + TimingData => Tmkr_DIA12_CLKA_posedge, + TestSignal => DIA_ipd(12), + TestSignalName => "DIA(12)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(12), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(12), + HoldLow => thold_DIA_CLKA_posedge_posedge(12), + HoldHigh => thold_DIA_CLKA_negedge_posedge(12), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA13_CLKA_posedge, + TimingData => Tmkr_DIA13_CLKA_posedge, + TestSignal => DIA_ipd(13), + TestSignalName => "DIA(13)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(13), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(13), + HoldLow => thold_DIA_CLKA_posedge_posedge(13), + HoldHigh => thold_DIA_CLKA_negedge_posedge(13), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA14_CLKA_posedge, + TimingData => Tmkr_DIA14_CLKA_posedge, + TestSignal => DIA_ipd(14), + TestSignalName => "DIA(14)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(14), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(14), + HoldLow => thold_DIA_CLKA_posedge_posedge(14), + HoldHigh => thold_DIA_CLKA_negedge_posedge(14), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB0_CLKB_posedge, + TimingData => Tmkr_DIPB0_CLKB_posedge, + TestSignal => DIPB_ipd(0), + TestSignalName => "DIPB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(0), + HoldLow => thold_DIPB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB1_CLKB_posedge, + TimingData => Tmkr_DIPB1_CLKB_posedge, + TestSignal => DIPB_ipd(1), + TestSignalName => "DIPB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(1), + HoldLow => thold_DIPB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB2_CLKB_posedge, + TimingData => Tmkr_DIPB2_CLKB_posedge, + TestSignal => DIPB_ipd(2), + TestSignalName => "DIPB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(2), + HoldLow => thold_DIPB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB7_CLKB_posedge, + TimingData => Tmkr_DIB7_CLKB_posedge, + TestSignal => DIB_ipd(7), + TestSignalName => "DIB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(7), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(7), + HoldLow => thold_DIB_CLKB_posedge_posedge(7), + HoldHigh => thold_DIB_CLKB_negedge_posedge(7), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB8_CLKB_posedge, + TimingData => Tmkr_DIB8_CLKB_posedge, + TestSignal => DIB_ipd(8), + TestSignalName => "DIB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(8), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(8), + HoldLow => thold_DIB_CLKB_posedge_posedge(8), + HoldHigh => thold_DIB_CLKB_negedge_posedge(8), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB9_CLKB_posedge, + TimingData => Tmkr_DIB9_CLKB_posedge, + TestSignal => DIB_ipd(9), + TestSignalName => "DIB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(9), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(9), + HoldLow => thold_DIB_CLKB_posedge_posedge(9), + HoldHigh => thold_DIB_CLKB_negedge_posedge(9), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB10_CLKB_posedge, + TimingData => Tmkr_DIB10_CLKB_posedge, + TestSignal => DIB_ipd(10), + TestSignalName => "DIB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(10), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(10), + HoldLow => thold_DIB_CLKB_posedge_posedge(10), + HoldHigh => thold_DIB_CLKB_negedge_posedge(10), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB11_CLKB_posedge, + TimingData => Tmkr_DIB11_CLKB_posedge, + TestSignal => DIB_ipd(11), + TestSignalName => "DIB(11)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(11), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(11), + HoldLow => thold_DIB_CLKB_posedge_posedge(11), + HoldHigh => thold_DIB_CLKB_negedge_posedge(11), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB12_CLKB_posedge, + TimingData => Tmkr_DIB12_CLKB_posedge, + TestSignal => DIB_ipd(12), + TestSignalName => "DIB(12)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(12), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(12), + HoldLow => thold_DIB_CLKB_posedge_posedge(12), + HoldHigh => thold_DIB_CLKB_negedge_posedge(12), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB13_CLKB_posedge, + TimingData => Tmkr_DIB13_CLKB_posedge, + TestSignal => DIB_ipd(13), + TestSignalName => "DIB(13)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(13), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(13), + HoldLow => thold_DIB_CLKB_posedge_posedge(13), + HoldHigh => thold_DIB_CLKB_negedge_posedge(13), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB14_CLKB_posedge, + TimingData => Tmkr_DIB14_CLKB_posedge, + TestSignal => DIB_ipd(14), + TestSignalName => "DIB(14)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(14), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(14), + HoldLow => thold_DIB_CLKB_posedge_posedge(14), + HoldHigh => thold_DIB_CLKB_negedge_posedge(14), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB15_CLKB_posedge, + TimingData => Tmkr_DIB15_CLKB_posedge, + TestSignal => DIB_ipd(15), + TestSignalName => "DIB(15)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(15), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(15), + HoldLow => thold_DIB_CLKB_posedge_posedge(15), + HoldHigh => thold_DIB_CLKB_negedge_posedge(15), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB16_CLKB_posedge, + TimingData => Tmkr_DIB16_CLKB_posedge, + TestSignal => DIB_ipd(16), + TestSignalName => "DIB(16)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(16), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(16), + HoldLow => thold_DIB_CLKB_posedge_posedge(16), + HoldHigh => thold_DIB_CLKB_negedge_posedge(16), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB17_CLKB_posedge, + TimingData => Tmkr_DIB17_CLKB_posedge, + TestSignal => DIB_ipd(17), + TestSignalName => "DIB(17)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(17), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(17), + HoldLow => thold_DIB_CLKB_posedge_posedge(17), + HoldHigh => thold_DIB_CLKB_negedge_posedge(17), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB18_CLKB_posedge, + TimingData => Tmkr_DIB18_CLKB_posedge, + TestSignal => DIB_ipd(18), + TestSignalName => "DIB(18)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(18), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(18), + HoldLow => thold_DIB_CLKB_posedge_posedge(18), + HoldHigh => thold_DIB_CLKB_negedge_posedge(18), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB19_CLKB_posedge, + TimingData => Tmkr_DIB19_CLKB_posedge, + TestSignal => DIB_ipd(19), + TestSignalName => "DIB(19)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(19), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(19), + HoldLow => thold_DIB_CLKB_posedge_posedge(19), + HoldHigh => thold_DIB_CLKB_negedge_posedge(19), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB20_CLKB_posedge, + TimingData => Tmkr_DIB20_CLKB_posedge, + TestSignal => DIB_ipd(20), + TestSignalName => "DIB(20)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(20), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(20), + HoldLow => thold_DIB_CLKB_posedge_posedge(20), + HoldHigh => thold_DIB_CLKB_negedge_posedge(20), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB21_CLKB_posedge, + TimingData => Tmkr_DIB21_CLKB_posedge, + TestSignal => DIB_ipd(21), + TestSignalName => "DIB(21)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(21), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(21), + HoldLow => thold_DIB_CLKB_posedge_posedge(21), + HoldHigh => thold_DIB_CLKB_negedge_posedge(21), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB22_CLKB_posedge, + TimingData => Tmkr_DIB22_CLKB_posedge, + TestSignal => DIB_ipd(22), + TestSignalName => "DIB(22)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(22), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(22), + HoldLow => thold_DIB_CLKB_posedge_posedge(22), + HoldHigh => thold_DIB_CLKB_negedge_posedge(22), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB23_CLKB_posedge, + TimingData => Tmkr_DIB23_CLKB_posedge, + TestSignal => DIB_ipd(23), + TestSignalName => "DIB(23)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(23), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(23), + HoldLow => thold_DIB_CLKB_posedge_posedge(23), + HoldHigh => thold_DIB_CLKB_negedge_posedge(23), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB24_CLKB_posedge, + TimingData => Tmkr_DIB24_CLKB_posedge, + TestSignal => DIB_ipd(24), + TestSignalName => "DIB(24)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(24), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(24), + HoldLow => thold_DIB_CLKB_posedge_posedge(24), + HoldHigh => thold_DIB_CLKB_negedge_posedge(24), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB25_CLKB_posedge, + TimingData => Tmkr_DIB25_CLKB_posedge, + TestSignal => DIB_ipd(25), + TestSignalName => "DIB(25)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(25), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(25), + HoldLow => thold_DIB_CLKB_posedge_posedge(25), + HoldHigh => thold_DIB_CLKB_negedge_posedge(25), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB26_CLKB_posedge, + TimingData => Tmkr_DIB26_CLKB_posedge, + TestSignal => DIB_ipd(26), + TestSignalName => "DIB(26)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(26), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(26), + HoldLow => thold_DIB_CLKB_posedge_posedge(26), + HoldHigh => thold_DIB_CLKB_negedge_posedge(26), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB27_CLKB_posedge, + TimingData => Tmkr_DIB27_CLKB_posedge, + TestSignal => DIB_ipd(27), + TestSignalName => "DIB(27)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(27), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(27), + HoldLow => thold_DIB_CLKB_posedge_posedge(27), + HoldHigh => thold_DIB_CLKB_negedge_posedge(27), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB28_CLKB_posedge, + TimingData => Tmkr_DIB28_CLKB_posedge, + TestSignal => DIB_ipd(28), + TestSignalName => "DIB(28)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(28), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(28), + HoldLow => thold_DIB_CLKB_posedge_posedge(28), + HoldHigh => thold_DIB_CLKB_negedge_posedge(28), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB29_CLKB_posedge, + TimingData => Tmkr_DIB29_CLKB_posedge, + TestSignal => DIB_ipd(29), + TestSignalName => "DIB(29)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(29), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(29), + HoldLow => thold_DIB_CLKB_posedge_posedge(29), + HoldHigh => thold_DIB_CLKB_negedge_posedge(29), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB30_CLKB_posedge, + TimingData => Tmkr_DIB30_CLKB_posedge, + TestSignal => DIB_ipd(30), + TestSignalName => "DIB(30)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(30), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(30), + HoldLow => thold_DIB_CLKB_posedge_posedge(30), + HoldHigh => thold_DIB_CLKB_negedge_posedge(30), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S18_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_DIA2_CLKA_posedge or + Tviol_DIA3_CLKA_posedge or + Tviol_DIA4_CLKA_posedge or + Tviol_DIA5_CLKA_posedge or + Tviol_DIA6_CLKA_posedge or + Tviol_DIA7_CLKA_posedge or + Tviol_DIA8_CLKA_posedge or + Tviol_DIA9_CLKA_posedge or + Tviol_DIA10_CLKA_posedge or + Tviol_DIA11_CLKA_posedge or + Tviol_DIA12_CLKA_posedge or + Tviol_DIA13_CLKA_posedge or + Tviol_DIA14_CLKA_posedge or + Tviol_DIA15_CLKA_posedge or + Tviol_DIPA0_CLKA_posedge or + Tviol_DIPA1_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIB8_CLKB_posedge or + Tviol_DIB9_CLKB_posedge or + Tviol_DIB10_CLKB_posedge or + Tviol_DIB11_CLKB_posedge or + Tviol_DIB12_CLKB_posedge or + Tviol_DIB13_CLKB_posedge or + Tviol_DIB14_CLKB_posedge or + Tviol_DIB15_CLKB_posedge or + Tviol_DIB16_CLKB_posedge or + Tviol_DIB17_CLKB_posedge or + Tviol_DIB18_CLKB_posedge or + Tviol_DIB19_CLKB_posedge or + Tviol_DIB20_CLKB_posedge or + Tviol_DIB21_CLKB_posedge or + Tviol_DIB22_CLKB_posedge or + Tviol_DIB23_CLKB_posedge or + Tviol_DIB24_CLKB_posedge or + Tviol_DIB25_CLKB_posedge or + Tviol_DIB26_CLKB_posedge or + Tviol_DIB27_CLKB_posedge or + Tviol_DIB28_CLKB_posedge or + Tviol_DIB29_CLKB_posedge or + Tviol_DIB30_CLKB_posedge or + Tviol_DIB31_CLKB_posedge or + Tviol_DIPB0_CLKB_posedge or + Tviol_DIPB1_CLKB_posedge or + Tviol_DIPB2_CLKB_posedge or + Tviol_DIPB3_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + addr_overlap (address_a, address_b, parity_width_a, parity_width_b, has_overlap_p, olpp_lsb, olpp_msb, dopa_ov_lsb, dopa_ov_msb, dopb_ov_lsb, dopb_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S18_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + DOPA_zd := DIPA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S18_S36", + InstanceName => ramb16_s18_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S18_S36", + InstanceName => ramb16_s18_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S18_S36", + InstanceName => ramb16_s18_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S18_S36", + InstanceName => ramb16_s18_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S18_S36", + InstanceName => ramb16_s18_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S18_S36", + InstanceName => ramb16_s18_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S18_S36", + InstanceName => ramb16_s18_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(15 downto 0); + DOPA_zd := SRVA_A(17 downto 16); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + DOPB_zd := DIPB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S18_S36", + InstanceName => ramb16_s18_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S18_S36", + InstanceName => ramb16_s18_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S18_S36", + InstanceName => ramb16_s18_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S18_S36", + InstanceName => ramb16_s18_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S18_S36", + InstanceName => ramb16_s18_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S18_S36", + InstanceName => ramb16_s18_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S18_S36", + InstanceName => ramb16_s18_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(31 downto 0); + DOPB_zd := SRVA_B(35 downto 32); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + DOA_zd(1) := ViolationA xor DOA_zd(1); + DOA_zd(2) := ViolationA xor DOA_zd(2); + DOA_zd(3) := ViolationA xor DOA_zd(3); + DOA_zd(4) := ViolationA xor DOA_zd(4); + DOA_zd(5) := ViolationA xor DOA_zd(5); + DOA_zd(6) := ViolationA xor DOA_zd(6); + DOA_zd(7) := ViolationA xor DOA_zd(7); + DOA_zd(8) := ViolationA xor DOA_zd(8); + DOA_zd(9) := ViolationA xor DOA_zd(9); + DOA_zd(10) := ViolationA xor DOA_zd(10); + DOA_zd(11) := ViolationA xor DOA_zd(11); + DOA_zd(12) := ViolationA xor DOA_zd(12); + DOA_zd(13) := ViolationA xor DOA_zd(13); + DOA_zd(14) := ViolationA xor DOA_zd(14); + DOA_zd(15) := ViolationA xor DOA_zd(15); + DOPA_zd(0) := ViolationA xor DOPA_zd(0); + DOPA_zd(1) := ViolationA xor DOPA_zd(1); + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOB_zd(8) := ViolationB xor DOB_zd(8); + DOB_zd(9) := ViolationB xor DOB_zd(9); + DOB_zd(10) := ViolationB xor DOB_zd(10); + DOB_zd(11) := ViolationB xor DOB_zd(11); + DOB_zd(12) := ViolationB xor DOB_zd(12); + DOB_zd(13) := ViolationB xor DOB_zd(13); + DOB_zd(14) := ViolationB xor DOB_zd(14); + DOB_zd(15) := ViolationB xor DOB_zd(15); + DOB_zd(16) := ViolationB xor DOB_zd(16); + DOB_zd(17) := ViolationB xor DOB_zd(17); + DOB_zd(18) := ViolationB xor DOB_zd(18); + DOB_zd(19) := ViolationB xor DOB_zd(19); + DOB_zd(20) := ViolationB xor DOB_zd(20); + DOB_zd(21) := ViolationB xor DOB_zd(21); + DOB_zd(22) := ViolationB xor DOB_zd(22); + DOB_zd(23) := ViolationB xor DOB_zd(23); + DOB_zd(24) := ViolationB xor DOB_zd(24); + DOB_zd(25) := ViolationB xor DOB_zd(25); + DOB_zd(26) := ViolationB xor DOB_zd(26); + DOB_zd(27) := ViolationB xor DOB_zd(27); + DOB_zd(28) := ViolationB xor DOB_zd(28); + DOB_zd(29) := ViolationB xor DOB_zd(29); + DOB_zd(30) := ViolationB xor DOB_zd(30); + DOB_zd(31) := ViolationB xor DOB_zd(31); + DOPB_zd(0) := ViolationB xor DOPB_zd(0); + DOPB_zd(1) := ViolationB xor DOPB_zd(1); + DOPB_zd(2) := ViolationB xor DOPB_zd(2); + DOPB_zd(3) := ViolationB xor DOPB_zd(3); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(2), + GlitchData => DOA_GlitchData2, + OutSignalName => "DOA(2)", + OutTemp => DOA_zd(2), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(3), + GlitchData => DOA_GlitchData3, + OutSignalName => "DOA(3)", + OutTemp => DOA_zd(3), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(4), + GlitchData => DOA_GlitchData4, + OutSignalName => "DOA(4)", + OutTemp => DOA_zd(4), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(5), + GlitchData => DOA_GlitchData5, + OutSignalName => "DOA(5)", + OutTemp => DOA_zd(5), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(6), + GlitchData => DOA_GlitchData6, + OutSignalName => "DOA(6)", + OutTemp => DOA_zd(6), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(7), + GlitchData => DOA_GlitchData7, + OutSignalName => "DOA(7)", + OutTemp => DOA_zd(7), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(8), + GlitchData => DOA_GlitchData8, + OutSignalName => "DOA(8)", + OutTemp => DOA_zd(8), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(9), + GlitchData => DOA_GlitchData9, + OutSignalName => "DOA(9)", + OutTemp => DOA_zd(9), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(10), + GlitchData => DOA_GlitchData10, + OutSignalName => "DOA(10)", + OutTemp => DOA_zd(10), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(11), + GlitchData => DOA_GlitchData11, + OutSignalName => "DOA(11)", + OutTemp => DOA_zd(11), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(12), + GlitchData => DOA_GlitchData12, + OutSignalName => "DOA(12)", + OutTemp => DOA_zd(12), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(13), + GlitchData => DOA_GlitchData13, + OutSignalName => "DOA(13)", + OutTemp => DOA_zd(13), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(14), + GlitchData => DOA_GlitchData14, + OutSignalName => "DOA(14)", + OutTemp => DOA_zd(14), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(15), + GlitchData => DOA_GlitchData15, + OutSignalName => "DOA(15)", + OutTemp => DOA_zd(15), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPA(0), + GlitchData => DOPA_GlitchData0, + OutSignalName => "DOPA(0)", + OutTemp => DOPA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPA(1), + GlitchData => DOPA_GlitchData1, + OutSignalName => "DOPA(1)", + OutTemp => DOPA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(8), + GlitchData => DOB_GlitchData8, + OutSignalName => "DOB(8)", + OutTemp => DOB_zd(8), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(9), + GlitchData => DOB_GlitchData9, + OutSignalName => "DOB(9)", + OutTemp => DOB_zd(9), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(10), + GlitchData => DOB_GlitchData10, + OutSignalName => "DOB(10)", + OutTemp => DOB_zd(10), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(11), + GlitchData => DOB_GlitchData11, + OutSignalName => "DOB(11)", + OutTemp => DOB_zd(11), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(12), + GlitchData => DOB_GlitchData12, + OutSignalName => "DOB(12)", + OutTemp => DOB_zd(12), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(13), + GlitchData => DOB_GlitchData13, + OutSignalName => "DOB(13)", + OutTemp => DOB_zd(13), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(14), + GlitchData => DOB_GlitchData14, + OutSignalName => "DOB(14)", + OutTemp => DOB_zd(14), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(15), + GlitchData => DOB_GlitchData15, + OutSignalName => "DOB(15)", + OutTemp => DOB_zd(15), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(16), + GlitchData => DOB_GlitchData16, + OutSignalName => "DOB(16)", + OutTemp => DOB_zd(16), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(16), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(17), + GlitchData => DOB_GlitchData17, + OutSignalName => "DOB(17)", + OutTemp => DOB_zd(17), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(17), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(18), + GlitchData => DOB_GlitchData18, + OutSignalName => "DOB(18)", + OutTemp => DOB_zd(18), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(18), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(19), + GlitchData => DOB_GlitchData19, + OutSignalName => "DOB(19)", + OutTemp => DOB_zd(19), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(19), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(20), + GlitchData => DOB_GlitchData20, + OutSignalName => "DOB(20)", + OutTemp => DOB_zd(20), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(20), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(21), + GlitchData => DOB_GlitchData21, + OutSignalName => "DOB(21)", + OutTemp => DOB_zd(21), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(21), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(22), + GlitchData => DOB_GlitchData22, + OutSignalName => "DOB(22)", + OutTemp => DOB_zd(22), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(22), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(23), + GlitchData => DOB_GlitchData23, + OutSignalName => "DOB(23)", + OutTemp => DOB_zd(23), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(23), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(24), + GlitchData => DOB_GlitchData24, + OutSignalName => "DOB(24)", + OutTemp => DOB_zd(24), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(24), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(25), + GlitchData => DOB_GlitchData25, + OutSignalName => "DOB(25)", + OutTemp => DOB_zd(25), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(25), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(26), + GlitchData => DOB_GlitchData26, + OutSignalName => "DOB(26)", + OutTemp => DOB_zd(26), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(26), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(27), + GlitchData => DOB_GlitchData27, + OutSignalName => "DOB(27)", + OutTemp => DOB_zd(27), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(27), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(28), + GlitchData => DOB_GlitchData28, + OutSignalName => "DOB(28)", + OutTemp => DOB_zd(28), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(28), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(29), + GlitchData => DOB_GlitchData29, + OutSignalName => "DOB(29)", + OutTemp => DOB_zd(29), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(29), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(30), + GlitchData => DOB_GlitchData30, + OutSignalName => "DOB(30)", + OutTemp => DOB_zd(30), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(30), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(31), + GlitchData => DOB_GlitchData31, + OutSignalName => "DOB(31)", + OutTemp => DOB_zd(31), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(31), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(0), + GlitchData => DOPB_GlitchData0, + OutSignalName => "DOPB(0)", + OutTemp => DOPB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(1), + GlitchData => DOPB_GlitchData1, + OutSignalName => "DOPB(1)", + OutTemp => DOPB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(2), + GlitchData => DOPB_GlitchData2, + OutSignalName => "DOPB(2)", + OutTemp => DOPB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(3), + GlitchData => DOPB_GlitchData3, + OutSignalName => "DOPB(3)", + OutTemp => DOPB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPA_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S18_S36_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S1_S1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s1_s1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S1_S1 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(13 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(13 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"0"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"0"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(0 downto 0); + + ADDRA : in std_logic_vector(13 downto 0); + ADDRB : in std_logic_vector(13 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S1_S1 : entity is true; +end ramb16_s1_s1; + +architecture RAMB16_S1_S1_V of RAMB16_S1_S1 is + attribute VITAL_LEVEL0 of + RAMB16_S1_S1_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(13 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(13 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 16384; + constant length_b : integer := 16384; + constant width_a : integer := 1; + constant width_b : integer := 1; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 13 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 13 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA13_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB12_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB13_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA13_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB13_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (0 downto 0) := "0"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (0 downto 0) := "0"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (0 downto 0) := "0"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (0 downto 0) := "0"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(0 downto 0) := INI_A(0 downto 0); + variable DOB_zd : std_logic_vector(0 downto 0) := INI_B(0 downto 0); + + variable ADDRA_ipd_sampled : std_logic_vector(13 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(13 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S1_S1", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 1) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(0 downto 0) := INI_A_UNBOUND(0 downto 0); + + for I in INI_A_UNBOUND'high downto 1 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 1 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S1_S1", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 1) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S1_S1", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 1) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 1) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(0 downto 0) := INI_B_UNBOUND(0 downto 0); + + for I in INI_B_UNBOUND'high downto 1 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 1 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S1_S1", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 1) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S1_S1", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 1) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 1) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(0 downto 0) := SRVA_A_UNBOUND(0 downto 0); + + for I in SRVA_A_UNBOUND'high downto 1 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 1 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S1_S1", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 1) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S1_S1", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 1) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 1) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(0 downto 0) := SRVA_B_UNBOUND(0 downto 0); + + for I in SRVA_B_UNBOUND'high downto 1 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 1 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S1_S1", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 1) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S1_S1", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 1) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(0 downto 0) := INI_A(0 downto 0); + DOB_zd(0 downto 0) := INI_B(0 downto 0); + DOA <= DOA_zd; + DOB <= DOB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S1_S1", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S1_S1", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA11_CLKA_posedge, + TimingData => Tmkr_ADDRA11_CLKA_posedge, + TestSignal => ADDRA_ipd(11), + TestSignalName => "ADDRA(11)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(11), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(11), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(11), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(11), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA12_CLKA_posedge, + TimingData => Tmkr_ADDRA12_CLKA_posedge, + TestSignal => ADDRA_ipd(12), + TestSignalName => "ADDRA(12)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(12), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(12), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(12), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(12), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB9_CLKB_posedge, + TimingData => Tmkr_ADDRB9_CLKB_posedge, + TestSignal => ADDRB_ipd(9), + TestSignalName => "ADDRB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(9), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(9), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(9), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(9), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB10_CLKB_posedge, + TimingData => Tmkr_ADDRB10_CLKB_posedge, + TestSignal => ADDRB_ipd(10), + TestSignalName => "ADDRB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(10), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(10), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(10), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(10), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB11_CLKB_posedge, + TimingData => Tmkr_ADDRB11_CLKB_posedge, + TestSignal => ADDRB_ipd(11), + TestSignalName => "ADDRB(11)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(11), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(11), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(11), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(11), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB12_CLKB_posedge, + TimingData => Tmkr_ADDRB12_CLKB_posedge, + TestSignal => ADDRB_ipd(12), + TestSignalName => "ADDRB(12)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(12), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(12), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(12), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(12), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_ADDRA12_CLKA_posedge or + Tviol_ADDRA13_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_ADDRB10_CLKB_posedge or + Tviol_ADDRB11_CLKB_posedge or + Tviol_ADDRB12_CLKB_posedge or + Tviol_ADDRB13_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S1", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S1", + InstanceName => ramb16_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S1", + InstanceName => ramb16_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S1", + InstanceName => ramb16_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S1", + InstanceName => ramb16_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S1", + InstanceName => ramb16_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S1", + InstanceName => ramb16_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S1", + InstanceName => ramb16_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(0 downto 0); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S1", + InstanceName => ramb16_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S1", + InstanceName => ramb16_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S1", + InstanceName => ramb16_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S1", + InstanceName => ramb16_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S1", + InstanceName => ramb16_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S1", + InstanceName => ramb16_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S1", + InstanceName => ramb16_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(0 downto 0); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + end if; + + DOB_zd(0) := ViolationB xor DOB_zd(0); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S1_S1_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S1_S18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s1_s18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S1_S18 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(13 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(9 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPB : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOPB : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"00000"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"00000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPB : out std_logic_vector(1 downto 0); + + ADDRA : in std_logic_vector(13 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S1_S18 : entity is true; +end ramb16_s1_s18; + +architecture RAMB16_S1_S18_V of RAMB16_S1_S18 is + attribute VITAL_LEVEL0 of + RAMB16_S1_S18_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(13 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(9 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(15 downto 0) := (others => 'X'); + signal DIPB_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 16384; + constant length_b : integer := 1024; + constant width_a : integer := 1; + constant width_b : integer := 16; + + constant parity_width_b : integer := 2; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + + function slv_to_two_D_parity_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_parity_array_type is + variable two_D_parity_array : two_D_parity_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_parity_array(i) := intermediate; + end loop; + return two_D_parity_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 13 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 9 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 15 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + DIPB_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i)); + end generate DIPB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA13_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB12_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB13_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB14_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB15_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA13_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB13_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB14_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB15_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOB_GlitchData8 : VitalGlitchDataType; + variable DOB_GlitchData9 : VitalGlitchDataType; + variable DOB_GlitchData10 : VitalGlitchDataType; + variable DOB_GlitchData11 : VitalGlitchDataType; + variable DOB_GlitchData12 : VitalGlitchDataType; + variable DOB_GlitchData13 : VitalGlitchDataType; + variable DOB_GlitchData14 : VitalGlitchDataType; + variable DOB_GlitchData15 : VitalGlitchDataType; + variable DOPB_GlitchData0 : VitalGlitchDataType; + variable DOPB_GlitchData1 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) & + To_StdLogicVector(INITP_06) & + To_StdLogicVector(INITP_05) & + To_StdLogicVector(INITP_04) & + To_StdLogicVector(INITP_03) & + To_StdLogicVector(INITP_02) & + To_StdLogicVector(INITP_01) & + To_StdLogicVector(INITP_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOPB_OV_LSB : integer := 0; + variable DOPB_OV_MSB : integer := 1; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (0 downto 0) := "0"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (17 downto 0) := "000000000000000000"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (0 downto 0) := "0"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (17 downto 0) := "000000000000000000"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(0 downto 0) := INI_A(0 downto 0); + variable DOB_zd : std_logic_vector(15 downto 0) := INI_B(15 downto 0); + variable DOPB_zd : std_logic_vector(1 downto 0) := INI_B(17 downto 16); + + variable ADDRA_ipd_sampled : std_logic_vector(13 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S1_S18", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 1) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(0 downto 0) := INI_A_UNBOUND(0 downto 0); + + for I in INI_A_UNBOUND'high downto 1 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 1 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S1_S18", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 1) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S1_S18", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 1) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 18) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(17 downto 0) := INI_B_UNBOUND(17 downto 0); + + for I in INI_B_UNBOUND'high downto 18 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 18 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S1_S18", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 18) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S1_S18", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 18) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 1) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(0 downto 0) := SRVA_A_UNBOUND(0 downto 0); + + for I in SRVA_A_UNBOUND'high downto 1 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 1 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S1_S18", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 1) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S1_S18", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 1) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 18) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(17 downto 0) := SRVA_B_UNBOUND(17 downto 0); + + for I in SRVA_B_UNBOUND'high downto 18 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 18 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S1_S18", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 18) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S1_S18", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 18) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(0 downto 0) := INI_A(0 downto 0); + DOB_zd(15 downto 0) := INI_B(15 downto 0); + DOPB_zd(1 downto 0) := INI_B(17 downto 16); + DOA <= DOA_zd; + DOB <= DOB_zd; + DOPB <= DOPB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S1_S18", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S1_S18", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA11_CLKA_posedge, + TimingData => Tmkr_ADDRA11_CLKA_posedge, + TestSignal => ADDRA_ipd(11), + TestSignalName => "ADDRA(11)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(11), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(11), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(11), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(11), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA12_CLKA_posedge, + TimingData => Tmkr_ADDRA12_CLKA_posedge, + TestSignal => ADDRA_ipd(12), + TestSignalName => "ADDRA(12)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(12), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(12), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(12), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(12), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB0_CLKB_posedge, + TimingData => Tmkr_DIPB0_CLKB_posedge, + TestSignal => DIPB_ipd(0), + TestSignalName => "DIPB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(0), + HoldLow => thold_DIPB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB7_CLKB_posedge, + TimingData => Tmkr_DIB7_CLKB_posedge, + TestSignal => DIB_ipd(7), + TestSignalName => "DIB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(7), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(7), + HoldLow => thold_DIB_CLKB_posedge_posedge(7), + HoldHigh => thold_DIB_CLKB_negedge_posedge(7), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB8_CLKB_posedge, + TimingData => Tmkr_DIB8_CLKB_posedge, + TestSignal => DIB_ipd(8), + TestSignalName => "DIB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(8), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(8), + HoldLow => thold_DIB_CLKB_posedge_posedge(8), + HoldHigh => thold_DIB_CLKB_negedge_posedge(8), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB9_CLKB_posedge, + TimingData => Tmkr_DIB9_CLKB_posedge, + TestSignal => DIB_ipd(9), + TestSignalName => "DIB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(9), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(9), + HoldLow => thold_DIB_CLKB_posedge_posedge(9), + HoldHigh => thold_DIB_CLKB_negedge_posedge(9), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB10_CLKB_posedge, + TimingData => Tmkr_DIB10_CLKB_posedge, + TestSignal => DIB_ipd(10), + TestSignalName => "DIB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(10), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(10), + HoldLow => thold_DIB_CLKB_posedge_posedge(10), + HoldHigh => thold_DIB_CLKB_negedge_posedge(10), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB11_CLKB_posedge, + TimingData => Tmkr_DIB11_CLKB_posedge, + TestSignal => DIB_ipd(11), + TestSignalName => "DIB(11)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(11), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(11), + HoldLow => thold_DIB_CLKB_posedge_posedge(11), + HoldHigh => thold_DIB_CLKB_negedge_posedge(11), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB12_CLKB_posedge, + TimingData => Tmkr_DIB12_CLKB_posedge, + TestSignal => DIB_ipd(12), + TestSignalName => "DIB(12)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(12), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(12), + HoldLow => thold_DIB_CLKB_posedge_posedge(12), + HoldHigh => thold_DIB_CLKB_negedge_posedge(12), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB13_CLKB_posedge, + TimingData => Tmkr_DIB13_CLKB_posedge, + TestSignal => DIB_ipd(13), + TestSignalName => "DIB(13)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(13), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(13), + HoldLow => thold_DIB_CLKB_posedge_posedge(13), + HoldHigh => thold_DIB_CLKB_negedge_posedge(13), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB14_CLKB_posedge, + TimingData => Tmkr_DIB14_CLKB_posedge, + TestSignal => DIB_ipd(14), + TestSignalName => "DIB(14)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(14), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(14), + HoldLow => thold_DIB_CLKB_posedge_posedge(14), + HoldHigh => thold_DIB_CLKB_negedge_posedge(14), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S1_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_ADDRA12_CLKA_posedge or + Tviol_ADDRA13_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIB8_CLKB_posedge or + Tviol_DIB9_CLKB_posedge or + Tviol_DIB10_CLKB_posedge or + Tviol_DIB11_CLKB_posedge or + Tviol_DIB12_CLKB_posedge or + Tviol_DIB13_CLKB_posedge or + Tviol_DIB14_CLKB_posedge or + Tviol_DIB15_CLKB_posedge or + Tviol_DIPB0_CLKB_posedge or + Tviol_DIPB1_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S18", + InstanceName => ramb16_s1_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S18", + InstanceName => ramb16_s1_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S18", + InstanceName => ramb16_s1_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S18", + InstanceName => ramb16_s1_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S18", + InstanceName => ramb16_s1_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S18", + InstanceName => ramb16_s1_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S18", + InstanceName => ramb16_s1_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(0 downto 0); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + DOPB_zd := DIPB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S18", + InstanceName => ramb16_s1_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S18", + InstanceName => ramb16_s1_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S18", + InstanceName => ramb16_s1_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S18", + InstanceName => ramb16_s1_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S18", + InstanceName => ramb16_s1_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S18", + InstanceName => ramb16_s1_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S18", + InstanceName => ramb16_s1_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(15 downto 0); + DOPB_zd := SRVA_B(17 downto 16); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOB_zd(8) := ViolationB xor DOB_zd(8); + DOB_zd(9) := ViolationB xor DOB_zd(9); + DOB_zd(10) := ViolationB xor DOB_zd(10); + DOB_zd(11) := ViolationB xor DOB_zd(11); + DOB_zd(12) := ViolationB xor DOB_zd(12); + DOB_zd(13) := ViolationB xor DOB_zd(13); + DOB_zd(14) := ViolationB xor DOB_zd(14); + DOB_zd(15) := ViolationB xor DOB_zd(15); + DOPB_zd(0) := ViolationB xor DOPB_zd(0); + DOPB_zd(1) := ViolationB xor DOPB_zd(1); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(8), + GlitchData => DOB_GlitchData8, + OutSignalName => "DOB(8)", + OutTemp => DOB_zd(8), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(9), + GlitchData => DOB_GlitchData9, + OutSignalName => "DOB(9)", + OutTemp => DOB_zd(9), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(10), + GlitchData => DOB_GlitchData10, + OutSignalName => "DOB(10)", + OutTemp => DOB_zd(10), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(11), + GlitchData => DOB_GlitchData11, + OutSignalName => "DOB(11)", + OutTemp => DOB_zd(11), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(12), + GlitchData => DOB_GlitchData12, + OutSignalName => "DOB(12)", + OutTemp => DOB_zd(12), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(13), + GlitchData => DOB_GlitchData13, + OutSignalName => "DOB(13)", + OutTemp => DOB_zd(13), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(14), + GlitchData => DOB_GlitchData14, + OutSignalName => "DOB(14)", + OutTemp => DOB_zd(14), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(15), + GlitchData => DOB_GlitchData15, + OutSignalName => "DOB(15)", + OutTemp => DOB_zd(15), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(0), + GlitchData => DOPB_GlitchData0, + OutSignalName => "DOPB(0)", + OutTemp => DOPB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(1), + GlitchData => DOPB_GlitchData1, + OutSignalName => "DOPB(1)", + OutTemp => DOPB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S1_S18_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S1_S2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s1_s2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S1_S2 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(13 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(12 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"0"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"0"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(1 downto 0); + + ADDRA : in std_logic_vector(13 downto 0); + ADDRB : in std_logic_vector(12 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S1_S2 : entity is true; +end ramb16_s1_s2; + +architecture RAMB16_S1_S2_V of RAMB16_S1_S2 is + attribute VITAL_LEVEL0 of + RAMB16_S1_S2_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(13 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(12 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 16384; + constant length_b : integer := 8192; + constant width_a : integer := 1; + constant width_b : integer := 2; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 13 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 12 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA13_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB12_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA13_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (0 downto 0) := "0"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (1 downto 0) := "00"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (0 downto 0) := "0"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (1 downto 0) := "00"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(0 downto 0) := INI_A(0 downto 0); + variable DOB_zd : std_logic_vector(1 downto 0) := INI_B(1 downto 0); + + variable ADDRA_ipd_sampled : std_logic_vector(13 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(12 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S1_S2", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 1) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(0 downto 0) := INI_A_UNBOUND(0 downto 0); + + for I in INI_A_UNBOUND'high downto 1 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 1 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S1_S2", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 1) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S1_S2", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 1) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 2) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(1 downto 0) := INI_B_UNBOUND(1 downto 0); + + for I in INI_B_UNBOUND'high downto 2 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 2 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S1_S2", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 2) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S1_S2", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 2) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 1) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(0 downto 0) := SRVA_A_UNBOUND(0 downto 0); + + for I in SRVA_A_UNBOUND'high downto 1 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 1 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S1_S2", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 1) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S1_S2", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 1) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 2) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(1 downto 0) := SRVA_B_UNBOUND(1 downto 0); + + for I in SRVA_B_UNBOUND'high downto 2 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 2 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S1_S2", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 2) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S1_S2", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 2) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(0 downto 0) := INI_A(0 downto 0); + DOB_zd(1 downto 0) := INI_B(1 downto 0); + DOA <= DOA_zd; + DOB <= DOB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S1_S2", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S1_S2", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA11_CLKA_posedge, + TimingData => Tmkr_ADDRA11_CLKA_posedge, + TestSignal => ADDRA_ipd(11), + TestSignalName => "ADDRA(11)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(11), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(11), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(11), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(11), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA12_CLKA_posedge, + TimingData => Tmkr_ADDRA12_CLKA_posedge, + TestSignal => ADDRA_ipd(12), + TestSignalName => "ADDRA(12)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(12), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(12), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(12), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(12), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB9_CLKB_posedge, + TimingData => Tmkr_ADDRB9_CLKB_posedge, + TestSignal => ADDRB_ipd(9), + TestSignalName => "ADDRB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(9), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(9), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(9), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(9), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB10_CLKB_posedge, + TimingData => Tmkr_ADDRB10_CLKB_posedge, + TestSignal => ADDRB_ipd(10), + TestSignalName => "ADDRB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(10), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(10), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(10), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(10), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB11_CLKB_posedge, + TimingData => Tmkr_ADDRB11_CLKB_posedge, + TestSignal => ADDRB_ipd(11), + TestSignalName => "ADDRB(11)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(11), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(11), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(11), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(11), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_ADDRA12_CLKA_posedge or + Tviol_ADDRA13_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_ADDRB10_CLKB_posedge or + Tviol_ADDRB11_CLKB_posedge or + Tviol_ADDRB12_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S2", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S2", + InstanceName => ramb16_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S2", + InstanceName => ramb16_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S2", + InstanceName => ramb16_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S2", + InstanceName => ramb16_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S2", + InstanceName => ramb16_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S2", + InstanceName => ramb16_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S2", + InstanceName => ramb16_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(0 downto 0); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S2", + InstanceName => ramb16_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S2", + InstanceName => ramb16_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S2", + InstanceName => ramb16_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S2", + InstanceName => ramb16_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S2", + InstanceName => ramb16_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S2", + InstanceName => ramb16_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S2", + InstanceName => ramb16_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(1 downto 0); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + end if; + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S1_S2_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S1_S36.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s1_s36 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S1_S36 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(13 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(8 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPB : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(31 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOPB : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"000000000"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"000000000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPB : out std_logic_vector(3 downto 0); + + ADDRA : in std_logic_vector(13 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S1_S36 : entity is true; +end ramb16_s1_s36; + +architecture RAMB16_S1_S36_V of RAMB16_S1_S36 is + attribute VITAL_LEVEL0 of + RAMB16_S1_S36_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(13 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(8 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(31 downto 0) := (others => 'X'); + signal DIPB_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 16384; + constant length_b : integer := 512; + constant width_a : integer := 1; + constant width_b : integer := 32; + + constant parity_width_b : integer := 4; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + + function slv_to_two_D_parity_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_parity_array_type is + variable two_D_parity_array : two_D_parity_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_parity_array(i) := intermediate; + end loop; + return two_D_parity_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 13 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 8 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 31 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + DIPB_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i)); + end generate DIPB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA13_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB12_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB13_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB14_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB15_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB16_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB17_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB18_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB19_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB20_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB21_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB22_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB23_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB24_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB25_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB26_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB27_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB28_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB29_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB30_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB31_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA13_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB13_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB14_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB15_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB16_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB17_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB18_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB19_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB20_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB21_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB22_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB23_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB24_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB25_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB26_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB27_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB28_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB29_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB30_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB31_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOB_GlitchData8 : VitalGlitchDataType; + variable DOB_GlitchData9 : VitalGlitchDataType; + variable DOB_GlitchData10 : VitalGlitchDataType; + variable DOB_GlitchData11 : VitalGlitchDataType; + variable DOB_GlitchData12 : VitalGlitchDataType; + variable DOB_GlitchData13 : VitalGlitchDataType; + variable DOB_GlitchData14 : VitalGlitchDataType; + variable DOB_GlitchData15 : VitalGlitchDataType; + variable DOB_GlitchData16 : VitalGlitchDataType; + variable DOB_GlitchData17 : VitalGlitchDataType; + variable DOB_GlitchData18 : VitalGlitchDataType; + variable DOB_GlitchData19 : VitalGlitchDataType; + variable DOB_GlitchData20 : VitalGlitchDataType; + variable DOB_GlitchData21 : VitalGlitchDataType; + variable DOB_GlitchData22 : VitalGlitchDataType; + variable DOB_GlitchData23 : VitalGlitchDataType; + variable DOB_GlitchData24 : VitalGlitchDataType; + variable DOB_GlitchData25 : VitalGlitchDataType; + variable DOB_GlitchData26 : VitalGlitchDataType; + variable DOB_GlitchData27 : VitalGlitchDataType; + variable DOB_GlitchData28 : VitalGlitchDataType; + variable DOB_GlitchData29 : VitalGlitchDataType; + variable DOB_GlitchData30 : VitalGlitchDataType; + variable DOB_GlitchData31 : VitalGlitchDataType; + variable DOPB_GlitchData0 : VitalGlitchDataType; + variable DOPB_GlitchData1 : VitalGlitchDataType; + variable DOPB_GlitchData2 : VitalGlitchDataType; + variable DOPB_GlitchData3 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) & + To_StdLogicVector(INITP_06) & + To_StdLogicVector(INITP_05) & + To_StdLogicVector(INITP_04) & + To_StdLogicVector(INITP_03) & + To_StdLogicVector(INITP_02) & + To_StdLogicVector(INITP_01) & + To_StdLogicVector(INITP_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOPB_OV_LSB : integer := 0; + variable DOPB_OV_MSB : integer := 3; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (0 downto 0) := "0"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (35 downto 0) := "000000000000000000000000000000000000"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (0 downto 0) := "0"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (35 downto 0) := "000000000000000000000000000000000000"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(0 downto 0) := INI_A(0 downto 0); + variable DOB_zd : std_logic_vector(31 downto 0) := INI_B(31 downto 0); + variable DOPB_zd : std_logic_vector(3 downto 0) := INI_B(35 downto 32); + + variable ADDRA_ipd_sampled : std_logic_vector(13 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S1_S36", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 1) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(0 downto 0) := INI_A_UNBOUND(0 downto 0); + + for I in INI_A_UNBOUND'high downto 1 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 1 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S1_S36", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 1) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S1_S36", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 1) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 36) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(35 downto 0) := INI_B_UNBOUND(35 downto 0); + + for I in INI_B_UNBOUND'high downto 36 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 36 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S1_S36", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S1_S36", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 1) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(0 downto 0) := SRVA_A_UNBOUND(0 downto 0); + + for I in SRVA_A_UNBOUND'high downto 1 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 1 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S1_S36", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 1) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S1_S36", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 1) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 36) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(35 downto 0) := SRVA_B_UNBOUND(35 downto 0); + + for I in SRVA_B_UNBOUND'high downto 36 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 36 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S1_S36", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S1_S36", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(0 downto 0) := INI_A(0 downto 0); + DOB_zd(31 downto 0) := INI_B(31 downto 0); + DOPB_zd(3 downto 0) := INI_B(35 downto 32); + DOA <= DOA_zd; + DOB <= DOB_zd; + DOPB <= DOPB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S1_S36", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S1_S36", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA11_CLKA_posedge, + TimingData => Tmkr_ADDRA11_CLKA_posedge, + TestSignal => ADDRA_ipd(11), + TestSignalName => "ADDRA(11)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(11), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(11), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(11), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(11), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA12_CLKA_posedge, + TimingData => Tmkr_ADDRA12_CLKA_posedge, + TestSignal => ADDRA_ipd(12), + TestSignalName => "ADDRA(12)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(12), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(12), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(12), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(12), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB0_CLKB_posedge, + TimingData => Tmkr_DIPB0_CLKB_posedge, + TestSignal => DIPB_ipd(0), + TestSignalName => "DIPB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(0), + HoldLow => thold_DIPB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB1_CLKB_posedge, + TimingData => Tmkr_DIPB1_CLKB_posedge, + TestSignal => DIPB_ipd(1), + TestSignalName => "DIPB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(1), + HoldLow => thold_DIPB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB2_CLKB_posedge, + TimingData => Tmkr_DIPB2_CLKB_posedge, + TestSignal => DIPB_ipd(2), + TestSignalName => "DIPB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(2), + HoldLow => thold_DIPB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB7_CLKB_posedge, + TimingData => Tmkr_DIB7_CLKB_posedge, + TestSignal => DIB_ipd(7), + TestSignalName => "DIB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(7), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(7), + HoldLow => thold_DIB_CLKB_posedge_posedge(7), + HoldHigh => thold_DIB_CLKB_negedge_posedge(7), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB8_CLKB_posedge, + TimingData => Tmkr_DIB8_CLKB_posedge, + TestSignal => DIB_ipd(8), + TestSignalName => "DIB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(8), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(8), + HoldLow => thold_DIB_CLKB_posedge_posedge(8), + HoldHigh => thold_DIB_CLKB_negedge_posedge(8), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB9_CLKB_posedge, + TimingData => Tmkr_DIB9_CLKB_posedge, + TestSignal => DIB_ipd(9), + TestSignalName => "DIB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(9), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(9), + HoldLow => thold_DIB_CLKB_posedge_posedge(9), + HoldHigh => thold_DIB_CLKB_negedge_posedge(9), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB10_CLKB_posedge, + TimingData => Tmkr_DIB10_CLKB_posedge, + TestSignal => DIB_ipd(10), + TestSignalName => "DIB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(10), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(10), + HoldLow => thold_DIB_CLKB_posedge_posedge(10), + HoldHigh => thold_DIB_CLKB_negedge_posedge(10), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB11_CLKB_posedge, + TimingData => Tmkr_DIB11_CLKB_posedge, + TestSignal => DIB_ipd(11), + TestSignalName => "DIB(11)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(11), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(11), + HoldLow => thold_DIB_CLKB_posedge_posedge(11), + HoldHigh => thold_DIB_CLKB_negedge_posedge(11), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB12_CLKB_posedge, + TimingData => Tmkr_DIB12_CLKB_posedge, + TestSignal => DIB_ipd(12), + TestSignalName => "DIB(12)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(12), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(12), + HoldLow => thold_DIB_CLKB_posedge_posedge(12), + HoldHigh => thold_DIB_CLKB_negedge_posedge(12), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB13_CLKB_posedge, + TimingData => Tmkr_DIB13_CLKB_posedge, + TestSignal => DIB_ipd(13), + TestSignalName => "DIB(13)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(13), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(13), + HoldLow => thold_DIB_CLKB_posedge_posedge(13), + HoldHigh => thold_DIB_CLKB_negedge_posedge(13), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB14_CLKB_posedge, + TimingData => Tmkr_DIB14_CLKB_posedge, + TestSignal => DIB_ipd(14), + TestSignalName => "DIB(14)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(14), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(14), + HoldLow => thold_DIB_CLKB_posedge_posedge(14), + HoldHigh => thold_DIB_CLKB_negedge_posedge(14), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB15_CLKB_posedge, + TimingData => Tmkr_DIB15_CLKB_posedge, + TestSignal => DIB_ipd(15), + TestSignalName => "DIB(15)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(15), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(15), + HoldLow => thold_DIB_CLKB_posedge_posedge(15), + HoldHigh => thold_DIB_CLKB_negedge_posedge(15), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB16_CLKB_posedge, + TimingData => Tmkr_DIB16_CLKB_posedge, + TestSignal => DIB_ipd(16), + TestSignalName => "DIB(16)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(16), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(16), + HoldLow => thold_DIB_CLKB_posedge_posedge(16), + HoldHigh => thold_DIB_CLKB_negedge_posedge(16), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB17_CLKB_posedge, + TimingData => Tmkr_DIB17_CLKB_posedge, + TestSignal => DIB_ipd(17), + TestSignalName => "DIB(17)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(17), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(17), + HoldLow => thold_DIB_CLKB_posedge_posedge(17), + HoldHigh => thold_DIB_CLKB_negedge_posedge(17), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB18_CLKB_posedge, + TimingData => Tmkr_DIB18_CLKB_posedge, + TestSignal => DIB_ipd(18), + TestSignalName => "DIB(18)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(18), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(18), + HoldLow => thold_DIB_CLKB_posedge_posedge(18), + HoldHigh => thold_DIB_CLKB_negedge_posedge(18), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB19_CLKB_posedge, + TimingData => Tmkr_DIB19_CLKB_posedge, + TestSignal => DIB_ipd(19), + TestSignalName => "DIB(19)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(19), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(19), + HoldLow => thold_DIB_CLKB_posedge_posedge(19), + HoldHigh => thold_DIB_CLKB_negedge_posedge(19), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB20_CLKB_posedge, + TimingData => Tmkr_DIB20_CLKB_posedge, + TestSignal => DIB_ipd(20), + TestSignalName => "DIB(20)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(20), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(20), + HoldLow => thold_DIB_CLKB_posedge_posedge(20), + HoldHigh => thold_DIB_CLKB_negedge_posedge(20), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB21_CLKB_posedge, + TimingData => Tmkr_DIB21_CLKB_posedge, + TestSignal => DIB_ipd(21), + TestSignalName => "DIB(21)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(21), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(21), + HoldLow => thold_DIB_CLKB_posedge_posedge(21), + HoldHigh => thold_DIB_CLKB_negedge_posedge(21), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB22_CLKB_posedge, + TimingData => Tmkr_DIB22_CLKB_posedge, + TestSignal => DIB_ipd(22), + TestSignalName => "DIB(22)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(22), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(22), + HoldLow => thold_DIB_CLKB_posedge_posedge(22), + HoldHigh => thold_DIB_CLKB_negedge_posedge(22), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB23_CLKB_posedge, + TimingData => Tmkr_DIB23_CLKB_posedge, + TestSignal => DIB_ipd(23), + TestSignalName => "DIB(23)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(23), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(23), + HoldLow => thold_DIB_CLKB_posedge_posedge(23), + HoldHigh => thold_DIB_CLKB_negedge_posedge(23), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB24_CLKB_posedge, + TimingData => Tmkr_DIB24_CLKB_posedge, + TestSignal => DIB_ipd(24), + TestSignalName => "DIB(24)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(24), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(24), + HoldLow => thold_DIB_CLKB_posedge_posedge(24), + HoldHigh => thold_DIB_CLKB_negedge_posedge(24), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB25_CLKB_posedge, + TimingData => Tmkr_DIB25_CLKB_posedge, + TestSignal => DIB_ipd(25), + TestSignalName => "DIB(25)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(25), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(25), + HoldLow => thold_DIB_CLKB_posedge_posedge(25), + HoldHigh => thold_DIB_CLKB_negedge_posedge(25), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB26_CLKB_posedge, + TimingData => Tmkr_DIB26_CLKB_posedge, + TestSignal => DIB_ipd(26), + TestSignalName => "DIB(26)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(26), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(26), + HoldLow => thold_DIB_CLKB_posedge_posedge(26), + HoldHigh => thold_DIB_CLKB_negedge_posedge(26), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB27_CLKB_posedge, + TimingData => Tmkr_DIB27_CLKB_posedge, + TestSignal => DIB_ipd(27), + TestSignalName => "DIB(27)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(27), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(27), + HoldLow => thold_DIB_CLKB_posedge_posedge(27), + HoldHigh => thold_DIB_CLKB_negedge_posedge(27), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB28_CLKB_posedge, + TimingData => Tmkr_DIB28_CLKB_posedge, + TestSignal => DIB_ipd(28), + TestSignalName => "DIB(28)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(28), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(28), + HoldLow => thold_DIB_CLKB_posedge_posedge(28), + HoldHigh => thold_DIB_CLKB_negedge_posedge(28), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB29_CLKB_posedge, + TimingData => Tmkr_DIB29_CLKB_posedge, + TestSignal => DIB_ipd(29), + TestSignalName => "DIB(29)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(29), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(29), + HoldLow => thold_DIB_CLKB_posedge_posedge(29), + HoldHigh => thold_DIB_CLKB_negedge_posedge(29), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB30_CLKB_posedge, + TimingData => Tmkr_DIB30_CLKB_posedge, + TestSignal => DIB_ipd(30), + TestSignalName => "DIB(30)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(30), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(30), + HoldLow => thold_DIB_CLKB_posedge_posedge(30), + HoldHigh => thold_DIB_CLKB_negedge_posedge(30), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S1_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_ADDRA12_CLKA_posedge or + Tviol_ADDRA13_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIB8_CLKB_posedge or + Tviol_DIB9_CLKB_posedge or + Tviol_DIB10_CLKB_posedge or + Tviol_DIB11_CLKB_posedge or + Tviol_DIB12_CLKB_posedge or + Tviol_DIB13_CLKB_posedge or + Tviol_DIB14_CLKB_posedge or + Tviol_DIB15_CLKB_posedge or + Tviol_DIB16_CLKB_posedge or + Tviol_DIB17_CLKB_posedge or + Tviol_DIB18_CLKB_posedge or + Tviol_DIB19_CLKB_posedge or + Tviol_DIB20_CLKB_posedge or + Tviol_DIB21_CLKB_posedge or + Tviol_DIB22_CLKB_posedge or + Tviol_DIB23_CLKB_posedge or + Tviol_DIB24_CLKB_posedge or + Tviol_DIB25_CLKB_posedge or + Tviol_DIB26_CLKB_posedge or + Tviol_DIB27_CLKB_posedge or + Tviol_DIB28_CLKB_posedge or + Tviol_DIB29_CLKB_posedge or + Tviol_DIB30_CLKB_posedge or + Tviol_DIB31_CLKB_posedge or + Tviol_DIPB0_CLKB_posedge or + Tviol_DIPB1_CLKB_posedge or + Tviol_DIPB2_CLKB_posedge or + Tviol_DIPB3_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S36", + InstanceName => ramb16_s1_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S36", + InstanceName => ramb16_s1_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S36", + InstanceName => ramb16_s1_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S36", + InstanceName => ramb16_s1_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S36", + InstanceName => ramb16_s1_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S36", + InstanceName => ramb16_s1_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S36", + InstanceName => ramb16_s1_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(0 downto 0); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + DOPB_zd := DIPB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S36", + InstanceName => ramb16_s1_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S36", + InstanceName => ramb16_s1_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S36", + InstanceName => ramb16_s1_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S36", + InstanceName => ramb16_s1_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S36", + InstanceName => ramb16_s1_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S36", + InstanceName => ramb16_s1_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S36", + InstanceName => ramb16_s1_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(31 downto 0); + DOPB_zd := SRVA_B(35 downto 32); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOB_zd(8) := ViolationB xor DOB_zd(8); + DOB_zd(9) := ViolationB xor DOB_zd(9); + DOB_zd(10) := ViolationB xor DOB_zd(10); + DOB_zd(11) := ViolationB xor DOB_zd(11); + DOB_zd(12) := ViolationB xor DOB_zd(12); + DOB_zd(13) := ViolationB xor DOB_zd(13); + DOB_zd(14) := ViolationB xor DOB_zd(14); + DOB_zd(15) := ViolationB xor DOB_zd(15); + DOB_zd(16) := ViolationB xor DOB_zd(16); + DOB_zd(17) := ViolationB xor DOB_zd(17); + DOB_zd(18) := ViolationB xor DOB_zd(18); + DOB_zd(19) := ViolationB xor DOB_zd(19); + DOB_zd(20) := ViolationB xor DOB_zd(20); + DOB_zd(21) := ViolationB xor DOB_zd(21); + DOB_zd(22) := ViolationB xor DOB_zd(22); + DOB_zd(23) := ViolationB xor DOB_zd(23); + DOB_zd(24) := ViolationB xor DOB_zd(24); + DOB_zd(25) := ViolationB xor DOB_zd(25); + DOB_zd(26) := ViolationB xor DOB_zd(26); + DOB_zd(27) := ViolationB xor DOB_zd(27); + DOB_zd(28) := ViolationB xor DOB_zd(28); + DOB_zd(29) := ViolationB xor DOB_zd(29); + DOB_zd(30) := ViolationB xor DOB_zd(30); + DOB_zd(31) := ViolationB xor DOB_zd(31); + DOPB_zd(0) := ViolationB xor DOPB_zd(0); + DOPB_zd(1) := ViolationB xor DOPB_zd(1); + DOPB_zd(2) := ViolationB xor DOPB_zd(2); + DOPB_zd(3) := ViolationB xor DOPB_zd(3); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(8), + GlitchData => DOB_GlitchData8, + OutSignalName => "DOB(8)", + OutTemp => DOB_zd(8), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(9), + GlitchData => DOB_GlitchData9, + OutSignalName => "DOB(9)", + OutTemp => DOB_zd(9), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(10), + GlitchData => DOB_GlitchData10, + OutSignalName => "DOB(10)", + OutTemp => DOB_zd(10), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(11), + GlitchData => DOB_GlitchData11, + OutSignalName => "DOB(11)", + OutTemp => DOB_zd(11), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(12), + GlitchData => DOB_GlitchData12, + OutSignalName => "DOB(12)", + OutTemp => DOB_zd(12), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(13), + GlitchData => DOB_GlitchData13, + OutSignalName => "DOB(13)", + OutTemp => DOB_zd(13), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(14), + GlitchData => DOB_GlitchData14, + OutSignalName => "DOB(14)", + OutTemp => DOB_zd(14), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(15), + GlitchData => DOB_GlitchData15, + OutSignalName => "DOB(15)", + OutTemp => DOB_zd(15), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(16), + GlitchData => DOB_GlitchData16, + OutSignalName => "DOB(16)", + OutTemp => DOB_zd(16), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(16), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(17), + GlitchData => DOB_GlitchData17, + OutSignalName => "DOB(17)", + OutTemp => DOB_zd(17), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(17), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(18), + GlitchData => DOB_GlitchData18, + OutSignalName => "DOB(18)", + OutTemp => DOB_zd(18), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(18), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(19), + GlitchData => DOB_GlitchData19, + OutSignalName => "DOB(19)", + OutTemp => DOB_zd(19), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(19), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(20), + GlitchData => DOB_GlitchData20, + OutSignalName => "DOB(20)", + OutTemp => DOB_zd(20), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(20), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(21), + GlitchData => DOB_GlitchData21, + OutSignalName => "DOB(21)", + OutTemp => DOB_zd(21), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(21), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(22), + GlitchData => DOB_GlitchData22, + OutSignalName => "DOB(22)", + OutTemp => DOB_zd(22), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(22), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(23), + GlitchData => DOB_GlitchData23, + OutSignalName => "DOB(23)", + OutTemp => DOB_zd(23), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(23), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(24), + GlitchData => DOB_GlitchData24, + OutSignalName => "DOB(24)", + OutTemp => DOB_zd(24), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(24), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(25), + GlitchData => DOB_GlitchData25, + OutSignalName => "DOB(25)", + OutTemp => DOB_zd(25), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(25), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(26), + GlitchData => DOB_GlitchData26, + OutSignalName => "DOB(26)", + OutTemp => DOB_zd(26), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(26), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(27), + GlitchData => DOB_GlitchData27, + OutSignalName => "DOB(27)", + OutTemp => DOB_zd(27), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(27), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(28), + GlitchData => DOB_GlitchData28, + OutSignalName => "DOB(28)", + OutTemp => DOB_zd(28), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(28), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(29), + GlitchData => DOB_GlitchData29, + OutSignalName => "DOB(29)", + OutTemp => DOB_zd(29), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(29), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(30), + GlitchData => DOB_GlitchData30, + OutSignalName => "DOB(30)", + OutTemp => DOB_zd(30), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(30), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(31), + GlitchData => DOB_GlitchData31, + OutSignalName => "DOB(31)", + OutTemp => DOB_zd(31), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(31), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(0), + GlitchData => DOPB_GlitchData0, + OutSignalName => "DOPB(0)", + OutTemp => DOPB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(1), + GlitchData => DOPB_GlitchData1, + OutSignalName => "DOPB(1)", + OutTemp => DOPB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(2), + GlitchData => DOPB_GlitchData2, + OutSignalName => "DOPB(2)", + OutTemp => DOPB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(3), + GlitchData => DOPB_GlitchData3, + OutSignalName => "DOPB(3)", + OutTemp => DOPB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S1_S36_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S1_S4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s1_s4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S1_S4 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(13 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(11 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"0"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"0"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(3 downto 0); + + ADDRA : in std_logic_vector(13 downto 0); + ADDRB : in std_logic_vector(11 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S1_S4 : entity is true; +end ramb16_s1_s4; + +architecture RAMB16_S1_S4_V of RAMB16_S1_S4 is + attribute VITAL_LEVEL0 of + RAMB16_S1_S4_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(13 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(11 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 16384; + constant length_b : integer := 4096; + constant width_a : integer := 1; + constant width_b : integer := 4; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 13 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 11 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA13_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA13_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (0 downto 0) := "0"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (3 downto 0) := "0000"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (0 downto 0) := "0"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (3 downto 0) := "0000"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(0 downto 0) := INI_A(0 downto 0); + variable DOB_zd : std_logic_vector(3 downto 0) := INI_B(3 downto 0); + + variable ADDRA_ipd_sampled : std_logic_vector(13 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S1_S4", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 1) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(0 downto 0) := INI_A_UNBOUND(0 downto 0); + + for I in INI_A_UNBOUND'high downto 1 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 1 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S1_S4", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 1) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S1_S4", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 1) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 4) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(3 downto 0) := INI_B_UNBOUND(3 downto 0); + + for I in INI_B_UNBOUND'high downto 4 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 4 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S1_S4", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 4) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S1_S4", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 4) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 1) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(0 downto 0) := SRVA_A_UNBOUND(0 downto 0); + + for I in SRVA_A_UNBOUND'high downto 1 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 1 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S1_S4", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 1) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S1_S4", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 1) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 4) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(3 downto 0) := SRVA_B_UNBOUND(3 downto 0); + + for I in SRVA_B_UNBOUND'high downto 4 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 4 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S1_S4", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 4) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S1_S4", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 4) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(0 downto 0) := INI_A(0 downto 0); + DOB_zd(3 downto 0) := INI_B(3 downto 0); + DOA <= DOA_zd; + DOB <= DOB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S1_S4", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S1_S4", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA11_CLKA_posedge, + TimingData => Tmkr_ADDRA11_CLKA_posedge, + TestSignal => ADDRA_ipd(11), + TestSignalName => "ADDRA(11)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(11), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(11), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(11), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(11), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA12_CLKA_posedge, + TimingData => Tmkr_ADDRA12_CLKA_posedge, + TestSignal => ADDRA_ipd(12), + TestSignalName => "ADDRA(12)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(12), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(12), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(12), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(12), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB9_CLKB_posedge, + TimingData => Tmkr_ADDRB9_CLKB_posedge, + TestSignal => ADDRB_ipd(9), + TestSignalName => "ADDRB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(9), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(9), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(9), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(9), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB10_CLKB_posedge, + TimingData => Tmkr_ADDRB10_CLKB_posedge, + TestSignal => ADDRB_ipd(10), + TestSignalName => "ADDRB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(10), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(10), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(10), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(10), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_ADDRA12_CLKA_posedge or + Tviol_ADDRA13_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_ADDRB10_CLKB_posedge or + Tviol_ADDRB11_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S4", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S4", + InstanceName => ramb16_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S4", + InstanceName => ramb16_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S4", + InstanceName => ramb16_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S4", + InstanceName => ramb16_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S4", + InstanceName => ramb16_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S4", + InstanceName => ramb16_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S4", + InstanceName => ramb16_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(0 downto 0); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S4", + InstanceName => ramb16_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S4", + InstanceName => ramb16_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S4", + InstanceName => ramb16_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S4", + InstanceName => ramb16_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S4", + InstanceName => ramb16_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S4", + InstanceName => ramb16_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S4", + InstanceName => ramb16_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(3 downto 0); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + end if; + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S1_S4_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S1_S9.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s1_s9 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S1_S9 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(13 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(10 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPB : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOPB : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(13 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"000"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPB : out std_logic_vector(0 downto 0); + + ADDRA : in std_logic_vector(13 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S1_S9 : entity is true; +end ramb16_s1_s9; + +architecture RAMB16_S1_S9_V of RAMB16_S1_S9 is + attribute VITAL_LEVEL0 of + RAMB16_S1_S9_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(13 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(10 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(7 downto 0) := (others => 'X'); + signal DIPB_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 16384; + constant length_b : integer := 2048; + constant width_a : integer := 1; + constant width_b : integer := 8; + + constant parity_width_b : integer := 1; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + + function slv_to_two_D_parity_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_parity_array_type is + variable two_D_parity_array : two_D_parity_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_parity_array(i) := intermediate; + end loop; + return two_D_parity_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 13 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 10 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 7 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + DIPB_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i)); + end generate DIPB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA13_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA13_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOPB_GlitchData0 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) & + To_StdLogicVector(INITP_06) & + To_StdLogicVector(INITP_05) & + To_StdLogicVector(INITP_04) & + To_StdLogicVector(INITP_03) & + To_StdLogicVector(INITP_02) & + To_StdLogicVector(INITP_01) & + To_StdLogicVector(INITP_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOPB_OV_LSB : integer := 0; + variable DOPB_OV_MSB : integer := 0; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (0 downto 0) := "0"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (8 downto 0) := "000000000"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (0 downto 0) := "0"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (8 downto 0) := "000000000"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(0 downto 0) := INI_A(0 downto 0); + variable DOB_zd : std_logic_vector(7 downto 0) := INI_B(7 downto 0); + variable DOPB_zd : std_logic_vector(0 downto 0) := INI_B(8 downto 8); + + variable ADDRA_ipd_sampled : std_logic_vector(13 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S1_S9", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 1) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(0 downto 0) := INI_A_UNBOUND(0 downto 0); + + for I in INI_A_UNBOUND'high downto 1 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 1 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S1_S9", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 1) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S1_S9", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 1) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 9) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(8 downto 0) := INI_B_UNBOUND(8 downto 0); + + for I in INI_B_UNBOUND'high downto 9 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 9 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S1_S9", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 9) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S1_S9", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 9) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 1) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(0 downto 0) := SRVA_A_UNBOUND(0 downto 0); + + for I in SRVA_A_UNBOUND'high downto 1 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 1 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S1_S9", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 1) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S1_S9", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 1, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 1) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 9) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(8 downto 0) := SRVA_B_UNBOUND(8 downto 0); + + for I in SRVA_B_UNBOUND'high downto 9 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 9 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S1_S9", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 9) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S1_S9", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 9) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(0 downto 0) := INI_A(0 downto 0); + DOB_zd(7 downto 0) := INI_B(7 downto 0); + DOPB_zd(0 downto 0) := INI_B(8 downto 8); + DOA <= DOA_zd; + DOB <= DOB_zd; + DOPB <= DOPB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S1_S9", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S1_S9", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA11_CLKA_posedge, + TimingData => Tmkr_ADDRA11_CLKA_posedge, + TestSignal => ADDRA_ipd(11), + TestSignalName => "ADDRA(11)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(11), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(11), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(11), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(11), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA12_CLKA_posedge, + TimingData => Tmkr_ADDRA12_CLKA_posedge, + TestSignal => ADDRA_ipd(12), + TestSignalName => "ADDRA(12)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(12), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(12), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(12), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(12), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB9_CLKB_posedge, + TimingData => Tmkr_ADDRB9_CLKB_posedge, + TestSignal => ADDRB_ipd(9), + TestSignalName => "ADDRB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(9), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(9), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(9), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(9), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S1_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_ADDRA12_CLKA_posedge or + Tviol_ADDRA13_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_ADDRB10_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIPB0_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S1_S9", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S9", + InstanceName => ramb16_s1_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S9", + InstanceName => ramb16_s1_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S9", + InstanceName => ramb16_s1_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S9", + InstanceName => ramb16_s1_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S9", + InstanceName => ramb16_s1_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S9", + InstanceName => ramb16_s1_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S9", + InstanceName => ramb16_s1_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(0 downto 0); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + DOPB_zd := DIPB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S9", + InstanceName => ramb16_s1_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S9", + InstanceName => ramb16_s1_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S9", + InstanceName => ramb16_s1_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S9", + InstanceName => ramb16_s1_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S1_S9", + InstanceName => ramb16_s1_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S1_S9", + InstanceName => ramb16_s1_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S1_S9", + InstanceName => ramb16_s1_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(7 downto 0); + DOPB_zd := SRVA_B(8 downto 8); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOPB_zd(0) := ViolationB xor DOPB_zd(0); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(0), + GlitchData => DOPB_GlitchData0, + OutSignalName => "DOPB(0)", + OutTemp => DOPB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S1_S9_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb16_s2.vhd,v 1.7 2005/10/07 18:35:24 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +-- /___/ /\ Filename : RAMB16_S2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:51 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 09/26/05 - Fixed CR# 216846. INIT and SRVAL attributes length check and adjustment. +-- END Revision + +----- CELL RAMB16_S2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S2 is + + generic ( + INIT : bit_vector := X"0"; + SRVAL : bit_vector := X"0"; + WRITE_MODE : string := "WRITE_FIRST"; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + + port ( + DO : out STD_LOGIC_VECTOR (1 downto 0); + + ADDR : in STD_LOGIC_VECTOR (12 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (1 downto 0); + EN : in STD_ULOGIC; + SSR : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end RAMB16_S2; + +architecture RAMB16_S2_V of RAMB16_S2 is + constant length : integer := 8192; + constant width : integer := 2; + + type Two_D_array_type is array ((length - 1) downto 0) of std_logic_vector((width - 1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + VITALBehavior : process + variable address : integer; + variable valid_addr : boolean := FALSE; + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F & INIT_3E & INIT_3D & INIT_3C & + INIT_3B & INIT_3A & INIT_39 & INIT_38 & + INIT_37 & INIT_36 & INIT_35 & INIT_34 & + INIT_33 & INIT_32 & INIT_31 & INIT_30 & + INIT_2F & INIT_2E & INIT_2D & INIT_2C & + INIT_2B & INIT_2A & INIT_29 & INIT_28 & + INIT_27 & INIT_26 & INIT_25 & INIT_24 & + INIT_23 & INIT_22 & INIT_21 & INIT_20 & + INIT_1F & INIT_1E & INIT_1D & INIT_1C & + INIT_1B & INIT_1A & INIT_19 & INIT_18 & + INIT_17 & INIT_16 & INIT_15 & INIT_14 & + INIT_13 & INIT_12 & INIT_11 & INIT_10 & + INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(length, width, mem_slv); + + variable wr_mode : integer := 0; + variable first_time : boolean := true; + + variable INIT_reg : std_logic_vector (1 downto 0) := "00"; + variable SRVAL_reg : std_logic_vector (1 downto 0) := "00"; + + begin + if (first_time) then + if ((WRITE_MODE = "write_first") or (WRITE_MODE = "WRITE_FIRST")) then + wr_mode := 0; + elsif ((WRITE_MODE = "read_first") or (WRITE_MODE = "READ_FIRST")) then + wr_mode := 1; + elsif ((WRITE_MODE = "no_change") or (WRITE_MODE = "NO_CHANGE")) then + wr_mode := 2; + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Error ", + GenericName => " WRITE_MODE ", + EntityName => "/RAMB16_S2", + GenericValue => WRITE_MODE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT'length > 2) then + INIT_reg(1 downto 0) := To_StdLogicVector(INIT)(1 downto 0); + else + INIT_reg(INIT'length-1 downto 0) := To_StdLogicVector(INIT); + end if; + DO <= INIT_reg(1 downto 0); + + if (SRVAL'length > 2) then + SRVAL_reg(1 downto 0) := To_StdLogicVector(SRVAL)(1 downto 0); + else + SRVAL_reg(SRVAL'length-1 downto 0) := To_StdLogicVector(SRVAL); + end if; + first_time := false; + end if; + + valid_addr := addr_is_valid(addr); + + if (valid_addr) then + address := slv_to_int(addr); + end if; + + if (rising_edge(CLK)) then + if (EN = '1') then + if (SSR = '1') then + DO <= SRVAL_reg(1 downto 0) after 100 ps; + else + if (WE = '1') then + if (wr_mode = 0) then + DO <= DI after 100 ps; + elsif (wr_mode = 1) then + DO <= mem(address) after 100 ps; + end if; + else + if (valid_addr) then + DO <= mem(address) after 100 ps; + end if; + end if; + end if; + if (WE = '1') then + if (valid_addr) then + mem(address) := DI; + end if; + end if; + end if; + end if; + wait on CLK; + + end process VITALBehavior; + +end RAMB16_S2_V; + + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S2_S18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s2_s18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S2_S18 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(12 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(9 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPB : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOPB : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"00000"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"00000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(1 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPB : out std_logic_vector(1 downto 0); + + ADDRA : in std_logic_vector(12 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(1 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S2_S18 : entity is true; +end ramb16_s2_s18; + +architecture RAMB16_S2_S18_V of RAMB16_S2_S18 is + attribute VITAL_LEVEL0 of + RAMB16_S2_S18_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(12 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(9 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(15 downto 0) := (others => 'X'); + signal DIPB_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 8192; + constant length_b : integer := 1024; + constant width_a : integer := 2; + constant width_b : integer := 16; + + constant parity_width_b : integer := 2; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + + function slv_to_two_D_parity_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_parity_array_type is + variable two_D_parity_array : two_D_parity_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_parity_array(i) := intermediate; + end loop; + return two_D_parity_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 12 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 9 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 15 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + DIPB_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i)); + end generate DIPB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB12_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB13_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB14_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB15_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB13_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB14_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB15_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOB_GlitchData8 : VitalGlitchDataType; + variable DOB_GlitchData9 : VitalGlitchDataType; + variable DOB_GlitchData10 : VitalGlitchDataType; + variable DOB_GlitchData11 : VitalGlitchDataType; + variable DOB_GlitchData12 : VitalGlitchDataType; + variable DOB_GlitchData13 : VitalGlitchDataType; + variable DOB_GlitchData14 : VitalGlitchDataType; + variable DOB_GlitchData15 : VitalGlitchDataType; + variable DOPB_GlitchData0 : VitalGlitchDataType; + variable DOPB_GlitchData1 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) & + To_StdLogicVector(INITP_06) & + To_StdLogicVector(INITP_05) & + To_StdLogicVector(INITP_04) & + To_StdLogicVector(INITP_03) & + To_StdLogicVector(INITP_02) & + To_StdLogicVector(INITP_01) & + To_StdLogicVector(INITP_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOPB_OV_LSB : integer := 0; + variable DOPB_OV_MSB : integer := 1; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (1 downto 0) := "00"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (17 downto 0) := "000000000000000000"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (1 downto 0) := "00"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (17 downto 0) := "000000000000000000"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(1 downto 0) := INI_A(1 downto 0); + variable DOB_zd : std_logic_vector(15 downto 0) := INI_B(15 downto 0); + variable DOPB_zd : std_logic_vector(1 downto 0) := INI_B(17 downto 16); + + variable ADDRA_ipd_sampled : std_logic_vector(12 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S2_S18", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 2) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(1 downto 0) := INI_A_UNBOUND(1 downto 0); + + for I in INI_A_UNBOUND'high downto 2 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 2 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S2_S18", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 2) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S2_S18", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 2) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 18) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(17 downto 0) := INI_B_UNBOUND(17 downto 0); + + for I in INI_B_UNBOUND'high downto 18 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 18 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S2_S18", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 18) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S2_S18", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 18) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 2) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(1 downto 0) := SRVA_A_UNBOUND(1 downto 0); + + for I in SRVA_A_UNBOUND'high downto 2 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 2 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S2_S18", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 2) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S2_S18", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 2) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 18) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(17 downto 0) := SRVA_B_UNBOUND(17 downto 0); + + for I in SRVA_B_UNBOUND'high downto 18 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 18 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S2_S18", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 18) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S2_S18", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 18) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(1 downto 0) := INI_A(1 downto 0); + DOB_zd(15 downto 0) := INI_B(15 downto 0); + DOPB_zd(1 downto 0) := INI_B(17 downto 16); + DOA <= DOA_zd; + DOB <= DOB_zd; + DOPB <= DOPB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S2_S18", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S2_S18", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA11_CLKA_posedge, + TimingData => Tmkr_ADDRA11_CLKA_posedge, + TestSignal => ADDRA_ipd(11), + TestSignalName => "ADDRA(11)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(11), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(11), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(11), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(11), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB0_CLKB_posedge, + TimingData => Tmkr_DIPB0_CLKB_posedge, + TestSignal => DIPB_ipd(0), + TestSignalName => "DIPB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(0), + HoldLow => thold_DIPB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB7_CLKB_posedge, + TimingData => Tmkr_DIB7_CLKB_posedge, + TestSignal => DIB_ipd(7), + TestSignalName => "DIB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(7), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(7), + HoldLow => thold_DIB_CLKB_posedge_posedge(7), + HoldHigh => thold_DIB_CLKB_negedge_posedge(7), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB8_CLKB_posedge, + TimingData => Tmkr_DIB8_CLKB_posedge, + TestSignal => DIB_ipd(8), + TestSignalName => "DIB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(8), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(8), + HoldLow => thold_DIB_CLKB_posedge_posedge(8), + HoldHigh => thold_DIB_CLKB_negedge_posedge(8), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB9_CLKB_posedge, + TimingData => Tmkr_DIB9_CLKB_posedge, + TestSignal => DIB_ipd(9), + TestSignalName => "DIB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(9), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(9), + HoldLow => thold_DIB_CLKB_posedge_posedge(9), + HoldHigh => thold_DIB_CLKB_negedge_posedge(9), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB10_CLKB_posedge, + TimingData => Tmkr_DIB10_CLKB_posedge, + TestSignal => DIB_ipd(10), + TestSignalName => "DIB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(10), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(10), + HoldLow => thold_DIB_CLKB_posedge_posedge(10), + HoldHigh => thold_DIB_CLKB_negedge_posedge(10), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB11_CLKB_posedge, + TimingData => Tmkr_DIB11_CLKB_posedge, + TestSignal => DIB_ipd(11), + TestSignalName => "DIB(11)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(11), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(11), + HoldLow => thold_DIB_CLKB_posedge_posedge(11), + HoldHigh => thold_DIB_CLKB_negedge_posedge(11), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB12_CLKB_posedge, + TimingData => Tmkr_DIB12_CLKB_posedge, + TestSignal => DIB_ipd(12), + TestSignalName => "DIB(12)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(12), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(12), + HoldLow => thold_DIB_CLKB_posedge_posedge(12), + HoldHigh => thold_DIB_CLKB_negedge_posedge(12), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB13_CLKB_posedge, + TimingData => Tmkr_DIB13_CLKB_posedge, + TestSignal => DIB_ipd(13), + TestSignalName => "DIB(13)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(13), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(13), + HoldLow => thold_DIB_CLKB_posedge_posedge(13), + HoldHigh => thold_DIB_CLKB_negedge_posedge(13), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB14_CLKB_posedge, + TimingData => Tmkr_DIB14_CLKB_posedge, + TestSignal => DIB_ipd(14), + TestSignalName => "DIB(14)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(14), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(14), + HoldLow => thold_DIB_CLKB_posedge_posedge(14), + HoldHigh => thold_DIB_CLKB_negedge_posedge(14), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S2_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_ADDRA12_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIB8_CLKB_posedge or + Tviol_DIB9_CLKB_posedge or + Tviol_DIB10_CLKB_posedge or + Tviol_DIB11_CLKB_posedge or + Tviol_DIB12_CLKB_posedge or + Tviol_DIB13_CLKB_posedge or + Tviol_DIB14_CLKB_posedge or + Tviol_DIB15_CLKB_posedge or + Tviol_DIPB0_CLKB_posedge or + Tviol_DIPB1_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S18", + InstanceName => ramb16_s2_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S18", + InstanceName => ramb16_s2_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S18", + InstanceName => ramb16_s2_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S18", + InstanceName => ramb16_s2_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S18", + InstanceName => ramb16_s2_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S18", + InstanceName => ramb16_s2_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S18", + InstanceName => ramb16_s2_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(1 downto 0); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + DOPB_zd := DIPB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S18", + InstanceName => ramb16_s2_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S18", + InstanceName => ramb16_s2_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S18", + InstanceName => ramb16_s2_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S18", + InstanceName => ramb16_s2_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S18", + InstanceName => ramb16_s2_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S18", + InstanceName => ramb16_s2_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S18", + InstanceName => ramb16_s2_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(15 downto 0); + DOPB_zd := SRVA_B(17 downto 16); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOB_zd(8) := ViolationB xor DOB_zd(8); + DOB_zd(9) := ViolationB xor DOB_zd(9); + DOB_zd(10) := ViolationB xor DOB_zd(10); + DOB_zd(11) := ViolationB xor DOB_zd(11); + DOB_zd(12) := ViolationB xor DOB_zd(12); + DOB_zd(13) := ViolationB xor DOB_zd(13); + DOB_zd(14) := ViolationB xor DOB_zd(14); + DOB_zd(15) := ViolationB xor DOB_zd(15); + DOPB_zd(0) := ViolationB xor DOPB_zd(0); + DOPB_zd(1) := ViolationB xor DOPB_zd(1); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(8), + GlitchData => DOB_GlitchData8, + OutSignalName => "DOB(8)", + OutTemp => DOB_zd(8), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(9), + GlitchData => DOB_GlitchData9, + OutSignalName => "DOB(9)", + OutTemp => DOB_zd(9), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(10), + GlitchData => DOB_GlitchData10, + OutSignalName => "DOB(10)", + OutTemp => DOB_zd(10), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(11), + GlitchData => DOB_GlitchData11, + OutSignalName => "DOB(11)", + OutTemp => DOB_zd(11), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(12), + GlitchData => DOB_GlitchData12, + OutSignalName => "DOB(12)", + OutTemp => DOB_zd(12), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(13), + GlitchData => DOB_GlitchData13, + OutSignalName => "DOB(13)", + OutTemp => DOB_zd(13), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(14), + GlitchData => DOB_GlitchData14, + OutSignalName => "DOB(14)", + OutTemp => DOB_zd(14), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(15), + GlitchData => DOB_GlitchData15, + OutSignalName => "DOB(15)", + OutTemp => DOB_zd(15), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(0), + GlitchData => DOPB_GlitchData0, + OutSignalName => "DOPB(0)", + OutTemp => DOPB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(1), + GlitchData => DOPB_GlitchData1, + OutSignalName => "DOPB(1)", + OutTemp => DOPB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S2_S18_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S2_S2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s2_s2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S2_S2 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(12 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(12 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"0"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"0"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(1 downto 0); + DOB : out std_logic_vector(1 downto 0); + + ADDRA : in std_logic_vector(12 downto 0); + ADDRB : in std_logic_vector(12 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(1 downto 0); + DIB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S2_S2 : entity is true; +end ramb16_s2_s2; + +architecture RAMB16_S2_S2_V of RAMB16_S2_S2 is + attribute VITAL_LEVEL0 of + RAMB16_S2_S2_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(12 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(12 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 8192; + constant length_b : integer := 8192; + constant width_a : integer := 2; + constant width_b : integer := 2; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 12 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 12 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB12_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (1 downto 0) := "00"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (1 downto 0) := "00"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (1 downto 0) := "00"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (1 downto 0) := "00"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(1 downto 0) := INI_A(1 downto 0); + variable DOB_zd : std_logic_vector(1 downto 0) := INI_B(1 downto 0); + + variable ADDRA_ipd_sampled : std_logic_vector(12 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(12 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S2_S2", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 2) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(1 downto 0) := INI_A_UNBOUND(1 downto 0); + + for I in INI_A_UNBOUND'high downto 2 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 2 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S2_S2", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 2) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S2_S2", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 2) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 2) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(1 downto 0) := INI_B_UNBOUND(1 downto 0); + + for I in INI_B_UNBOUND'high downto 2 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 2 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S2_S2", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 2) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S2_S2", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 2) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 2) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(1 downto 0) := SRVA_A_UNBOUND(1 downto 0); + + for I in SRVA_A_UNBOUND'high downto 2 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 2 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S2_S2", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 2) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S2_S2", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 2) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 2) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(1 downto 0) := SRVA_B_UNBOUND(1 downto 0); + + for I in SRVA_B_UNBOUND'high downto 2 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 2 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S2_S2", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 2) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S2_S2", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 2) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(1 downto 0) := INI_A(1 downto 0); + DOB_zd(1 downto 0) := INI_B(1 downto 0); + DOA <= DOA_zd; + DOB <= DOB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S2_S2", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S2_S2", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA11_CLKA_posedge, + TimingData => Tmkr_ADDRA11_CLKA_posedge, + TestSignal => ADDRA_ipd(11), + TestSignalName => "ADDRA(11)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(11), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(11), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(11), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(11), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB9_CLKB_posedge, + TimingData => Tmkr_ADDRB9_CLKB_posedge, + TestSignal => ADDRB_ipd(9), + TestSignalName => "ADDRB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(9), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(9), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(9), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(9), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB10_CLKB_posedge, + TimingData => Tmkr_ADDRB10_CLKB_posedge, + TestSignal => ADDRB_ipd(10), + TestSignalName => "ADDRB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(10), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(10), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(10), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(10), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB11_CLKB_posedge, + TimingData => Tmkr_ADDRB11_CLKB_posedge, + TestSignal => ADDRB_ipd(11), + TestSignalName => "ADDRB(11)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(11), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(11), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(11), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(11), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_ADDRA12_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_ADDRB10_CLKB_posedge or + Tviol_ADDRB11_CLKB_posedge or + Tviol_ADDRB12_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S2", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S2", + InstanceName => ramb16_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S2", + InstanceName => ramb16_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S2", + InstanceName => ramb16_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S2", + InstanceName => ramb16_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S2", + InstanceName => ramb16_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S2", + InstanceName => ramb16_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S2", + InstanceName => ramb16_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(1 downto 0); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S2", + InstanceName => ramb16_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S2", + InstanceName => ramb16_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S2", + InstanceName => ramb16_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S2", + InstanceName => ramb16_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S2", + InstanceName => ramb16_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S2", + InstanceName => ramb16_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S2", + InstanceName => ramb16_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(1 downto 0); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + end if; + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S2_S2_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S2_S36.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s2_s36 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S2_S36 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(12 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(8 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPB : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(31 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOPB : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"000000000"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"000000000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(1 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPB : out std_logic_vector(3 downto 0); + + ADDRA : in std_logic_vector(12 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(1 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S2_S36 : entity is true; +end ramb16_s2_s36; + +architecture RAMB16_S2_S36_V of RAMB16_S2_S36 is + attribute VITAL_LEVEL0 of + RAMB16_S2_S36_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(12 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(8 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(31 downto 0) := (others => 'X'); + signal DIPB_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 8192; + constant length_b : integer := 512; + constant width_a : integer := 2; + constant width_b : integer := 32; + + constant parity_width_b : integer := 4; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + + function slv_to_two_D_parity_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_parity_array_type is + variable two_D_parity_array : two_D_parity_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_parity_array(i) := intermediate; + end loop; + return two_D_parity_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 12 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 8 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 31 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + DIPB_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i)); + end generate DIPB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB12_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB13_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB14_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB15_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB16_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB17_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB18_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB19_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB20_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB21_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB22_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB23_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB24_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB25_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB26_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB27_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB28_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB29_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB30_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB31_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB13_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB14_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB15_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB16_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB17_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB18_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB19_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB20_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB21_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB22_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB23_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB24_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB25_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB26_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB27_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB28_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB29_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB30_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB31_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOB_GlitchData8 : VitalGlitchDataType; + variable DOB_GlitchData9 : VitalGlitchDataType; + variable DOB_GlitchData10 : VitalGlitchDataType; + variable DOB_GlitchData11 : VitalGlitchDataType; + variable DOB_GlitchData12 : VitalGlitchDataType; + variable DOB_GlitchData13 : VitalGlitchDataType; + variable DOB_GlitchData14 : VitalGlitchDataType; + variable DOB_GlitchData15 : VitalGlitchDataType; + variable DOB_GlitchData16 : VitalGlitchDataType; + variable DOB_GlitchData17 : VitalGlitchDataType; + variable DOB_GlitchData18 : VitalGlitchDataType; + variable DOB_GlitchData19 : VitalGlitchDataType; + variable DOB_GlitchData20 : VitalGlitchDataType; + variable DOB_GlitchData21 : VitalGlitchDataType; + variable DOB_GlitchData22 : VitalGlitchDataType; + variable DOB_GlitchData23 : VitalGlitchDataType; + variable DOB_GlitchData24 : VitalGlitchDataType; + variable DOB_GlitchData25 : VitalGlitchDataType; + variable DOB_GlitchData26 : VitalGlitchDataType; + variable DOB_GlitchData27 : VitalGlitchDataType; + variable DOB_GlitchData28 : VitalGlitchDataType; + variable DOB_GlitchData29 : VitalGlitchDataType; + variable DOB_GlitchData30 : VitalGlitchDataType; + variable DOB_GlitchData31 : VitalGlitchDataType; + variable DOPB_GlitchData0 : VitalGlitchDataType; + variable DOPB_GlitchData1 : VitalGlitchDataType; + variable DOPB_GlitchData2 : VitalGlitchDataType; + variable DOPB_GlitchData3 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) & + To_StdLogicVector(INITP_06) & + To_StdLogicVector(INITP_05) & + To_StdLogicVector(INITP_04) & + To_StdLogicVector(INITP_03) & + To_StdLogicVector(INITP_02) & + To_StdLogicVector(INITP_01) & + To_StdLogicVector(INITP_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOPB_OV_LSB : integer := 0; + variable DOPB_OV_MSB : integer := 3; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (1 downto 0) := "00"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (35 downto 0) := "000000000000000000000000000000000000"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (1 downto 0) := "00"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (35 downto 0) := "000000000000000000000000000000000000"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(1 downto 0) := INI_A(1 downto 0); + variable DOB_zd : std_logic_vector(31 downto 0) := INI_B(31 downto 0); + variable DOPB_zd : std_logic_vector(3 downto 0) := INI_B(35 downto 32); + + variable ADDRA_ipd_sampled : std_logic_vector(12 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S2_S36", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 2) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(1 downto 0) := INI_A_UNBOUND(1 downto 0); + + for I in INI_A_UNBOUND'high downto 2 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 2 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S2_S36", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 2) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S2_S36", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 2) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 36) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(35 downto 0) := INI_B_UNBOUND(35 downto 0); + + for I in INI_B_UNBOUND'high downto 36 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 36 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S2_S36", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S2_S36", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 2) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(1 downto 0) := SRVA_A_UNBOUND(1 downto 0); + + for I in SRVA_A_UNBOUND'high downto 2 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 2 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S2_S36", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 2) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S2_S36", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 2) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 36) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(35 downto 0) := SRVA_B_UNBOUND(35 downto 0); + + for I in SRVA_B_UNBOUND'high downto 36 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 36 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S2_S36", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S2_S36", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(1 downto 0) := INI_A(1 downto 0); + DOB_zd(31 downto 0) := INI_B(31 downto 0); + DOPB_zd(3 downto 0) := INI_B(35 downto 32); + DOA <= DOA_zd; + DOB <= DOB_zd; + DOPB <= DOPB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S2_S36", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S2_S36", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA11_CLKA_posedge, + TimingData => Tmkr_ADDRA11_CLKA_posedge, + TestSignal => ADDRA_ipd(11), + TestSignalName => "ADDRA(11)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(11), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(11), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(11), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(11), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB0_CLKB_posedge, + TimingData => Tmkr_DIPB0_CLKB_posedge, + TestSignal => DIPB_ipd(0), + TestSignalName => "DIPB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(0), + HoldLow => thold_DIPB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB1_CLKB_posedge, + TimingData => Tmkr_DIPB1_CLKB_posedge, + TestSignal => DIPB_ipd(1), + TestSignalName => "DIPB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(1), + HoldLow => thold_DIPB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB2_CLKB_posedge, + TimingData => Tmkr_DIPB2_CLKB_posedge, + TestSignal => DIPB_ipd(2), + TestSignalName => "DIPB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(2), + HoldLow => thold_DIPB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB7_CLKB_posedge, + TimingData => Tmkr_DIB7_CLKB_posedge, + TestSignal => DIB_ipd(7), + TestSignalName => "DIB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(7), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(7), + HoldLow => thold_DIB_CLKB_posedge_posedge(7), + HoldHigh => thold_DIB_CLKB_negedge_posedge(7), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB8_CLKB_posedge, + TimingData => Tmkr_DIB8_CLKB_posedge, + TestSignal => DIB_ipd(8), + TestSignalName => "DIB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(8), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(8), + HoldLow => thold_DIB_CLKB_posedge_posedge(8), + HoldHigh => thold_DIB_CLKB_negedge_posedge(8), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB9_CLKB_posedge, + TimingData => Tmkr_DIB9_CLKB_posedge, + TestSignal => DIB_ipd(9), + TestSignalName => "DIB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(9), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(9), + HoldLow => thold_DIB_CLKB_posedge_posedge(9), + HoldHigh => thold_DIB_CLKB_negedge_posedge(9), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB10_CLKB_posedge, + TimingData => Tmkr_DIB10_CLKB_posedge, + TestSignal => DIB_ipd(10), + TestSignalName => "DIB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(10), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(10), + HoldLow => thold_DIB_CLKB_posedge_posedge(10), + HoldHigh => thold_DIB_CLKB_negedge_posedge(10), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB11_CLKB_posedge, + TimingData => Tmkr_DIB11_CLKB_posedge, + TestSignal => DIB_ipd(11), + TestSignalName => "DIB(11)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(11), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(11), + HoldLow => thold_DIB_CLKB_posedge_posedge(11), + HoldHigh => thold_DIB_CLKB_negedge_posedge(11), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB12_CLKB_posedge, + TimingData => Tmkr_DIB12_CLKB_posedge, + TestSignal => DIB_ipd(12), + TestSignalName => "DIB(12)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(12), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(12), + HoldLow => thold_DIB_CLKB_posedge_posedge(12), + HoldHigh => thold_DIB_CLKB_negedge_posedge(12), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB13_CLKB_posedge, + TimingData => Tmkr_DIB13_CLKB_posedge, + TestSignal => DIB_ipd(13), + TestSignalName => "DIB(13)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(13), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(13), + HoldLow => thold_DIB_CLKB_posedge_posedge(13), + HoldHigh => thold_DIB_CLKB_negedge_posedge(13), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB14_CLKB_posedge, + TimingData => Tmkr_DIB14_CLKB_posedge, + TestSignal => DIB_ipd(14), + TestSignalName => "DIB(14)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(14), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(14), + HoldLow => thold_DIB_CLKB_posedge_posedge(14), + HoldHigh => thold_DIB_CLKB_negedge_posedge(14), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB15_CLKB_posedge, + TimingData => Tmkr_DIB15_CLKB_posedge, + TestSignal => DIB_ipd(15), + TestSignalName => "DIB(15)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(15), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(15), + HoldLow => thold_DIB_CLKB_posedge_posedge(15), + HoldHigh => thold_DIB_CLKB_negedge_posedge(15), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB16_CLKB_posedge, + TimingData => Tmkr_DIB16_CLKB_posedge, + TestSignal => DIB_ipd(16), + TestSignalName => "DIB(16)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(16), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(16), + HoldLow => thold_DIB_CLKB_posedge_posedge(16), + HoldHigh => thold_DIB_CLKB_negedge_posedge(16), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB17_CLKB_posedge, + TimingData => Tmkr_DIB17_CLKB_posedge, + TestSignal => DIB_ipd(17), + TestSignalName => "DIB(17)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(17), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(17), + HoldLow => thold_DIB_CLKB_posedge_posedge(17), + HoldHigh => thold_DIB_CLKB_negedge_posedge(17), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB18_CLKB_posedge, + TimingData => Tmkr_DIB18_CLKB_posedge, + TestSignal => DIB_ipd(18), + TestSignalName => "DIB(18)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(18), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(18), + HoldLow => thold_DIB_CLKB_posedge_posedge(18), + HoldHigh => thold_DIB_CLKB_negedge_posedge(18), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB19_CLKB_posedge, + TimingData => Tmkr_DIB19_CLKB_posedge, + TestSignal => DIB_ipd(19), + TestSignalName => "DIB(19)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(19), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(19), + HoldLow => thold_DIB_CLKB_posedge_posedge(19), + HoldHigh => thold_DIB_CLKB_negedge_posedge(19), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB20_CLKB_posedge, + TimingData => Tmkr_DIB20_CLKB_posedge, + TestSignal => DIB_ipd(20), + TestSignalName => "DIB(20)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(20), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(20), + HoldLow => thold_DIB_CLKB_posedge_posedge(20), + HoldHigh => thold_DIB_CLKB_negedge_posedge(20), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB21_CLKB_posedge, + TimingData => Tmkr_DIB21_CLKB_posedge, + TestSignal => DIB_ipd(21), + TestSignalName => "DIB(21)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(21), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(21), + HoldLow => thold_DIB_CLKB_posedge_posedge(21), + HoldHigh => thold_DIB_CLKB_negedge_posedge(21), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB22_CLKB_posedge, + TimingData => Tmkr_DIB22_CLKB_posedge, + TestSignal => DIB_ipd(22), + TestSignalName => "DIB(22)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(22), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(22), + HoldLow => thold_DIB_CLKB_posedge_posedge(22), + HoldHigh => thold_DIB_CLKB_negedge_posedge(22), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB23_CLKB_posedge, + TimingData => Tmkr_DIB23_CLKB_posedge, + TestSignal => DIB_ipd(23), + TestSignalName => "DIB(23)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(23), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(23), + HoldLow => thold_DIB_CLKB_posedge_posedge(23), + HoldHigh => thold_DIB_CLKB_negedge_posedge(23), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB24_CLKB_posedge, + TimingData => Tmkr_DIB24_CLKB_posedge, + TestSignal => DIB_ipd(24), + TestSignalName => "DIB(24)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(24), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(24), + HoldLow => thold_DIB_CLKB_posedge_posedge(24), + HoldHigh => thold_DIB_CLKB_negedge_posedge(24), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB25_CLKB_posedge, + TimingData => Tmkr_DIB25_CLKB_posedge, + TestSignal => DIB_ipd(25), + TestSignalName => "DIB(25)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(25), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(25), + HoldLow => thold_DIB_CLKB_posedge_posedge(25), + HoldHigh => thold_DIB_CLKB_negedge_posedge(25), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB26_CLKB_posedge, + TimingData => Tmkr_DIB26_CLKB_posedge, + TestSignal => DIB_ipd(26), + TestSignalName => "DIB(26)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(26), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(26), + HoldLow => thold_DIB_CLKB_posedge_posedge(26), + HoldHigh => thold_DIB_CLKB_negedge_posedge(26), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB27_CLKB_posedge, + TimingData => Tmkr_DIB27_CLKB_posedge, + TestSignal => DIB_ipd(27), + TestSignalName => "DIB(27)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(27), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(27), + HoldLow => thold_DIB_CLKB_posedge_posedge(27), + HoldHigh => thold_DIB_CLKB_negedge_posedge(27), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB28_CLKB_posedge, + TimingData => Tmkr_DIB28_CLKB_posedge, + TestSignal => DIB_ipd(28), + TestSignalName => "DIB(28)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(28), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(28), + HoldLow => thold_DIB_CLKB_posedge_posedge(28), + HoldHigh => thold_DIB_CLKB_negedge_posedge(28), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB29_CLKB_posedge, + TimingData => Tmkr_DIB29_CLKB_posedge, + TestSignal => DIB_ipd(29), + TestSignalName => "DIB(29)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(29), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(29), + HoldLow => thold_DIB_CLKB_posedge_posedge(29), + HoldHigh => thold_DIB_CLKB_negedge_posedge(29), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB30_CLKB_posedge, + TimingData => Tmkr_DIB30_CLKB_posedge, + TestSignal => DIB_ipd(30), + TestSignalName => "DIB(30)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(30), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(30), + HoldLow => thold_DIB_CLKB_posedge_posedge(30), + HoldHigh => thold_DIB_CLKB_negedge_posedge(30), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S2_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_ADDRA12_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIB8_CLKB_posedge or + Tviol_DIB9_CLKB_posedge or + Tviol_DIB10_CLKB_posedge or + Tviol_DIB11_CLKB_posedge or + Tviol_DIB12_CLKB_posedge or + Tviol_DIB13_CLKB_posedge or + Tviol_DIB14_CLKB_posedge or + Tviol_DIB15_CLKB_posedge or + Tviol_DIB16_CLKB_posedge or + Tviol_DIB17_CLKB_posedge or + Tviol_DIB18_CLKB_posedge or + Tviol_DIB19_CLKB_posedge or + Tviol_DIB20_CLKB_posedge or + Tviol_DIB21_CLKB_posedge or + Tviol_DIB22_CLKB_posedge or + Tviol_DIB23_CLKB_posedge or + Tviol_DIB24_CLKB_posedge or + Tviol_DIB25_CLKB_posedge or + Tviol_DIB26_CLKB_posedge or + Tviol_DIB27_CLKB_posedge or + Tviol_DIB28_CLKB_posedge or + Tviol_DIB29_CLKB_posedge or + Tviol_DIB30_CLKB_posedge or + Tviol_DIB31_CLKB_posedge or + Tviol_DIPB0_CLKB_posedge or + Tviol_DIPB1_CLKB_posedge or + Tviol_DIPB2_CLKB_posedge or + Tviol_DIPB3_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S36", + InstanceName => ramb16_s2_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S36", + InstanceName => ramb16_s2_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S36", + InstanceName => ramb16_s2_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S36", + InstanceName => ramb16_s2_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S36", + InstanceName => ramb16_s2_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S36", + InstanceName => ramb16_s2_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S36", + InstanceName => ramb16_s2_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(1 downto 0); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + DOPB_zd := DIPB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S36", + InstanceName => ramb16_s2_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S36", + InstanceName => ramb16_s2_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S36", + InstanceName => ramb16_s2_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S36", + InstanceName => ramb16_s2_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S36", + InstanceName => ramb16_s2_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S36", + InstanceName => ramb16_s2_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S36", + InstanceName => ramb16_s2_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(31 downto 0); + DOPB_zd := SRVA_B(35 downto 32); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOB_zd(8) := ViolationB xor DOB_zd(8); + DOB_zd(9) := ViolationB xor DOB_zd(9); + DOB_zd(10) := ViolationB xor DOB_zd(10); + DOB_zd(11) := ViolationB xor DOB_zd(11); + DOB_zd(12) := ViolationB xor DOB_zd(12); + DOB_zd(13) := ViolationB xor DOB_zd(13); + DOB_zd(14) := ViolationB xor DOB_zd(14); + DOB_zd(15) := ViolationB xor DOB_zd(15); + DOB_zd(16) := ViolationB xor DOB_zd(16); + DOB_zd(17) := ViolationB xor DOB_zd(17); + DOB_zd(18) := ViolationB xor DOB_zd(18); + DOB_zd(19) := ViolationB xor DOB_zd(19); + DOB_zd(20) := ViolationB xor DOB_zd(20); + DOB_zd(21) := ViolationB xor DOB_zd(21); + DOB_zd(22) := ViolationB xor DOB_zd(22); + DOB_zd(23) := ViolationB xor DOB_zd(23); + DOB_zd(24) := ViolationB xor DOB_zd(24); + DOB_zd(25) := ViolationB xor DOB_zd(25); + DOB_zd(26) := ViolationB xor DOB_zd(26); + DOB_zd(27) := ViolationB xor DOB_zd(27); + DOB_zd(28) := ViolationB xor DOB_zd(28); + DOB_zd(29) := ViolationB xor DOB_zd(29); + DOB_zd(30) := ViolationB xor DOB_zd(30); + DOB_zd(31) := ViolationB xor DOB_zd(31); + DOPB_zd(0) := ViolationB xor DOPB_zd(0); + DOPB_zd(1) := ViolationB xor DOPB_zd(1); + DOPB_zd(2) := ViolationB xor DOPB_zd(2); + DOPB_zd(3) := ViolationB xor DOPB_zd(3); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(8), + GlitchData => DOB_GlitchData8, + OutSignalName => "DOB(8)", + OutTemp => DOB_zd(8), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(9), + GlitchData => DOB_GlitchData9, + OutSignalName => "DOB(9)", + OutTemp => DOB_zd(9), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(10), + GlitchData => DOB_GlitchData10, + OutSignalName => "DOB(10)", + OutTemp => DOB_zd(10), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(11), + GlitchData => DOB_GlitchData11, + OutSignalName => "DOB(11)", + OutTemp => DOB_zd(11), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(12), + GlitchData => DOB_GlitchData12, + OutSignalName => "DOB(12)", + OutTemp => DOB_zd(12), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(13), + GlitchData => DOB_GlitchData13, + OutSignalName => "DOB(13)", + OutTemp => DOB_zd(13), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(14), + GlitchData => DOB_GlitchData14, + OutSignalName => "DOB(14)", + OutTemp => DOB_zd(14), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(15), + GlitchData => DOB_GlitchData15, + OutSignalName => "DOB(15)", + OutTemp => DOB_zd(15), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(16), + GlitchData => DOB_GlitchData16, + OutSignalName => "DOB(16)", + OutTemp => DOB_zd(16), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(16), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(17), + GlitchData => DOB_GlitchData17, + OutSignalName => "DOB(17)", + OutTemp => DOB_zd(17), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(17), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(18), + GlitchData => DOB_GlitchData18, + OutSignalName => "DOB(18)", + OutTemp => DOB_zd(18), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(18), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(19), + GlitchData => DOB_GlitchData19, + OutSignalName => "DOB(19)", + OutTemp => DOB_zd(19), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(19), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(20), + GlitchData => DOB_GlitchData20, + OutSignalName => "DOB(20)", + OutTemp => DOB_zd(20), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(20), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(21), + GlitchData => DOB_GlitchData21, + OutSignalName => "DOB(21)", + OutTemp => DOB_zd(21), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(21), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(22), + GlitchData => DOB_GlitchData22, + OutSignalName => "DOB(22)", + OutTemp => DOB_zd(22), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(22), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(23), + GlitchData => DOB_GlitchData23, + OutSignalName => "DOB(23)", + OutTemp => DOB_zd(23), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(23), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(24), + GlitchData => DOB_GlitchData24, + OutSignalName => "DOB(24)", + OutTemp => DOB_zd(24), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(24), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(25), + GlitchData => DOB_GlitchData25, + OutSignalName => "DOB(25)", + OutTemp => DOB_zd(25), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(25), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(26), + GlitchData => DOB_GlitchData26, + OutSignalName => "DOB(26)", + OutTemp => DOB_zd(26), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(26), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(27), + GlitchData => DOB_GlitchData27, + OutSignalName => "DOB(27)", + OutTemp => DOB_zd(27), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(27), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(28), + GlitchData => DOB_GlitchData28, + OutSignalName => "DOB(28)", + OutTemp => DOB_zd(28), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(28), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(29), + GlitchData => DOB_GlitchData29, + OutSignalName => "DOB(29)", + OutTemp => DOB_zd(29), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(29), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(30), + GlitchData => DOB_GlitchData30, + OutSignalName => "DOB(30)", + OutTemp => DOB_zd(30), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(30), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(31), + GlitchData => DOB_GlitchData31, + OutSignalName => "DOB(31)", + OutTemp => DOB_zd(31), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(31), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(0), + GlitchData => DOPB_GlitchData0, + OutSignalName => "DOPB(0)", + OutTemp => DOPB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(1), + GlitchData => DOPB_GlitchData1, + OutSignalName => "DOPB(1)", + OutTemp => DOPB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(2), + GlitchData => DOPB_GlitchData2, + OutSignalName => "DOPB(2)", + OutTemp => DOPB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(3), + GlitchData => DOPB_GlitchData3, + OutSignalName => "DOPB(3)", + OutTemp => DOPB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S2_S36_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S2_S4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s2_s4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S2_S4 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(12 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(11 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"0"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"0"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(1 downto 0); + DOB : out std_logic_vector(3 downto 0); + + ADDRA : in std_logic_vector(12 downto 0); + ADDRB : in std_logic_vector(11 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(1 downto 0); + DIB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S2_S4 : entity is true; +end ramb16_s2_s4; + +architecture RAMB16_S2_S4_V of RAMB16_S2_S4 is + attribute VITAL_LEVEL0 of + RAMB16_S2_S4_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(12 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(11 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 8192; + constant length_b : integer := 4096; + constant width_a : integer := 2; + constant width_b : integer := 4; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 12 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 11 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (1 downto 0) := "00"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (3 downto 0) := "0000"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (1 downto 0) := "00"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (3 downto 0) := "0000"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(1 downto 0) := INI_A(1 downto 0); + variable DOB_zd : std_logic_vector(3 downto 0) := INI_B(3 downto 0); + + variable ADDRA_ipd_sampled : std_logic_vector(12 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S2_S4", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 2) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(1 downto 0) := INI_A_UNBOUND(1 downto 0); + + for I in INI_A_UNBOUND'high downto 2 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 2 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S2_S4", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 2) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S2_S4", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 2) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 4) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(3 downto 0) := INI_B_UNBOUND(3 downto 0); + + for I in INI_B_UNBOUND'high downto 4 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 4 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S2_S4", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 4) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S2_S4", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 4) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 2) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(1 downto 0) := SRVA_A_UNBOUND(1 downto 0); + + for I in SRVA_A_UNBOUND'high downto 2 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 2 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S2_S4", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 2) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S2_S4", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 2) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 4) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(3 downto 0) := SRVA_B_UNBOUND(3 downto 0); + + for I in SRVA_B_UNBOUND'high downto 4 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 4 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S2_S4", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 4) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S2_S4", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 4) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(1 downto 0) := INI_A(1 downto 0); + DOB_zd(3 downto 0) := INI_B(3 downto 0); + DOA <= DOA_zd; + DOB <= DOB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S2_S4", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S2_S4", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA11_CLKA_posedge, + TimingData => Tmkr_ADDRA11_CLKA_posedge, + TestSignal => ADDRA_ipd(11), + TestSignalName => "ADDRA(11)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(11), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(11), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(11), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(11), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB9_CLKB_posedge, + TimingData => Tmkr_ADDRB9_CLKB_posedge, + TestSignal => ADDRB_ipd(9), + TestSignalName => "ADDRB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(9), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(9), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(9), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(9), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB10_CLKB_posedge, + TimingData => Tmkr_ADDRB10_CLKB_posedge, + TestSignal => ADDRB_ipd(10), + TestSignalName => "ADDRB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(10), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(10), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(10), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(10), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_ADDRA12_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_ADDRB10_CLKB_posedge or + Tviol_ADDRB11_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S4", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S4", + InstanceName => ramb16_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S4", + InstanceName => ramb16_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S4", + InstanceName => ramb16_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S4", + InstanceName => ramb16_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S4", + InstanceName => ramb16_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S4", + InstanceName => ramb16_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S4", + InstanceName => ramb16_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(1 downto 0); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S4", + InstanceName => ramb16_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S4", + InstanceName => ramb16_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S4", + InstanceName => ramb16_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S4", + InstanceName => ramb16_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S4", + InstanceName => ramb16_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S4", + InstanceName => ramb16_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S4", + InstanceName => ramb16_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(3 downto 0); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + end if; + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S2_S4_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S2_S9.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s2_s9 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S2_S9 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(12 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(10 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPB : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOPB : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(12 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"000"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(1 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPB : out std_logic_vector(0 downto 0); + + ADDRA : in std_logic_vector(12 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(1 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S2_S9 : entity is true; +end ramb16_s2_s9; + +architecture RAMB16_S2_S9_V of RAMB16_S2_S9 is + attribute VITAL_LEVEL0 of + RAMB16_S2_S9_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(12 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(10 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(7 downto 0) := (others => 'X'); + signal DIPB_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 8192; + constant length_b : integer := 2048; + constant width_a : integer := 2; + constant width_b : integer := 8; + + constant parity_width_b : integer := 1; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + + function slv_to_two_D_parity_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_parity_array_type is + variable two_D_parity_array : two_D_parity_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_parity_array(i) := intermediate; + end loop; + return two_D_parity_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 12 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 10 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 7 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + DIPB_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i)); + end generate DIPB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA12_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOPB_GlitchData0 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) & + To_StdLogicVector(INITP_06) & + To_StdLogicVector(INITP_05) & + To_StdLogicVector(INITP_04) & + To_StdLogicVector(INITP_03) & + To_StdLogicVector(INITP_02) & + To_StdLogicVector(INITP_01) & + To_StdLogicVector(INITP_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOPB_OV_LSB : integer := 0; + variable DOPB_OV_MSB : integer := 0; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (1 downto 0) := "00"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (8 downto 0) := "000000000"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (1 downto 0) := "00"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (8 downto 0) := "000000000"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(1 downto 0) := INI_A(1 downto 0); + variable DOB_zd : std_logic_vector(7 downto 0) := INI_B(7 downto 0); + variable DOPB_zd : std_logic_vector(0 downto 0) := INI_B(8 downto 8); + + variable ADDRA_ipd_sampled : std_logic_vector(12 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S2_S9", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 2) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(1 downto 0) := INI_A_UNBOUND(1 downto 0); + + for I in INI_A_UNBOUND'high downto 2 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 2 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S2_S9", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 2) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S2_S9", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 2) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 9) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(8 downto 0) := INI_B_UNBOUND(8 downto 0); + + for I in INI_B_UNBOUND'high downto 9 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 9 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S2_S9", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 9) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S2_S9", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 9) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 2) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(1 downto 0) := SRVA_A_UNBOUND(1 downto 0); + + for I in SRVA_A_UNBOUND'high downto 2 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 2 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S2_S9", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 2) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S2_S9", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 2, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 2) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 9) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(8 downto 0) := SRVA_B_UNBOUND(8 downto 0); + + for I in SRVA_B_UNBOUND'high downto 9 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 9 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S2_S9", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 9) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S2_S9", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 9) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(1 downto 0) := INI_A(1 downto 0); + DOB_zd(7 downto 0) := INI_B(7 downto 0); + DOPB_zd(0 downto 0) := INI_B(8 downto 8); + DOA <= DOA_zd; + DOB <= DOB_zd; + DOPB <= DOPB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S2_S9", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S2_S9", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA11_CLKA_posedge, + TimingData => Tmkr_ADDRA11_CLKA_posedge, + TestSignal => ADDRA_ipd(11), + TestSignalName => "ADDRA(11)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(11), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(11), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(11), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(11), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB9_CLKB_posedge, + TimingData => Tmkr_ADDRB9_CLKB_posedge, + TestSignal => ADDRB_ipd(9), + TestSignalName => "ADDRB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(9), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(9), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(9), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(9), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S2_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_ADDRA12_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_ADDRB10_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIPB0_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S2_S9", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S9", + InstanceName => ramb16_s2_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S9", + InstanceName => ramb16_s2_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S9", + InstanceName => ramb16_s2_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S9", + InstanceName => ramb16_s2_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S9", + InstanceName => ramb16_s2_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S9", + InstanceName => ramb16_s2_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S9", + InstanceName => ramb16_s2_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(1 downto 0); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + DOPB_zd := DIPB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S9", + InstanceName => ramb16_s2_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S9", + InstanceName => ramb16_s2_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S9", + InstanceName => ramb16_s2_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S9", + InstanceName => ramb16_s2_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S2_S9", + InstanceName => ramb16_s2_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S2_S9", + InstanceName => ramb16_s2_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S2_S9", + InstanceName => ramb16_s2_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(7 downto 0); + DOPB_zd := SRVA_B(8 downto 8); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOPB_zd(0) := ViolationB xor DOPB_zd(0); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(0), + GlitchData => DOPB_GlitchData0, + OutSignalName => "DOPB(0)", + OutTemp => DOPB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S2_S9_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb16_s36.vhd,v 1.8 2005/10/07 18:35:24 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +-- /___/ /\ Filename : RAMB16_S36.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:52 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 09/26/05 - Fixed CR# 216846. INIT and SRVAL attributes length check and adjustment. +-- END Revision + +----- CELL RAMB16_S36 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S36 is + + generic ( + INIT : bit_vector := X"000000000"; + SRVAL : bit_vector := X"000000000"; + WRITE_MODE : string := "WRITE_FIRST"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + + port ( + DO : out STD_LOGIC_VECTOR (31 downto 0); + DOP : out STD_LOGIC_VECTOR (3 downto 0); + + ADDR : in STD_LOGIC_VECTOR (8 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (31 downto 0); + DIP : in STD_LOGIC_VECTOR (3 downto 0); + EN : in STD_ULOGIC; + SSR : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end RAMB16_S36; + +architecture RAMB16_S36_V of RAMB16_S36 is + constant length : integer := 512; + constant width : integer := 32; + + constant parity_width : integer := 4; + + type Two_D_array_type is array ((length - 1) downto 0) of std_logic_vector((width - 1) downto 0); + type Two_D_parity_array_type is array ((length - 1) downto 0) of std_logic_vector((parity_width - 1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + + function slv_to_two_D_parity_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_parity_array_type is + variable two_D_parity_array : two_D_parity_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_parity_array(i) := intermediate; + end loop; + return two_D_parity_array; + end; +begin + VITALBehavior : process + variable address : integer; + variable valid_addr : boolean := FALSE; + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F & INIT_3E & INIT_3D & INIT_3C & + INIT_3B & INIT_3A & INIT_39 & INIT_38 & + INIT_37 & INIT_36 & INIT_35 & INIT_34 & + INIT_33 & INIT_32 & INIT_31 & INIT_30 & + INIT_2F & INIT_2E & INIT_2D & INIT_2C & + INIT_2B & INIT_2A & INIT_29 & INIT_28 & + INIT_27 & INIT_26 & INIT_25 & INIT_24 & + INIT_23 & INIT_22 & INIT_21 & INIT_20 & + INIT_1F & INIT_1E & INIT_1D & INIT_1C & + INIT_1B & INIT_1A & INIT_19 & INIT_18 & + INIT_17 & INIT_16 & INIT_15 & INIT_14 & + INIT_13 & INIT_12 & INIT_11 & INIT_10 & + INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + + variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07 & INITP_06 & INITP_05 & INITP_04 & + INITP_03 & INITP_02 & INITP_01 & INITP_00); + variable mem : Two_D_array_type := slv_to_two_D_array(length, width, mem_slv); + variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length, parity_width, memp_slv); + + variable wr_mode : integer := 0; + variable first_time : boolean := true; + + variable INIT_reg : std_logic_vector (35 downto 0) := "000000000000000000000000000000000000"; + variable SRVAL_reg : std_logic_vector (35 downto 0) := "000000000000000000000000000000000000"; + + begin + if (first_time) then + if ((WRITE_MODE = "write_first") or (WRITE_MODE = "WRITE_FIRST")) then + wr_mode := 0; + elsif ((WRITE_MODE = "read_first") or (WRITE_MODE = "READ_FIRST")) then + wr_mode := 1; + elsif ((WRITE_MODE = "no_change") or (WRITE_MODE = "NO_CHANGE")) then + wr_mode := 2; + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Error ", + GenericName => " WRITE_MODE ", + EntityName => "/RAMB16_S36", + GenericValue => WRITE_MODE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT'length > 36) then + INIT_reg(35 downto 0) := To_StdLogicVector(INIT)(35 downto 0); + else + INIT_reg(INIT'length-1 downto 0) := To_StdLogicVector(INIT); + end if; + + DO <= INIT_reg(31 downto 0); + DOP <= INIT_reg(35 downto 32); + + if (SRVAL'length > 36) then + SRVAL_reg(35 downto 0) := To_StdLogicVector(SRVAL)(35 downto 0); + else + SRVAL_reg(SRVAL'length-1 downto 0) := To_StdLogicVector(SRVAL); + end if; + + first_time := false; + end if; + + valid_addr := addr_is_valid(addr); + + if (valid_addr) then + address := slv_to_int(addr); + end if; + + if (rising_edge(CLK)) then + if (EN = '1') then + if (SSR = '1') then + DO <= SRVAL_reg(31 downto 0) after 100 ps; + DOP <= SRVAL_reg(35 downto 32) after 100 ps; + else + if (WE = '1') then + if (wr_mode = 0) then + DO <= DI after 100 ps; + DOP <= DIP after 100 ps; + elsif (wr_mode = 1) then + DO <= mem(address) after 100 ps; + DOP <= memp(address) after 100 ps; + end if; + else + if (valid_addr) then + DO <= mem(address) after 100 ps; + DOP <= memp(address) after 100 ps; + end if; + end if; + end if; + if (WE = '1') then + if (valid_addr) then + mem(address) := DI; + memp(address) := DIP; + end if; + end if; + end if; + end if; + wait on CLK; + end process VITALBehavior; + +end RAMB16_S36_V; + + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S36_S36.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s36_s36 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S36_S36 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(8 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPA : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(8 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPB : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(31 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKA_DOPA : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(31 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOPB : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + tsetup_DIPA_CLKA_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIPA_CLKA_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + thold_DIPA_CLKA_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIPA_CLKA_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S36_S36 : entity is true; +end ramb16_s36_s36; + +architecture RAMB16_S36_S36_V of RAMB16_S36_S36 is + attribute VITAL_LEVEL0 of + RAMB16_S36_S36_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(8 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(31 downto 0) := (others => 'X'); + signal DIPA_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(8 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(31 downto 0) := (others => 'X'); + signal DIPB_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 512; + constant length_b : integer := 512; + constant width_a : integer := 32; + constant width_b : integer := 32; + + constant parity_width_a : integer := 4; + constant parity_width_b : integer := 4; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + + function slv_to_two_D_parity_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_parity_array_type is + variable two_D_parity_array : two_D_parity_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_parity_array(i) := intermediate; + end loop; + return two_D_parity_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 8 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 31 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + DIPA_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIPA_ipd(i), DIPA(i), tipd_DIPA(i)); + end generate DIPA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 8 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 31 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + DIPB_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i)); + end generate DIPB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA12_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA13_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA14_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA15_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA16_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA17_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA18_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA19_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA20_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA21_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA22_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA23_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA24_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA25_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA26_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA27_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA28_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA29_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA30_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA31_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIPA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIPA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIPA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIPA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB12_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB13_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB14_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB15_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB16_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB17_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB18_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB19_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB20_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB21_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB22_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB23_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB24_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB25_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB26_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB27_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB28_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB29_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB30_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB31_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA13_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA14_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA15_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA16_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA17_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA18_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA19_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA20_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA21_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA22_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA23_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA24_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA25_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA26_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA27_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA28_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA29_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA30_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA31_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB13_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB14_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB15_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB16_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB17_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB18_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB19_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB20_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB21_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB22_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB23_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB24_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB25_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB26_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB27_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB28_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB29_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB30_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB31_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + variable DOA_GlitchData2 : VitalGlitchDataType; + variable DOA_GlitchData3 : VitalGlitchDataType; + variable DOA_GlitchData4 : VitalGlitchDataType; + variable DOA_GlitchData5 : VitalGlitchDataType; + variable DOA_GlitchData6 : VitalGlitchDataType; + variable DOA_GlitchData7 : VitalGlitchDataType; + variable DOA_GlitchData8 : VitalGlitchDataType; + variable DOA_GlitchData9 : VitalGlitchDataType; + variable DOA_GlitchData10 : VitalGlitchDataType; + variable DOA_GlitchData11 : VitalGlitchDataType; + variable DOA_GlitchData12 : VitalGlitchDataType; + variable DOA_GlitchData13 : VitalGlitchDataType; + variable DOA_GlitchData14 : VitalGlitchDataType; + variable DOA_GlitchData15 : VitalGlitchDataType; + variable DOA_GlitchData16 : VitalGlitchDataType; + variable DOA_GlitchData17 : VitalGlitchDataType; + variable DOA_GlitchData18 : VitalGlitchDataType; + variable DOA_GlitchData19 : VitalGlitchDataType; + variable DOA_GlitchData20 : VitalGlitchDataType; + variable DOA_GlitchData21 : VitalGlitchDataType; + variable DOA_GlitchData22 : VitalGlitchDataType; + variable DOA_GlitchData23 : VitalGlitchDataType; + variable DOA_GlitchData24 : VitalGlitchDataType; + variable DOA_GlitchData25 : VitalGlitchDataType; + variable DOA_GlitchData26 : VitalGlitchDataType; + variable DOA_GlitchData27 : VitalGlitchDataType; + variable DOA_GlitchData28 : VitalGlitchDataType; + variable DOA_GlitchData29 : VitalGlitchDataType; + variable DOA_GlitchData30 : VitalGlitchDataType; + variable DOA_GlitchData31 : VitalGlitchDataType; + variable DOPA_GlitchData0 : VitalGlitchDataType; + variable DOPA_GlitchData1 : VitalGlitchDataType; + variable DOPA_GlitchData2 : VitalGlitchDataType; + variable DOPA_GlitchData3 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOB_GlitchData8 : VitalGlitchDataType; + variable DOB_GlitchData9 : VitalGlitchDataType; + variable DOB_GlitchData10 : VitalGlitchDataType; + variable DOB_GlitchData11 : VitalGlitchDataType; + variable DOB_GlitchData12 : VitalGlitchDataType; + variable DOB_GlitchData13 : VitalGlitchDataType; + variable DOB_GlitchData14 : VitalGlitchDataType; + variable DOB_GlitchData15 : VitalGlitchDataType; + variable DOB_GlitchData16 : VitalGlitchDataType; + variable DOB_GlitchData17 : VitalGlitchDataType; + variable DOB_GlitchData18 : VitalGlitchDataType; + variable DOB_GlitchData19 : VitalGlitchDataType; + variable DOB_GlitchData20 : VitalGlitchDataType; + variable DOB_GlitchData21 : VitalGlitchDataType; + variable DOB_GlitchData22 : VitalGlitchDataType; + variable DOB_GlitchData23 : VitalGlitchDataType; + variable DOB_GlitchData24 : VitalGlitchDataType; + variable DOB_GlitchData25 : VitalGlitchDataType; + variable DOB_GlitchData26 : VitalGlitchDataType; + variable DOB_GlitchData27 : VitalGlitchDataType; + variable DOB_GlitchData28 : VitalGlitchDataType; + variable DOB_GlitchData29 : VitalGlitchDataType; + variable DOB_GlitchData30 : VitalGlitchDataType; + variable DOB_GlitchData31 : VitalGlitchDataType; + variable DOPB_GlitchData0 : VitalGlitchDataType; + variable DOPB_GlitchData1 : VitalGlitchDataType; + variable DOPB_GlitchData2 : VitalGlitchDataType; + variable DOPB_GlitchData3 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) & + To_StdLogicVector(INITP_06) & + To_StdLogicVector(INITP_05) & + To_StdLogicVector(INITP_04) & + To_StdLogicVector(INITP_03) & + To_StdLogicVector(INITP_02) & + To_StdLogicVector(INITP_01) & + To_StdLogicVector(INITP_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOPA_OV_LSB : integer := 0; + variable DOPA_OV_MSB : integer := 3; + variable DOPB_OV_LSB : integer := 0; + variable DOPB_OV_MSB : integer := 3; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (35 downto 0) := "000000000000000000000000000000000000"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (35 downto 0) := "000000000000000000000000000000000000"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (35 downto 0) := "000000000000000000000000000000000000"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (35 downto 0) := "000000000000000000000000000000000000"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(31 downto 0) := INI_A(31 downto 0); + variable DOB_zd : std_logic_vector(31 downto 0) := INI_B(31 downto 0); + variable DOPA_zd : std_logic_vector(3 downto 0) := INI_A(35 downto 32); + variable DOPB_zd : std_logic_vector(3 downto 0) := INI_B(35 downto 32); + + variable ADDRA_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S36_S36", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 36) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(35 downto 0) := INI_A_UNBOUND(35 downto 0); + + for I in INI_A_UNBOUND'high downto 36 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 36 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S36_S36", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 36) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S36_S36", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 36) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 36) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(35 downto 0) := INI_B_UNBOUND(35 downto 0); + + for I in INI_B_UNBOUND'high downto 36 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 36 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S36_S36", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S36_S36", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 36) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(35 downto 0) := SRVA_A_UNBOUND(35 downto 0); + + for I in SRVA_A_UNBOUND'high downto 36 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 36 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S36_S36", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 36) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S36_S36", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 36) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 36) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(35 downto 0) := SRVA_B_UNBOUND(35 downto 0); + + for I in SRVA_B_UNBOUND'high downto 36 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 36 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S36_S36", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S36_S36", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(31 downto 0) := INI_A(31 downto 0); + DOB_zd(31 downto 0) := INI_B(31 downto 0); + DOPA_zd(3 downto 0) := INI_A(35 downto 32); + DOPB_zd(3 downto 0) := INI_B(35 downto 32); + DOA <= DOA_zd; + DOPA <= DOPA_zd; + DOB <= DOB_zd; + DOPB <= DOPB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S36_S36", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S36_S36", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPA0_CLKA_posedge, + TimingData => Tmkr_DIPA0_CLKA_posedge, + TestSignal => DIPA_ipd(0), + TestSignalName => "DIPA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIPA_CLKA_negedge_posedge(0), + HoldLow => thold_DIPA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIPA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPA1_CLKA_posedge, + TimingData => Tmkr_DIPA1_CLKA_posedge, + TestSignal => DIPA_ipd(1), + TestSignalName => "DIPA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPA_CLKA_posedge_posedge(1), + SetupLow => tsetup_DIPA_CLKA_negedge_posedge(1), + HoldLow => thold_DIPA_CLKA_posedge_posedge(1), + HoldHigh => thold_DIPA_CLKA_negedge_posedge(1), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPA2_CLKA_posedge, + TimingData => Tmkr_DIPA2_CLKA_posedge, + TestSignal => DIPA_ipd(2), + TestSignalName => "DIPA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPA_CLKA_posedge_posedge(2), + SetupLow => tsetup_DIPA_CLKA_negedge_posedge(2), + HoldLow => thold_DIPA_CLKA_posedge_posedge(2), + HoldHigh => thold_DIPA_CLKA_negedge_posedge(2), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA1_CLKA_posedge, + TimingData => Tmkr_DIA1_CLKA_posedge, + TestSignal => DIA_ipd(1), + TestSignalName => "DIA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(1), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(1), + HoldLow => thold_DIA_CLKA_posedge_posedge(1), + HoldHigh => thold_DIA_CLKA_negedge_posedge(1), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA2_CLKA_posedge, + TimingData => Tmkr_DIA2_CLKA_posedge, + TestSignal => DIA_ipd(2), + TestSignalName => "DIA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(2), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(2), + HoldLow => thold_DIA_CLKA_posedge_posedge(2), + HoldHigh => thold_DIA_CLKA_negedge_posedge(2), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA3_CLKA_posedge, + TimingData => Tmkr_DIA3_CLKA_posedge, + TestSignal => DIA_ipd(3), + TestSignalName => "DIA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(3), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(3), + HoldLow => thold_DIA_CLKA_posedge_posedge(3), + HoldHigh => thold_DIA_CLKA_negedge_posedge(3), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA4_CLKA_posedge, + TimingData => Tmkr_DIA4_CLKA_posedge, + TestSignal => DIA_ipd(4), + TestSignalName => "DIA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(4), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(4), + HoldLow => thold_DIA_CLKA_posedge_posedge(4), + HoldHigh => thold_DIA_CLKA_negedge_posedge(4), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA5_CLKA_posedge, + TimingData => Tmkr_DIA5_CLKA_posedge, + TestSignal => DIA_ipd(5), + TestSignalName => "DIA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(5), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(5), + HoldLow => thold_DIA_CLKA_posedge_posedge(5), + HoldHigh => thold_DIA_CLKA_negedge_posedge(5), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA6_CLKA_posedge, + TimingData => Tmkr_DIA6_CLKA_posedge, + TestSignal => DIA_ipd(6), + TestSignalName => "DIA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(6), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(6), + HoldLow => thold_DIA_CLKA_posedge_posedge(6), + HoldHigh => thold_DIA_CLKA_negedge_posedge(6), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA7_CLKA_posedge, + TimingData => Tmkr_DIA7_CLKA_posedge, + TestSignal => DIA_ipd(7), + TestSignalName => "DIA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(7), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(7), + HoldLow => thold_DIA_CLKA_posedge_posedge(7), + HoldHigh => thold_DIA_CLKA_negedge_posedge(7), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA8_CLKA_posedge, + TimingData => Tmkr_DIA8_CLKA_posedge, + TestSignal => DIA_ipd(8), + TestSignalName => "DIA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(8), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(8), + HoldLow => thold_DIA_CLKA_posedge_posedge(8), + HoldHigh => thold_DIA_CLKA_negedge_posedge(8), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA9_CLKA_posedge, + TimingData => Tmkr_DIA9_CLKA_posedge, + TestSignal => DIA_ipd(9), + TestSignalName => "DIA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(9), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(9), + HoldLow => thold_DIA_CLKA_posedge_posedge(9), + HoldHigh => thold_DIA_CLKA_negedge_posedge(9), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA10_CLKA_posedge, + TimingData => Tmkr_DIA10_CLKA_posedge, + TestSignal => DIA_ipd(10), + TestSignalName => "DIA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(10), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(10), + HoldLow => thold_DIA_CLKA_posedge_posedge(10), + HoldHigh => thold_DIA_CLKA_negedge_posedge(10), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA11_CLKA_posedge, + TimingData => Tmkr_DIA11_CLKA_posedge, + TestSignal => DIA_ipd(11), + TestSignalName => "DIA(11)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(11), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(11), + HoldLow => thold_DIA_CLKA_posedge_posedge(11), + HoldHigh => thold_DIA_CLKA_negedge_posedge(11), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA12_CLKA_posedge, + TimingData => Tmkr_DIA12_CLKA_posedge, + TestSignal => DIA_ipd(12), + TestSignalName => "DIA(12)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(12), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(12), + HoldLow => thold_DIA_CLKA_posedge_posedge(12), + HoldHigh => thold_DIA_CLKA_negedge_posedge(12), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA13_CLKA_posedge, + TimingData => Tmkr_DIA13_CLKA_posedge, + TestSignal => DIA_ipd(13), + TestSignalName => "DIA(13)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(13), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(13), + HoldLow => thold_DIA_CLKA_posedge_posedge(13), + HoldHigh => thold_DIA_CLKA_negedge_posedge(13), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA14_CLKA_posedge, + TimingData => Tmkr_DIA14_CLKA_posedge, + TestSignal => DIA_ipd(14), + TestSignalName => "DIA(14)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(14), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(14), + HoldLow => thold_DIA_CLKA_posedge_posedge(14), + HoldHigh => thold_DIA_CLKA_negedge_posedge(14), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA15_CLKA_posedge, + TimingData => Tmkr_DIA15_CLKA_posedge, + TestSignal => DIA_ipd(15), + TestSignalName => "DIA(15)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(15), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(15), + HoldLow => thold_DIA_CLKA_posedge_posedge(15), + HoldHigh => thold_DIA_CLKA_negedge_posedge(15), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA16_CLKA_posedge, + TimingData => Tmkr_DIA16_CLKA_posedge, + TestSignal => DIA_ipd(16), + TestSignalName => "DIA(16)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(16), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(16), + HoldLow => thold_DIA_CLKA_posedge_posedge(16), + HoldHigh => thold_DIA_CLKA_negedge_posedge(16), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA17_CLKA_posedge, + TimingData => Tmkr_DIA17_CLKA_posedge, + TestSignal => DIA_ipd(17), + TestSignalName => "DIA(17)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(17), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(17), + HoldLow => thold_DIA_CLKA_posedge_posedge(17), + HoldHigh => thold_DIA_CLKA_negedge_posedge(17), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA18_CLKA_posedge, + TimingData => Tmkr_DIA18_CLKA_posedge, + TestSignal => DIA_ipd(18), + TestSignalName => "DIA(18)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(18), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(18), + HoldLow => thold_DIA_CLKA_posedge_posedge(18), + HoldHigh => thold_DIA_CLKA_negedge_posedge(18), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA19_CLKA_posedge, + TimingData => Tmkr_DIA19_CLKA_posedge, + TestSignal => DIA_ipd(19), + TestSignalName => "DIA(19)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(19), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(19), + HoldLow => thold_DIA_CLKA_posedge_posedge(19), + HoldHigh => thold_DIA_CLKA_negedge_posedge(19), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA20_CLKA_posedge, + TimingData => Tmkr_DIA20_CLKA_posedge, + TestSignal => DIA_ipd(20), + TestSignalName => "DIA(20)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(20), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(20), + HoldLow => thold_DIA_CLKA_posedge_posedge(20), + HoldHigh => thold_DIA_CLKA_negedge_posedge(20), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA21_CLKA_posedge, + TimingData => Tmkr_DIA21_CLKA_posedge, + TestSignal => DIA_ipd(21), + TestSignalName => "DIA(21)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(21), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(21), + HoldLow => thold_DIA_CLKA_posedge_posedge(21), + HoldHigh => thold_DIA_CLKA_negedge_posedge(21), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA22_CLKA_posedge, + TimingData => Tmkr_DIA22_CLKA_posedge, + TestSignal => DIA_ipd(22), + TestSignalName => "DIA(22)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(22), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(22), + HoldLow => thold_DIA_CLKA_posedge_posedge(22), + HoldHigh => thold_DIA_CLKA_negedge_posedge(22), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA23_CLKA_posedge, + TimingData => Tmkr_DIA23_CLKA_posedge, + TestSignal => DIA_ipd(23), + TestSignalName => "DIA(23)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(23), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(23), + HoldLow => thold_DIA_CLKA_posedge_posedge(23), + HoldHigh => thold_DIA_CLKA_negedge_posedge(23), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA24_CLKA_posedge, + TimingData => Tmkr_DIA24_CLKA_posedge, + TestSignal => DIA_ipd(24), + TestSignalName => "DIA(24)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(24), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(24), + HoldLow => thold_DIA_CLKA_posedge_posedge(24), + HoldHigh => thold_DIA_CLKA_negedge_posedge(24), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA25_CLKA_posedge, + TimingData => Tmkr_DIA25_CLKA_posedge, + TestSignal => DIA_ipd(25), + TestSignalName => "DIA(25)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(25), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(25), + HoldLow => thold_DIA_CLKA_posedge_posedge(25), + HoldHigh => thold_DIA_CLKA_negedge_posedge(25), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA26_CLKA_posedge, + TimingData => Tmkr_DIA26_CLKA_posedge, + TestSignal => DIA_ipd(26), + TestSignalName => "DIA(26)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(26), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(26), + HoldLow => thold_DIA_CLKA_posedge_posedge(26), + HoldHigh => thold_DIA_CLKA_negedge_posedge(26), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA27_CLKA_posedge, + TimingData => Tmkr_DIA27_CLKA_posedge, + TestSignal => DIA_ipd(27), + TestSignalName => "DIA(27)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(27), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(27), + HoldLow => thold_DIA_CLKA_posedge_posedge(27), + HoldHigh => thold_DIA_CLKA_negedge_posedge(27), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA28_CLKA_posedge, + TimingData => Tmkr_DIA28_CLKA_posedge, + TestSignal => DIA_ipd(28), + TestSignalName => "DIA(28)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(28), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(28), + HoldLow => thold_DIA_CLKA_posedge_posedge(28), + HoldHigh => thold_DIA_CLKA_negedge_posedge(28), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA29_CLKA_posedge, + TimingData => Tmkr_DIA29_CLKA_posedge, + TestSignal => DIA_ipd(29), + TestSignalName => "DIA(29)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(29), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(29), + HoldLow => thold_DIA_CLKA_posedge_posedge(29), + HoldHigh => thold_DIA_CLKA_negedge_posedge(29), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA30_CLKA_posedge, + TimingData => Tmkr_DIA30_CLKA_posedge, + TestSignal => DIA_ipd(30), + TestSignalName => "DIA(30)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(30), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(30), + HoldLow => thold_DIA_CLKA_posedge_posedge(30), + HoldHigh => thold_DIA_CLKA_negedge_posedge(30), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB0_CLKB_posedge, + TimingData => Tmkr_DIPB0_CLKB_posedge, + TestSignal => DIPB_ipd(0), + TestSignalName => "DIPB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(0), + HoldLow => thold_DIPB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB1_CLKB_posedge, + TimingData => Tmkr_DIPB1_CLKB_posedge, + TestSignal => DIPB_ipd(1), + TestSignalName => "DIPB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(1), + HoldLow => thold_DIPB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB2_CLKB_posedge, + TimingData => Tmkr_DIPB2_CLKB_posedge, + TestSignal => DIPB_ipd(2), + TestSignalName => "DIPB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(2), + HoldLow => thold_DIPB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB7_CLKB_posedge, + TimingData => Tmkr_DIB7_CLKB_posedge, + TestSignal => DIB_ipd(7), + TestSignalName => "DIB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(7), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(7), + HoldLow => thold_DIB_CLKB_posedge_posedge(7), + HoldHigh => thold_DIB_CLKB_negedge_posedge(7), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB8_CLKB_posedge, + TimingData => Tmkr_DIB8_CLKB_posedge, + TestSignal => DIB_ipd(8), + TestSignalName => "DIB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(8), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(8), + HoldLow => thold_DIB_CLKB_posedge_posedge(8), + HoldHigh => thold_DIB_CLKB_negedge_posedge(8), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB9_CLKB_posedge, + TimingData => Tmkr_DIB9_CLKB_posedge, + TestSignal => DIB_ipd(9), + TestSignalName => "DIB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(9), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(9), + HoldLow => thold_DIB_CLKB_posedge_posedge(9), + HoldHigh => thold_DIB_CLKB_negedge_posedge(9), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB10_CLKB_posedge, + TimingData => Tmkr_DIB10_CLKB_posedge, + TestSignal => DIB_ipd(10), + TestSignalName => "DIB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(10), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(10), + HoldLow => thold_DIB_CLKB_posedge_posedge(10), + HoldHigh => thold_DIB_CLKB_negedge_posedge(10), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB11_CLKB_posedge, + TimingData => Tmkr_DIB11_CLKB_posedge, + TestSignal => DIB_ipd(11), + TestSignalName => "DIB(11)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(11), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(11), + HoldLow => thold_DIB_CLKB_posedge_posedge(11), + HoldHigh => thold_DIB_CLKB_negedge_posedge(11), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB12_CLKB_posedge, + TimingData => Tmkr_DIB12_CLKB_posedge, + TestSignal => DIB_ipd(12), + TestSignalName => "DIB(12)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(12), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(12), + HoldLow => thold_DIB_CLKB_posedge_posedge(12), + HoldHigh => thold_DIB_CLKB_negedge_posedge(12), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB13_CLKB_posedge, + TimingData => Tmkr_DIB13_CLKB_posedge, + TestSignal => DIB_ipd(13), + TestSignalName => "DIB(13)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(13), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(13), + HoldLow => thold_DIB_CLKB_posedge_posedge(13), + HoldHigh => thold_DIB_CLKB_negedge_posedge(13), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB14_CLKB_posedge, + TimingData => Tmkr_DIB14_CLKB_posedge, + TestSignal => DIB_ipd(14), + TestSignalName => "DIB(14)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(14), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(14), + HoldLow => thold_DIB_CLKB_posedge_posedge(14), + HoldHigh => thold_DIB_CLKB_negedge_posedge(14), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB15_CLKB_posedge, + TimingData => Tmkr_DIB15_CLKB_posedge, + TestSignal => DIB_ipd(15), + TestSignalName => "DIB(15)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(15), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(15), + HoldLow => thold_DIB_CLKB_posedge_posedge(15), + HoldHigh => thold_DIB_CLKB_negedge_posedge(15), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB16_CLKB_posedge, + TimingData => Tmkr_DIB16_CLKB_posedge, + TestSignal => DIB_ipd(16), + TestSignalName => "DIB(16)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(16), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(16), + HoldLow => thold_DIB_CLKB_posedge_posedge(16), + HoldHigh => thold_DIB_CLKB_negedge_posedge(16), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB17_CLKB_posedge, + TimingData => Tmkr_DIB17_CLKB_posedge, + TestSignal => DIB_ipd(17), + TestSignalName => "DIB(17)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(17), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(17), + HoldLow => thold_DIB_CLKB_posedge_posedge(17), + HoldHigh => thold_DIB_CLKB_negedge_posedge(17), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB18_CLKB_posedge, + TimingData => Tmkr_DIB18_CLKB_posedge, + TestSignal => DIB_ipd(18), + TestSignalName => "DIB(18)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(18), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(18), + HoldLow => thold_DIB_CLKB_posedge_posedge(18), + HoldHigh => thold_DIB_CLKB_negedge_posedge(18), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB19_CLKB_posedge, + TimingData => Tmkr_DIB19_CLKB_posedge, + TestSignal => DIB_ipd(19), + TestSignalName => "DIB(19)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(19), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(19), + HoldLow => thold_DIB_CLKB_posedge_posedge(19), + HoldHigh => thold_DIB_CLKB_negedge_posedge(19), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB20_CLKB_posedge, + TimingData => Tmkr_DIB20_CLKB_posedge, + TestSignal => DIB_ipd(20), + TestSignalName => "DIB(20)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(20), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(20), + HoldLow => thold_DIB_CLKB_posedge_posedge(20), + HoldHigh => thold_DIB_CLKB_negedge_posedge(20), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB21_CLKB_posedge, + TimingData => Tmkr_DIB21_CLKB_posedge, + TestSignal => DIB_ipd(21), + TestSignalName => "DIB(21)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(21), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(21), + HoldLow => thold_DIB_CLKB_posedge_posedge(21), + HoldHigh => thold_DIB_CLKB_negedge_posedge(21), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB22_CLKB_posedge, + TimingData => Tmkr_DIB22_CLKB_posedge, + TestSignal => DIB_ipd(22), + TestSignalName => "DIB(22)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(22), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(22), + HoldLow => thold_DIB_CLKB_posedge_posedge(22), + HoldHigh => thold_DIB_CLKB_negedge_posedge(22), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB23_CLKB_posedge, + TimingData => Tmkr_DIB23_CLKB_posedge, + TestSignal => DIB_ipd(23), + TestSignalName => "DIB(23)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(23), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(23), + HoldLow => thold_DIB_CLKB_posedge_posedge(23), + HoldHigh => thold_DIB_CLKB_negedge_posedge(23), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB24_CLKB_posedge, + TimingData => Tmkr_DIB24_CLKB_posedge, + TestSignal => DIB_ipd(24), + TestSignalName => "DIB(24)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(24), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(24), + HoldLow => thold_DIB_CLKB_posedge_posedge(24), + HoldHigh => thold_DIB_CLKB_negedge_posedge(24), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB25_CLKB_posedge, + TimingData => Tmkr_DIB25_CLKB_posedge, + TestSignal => DIB_ipd(25), + TestSignalName => "DIB(25)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(25), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(25), + HoldLow => thold_DIB_CLKB_posedge_posedge(25), + HoldHigh => thold_DIB_CLKB_negedge_posedge(25), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB26_CLKB_posedge, + TimingData => Tmkr_DIB26_CLKB_posedge, + TestSignal => DIB_ipd(26), + TestSignalName => "DIB(26)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(26), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(26), + HoldLow => thold_DIB_CLKB_posedge_posedge(26), + HoldHigh => thold_DIB_CLKB_negedge_posedge(26), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB27_CLKB_posedge, + TimingData => Tmkr_DIB27_CLKB_posedge, + TestSignal => DIB_ipd(27), + TestSignalName => "DIB(27)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(27), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(27), + HoldLow => thold_DIB_CLKB_posedge_posedge(27), + HoldHigh => thold_DIB_CLKB_negedge_posedge(27), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB28_CLKB_posedge, + TimingData => Tmkr_DIB28_CLKB_posedge, + TestSignal => DIB_ipd(28), + TestSignalName => "DIB(28)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(28), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(28), + HoldLow => thold_DIB_CLKB_posedge_posedge(28), + HoldHigh => thold_DIB_CLKB_negedge_posedge(28), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB29_CLKB_posedge, + TimingData => Tmkr_DIB29_CLKB_posedge, + TestSignal => DIB_ipd(29), + TestSignalName => "DIB(29)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(29), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(29), + HoldLow => thold_DIB_CLKB_posedge_posedge(29), + HoldHigh => thold_DIB_CLKB_negedge_posedge(29), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB30_CLKB_posedge, + TimingData => Tmkr_DIB30_CLKB_posedge, + TestSignal => DIB_ipd(30), + TestSignalName => "DIB(30)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(30), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(30), + HoldLow => thold_DIB_CLKB_posedge_posedge(30), + HoldHigh => thold_DIB_CLKB_negedge_posedge(30), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S36_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_DIA2_CLKA_posedge or + Tviol_DIA3_CLKA_posedge or + Tviol_DIA4_CLKA_posedge or + Tviol_DIA5_CLKA_posedge or + Tviol_DIA6_CLKA_posedge or + Tviol_DIA7_CLKA_posedge or + Tviol_DIA8_CLKA_posedge or + Tviol_DIA9_CLKA_posedge or + Tviol_DIA10_CLKA_posedge or + Tviol_DIA11_CLKA_posedge or + Tviol_DIA12_CLKA_posedge or + Tviol_DIA13_CLKA_posedge or + Tviol_DIA14_CLKA_posedge or + Tviol_DIA15_CLKA_posedge or + Tviol_DIA16_CLKA_posedge or + Tviol_DIA17_CLKA_posedge or + Tviol_DIA18_CLKA_posedge or + Tviol_DIA19_CLKA_posedge or + Tviol_DIA20_CLKA_posedge or + Tviol_DIA21_CLKA_posedge or + Tviol_DIA22_CLKA_posedge or + Tviol_DIA23_CLKA_posedge or + Tviol_DIA24_CLKA_posedge or + Tviol_DIA25_CLKA_posedge or + Tviol_DIA26_CLKA_posedge or + Tviol_DIA27_CLKA_posedge or + Tviol_DIA28_CLKA_posedge or + Tviol_DIA29_CLKA_posedge or + Tviol_DIA30_CLKA_posedge or + Tviol_DIA31_CLKA_posedge or + Tviol_DIPA0_CLKA_posedge or + Tviol_DIPA1_CLKA_posedge or + Tviol_DIPA2_CLKA_posedge or + Tviol_DIPA3_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIB8_CLKB_posedge or + Tviol_DIB9_CLKB_posedge or + Tviol_DIB10_CLKB_posedge or + Tviol_DIB11_CLKB_posedge or + Tviol_DIB12_CLKB_posedge or + Tviol_DIB13_CLKB_posedge or + Tviol_DIB14_CLKB_posedge or + Tviol_DIB15_CLKB_posedge or + Tviol_DIB16_CLKB_posedge or + Tviol_DIB17_CLKB_posedge or + Tviol_DIB18_CLKB_posedge or + Tviol_DIB19_CLKB_posedge or + Tviol_DIB20_CLKB_posedge or + Tviol_DIB21_CLKB_posedge or + Tviol_DIB22_CLKB_posedge or + Tviol_DIB23_CLKB_posedge or + Tviol_DIB24_CLKB_posedge or + Tviol_DIB25_CLKB_posedge or + Tviol_DIB26_CLKB_posedge or + Tviol_DIB27_CLKB_posedge or + Tviol_DIB28_CLKB_posedge or + Tviol_DIB29_CLKB_posedge or + Tviol_DIB30_CLKB_posedge or + Tviol_DIB31_CLKB_posedge or + Tviol_DIPB0_CLKB_posedge or + Tviol_DIPB1_CLKB_posedge or + Tviol_DIPB2_CLKB_posedge or + Tviol_DIPB3_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + addr_overlap (address_a, address_b, parity_width_a, parity_width_b, has_overlap_p, olpp_lsb, olpp_msb, dopa_ov_lsb, dopa_ov_msb, dopb_ov_lsb, dopb_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S36_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + DOPA_zd := DIPA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S36_S36", + InstanceName => ramb16_s36_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S36_S36", + InstanceName => ramb16_s36_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S36_S36", + InstanceName => ramb16_s36_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S36_S36", + InstanceName => ramb16_s36_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S36_S36", + InstanceName => ramb16_s36_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S36_S36", + InstanceName => ramb16_s36_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S36_S36", + InstanceName => ramb16_s36_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(31 downto 0); + DOPA_zd := SRVA_A(35 downto 32); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + DOPB_zd := DIPB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S36_S36", + InstanceName => ramb16_s36_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S36_S36", + InstanceName => ramb16_s36_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S36_S36", + InstanceName => ramb16_s36_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S36_S36", + InstanceName => ramb16_s36_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S36_S36", + InstanceName => ramb16_s36_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S36_S36", + InstanceName => ramb16_s36_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S36_S36", + InstanceName => ramb16_s36_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(31 downto 0); + DOPB_zd := SRVA_B(35 downto 32); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + DOA_zd(1) := ViolationA xor DOA_zd(1); + DOA_zd(2) := ViolationA xor DOA_zd(2); + DOA_zd(3) := ViolationA xor DOA_zd(3); + DOA_zd(4) := ViolationA xor DOA_zd(4); + DOA_zd(5) := ViolationA xor DOA_zd(5); + DOA_zd(6) := ViolationA xor DOA_zd(6); + DOA_zd(7) := ViolationA xor DOA_zd(7); + DOA_zd(8) := ViolationA xor DOA_zd(8); + DOA_zd(9) := ViolationA xor DOA_zd(9); + DOA_zd(10) := ViolationA xor DOA_zd(10); + DOA_zd(11) := ViolationA xor DOA_zd(11); + DOA_zd(12) := ViolationA xor DOA_zd(12); + DOA_zd(13) := ViolationA xor DOA_zd(13); + DOA_zd(14) := ViolationA xor DOA_zd(14); + DOA_zd(15) := ViolationA xor DOA_zd(15); + DOA_zd(16) := ViolationA xor DOA_zd(16); + DOA_zd(17) := ViolationA xor DOA_zd(17); + DOA_zd(18) := ViolationA xor DOA_zd(18); + DOA_zd(19) := ViolationA xor DOA_zd(19); + DOA_zd(20) := ViolationA xor DOA_zd(20); + DOA_zd(21) := ViolationA xor DOA_zd(21); + DOA_zd(22) := ViolationA xor DOA_zd(22); + DOA_zd(23) := ViolationA xor DOA_zd(23); + DOA_zd(24) := ViolationA xor DOA_zd(24); + DOA_zd(25) := ViolationA xor DOA_zd(25); + DOA_zd(26) := ViolationA xor DOA_zd(26); + DOA_zd(27) := ViolationA xor DOA_zd(27); + DOA_zd(28) := ViolationA xor DOA_zd(28); + DOA_zd(29) := ViolationA xor DOA_zd(29); + DOA_zd(30) := ViolationA xor DOA_zd(30); + DOA_zd(31) := ViolationA xor DOA_zd(31); + DOPA_zd(0) := ViolationA xor DOPA_zd(0); + DOPA_zd(1) := ViolationA xor DOPA_zd(1); + DOPA_zd(2) := ViolationA xor DOPA_zd(2); + DOPA_zd(3) := ViolationA xor DOPA_zd(3); + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOB_zd(8) := ViolationB xor DOB_zd(8); + DOB_zd(9) := ViolationB xor DOB_zd(9); + DOB_zd(10) := ViolationB xor DOB_zd(10); + DOB_zd(11) := ViolationB xor DOB_zd(11); + DOB_zd(12) := ViolationB xor DOB_zd(12); + DOB_zd(13) := ViolationB xor DOB_zd(13); + DOB_zd(14) := ViolationB xor DOB_zd(14); + DOB_zd(15) := ViolationB xor DOB_zd(15); + DOB_zd(16) := ViolationB xor DOB_zd(16); + DOB_zd(17) := ViolationB xor DOB_zd(17); + DOB_zd(18) := ViolationB xor DOB_zd(18); + DOB_zd(19) := ViolationB xor DOB_zd(19); + DOB_zd(20) := ViolationB xor DOB_zd(20); + DOB_zd(21) := ViolationB xor DOB_zd(21); + DOB_zd(22) := ViolationB xor DOB_zd(22); + DOB_zd(23) := ViolationB xor DOB_zd(23); + DOB_zd(24) := ViolationB xor DOB_zd(24); + DOB_zd(25) := ViolationB xor DOB_zd(25); + DOB_zd(26) := ViolationB xor DOB_zd(26); + DOB_zd(27) := ViolationB xor DOB_zd(27); + DOB_zd(28) := ViolationB xor DOB_zd(28); + DOB_zd(29) := ViolationB xor DOB_zd(29); + DOB_zd(30) := ViolationB xor DOB_zd(30); + DOB_zd(31) := ViolationB xor DOB_zd(31); + DOPB_zd(0) := ViolationB xor DOPB_zd(0); + DOPB_zd(1) := ViolationB xor DOPB_zd(1); + DOPB_zd(2) := ViolationB xor DOPB_zd(2); + DOPB_zd(3) := ViolationB xor DOPB_zd(3); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(2), + GlitchData => DOA_GlitchData2, + OutSignalName => "DOA(2)", + OutTemp => DOA_zd(2), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(3), + GlitchData => DOA_GlitchData3, + OutSignalName => "DOA(3)", + OutTemp => DOA_zd(3), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(4), + GlitchData => DOA_GlitchData4, + OutSignalName => "DOA(4)", + OutTemp => DOA_zd(4), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(5), + GlitchData => DOA_GlitchData5, + OutSignalName => "DOA(5)", + OutTemp => DOA_zd(5), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(6), + GlitchData => DOA_GlitchData6, + OutSignalName => "DOA(6)", + OutTemp => DOA_zd(6), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(7), + GlitchData => DOA_GlitchData7, + OutSignalName => "DOA(7)", + OutTemp => DOA_zd(7), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(8), + GlitchData => DOA_GlitchData8, + OutSignalName => "DOA(8)", + OutTemp => DOA_zd(8), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(9), + GlitchData => DOA_GlitchData9, + OutSignalName => "DOA(9)", + OutTemp => DOA_zd(9), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(10), + GlitchData => DOA_GlitchData10, + OutSignalName => "DOA(10)", + OutTemp => DOA_zd(10), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(11), + GlitchData => DOA_GlitchData11, + OutSignalName => "DOA(11)", + OutTemp => DOA_zd(11), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(12), + GlitchData => DOA_GlitchData12, + OutSignalName => "DOA(12)", + OutTemp => DOA_zd(12), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(13), + GlitchData => DOA_GlitchData13, + OutSignalName => "DOA(13)", + OutTemp => DOA_zd(13), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(14), + GlitchData => DOA_GlitchData14, + OutSignalName => "DOA(14)", + OutTemp => DOA_zd(14), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(15), + GlitchData => DOA_GlitchData15, + OutSignalName => "DOA(15)", + OutTemp => DOA_zd(15), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(16), + GlitchData => DOA_GlitchData16, + OutSignalName => "DOA(16)", + OutTemp => DOA_zd(16), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(16), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(17), + GlitchData => DOA_GlitchData17, + OutSignalName => "DOA(17)", + OutTemp => DOA_zd(17), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(17), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(18), + GlitchData => DOA_GlitchData18, + OutSignalName => "DOA(18)", + OutTemp => DOA_zd(18), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(18), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(19), + GlitchData => DOA_GlitchData19, + OutSignalName => "DOA(19)", + OutTemp => DOA_zd(19), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(19), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(20), + GlitchData => DOA_GlitchData20, + OutSignalName => "DOA(20)", + OutTemp => DOA_zd(20), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(20), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(21), + GlitchData => DOA_GlitchData21, + OutSignalName => "DOA(21)", + OutTemp => DOA_zd(21), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(21), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(22), + GlitchData => DOA_GlitchData22, + OutSignalName => "DOA(22)", + OutTemp => DOA_zd(22), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(22), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(23), + GlitchData => DOA_GlitchData23, + OutSignalName => "DOA(23)", + OutTemp => DOA_zd(23), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(23), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(24), + GlitchData => DOA_GlitchData24, + OutSignalName => "DOA(24)", + OutTemp => DOA_zd(24), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(24), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(25), + GlitchData => DOA_GlitchData25, + OutSignalName => "DOA(25)", + OutTemp => DOA_zd(25), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(25), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(26), + GlitchData => DOA_GlitchData26, + OutSignalName => "DOA(26)", + OutTemp => DOA_zd(26), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(26), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(27), + GlitchData => DOA_GlitchData27, + OutSignalName => "DOA(27)", + OutTemp => DOA_zd(27), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(27), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(28), + GlitchData => DOA_GlitchData28, + OutSignalName => "DOA(28)", + OutTemp => DOA_zd(28), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(28), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(29), + GlitchData => DOA_GlitchData29, + OutSignalName => "DOA(29)", + OutTemp => DOA_zd(29), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(29), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(30), + GlitchData => DOA_GlitchData30, + OutSignalName => "DOA(30)", + OutTemp => DOA_zd(30), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(30), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(31), + GlitchData => DOA_GlitchData31, + OutSignalName => "DOA(31)", + OutTemp => DOA_zd(31), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(31), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPA(0), + GlitchData => DOPA_GlitchData0, + OutSignalName => "DOPA(0)", + OutTemp => DOPA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPA(1), + GlitchData => DOPA_GlitchData1, + OutSignalName => "DOPA(1)", + OutTemp => DOPA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPA(2), + GlitchData => DOPA_GlitchData2, + OutSignalName => "DOPA(2)", + OutTemp => DOPA_zd(2), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPA(3), + GlitchData => DOPA_GlitchData3, + OutSignalName => "DOPA(3)", + OutTemp => DOPA_zd(3), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(8), + GlitchData => DOB_GlitchData8, + OutSignalName => "DOB(8)", + OutTemp => DOB_zd(8), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(9), + GlitchData => DOB_GlitchData9, + OutSignalName => "DOB(9)", + OutTemp => DOB_zd(9), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(10), + GlitchData => DOB_GlitchData10, + OutSignalName => "DOB(10)", + OutTemp => DOB_zd(10), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(11), + GlitchData => DOB_GlitchData11, + OutSignalName => "DOB(11)", + OutTemp => DOB_zd(11), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(12), + GlitchData => DOB_GlitchData12, + OutSignalName => "DOB(12)", + OutTemp => DOB_zd(12), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(13), + GlitchData => DOB_GlitchData13, + OutSignalName => "DOB(13)", + OutTemp => DOB_zd(13), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(14), + GlitchData => DOB_GlitchData14, + OutSignalName => "DOB(14)", + OutTemp => DOB_zd(14), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(15), + GlitchData => DOB_GlitchData15, + OutSignalName => "DOB(15)", + OutTemp => DOB_zd(15), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(16), + GlitchData => DOB_GlitchData16, + OutSignalName => "DOB(16)", + OutTemp => DOB_zd(16), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(16), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(17), + GlitchData => DOB_GlitchData17, + OutSignalName => "DOB(17)", + OutTemp => DOB_zd(17), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(17), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(18), + GlitchData => DOB_GlitchData18, + OutSignalName => "DOB(18)", + OutTemp => DOB_zd(18), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(18), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(19), + GlitchData => DOB_GlitchData19, + OutSignalName => "DOB(19)", + OutTemp => DOB_zd(19), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(19), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(20), + GlitchData => DOB_GlitchData20, + OutSignalName => "DOB(20)", + OutTemp => DOB_zd(20), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(20), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(21), + GlitchData => DOB_GlitchData21, + OutSignalName => "DOB(21)", + OutTemp => DOB_zd(21), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(21), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(22), + GlitchData => DOB_GlitchData22, + OutSignalName => "DOB(22)", + OutTemp => DOB_zd(22), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(22), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(23), + GlitchData => DOB_GlitchData23, + OutSignalName => "DOB(23)", + OutTemp => DOB_zd(23), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(23), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(24), + GlitchData => DOB_GlitchData24, + OutSignalName => "DOB(24)", + OutTemp => DOB_zd(24), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(24), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(25), + GlitchData => DOB_GlitchData25, + OutSignalName => "DOB(25)", + OutTemp => DOB_zd(25), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(25), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(26), + GlitchData => DOB_GlitchData26, + OutSignalName => "DOB(26)", + OutTemp => DOB_zd(26), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(26), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(27), + GlitchData => DOB_GlitchData27, + OutSignalName => "DOB(27)", + OutTemp => DOB_zd(27), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(27), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(28), + GlitchData => DOB_GlitchData28, + OutSignalName => "DOB(28)", + OutTemp => DOB_zd(28), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(28), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(29), + GlitchData => DOB_GlitchData29, + OutSignalName => "DOB(29)", + OutTemp => DOB_zd(29), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(29), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(30), + GlitchData => DOB_GlitchData30, + OutSignalName => "DOB(30)", + OutTemp => DOB_zd(30), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(30), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(31), + GlitchData => DOB_GlitchData31, + OutSignalName => "DOB(31)", + OutTemp => DOB_zd(31), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(31), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(0), + GlitchData => DOPB_GlitchData0, + OutSignalName => "DOPB(0)", + OutTemp => DOPB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(1), + GlitchData => DOPB_GlitchData1, + OutSignalName => "DOPB(1)", + OutTemp => DOPB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(2), + GlitchData => DOPB_GlitchData2, + OutSignalName => "DOPB(2)", + OutTemp => DOPB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(3), + GlitchData => DOPB_GlitchData3, + OutSignalName => "DOPB(3)", + OutTemp => DOPB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPA_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S36_S36_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb16_s4.vhd,v 1.7 2005/10/07 18:35:24 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +-- /___/ /\ Filename : RAMB16_S4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:52 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 09/26/05 - Fixed CR# 216846. INIT and SRVAL attributes length check and adjustment. +-- END Revision + +----- CELL RAMB16_S4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S4 is + + generic ( + INIT : bit_vector := X"0"; + SRVAL : bit_vector := X"0"; + WRITE_MODE : string := "WRITE_FIRST"; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + + port ( + DO : out STD_LOGIC_VECTOR (3 downto 0); + + ADDR : in STD_LOGIC_VECTOR (11 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (3 downto 0); + EN : in STD_ULOGIC; + SSR : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end RAMB16_S4; + +architecture RAMB16_S4_V of RAMB16_S4 is + constant length : integer := 4096; + constant width : integer := 4; + + type Two_D_array_type is array ((length - 1) downto 0) of std_logic_vector((width - 1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + VITALBehavior : process + variable address : integer; + variable valid_addr : boolean := FALSE; + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F & INIT_3E & INIT_3D & INIT_3C & + INIT_3B & INIT_3A & INIT_39 & INIT_38 & + INIT_37 & INIT_36 & INIT_35 & INIT_34 & + INIT_33 & INIT_32 & INIT_31 & INIT_30 & + INIT_2F & INIT_2E & INIT_2D & INIT_2C & + INIT_2B & INIT_2A & INIT_29 & INIT_28 & + INIT_27 & INIT_26 & INIT_25 & INIT_24 & + INIT_23 & INIT_22 & INIT_21 & INIT_20 & + INIT_1F & INIT_1E & INIT_1D & INIT_1C & + INIT_1B & INIT_1A & INIT_19 & INIT_18 & + INIT_17 & INIT_16 & INIT_15 & INIT_14 & + INIT_13 & INIT_12 & INIT_11 & INIT_10 & + INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(length, width, mem_slv); + + variable wr_mode : integer := 0; + variable first_time : boolean := true; + + variable INIT_reg : std_logic_vector (3 downto 0) := "0000"; + variable SRVAL_reg : std_logic_vector (3 downto 0) := "0000"; + begin + if (first_time) then + if ((WRITE_MODE = "write_first") or (WRITE_MODE = "WRITE_FIRST")) then + wr_mode := 0; + elsif ((WRITE_MODE = "read_first") or (WRITE_MODE = "READ_FIRST")) then + wr_mode := 1; + elsif ((WRITE_MODE = "no_change") or (WRITE_MODE = "NO_CHANGE")) then + wr_mode := 2; + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Error ", + GenericName => " WRITE_MODE ", + EntityName => "/RAMB16_S4", + GenericValue => WRITE_MODE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT'length > 4) then + INIT_reg(3 downto 0) := To_StdLogicVector(INIT)(3 downto 0); + else + INIT_reg(INIT'length-1 downto 0) := To_StdLogicVector(INIT); + end if; + DO <= INIT_reg(3 downto 0); + if (SRVAL'length > 4) then + SRVAL_reg(3 downto 0) := To_StdLogicVector(SRVAL)(3 downto 0); + else + SRVAL_reg(SRVAL'length-1 downto 0) := To_StdLogicVector(SRVAL); + end if; + first_time := false; + end if; + + valid_addr := addr_is_valid(addr); + + if (valid_addr) then + address := slv_to_int(addr); + end if; + + if (rising_edge(CLK)) then + if (EN = '1') then + if (SSR = '1') then + DO <= SRVAL_reg(3 downto 0) after 100 ps; + else + if (WE = '1') then + if (wr_mode = 0) then + DO <= DI after 100 ps; + elsif (wr_mode = 1) then + DO <= mem(address) after 100 ps; + end if; + else + if (valid_addr) then + DO <= mem(address) after 100 ps; + end if; + end if; + end if; + if (WE = '1') then + if (valid_addr) then + mem(address) := DI; + end if; + end if; + end if; + end if; + wait on CLK; + end process VITALBehavior; +end RAMB16_S4_V; + + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S4_S18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s4_s18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S4_S18 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(11 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(9 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPB : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOPB : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"00000"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"00000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(3 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPB : out std_logic_vector(1 downto 0); + + ADDRA : in std_logic_vector(11 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(3 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S4_S18 : entity is true; +end ramb16_s4_s18; + +architecture RAMB16_S4_S18_V of RAMB16_S4_S18 is + attribute VITAL_LEVEL0 of + RAMB16_S4_S18_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(11 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(9 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(15 downto 0) := (others => 'X'); + signal DIPB_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 4096; + constant length_b : integer := 1024; + constant width_a : integer := 4; + constant width_b : integer := 16; + + constant parity_width_b : integer := 2; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + + function slv_to_two_D_parity_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_parity_array_type is + variable two_D_parity_array : two_D_parity_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_parity_array(i) := intermediate; + end loop; + return two_D_parity_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 11 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 9 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 15 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + DIPB_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i)); + end generate DIPB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB12_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB13_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB14_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB15_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB13_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB14_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB15_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + variable DOA_GlitchData2 : VitalGlitchDataType; + variable DOA_GlitchData3 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOB_GlitchData8 : VitalGlitchDataType; + variable DOB_GlitchData9 : VitalGlitchDataType; + variable DOB_GlitchData10 : VitalGlitchDataType; + variable DOB_GlitchData11 : VitalGlitchDataType; + variable DOB_GlitchData12 : VitalGlitchDataType; + variable DOB_GlitchData13 : VitalGlitchDataType; + variable DOB_GlitchData14 : VitalGlitchDataType; + variable DOB_GlitchData15 : VitalGlitchDataType; + variable DOPB_GlitchData0 : VitalGlitchDataType; + variable DOPB_GlitchData1 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) & + To_StdLogicVector(INITP_06) & + To_StdLogicVector(INITP_05) & + To_StdLogicVector(INITP_04) & + To_StdLogicVector(INITP_03) & + To_StdLogicVector(INITP_02) & + To_StdLogicVector(INITP_01) & + To_StdLogicVector(INITP_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOPB_OV_LSB : integer := 0; + variable DOPB_OV_MSB : integer := 1; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (3 downto 0) := "0000"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (17 downto 0) := "000000000000000000"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (3 downto 0) := "0000"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (17 downto 0) := "000000000000000000"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(3 downto 0) := INI_A(3 downto 0); + variable DOB_zd : std_logic_vector(15 downto 0) := INI_B(15 downto 0); + variable DOPB_zd : std_logic_vector(1 downto 0) := INI_B(17 downto 16); + + variable ADDRA_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S4_S18", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 4) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(3 downto 0) := INI_A_UNBOUND(3 downto 0); + + for I in INI_A_UNBOUND'high downto 4 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 4 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S4_S18", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 4) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S4_S18", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 4) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 18) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(17 downto 0) := INI_B_UNBOUND(17 downto 0); + + for I in INI_B_UNBOUND'high downto 18 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 18 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S4_S18", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 18) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S4_S18", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 18) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 4) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(3 downto 0) := SRVA_A_UNBOUND(3 downto 0); + + for I in SRVA_A_UNBOUND'high downto 4 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 4 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S4_S18", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 4) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S4_S18", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 4) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 18) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(17 downto 0) := SRVA_B_UNBOUND(17 downto 0); + + for I in SRVA_B_UNBOUND'high downto 18 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 18 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S4_S18", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 18) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S4_S18", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 18) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(3 downto 0) := INI_A(3 downto 0); + DOB_zd(15 downto 0) := INI_B(15 downto 0); + DOPB_zd(1 downto 0) := INI_B(17 downto 16); + DOA <= DOA_zd; + DOB <= DOB_zd; + DOPB <= DOPB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S4_S18", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S4_S18", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA1_CLKA_posedge, + TimingData => Tmkr_DIA1_CLKA_posedge, + TestSignal => DIA_ipd(1), + TestSignalName => "DIA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(1), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(1), + HoldLow => thold_DIA_CLKA_posedge_posedge(1), + HoldHigh => thold_DIA_CLKA_negedge_posedge(1), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA2_CLKA_posedge, + TimingData => Tmkr_DIA2_CLKA_posedge, + TestSignal => DIA_ipd(2), + TestSignalName => "DIA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(2), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(2), + HoldLow => thold_DIA_CLKA_posedge_posedge(2), + HoldHigh => thold_DIA_CLKA_negedge_posedge(2), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB0_CLKB_posedge, + TimingData => Tmkr_DIPB0_CLKB_posedge, + TestSignal => DIPB_ipd(0), + TestSignalName => "DIPB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(0), + HoldLow => thold_DIPB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB7_CLKB_posedge, + TimingData => Tmkr_DIB7_CLKB_posedge, + TestSignal => DIB_ipd(7), + TestSignalName => "DIB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(7), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(7), + HoldLow => thold_DIB_CLKB_posedge_posedge(7), + HoldHigh => thold_DIB_CLKB_negedge_posedge(7), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB8_CLKB_posedge, + TimingData => Tmkr_DIB8_CLKB_posedge, + TestSignal => DIB_ipd(8), + TestSignalName => "DIB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(8), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(8), + HoldLow => thold_DIB_CLKB_posedge_posedge(8), + HoldHigh => thold_DIB_CLKB_negedge_posedge(8), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB9_CLKB_posedge, + TimingData => Tmkr_DIB9_CLKB_posedge, + TestSignal => DIB_ipd(9), + TestSignalName => "DIB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(9), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(9), + HoldLow => thold_DIB_CLKB_posedge_posedge(9), + HoldHigh => thold_DIB_CLKB_negedge_posedge(9), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB10_CLKB_posedge, + TimingData => Tmkr_DIB10_CLKB_posedge, + TestSignal => DIB_ipd(10), + TestSignalName => "DIB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(10), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(10), + HoldLow => thold_DIB_CLKB_posedge_posedge(10), + HoldHigh => thold_DIB_CLKB_negedge_posedge(10), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB11_CLKB_posedge, + TimingData => Tmkr_DIB11_CLKB_posedge, + TestSignal => DIB_ipd(11), + TestSignalName => "DIB(11)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(11), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(11), + HoldLow => thold_DIB_CLKB_posedge_posedge(11), + HoldHigh => thold_DIB_CLKB_negedge_posedge(11), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB12_CLKB_posedge, + TimingData => Tmkr_DIB12_CLKB_posedge, + TestSignal => DIB_ipd(12), + TestSignalName => "DIB(12)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(12), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(12), + HoldLow => thold_DIB_CLKB_posedge_posedge(12), + HoldHigh => thold_DIB_CLKB_negedge_posedge(12), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB13_CLKB_posedge, + TimingData => Tmkr_DIB13_CLKB_posedge, + TestSignal => DIB_ipd(13), + TestSignalName => "DIB(13)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(13), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(13), + HoldLow => thold_DIB_CLKB_posedge_posedge(13), + HoldHigh => thold_DIB_CLKB_negedge_posedge(13), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB14_CLKB_posedge, + TimingData => Tmkr_DIB14_CLKB_posedge, + TestSignal => DIB_ipd(14), + TestSignalName => "DIB(14)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(14), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(14), + HoldLow => thold_DIB_CLKB_posedge_posedge(14), + HoldHigh => thold_DIB_CLKB_negedge_posedge(14), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S4_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_DIA2_CLKA_posedge or + Tviol_DIA3_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIB8_CLKB_posedge or + Tviol_DIB9_CLKB_posedge or + Tviol_DIB10_CLKB_posedge or + Tviol_DIB11_CLKB_posedge or + Tviol_DIB12_CLKB_posedge or + Tviol_DIB13_CLKB_posedge or + Tviol_DIB14_CLKB_posedge or + Tviol_DIB15_CLKB_posedge or + Tviol_DIPB0_CLKB_posedge or + Tviol_DIPB1_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S18", + InstanceName => ramb16_s4_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S4_S18", + InstanceName => ramb16_s4_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S18", + InstanceName => ramb16_s4_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S4_S18", + InstanceName => ramb16_s4_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S18", + InstanceName => ramb16_s4_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S4_S18", + InstanceName => ramb16_s4_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S4_S18", + InstanceName => ramb16_s4_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(3 downto 0); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + DOPB_zd := DIPB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S18", + InstanceName => ramb16_s4_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S4_S18", + InstanceName => ramb16_s4_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S18", + InstanceName => ramb16_s4_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S4_S18", + InstanceName => ramb16_s4_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S18", + InstanceName => ramb16_s4_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S4_S18", + InstanceName => ramb16_s4_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S4_S18", + InstanceName => ramb16_s4_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(15 downto 0); + DOPB_zd := SRVA_B(17 downto 16); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOB_zd(8) := ViolationB xor DOB_zd(8); + DOB_zd(9) := ViolationB xor DOB_zd(9); + DOB_zd(10) := ViolationB xor DOB_zd(10); + DOB_zd(11) := ViolationB xor DOB_zd(11); + DOB_zd(12) := ViolationB xor DOB_zd(12); + DOB_zd(13) := ViolationB xor DOB_zd(13); + DOB_zd(14) := ViolationB xor DOB_zd(14); + DOB_zd(15) := ViolationB xor DOB_zd(15); + DOPB_zd(0) := ViolationB xor DOPB_zd(0); + DOPB_zd(1) := ViolationB xor DOPB_zd(1); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(2), + GlitchData => DOA_GlitchData2, + OutSignalName => "DOA(2)", + OutTemp => DOA_zd(2), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(3), + GlitchData => DOA_GlitchData3, + OutSignalName => "DOA(3)", + OutTemp => DOA_zd(3), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(8), + GlitchData => DOB_GlitchData8, + OutSignalName => "DOB(8)", + OutTemp => DOB_zd(8), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(9), + GlitchData => DOB_GlitchData9, + OutSignalName => "DOB(9)", + OutTemp => DOB_zd(9), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(10), + GlitchData => DOB_GlitchData10, + OutSignalName => "DOB(10)", + OutTemp => DOB_zd(10), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(11), + GlitchData => DOB_GlitchData11, + OutSignalName => "DOB(11)", + OutTemp => DOB_zd(11), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(12), + GlitchData => DOB_GlitchData12, + OutSignalName => "DOB(12)", + OutTemp => DOB_zd(12), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(13), + GlitchData => DOB_GlitchData13, + OutSignalName => "DOB(13)", + OutTemp => DOB_zd(13), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(14), + GlitchData => DOB_GlitchData14, + OutSignalName => "DOB(14)", + OutTemp => DOB_zd(14), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(15), + GlitchData => DOB_GlitchData15, + OutSignalName => "DOB(15)", + OutTemp => DOB_zd(15), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(0), + GlitchData => DOPB_GlitchData0, + OutSignalName => "DOPB(0)", + OutTemp => DOPB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(1), + GlitchData => DOPB_GlitchData1, + OutSignalName => "DOPB(1)", + OutTemp => DOPB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S4_S18_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S4_S36.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s4_s36 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S4_S36 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(11 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(8 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPB : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(31 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOPB : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"000000000"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"000000000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(3 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPB : out std_logic_vector(3 downto 0); + + ADDRA : in std_logic_vector(11 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(3 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S4_S36 : entity is true; +end ramb16_s4_s36; + +architecture RAMB16_S4_S36_V of RAMB16_S4_S36 is + attribute VITAL_LEVEL0 of + RAMB16_S4_S36_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(11 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(8 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(31 downto 0) := (others => 'X'); + signal DIPB_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 4096; + constant length_b : integer := 512; + constant width_a : integer := 4; + constant width_b : integer := 32; + + constant parity_width_b : integer := 4; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + + function slv_to_two_D_parity_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_parity_array_type is + variable two_D_parity_array : two_D_parity_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_parity_array(i) := intermediate; + end loop; + return two_D_parity_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 11 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 8 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 31 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + DIPB_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i)); + end generate DIPB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB12_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB13_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB14_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB15_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB16_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB17_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB18_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB19_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB20_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB21_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB22_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB23_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB24_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB25_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB26_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB27_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB28_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB29_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB30_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB31_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB13_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB14_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB15_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB16_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB17_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB18_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB19_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB20_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB21_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB22_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB23_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB24_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB25_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB26_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB27_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB28_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB29_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB30_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB31_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + variable DOA_GlitchData2 : VitalGlitchDataType; + variable DOA_GlitchData3 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOB_GlitchData8 : VitalGlitchDataType; + variable DOB_GlitchData9 : VitalGlitchDataType; + variable DOB_GlitchData10 : VitalGlitchDataType; + variable DOB_GlitchData11 : VitalGlitchDataType; + variable DOB_GlitchData12 : VitalGlitchDataType; + variable DOB_GlitchData13 : VitalGlitchDataType; + variable DOB_GlitchData14 : VitalGlitchDataType; + variable DOB_GlitchData15 : VitalGlitchDataType; + variable DOB_GlitchData16 : VitalGlitchDataType; + variable DOB_GlitchData17 : VitalGlitchDataType; + variable DOB_GlitchData18 : VitalGlitchDataType; + variable DOB_GlitchData19 : VitalGlitchDataType; + variable DOB_GlitchData20 : VitalGlitchDataType; + variable DOB_GlitchData21 : VitalGlitchDataType; + variable DOB_GlitchData22 : VitalGlitchDataType; + variable DOB_GlitchData23 : VitalGlitchDataType; + variable DOB_GlitchData24 : VitalGlitchDataType; + variable DOB_GlitchData25 : VitalGlitchDataType; + variable DOB_GlitchData26 : VitalGlitchDataType; + variable DOB_GlitchData27 : VitalGlitchDataType; + variable DOB_GlitchData28 : VitalGlitchDataType; + variable DOB_GlitchData29 : VitalGlitchDataType; + variable DOB_GlitchData30 : VitalGlitchDataType; + variable DOB_GlitchData31 : VitalGlitchDataType; + variable DOPB_GlitchData0 : VitalGlitchDataType; + variable DOPB_GlitchData1 : VitalGlitchDataType; + variable DOPB_GlitchData2 : VitalGlitchDataType; + variable DOPB_GlitchData3 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) & + To_StdLogicVector(INITP_06) & + To_StdLogicVector(INITP_05) & + To_StdLogicVector(INITP_04) & + To_StdLogicVector(INITP_03) & + To_StdLogicVector(INITP_02) & + To_StdLogicVector(INITP_01) & + To_StdLogicVector(INITP_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOPB_OV_LSB : integer := 0; + variable DOPB_OV_MSB : integer := 3; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (3 downto 0) := "0000"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (35 downto 0) := "000000000000000000000000000000000000"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (3 downto 0) := "0000"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (35 downto 0) := "000000000000000000000000000000000000"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(3 downto 0) := INI_A(3 downto 0); + variable DOB_zd : std_logic_vector(31 downto 0) := INI_B(31 downto 0); + variable DOPB_zd : std_logic_vector(3 downto 0) := INI_B(35 downto 32); + + variable ADDRA_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S4_S36", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 4) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(3 downto 0) := INI_A_UNBOUND(3 downto 0); + + for I in INI_A_UNBOUND'high downto 4 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 4 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S4_S36", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 4) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S4_S36", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 4) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 36) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(35 downto 0) := INI_B_UNBOUND(35 downto 0); + + for I in INI_B_UNBOUND'high downto 36 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 36 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S4_S36", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S4_S36", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 4) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(3 downto 0) := SRVA_A_UNBOUND(3 downto 0); + + for I in SRVA_A_UNBOUND'high downto 4 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 4 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S4_S36", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 4) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S4_S36", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 4) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 36) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(35 downto 0) := SRVA_B_UNBOUND(35 downto 0); + + for I in SRVA_B_UNBOUND'high downto 36 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 36 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S4_S36", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S4_S36", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(3 downto 0) := INI_A(3 downto 0); + DOB_zd(31 downto 0) := INI_B(31 downto 0); + DOPB_zd(3 downto 0) := INI_B(35 downto 32); + DOA <= DOA_zd; + DOB <= DOB_zd; + DOPB <= DOPB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S4_S36", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S4_S36", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA1_CLKA_posedge, + TimingData => Tmkr_DIA1_CLKA_posedge, + TestSignal => DIA_ipd(1), + TestSignalName => "DIA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(1), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(1), + HoldLow => thold_DIA_CLKA_posedge_posedge(1), + HoldHigh => thold_DIA_CLKA_negedge_posedge(1), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA2_CLKA_posedge, + TimingData => Tmkr_DIA2_CLKA_posedge, + TestSignal => DIA_ipd(2), + TestSignalName => "DIA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(2), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(2), + HoldLow => thold_DIA_CLKA_posedge_posedge(2), + HoldHigh => thold_DIA_CLKA_negedge_posedge(2), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB0_CLKB_posedge, + TimingData => Tmkr_DIPB0_CLKB_posedge, + TestSignal => DIPB_ipd(0), + TestSignalName => "DIPB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(0), + HoldLow => thold_DIPB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB1_CLKB_posedge, + TimingData => Tmkr_DIPB1_CLKB_posedge, + TestSignal => DIPB_ipd(1), + TestSignalName => "DIPB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(1), + HoldLow => thold_DIPB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB2_CLKB_posedge, + TimingData => Tmkr_DIPB2_CLKB_posedge, + TestSignal => DIPB_ipd(2), + TestSignalName => "DIPB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(2), + HoldLow => thold_DIPB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB7_CLKB_posedge, + TimingData => Tmkr_DIB7_CLKB_posedge, + TestSignal => DIB_ipd(7), + TestSignalName => "DIB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(7), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(7), + HoldLow => thold_DIB_CLKB_posedge_posedge(7), + HoldHigh => thold_DIB_CLKB_negedge_posedge(7), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB8_CLKB_posedge, + TimingData => Tmkr_DIB8_CLKB_posedge, + TestSignal => DIB_ipd(8), + TestSignalName => "DIB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(8), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(8), + HoldLow => thold_DIB_CLKB_posedge_posedge(8), + HoldHigh => thold_DIB_CLKB_negedge_posedge(8), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB9_CLKB_posedge, + TimingData => Tmkr_DIB9_CLKB_posedge, + TestSignal => DIB_ipd(9), + TestSignalName => "DIB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(9), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(9), + HoldLow => thold_DIB_CLKB_posedge_posedge(9), + HoldHigh => thold_DIB_CLKB_negedge_posedge(9), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB10_CLKB_posedge, + TimingData => Tmkr_DIB10_CLKB_posedge, + TestSignal => DIB_ipd(10), + TestSignalName => "DIB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(10), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(10), + HoldLow => thold_DIB_CLKB_posedge_posedge(10), + HoldHigh => thold_DIB_CLKB_negedge_posedge(10), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB11_CLKB_posedge, + TimingData => Tmkr_DIB11_CLKB_posedge, + TestSignal => DIB_ipd(11), + TestSignalName => "DIB(11)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(11), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(11), + HoldLow => thold_DIB_CLKB_posedge_posedge(11), + HoldHigh => thold_DIB_CLKB_negedge_posedge(11), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB12_CLKB_posedge, + TimingData => Tmkr_DIB12_CLKB_posedge, + TestSignal => DIB_ipd(12), + TestSignalName => "DIB(12)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(12), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(12), + HoldLow => thold_DIB_CLKB_posedge_posedge(12), + HoldHigh => thold_DIB_CLKB_negedge_posedge(12), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB13_CLKB_posedge, + TimingData => Tmkr_DIB13_CLKB_posedge, + TestSignal => DIB_ipd(13), + TestSignalName => "DIB(13)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(13), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(13), + HoldLow => thold_DIB_CLKB_posedge_posedge(13), + HoldHigh => thold_DIB_CLKB_negedge_posedge(13), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB14_CLKB_posedge, + TimingData => Tmkr_DIB14_CLKB_posedge, + TestSignal => DIB_ipd(14), + TestSignalName => "DIB(14)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(14), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(14), + HoldLow => thold_DIB_CLKB_posedge_posedge(14), + HoldHigh => thold_DIB_CLKB_negedge_posedge(14), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB15_CLKB_posedge, + TimingData => Tmkr_DIB15_CLKB_posedge, + TestSignal => DIB_ipd(15), + TestSignalName => "DIB(15)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(15), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(15), + HoldLow => thold_DIB_CLKB_posedge_posedge(15), + HoldHigh => thold_DIB_CLKB_negedge_posedge(15), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB16_CLKB_posedge, + TimingData => Tmkr_DIB16_CLKB_posedge, + TestSignal => DIB_ipd(16), + TestSignalName => "DIB(16)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(16), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(16), + HoldLow => thold_DIB_CLKB_posedge_posedge(16), + HoldHigh => thold_DIB_CLKB_negedge_posedge(16), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB17_CLKB_posedge, + TimingData => Tmkr_DIB17_CLKB_posedge, + TestSignal => DIB_ipd(17), + TestSignalName => "DIB(17)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(17), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(17), + HoldLow => thold_DIB_CLKB_posedge_posedge(17), + HoldHigh => thold_DIB_CLKB_negedge_posedge(17), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB18_CLKB_posedge, + TimingData => Tmkr_DIB18_CLKB_posedge, + TestSignal => DIB_ipd(18), + TestSignalName => "DIB(18)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(18), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(18), + HoldLow => thold_DIB_CLKB_posedge_posedge(18), + HoldHigh => thold_DIB_CLKB_negedge_posedge(18), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB19_CLKB_posedge, + TimingData => Tmkr_DIB19_CLKB_posedge, + TestSignal => DIB_ipd(19), + TestSignalName => "DIB(19)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(19), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(19), + HoldLow => thold_DIB_CLKB_posedge_posedge(19), + HoldHigh => thold_DIB_CLKB_negedge_posedge(19), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB20_CLKB_posedge, + TimingData => Tmkr_DIB20_CLKB_posedge, + TestSignal => DIB_ipd(20), + TestSignalName => "DIB(20)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(20), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(20), + HoldLow => thold_DIB_CLKB_posedge_posedge(20), + HoldHigh => thold_DIB_CLKB_negedge_posedge(20), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB21_CLKB_posedge, + TimingData => Tmkr_DIB21_CLKB_posedge, + TestSignal => DIB_ipd(21), + TestSignalName => "DIB(21)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(21), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(21), + HoldLow => thold_DIB_CLKB_posedge_posedge(21), + HoldHigh => thold_DIB_CLKB_negedge_posedge(21), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB22_CLKB_posedge, + TimingData => Tmkr_DIB22_CLKB_posedge, + TestSignal => DIB_ipd(22), + TestSignalName => "DIB(22)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(22), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(22), + HoldLow => thold_DIB_CLKB_posedge_posedge(22), + HoldHigh => thold_DIB_CLKB_negedge_posedge(22), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB23_CLKB_posedge, + TimingData => Tmkr_DIB23_CLKB_posedge, + TestSignal => DIB_ipd(23), + TestSignalName => "DIB(23)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(23), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(23), + HoldLow => thold_DIB_CLKB_posedge_posedge(23), + HoldHigh => thold_DIB_CLKB_negedge_posedge(23), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB24_CLKB_posedge, + TimingData => Tmkr_DIB24_CLKB_posedge, + TestSignal => DIB_ipd(24), + TestSignalName => "DIB(24)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(24), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(24), + HoldLow => thold_DIB_CLKB_posedge_posedge(24), + HoldHigh => thold_DIB_CLKB_negedge_posedge(24), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB25_CLKB_posedge, + TimingData => Tmkr_DIB25_CLKB_posedge, + TestSignal => DIB_ipd(25), + TestSignalName => "DIB(25)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(25), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(25), + HoldLow => thold_DIB_CLKB_posedge_posedge(25), + HoldHigh => thold_DIB_CLKB_negedge_posedge(25), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB26_CLKB_posedge, + TimingData => Tmkr_DIB26_CLKB_posedge, + TestSignal => DIB_ipd(26), + TestSignalName => "DIB(26)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(26), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(26), + HoldLow => thold_DIB_CLKB_posedge_posedge(26), + HoldHigh => thold_DIB_CLKB_negedge_posedge(26), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB27_CLKB_posedge, + TimingData => Tmkr_DIB27_CLKB_posedge, + TestSignal => DIB_ipd(27), + TestSignalName => "DIB(27)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(27), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(27), + HoldLow => thold_DIB_CLKB_posedge_posedge(27), + HoldHigh => thold_DIB_CLKB_negedge_posedge(27), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB28_CLKB_posedge, + TimingData => Tmkr_DIB28_CLKB_posedge, + TestSignal => DIB_ipd(28), + TestSignalName => "DIB(28)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(28), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(28), + HoldLow => thold_DIB_CLKB_posedge_posedge(28), + HoldHigh => thold_DIB_CLKB_negedge_posedge(28), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB29_CLKB_posedge, + TimingData => Tmkr_DIB29_CLKB_posedge, + TestSignal => DIB_ipd(29), + TestSignalName => "DIB(29)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(29), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(29), + HoldLow => thold_DIB_CLKB_posedge_posedge(29), + HoldHigh => thold_DIB_CLKB_negedge_posedge(29), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB30_CLKB_posedge, + TimingData => Tmkr_DIB30_CLKB_posedge, + TestSignal => DIB_ipd(30), + TestSignalName => "DIB(30)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(30), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(30), + HoldLow => thold_DIB_CLKB_posedge_posedge(30), + HoldHigh => thold_DIB_CLKB_negedge_posedge(30), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S4_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_DIA2_CLKA_posedge or + Tviol_DIA3_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIB8_CLKB_posedge or + Tviol_DIB9_CLKB_posedge or + Tviol_DIB10_CLKB_posedge or + Tviol_DIB11_CLKB_posedge or + Tviol_DIB12_CLKB_posedge or + Tviol_DIB13_CLKB_posedge or + Tviol_DIB14_CLKB_posedge or + Tviol_DIB15_CLKB_posedge or + Tviol_DIB16_CLKB_posedge or + Tviol_DIB17_CLKB_posedge or + Tviol_DIB18_CLKB_posedge or + Tviol_DIB19_CLKB_posedge or + Tviol_DIB20_CLKB_posedge or + Tviol_DIB21_CLKB_posedge or + Tviol_DIB22_CLKB_posedge or + Tviol_DIB23_CLKB_posedge or + Tviol_DIB24_CLKB_posedge or + Tviol_DIB25_CLKB_posedge or + Tviol_DIB26_CLKB_posedge or + Tviol_DIB27_CLKB_posedge or + Tviol_DIB28_CLKB_posedge or + Tviol_DIB29_CLKB_posedge or + Tviol_DIB30_CLKB_posedge or + Tviol_DIB31_CLKB_posedge or + Tviol_DIPB0_CLKB_posedge or + Tviol_DIPB1_CLKB_posedge or + Tviol_DIPB2_CLKB_posedge or + Tviol_DIPB3_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S36", + InstanceName => ramb16_s4_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S4_S36", + InstanceName => ramb16_s4_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S36", + InstanceName => ramb16_s4_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S4_S36", + InstanceName => ramb16_s4_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S36", + InstanceName => ramb16_s4_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S4_S36", + InstanceName => ramb16_s4_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S4_S36", + InstanceName => ramb16_s4_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(3 downto 0); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + DOPB_zd := DIPB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S36", + InstanceName => ramb16_s4_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S4_S36", + InstanceName => ramb16_s4_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S36", + InstanceName => ramb16_s4_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S4_S36", + InstanceName => ramb16_s4_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S36", + InstanceName => ramb16_s4_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S4_S36", + InstanceName => ramb16_s4_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S4_S36", + InstanceName => ramb16_s4_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(31 downto 0); + DOPB_zd := SRVA_B(35 downto 32); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOB_zd(8) := ViolationB xor DOB_zd(8); + DOB_zd(9) := ViolationB xor DOB_zd(9); + DOB_zd(10) := ViolationB xor DOB_zd(10); + DOB_zd(11) := ViolationB xor DOB_zd(11); + DOB_zd(12) := ViolationB xor DOB_zd(12); + DOB_zd(13) := ViolationB xor DOB_zd(13); + DOB_zd(14) := ViolationB xor DOB_zd(14); + DOB_zd(15) := ViolationB xor DOB_zd(15); + DOB_zd(16) := ViolationB xor DOB_zd(16); + DOB_zd(17) := ViolationB xor DOB_zd(17); + DOB_zd(18) := ViolationB xor DOB_zd(18); + DOB_zd(19) := ViolationB xor DOB_zd(19); + DOB_zd(20) := ViolationB xor DOB_zd(20); + DOB_zd(21) := ViolationB xor DOB_zd(21); + DOB_zd(22) := ViolationB xor DOB_zd(22); + DOB_zd(23) := ViolationB xor DOB_zd(23); + DOB_zd(24) := ViolationB xor DOB_zd(24); + DOB_zd(25) := ViolationB xor DOB_zd(25); + DOB_zd(26) := ViolationB xor DOB_zd(26); + DOB_zd(27) := ViolationB xor DOB_zd(27); + DOB_zd(28) := ViolationB xor DOB_zd(28); + DOB_zd(29) := ViolationB xor DOB_zd(29); + DOB_zd(30) := ViolationB xor DOB_zd(30); + DOB_zd(31) := ViolationB xor DOB_zd(31); + DOPB_zd(0) := ViolationB xor DOPB_zd(0); + DOPB_zd(1) := ViolationB xor DOPB_zd(1); + DOPB_zd(2) := ViolationB xor DOPB_zd(2); + DOPB_zd(3) := ViolationB xor DOPB_zd(3); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(2), + GlitchData => DOA_GlitchData2, + OutSignalName => "DOA(2)", + OutTemp => DOA_zd(2), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(3), + GlitchData => DOA_GlitchData3, + OutSignalName => "DOA(3)", + OutTemp => DOA_zd(3), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(8), + GlitchData => DOB_GlitchData8, + OutSignalName => "DOB(8)", + OutTemp => DOB_zd(8), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(9), + GlitchData => DOB_GlitchData9, + OutSignalName => "DOB(9)", + OutTemp => DOB_zd(9), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(10), + GlitchData => DOB_GlitchData10, + OutSignalName => "DOB(10)", + OutTemp => DOB_zd(10), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(11), + GlitchData => DOB_GlitchData11, + OutSignalName => "DOB(11)", + OutTemp => DOB_zd(11), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(12), + GlitchData => DOB_GlitchData12, + OutSignalName => "DOB(12)", + OutTemp => DOB_zd(12), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(13), + GlitchData => DOB_GlitchData13, + OutSignalName => "DOB(13)", + OutTemp => DOB_zd(13), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(14), + GlitchData => DOB_GlitchData14, + OutSignalName => "DOB(14)", + OutTemp => DOB_zd(14), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(15), + GlitchData => DOB_GlitchData15, + OutSignalName => "DOB(15)", + OutTemp => DOB_zd(15), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(16), + GlitchData => DOB_GlitchData16, + OutSignalName => "DOB(16)", + OutTemp => DOB_zd(16), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(16), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(17), + GlitchData => DOB_GlitchData17, + OutSignalName => "DOB(17)", + OutTemp => DOB_zd(17), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(17), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(18), + GlitchData => DOB_GlitchData18, + OutSignalName => "DOB(18)", + OutTemp => DOB_zd(18), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(18), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(19), + GlitchData => DOB_GlitchData19, + OutSignalName => "DOB(19)", + OutTemp => DOB_zd(19), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(19), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(20), + GlitchData => DOB_GlitchData20, + OutSignalName => "DOB(20)", + OutTemp => DOB_zd(20), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(20), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(21), + GlitchData => DOB_GlitchData21, + OutSignalName => "DOB(21)", + OutTemp => DOB_zd(21), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(21), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(22), + GlitchData => DOB_GlitchData22, + OutSignalName => "DOB(22)", + OutTemp => DOB_zd(22), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(22), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(23), + GlitchData => DOB_GlitchData23, + OutSignalName => "DOB(23)", + OutTemp => DOB_zd(23), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(23), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(24), + GlitchData => DOB_GlitchData24, + OutSignalName => "DOB(24)", + OutTemp => DOB_zd(24), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(24), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(25), + GlitchData => DOB_GlitchData25, + OutSignalName => "DOB(25)", + OutTemp => DOB_zd(25), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(25), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(26), + GlitchData => DOB_GlitchData26, + OutSignalName => "DOB(26)", + OutTemp => DOB_zd(26), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(26), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(27), + GlitchData => DOB_GlitchData27, + OutSignalName => "DOB(27)", + OutTemp => DOB_zd(27), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(27), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(28), + GlitchData => DOB_GlitchData28, + OutSignalName => "DOB(28)", + OutTemp => DOB_zd(28), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(28), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(29), + GlitchData => DOB_GlitchData29, + OutSignalName => "DOB(29)", + OutTemp => DOB_zd(29), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(29), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(30), + GlitchData => DOB_GlitchData30, + OutSignalName => "DOB(30)", + OutTemp => DOB_zd(30), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(30), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(31), + GlitchData => DOB_GlitchData31, + OutSignalName => "DOB(31)", + OutTemp => DOB_zd(31), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(31), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(0), + GlitchData => DOPB_GlitchData0, + OutSignalName => "DOPB(0)", + OutTemp => DOPB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(1), + GlitchData => DOPB_GlitchData1, + OutSignalName => "DOPB(1)", + OutTemp => DOPB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(2), + GlitchData => DOPB_GlitchData2, + OutSignalName => "DOPB(2)", + OutTemp => DOPB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(3), + GlitchData => DOPB_GlitchData3, + OutSignalName => "DOPB(3)", + OutTemp => DOPB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S4_S36_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S4_S4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s4_s4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S4_S4 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(11 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(11 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"0"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"0"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(3 downto 0); + DOB : out std_logic_vector(3 downto 0); + + ADDRA : in std_logic_vector(11 downto 0); + ADDRB : in std_logic_vector(11 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(3 downto 0); + DIB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S4_S4 : entity is true; +end ramb16_s4_s4; + +architecture RAMB16_S4_S4_V of RAMB16_S4_S4 is + attribute VITAL_LEVEL0 of + RAMB16_S4_S4_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(11 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(11 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 4096; + constant length_b : integer := 4096; + constant width_a : integer := 4; + constant width_b : integer := 4; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 11 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 11 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + variable DOA_GlitchData2 : VitalGlitchDataType; + variable DOA_GlitchData3 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (3 downto 0) := "0000"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (3 downto 0) := "0000"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (3 downto 0) := "0000"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (3 downto 0) := "0000"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(3 downto 0) := INI_A(3 downto 0); + variable DOB_zd : std_logic_vector(3 downto 0) := INI_B(3 downto 0); + + variable ADDRA_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S4_S4", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 4) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(3 downto 0) := INI_A_UNBOUND(3 downto 0); + + for I in INI_A_UNBOUND'high downto 4 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 4 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S4_S4", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 4) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S4_S4", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 4) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 4) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(3 downto 0) := INI_B_UNBOUND(3 downto 0); + + for I in INI_B_UNBOUND'high downto 4 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 4 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S4_S4", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 4) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S4_S4", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 4) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 4) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(3 downto 0) := SRVA_A_UNBOUND(3 downto 0); + + for I in SRVA_A_UNBOUND'high downto 4 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 4 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S4_S4", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 4) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S4_S4", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 4) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 4) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(3 downto 0) := SRVA_B_UNBOUND(3 downto 0); + + for I in SRVA_B_UNBOUND'high downto 4 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 4 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S4_S4", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 4) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S4_S4", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 4) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(3 downto 0) := INI_A(3 downto 0); + DOB_zd(3 downto 0) := INI_B(3 downto 0); + DOA <= DOA_zd; + DOB <= DOB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S4_S4", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S4_S4", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA1_CLKA_posedge, + TimingData => Tmkr_DIA1_CLKA_posedge, + TestSignal => DIA_ipd(1), + TestSignalName => "DIA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(1), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(1), + HoldLow => thold_DIA_CLKA_posedge_posedge(1), + HoldHigh => thold_DIA_CLKA_negedge_posedge(1), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA2_CLKA_posedge, + TimingData => Tmkr_DIA2_CLKA_posedge, + TestSignal => DIA_ipd(2), + TestSignalName => "DIA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(2), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(2), + HoldLow => thold_DIA_CLKA_posedge_posedge(2), + HoldHigh => thold_DIA_CLKA_negedge_posedge(2), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB9_CLKB_posedge, + TimingData => Tmkr_ADDRB9_CLKB_posedge, + TestSignal => ADDRB_ipd(9), + TestSignalName => "ADDRB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(9), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(9), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(9), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(9), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB10_CLKB_posedge, + TimingData => Tmkr_ADDRB10_CLKB_posedge, + TestSignal => ADDRB_ipd(10), + TestSignalName => "ADDRB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(10), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(10), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(10), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(10), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_DIA2_CLKA_posedge or + Tviol_DIA3_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_ADDRB10_CLKB_posedge or + Tviol_ADDRB11_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S4", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S4", + InstanceName => ramb16_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S4_S4", + InstanceName => ramb16_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S4", + InstanceName => ramb16_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S4_S4", + InstanceName => ramb16_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S4", + InstanceName => ramb16_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S4_S4", + InstanceName => ramb16_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S4_S4", + InstanceName => ramb16_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(3 downto 0); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S4", + InstanceName => ramb16_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S4_S4", + InstanceName => ramb16_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S4", + InstanceName => ramb16_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S4_S4", + InstanceName => ramb16_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S4", + InstanceName => ramb16_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S4_S4", + InstanceName => ramb16_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S4_S4", + InstanceName => ramb16_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(3 downto 0); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + end if; + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(2), + GlitchData => DOA_GlitchData2, + OutSignalName => "DOA(2)", + OutTemp => DOA_zd(2), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(3), + GlitchData => DOA_GlitchData3, + OutSignalName => "DOA(3)", + OutTemp => DOA_zd(3), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S4_S4_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S4_S9.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s4_s9 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S4_S9 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(11 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(10 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPB : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOPB : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"0"; + INIT_B : bit_vector := X"000"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"0"; + SRVAL_B : bit_vector := X"000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(3 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPB : out std_logic_vector(0 downto 0); + + ADDRA : in std_logic_vector(11 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(3 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S4_S9 : entity is true; +end ramb16_s4_s9; + +architecture RAMB16_S4_S9_V of RAMB16_S4_S9 is + attribute VITAL_LEVEL0 of + RAMB16_S4_S9_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(11 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(10 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(7 downto 0) := (others => 'X'); + signal DIPB_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 4096; + constant length_b : integer := 2048; + constant width_a : integer := 4; + constant width_b : integer := 8; + + constant parity_width_b : integer := 1; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + + function slv_to_two_D_parity_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_parity_array_type is + variable two_D_parity_array : two_D_parity_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_parity_array(i) := intermediate; + end loop; + return two_D_parity_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 11 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 10 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 7 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + DIPB_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i)); + end generate DIPB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + variable DOA_GlitchData2 : VitalGlitchDataType; + variable DOA_GlitchData3 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOPB_GlitchData0 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) & + To_StdLogicVector(INITP_06) & + To_StdLogicVector(INITP_05) & + To_StdLogicVector(INITP_04) & + To_StdLogicVector(INITP_03) & + To_StdLogicVector(INITP_02) & + To_StdLogicVector(INITP_01) & + To_StdLogicVector(INITP_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOPB_OV_LSB : integer := 0; + variable DOPB_OV_MSB : integer := 0; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (3 downto 0) := "0000"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (8 downto 0) := "000000000"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (3 downto 0) := "0000"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (8 downto 0) := "000000000"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(3 downto 0) := INI_A(3 downto 0); + variable DOB_zd : std_logic_vector(7 downto 0) := INI_B(7 downto 0); + variable DOPB_zd : std_logic_vector(0 downto 0) := INI_B(8 downto 8); + + variable ADDRA_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S4_S9", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 4) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(3 downto 0) := INI_A_UNBOUND(3 downto 0); + + for I in INI_A_UNBOUND'high downto 4 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 4 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S4_S9", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 4) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S4_S9", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 4) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 9) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(8 downto 0) := INI_B_UNBOUND(8 downto 0); + + for I in INI_B_UNBOUND'high downto 9 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 9 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S4_S9", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 9) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S4_S9", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 9) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 4) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(3 downto 0) := SRVA_A_UNBOUND(3 downto 0); + + for I in SRVA_A_UNBOUND'high downto 4 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 4 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S4_S9", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 4) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S4_S9", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 4, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 4) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 9) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(8 downto 0) := SRVA_B_UNBOUND(8 downto 0); + + for I in SRVA_B_UNBOUND'high downto 9 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 9 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S4_S9", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 9) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S4_S9", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 9) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(3 downto 0) := INI_A(3 downto 0); + DOB_zd(7 downto 0) := INI_B(7 downto 0); + DOPB_zd(0 downto 0) := INI_B(8 downto 8); + DOA <= DOA_zd; + DOB <= DOB_zd; + DOPB <= DOPB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S4_S9", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S4_S9", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA1_CLKA_posedge, + TimingData => Tmkr_DIA1_CLKA_posedge, + TestSignal => DIA_ipd(1), + TestSignalName => "DIA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(1), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(1), + HoldLow => thold_DIA_CLKA_posedge_posedge(1), + HoldHigh => thold_DIA_CLKA_negedge_posedge(1), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA2_CLKA_posedge, + TimingData => Tmkr_DIA2_CLKA_posedge, + TestSignal => DIA_ipd(2), + TestSignalName => "DIA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(2), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(2), + HoldLow => thold_DIA_CLKA_posedge_posedge(2), + HoldHigh => thold_DIA_CLKA_negedge_posedge(2), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB9_CLKB_posedge, + TimingData => Tmkr_ADDRB9_CLKB_posedge, + TestSignal => ADDRB_ipd(9), + TestSignalName => "ADDRB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(9), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(9), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(9), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(9), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S4_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_DIA2_CLKA_posedge or + Tviol_DIA3_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_ADDRB10_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIPB0_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S4_S9", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S9", + InstanceName => ramb16_s4_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S4_S9", + InstanceName => ramb16_s4_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S9", + InstanceName => ramb16_s4_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S4_S9", + InstanceName => ramb16_s4_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S9", + InstanceName => ramb16_s4_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S4_S9", + InstanceName => ramb16_s4_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S4_S9", + InstanceName => ramb16_s4_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(3 downto 0); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + DOPB_zd := DIPB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S9", + InstanceName => ramb16_s4_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S4_S9", + InstanceName => ramb16_s4_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S9", + InstanceName => ramb16_s4_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S4_S9", + InstanceName => ramb16_s4_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S4_S9", + InstanceName => ramb16_s4_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S4_S9", + InstanceName => ramb16_s4_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S4_S9", + InstanceName => ramb16_s4_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(7 downto 0); + DOPB_zd := SRVA_B(8 downto 8); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOPB_zd(0) := ViolationB xor DOPB_zd(0); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(2), + GlitchData => DOA_GlitchData2, + OutSignalName => "DOA(2)", + OutTemp => DOA_zd(2), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(3), + GlitchData => DOA_GlitchData3, + OutSignalName => "DOA(3)", + OutTemp => DOA_zd(3), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(0), + GlitchData => DOPB_GlitchData0, + OutSignalName => "DOPB(0)", + OutTemp => DOPB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S4_S9_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb16_s9.vhd,v 1.7 2005/10/07 18:35:24 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +-- /___/ /\ Filename : RAMB16_S9.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:53 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 09/26/05 - Fixed CR# 216846. INIT and SRVAL attributes length check and adjustment. +-- END Revision + +----- CELL RAMB16_S9 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S9 is + + generic ( + INIT : bit_vector := X"000"; + SRVAL : bit_vector := X"000"; + WRITE_MODE : string := "WRITE_FIRST"; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + + port ( + DO : out STD_LOGIC_VECTOR (7 downto 0); + DOP : out STD_LOGIC_VECTOR (0 downto 0); + + ADDR : in STD_LOGIC_VECTOR (10 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (7 downto 0); + DIP : in STD_LOGIC_VECTOR (0 downto 0); + EN : in STD_ULOGIC; + SSR : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end RAMB16_S9; + +architecture RAMB16_S9_V of RAMB16_S9 is + constant length : integer := 2048; + constant width : integer := 8; + + constant parity_width : integer := 1; + + type Two_D_array_type is array ((length - 1) downto 0) of std_logic_vector((width - 1) downto 0); + type Two_D_parity_array_type is array ((length - 1) downto 0) of std_logic_vector((parity_width - 1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + + function slv_to_two_D_parity_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_parity_array_type is + variable two_D_parity_array : two_D_parity_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_parity_array(i) := intermediate; + end loop; + return two_D_parity_array; + end; +begin + VITALBehavior : process + variable address : integer; + variable valid_addr : boolean := FALSE; + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F & INIT_3E & INIT_3D & INIT_3C & + INIT_3B & INIT_3A & INIT_39 & INIT_38 & + INIT_37 & INIT_36 & INIT_35 & INIT_34 & + INIT_33 & INIT_32 & INIT_31 & INIT_30 & + INIT_2F & INIT_2E & INIT_2D & INIT_2C & + INIT_2B & INIT_2A & INIT_29 & INIT_28 & + INIT_27 & INIT_26 & INIT_25 & INIT_24 & + INIT_23 & INIT_22 & INIT_21 & INIT_20 & + INIT_1F & INIT_1E & INIT_1D & INIT_1C & + INIT_1B & INIT_1A & INIT_19 & INIT_18 & + INIT_17 & INIT_16 & INIT_15 & INIT_14 & + INIT_13 & INIT_12 & INIT_11 & INIT_10 & + INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + + variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07 & INITP_06 & INITP_05 & INITP_04 & + INITP_03 & INITP_02 & INITP_01 & INITP_00); + variable mem : Two_D_array_type := slv_to_two_D_array(length, width, mem_slv); + variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length, parity_width, memp_slv); + + variable wr_mode : integer := 0; + variable first_time : boolean := true; + + variable INIT_reg : std_logic_vector (8 downto 0) := "000000000"; + variable SRVAL_reg : std_logic_vector (8 downto 0) := "000000000"; + begin + if (first_time) then + if ((WRITE_MODE = "write_first") or (WRITE_MODE = "WRITE_FIRST")) then + wr_mode := 0; + elsif ((WRITE_MODE = "read_first") or (WRITE_MODE = "READ_FIRST")) then + wr_mode := 1; + elsif ((WRITE_MODE = "no_change") or (WRITE_MODE = "NO_CHANGE")) then + wr_mode := 2; + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Error ", + GenericName => " WRITE_MODE ", + EntityName => "/RAMB16_S9", + GenericValue => WRITE_MODE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if (INIT'length > 9) then + INIT_reg(8 downto 0) := To_StdLogicVector(INIT)(8 downto 0); + else + INIT_reg(INIT'length-1 downto 0) := To_StdLogicVector(INIT); + end if; + DO <= INIT_reg(7 downto 0); + DOP <= INIT_reg(8 downto 8); + if (SRVAL'length > 9) then + SRVAL_reg(8 downto 0) := To_StdLogicVector(SRVAL)(8 downto 0); + else + SRVAL_reg(SRVAL'length-1 downto 0) := To_StdLogicVector(SRVAL); + end if; + first_time := false; + end if; + + valid_addr := addr_is_valid(addr); + + if (valid_addr) then + address := slv_to_int(addr); + end if; + + if (rising_edge(CLK)) then + if (EN = '1') then + if (SSR = '1') then + DO <= SRVAL_reg(7 downto 0) after 100 ps; + DOP <= SRVAL_reg(8 downto 8) after 100 ps; + else + if (WE = '1') then + if (wr_mode = 0) then + DO <= DI after 100 ps; + DOP <= DIP after 100 ps; + elsif (wr_mode = 1) then + DO <= mem(address) after 100 ps; + DOP <= memp(address) after 100 ps; + end if; + else + if (valid_addr) then + DO <= mem(address) after 100 ps; + DOP <= memp(address) after 100 ps; + end if; + end if; + end if; + if (WE = '1') then + if (valid_addr) then + mem(address) := DI; + memp(address) := DIP; + end if; + end if; + end if; + end if; + wait on CLK; + end process VITALBehavior; +end RAMB16_S9_V; + + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S9_S18.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s9_s18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S9_S18 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(10 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(9 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPB : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKA_DOPA : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOPB : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIPA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIPA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIPA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIPA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"000"; + INIT_B : bit_vector := X"00000"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"000"; + SRVAL_B : bit_vector := X"00000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(7 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPA : out std_logic_vector(0 downto 0); + DOPB : out std_logic_vector(1 downto 0); + + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(7 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPA : in std_logic_vector(0 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S9_S18 : entity is true; +end ramb16_s9_s18; + +architecture RAMB16_S9_S18_V of RAMB16_S9_S18 is + attribute VITAL_LEVEL0 of + RAMB16_S9_S18_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(10 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(7 downto 0) := (others => 'X'); + signal DIPA_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(9 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(15 downto 0) := (others => 'X'); + signal DIPB_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 2048; + constant length_b : integer := 1024; + constant width_a : integer := 8; + constant width_b : integer := 16; + + constant parity_width_a : integer := 1; + constant parity_width_b : integer := 2; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + + function slv_to_two_D_parity_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_parity_array_type is + variable two_D_parity_array : two_D_parity_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_parity_array(i) := intermediate; + end loop; + return two_D_parity_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 10 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 7 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + DIPA_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIPA_ipd(i), DIPA(i), tipd_DIPA(i)); + end generate DIPA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 9 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 15 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + DIPB_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i)); + end generate DIPB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIPA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB12_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB13_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB14_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB15_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB13_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB14_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB15_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + variable DOA_GlitchData2 : VitalGlitchDataType; + variable DOA_GlitchData3 : VitalGlitchDataType; + variable DOA_GlitchData4 : VitalGlitchDataType; + variable DOA_GlitchData5 : VitalGlitchDataType; + variable DOA_GlitchData6 : VitalGlitchDataType; + variable DOA_GlitchData7 : VitalGlitchDataType; + variable DOPA_GlitchData0 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOB_GlitchData8 : VitalGlitchDataType; + variable DOB_GlitchData9 : VitalGlitchDataType; + variable DOB_GlitchData10 : VitalGlitchDataType; + variable DOB_GlitchData11 : VitalGlitchDataType; + variable DOB_GlitchData12 : VitalGlitchDataType; + variable DOB_GlitchData13 : VitalGlitchDataType; + variable DOB_GlitchData14 : VitalGlitchDataType; + variable DOB_GlitchData15 : VitalGlitchDataType; + variable DOPB_GlitchData0 : VitalGlitchDataType; + variable DOPB_GlitchData1 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) & + To_StdLogicVector(INITP_06) & + To_StdLogicVector(INITP_05) & + To_StdLogicVector(INITP_04) & + To_StdLogicVector(INITP_03) & + To_StdLogicVector(INITP_02) & + To_StdLogicVector(INITP_01) & + To_StdLogicVector(INITP_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOPA_OV_LSB : integer := 0; + variable DOPA_OV_MSB : integer := 0; + variable DOPB_OV_LSB : integer := 0; + variable DOPB_OV_MSB : integer := 1; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (8 downto 0) := "000000000"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (17 downto 0) := "000000000000000000"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (8 downto 0) := "000000000"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (17 downto 0) := "000000000000000000"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(7 downto 0) := INI_A(7 downto 0); + variable DOB_zd : std_logic_vector(15 downto 0) := INI_B(15 downto 0); + variable DOPA_zd : std_logic_vector(0 downto 0) := INI_A(8 downto 8); + variable DOPB_zd : std_logic_vector(1 downto 0) := INI_B(17 downto 16); + + variable ADDRA_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S9_S18", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 9) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(8 downto 0) := INI_A_UNBOUND(8 downto 0); + + for I in INI_A_UNBOUND'high downto 9 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 9 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S9_S18", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 9) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S9_S18", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 9) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 18) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(17 downto 0) := INI_B_UNBOUND(17 downto 0); + + for I in INI_B_UNBOUND'high downto 18 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 18 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S9_S18", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 18) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S9_S18", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 18) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 9) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(8 downto 0) := SRVA_A_UNBOUND(8 downto 0); + + for I in SRVA_A_UNBOUND'high downto 9 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 9 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S9_S18", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 9) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S9_S18", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 9) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 18) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(17 downto 0) := SRVA_B_UNBOUND(17 downto 0); + + for I in SRVA_B_UNBOUND'high downto 18 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 18 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S9_S18", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 18) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S9_S18", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 18, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 18) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(7 downto 0) := INI_A(7 downto 0); + DOB_zd(15 downto 0) := INI_B(15 downto 0); + DOPA_zd(0 downto 0) := INI_A(8 downto 8); + DOPB_zd(1 downto 0) := INI_B(17 downto 16); + DOA <= DOA_zd; + DOPA <= DOPA_zd; + DOB <= DOB_zd; + DOPB <= DOPB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S9_S18", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S9_S18", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA1_CLKA_posedge, + TimingData => Tmkr_DIA1_CLKA_posedge, + TestSignal => DIA_ipd(1), + TestSignalName => "DIA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(1), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(1), + HoldLow => thold_DIA_CLKA_posedge_posedge(1), + HoldHigh => thold_DIA_CLKA_negedge_posedge(1), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA2_CLKA_posedge, + TimingData => Tmkr_DIA2_CLKA_posedge, + TestSignal => DIA_ipd(2), + TestSignalName => "DIA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(2), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(2), + HoldLow => thold_DIA_CLKA_posedge_posedge(2), + HoldHigh => thold_DIA_CLKA_negedge_posedge(2), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA3_CLKA_posedge, + TimingData => Tmkr_DIA3_CLKA_posedge, + TestSignal => DIA_ipd(3), + TestSignalName => "DIA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(3), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(3), + HoldLow => thold_DIA_CLKA_posedge_posedge(3), + HoldHigh => thold_DIA_CLKA_negedge_posedge(3), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA4_CLKA_posedge, + TimingData => Tmkr_DIA4_CLKA_posedge, + TestSignal => DIA_ipd(4), + TestSignalName => "DIA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(4), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(4), + HoldLow => thold_DIA_CLKA_posedge_posedge(4), + HoldHigh => thold_DIA_CLKA_negedge_posedge(4), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA5_CLKA_posedge, + TimingData => Tmkr_DIA5_CLKA_posedge, + TestSignal => DIA_ipd(5), + TestSignalName => "DIA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(5), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(5), + HoldLow => thold_DIA_CLKA_posedge_posedge(5), + HoldHigh => thold_DIA_CLKA_negedge_posedge(5), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA6_CLKA_posedge, + TimingData => Tmkr_DIA6_CLKA_posedge, + TestSignal => DIA_ipd(6), + TestSignalName => "DIA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(6), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(6), + HoldLow => thold_DIA_CLKA_posedge_posedge(6), + HoldHigh => thold_DIA_CLKA_negedge_posedge(6), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB0_CLKB_posedge, + TimingData => Tmkr_DIPB0_CLKB_posedge, + TestSignal => DIPB_ipd(0), + TestSignalName => "DIPB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(0), + HoldLow => thold_DIPB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB7_CLKB_posedge, + TimingData => Tmkr_DIB7_CLKB_posedge, + TestSignal => DIB_ipd(7), + TestSignalName => "DIB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(7), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(7), + HoldLow => thold_DIB_CLKB_posedge_posedge(7), + HoldHigh => thold_DIB_CLKB_negedge_posedge(7), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB8_CLKB_posedge, + TimingData => Tmkr_DIB8_CLKB_posedge, + TestSignal => DIB_ipd(8), + TestSignalName => "DIB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(8), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(8), + HoldLow => thold_DIB_CLKB_posedge_posedge(8), + HoldHigh => thold_DIB_CLKB_negedge_posedge(8), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB9_CLKB_posedge, + TimingData => Tmkr_DIB9_CLKB_posedge, + TestSignal => DIB_ipd(9), + TestSignalName => "DIB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(9), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(9), + HoldLow => thold_DIB_CLKB_posedge_posedge(9), + HoldHigh => thold_DIB_CLKB_negedge_posedge(9), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB10_CLKB_posedge, + TimingData => Tmkr_DIB10_CLKB_posedge, + TestSignal => DIB_ipd(10), + TestSignalName => "DIB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(10), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(10), + HoldLow => thold_DIB_CLKB_posedge_posedge(10), + HoldHigh => thold_DIB_CLKB_negedge_posedge(10), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB11_CLKB_posedge, + TimingData => Tmkr_DIB11_CLKB_posedge, + TestSignal => DIB_ipd(11), + TestSignalName => "DIB(11)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(11), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(11), + HoldLow => thold_DIB_CLKB_posedge_posedge(11), + HoldHigh => thold_DIB_CLKB_negedge_posedge(11), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB12_CLKB_posedge, + TimingData => Tmkr_DIB12_CLKB_posedge, + TestSignal => DIB_ipd(12), + TestSignalName => "DIB(12)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(12), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(12), + HoldLow => thold_DIB_CLKB_posedge_posedge(12), + HoldHigh => thold_DIB_CLKB_negedge_posedge(12), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB13_CLKB_posedge, + TimingData => Tmkr_DIB13_CLKB_posedge, + TestSignal => DIB_ipd(13), + TestSignalName => "DIB(13)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(13), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(13), + HoldLow => thold_DIB_CLKB_posedge_posedge(13), + HoldHigh => thold_DIB_CLKB_negedge_posedge(13), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB14_CLKB_posedge, + TimingData => Tmkr_DIB14_CLKB_posedge, + TestSignal => DIB_ipd(14), + TestSignalName => "DIB(14)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(14), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(14), + HoldLow => thold_DIB_CLKB_posedge_posedge(14), + HoldHigh => thold_DIB_CLKB_negedge_posedge(14), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S9_S18", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_DIA2_CLKA_posedge or + Tviol_DIA3_CLKA_posedge or + Tviol_DIA4_CLKA_posedge or + Tviol_DIA5_CLKA_posedge or + Tviol_DIA6_CLKA_posedge or + Tviol_DIA7_CLKA_posedge or + Tviol_DIPA0_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIB8_CLKB_posedge or + Tviol_DIB9_CLKB_posedge or + Tviol_DIB10_CLKB_posedge or + Tviol_DIB11_CLKB_posedge or + Tviol_DIB12_CLKB_posedge or + Tviol_DIB13_CLKB_posedge or + Tviol_DIB14_CLKB_posedge or + Tviol_DIB15_CLKB_posedge or + Tviol_DIPB0_CLKB_posedge or + Tviol_DIPB1_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + addr_overlap (address_a, address_b, parity_width_a, parity_width_b, has_overlap_p, olpp_lsb, olpp_msb, dopa_ov_lsb, dopa_ov_msb, dopb_ov_lsb, dopb_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S18", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + DOPA_zd := DIPA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S9_S18", + InstanceName => ramb16_s9_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S9_S18", + InstanceName => ramb16_s9_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S9_S18", + InstanceName => ramb16_s9_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S9_S18", + InstanceName => ramb16_s9_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S9_S18", + InstanceName => ramb16_s9_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S9_S18", + InstanceName => ramb16_s9_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S9_S18", + InstanceName => ramb16_s9_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(7 downto 0); + DOPA_zd := SRVA_A(8 downto 8); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + DOPB_zd := DIPB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S9_S18", + InstanceName => ramb16_s9_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S9_S18", + InstanceName => ramb16_s9_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S9_S18", + InstanceName => ramb16_s9_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S9_S18", + InstanceName => ramb16_s9_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S9_S18", + InstanceName => ramb16_s9_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S9_S18", + InstanceName => ramb16_s9_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S9_S18", + InstanceName => ramb16_s9_s18'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(15 downto 0); + DOPB_zd := SRVA_B(17 downto 16); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + DOA_zd(1) := ViolationA xor DOA_zd(1); + DOA_zd(2) := ViolationA xor DOA_zd(2); + DOA_zd(3) := ViolationA xor DOA_zd(3); + DOA_zd(4) := ViolationA xor DOA_zd(4); + DOA_zd(5) := ViolationA xor DOA_zd(5); + DOA_zd(6) := ViolationA xor DOA_zd(6); + DOA_zd(7) := ViolationA xor DOA_zd(7); + DOPA_zd(0) := ViolationA xor DOPA_zd(0); + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOB_zd(8) := ViolationB xor DOB_zd(8); + DOB_zd(9) := ViolationB xor DOB_zd(9); + DOB_zd(10) := ViolationB xor DOB_zd(10); + DOB_zd(11) := ViolationB xor DOB_zd(11); + DOB_zd(12) := ViolationB xor DOB_zd(12); + DOB_zd(13) := ViolationB xor DOB_zd(13); + DOB_zd(14) := ViolationB xor DOB_zd(14); + DOB_zd(15) := ViolationB xor DOB_zd(15); + DOPB_zd(0) := ViolationB xor DOPB_zd(0); + DOPB_zd(1) := ViolationB xor DOPB_zd(1); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(2), + GlitchData => DOA_GlitchData2, + OutSignalName => "DOA(2)", + OutTemp => DOA_zd(2), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(3), + GlitchData => DOA_GlitchData3, + OutSignalName => "DOA(3)", + OutTemp => DOA_zd(3), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(4), + GlitchData => DOA_GlitchData4, + OutSignalName => "DOA(4)", + OutTemp => DOA_zd(4), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(5), + GlitchData => DOA_GlitchData5, + OutSignalName => "DOA(5)", + OutTemp => DOA_zd(5), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(6), + GlitchData => DOA_GlitchData6, + OutSignalName => "DOA(6)", + OutTemp => DOA_zd(6), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(7), + GlitchData => DOA_GlitchData7, + OutSignalName => "DOA(7)", + OutTemp => DOA_zd(7), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPA(0), + GlitchData => DOPA_GlitchData0, + OutSignalName => "DOPA(0)", + OutTemp => DOPA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(8), + GlitchData => DOB_GlitchData8, + OutSignalName => "DOB(8)", + OutTemp => DOB_zd(8), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(9), + GlitchData => DOB_GlitchData9, + OutSignalName => "DOB(9)", + OutTemp => DOB_zd(9), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(10), + GlitchData => DOB_GlitchData10, + OutSignalName => "DOB(10)", + OutTemp => DOB_zd(10), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(11), + GlitchData => DOB_GlitchData11, + OutSignalName => "DOB(11)", + OutTemp => DOB_zd(11), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(12), + GlitchData => DOB_GlitchData12, + OutSignalName => "DOB(12)", + OutTemp => DOB_zd(12), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(13), + GlitchData => DOB_GlitchData13, + OutSignalName => "DOB(13)", + OutTemp => DOB_zd(13), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(14), + GlitchData => DOB_GlitchData14, + OutSignalName => "DOB(14)", + OutTemp => DOB_zd(14), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(15), + GlitchData => DOB_GlitchData15, + OutSignalName => "DOB(15)", + OutTemp => DOB_zd(15), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(0), + GlitchData => DOPB_GlitchData0, + OutSignalName => "DOPB(0)", + OutTemp => DOPB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(1), + GlitchData => DOPB_GlitchData1, + OutSignalName => "DOPB(1)", + OutTemp => DOPB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPA_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S9_S18_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S9_S36.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s9_s36 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S9_S36 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(10 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(8 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPB : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKA_DOPA : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(31 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOPB : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIPA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIPA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIPA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIPA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(31 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"000"; + INIT_B : bit_vector := X"000000000"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"000"; + SRVAL_B : bit_vector := X"000000000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(7 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(0 downto 0); + DOPB : out std_logic_vector(3 downto 0); + + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(7 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(0 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S9_S36 : entity is true; +end ramb16_s9_s36; + +architecture RAMB16_S9_S36_V of RAMB16_S9_S36 is + attribute VITAL_LEVEL0 of + RAMB16_S9_S36_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(10 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(7 downto 0) := (others => 'X'); + signal DIPA_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(8 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(31 downto 0) := (others => 'X'); + signal DIPB_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 2048; + constant length_b : integer := 512; + constant width_a : integer := 8; + constant width_b : integer := 32; + + constant parity_width_a : integer := 1; + constant parity_width_b : integer := 4; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + + function slv_to_two_D_parity_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_parity_array_type is + variable two_D_parity_array : two_D_parity_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_parity_array(i) := intermediate; + end loop; + return two_D_parity_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 10 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 7 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + DIPA_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIPA_ipd(i), DIPA(i), tipd_DIPA(i)); + end generate DIPA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 8 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 31 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + DIPB_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i)); + end generate DIPB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIPA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB12_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB13_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB14_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB15_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB16_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB17_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB18_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB19_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB20_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB21_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB22_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB23_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB24_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB25_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB26_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB27_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB28_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB29_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB30_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB31_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB13_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB14_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB15_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB16_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB17_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB18_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB19_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB20_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB21_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB22_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB23_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB24_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB25_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB26_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB27_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB28_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB29_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB30_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB31_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + variable DOA_GlitchData2 : VitalGlitchDataType; + variable DOA_GlitchData3 : VitalGlitchDataType; + variable DOA_GlitchData4 : VitalGlitchDataType; + variable DOA_GlitchData5 : VitalGlitchDataType; + variable DOA_GlitchData6 : VitalGlitchDataType; + variable DOA_GlitchData7 : VitalGlitchDataType; + variable DOPA_GlitchData0 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOB_GlitchData8 : VitalGlitchDataType; + variable DOB_GlitchData9 : VitalGlitchDataType; + variable DOB_GlitchData10 : VitalGlitchDataType; + variable DOB_GlitchData11 : VitalGlitchDataType; + variable DOB_GlitchData12 : VitalGlitchDataType; + variable DOB_GlitchData13 : VitalGlitchDataType; + variable DOB_GlitchData14 : VitalGlitchDataType; + variable DOB_GlitchData15 : VitalGlitchDataType; + variable DOB_GlitchData16 : VitalGlitchDataType; + variable DOB_GlitchData17 : VitalGlitchDataType; + variable DOB_GlitchData18 : VitalGlitchDataType; + variable DOB_GlitchData19 : VitalGlitchDataType; + variable DOB_GlitchData20 : VitalGlitchDataType; + variable DOB_GlitchData21 : VitalGlitchDataType; + variable DOB_GlitchData22 : VitalGlitchDataType; + variable DOB_GlitchData23 : VitalGlitchDataType; + variable DOB_GlitchData24 : VitalGlitchDataType; + variable DOB_GlitchData25 : VitalGlitchDataType; + variable DOB_GlitchData26 : VitalGlitchDataType; + variable DOB_GlitchData27 : VitalGlitchDataType; + variable DOB_GlitchData28 : VitalGlitchDataType; + variable DOB_GlitchData29 : VitalGlitchDataType; + variable DOB_GlitchData30 : VitalGlitchDataType; + variable DOB_GlitchData31 : VitalGlitchDataType; + variable DOPB_GlitchData0 : VitalGlitchDataType; + variable DOPB_GlitchData1 : VitalGlitchDataType; + variable DOPB_GlitchData2 : VitalGlitchDataType; + variable DOPB_GlitchData3 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) & + To_StdLogicVector(INITP_06) & + To_StdLogicVector(INITP_05) & + To_StdLogicVector(INITP_04) & + To_StdLogicVector(INITP_03) & + To_StdLogicVector(INITP_02) & + To_StdLogicVector(INITP_01) & + To_StdLogicVector(INITP_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOPA_OV_LSB : integer := 0; + variable DOPA_OV_MSB : integer := 0; + variable DOPB_OV_LSB : integer := 0; + variable DOPB_OV_MSB : integer := 3; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (8 downto 0) := "000000000"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (35 downto 0) := "000000000000000000000000000000000000"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (8 downto 0) := "000000000"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (35 downto 0) := "000000000000000000000000000000000000"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(7 downto 0) := INI_A(7 downto 0); + variable DOB_zd : std_logic_vector(31 downto 0) := INI_B(31 downto 0); + variable DOPA_zd : std_logic_vector(0 downto 0) := INI_A(8 downto 8); + variable DOPB_zd : std_logic_vector(3 downto 0) := INI_B(35 downto 32); + + variable ADDRA_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S9_S36", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 9) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(8 downto 0) := INI_A_UNBOUND(8 downto 0); + + for I in INI_A_UNBOUND'high downto 9 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 9 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S9_S36", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 9) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S9_S36", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 9) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 36) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(35 downto 0) := INI_B_UNBOUND(35 downto 0); + + for I in INI_B_UNBOUND'high downto 36 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 36 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S9_S36", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S9_S36", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 9) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(8 downto 0) := SRVA_A_UNBOUND(8 downto 0); + + for I in SRVA_A_UNBOUND'high downto 9 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 9 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S9_S36", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 9) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S9_S36", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 9) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 36) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(35 downto 0) := SRVA_B_UNBOUND(35 downto 0); + + for I in SRVA_B_UNBOUND'high downto 36 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 36 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S9_S36", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S9_S36", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 36, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(7 downto 0) := INI_A(7 downto 0); + DOB_zd(31 downto 0) := INI_B(31 downto 0); + DOPA_zd(0 downto 0) := INI_A(8 downto 8); + DOPB_zd(3 downto 0) := INI_B(35 downto 32); + DOA <= DOA_zd; + DOPA <= DOPA_zd; + DOB <= DOB_zd; + DOPB <= DOPB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S9_S36", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S9_S36", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA1_CLKA_posedge, + TimingData => Tmkr_DIA1_CLKA_posedge, + TestSignal => DIA_ipd(1), + TestSignalName => "DIA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(1), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(1), + HoldLow => thold_DIA_CLKA_posedge_posedge(1), + HoldHigh => thold_DIA_CLKA_negedge_posedge(1), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA2_CLKA_posedge, + TimingData => Tmkr_DIA2_CLKA_posedge, + TestSignal => DIA_ipd(2), + TestSignalName => "DIA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(2), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(2), + HoldLow => thold_DIA_CLKA_posedge_posedge(2), + HoldHigh => thold_DIA_CLKA_negedge_posedge(2), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA3_CLKA_posedge, + TimingData => Tmkr_DIA3_CLKA_posedge, + TestSignal => DIA_ipd(3), + TestSignalName => "DIA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(3), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(3), + HoldLow => thold_DIA_CLKA_posedge_posedge(3), + HoldHigh => thold_DIA_CLKA_negedge_posedge(3), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA4_CLKA_posedge, + TimingData => Tmkr_DIA4_CLKA_posedge, + TestSignal => DIA_ipd(4), + TestSignalName => "DIA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(4), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(4), + HoldLow => thold_DIA_CLKA_posedge_posedge(4), + HoldHigh => thold_DIA_CLKA_negedge_posedge(4), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA5_CLKA_posedge, + TimingData => Tmkr_DIA5_CLKA_posedge, + TestSignal => DIA_ipd(5), + TestSignalName => "DIA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(5), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(5), + HoldLow => thold_DIA_CLKA_posedge_posedge(5), + HoldHigh => thold_DIA_CLKA_negedge_posedge(5), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA6_CLKA_posedge, + TimingData => Tmkr_DIA6_CLKA_posedge, + TestSignal => DIA_ipd(6), + TestSignalName => "DIA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(6), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(6), + HoldLow => thold_DIA_CLKA_posedge_posedge(6), + HoldHigh => thold_DIA_CLKA_negedge_posedge(6), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB0_CLKB_posedge, + TimingData => Tmkr_DIPB0_CLKB_posedge, + TestSignal => DIPB_ipd(0), + TestSignalName => "DIPB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(0), + HoldLow => thold_DIPB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB1_CLKB_posedge, + TimingData => Tmkr_DIPB1_CLKB_posedge, + TestSignal => DIPB_ipd(1), + TestSignalName => "DIPB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(1), + HoldLow => thold_DIPB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIPB2_CLKB_posedge, + TimingData => Tmkr_DIPB2_CLKB_posedge, + TestSignal => DIPB_ipd(2), + TestSignalName => "DIPB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIPB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIPB_CLKB_negedge_posedge(2), + HoldLow => thold_DIPB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIPB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB7_CLKB_posedge, + TimingData => Tmkr_DIB7_CLKB_posedge, + TestSignal => DIB_ipd(7), + TestSignalName => "DIB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(7), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(7), + HoldLow => thold_DIB_CLKB_posedge_posedge(7), + HoldHigh => thold_DIB_CLKB_negedge_posedge(7), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB8_CLKB_posedge, + TimingData => Tmkr_DIB8_CLKB_posedge, + TestSignal => DIB_ipd(8), + TestSignalName => "DIB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(8), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(8), + HoldLow => thold_DIB_CLKB_posedge_posedge(8), + HoldHigh => thold_DIB_CLKB_negedge_posedge(8), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB9_CLKB_posedge, + TimingData => Tmkr_DIB9_CLKB_posedge, + TestSignal => DIB_ipd(9), + TestSignalName => "DIB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(9), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(9), + HoldLow => thold_DIB_CLKB_posedge_posedge(9), + HoldHigh => thold_DIB_CLKB_negedge_posedge(9), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB10_CLKB_posedge, + TimingData => Tmkr_DIB10_CLKB_posedge, + TestSignal => DIB_ipd(10), + TestSignalName => "DIB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(10), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(10), + HoldLow => thold_DIB_CLKB_posedge_posedge(10), + HoldHigh => thold_DIB_CLKB_negedge_posedge(10), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB11_CLKB_posedge, + TimingData => Tmkr_DIB11_CLKB_posedge, + TestSignal => DIB_ipd(11), + TestSignalName => "DIB(11)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(11), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(11), + HoldLow => thold_DIB_CLKB_posedge_posedge(11), + HoldHigh => thold_DIB_CLKB_negedge_posedge(11), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB12_CLKB_posedge, + TimingData => Tmkr_DIB12_CLKB_posedge, + TestSignal => DIB_ipd(12), + TestSignalName => "DIB(12)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(12), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(12), + HoldLow => thold_DIB_CLKB_posedge_posedge(12), + HoldHigh => thold_DIB_CLKB_negedge_posedge(12), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB13_CLKB_posedge, + TimingData => Tmkr_DIB13_CLKB_posedge, + TestSignal => DIB_ipd(13), + TestSignalName => "DIB(13)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(13), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(13), + HoldLow => thold_DIB_CLKB_posedge_posedge(13), + HoldHigh => thold_DIB_CLKB_negedge_posedge(13), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB14_CLKB_posedge, + TimingData => Tmkr_DIB14_CLKB_posedge, + TestSignal => DIB_ipd(14), + TestSignalName => "DIB(14)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(14), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(14), + HoldLow => thold_DIB_CLKB_posedge_posedge(14), + HoldHigh => thold_DIB_CLKB_negedge_posedge(14), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB15_CLKB_posedge, + TimingData => Tmkr_DIB15_CLKB_posedge, + TestSignal => DIB_ipd(15), + TestSignalName => "DIB(15)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(15), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(15), + HoldLow => thold_DIB_CLKB_posedge_posedge(15), + HoldHigh => thold_DIB_CLKB_negedge_posedge(15), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB16_CLKB_posedge, + TimingData => Tmkr_DIB16_CLKB_posedge, + TestSignal => DIB_ipd(16), + TestSignalName => "DIB(16)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(16), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(16), + HoldLow => thold_DIB_CLKB_posedge_posedge(16), + HoldHigh => thold_DIB_CLKB_negedge_posedge(16), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB17_CLKB_posedge, + TimingData => Tmkr_DIB17_CLKB_posedge, + TestSignal => DIB_ipd(17), + TestSignalName => "DIB(17)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(17), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(17), + HoldLow => thold_DIB_CLKB_posedge_posedge(17), + HoldHigh => thold_DIB_CLKB_negedge_posedge(17), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB18_CLKB_posedge, + TimingData => Tmkr_DIB18_CLKB_posedge, + TestSignal => DIB_ipd(18), + TestSignalName => "DIB(18)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(18), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(18), + HoldLow => thold_DIB_CLKB_posedge_posedge(18), + HoldHigh => thold_DIB_CLKB_negedge_posedge(18), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB19_CLKB_posedge, + TimingData => Tmkr_DIB19_CLKB_posedge, + TestSignal => DIB_ipd(19), + TestSignalName => "DIB(19)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(19), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(19), + HoldLow => thold_DIB_CLKB_posedge_posedge(19), + HoldHigh => thold_DIB_CLKB_negedge_posedge(19), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB20_CLKB_posedge, + TimingData => Tmkr_DIB20_CLKB_posedge, + TestSignal => DIB_ipd(20), + TestSignalName => "DIB(20)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(20), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(20), + HoldLow => thold_DIB_CLKB_posedge_posedge(20), + HoldHigh => thold_DIB_CLKB_negedge_posedge(20), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB21_CLKB_posedge, + TimingData => Tmkr_DIB21_CLKB_posedge, + TestSignal => DIB_ipd(21), + TestSignalName => "DIB(21)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(21), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(21), + HoldLow => thold_DIB_CLKB_posedge_posedge(21), + HoldHigh => thold_DIB_CLKB_negedge_posedge(21), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB22_CLKB_posedge, + TimingData => Tmkr_DIB22_CLKB_posedge, + TestSignal => DIB_ipd(22), + TestSignalName => "DIB(22)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(22), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(22), + HoldLow => thold_DIB_CLKB_posedge_posedge(22), + HoldHigh => thold_DIB_CLKB_negedge_posedge(22), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB23_CLKB_posedge, + TimingData => Tmkr_DIB23_CLKB_posedge, + TestSignal => DIB_ipd(23), + TestSignalName => "DIB(23)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(23), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(23), + HoldLow => thold_DIB_CLKB_posedge_posedge(23), + HoldHigh => thold_DIB_CLKB_negedge_posedge(23), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB24_CLKB_posedge, + TimingData => Tmkr_DIB24_CLKB_posedge, + TestSignal => DIB_ipd(24), + TestSignalName => "DIB(24)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(24), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(24), + HoldLow => thold_DIB_CLKB_posedge_posedge(24), + HoldHigh => thold_DIB_CLKB_negedge_posedge(24), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB25_CLKB_posedge, + TimingData => Tmkr_DIB25_CLKB_posedge, + TestSignal => DIB_ipd(25), + TestSignalName => "DIB(25)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(25), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(25), + HoldLow => thold_DIB_CLKB_posedge_posedge(25), + HoldHigh => thold_DIB_CLKB_negedge_posedge(25), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB26_CLKB_posedge, + TimingData => Tmkr_DIB26_CLKB_posedge, + TestSignal => DIB_ipd(26), + TestSignalName => "DIB(26)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(26), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(26), + HoldLow => thold_DIB_CLKB_posedge_posedge(26), + HoldHigh => thold_DIB_CLKB_negedge_posedge(26), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB27_CLKB_posedge, + TimingData => Tmkr_DIB27_CLKB_posedge, + TestSignal => DIB_ipd(27), + TestSignalName => "DIB(27)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(27), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(27), + HoldLow => thold_DIB_CLKB_posedge_posedge(27), + HoldHigh => thold_DIB_CLKB_negedge_posedge(27), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB28_CLKB_posedge, + TimingData => Tmkr_DIB28_CLKB_posedge, + TestSignal => DIB_ipd(28), + TestSignalName => "DIB(28)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(28), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(28), + HoldLow => thold_DIB_CLKB_posedge_posedge(28), + HoldHigh => thold_DIB_CLKB_negedge_posedge(28), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB29_CLKB_posedge, + TimingData => Tmkr_DIB29_CLKB_posedge, + TestSignal => DIB_ipd(29), + TestSignalName => "DIB(29)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(29), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(29), + HoldLow => thold_DIB_CLKB_posedge_posedge(29), + HoldHigh => thold_DIB_CLKB_negedge_posedge(29), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB30_CLKB_posedge, + TimingData => Tmkr_DIB30_CLKB_posedge, + TestSignal => DIB_ipd(30), + TestSignalName => "DIB(30)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(30), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(30), + HoldLow => thold_DIB_CLKB_posedge_posedge(30), + HoldHigh => thold_DIB_CLKB_negedge_posedge(30), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S9_S36", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_DIA2_CLKA_posedge or + Tviol_DIA3_CLKA_posedge or + Tviol_DIA4_CLKA_posedge or + Tviol_DIA5_CLKA_posedge or + Tviol_DIA6_CLKA_posedge or + Tviol_DIA7_CLKA_posedge or + Tviol_DIPA0_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIB8_CLKB_posedge or + Tviol_DIB9_CLKB_posedge or + Tviol_DIB10_CLKB_posedge or + Tviol_DIB11_CLKB_posedge or + Tviol_DIB12_CLKB_posedge or + Tviol_DIB13_CLKB_posedge or + Tviol_DIB14_CLKB_posedge or + Tviol_DIB15_CLKB_posedge or + Tviol_DIB16_CLKB_posedge or + Tviol_DIB17_CLKB_posedge or + Tviol_DIB18_CLKB_posedge or + Tviol_DIB19_CLKB_posedge or + Tviol_DIB20_CLKB_posedge or + Tviol_DIB21_CLKB_posedge or + Tviol_DIB22_CLKB_posedge or + Tviol_DIB23_CLKB_posedge or + Tviol_DIB24_CLKB_posedge or + Tviol_DIB25_CLKB_posedge or + Tviol_DIB26_CLKB_posedge or + Tviol_DIB27_CLKB_posedge or + Tviol_DIB28_CLKB_posedge or + Tviol_DIB29_CLKB_posedge or + Tviol_DIB30_CLKB_posedge or + Tviol_DIB31_CLKB_posedge or + Tviol_DIPB0_CLKB_posedge or + Tviol_DIPB1_CLKB_posedge or + Tviol_DIPB2_CLKB_posedge or + Tviol_DIPB3_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + addr_overlap (address_a, address_b, parity_width_a, parity_width_b, has_overlap_p, olpp_lsb, olpp_msb, dopa_ov_lsb, dopa_ov_msb, dopb_ov_lsb, dopb_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S36", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + DOPA_zd := DIPA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S9_S36", + InstanceName => ramb16_s9_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S9_S36", + InstanceName => ramb16_s9_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S9_S36", + InstanceName => ramb16_s9_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S9_S36", + InstanceName => ramb16_s9_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S9_S36", + InstanceName => ramb16_s9_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S9_S36", + InstanceName => ramb16_s9_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S9_S36", + InstanceName => ramb16_s9_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(7 downto 0); + DOPA_zd := SRVA_A(8 downto 8); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + DOPB_zd := DIPB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S9_S36", + InstanceName => ramb16_s9_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S9_S36", + InstanceName => ramb16_s9_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S9_S36", + InstanceName => ramb16_s9_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S9_S36", + InstanceName => ramb16_s9_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S9_S36", + InstanceName => ramb16_s9_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S9_S36", + InstanceName => ramb16_s9_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S9_S36", + InstanceName => ramb16_s9_s36'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(31 downto 0); + DOPB_zd := SRVA_B(35 downto 32); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + DOA_zd(1) := ViolationA xor DOA_zd(1); + DOA_zd(2) := ViolationA xor DOA_zd(2); + DOA_zd(3) := ViolationA xor DOA_zd(3); + DOA_zd(4) := ViolationA xor DOA_zd(4); + DOA_zd(5) := ViolationA xor DOA_zd(5); + DOA_zd(6) := ViolationA xor DOA_zd(6); + DOA_zd(7) := ViolationA xor DOA_zd(7); + DOPA_zd(0) := ViolationA xor DOPA_zd(0); + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOB_zd(8) := ViolationB xor DOB_zd(8); + DOB_zd(9) := ViolationB xor DOB_zd(9); + DOB_zd(10) := ViolationB xor DOB_zd(10); + DOB_zd(11) := ViolationB xor DOB_zd(11); + DOB_zd(12) := ViolationB xor DOB_zd(12); + DOB_zd(13) := ViolationB xor DOB_zd(13); + DOB_zd(14) := ViolationB xor DOB_zd(14); + DOB_zd(15) := ViolationB xor DOB_zd(15); + DOB_zd(16) := ViolationB xor DOB_zd(16); + DOB_zd(17) := ViolationB xor DOB_zd(17); + DOB_zd(18) := ViolationB xor DOB_zd(18); + DOB_zd(19) := ViolationB xor DOB_zd(19); + DOB_zd(20) := ViolationB xor DOB_zd(20); + DOB_zd(21) := ViolationB xor DOB_zd(21); + DOB_zd(22) := ViolationB xor DOB_zd(22); + DOB_zd(23) := ViolationB xor DOB_zd(23); + DOB_zd(24) := ViolationB xor DOB_zd(24); + DOB_zd(25) := ViolationB xor DOB_zd(25); + DOB_zd(26) := ViolationB xor DOB_zd(26); + DOB_zd(27) := ViolationB xor DOB_zd(27); + DOB_zd(28) := ViolationB xor DOB_zd(28); + DOB_zd(29) := ViolationB xor DOB_zd(29); + DOB_zd(30) := ViolationB xor DOB_zd(30); + DOB_zd(31) := ViolationB xor DOB_zd(31); + DOPB_zd(0) := ViolationB xor DOPB_zd(0); + DOPB_zd(1) := ViolationB xor DOPB_zd(1); + DOPB_zd(2) := ViolationB xor DOPB_zd(2); + DOPB_zd(3) := ViolationB xor DOPB_zd(3); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(2), + GlitchData => DOA_GlitchData2, + OutSignalName => "DOA(2)", + OutTemp => DOA_zd(2), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(3), + GlitchData => DOA_GlitchData3, + OutSignalName => "DOA(3)", + OutTemp => DOA_zd(3), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(4), + GlitchData => DOA_GlitchData4, + OutSignalName => "DOA(4)", + OutTemp => DOA_zd(4), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(5), + GlitchData => DOA_GlitchData5, + OutSignalName => "DOA(5)", + OutTemp => DOA_zd(5), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(6), + GlitchData => DOA_GlitchData6, + OutSignalName => "DOA(6)", + OutTemp => DOA_zd(6), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(7), + GlitchData => DOA_GlitchData7, + OutSignalName => "DOA(7)", + OutTemp => DOA_zd(7), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPA(0), + GlitchData => DOPA_GlitchData0, + OutSignalName => "DOPA(0)", + OutTemp => DOPA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(8), + GlitchData => DOB_GlitchData8, + OutSignalName => "DOB(8)", + OutTemp => DOB_zd(8), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(9), + GlitchData => DOB_GlitchData9, + OutSignalName => "DOB(9)", + OutTemp => DOB_zd(9), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(10), + GlitchData => DOB_GlitchData10, + OutSignalName => "DOB(10)", + OutTemp => DOB_zd(10), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(11), + GlitchData => DOB_GlitchData11, + OutSignalName => "DOB(11)", + OutTemp => DOB_zd(11), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(12), + GlitchData => DOB_GlitchData12, + OutSignalName => "DOB(12)", + OutTemp => DOB_zd(12), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(13), + GlitchData => DOB_GlitchData13, + OutSignalName => "DOB(13)", + OutTemp => DOB_zd(13), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(14), + GlitchData => DOB_GlitchData14, + OutSignalName => "DOB(14)", + OutTemp => DOB_zd(14), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(15), + GlitchData => DOB_GlitchData15, + OutSignalName => "DOB(15)", + OutTemp => DOB_zd(15), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(16), + GlitchData => DOB_GlitchData16, + OutSignalName => "DOB(16)", + OutTemp => DOB_zd(16), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(16), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(17), + GlitchData => DOB_GlitchData17, + OutSignalName => "DOB(17)", + OutTemp => DOB_zd(17), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(17), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(18), + GlitchData => DOB_GlitchData18, + OutSignalName => "DOB(18)", + OutTemp => DOB_zd(18), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(18), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(19), + GlitchData => DOB_GlitchData19, + OutSignalName => "DOB(19)", + OutTemp => DOB_zd(19), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(19), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(20), + GlitchData => DOB_GlitchData20, + OutSignalName => "DOB(20)", + OutTemp => DOB_zd(20), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(20), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(21), + GlitchData => DOB_GlitchData21, + OutSignalName => "DOB(21)", + OutTemp => DOB_zd(21), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(21), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(22), + GlitchData => DOB_GlitchData22, + OutSignalName => "DOB(22)", + OutTemp => DOB_zd(22), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(22), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(23), + GlitchData => DOB_GlitchData23, + OutSignalName => "DOB(23)", + OutTemp => DOB_zd(23), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(23), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(24), + GlitchData => DOB_GlitchData24, + OutSignalName => "DOB(24)", + OutTemp => DOB_zd(24), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(24), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(25), + GlitchData => DOB_GlitchData25, + OutSignalName => "DOB(25)", + OutTemp => DOB_zd(25), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(25), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(26), + GlitchData => DOB_GlitchData26, + OutSignalName => "DOB(26)", + OutTemp => DOB_zd(26), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(26), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(27), + GlitchData => DOB_GlitchData27, + OutSignalName => "DOB(27)", + OutTemp => DOB_zd(27), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(27), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(28), + GlitchData => DOB_GlitchData28, + OutSignalName => "DOB(28)", + OutTemp => DOB_zd(28), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(28), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(29), + GlitchData => DOB_GlitchData29, + OutSignalName => "DOB(29)", + OutTemp => DOB_zd(29), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(29), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(30), + GlitchData => DOB_GlitchData30, + OutSignalName => "DOB(30)", + OutTemp => DOB_zd(30), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(30), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(31), + GlitchData => DOB_GlitchData31, + OutSignalName => "DOB(31)", + OutTemp => DOB_zd(31), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(31), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(0), + GlitchData => DOPB_GlitchData0, + OutSignalName => "DOPB(0)", + OutTemp => DOPB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(1), + GlitchData => DOPB_GlitchData1, + OutSignalName => "DOPB(1)", + OutTemp => DOPB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(2), + GlitchData => DOPB_GlitchData2, + OutSignalName => "DOPB(2)", + OutTemp => DOPB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(3), + GlitchData => DOPB_GlitchData3, + OutSignalName => "DOPB(3)", + OutTemp => DOPB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPA_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S9_S36_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16_S9_S9.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/07 - Fixed invalid address of port B. (CR 430253). +-- End Revision + +----- CELL ramb16_s9_s9 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library STD; +use STD.TEXTIO.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB16_S9_S9 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(10 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRA : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := (0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(10 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := (0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps)); + tipd_DIPB : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := (0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := (0 ps, 0 ps); + tipd_SSRB : VitalDelayType01 := (0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKA_DOPA : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOPB : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIPA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIPA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIPA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIPA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIPB_CLKB_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_SSRB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"000"; + INIT_B : bit_vector := X"000"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"000"; + SRVAL_B : bit_vector := X"000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector(7 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPA : out std_logic_vector(0 downto 0); + DOPB : out std_logic_vector(0 downto 0); + + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(7 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPA : in std_logic_vector(0 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB16_S9_S9 : entity is true; +end ramb16_s9_s9; + +architecture RAMB16_S9_S9_V of RAMB16_S9_S9 is + attribute VITAL_LEVEL0 of + RAMB16_S9_S9_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(10 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(7 downto 0) := (others => 'X'); + signal DIPA_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(10 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(7 downto 0) := (others => 'X'); + signal DIPB_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant SETUP_READ_FIRST : VitalDelayType := 1000 ps; + constant length_a : integer := 2048; + constant length_b : integer := 2048; + constant width_a : integer := 8; + constant width_b : integer := 8; + + constant parity_width_a : integer := 1; + constant parity_width_b : integer := 1; + + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + type Two_D_parity_array_type is array ((length_b - 1) downto 0) of std_logic_vector((parity_width_b -1) downto 0); + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + + function slv_to_two_D_parity_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_parity_array_type is + variable two_D_parity_array : two_D_parity_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_parity_array(i) := intermediate; + end loop; + return two_D_parity_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 10 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 7 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + DIPA_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIPA_ipd(i), DIPA(i), tipd_DIPA(i)); + end generate DIPA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (SSRA_ipd, SSRA, tipd_SSRA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 10 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 7 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + DIPB_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIPB_ipd(i), DIPB(i), tipd_DIPB(i)); + end generate DIPB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (SSRB_ipd, SSRB, tipd_SSRB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIPA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_SSRA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIPB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_SSRB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_all : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_read_first : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_all : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_read_first : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIPB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_SSRB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + variable Tmkr_CLKA_CLKB_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_read_first : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_all : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_read_first : VitalTimingDataType := VitalTimingDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + variable DOA_GlitchData2 : VitalGlitchDataType; + variable DOA_GlitchData3 : VitalGlitchDataType; + variable DOA_GlitchData4 : VitalGlitchDataType; + variable DOA_GlitchData5 : VitalGlitchDataType; + variable DOA_GlitchData6 : VitalGlitchDataType; + variable DOA_GlitchData7 : VitalGlitchDataType; + variable DOPA_GlitchData0 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOPB_GlitchData0 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(16383 downto 0) := To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable memp_slv : std_logic_vector(2047 downto 0) := To_StdLogicVector(INITP_07) & + To_StdLogicVector(INITP_06) & + To_StdLogicVector(INITP_05) & + To_StdLogicVector(INITP_04) & + To_StdLogicVector(INITP_03) & + To_StdLogicVector(INITP_02) & + To_StdLogicVector(INITP_01) & + To_StdLogicVector(INITP_00); + + variable mem : Two_D_array_type := slv_to_two_D_array(length_b, width_b, mem_slv); + variable memp : Two_D_parity_array_type := slv_to_two_D_parity_array(length_b, parity_width_b, memp_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOPA_OV_LSB : integer := 0; + variable DOPA_OV_MSB : integer := 0; + variable DOPB_OV_LSB : integer := 0; + variable DOPB_OV_MSB : integer := 0; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable INIT_A_val : std_logic_vector(INIT_A'length-1 downto 0) := (others => 'X'); + variable INIT_B_val : std_logic_vector(INIT_B'length-1 downto 0) := (others => 'X'); + variable INI_A : std_logic_vector (8 downto 0) := "000000000"; + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (8 downto 0) := "000000000"; + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + variable IS_VALID : boolean := true; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVAL_A_val : std_logic_vector(SRVAL_A'length-1 downto 0) := (others => 'X'); + variable SRVAL_B_val : std_logic_vector(SRVAL_B'length-1 downto 0) := (others => 'X'); + variable SRVA_A : std_logic_vector (8 downto 0) := "000000000"; + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (8 downto 0) := "000000000"; + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable TEMPLINE : line; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable WR_A_LATER : boolean := false; + variable WR_B_LATER : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable wr_mode_a : integer := 0; + variable wr_mode_b : integer := 0; + + variable DOA_zd : std_logic_vector(7 downto 0) := INI_A(7 downto 0); + variable DOB_zd : std_logic_vector(7 downto 0) := INI_B(7 downto 0); + variable DOPA_zd : std_logic_vector(0 downto 0) := INI_A(8 downto 8); + variable DOPB_zd : std_logic_vector(0 downto 0) := INI_B(8 downto 8); + + variable ADDRA_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X'); + variable ADDRB_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable SSRA_ipd_sampled : std_ulogic := 'X'; + variable SSRB_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + variable full_4bit_words : integer := 0; + variable needed_bits : integer := 0; + variable collision_type : integer := 3; + + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB16_S9_S9", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if (INIT_A'length > 9) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + INI_A(8 downto 0) := INI_A_UNBOUND(8 downto 0); + + for I in INI_A_UNBOUND'high downto 9 loop + if (INI_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 9 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S9_S9", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_A'length < 9) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_A ", + EntityName => "/RAMB16_S9_S9", + GenericValue => INIT_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => " Remaining MSB's of INIT_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_A'length = 9) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + end if; + + if (INIT_B'length > 9) then + IS_VALID := true; + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + INI_B(8 downto 0) := INI_B_UNBOUND(8 downto 0); + + for I in INI_B_UNBOUND'high downto 9 loop + if (INI_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 9 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(INIT_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of INIT_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S9_S9", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (INIT_B'length < 9) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " INIT_B ", + EntityName => "/RAMB16_S9_S9", + GenericValue => INIT_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => " Remaining MSB's of INIT_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (INIT_B'length = 9) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + end if; + + if (SRVAL_A'length > 9) then + IS_VALID := true; + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + SRVA_A(8 downto 0) := SRVA_A_UNBOUND(8 downto 0); + + for I in SRVA_A_UNBOUND'high downto 9 loop + if (SRVA_A_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 9 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_A'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_A passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S9_S9", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_A'length < 9) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_A ", + EntityName => "/RAMB16_S9_S9", + GenericValue => SRVAL_A'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => " Remaining MSB's of SRVAL_A are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_A'length = 9) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + end if; + + if (SRVAL_B'length > 9) then + IS_VALID := true; + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + SRVA_B(8 downto 0) := SRVA_B_UNBOUND(8 downto 0); + + for I in SRVA_B_UNBOUND'high downto 9 loop + if (SRVA_B_UNBOUND(I) /= '0') then + IS_VALID := false; + end if; + end loop; + + if (IS_VALID = true) then + full_4bit_words := 9 / 4; + needed_bits := (full_4bit_words +1) * 4; + if(SRVAL_B'length /= needed_bits) then + write(TEMPLINE, string'("Length of SRVAL_B passed is greater than expected one.")); + write(TEMPLINE, LF); + write(TEMPLINE, string'("Ignoring the extra leading bits as those bits are all zeros.")); + write(TEMPLINE, LF); + assert false report + TEMPLINE.all + severity warning; + write(TEMPLINE, LF); + DEALLOCATE (TEMPLINE); + end if; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S9_S9", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => "", + MsgSeverity => warning + ); + end if; + + elsif (SRVAL_B'length < 9) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRVAL_B ", + EntityName => "/RAMB16_S9_S9", + GenericValue => SRVAL_B'length, + Unit => " bit value ", + ExpectedValueMsg => " The expected length for this attribute is ", + ExpectedGenericValue => 9, + TailMsg => " Remaining MSB's of SRVAL_B are padded with 0's ", + MsgSeverity => warning + ); + + elsif (SRVAL_B'length = 9) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + end if; + + DOA_zd(7 downto 0) := INI_A(7 downto 0); + DOB_zd(7 downto 0) := INI_B(7 downto 0); + DOPA_zd(0 downto 0) := INI_A(8 downto 8); + DOPB_zd(0 downto 0) := INI_B(8 downto 8); + DOA <= DOA_zd; + DOPA <= DOPA_zd; + DOB <= DOB_zd; + DOPB <= DOPB_zd; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := 0; + + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := 1; + + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16_S9_S9", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := 0; + + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := 1; + + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := 2; + + else + GenericValueCheckMessage + (HeaderMsg => " Attribute Syntax Warning ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16_S9_S9", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + SSRA_ipd_sampled := SSRA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + SSRB_ipd_sampled := SSRB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRA_CLKA_posedge, + TimingData => Tmkr_SSRA_CLKA_posedge, + TestSignal => SSRA_ipd, + TestSignalName => "SSRA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRA_CLKA_posedge_posedge, + SetupLow => tsetup_SSRA_CLKA_negedge_posedge, + HoldLow => thold_SSRA_CLKA_posedge_posedge, + HoldHigh => thold_SSRA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA1_CLKA_posedge, + TimingData => Tmkr_DIA1_CLKA_posedge, + TestSignal => DIA_ipd(1), + TestSignalName => "DIA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(1), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(1), + HoldLow => thold_DIA_CLKA_posedge_posedge(1), + HoldHigh => thold_DIA_CLKA_negedge_posedge(1), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA2_CLKA_posedge, + TimingData => Tmkr_DIA2_CLKA_posedge, + TestSignal => DIA_ipd(2), + TestSignalName => "DIA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(2), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(2), + HoldLow => thold_DIA_CLKA_posedge_posedge(2), + HoldHigh => thold_DIA_CLKA_negedge_posedge(2), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA3_CLKA_posedge, + TimingData => Tmkr_DIA3_CLKA_posedge, + TestSignal => DIA_ipd(3), + TestSignalName => "DIA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(3), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(3), + HoldLow => thold_DIA_CLKA_posedge_posedge(3), + HoldHigh => thold_DIA_CLKA_negedge_posedge(3), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA4_CLKA_posedge, + TimingData => Tmkr_DIA4_CLKA_posedge, + TestSignal => DIA_ipd(4), + TestSignalName => "DIA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(4), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(4), + HoldLow => thold_DIA_CLKA_posedge_posedge(4), + HoldHigh => thold_DIA_CLKA_negedge_posedge(4), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA5_CLKA_posedge, + TimingData => Tmkr_DIA5_CLKA_posedge, + TestSignal => DIA_ipd(5), + TestSignalName => "DIA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(5), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(5), + HoldLow => thold_DIA_CLKA_posedge_posedge(5), + HoldHigh => thold_DIA_CLKA_negedge_posedge(5), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA6_CLKA_posedge, + TimingData => Tmkr_DIA6_CLKA_posedge, + TestSignal => DIA_ipd(6), + TestSignalName => "DIA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(6), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(6), + HoldLow => thold_DIA_CLKA_posedge_posedge(6), + HoldHigh => thold_DIA_CLKA_negedge_posedge(6), + CheckEnabled => (TO_X01(ena_ipd_sampled) = '1' and TO_X01(wea_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_SSRB_CLKB_posedge, + TimingData => Tmkr_SSRB_CLKB_posedge, + TestSignal => SSRB_ipd, + TestSignalName => "SSRB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_SSRB_CLKB_posedge_posedge, + SetupLow => tsetup_SSRB_CLKB_negedge_posedge, + HoldLow => thold_SSRB_CLKB_posedge_posedge, + HoldHigh => thold_SSRB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB9_CLKB_posedge, + TimingData => Tmkr_ADDRB9_CLKB_posedge, + TestSignal => ADDRB_ipd(9), + TestSignalName => "ADDRB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(9), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(9), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(9), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(9), + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(enb_ipd_sampled) = '1' and TO_X01(web_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ena_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(enb_ipd_sampled) = '1', + HeaderMsg => "/RAMB16_S9_S9", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_DIA2_CLKA_posedge or + Tviol_DIA3_CLKA_posedge or + Tviol_DIA4_CLKA_posedge or + Tviol_DIA5_CLKA_posedge or + Tviol_DIA6_CLKA_posedge or + Tviol_DIA7_CLKA_posedge or + Tviol_DIPA0_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_SSRA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_ADDRB10_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIPB0_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_SSRB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(addra_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(addrb_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(addra_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(addrb_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + addr_overlap (address_a, address_b, parity_width_a, parity_width_b, has_overlap_p, olpp_lsb, olpp_msb, dopa_ov_lsb, dopa_ov_msb, dopb_ov_lsb, dopb_ov_msb); + end if; + + ViolationCLKAB := '0'; + ViolationCLKAB_S0 := false; + Violation_S1 := false; + Violation_S3 := false; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_all, + TimingData => Tmkr_CLKB_CLKA_all, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((web_ipd_sampled = '1' and wr_mode_b /= 1) or (wea_ipd_sampled = '1' and wr_mode_a /= 1 and web_ipd_sampled = '0'))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_all, + TimingData => Tmkr_CLKA_CLKB_all, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_ALL, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and ((wea_ipd_sampled = '1' and wr_mode_a /= 1) or (web_ipd_sampled = '1' and wea_ipd_sampled = '0' and wr_mode_b /= 1))), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKB_CLKA_read_first, + TimingData => Tmkr_CLKB_CLKA_read_first, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and web_ipd_sampled = '1' and wr_mode_b = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLKA_CLKB_read_first, + TimingData => Tmkr_CLKA_CLKB_read_first, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + Recovery => SETUP_READ_FIRST, + Removal => 1 ps, + ActiveLow => true, + CheckEnabled => (HAS_OVERLAP = true and ena_ipd_sampled = '1' and enb_ipd_sampled = '1' and wea_ipd_sampled = '1' and wr_mode_a = 1 and (CLKA_ipd'last_event /= CLKB_ipd'last_event)), + RefTransition => 'R', + HeaderMsg => "/RAMB16_S9_S9", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + ViolationCLKAB := Tviol_CLKB_CLKA_all or Tviol_CLKA_CLKB_all or Tviol_CLKB_CLKA_read_first or Tviol_CLKA_CLKB_read_first; + + + WR_A_LATER := false; + WR_B_LATER := false; + + if (ena_ipd_sampled = '1')then + if (rising_edge(CLKA_ipd)) then + + if (wea_ipd_sampled = '1') then + case wr_mode_a is + when 0 => + DOA_zd := DIA_ipd; + DOPA_zd := DIPA_ipd; + + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S9_S9", + InstanceName => ramb16_s9_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + + end if; + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S9_S9", + InstanceName => ramb16_s9_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (VALID_ADDRA ) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + end if; + + when 1 => + if (VALID_ADDRA ) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))); + WR_A_LATER := true; + end if; + + if (ViolationCLKAB = 'X') then + + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S9_S9", + InstanceName => ramb16_s9_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S9_S9", + InstanceName => ramb16_s9_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + end if; + + when 2 => + if (ViolationCLKAB = 'X') then + if (web_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S9_S9", + InstanceName => ramb16_s9_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_A/(length_a/length_b))(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_b /= 2 ) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S9_S9", + InstanceName => ramb16_s9_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + + else + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + end if; + + when others => null; + end case; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + DOPA_zd := MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S9_S9", + InstanceName => ramb16_s9_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + + if (ssra_ipd_sampled = '1') then + DOA_zd := SRVA_A(7 downto 0); + DOPA_zd := SRVA_A(8 downto 8); + end if; + end if; + end if; + + if (enb_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (web_ipd_sampled = '1') then + case wr_mode_b is + when 0 => + DOB_zd := DIB_ipd; + DOPB_zd := DIPB_ipd; + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S9_S9", + InstanceName => ramb16_s9_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S9_S9", + InstanceName => ramb16_s9_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + + when 1 => + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + WR_B_LATER := true; + MEM(ADDRESS_B) := DIB_ipd ; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S9_S9", + InstanceName => ramb16_s9_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S9_S9", + InstanceName => ramb16_s9_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + + when 2 => + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + if (ViolationCLKAB = 'X') then + + if (wea_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB16_S9_S9", + InstanceName => ramb16_s9_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + MEMP(ADDRESS_B)(DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + + if (wr_mode_a /= 2 ) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + + else + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB16_S9_S9", + InstanceName => ramb16_s9_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + DOPA_zd := (others => 'X'); + end if; + end if; + end if; + when others => null; + end case; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + DOPB_zd := MEMP(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB16_S9_S9", + InstanceName => ramb16_s9_s9'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd (DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOPB_zd (DOPB_OV_MSB downto DOPB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (ssrb_ipd_sampled = '1') then + DOB_zd := SRVA_B(7 downto 0); + DOPB_zd := SRVA_B(8 downto 8); + end if; + end if; + end if; + + if ((WR_A_LATER = true) and (VALID_ADDRA)) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + MEMP(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(parity_width_a)) + (parity_width_a - 1)) downto (((address_a)rem(length_a/length_b))*(parity_width_a))):= DIPA_ipd; + end if; + + if ((WR_B_LATER = true ) and (VALID_ADDRB))then + MEM(ADDRESS_B) := DIB_ipd; + MEMP(ADDRESS_B) := DIPB_ipd; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + DOA_zd(1) := ViolationA xor DOA_zd(1); + DOA_zd(2) := ViolationA xor DOA_zd(2); + DOA_zd(3) := ViolationA xor DOA_zd(3); + DOA_zd(4) := ViolationA xor DOA_zd(4); + DOA_zd(5) := ViolationA xor DOA_zd(5); + DOA_zd(6) := ViolationA xor DOA_zd(6); + DOA_zd(7) := ViolationA xor DOA_zd(7); + DOPA_zd(0) := ViolationA xor DOPA_zd(0); + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOPB_zd(0) := ViolationB xor DOPB_zd(0); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(2), + GlitchData => DOA_GlitchData2, + OutSignalName => "DOA(2)", + OutTemp => DOA_zd(2), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(3), + GlitchData => DOA_GlitchData3, + OutSignalName => "DOA(3)", + OutTemp => DOA_zd(3), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(4), + GlitchData => DOA_GlitchData4, + OutSignalName => "DOA(4)", + OutTemp => DOA_zd(4), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(5), + GlitchData => DOA_GlitchData5, + OutSignalName => "DOA(5)", + OutTemp => DOA_zd(5), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(6), + GlitchData => DOA_GlitchData6, + OutSignalName => "DOA(6)", + OutTemp => DOA_zd(6), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(7), + GlitchData => DOA_GlitchData7, + OutSignalName => "DOA(7)", + OutTemp => DOA_zd(7), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPA(0), + GlitchData => DOPA_GlitchData0, + OutSignalName => "DOPA(0)", + OutTemp => DOPA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOPA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOPB(0), + GlitchData => DOPB_GlitchData0, + OutSignalName => "DOPB(0)", + OutTemp => DOPB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOPB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, DIPA_ipd, DIPB_ipd, ENA_ipd, ENB_ipd, SSRA_ipd, SSRB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB16_S9_S9_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb4_s1.vhd,v 1.5 2004/08/31 13:40:21 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Single Port Block RAM +-- /___/ /\ Filename : RAMB4_S1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:53 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAMB4_S1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S1 is + + generic ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + + port ( + DO : out STD_LOGIC_VECTOR (0 downto 0); + + ADDR : in STD_LOGIC_VECTOR (11 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (0 downto 0); + EN : in STD_ULOGIC; + RST : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end RAMB4_S1; + +architecture RAMB4_S1_V of RAMB4_S1 is + constant length : integer := 4096; + constant width : integer := 1; + type Two_D_array_type is array ((length - 1) downto 0) of std_logic_vector((width - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width) + (width - 1)) downto (i* width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + +begin + + VITALBehavior : process + + variable address : integer; + variable valid_addr : boolean := FALSE; + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + begin + valid_addr := addr_is_valid(addr); + + if (valid_addr) then + address := slv_to_int(addr); + end if; + + if (rising_edge(CLK)) then + if (EN = '1') then + if (RST = '1') then + DO <= (others => '0') after 100 ps; + else + if (WE = '1') then + DO <= DI after 100 ps; + else + if (valid_addr) then + DO <= mem(address) after 100 ps; + end if; + end if; + end if; + if (WE = '1') then + if (valid_addr) then + mem(address) := DI; + end if; + end if; + end if; + end if; + wait on CLK; + + end process VITALBehavior; +end RAMB4_S1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb4_s16.vhd,v 1.5 2004/08/31 13:40:21 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Single Port Block RAM +-- /___/ /\ Filename : RAMB4_S16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:53 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAMB4_S16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S16 is + + generic ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + + port ( + DO : out STD_LOGIC_VECTOR (15 downto 0); + + ADDR : in STD_LOGIC_VECTOR (7 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (15 downto 0); + EN : in STD_ULOGIC; + RST : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end RAMB4_S16; + +architecture RAMB4_S16_V of RAMB4_S16 is + constant length : integer := 256; + constant width : integer := 16; + type Two_D_array_type is array ((length - 1) downto 0) of std_logic_vector((width - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width) + (width - 1)) downto (i* width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + + VITALBehavior : process + + + variable address : integer; + variable valid_addr : boolean := FALSE; + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + begin + + valid_addr := addr_is_valid(addr); + + if (valid_addr) then + address := slv_to_int(addr); + end if; + + if (rising_edge(CLK)) then + if (EN = '1') then + if (RST = '1') then + DO <= (others => '0') after 100 ps; + else + if (WE = '1') then + DO <= DI after 100 ps; + else + if (valid_addr) then + DO <= mem(address) after 100 ps; + end if; + end if; + end if; + if (WE = '1') then + if (valid_addr) then + mem(address) := DI; + end if; + end if; + end if; + end if; + wait on CLK; + end process VITALBehavior; +end RAMB4_S16_V; + + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Dual Port Block RAM +-- /___/ /\ Filename : RAMB4_S16_S16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +----- CELL ramb4_s16_s16 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S16_S16 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := ( 0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := ( 0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL" + + ); + + port( + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(15 downto 0); + + ADDRA : in std_logic_vector(7 downto 0); + ADDRB : in std_logic_vector(7 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(15 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB4_S16_S16 : entity is true; +end ramb4_s16_s16; + +architecture RAMB4_S16_S16_V of RAMB4_S16_S16 is + attribute VITAL_LEVEL0 of + RAMB4_S16_S16_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(7 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(15 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal RSTA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(7 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(15 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal RSTB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant length_a : integer := 256; + constant length_b : integer := 256; + constant width_a : integer := 16; + constant width_b : integer := 16; + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width_b - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 7 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 15 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 7 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 15 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA12_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA13_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA14_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA15_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_RSTA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB12_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB13_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB14_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB15_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_RSTB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA12_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA13_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA14_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA15_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB13_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB14_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB15_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + variable DOA_GlitchData2 : VitalGlitchDataType; + variable DOA_GlitchData3 : VitalGlitchDataType; + variable DOA_GlitchData4 : VitalGlitchDataType; + variable DOA_GlitchData5 : VitalGlitchDataType; + variable DOA_GlitchData6 : VitalGlitchDataType; + variable DOA_GlitchData7 : VitalGlitchDataType; + variable DOA_GlitchData8 : VitalGlitchDataType; + variable DOA_GlitchData9 : VitalGlitchDataType; + variable DOA_GlitchData10 : VitalGlitchDataType; + variable DOA_GlitchData11 : VitalGlitchDataType; + variable DOA_GlitchData12 : VitalGlitchDataType; + variable DOA_GlitchData13 : VitalGlitchDataType; + variable DOA_GlitchData14 : VitalGlitchDataType; + variable DOA_GlitchData15 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOB_GlitchData8 : VitalGlitchDataType; + variable DOB_GlitchData9 : VitalGlitchDataType; + variable DOB_GlitchData10 : VitalGlitchDataType; + variable DOB_GlitchData11 : VitalGlitchDataType; + variable DOB_GlitchData12 : VitalGlitchDataType; + variable DOB_GlitchData13 : VitalGlitchDataType; + variable DOB_GlitchData14 : VitalGlitchDataType; + variable DOB_GlitchData15 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOA_zd : std_logic_vector(15 downto 0) := (others => 'X'); + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOB_zd : std_logic_vector(15 downto 0) := (others => 'X'); + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + + variable ADDRA_ipd_sampled : std_logic_vector(7 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable RSTA_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + + variable ADDRB_ipd_sampled : std_logic_vector(7 downto 0) := (others => 'X'); + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable RSTB_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + + variable collision_type : integer := 3; + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB4_S16_S16", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + DOA <= DOA_zd; + DOB <= DOB_zd; + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + RSTA_ipd_sampled := RSTA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + RSTB_ipd_sampled := RSTB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTA_CLKA_posedge, + TimingData => Tmkr_RSTA_CLKA_posedge, + TestSignal => RSTA_ipd, + TestSignalName => "RSTA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTA_CLKA_posedge_posedge, + SetupLow => tsetup_RSTA_CLKA_negedge_posedge, + HoldLow => thold_RSTA_CLKA_posedge_posedge, + HoldHigh => thold_RSTA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA1_CLKA_posedge, + TimingData => Tmkr_DIA1_CLKA_posedge, + TestSignal => DIA_ipd(1), + TestSignalName => "DIA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(1), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(1), + HoldLow => thold_DIA_CLKA_posedge_posedge(1), + HoldHigh => thold_DIA_CLKA_negedge_posedge(1), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA2_CLKA_posedge, + TimingData => Tmkr_DIA2_CLKA_posedge, + TestSignal => DIA_ipd(2), + TestSignalName => "DIA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(2), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(2), + HoldLow => thold_DIA_CLKA_posedge_posedge(2), + HoldHigh => thold_DIA_CLKA_negedge_posedge(2), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA3_CLKA_posedge, + TimingData => Tmkr_DIA3_CLKA_posedge, + TestSignal => DIA_ipd(3), + TestSignalName => "DIA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(3), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(3), + HoldLow => thold_DIA_CLKA_posedge_posedge(3), + HoldHigh => thold_DIA_CLKA_negedge_posedge(3), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA4_CLKA_posedge, + TimingData => Tmkr_DIA4_CLKA_posedge, + TestSignal => DIA_ipd(4), + TestSignalName => "DIA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(4), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(4), + HoldLow => thold_DIA_CLKA_posedge_posedge(4), + HoldHigh => thold_DIA_CLKA_negedge_posedge(4), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA5_CLKA_posedge, + TimingData => Tmkr_DIA5_CLKA_posedge, + TestSignal => DIA_ipd(5), + TestSignalName => "DIA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(5), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(5), + HoldLow => thold_DIA_CLKA_posedge_posedge(5), + HoldHigh => thold_DIA_CLKA_negedge_posedge(5), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA6_CLKA_posedge, + TimingData => Tmkr_DIA6_CLKA_posedge, + TestSignal => DIA_ipd(6), + TestSignalName => "DIA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(6), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(6), + HoldLow => thold_DIA_CLKA_posedge_posedge(6), + HoldHigh => thold_DIA_CLKA_negedge_posedge(6), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA7_CLKA_posedge, + TimingData => Tmkr_DIA7_CLKA_posedge, + TestSignal => DIA_ipd(7), + TestSignalName => "DIA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(7), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(7), + HoldLow => thold_DIA_CLKA_posedge_posedge(7), + HoldHigh => thold_DIA_CLKA_negedge_posedge(7), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA8_CLKA_posedge, + TimingData => Tmkr_DIA8_CLKA_posedge, + TestSignal => DIA_ipd(8), + TestSignalName => "DIA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(8), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(8), + HoldLow => thold_DIA_CLKA_posedge_posedge(8), + HoldHigh => thold_DIA_CLKA_negedge_posedge(8), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA9_CLKA_posedge, + TimingData => Tmkr_DIA9_CLKA_posedge, + TestSignal => DIA_ipd(9), + TestSignalName => "DIA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(9), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(9), + HoldLow => thold_DIA_CLKA_posedge_posedge(9), + HoldHigh => thold_DIA_CLKA_negedge_posedge(9), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA10_CLKA_posedge, + TimingData => Tmkr_DIA10_CLKA_posedge, + TestSignal => DIA_ipd(10), + TestSignalName => "DIA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(10), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(10), + HoldLow => thold_DIA_CLKA_posedge_posedge(10), + HoldHigh => thold_DIA_CLKA_negedge_posedge(10), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA11_CLKA_posedge, + TimingData => Tmkr_DIA11_CLKA_posedge, + TestSignal => DIA_ipd(11), + TestSignalName => "DIA(11)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(11), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(11), + HoldLow => thold_DIA_CLKA_posedge_posedge(11), + HoldHigh => thold_DIA_CLKA_negedge_posedge(11), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA12_CLKA_posedge, + TimingData => Tmkr_DIA12_CLKA_posedge, + TestSignal => DIA_ipd(12), + TestSignalName => "DIA(12)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(12), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(12), + HoldLow => thold_DIA_CLKA_posedge_posedge(12), + HoldHigh => thold_DIA_CLKA_negedge_posedge(12), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA13_CLKA_posedge, + TimingData => Tmkr_DIA13_CLKA_posedge, + TestSignal => DIA_ipd(13), + TestSignalName => "DIA(13)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(13), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(13), + HoldLow => thold_DIA_CLKA_posedge_posedge(13), + HoldHigh => thold_DIA_CLKA_negedge_posedge(13), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA14_CLKA_posedge, + TimingData => Tmkr_DIA14_CLKA_posedge, + TestSignal => DIA_ipd(14), + TestSignalName => "DIA(14)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(14), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(14), + HoldLow => thold_DIA_CLKA_posedge_posedge(14), + HoldHigh => thold_DIA_CLKA_negedge_posedge(14), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTB_CLKB_posedge, + TimingData => Tmkr_RSTB_CLKB_posedge, + TestSignal => RSTB_ipd, + TestSignalName => "RSTB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTB_CLKB_posedge_posedge, + SetupLow => tsetup_RSTB_CLKB_negedge_posedge, + HoldLow => thold_RSTB_CLKB_posedge_posedge, + HoldHigh => thold_RSTB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB7_CLKB_posedge, + TimingData => Tmkr_DIB7_CLKB_posedge, + TestSignal => DIB_ipd(7), + TestSignalName => "DIB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(7), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(7), + HoldLow => thold_DIB_CLKB_posedge_posedge(7), + HoldHigh => thold_DIB_CLKB_negedge_posedge(7), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB8_CLKB_posedge, + TimingData => Tmkr_DIB8_CLKB_posedge, + TestSignal => DIB_ipd(8), + TestSignalName => "DIB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(8), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(8), + HoldLow => thold_DIB_CLKB_posedge_posedge(8), + HoldHigh => thold_DIB_CLKB_negedge_posedge(8), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB9_CLKB_posedge, + TimingData => Tmkr_DIB9_CLKB_posedge, + TestSignal => DIB_ipd(9), + TestSignalName => "DIB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(9), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(9), + HoldLow => thold_DIB_CLKB_posedge_posedge(9), + HoldHigh => thold_DIB_CLKB_negedge_posedge(9), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB10_CLKB_posedge, + TimingData => Tmkr_DIB10_CLKB_posedge, + TestSignal => DIB_ipd(10), + TestSignalName => "DIB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(10), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(10), + HoldLow => thold_DIB_CLKB_posedge_posedge(10), + HoldHigh => thold_DIB_CLKB_negedge_posedge(10), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB11_CLKB_posedge, + TimingData => Tmkr_DIB11_CLKB_posedge, + TestSignal => DIB_ipd(11), + TestSignalName => "DIB(11)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(11), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(11), + HoldLow => thold_DIB_CLKB_posedge_posedge(11), + HoldHigh => thold_DIB_CLKB_negedge_posedge(11), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB12_CLKB_posedge, + TimingData => Tmkr_DIB12_CLKB_posedge, + TestSignal => DIB_ipd(12), + TestSignalName => "DIB(12)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(12), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(12), + HoldLow => thold_DIB_CLKB_posedge_posedge(12), + HoldHigh => thold_DIB_CLKB_negedge_posedge(12), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB13_CLKB_posedge, + TimingData => Tmkr_DIB13_CLKB_posedge, + TestSignal => DIB_ipd(13), + TestSignalName => "DIB(13)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(13), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(13), + HoldLow => thold_DIB_CLKB_posedge_posedge(13), + HoldHigh => thold_DIB_CLKB_negedge_posedge(13), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB14_CLKB_posedge, + TimingData => Tmkr_DIB14_CLKB_posedge, + TestSignal => DIB_ipd(14), + TestSignalName => "DIB(14)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(14), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(14), + HoldLow => thold_DIB_CLKB_posedge_posedge(14), + HoldHigh => thold_DIB_CLKB_negedge_posedge(14), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S16_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_DIA2_CLKA_posedge or + Tviol_DIA3_CLKA_posedge or + Tviol_DIA4_CLKA_posedge or + Tviol_DIA5_CLKA_posedge or + Tviol_DIA6_CLKA_posedge or + Tviol_DIA7_CLKA_posedge or + Tviol_DIA8_CLKA_posedge or + Tviol_DIA9_CLKA_posedge or + Tviol_DIA10_CLKA_posedge or + Tviol_DIA11_CLKA_posedge or + Tviol_DIA12_CLKA_posedge or + Tviol_DIA13_CLKA_posedge or + Tviol_DIA14_CLKA_posedge or + Tviol_DIA15_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_RSTA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIB8_CLKB_posedge or + Tviol_DIB9_CLKB_posedge or + Tviol_DIB10_CLKB_posedge or + Tviol_DIB11_CLKB_posedge or + Tviol_DIB12_CLKB_posedge or + Tviol_DIB13_CLKB_posedge or + Tviol_DIB14_CLKB_posedge or + Tviol_DIB15_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_RSTB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalSetupHoldCheck ( + Violation => Tviol_CLKB_CLKA_posedge, + TimingData => Tmkr_CLKB_CLKA_posedge, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_CLKA_CLKB_posedge, + TimingData => Tmkr_CLKA_CLKB_posedge, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S16_S16", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + + ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge; + + if (ENA_ipd_sampled = '1') then + if (rising_edge(CLKA_ipd)) then + if (WEA_ipd_sampled = '1') then + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (WEB_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S16_S16", + InstanceName => ramb4_s16_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOA_zd := (others => 'X'); + + if (RSTB_ipd_sampled = '0' ) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (RSTB_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S16_S16", + InstanceName => ramb4_s16_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S16_S16", + InstanceName => ramb4_s16_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (RSTA_ipd_sampled = '1') then + DOA_zd := (others => '0'); + end if; + end if; + end if; + + if (ENB_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (WEB_ipd_sampled = '1') then + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + DOB_zd := DIB_ipd; + + if (ViolationCLKAB = 'X') then + if (WEA_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S16_S16", + InstanceName => ramb4_s16_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (RSTA_ipd_sampled = '0' ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if (RSTA_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S16_S16", + InstanceName => ramb4_s16_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S16_S16", + InstanceName => ramb4_s16_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (RSTB_ipd_sampled = '1') then + DOB_zd := (others => '0'); + end if; + end if; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + DOA_zd(1) := ViolationA xor DOA_zd(1); + DOA_zd(2) := ViolationA xor DOA_zd(2); + DOA_zd(3) := ViolationA xor DOA_zd(3); + DOA_zd(4) := ViolationA xor DOA_zd(4); + DOA_zd(5) := ViolationA xor DOA_zd(5); + DOA_zd(6) := ViolationA xor DOA_zd(6); + DOA_zd(7) := ViolationA xor DOA_zd(7); + DOA_zd(8) := ViolationA xor DOA_zd(8); + DOA_zd(9) := ViolationA xor DOA_zd(9); + DOA_zd(10) := ViolationA xor DOA_zd(10); + DOA_zd(11) := ViolationA xor DOA_zd(11); + DOA_zd(12) := ViolationA xor DOA_zd(12); + DOA_zd(13) := ViolationA xor DOA_zd(13); + DOA_zd(14) := ViolationA xor DOA_zd(14); + DOA_zd(15) := ViolationA xor DOA_zd(15); + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOB_zd(8) := ViolationB xor DOB_zd(8); + DOB_zd(9) := ViolationB xor DOB_zd(9); + DOB_zd(10) := ViolationB xor DOB_zd(10); + DOB_zd(11) := ViolationB xor DOB_zd(11); + DOB_zd(12) := ViolationB xor DOB_zd(12); + DOB_zd(13) := ViolationB xor DOB_zd(13); + DOB_zd(14) := ViolationB xor DOB_zd(14); + DOB_zd(15) := ViolationB xor DOB_zd(15); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(2), + GlitchData => DOA_GlitchData2, + OutSignalName => "DOA(2)", + OutTemp => DOA_zd(2), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(3), + GlitchData => DOA_GlitchData3, + OutSignalName => "DOA(3)", + OutTemp => DOA_zd(3), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(4), + GlitchData => DOA_GlitchData4, + OutSignalName => "DOA(4)", + OutTemp => DOA_zd(4), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(5), + GlitchData => DOA_GlitchData5, + OutSignalName => "DOA(5)", + OutTemp => DOA_zd(5), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(6), + GlitchData => DOA_GlitchData6, + OutSignalName => "DOA(6)", + OutTemp => DOA_zd(6), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(7), + GlitchData => DOA_GlitchData7, + OutSignalName => "DOA(7)", + OutTemp => DOA_zd(7), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(8), + GlitchData => DOA_GlitchData8, + OutSignalName => "DOA(8)", + OutTemp => DOA_zd(8), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(9), + GlitchData => DOA_GlitchData9, + OutSignalName => "DOA(9)", + OutTemp => DOA_zd(9), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(10), + GlitchData => DOA_GlitchData10, + OutSignalName => "DOA(10)", + OutTemp => DOA_zd(10), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(11), + GlitchData => DOA_GlitchData11, + OutSignalName => "DOA(11)", + OutTemp => DOA_zd(11), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(12), + GlitchData => DOA_GlitchData12, + OutSignalName => "DOA(12)", + OutTemp => DOA_zd(12), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(13), + GlitchData => DOA_GlitchData13, + OutSignalName => "DOA(13)", + OutTemp => DOA_zd(13), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(14), + GlitchData => DOA_GlitchData14, + OutSignalName => "DOA(14)", + OutTemp => DOA_zd(14), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(15), + GlitchData => DOA_GlitchData15, + OutSignalName => "DOA(15)", + OutTemp => DOA_zd(15), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(8), + GlitchData => DOB_GlitchData8, + OutSignalName => "DOB(8)", + OutTemp => DOB_zd(8), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(9), + GlitchData => DOB_GlitchData9, + OutSignalName => "DOB(9)", + OutTemp => DOB_zd(9), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(10), + GlitchData => DOB_GlitchData10, + OutSignalName => "DOB(10)", + OutTemp => DOB_zd(10), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(11), + GlitchData => DOB_GlitchData11, + OutSignalName => "DOB(11)", + OutTemp => DOB_zd(11), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(12), + GlitchData => DOB_GlitchData12, + OutSignalName => "DOB(12)", + OutTemp => DOB_zd(12), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(13), + GlitchData => DOB_GlitchData13, + OutSignalName => "DOB(13)", + OutTemp => DOB_zd(13), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(14), + GlitchData => DOB_GlitchData14, + OutSignalName => "DOB(14)", + OutTemp => DOB_zd(14), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(15), + GlitchData => DOB_GlitchData15, + OutSignalName => "DOB(15)", + OutTemp => DOB_zd(15), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB4_S16_S16_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Dual Port Block RAM +-- /___/ /\ Filename : RAMB4_S1_S1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +----- CELL ramb4_s1_s1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S1_S1 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(11 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := ( 0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(11 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := ( 0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL" + + ); + + port( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(0 downto 0); + + ADDRA : in std_logic_vector(11 downto 0); + ADDRB : in std_logic_vector(11 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB4_S1_S1 : entity is true; +end ramb4_s1_s1; + +architecture RAMB4_S1_S1_V of RAMB4_S1_S1 is + attribute VITAL_LEVEL0 of + RAMB4_S1_S1_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(11 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal RSTA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(11 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal RSTB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant length_a : integer := 4096; + constant length_b : integer := 4096; + constant width_a : integer := 1; + constant width_b : integer := 1; + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width_b - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 11 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 11 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_RSTA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_RSTB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOA_zd : std_logic_vector(0 downto 0) := (others => 'X'); + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOB_zd : std_logic_vector(0 downto 0) := (others => 'X'); + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + + variable ADDRA_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable RSTA_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + + variable ADDRB_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X'); + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable RSTB_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + + variable collision_type : integer := 3; + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB4_S1_S1", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + DOA <= DOA_zd; + DOB <= DOB_zd; + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + RSTA_ipd_sampled := RSTA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + RSTB_ipd_sampled := RSTB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTA_CLKA_posedge, + TimingData => Tmkr_RSTA_CLKA_posedge, + TestSignal => RSTA_ipd, + TestSignalName => "RSTA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTA_CLKA_posedge_posedge, + SetupLow => tsetup_RSTA_CLKA_negedge_posedge, + HoldLow => thold_RSTA_CLKA_posedge_posedge, + HoldHigh => thold_RSTA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTB_CLKB_posedge, + TimingData => Tmkr_RSTB_CLKB_posedge, + TestSignal => RSTB_ipd, + TestSignalName => "RSTB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTB_CLKB_posedge_posedge, + SetupLow => tsetup_RSTB_CLKB_negedge_posedge, + HoldLow => thold_RSTB_CLKB_posedge_posedge, + HoldHigh => thold_RSTB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB9_CLKB_posedge, + TimingData => Tmkr_ADDRB9_CLKB_posedge, + TestSignal => ADDRB_ipd(9), + TestSignalName => "ADDRB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(9), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(9), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(9), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(9), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB10_CLKB_posedge, + TimingData => Tmkr_ADDRB10_CLKB_posedge, + TestSignal => ADDRB_ipd(10), + TestSignalName => "ADDRB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(10), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(10), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(10), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(10), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S1_S1", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_RSTA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_ADDRB10_CLKB_posedge or + Tviol_ADDRB11_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_RSTB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalSetupHoldCheck ( + Violation => Tviol_CLKB_CLKA_posedge, + TimingData => Tmkr_CLKB_CLKA_posedge, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S1", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_CLKA_CLKB_posedge, + TimingData => Tmkr_CLKA_CLKB_posedge, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S1", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + + ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge; + + if (ENA_ipd_sampled = '1') then + if (rising_edge(CLKA_ipd)) then + if (WEA_ipd_sampled = '1') then + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (WEB_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S1_S1", + InstanceName => ramb4_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOA_zd := (others => 'X'); + + if (RSTB_ipd_sampled = '0' ) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (RSTB_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S1_S1", + InstanceName => ramb4_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S1_S1", + InstanceName => ramb4_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (RSTA_ipd_sampled = '1') then + DOA_zd := (others => '0'); + end if; + end if; + end if; + + if (ENB_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (WEB_ipd_sampled = '1') then + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + DOB_zd := DIB_ipd; + + if (ViolationCLKAB = 'X') then + if (WEA_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S1_S1", + InstanceName => ramb4_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (RSTA_ipd_sampled = '0' ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if (RSTA_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S1_S1", + InstanceName => ramb4_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S1_S1", + InstanceName => ramb4_s1_s1'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (RSTB_ipd_sampled = '1') then + DOB_zd := (others => '0'); + end if; + end if; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + + DOB_zd(0) := ViolationB xor DOB_zd(0); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB4_S1_S1_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Dual Port Block RAM +-- /___/ /\ Filename : RAMB4_S1_S16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +----- CELL ramb4_s1_s16 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S1_S16 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(11 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := ( 0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := ( 0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL" + + ); + + port( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(15 downto 0); + + ADDRA : in std_logic_vector(11 downto 0); + ADDRB : in std_logic_vector(7 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(15 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB4_S1_S16 : entity is true; +end ramb4_s1_s16; + +architecture RAMB4_S1_S16_V of RAMB4_S1_S16 is + attribute VITAL_LEVEL0 of + RAMB4_S1_S16_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(11 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal RSTA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(7 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(15 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal RSTB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant length_a : integer := 4096; + constant length_b : integer := 256; + constant width_a : integer := 1; + constant width_b : integer := 16; + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width_b - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 11 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 7 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 15 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_RSTA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB12_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB13_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB14_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB15_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_RSTB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB13_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB14_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB15_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOB_GlitchData8 : VitalGlitchDataType; + variable DOB_GlitchData9 : VitalGlitchDataType; + variable DOB_GlitchData10 : VitalGlitchDataType; + variable DOB_GlitchData11 : VitalGlitchDataType; + variable DOB_GlitchData12 : VitalGlitchDataType; + variable DOB_GlitchData13 : VitalGlitchDataType; + variable DOB_GlitchData14 : VitalGlitchDataType; + variable DOB_GlitchData15 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOA_zd : std_logic_vector(0 downto 0) := (others => 'X'); + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOB_zd : std_logic_vector(15 downto 0) := (others => 'X'); + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + + variable ADDRA_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable RSTA_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + + variable ADDRB_ipd_sampled : std_logic_vector(7 downto 0) := (others => 'X'); + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable RSTB_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + + variable collision_type : integer := 3; + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB4_S1_S16", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + DOA <= DOA_zd; + DOB <= DOB_zd; + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + RSTA_ipd_sampled := RSTA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + RSTB_ipd_sampled := RSTB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTA_CLKA_posedge, + TimingData => Tmkr_RSTA_CLKA_posedge, + TestSignal => RSTA_ipd, + TestSignalName => "RSTA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTA_CLKA_posedge_posedge, + SetupLow => tsetup_RSTA_CLKA_negedge_posedge, + HoldLow => thold_RSTA_CLKA_posedge_posedge, + HoldHigh => thold_RSTA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTB_CLKB_posedge, + TimingData => Tmkr_RSTB_CLKB_posedge, + TestSignal => RSTB_ipd, + TestSignalName => "RSTB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTB_CLKB_posedge_posedge, + SetupLow => tsetup_RSTB_CLKB_negedge_posedge, + HoldLow => thold_RSTB_CLKB_posedge_posedge, + HoldHigh => thold_RSTB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB7_CLKB_posedge, + TimingData => Tmkr_DIB7_CLKB_posedge, + TestSignal => DIB_ipd(7), + TestSignalName => "DIB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(7), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(7), + HoldLow => thold_DIB_CLKB_posedge_posedge(7), + HoldHigh => thold_DIB_CLKB_negedge_posedge(7), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB8_CLKB_posedge, + TimingData => Tmkr_DIB8_CLKB_posedge, + TestSignal => DIB_ipd(8), + TestSignalName => "DIB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(8), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(8), + HoldLow => thold_DIB_CLKB_posedge_posedge(8), + HoldHigh => thold_DIB_CLKB_negedge_posedge(8), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB9_CLKB_posedge, + TimingData => Tmkr_DIB9_CLKB_posedge, + TestSignal => DIB_ipd(9), + TestSignalName => "DIB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(9), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(9), + HoldLow => thold_DIB_CLKB_posedge_posedge(9), + HoldHigh => thold_DIB_CLKB_negedge_posedge(9), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB10_CLKB_posedge, + TimingData => Tmkr_DIB10_CLKB_posedge, + TestSignal => DIB_ipd(10), + TestSignalName => "DIB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(10), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(10), + HoldLow => thold_DIB_CLKB_posedge_posedge(10), + HoldHigh => thold_DIB_CLKB_negedge_posedge(10), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB11_CLKB_posedge, + TimingData => Tmkr_DIB11_CLKB_posedge, + TestSignal => DIB_ipd(11), + TestSignalName => "DIB(11)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(11), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(11), + HoldLow => thold_DIB_CLKB_posedge_posedge(11), + HoldHigh => thold_DIB_CLKB_negedge_posedge(11), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB12_CLKB_posedge, + TimingData => Tmkr_DIB12_CLKB_posedge, + TestSignal => DIB_ipd(12), + TestSignalName => "DIB(12)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(12), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(12), + HoldLow => thold_DIB_CLKB_posedge_posedge(12), + HoldHigh => thold_DIB_CLKB_negedge_posedge(12), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB13_CLKB_posedge, + TimingData => Tmkr_DIB13_CLKB_posedge, + TestSignal => DIB_ipd(13), + TestSignalName => "DIB(13)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(13), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(13), + HoldLow => thold_DIB_CLKB_posedge_posedge(13), + HoldHigh => thold_DIB_CLKB_negedge_posedge(13), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB14_CLKB_posedge, + TimingData => Tmkr_DIB14_CLKB_posedge, + TestSignal => DIB_ipd(14), + TestSignalName => "DIB(14)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(14), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(14), + HoldLow => thold_DIB_CLKB_posedge_posedge(14), + HoldHigh => thold_DIB_CLKB_negedge_posedge(14), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S1_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_RSTA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIB8_CLKB_posedge or + Tviol_DIB9_CLKB_posedge or + Tviol_DIB10_CLKB_posedge or + Tviol_DIB11_CLKB_posedge or + Tviol_DIB12_CLKB_posedge or + Tviol_DIB13_CLKB_posedge or + Tviol_DIB14_CLKB_posedge or + Tviol_DIB15_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_RSTB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalSetupHoldCheck ( + Violation => Tviol_CLKB_CLKA_posedge, + TimingData => Tmkr_CLKB_CLKA_posedge, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_CLKA_CLKB_posedge, + TimingData => Tmkr_CLKA_CLKB_posedge, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S16", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + + ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge; + + if (ENA_ipd_sampled = '1') then + if (rising_edge(CLKA_ipd)) then + if (WEA_ipd_sampled = '1') then + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (WEB_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S1_S16", + InstanceName => ramb4_s1_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOA_zd := (others => 'X'); + + if (RSTB_ipd_sampled = '0' ) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (RSTB_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S1_S16", + InstanceName => ramb4_s1_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S1_S16", + InstanceName => ramb4_s1_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (RSTA_ipd_sampled = '1') then + DOA_zd := (others => '0'); + end if; + end if; + end if; + + if (ENB_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (WEB_ipd_sampled = '1') then + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + DOB_zd := DIB_ipd; + + if (ViolationCLKAB = 'X') then + if (WEA_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S1_S16", + InstanceName => ramb4_s1_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (RSTA_ipd_sampled = '0' ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if (RSTA_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S1_S16", + InstanceName => ramb4_s1_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S1_S16", + InstanceName => ramb4_s1_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (RSTB_ipd_sampled = '1') then + DOB_zd := (others => '0'); + end if; + end if; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOB_zd(8) := ViolationB xor DOB_zd(8); + DOB_zd(9) := ViolationB xor DOB_zd(9); + DOB_zd(10) := ViolationB xor DOB_zd(10); + DOB_zd(11) := ViolationB xor DOB_zd(11); + DOB_zd(12) := ViolationB xor DOB_zd(12); + DOB_zd(13) := ViolationB xor DOB_zd(13); + DOB_zd(14) := ViolationB xor DOB_zd(14); + DOB_zd(15) := ViolationB xor DOB_zd(15); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(8), + GlitchData => DOB_GlitchData8, + OutSignalName => "DOB(8)", + OutTemp => DOB_zd(8), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(9), + GlitchData => DOB_GlitchData9, + OutSignalName => "DOB(9)", + OutTemp => DOB_zd(9), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(10), + GlitchData => DOB_GlitchData10, + OutSignalName => "DOB(10)", + OutTemp => DOB_zd(10), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(11), + GlitchData => DOB_GlitchData11, + OutSignalName => "DOB(11)", + OutTemp => DOB_zd(11), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(12), + GlitchData => DOB_GlitchData12, + OutSignalName => "DOB(12)", + OutTemp => DOB_zd(12), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(13), + GlitchData => DOB_GlitchData13, + OutSignalName => "DOB(13)", + OutTemp => DOB_zd(13), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(14), + GlitchData => DOB_GlitchData14, + OutSignalName => "DOB(14)", + OutTemp => DOB_zd(14), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(15), + GlitchData => DOB_GlitchData15, + OutSignalName => "DOB(15)", + OutTemp => DOB_zd(15), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB4_S1_S16_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Dual Port Block RAM +-- /___/ /\ Filename : RAMB4_S1_S2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +----- CELL ramb4_s1_s2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S1_S2 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(11 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := ( 0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(10 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := ( 0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL" + + ); + + port( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(1 downto 0); + + ADDRA : in std_logic_vector(11 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB4_S1_S2 : entity is true; +end ramb4_s1_s2; + +architecture RAMB4_S1_S2_V of RAMB4_S1_S2 is + attribute VITAL_LEVEL0 of + RAMB4_S1_S2_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(11 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal RSTA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(10 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal RSTB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant length_a : integer := 4096; + constant length_b : integer := 2048; + constant width_a : integer := 1; + constant width_b : integer := 2; + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width_b - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 11 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 10 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_RSTA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_RSTB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOA_zd : std_logic_vector(0 downto 0) := (others => 'X'); + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOB_zd : std_logic_vector(1 downto 0) := (others => 'X'); + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + + variable ADDRA_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable RSTA_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + + variable ADDRB_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X'); + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable RSTB_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + + variable collision_type : integer := 3; + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB4_S1_S2", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + DOA <= DOA_zd; + DOB <= DOB_zd; + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + RSTA_ipd_sampled := RSTA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + RSTB_ipd_sampled := RSTB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTA_CLKA_posedge, + TimingData => Tmkr_RSTA_CLKA_posedge, + TestSignal => RSTA_ipd, + TestSignalName => "RSTA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTA_CLKA_posedge_posedge, + SetupLow => tsetup_RSTA_CLKA_negedge_posedge, + HoldLow => thold_RSTA_CLKA_posedge_posedge, + HoldHigh => thold_RSTA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTB_CLKB_posedge, + TimingData => Tmkr_RSTB_CLKB_posedge, + TestSignal => RSTB_ipd, + TestSignalName => "RSTB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTB_CLKB_posedge_posedge, + SetupLow => tsetup_RSTB_CLKB_negedge_posedge, + HoldLow => thold_RSTB_CLKB_posedge_posedge, + HoldHigh => thold_RSTB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB9_CLKB_posedge, + TimingData => Tmkr_ADDRB9_CLKB_posedge, + TestSignal => ADDRB_ipd(9), + TestSignalName => "ADDRB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(9), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(9), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(9), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(9), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S1_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_RSTA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_ADDRB10_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_RSTB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalSetupHoldCheck ( + Violation => Tviol_CLKB_CLKA_posedge, + TimingData => Tmkr_CLKB_CLKA_posedge, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_CLKA_CLKB_posedge, + TimingData => Tmkr_CLKA_CLKB_posedge, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S2", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + + ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge; + + if (ENA_ipd_sampled = '1') then + if (rising_edge(CLKA_ipd)) then + if (WEA_ipd_sampled = '1') then + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (WEB_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S1_S2", + InstanceName => ramb4_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOA_zd := (others => 'X'); + + if (RSTB_ipd_sampled = '0' ) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (RSTB_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S1_S2", + InstanceName => ramb4_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S1_S2", + InstanceName => ramb4_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (RSTA_ipd_sampled = '1') then + DOA_zd := (others => '0'); + end if; + end if; + end if; + + if (ENB_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (WEB_ipd_sampled = '1') then + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + DOB_zd := DIB_ipd; + + if (ViolationCLKAB = 'X') then + if (WEA_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S1_S2", + InstanceName => ramb4_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (RSTA_ipd_sampled = '0' ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if (RSTA_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S1_S2", + InstanceName => ramb4_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S1_S2", + InstanceName => ramb4_s1_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (RSTB_ipd_sampled = '1') then + DOB_zd := (others => '0'); + end if; + end if; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB4_S1_S2_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Dual Port Block RAM +-- /___/ /\ Filename : RAMB4_S1_S4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +----- CELL ramb4_s1_s4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S1_S4 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(11 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := ( 0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(9 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := ( 0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL" + + ); + + port( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(3 downto 0); + + ADDRA : in std_logic_vector(11 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB4_S1_S4 : entity is true; +end ramb4_s1_s4; + +architecture RAMB4_S1_S4_V of RAMB4_S1_S4 is + attribute VITAL_LEVEL0 of + RAMB4_S1_S4_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(11 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal RSTA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(9 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal RSTB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant length_a : integer := 4096; + constant length_b : integer := 1024; + constant width_a : integer := 1; + constant width_b : integer := 4; + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width_b - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 11 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 9 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_RSTA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_RSTB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOA_zd : std_logic_vector(0 downto 0) := (others => 'X'); + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOB_zd : std_logic_vector(3 downto 0) := (others => 'X'); + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + + variable ADDRA_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable RSTA_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + + variable ADDRB_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X'); + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable RSTB_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + + variable collision_type : integer := 3; + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB4_S1_S4", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + DOA <= DOA_zd; + DOB <= DOB_zd; + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + RSTA_ipd_sampled := RSTA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + RSTB_ipd_sampled := RSTB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTA_CLKA_posedge, + TimingData => Tmkr_RSTA_CLKA_posedge, + TestSignal => RSTA_ipd, + TestSignalName => "RSTA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTA_CLKA_posedge_posedge, + SetupLow => tsetup_RSTA_CLKA_negedge_posedge, + HoldLow => thold_RSTA_CLKA_posedge_posedge, + HoldHigh => thold_RSTA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTB_CLKB_posedge, + TimingData => Tmkr_RSTB_CLKB_posedge, + TestSignal => RSTB_ipd, + TestSignalName => "RSTB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTB_CLKB_posedge_posedge, + SetupLow => tsetup_RSTB_CLKB_negedge_posedge, + HoldLow => thold_RSTB_CLKB_posedge_posedge, + HoldHigh => thold_RSTB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S1_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_RSTA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_RSTB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalSetupHoldCheck ( + Violation => Tviol_CLKB_CLKA_posedge, + TimingData => Tmkr_CLKB_CLKA_posedge, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_CLKA_CLKB_posedge, + TimingData => Tmkr_CLKA_CLKB_posedge, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S4", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + + ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge; + + if (ENA_ipd_sampled = '1') then + if (rising_edge(CLKA_ipd)) then + if (WEA_ipd_sampled = '1') then + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (WEB_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S1_S4", + InstanceName => ramb4_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOA_zd := (others => 'X'); + + if (RSTB_ipd_sampled = '0' ) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (RSTB_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S1_S4", + InstanceName => ramb4_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S1_S4", + InstanceName => ramb4_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (RSTA_ipd_sampled = '1') then + DOA_zd := (others => '0'); + end if; + end if; + end if; + + if (ENB_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (WEB_ipd_sampled = '1') then + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + DOB_zd := DIB_ipd; + + if (ViolationCLKAB = 'X') then + if (WEA_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S1_S4", + InstanceName => ramb4_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (RSTA_ipd_sampled = '0' ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if (RSTA_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S1_S4", + InstanceName => ramb4_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S1_S4", + InstanceName => ramb4_s1_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (RSTB_ipd_sampled = '1') then + DOB_zd := (others => '0'); + end if; + end if; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB4_S1_S4_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Dual Port Block RAM +-- /___/ /\ Filename : RAMB4_S1_S8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +----- CELL ramb4_s1_s8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S1_S8 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(11 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := ( 0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(8 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := ( 0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(0 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(11 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(0 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL" + + ); + + port( + DOA : out std_logic_vector(0 downto 0); + DOB : out std_logic_vector(7 downto 0); + + ADDRA : in std_logic_vector(11 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(0 downto 0); + DIB : in std_logic_vector(7 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB4_S1_S8 : entity is true; +end ramb4_s1_s8; + +architecture RAMB4_S1_S8_V of RAMB4_S1_S8 is + attribute VITAL_LEVEL0 of + RAMB4_S1_S8_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(11 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(0 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal RSTA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(8 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(7 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal RSTB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant length_a : integer := 4096; + constant length_b : integer := 512; + constant width_a : integer := 1; + constant width_b : integer := 8; + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width_b - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 11 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 0 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 8 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 7 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA11_CLKA_posedge : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_RSTA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_RSTB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA11_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOA_zd : std_logic_vector(0 downto 0) := (others => 'X'); + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOB_zd : std_logic_vector(7 downto 0) := (others => 'X'); + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + + variable ADDRA_ipd_sampled : std_logic_vector(11 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable RSTA_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + + variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X'); + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable RSTB_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + + variable collision_type : integer := 3; + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB4_S1_S8", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + DOA <= DOA_zd; + DOB <= DOB_zd; + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + RSTA_ipd_sampled := RSTA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + RSTB_ipd_sampled := RSTB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTA_CLKA_posedge, + TimingData => Tmkr_RSTA_CLKA_posedge, + TestSignal => RSTA_ipd, + TestSignalName => "RSTA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTA_CLKA_posedge_posedge, + SetupLow => tsetup_RSTA_CLKA_negedge_posedge, + HoldLow => thold_RSTA_CLKA_posedge_posedge, + HoldHigh => thold_RSTA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA10_CLKA_posedge, + TimingData => Tmkr_ADDRA10_CLKA_posedge, + TestSignal => ADDRA_ipd(10), + TestSignalName => "ADDRA(10)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(10), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(10), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(10), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(10), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTB_CLKB_posedge, + TimingData => Tmkr_RSTB_CLKB_posedge, + TestSignal => RSTB_ipd, + TestSignalName => "RSTB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTB_CLKB_posedge_posedge, + SetupLow => tsetup_RSTB_CLKB_negedge_posedge, + HoldLow => thold_RSTB_CLKB_posedge_posedge, + HoldHigh => thold_RSTB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S1_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_ADDRA11_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_RSTA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_RSTB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalSetupHoldCheck ( + Violation => Tviol_CLKB_CLKA_posedge, + TimingData => Tmkr_CLKB_CLKA_posedge, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_CLKA_CLKB_posedge, + TimingData => Tmkr_CLKA_CLKB_posedge, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S1_S8", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + + ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge; + + if (ENA_ipd_sampled = '1') then + if (rising_edge(CLKA_ipd)) then + if (WEA_ipd_sampled = '1') then + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (WEB_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S1_S8", + InstanceName => ramb4_s1_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOA_zd := (others => 'X'); + + if (RSTB_ipd_sampled = '0' ) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (RSTB_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S1_S8", + InstanceName => ramb4_s1_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S1_S8", + InstanceName => ramb4_s1_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (RSTA_ipd_sampled = '1') then + DOA_zd := (others => '0'); + end if; + end if; + end if; + + if (ENB_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (WEB_ipd_sampled = '1') then + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + DOB_zd := DIB_ipd; + + if (ViolationCLKAB = 'X') then + if (WEA_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S1_S8", + InstanceName => ramb4_s1_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (RSTA_ipd_sampled = '0' ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if (RSTA_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S1_S8", + InstanceName => ramb4_s1_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S1_S8", + InstanceName => ramb4_s1_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (RSTB_ipd_sampled = '1') then + DOB_zd := (others => '0'); + end if; + end if; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB4_S1_S8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb4_s2.vhd,v 1.5 2004/08/31 13:40:21 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Single Port Block RAM +-- /___/ /\ Filename : RAMB4_S2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:54 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAMB4_S2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S2 is + + generic ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + + port ( + DO : out STD_LOGIC_VECTOR (1 downto 0); + + ADDR : in STD_LOGIC_VECTOR (10 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (1 downto 0); + EN : in STD_ULOGIC; + RST : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end RAMB4_S2; + +architecture RAMB4_S2_V of RAMB4_S2 is + constant length : integer := 2048; + constant width : integer := 2; + type Two_D_array_type is array ((length - 1) downto 0) of std_logic_vector((width - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width) + (width - 1)) downto (i* width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + VITALBehavior : process + + variable address : integer; + variable valid_addr : boolean := FALSE; + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + begin + valid_addr := addr_is_valid(addr); + + if (valid_addr) then + address := slv_to_int(addr); + end if; + + if (rising_edge(CLK)) then + if (EN = '1') then + if (RST = '1') then + DO <= (others => '0') after 100 ps; + else + if (WE = '1') then + DO <= DI after 100 ps; + else + if (valid_addr) then + DO <= mem(address) after 100 ps; + end if; + end if; + end if; + if (WE = '1') then + if (valid_addr) then + mem(address) := DI; + end if; + end if; + end if; + end if; + wait on CLK; + end process VITALBehavior; +end RAMB4_S2_V; + + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Dual Port Block RAM +-- /___/ /\ Filename : RAMB4_S2_S16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +----- CELL ramb4_s2_s16 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S2_S16 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(10 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := ( 0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := ( 0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL" + + ); + + port( + DOA : out std_logic_vector(1 downto 0); + DOB : out std_logic_vector(15 downto 0); + + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(7 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(1 downto 0); + DIB : in std_logic_vector(15 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB4_S2_S16 : entity is true; +end ramb4_s2_s16; + +architecture RAMB4_S2_S16_V of RAMB4_S2_S16 is + attribute VITAL_LEVEL0 of + RAMB4_S2_S16_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(10 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal RSTA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(7 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(15 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal RSTB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant length_a : integer := 2048; + constant length_b : integer := 256; + constant width_a : integer := 2; + constant width_b : integer := 16; + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width_b - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 10 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 7 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 15 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_RSTA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB12_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB13_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB14_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB15_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_RSTB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB13_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB14_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB15_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOB_GlitchData8 : VitalGlitchDataType; + variable DOB_GlitchData9 : VitalGlitchDataType; + variable DOB_GlitchData10 : VitalGlitchDataType; + variable DOB_GlitchData11 : VitalGlitchDataType; + variable DOB_GlitchData12 : VitalGlitchDataType; + variable DOB_GlitchData13 : VitalGlitchDataType; + variable DOB_GlitchData14 : VitalGlitchDataType; + variable DOB_GlitchData15 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOA_zd : std_logic_vector(1 downto 0) := (others => 'X'); + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOB_zd : std_logic_vector(15 downto 0) := (others => 'X'); + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + + variable ADDRA_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable RSTA_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + + variable ADDRB_ipd_sampled : std_logic_vector(7 downto 0) := (others => 'X'); + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable RSTB_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + + variable collision_type : integer := 3; + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB4_S2_S16", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + DOA <= DOA_zd; + DOB <= DOB_zd; + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + RSTA_ipd_sampled := RSTA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + RSTB_ipd_sampled := RSTB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTA_CLKA_posedge, + TimingData => Tmkr_RSTA_CLKA_posedge, + TestSignal => RSTA_ipd, + TestSignalName => "RSTA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTA_CLKA_posedge_posedge, + SetupLow => tsetup_RSTA_CLKA_negedge_posedge, + HoldLow => thold_RSTA_CLKA_posedge_posedge, + HoldHigh => thold_RSTA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTB_CLKB_posedge, + TimingData => Tmkr_RSTB_CLKB_posedge, + TestSignal => RSTB_ipd, + TestSignalName => "RSTB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTB_CLKB_posedge_posedge, + SetupLow => tsetup_RSTB_CLKB_negedge_posedge, + HoldLow => thold_RSTB_CLKB_posedge_posedge, + HoldHigh => thold_RSTB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB7_CLKB_posedge, + TimingData => Tmkr_DIB7_CLKB_posedge, + TestSignal => DIB_ipd(7), + TestSignalName => "DIB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(7), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(7), + HoldLow => thold_DIB_CLKB_posedge_posedge(7), + HoldHigh => thold_DIB_CLKB_negedge_posedge(7), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB8_CLKB_posedge, + TimingData => Tmkr_DIB8_CLKB_posedge, + TestSignal => DIB_ipd(8), + TestSignalName => "DIB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(8), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(8), + HoldLow => thold_DIB_CLKB_posedge_posedge(8), + HoldHigh => thold_DIB_CLKB_negedge_posedge(8), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB9_CLKB_posedge, + TimingData => Tmkr_DIB9_CLKB_posedge, + TestSignal => DIB_ipd(9), + TestSignalName => "DIB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(9), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(9), + HoldLow => thold_DIB_CLKB_posedge_posedge(9), + HoldHigh => thold_DIB_CLKB_negedge_posedge(9), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB10_CLKB_posedge, + TimingData => Tmkr_DIB10_CLKB_posedge, + TestSignal => DIB_ipd(10), + TestSignalName => "DIB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(10), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(10), + HoldLow => thold_DIB_CLKB_posedge_posedge(10), + HoldHigh => thold_DIB_CLKB_negedge_posedge(10), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB11_CLKB_posedge, + TimingData => Tmkr_DIB11_CLKB_posedge, + TestSignal => DIB_ipd(11), + TestSignalName => "DIB(11)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(11), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(11), + HoldLow => thold_DIB_CLKB_posedge_posedge(11), + HoldHigh => thold_DIB_CLKB_negedge_posedge(11), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB12_CLKB_posedge, + TimingData => Tmkr_DIB12_CLKB_posedge, + TestSignal => DIB_ipd(12), + TestSignalName => "DIB(12)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(12), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(12), + HoldLow => thold_DIB_CLKB_posedge_posedge(12), + HoldHigh => thold_DIB_CLKB_negedge_posedge(12), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB13_CLKB_posedge, + TimingData => Tmkr_DIB13_CLKB_posedge, + TestSignal => DIB_ipd(13), + TestSignalName => "DIB(13)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(13), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(13), + HoldLow => thold_DIB_CLKB_posedge_posedge(13), + HoldHigh => thold_DIB_CLKB_negedge_posedge(13), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB14_CLKB_posedge, + TimingData => Tmkr_DIB14_CLKB_posedge, + TestSignal => DIB_ipd(14), + TestSignalName => "DIB(14)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(14), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(14), + HoldLow => thold_DIB_CLKB_posedge_posedge(14), + HoldHigh => thold_DIB_CLKB_negedge_posedge(14), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S2_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_RSTA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIB8_CLKB_posedge or + Tviol_DIB9_CLKB_posedge or + Tviol_DIB10_CLKB_posedge or + Tviol_DIB11_CLKB_posedge or + Tviol_DIB12_CLKB_posedge or + Tviol_DIB13_CLKB_posedge or + Tviol_DIB14_CLKB_posedge or + Tviol_DIB15_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_RSTB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalSetupHoldCheck ( + Violation => Tviol_CLKB_CLKA_posedge, + TimingData => Tmkr_CLKB_CLKA_posedge, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_CLKA_CLKB_posedge, + TimingData => Tmkr_CLKA_CLKB_posedge, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S16", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + + ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge; + + if (ENA_ipd_sampled = '1') then + if (rising_edge(CLKA_ipd)) then + if (WEA_ipd_sampled = '1') then + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (WEB_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S2_S16", + InstanceName => ramb4_s2_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOA_zd := (others => 'X'); + + if (RSTB_ipd_sampled = '0' ) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (RSTB_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S2_S16", + InstanceName => ramb4_s2_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S2_S16", + InstanceName => ramb4_s2_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (RSTA_ipd_sampled = '1') then + DOA_zd := (others => '0'); + end if; + end if; + end if; + + if (ENB_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (WEB_ipd_sampled = '1') then + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + DOB_zd := DIB_ipd; + + if (ViolationCLKAB = 'X') then + if (WEA_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S2_S16", + InstanceName => ramb4_s2_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (RSTA_ipd_sampled = '0' ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if (RSTA_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S2_S16", + InstanceName => ramb4_s2_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S2_S16", + InstanceName => ramb4_s2_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (RSTB_ipd_sampled = '1') then + DOB_zd := (others => '0'); + end if; + end if; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + DOA_zd(1) := ViolationA xor DOA_zd(1); + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOB_zd(8) := ViolationB xor DOB_zd(8); + DOB_zd(9) := ViolationB xor DOB_zd(9); + DOB_zd(10) := ViolationB xor DOB_zd(10); + DOB_zd(11) := ViolationB xor DOB_zd(11); + DOB_zd(12) := ViolationB xor DOB_zd(12); + DOB_zd(13) := ViolationB xor DOB_zd(13); + DOB_zd(14) := ViolationB xor DOB_zd(14); + DOB_zd(15) := ViolationB xor DOB_zd(15); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(8), + GlitchData => DOB_GlitchData8, + OutSignalName => "DOB(8)", + OutTemp => DOB_zd(8), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(9), + GlitchData => DOB_GlitchData9, + OutSignalName => "DOB(9)", + OutTemp => DOB_zd(9), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(10), + GlitchData => DOB_GlitchData10, + OutSignalName => "DOB(10)", + OutTemp => DOB_zd(10), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(11), + GlitchData => DOB_GlitchData11, + OutSignalName => "DOB(11)", + OutTemp => DOB_zd(11), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(12), + GlitchData => DOB_GlitchData12, + OutSignalName => "DOB(12)", + OutTemp => DOB_zd(12), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(13), + GlitchData => DOB_GlitchData13, + OutSignalName => "DOB(13)", + OutTemp => DOB_zd(13), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(14), + GlitchData => DOB_GlitchData14, + OutSignalName => "DOB(14)", + OutTemp => DOB_zd(14), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(15), + GlitchData => DOB_GlitchData15, + OutSignalName => "DOB(15)", + OutTemp => DOB_zd(15), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB4_S2_S16_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Dual Port Block RAM +-- /___/ /\ Filename : RAMB4_S2_S2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +----- CELL ramb4_s2_s2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S2_S2 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(10 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := ( 0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(10 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := ( 0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL" + + ); + + port( + DOA : out std_logic_vector(1 downto 0); + DOB : out std_logic_vector(1 downto 0); + + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(1 downto 0); + DIB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB4_S2_S2 : entity is true; +end ramb4_s2_s2; + +architecture RAMB4_S2_S2_V of RAMB4_S2_S2 is + attribute VITAL_LEVEL0 of + RAMB4_S2_S2_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(10 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal RSTA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(10 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal RSTB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant length_a : integer := 2048; + constant length_b : integer := 2048; + constant width_a : integer := 2; + constant width_b : integer := 2; + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width_b - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 10 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 10 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_RSTA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_RSTB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOA_zd : std_logic_vector(1 downto 0) := (others => 'X'); + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOB_zd : std_logic_vector(1 downto 0) := (others => 'X'); + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + + variable ADDRA_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable RSTA_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + + variable ADDRB_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X'); + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable RSTB_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + + variable collision_type : integer := 3; + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB4_S2_S2", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + DOA <= DOA_zd; + DOB <= DOB_zd; + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + RSTA_ipd_sampled := RSTA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + RSTB_ipd_sampled := RSTB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTA_CLKA_posedge, + TimingData => Tmkr_RSTA_CLKA_posedge, + TestSignal => RSTA_ipd, + TestSignalName => "RSTA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTA_CLKA_posedge_posedge, + SetupLow => tsetup_RSTA_CLKA_negedge_posedge, + HoldLow => thold_RSTA_CLKA_posedge_posedge, + HoldHigh => thold_RSTA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTB_CLKB_posedge, + TimingData => Tmkr_RSTB_CLKB_posedge, + TestSignal => RSTB_ipd, + TestSignalName => "RSTB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTB_CLKB_posedge_posedge, + SetupLow => tsetup_RSTB_CLKB_negedge_posedge, + HoldLow => thold_RSTB_CLKB_posedge_posedge, + HoldHigh => thold_RSTB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB9_CLKB_posedge, + TimingData => Tmkr_ADDRB9_CLKB_posedge, + TestSignal => ADDRB_ipd(9), + TestSignalName => "ADDRB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(9), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(9), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(9), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(9), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S2_S2", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_RSTA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_ADDRB10_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_RSTB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalSetupHoldCheck ( + Violation => Tviol_CLKB_CLKA_posedge, + TimingData => Tmkr_CLKB_CLKA_posedge, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_CLKA_CLKB_posedge, + TimingData => Tmkr_CLKA_CLKB_posedge, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S2", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + + ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge; + + if (ENA_ipd_sampled = '1') then + if (rising_edge(CLKA_ipd)) then + if (WEA_ipd_sampled = '1') then + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (WEB_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S2_S2", + InstanceName => ramb4_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOA_zd := (others => 'X'); + + if (RSTB_ipd_sampled = '0' ) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (RSTB_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S2_S2", + InstanceName => ramb4_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S2_S2", + InstanceName => ramb4_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (RSTA_ipd_sampled = '1') then + DOA_zd := (others => '0'); + end if; + end if; + end if; + + if (ENB_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (WEB_ipd_sampled = '1') then + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + DOB_zd := DIB_ipd; + + if (ViolationCLKAB = 'X') then + if (WEA_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S2_S2", + InstanceName => ramb4_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (RSTA_ipd_sampled = '0' ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if (RSTA_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S2_S2", + InstanceName => ramb4_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S2_S2", + InstanceName => ramb4_s2_s2'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (RSTB_ipd_sampled = '1') then + DOB_zd := (others => '0'); + end if; + end if; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + DOA_zd(1) := ViolationA xor DOA_zd(1); + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB4_S2_S2_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Dual Port Block RAM +-- /___/ /\ Filename : RAMB4_S2_S4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +----- CELL ramb4_s2_s4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S2_S4 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(10 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := ( 0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(9 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := ( 0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL" + + ); + + port( + DOA : out std_logic_vector(1 downto 0); + DOB : out std_logic_vector(3 downto 0); + + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(1 downto 0); + DIB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB4_S2_S4 : entity is true; +end ramb4_s2_s4; + +architecture RAMB4_S2_S4_V of RAMB4_S2_S4 is + attribute VITAL_LEVEL0 of + RAMB4_S2_S4_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(10 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal RSTA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(9 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal RSTB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant length_a : integer := 2048; + constant length_b : integer := 1024; + constant width_a : integer := 2; + constant width_b : integer := 4; + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width_b - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 10 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 9 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_RSTA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_RSTB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOA_zd : std_logic_vector(1 downto 0) := (others => 'X'); + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOB_zd : std_logic_vector(3 downto 0) := (others => 'X'); + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + + variable ADDRA_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable RSTA_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + + variable ADDRB_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X'); + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable RSTB_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + + variable collision_type : integer := 3; + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB4_S2_S4", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + DOA <= DOA_zd; + DOB <= DOB_zd; + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + RSTA_ipd_sampled := RSTA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + RSTB_ipd_sampled := RSTB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTA_CLKA_posedge, + TimingData => Tmkr_RSTA_CLKA_posedge, + TestSignal => RSTA_ipd, + TestSignalName => "RSTA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTA_CLKA_posedge_posedge, + SetupLow => tsetup_RSTA_CLKA_negedge_posedge, + HoldLow => thold_RSTA_CLKA_posedge_posedge, + HoldHigh => thold_RSTA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTB_CLKB_posedge, + TimingData => Tmkr_RSTB_CLKB_posedge, + TestSignal => RSTB_ipd, + TestSignalName => "RSTB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTB_CLKB_posedge_posedge, + SetupLow => tsetup_RSTB_CLKB_negedge_posedge, + HoldLow => thold_RSTB_CLKB_posedge_posedge, + HoldHigh => thold_RSTB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S2_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_RSTA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_RSTB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalSetupHoldCheck ( + Violation => Tviol_CLKB_CLKA_posedge, + TimingData => Tmkr_CLKB_CLKA_posedge, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_CLKA_CLKB_posedge, + TimingData => Tmkr_CLKA_CLKB_posedge, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S4", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + + ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge; + + if (ENA_ipd_sampled = '1') then + if (rising_edge(CLKA_ipd)) then + if (WEA_ipd_sampled = '1') then + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (WEB_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S2_S4", + InstanceName => ramb4_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOA_zd := (others => 'X'); + + if (RSTB_ipd_sampled = '0' ) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (RSTB_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S2_S4", + InstanceName => ramb4_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S2_S4", + InstanceName => ramb4_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (RSTA_ipd_sampled = '1') then + DOA_zd := (others => '0'); + end if; + end if; + end if; + + if (ENB_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (WEB_ipd_sampled = '1') then + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + DOB_zd := DIB_ipd; + + if (ViolationCLKAB = 'X') then + if (WEA_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S2_S4", + InstanceName => ramb4_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (RSTA_ipd_sampled = '0' ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if (RSTA_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S2_S4", + InstanceName => ramb4_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S2_S4", + InstanceName => ramb4_s2_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (RSTB_ipd_sampled = '1') then + DOB_zd := (others => '0'); + end if; + end if; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + DOA_zd(1) := ViolationA xor DOA_zd(1); + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB4_S2_S4_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Dual Port Block RAM +-- /___/ /\ Filename : RAMB4_S2_S8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +----- CELL ramb4_s2_s8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S2_S8 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(10 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := ( 0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(8 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := ( 0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(1 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(10 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(1 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL" + + ); + + port( + DOA : out std_logic_vector(1 downto 0); + DOB : out std_logic_vector(7 downto 0); + + ADDRA : in std_logic_vector(10 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(1 downto 0); + DIB : in std_logic_vector(7 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB4_S2_S8 : entity is true; +end ramb4_s2_s8; + +architecture RAMB4_S2_S8_V of RAMB4_S2_S8 is + attribute VITAL_LEVEL0 of + RAMB4_S2_S8_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(10 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal RSTA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(8 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(7 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal RSTB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant length_a : integer := 2048; + constant length_b : integer := 512; + constant width_a : integer := 2; + constant width_b : integer := 8; + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width_b - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 10 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 1 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 8 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 7 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA10_CLKA_posedge : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_RSTA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_RSTB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA10_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOA_zd : std_logic_vector(1 downto 0) := (others => 'X'); + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOB_zd : std_logic_vector(7 downto 0) := (others => 'X'); + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + + variable ADDRA_ipd_sampled : std_logic_vector(10 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable RSTA_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + + variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X'); + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable RSTB_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + + variable collision_type : integer := 3; + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB4_S2_S8", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + DOA <= DOA_zd; + DOB <= DOB_zd; + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + RSTA_ipd_sampled := RSTA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + RSTB_ipd_sampled := RSTB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTA_CLKA_posedge, + TimingData => Tmkr_RSTA_CLKA_posedge, + TestSignal => RSTA_ipd, + TestSignalName => "RSTA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTA_CLKA_posedge_posedge, + SetupLow => tsetup_RSTA_CLKA_negedge_posedge, + HoldLow => thold_RSTA_CLKA_posedge_posedge, + HoldHigh => thold_RSTA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA9_CLKA_posedge, + TimingData => Tmkr_ADDRA9_CLKA_posedge, + TestSignal => ADDRA_ipd(9), + TestSignalName => "ADDRA(9)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(9), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(9), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(9), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(9), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTB_CLKB_posedge, + TimingData => Tmkr_RSTB_CLKB_posedge, + TestSignal => RSTB_ipd, + TestSignalName => "RSTB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTB_CLKB_posedge_posedge, + SetupLow => tsetup_RSTB_CLKB_negedge_posedge, + HoldLow => thold_RSTB_CLKB_posedge_posedge, + HoldHigh => thold_RSTB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S2_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_ADDRA10_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_RSTA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_RSTB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalSetupHoldCheck ( + Violation => Tviol_CLKB_CLKA_posedge, + TimingData => Tmkr_CLKB_CLKA_posedge, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_CLKA_CLKB_posedge, + TimingData => Tmkr_CLKA_CLKB_posedge, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S2_S8", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + + ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge; + + if (ENA_ipd_sampled = '1') then + if (rising_edge(CLKA_ipd)) then + if (WEA_ipd_sampled = '1') then + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (WEB_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S2_S8", + InstanceName => ramb4_s2_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOA_zd := (others => 'X'); + + if (RSTB_ipd_sampled = '0' ) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (RSTB_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S2_S8", + InstanceName => ramb4_s2_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S2_S8", + InstanceName => ramb4_s2_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (RSTA_ipd_sampled = '1') then + DOA_zd := (others => '0'); + end if; + end if; + end if; + + if (ENB_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (WEB_ipd_sampled = '1') then + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + DOB_zd := DIB_ipd; + + if (ViolationCLKAB = 'X') then + if (WEA_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S2_S8", + InstanceName => ramb4_s2_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (RSTA_ipd_sampled = '0' ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if (RSTA_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S2_S8", + InstanceName => ramb4_s2_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S2_S8", + InstanceName => ramb4_s2_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (RSTB_ipd_sampled = '1') then + DOB_zd := (others => '0'); + end if; + end if; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + DOA_zd(1) := ViolationA xor DOA_zd(1); + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB4_S2_S8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb4_s4.vhd,v 1.5 2004/08/31 13:40:21 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Single Port Block RAM +-- /___/ /\ Filename : RAMB4_S4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:55 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAMB4_S4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S4 is + + generic ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + + port ( + DO : out STD_LOGIC_VECTOR (3 downto 0); + + ADDR : in STD_LOGIC_VECTOR (9 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (3 downto 0); + EN : in STD_ULOGIC; + RST : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end RAMB4_S4; + +architecture RAMB4_S4_V of RAMB4_S4 is + constant length : integer := 1024; + constant width : integer := 4; + type Two_D_array_type is array ((length - 1) downto 0) of std_logic_vector((width - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width) + (width - 1)) downto (i* width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + + VITALBehavior : process + + variable address : integer; + variable valid_addr : boolean := FALSE; + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + begin + valid_addr := addr_is_valid(addr); + + if (valid_addr) then + address := slv_to_int(addr); + end if; + + if (rising_edge(CLK)) then + if (EN = '1') then + if (RST = '1') then + DO <= (others => '0') after 100 ps; + else + if (WE = '1') then + DO <= DI after 100 ps; + else + if (valid_addr) then + DO <= mem(address) after 100 ps; + end if; + end if; + end if; + if (WE = '1') then + if (valid_addr) then + mem(address) := DI; + end if; + end if; + end if; + end if; + wait on CLK; + end process VITALBehavior; +end RAMB4_S4_V; + + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Dual Port Block RAM +-- /___/ /\ Filename : RAMB4_S4_S16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +----- CELL ramb4_s4_s16 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S4_S16 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(9 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := ( 0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := ( 0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL" + + ); + + port( + DOA : out std_logic_vector(3 downto 0); + DOB : out std_logic_vector(15 downto 0); + + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(7 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(3 downto 0); + DIB : in std_logic_vector(15 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB4_S4_S16 : entity is true; +end ramb4_s4_s16; + +architecture RAMB4_S4_S16_V of RAMB4_S4_S16 is + attribute VITAL_LEVEL0 of + RAMB4_S4_S16_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(9 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal RSTA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(7 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(15 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal RSTB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant length_a : integer := 1024; + constant length_b : integer := 256; + constant width_a : integer := 4; + constant width_b : integer := 16; + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width_b - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 9 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 7 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 15 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_RSTA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB12_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB13_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB14_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB15_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_RSTB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB13_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB14_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB15_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + variable DOA_GlitchData2 : VitalGlitchDataType; + variable DOA_GlitchData3 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOB_GlitchData8 : VitalGlitchDataType; + variable DOB_GlitchData9 : VitalGlitchDataType; + variable DOB_GlitchData10 : VitalGlitchDataType; + variable DOB_GlitchData11 : VitalGlitchDataType; + variable DOB_GlitchData12 : VitalGlitchDataType; + variable DOB_GlitchData13 : VitalGlitchDataType; + variable DOB_GlitchData14 : VitalGlitchDataType; + variable DOB_GlitchData15 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOA_zd : std_logic_vector(3 downto 0) := (others => 'X'); + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOB_zd : std_logic_vector(15 downto 0) := (others => 'X'); + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + + variable ADDRA_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable RSTA_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + + variable ADDRB_ipd_sampled : std_logic_vector(7 downto 0) := (others => 'X'); + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable RSTB_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + + variable collision_type : integer := 3; + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB4_S4_S16", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + DOA <= DOA_zd; + DOB <= DOB_zd; + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + RSTA_ipd_sampled := RSTA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + RSTB_ipd_sampled := RSTB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTA_CLKA_posedge, + TimingData => Tmkr_RSTA_CLKA_posedge, + TestSignal => RSTA_ipd, + TestSignalName => "RSTA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTA_CLKA_posedge_posedge, + SetupLow => tsetup_RSTA_CLKA_negedge_posedge, + HoldLow => thold_RSTA_CLKA_posedge_posedge, + HoldHigh => thold_RSTA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA1_CLKA_posedge, + TimingData => Tmkr_DIA1_CLKA_posedge, + TestSignal => DIA_ipd(1), + TestSignalName => "DIA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(1), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(1), + HoldLow => thold_DIA_CLKA_posedge_posedge(1), + HoldHigh => thold_DIA_CLKA_negedge_posedge(1), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA2_CLKA_posedge, + TimingData => Tmkr_DIA2_CLKA_posedge, + TestSignal => DIA_ipd(2), + TestSignalName => "DIA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(2), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(2), + HoldLow => thold_DIA_CLKA_posedge_posedge(2), + HoldHigh => thold_DIA_CLKA_negedge_posedge(2), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTB_CLKB_posedge, + TimingData => Tmkr_RSTB_CLKB_posedge, + TestSignal => RSTB_ipd, + TestSignalName => "RSTB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTB_CLKB_posedge_posedge, + SetupLow => tsetup_RSTB_CLKB_negedge_posedge, + HoldLow => thold_RSTB_CLKB_posedge_posedge, + HoldHigh => thold_RSTB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB7_CLKB_posedge, + TimingData => Tmkr_DIB7_CLKB_posedge, + TestSignal => DIB_ipd(7), + TestSignalName => "DIB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(7), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(7), + HoldLow => thold_DIB_CLKB_posedge_posedge(7), + HoldHigh => thold_DIB_CLKB_negedge_posedge(7), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB8_CLKB_posedge, + TimingData => Tmkr_DIB8_CLKB_posedge, + TestSignal => DIB_ipd(8), + TestSignalName => "DIB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(8), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(8), + HoldLow => thold_DIB_CLKB_posedge_posedge(8), + HoldHigh => thold_DIB_CLKB_negedge_posedge(8), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB9_CLKB_posedge, + TimingData => Tmkr_DIB9_CLKB_posedge, + TestSignal => DIB_ipd(9), + TestSignalName => "DIB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(9), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(9), + HoldLow => thold_DIB_CLKB_posedge_posedge(9), + HoldHigh => thold_DIB_CLKB_negedge_posedge(9), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB10_CLKB_posedge, + TimingData => Tmkr_DIB10_CLKB_posedge, + TestSignal => DIB_ipd(10), + TestSignalName => "DIB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(10), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(10), + HoldLow => thold_DIB_CLKB_posedge_posedge(10), + HoldHigh => thold_DIB_CLKB_negedge_posedge(10), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB11_CLKB_posedge, + TimingData => Tmkr_DIB11_CLKB_posedge, + TestSignal => DIB_ipd(11), + TestSignalName => "DIB(11)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(11), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(11), + HoldLow => thold_DIB_CLKB_posedge_posedge(11), + HoldHigh => thold_DIB_CLKB_negedge_posedge(11), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB12_CLKB_posedge, + TimingData => Tmkr_DIB12_CLKB_posedge, + TestSignal => DIB_ipd(12), + TestSignalName => "DIB(12)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(12), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(12), + HoldLow => thold_DIB_CLKB_posedge_posedge(12), + HoldHigh => thold_DIB_CLKB_negedge_posedge(12), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB13_CLKB_posedge, + TimingData => Tmkr_DIB13_CLKB_posedge, + TestSignal => DIB_ipd(13), + TestSignalName => "DIB(13)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(13), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(13), + HoldLow => thold_DIB_CLKB_posedge_posedge(13), + HoldHigh => thold_DIB_CLKB_negedge_posedge(13), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB14_CLKB_posedge, + TimingData => Tmkr_DIB14_CLKB_posedge, + TestSignal => DIB_ipd(14), + TestSignalName => "DIB(14)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(14), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(14), + HoldLow => thold_DIB_CLKB_posedge_posedge(14), + HoldHigh => thold_DIB_CLKB_negedge_posedge(14), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S4_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_DIA2_CLKA_posedge or + Tviol_DIA3_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_RSTA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIB8_CLKB_posedge or + Tviol_DIB9_CLKB_posedge or + Tviol_DIB10_CLKB_posedge or + Tviol_DIB11_CLKB_posedge or + Tviol_DIB12_CLKB_posedge or + Tviol_DIB13_CLKB_posedge or + Tviol_DIB14_CLKB_posedge or + Tviol_DIB15_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_RSTB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalSetupHoldCheck ( + Violation => Tviol_CLKB_CLKA_posedge, + TimingData => Tmkr_CLKB_CLKA_posedge, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_CLKA_CLKB_posedge, + TimingData => Tmkr_CLKA_CLKB_posedge, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S16", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + + ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge; + + if (ENA_ipd_sampled = '1') then + if (rising_edge(CLKA_ipd)) then + if (WEA_ipd_sampled = '1') then + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (WEB_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S4_S16", + InstanceName => ramb4_s4_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOA_zd := (others => 'X'); + + if (RSTB_ipd_sampled = '0' ) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (RSTB_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S4_S16", + InstanceName => ramb4_s4_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S4_S16", + InstanceName => ramb4_s4_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (RSTA_ipd_sampled = '1') then + DOA_zd := (others => '0'); + end if; + end if; + end if; + + if (ENB_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (WEB_ipd_sampled = '1') then + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + DOB_zd := DIB_ipd; + + if (ViolationCLKAB = 'X') then + if (WEA_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S4_S16", + InstanceName => ramb4_s4_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (RSTA_ipd_sampled = '0' ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if (RSTA_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S4_S16", + InstanceName => ramb4_s4_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S4_S16", + InstanceName => ramb4_s4_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (RSTB_ipd_sampled = '1') then + DOB_zd := (others => '0'); + end if; + end if; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + DOA_zd(1) := ViolationA xor DOA_zd(1); + DOA_zd(2) := ViolationA xor DOA_zd(2); + DOA_zd(3) := ViolationA xor DOA_zd(3); + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOB_zd(8) := ViolationB xor DOB_zd(8); + DOB_zd(9) := ViolationB xor DOB_zd(9); + DOB_zd(10) := ViolationB xor DOB_zd(10); + DOB_zd(11) := ViolationB xor DOB_zd(11); + DOB_zd(12) := ViolationB xor DOB_zd(12); + DOB_zd(13) := ViolationB xor DOB_zd(13); + DOB_zd(14) := ViolationB xor DOB_zd(14); + DOB_zd(15) := ViolationB xor DOB_zd(15); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(2), + GlitchData => DOA_GlitchData2, + OutSignalName => "DOA(2)", + OutTemp => DOA_zd(2), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(3), + GlitchData => DOA_GlitchData3, + OutSignalName => "DOA(3)", + OutTemp => DOA_zd(3), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(8), + GlitchData => DOB_GlitchData8, + OutSignalName => "DOB(8)", + OutTemp => DOB_zd(8), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(9), + GlitchData => DOB_GlitchData9, + OutSignalName => "DOB(9)", + OutTemp => DOB_zd(9), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(10), + GlitchData => DOB_GlitchData10, + OutSignalName => "DOB(10)", + OutTemp => DOB_zd(10), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(11), + GlitchData => DOB_GlitchData11, + OutSignalName => "DOB(11)", + OutTemp => DOB_zd(11), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(12), + GlitchData => DOB_GlitchData12, + OutSignalName => "DOB(12)", + OutTemp => DOB_zd(12), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(13), + GlitchData => DOB_GlitchData13, + OutSignalName => "DOB(13)", + OutTemp => DOB_zd(13), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(14), + GlitchData => DOB_GlitchData14, + OutSignalName => "DOB(14)", + OutTemp => DOB_zd(14), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(15), + GlitchData => DOB_GlitchData15, + OutSignalName => "DOB(15)", + OutTemp => DOB_zd(15), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB4_S4_S16_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Dual Port Block RAM +-- /___/ /\ Filename : RAMB4_S4_S4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +----- CELL ramb4_s4_s4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S4_S4 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(9 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := ( 0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(9 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := ( 0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL" + + ); + + port( + DOA : out std_logic_vector(3 downto 0); + DOB : out std_logic_vector(3 downto 0); + + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(3 downto 0); + DIB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB4_S4_S4 : entity is true; +end ramb4_s4_s4; + +architecture RAMB4_S4_S4_V of RAMB4_S4_S4 is + attribute VITAL_LEVEL0 of + RAMB4_S4_S4_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(9 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal RSTA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(9 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal RSTB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant length_a : integer := 1024; + constant length_b : integer := 1024; + constant width_a : integer := 4; + constant width_b : integer := 4; + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width_b - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 9 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 9 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_RSTA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_RSTB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + variable DOA_GlitchData2 : VitalGlitchDataType; + variable DOA_GlitchData3 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOA_zd : std_logic_vector(3 downto 0) := (others => 'X'); + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOB_zd : std_logic_vector(3 downto 0) := (others => 'X'); + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + + variable ADDRA_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable RSTA_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + + variable ADDRB_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X'); + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable RSTB_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + + variable collision_type : integer := 3; + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB4_S4_S4", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + DOA <= DOA_zd; + DOB <= DOB_zd; + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + RSTA_ipd_sampled := RSTA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + RSTB_ipd_sampled := RSTB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTA_CLKA_posedge, + TimingData => Tmkr_RSTA_CLKA_posedge, + TestSignal => RSTA_ipd, + TestSignalName => "RSTA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTA_CLKA_posedge_posedge, + SetupLow => tsetup_RSTA_CLKA_negedge_posedge, + HoldLow => thold_RSTA_CLKA_posedge_posedge, + HoldHigh => thold_RSTA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA1_CLKA_posedge, + TimingData => Tmkr_DIA1_CLKA_posedge, + TestSignal => DIA_ipd(1), + TestSignalName => "DIA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(1), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(1), + HoldLow => thold_DIA_CLKA_posedge_posedge(1), + HoldHigh => thold_DIA_CLKA_negedge_posedge(1), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA2_CLKA_posedge, + TimingData => Tmkr_DIA2_CLKA_posedge, + TestSignal => DIA_ipd(2), + TestSignalName => "DIA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(2), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(2), + HoldLow => thold_DIA_CLKA_posedge_posedge(2), + HoldHigh => thold_DIA_CLKA_negedge_posedge(2), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTB_CLKB_posedge, + TimingData => Tmkr_RSTB_CLKB_posedge, + TestSignal => RSTB_ipd, + TestSignalName => "RSTB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTB_CLKB_posedge_posedge, + SetupLow => tsetup_RSTB_CLKB_negedge_posedge, + HoldLow => thold_RSTB_CLKB_posedge_posedge, + HoldHigh => thold_RSTB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB8_CLKB_posedge, + TimingData => Tmkr_ADDRB8_CLKB_posedge, + TestSignal => ADDRB_ipd(8), + TestSignalName => "ADDRB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(8), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(8), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(8), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(8), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S4_S4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_DIA2_CLKA_posedge or + Tviol_DIA3_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_RSTA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_ADDRB9_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_RSTB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalSetupHoldCheck ( + Violation => Tviol_CLKB_CLKA_posedge, + TimingData => Tmkr_CLKB_CLKA_posedge, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_CLKA_CLKB_posedge, + TimingData => Tmkr_CLKA_CLKB_posedge, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S4", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + + ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge; + + if (ENA_ipd_sampled = '1') then + if (rising_edge(CLKA_ipd)) then + if (WEA_ipd_sampled = '1') then + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (WEB_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S4_S4", + InstanceName => ramb4_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOA_zd := (others => 'X'); + + if (RSTB_ipd_sampled = '0' ) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (RSTB_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S4_S4", + InstanceName => ramb4_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S4_S4", + InstanceName => ramb4_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (RSTA_ipd_sampled = '1') then + DOA_zd := (others => '0'); + end if; + end if; + end if; + + if (ENB_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (WEB_ipd_sampled = '1') then + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + DOB_zd := DIB_ipd; + + if (ViolationCLKAB = 'X') then + if (WEA_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S4_S4", + InstanceName => ramb4_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (RSTA_ipd_sampled = '0' ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if (RSTA_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S4_S4", + InstanceName => ramb4_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S4_S4", + InstanceName => ramb4_s4_s4'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (RSTB_ipd_sampled = '1') then + DOB_zd := (others => '0'); + end if; + end if; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + DOA_zd(1) := ViolationA xor DOA_zd(1); + DOA_zd(2) := ViolationA xor DOA_zd(2); + DOA_zd(3) := ViolationA xor DOA_zd(3); + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(2), + GlitchData => DOA_GlitchData2, + OutSignalName => "DOA(2)", + OutTemp => DOA_zd(2), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(3), + GlitchData => DOA_GlitchData3, + OutSignalName => "DOA(3)", + OutTemp => DOA_zd(3), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB4_S4_S4_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Dual Port Block RAM +-- /___/ /\ Filename : RAMB4_S4_S8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +----- CELL ramb4_s4_s8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S4_S8 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(9 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := ( 0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(8 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := ( 0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(3 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(9 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(3 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL" + + ); + + port( + DOA : out std_logic_vector(3 downto 0); + DOB : out std_logic_vector(7 downto 0); + + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(3 downto 0); + DIB : in std_logic_vector(7 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB4_S4_S8 : entity is true; +end ramb4_s4_s8; + +architecture RAMB4_S4_S8_V of RAMB4_S4_S8 is + attribute VITAL_LEVEL0 of + RAMB4_S4_S8_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(9 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(3 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal RSTA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(8 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(7 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal RSTB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant length_a : integer := 1024; + constant length_b : integer := 512; + constant width_a : integer := 4; + constant width_b : integer := 8; + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width_b - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 9 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 3 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 8 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 7 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA9_CLKA_posedge : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_RSTA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_RSTB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA9_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + variable DOA_GlitchData2 : VitalGlitchDataType; + variable DOA_GlitchData3 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOA_zd : std_logic_vector(3 downto 0) := (others => 'X'); + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOB_zd : std_logic_vector(7 downto 0) := (others => 'X'); + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + + variable ADDRA_ipd_sampled : std_logic_vector(9 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable RSTA_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + + variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X'); + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable RSTB_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + + variable collision_type : integer := 3; + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB4_S4_S8", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + DOA <= DOA_zd; + DOB <= DOB_zd; + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + RSTA_ipd_sampled := RSTA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + RSTB_ipd_sampled := RSTB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTA_CLKA_posedge, + TimingData => Tmkr_RSTA_CLKA_posedge, + TestSignal => RSTA_ipd, + TestSignalName => "RSTA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTA_CLKA_posedge_posedge, + SetupLow => tsetup_RSTA_CLKA_negedge_posedge, + HoldLow => thold_RSTA_CLKA_posedge_posedge, + HoldHigh => thold_RSTA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA8_CLKA_posedge, + TimingData => Tmkr_ADDRA8_CLKA_posedge, + TestSignal => ADDRA_ipd(8), + TestSignalName => "ADDRA(8)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(8), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(8), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(8), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(8), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA1_CLKA_posedge, + TimingData => Tmkr_DIA1_CLKA_posedge, + TestSignal => DIA_ipd(1), + TestSignalName => "DIA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(1), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(1), + HoldLow => thold_DIA_CLKA_posedge_posedge(1), + HoldHigh => thold_DIA_CLKA_negedge_posedge(1), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA2_CLKA_posedge, + TimingData => Tmkr_DIA2_CLKA_posedge, + TestSignal => DIA_ipd(2), + TestSignalName => "DIA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(2), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(2), + HoldLow => thold_DIA_CLKA_posedge_posedge(2), + HoldHigh => thold_DIA_CLKA_negedge_posedge(2), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTB_CLKB_posedge, + TimingData => Tmkr_RSTB_CLKB_posedge, + TestSignal => RSTB_ipd, + TestSignalName => "RSTB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTB_CLKB_posedge_posedge, + SetupLow => tsetup_RSTB_CLKB_negedge_posedge, + HoldLow => thold_RSTB_CLKB_posedge_posedge, + HoldHigh => thold_RSTB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S4_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_ADDRA9_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_DIA2_CLKA_posedge or + Tviol_DIA3_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_RSTA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_RSTB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalSetupHoldCheck ( + Violation => Tviol_CLKB_CLKA_posedge, + TimingData => Tmkr_CLKB_CLKA_posedge, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_CLKA_CLKB_posedge, + TimingData => Tmkr_CLKA_CLKB_posedge, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S4_S8", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + + ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge; + + if (ENA_ipd_sampled = '1') then + if (rising_edge(CLKA_ipd)) then + if (WEA_ipd_sampled = '1') then + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (WEB_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S4_S8", + InstanceName => ramb4_s4_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOA_zd := (others => 'X'); + + if (RSTB_ipd_sampled = '0' ) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (RSTB_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S4_S8", + InstanceName => ramb4_s4_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S4_S8", + InstanceName => ramb4_s4_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (RSTA_ipd_sampled = '1') then + DOA_zd := (others => '0'); + end if; + end if; + end if; + + if (ENB_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (WEB_ipd_sampled = '1') then + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + DOB_zd := DIB_ipd; + + if (ViolationCLKAB = 'X') then + if (WEA_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S4_S8", + InstanceName => ramb4_s4_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (RSTA_ipd_sampled = '0' ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if (RSTA_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S4_S8", + InstanceName => ramb4_s4_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S4_S8", + InstanceName => ramb4_s4_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (RSTB_ipd_sampled = '1') then + DOB_zd := (others => '0'); + end if; + end if; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + DOA_zd(1) := ViolationA xor DOA_zd(1); + DOA_zd(2) := ViolationA xor DOA_zd(2); + DOA_zd(3) := ViolationA xor DOA_zd(3); + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(2), + GlitchData => DOA_GlitchData2, + OutSignalName => "DOA(2)", + OutTemp => DOA_zd(2), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(3), + GlitchData => DOA_GlitchData3, + OutSignalName => "DOA(3)", + OutTemp => DOA_zd(3), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB4_S4_S8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/ramb4_s8.vhd,v 1.5 2004/08/31 13:40:21 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Single Port Block RAM +-- /___/ /\ Filename : RAMB4_S8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAMB4_S8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S8 is + + generic ( + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + + port ( + DO : out STD_LOGIC_VECTOR (7 downto 0); + + ADDR : in STD_LOGIC_VECTOR (8 downto 0); + CLK : in STD_ULOGIC; + DI : in STD_LOGIC_VECTOR (7 downto 0); + EN : in STD_ULOGIC; + RST : in STD_ULOGIC; + WE : in STD_ULOGIC + ); +end RAMB4_S8; + +architecture RAMB4_S8_V of RAMB4_S8 is + constant length : integer := 512; + constant width : integer := 8; + type Two_D_array_type is array ((length - 1) downto 0) of std_logic_vector((width - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width) + (width - 1)) downto (i* width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + + VITALBehavior : process + + variable address : integer; + variable valid_addr : boolean := FALSE; + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + begin + valid_addr := addr_is_valid(addr); + + if (valid_addr) then + address := slv_to_int(addr); + end if; + + if (rising_edge(CLK)) then + if (EN = '1') then + if (RST = '1') then + DO <= (others => '0') after 100 ps; + else + if (WE = '1') then + DO <= DI after 100 ps; + else + if (valid_addr) then + DO <= mem(address) after 100 ps; + end if; + end if; + end if; + if (WE = '1') then + if (valid_addr) then + mem(address) := DI; + end if; + end if; + end if; + end if; + wait on CLK; + end process VITALBehavior; +end RAMB4_S8_V; + + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Dual Port Block RAM +-- /___/ /\ Filename : RAMB4_S8_S16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +----- CELL ramb4_s8_s16 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S8_S16 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(8 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := ( 0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := ( 0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(15 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(15 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL" + + ); + + port( + DOA : out std_logic_vector(7 downto 0); + DOB : out std_logic_vector(15 downto 0); + + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(7 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(7 downto 0); + DIB : in std_logic_vector(15 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB4_S8_S16 : entity is true; +end ramb4_s8_s16; + +architecture RAMB4_S8_S16_V of RAMB4_S8_S16 is + attribute VITAL_LEVEL0 of + RAMB4_S8_S16_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(8 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(7 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal RSTA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(7 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(15 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal RSTB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant length_a : integer := 512; + constant length_b : integer := 256; + constant width_a : integer := 8; + constant width_b : integer := 16; + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width_b - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 8 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 7 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 7 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 15 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_RSTA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB9_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB10_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB11_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB12_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB13_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB14_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB15_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_RSTB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB9_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB10_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB11_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB12_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB13_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB14_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB15_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + variable DOA_GlitchData2 : VitalGlitchDataType; + variable DOA_GlitchData3 : VitalGlitchDataType; + variable DOA_GlitchData4 : VitalGlitchDataType; + variable DOA_GlitchData5 : VitalGlitchDataType; + variable DOA_GlitchData6 : VitalGlitchDataType; + variable DOA_GlitchData7 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + variable DOB_GlitchData8 : VitalGlitchDataType; + variable DOB_GlitchData9 : VitalGlitchDataType; + variable DOB_GlitchData10 : VitalGlitchDataType; + variable DOB_GlitchData11 : VitalGlitchDataType; + variable DOB_GlitchData12 : VitalGlitchDataType; + variable DOB_GlitchData13 : VitalGlitchDataType; + variable DOB_GlitchData14 : VitalGlitchDataType; + variable DOB_GlitchData15 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOA_zd : std_logic_vector(7 downto 0) := (others => 'X'); + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOB_zd : std_logic_vector(15 downto 0) := (others => 'X'); + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + + variable ADDRA_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable RSTA_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + + variable ADDRB_ipd_sampled : std_logic_vector(7 downto 0) := (others => 'X'); + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable RSTB_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + + variable collision_type : integer := 3; + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB4_S8_S16", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + DOA <= DOA_zd; + DOB <= DOB_zd; + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + RSTA_ipd_sampled := RSTA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + RSTB_ipd_sampled := RSTB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTA_CLKA_posedge, + TimingData => Tmkr_RSTA_CLKA_posedge, + TestSignal => RSTA_ipd, + TestSignalName => "RSTA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTA_CLKA_posedge_posedge, + SetupLow => tsetup_RSTA_CLKA_negedge_posedge, + HoldLow => thold_RSTA_CLKA_posedge_posedge, + HoldHigh => thold_RSTA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA1_CLKA_posedge, + TimingData => Tmkr_DIA1_CLKA_posedge, + TestSignal => DIA_ipd(1), + TestSignalName => "DIA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(1), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(1), + HoldLow => thold_DIA_CLKA_posedge_posedge(1), + HoldHigh => thold_DIA_CLKA_negedge_posedge(1), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA2_CLKA_posedge, + TimingData => Tmkr_DIA2_CLKA_posedge, + TestSignal => DIA_ipd(2), + TestSignalName => "DIA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(2), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(2), + HoldLow => thold_DIA_CLKA_posedge_posedge(2), + HoldHigh => thold_DIA_CLKA_negedge_posedge(2), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA3_CLKA_posedge, + TimingData => Tmkr_DIA3_CLKA_posedge, + TestSignal => DIA_ipd(3), + TestSignalName => "DIA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(3), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(3), + HoldLow => thold_DIA_CLKA_posedge_posedge(3), + HoldHigh => thold_DIA_CLKA_negedge_posedge(3), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA4_CLKA_posedge, + TimingData => Tmkr_DIA4_CLKA_posedge, + TestSignal => DIA_ipd(4), + TestSignalName => "DIA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(4), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(4), + HoldLow => thold_DIA_CLKA_posedge_posedge(4), + HoldHigh => thold_DIA_CLKA_negedge_posedge(4), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA5_CLKA_posedge, + TimingData => Tmkr_DIA5_CLKA_posedge, + TestSignal => DIA_ipd(5), + TestSignalName => "DIA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(5), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(5), + HoldLow => thold_DIA_CLKA_posedge_posedge(5), + HoldHigh => thold_DIA_CLKA_negedge_posedge(5), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA6_CLKA_posedge, + TimingData => Tmkr_DIA6_CLKA_posedge, + TestSignal => DIA_ipd(6), + TestSignalName => "DIA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(6), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(6), + HoldLow => thold_DIA_CLKA_posedge_posedge(6), + HoldHigh => thold_DIA_CLKA_negedge_posedge(6), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTB_CLKB_posedge, + TimingData => Tmkr_RSTB_CLKB_posedge, + TestSignal => RSTB_ipd, + TestSignalName => "RSTB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTB_CLKB_posedge_posedge, + SetupLow => tsetup_RSTB_CLKB_negedge_posedge, + HoldLow => thold_RSTB_CLKB_posedge_posedge, + HoldHigh => thold_RSTB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB7_CLKB_posedge, + TimingData => Tmkr_DIB7_CLKB_posedge, + TestSignal => DIB_ipd(7), + TestSignalName => "DIB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(7), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(7), + HoldLow => thold_DIB_CLKB_posedge_posedge(7), + HoldHigh => thold_DIB_CLKB_negedge_posedge(7), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB8_CLKB_posedge, + TimingData => Tmkr_DIB8_CLKB_posedge, + TestSignal => DIB_ipd(8), + TestSignalName => "DIB(8)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(8), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(8), + HoldLow => thold_DIB_CLKB_posedge_posedge(8), + HoldHigh => thold_DIB_CLKB_negedge_posedge(8), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB9_CLKB_posedge, + TimingData => Tmkr_DIB9_CLKB_posedge, + TestSignal => DIB_ipd(9), + TestSignalName => "DIB(9)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(9), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(9), + HoldLow => thold_DIB_CLKB_posedge_posedge(9), + HoldHigh => thold_DIB_CLKB_negedge_posedge(9), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB10_CLKB_posedge, + TimingData => Tmkr_DIB10_CLKB_posedge, + TestSignal => DIB_ipd(10), + TestSignalName => "DIB(10)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(10), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(10), + HoldLow => thold_DIB_CLKB_posedge_posedge(10), + HoldHigh => thold_DIB_CLKB_negedge_posedge(10), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB11_CLKB_posedge, + TimingData => Tmkr_DIB11_CLKB_posedge, + TestSignal => DIB_ipd(11), + TestSignalName => "DIB(11)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(11), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(11), + HoldLow => thold_DIB_CLKB_posedge_posedge(11), + HoldHigh => thold_DIB_CLKB_negedge_posedge(11), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB12_CLKB_posedge, + TimingData => Tmkr_DIB12_CLKB_posedge, + TestSignal => DIB_ipd(12), + TestSignalName => "DIB(12)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(12), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(12), + HoldLow => thold_DIB_CLKB_posedge_posedge(12), + HoldHigh => thold_DIB_CLKB_negedge_posedge(12), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB13_CLKB_posedge, + TimingData => Tmkr_DIB13_CLKB_posedge, + TestSignal => DIB_ipd(13), + TestSignalName => "DIB(13)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(13), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(13), + HoldLow => thold_DIB_CLKB_posedge_posedge(13), + HoldHigh => thold_DIB_CLKB_negedge_posedge(13), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB14_CLKB_posedge, + TimingData => Tmkr_DIB14_CLKB_posedge, + TestSignal => DIB_ipd(14), + TestSignalName => "DIB(14)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(14), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(14), + HoldLow => thold_DIB_CLKB_posedge_posedge(14), + HoldHigh => thold_DIB_CLKB_negedge_posedge(14), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S8_S16", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_DIA2_CLKA_posedge or + Tviol_DIA3_CLKA_posedge or + Tviol_DIA4_CLKA_posedge or + Tviol_DIA5_CLKA_posedge or + Tviol_DIA6_CLKA_posedge or + Tviol_DIA7_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_RSTA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_DIB8_CLKB_posedge or + Tviol_DIB9_CLKB_posedge or + Tviol_DIB10_CLKB_posedge or + Tviol_DIB11_CLKB_posedge or + Tviol_DIB12_CLKB_posedge or + Tviol_DIB13_CLKB_posedge or + Tviol_DIB14_CLKB_posedge or + Tviol_DIB15_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_RSTB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalSetupHoldCheck ( + Violation => Tviol_CLKB_CLKA_posedge, + TimingData => Tmkr_CLKB_CLKA_posedge, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_CLKA_CLKB_posedge, + TimingData => Tmkr_CLKA_CLKB_posedge, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S16", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + + ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge; + + if (ENA_ipd_sampled = '1') then + if (rising_edge(CLKA_ipd)) then + if (WEA_ipd_sampled = '1') then + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (WEB_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S8_S16", + InstanceName => ramb4_s8_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOA_zd := (others => 'X'); + + if (RSTB_ipd_sampled = '0' ) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (RSTB_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S8_S16", + InstanceName => ramb4_s8_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S8_S16", + InstanceName => ramb4_s8_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (RSTA_ipd_sampled = '1') then + DOA_zd := (others => '0'); + end if; + end if; + end if; + + if (ENB_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (WEB_ipd_sampled = '1') then + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + DOB_zd := DIB_ipd; + + if (ViolationCLKAB = 'X') then + if (WEA_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S8_S16", + InstanceName => ramb4_s8_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (RSTA_ipd_sampled = '0' ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if (RSTA_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S8_S16", + InstanceName => ramb4_s8_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S8_S16", + InstanceName => ramb4_s8_s16'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (RSTB_ipd_sampled = '1') then + DOB_zd := (others => '0'); + end if; + end if; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + DOA_zd(1) := ViolationA xor DOA_zd(1); + DOA_zd(2) := ViolationA xor DOA_zd(2); + DOA_zd(3) := ViolationA xor DOA_zd(3); + DOA_zd(4) := ViolationA xor DOA_zd(4); + DOA_zd(5) := ViolationA xor DOA_zd(5); + DOA_zd(6) := ViolationA xor DOA_zd(6); + DOA_zd(7) := ViolationA xor DOA_zd(7); + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + DOB_zd(8) := ViolationB xor DOB_zd(8); + DOB_zd(9) := ViolationB xor DOB_zd(9); + DOB_zd(10) := ViolationB xor DOB_zd(10); + DOB_zd(11) := ViolationB xor DOB_zd(11); + DOB_zd(12) := ViolationB xor DOB_zd(12); + DOB_zd(13) := ViolationB xor DOB_zd(13); + DOB_zd(14) := ViolationB xor DOB_zd(14); + DOB_zd(15) := ViolationB xor DOB_zd(15); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(2), + GlitchData => DOA_GlitchData2, + OutSignalName => "DOA(2)", + OutTemp => DOA_zd(2), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(3), + GlitchData => DOA_GlitchData3, + OutSignalName => "DOA(3)", + OutTemp => DOA_zd(3), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(4), + GlitchData => DOA_GlitchData4, + OutSignalName => "DOA(4)", + OutTemp => DOA_zd(4), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(5), + GlitchData => DOA_GlitchData5, + OutSignalName => "DOA(5)", + OutTemp => DOA_zd(5), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(6), + GlitchData => DOA_GlitchData6, + OutSignalName => "DOA(6)", + OutTemp => DOA_zd(6), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(7), + GlitchData => DOA_GlitchData7, + OutSignalName => "DOA(7)", + OutTemp => DOA_zd(7), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(8), + GlitchData => DOB_GlitchData8, + OutSignalName => "DOB(8)", + OutTemp => DOB_zd(8), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(8), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(9), + GlitchData => DOB_GlitchData9, + OutSignalName => "DOB(9)", + OutTemp => DOB_zd(9), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(9), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(10), + GlitchData => DOB_GlitchData10, + OutSignalName => "DOB(10)", + OutTemp => DOB_zd(10), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(10), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(11), + GlitchData => DOB_GlitchData11, + OutSignalName => "DOB(11)", + OutTemp => DOB_zd(11), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(11), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(12), + GlitchData => DOB_GlitchData12, + OutSignalName => "DOB(12)", + OutTemp => DOB_zd(12), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(12), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(13), + GlitchData => DOB_GlitchData13, + OutSignalName => "DOB(13)", + OutTemp => DOB_zd(13), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(13), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(14), + GlitchData => DOB_GlitchData14, + OutSignalName => "DOB(14)", + OutTemp => DOB_zd(14), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(14), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(15), + GlitchData => DOB_GlitchData15, + OutSignalName => "DOB(15)", + OutTemp => DOB_zd(15), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(15), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB4_S8_S16_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4K-Bit Data Dual Port Block RAM +-- /___/ /\ Filename : RAMB4_S8_S8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +----- CELL ramb4_s8_s8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAMB4_S8_S8 is + generic ( + TimingChecksOn : boolean := false; + Xon : boolean := false; + MsgOn : boolean := false; + + tipd_ADDRA : VitalDelayArrayType01(8 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIA : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTA : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEA : VitalDelayType01 := ( 0 ps, 0 ps); + + tipd_ADDRB : VitalDelayArrayType01(8 downto 0) := (others => (0 ps, 0 ps)); + tipd_CLKB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_DIB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps)); + tipd_ENB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_RSTB : VitalDelayType01 := ( 0 ps, 0 ps); + tipd_WEB : VitalDelayType01 := ( 0 ps, 0 ps); + + tpd_CLKA_DOA : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps)); + tpd_CLKB_DOB : VitalDelayArrayType01(7 downto 0) := (others => (100 ps, 100 ps)); + + tsetup_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIA_CLKA_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + tsetup_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_DIB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + tsetup_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + tsetup_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRA_CLKA_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_ADDRA_CLKA_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_DIA_CLKA_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIA_CLKA_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_ENA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_ENA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_negedge_posedge : VitalDelayType := 0 ps; + thold_WEA_CLKA_posedge_posedge : VitalDelayType := 0 ps; + + thold_ADDRB_CLKB_negedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_ADDRB_CLKB_posedge_posedge : VitalDelayArrayType(8 downto 0) := (others => 0 ps); + thold_DIB_CLKB_negedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_DIB_CLKB_posedge_posedge : VitalDelayArrayType(7 downto 0) := (others => 0 ps); + thold_ENB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_ENB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_RSTB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_negedge_posedge : VitalDelayType := 0 ps; + thold_WEB_CLKB_posedge_posedge : VitalDelayType := 0 ps; + + tpw_CLKA_negedge : VitalDelayType := 0 ps; + tpw_CLKA_posedge : VitalDelayType := 0 ps; + tpw_CLKB_negedge : VitalDelayType := 0 ps; + tpw_CLKB_posedge : VitalDelayType := 0 ps; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL" + + ); + + port( + DOA : out std_logic_vector(7 downto 0); + DOB : out std_logic_vector(7 downto 0); + + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(7 downto 0); + DIB : in std_logic_vector(7 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_ulogic; + WEB : in std_ulogic + ); + + attribute VITAL_LEVEL0 of + RAMB4_S8_S8 : entity is true; +end ramb4_s8_s8; + +architecture RAMB4_S8_S8_V of RAMB4_S8_S8 is + attribute VITAL_LEVEL0 of + RAMB4_S8_S8_V : architecture is true; + + signal ADDRA_ipd : std_logic_vector(8 downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(7 downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal RSTA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_ulogic := 'X'; + + signal ADDRB_ipd : std_logic_vector(8 downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(7 downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal RSTB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_ulogic := 'X'; + + constant SETUP_ALL : VitalDelayType := 1000 ps; + constant length_a : integer := 512; + constant length_b : integer := 512; + constant width_a : integer := 8; + constant width_b : integer := 8; + type Two_D_array_type is array ((length_b - 1) downto 0) of std_logic_vector((width_b - 1) downto 0); + + function slv_to_two_D_array( + SLV : in std_logic_vector) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((width_b - 1) downto 0); + begin + for i in two_D_array'low to two_D_array'high loop + intermediate := SLV(((i*width_b) + (width_b - 1)) downto (i* width_b)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; +begin + WireDelay : block + begin + ADDRA_DELAY : for i in 8 downto 0 generate + VitalWireDelay (ADDRA_ipd(i), ADDRA(i), tipd_ADDRA(i)); + end generate ADDRA_DELAY; + VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); + DIA_DELAY : for i in 7 downto 0 generate + VitalWireDelay (DIA_ipd(i), DIA(i), tipd_DIA(i)); + end generate DIA_DELAY; + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + VitalWireDelay (RSTA_ipd, RSTA, tipd_RSTA); + VitalWireDelay (WEA_ipd, WEA, tipd_WEA); + + ADDRB_DELAY : for i in 8 downto 0 generate + VitalWireDelay (ADDRB_ipd(i), ADDRB(i), tipd_ADDRB(i)); + end generate ADDRB_DELAY; + VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); + DIB_DELAY : for i in 7 downto 0 generate + VitalWireDelay (DIB_ipd(i), DIB(i), tipd_DIB(i)); + end generate DIB_DELAY; + VitalWireDelay (ENB_ipd, ENB, tipd_ENB); + VitalWireDelay (RSTB_ipd, RSTB, tipd_RSTB); + VitalWireDelay (WEB_ipd, WEB, tipd_WEB); + end block; + + VITALBehavior : process + variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ADDRA8_CLKA_posedge : std_ulogic := '0'; + variable Tviol_CLKB_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA0_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA1_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA2_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA3_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA4_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA5_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA6_CLKA_posedge : std_ulogic := '0'; + variable Tviol_DIA7_CLKA_posedge : std_ulogic := '0'; + variable Tviol_ENA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_RSTA_CLKA_posedge : std_ulogic := '0'; + variable Tviol_WEA_CLKA_posedge : std_ulogic := '0'; + + variable Tviol_ADDRB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ADDRB8_CLKB_posedge : std_ulogic := '0'; + variable Tviol_CLKA_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB0_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB1_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB2_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB3_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB4_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB5_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB6_CLKB_posedge : std_ulogic := '0'; + variable Tviol_DIB7_CLKB_posedge : std_ulogic := '0'; + variable Tviol_ENB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_RSTB_CLKB_posedge : std_ulogic := '0'; + variable Tviol_WEB_CLKB_posedge : std_ulogic := '0'; + + variable PViol_CLKA : std_ulogic := '0'; + variable PViol_CLKB : std_ulogic := '0'; + + variable Tmkr_ADDRA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRA8_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKB_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA0_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA1_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA2_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA3_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA4_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA5_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA6_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIA7_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEA_CLKA_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable Tmkr_ADDRB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ADDRB8_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_CLKA_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB0_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB1_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB2_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB3_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB4_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB5_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB6_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_DIB7_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_ENB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_RSTB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tmkr_WEB_CLKB_posedge : VitalTimingDataType := VitalTimingDataInit; + + variable PInfo_CLKA : VitalPeriodDataType := VitalPeriodDataInit; + variable PInfo_CLKB : VitalPeriodDataType := VitalPeriodDataInit; + + variable DOA_GlitchData0 : VitalGlitchDataType; + variable DOA_GlitchData1 : VitalGlitchDataType; + variable DOA_GlitchData2 : VitalGlitchDataType; + variable DOA_GlitchData3 : VitalGlitchDataType; + variable DOA_GlitchData4 : VitalGlitchDataType; + variable DOA_GlitchData5 : VitalGlitchDataType; + variable DOA_GlitchData6 : VitalGlitchDataType; + variable DOA_GlitchData7 : VitalGlitchDataType; + + variable DOB_GlitchData0 : VitalGlitchDataType; + variable DOB_GlitchData1 : VitalGlitchDataType; + variable DOB_GlitchData2 : VitalGlitchDataType; + variable DOB_GlitchData3 : VitalGlitchDataType; + variable DOB_GlitchData4 : VitalGlitchDataType; + variable DOB_GlitchData5 : VitalGlitchDataType; + variable DOB_GlitchData6 : VitalGlitchDataType; + variable DOB_GlitchData7 : VitalGlitchDataType; + + variable mem_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INIT_0F & INIT_0E & INIT_0D & INIT_0C & + INIT_0B & INIT_0A & INIT_09 & INIT_08 & + INIT_07 & INIT_06 & INIT_05 & INIT_04 & + INIT_03 & INIT_02 & INIT_01 & INIT_00); + variable mem : Two_D_array_type := slv_to_two_D_array(mem_slv); + + + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOA_zd : std_logic_vector(7 downto 0) := (others => 'X'); + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOB_zd : std_logic_vector(7 downto 0) := (others => 'X'); + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable VALID_ADDRA : boolean := false; + variable VALID_ADDRB : boolean := false; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + + variable ADDRA_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X'); + variable ENA_ipd_sampled : std_ulogic := 'X'; + variable RSTA_ipd_sampled : std_ulogic := 'X'; + variable WEA_ipd_sampled : std_ulogic := 'X'; + + variable ADDRB_ipd_sampled : std_logic_vector(8 downto 0) := (others => 'X'); + variable ENB_ipd_sampled : std_ulogic := 'X'; + variable RSTB_ipd_sampled : std_ulogic := 'X'; + variable WEB_ipd_sampled : std_ulogic := 'X'; + + variable collision_type : integer := 3; + begin + if (FIRST_TIME) then + if ((SIM_COLLISION_CHECK = "none") or (SIM_COLLISION_CHECK = "NONE")) then + collision_type := 0; + elsif ((SIM_COLLISION_CHECK = "warning_only") or (SIM_COLLISION_CHECK = "WARNING_ONLY")) then + collision_type := 1; + elsif ((SIM_COLLISION_CHECK = "generate_x_only") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY")) then + collision_type := 2; + elsif ((SIM_COLLISION_CHECK = "all") or (SIM_COLLISION_CHECK = "ALL")) then + collision_type := 3; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "RAMB4_S8_S8", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + DOA <= DOA_zd; + DOB <= DOB_zd; + FIRST_TIME := false; + end if; + + if (CLKA_ipd'event) then + ENA_ipd_sampled := ENA_ipd; + RSTA_ipd_sampled := RSTA_ipd; + WEA_ipd_sampled := WEA_ipd; + ADDRA_ipd_sampled := ADDRA_ipd; + end if; + + if (CLKB_ipd'event) then + ENB_ipd_sampled := ENB_ipd; + RSTB_ipd_sampled := RSTB_ipd; + WEB_ipd_sampled := WEB_ipd; + ADDRB_ipd_sampled := ADDRB_ipd; + end if; + + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLKA_posedge, + TimingData => Tmkr_ENA_CLKA_posedge, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ENA_CLKA_posedge_posedge, + SetupLow => tsetup_ENA_CLKA_negedge_posedge, + HoldLow => thold_ENA_CLKA_posedge_posedge, + HoldHigh => thold_ENA_CLKA_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTA_CLKA_posedge, + TimingData => Tmkr_RSTA_CLKA_posedge, + TestSignal => RSTA_ipd, + TestSignalName => "RSTA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTA_CLKA_posedge_posedge, + SetupLow => tsetup_RSTA_CLKA_negedge_posedge, + HoldLow => thold_RSTA_CLKA_posedge_posedge, + HoldHigh => thold_RSTA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEA_CLKA_posedge, + TimingData => Tmkr_WEA_CLKA_posedge, + TestSignal => WEA_ipd, + TestSignalName => "WEA", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_WEA_CLKA_posedge_posedge, + SetupLow => tsetup_WEA_CLKA_negedge_posedge, + HoldLow => thold_WEA_CLKA_posedge_posedge, + HoldHigh => thold_WEA_CLKA_negedge_posedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA0_CLKA_posedge, + TimingData => Tmkr_ADDRA0_CLKA_posedge, + TestSignal => ADDRA_ipd(0), + TestSignalName => "ADDRA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(0), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(0), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(0), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(0), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA1_CLKA_posedge, + TimingData => Tmkr_ADDRA1_CLKA_posedge, + TestSignal => ADDRA_ipd(1), + TestSignalName => "ADDRA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(1), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(1), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(1), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(1), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA2_CLKA_posedge, + TimingData => Tmkr_ADDRA2_CLKA_posedge, + TestSignal => ADDRA_ipd(2), + TestSignalName => "ADDRA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(2), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(2), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(2), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(2), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA3_CLKA_posedge, + TimingData => Tmkr_ADDRA3_CLKA_posedge, + TestSignal => ADDRA_ipd(3), + TestSignalName => "ADDRA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(3), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(3), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(3), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(3), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA4_CLKA_posedge, + TimingData => Tmkr_ADDRA4_CLKA_posedge, + TestSignal => ADDRA_ipd(4), + TestSignalName => "ADDRA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(4), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(4), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(4), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(4), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA5_CLKA_posedge, + TimingData => Tmkr_ADDRA5_CLKA_posedge, + TestSignal => ADDRA_ipd(5), + TestSignalName => "ADDRA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(5), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(5), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(5), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(5), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA6_CLKA_posedge, + TimingData => Tmkr_ADDRA6_CLKA_posedge, + TestSignal => ADDRA_ipd(6), + TestSignalName => "ADDRA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(6), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(6), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(6), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(6), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRA7_CLKA_posedge, + TimingData => Tmkr_ADDRA7_CLKA_posedge, + TestSignal => ADDRA_ipd(7), + TestSignalName => "ADDRA(7)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRA_CLKA_posedge_posedge(7), + SetupLow => tsetup_ADDRA_CLKA_negedge_posedge(7), + HoldLow => thold_ADDRA_CLKA_posedge_posedge(7), + HoldHigh => thold_ADDRA_CLKA_negedge_posedge(7), + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA0_CLKA_posedge, + TimingData => Tmkr_DIA0_CLKA_posedge, + TestSignal => DIA_ipd(0), + TestSignalName => "DIA(0)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(0), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(0), + HoldLow => thold_DIA_CLKA_posedge_posedge(0), + HoldHigh => thold_DIA_CLKA_negedge_posedge(0), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA1_CLKA_posedge, + TimingData => Tmkr_DIA1_CLKA_posedge, + TestSignal => DIA_ipd(1), + TestSignalName => "DIA(1)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(1), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(1), + HoldLow => thold_DIA_CLKA_posedge_posedge(1), + HoldHigh => thold_DIA_CLKA_negedge_posedge(1), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA2_CLKA_posedge, + TimingData => Tmkr_DIA2_CLKA_posedge, + TestSignal => DIA_ipd(2), + TestSignalName => "DIA(2)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(2), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(2), + HoldLow => thold_DIA_CLKA_posedge_posedge(2), + HoldHigh => thold_DIA_CLKA_negedge_posedge(2), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA3_CLKA_posedge, + TimingData => Tmkr_DIA3_CLKA_posedge, + TestSignal => DIA_ipd(3), + TestSignalName => "DIA(3)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(3), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(3), + HoldLow => thold_DIA_CLKA_posedge_posedge(3), + HoldHigh => thold_DIA_CLKA_negedge_posedge(3), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA4_CLKA_posedge, + TimingData => Tmkr_DIA4_CLKA_posedge, + TestSignal => DIA_ipd(4), + TestSignalName => "DIA(4)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(4), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(4), + HoldLow => thold_DIA_CLKA_posedge_posedge(4), + HoldHigh => thold_DIA_CLKA_negedge_posedge(4), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA5_CLKA_posedge, + TimingData => Tmkr_DIA5_CLKA_posedge, + TestSignal => DIA_ipd(5), + TestSignalName => "DIA(5)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(5), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(5), + HoldLow => thold_DIA_CLKA_posedge_posedge(5), + HoldHigh => thold_DIA_CLKA_negedge_posedge(5), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIA6_CLKA_posedge, + TimingData => Tmkr_DIA6_CLKA_posedge, + TestSignal => DIA_ipd(6), + TestSignalName => "DIA(6)", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => tsetup_DIA_CLKA_posedge_posedge(6), + SetupLow => tsetup_DIA_CLKA_negedge_posedge(6), + HoldLow => thold_DIA_CLKA_posedge_posedge(6), + HoldHigh => thold_DIA_CLKA_negedge_posedge(6), + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(WEA_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ENB_CLKB_posedge, + TimingData => Tmkr_ENB_CLKB_posedge, + TestSignal => ENB_ipd, + TestSignalName => "ENB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ENB_CLKB_posedge_posedge, + SetupLow => tsetup_ENB_CLKB_negedge_posedge, + HoldLow => thold_ENB_CLKB_posedge_posedge, + HoldHigh => thold_ENB_CLKB_negedge_posedge, + CheckEnabled => true, + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_RSTB_CLKB_posedge, + TimingData => Tmkr_RSTB_CLKB_posedge, + TestSignal => RSTB_ipd, + TestSignalName => "RSTB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_RSTB_CLKB_posedge_posedge, + SetupLow => tsetup_RSTB_CLKB_negedge_posedge, + HoldLow => thold_RSTB_CLKB_posedge_posedge, + HoldHigh => thold_RSTB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_WEB_CLKB_posedge, + TimingData => Tmkr_WEB_CLKB_posedge, + TestSignal => WEB_ipd, + TestSignalName => "WEB", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_WEB_CLKB_posedge_posedge, + SetupLow => tsetup_WEB_CLKB_negedge_posedge, + HoldLow => thold_WEB_CLKB_posedge_posedge, + HoldHigh => thold_WEB_CLKB_negedge_posedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB0_CLKB_posedge, + TimingData => Tmkr_ADDRB0_CLKB_posedge, + TestSignal => ADDRB_ipd(0), + TestSignalName => "ADDRB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(0), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(0), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(0), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(0), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB1_CLKB_posedge, + TimingData => Tmkr_ADDRB1_CLKB_posedge, + TestSignal => ADDRB_ipd(1), + TestSignalName => "ADDRB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(1), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(1), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(1), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(1), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB2_CLKB_posedge, + TimingData => Tmkr_ADDRB2_CLKB_posedge, + TestSignal => ADDRB_ipd(2), + TestSignalName => "ADDRB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(2), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(2), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(2), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(2), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB3_CLKB_posedge, + TimingData => Tmkr_ADDRB3_CLKB_posedge, + TestSignal => ADDRB_ipd(3), + TestSignalName => "ADDRB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(3), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(3), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(3), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(3), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB4_CLKB_posedge, + TimingData => Tmkr_ADDRB4_CLKB_posedge, + TestSignal => ADDRB_ipd(4), + TestSignalName => "ADDRB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(4), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(4), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(4), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(4), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB5_CLKB_posedge, + TimingData => Tmkr_ADDRB5_CLKB_posedge, + TestSignal => ADDRB_ipd(5), + TestSignalName => "ADDRB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(5), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(5), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(5), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(5), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB6_CLKB_posedge, + TimingData => Tmkr_ADDRB6_CLKB_posedge, + TestSignal => ADDRB_ipd(6), + TestSignalName => "ADDRB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(6), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(6), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(6), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(6), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_ADDRB7_CLKB_posedge, + TimingData => Tmkr_ADDRB7_CLKB_posedge, + TestSignal => ADDRB_ipd(7), + TestSignalName => "ADDRB(7)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_ADDRB_CLKB_posedge_posedge(7), + SetupLow => tsetup_ADDRB_CLKB_negedge_posedge(7), + HoldLow => thold_ADDRB_CLKB_posedge_posedge(7), + HoldHigh => thold_ADDRB_CLKB_negedge_posedge(7), + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + RefTransition => 'R', + HeaderMsg => "/${CELL}", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB0_CLKB_posedge, + TimingData => Tmkr_DIB0_CLKB_posedge, + TestSignal => DIB_ipd(0), + TestSignalName => "DIB(0)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(0), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(0), + HoldLow => thold_DIB_CLKB_posedge_posedge(0), + HoldHigh => thold_DIB_CLKB_negedge_posedge(0), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB1_CLKB_posedge, + TimingData => Tmkr_DIB1_CLKB_posedge, + TestSignal => DIB_ipd(1), + TestSignalName => "DIB(1)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(1), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(1), + HoldLow => thold_DIB_CLKB_posedge_posedge(1), + HoldHigh => thold_DIB_CLKB_negedge_posedge(1), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB2_CLKB_posedge, + TimingData => Tmkr_DIB2_CLKB_posedge, + TestSignal => DIB_ipd(2), + TestSignalName => "DIB(2)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(2), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(2), + HoldLow => thold_DIB_CLKB_posedge_posedge(2), + HoldHigh => thold_DIB_CLKB_negedge_posedge(2), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB3_CLKB_posedge, + TimingData => Tmkr_DIB3_CLKB_posedge, + TestSignal => DIB_ipd(3), + TestSignalName => "DIB(3)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(3), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(3), + HoldLow => thold_DIB_CLKB_posedge_posedge(3), + HoldHigh => thold_DIB_CLKB_negedge_posedge(3), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB4_CLKB_posedge, + TimingData => Tmkr_DIB4_CLKB_posedge, + TestSignal => DIB_ipd(4), + TestSignalName => "DIB(4)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(4), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(4), + HoldLow => thold_DIB_CLKB_posedge_posedge(4), + HoldHigh => thold_DIB_CLKB_negedge_posedge(4), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB5_CLKB_posedge, + TimingData => Tmkr_DIB5_CLKB_posedge, + TestSignal => DIB_ipd(5), + TestSignalName => "DIB(5)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(5), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(5), + HoldLow => thold_DIB_CLKB_posedge_posedge(5), + HoldHigh => thold_DIB_CLKB_negedge_posedge(5), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_DIB6_CLKB_posedge, + TimingData => Tmkr_DIB6_CLKB_posedge, + TestSignal => DIB_ipd(6), + TestSignalName => "DIB(6)", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => tsetup_DIB_CLKB_posedge_posedge(6), + SetupLow => tsetup_DIB_CLKB_negedge_posedge(6), + HoldLow => thold_DIB_CLKB_posedge_posedge(6), + HoldHigh => thold_DIB_CLKB_negedge_posedge(6), + CheckEnabled => (TO_X01(ENB_ipd_sampled) = '1' and TO_X01(WEB_ipd_sampled) = '1'), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKA, + PeriodData => PInfo_CLKA, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKA_posedge, + PulseWidthLow => tpw_CLKA_negedge, + CheckEnabled => TO_X01(ENA_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + Violation => Pviol_CLKB, + PeriodData => PInfo_CLKB, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + Period => 0 ps, + PulseWidthHigh => tpw_CLKB_posedge, + PulseWidthLow => tpw_CLKB_negedge, + CheckEnabled => TO_X01(ENB_ipd_sampled) = '1', + HeaderMsg => "/RAMB4_S8_S8", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + + ViolationA := Pviol_CLKA or + Tviol_ADDRA0_CLKA_posedge or + Tviol_ADDRA1_CLKA_posedge or + Tviol_ADDRA2_CLKA_posedge or + Tviol_ADDRA3_CLKA_posedge or + Tviol_ADDRA4_CLKA_posedge or + Tviol_ADDRA5_CLKA_posedge or + Tviol_ADDRA6_CLKA_posedge or + Tviol_ADDRA7_CLKA_posedge or + Tviol_ADDRA8_CLKA_posedge or + Tviol_DIA0_CLKA_posedge or + Tviol_DIA1_CLKA_posedge or + Tviol_DIA2_CLKA_posedge or + Tviol_DIA3_CLKA_posedge or + Tviol_DIA4_CLKA_posedge or + Tviol_DIA5_CLKA_posedge or + Tviol_DIA6_CLKA_posedge or + Tviol_DIA7_CLKA_posedge or + Tviol_ENA_CLKA_posedge or + Tviol_RSTA_CLKA_posedge or + Tviol_WEA_CLKA_posedge; + + ViolationB := Pviol_CLKB or + Tviol_ADDRB0_CLKB_posedge or + Tviol_ADDRB1_CLKB_posedge or + Tviol_ADDRB2_CLKB_posedge or + Tviol_ADDRB3_CLKB_posedge or + Tviol_ADDRB4_CLKB_posedge or + Tviol_ADDRB5_CLKB_posedge or + Tviol_ADDRB6_CLKB_posedge or + Tviol_ADDRB7_CLKB_posedge or + Tviol_ADDRB8_CLKB_posedge or + Tviol_DIB0_CLKB_posedge or + Tviol_DIB1_CLKB_posedge or + Tviol_DIB2_CLKB_posedge or + Tviol_DIB3_CLKB_posedge or + Tviol_DIB4_CLKB_posedge or + Tviol_DIB5_CLKB_posedge or + Tviol_DIB6_CLKB_posedge or + Tviol_DIB7_CLKB_posedge or + Tviol_ENB_CLKB_posedge or + Tviol_RSTB_CLKB_posedge or + Tviol_WEB_CLKB_posedge; + + VALID_ADDRA := ADDR_IS_VALID(ADDRA_ipd_sampled); + VALID_ADDRB := ADDR_IS_VALID(ADDRB_ipd_sampled); + + if (VALID_ADDRA) then + ADDRESS_A := SLV_TO_INT(ADDRA_ipd_sampled); + end if; + + if (VALID_ADDRB) then + ADDRESS_B := SLV_TO_INT(ADDRB_ipd_sampled); + end if; + + if (VALID_ADDRA and VALID_ADDRB) then + addr_overlap (address_a, address_b, width_a, width_b, has_overlap, olp_lsb, olp_msb, doa_ov_lsb, doa_ov_msb, dob_ov_lsb, dob_ov_msb); + end if; + + ViolationCLKAB := '0'; + + if ((collision_type = 1) or (collision_type = 2) or (collision_type = 3)) then + VitalSetupHoldCheck ( + Violation => Tviol_CLKB_CLKA_posedge, + TimingData => Tmkr_CLKB_CLKA_posedge, + TestSignal => CLKB_ipd, + TestSignalName => "CLKB", + TestDelay => 0 ps, + RefSignal => CLKA_ipd, + RefSignalName => "CLKA", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + VitalSetupHoldCheck ( + Violation => Tviol_CLKA_CLKB_posedge, + TimingData => Tmkr_CLKA_CLKB_posedge, + TestSignal => CLKA_ipd, + TestSignalName => "CLKA", + TestDelay => 0 ps, + RefSignal => CLKB_ipd, + RefSignalName => "CLKB", + RefDelay => 0 ps, + SetupHigh => SETUP_ALL, + CheckEnabled => (TO_X01(ENA_ipd_sampled) = '1' and TO_X01(ENB_ipd_sampled) = '1' and (TO_X01(WEA_ipd_sampled) = '1' or TO_X01(WEB_ipd_sampled) = '1') and HAS_OVERLAP = true), + RefTransition => 'R', + HeaderMsg => "/RAMB4_S8_S8", + Xon => true, + MsgOn => false, + MsgSeverity => warning); + end if; + + ViolationCLKAB := Tviol_CLKB_CLKA_posedge or Tviol_CLKA_CLKB_posedge; + + if (ENA_ipd_sampled = '1') then + if (rising_edge(CLKA_ipd)) then + if (WEA_ipd_sampled = '1') then + if (VALID_ADDRA) then + MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))):= DIA_ipd; + end if; + DOA_zd := DIA_ipd; + + if (ViolationCLKAB = 'X') then + if (WEB_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S8_S8", + InstanceName => ramb4_s8_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_A/(length_a/length_b))(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + DOA_zd := (others => 'X'); + + if (RSTB_ipd_sampled = '0' ) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + + else + if (RSTB_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S8_S8", + InstanceName => ramb4_s8_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRA) then + DOA_zd := MEM(ADDRESS_A/(length_a/length_b))(((((address_a)rem(length_a/length_b))*(width_a)) + (width_a - 1)) downto (((address_a)rem(length_a/length_b))*(width_a))); + end if; + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S8_S8", + InstanceName => ramb4_s8_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + + if (RSTA_ipd_sampled = '1') then + DOA_zd := (others => '0'); + end if; + end if; + end if; + + if (ENB_ipd_sampled = '1') then + if (rising_edge(CLKB_ipd)) then + + if (WEB_ipd_sampled = '1') then + if (VALID_ADDRB) then + MEM(ADDRESS_B) := DIB_ipd; + end if; + DOB_zd := DIB_ipd; + + if (ViolationCLKAB = 'X') then + if (WEA_ipd_sampled /= '0') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Write_A_Write_B, + EntityName => "RAMB4_S8_S8", + InstanceName => ramb4_s8_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + MEM(ADDRESS_B)(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + + if (RSTA_ipd_sampled = '0' ) then + DOA_zd := (others => 'X'); + end if; + end if; + + else + if (RSTA_ipd_sampled = '0' ) then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_A_Write_B, + EntityName => "RAMB4_S8_S8", + InstanceName => ramb4_s8_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOA_zd := (others => 'X'); + end if; + end if; + end if; + end if; + + else + if (VALID_ADDRB) then + DOB_zd := MEM(ADDRESS_B); + end if; + + if (ViolationCLKAB = 'X') then + if ((collision_type = 1) or (collision_type = 3)) then + Memory_Collision_Msg + (collision_type => Read_B_Write_A, + EntityName => "RAMB4_S8_S8", + InstanceName => ramb4_s8_s8'path_name, + address_a => addra_ipd_sampled, + address_b => addrb_ipd_sampled + ); + end if; + if ((collision_type = 2) or (collision_type = 3)) then + DOB_zd(DOB_OV_MSB downto DOB_OV_LSB) := (others => 'X'); + end if; + end if; + end if; + + if (RSTB_ipd_sampled = '1') then + DOB_zd := (others => '0'); + end if; + end if; + end if; + + DOA_zd(0) := ViolationA xor DOA_zd(0); + DOA_zd(1) := ViolationA xor DOA_zd(1); + DOA_zd(2) := ViolationA xor DOA_zd(2); + DOA_zd(3) := ViolationA xor DOA_zd(3); + DOA_zd(4) := ViolationA xor DOA_zd(4); + DOA_zd(5) := ViolationA xor DOA_zd(5); + DOA_zd(6) := ViolationA xor DOA_zd(6); + DOA_zd(7) := ViolationA xor DOA_zd(7); + + DOB_zd(0) := ViolationB xor DOB_zd(0); + DOB_zd(1) := ViolationB xor DOB_zd(1); + DOB_zd(2) := ViolationB xor DOB_zd(2); + DOB_zd(3) := ViolationB xor DOB_zd(3); + DOB_zd(4) := ViolationB xor DOB_zd(4); + DOB_zd(5) := ViolationB xor DOB_zd(5); + DOB_zd(6) := ViolationB xor DOB_zd(6); + DOB_zd(7) := ViolationB xor DOB_zd(7); + + VitalPathDelay01 ( + OutSignal => DOA(0), + GlitchData => DOA_GlitchData0, + OutSignalName => "DOA(0)", + OutTemp => DOA_zd(0), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(1), + GlitchData => DOA_GlitchData1, + OutSignalName => "DOA(1)", + OutTemp => DOA_zd(1), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(2), + GlitchData => DOA_GlitchData2, + OutSignalName => "DOA(2)", + OutTemp => DOA_zd(2), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(3), + GlitchData => DOA_GlitchData3, + OutSignalName => "DOA(3)", + OutTemp => DOA_zd(3), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(4), + GlitchData => DOA_GlitchData4, + OutSignalName => "DOA(4)", + OutTemp => DOA_zd(4), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(5), + GlitchData => DOA_GlitchData5, + OutSignalName => "DOA(5)", + OutTemp => DOA_zd(5), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(6), + GlitchData => DOA_GlitchData6, + OutSignalName => "DOA(6)", + OutTemp => DOA_zd(6), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOA(7), + GlitchData => DOA_GlitchData7, + OutSignalName => "DOA(7)", + OutTemp => DOA_zd(7), + Paths => (0 => (CLKA_ipd'last_event, tpd_CLKA_DOA(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(0), + GlitchData => DOB_GlitchData0, + OutSignalName => "DOB(0)", + OutTemp => DOB_zd(0), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(0), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(1), + GlitchData => DOB_GlitchData1, + OutSignalName => "DOB(1)", + OutTemp => DOB_zd(1), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(1), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(2), + GlitchData => DOB_GlitchData2, + OutSignalName => "DOB(2)", + OutTemp => DOB_zd(2), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(2), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(3), + GlitchData => DOB_GlitchData3, + OutSignalName => "DOB(3)", + OutTemp => DOB_zd(3), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(3), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(4), + GlitchData => DOB_GlitchData4, + OutSignalName => "DOB(4)", + OutTemp => DOB_zd(4), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(4), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(5), + GlitchData => DOB_GlitchData5, + OutSignalName => "DOB(5)", + OutTemp => DOB_zd(5), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(5), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(6), + GlitchData => DOB_GlitchData6, + OutSignalName => "DOB(6)", + OutTemp => DOB_zd(6), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(6), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + VitalPathDelay01 ( + OutSignal => DOB(7), + GlitchData => DOB_GlitchData7, + OutSignalName => "DOB(7)", + OutTemp => DOB_zd(7), + Paths => (0 => (CLKB_ipd'last_event, tpd_CLKB_DOB(7), true)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + wait on ADDRA_ipd, ADDRB_ipd, CLKA_ipd, CLKB_ipd, DIA_ipd, DIB_ipd, ENA_ipd, ENB_ipd, RSTA_ipd, RSTB_ipd, WEA_ipd, WEB_ipd; + end process VITALBehavior; +end RAMB4_S8_S8_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/roc.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Reset On Configuration +-- /___/ /\ Filename : ROC.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL ROC ----- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity ROC is + generic ( + InstancePath : string := "*"; + WIDTH : time := 100 ns + ); + port( + O : out std_ulogic := '1' + ); +end ROC; + +architecture ROC_V of ROC is +begin + ONE_SHOT : process + begin + if (WIDTH <= 0 ns) then + assert false report + "*** Error : a positive value of WIDTH must be specified ***" + severity failure; + else + wait for WIDTH; + O <= '0'; + end if; + wait; + end process ONE_SHOT; +end ROC_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/rocbuf.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Reset On Configuration Buffer +-- /___/ /\ Filename : ROCBUF.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:56 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL ROCBUF ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity ROCBUF is + port( + O : out std_ulogic; + I : in std_ulogic + ); +end ROCBUF; + +architecture ROCBUF_V of ROCBUF is +begin + O <= I; +end ROCBUF_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/rom128x1.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 128-Deep by 1-Wide ROM +-- /___/ /\ Filename : ROM128X1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:57 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL ROM128X1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity ROM128X1 is + + generic ( + INIT : bit_vector := X"00000000000000000000000000000000" + ); + + port ( + O : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic; + A6 : in std_ulogic + ); +end ROM128X1; + +architecture ROM128X1_V of ROM128X1 is +begin + VITALBehavior : process (A6, A5, A4, A3, A2, A1, A0) + variable INIT_BITS : std_logic_vector(127 downto 0) := To_StdLogicVector(INIT); + variable MEM : std_logic_vector( 128 downto 0 ); + variable Index : integer := 128; + variable Raddress : std_logic_vector (6 downto 0); + variable FIRST_TIME : boolean := true; + + begin + if (FIRST_TIME = true) then + MEM := ('X' & INIT_BITS(127 downto 0)); + FIRST_TIME := false; + end if; + Raddress := (A6, A5, A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Raddress); + O <= MEM(Index); + end process VITALBehavior; +end ROM128X1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/rom16x1.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16-Deep by 1-Wide ROM +-- /___/ /\ Filename : ROM16X1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:57 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL ROM16X1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity ROM16X1 is + generic ( + INIT : bit_vector := X"0000" + ); + + port ( + O : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic + ); +end ROM16X1; + +architecture ROM16X1_V of ROM16X1 is +begin + VITALBehavior : process (A3, A2, A1, A0) + variable INIT_BITS : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT); + variable MEM : std_logic_vector( 16 downto 0 ) ; + variable Index : integer := 16; + variable FIRST_TIME : boolean := TRUE; + begin + if (FIRST_TIME = TRUE) then + MEM := ('X' & INIT_BITS(15 downto 0)); + FIRST_TIME := FALSE; + end if; + Index := DECODE_ADDR4(ADDRESS => (A3, A2, A1, A0)); + O <= MEM(Index); + end process VITALBehavior; +end ROM16X1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/rom256x1.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 256-Deep by 1-Wide ROM +-- /___/ /\ Filename : ROM256X1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:57 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL ROM256X1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity ROM256X1 is + generic ( + INIT : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + + port ( + O : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic; + A6 : in std_ulogic; + A7 : in std_ulogic + ); +end ROM256X1; + +architecture ROM256X1_V of ROM256X1 is +begin + VITALBehavior : process (A7, A6, A5, A4, A3, A2, A1, A0) + variable INIT_BITS : std_logic_vector(255 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + variable MEM : std_logic_vector( 256 downto 0 ); + variable Index : integer := 256; + variable Raddress : std_logic_vector (7 downto 0); + variable FIRST_TIME : boolean := true; + + begin + if (FIRST_TIME = true) then + INIT_BITS(INIT'length-1 downto 0) := To_StdLogicVector(INIT ); + MEM := ('X' & INIT_BITS(255 downto 0)); + FIRST_TIME := false; + end if; + Raddress := (A7, A6, A5, A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Raddress ); + O <= MEM(Index); + end process VITALBehavior; +end ROM256X1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/rom32x1.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 32-Deep by 1-Wide ROM +-- /___/ /\ Filename : ROM32X1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:57 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL ROM32X1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity ROM32X1 is + generic ( + INIT : bit_vector := X"00000000" + ); + + port ( + O : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic + ); +end ROM32X1; + +architecture ROM32X1_V of ROM32X1 is +begin + VITALBehavior : process (A4, A3, A2, A1, A0) + variable INIT_BITS : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT); + variable MEM : std_logic_vector( 32 downto 0 ); + variable Index : integer := 32; + variable FIRST_TIME : boolean := true; + + begin + if (FIRST_TIME = true) then + MEM := ('X' & INIT_BITS(31 downto 0)); + FIRST_TIME := false; + end if; + Index := DECODE_ADDR5(ADDRESS => (A4, A3, A2, A1, A0)); + O <= MEM(Index); + end process VITALBehavior; +end ROM32X1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/rom64x1.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 64-Deep by 1-Wide ROM +-- /___/ /\ Filename : ROM64X1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:57 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL ROM64X1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity ROM64X1 is + generic ( + INIT : bit_vector := X"0000000000000000" + ); + + port ( + O : out std_ulogic; + + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + A4 : in std_ulogic; + A5 : in std_ulogic + ); +end ROM64X1; +architecture ROM64X1_V of ROM64X1 is +begin + VITALBehavior : process (A5, A4, A3, A2, A1, A0) + variable INIT_BITS : std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + variable MEM : std_logic_vector( 64 downto 0 ); + variable Index : integer := 64; + variable Raddress : std_logic_vector (5 downto 0); + variable FIRST_TIME : boolean := true; + begin + if (FIRST_TIME = true) then + INIT_BITS(INIT'length-1 downto 0) := To_StdLogicVector(INIT ); + MEM := ('X' & INIT_BITS(63 downto 0)); + FIRST_TIME := false; + end if; + Raddress := (A5, A4, A3, A2, A1, A0); + Index := SLV_TO_INT(SLV => Raddress ); + O <= MEM(Index); + end process VITALBehavior; +end ROM64X1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/srl16.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16-Bit Shift Register Look-Up-Table +-- /___/ /\ Filename : SRL16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:57 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL SRL16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity SRL16 is + + generic ( + INIT : bit_vector := X"0000" + ); + + port ( + Q : out STD_ULOGIC; + + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + CLK : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end SRL16; + +architecture SRL16_V of SRL16 is + + signal SHIFT_REG : std_logic_vector (16 downto 0) := ('X' & To_StdLogicVector(INIT)); + +begin + + VITALReadBehavior : process(A0, A1, A2, A3, SHIFT_REG) + + variable VALID_ADDR : boolean := FALSE; + variable LENGTH : integer; + variable ADDR: std_logic_vector (3 downto 0) ; + + begin + + ADDR := (A3, A2, A1, A0); + VALID_ADDR := ADDR_IS_VALID(SLV => ADDR); + + if (VALID_ADDR) then + LENGTH := SLV_TO_INT(SLV => ADDR); + else + LENGTH := 16; + end if; + Q <= SHIFT_REG(LENGTH); + + end process VITALReadBehavior; + +VITALWriteBehavior : process + + variable FIRST_TIME : boolean := TRUE; + + begin + + if (FIRST_TIME) then + wait until ((CLK'last_value = '0' or CLK'last_value = '1') and + (CLK = '0' or CLK = '1')); + FIRST_TIME := FALSE; + end if; + + if (CLK'event AND CLK'last_value = '0') then + if (CLK = '1') then + for I in 15 downto 1 loop + SHIFT_REG(I) <= SHIFT_REG(I-1) after 100 ps; + end loop; + SHIFT_REG(0) <= D after 100 ps; + elsif (CLK = 'X') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + elsif (CLK'event AND CLK'last_value = 'X') then + if (CLK = '1') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + end if; + + wait on CLK; + + end process VITALWriteBehavior; + +end SRL16_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/srl16_1.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16-Bit Shift Register Look-Up-Table with Negative-Edge Clock +-- /___/ /\ Filename : SRL16_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:57 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL SRL16_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity SRL16_1 is + + generic ( + INIT : bit_vector := X"0000" + ); + + port ( + Q : out STD_ULOGIC; + + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + CLK : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end SRL16_1; + +architecture SRL16_1_V of SRL16_1 is + signal SHIFT_REG : std_logic_vector (16 downto 0) := ('X' & To_StdLogicVector(INIT)); +begin + + VITALreadBehavior : process (A0, A1, A2, A3, SHIFT_REG) + + variable VALID_ADDR : boolean := FALSE; + variable LENGTH : integer; + variable ADDR: std_logic_vector (3 downto 0) ; + + begin + ADDR := (A3, A2, A1, A0); + VALID_ADDR := ADDR_IS_VALID(SLV => ADDR); + + if (VALID_ADDR) then + LENGTH := SLV_TO_INT(SLV => ADDR); + else + LENGTH := 16; + end if; + Q <= SHIFT_REG(LENGTH); + + end process VITALReadBehavior; + +VITALWriteBehavior : process + variable FIRST_TIME : boolean := TRUE; + begin + + if (FIRST_TIME) then + wait until ((CLK'last_value = '0' or CLK'last_value = '1') and + (CLK = '0' or CLK = '1')); + FIRST_TIME := FALSE; + end if; + + if (CLK'event AND CLK'last_value = '1') then + if (CLK = '0') then + for I in 15 downto 1 loop + SHIFT_REG(I) <= SHIFT_REG(I-1) after 100 ps; + end loop; + SHIFT_REG(0) <= D after 100 ps; + elsif (CLK = 'X') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + elsif (CLK'event AND CLK'last_value = 'X') then + if (CLK = '0') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + end if; + + wait on CLK; + + end process VITALWriteBehavior; +end SRL16_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/srl16e.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16-Bit Shift Register Look-Up-Table with Clock Enable +-- /___/ /\ Filename : SRL16E.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:57 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL SRL16E ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity SRL16E is + + generic ( + INIT : bit_vector := X"0000" + ); + + port ( + Q : out STD_ULOGIC; + + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end SRL16E; + +architecture SRL16E_V of SRL16E is + signal SHIFT_REG : std_logic_vector (16 downto 0) := ('X' & To_StdLogicVector(INIT)); +begin + VITALReadBehavior : process(A0, A1, A2, A3, SHIFT_REG) + + variable VALID_ADDR : boolean := FALSE; + variable LENGTH : integer; + variable ADDR : std_logic_vector(3 downto 0); + + begin + + ADDR := (A3, A2, A1, A0); + VALID_ADDR := ADDR_IS_VALID(SLV => ADDR); + + if (VALID_ADDR) then + LENGTH := SLV_TO_INT(SLV => ADDR); + else + LENGTH := 16; + end if; + Q <= SHIFT_REG(LENGTH); + + end process VITALReadBehavior; + + VITALWriteBehavior : process + variable FIRST_TIME : boolean := TRUE; + begin + + if (FIRST_TIME) then + wait until ((CE = '1' or CE = '0') and + (CLK'last_value = '0' or CLK'last_value = '1') and + (CLK = '0' or CLK = '1')); + FIRST_TIME := FALSE; + end if; + + if (CLK'event AND CLK'last_value = '0') then + if (CLK = '1') then + if (CE = '1') then + for I in 15 downto 1 loop + SHIFT_REG(I) <= SHIFT_REG(I-1) after 100 ps; + end loop; + SHIFT_REG(0) <= D after 100 ps; + elsif (CE = 'X') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + elsif (CLK = 'X') then + if (CE /= '0') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + end if; + elsif (CLK'event AND CLK'last_value = 'X') then + if (CLK = '1') then + if (CE /= '0') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + end if; + end if; + wait on CLK; + end process VITALWriteBehavior; +end SRL16E_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/srl16e_1.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16-Bit Shift Register Look-Up-Table with Clock Enable and Negative-Edge Clock +-- /___/ /\ Filename : SRL16E_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:57 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL SRL16E_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity SRL16E_1 is + + generic ( + INIT : bit_vector := X"0000" + ); + + port ( + Q : out STD_ULOGIC; + + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end SRL16E_1; + +architecture SRL16E_1_V of SRL16E_1 is +signal SHIFT_REG : std_logic_vector (16 downto 0) := ('X' & To_StdLogicVector( INIT)); + + +begin + VITALReadBehavior : process(A0, A1, A2, A3, SHIFT_REG) + variable ADDR : std_logic_vector(3 downto 0); + variable VALID_ADDR : boolean := FALSE; + variable LENGTH : integer; + + begin + + ADDR := (A3, A2, A1, A0); + VALID_ADDR := ADDR_IS_VALID(SLV => ADDR); + + if (VALID_ADDR) then + LENGTH := SLV_TO_INT(SLV => ADDR); + else + LENGTH := 16; + end if; + Q <= SHIFT_REG(LENGTH); + + end process VITALReadBehavior; + + VITALWriteBehavior : process + variable FIRST_TIME : boolean := TRUE; + begin + if (FIRST_TIME) then + wait until ((CE = '1' or CE = '0') and + (CLK'last_value = '0' or CLK'last_value = '1') and + (CLK = '0' or CLK = '1')); + FIRST_TIME := FALSE; + end if; + + if (CLK'event AND CLK'last_value = '1') then + if (CLK = '0') then + if (CE = '1') then + for I in 15 downto 1 loop + SHIFT_REG(I) <= SHIFT_REG(I-1) after 100 ps; + end loop; + SHIFT_REG(0) <= D after 100 ps; + elsif (CE = 'X') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + elsif (CLK = 'X') then + if (CE /= '0') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + end if; + elsif (CLK'event AND CLK'last_value = 'X') then + if (CLK = '0') then + if (CE /= '0') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + end if; + end if; + wait on CLK; + end process VITALWriteBehavior; + +end SRL16E_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/srlc16.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16-Bit Shift Register Look-Up-Table with Carry +-- /___/ /\ Filename : SRLC16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:58 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL SRLC16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity SRLC16 is + + generic ( + INIT : bit_vector := X"0000" + ); + + port ( + Q : out STD_ULOGIC; + Q15 : out STD_ULOGIC; + + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + CLK : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end SRLC16; + +architecture SRLC16_V of SRLC16 is + signal SHIFT_REG : std_logic_vector (16 downto 0) := ('X' & To_StdLogicVector(INIT)); +begin + VITALReadBehavior : process(A0, A1, A2, A3, SHIFT_REG) + + variable VALID_ADDR : boolean := FALSE; + variable LENGTH : integer; + variable ADDR: std_logic_vector (3 downto 0) ; + + begin + + ADDR := (A3, A2, A1, A0); + VALID_ADDR := ADDR_IS_VALID(SLV => ADDR); + + if (VALID_ADDR) then + LENGTH := SLV_TO_INT(SLV => ADDR); + else + LENGTH := 16; + end if; + Q <= SHIFT_REG(LENGTH); + Q15 <= SHIFT_REG(15); + + end process VITALReadBehavior; + +VITALWriteBehavior : process + + variable FIRST_TIME : boolean := TRUE; + + begin -- process + + if (FIRST_TIME) then + wait until ((CLK'last_value = '0' or CLK'last_value = '1') and + (CLK = '0' or CLK = '1')); + FIRST_TIME := FALSE; + end if; + + if (CLK'event AND CLK'last_value = '0') then + if (CLK = '1') then + for I in 15 downto 1 loop + SHIFT_REG(I) <= SHIFT_REG(I-1) after 100 ps; + end loop; + SHIFT_REG(0) <= D after 100 ps; + elsif (CLK = 'X') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + elsif (CLK'event AND CLK'last_value = 'X') then + if (CLK = '1') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + end if; + + wait on CLK; + end process VITALWriteBehavior; +end SRLC16_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/srlc16_1.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16-Bit Shift Register Look-Up-Table with Carry and Negative-Edge Clock +-- /___/ /\ Filename : SRLC16_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:58 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL SRLC16_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity SRLC16_1 is + + generic ( + INIT : bit_vector := X"0000" + ); + + port ( + Q : out STD_ULOGIC; + Q15 : out STD_ULOGIC; + + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + CLK : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end SRLC16_1; + +architecture SRLC16_1_V of SRLC16_1 is + signal SHIFT_REG : std_logic_vector (16 downto 0) := ('X' & To_StdLogicVector(INIT)); +begin + VITALreadBehavior : process (A0, A1, A2, A3, SHIFT_REG) + + variable VALID_ADDR : boolean := FALSE; + variable LENGTH : integer; + variable ADDR: std_logic_vector (3 downto 0) ; + + begin + + ADDR := (A3, A2, A1, A0); + VALID_ADDR := ADDR_IS_VALID(SLV => ADDR); + + if (VALID_ADDR) then + LENGTH := SLV_TO_INT(SLV => ADDR); + else + LENGTH := 16; + end if; + Q <= SHIFT_REG(LENGTH); + Q15 <= SHIFT_REG(15); + end process VITALReadBehavior; + +VITALWriteBehavior : process + variable FIRST_TIME : boolean := TRUE; + begin + if (FIRST_TIME) then + wait until ((CLK'last_value = '0' or CLK'last_value = '1') and + (CLK = '0' or CLK = '1')); + FIRST_TIME := FALSE; + end if; + + if (CLK'event AND CLK'last_value = '1') then + if (CLK = '0') then + for I in 15 downto 1 loop + SHIFT_REG(I) <= SHIFT_REG(I-1) after 100 ps; + end loop; + SHIFT_REG(0) <= D after 100 ps; + elsif (CLK = 'X') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + elsif (CLK'event AND CLK'last_value = 'X') then + if (CLK = '0') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + end if; + + wait on CLK; + + end process VITALWriteBehavior; +end SRLC16_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/srlc16e.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16-Bit Shift Register Look-Up-Table with Carry and Clock Enable +-- /___/ /\ Filename : SRLC16E.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:58 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL SRLC16E ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity SRLC16E is + + generic ( + INIT : bit_vector := X"0000" + ); + + port ( + Q : out STD_ULOGIC; + Q15 : out STD_ULOGIC; + + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end SRLC16E; + +architecture SRLC16E_V of SRLC16E is + signal SHIFT_REG : std_logic_vector (16 downto 0) := ('X' & To_StdLogicVector(INIT)); +begin + VITALReadBehavior : process(A0, A1, A2, A3, SHIFT_REG) + + variable VALID_ADDR : boolean := FALSE; + variable LENGTH : integer; + variable ADDR : std_logic_vector(3 downto 0); + + begin + + ADDR := (A3, A2, A1, A0); + VALID_ADDR := ADDR_IS_VALID(SLV => ADDR); + + if (VALID_ADDR) then + LENGTH := SLV_TO_INT(SLV => ADDR); + else + LENGTH := 16; + end if; + Q <= SHIFT_REG(LENGTH); + Q15 <= SHIFT_REG(15); + + end process VITALReadBehavior; + + VITALWriteBehavior : process + + variable FIRST_TIME : boolean := TRUE; + + begin + + if (FIRST_TIME) then + wait until ((CE = '1' or CE = '0') and + (CLK'last_value = '0' or CLK'last_value = '1') and + (CLK = '0' or CLK = '1')); + FIRST_TIME := FALSE; + end if; + + if (CLK'event AND CLK'last_value = '0') then + if (CLK = '1') then + if (CE = '1') then + for I in 15 downto 1 loop + SHIFT_REG(I) <= SHIFT_REG(I-1) after 100 ps; + end loop; + SHIFT_REG(0) <= D after 100 ps; + elsif (CE = 'X') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + elsif (CLK = 'X') then + if (CE /= '0') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + end if; + elsif (CLK'event AND CLK'last_value = 'X') then + if (CLK = '1') then + if (CE /= '0') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + end if; + end if; + + wait on CLK; + + end process VITALWriteBehavior; +end SRLC16E_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/srlc16e_1.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16-Bit Shift Register Look-Up-Table with Carry, Clock Enable and Negative-Edge Clock +-- /___/ /\ Filename : SRLC16E_1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:58 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL SRLC16E_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity SRLC16E_1 is + + generic ( + INIT : bit_vector := X"0000" + ); + + port ( + Q : out STD_ULOGIC; + Q15 : out STD_ULOGIC; + + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end SRLC16E_1; + +architecture SRLC16E_1_V of SRLC16E_1 is + signal SHIFT_REG : std_logic_vector (16 downto 0) := ('X' & To_StdLogicVector( INIT)); + +begin + VITALReadBehavior : process(A0, A1, A2, A3, SHIFT_REG) + + variable ADDR : std_logic_vector(3 downto 0); + variable VALID_ADDR : boolean := FALSE; + variable LENGTH : integer; + + begin + + ADDR := (A3, A2, A1, A0); + VALID_ADDR := ADDR_IS_VALID(SLV => ADDR); + + if (VALID_ADDR) then + LENGTH := SLV_TO_INT(SLV => ADDR); + else + LENGTH := 16; + end if; + Q <= SHIFT_REG(LENGTH); + Q15 <= SHIFT_REG(15); + + end process VITALReadBehavior; + + VITALWriteBehavior : process + + variable FIRST_TIME : boolean := TRUE; + + + begin + + if (FIRST_TIME) then + wait until ((CE = '1' or CE = '0') and + (CLK'last_value = '0' or CLK'last_value = '1') and + (CLK = '0' or CLK = '1')); + FIRST_TIME := FALSE; + end if; + if (CLK'event AND CLK'last_value = '1') then + if (CLK = '0') then + if (CE = '1') then + for I in 15 downto 1 loop + SHIFT_REG(I) <= SHIFT_REG(I-1) after 100 ps; + end loop; + SHIFT_REG(0) <= D after 100 ps; + elsif (CE = 'X') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + elsif (CLK = 'X') then + if (CE /= '0') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + end if; + elsif (CLK'event AND CLK'last_value = 'X') then + if (CLK = '0') then + if (CE /= '0') then + SHIFT_REG <= (others => 'X') after 100 ps; + end if; + end if; + end if; + + wait on CLK; + + end process VITALWriteBehavior; +end SRLC16E_1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startbuf_fpgacore.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / User Interface to Global Clock, Reset and 3-State Controls for FPGACORE +-- /___/ /\ Filename : STARTBUF_FPGACORE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:58 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL STARTBUF_FPGACORE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity STARTBUF_FPGACORE is + port( + GSROUT : out std_ulogic; + + CLKIN : in std_ulogic := 'X'; + GSRIN : in std_ulogic := 'X' +); +end STARTBUF_FPGACORE; + +architecture STARTBUF_FPGACORE_V of STARTBUF_FPGACORE is +begin + GSROUT <= TO_X01(GSRIN); +end STARTBUF_FPGACORE_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startbuf_spartan2.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / User Interface to Global Clock, Reset and 3-State Controls for SPARTAN2 +-- /___/ /\ Filename : STARTBUF_SPARTAN2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:58 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL STARTBUF_SPARTAN2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity STARTBUF_SPARTAN2 is + port( + GSROUT : out std_ulogic; + GTSOUT : out std_ulogic; + + CLKIN : in std_ulogic := 'X'; + GSRIN : in std_ulogic := 'X'; + GTSIN : in std_ulogic := 'X' + ); +end STARTBUF_SPARTAN2; + +architecture STARTBUF_SPARTAN2_V of STARTBUF_SPARTAN2 is + begin + GTSOUT <= TO_X01(GTSIN); + GSROUT <= TO_X01(GSRIN); + end STARTBUF_SPARTAN2_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startbuf_spartan3.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / User Interface to Global Clock, Reset and 3-State Controls for SPARTAN3 +-- /___/ /\ Filename : STARTBUF_SPARTAN3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:58 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL STARTBUF_SPARTAN3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity STARTBUF_SPARTAN3 is + port( + GSROUT : out std_ulogic; + GTSOUT : out std_ulogic; + + CLKIN : in std_ulogic := 'X'; + GSRIN : in std_ulogic := 'X'; + GTSIN : in std_ulogic := 'X' +); +end STARTBUF_SPARTAN3; + +architecture STARTBUF_SPARTAN3_V of STARTBUF_SPARTAN3 is + begin + GTSOUT <= TO_X01(GTSIN); + GSROUT <= TO_X01(GSRIN); + end STARTBUF_SPARTAN3_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startbuf_virtex.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / User Interface to Global Clock, Reset and 3-State Controls for VIRTEX +-- /___/ /\ Filename : STARTBUF_VIRTEX.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:58 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL STARTBUF_VIRTEX ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity STARTBUF_VIRTEX is + port( + GSROUT : out std_ulogic; + GTSOUT : out std_ulogic; + + CLKIN : in std_ulogic := 'X'; + GSRIN : in std_ulogic := 'X'; + GTSIN : in std_ulogic := 'X' +); +end STARTBUF_VIRTEX; + +architecture STARTBUF_VIRTEX_V of STARTBUF_VIRTEX is + begin + GTSOUT <= TO_X01(GTSIN); + GSROUT <= TO_X01(GSRIN); + end STARTBUF_VIRTEX_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startbuf_virtex2.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / User Interface to Global Clock, Reset and 3-State Controls for VIRTEX2 +-- /___/ /\ Filename : STARTBUF_VIRTEX2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:58 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL STARTBUF_VIRTEX2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity STARTBUF_VIRTEX2 is + port( + GSROUT : out std_ulogic; + GTSOUT : out std_ulogic; + + CLKIN : in std_ulogic := 'X'; + GSRIN : in std_ulogic := 'X'; + GTSIN : in std_ulogic := 'X' +); +end STARTBUF_VIRTEX2; + +architecture STARTBUF_VIRTEX2_V of STARTBUF_VIRTEX2 is + begin + GTSOUT <= TO_X01(GTSIN); + GSROUT <= TO_X01(GSRIN); + end STARTBUF_VIRTEX2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startup_fpgacore.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / User Interface to Global Clock, Reset and 3-State Controls for FPGACORE +-- /___/ /\ Filename : STARTUP_FPGACORE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:59 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL STARTUP_FPGACORE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity STARTUP_FPGACORE is + port( + CLK : in std_ulogic := 'X'; + GSR : in std_ulogic := 'X' + ); +end STARTUP_FPGACORE; + +architecture STARTUP_FPGACORE_V of STARTUP_FPGACORE is +begin +end STARTUP_FPGACORE_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startup_spartan2.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / User Interface to Global Clock, Reset and 3-State Controls for SPARTAN2 +-- /___/ /\ Filename : STARTUP_SPARTAN2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:59 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL STARTUP_SPARTAN2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity STARTUP_SPARTAN2 is + port( + CLK : in std_ulogic := 'X'; + GSR : in std_ulogic := 'X'; + GTS : in std_ulogic := 'X' + ); +end STARTUP_SPARTAN2; + +architecture STARTUP_SPARTAN2_V of STARTUP_SPARTAN2 is +begin +end STARTUP_SPARTAN2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startup_spartan3.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / User Interface to Global Clock, Reset and 3-State Controls for SPARTAN3 +-- /___/ /\ Filename : STARTUP_SPARTAN3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:59 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL STARTUP_SPARTAN3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity STARTUP_SPARTAN3 is + port( + CLK : in std_ulogic := 'X'; + GSR : in std_ulogic := 'X'; + GTS : in std_ulogic := 'X' + ); +end STARTUP_SPARTAN3; + +architecture STARTUP_SPARTAN3_V of STARTUP_SPARTAN3 is +begin +end STARTUP_SPARTAN3_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startup_virtex.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / User Interface to Global Clock, Reset and 3-State Controls for VIRTEX +-- /___/ /\ Filename : STARTUP_VIRTEX.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:59 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL STARTUP_VIRTEX ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity STARTUP_VIRTEX is + port( + CLK : in std_ulogic := 'X'; + GSR : in std_ulogic := 'X'; + GTS : in std_ulogic := 'X' + ); +end STARTUP_VIRTEX; + +architecture STARTUP_VIRTEX_V of STARTUP_VIRTEX is +begin +end STARTUP_VIRTEX_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/startup_virtex2.vhd,v 1.5 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / User Interface to Global Clock, Reset and 3-State Controls for VIRTEX2 +-- /___/ /\ Filename : STARTUP_VIRTEX2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:59 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL STARTUP_VIRTEX2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity STARTUP_VIRTEX2 is + port( + CLK : in std_ulogic := 'X'; + GSR : in std_ulogic := 'X'; + GTS : in std_ulogic := 'X' + ); +end STARTUP_VIRTEX2; + +architecture STARTUP_VIRTEX2_V of STARTUP_VIRTEX2 is +begin +end STARTUP_VIRTEX2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/tblock.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / +-- /___/ /\ Filename : TBLOCK.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:59 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL TBLOCK ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity TBLOCK is +end TBLOCK; + +architecture TBLOCK_V of TBLOCK is +begin +end TBLOCK_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/timegrp.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / +-- /___/ /\ Filename : TIMEGRP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:59 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL TIMEGRP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity TIMEGRP is +end TIMEGRP; + +architecture TIMEGRP_V of TIMEGRP is +begin +end TIMEGRP_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/timespec.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / +-- /___/ /\ Filename : TIMESPEC.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:59 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL TIMESPEC ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity TIMESPEC is +end TIMESPEC; + +architecture TIMESPEC_V of TIMESPEC is +begin +end TIMESPEC_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/toc.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Three-State on Configuration +-- /___/ /\ Filename : TOC.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:00 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL TOC ----- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity TOC is + generic ( + InstancePath : string := "*"; + WIDTH : time := 100 ns + ); + + port( + O : out std_ulogic := '0' + ); +end TOC; + +architecture TOC_V of TOC is +begin + ONE_SHOT : process + begin + O <= '1'; + if (WIDTH <= 0 ns) then + O <= '0'; + else + wait for WIDTH; + O <= '0'; + end if; + wait; + end process ONE_SHOT; +end TOC_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/tocbuf.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Three-State on Configuration Buffer +-- /___/ /\ Filename : TOCBUF.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:00 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL TOCBUF ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity TOCBUF is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end TOCBUF; + +architecture TOCBUF_V of TOCBUF is +begin + O <= I; +end TOCBUF_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/vcc.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / VCC Connection +-- /___/ /\ Filename : VCC.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:00 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL VCC ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity VCC is + port( + P : out std_ulogic := '1' + ); +end VCC; + +architecture VCC_V of VCC is +begin + P <= '1'; +end VCC_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xnor2.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-input XNOR Gate +-- /___/ /\ Filename : XNOR2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:00 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL XNOR2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity XNOR2 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end XNOR2; + +architecture XNOR2_V of XNOR2 is +begin + O <= (not (I0 xor I1)); +end XNOR2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xnor3.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input XNOR Gate +-- /___/ /\ Filename : XNOR3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:00 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL XNOR3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity XNOR3 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end XNOR3; + +architecture XNOR3_V of XNOR3 is +begin + O <= (not (I0 xor I1 xor I2)); +end XNOR3_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xnor4.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input XNOR Gate +-- /___/ /\ Filename : XNOR4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:00 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL XNOR4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity XNOR4 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end XNOR4; + +architecture XNOR4_V of XNOR4 is +begin + O <= (not (I0 xor I1 xor I2 xor I3)); +end XNOR4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xnor5.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input XNOR Gate +-- /___/ /\ Filename : XNOR5.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:00 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL XNOR5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity XNOR5 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end XNOR5; + +architecture XNOR5_V of XNOR5 is +begin + O <= (not (I0 xor I1 xor I2 xor I3 xor I4)); +end XNOR5_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xor2.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 2-input XOR Gate +-- /___/ /\ Filename : XOR2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:00 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL XOR2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity XOR2 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic + ); +end XOR2; + +architecture XOR2_V of XOR2 is +begin + O <= (I0 xor I1); +end XOR2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xor3.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-input XOR Gate +-- /___/ /\ Filename : XOR3.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL XOR3 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity XOR3 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic + ); +end XOR3; + +architecture XOR3_V of XOR3 is +begin + O <= (I0 xor I1 xor I2); +end XOR3_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xor4.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 4-input XOR Gate +-- /___/ /\ Filename : XOR4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL XOR4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity XOR4 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic + ); +end XOR4; + +architecture XOR4_V of XOR4 is +begin + O <= (I0 xor I1 xor I2 xor I3); +end XOR4_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xor5.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input XOR Gate +-- /___/ /\ Filename : XOR5.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL XOR5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity XOR5 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end XOR5; + +architecture XOR5_V of XOR5 is +begin + O <= (I0 xor I1 xor I2 xor I3 xor I4); +end XOR5_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xorcy.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / XOR for Carry Logic with General Output +-- /___/ /\ Filename : XORCY.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL XORCY ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity XORCY is + port( + O : out std_ulogic; + + CI : in std_ulogic; + LI : in std_ulogic + ); +end XORCY; + +architecture XORCY_V of XORCY is +begin + O <= (CI xor LI); +end XORCY_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xorcy_d.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / XOR for Carry Logic with Dual Output +-- /___/ /\ Filename : XORCY_D.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL XORCY_D ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity XORCY_D is + port( + LO : out std_ulogic; + O : out std_ulogic; + + CI : in std_ulogic; + LI : in std_ulogic + ); +end XORCY_D; + +architecture XORCY_D_V of XORCY_D is +begin + O <= (CI xor LI); + LO <= (CI xor LI); +end XORCY_D_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/Attic/xorcy_l.vhd,v 1.4 2004/04/08 18:46:29 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / XOR for Carry Logic with Local Output +-- /___/ /\ Filename : XORCY_L.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL XORCY_L ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity XORCY_L is + port( + LO : out std_ulogic; + + CI : in std_ulogic; + LI : in std_ulogic + ); +end XORCY_L; + +architecture XORCY_L_V of XORCY_L is +begin + LO <= (CI xor LI); +end XORCY_L_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/and6.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 6-input AND Gate +-- /___/ /\ Filename : AND6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:14 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND6 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic + ); +end AND6; + +architecture AND6_V of AND6 is +begin + O <= I0 and I1 and I2 and I3 and I4 and I5; +end AND6_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/and7.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 7-input AND Gate +-- /___/ /\ Filename : AND7.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:14 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND7 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND7 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic; + I6 : in std_ulogic + ); +end AND7; + +architecture AND7_V of AND7 is +begin + O <= I0 and I1 and I2 and I3 and I4 and I5 and I6; +end AND7_V; + + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/and8.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 8-input AND Gate +-- /___/ /\ Filename : AND8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:14 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL AND8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity AND8 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic; + I6 : in std_ulogic; + I7 : in std_ulogic + ); +end AND8; + +architecture AND8_V of AND8 is +begin + O <= I0 and I1 and I2 and I3 and I4 and I5 and I6 and I7; +end AND8_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/buffoe.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / +-- /___/ /\ Filename : BUFFOE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:15 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BUFFOE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity BUFFOE is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end BUFFOE; + +architecture BUFFOE_V of BUFFOE is +begin + O <= TO_X01(I); +end BUFFOE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/bufgsr.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Set/Reset Input Buffer +-- /___/ /\ Filename : BUFGSR.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:16 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BUFGSR ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity BUFGSR is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end BUFGSR; + +architecture BUFGSR_V of BUFGSR is +begin + O <= TO_X01(I); +end BUFGSR_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/bufgts.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global 3-State Input Buffer +-- /___/ /\ Filename : BUFGTS.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:16 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BUFGTS ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity BUFGTS is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end BUFGTS; + +architecture BUFGTS_V of BUFGTS is +begin + O <= TO_X01(I); +end BUFGTS_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div10.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider +-- /___/ /\ Filename : CLK_DIV10.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:17 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV10 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV10 is + generic ( + DIVIDE_BY : integer := 10 + ); + port( + CLKDV : out std_ulogic := '0'; + + CLKIN : in std_ulogic := '0' + ); + +end CLK_DIV10; + +architecture CLK_DIV10_V of CLK_DIV10 is + + signal CLKDV_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN) + variable CLOCK_DIVIDER : integer := 0; + + begin + if (CLKIN'event and CLKIN = '1') then + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV10_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div10r.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Synchronous Reset +-- /___/ /\ Filename : CLK_DIV10R.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:17 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV10R ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV10R is + generic ( + DIVIDE_BY : integer := 10 + ); + port( + CLKDV : out std_ulogic := '0'; + + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); + +end CLK_DIV10R; + +architecture CLK_DIV10R_V of CLK_DIV10R is + + signal CLKDV_i : std_ulogic := '0'; + signal CDRST_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN, CDRST) + variable RESET_WAIT_COUNT : integer := 0; + variable CLOCK_DIVIDER : integer := 0; + variable NO_BITS_REMAINING : integer := 0; + variable DELAY_RESET : boolean := false; + variable STARTUP : boolean := true; + + begin + if (CLKIN'event and CLKIN = '0') then + CDRST_i <= CDRST; + end if; + + if (CLKIN'event and CLKIN = '1') then + + if (CDRST_i = '1' and CLKDV_i = '0') then + CLOCK_DIVIDER := 0; + STARTUP := true; + end if; + + if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true then + CLKDV_i <= '0'; + CLOCK_DIVIDER := 0; + end if; + + + if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false then + NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER); + DELAY_RESET := true; + end if; + + if (DELAY_RESET = true) then + RESET_WAIT_COUNT := RESET_WAIT_COUNT + 1; + if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then + CLKDV_i <= '0'; + DELAY_RESET := false; + RESET_WAIT_COUNT := 0; + STARTUP := true; + CLOCK_DIVIDER := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_RESET = false) then + if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then + CLKDV_i <= '1'; + end if; + + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + STARTUP := false; + CLKDV_i <= not CLKDV_i; + CLOCK_DIVIDER := 1; + end if; + end if; + end if; + + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV10R_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div10rsd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Synchronous Reset and Start Delay +-- /___/ /\ Filename : CLK_DIV10RSD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:17 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV10RSD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV10RSD is + generic ( + DIVIDE_BY : integer := 10; + DIVIDER_DELAY : integer := 1 + ); + port( + CLKDV : out std_ulogic := '0'; + + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV10RSD; + +architecture CLK_DIV10RSD_V of CLK_DIV10RSD is + + signal CLKDV_i : std_ulogic := '0'; + signal CDRST_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN, CDRST) + variable CLOCK_DIVIDER : integer := 0; + variable RESET_WAIT_COUNT : integer := 0; + variable START_WAIT_COUNT : integer := 0; + variable DELAY_RESET : boolean := false; + variable STARTUP : boolean := true; + variable DELAY_START : integer := DIVIDER_DELAY; + variable NO_BITS_REMAINING : integer := 0; + + begin + if (CLKIN'event and CLKIN = '0') then + CDRST_i <= CDRST; + end if; + + if (CLKIN'event and CLKIN = '1') then + + if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true) then + CLKDV_i <= '0'; + CLOCK_DIVIDER := 0; + DELAY_START := 1; + end if; + + if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false) then + NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER); + DELAY_RESET := true; + DELAY_START := DIVIDER_DELAY; + end if; + + if (DELAY_RESET = true) then + RESET_WAIT_COUNT := RESET_WAIT_COUNT + 1; + if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then + CLKDV_i <= '0'; + DELAY_RESET := false; + RESET_WAIT_COUNT := 0; + STARTUP := true; + CLOCK_DIVIDER := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_START = 1) then + START_WAIT_COUNT := START_WAIT_COUNT + 1; + if (START_WAIT_COUNT = DIVIDE_BY+1) then + START_WAIT_COUNT := 0; + DELAY_START := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_START = 0 and DELAY_RESET = false) then + + if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then + CLKDV_i <= '1'; + end if; + + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + STARTUP := false; + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV10RSD_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div10sd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Start Delay +-- /___/ /\ Filename : CLK_DIV10SD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:17 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV10SD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV10SD is + generic ( + DIVIDE_BY : integer := 10; + DIVIDER_DELAY : integer := 1 + ); + + port( + CLKDV : out std_ulogic := '0'; + + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV10SD; + +architecture CLK_DIV10SD_V of CLK_DIV10SD is + + signal CLKDV_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN) + variable START_WAIT_COUNT : integer := 0; + variable CLOCK_DIVIDER : integer := 0; + variable DELAY_START : integer := DIVIDER_DELAY; + + begin + if (CLKIN'event and CLKIN = '1') then + + if (DELAY_START = 1) then + START_WAIT_COUNT := START_WAIT_COUNT + 1; + if (START_WAIT_COUNT = DIVIDE_BY+1) then + DELAY_START := 0; + START_WAIT_COUNT := 0; + end if; + end if; + + if (DELAY_START = 0) then + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV10SD_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div12.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider +-- /___/ /\ Filename : CLK_DIV12.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:17 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV12 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV12 is + generic ( + DIVIDE_BY : integer := 12 + ); + port( + CLKDV : out std_ulogic := '0'; + + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV12; + +architecture CLK_DIV12_V of CLK_DIV12 is + + signal CLKDV_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN) + variable CLOCK_DIVIDER : integer := 0; + + begin + if (CLKIN'event and CLKIN = '1') then + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV12_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div12r.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Synchronous Reset +-- /___/ /\ Filename : CLK_DIV12R.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:17 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV12R ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV12R is + generic ( + DIVIDE_BY : integer := 12 + ); + + port( + CLKDV : out std_ulogic := '0'; + + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV12R; + +architecture CLK_DIV12R_V of CLK_DIV12R is + + signal CLKDV_i : std_ulogic := '0'; + signal CDRST_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN, CDRST) + variable RESET_WAIT_COUNT : integer := 0; + variable CLOCK_DIVIDER : integer := 0; + variable NO_BITS_REMAINING : integer := 0; + variable DELAY_RESET : boolean := false; + variable STARTUP : boolean := true; + + begin + if (CLKIN'event and CLKIN = '0') then + CDRST_i <= CDRST; + end if; + + if (CLKIN'event and CLKIN = '1') then + + if (CDRST_i = '1' and CLKDV_i = '0') then + CLOCK_DIVIDER := 0; + STARTUP := true; + end if; + + if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true then + CLKDV_i <= '0'; + CLOCK_DIVIDER := 0; + end if; + + + if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false then + NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER); + DELAY_RESET := true; + end if; + + if (DELAY_RESET = true) then + RESET_WAIT_COUNT := RESET_WAIT_COUNT + 1; + if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then + CLKDV_i <= '0'; + DELAY_RESET := false; + RESET_WAIT_COUNT := 0; + STARTUP := true; + CLOCK_DIVIDER := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_RESET = false) then + if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then + CLKDV_i <= '1'; + end if; + + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + STARTUP := false; + CLKDV_i <= not CLKDV_i; + CLOCK_DIVIDER := 1; + end if; + end if; + end if; + + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV12R_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div12rsd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Synchronous Reset and Start Delay +-- /___/ /\ Filename : CLK_DIV12RSD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:18 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV12RSD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV12RSD is + generic ( + DIVIDE_BY : integer := 12; + DIVIDER_DELAY : integer := 1 + ); + port( + CLKDV : out std_ulogic := '0'; + CDRST : in std_ulogic := '0'; + + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV12RSD; + +architecture CLK_DIV12RSD_V of CLK_DIV12RSD is + + signal CLKDV_i : std_ulogic := '0'; + signal CDRST_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN, CDRST) + variable CLOCK_DIVIDER : integer := 0; + variable RESET_WAIT_COUNT : integer := 0; + variable START_WAIT_COUNT : integer := 0; + variable DELAY_RESET : boolean := false; + variable STARTUP : boolean := true; + variable DELAY_START : integer := DIVIDER_DELAY; + variable NO_BITS_REMAINING : integer := 0; + + begin + if (CLKIN'event and CLKIN = '0') then + CDRST_i <= CDRST; + end if; + + if (CLKIN'event and CLKIN = '1') then + + if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true) then + CLKDV_i <= '0'; + CLOCK_DIVIDER := 0; + DELAY_START := 1; + end if; + + if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false) then + NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER); + DELAY_RESET := true; + DELAY_START := DIVIDER_DELAY; + end if; + + if (DELAY_RESET = true) then + RESET_WAIT_COUNT := RESET_WAIT_COUNT + 1; + if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then + CLKDV_i <= '0'; + DELAY_RESET := false; + RESET_WAIT_COUNT := 0; + STARTUP := true; + CLOCK_DIVIDER := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_START = 1) then + START_WAIT_COUNT := START_WAIT_COUNT + 1; + if (START_WAIT_COUNT = DIVIDE_BY+1) then + START_WAIT_COUNT := 0; + DELAY_START := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_START = 0 and DELAY_RESET = false) then + + if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then + CLKDV_i <= '1'; + end if; + + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + STARTUP := false; + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV12RSD_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div12sd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Start Delay +-- /___/ /\ Filename : CLK_DIV12SD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:18 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV12SD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV12SD is + generic ( + DIVIDE_BY : integer := 12; + DIVIDER_DELAY : integer := 1 + ); + port( + CLKDV : out std_ulogic := '0'; + + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV12SD; + +architecture CLK_DIV12SD_V of CLK_DIV12SD is + + signal CLKDV_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN) + variable START_WAIT_COUNT : integer := 0; + variable CLOCK_DIVIDER : integer := 0; + variable DELAY_START : integer := DIVIDER_DELAY; + + begin + if (CLKIN'event and CLKIN = '1') then + + if (DELAY_START = 1) then + START_WAIT_COUNT := START_WAIT_COUNT + 1; + if (START_WAIT_COUNT = DIVIDE_BY+1) then + DELAY_START := 0; + START_WAIT_COUNT := 0; + end if; + end if; + + if (DELAY_START = 0) then + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV12SD_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div14.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider +-- /___/ /\ Filename : CLK_DIV14.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:18 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV14 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV14 is + generic ( + DIVIDE_BY : integer := 14 + ); + + port( + CLKDV : out std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV14; + +architecture CLK_DIV14_V of CLK_DIV14 is + + signal CLKDV_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN) + variable CLOCK_DIVIDER : integer := 0; + + begin + if (CLKIN'event and CLKIN = '1') then + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV14_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div14r.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Synchronous Reset +-- /___/ /\ Filename : CLK_DIV14R.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:18 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV14R ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV14R is + generic ( + DIVIDE_BY : integer := 14 + ); + port( + CLKDV : out std_ulogic := '0'; + + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV14R; + +architecture CLK_DIV14R_V of CLK_DIV14R is + + signal CLKDV_i : std_ulogic := '0'; + signal CDRST_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN, CDRST) + variable RESET_WAIT_COUNT : integer := 0; + variable CLOCK_DIVIDER : integer := 0; + variable NO_BITS_REMAINING : integer := 0; + variable DELAY_RESET : boolean := false; + variable STARTUP : boolean := true; + + begin + if (CLKIN'event and CLKIN = '0') then + CDRST_i <= CDRST; + end if; + + if (CLKIN'event and CLKIN = '1') then + + if (CDRST_i = '1' and CLKDV_i = '0') then + CLOCK_DIVIDER := 0; + STARTUP := true; + end if; + + if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true then + CLKDV_i <= '0'; + CLOCK_DIVIDER := 0; + end if; + + + if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false then + NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER); + DELAY_RESET := true; + end if; + + if (DELAY_RESET = true) then + RESET_WAIT_COUNT := RESET_WAIT_COUNT + 1; + if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then + CLKDV_i <= '0'; + DELAY_RESET := false; + RESET_WAIT_COUNT := 0; + STARTUP := true; + CLOCK_DIVIDER := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_RESET = false) then + if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then + CLKDV_i <= '1'; + end if; + + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + STARTUP := false; + CLKDV_i <= not CLKDV_i; + CLOCK_DIVIDER := 1; + end if; + end if; + end if; + + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV14R_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div14rsd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Synchronous Reset and Start Delay +-- /___/ /\ Filename : CLK_DIV14RSD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:18 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV14RSD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV14RSD is + generic ( + DIVIDE_BY : integer := 14; + DIVIDER_DELAY : integer := 1 + ); + + port( + CLKDV : out std_ulogic := '0'; + + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV14RSD; + +architecture CLK_DIV14RSD_V of CLK_DIV14RSD is + + signal CLKDV_i : std_ulogic := '0'; + signal CDRST_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN, CDRST) + variable CLOCK_DIVIDER : integer := 0; + variable RESET_WAIT_COUNT : integer := 0; + variable START_WAIT_COUNT : integer := 0; + variable DELAY_RESET : boolean := false; + variable STARTUP : boolean := true; + variable DELAY_START : integer := DIVIDER_DELAY; + variable NO_BITS_REMAINING : integer := 0; + + begin + if (CLKIN'event and CLKIN = '0') then + CDRST_i <= CDRST; + end if; + + if (CLKIN'event and CLKIN = '1') then + + if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true) then + CLKDV_i <= '0'; + CLOCK_DIVIDER := 0; + DELAY_START := 1; + end if; + + if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false) then + NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER); + DELAY_RESET := true; + DELAY_START := DIVIDER_DELAY; + end if; + + if (DELAY_RESET = true) then + RESET_WAIT_COUNT := RESET_WAIT_COUNT + 1; + if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then + CLKDV_i <= '0'; + DELAY_RESET := false; + RESET_WAIT_COUNT := 0; + STARTUP := true; + CLOCK_DIVIDER := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_START = 1) then + START_WAIT_COUNT := START_WAIT_COUNT + 1; + if (START_WAIT_COUNT = DIVIDE_BY+1) then + START_WAIT_COUNT := 0; + DELAY_START := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_START = 0 and DELAY_RESET = false) then + + if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then + CLKDV_i <= '1'; + end if; + + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + STARTUP := false; + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV14RSD_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div14sd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Start Delay +-- /___/ /\ Filename : CLK_DIV14SD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:18 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV14SD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV14SD is + generic ( + DIVIDE_BY : integer := 14; + DIVIDER_DELAY : integer := 1 + ); + + port( + CLKDV : out std_ulogic := '0'; + + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV14SD; + +architecture CLK_DIV14SD_V of CLK_DIV14SD is + + signal CLKDV_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN) + variable START_WAIT_COUNT : integer := 0; + variable CLOCK_DIVIDER : integer := 0; + variable DELAY_START : integer := DIVIDER_DELAY; + + begin + if (CLKIN'event and CLKIN = '1') then + + if (DELAY_START = 1) then + START_WAIT_COUNT := START_WAIT_COUNT + 1; + if (START_WAIT_COUNT = DIVIDE_BY+1) then + DELAY_START := 0; + START_WAIT_COUNT := 0; + end if; + end if; + + if (DELAY_START = 0) then + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV14SD_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div16.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider +-- /___/ /\ Filename : CLK_DIV16.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:18 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV16 is + generic ( + DIVIDE_BY : integer := 16 + ); + + port( + CLKDV : out std_ulogic := '0'; + + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV16; + +architecture CLK_DIV16_V of CLK_DIV16 is + + signal CLKDV_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN) + variable CLOCK_DIVIDER : integer := 0; + + begin + if (CLKIN'event and CLKIN = '1') then + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV16_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div16r.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Synchronous Reset +-- /___/ /\ Filename : CLK_DIV16R.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:18 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV16R ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV16R is + generic ( + DIVIDE_BY : integer := 16 + ); + port( + CLKDV : out std_ulogic := '0'; + + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV16R; + +architecture CLK_DIV16R_V of CLK_DIV16R is + + signal CLKDV_i : std_ulogic := '0'; + signal CDRST_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN, CDRST) + variable RESET_WAIT_COUNT : integer := 0; + variable CLOCK_DIVIDER : integer := 0; + variable NO_BITS_REMAINING : integer := 0; + variable DELAY_RESET : boolean := false; + variable STARTUP : boolean := true; + + begin + if (CLKIN'event and CLKIN = '0') then + CDRST_i <= CDRST; + end if; + + if (CLKIN'event and CLKIN = '1') then + + if (CDRST_i = '1' and CLKDV_i = '0') then + CLOCK_DIVIDER := 0; + STARTUP := true; + end if; + + if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true then + CLKDV_i <= '0'; + CLOCK_DIVIDER := 0; + end if; + + + if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false then + NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER); + DELAY_RESET := true; + end if; + + if (DELAY_RESET = true) then + RESET_WAIT_COUNT := RESET_WAIT_COUNT + 1; + if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then + CLKDV_i <= '0'; + DELAY_RESET := false; + RESET_WAIT_COUNT := 0; + STARTUP := true; + CLOCK_DIVIDER := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_RESET = false) then + if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then + CLKDV_i <= '1'; + end if; + + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + STARTUP := false; + CLKDV_i <= not CLKDV_i; + CLOCK_DIVIDER := 1; + end if; + end if; + end if; + + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV16R_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div16rsd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Synchronous Reset and Start Delay +-- /___/ /\ Filename : CLK_DIV16RSD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:18 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV16RSD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV16RSD is + generic ( + DIVIDE_BY : integer := 16; + DIVIDER_DELAY : integer := 1 + ); + + port( + CLKDV : out std_ulogic := '0'; + + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV16RSD; + +architecture CLK_DIV16RSD_V of CLK_DIV16RSD is + + signal CLKDV_i : std_ulogic := '0'; + signal CDRST_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN, CDRST) + variable CLOCK_DIVIDER : integer := 0; + variable RESET_WAIT_COUNT : integer := 0; + variable START_WAIT_COUNT : integer := 0; + variable DELAY_RESET : boolean := false; + variable STARTUP : boolean := true; + variable DELAY_START : integer := DIVIDER_DELAY; + variable NO_BITS_REMAINING : integer := 0; + + begin + if (CLKIN'event and CLKIN = '0') then + CDRST_i <= CDRST; + end if; + + if (CLKIN'event and CLKIN = '1') then + + if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true) then + CLKDV_i <= '0'; + CLOCK_DIVIDER := 0; + DELAY_START := 1; + end if; + + if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false) then + NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER); + DELAY_RESET := true; + DELAY_START := DIVIDER_DELAY; + end if; + + if (DELAY_RESET = true) then + RESET_WAIT_COUNT := RESET_WAIT_COUNT + 1; + if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then + CLKDV_i <= '0'; + DELAY_RESET := false; + RESET_WAIT_COUNT := 0; + STARTUP := true; + CLOCK_DIVIDER := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_START = 1) then + START_WAIT_COUNT := START_WAIT_COUNT + 1; + if (START_WAIT_COUNT = DIVIDE_BY+1) then + START_WAIT_COUNT := 0; + DELAY_START := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_START = 0 and DELAY_RESET = false) then + + if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then + CLKDV_i <= '1'; + end if; + + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + STARTUP := false; + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV16RSD_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div16sd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Start Delay +-- /___/ /\ Filename : CLK_DIV16SD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:19 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV16SD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV16SD is + generic ( + DIVIDE_BY : integer := 16; + DIVIDER_DELAY : integer := 1 + ); + port( + CLKDV : out std_ulogic := '0'; + + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV16SD; + +architecture CLK_DIV16SD_V of CLK_DIV16SD is + + signal CLKDV_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN) + variable START_WAIT_COUNT : integer := 0; + variable CLOCK_DIVIDER : integer := 0; + variable DELAY_START : integer := DIVIDER_DELAY; + + begin + if (CLKIN'event and CLKIN = '1') then + + if (DELAY_START = 1) then + START_WAIT_COUNT := START_WAIT_COUNT + 1; + if (START_WAIT_COUNT = DIVIDE_BY+1) then + DELAY_START := 0; + START_WAIT_COUNT := 0; + end if; + end if; + + if (DELAY_START = 0) then + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV16SD_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div2.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider +-- /___/ /\ Filename : CLK_DIV2.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:19 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV2 is + generic ( + DIVIDE_BY : integer := 2 + ); + + port( + CLKDV : out std_ulogic := '0'; + + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV2; + +architecture CLK_DIV2_V of CLK_DIV2 is + + signal CLKDV_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN) + variable CLOCK_DIVIDER : integer := 0; + + begin + if (CLKIN'event and CLKIN = '1') then + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV2_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div2r.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Synchronous Reset +-- /___/ /\ Filename : CLK_DIV2R.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:19 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV2R ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV2R is + generic ( + DIVIDE_BY : integer := 2 + ); + port( + CLKDV : out std_ulogic := '0'; + + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV2R; + +architecture CLK_DIV2R_V of CLK_DIV2R is + + signal CLKDV_i : std_ulogic := '0'; + signal CDRST_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN, CDRST) + variable RESET_WAIT_COUNT : integer := 0; + variable CLOCK_DIVIDER : integer := 0; + variable NO_BITS_REMAINING : integer := 0; + variable DELAY_RESET : boolean := false; + variable STARTUP : boolean := true; + + begin + if (CLKIN'event and CLKIN = '0') then + CDRST_i <= CDRST; + end if; + + if (CLKIN'event and CLKIN = '1') then + + if (CDRST_i = '1' and CLKDV_i = '0') then + CLOCK_DIVIDER := 0; + STARTUP := true; + end if; + + if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true then + CLKDV_i <= '0'; + CLOCK_DIVIDER := 0; + end if; + + + if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false then + NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER); + DELAY_RESET := true; + end if; + + if (DELAY_RESET = true) then + RESET_WAIT_COUNT := RESET_WAIT_COUNT + 1; + if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then + CLKDV_i <= '0'; + DELAY_RESET := false; + RESET_WAIT_COUNT := 0; + STARTUP := true; + CLOCK_DIVIDER := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_RESET = false) then + if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then + CLKDV_i <= '1'; + end if; + + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + STARTUP := false; + CLKDV_i <= not CLKDV_i; + CLOCK_DIVIDER := 1; + end if; + end if; + end if; + + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV2R_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div2rsd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Synchronous Reset and Start Delay +-- /___/ /\ Filename : CLK_DIV2RSD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:19 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV2RSD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV2RSD is + generic ( + DIVIDE_BY : integer := 2; + DIVIDER_DELAY : integer := 1 + ); + + port( + CLKDV : out std_ulogic := '0'; + + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV2RSD; + +architecture CLK_DIV2RSD_V of CLK_DIV2RSD is + + signal CLKDV_i : std_ulogic := '0'; + signal CDRST_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN, CDRST) + variable CLOCK_DIVIDER : integer := 0; + variable RESET_WAIT_COUNT : integer := 0; + variable START_WAIT_COUNT : integer := 0; + variable DELAY_RESET : boolean := false; + variable STARTUP : boolean := true; + variable DELAY_START : integer := DIVIDER_DELAY; + variable NO_BITS_REMAINING : integer := 0; + + begin + if (CLKIN'event and CLKIN = '0') then + CDRST_i <= CDRST; + end if; + + if (CLKIN'event and CLKIN = '1') then + + if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true) then + CLKDV_i <= '0'; + CLOCK_DIVIDER := 0; + DELAY_START := 1; + end if; + + if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false) then + NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER); + DELAY_RESET := true; + DELAY_START := DIVIDER_DELAY; + end if; + + if (DELAY_RESET = true) then + RESET_WAIT_COUNT := RESET_WAIT_COUNT + 1; + if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then + CLKDV_i <= '0'; + DELAY_RESET := false; + RESET_WAIT_COUNT := 0; + STARTUP := true; + CLOCK_DIVIDER := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_START = 1) then + START_WAIT_COUNT := START_WAIT_COUNT + 1; + if (START_WAIT_COUNT = DIVIDE_BY+1) then + START_WAIT_COUNT := 0; + DELAY_START := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_START = 0 and DELAY_RESET = false) then + + if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then + CLKDV_i <= '1'; + end if; + + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + STARTUP := false; + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV2RSD_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div2sd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Start Delay +-- /___/ /\ Filename : CLK_DIV2SD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:19 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV2SD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV2SD is + generic ( + DIVIDE_BY : integer := 2; + DIVIDER_DELAY : integer := 1 + ); + + port( + CLKDV : out std_ulogic := '0'; + + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV2SD; + +architecture CLK_DIV2SD_V of CLK_DIV2SD is + + signal CLKDV_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN) + variable START_WAIT_COUNT : integer := 0; + variable CLOCK_DIVIDER : integer := 0; + variable DELAY_START : integer := DIVIDER_DELAY; + + begin + if (CLKIN'event and CLKIN = '1') then + + if (DELAY_START = 1) then + START_WAIT_COUNT := START_WAIT_COUNT + 1; + if (START_WAIT_COUNT = DIVIDE_BY+1) then + DELAY_START := 0; + START_WAIT_COUNT := 0; + end if; + end if; + + if (DELAY_START = 0) then + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV2SD_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div4.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider +-- /___/ /\ Filename : CLK_DIV4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:19 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV4 is + generic ( + DIVIDE_BY : integer := 4 + ); + + port( + CLKDV : out std_ulogic := '0'; + + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV4; + +architecture CLK_DIV4_V of CLK_DIV4 is + + signal CLKDV_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN) + variable CLOCK_DIVIDER : integer := 0; + + begin + if (CLKIN'event and CLKIN = '1') then + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV4_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div4r.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Synchronous Reset +-- /___/ /\ Filename : CLK_DIV4R.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:19 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV4R ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV4R is + generic ( + DIVIDE_BY : integer := 4 + ); + + port( + CLKDV : out std_ulogic := '0'; + + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV4R; + +architecture CLK_DIV4R_V of CLK_DIV4R is + + signal CLKDV_i : std_ulogic := '0'; + signal CDRST_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN, CDRST) + variable RESET_WAIT_COUNT : integer := 0; + variable CLOCK_DIVIDER : integer := 0; + variable NO_BITS_REMAINING : integer := 0; + variable DELAY_RESET : boolean := false; + variable STARTUP : boolean := true; + + begin + if (CLKIN'event and CLKIN = '0') then + CDRST_i <= CDRST; + end if; + + if (CLKIN'event and CLKIN = '1') then + + if (CDRST_i = '1' and CLKDV_i = '0') then + CLOCK_DIVIDER := 0; + STARTUP := true; + end if; + + if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true then + CLKDV_i <= '0'; + CLOCK_DIVIDER := 0; + end if; + + + if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false then + NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER); + DELAY_RESET := true; + end if; + + if (DELAY_RESET = true) then + RESET_WAIT_COUNT := RESET_WAIT_COUNT + 1; + if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then + CLKDV_i <= '0'; + DELAY_RESET := false; + RESET_WAIT_COUNT := 0; + STARTUP := true; + CLOCK_DIVIDER := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_RESET = false) then + if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then + CLKDV_i <= '1'; + end if; + + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + STARTUP := false; + CLKDV_i <= not CLKDV_i; + CLOCK_DIVIDER := 1; + end if; + end if; + end if; + + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV4R_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div4rsd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Synchronous Reset and Start Delay +-- /___/ /\ Filename : CLK_DIV4RSD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:19 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV4RSD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV4RSD is + generic ( + DIVIDE_BY : integer := 4; + DIVIDER_DELAY : integer := 1 + ); + port( + CLKDV : out std_ulogic := '0'; + CDRST : in std_ulogic := '0'; + + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV4RSD; + +architecture CLK_DIV4RSD_V of CLK_DIV4RSD is + + signal CLKDV_i : std_ulogic := '0'; + signal CDRST_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN, CDRST) + variable CLOCK_DIVIDER : integer := 0; + variable RESET_WAIT_COUNT : integer := 0; + variable START_WAIT_COUNT : integer := 0; + variable DELAY_RESET : boolean := false; + variable STARTUP : boolean := true; + variable DELAY_START : integer := DIVIDER_DELAY; + variable NO_BITS_REMAINING : integer := 0; + + begin + if (CLKIN'event and CLKIN = '0') then + CDRST_i <= CDRST; + end if; + + if (CLKIN'event and CLKIN = '1') then + + if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true) then + CLKDV_i <= '0'; + CLOCK_DIVIDER := 0; + DELAY_START := 1; + end if; + + if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false) then + NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER); + DELAY_RESET := true; + DELAY_START := DIVIDER_DELAY; + end if; + + if (DELAY_RESET = true) then + RESET_WAIT_COUNT := RESET_WAIT_COUNT + 1; + if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then + CLKDV_i <= '0'; + DELAY_RESET := false; + RESET_WAIT_COUNT := 0; + STARTUP := true; + CLOCK_DIVIDER := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_START = 1) then + START_WAIT_COUNT := START_WAIT_COUNT + 1; + if (START_WAIT_COUNT = DIVIDE_BY+1) then + START_WAIT_COUNT := 0; + DELAY_START := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_START = 0 and DELAY_RESET = false) then + + if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then + CLKDV_i <= '1'; + end if; + + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + STARTUP := false; + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV4RSD_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div4sd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Start Delay +-- /___/ /\ Filename : CLK_DIV4SD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:19 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV4SD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV4SD is + generic ( + DIVIDE_BY : integer := 4; + DIVIDER_DELAY : integer := 1 + ); + port( + CLKDV : out std_ulogic := '0'; + + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV4SD; + +architecture CLK_DIV4SD_V of CLK_DIV4SD is + + signal CLKDV_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN) + variable START_WAIT_COUNT : integer := 0; + variable CLOCK_DIVIDER : integer := 0; + variable DELAY_START : integer := DIVIDER_DELAY; + + begin + if (CLKIN'event and CLKIN = '1') then + + if (DELAY_START = 1) then + START_WAIT_COUNT := START_WAIT_COUNT + 1; + if (START_WAIT_COUNT = DIVIDE_BY+1) then + DELAY_START := 0; + START_WAIT_COUNT := 0; + end if; + end if; + + if (DELAY_START = 0) then + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV4SD_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div6.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider +-- /___/ /\ Filename : CLK_DIV6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:20 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV6 is + generic ( + DIVIDE_BY : integer := 6 + ); + + port( + CLKDV : out std_ulogic := '0'; + + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV6; + +architecture CLK_DIV6_V of CLK_DIV6 is + + signal CLKDV_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN) + variable CLOCK_DIVIDER : integer := 0; + + begin + if (CLKIN'event and CLKIN = '1') then + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV6_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div6r.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Synchronous Reset +-- /___/ /\ Filename : CLK_DIV6R.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:20 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV6R ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV6R is + generic ( + DIVIDE_BY : integer := 6 + ); + port( + CLKDV : out std_ulogic := '0'; + + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV6R; + +architecture CLK_DIV6R_V of CLK_DIV6R is + + signal CLKDV_i : std_ulogic := '0'; + signal CDRST_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN, CDRST) + variable RESET_WAIT_COUNT : integer := 0; + variable CLOCK_DIVIDER : integer := 0; + variable NO_BITS_REMAINING : integer := 0; + variable DELAY_RESET : boolean := false; + variable STARTUP : boolean := true; + + begin + if (CLKIN'event and CLKIN = '0') then + CDRST_i <= CDRST; + end if; + + if (CLKIN'event and CLKIN = '1') then + + if (CDRST_i = '1' and CLKDV_i = '0') then + CLOCK_DIVIDER := 0; + STARTUP := true; + end if; + + if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true then + CLKDV_i <= '0'; + CLOCK_DIVIDER := 0; + end if; + + + if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false then + NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER); + DELAY_RESET := true; + end if; + + if (DELAY_RESET = true) then + RESET_WAIT_COUNT := RESET_WAIT_COUNT + 1; + if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then + CLKDV_i <= '0'; + DELAY_RESET := false; + RESET_WAIT_COUNT := 0; + STARTUP := true; + CLOCK_DIVIDER := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_RESET = false) then + if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then + CLKDV_i <= '1'; + end if; + + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + STARTUP := false; + CLKDV_i <= not CLKDV_i; + CLOCK_DIVIDER := 1; + end if; + end if; + end if; + + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV6R_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div6rsd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Synchronous Reset and Start Delay +-- /___/ /\ Filename : CLK_DIV6RSD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:20 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV6RSD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV6RSD is + generic ( + DIVIDE_BY : integer := 6; + DIVIDER_DELAY : integer := 1 + ); + + port( + CLKDV : out std_ulogic := '0'; + + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV6RSD; + +architecture CLK_DIV6RSD_V of CLK_DIV6RSD is + + signal CLKDV_i : std_ulogic := '0'; + signal CDRST_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN, CDRST) + variable CLOCK_DIVIDER : integer := 0; + variable RESET_WAIT_COUNT : integer := 0; + variable START_WAIT_COUNT : integer := 0; + variable DELAY_RESET : boolean := false; + variable STARTUP : boolean := true; + variable DELAY_START : integer := DIVIDER_DELAY; + variable NO_BITS_REMAINING : integer := 0; + + begin + if (CLKIN'event and CLKIN = '0') then + CDRST_i <= CDRST; + end if; + + if (CLKIN'event and CLKIN = '1') then + + if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true) then + CLKDV_i <= '0'; + CLOCK_DIVIDER := 0; + DELAY_START := 1; + end if; + + if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false) then + NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER); + DELAY_RESET := true; + DELAY_START := DIVIDER_DELAY; + end if; + + if (DELAY_RESET = true) then + RESET_WAIT_COUNT := RESET_WAIT_COUNT + 1; + if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then + CLKDV_i <= '0'; + DELAY_RESET := false; + RESET_WAIT_COUNT := 0; + STARTUP := true; + CLOCK_DIVIDER := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_START = 1) then + START_WAIT_COUNT := START_WAIT_COUNT + 1; + if (START_WAIT_COUNT = DIVIDE_BY+1) then + START_WAIT_COUNT := 0; + DELAY_START := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_START = 0 and DELAY_RESET = false) then + + if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then + CLKDV_i <= '1'; + end if; + + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + STARTUP := false; + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV6RSD_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div6sd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Start Delay +-- /___/ /\ Filename : CLK_DIV6SD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:20 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV6SD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV6SD is + generic ( + DIVIDE_BY : integer := 6; + DIVIDER_DELAY : integer := 1 + ); + + port( + CLKDV : out std_ulogic := '0'; + + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV6SD; + +architecture CLK_DIV6SD_V of CLK_DIV6SD is + + signal CLKDV_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN) + variable START_WAIT_COUNT : integer := 0; + variable CLOCK_DIVIDER : integer := 0; + variable DELAY_START : integer := DIVIDER_DELAY; + + begin + if (CLKIN'event and CLKIN = '1') then + + if (DELAY_START = 1) then + START_WAIT_COUNT := START_WAIT_COUNT + 1; + if (START_WAIT_COUNT = DIVIDE_BY+1) then + DELAY_START := 0; + START_WAIT_COUNT := 0; + end if; + end if; + + if (DELAY_START = 0) then + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV6SD_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div8.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider +-- /___/ /\ Filename : CLK_DIV8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:20 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV8 is + generic ( + DIVIDE_BY : integer := 8 + ); + + port( + CLKDV : out std_ulogic := '0'; + + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV8; + +architecture CLK_DIV8_V of CLK_DIV8 is + + signal CLKDV_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN) + variable CLOCK_DIVIDER : integer := 0; + + begin + if (CLKIN'event and CLKIN = '1') then + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV8_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div8r.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Synchronous Reset +-- /___/ /\ Filename : CLK_DIV8R.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:20 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV8R ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV8R is + generic ( + DIVIDE_BY : integer := 8 + ); + + port( + CLKDV : out std_ulogic := '0'; + + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV8R; + +architecture CLK_DIV8R_V of CLK_DIV8R is + + signal CLKDV_i : std_ulogic := '0'; + signal CDRST_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN, CDRST) + variable RESET_WAIT_COUNT : integer := 0; + variable CLOCK_DIVIDER : integer := 0; + variable NO_BITS_REMAINING : integer := 0; + variable DELAY_RESET : boolean := false; + variable STARTUP : boolean := true; + + begin + if (CLKIN'event and CLKIN = '0') then + CDRST_i <= CDRST; + end if; + + if (CLKIN'event and CLKIN = '1') then + + if (CDRST_i = '1' and CLKDV_i = '0') then + CLOCK_DIVIDER := 0; + STARTUP := true; + end if; + + if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true then + CLKDV_i <= '0'; + CLOCK_DIVIDER := 0; + end if; + + + if CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false then + NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER); + DELAY_RESET := true; + end if; + + if (DELAY_RESET = true) then + RESET_WAIT_COUNT := RESET_WAIT_COUNT + 1; + if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then + CLKDV_i <= '0'; + DELAY_RESET := false; + RESET_WAIT_COUNT := 0; + STARTUP := true; + CLOCK_DIVIDER := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_RESET = false) then + if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then + CLKDV_i <= '1'; + end if; + + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + STARTUP := false; + CLKDV_i <= not CLKDV_i; + CLOCK_DIVIDER := 1; + end if; + end if; + end if; + + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV8R_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div8rsd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Synchronous Reset and Start Delay +-- /___/ /\ Filename : CLK_DIV8RSD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:20 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV8RSD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV8RSD is + generic ( + DIVIDE_BY : integer := 8; + DIVIDER_DELAY : integer := 1 + ); + + port( + CLKDV : out std_ulogic := '0'; + + CDRST : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV8RSD; + +architecture CLK_DIV8RSD_V of CLK_DIV8RSD is + + signal CLKDV_i : std_ulogic := '0'; + signal CDRST_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN, CDRST) + variable CLOCK_DIVIDER : integer := 0; + variable RESET_WAIT_COUNT : integer := 0; + variable START_WAIT_COUNT : integer := 0; + variable DELAY_RESET : boolean := false; + variable STARTUP : boolean := true; + variable DELAY_START : integer := DIVIDER_DELAY; + variable NO_BITS_REMAINING : integer := 0; + + begin + if (CLKIN'event and CLKIN = '0') then + CDRST_i <= CDRST; + end if; + + if (CLKIN'event and CLKIN = '1') then + + if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = true) then + CLKDV_i <= '0'; + CLOCK_DIVIDER := 0; + DELAY_START := 1; + end if; + + if (CDRST_i = '1' and CLKDV_i = '1' and STARTUP = false) then + NO_BITS_REMAINING := ((DIVIDE_BY/2 + 1) - CLOCK_DIVIDER); + DELAY_RESET := true; + DELAY_START := DIVIDER_DELAY; + end if; + + if (DELAY_RESET = true) then + RESET_WAIT_COUNT := RESET_WAIT_COUNT + 1; + if (RESET_WAIT_COUNT = NO_BITS_REMAINING) then + CLKDV_i <= '0'; + DELAY_RESET := false; + RESET_WAIT_COUNT := 0; + STARTUP := true; + CLOCK_DIVIDER := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_START = 1) then + START_WAIT_COUNT := START_WAIT_COUNT + 1; + if (START_WAIT_COUNT = DIVIDE_BY+1) then + START_WAIT_COUNT := 0; + DELAY_START := 0; + end if; + end if; + + if (CDRST_i = '0' and DELAY_START = 0 and DELAY_RESET = false) then + + if ((CLOCK_DIVIDER = 0) and (STARTUP = true)) then + CLKDV_i <= '1'; + end if; + + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + STARTUP := false; + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV8RSD_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/clk_div8sd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Divider with Start Delay +-- /___/ /\ Filename : CLK_DIV8SD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:20 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CLK_DIV8SD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CLK_DIV8SD is + generic ( + DIVIDE_BY : integer := 8; + DIVIDER_DELAY : integer := 1 + ); + port( + CLKDV : out std_ulogic := '0'; + + CLKIN : in std_ulogic := '0' + ); +end CLK_DIV8SD; + +architecture CLK_DIV8SD_V of CLK_DIV8SD is + + signal CLKDV_i : std_ulogic := '0'; + +begin + + CLOCK_DIVIDE : process (CLKIN) + variable START_WAIT_COUNT : integer := 0; + variable CLOCK_DIVIDER : integer := 0; + variable DELAY_START : integer := DIVIDER_DELAY; + + begin + if (CLKIN'event and CLKIN = '1') then + + if (DELAY_START = 1) then + START_WAIT_COUNT := START_WAIT_COUNT + 1; + if (START_WAIT_COUNT = DIVIDE_BY+1) then + DELAY_START := 0; + START_WAIT_COUNT := 0; + end if; + end if; + + if (DELAY_START = 0) then + CLOCK_DIVIDER := CLOCK_DIVIDER + 1; + if (CLOCK_DIVIDER = (DIVIDE_BY/2 + 1)) then + CLOCK_DIVIDER := 1; + CLKDV_i <= not CLKDV_i; + end if; + end if; + + end if; + end process; + + CLKDV <= CLKDV_i; + +end CLK_DIV8SD_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/fdcpx1.vhd,v 1.2 2005/07/23 00:43:54 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / D Flip-Flop with Asynchronous Clear and Preset +-- /___/ /\ Filename : FDCPX1.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:22 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 07/23/05 -- Removed INIT to match verilog +-- End Revision + +----- CELL FDCPX1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FDCPX1 is + port( + Q : out std_ulogic; + + C : in std_ulogic; + CLR : in std_ulogic; + D : in std_ulogic; + PRE : in std_ulogic + ); +end FDCPX1; + +architecture FDCPX1_V of FDCPX1 is +begin + VITALBehavior : process(C, CLR, PRE) + variable FIRST_TIME : boolean := true ; + begin + + if (FIRST_TIME = true) then + Q <= '0'; + FIRST_TIME := false; + end if; + + if (CLR = '1') then + Q <= '0'; + elsif (PRE = '1') then + Q <= '1'; + elsif (rising_edge(C)) then + Q <= D after 100 ps; + end if; + end process; +end FDCPX1_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/fdd.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Dual Edge Triggered D Flip-Flop +-- /___/ /\ Filename : FDD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:22 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity FDD is + generic( + TimingChecksOn: Boolean := TRUE; + InstancePath: STRING := "*"; + Xon: Boolean := True; + MsgOn: Boolean := False; + INIT : bit := '0' ; + tpd_C_Q : VitalDelayType01 := (0.1 ns, 0.1 ns); + tsetup_D_C_posedge_posedge : VitalDelayType := 0.000 ns; + tsetup_D_C_negedge_posedge : VitalDelayType := 0.000 ns; + thold_D_C_posedge_posedge : VitalDelayType := 0.000 ns; + thold_D_C_negedge_posedge : VitalDelayType := 0.000 ns; + tpw_C_posedge : VitalDelayType := 0.000 ns; + tpw_C_negedge : VitalDelayType := 0.000 ns; + tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns) + ); + + port( + Q : out STD_ULOGIC; + + C : in STD_ULOGIC; + D : in STD_ULOGIC + ); +attribute VITAL_LEVEL0 of FDD : entity is TRUE; +end FDD; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library UNISIM; +use unisim.VPKG.all; +architecture FDD_V of FDD is + --attribute VITAL_LEVEL1 of FDD_V : architecture is TRUE; + + SIGNAL D_ipd : STD_ULOGIC := 'X'; + SIGNAL C_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (D_ipd, D, tipd_D); + VitalWireDelay (C_ipd, C, tipd_C); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process + + -- timing check results + VARIABLE Tviol_D_C_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_D_C_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Pviol_C : STD_ULOGIC := '0'; + VARIABLE PInfo_C : VitalPeriodDataType := VitalPeriodDataInit; + + -- functionality results + VARIABLE Violation : STD_ULOGIC := '0'; + VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); + VARIABLE D_delayed : STD_ULOGIC := 'X'; + VARIABLE C_delayed : STD_ULOGIC := 'X'; + --VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + VARIABLE Q_zd : STD_ULOGIC := TO_X01(INIT); + VARIABLE FIRST_TIME : boolean := True ; + + -- output glitch detection variables + VARIABLE Q_GlitchData : VitalGlitchDataType; + + begin + + if (FIRST_TIME = TRUE) then + + Q <= Q_zd ; + + wait until (rising_edge(c_ipd) ); + + C_delayed := C_ipd'last_value; + D_delayed := D_ipd; + + + FIRST_TIME := FALSE; + end if; + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_D_C_posedge, + TimingData => Tmkr_D_C_posedge, + TestSignal => D_ipd, + TestSignalName => "D", + TestDelay => 0 ns, + RefSignal => C_ipd, + RefSignalName => "C", + RefDelay => 0 ns, + SetupHigh => tsetup_D_C_posedge_posedge, + SetupLow => tsetup_D_C_negedge_posedge, + HoldLow => thold_D_C_posedge_posedge, + HoldHigh => thold_D_C_negedge_posedge, + CheckEnabled => + TRUE, + RefTransition => 'R', + HeaderMsg => InstancePath & "/FDD", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalPeriodPulseCheck ( + Violation => Pviol_C, + PeriodData => PInfo_C, + TestSignal => C_ipd, + TestSignalName => "C", + TestDelay => 0 ns, + Period => 0 ns, + PulseWidthHigh => tpw_C_posedge, + PulseWidthLow => tpw_C_negedge, + CheckEnabled => TRUE, + HeaderMsg => InstancePath &"/FDD", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + end if; + + ------------------------- + -- Functionality Section + ------------------------- + Violation := Tviol_D_C_posedge or Pviol_C; + VitalStateTable( + Result => Q_zd, + PreviousDataIn => PrevData_Q, + StateTable => FDD_Q_tab, + DataIn => ( + C_delayed, D_delayed, C_ipd)); + Q_zd := Violation XOR Q_zd; + D_delayed := D_ipd; + C_delayed := C_ipd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => Q, + GlitchData => Q_GlitchData, + OutSignalName => "Q", + OutTemp => Q_zd, + Paths => (0 => (C_ipd'last_event, tpd_C_Q, TRUE)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + + wait on D_ipd, C_ipd; +end process; + +end FDD_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/fddc.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Dual Edge Triggered D Flip-Flop with Asynchronous Clear +-- /___/ /\ Filename : FDDC.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:22 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDDC ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity FDDC is + generic( + TimingChecksOn: Boolean := TRUE; + InstancePath: STRING := "*"; + Xon: Boolean := True; + MsgOn: Boolean := False; + INIT : bit := '0' ; + tpd_CLR_Q : VitalDelayType01 := (0.000 ns, 0.000 ns); + tpd_C_Q : VitalDelayType01 := (0.1 ns, 0.1 ns); + tsetup_D_C_posedge_posedge : VitalDelayType := 0.000 ns; + tsetup_D_C_negedge_posedge : VitalDelayType := 0.000 ns; + thold_D_C_posedge_posedge : VitalDelayType := 0.000 ns; + thold_D_C_negedge_posedge : VitalDelayType := 0.000 ns; + trecovery_CLR_C_negedge_posedge : VitalDelayType := 0.000 ns; + thold_CLR_C_negedge_posedge : VitalDelayType := 0.000 ns; + tpw_C_posedge : VitalDelayType := 0.000 ns; + tpw_CLR_posedge : VitalDelayType := 0.000 ns; + tpw_C_negedge : VitalDelayType := 0.000 ns; + tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns) + ); + + port( + Q : out STD_ULOGIC; + + C : in STD_ULOGIC; + CLR : in STD_ULOGIC; + D : in STD_ULOGIC + ); +attribute VITAL_LEVEL0 of FDDC : entity is TRUE; +end FDDC; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library UNISIM; +use unisim.VPKG.all; +architecture FDDC_V of FDDC is + --attribute VITAL_LEVEL1 of FDDC_V : architecture is TRUE; + + SIGNAL D_ipd : STD_ULOGIC := 'X'; + SIGNAL C_ipd : STD_ULOGIC := 'X'; + SIGNAL CLR_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (D_ipd, D, tipd_D); + VitalWireDelay (C_ipd, C, tipd_C); + VitalWireDelay (CLR_ipd, CLR, tipd_CLR); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process + + -- timing check results + VARIABLE Tviol_D_C_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_D_C_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Tviol_CLR_C_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_CLR_C_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Pviol_C : STD_ULOGIC := '0'; + VARIABLE PInfo_C : VitalPeriodDataType := VitalPeriodDataInit; + VARIABLE Pviol_CLR : STD_ULOGIC := '0'; + VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; + + -- functionality results + VARIABLE Violation : STD_ULOGIC := '0'; + VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); + VARIABLE D_delayed : STD_ULOGIC := 'X'; + VARIABLE C_delayed : STD_ULOGIC := 'X'; + --VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + VARIABLE Q_zd : STD_ULOGIC := TO_X01(INIT); + VARIABLE FIRST_TIME : boolean := True ; + + -- output glitch detection variables + VARIABLE Q_GlitchData : VitalGlitchDataType; + + begin + + + if (FIRST_TIME = TRUE) then + + Q <= Q_zd; + + wait until (CLR_ipd = '1' or rising_edge(c_ipd)); + + C_delayed := C_ipd'last_value; + D_delayed := D_ipd; + + + FIRST_TIME := FALSE; + end if; + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_D_C_posedge, + TimingData => Tmkr_D_C_posedge, + TestSignal => D_ipd, + TestSignalName => "D", + TestDelay => 0 ns, + RefSignal => C_ipd, + RefSignalName => "C", + RefDelay => 0 ns, + SetupHigh => tsetup_D_C_posedge_posedge, + SetupLow => tsetup_D_C_negedge_posedge, + HoldLow => thold_D_C_posedge_posedge, + HoldHigh => thold_D_C_negedge_posedge, + CheckEnabled => + TO_X01((NOT CLR_ipd)) /= '0', + RefTransition => 'R', + HeaderMsg => InstancePath & "/FDDC", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLR_C_posedge, + TimingData => Tmkr_CLR_C_posedge, + TestSignal => CLR_ipd, + TestSignalName => "CLR", + TestDelay => 0 ns, + RefSignal => C_ipd, + RefSignalName => "C", + RefDelay => 0 ns, + Recovery => trecovery_CLR_C_negedge_posedge, + Removal => thold_CLR_C_negedge_posedge, + ActiveLow => FALSE, + CheckEnabled => + TO_X01(CLR_ipd ) /= '1', + RefTransition => 'R', + HeaderMsg => InstancePath & "/FDDC", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalPeriodPulseCheck ( + Violation => Pviol_C, + PeriodData => PInfo_C, + TestSignal => C_ipd, + TestSignalName => "C", + TestDelay => 0 ns, + Period => 0 ns, + PulseWidthHigh => tpw_C_posedge, + PulseWidthLow => tpw_C_negedge, + CheckEnabled => TRUE, + HeaderMsg => InstancePath &"/FDDC", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalPeriodPulseCheck ( + Violation => Pviol_CLR, + PeriodData => PInfo_CLR, + TestSignal => CLR_ipd, + TestSignalName => "CLR", + TestDelay => 0 ns, + Period => 0 ns, + PulseWidthHigh => tpw_CLR_posedge, + PulseWidthLow => 0 ns, + CheckEnabled => TRUE, + HeaderMsg => InstancePath &"/FDDC", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + end if; + + ------------------------- + -- Functionality Section + ------------------------- + Violation := Tviol_D_C_posedge or Tviol_CLR_C_posedge or Pviol_C or Pviol_CLR; + VitalStateTable( + Result => Q_zd, + PreviousDataIn => PrevData_Q, + StateTable => FDDC_Q_tab, + DataIn => ( + C_delayed, D_delayed, C_ipd, CLR_ipd)); + Q_zd := Violation XOR Q_zd; + D_delayed := D_ipd; + C_delayed := C_ipd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => Q, + GlitchData => Q_GlitchData, + OutSignalName => "Q", + OutTemp => Q_zd, + Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), + 1 => (C_ipd'last_event, tpd_C_Q, TRUE)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + + wait on D_ipd, C_ipd, CLR_ipd; +end process; + +end FDDC_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/fddce.vhd,v 1.2 2005/07/23 00:43:54 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Dual Edge Triggered D Flip-Flop with Asynchronous Clear and Clock Enable +-- /___/ /\ Filename : FDDCE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:23 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 07/23/05 -- Removed INIT to match verilog +-- End Revision + +----- CELL FDDCE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity FDDCE is + generic( + TimingChecksOn: Boolean := TRUE; + InstancePath: STRING := "*"; + Xon: Boolean := True; + MsgOn: Boolean := False; + tpd_CLR_Q : VitalDelayType01 := (0.000 ns, 0.000 ns); + tpd_C_Q : VitalDelayType01 := (0.1 ns, 0.1 ns); + tsetup_D_C_posedge_posedge : VitalDelayType := 0.000 ns; + tsetup_D_C_negedge_posedge : VitalDelayType := 0.000 ns; + thold_D_C_posedge_posedge : VitalDelayType := 0.000 ns; + thold_D_C_negedge_posedge : VitalDelayType := 0.000 ns; + tsetup_CE_C_posedge_posedge : VitalDelayType := 0.000 ns; + tsetup_CE_C_negedge_posedge : VitalDelayType := 0.000 ns; + thold_CE_C_posedge_posedge : VitalDelayType := 0.000 ns; + thold_CE_C_negedge_posedge : VitalDelayType := 0.000 ns; + trecovery_CLR_C_negedge_posedge : VitalDelayType := 0.000 ns; + thold_CLR_C_negedge_posedge : VitalDelayType := 0.000 ns; + tpw_C_posedge : VitalDelayType := 0.000 ns; + tpw_CLR_posedge : VitalDelayType := 0.000 ns; + tpw_C_negedge : VitalDelayType := 0.000 ns; + tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_CE : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + Q : out STD_ULOGIC; + + C : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLR : in STD_ULOGIC; + D : in STD_ULOGIC + ); +attribute VITAL_LEVEL0 of FDDCE : entity is TRUE; +end FDDCE; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library UNISIM; +use unisim.VPKG.all; +architecture FDDCE_V of FDDCE is + --attribute VITAL_LEVEL1 of FDDCE_V : architecture is TRUE; + + SIGNAL D_ipd : STD_ULOGIC := 'X'; + SIGNAL C_ipd : STD_ULOGIC := 'X'; + SIGNAL CE_ipd : STD_ULOGIC := 'X'; + SIGNAL CLR_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (D_ipd, D, tipd_D); + VitalWireDelay (C_ipd, C, tipd_C); + VitalWireDelay (CE_ipd, CE, tipd_CE); + VitalWireDelay (CLR_ipd, CLR, tipd_CLR); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process + + -- timing check results + VARIABLE Tviol_D_C_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_D_C_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Tviol_CE_C_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_CE_C_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Tviol_CLR_C_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_CLR_C_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Pviol_C : STD_ULOGIC := '0'; + VARIABLE PInfo_C : VitalPeriodDataType := VitalPeriodDataInit; + VARIABLE Pviol_CLR : STD_ULOGIC := '0'; + VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; + + -- functionality results + VARIABLE Violation : STD_ULOGIC := '0'; + VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); + VARIABLE D_delayed : STD_ULOGIC := 'X'; + VARIABLE C_delayed : STD_ULOGIC := 'X'; + VARIABLE CE_delayed : STD_ULOGIC := 'X'; + --VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + --ALIAS Q_zd : STD_LOGIC is Results(1); +-- variable Q_zd : STD_ULOGIC := TO_X01(INIT); + variable Q_zd : STD_ULOGIC := '0'; + VARIABLE FIRST_TIME : boolean := True ; + + -- output glitch detection variables + VARIABLE Q_GlitchData : VitalGlitchDataType; + + begin + + if (FIRST_TIME = TRUE) then + + Q <= '0'; + + wait until (CLR_ipd = '1' or rising_edge(c_ipd )); + CE_delayed := CE_ipd; + D_delayed := D_ipd; + C_delayed := C_ipd'last_value; + + FIRST_TIME := FALSE; + end if; + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_D_C_posedge, + TimingData => Tmkr_D_C_posedge, + TestSignal => D_ipd, + TestSignalName => "D", + TestDelay => 0 ns, + RefSignal => C_ipd, + RefSignalName => "C", + RefDelay => 0 ns, + SetupHigh => tsetup_D_C_posedge_posedge, + SetupLow => tsetup_D_C_negedge_posedge, + HoldLow => thold_D_C_posedge_posedge, + HoldHigh => thold_D_C_negedge_posedge, + CheckEnabled => + TO_X01(((NOT CLR_ipd)) AND (CE_ipd)) /= '0', + RefTransition => 'R', + HeaderMsg => InstancePath & "/FDDCE", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalSetupHoldCheck ( + Violation => Tviol_CE_C_posedge, + TimingData => Tmkr_CE_C_posedge, + TestSignal => CE_ipd, + TestSignalName => "CE", + TestDelay => 0 ns, + RefSignal => C_ipd, + RefSignalName => "C", + RefDelay => 0 ns, + SetupHigh => tsetup_CE_C_posedge_posedge, + SetupLow => tsetup_CE_C_negedge_posedge, + HoldLow => thold_CE_C_posedge_posedge, + HoldHigh => thold_CE_C_negedge_posedge, + CheckEnabled => + TO_X01(((NOT CLR_ipd)) AND ((Q_zd) XOR (D_ipd))) + /= '0', + RefTransition => 'R', + HeaderMsg => InstancePath & "/FDDCE", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLR_C_posedge, + TimingData => Tmkr_CLR_C_posedge, + TestSignal => CLR_ipd, + TestSignalName => "CLR", + TestDelay => 0 ns, + RefSignal => C_ipd, + RefSignalName => "C", + RefDelay => 0 ns, + Recovery => trecovery_CLR_C_negedge_posedge, + Removal => thold_CLR_C_negedge_posedge, + ActiveLow => FALSE, + CheckEnabled => + TO_X01(CE_ipd) /= '0', + RefTransition => 'R', + HeaderMsg => InstancePath & "/FDDCE", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalPeriodPulseCheck ( + Violation => Pviol_C, + PeriodData => PInfo_C, + TestSignal => C_ipd, + TestSignalName => "C", + TestDelay => 0 ns, + Period => 0 ns, + PulseWidthHigh => tpw_C_posedge, + PulseWidthLow => tpw_C_negedge, + CheckEnabled => TRUE, + HeaderMsg => InstancePath &"/FDDCE", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalPeriodPulseCheck ( + Violation => Pviol_CLR, + PeriodData => PInfo_CLR, + TestSignal => CLR_ipd, + TestSignalName => "CLR", + TestDelay => 0 ns, + Period => 0 ns, + PulseWidthHigh => tpw_CLR_posedge, + PulseWidthLow => 0 ns, + CheckEnabled => TRUE, + HeaderMsg => InstancePath &"/FDDCE", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + end if; + + ------------------------- + -- Functionality Section + ------------------------- + Violation := Tviol_D_C_posedge or Tviol_CLR_C_posedge or Pviol_C or Tviol_CE_C_posedge or Pviol_CLR; + VitalStateTable( + Result => Q_zd, + PreviousDataIn => PrevData_Q, + StateTable => FDDCE_Q_tab, + DataIn => ( + C_delayed, Q_zd, D_delayed, CE_delayed, C_ipd, CLR_ipd)); + Q_zd := Violation XOR Q_zd; + D_delayed := D_ipd; + C_delayed := C_ipd; + CE_delayed := CE_ipd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => Q, + GlitchData => Q_GlitchData, + OutSignalName => "Q", + OutTemp => Q_zd, + Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), + 1 => (C_ipd'last_event, tpd_C_Q, TRUE)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + + wait on D_ipd, C_ipd, CE_ipd, CLR_ipd; +end process; + +end FDDCE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/fddcp.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Dual Edge Triggered D Flip-Flop with Asynchronous Clear and Preset +-- /___/ /\ Filename : FDDCP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:23 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDDCP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity FDDCP is + generic( + TimingChecksOn: Boolean := TRUE; + InstancePath: STRING := "*"; + Xon: Boolean := True; + MsgOn: Boolean := False; + INIT : bit := '0' ; + tpd_CLR_Q : VitalDelayType01 := (0.000 ns, 0.000 ns); + tpd_PRE_Q : VitalDelayType01 := (0.000 ns, 0.000 ns); + tpd_C_Q : VitalDelayType01 := (0.1 ns, 0.1 ns); + tsetup_D_C_posedge_posedge : VitalDelayType := 0.000 ns; + tsetup_D_C_negedge_posedge : VitalDelayType := 0.000 ns; + thold_D_C_posedge_posedge : VitalDelayType := 0.000 ns; + thold_D_C_negedge_posedge : VitalDelayType := 0.000 ns; + trecovery_CLR_C_negedge_posedge : VitalDelayType := 0.000 ns; + thold_CLR_C_negedge_posedge : VitalDelayType := 0.000 ns; + trecovery_PRE_C_negedge_posedge : VitalDelayType := 0.000 ns; + thold_PRE_C_negedge_posedge : VitalDelayType := 0.000 ns; + tpw_C_posedge : VitalDelayType := 0.000 ns; + tpw_CLR_posedge : VitalDelayType := 0.000 ns; + tpw_PRE_posedge : VitalDelayType := 0.000 ns; + tpw_C_negedge : VitalDelayType := 0.000 ns; + tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + Q : out STD_ULOGIC; + + C : in STD_ULOGIC; + CLR : in STD_ULOGIC; + D : in STD_ULOGIC; + PRE : in STD_ULOGIC + ); +attribute VITAL_LEVEL0 of FDDCP : entity is TRUE; +end FDDCP; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library UNISIM; +use unisim.VPKG.all; +architecture FDDCP_V of FDDCP is + --attribute VITAL_LEVEL1 of FDDCP_V : architecture is TRUE; + + SIGNAL D_ipd : STD_ULOGIC := 'X'; + SIGNAL C_ipd : STD_ULOGIC := 'X'; + SIGNAL CLR_ipd : STD_ULOGIC := 'X'; + SIGNAL PRE_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (D_ipd, D, tipd_D); + VitalWireDelay (C_ipd, C, tipd_C); + VitalWireDelay (CLR_ipd, CLR, tipd_CLR); + VitalWireDelay (PRE_ipd, PRE, tipd_PRE); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process + + -- timing check results + VARIABLE Tviol_D_C_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_D_C_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Tviol_CLR_C_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_CLR_C_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Tviol_PRE_C_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_PRE_C_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Pviol_C : STD_ULOGIC := '0'; + VARIABLE PInfo_C : VitalPeriodDataType := VitalPeriodDataInit; + VARIABLE Pviol_CLR : STD_ULOGIC := '0'; + VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; + VARIABLE Pviol_PRE : STD_ULOGIC := '0'; + VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; + + -- functionality results + VARIABLE Violation : STD_ULOGIC := '0'; + VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); + VARIABLE D_delayed : STD_ULOGIC := 'X'; + VARIABLE C_delayed : STD_ULOGIC := 'X'; + --VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + --ALIAS Q_zd : STD_LOGIC is Results(1); + variable Q_zd : STD_ULOGIC := TO_X01(INIT); + VARIABLE FIRST_TIME : boolean := True ; + + -- output glitch detection variables + VARIABLE Q_GlitchData : VitalGlitchDataType; + + begin + + if (FIRST_TIME = TRUE) then + + Q <= Q_zd; + + wait until (CLR_ipd = '1' or PRE_ipd = '1' or rising_edge(c_ipd)); + C_delayed := C_ipd'last_value; + D_delayed := D_ipd; + + FIRST_TIME := FALSE; + end if; + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_D_C_posedge, + TimingData => Tmkr_D_C_posedge, + TestSignal => D_ipd, + TestSignalName => "D", + TestDelay => 0 ns, + RefSignal => C_ipd, + RefSignalName => "C", + RefDelay => 0 ns, + SetupHigh => tsetup_D_C_posedge_posedge, + SetupLow => tsetup_D_C_negedge_posedge, + HoldLow => thold_D_C_posedge_posedge, + HoldHigh => thold_D_C_negedge_posedge, + CheckEnabled => + TO_X01(((NOT PRE_ipd)) AND ((NOT CLR_ipd))) /= '0', + RefTransition => 'R', + HeaderMsg => InstancePath & "/FDDCP", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLR_C_posedge, + TimingData => Tmkr_CLR_C_posedge, + TestSignal => CLR_ipd, + TestSignalName => "CLR", + TestDelay => 0 ns, + RefSignal => C_ipd, + RefSignalName => "C", + RefDelay => 0 ns, + Recovery => trecovery_CLR_C_negedge_posedge, + Removal => thold_CLR_C_negedge_posedge, + ActiveLow => FALSE, + CheckEnabled => + TO_X01((NOT PRE_ipd)) /= '0', + RefTransition => 'R', + HeaderMsg => InstancePath & "/FDDCP", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalRecoveryRemovalCheck ( + Violation => Tviol_PRE_C_posedge, + TimingData => Tmkr_PRE_C_posedge, + TestSignal => PRE_ipd, + TestSignalName => "PRE", + TestDelay => 0 ns, + RefSignal => C_ipd, + RefSignalName => "C", + RefDelay => 0 ns, + Recovery => trecovery_PRE_C_negedge_posedge, + Removal => thold_PRE_C_negedge_posedge, + ActiveLow => FALSE, + CheckEnabled => + TO_X01((NOT CLR_ipd)) /= '0', + RefTransition => 'R', + HeaderMsg => InstancePath & "/FDDCP", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalPeriodPulseCheck ( + Violation => Pviol_C, + PeriodData => PInfo_C, + TestSignal => C_ipd, + TestSignalName => "C", + TestDelay => 0 ns, + Period => 0 ns, + PulseWidthHigh => tpw_C_posedge, + PulseWidthLow => tpw_C_negedge, + CheckEnabled => TRUE, + HeaderMsg => InstancePath &"/FDDCP", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalPeriodPulseCheck ( + Violation => Pviol_CLR, + PeriodData => PInfo_CLR, + TestSignal => CLR_ipd, + TestSignalName => "CLR", + TestDelay => 0 ns, + Period => 0 ns, + PulseWidthHigh => tpw_CLR_posedge, + PulseWidthLow => 0 ns, + CheckEnabled => TRUE, + HeaderMsg => InstancePath &"/FDDCP", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalPeriodPulseCheck ( + Violation => Pviol_PRE, + PeriodData => PInfo_PRE, + TestSignal => PRE_ipd, + TestSignalName => "PRE", + TestDelay => 0 ns, + Period => 0 ns, + PulseWidthHigh => tpw_PRE_posedge, + PulseWidthLow => 0 ns, + CheckEnabled => TRUE, + HeaderMsg => InstancePath &"/FDDCP", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + end if; + + ------------------------- + -- Functionality Section + ------------------------- + Violation := Tviol_D_C_posedge or Tviol_CLR_C_posedge or Tviol_PRE_C_posedge or Pviol_PRE or Pviol_C or Pviol_CLR; + VitalStateTable( + Result => Q_zd, + PreviousDataIn => PrevData_Q, + StateTable => FDDCP_Q_tab, + DataIn => ( + C_delayed, D_delayed, PRE_ipd, C_ipd, CLR_ipd)); + Q_zd := Violation XOR Q_zd; + D_delayed := D_ipd; + C_delayed := C_ipd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => Q, + GlitchData => Q_GlitchData, + OutSignalName => "Q", + OutTemp => Q_zd, + Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), + 1 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), + 2 => (C_ipd'last_event, tpd_C_Q, TRUE)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + + wait on D_ipd, C_ipd, CLR_ipd, PRE_ipd; +end process; + +end FDDCP_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/fddcpe.vhd,v 1.2 2005/07/23 00:43:54 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Dual Edge Triggered D Flip-Flop with Asynchronous Clear and Preset and Clock Enable +-- /___/ /\ Filename : FDDCPE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:23 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 07/23/05 -- Removed INIT to match verilog +-- End Revision + +----- CELL FDDCPE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity FDDCPE is + generic( + TimingChecksOn: Boolean := TRUE; + InstancePath: STRING := "*"; + Xon: Boolean := True; + MsgOn: Boolean := False; + tpd_PRE_Q : VitalDelayType01 := (0.000 ns, 0.000 ns); + tpd_CLR_Q : VitalDelayType01 := (0.000 ns, 0.000 ns); + tpd_C_Q : VitalDelayType01 := (0.1 ns, 0.1 ns); + tsetup_D_C_posedge_posedge : VitalDelayType := 0.000 ns; + tsetup_D_C_negedge_posedge : VitalDelayType := 0.000 ns; + thold_D_C_posedge_posedge : VitalDelayType := 0.000 ns; + thold_D_C_negedge_posedge : VitalDelayType := 0.000 ns; + tsetup_CE_C_posedge_posedge : VitalDelayType := 0.000 ns; + tsetup_CE_C_negedge_posedge : VitalDelayType := 0.000 ns; + thold_CE_C_posedge_posedge : VitalDelayType := 0.000 ns; + thold_CE_C_negedge_posedge : VitalDelayType := 0.000 ns; + trecovery_CLR_C_negedge_posedge : VitalDelayType := 0.000 ns; + thold_CLR_C_negedge_posedge : VitalDelayType := 0.000 ns; + trecovery_PRE_C_negedge_posedge : VitalDelayType := 0.000 ns; + thold_PRE_C_negedge_posedge : VitalDelayType := 0.000 ns; + tpw_C_posedge : VitalDelayType := 0.000 ns; + tpw_CLR_posedge : VitalDelayType := 0.000 ns; + tpw_PRE_posedge : VitalDelayType := 0.000 ns; + tpw_C_negedge : VitalDelayType := 0.000 ns; + tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_CE : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + Q : out STD_ULOGIC; + + C : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLR : in STD_ULOGIC; + D : in STD_ULOGIC; + PRE : in STD_ULOGIC + ); +attribute VITAL_LEVEL0 of FDDCPE : entity is TRUE; +end FDDCPE; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library UNISIM; +use unisim.VPKG.all; +architecture FDDCPE_V of FDDCPE is + --attribute VITAL_LEVEL1 of FDDCPE_V : architecture is TRUE; + + SIGNAL D_ipd : STD_ULOGIC := 'X'; + SIGNAL C_ipd : STD_ULOGIC := 'X'; + SIGNAL CE_ipd : STD_ULOGIC := 'X'; + SIGNAL CLR_ipd : STD_ULOGIC := 'X'; + SIGNAL PRE_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (D_ipd, D, tipd_D); + VitalWireDelay (C_ipd, C, tipd_C); + VitalWireDelay (CE_ipd, CE, tipd_CE); + VitalWireDelay (CLR_ipd, CLR, tipd_CLR); + VitalWireDelay (PRE_ipd, PRE, tipd_PRE); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process + + -- timing check results + VARIABLE Tviol_D_C_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_D_C_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Tviol_CE_C_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_CE_C_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Tviol_CLR_C_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_CLR_C_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Tviol_PRE_C_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_PRE_C_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Pviol_C : STD_ULOGIC := '0'; + VARIABLE PInfo_C : VitalPeriodDataType := VitalPeriodDataInit; + VARIABLE Pviol_CLR : STD_ULOGIC := '0'; + VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; + VARIABLE Pviol_PRE : STD_ULOGIC := '0'; + VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; + + -- functionality results + VARIABLE Violation : STD_ULOGIC := '0'; + VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 6); + VARIABLE D_delayed : STD_ULOGIC := 'X'; + VARIABLE C_delayed : STD_ULOGIC := 'X'; + VARIABLE CE_delayed : STD_ULOGIC := 'X'; + --VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + --ALIAS Q_zd : STD_LOGIC is Results(1); + -- variable Q_zd : STD_ULOGIC := TO_X01(INIT); + variable Q_zd : STD_ULOGIC := '0'; + VARIABLE FIRST_TIME : boolean := True ; + + -- output glitch detection variables + VARIABLE Q_GlitchData : VitalGlitchDataType; + + begin + + if (FIRST_TIME = TRUE) then + + Q <= '0'; + + wait until (CLR_ipd = '1' or PRE_ipd = '1' or rising_edge(c_ipd )); + + CE_delayed := CE_ipd; + C_delayed := C_ipd'last_value; + D_delayed := D_ipd; + + FIRST_TIME := FALSE; + end if; + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_D_C_posedge, + TimingData => Tmkr_D_C_posedge, + TestSignal => D_ipd, + TestSignalName => "D", + TestDelay => 0 ns, + RefSignal => C_ipd, + RefSignalName => "C", + RefDelay => 0 ns, + SetupHigh => tsetup_D_C_posedge_posedge, + SetupLow => tsetup_D_C_negedge_posedge, + HoldLow => thold_D_C_posedge_posedge, + HoldHigh => thold_D_C_negedge_posedge, + CheckEnabled => + TO_X01(((NOT CLR_ipd)) AND (CE_ipd) AND ((NOT + PRE_ipd))) /= '0', + RefTransition => 'R', + HeaderMsg => InstancePath & "/FDDCPE", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalSetupHoldCheck ( + Violation => Tviol_CE_C_posedge, + TimingData => Tmkr_CE_C_posedge, + TestSignal => CE_ipd, + TestSignalName => "CE", + TestDelay => 0 ns, + RefSignal => C_ipd, + RefSignalName => "C", + RefDelay => 0 ns, + SetupHigh => tsetup_CE_C_posedge_posedge, + SetupLow => tsetup_CE_C_negedge_posedge, + HoldLow => thold_CE_C_posedge_posedge, + HoldHigh => thold_CE_C_negedge_posedge, + CheckEnabled => + TO_X01(((NOT CLR_ipd)) AND ((Q_zd) XOR (D_ipd)) + AND ((NOT PRE_ipd))) /= '0', + RefTransition => 'R', + HeaderMsg => InstancePath & "/FDDCPE", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalRecoveryRemovalCheck ( + Violation => Tviol_CLR_C_posedge, + TimingData => Tmkr_CLR_C_posedge, + TestSignal => CLR_ipd, + TestSignalName => "CLR", + TestDelay => 0 ns, + RefSignal => C_ipd, + RefSignalName => "C", + RefDelay => 0 ns, + Recovery => trecovery_CLR_C_negedge_posedge, + Removal => thold_CLR_C_negedge_posedge, + ActiveLow => FALSE, + CheckEnabled => + TO_X01(((NOT PRE_ipd)) AND (CE_ipd)) /= '0', + RefTransition => 'R', + HeaderMsg => InstancePath & "/FDDCPE", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalRecoveryRemovalCheck ( + Violation => Tviol_PRE_C_posedge, + TimingData => Tmkr_PRE_C_posedge, + TestSignal => PRE_ipd, + TestSignalName => "PRE", + TestDelay => 0 ns, + RefSignal => C_ipd, + RefSignalName => "C", + RefDelay => 0 ns, + Recovery => trecovery_PRE_C_negedge_posedge, + Removal => thold_PRE_C_negedge_posedge, + ActiveLow => FALSE, + CheckEnabled => + TO_X01(((NOT CLR_ipd)) AND (CE_ipd)) /= '0', + RefTransition => 'R', + HeaderMsg => InstancePath & "/FDDCPE", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalPeriodPulseCheck ( + Violation => Pviol_C, + PeriodData => PInfo_C, + TestSignal => C_ipd, + TestSignalName => "C", + TestDelay => 0 ns, + Period => 0 ns, + PulseWidthHigh => tpw_C_posedge, + PulseWidthLow => tpw_C_negedge, + CheckEnabled => TRUE, + HeaderMsg => InstancePath &"/FDDCPE", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalPeriodPulseCheck ( + Violation => Pviol_CLR, + PeriodData => PInfo_CLR, + TestSignal => CLR_ipd, + TestSignalName => "CLR", + TestDelay => 0 ns, + Period => 0 ns, + PulseWidthHigh => tpw_CLR_posedge, + PulseWidthLow => 0 ns, + CheckEnabled => TRUE, + HeaderMsg => InstancePath &"/FDDCPE", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalPeriodPulseCheck ( + Violation => Pviol_PRE, + PeriodData => PInfo_PRE, + TestSignal => PRE_ipd, + TestSignalName => "PRE", + TestDelay => 0 ns, + Period => 0 ns, + PulseWidthHigh => tpw_PRE_posedge, + PulseWidthLow => 0 ns, + CheckEnabled => TRUE, + HeaderMsg => InstancePath &"/FDDCPE", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + end if; + + ------------------------- + -- Functionality Section + ------------------------- + Violation := Tviol_D_C_posedge or Tviol_CLR_C_posedge or Tviol_PRE_C_posedge or Pviol_PRE or Pviol_C or Tviol_CE_C_posedge or Pviol_CLR; + VitalStateTable( + Result => Q_zd, + PreviousDataIn => PrevData_Q, + StateTable => FDDCPE_Q_tab, + DataIn => ( + C_delayed, PRE_ipd, Q_zd, D_delayed, CE_delayed, C_ipd, CLR_ipd)); + Q_zd := Violation XOR Q_zd; + D_delayed := D_ipd; + C_delayed := C_ipd; + CE_delayed := CE_ipd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => Q, + GlitchData => Q_GlitchData, + OutSignalName => "Q", + OutTemp => Q_zd, + Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), + 1 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), + 2 => (C_ipd'last_event, tpd_C_Q, TRUE)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + + wait on D_ipd, C_ipd, CE_ipd, CLR_ipd, PRE_ipd; +end process; + +end FDDCPE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/fddp.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Dual Edge Triggered D Flip-Flop with Asynchronous Preset +-- /___/ /\ Filename : FDDP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:23 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FDDP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity FDDP is + generic( + TimingChecksOn: Boolean := TRUE; + InstancePath: STRING := "*"; + Xon: Boolean := True; + MsgOn: Boolean := False; + INIT : bit := '1' ; + tpd_PRE_Q : VitalDelayType01 := (0.000 ns, 0.000 ns); + tpd_C_Q : VitalDelayType01 := (0.1 ns, 0.1 ns); + tsetup_D_C_posedge_posedge : VitalDelayType := 0.000 ns; + tsetup_D_C_negedge_posedge : VitalDelayType := 0.000 ns; + thold_D_C_posedge_posedge : VitalDelayType := 0.000 ns; + thold_D_C_negedge_posedge : VitalDelayType := 0.000 ns; + trecovery_PRE_C_negedge_posedge : VitalDelayType := 0.000 ns; + thold_PRE_C_negedge_posedge : VitalDelayType := 0.000 ns; + tpw_C_posedge : VitalDelayType := 0.000 ns; + tpw_PRE_posedge : VitalDelayType := 0.000 ns; + tpw_C_negedge : VitalDelayType := 0.000 ns; + tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + Q : out STD_ULOGIC; + + C : in STD_ULOGIC; + D : in STD_ULOGIC; + PRE : in STD_ULOGIC + ); +attribute VITAL_LEVEL0 of FDDP : entity is TRUE; +end FDDP; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library UNISIM; +use unisim.VPKG.all; +architecture FDDP_V of FDDP is + --attribute VITAL_LEVEL1 of FDDP_V : architecture is TRUE; + + SIGNAL D_ipd : STD_ULOGIC := 'X'; + SIGNAL C_ipd : STD_ULOGIC := 'X'; + SIGNAL PRE_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (D_ipd, D, tipd_D); + VitalWireDelay (C_ipd, C, tipd_C); + VitalWireDelay (PRE_ipd, PRE, tipd_PRE); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process + + -- timing check results + VARIABLE Tviol_D_C_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_D_C_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Tviol_PRE_C_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_PRE_C_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Pviol_C : STD_ULOGIC := '0'; + VARIABLE PInfo_C : VitalPeriodDataType := VitalPeriodDataInit; + VARIABLE Pviol_PRE : STD_ULOGIC := '0'; + VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; + + -- functionality results + VARIABLE Violation : STD_ULOGIC := '0'; + VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); + VARIABLE D_delayed : STD_ULOGIC := 'X'; + VARIABLE C_delayed : STD_ULOGIC := 'X'; + --VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + --ALIAS Q_zd : STD_LOGIC is Results(1); + variable Q_zd : STD_ULOGIC := TO_X01(INIT); + VARIABLE FIRST_TIME : boolean := True ; + + -- output glitch detection variables + VARIABLE Q_GlitchData : VitalGlitchDataType; + + begin + + if (FIRST_TIME = TRUE) then + + Q <= Q_zd; + + wait until (PRE_ipd = '1' or rising_edge(c_ipd )); + + C_delayed := C_ipd'last_value; + D_delayed := D_ipd; + + FIRST_TIME := FALSE; + end if; + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_D_C_posedge, + TimingData => Tmkr_D_C_posedge, + TestSignal => D_ipd, + TestSignalName => "D", + TestDelay => 0 ns, + RefSignal => C_ipd, + RefSignalName => "C", + RefDelay => 0 ns, + SetupHigh => tsetup_D_C_posedge_posedge, + SetupLow => tsetup_D_C_negedge_posedge, + HoldLow => thold_D_C_posedge_posedge, + HoldHigh => thold_D_C_negedge_posedge, + CheckEnabled => + TO_X01((NOT PRE_ipd)) /= '0', + RefTransition => 'R', + HeaderMsg => InstancePath & "/FDDP", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalRecoveryRemovalCheck ( + Violation => Tviol_PRE_C_posedge, + TimingData => Tmkr_PRE_C_posedge, + TestSignal => PRE_ipd, + TestSignalName => "PRE", + TestDelay => 0 ns, + RefSignal => C_ipd, + RefSignalName => "C", + RefDelay => 0 ns, + Recovery => trecovery_PRE_C_negedge_posedge, + Removal => thold_PRE_C_negedge_posedge, + ActiveLow => FALSE, + CheckEnabled => + TO_X01(PRE_ipd ) /= '1', + RefTransition => 'R', + HeaderMsg => InstancePath & "/FDDP", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalPeriodPulseCheck ( + Violation => Pviol_C, + PeriodData => PInfo_C, + TestSignal => C_ipd, + TestSignalName => "C", + TestDelay => 0 ns, + Period => 0 ns, + PulseWidthHigh => tpw_C_posedge, + PulseWidthLow => tpw_C_negedge, + CheckEnabled => TRUE, + HeaderMsg => InstancePath &"/FDDP", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalPeriodPulseCheck ( + Violation => Pviol_PRE, + PeriodData => PInfo_PRE, + TestSignal => PRE_ipd, + TestSignalName => "PRE", + TestDelay => 0 ns, + Period => 0 ns, + PulseWidthHigh => tpw_PRE_posedge, + PulseWidthLow => 0 ns, + CheckEnabled => TRUE, + HeaderMsg => InstancePath &"/FDDP", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + end if; + + ------------------------- + -- Functionality Section + ------------------------- + Violation := Tviol_D_C_posedge or Tviol_PRE_C_posedge or Pviol_PRE or Pviol_C; + VitalStateTable( + Result => Q_zd, + PreviousDataIn => PrevData_Q, + StateTable => FDDP_Q_tab, + DataIn => ( + C_delayed, D_delayed, PRE_ipd, C_ipd)); + Q_zd := Violation XOR Q_zd; + D_delayed := D_ipd; + C_delayed := C_ipd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => Q, + GlitchData => Q_GlitchData, + OutSignalName => "Q", + OutTemp => Q_zd, + Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), + 1 => (C_ipd'last_event, tpd_C_Q, TRUE)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + + wait on D_ipd, C_ipd, PRE_ipd; +end process; + +end FDDP_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/fddpe.vhd,v 1.2 2005/07/23 00:43:54 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Dual Edge Triggered D Flip-Flop with Asynchronous Preset and Clock Enable +-- /___/ /\ Filename : FDDPE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:23 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 07/23/05 -- Removed INIT to match verilog +-- End Revision + +----- CELL FDDPE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity FDDPE is + generic( + TimingChecksOn: Boolean := TRUE; + InstancePath: STRING := "*"; + Xon: Boolean := True; + MsgOn: Boolean := False; + tpd_PRE_Q : VitalDelayType01 := (0.000 ns, 0.000 ns); + tpd_C_Q : VitalDelayType01 := (0.1 ns, 0.1 ns); + tsetup_D_C_posedge_posedge : VitalDelayType := 0.000 ns; + tsetup_D_C_negedge_posedge : VitalDelayType := 0.000 ns; + thold_D_C_posedge_posedge : VitalDelayType := 0.000 ns; + thold_D_C_negedge_posedge : VitalDelayType := 0.000 ns; + tsetup_CE_C_posedge_posedge : VitalDelayType := 0.000 ns; + tsetup_CE_C_negedge_posedge : VitalDelayType := 0.000 ns; + thold_CE_C_posedge_posedge : VitalDelayType := 0.000 ns; + thold_CE_C_negedge_posedge : VitalDelayType := 0.000 ns; + trecovery_PRE_C_negedge_posedge : VitalDelayType := 0.000 ns; + thold_PRE_C_negedge_posedge : VitalDelayType := 0.000 ns; + tpw_C_posedge : VitalDelayType := 0.000 ns; + tpw_PRE_posedge : VitalDelayType := 0.000 ns; + tpw_C_negedge : VitalDelayType := 0.000 ns; + tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_CE : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + Q : out STD_ULOGIC; + + C : in STD_ULOGIC; + CE : in STD_ULOGIC; + D : in STD_ULOGIC; + PRE : in STD_ULOGIC + ); +attribute VITAL_LEVEL0 of FDDPE : entity is TRUE; +end FDDPE; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library UNISIM; +use unisim.VPKG.all; +architecture FDDPE_V of FDDPE is + --attribute VITAL_LEVEL1 of FDDPE_V : architecture is TRUE; + + SIGNAL D_ipd : STD_ULOGIC := 'X'; + SIGNAL C_ipd : STD_ULOGIC := 'X'; + SIGNAL CE_ipd : STD_ULOGIC := 'X'; + SIGNAL PRE_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (D_ipd, D, tipd_D); + VitalWireDelay (C_ipd, C, tipd_C); + VitalWireDelay (CE_ipd, CE, tipd_CE); + VitalWireDelay (PRE_ipd, PRE, tipd_PRE); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process + + -- timing check results + VARIABLE Tviol_D_C_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_D_C_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Tviol_CE_C_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_CE_C_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Tviol_PRE_C_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_PRE_C_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Pviol_C : STD_ULOGIC := '0'; + VARIABLE PInfo_C : VitalPeriodDataType := VitalPeriodDataInit; + VARIABLE Pviol_PRE : STD_ULOGIC := '0'; + VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; + + -- functionality results + VARIABLE Violation : STD_ULOGIC := '0'; + VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); + VARIABLE D_delayed : STD_ULOGIC := 'X'; + VARIABLE C_delayed : STD_ULOGIC := 'X'; + VARIABLE CE_delayed : STD_ULOGIC := 'X'; + --VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + --ALIAS Q_zd : STD_LOGIC is Results(1); + -- variable Q_zd : STD_ULOGIC := TO_X01(INIT); + variable Q_zd : STD_ULOGIC := '0'; + VARIABLE FIRST_TIME : boolean := True ; + + -- output glitch detection variables + VARIABLE Q_GlitchData : VitalGlitchDataType; + + begin + + if (FIRST_TIME = TRUE) then + + Q <= '1'; + + wait until (PRE_ipd = '1' or rising_edge(c_ipd )); + + CE_delayed := CE_ipd; + C_delayed := C_ipd'last_value; + D_delayed := D_ipd; + + + FIRST_TIME := FALSE; + end if; + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_D_C_posedge, + TimingData => Tmkr_D_C_posedge, + TestSignal => D_ipd, + TestSignalName => "D", + TestDelay => 0 ns, + RefSignal => C_ipd, + RefSignalName => "C", + RefDelay => 0 ns, + SetupHigh => tsetup_D_C_posedge_posedge, + SetupLow => tsetup_D_C_negedge_posedge, + HoldLow => thold_D_C_posedge_posedge, + HoldHigh => thold_D_C_negedge_posedge, + CheckEnabled => + TO_X01(((NOT PRE_ipd)) AND (CE_ipd)) /= '0', + RefTransition => 'R', + HeaderMsg => InstancePath & "/FDDPE", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalSetupHoldCheck ( + Violation => Tviol_CE_C_posedge, + TimingData => Tmkr_CE_C_posedge, + TestSignal => CE_ipd, + TestSignalName => "CE", + TestDelay => 0 ns, + RefSignal => C_ipd, + RefSignalName => "C", + RefDelay => 0 ns, + SetupHigh => tsetup_CE_C_posedge_posedge, + SetupLow => tsetup_CE_C_negedge_posedge, + HoldLow => thold_CE_C_posedge_posedge, + HoldHigh => thold_CE_C_negedge_posedge, + CheckEnabled => + TO_X01(((NOT PRE_ipd)) AND ((Q_zd) XOR (D_ipd))) + /= '0', + RefTransition => 'R', + HeaderMsg => InstancePath & "/FDDPE", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalRecoveryRemovalCheck ( + Violation => Tviol_PRE_C_posedge, + TimingData => Tmkr_PRE_C_posedge, + TestSignal => PRE_ipd, + TestSignalName => "PRE", + TestDelay => 0 ns, + RefSignal => C_ipd, + RefSignalName => "C", + RefDelay => 0 ns, + Recovery => trecovery_PRE_C_negedge_posedge, + Removal => thold_PRE_C_negedge_posedge, + ActiveLow => FALSE, + CheckEnabled => + TO_X01(CE_ipd) /= '0', + RefTransition => 'R', + HeaderMsg => InstancePath & "/FDDPE", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalPeriodPulseCheck ( + Violation => Pviol_C, + PeriodData => PInfo_C, + TestSignal => C_ipd, + TestSignalName => "C", + TestDelay => 0 ns, + Period => 0 ns, + PulseWidthHigh => tpw_C_posedge, + PulseWidthLow => tpw_C_negedge, + CheckEnabled => TRUE, + HeaderMsg => InstancePath &"/FDDPE", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalPeriodPulseCheck ( + Violation => Pviol_PRE, + PeriodData => PInfo_PRE, + TestSignal => PRE_ipd, + TestSignalName => "PRE", + TestDelay => 0 ns, + Period => 0 ns, + PulseWidthHigh => tpw_PRE_posedge, + PulseWidthLow => 0 ns, + CheckEnabled => TRUE, + HeaderMsg => InstancePath &"/FDDPE", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + end if; + + ------------------------- + -- Functionality Section + ------------------------- + Violation := Tviol_D_C_posedge or Tviol_PRE_C_posedge or Pviol_PRE or Pviol_C or Tviol_CE_C_posedge; + VitalStateTable( + Result => Q_zd, + PreviousDataIn => PrevData_Q, + StateTable => FDDPE_Q_tab, + DataIn => ( + C_delayed, PRE_ipd, Q_zd, D_delayed, CE_delayed, C_ipd)); + Q_zd := Violation XOR Q_zd; + D_delayed := D_ipd; + C_delayed := C_ipd; + CE_delayed := CE_ipd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => Q, + GlitchData => Q_GlitchData, + OutSignalName => "Q", + OutTemp => Q_zd, + Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), + 1 => (C_ipd'last_event, tpd_C_Q, TRUE)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + + wait on D_ipd, C_ipd, CE_ipd, PRE_ipd; +end process; + +end FDDPE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/ftc.vhd,v 1.2 2005/07/23 00:43:54 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Toggle Flip-Flop with Toggle Enable and Asynchronous Clear +-- /___/ /\ Filename : FTC.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:26 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 07/23/05 -- Removed INIT to match verilog +-- End Revision + +----- CELL FTC ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FTC is + port( + Q : out std_ulogic; + + C : in std_ulogic; + CLR : in std_ulogic; + T : in std_ulogic + ); +end FTC; + +architecture FTC_V of FTC is +begin + VITALBehavior : process(C, CLR) + variable FIRST_TIME : boolean := true ; + variable Q_zd : std_ulogic := '0'; + begin + + if (FIRST_TIME = true) then + Q <= '0'; + FIRST_TIME := false; + end if; + + if (CLR = '1') then + Q <= '0'; + elsif (rising_edge(C)) then + if (T = '1') then + Q_zd := not Q_zd; + Q <= Q_zd after 100 ps; + end if; + + end if; + end process; +end FTC_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/ftcp.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Toggle Flip-Flop with Toggle Enable and Asynchronous Clear and Preset +-- /___/ /\ Filename : FTCP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:26 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FTCP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FTCP is + generic( + INIT : bit := '0' + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CLR : in std_ulogic; + PRE : in std_ulogic; + T : in std_ulogic + ); +end FTCP; + +architecture FTCP_V of FTCP is +begin + VITALBehavior : process(C, CLR, PRE) + variable FIRST_TIME : boolean := true ; + variable Q_zd : std_ulogic := TO_X01(INIT); + begin + + if (FIRST_TIME = true) then + Q <= TO_X01(INIT); + FIRST_TIME := false; + end if; + + if (CLR = '1') then + Q <= '0'; + Q_zd := '0'; + elsif (PRE = '1') then + Q <= '1'; + Q_zd := '1'; + elsif (C'event and C = '1') then + if (T = '1') then + Q_zd := not Q_zd; + Q <= Q_zd after 100 ps; + end if; + end if; + end process; +end FTCP_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/ftp.vhd,v 1.2 2005/07/23 00:43:54 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Toggle Flip-Flop with Toggle Enable and Asynchronous Preset +-- /___/ /\ Filename : FTP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:26 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 07/23/05 -- Removed INIT to match verilog +-- End Revision + +----- CELL FTP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FTP is + port( + Q : out std_ulogic; + + C : in std_ulogic; + PRE : in std_ulogic; + T : in std_ulogic + ); +end FTP; + +architecture FTP_V of FTP is +begin + VITALBehavior : process(C, PRE) + variable FIRST_TIME : boolean := true ; + variable Q_zd : std_ulogic := '1'; + begin + + if (FIRST_TIME = true) then + Q <= '1'; + FIRST_TIME := false; + end if; + + if (PRE = '1') then + Q <= '1'; + elsif (C'event and C = '1') then + if (T = '1') then + Q_zd := not Q_zd; + Q <= Q_zd after 100 ps; + end if; + end if; + end process; +end FTP_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/ild.vhd,v 1.2 2005/07/25 16:07:35 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Tranparent Input Data Latch +-- /___/ /\ Filename : ILD.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:42 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 07/25/04 - Removed INIT to match the verilog model. + +----- CELL ILD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity ILD is + port( + Q : out std_ulogic; + + D : in std_ulogic; + G : in std_ulogic + ); +end ILD; + +architecture ILD_V of ILD is +begin + VITALBehavior : process(D, G) + variable Q_zd : std_ulogic := '0'; + begin + if (G = '1') then + Q <= D after 100 ps; + end if; + end process; +end ILD_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/iobufe.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer +-- /___/ /\ Filename : IOBUFE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:59 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUFE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUFE is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + E : in std_ulogic; + I : in std_ulogic + ); +end IOBUFE; + +architecture IOBUFE_V of IOBUFE is +begin + VPKGBehavior : process (IO, I, E) + variable IO_zd : std_ulogic; + begin + O <= IO; + if ((E = '0') or (E = 'L')) then + IO <= 'Z'; + elsif ((E = '1') or (E = 'H')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (E = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUFE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/iobufe_f.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer +-- /___/ /\ Filename : IOBUFE_F.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:59 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUFE_F ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUFE_F is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + E : in std_ulogic; + I : in std_ulogic + ); +end IOBUFE_F; + +architecture IOBUFE_F_V of IOBUFE_F is +begin + VPKGBehavior : process (IO, I, E) + variable IO_zd : std_ulogic; + begin + O <= IO; + if ((E = '1') or (E = 'H')) then + IO <= 'Z'; + elsif ((E = '0') or (E = 'L')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (E = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUFE_F_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/iobufe_s.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Bi-Directional Buffer +-- /___/ /\ Filename : IOBUFE_S.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:59 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IOBUFE_S ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity IOBUFE_S is + port( + O : out std_ulogic; + + IO : inout std_ulogic; + + E : in std_ulogic; + I : in std_ulogic + ); +end IOBUFE_S; + +architecture IOBUFE_S_V of IOBUFE_S is +begin + VPKGBehavior : process (IO, I, E) + variable IO_zd : std_ulogic; + begin + O <= IO; + if ((E = '0') or (E = 'L')) then + IO <= 'Z'; + elsif ((E = '1') or (E = 'H')) then + if ((I = '1') or (I = 'H')) then + IO <= '1'; + elsif ((I = '0') or (I = 'L')) then + IO <= '0'; + elsif (I = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + elsif (E = 'U') then + IO <= 'U'; + else + IO <= 'X'; + end if; + end process; +end IOBUFE_S_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/keep.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / +-- /___/ /\ Filename : KEEP.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:55:59 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL KEEP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity KEEP is + port( + O : out std_ulogic; + + I : in std_ulogic + ); +end KEEP; + +architecture KEEP_V of KEEP is +begin + VITALBehavior : process (I) + begin + O <= TO_X01(I); + end process; +end KEEP_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/ldg.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Transparent Datagate Latch +-- /___/ /\ Filename : LDG.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:00 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL LDG ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity LDG is + generic( + TimingChecksOn: Boolean := TRUE; + InstancePath: STRING := "*"; + Xon: Boolean := True; + MsgOn: Boolean := False; + INIT : bit := '0' ; + tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns); + tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns); + tsetup_D_G_posedge_negedge : VitalDelayType := 0.000 ns; + tsetup_D_G_negedge_negedge : VitalDelayType := 0.000 ns; + thold_D_G_posedge_negedge : VitalDelayType := 0.000 ns; + thold_D_G_negedge_negedge : VitalDelayType := 0.000 ns; + tpw_G_posedge : VitalDelayType := 0.000 ns; + tpw_G_negedge : VitalDelayType := 0.000 ns; + tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns) + ); + + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + G : in STD_ULOGIC + ); +attribute VITAL_LEVEL0 of LDG : entity is TRUE; +end LDG; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library UNISIM; +use UNISIM.VPKG.all; +architecture LDG_V of LDG is + --attribute VITAL_LEVEL1 of LDG_V : architecture is TRUE; + + SIGNAL D_ipd : STD_ULOGIC := 'X'; + SIGNAL G_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (D_ipd, D, tipd_D); + VitalWireDelay (G_ipd, G, tipd_G); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process + + -- timing check results + VARIABLE Tviol_D_G_negedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_D_G_negedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Pviol_G : STD_ULOGIC := '0'; + VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; + + -- functionality results + VARIABLE Violation : STD_ULOGIC := '0'; + VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 1); + --VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + VARIABLE Q_zd : STD_ULOGIC := TO_X01(INIT); + VARIABLE FIRST_TIME : boolean := True ; + --ALIAS Q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE Q_GlitchData : VitalGlitchDataType; + + begin + + if (FIRST_TIME = TRUE) then + + Q <= Q_zd ; + + wait until (G_ipd = '0' or G_ipd = '1'); + + + FIRST_TIME := FALSE; + end if; + + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_D_G_negedge, + TimingData => Tmkr_D_G_negedge, + TestSignal => D_ipd, + TestSignalName => "D", + TestDelay => 0 ns, + RefSignal => G_ipd, + RefSignalName => "G", + RefDelay => 0 ns, + SetupHigh => tsetup_D_G_posedge_negedge, + SetupLow => tsetup_D_G_negedge_negedge, + HoldHigh => thold_D_G_posedge_negedge, + HoldLow => thold_D_G_negedge_negedge, + CheckEnabled => TRUE, + RefTransition => 'F', + HeaderMsg => InstancePath & "/LD", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + + VitalPeriodPulseCheck ( + Violation => Pviol_G, + PeriodData => PInfo_G, + TestSignal => G_ipd, + TestSignalName => "G", + TestDelay => 0 ns, + Period => 0 ns, + PulseWidthHigh => tpw_G_posedge, + PulseWidthLow => tpw_G_negedge, + CheckEnabled => TRUE, + HeaderMsg => InstancePath &"/LD", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + end if; + + ------------------------- + -- Functionality Section + ------------------------- + Violation := Tviol_D_G_negedge or Pviol_G; + VitalStateTable( + Result => Q_zd, + PreviousDataIn => PrevData_Q, + StateTable => ILDI_1_Q_tab, + DataIn => ( + G_ipd, D_ipd)); + Q_zd := Violation XOR Q_zd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => Q, + GlitchData => Q_GlitchData, + OutSignalName => "Q", + OutTemp => Q_zd, + Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), + 1 => (G_ipd'last_event, tpd_G_Q, TRUE)), + Mode => OnEvent, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +wait on D_ipd, G_ipd; +end process; + +end LDG_V; + + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/merge.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / +-- /___/ /\ Filename : MERGE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:02 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL MERGE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity MERGE is + port( + I : in std_ulogic + ); +end MERGE; + +architecture MERGE_V of MERGE is +begin +end MERGE_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/min_off.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / +-- /___/ /\ Filename : MIN_OFF.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:02 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL MIN_OFF ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity MIN_OFF is + port( + I : in std_ulogic + ); +end MIN_OFF; + +architecture MIN_OFF_V of MIN_OFF is +begin +end MIN_OFF_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/obufe.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 3-State Output Buffer +-- /___/ /\ Filename : OBUFE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:26 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OBUFE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OBUFE is + port( + O : out std_ulogic; + I : in std_ulogic; + E : in std_ulogic + ); +end OBUFE; + +architecture OBUFE_V of OBUFE is +begin + + VITALBehavior : process (I, E) + begin + if (((not E) = '1') or ((not E) = 'H')) then + O <= 'Z'; + elsif (((not E) = '0') or ((not E) = 'L')) then + if ((I = '1') or (I = 'H')) then + O <= '1'; + elsif ((I = '0') or (I = 'L')) then + O <= '0'; + elsif (I = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + elsif ((not E) = 'U') then + O <= 'U'; + else + O <= 'X'; + end if; + end process; +end OBUFE_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/opt_off.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / +-- /___/ /\ Filename : OPT_OFF.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:44 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OPT_OFF ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OPT_OFF is + port( + I : in std_ulogic + ); +end OPT_OFF; + +architecture OPT_OFF_V of OPT_OFF is +begin +end OPT_OFF_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/opt_uim.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / +-- /___/ /\ Filename : OPT_UIM.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:44 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OPT_UIM ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OPT_UIM is + port( + I : in std_ulogic + ); +end OPT_UIM; + +architecture OPT_UIM_V of OPT_UIM is +begin +end OPT_UIM_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/or6.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 6-input OR Gate +-- /___/ /\ Filename : OR6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:46 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR6 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic + ); +end OR6; + +architecture OR6_V of OR6 is +begin + O <= (I0 or I1 or I2 or I3 or I4 or I5); +end OR6_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/or7.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 7-input OR Gate +-- /___/ /\ Filename : OR7.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:46 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR7 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR7 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic; + I6 : in std_ulogic + ); +end OR7; + +architecture OR7_V of OR7 is +begin + O <= (I0 or I1 or I2 or I3 or I4 or I5 or I6); +end OR7_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/or8.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 8-input OR Gate +-- /___/ /\ Filename : OR8.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:47 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL OR8 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity OR8 is + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic; + I6 : in std_ulogic; + I7 : in std_ulogic + ); +end OR8; + +architecture OR8_V of OR8 is +begin + O <= (I0 or I1 or I2 or I3 or I4 or I5 or I6 or I7); +end OR8_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/cpld/VITAL/Attic/wireand.vhd,v 1.1 2005/05/27 00:01:49 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / +-- /___/ /\ Filename : WIREAND.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:00 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL WIREAND ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity WIREAND is + port( + I : in std_ulogic + ); +end WIREAND; +architecture WIREAND_V of WIREAND is +begin +end WIREAND_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/bscan_virtex4.vhd,v 1.6 2005/03/10 22:45:35 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Boundary Scan Logic Control Circuit for VIRTEX4 +-- /___/ /\ Filename : BSCAN_VIRTEX4.v +-- \ \ / \ Timestamp : Fri Mar 26 08:17:58 PST 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BSCAN_VIRTEX4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.vcomponents.all; +entity BSCAN_VIRTEX4 is + generic( + JTAG_CHAIN : integer := 1 + ); + + port( + CAPTURE : out std_ulogic := 'H'; + DRCK : out std_ulogic := 'H'; + RESET : out std_ulogic := 'H'; + SEL : out std_ulogic := 'L'; + SHIFT : out std_ulogic := 'L'; + TDI : out std_ulogic := 'L'; + UPDATE : out std_ulogic := 'L'; + + TDO : in std_ulogic := 'X' + ); + +end BSCAN_VIRTEX4; + +architecture BSCAN_VIRTEX4_V of BSCAN_VIRTEX4 is + +signal SEL_zd : std_ulogic := '0'; +signal UPDATE_zd : std_ulogic := '0'; + +begin + +--#################################################################### +--##### Initialization ### +--#################################################################### + prcs_init:process + begin + if((JTAG_CHAIN /= 1) and (JTAG_CHAIN /= 2) and (JTAG_CHAIN /= 3) + and (JTAG_CHAIN /= 4)) then + assert false + report "Attribute Syntax Error: The allowed values for JTAG_CHAIN are 1, 2, 3 or 4" + severity Failure; + end if; + wait; + end process prcs_init; + +-- synopsys translate_off + +--#################################################################### +--##### jtag_select ### +--#################################################################### + prcs_jtag_select:process (JTAG_SEL1_GLBL, JTAG_SEL2_GLBL, JTAG_SEL3_GLBL, JTAG_SEL4_GLBL) + begin + if(JTAG_CHAIN = 1) then + SEL_zd <= JTAG_SEL1_GLBL; + elsif(JTAG_CHAIN = 2) then + SEL_zd <= JTAG_SEL2_GLBL; + elsif(JTAG_CHAIN = 3) then + SEL_zd <= JTAG_SEL3_GLBL; + elsif(JTAG_CHAIN = 4) then + SEL_zd <= JTAG_SEL4_GLBL; + end if; + + end process prcs_jtag_select; + +--#################################################################### +--##### USER_TDO ### +--#################################################################### + prcs_jtag_UserTDO:process (TDO) + begin + if(JTAG_CHAIN = 1) then + JTAG_USER_TDO1_GLBL <= TDO; + elsif(JTAG_CHAIN = 2) then + JTAG_USER_TDO2_GLBL <= TDO; + elsif(JTAG_CHAIN = 3) then + JTAG_USER_TDO3_GLBL <= TDO; + elsif(JTAG_CHAIN = 4) then + JTAG_USER_TDO4_GLBL <= TDO; + end if; + + end process prcs_jtag_UserTDO; +--#################################################################### + + CAPTURE <= JTAG_CAPTURE_GLBL; + DRCK <= ((SEL_zd and not JTAG_SHIFT_GLBL and not JTAG_CAPTURE_GLBL) or + (SEL_zd and JTAG_SHIFT_GLBL and JTAG_TCK_GLBL) or + (SEL_zd and JTAG_CAPTURE_GLBL and JTAG_TCK_GLBL)); + TDI <= JTAG_TDI_GLBL; + SEL <= SEL_zd; + SHIFT <= JTAG_SHIFT_GLBL; + UPDATE <= JTAG_UPDATE_GLBL; + RESET <= JTAG_RESET_GLBL; + +-- synopsys translate_on + +end BSCAN_VIRTEX4_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Mux Buffer +-- /___/ /\ Filename : BUFGCTRL.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:18:19 PST 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 11/28/05 - CR 221551 fix. +-- 08/13/07 - CR 413180 Initialization mismatch fix for unisims. +-- 04/07/08 - CR 469973 -- Header Description fix +-- 05/22/08 - Add init_done to pass initial values (CR 473625). +-- End Revision + +----- CELL BUFGCTRL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + + +library unisim; +use unisim.vpkg.all; +use unisim.vcomponents.all; + +entity BUFGCTRL is + + generic( + + + INIT_OUT : integer := 0; + PRESELECT_I0 : boolean := false; + PRESELECT_I1 : boolean := false + ); + + port( + O : out std_ulogic; + + CE0 : in std_ulogic; + CE1 : in std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + IGNORE0 : in std_ulogic; + IGNORE1 : in std_ulogic; + S0 : in std_ulogic; + S1 : in std_ulogic + ); + +end BUFGCTRL; + +architecture BUFGCTRL_V OF BUFGCTRL is + + + constant SYNC_PATH_DELAY : time := 100 ps; + + signal CE0_dly : std_ulogic := 'X'; + signal CE1_dly : std_ulogic := 'X'; + signal I0_dly : std_ulogic := 'X'; + signal I1_dly : std_ulogic := 'X'; + signal IGNORE0_dly : std_ulogic := 'X'; + signal IGNORE1_dly : std_ulogic := 'X'; + signal GSR_I0_dly : std_ulogic := 'X'; + signal GSR_I1_dly : std_ulogic := 'X'; + signal S0_dly : std_ulogic := 'X'; + signal S1_dly : std_ulogic := 'X'; + + signal O_zd : std_ulogic := 'X'; + + signal q0 : std_ulogic := 'X'; + signal q1 : std_ulogic := 'X'; + signal q0_enable : std_ulogic := 'X'; + signal q1_enable : std_ulogic := 'X'; + + signal preslct_i0 : std_ulogic := 'X'; + signal preslct_i1 : std_ulogic := 'X'; + + signal i0_int : std_ulogic := 'X'; + signal i1_int : std_ulogic := 'X'; + signal init_done : boolean := false; +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + CE0_dly <= CE0 after 0 ps; + CE1_dly <= CE1 after 0 ps; + I0_dly <= I0 after 0 ps; + I1_dly <= I1 after 0 ps; + GSR_I0_dly <= GSR after 0 ps; + GSR_I1_dly <= GSR after 0 ps; + IGNORE0_dly <= IGNORE0 after 0 ps; + IGNORE1_dly <= IGNORE1 after 0 ps; + S0_dly <= S0 after 0 ps; + S1_dly <= S1 after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + variable FIRST_TIME : boolean := true; + variable preslct_i0_var : std_ulogic; + variable preslct_i1_var : std_ulogic; + + begin + if(FIRST_TIME) then + + -- check for PRESELECT_I0 + case PRESELECT_I0 is + when true => preslct_i0_var := '1'; + when false => preslct_i0_var := '0'; + when others => + assert false report + "*** Attribute Syntax Error: Legal values for PRESELECT_I0 are TRUE or FALSE" + severity failure; + end case; + + -- check for PRESELECT_I1 + case PRESELECT_I1 is + when true => preslct_i1_var := '1'; + when false => preslct_i1_var := '0'; + when others => + assert false report + "*** Attribute Syntax Error: Legal values for PRESELECT_I0 are TRUE or FALSE" + severity failure; + end case; + + -- both preslcts can not be 1 simultaneously + if((preslct_i0_var = '1') and (preslct_i1_var = '1')) then + assert false report + "*** Attribute Syntax Error: The attributes PRESELECT_I0 and PRESELECT_I1 should not be set to TRUE simultaneously" + severity failure; + end if; + + -- check for INIT_OUT + if((INIT_OUT /= 0) and (INIT_OUT /= 1)) then + assert false report + "*** Attribute Syntax Error: Legal values for INIT_OUT are 0 or 1 " + severity failure; + end if; + + preslct_i0 <= preslct_i0_var; + preslct_i1 <= preslct_i1_var; + FIRST_TIME := false; + init_done <= true; + + end if; + wait; + + end process prcs_init; + + +----- *** Start + + prcs_clk:process(i0_dly, i1_dly) + begin + if(INIT_OUT = 1) then + i0_int <= NOT i0_dly; + else + i0_int <= i0_dly; + end if; + + if(INIT_OUT = 1) then + i1_int <= NOT i1_dly; + else + i1_int <= i1_dly; + end if; + end process prcs_clk; +--#################################################################### +--##### I1 ##### +--#################################################################### +----- *** Input enable for i1 + prcs_en_i1:process(IGNORE1_dly, i1_int, S1_dly, GSR_I1_dly, q0, init_done) + variable FIRST_TIME : boolean := TRUE; + begin + if (((FIRST_TIME) and (init_done)) or (GSR_I1_dly = '1')) then + q1_enable <= preslct_i1; + FIRST_TIME := false; + elsif (GSR_I1_dly = '0') then + if ((i1_int = '0') and (IGNORE1_dly = '0')) then + q1_enable <= q1_enable; + elsif((i1_int = '1') or (IGNORE1_dly = '1')) then + q1_enable <= ((NOT q0) AND (S1_dly)); + end if; + + end if; + end process prcs_en_i1; + +----- *** Output q1 + prcs_out_i1:process(q1_enable, CE1_dly, i1_int, IGNORE1_dly, GSR_I1_dly, init_done) + variable FIRST_TIME : boolean := TRUE; + begin + if (((FIRST_TIME) and (init_done))or (GSR_I1_dly = '1')) then + q1 <= preslct_i1; + FIRST_TIME := false; + elsif (GSR_I1_dly = '0') then + if ((i1_int = '1') and (IGNORE1_dly = '0')) then + q1 <= q1; + elsif((i1_int = '0') or (IGNORE1_dly = '1')) then + if ((CE0_dly='1' and q0_enable='1') and (CE1_dly='1' and q1_enable='1')) then + q1 <= 'X'; + else + q1 <= CE1_dly AND q1_enable; + end if; + end if; + end if; + end process prcs_out_i1; + +--#################################################################### +--##### I0 ##### +--#################################################################### +----- *** Input enable for i0 + prcs_en_i0:process(IGNORE0_dly, i0_int, S0_dly, GSR_I0_dly, q1, init_done) + variable FIRST_TIME : boolean := TRUE; + begin + if (((FIRST_TIME) and (init_done)) or (GSR_I0_dly = '1')) then + q0_enable <= preslct_i0; + FIRST_TIME := false; + elsif (GSR_I0_dly = '0') then + if ((i0_int = '0') and (IGNORE0_dly = '0')) then + q0_enable <= q0_enable; + elsif((i0_int = '1') or (IGNORE0_dly = '1')) then + q0_enable <= ((NOT q1) AND (S0_dly)); + end if; + + end if; + end process prcs_en_i0; + +----- *** Output q0 + prcs_out_i0:process(q0_enable, CE0_dly, i0_int, IGNORE0_dly, GSR_I0_dly, init_done) + variable FIRST_TIME : boolean := TRUE; + begin + if (((FIRST_TIME) and (init_done)) or (GSR_I0_dly = '1')) then + q0 <= preslct_i0; + FIRST_TIME := false; + elsif (GSR_I0_dly = '0') then + if ((i0_int = '1') and (IGNORE0_dly = '0')) then + q0 <= q0; + elsif((i0_int = '0') or (IGNORE0_dly = '1')) then + if ((CE0_dly='1' and q0_enable='1') and (CE1_dly='1' and q1_enable='1')) then + q0 <= 'X'; + else + q0 <= CE0_dly AND q0_enable; + end if; + end if; + end if; + end process prcs_out_i0; + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_selectout:process(q0, q1, i0_int, i1_int) + variable tmp_buf : std_logic_vector(1 downto 0); + begin + tmp_buf := q1&q0; + case tmp_buf is + when "01" => O_zd <= I0_dly; + when "10" => O_zd <= I1_dly; + when "00" => + if(INIT_OUT = 1) then + O_zd <= '1'; + elsif(INIT_OUT = 0) then + O_zd <= '0'; + end if; + when "XX" => + O_zd <= 'X'; + when others => + end case; + end process prcs_selectout; +--#################################################################### + +-- CR 413180 enabling global GSR +--#################################################################### +--##### GSR ##### +--#################################################################### +-- prcs_gsr:process +-- variable FIRST_TIME : boolean := true; +-- begin +---- CR fix for 192413 +-- if(FIRST_TIME) then +-- GSR <= '1', +---- undo CR fix for 192413 +---- '0' after 100 ns; +-- '0' after 1 ns; +-- FIRST_TIME := false; +-- end if; +-- wait; +-- end process prcs_gsr; + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(O_zd) + begin +-- CR fix for 221551 +-- O <= O_zd after SYNC_PATH_DELAY; + O <= O_zd; + end process prcs_output; +--#################################################################### + +end BUFGCTRL_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/bufgmux_virtex4.vhd,v 1.5 2004/04/08 23:09:36 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Mux Buffer +-- /___/ /\ Filename : BUFGMUX_VIRTEX4.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:17:58 PST 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BUFGMUX_VIRTEX4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_arith.all; + +library unisim; +use unisim.vpkg.all; +use unisim.vcomponents.all; + +entity BUFGMUX_VIRTEX4 is + + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); + +end BUFGMUX_VIRTEX4; + + +architecture BUFGMUX_VIRTEX4_V OF BUFGMUX_VIRTEX4 is + + + signal SigPullUp : std_ulogic := '1'; + signal SigPullDown : std_ulogic := '0'; + signal NOT_S : std_ulogic := 'X'; + +begin + + NOT_S <= NOT S; + +---------------------------------------------------------------------- +----------- Instant BUFGCTRL ------------------------------------- +---------------------------------------------------------------------- + INST_BUFGCTRL : BUFGCTRL + generic map ( + INIT_OUT => 0, + PRESELECT_I0 => true, + PRESELECT_I1 => false + ) + port map ( + O => O, + + CE0 => SigPullUp, + CE1 => SigPullUp, + I0 => I0, + I1 => I1, + IGNORE0 => SigPullDown, + IGNORE1 => SigPullDown, + S0 => NOT_S, + S1 => S + ); +end BUFGMUX_VIRTEX4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/bufio.vhd,v 1.5 2004/04/08 23:09:36 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Local Clock Buffer for I/O +-- /___/ /\ Filename : BUFIO.v +-- \ \ / \ Timestamp : Fri Mar 26 08:17:58 PST 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL BUFIO ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity BUFIO is + port( + O : out std_ulogic; + + I : in std_ulogic + ); + +end BUFIO; + +architecture BUFIO_V of BUFIO is +begin + O <= I after 0 ps; +end BUFIO_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / Regional Clock Buffer +-- /___/ /\ Filename : BUFR.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:18:19 PST 2004 +-- \___\/\___\ +-- Revision: +-- 03/23/04 - Initial version. +-- 04/04/2005 - Add SIM_DEVICE paramter to support rainier. CE pin has 4 clock +-- latency for Virtex 4 and none for Rainier +-- 06/30/2005 - CR # 211199 -- removed sync path delay. Made delayed start only +-- depend on CE (not CLR) +-- 07/25/05 - Updated names to Virtex5 +-- 08/31/05 - Add ce_en to sensitivity list of i_in which make ce asynch. +-- 05/23/06 - Add clk_count =0 and first_time=true when CE = 0 (CR 232206). +-- 08/09/06 - Initial output (CR217760). +-- End Revision + + +----- CELL BUFR ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + + +library unisim; +use unisim.vpkg.all; + +entity BUFR is + + generic( + + BUFR_DIVIDE : string := "BYPASS"; + SIM_DEVICE : string := "VIRTEX4" + ); + + port( + O : out std_ulogic; + + CE : in std_ulogic; + CLR : in std_ulogic; + I : in std_ulogic + ); + +end BUFR; + +architecture BUFR_V OF BUFR is + + +-- 06/30/2005 - CR # 211199 -- +-- constant SYNC_PATH_DELAY : time := 100 ps; + + signal CE_ipd : std_ulogic := 'X'; + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := '0'; + signal I_ipd : std_ulogic := 'X'; + signal CLR_ipd : std_ulogic := 'X'; + + signal CE_dly : std_ulogic := 'X'; + signal GSR_dly : std_ulogic := '0'; + signal I_dly : std_ulogic := 'X'; + signal CLR_dly : std_ulogic := 'X'; + + signal O_zd : std_ulogic := '0'; + signal O_viol : std_ulogic := '0'; + + signal q4_sig : std_ulogic := 'X'; + signal ce_en : std_ulogic; + + signal divide : boolean := false; + signal divide_by : integer := -1; + signal FIRST_TOGGLE_COUNT : integer := -1; + signal SECOND_TOGGLE_COUNT : integer := -1; + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + CE_dly <= CE after 0 ps; + CLR_dly <= CLR after 0 ps; + GSR_dly <= GSR after 0 ps; + I_dly <= I after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + variable FIRST_TOGGLE_COUNT_var : integer := -1; + variable SECOND_TOGGLE_COUNT_var : integer := -1; + variable ODD : integer := -1; + variable divide_var : boolean := false; + variable divide_by_var : integer := -1; + + begin + if(BUFR_DIVIDE = "BYPASS") then + divide_var := false; + elsif(BUFR_DIVIDE = "1") then + divide_var := true; + divide_by_var := 1; + FIRST_TOGGLE_COUNT_var := 1; + SECOND_TOGGLE_COUNT_var := 1; + elsif(BUFR_DIVIDE = "2") then + divide_var := true; + divide_by_var := 2; + FIRST_TOGGLE_COUNT_var := 2; + SECOND_TOGGLE_COUNT_var := 2; + elsif(BUFR_DIVIDE = "3") then + divide_var := true; + divide_by_var := 3; + FIRST_TOGGLE_COUNT_var := 2; + SECOND_TOGGLE_COUNT_var := 4; + elsif(BUFR_DIVIDE = "4") then + divide_var := true; + divide_by_var := 4; + FIRST_TOGGLE_COUNT_var := 4; + SECOND_TOGGLE_COUNT_var := 4; + elsif(BUFR_DIVIDE = "5") then + divide_var := true; + divide_by_var := 5; + FIRST_TOGGLE_COUNT_var := 4; + SECOND_TOGGLE_COUNT_var := 6; + elsif(BUFR_DIVIDE = "6") then + divide_var := true; + divide_by_var := 6; + FIRST_TOGGLE_COUNT_var := 6; + SECOND_TOGGLE_COUNT_var := 6; + elsif(BUFR_DIVIDE = "7") then + divide_var := true; + divide_by_var := 7; + FIRST_TOGGLE_COUNT_var := 6; + SECOND_TOGGLE_COUNT_var := 8; + elsif(BUFR_DIVIDE = "8") then + divide_var := true; + divide_by_var := 8; + FIRST_TOGGLE_COUNT_var := 8; + SECOND_TOGGLE_COUNT_var := 8; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " BUFR_DIVIDE ", + EntityName => "/BUFR", + GenericValue => BUFR_DIVIDE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " BYPASS, 1, 2, 3, 4, 5, 6, 7 or 8 ", + TailMsg => "", + MsgSeverity => ERROR + ); + end if; + + if (SIM_DEVICE /= "VIRTEX4" and SIM_DEVICE /= "VIRTEX5") then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SIM_DEVICE ", + EntityName => "/BUFR", + GenericValue => SIM_DEVICE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " VIRTEX4 or VIRTEX5 ", + TailMsg => "", + MsgSeverity => ERROR + ); + end if; + + FIRST_TOGGLE_COUNT <= FIRST_TOGGLE_COUNT_var; + SECOND_TOGGLE_COUNT <= SECOND_TOGGLE_COUNT_var; + + divide <= divide_var; + divide_by <= divide_by_var; + + wait; + end process prcs_init; +--#################################################################### +--##### CLOCK_ENABLE ##### +--#################################################################### + prcs_ce:process(I_Dly, GSR_dly) + variable fall_i_count : integer := 0; + variable q4_var : std_ulogic := '0'; + variable q3_var : std_ulogic := '0'; + variable q2_var : std_ulogic := '0'; + variable q1_var : std_ulogic := '0'; + begin +-- 06/30/2005 - CR # 211199 -- removed CLR_dly dependency + if(GSR_dly = '1') then + q4_var := '0'; + q3_var := '0'; + q2_var := '0'; + q1_var := '0'; + elsif(GSR_dly = '0') then + if(falling_edge(I_dly)) then + q4_var := q3_var; + q3_var := q2_var; + q2_var := q1_var; + q1_var := CE_dly; + end if; + + q4_sig <= q4_var; + end if; + end process prcs_ce; + + ce_en <= CE_dly when (SIM_DEVICE = "VIRTEX5") else q4_sig; + +--#################################################################### +--##### CLK-I ##### +--#################################################################### + prcs_I:process(I_dly, GSR_dly, CLR_dly, ce_en) + variable clk_count : integer := 0; + variable toggle_count : integer := 0; + variable first : boolean := true; + variable FIRST_TIME : boolean := true; + begin + if(divide) then + if((GSR_dly = '1') or (CLR_dly = '1')) then + O_zd <= '0'; + clk_count := 0; + FIRST_TIME := true; + elsif((GSR_dly = '0') and (CLR_dly = '0')) then + if(ce_en = '1') then + if((I_dly='1') and (FIRST_TIME)) then + O_zd <= '1'; + first := true; + toggle_count := FIRST_TOGGLE_COUNT; + FIRST_TIME := false; + elsif ((I_dly'event) and ( FIRST_TIME = false)) then + if(clk_count = toggle_count) then + O_zd <= not O_zd; + clk_count := 0; + first := not first; + if(first = true) then + toggle_count := FIRST_TOGGLE_COUNT; + else + toggle_count := SECOND_TOGGLE_COUNT; + end if; + end if; + end if; + + if (FIRST_TIME = false) then + clk_count := clk_count + 1; + end if; + else + clk_count := 0; + FIRST_TIME := true; + end if; + end if; + else + O_zd <= I_dly; + end if; + end process prcs_I; + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(O_zd) + begin +-- 06/30/2005 - CR # 211199 -- +-- O <= O_zd after SYNC_PATH_DELAY; + O <= O_zd; + end process prcs_output; +--#################################################################### + + +end BUFR_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/capture_virtex4.vhd,v 1.5 2004/04/08 18:46:30 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Register State Capture for Bitstream Readback for VIRTEX4 +-- /___/ /\ Filename : CAPTURE_VIRTEX4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:03 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL CAPTURE_VIRTEX4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CAPTURE_VIRTEX4 is + generic( + ONESHOT : boolean := true + ); + port( + CAP : in std_ulogic; + CLK : in std_ulogic + ); + +end CAPTURE_VIRTEX4; + +architecture CAPTURE_VIRTEX4_V of CAPTURE_VIRTEX4 is + +begin +end CAPTURE_VIRTEX4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/dcireset.vhd,v 1.7 2005/03/10 22:45:35 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Reset for DCI State Machine +-- /___/ /\ Filename : DCIRESET.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:17:58 PST 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL DCIRESET ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + + +library unisim; +use unisim.vpkg.all; + +entity DCIRESET is + + port( + LOCKED : out std_ulogic; + + RST : in std_ulogic + ); + +end DCIRESET; + +architecture DCIRESET_V OF DCIRESET is + +begin + + -------------------- + -- BEHAVIOR SECTION + -------------------- + + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_rst:process(RST) + variable RiseTime : time := 0 ps; + variable FallTime : time := 0 ps; + variable HighPuLse : time := 0 ps; + variable LowPuLse : time := 0 ps; + + begin + + if(rising_edge(RST)) then + RiseTime := now; + if(RiseTime > 0 ps) then + LowPulse := RiseTIme - FallTime; + end if; + + if(LowPulse < 100 ns) then + assert false + report "Timing Violation Error : The low pulse of RST signal in DCIRESET has to be greater than 100 ns" + severity Error; + end if; + end if; + + if(falling_edge(RST)) then + FallTime := now; + if(FallTime > 0 ps) then + HighPulse := FallTime - RiseTime; + end if; + + if(HighPulse < 100 ns) then + assert false + report "Timing Violation Error : The high pulse of RST signal in DCIRESET has to be greater than 100 ns" + severity Error; + end if; + end if; + + if(RST = '1') then + LOCKED <= '0' after 0 ns; + elsif(RST = '0') then + LOCKED <= '1' after 100 ns; + end if; + end process prcs_rst; +end DCIRESET_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/dcm_adv.vhd,v 1.29.4.5 2008/03/28 19:14:21 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Digital Clock Manager with Advanced Features +-- /___/ /\ Filename : DCM_ADV.vhd +-- \ \ / \ Timestamp : Fri Jun 18 10:57:23 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 04/22/05 - Change DRP set clkfx M/D value effected on RST=1, not rising +-- edge. (CR 206731) +-- 05/03/05 - Made changes for speed improvement: seperate process for output +-- clocks; Use senstivity list instead of wait on; remove vital +-- timing check related code. +-- 05/11/05 - Add attribute DCM_AUTOCALIBRATION (CR 208095). +-- Add clkin alignment check control to remove the glitch when +-- clkin stopped. (CR207409). +-- 05/25/05 - Seperate clock_second_pos and neg to another process due to +-- wait caused unreset. (CR 208771) +-- 06/03/05 - Use after instead wait for clk0_out(CR209283). +-- Update error message (CR 209076). +-- 07/05/05 - Use counter to generate clkdv_out to align with clk0_out. (CR211465). +-- 07/25/05 - Set CLKIN_PERIOD default to 10.0ns to (CR 213190). +-- 08/30/05 - Change reset for CLK270, CLK180, etc (CR 213641). +-- 09/08/05 - Add positive edge trig to dcm_maximum_period_check_v. (CR 216828). +-- 12/05/05 - Add warning for un-used DRP address use. (CR 221885) +-- 12/22/05 - LOCKED = x when RST less than 3 clock cycles (CR 222795) +-- 01/06/06 - Remove GSR from 3 cycle check. (223099). +-- 01/12/06 - Remove GSR from reset logic. (223099). +-- 01/26/06 - Add reset to maximum period check module (CR 224287). +-- 02/28/06 - remove 1 ps in clkfx_out block to support fs resolution. (CR222390) +-- Add SIM_DEVICE generic to support V5 and V4 M and D for CLKFX (BT#1003). +-- Connect DO bit 4 to 15 to 0. (CR 226209) +-- 08/10/06 - Set PSDONE to 0 when CLKOUT_PHASE_SHIFT=FIXED (CR 227018). +-- 03/07/07 - Change DRP CLKFX Multiplier to bit 15 to 8 and Divider to bit 7 to 0. +-- (CR 435600). +-- 04/06/07 - Enable the clock out in clock low time after reset in model +-- clock_divide_by_2 (CR 437471). +-- 09/20/07 - Use 1.5 factor for clock stopped check when CLKIN divide by 2 set(CR446707). +-- 11/01/07 - Add DRP DFS_FREQUENCY_MODE and DLL_FREQUENCY_MODE read/write support (CR435651) +-- 12/20/07 - Add DRP CLKIN_DIV_BY_2 read/write support (CR457282) +-- 02/21/08 - Align clk2x to both clk0 pos and neg edges. (CR467858). +-- 03/01/08 - Disable alignment of clkfb and clkin_fb check when ps_lock high (CR468893). +-- 03/11/08 - Not check clock lost when negative edge period smaller than positive edge +-- period in dcm_adv_clock_lost module (CR469499). +-- 03/12/08 - always generate clk2x with even duty cycle regardless CLKIN duty cycle.(CR467858). +-- End Revision + + +----- dcm_adv_clock_divide_by_2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity dcm_adv_clock_divide_by_2 is + port( + clock_out : out std_ulogic := '0'; + + clock : in std_ulogic; + clock_type : in std_ulogic; + rst : in std_ulogic + ); +end dcm_adv_clock_divide_by_2; + +architecture dcm_adv_clock_divide_by_2_V of dcm_adv_clock_divide_by_2 is + signal clock_div2 : std_ulogic := '0'; + signal rst_reg : std_logic_vector(2 downto 0); + signal clk_src : std_ulogic; +begin + + CLKIN_DIVIDER : process + begin + if (rising_edge(clock)) then + clock_div2 <= not clock_div2; + end if; + wait on clock; + end process CLKIN_DIVIDER; + + gen_reset : process + begin + if (rising_edge(clock)) then + rst_reg(0) <= rst; + rst_reg(1) <= rst_reg(0) and rst; + rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst; + end if; + wait on clock; + end process gen_reset; + + clk_src <= clock_div2 when (clock_type = '1') else clock; + + assign_clkout : process + begin + if (rst = '0') then + clock_out <= clk_src; + elsif (rst = '1') then + clock_out <= '0'; + wait until falling_edge(rst_reg(2)); + if (clk_src = '1') then + wait until falling_edge(clk_src); + end if; + end if; + wait on clk_src, rst, rst_reg; + end process assign_clkout; + +end dcm_adv_clock_divide_by_2_V; + +----- dcm_adv_maximum_period_check ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library STD; +use STD.TEXTIO.all; + +entity dcm_adv_maximum_period_check is + generic ( + InstancePath : string := " "; + + clock_name : string := ""; + maximum_period : time); + port( + clock : in std_ulogic; + rst : in std_ulogic + ); +end dcm_adv_maximum_period_check; + +architecture dcm_adv_maximum_period_check_V of dcm_adv_maximum_period_check is +begin + + MAX_PERIOD_CHECKER : process + variable clock_edge_previous : time := 0 ps; + variable clock_edge_current : time := 0 ps; + variable clock_period : time := 0 ps; + variable Message : line; + begin + if (rising_edge(clock)) then + clock_edge_previous := clock_edge_current; + clock_edge_current := NOW; + + if (clock_edge_previous > 0 ps ) then + clock_period := clock_edge_current - clock_edge_previous; + end if; + + if (clock_period > maximum_period and rst = '0') then + Write ( Message, string'(" Warning : Input Clock Period of ")); + Write ( Message, clock_period ); + Write ( Message, string'(" on the ") ); + Write ( Message, clock_name ); + Write ( Message, string'(" port ") ); + Write ( Message, string'(" of DCM_ADV instance ") ); + Write ( Message, string'(" exceeds allowed value of ") ); + Write ( Message, maximum_period ); + Write ( Message, string'(" at simulation time ") ); + Write ( Message, clock_edge_current ); + Write ( Message, '.' & LF ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + end if; + end if; + wait on clock; + end process MAX_PERIOD_CHECKER; +end dcm_adv_maximum_period_check_V; + +----- dcm_adv_clock_lost ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity dcm_adv_clock_lost is + port( + lost : out std_ulogic := '0'; + + clock : in std_ulogic; + enable : in boolean := false; + rst : in std_ulogic + ); +end dcm_adv_clock_lost; + +architecture dcm_adv_clock_lost_V of dcm_adv_clock_lost is + signal period : time := 0 ps; + signal period_neg : time := 0 ps; + signal period_tmp_win : time := 0 ps; + signal period_neg_tmp_win : time := 0 ps; + signal period_chk_win : time := 0 ps; + signal lost_r : std_ulogic := '0'; + signal lost_f : std_ulogic := '0'; + signal lost_sig : std_ulogic := '0'; + signal clock_negedge, clock_posedge : integer := 0; + signal clock_low, clock_high : integer := 0; + signal clock_second_pos, clock_second_neg : integer := 0; +begin + + determine_period : process(clock,rst) + variable clock_edge_previous : time := 0 ps; + variable clock_edge_current : time := 0 ps; + variable period_tmp : time := 0 ps; + begin + if (rst = '1') then + period <= 0 ps; + elsif (rising_edge(clock)) then + clock_edge_previous := clock_edge_current; + clock_edge_current := NOW; + period_tmp := clock_edge_current - clock_edge_previous; + if (period /= 0 ps and (period_tmp <= period_tmp_win)) then + period <= period_tmp; + elsif (period /= 0 ps and (period_tmp > period_tmp_win)) then + period <= 0 ps; + elsif ((period = 0 ps) and (clock_edge_previous /= 0 ps) and (clock_second_pos = 1)) then + period <= period_tmp; + end if; + end if; + end process determine_period; + + period_15_p : process(period) begin + period_tmp_win <= 1.5 * period; + period_chk_win <= (period * 9.1) / 10; + end process; + + determine_period_neg : process(clock,rst) + variable clock_edge_neg_previous : time := 0 ps; + variable clock_edge_neg_current : time := 0 ps; + variable period_neg_tmp : time := 0 ps; + begin + if (rst = '1') then + period_neg <= 0 ps; + elsif (falling_edge(clock)) then + clock_edge_neg_previous := clock_edge_neg_current; + clock_edge_neg_current := NOW; + period_neg_tmp := clock_edge_neg_current - clock_edge_neg_previous; + if (period_neg /= 0 ps and (period_neg_tmp <= period_neg_tmp_win)) then + period_neg <= period_neg_tmp; + elsif (period_neg /= 0 ps and (period_neg_tmp > period_neg_tmp_win)) then + period_neg <= 0 ps; + elsif ((period_neg = 0 ps) and (clock_edge_neg_previous /= 0 ps) and (clock_second_neg = 1)) then + period_neg <= period_neg_tmp; + end if; + end if; + end process determine_period_neg; + + period_15_neg_p : process(period_neg) begin + period_neg_tmp_win <= 1.5 * period_neg; + end process; + + CLOCK_LOST_CHECKER : process + + begin + if (rst = '1') then + clock_low <= 0; + clock_high <= 0; + clock_posedge <= 0; + clock_negedge <= 0; + else + if (rising_edge(clock)) then + clock_low <= 0; + clock_high <= 1; + clock_posedge <= 0; + clock_negedge <= 1; + end if; + + if (falling_edge(clock)) then + clock_low <= 1; + clock_high <= 0; + clock_posedge <= 1; + clock_negedge <= 0; + end if; + end if; + + wait on clock, rst; + end process CLOCK_LOST_CHECKER; + + CLOCK_SECOND_P : process + begin + if (rst = '1') then + clock_second_pos <= 0; + clock_second_neg <= 0; + else + if (rising_edge(clock)) then + clock_second_pos <= 1; + end if; + if (falling_edge(clock)) then + clock_second_neg <= 1; + end if; + end if; + wait on clock, rst; + end process CLOCK_SECOND_P; + + + SET_RESET_LOST_R : process + begin + if (rst = '1') then + lost_r <= '0'; + else + if ((enable = true) and (clock_second_pos = 1))then + if (rising_edge(clock)) then + wait for 0 ps; + wait for 0 ps; + wait for 0 ps; + if (period /= 0 ps) then + lost_r <= '0'; + end if; + wait for period_chk_win; + if ((clock_low /= 1) and (clock_posedge /= 1) and (rst = '0')) then + lost_r <= '1'; + end if; + end if; + end if; + end if; + wait on clock, rst; + end process SET_RESET_LOST_R; + + SET_RESET_LOST_F : process + begin + if (rst = '1') then + lost_f <= '0'; + else + if ((enable = true) and (clock_second_neg = 1))then + if (falling_edge(clock)) then + if (period /= 0 ps) then + lost_f <= '0'; + end if; + wait for period_chk_win; + if ((clock_high /= 1) and (clock_negedge /= 1) and (rst = '0') and (period <= period_neg)) then + lost_f <= '1'; + end if; + end if; + end if; + end if; + wait on clock, rst; + end process SET_RESET_LOST_F; + + assign_lost : process + begin + if (enable = true) then + if (lost_r'event) then + lost <= lost_r; + end if; + if (lost_f'event) then + lost <= lost_f; + end if; + end if; + wait on lost_r, lost_f; + end process assign_lost; +end dcm_adv_clock_lost_V; + + + +----- CELL DCM_ADV ----- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.NUMERIC_STD.all; + + + + +library STD; +use STD.TEXTIO.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity DCM_ADV is + generic ( + TimingChecksOn : boolean := true; + InstancePath : string := " "; + Xon : boolean := true; + MsgOn : boolean := false; + + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := false; + CLKIN_PERIOD : real := 10.0; --non-simulatable + CLKOUT_PHASE_SHIFT : string := "NONE"; + CLK_FEEDBACK : string := "1X"; + DCM_AUTOCALIBRATION : boolean := true; + DCM_PERFORMANCE_MODE : string := "MAX_SPEED"; -- non-simulatable + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; --non-simulatable + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DUTY_CYCLE_CORRECTION : boolean := true; + FACTORY_JF : bit_vector := X"F0F0"; --non-simulatable + + + PHASE_SHIFT : integer := 0; + + + SIM_DEVICE : string := "VIRTEX4"; + STARTUP_WAIT : boolean := false --non-simulatable + ); + + port ( + CLK0 : out std_ulogic := '0'; + CLK180 : out std_ulogic := '0'; + CLK270 : out std_ulogic := '0'; + CLK2X : out std_ulogic := '0'; + CLK2X180 : out std_ulogic := '0'; + CLK90 : out std_ulogic := '0'; + CLKDV : out std_ulogic := '0'; + CLKFX : out std_ulogic := '0'; + CLKFX180 : out std_ulogic := '0'; + DO : out std_logic_vector(15 downto 0) := "0000000000000000"; + DRDY : out std_ulogic := '0'; + LOCKED : out std_ulogic := '0'; + PSDONE : out std_ulogic := '0'; + + + CLKFB : in std_ulogic := '0'; + CLKIN : in std_ulogic := '0'; + DADDR : in std_logic_vector(6 downto 0) := "0000000"; + DCLK : in std_ulogic := '0'; + DEN : in std_ulogic := '0'; + DI : in std_logic_vector(15 downto 0) := "0000000000000000"; + DWE : in std_ulogic := '0'; + PSCLK : in std_ulogic := '0'; + PSEN : in std_ulogic := '0'; + PSINCDEC : in std_ulogic := '0'; + RST : in std_ulogic := '0' + ); + + + +end DCM_ADV; + +architecture DCM_ADV_V of DCM_ADV is + + + component dcm_adv_clock_divide_by_2 + port( + clock_out : out std_ulogic; + + clock : in std_ulogic; + clock_type : in std_ulogic; + rst : in std_ulogic + ); + end component; + + component dcm_adv_maximum_period_check + generic ( + InstancePath : string := " "; + + clock_name : string := ""; + maximum_period : time); + port( + clock : in std_ulogic; + rst : in std_ulogic + ); + end component; + + component dcm_adv_clock_lost + port( + lost : out std_ulogic; + + clock : in std_ulogic; + enable : in boolean := false; + rst : in std_ulogic + ); + end component; + + + constant MAXPERCLKIN : time := 1000000 ps; + constant MAXPERPSCLK : time := 100000000 ps; + constant SIM_CLKIN_CYCLE_JITTER : time := 300 ps; + constant SIM_CLKIN_PERIOD_JITTER : time := 1000 ps; + + signal clkfb_ipd : std_ulogic; + signal clkin_ipd : std_ulogic; + signal daddr_ipd : std_logic_vector(6 downto 0); + signal dclk_ipd : std_ulogic; + signal den_ipd : std_ulogic; + signal di_ipd : std_logic_vector(15 downto 0); + signal dwe_ipd : std_ulogic; + signal psclk_ipd : std_ulogic; + signal psen_ipd : std_ulogic; + signal psincdec_ipd : std_ulogic; + signal rst_ipd : std_ulogic; + + signal CLKIN_dly : std_ulogic; + signal CLKFB_dly : std_ulogic; + signal RST_dly : std_ulogic; + signal PSINCDEC_dly : std_ulogic; + signal PSEN_dly : std_ulogic; + signal PSCLK_dly : std_ulogic; + signal DADDR_dly : std_logic_vector(6 downto 0); + signal DI_dly : std_logic_vector(15 downto 0); + signal DWE_dly : std_ulogic; + signal DEN_dly : std_ulogic; + signal DCLK_dly : std_ulogic; + signal GSR_dly : std_ulogic := '0'; + + signal clk0_out : std_ulogic := '0'; + signal clk2x_out : std_ulogic := '0'; + signal clkdv_out : std_ulogic := '0'; + signal clkfx_out : std_ulogic := '0'; + signal drdy_out : std_ulogic := '0'; + signal do_out : std_logic_vector(15 downto 0) := "0000000000000000"; + signal do_out_reg : std_logic_vector(15 downto 0) := "0000000000000000"; + signal do_out_s : std_logic_vector(15 downto 0) := "0000000000000000"; + signal do_out_drp : std_logic_vector(15 downto 0) := "0000000000000000"; + signal do_out_drp1 : std_logic_vector(15 downto 0) := "0000000000000000"; + signal do_stat_en : std_ulogic := '1'; + signal clkfx_md_reg : std_logic_vector(15 downto 0); + signal daddr_in_lat : std_logic_vector(6 downto 0); + signal clkdv_cnt : integer := 0; + signal locked_out : std_ulogic := '0'; + signal psdone_out : std_ulogic := '0'; + + signal locked_out_tmp : std_ulogic; + + signal locked_pulse : std_ulogic; + + signal ps_overflow_out, ps_lock : std_ulogic := '0'; + + signal clkfb_type : integer; + signal divide_type : integer; + signal clkin_type : std_ulogic := '0'; + signal ps_type : integer; + signal deskew_adjust_mode : integer; + signal dfs_mode_type : std_ulogic; + signal dll_mode_type : std_logic_vector(1 downto 0); + signal dfs_mode_reg : std_logic_vector(15 downto 0); + signal dll_mode_reg : std_logic_vector(15 downto 0); + signal clkin_div2_reg : std_logic_vector(15 downto 0); + signal sim_device_type : std_ulogic; + signal clk1x_type : integer; + signal ps_in_current, ps_min, ps_max : integer; + + signal lock_period, lock_delay, lock_clkin, lock_clkfb : std_ulogic := '0'; + signal lock_out : std_logic_vector(1 downto 0) := "00"; + signal lock_out1_neg : std_ulogic := '0'; + signal locked_out_out : std_ulogic := '0'; + + signal lock_fb, lock_ps, lock_ps_dly : std_ulogic := '0'; + signal fb_delay_found : std_ulogic := '0'; + + signal clkin_div : std_ulogic; + signal clkin_ps : std_ulogic; + signal clkin_fb : std_ulogic; + + + signal ps_delay : time := 0 ps; + + + type real_array_usr is array (2 downto 0) of time; + signal clkin_period_real : real_array_usr := (0.000 ns, 0.000 ns, 0.000 ns); + signal period : time := 0 ps; + signal period_25 : time := 0 ps; + signal period_50 : time := 0 ps; + signal period_div : time := 0 ps; + signal period_orig : time := 0 ps; + signal period_stop_ck : time := 0 ps; + signal period_ps : time := 0 ps; + signal clkout_delay : time := 0 ps; + signal fb_delay : time := 0 ps; + signal period_fx, remain_fx : time := 0 ps; + signal period_dv_high, period_dv_low : time := 0 ps; + signal cycle_jitter, period_jitter : time := 0 ps; + + signal clkin_window, clkfb_window : std_ulogic := '0'; + signal rst_reg : std_logic_vector(2 downto 0) := "000"; + signal rst_flag : std_ulogic := '0'; + + signal numerator : integer := CLKFX_MULTIPLY; + signal denominator : integer := CLKFX_DIVIDE; + signal gcd : integer := 1; + + signal clkin_lost_out : std_ulogic := '0'; + signal clkfx_lost_out : std_ulogic := '0'; + signal clkfb_lost_out : std_ulogic := '0'; + + signal remain_fx_temp : integer := 0; + + + signal clk0_sig : std_ulogic := '0'; + signal clk2x_sig : std_ulogic := '0'; + signal clkfx_sig : std_ulogic := '0'; + + signal first_time_locked : boolean := false; + + signal mem : std_logic_vector(1521 downto 0); + + signal drp_lock : std_ulogic := '0'; + signal drp_lock1 : std_ulogic := '0'; + + constant CLKFX_MULTIPLY_ADDR : integer := 80; + constant CLKFX_DIVIDE_ADDR : integer := 82; + constant PHASE_SHIFT_ADDR : integer := 85; + constant DFS_FREQ_MODE_ADDR : integer := 65; + constant DLL_FREQ_MODE_ADDR : integer := 81; + constant CLKIN_DIV_BY2_ADDR : integer := 68; + + constant PHASE_SHIFT_KICK_OFF_ADDR : integer := 17; + + constant DCM_DEFAULT_STATUS_ADDR : integer := 0; + + signal clkfx_multiply_drp : integer := CLKFX_MULTIPLY; + signal clkfx_divide_drp : integer := CLKFX_DIVIDE; + signal ps_in_drp : integer := 0; + + + signal single_step_done : std_ulogic := '0'; + + signal ps_drp_lock : std_ulogic := '0'; + signal ps_kick_off_cmd : std_ulogic := '0'; + + signal clock_stopped : std_ulogic := '1'; + signal clock_stopped_factor : real := 2.0; + + signal inc_dec : std_ulogic; + + signal tap_delay_step : time; + + signal en_status : boolean := false; + + signal ps_overflow_out_ext : std_ulogic := '0'; + signal clkin_lost_out_ext : std_ulogic := '0'; + signal clkfx_lost_out_ext : std_ulogic := '0'; + signal clkfb_lost_out_ext : std_ulogic := '0'; + + signal lock_period_dly : std_ulogic := '0'; + signal lock_period_pulse : std_ulogic := '0'; + + signal clkin_chkin, clkfb_chkin : std_ulogic := '0'; + signal chk_enable, chk_rst : std_ulogic := '0'; + + signal rst_input : std_ulogic; + + +begin + INITPROC : process + variable Message : line; + + variable FACTORY_JF_slv : std_logic_vector(15 downto 0) := To_StdLogicVector(FACTORY_JF); + begin + detect_resolution + (model_name => "DCM_ADV" + ); + if (CLKDV_DIVIDE = 1.5) then + divide_type <= 3; + elsif (CLKDV_DIVIDE = 2.0) then + divide_type <= 4; + elsif (CLKDV_DIVIDE = 2.5) then + divide_type <= 5; + elsif (CLKDV_DIVIDE = 3.0) then + divide_type <= 6; + elsif (CLKDV_DIVIDE = 3.5) then + divide_type <= 7; + elsif (CLKDV_DIVIDE = 4.0) then + divide_type <= 8; + elsif (CLKDV_DIVIDE = 4.5) then + divide_type <= 9; + elsif (CLKDV_DIVIDE = 5.0) then + divide_type <= 10; + elsif (CLKDV_DIVIDE = 5.5) then + divide_type <= 11; + elsif (CLKDV_DIVIDE = 6.0) then + divide_type <= 12; + elsif (CLKDV_DIVIDE = 6.5) then + divide_type <= 13; + elsif (CLKDV_DIVIDE = 7.0) then + divide_type <= 14; + elsif (CLKDV_DIVIDE = 7.5) then + divide_type <= 15; + elsif (CLKDV_DIVIDE = 8.0) then + divide_type <= 16; + elsif (CLKDV_DIVIDE = 9.0) then + divide_type <= 18; + elsif (CLKDV_DIVIDE = 10.0) then + divide_type <= 20; + elsif (CLKDV_DIVIDE = 11.0) then + divide_type <= 22; + elsif (CLKDV_DIVIDE = 12.0) then + divide_type <= 24; + elsif (CLKDV_DIVIDE = 13.0) then + divide_type <= 26; + elsif (CLKDV_DIVIDE = 14.0) then + divide_type <= 28; + elsif (CLKDV_DIVIDE = 15.0) then + divide_type <= 30; + elsif (CLKDV_DIVIDE = 16.0) then + divide_type <= 32; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLKDV_DIVIDE", + EntityName => "DCM_ADV", + InstanceName => InstancePath, + GenericValue => CLKDV_DIVIDE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if ((CLKFX_DIVIDE <= 0) or (32 < CLKFX_DIVIDE)) then + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLKFX_DIVIDE", + EntityName => "DCM_ADV", + InstanceName => InstancePath, + GenericValue => CLKFX_DIVIDE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are 1....32", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + if ((CLKFX_MULTIPLY <= 1) or (32 < CLKFX_MULTIPLY)) then + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLKFX_MULTIPLY", + EntityName => "DCM_ADV", + InstanceName => InstancePath, + GenericValue => CLKFX_MULTIPLY, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are 2....32", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + case CLKIN_DIVIDE_BY_2 is + when false => clock_stopped_factor <= 2.0; + when true => clock_stopped_factor <= 1.5; + when others => + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLKIN_DIVIDE_BY_2", + EntityName => "DCM_ADV", + InstanceName => InstancePath, + GenericValue => CLKIN_DIVIDE_BY_2, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end case; + + + if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then + ps_type <= 0; + elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then + ps_type <= 1; + if ((PHASE_SHIFT < -255) or (PHASE_SHIFT > 255)) then + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "PHASE_SHIFT", + EntityName => "DCM_ADV", + InstanceName => InstancePath, + GenericValue => PHASE_SHIFT, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are -255 ... 255", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + elsif ((CLKOUT_PHASE_SHIFT = "variable_positive") or (CLKOUT_PHASE_SHIFT = "VARIABLE_POSITIVE")) then + ps_type <= 3; + if ((PHASE_SHIFT < 0) or (PHASE_SHIFT > 255)) then + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "PHASE_SHIFT", + EntityName => "DCM_ADV", + InstanceName => InstancePath, + GenericValue => PHASE_SHIFT, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are 0 ... 255", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + elsif ((CLKOUT_PHASE_SHIFT = "variable_center") or (CLKOUT_PHASE_SHIFT = "VARIABLE_CENTER")) then + ps_type <= 4; + if ((PHASE_SHIFT < -255) or (PHASE_SHIFT > 255)) then + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "PHASE_SHIFT", + EntityName => "DCM_ADV", + InstanceName => InstancePath, + GenericValue => PHASE_SHIFT, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are -255 ... 255", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + elsif ((CLKOUT_PHASE_SHIFT = "direct") or (CLKOUT_PHASE_SHIFT = "DIRECT")) then + ps_type <= 5; + if ((PHASE_SHIFT < 0) or (PHASE_SHIFT > 1023))then + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "PHASE_SHIFT", + EntityName => "DCM_ADV", + InstanceName => InstancePath, + GenericValue => PHASE_SHIFT, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are 0 ... 1023", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLKOUT_PHASE_SHIFT", + EntityName => "DCM_ADV", + InstanceName => InstancePath, + GenericValue => CLKOUT_PHASE_SHIFT, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are NONE, FIXED, VARIABLE_POSITIVE, VARIABLE_CENTER OR DIRECT", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if ((CLK_FEEDBACK = "none") or (CLK_FEEDBACK = "NONE")) then + clkfb_type <= 0; + Write ( Message, string'(" Attribute CLK_FEEDBACK is set to value NONE.")); + Write ( Message, string'(" In this mode, the output ports CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90 and CLKDV can have any random phase relation w.r.t. input port CLKIN")); + Write ( Message, '.' & LF ); + assert false report Message.all severity note; + DEALLOCATE (Message); + elsif ((CLK_FEEDBACK = "1x") or (CLK_FEEDBACK = "1X")) then + clkfb_type <= 1; +-- elsif ((CLK_FEEDBACK = "2x") or (CLK_FEEDBACK = "2X")) then +-- clkfb_type <= 2; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLK_FEEDBACK", + EntityName => "DCM_ADV", + InstanceName => InstancePath, + GenericValue => CLK_FEEDBACK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are NONE or 1X", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if (DCM_PERFORMANCE_MODE = "MAX_SPEED") then + tap_delay_step <= 11 ps; + elsif (DCM_PERFORMANCE_MODE = "MAX_RANGE") then + tap_delay_step <= 18 ps; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "DCM_PERFORMANCE_MODE", + EntityName => "DCM_ADV", + InstanceName => InstancePath, + GenericValue => DCM_PERFORMANCE_MODE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are MAX_SPEED or MAX_RANGE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + + if ((DESKEW_ADJUST = "source_synchronous") or (DESKEW_ADJUST = "SOURCE_SYNCHRONOUS")) then + DESKEW_ADJUST_mode <= 8; + elsif ((DESKEW_ADJUST = "system_synchronous") or (DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS")) then + DESKEW_ADJUST_mode <= 11; + elsif ((DESKEW_ADJUST = "0")) then + DESKEW_ADJUST_mode <= 0; + elsif ((DESKEW_ADJUST = "1")) then + DESKEW_ADJUST_mode <= 1; + elsif ((DESKEW_ADJUST = "2")) then + DESKEW_ADJUST_mode <= 2; + elsif ((DESKEW_ADJUST = "3")) then + DESKEW_ADJUST_mode <= 3; + elsif ((DESKEW_ADJUST = "4")) then + DESKEW_ADJUST_mode <= 4; + elsif ((DESKEW_ADJUST = "5")) then + DESKEW_ADJUST_mode <= 5; + elsif ((DESKEW_ADJUST = "6")) then + DESKEW_ADJUST_mode <= 6; + elsif ((DESKEW_ADJUST = "7")) then + DESKEW_ADJUST_mode <= 7; + elsif ((DESKEW_ADJUST = "8")) then + DESKEW_ADJUST_mode <= 8; + elsif ((DESKEW_ADJUST = "9")) then + DESKEW_ADJUST_mode <= 9; + elsif ((DESKEW_ADJUST = "10")) then + DESKEW_ADJUST_mode <= 10; + elsif ((DESKEW_ADJUST = "11")) then + DESKEW_ADJUST_mode <= 11; + elsif ((DESKEW_ADJUST = "12")) then + DESKEW_ADJUST_mode <= 12; + elsif ((DESKEW_ADJUST = "13")) then + DESKEW_ADJUST_mode <= 13; + elsif ((DESKEW_ADJUST = "14")) then + DESKEW_ADJUST_mode <= 14; + elsif ((DESKEW_ADJUST = "15")) then + DESKEW_ADJUST_mode <= 15; + elsif ((DESKEW_ADJUST = "16")) then + DESKEW_ADJUST_mode <= 16; + elsif ((DESKEW_ADJUST = "17")) then + DESKEW_ADJUST_mode <= 17; + elsif ((DESKEW_ADJUST = "18")) then + DESKEW_ADJUST_mode <= 18; + elsif ((DESKEW_ADJUST = "19")) then + DESKEW_ADJUST_mode <= 19; + elsif ((DESKEW_ADJUST = "20")) then + DESKEW_ADJUST_mode <= 20; + elsif ((DESKEW_ADJUST = "21")) then + DESKEW_ADJUST_mode <= 21; + elsif ((DESKEW_ADJUST = "22")) then + DESKEW_ADJUST_mode <= 22; + elsif ((DESKEW_ADJUST = "23")) then + DESKEW_ADJUST_mode <= 23; + elsif ((DESKEW_ADJUST = "24")) then + DESKEW_ADJUST_mode <= 24; + elsif ((DESKEW_ADJUST = "25")) then + DESKEW_ADJUST_mode <= 25; + elsif ((DESKEW_ADJUST = "26")) then + DESKEW_ADJUST_mode <= 26; + elsif ((DESKEW_ADJUST = "27")) then + DESKEW_ADJUST_mode <= 27; + elsif ((DESKEW_ADJUST = "28")) then + DESKEW_ADJUST_mode <= 28; + elsif ((DESKEW_ADJUST = "29")) then + DESKEW_ADJUST_mode <= 29; + elsif ((DESKEW_ADJUST = "30")) then + DESKEW_ADJUST_mode <= 30; + elsif ((DESKEW_ADJUST = "31")) then + DESKEW_ADJUST_mode <= 31; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "DESKEW_ADJUST_MODE", + EntityName => "DCM_ADV", + InstanceName => InstancePath, + GenericValue => DESKEW_ADJUST_MODE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 1....15", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if ((DFS_FREQUENCY_MODE /= "HIGH") and (DFS_FREQUENCY_MODE /= "LOW")) then + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "DFS_FREQUENCY_MODE", + EntityName => "DCM_ADV", + InstanceName => InstancePath, + GenericValue => DFS_FREQUENCY_MODE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if ((DLL_FREQUENCY_MODE /= "HIGH") and (DLL_FREQUENCY_MODE /= "LOW")) then + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "DLL_FREQUENCY_MODE", + EntityName => "DCM_ADV", + InstanceName => InstancePath, + GenericValue => DLL_FREQUENCY_MODE, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are HIGH or LOW", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + case DUTY_CYCLE_CORRECTION is + when false => if (SIM_DEVICE = "VIRTEX4") then + clk1x_type <= 0; + else + clk1x_type <= 1; + end if; + when true => clk1x_type <= 1; + when others => + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "DUTY_CYCLE_CORRECTION", + EntityName => "DCM_ADV", + InstanceName => InstancePath, + GenericValue => DUTY_CYCLE_CORRECTION, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end case; + + if (FACTORY_JF = X"F0F0") then + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Warning", + GenericName => "FACTORY_JF", + EntityName => "DCM_ADV", + InstanceName => InstancePath, + GenericValue => SLV_TO_STR(FACTORY_JF_slv), + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute is F0F0 hex", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => warning + ); + end if; + + period_jitter <= SIM_CLKIN_PERIOD_JITTER; + cycle_jitter <= SIM_CLKIN_CYCLE_JITTER; + + case STARTUP_WAIT is + when false => null; + when true => null; + when others => + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "STARTUP_WAIT", + EntityName => "DCM_ADV", + InstanceName => InstancePath, + GenericValue => STARTUP_WAIT, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end case; + + case DCM_AUTOCALIBRATION is + when false => null; + when true => null; + when others => + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "DCM_AUTOCALIBRATION", + EntityName => "DCM_ADV", + InstanceName => InstancePath, + GenericValue => DCM_AUTOCALIBRATION, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are TRUE or FALSE", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end case; + + if ( SIM_DEVICE = "VIRTEX4") then + sim_device_type <= '0'; + elsif (SIM_DEVICE = "VIRTEX5") then + sim_device_type <= '1'; + else + Write ( Message, string'("Attribute Syntax Error : The Attribute SIM_DEVICE on DCM_ADV is set to ")); + Write ( Message, SIM_DEVICE); + Write ( Message, string'(". Legal values for this attribute are VIRTEX4 or VIRTEX5") ); + Write ( Message, '.' & LF ); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + + wait; + end process INITPROC; + +-- +-- input wire delays +-- + + CLKFB_ipd <= CLKFB; + CLKIN_ipd <= CLKIN; + DADDR_dly(6 downto 0) <= DADDR(6 downto 0); + DCLK_dly <= DCLK; + DEN_dly <= DEN; + DI_dly(15 downto 0) <= DI(15 downto 0); + DWE_dly <= DWE; + PSCLK_dly <= PSCLK; + PSEN_dly <= PSEN; + PSINCDEC_dly <= PSINCDEC; + rst_input <= RST; + + rst_ipd <= rst_input; + + i_clock_divide_by_2 : dcm_adv_clock_divide_by_2 + port map ( + clock => clkin_ipd, + clock_type => clkin_type, + rst => rst_ipd, + clock_out => clkin_div); + + i_max_clkin : dcm_adv_maximum_period_check + generic map ( + clock_name => "CLKIN", + maximum_period => MAXPERCLKIN) + + port map ( + clock => clkin_ipd, + rst => rst_ipd ); + + i_max_psclk : dcm_adv_maximum_period_check + generic map ( + clock_name => "PSCLK", + maximum_period => MAXPERPSCLK) + + port map ( + clock => PSCLK_dly, + rst => rst_ipd ); + + i_clkin_lost : dcm_adv_clock_lost + port map ( + lost => clkin_lost_out, + clock => clkin_ipd, + enable => first_time_locked, + rst => rst_ipd + ); + + i_clkfx_lost : dcm_adv_clock_lost + port map ( + lost => clkfx_lost_out, + clock => clkfx_out, + enable => first_time_locked, + rst => rst_ipd + ); + + i_clkfb_lost : dcm_adv_clock_lost + port map ( + lost => clkfb_lost_out, + clock => clkfb_ipd, + enable => first_time_locked, + rst => rst_ipd + ); + + + clkin_ps <= transport clkin_div after ps_delay; + + clkin_fb <= transport (clkin_ps and lock_fb); + + determine_period_div : process(clkin_div, rst_ipd) + variable clkin_div_edge_previous : time := 0 ps; + variable clkin_div_edge_current : time := 0 ps; + begin + if (rst_ipd = '1') then + clkin_div_edge_previous := 0 ps; + clkin_div_edge_current := 0 ps; + period_div <= 0 ps; + elsif (rising_edge(clkin_div)) then + clkin_div_edge_previous := clkin_div_edge_current; + clkin_div_edge_current := NOW; + if ((clkin_div_edge_current - clkin_div_edge_previous) <= (1.5 * period_div)) then + period_div <= clkin_div_edge_current - clkin_div_edge_previous; + elsif ((period_div = 0 ps) and (clkin_div_edge_previous /= 0 ps)) then + period_div <= clkin_div_edge_current - clkin_div_edge_previous; + end if; + end if; + end process determine_period_div; + + determine_period_ps : process(clkin_ps, rst_ipd) + variable clkin_ps_edge_previous : time := 0 ps; + variable clkin_ps_edge_current : time := 0 ps; + begin + if (rst_ipd = '1') then + clkin_ps_edge_previous := 0 ps; + clkin_ps_edge_current := 0 ps; + period_ps <= 0 ps; + elsif (rising_edge(clkin_ps)) then + clkin_ps_edge_previous := clkin_ps_edge_current; + clkin_ps_edge_current := NOW; + if ((clkin_ps_edge_current - clkin_ps_edge_previous) <= (1.5 * period_ps)) then + period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; + elsif ((period_ps = 0 ps) and (clkin_ps_edge_previous /= 0 ps)) then + period_ps <= clkin_ps_edge_current - clkin_ps_edge_previous; + end if; + end if; + end process determine_period_ps; + + assign_lock_ps_fb : process(clkin_ps, rst_ipd) + begin + if (rst_ipd = '1') then + lock_fb <= '0'; + lock_ps <= '0'; + lock_ps_dly <= '0'; + elsif (rising_edge(clkin_ps)) then + lock_ps <= lock_period; + lock_ps_dly <= lock_ps; + lock_fb <= lock_ps_dly; + end if; + end process assign_lock_ps_fb; + + calculate_clkout_delay : process(period, fb_delay, rst_ipd) + begin + if (rst_ipd = '1') then + clkout_delay <= 0 ps; + elsif (fb_delay = 0 ps) then + clkout_delay <= 0 ps; + else + clkout_delay <= period - fb_delay; + end if; + end process calculate_clkout_delay; + +-- +--generate master reset signal +-- + + gen_master_rst : process(clkin_ipd) + begin + if (rising_edge(clkin_ipd)) then + rst_reg(2) <= rst_reg(1) and rst_reg(0) and rst_input; + rst_reg(1) <= rst_reg(0) and rst_input; + rst_reg(0) <= rst_input; + end if; + end process gen_master_rst; + + check_rst_width : process(rst_input) + variable Message : line; + begin + if (rst_input = '1') then + rst_flag <= '0'; + end if; + if (falling_edge(rst_input)) then + if ((rst_reg(2) and rst_reg(1) and rst_reg(0)) = '0') then + rst_flag <= '1'; + Write ( Message, string'(" Input Error : RST on instance ")); + Write ( Message, Instancepath ); + Write ( Message, string'(" must be asserted for 3 CLKIN clock cycles. ")); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + end if; + end process check_rst_width; + +-- +--phase shift parameters +-- + + determine_phase_shift : process + variable Message : line; + variable FINE_SHIFT_RANGE : time; + variable first_time : boolean := true; + variable ps_in : integer; + variable single_step_lock : std_ulogic := '0'; + begin + if (first_time = true) then + if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then + ps_in := 256; + elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then + ps_in := PHASE_SHIFT + 256; + ps_max <= 255 + 256; + ps_min <= -255 + 256; + if (DCM_PERFORMANCE_MODE = "MAX_SPEED") then + FINE_SHIFT_RANGE := 7000 ps; + elsif (DCM_PERFORMANCE_MODE = "MAX_RANGE") then + FINE_SHIFT_RANGE := 10000 ps; + end if; + elsif ((CLKOUT_PHASE_SHIFT = "variable_positive") or (CLKOUT_PHASE_SHIFT = "VARIABLE_POSITIVE")) then + ps_in := PHASE_SHIFT + 256; + ps_max <= 255 + 256; + ps_min <= 0 + 256; + if (DCM_PERFORMANCE_MODE = "MAX_SPEED") then + FINE_SHIFT_RANGE := 7000 ps; + elsif (DCM_PERFORMANCE_MODE = "MAX_RANGE") then + FINE_SHIFT_RANGE := 10000 ps; + end if; + elsif ((CLKOUT_PHASE_SHIFT = "variable_center") or (CLKOUT_PHASE_SHIFT = "VARIABLE_CENTER")) then + ps_in := PHASE_SHIFT + 256; + ps_max <= 255 + 256; + ps_min <= -255 + 256; + if (DCM_PERFORMANCE_MODE = "MAX_SPEED") then + FINE_SHIFT_RANGE := 3500 ps; + elsif (DCM_PERFORMANCE_MODE = "MAX_RANGE") then + FINE_SHIFT_RANGE := 5000 ps; + end if; + elsif ((CLKOUT_PHASE_SHIFT = "direct") or (CLKOUT_PHASE_SHIFT = "DIRECT")) then + ps_max <= 1023; + ps_min <= 0; + if (DCM_PERFORMANCE_MODE = "MAX_SPEED") then + FINE_SHIFT_RANGE := 7000 ps; + elsif (DCM_PERFORMANCE_MODE = "MAX_RANGE") then + FINE_SHIFT_RANGE := 10000 ps; + end if; + ps_in := PHASE_SHIFT; + end if; + first_time := false; + end if; + + if ((rising_edge(rst_ipd)) or (rst_ipd = '1')) then + if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then + ps_in := 256; + elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then + ps_in := PHASE_SHIFT + 256; + elsif ((CLKOUT_PHASE_SHIFT = "variable_positive") or (CLKOUT_PHASE_SHIFT = "VARIABLE_POSITIVE")) then + ps_in := PHASE_SHIFT + 256; + elsif ((CLKOUT_PHASE_SHIFT = "variable_center") or (CLKOUT_PHASE_SHIFT = "VARIABLE_CENTER")) then + ps_in := PHASE_SHIFT + 256; + elsif ((CLKOUT_PHASE_SHIFT = "direct") or (CLKOUT_PHASE_SHIFT = "DIRECT")) then + ps_in := PHASE_SHIFT; + end if; + ps_lock <= '0'; + ps_overflow_out <= '0'; + ps_delay <= 0 ps; + else + if (rising_edge(lock_period_pulse)) then + if ((ps_type = 0) or (ps_type = 1) or (ps_type = 3) or (ps_type = 4)) then + ps_delay <= (ps_in * period_div / 256); + elsif (ps_type = 5) then + ps_delay <= ps_in * tap_delay_step; + end if; + end if; + if (rising_edge (lock_period)) then + if ((ps_type = 0) or (ps_type = 1) or (ps_type = 3) or (ps_type = 4)) then + if (PHASE_SHIFT > 0) then + if (((ps_in * period_orig) / 256) > (period_orig + FINE_SHIFT_RANGE)) then + Write ( Message, string'(" Function Error : Instance ")); + Write ( Message, Instancepath ); + Write ( Message, string'(" Requested Phase Shift = ")); + + Write ( Message, string'(" PHASE_SHIFT * PERIOD/256 = ")); + Write ( Message, PHASE_SHIFT); + Write ( Message, string'(" * ")); + Write ( Message, period_orig /256); + Write ( Message, string'(" = ")); + Write ( Message, (PHASE_SHIFT) * period_orig / 256 ); + Write ( Message, string'(" This exceeds the FINE_SHIFT_RANGE of ")); + Write ( Message, FINE_SHIFT_RANGE); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + elsif (PHASE_SHIFT < 0) then + if ((period_orig > FINE_SHIFT_RANGE) and ((ps_in * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) then + Write ( Message, string'(" Function Error : Instance ")); + Write ( Message, Instancepath ); + Write ( Message, string'(" Requested Phase Shift = ")); + + Write ( Message, string'(" PHASE_SHIFT * PERIOD/256 = ")); + Write ( Message, PHASE_SHIFT); + Write ( Message, string'(" * ")); + Write ( Message, period_orig /256); + Write ( Message, string'(" = ")); + Write ( Message, (-PHASE_SHIFT) * period_orig / 256); + Write ( Message, string'(" This exceeds the FINE_SHIFT_RANGE of ")); + Write ( Message, FINE_SHIFT_RANGE); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + end if; + end if; + if (ps_type = 5) then + if ((ps_in * tap_delay_step) > FINE_SHIFT_RANGE) then + Write ( Message, string'(" Functional Error : Allowed FINE_SHIFT_RANGE on instance ")); + Write ( Message, Instancepath ); + Write ( Message, string'(" is between 0 to ")); + Write ( Message, FINE_SHIFT_RANGE/tap_delay_step); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + end if; + end if; + + if (rising_edge(PSCLK_dly)) then + if ((ps_type = 3) or (ps_type = 4)) then + if (PSEN_dly = '1') then + if (ps_lock = '1') then + Write ( Message, string'(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift. ")); + assert false report Message.all severity warning; + DEALLOCATE (Message); + else + if (PSINCDEC_dly = '1') then + if (ps_in = ps_max) then + ps_overflow_out <= '1'; + elsif (((ps_in + 1) * period_orig / 256) > period_orig + FINE_SHIFT_RANGE) then + ps_overflow_out <= '1'; + else + ps_in := ps_in + 1; + ps_delay <= (ps_in * period_div / 256); + ps_overflow_out <= '0'; + end if; + ps_lock <= '1'; + elsif (PSINCDEC_dly = '0') then + if (ps_in = ps_min) then + ps_overflow_out <= '1'; + elsif ((period_orig > FINE_SHIFT_RANGE) and (((ps_in - 1) * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) then + ps_overflow_out <= '1'; + else + ps_in := ps_in - 1; + ps_delay <= (ps_in * period_div / 256); + ps_overflow_out <= '0'; + end if; + ps_lock <= '1'; + end if; + end if; + end if; + end if; + end if; + + if (rising_edge(PSCLK_dly)) then + if (ps_type = 5) then + if (PSEN_dly = '1') then + if (ps_lock = '1') then + Write ( Message, string'(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift. ")); + assert false report Message.all severity warning; + DEALLOCATE (Message); + else + if (PSINCDEC_dly = '1') then + if (ps_in = ps_max) then + ps_overflow_out <= '1'; + elsif (ps_in * tap_delay_step > FINE_SHIFT_RANGE) then + ps_overflow_out <= '1'; + else + ps_in := ps_in + 1; + ps_delay <= ps_in * tap_delay_step; + ps_overflow_out <= '0'; + end if; + ps_lock <= '1'; + elsif (PSINCDEC_dly = '0') then + if (ps_in = ps_min) then + ps_overflow_out <= '1'; + elsif (ps_in * tap_delay_step > FINE_SHIFT_RANGE) then + ps_overflow_out <= '1'; + else + ps_in := ps_in - 1; + ps_delay <= ps_in * tap_delay_step; + ps_overflow_out <= '0'; + end if; + ps_lock <= '1'; + end if; + end if; + end if; + end if; + end if; + + if (rising_edge(clkin_ps)) then + if (ps_type = 5) then + if (ps_drp_lock = '1') then + if (inc_dec = '1') then + if (ps_in < ps_in_drp) then + if (single_step_lock = '0') then + single_step_lock := '1'; + ps_in := ps_in + 1; + ps_delay <= ps_delay + tap_delay_step; + end if; + elsif (ps_in = ps_in_drp) then + ps_drp_lock <= '0'; + end if; + elsif (inc_dec = '0') then + if (ps_in > ps_in_drp) then + if (single_step_lock = '0') then + single_step_lock := '1'; + ps_in := ps_in - 1; + ps_delay <= ps_delay - tap_delay_step; + end if; + elsif (ps_in = ps_in_drp) then + ps_drp_lock <= '0'; + end if; + end if; + end if; + end if; + end if; + end if; + + ps_in_current <= ps_in; + if (falling_edge(psdone_out)) then + ps_lock <= '0'; + end if; + + if (single_step_lock = '1') then + wait until (rising_edge(clkin_ps)); + wait until (rising_edge(clkin_ps)); + wait until (rising_edge(clkin_ps)); + wait until (rising_edge(clkin_ps)); + single_step_lock := '0'; + end if; + + if (rising_edge(ps_kick_off_cmd)) then + wait until (rising_edge(DCLK_dly)); + wait until (rising_edge(DCLK_dly)); + wait until (rising_edge(clkin_ps)); + wait until (rising_edge(clkin_ps)); + wait until (rising_edge(clkin_ps)); + wait until (rising_edge(clkin_ps)); + wait until (rising_edge(clkin_ps)); + wait until (rising_edge(clkin_ps)); + ps_drp_lock <= '1'; + end if; + wait on clkin_ps, lock_period, lock_period_pulse, PSCLK_dly, rst_ipd, ps_kick_off_cmd, psdone_out; + end process determine_phase_shift; + + + drive_psdone_out : process + begin + if (ps_type /= 0 and ps_type /= 1) then + if (rising_edge(ps_lock)) then + wait until (rising_edge(clkin_ps)); + wait until (rising_edge(clkin_ps)); + wait until (rising_edge(clkin_ps)); + wait until (rising_edge(clkin_ps)); + wait until (rising_edge(psclk_dly)); + wait until (rising_edge(psclk_dly)); + psdone_out <= '1'; + wait until (rising_edge(psclk_dly)); + psdone_out <= '0'; + end if; + + if (falling_edge(ps_drp_lock)) then + if (ps_type = 5) then + wait until (rising_edge(clkin_ps)); + wait until (rising_edge(clkin_ps)); + wait until (rising_edge(clkin_ps)); + wait until (rising_edge(clkin_ps)); + wait until (rising_edge(PSCLK_dly)); + wait until (rising_edge(PSCLK_dly)); + psdone_out <= '1'; + wait until (rising_edge(PSCLK_dly)); + psdone_out <= '0'; + end if; + end if; + end if; + wait on ps_lock, ps_drp_lock; + end process drive_psdone_out; + +-- +--determine clock period +-- + process (period_orig) begin + period_stop_ck <= period_orig * clock_stopped_factor; + end process; + + determine_clock_period : process(clkin_div, rst_ipd) + variable clkin_edge_previous : time := 0 ps; + variable clkin_edge_current : time := 0 ps; + begin + if (rst_ipd = '1') then + clkin_period_real(0) <= 0 ps; + clkin_period_real(1) <= 0 ps; + clkin_period_real(2) <= 0 ps; + clkin_edge_previous := 0 ps; + clkin_edge_current := 0 ps; + elsif (rising_edge(clkin_div)) then + clkin_edge_previous := clkin_edge_current; + clkin_edge_current := NOW; + clkin_period_real(2) <= clkin_period_real(1); + clkin_period_real(1) <= clkin_period_real(0); + if (clkin_edge_previous /= 0 ps) then + clkin_period_real(0) <= clkin_edge_current - clkin_edge_previous; + end if; + elsif (falling_edge(clkin_div) ) then + if (lock_period = '1') then + if (100000000 ps < clkin_period_real(0)/1000) then + elsif ((period_stop_ck <= clkin_period_real(0)) and (clock_stopped = '0')) then + clkin_period_real(0) <= clkin_period_real(1); + end if; + end if; + end if; + end process determine_clock_period; + + evaluate_clock_period : process + variable Message : line; + begin + if (rst_ipd = '1') then + lock_period <= '0'; + clock_stopped <= '1'; + elsif (falling_edge(clkin_div) ) then + if (lock_period = '0') then + if ((clkin_period_real(0) /= 0 ps ) and (clkin_period_real(0) - cycle_jitter <= clkin_period_real(1)) and (clkin_period_real(1) <= clkin_period_real(0) + cycle_jitter) and (clkin_period_real(1) - cycle_jitter <= clkin_period_real(2)) and (clkin_period_real(2) <= clkin_period_real(1) + cycle_jitter)) then + lock_period <= '1'; + period_orig <= (clkin_period_real(0) + clkin_period_real(1) + clkin_period_real(2)) / 3; + period <= clkin_period_real(0); + end if; + elsif (lock_period = '1') then + if (100000000 ns < clkin_period_real(0)) then + Write ( Message, string'(" Warning : CLKIN stopped toggling on instance ")); + Write ( Message, Instancepath ); + Write ( Message, string'(" exceeds ")); + Write ( Message, string'(" 100 ms ")); + Write ( Message, string'(" Current CLKIN Period = ")); + Write ( Message, clkin_period_real(0)); + assert false report Message.all severity warning; + DEALLOCATE (Message); + lock_period <= '0'; + wait until (falling_edge(rst_reg(2))); + elsif ((period_stop_ck <= clkin_period_real(0)) and (clock_stopped = '0')) then + clock_stopped <= '1'; + elsif ((clkin_period_real(0) < period_orig - period_jitter) or (period_orig + period_jitter < clkin_period_real(0))) then + Write ( Message, string'(" Warning : Input Clock Period Jitter on instance ")); + Write ( Message, Instancepath ); + Write ( Message, string'(" exceeds ")); + Write ( Message, period_jitter ); + Write ( Message, string'(" Locked CLKIN Period = ")); + Write ( Message, period_orig ); + Write ( Message, string'(" Current CLKIN Period = ")); + Write ( Message, clkin_period_real(0) ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + lock_period <= '0'; + wait until (falling_edge(rst_reg(2))); + elsif ((clkin_period_real(0) < clkin_period_real(1) - cycle_jitter) or (clkin_period_real(1) + cycle_jitter < clkin_period_real(0))) then + Write ( Message, string'(" Warning : Input Clock Cycle Jitter on on instance ")); + Write ( Message, Instancepath ); + Write ( Message, string'(" exceeds ")); + Write ( Message, cycle_jitter ); + Write ( Message, string'(" Previous CLKIN Period = ")); + Write ( Message, clkin_period_real(1) ); + Write ( Message, string'(" Current CLKIN Period = ")); + Write ( Message, clkin_period_real(0) ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + lock_period <= '0'; + wait until (falling_edge(rst_reg(2))); + else + period <= clkin_period_real(0); + clock_stopped <= '0'; + end if; + end if; + end if; + wait on clkin_div, rst_ipd; + end process evaluate_clock_period; + + period_cal_p : process(period) + variable period_25_tmp : time := 0 ps; + begin + period_25_tmp := period / 4; + period_50 <= 2 * period_25_tmp; + period_25 <= period_25_tmp; + end process; + + lock_period_dly <= transport lock_period after period_50; + + lock_period_pulse <= '1' when ((lock_period = '1') and (lock_period_dly = '0')) else '0'; + +-- +--determine clock delay +-- + + determine_clock_delay : process + variable delay_edge : time := 0 ps; + variable temp1 : integer := 0; + variable temp2 : integer := 0; + variable temp : integer := 0; + variable delay_edge_current : time := 0 ps; + begin + if (rst_ipd = '1') then + fb_delay <= 0 ps; + fb_delay_found <= '0'; + elsif (rising_edge(lock_ps_dly)) then + if ((lock_period = '1') and (clkfb_type /= 0)) then + if (clkfb_type = 1) then + wait until ((rising_edge(clk0_sig)) or (rst_ipd'event)); + delay_edge := NOW; + elsif (clkfb_type = 2) then + wait until ((rising_edge(clk2x_sig)) or (rst_ipd'event)); + delay_edge := NOW; + end if; + wait until ((rising_edge(clkfb_ipd)) or (rst_ipd'event)); + temp1 := ((NOW*1) - (delay_edge*1))/ (1 ps); + temp2 := (period_orig * 1)/ (1 ps); + temp := temp1 mod temp2; + fb_delay <= temp * 1 ps; + fb_delay_found <= '1'; + end if; + end if; + wait on lock_ps_dly, rst_ipd; + end process determine_clock_delay; +-- +-- determine feedback lock +-- + GEN_CLKFB_WINDOW : process + begin + if (rst_ipd = '1') then + clkfb_window <= '0'; + elsif (rising_edge(CLKFB_ipd)) then + wait for 0 ps; + clkfb_window <= '1'; + wait for cycle_jitter; + clkfb_window <= '0'; + end if; + wait on clkfb_ipd, rst_ipd; + end process GEN_CLKFB_WINDOW; + + GEN_CLKIN_WINDOW : process + begin + if (rst_ipd = '1') then + clkin_window <= '0'; + elsif (rising_edge(clkin_fb)) then + wait for 0 ps; + clkin_window <= '1'; + wait for cycle_jitter; + clkin_window <= '0'; + end if; + wait on clkin_fb, rst_ipd; + end process GEN_CLKIN_WINDOW; + + set_reset_lock_clkin : process + begin + if (rst_ipd = '1') then + lock_clkin <= '0'; + elsif (rising_edge(clkin_fb)) then + wait for 1 ps; + if (((clkfb_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1'))) then + lock_clkin <= '1'; + else +-- if (chk_enable = '1') then + if (chk_enable = '1' and ps_lock = '0') then + lock_clkin <= '0'; + end if; + end if; + end if; + wait on clkin_fb, rst_ipd; + end process set_reset_lock_clkin; + + set_reset_lock_clkfb : process + begin + if (rst_ipd = '1') then + lock_clkfb <= '0'; + elsif (rising_edge(clkfb_ipd)) then + wait for 1 ps; + if (((clkin_window = '1') and (fb_delay_found = '1')) or ((clkin_lost_out = '1') and (lock_out(0) = '1'))) then + lock_clkfb <= '1'; + else +-- if (chk_enable = '1') then + if (chk_enable = '1' and ps_lock = '0') then + lock_clkfb <= '0'; + end if; + end if; + end if; + wait on clkfb_ipd, rst_ipd; + end process set_reset_lock_clkfb; + + assign_lock_delay : process(clkin_fb, rst_ipd) + begin + if (rst_ipd = '1') then + lock_delay <= '0'; + elsif (falling_edge(clkin_fb)) then + lock_delay <= lock_clkin or lock_clkfb; + end if; + end process; + +-- +--generate lock signal +-- + + + generate_lock : process(clkin_ps, rst_ipd) + begin + if (rst_ipd='1') then + lock_out <= "00"; + locked_out <= '0'; + lock_out1_neg <= '0'; + elsif (rising_edge(clkin_ps)) then + if (clkfb_type = 0) then + lock_out(0) <= lock_period; + else + lock_out(0) <= lock_period and lock_delay and lock_fb; + end if; + lock_out(1) <= lock_out(0); + locked_out <= lock_out(1); + elsif (falling_edge(clkin_ps)) then + lock_out1_neg <= lock_out(1); + end if; + end process generate_lock; + + locked_out_tmp <= locked_out after period_fx; + locked_pulse <= '1' when ((locked_out = '1') and (locked_out_tmp = '0')) else '0'; + + +-- +--generate the clk1x_out +-- + + gen_clk1x : process (clkin_ps, rst_ipd) + begin + if (rst_ipd = '1') then + clk0_out <= '0'; + elsif (rising_edge(clkin_ps)) then + if ((clk1x_type = 1) and (lock_out(0) = '1')) then + clk0_out <= '1', '0' after period/2; + else + clk0_out <= '1'; + end if; + elsif (falling_edge(clkin_ps)) then + if ((((clk1x_type = 1) and (lock_out(0) = '1')) = false) or ((lock_out(0) = '1') and (lock_out(1) = '0'))) then + clk0_out <= '0'; + end if; + end if; + end process gen_clk1x; + +-- +--generate the clk2x_out +-- + + gen_clk2x : process + begin + if (rst_ipd='1') then + clk2x_out <= '0'; + elsif (rising_edge(clkin_ps)) then + clk2x_out <= '1'; + wait for period_25; + clk2x_out <= '0'; + if (lock_out(0) = '1') then + wait for period_25; + clk2x_out <= '1'; + wait for period_25; + clk2x_out <= '0'; + else + wait for period_50; + end if; + end if; + wait on clkin_ps, rst_ipd; + end process gen_clk2x; + +-- +--generate the clkdv_out +-- + + gen_clkdv : process (clkin_ps, rst_ipd) + begin + if (rst_ipd='1') then + clkdv_out <= '0'; + clkdv_cnt <= 0; + elsif ((rising_edge(clkin_ps)) or (falling_edge(clkin_ps))) then + if (lock_out1_neg = '1') then + if (clkdv_cnt >= divide_type -1) then + clkdv_cnt <= 0; + else + clkdv_cnt <= clkdv_cnt + 1; + end if; + + if (clkdv_cnt < divide_type /2) then + clkdv_out <= '1'; + else + if ( ((divide_type rem (2)) > 0) and (dll_mode_type = "00")) then + clkdv_out <= '0' after (period/4); + else + clkdv_out <= '0'; + end if; + end if; + end if; + end if; + end process; + + + determine_clkfx_divide_multiply : process(rst_ipd, clkfx_multiply_drp, clkfx_divide_drp) + begin + if (rst_ipd = '1') then + numerator <= clkfx_multiply_drp; + denominator <= clkfx_divide_drp; + end if; + end process determine_clkfx_divide_multiply; + +-- +-- generate fx output signal +-- + + calculate_period_fx : process(lock_period, period) + begin + if (lock_period = '1') then + period_fx <= (period * denominator) / (numerator * 2); + remain_fx <= (((period/1 ps) * denominator) mod (numerator * 2)) * 1 ps; + end if; + end process calculate_period_fx; + + + generate_clkfx : process + variable temp : integer; + begin + if (rst_ipd = '1') then + clkfx_out <= '0'; + elsif (clkin_lost_out_ext = '1') then + if (locked_out = '1') then + wait until (falling_edge(rst_reg(2))); + end if; + elsif (rising_edge(clkin_ps)) then + if (lock_out(1) = '1') then + clkfx_out <= '1'; + temp := numerator * 2 - 1 - 1; + for p in 0 to temp loop + wait for (period_fx); + clkfx_out <= not clkfx_out; + end loop; + if (period_fx > (period / 2)) then + wait for (period_fx - (period / 2)); + end if; + end if; + if (clkin_lost_out_ext = '1') then + wait until (rising_edge(rst_ipd)); + clkfx_out <= '0'; + wait until (falling_edge(rst_reg(2))); + end if; + end if; + wait on clkin_lost_out_ext, clkin_ps, rst_ipd, rst_reg(2); + end process generate_clkfx; + + detect_first_time_locked : process + begin + if (first_time_locked = false) then + if (rising_edge(locked_out)) then + first_time_locked <= true; + end if; + end if; + wait on locked_out; + end process detect_first_time_locked; + + control_status_bits: process(clkfb_lost_out, clkfx_lost_out, clkin_lost_out, en_status, ps_overflow_out, rst_ipd) + begin + if ((rst_ipd = '1') or (en_status = false)) then + ps_overflow_out_ext <= '0'; + clkin_lost_out_ext <= '0'; + clkfx_lost_out_ext <= '0'; + clkfb_lost_out_ext <= '0'; + else + ps_overflow_out_ext <= ps_overflow_out; + clkin_lost_out_ext <= clkin_lost_out; + clkfx_lost_out_ext <= clkfx_lost_out; + clkfb_lost_out_ext <= clkfb_lost_out; + end if; + end process control_status_bits; + + do_out_s(0) <= ps_overflow_out_ext; + do_out_s(1) <= clkin_lost_out_ext; + do_out_s(2) <= clkfx_lost_out_ext; + do_out_s(3) <= clkfb_lost_out_ext; + + set_reset_en_status : process (locked_out, rst_ipd) + begin + if (rst_ipd='1') then + en_status <= false; + elsif (rising_edge(locked_out)) then + en_status <= true; + end if; + end process set_reset_en_status; + + set_reset_clkin_chkin : process (clkin_fb, chk_rst) + begin + if (chk_rst='1') then + clkin_chkin <= '0'; + elsif (rising_edge(clkin_fb)) then + clkin_chkin <= '1'; + end if; + end process set_reset_clkin_chkin; + + set_reset_clkfb_chkin : process(clkfb_ipd, chk_rst) + begin + if (chk_rst='1') then + clkfb_chkin <= '0'; + elsif (rising_edge(clkfb_ipd)) then + clkfb_chkin <= '1'; + end if; + end process set_reset_clkfb_chkin; + + chk_rst <= '1' when ((rst_ipd = '1') or (clock_stopped = '1')) else '0'; + chk_enable <= '1' when ((clkin_chkin = '1') and (clkfb_chkin = '1') and (lock_ps = '1') and (lock_fb = '1')) else '0'; + + + do_out <= do_out_drp1 when (do_stat_en = '0') else do_out_s; + + drp : process + variable first_time : boolean := true; + variable address : integer; + variable valid_daddr : boolean := false; + variable ps_drp : integer := 0; + variable dfs_mode_type_i : std_ulogic; + variable clkin_type_i : std_ulogic; + variable dll_mode_type_i : std_logic_vector(1 downto 0); + variable clkfx_m_reg : std_logic_vector(7 downto 0); + variable clkfx_d_reg : std_logic_vector(7 downto 0); + + variable Message : line; + + begin + if (first_time = true) then + clkfx_multiply_drp <= CLKFX_MULTIPLY; + clkfx_divide_drp <= CLKFX_DIVIDE; + clkfx_m_reg := STD_LOGIC_VECTOR(TO_UNSIGNED(CLKFX_MULTIPLY, 8)); + clkfx_d_reg := STD_LOGIC_VECTOR(TO_UNSIGNED(CLKFX_DIVIDE, 8)); + clkfx_md_reg <= (clkfx_m_reg & clkfx_d_reg); + if (DFS_FREQUENCY_MODE = "HIGH") then + dfs_mode_type_i := '1'; + dfs_mode_type <= '1'; + else + dfs_mode_type_i := '0'; + dfs_mode_type <= '0'; + end if; + if (DLL_FREQUENCY_MODE = "HIGH") then + dll_mode_type_i := "11"; + dll_mode_type <= "11"; + else + dll_mode_type_i := "00"; + dll_mode_type <= "00"; + end if; + if (CLKIN_DIVIDE_BY_2 = TRUE) then + clkin_type_i := '1'; + clkin_type <= '1'; + else + clkin_type_i := '0'; + clkin_type <= '0'; + end if; + dfs_mode_reg <= ("XXXXXXXXXXXXX" & dfs_mode_type_i & "XX"); + dll_mode_reg <= ("XXXXXXXXXXXX" & dll_mode_type_i & "XX"); + clkin_div2_reg <= ("XXXXX" & clkin_type_i & "XXXXXXXXXX"); + + do_stat_en <= '1'; + first_time := false; + end if; + + valid_daddr := addr_is_valid(DADDR_dly); + if (valid_daddr) then + address := slv_to_int(DADDR_dly); + end if; + + if (GSR_dly = '1') then + drp_lock <= '0'; + ps_in_drp <= 0; + ps_kick_off_cmd <= '0'; + do_out_drp <= "0000000000000000"; + do_out_drp1 <= "0000000000000000"; + do_stat_en <= '1'; + drdy_out <= '0'; + elsif (rising_edge(DCLK_dly)) then + if (DEN_dly = '1') then + if (drp_lock = '1') then + Write ( Message, string'(" Warning : DEN is high. Please wait for DRDY signal before next read/write operation through DRP. ")); + assert false report Message.all severity warning; + DEALLOCATE (Message); + else + drp_lock <= '1'; + if (DWE_dly = '0') then + if (valid_daddr) then + if (SIM_DEVICE = "VIRTEX5") then + if (address = DCM_DEFAULT_STATUS_ADDR) then + do_stat_en <= '1'; + else + do_stat_en <= '0'; + if (address = DFS_FREQ_MODE_ADDR) then + do_out_drp <= dfs_mode_reg; + elsif (address = DLL_FREQ_MODE_ADDR) then + do_out_drp <= dll_mode_reg; + elsif (address = CLKFX_MULTIPLY_ADDR) then + do_out_drp <= clkfx_md_reg; + elsif (address = CLKIN_DIV_BY2_ADDR) then + do_out_drp <= clkin_div2_reg; + else + do_out_drp <= "0000000000000000"; + end if; + end if; + end if; + end if; + end if; -- DWE_dly = '0' + + if (DWE_dly = '1') then + if (valid_daddr) then + if (address = CLKFX_MULTIPLY_ADDR) then + if (sim_device_type = '1') then + clkfx_divide_drp <= slv_to_int(DI_dly(7 downto 0)) + 1; + clkfx_multiply_drp <= slv_to_int(DI_dly(15 downto 8)) + 1; + clkfx_md_reg <= DI_dly; + else + clkfx_multiply_drp <= slv_to_int(DI_dly(4 downto 0)) + 1; + end if; + elsif (address = CLKFX_DIVIDE_ADDR and sim_device_type = '0') then + clkfx_divide_drp <= slv_to_int(DI_dly(4 downto 0)) + 1; + elsif (address = PHASE_SHIFT_ADDR) then + ps_drp := slv_to_int(DI_dly(10 downto 0)); + elsif (address = PHASE_SHIFT_KICK_OFF_ADDR) then + if (ps_kick_off_cmd = '0') then + ps_kick_off_cmd <= '1'; + ps_in_drp <= ps_drp; + if (ps_in_current < ps_drp) then + inc_dec <= '1'; + elsif (ps_in_current > ps_drp) then + inc_dec <= '0'; + end if; + end if; + elsif ((address = DFS_FREQ_MODE_ADDR) and (sim_device_type = '1')) then + dfs_mode_reg <= DI_dly; + dfs_mode_type <= DI_dly(2); + elsif ((address = DLL_FREQ_MODE_ADDR) and (sim_device_type = '1')) then + dll_mode_reg <= DI_dly; + dll_mode_type <= DI_dly(3 downto 2); + elsif ((address = CLKIN_DIV_BY2_ADDR) and (sim_device_type = '1')) then + clkin_div2_reg <= DI_dly; + clkin_type <= DI_dly(10); + else + Write ( Message, string'(" Warning : Address DADDR=")); + Write ( Message, address); + Write ( Message, string'(" on the DCM_ADV instance is unsupported") ); + Write ( Message, '.' & LF ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + end if; + end if; + end if; -- DWE = 1 +-- end if; + end if; + end if; + if (drp_lock = '1') then + drp_lock1 <= '1'; + end if; + if (drp_lock1 = '1') then + drp_lock <= '0'; + drp_lock1 <= '0'; + drdy_out <= '1'; + do_out_drp1 <= do_out_drp; + do_out_drp <= "0000000000000000"; + end if; + + if (drdy_out = '1') then + drdy_out <= '0'; + do_out_drp1 <= "0000000000000000"; + end if; + + if (falling_edge(ps_drp_lock)) then + if (ps_kick_off_cmd = '1') then + ps_kick_off_cmd <= '0'; + end if; + end if; + end if; -- GSR_dly + + wait on DCLK_dly, ps_drp_lock, GSR_dly; + + end process drp; + + +-- drive_drdy_out : process +-- begin +-- if (falling_edge(drp_lock)) then +-- wait until (rising_edge(DCLK_dly)); +-- drdy_out <= '1'; +-- wait until (rising_edge(DCLK_dly)); +-- drdy_out <= '0'; +-- end if; +-- wait on drp_lock; +-- end process drive_drdy_out; + +-- +--generate all output signal +-- + + schedule_clk0 : process(clk0_out, rst_ipd) + begin + if (rst_ipd = '1') then + CLK180 <= '0'; + CLK270 <= '0'; + clk0_sig <= '0'; + CLK90 <= '0'; + CLK0 <= '0'; + elsif (CLK0_out'event) then + CLK0 <= transport CLK0_out after clkout_delay; + clk0_sig <= transport CLK0_out after clkout_delay; + CLK90 <= transport clk0_out after (clkout_delay + period / 4); + CLK180 <= transport clk0_out after (clkout_delay + period/2); + CLK270 <= transport (not clk0_out) after (clkout_delay + period/4); + end if; + end process schedule_clk0; + + schedule_clk2x : process (CLK2X_out, rst_ipd) + begin + if (rst_ipd = '1') then + CLK2X180 <= '0'; + CLK2X <= '0'; + clk2x_sig <= '0'; + elsif (clk2x_out'event) then + CLK2X <= transport clk2x_out after clkout_delay; + clk2x_sig <= transport clk2x_out after clkout_delay; + CLK2X180 <= transport (not CLK2X_out) after clkout_delay; + end if; + end process schedule_clk2x; + + CLKDV <= transport clkdv_out after clkout_delay; + + schedule_clkfx : process + begin + if (rst_ipd = '1') then + CLKFX <= '0'; + elsif (clkfx_out'event) then + CLKFX <= transport clkfx_out after clkout_delay; + end if; + + if ((rst_ipd = '1') or (not first_time_locked)) then + CLKFX180 <= '0'; + elsif (clkfx_out'event or (first_time_locked'event and first_time_locked = true) + or locked_out'event) then + CLKFX180 <= transport (not clkfx_out) after clkout_delay; + end if; + wait on clkfx_out, rst_ipd, first_time_locked, locked_out; + end process schedule_clkfx; + + + DO <= do_out; + locked_out_out <= 'X' when rst_flag = '1' else locked_out; + + DRDY <= drdy_out; + LOCKED <= locked_out_out; + PSDONE <= psdone_out; + + + +end DCM_ADV_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/dcm_base.vhd,v 1.12 2007/06/01 23:03:01 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Digital Clock Manager with Basic Features +-- /___/ /\ Filename : DCM_BASE.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:03 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 08/08/05 - Add parameter DCM_AUTOCALIBRATION (CR 214040). +-- 05/10/07 - Remove Vital timing. +-- End Revision + +----- CELL DCM_BASE ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library unisim; +use unisim.VCOMPONENTS.all; +use unisim.VPKG.all; +library STD; +use STD.TEXTIO.all; + +entity DCM_BASE is +generic ( + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := FALSE; + CLKIN_PERIOD : real := 10.0; + CLKOUT_PHASE_SHIFT : string := "NONE"; + CLK_FEEDBACK : string := "1X"; + DCM_AUTOCALIBRATION : boolean := TRUE; + DCM_PERFORMANCE_MODE : string := "MAX_SPEED"; + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DUTY_CYCLE_CORRECTION : boolean := TRUE; + FACTORY_JF : bit_vector := X"F0F0"; + PHASE_SHIFT : integer := 0; + STARTUP_WAIT : boolean := false + ); + +port ( + CLK0 : out std_ulogic; + CLK180 : out std_ulogic; + CLK270 : out std_ulogic; + CLK2X : out std_ulogic; + CLK2X180 : out std_ulogic; + CLK90 : out std_ulogic; + CLKDV : out std_ulogic; + CLKFX : out std_ulogic; + CLKFX180 : out std_ulogic; + LOCKED : out std_ulogic; + + CLKFB : in std_ulogic; + CLKIN : in std_ulogic; + RST : in std_ulogic + ); +end DCM_BASE; + +-- Architecture body -- + +architecture DCM_BASE_V of DCM_BASE is + +signal OPEN_DRDY : std_ulogic; +signal OPEN_PSDONE : std_ulogic; +signal OPEN_DO : std_logic_vector(15 downto 0); + +signal GND_DADDR : std_logic_vector(6 downto 0) := "0000000"; +signal GND_DCLK : std_ulogic := '0'; +signal GND_DEN : std_ulogic := '0'; +signal GND_DI : std_logic_vector(15 downto 0) := "0000000000000000"; +signal GND_DWE : std_ulogic := '0'; +signal GND_PSCLK : std_ulogic := '0'; +signal GND_PSEN : std_ulogic := '0'; +signal GND_PSINCDEC : std_ulogic := '0'; +signal GND_RST : std_ulogic := '0'; + +begin + + INITPROC : process + variable Message : line; + begin + if ((CLKOUT_PHASE_SHIFT = "none") or (CLKOUT_PHASE_SHIFT = "NONE")) then + elsif ((CLKOUT_PHASE_SHIFT = "fixed") or (CLKOUT_PHASE_SHIFT = "FIXED")) then + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLKOUT_PHASE_SHIFT", + EntityName => "DCM_BASE", +-- InstanceName => InstancePath, + GenericValue => CLKOUT_PHASE_SHIFT, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are NONE or FIXED", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if ((CLK_FEEDBACK = "none") or (CLK_FEEDBACK = "NONE")) then + Write ( Message, string'(" Attribute CLK_FEEDBACK is set to value NONE.")); + Write ( Message, string'(" In this mode, the output ports CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90 and CLKDV can have any random phase relation w.r.t. input port CLKIN")); + Write ( Message, '.' & LF ); + assert false report Message.all severity note; + DEALLOCATE (Message); + elsif ((CLK_FEEDBACK = "1x") or (CLK_FEEDBACK = "1X")) then +-- elsif ((CLK_FEEDBACK = "2x") or (CLK_FEEDBACK = "2X")) then +-- clkfb_type <= 2; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLK_FEEDBACK", + EntityName => "DCM_BASE", +-- InstanceName => InstancePath, + GenericValue => CLK_FEEDBACK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are NONE or 1X", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + wait; + end process INITPROC; + +-- DCM_ADV Instatiation (port map, generic map) +DCM_ADV_inst : DCM_ADV + generic map ( + CLKDV_DIVIDE => CLKDV_DIVIDE, + CLKFX_DIVIDE => CLKFX_DIVIDE, + CLKFX_MULTIPLY => CLKFX_MULTIPLY, + CLKIN_DIVIDE_BY_2 => CLKIN_DIVIDE_BY_2, + CLKIN_PERIOD => CLKIN_PERIOD, + CLKOUT_PHASE_SHIFT => CLKOUT_PHASE_SHIFT, + CLK_FEEDBACK => CLK_FEEDBACK, + DCM_AUTOCALIBRATION => DCM_AUTOCALIBRATION, + DCM_PERFORMANCE_MODE => DCM_PERFORMANCE_MODE, + DESKEW_ADJUST => DESKEW_ADJUST, + DFS_FREQUENCY_MODE => DFS_FREQUENCY_MODE, + DLL_FREQUENCY_MODE => DLL_FREQUENCY_MODE, + DUTY_CYCLE_CORRECTION => DUTY_CYCLE_CORRECTION, + FACTORY_JF => FACTORY_JF, + PHASE_SHIFT => PHASE_SHIFT, + STARTUP_WAIT => STARTUP_WAIT +) + port map ( + CLK0 => CLK0, + CLK180 => CLK180, + CLK270 => CLK270, + CLK2X => CLK2X, + CLK2X180 => CLK2X180, + CLK90 => CLK90, + CLKDV => CLKDV, + CLKFX => CLKFX, + CLKFX180 => CLKFX180, + DO => OPEN_DO, + DRDY => OPEN_DRDY, + LOCKED => LOCKED, + PSDONE => OPEN_PSDONE, + + CLKFB => CLKFB, + CLKIN => CLKIN, + DADDR => GND_DADDR, + DCLK => GND_DCLK, + DEN => GND_DEN, + DI => GND_DI, + DWE => GND_DWE, + PSCLK => GND_PSCLK, + PSEN => GND_PSEN, + PSINCDEC => GND_PSINCDEC, + RST => RST + ); + +end DCM_BASE_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/dcm_ps.vhd,v 1.12 2007/06/01 23:03:01 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Digital Clock Manager with Basic and Phase Shift Features +-- /___/ /\ Filename : DCM_PS.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:03 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 08/08/05 - Add parameter DCM_AUTOCALIBRATION (CR 214040). +-- 05/10/07 - Remove Vital timing. +-- End Revision +----- CELL DCM_PS ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library unisim; +use unisim.VCOMPONENTS.all; +use unisim.VPKG.all; +library STD; +use STD.TEXTIO.all; + +entity DCM_PS is +generic ( + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := FALSE; + CLKIN_PERIOD : real := 10.0; + CLKOUT_PHASE_SHIFT : string := "NONE"; + CLK_FEEDBACK : string := "1X"; + DCM_AUTOCALIBRATION : boolean := TRUE; + DCM_PERFORMANCE_MODE : string := "MAX_SPEED"; + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DUTY_CYCLE_CORRECTION : boolean := TRUE; + FACTORY_JF : bit_vector := X"F0F0"; --non-simulatable + PHASE_SHIFT : integer := 0; + STARTUP_WAIT : boolean := FALSE + ); + +port ( + CLK0 : out std_ulogic; + CLK180 : out std_ulogic; + CLK270 : out std_ulogic; + CLK2X : out std_ulogic; + CLK2X180 : out std_ulogic; + CLK90 : out std_ulogic; + CLKDV : out std_ulogic; + CLKFX : out std_ulogic; + CLKFX180 : out std_ulogic; + DO : out std_logic_vector(15 downto 0); + LOCKED : out std_ulogic; + PSDONE : out std_ulogic; + + CLKFB : in std_ulogic; + CLKIN : in std_ulogic; + PSCLK : in std_ulogic; + PSEN : in std_ulogic; + PSINCDEC : in std_ulogic; + RST : in std_ulogic + ); +end DCM_PS; + +-- Architecture body -- + +architecture DCM_PS_V of DCM_PS is + +signal OPEN_DRDY : std_ulogic; + +begin + + INITPROC : process + variable Message : line; + begin + + + if ((CLK_FEEDBACK = "none") or (CLK_FEEDBACK = "NONE")) then + Write ( Message, string'(" Attribute CLK_FEEDBACK is set to value NONE.")); + Write ( Message, string'(" In this mode, the output ports CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90 and CLKDV can have any random phase relation w.r.t. input port CLKIN")); + Write ( Message, '.' & LF ); + assert false report Message.all severity note; + DEALLOCATE (Message); + elsif ((CLK_FEEDBACK = "1x") or (CLK_FEEDBACK = "1X")) then +-- elsif ((CLK_FEEDBACK = "2x") or (CLK_FEEDBACK = "2X")) then +-- clkfb_type <= 2; + else + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "CLK_FEEDBACK", + EntityName => "DCM_PS", +-- InstanceName => InstancePath, + GenericValue => CLK_FEEDBACK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are NONE or 1X", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + wait; + end process INITPROC; + +-- DCM_ADV Instatiation (port map, generic map) +DCM_ADV_inst : DCM_ADV + generic map ( + CLKDV_DIVIDE => CLKDV_DIVIDE, + CLKFX_DIVIDE => CLKFX_DIVIDE, + CLKFX_MULTIPLY => CLKFX_MULTIPLY, + CLKIN_DIVIDE_BY_2 => CLKIN_DIVIDE_BY_2, + CLKIN_PERIOD => CLKIN_PERIOD, + CLKOUT_PHASE_SHIFT => CLKOUT_PHASE_SHIFT, + CLK_FEEDBACK => CLK_FEEDBACK, + DCM_AUTOCALIBRATION => DCM_AUTOCALIBRATION, + DCM_PERFORMANCE_MODE => DCM_PERFORMANCE_MODE, + DESKEW_ADJUST => DESKEW_ADJUST, + DFS_FREQUENCY_MODE => DFS_FREQUENCY_MODE, + DLL_FREQUENCY_MODE => DLL_FREQUENCY_MODE, + DUTY_CYCLE_CORRECTION => DUTY_CYCLE_CORRECTION, + FACTORY_JF => FACTORY_JF, + PHASE_SHIFT => PHASE_SHIFT, + STARTUP_WAIT => STARTUP_WAIT +) +port map ( + DRDY => OPEN_DRDY, + CLKIN => CLKIN, + CLKFB => CLKFB, + RST => RST, + PSINCDEC => PSINCDEC, + PSEN => PSEN, + PSCLK => PSCLK, + + CLK0 => CLK0, + CLK90 => CLK90, + CLK180 => CLK180, + CLK270 => CLK270, + CLK2X => CLK2X, + CLK2X180 => CLK2X180, + CLKDV => CLKDV, + CLKFX => CLKFX, + CLKFX180 => CLKFX180, + LOCKED => LOCKED, + PSDONE => PSDONE, + DO => DO +); + +end DCM_PS_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / 18X18 Signed Multiplier Followed by Three-Input Adder with Pipeline Registers +-- /___/ /\ Filename : DSP48.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:18:19 PST 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 05/25/05 - CR 204870 changed all bit_vector message calls to strings. +-- 06/30/05 - CR 210790 fixed CheckEnabled in Vital so that timing. +-- violation are not reported when global GSR_dly = 1. +-- 01/17/06 - CR 224235 CECARRYIN, CECINSUB fasle hold violation fix. +-- 02/28/06 - CR 225886 -- LEGACY_MODE check updates. +-- 06/30/06 - CR 234078 -- Fixed False Timing error on RSTCARRYIN +-- 08/21/06 - CR 232521 -- fixed DRC check to allow "0010101_11" +-- 02/06/08 - CR 455601 -- DRC relax for OPMODEREG/CARRYINSELREG +-- End Revision +----- CELL DSP48 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_SIGNED.all; +use IEEE.STD_LOGIC_ARITH.all; + +library STD; +use STD.TEXTIO.all; + + +library unisim; +use unisim.vpkg.all; + +entity DSP48 is + + generic( + + AREG : integer := 1; + B_INPUT : string := "DIRECT"; + BREG : integer := 1; + CARRYINREG : integer := 1; + CARRYINSELREG : integer := 1; + CREG : integer := 1; + LEGACY_MODE : string := "MULT18X18S"; + MREG : integer := 1; + OPMODEREG : integer := 1; + PREG : integer := 1; + SUBTRACTREG : integer := 1 + ); + + port( + BCOUT : out std_logic_vector(17 downto 0); + P : out std_logic_vector(47 downto 0); + PCOUT : out std_logic_vector(47 downto 0); + + A : in std_logic_vector(17 downto 0); + B : in std_logic_vector(17 downto 0); + BCIN : in std_logic_vector(17 downto 0); + C : in std_logic_vector(47 downto 0); + CARRYIN : in std_ulogic; + CARRYINSEL : in std_logic_vector(1 downto 0); + CEA : in std_ulogic; + CEB : in std_ulogic; + CEC : in std_ulogic; + CECARRYIN : in std_ulogic; + CECINSUB : in std_ulogic; + CECTRL : in std_ulogic; + CEM : in std_ulogic; + CEP : in std_ulogic; + CLK : in std_ulogic; + OPMODE : in std_logic_vector(6 downto 0); + PCIN : in std_logic_vector(47 downto 0); + RSTA : in std_ulogic; + RSTB : in std_ulogic; + RSTC : in std_ulogic; + RSTCARRYIN : in std_ulogic; + RSTCTRL : in std_ulogic; + RSTM : in std_ulogic; + RSTP : in std_ulogic; + SUBTRACT : in std_ulogic + ); + +end DSP48; + +-- architecture body -- + +architecture DSP48_V of DSP48 is + + procedure invalid_opmode_preg_msg( OPMODE : IN string ; + CARRYINSEL : IN string ) is + variable Message : line; + begin + Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); + Write ( Message, OPMODE); + Write ( Message, string'(" with CARRYINSEL ")); + Write ( Message, CARRYINSEL); + Write ( Message, string'(" to DSP48 instance ")); + Write ( Message, string'("requires attribute PREG set to 1.")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end invalid_opmode_preg_msg; + + procedure invalid_opmode_mreg_msg( OPMODE : IN string ; + CARRYINSEL : IN string ) is + variable Message : line; + begin + Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); + Write ( Message, OPMODE); + Write ( Message, string'(" with CARRYINSEL ")); + Write ( Message, CARRYINSEL); + Write ( Message, string'(" to DSP48 instance ")); + Write ( Message, string'("requires attribute MREG set to 1.")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end invalid_opmode_mreg_msg; + + procedure invalid_opmode_no_mreg_msg( OPMODE : IN string ; + CARRYINSEL : IN string ) is + variable Message : line; + begin + Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); + Write ( Message, OPMODE); + Write ( Message, string'(" with CARRYINSEL ")); + Write ( Message, CARRYINSEL); + Write ( Message, string'(" to DSP48 instance ")); + Write ( Message, string'("requires attribute MREG set to 0.")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end invalid_opmode_no_mreg_msg; + + + + + constant SYNC_PATH_DELAY : time := 100 ps; + + constant MAX_P : integer := 48; + constant MAX_PCIN : integer := 48; + constant MAX_OPMODE : integer := 7; + constant MAX_BCIN : integer := 18; + constant MAX_B : integer := 18; + constant MAX_A : integer := 18; + constant MAX_C : integer := 48; + + constant MSB_PCIN : integer := 47; + constant MSB_OPMODE : integer := 6; + constant MSB_BCIN : integer := 17; + constant MSB_B : integer := 17; + constant MSB_A : integer := 17; + constant MSB_C : integer := 47; + constant MSB_CARRYINSEL : integer := 1; + + constant MSB_P : integer := 47; + constant MSB_PCOUT : integer := 47; + constant MSB_BCOUT : integer := 17; + + constant SHIFT_MUXZ : integer := 17; + + signal A_ipd : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal B_ipd : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal BCIN_ipd : std_logic_vector(MSB_BCIN downto 0) := (others => '0'); + signal C_ipd : std_logic_vector(MSB_C downto 0) := (others => '0'); + signal CARRYIN_ipd : std_ulogic := '0'; + signal CARRYINSEL_ipd : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0'); + signal CEA_ipd : std_ulogic := '0'; + signal CEB_ipd : std_ulogic := '0'; + signal CEC_ipd : std_ulogic := '0'; + signal CECARRYIN_ipd : std_ulogic := '0'; + signal CECINSUB_ipd : std_ulogic := '0'; + signal CECTRL_ipd : std_ulogic := '0'; + signal CEM_ipd : std_ulogic := '0'; + signal CEP_ipd : std_ulogic := '0'; + signal CLK_ipd : std_ulogic := '0'; + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := '0'; + signal OPMODE_ipd : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); + signal PCIN_ipd : std_logic_vector(MSB_PCIN downto 0) := (others => '0'); + signal RSTA_ipd : std_ulogic := '0'; + signal RSTB_ipd : std_ulogic := '0'; + signal RSTC_ipd : std_ulogic := '0'; + signal RSTCARRYIN_ipd : std_ulogic := '0'; + signal RSTCTRL_ipd : std_ulogic := '0'; + signal RSTM_ipd : std_ulogic := '0'; + signal RSTP_ipd : std_ulogic := '0'; + signal SUBTRACT_ipd : std_ulogic := '0'; + + signal A_dly : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal B_dly : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal BCIN_dly : std_logic_vector(MSB_BCIN downto 0) := (others => '0'); + signal C_dly : std_logic_vector(MSB_C downto 0) := (others => '0'); + signal CARRYIN_dly : std_ulogic := '0'; + signal CARRYINSEL_dly : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0'); + signal CEA_dly : std_ulogic := '0'; + signal CEB_dly : std_ulogic := '0'; + signal CEC_dly : std_ulogic := '0'; + signal CECARRYIN_dly : std_ulogic := '0'; + signal CECINSUB_dly : std_ulogic := '0'; + signal CECTRL_dly : std_ulogic := '0'; + signal CEM_dly : std_ulogic := '0'; + signal CEP_dly : std_ulogic := '0'; + signal CLK_dly : std_ulogic := '0'; + signal GSR_dly : std_ulogic := '0'; + signal OPMODE_dly : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); + signal PCIN_dly : std_logic_vector(MSB_PCIN downto 0) := (others => '0'); + signal RSTA_dly : std_ulogic := '0'; + signal RSTB_dly : std_ulogic := '0'; + signal RSTC_dly : std_ulogic := '0'; + signal RSTCARRYIN_dly : std_ulogic := '0'; + signal RSTCTRL_dly : std_ulogic := '0'; + signal RSTM_dly : std_ulogic := '0'; + signal RSTP_dly : std_ulogic := '0'; + signal SUBTRACT_dly : std_ulogic := '0'; + + signal BCOUT_zd : std_logic_vector(MSB_BCOUT downto 0) := (others => '0'); + signal P_zd : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal PCOUT_zd : std_logic_vector(MSB_PCOUT downto 0) := (others => '0'); + + --- Internal Signal Declarations + signal qa_o_reg1 : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal qa_o_reg2 : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal qa_o_mux : std_logic_vector(MSB_A downto 0) := (others => '0'); + + signal b_o_mux : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal qb_o_reg1 : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal qb_o_reg2 : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal qb_o_mux : std_logic_vector(MSB_B downto 0) := (others => '0'); + + signal qc_o_reg : std_logic_vector(MSB_C downto 0) := (others => '0'); + signal qc_o_mux : std_logic_vector(MSB_C downto 0) := (others => '0'); + + signal mult_o_int : std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0'); + signal mult_o_reg : std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0'); + signal mult_o_mux : std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0'); + + signal opmode_o_reg : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); + signal opmode_o_mux : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); + + signal muxx_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal muxy_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal muxz_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); + + signal subtract_o_reg : std_ulogic := '0'; + signal subtract_o_mux : std_ulogic := '0'; + + signal carryinsel_o_reg : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0'); + signal carryinsel_o_mux : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0'); + + signal qcarryin_o_reg1 : std_ulogic := '0'; + signal carryin0_o_mux : std_ulogic := '0'; + signal carryin1_o_mux : std_ulogic := '0'; + signal carryin2_o_mux : std_ulogic := '0'; + + signal qcarryin_o_reg2 : std_ulogic := '0'; + + signal carryin_o_mux : std_ulogic := '0'; + + signal accum_o : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal qp_o_reg : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal qp_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); + + signal add_i_int : std_logic_vector(47 downto 0) := (others => '0'); + signal add_o_int : std_logic_vector(47 downto 0) := (others => '0'); + + signal reg_p_int : std_logic_vector(47 downto 0) := (others => '0'); + signal p_o_int : std_logic_vector(47 downto 0) := (others => '0'); + + signal subtract1_o_int : std_ulogic := '0'; + signal carryinsel1_o_int : std_logic_vector(1 downto 0) := (others => '0'); + signal carry1_o_int : std_ulogic := '0'; + signal carry2_o_int : std_ulogic := '0'; + + + signal output_x_sig : std_ulogic := '0'; + + signal RST_META : std_ulogic := '0'; + + signal DefDelay : time := 10 ps; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + + A_dly <= A after 0 ps; + B_dly <= B after 0 ps; + BCIN_dly <= BCIN after 0 ps; + C_dly <= C after 0 ps; + CARRYIN_dly <= CARRYIN after 0 ps; + CARRYINSEL_dly <= CARRYINSEL after 0 ps; + CEA_dly <= CEA after 0 ps; + CEB_dly <= CEB after 0 ps; + CEC_dly <= CEC after 0 ps; + CECARRYIN_dly <= CECARRYIN after 0 ps; + CECINSUB_dly <= CECINSUB after 0 ps; + CECTRL_dly <= CECTRL after 0 ps; + CEM_dly <= CEM after 0 ps; + CEP_dly <= CEP after 0 ps; + CLK_dly <= CLK after 0 ps; + GSR_dly <= GSR after 0 ps; + OPMODE_dly <= OPMODE after 0 ps; + PCIN_dly <= PCIN after 0 ps; + RSTA_dly <= RSTA after 0 ps; + RSTB_dly <= RSTB after 0 ps; + RSTC_dly <= RSTC after 0 ps; + RSTCARRYIN_dly <= RSTCARRYIN after 0 ps; + RSTCTRL_dly <= RSTCTRL after 0 ps; + RSTM_dly <= RSTM after 0 ps; + RSTP_dly <= RSTP after 0 ps; + SUBTRACT_dly <= SUBTRACT after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialization ### +--#################################################################### + prcs_init:process + begin + if((LEGACY_MODE /="NONE") and (LEGACY_MODE /="MULT18X18") and + (LEGACY_MODE /="MULT18X18S")) then + assert false + report "Attribute Syntax Error: The allowed values for LEGACY_MODE are NONE, MULT18X18 or MULT18X18S." + severity Failure; + elsif((LEGACY_MODE ="MULT18X18") and (MREG /= 0)) then + assert false + report "Attribute Syntax Error: The attribute LEGACY_MODE on DSP48 is set to MULT18X18. This requires attribute MREG to be set to 0." + severity Failure; + elsif((LEGACY_MODE ="MULT18X18S") and (MREG /= 1)) then + assert false + report "Attribute Syntax Error: The attribute LEGACY_MODE on DSP48 is set to MULT18X18S. This requires attribute MREG to be set to 1." + severity Failure; + end if; + + wait; + end process prcs_init; +--#################################################################### +--##### Input Register A with two levels of registers and a mux ### +--#################################################################### + prcs_qa_2lvl:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qa_o_reg1 <= ( others => '0'); + qa_o_reg2 <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then +--FP if((RSTA_dly = '1') and (CEA_dly = '1')) then + if(RSTA_dly = '1') then + qa_o_reg1 <= ( others => '0'); + qa_o_reg2 <= ( others => '0'); + elsif ((RSTA_dly = '0') and (CEA_dly = '1')) then + qa_o_reg2 <= qa_o_reg1; + qa_o_reg1 <= A_dly; + end if; + end if; + end if; + end process prcs_qa_2lvl; +------------------------------------------------------------------ + prcs_qa_o_mux:process(A_dly, qa_o_reg1, qa_o_reg2) + begin + case AREG is + when 0 => qa_o_mux <= A_dly; + when 1 => qa_o_mux <= qa_o_reg1; + when 2 => qa_o_mux <= qa_o_reg2; + when others => + assert false + report "Attribute Syntax Error: The allowed values for AREG are 0 or 1 or 2" + severity Failure; + end case; + end process prcs_qa_o_mux; + +--#################################################################### +--##### Input Register B with two levels of registers and a mux ### +--#################################################################### + prcs_b_in:process(B_dly, BCIN_dly) + begin + if(B_INPUT ="DIRECT") then + b_o_mux <= B_dly; + elsif(B_INPUT ="CASCADE") then + b_o_mux <= BCIN_dly; + else + assert false + report "Attribute Syntax Error: The allowed values for B_INPUT are DIRECT or CASCADE." + severity Failure; + end if; + + end process prcs_b_in; +------------------------------------------------------------------ + prcs_qb_2lvl:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qb_o_reg1 <= ( others => '0'); + qb_o_reg2 <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then +-- FP if((RSTB_dly = '1') and (CEB_dly = '1')) then + if(RSTB_dly = '1') then + qb_o_reg1 <= ( others => '0'); + qb_o_reg2 <= ( others => '0'); + elsif ((RSTB_dly = '0') and (CEB_dly = '1')) then + qb_o_reg2 <= qb_o_reg1; + qb_o_reg1 <= b_o_mux; + end if; + end if; + end if; + end process prcs_qb_2lvl; +------------------------------------------------------------------ + prcs_qb_o_mux:process(b_o_mux, qb_o_reg1, qb_o_reg2) + begin + case BREG is + when 0 => qb_o_mux <= b_o_mux; + when 1 => qb_o_mux <= qb_o_reg1; + when 2 => qb_o_mux <= qb_o_reg2; + when others => + assert false + report "Attribute Syntax Error: The allowed values for BREG are 0 or 1 or 2 " + severity Failure; + end case; + + end process prcs_qb_o_mux; + +--#################################################################### +--##### Input Register C with 0, 1, level of registers ##### +--#################################################################### + prcs_qc_1lvl:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qc_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then +-- FP if((RSTC_dly = '1') and (CEC_dly = '1'))then + if(RSTC_dly = '1') then + qc_o_reg <= ( others => '0'); + elsif ((RSTC_dly = '0') and (CEC_dly = '1')) then + qc_o_reg <= C_dly; + end if; + end if; + end if; + end process prcs_qc_1lvl; +------------------------------------------------------------------ + prcs_qc_o_mux:process(C_dly, qc_o_reg) + begin + case CREG is + when 0 => qc_o_mux <= C_dly; + when 1 => qc_o_mux <= qc_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for CREG are 0 or 1" + severity Failure; + end case; + end process prcs_qc_o_mux; + +--#################################################################### +--##### Mulitplier ##### +--#################################################################### + prcs_mult:process(qa_o_mux, qb_o_mux) + begin + mult_o_int <= qa_o_mux * qb_o_mux; + end process prcs_mult; +------------------------------------------------------------------ + prcs_mult_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + mult_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then +--FP if((RSTM_dly = '1') and (CEM_dly = '1'))then + if(RSTM_dly = '1') then + mult_o_reg <= ( others => '0'); + elsif ((RSTM_dly = '0') and (CEM_dly = '1')) then + mult_o_reg <= mult_o_int; + end if; + end if; + end if; + end process prcs_mult_reg; +------------------------------------------------------------------ + prcs_mult_mux:process(mult_o_reg, mult_o_int) + begin + case MREG is + when 0 => mult_o_mux <= mult_o_int; + when 1 => mult_o_mux <= mult_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for MREG are 0 or 1" + severity Failure; + end case; + end process prcs_mult_mux; + +--#################################################################### +--##### OpMode ##### +--#################################################################### + prcs_opmode_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + opmode_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then +--FP if((RSTCTRL_dly = '1') and (CECTRL_dly = '1'))then + if(RSTCTRL_dly = '1') then + opmode_o_reg <= ( others => '0'); + elsif ((RSTCTRL_dly = '0') and (CECTRL_dly = '1')) then + opmode_o_reg <= OPMODE_dly; + end if; + end if; + end if; + end process prcs_opmode_reg; +------------------------------------------------------------------ + prcs_opmode_mux:process(opmode_o_reg, OPMODE_dly) + begin + case OPMODEREG is + when 0 => opmode_o_mux <= OPMODE_dly; + when 1 => opmode_o_mux <= opmode_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for OPMODEREG are 0 or 1" + severity Failure; + end case; + end process prcs_opmode_mux; +--#################################################################### +--##### MUX_XYZ ##### +--#################################################################### +-- prcs_mux_xyz:process(opmode_o_mux,,,, FP) + -- FP ?? more (Z) should be added to sensitivity list + prcs_mux_xyz:process(opmode_o_mux, qp_o_mux, qa_o_mux, qb_o_mux, mult_o_mux, + qc_o_mux, PCIN_dly, output_x_sig) + begin + if(output_x_sig = '1') then + muxx_o_mux(MSB_P downto 0) <= ( others => 'X'); + muxy_o_mux(MSB_P downto 0) <= ( others => 'X'); + muxz_o_mux(MSB_P downto 0) <= ( others => 'X'); + elsif(output_x_sig = '0') then + --MUX_X ----- + case opmode_o_mux(1 downto 0) is + when "00" => muxx_o_mux <= ( others => '0'); + -- FP ?? better way to concat ? and sign extend ? + when "01" => muxx_o_mux((MAX_A + MAX_B - 1) downto 0) <= mult_o_mux; + if(mult_o_mux(MAX_A + MAX_B - 1) = '1') then + muxx_o_mux(MSB_PCIN downto (MAX_A + MAX_B)) <= ( others => '1'); + elsif (mult_o_mux(MSB_A + MSB_B + 1) = '0') then + muxx_o_mux(MSB_PCIN downto (MAX_A + MAX_B)) <= ( others => '0'); + end if; + + when "10" => muxx_o_mux <= qp_o_mux; + when "11" => if(qa_o_mux(MSB_A) = '0') then + muxx_o_mux(MSB_P downto 0) <= ("000000000000" & qa_o_mux & qb_o_mux); + elsif(qa_o_mux(MSB_A) = '1') then + muxx_o_mux(MSB_P downto 0) <= ("111111111111" & qa_o_mux & qb_o_mux); + end if; +-- when "11" => muxx_o_mux(MSB_B downto 0) <= qb_o_mux; +-- muxx_o_mux((MAX_A + MAX_B - 1) downto MAX_B) <= qa_o_mux; +-- +-- if(mult_o_mux(MAX_A + MAX_B - 1) = '1') then +-- muxx_o_mux(MSB_PCIN downto (MAX_A + MAX_B)) <= ( others => '1'); +-- elsif (mult_o_mux(MSB_A + MSB_B + 1) = '0') then +-- muxx_o_mux(MSB_PCIN downto (MAX_A + MAX_B)) <= ( others => '0'); +-- end if; + when others => null; +-- assert false +-- report "Error: input signal OPMODE(1 downto 0) has unknown values" +-- severity Failure; + end case; + + --MUX_Y ----- + case opmode_o_mux(3 downto 2) is + when "00" => muxy_o_mux <= ( others => '0'); + when "01" => muxy_o_mux <= ( others => '0'); + when "10" => null; + when "11" => muxy_o_mux <= qc_o_mux; + when others => null; +-- assert false +-- report "Error: input signal OPMODE(3 downto 2) has unknown values" +-- severity Failure; + end case; + --MUX_Z ----- + case opmode_o_mux(6 downto 4) is + when "000" => muxz_o_mux <= ( others => '0'); + when "001" => muxz_o_mux <= PCIN_dly; + when "010" => muxz_o_mux <= qp_o_mux; + when "011" => muxz_o_mux <= qc_o_mux; + when "100" => null; + -- FP ?? better shift possible ? + when "101" => if(PCIN_dly(MSB_PCIN) = '0') then + muxz_o_mux <= ( others => '0'); + elsif(PCIN_dly(MSB_PCIN) = '1') then + muxz_o_mux <= ( others => '1'); + end if; + muxz_o_mux ((MSB_PCIN - SHIFT_MUXZ) downto 0) <= PCIN_dly(MSB_PCIN downto SHIFT_MUXZ ); + when "110" => if(qp_o_mux(MSB_P) = '0') then + muxz_o_mux <= ( others => '0'); + elsif(qp_o_mux(MSB_P) = '1') then + muxz_o_mux <= ( others => '1'); + end if; +-- muxz_o_mux ((MAX_P - SHIFT_MUXZ) downto 0) <= qp_o_mux(MSB_P downto (SHIFT_MUXZ - 1)); + muxz_o_mux ((MSB_P - SHIFT_MUXZ) downto 0) <= qp_o_mux(MSB_P downto SHIFT_MUXZ ); + + when "111" => null; + when others => null; +-- assert false +-- report "Error: input signal OPMODE(6 downto 4) has unknown values" +-- severity Failure; + end case; + end if; + end process prcs_mux_xyz; +--#################################################################### +--##### Subtract ##### +--#################################################################### + prcs_subtract_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + subtract_o_reg <= '0'; + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTCTRL_dly = '1') then + subtract_o_reg <= '0'; + elsif ((RSTCTRL_dly = '0') and (CECINSUB_dly = '1'))then + subtract_o_reg <= SUBTRACT_dly; + end if; + end if; + end if; + end process prcs_subtract_reg; +------------------------------------------------------------------ + prcs_subtract_mux:process(subtract_o_reg, SUBTRACT_dly) + begin + case SUBTRACTREG is + when 0 => subtract_o_mux <= SUBTRACT_dly; + when 1 => subtract_o_mux <= subtract_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for SUBTRACTREG are 0 or 1" + severity Failure; + end case; + end process prcs_subtract_mux; + +--#################################################################### +--##### CarryInSel ##### +--#################################################################### + prcs_carryinsel_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + carryinsel_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then +--FP if((RSTCTRL_dly = '1') and (CECTRL_dly = '1'))then + if(RSTCTRL_dly = '1') then + carryinsel_o_reg <= ( others => '0'); + elsif ((RSTCTRL_dly = '0') and (CECTRL_dly = '1')) then + carryinsel_o_reg <= CARRYINSEL_dly; + end if; + end if; + end if; + end process prcs_carryinsel_reg; +------------------------------------------------------------------ + prcs_carryinsel_mux:process(carryinsel_o_reg, CARRYINSEL_dly) + begin + case CARRYINSELREG is + when 0 => carryinsel_o_mux <= CARRYINSEL_dly; + when 1 => carryinsel_o_mux <= carryinsel_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for CARRYINSELREG are 0 or 1" + severity Failure; + end case; + end process prcs_carryinsel_mux; + +--#################################################################### +--##### CarryIn ##### +--#################################################################### + prcs_carryin_reg1:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qcarryin_o_reg1 <= '0'; + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTCARRYIN_dly = '1') then + qcarryin_o_reg1 <= '0'; + elsif((RSTCARRYIN_dly = '0') and (CECINSUB_dly = '1')) then + qcarryin_o_reg1 <= CARRYIN_dly; + end if; + end if; + end if; + end process prcs_carryin_reg1; +------------------------------------------------------------------ + prcs_carryin0_mux:process(qcarryin_o_reg1, CARRYIN_dly) + begin + case CARRYINREG is + when 0 => carryin0_o_mux <= CARRYIN_dly; + when 1 => carryin0_o_mux <= qcarryin_o_reg1; + when others => + assert false + report "Attribute Syntax Error: The allowed values for CARRYINREG are 0 or 1" + severity Failure; + end case; + end process prcs_carryin0_mux; +------------------------------------------------------------------ + prcs_carryin1_mux:process(opmode_o_mux(0), opmode_o_mux(1), qa_o_mux(17), qb_o_mux(17)) + begin + case (opmode_o_mux(0) and opmode_o_mux(1)) is + when '0' => carryin1_o_mux <= NOT(qa_o_mux(17) xor qb_o_mux(17)); + when '1' => carryin1_o_mux <= NOT qa_o_mux(17); + when others => null; +-- assert false +-- report "Error: UNKOWN Value at PORT OPMODE(1) " +-- severity Failure; + end case; + end process prcs_carryin1_mux; +------------------------------------------------------------------ + prcs_carryin2_mux:process(opmode_o_mux(0), opmode_o_mux(1), qp_o_mux(47), PCIN_dly(47)) + begin + if(((opmode_o_mux(1) = '1') and (opmode_o_mux(0) = '0')) or + (opmode_o_mux(5) = '1') or + (NOT ((opmode_o_mux(6) = '1') or (opmode_o_mux(4) = '1')))) then + carryin2_o_mux <= NOT qp_o_mux(47); + else + carryin2_o_mux <= NOT PCIN_dly(47); + end if; + end process prcs_carryin2_mux; +------------------------------------------------------------------ + prcs_carryin_reg2:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qcarryin_o_reg2 <= '0'; + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTCARRYIN_dly = '1') then + qcarryin_o_reg2 <= '0'; + elsif ((RSTCARRYIN_dly = '0') and (CECARRYIN_dly = '1'))then + qcarryin_o_reg2 <= carryin1_o_mux; + end if; + end if; + end if; + end process prcs_carryin_reg2; +------------------------------------------------------------------ + prcs_carryin_mux:process(carryinsel_o_mux, carryin0_o_mux, carryin1_o_mux, carryin2_o_mux, qcarryin_o_reg2) + begin + case carryinsel_o_mux is + when "00" => carryin_o_mux <= carryin0_o_mux; + when "01" => carryin_o_mux <= carryin2_o_mux; + when "10" => carryin_o_mux <= carryin1_o_mux; + when "11" => carryin_o_mux <= qcarryin_o_reg2; + when others => null; +-- assert false +-- report "Error: UNKOWN Value at carryinsel_o_mux" +-- severity Failure; + end case; + end process prcs_carryin_mux; +--#################################################################### +--##### ACCUM ##### +--#################################################################### +-- +-- NOTE : moved it to the drc process +-- +-- prcs_accum_xyz:process(muxx_o_mux, muxy_o_mux, muxz_o_mux, subtract_o_mux, carryin_o_mux ) +-- variable carry_var : integer; +-- begin +-- if(carryin_o_mux = '1') then +-- carry_var := 1; +-- elsif (carryin_o_mux = '0') then +-- carry_var := 0; +---- else +---- assert false +---- report "Error : CarryIn has Unknown value." +---- severity Failure; +-- end if; + +-- if(subtract_o_mux = '0') then +-- accum_o <= muxz_o_mux + (muxx_o_mux + muxy_o_mux + carryin_o_mux); +-- elsif(subtract_o_mux = '1') then +-- accum_o <= muxz_o_mux - (muxx_o_mux + muxy_o_mux + carryin_o_mux); +---- else +---- assert false +---- report "Error : Subtract has Unknown value." +---- severity Failure; +-- end if; +-- end process prcs_accum_xyz; +--#################################################################### +--##### PCOUT ##### +--#################################################################### + prcs_qp_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qp_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTP_dly = '1') then + qp_o_reg <= ( others => '0'); + elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then + qp_o_reg <= accum_o; + end if; + end if; + end if; + end process prcs_qp_reg; +------------------------------------------------------------------ + prcs_qp_mux:process(accum_o, qp_o_reg) + begin + case PREG is + when 0 => qp_o_mux <= accum_o; + when 1 => qp_o_mux <= qp_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for PREG are 0 or 1" + severity Failure; + end case; + + end process prcs_qp_mux; +--#################################################################### +--##### ZERO_DELAY_OUTPUTS ##### +--#################################################################### + prcs_zero_delay_outputs:process(qb_o_mux, qp_o_mux) + begin + BCOUT_zd <= qb_o_mux; + P_zd <= qp_o_mux; + PCOUT_zd <= qp_o_mux; + end process prcs_zero_delay_outputs; + +--#################################################################### +--##### PMODE DRC ##### +--#################################################################### + prcs_opmode_drc:process(opmode_o_mux, carryinsel_o_mux, subtract_o_mux, + muxx_o_mux, muxy_o_mux, muxz_o_mux, carryin_o_mux) + variable Message : line; + variable invalid_opmode_flg : boolean := true; + variable add_flg : boolean := true; + variable opmode_carryinsel_var : std_logic_vector(8 downto 0) := (others => '0'); + begin +-- if now > 100 ns then +-- The above line was cusing the intial values of A, B or C not trigger + opmode_carryinsel_var := opmode_o_mux & carryinsel_o_mux; + case opmode_carryinsel_var is + + + when "000000000" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "000001000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; +-- CR 455601 eased the following drc + when "000001001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; +-- + + when "000001100" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "000010100" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "000110000" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "000111000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "000111001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "000111100" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "000111110" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "001000000" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "001001000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "001001001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "001001100" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "001001101" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "001001110" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "001010100" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "001010101" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "001010110" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "001010111" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "001110000" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "001110001" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "001111000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "001111001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "001111100" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "001111101" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "001111110" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "010000000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "010001000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "010001100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "010001101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "010010100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "010010101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "010110000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "010110001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "010111000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "010111001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "010111100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "010111101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "010111110" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "011000000" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "011001000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "011001001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "011001100" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "011001110" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "011010100" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "011010110" => + if (MREG /= 0) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_no_mreg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "011010111" => + if (MREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_mreg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "011110000" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "011111000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "011111100" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + + when "011111101" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "101000000" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "101001000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "101001100" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "101001101" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "101001110" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "101010100" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "101010101" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "101010110" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "101010111" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "101110000" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "101110001" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "101111000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "101111001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "101111100" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "101111101" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "101111110" => + invalid_opmode_flg := true ; + add_flg := true ; + output_x_sig <= '0'; + + when "110000000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "110001000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "110001100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "110001101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "110010100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "110010101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "110110000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "110110001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "110111000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "110111001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "110111100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "110111101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + + when "110111110" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + add_flg := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + add_flg := true; + output_x_sig <= '0'; + end if; + when others => + if(invalid_opmode_flg = true) then + invalid_opmode_flg := false; + add_flg := false; + output_x_sig <= '1'; + accum_o <= (others => 'X'); + Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); + Write ( Message, slv_to_str(opmode_o_mux)); + Write ( Message, string'(" with CARRYINSEL ")); + Write ( Message, slv_to_str(carryinsel_o_mux)); + Write ( Message, string'(" to DSP48 instance")); + Write ( Message, string'(" is invalid.")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end if; + end case; + + + if(add_flg) then + if(subtract_o_mux = '0') then + accum_o <= muxz_o_mux + (muxx_o_mux + muxy_o_mux + carryin_o_mux); + elsif(subtract_o_mux = '1') then + accum_o <= muxz_o_mux - (muxx_o_mux + muxy_o_mux + carryin_o_mux); + end if; + end if; +-- end if; + end process prcs_opmode_drc; + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(BCOUT_zd, PCOUT_zd, P_zd) + begin + BCOUT <= BCOUT_zd after SYNC_PATH_DELAY; + P <= P_zd after SYNC_PATH_DELAY; + PCOUT <= PCOUT_zd after SYNC_PATH_DELAY; + end process prcs_output; + + + +end DSP48_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / 16K-Bit FIFO +-- /___/ /\ Filename : FIFO16.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:18:20 PST 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 02/06/06 - Updated the reset requirement message. +-- 05/31/06 - Added feature for invalid reset condition. (CR 223364). +-- End Revision + +----- CELL FIFO16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_arith.all; + +library STD; +use STD.TEXTIO.ALL; + + +library unisim; +use unisim.vpkg.all; + +entity FIFO16 is + + generic( + + ALMOST_FULL_OFFSET : bit_vector := X"080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"080"; + DATA_WIDTH : integer := 36; + FIRST_WORD_FALL_THROUGH : boolean := false + ); + + port( + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DO : out std_logic_vector (31 downto 0); + DOP : out std_logic_vector (3 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (11 downto 0); + RDERR : out std_ulogic; + WRCOUNT : out std_logic_vector (11 downto 0); + WRERR : out std_ulogic; + + DI : in std_logic_vector (31 downto 0); + DIP : in std_logic_vector (3 downto 0); + RDCLK : in std_ulogic; + RDEN : in std_ulogic; + RST : in std_ulogic; + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); + +end FIFO16; + +-- architecture body -- + +architecture FIFO16_V of FIFO16 is + + + constant SYNC_PATH_DELAY: time := 100 ps; + + constant MAX_DO : integer := 32; + constant MAX_DOP : integer := 4; + constant MAX_RDCOUNT : integer := 12; + constant MAX_WRCOUNT : integer := 12; + constant MSB_MAX_DO : integer := 31; + constant MSB_MAX_DOP : integer := 3; + constant MSB_MAX_RDCOUNT : integer := 11; + constant MSB_MAX_WRCOUNT : integer := 11; + + constant MAX_DI : integer := 32; + constant MAX_DIP : integer := 4; + constant MSB_MAX_DI : integer := 31; + constant MSB_MAX_DIP : integer := 3; + + constant MAX_LATENCY_EMPTY : integer := 3; + constant MAX_LATENCY_FULL : integer := 3; + + signal MEM : std_logic_vector( 16383 downto 0 ) := (others => 'X'); + signal MEMP : std_logic_vector( 2047 downto 0 ) := (others => 'X'); + + signal DI_ipd : std_logic_vector(MSB_MAX_DI downto 0) := (others => 'X'); + signal DIP_ipd : std_logic_vector(MSB_MAX_DIP downto 0) := (others => 'X'); + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := 'X'; + signal RDCLK_ipd : std_ulogic := 'X'; + signal RDEN_ipd : std_ulogic := 'X'; + signal RST_ipd : std_ulogic := 'X'; + signal WRCLK_ipd : std_ulogic := 'X'; + signal WREN_ipd : std_ulogic := 'X'; + + signal DI_dly : std_logic_vector(MSB_MAX_DI downto 0) := (others => 'X'); + signal DIP_dly : std_logic_vector(MSB_MAX_DIP downto 0) := (others => 'X'); + signal GSR_dly : std_ulogic := 'X'; + signal RDCLK_dly : std_ulogic := 'X'; + signal RDEN_dly : std_ulogic := 'X'; + signal RST_dly : std_ulogic := 'X'; + signal WRCLK_dly : std_ulogic := 'X'; + signal WREN_dly : std_ulogic := 'X'; + + signal DO_zd : std_logic_vector(MSB_MAX_DO downto 0) := (others => '0'); + signal DOP_zd : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + signal ALMOSTEMPTY_zd : std_ulogic := '1'; + signal ALMOSTFULL_zd : std_ulogic := '0'; + signal EMPTY_zd : std_ulogic := '1'; + signal FULL_zd : std_ulogic := '0'; + signal RDCOUNT_zd : std_logic_vector(MSB_MAX_RDCOUNT downto 0) := (others => '0'); + signal RDERR_zd : std_ulogic := '0'; + signal WRCOUNT_zd : std_logic_vector(MSB_MAX_WRCOUNT downto 0) := (others => '0'); + signal WRERR_zd : std_ulogic := '0'; + signal RDCOUNT_OUT_zd : std_logic_vector(MSB_MAX_RDCOUNT downto 0) := (others => '1'); + signal WRCOUNT_OUT_zd : std_logic_vector(MSB_MAX_WRCOUNT downto 0) := (others => '1'); + signal DO_OUT_zd : std_logic_vector(MSB_MAX_DO downto 0) := (others => 'X'); + signal DOP_OUT_zd : std_logic_vector(MSB_MAX_DOP downto 0) := (others => 'X'); + + --- Internal Signal Declarations + + signal RST_META : std_ulogic := '0'; + + signal DefDelay : time := 10 ps; + + signal addr_limit : integer := 0; + signal wr_addr : integer := 0; + signal rd_addr : integer := 0; + signal rd_addr_range : integer := 0; + signal wr_addr_range : integer := 0; + + signal rd_flag : std_ulogic := '0'; + signal wr_flag : std_ulogic := '0'; + + signal rdcount_flag : std_ulogic := '0'; + + signal D_W : integer := 32; + signal P_W : integer := 4; + + signal almostempty_limit : real := 0.0; + signal almostfull_limit : real := 0.0; + + signal violation : std_ulogic := '0'; + + signal fwft : std_ulogic := 'X'; + + signal update_from_write_prcs : std_ulogic := '0'; + signal update_from_read_prcs : std_ulogic := '0'; + + signal ae_empty : integer := 0; + +-- CR 182616 fix + signal rst_rdckreg : std_logic_vector (2 downto 0) := (others => '0'); + signal rst_wrckreg : std_logic_vector (2 downto 0) := (others => '0'); + signal rst_rdclk_flag : std_ulogic := '0'; + signal rst_wrclk_flag : std_ulogic := '0'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + + DI_dly <= DI after 0 ps; + DIP_dly <= DIP after 0 ps; + GSR_dly <= GSR after 0 ps; + RDCLK_dly <= RDCLK after 0 ps; + RDEN_dly <= RDEN after 0 ps; + RST_dly <= RST after 0 ps; + WRCLK_dly <= WRCLK after 0 ps; + WREN_dly <= WREN after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_initialize:process + variable first_time : boolean := true; + variable addr_limit_var : integer := 0; + variable fwft_var : std_ulogic := 'X'; + variable rd_offset_stdlogic : std_logic_vector (ALMOST_EMPTY_OFFSET'length-1 downto 0); + variable rd_offset_int : integer := 0; + variable wr_offset_stdlogic : std_logic_vector (ALMOST_FULL_OFFSET'length-1 downto 0); + variable wr_offset_int : integer := 0; + variable Message : LINE; + variable ae_empty_var : integer := 0; + + begin + if (first_time) then + case DATA_WIDTH is + when 4 => + addr_limit_var := 4096; + D_W <= 4; + P_W <= 0; + when 9 => + addr_limit_var := 2048; + D_W <= 8; + P_W <= 1; + when 18 => + addr_limit_var := 1024; + D_W <= 16; + P_W <= 2; + when 36 => + addr_limit_var := 512; + D_W <= 32; + P_W <= 4; + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error ", + GenericName => " DATA_WIDTH ", + EntityName => "FIFO16", + GenericValue => DATA_WIDTH, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 4, 9, 18 and 36 ", + TailMsg => "", + MsgSeverity => error + ); + end case; + + rd_offset_stdlogic := To_StdLogicVector(ALMOST_EMPTY_OFFSET); + rd_offset_int := SLV_TO_INT(rd_offset_stdlogic); + + wr_offset_stdlogic := To_StdLogicVector(ALMOST_FULL_OFFSET); + wr_offset_int := SLV_TO_INT(wr_offset_stdlogic); + + case FIRST_WORD_FALL_THROUGH is + when true => + fwft_var := '1'; + ae_empty_var := rd_offset_int - 2; + when false => + fwft_var := '0'; + ae_empty_var := rd_offset_int - 1; + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error ", + GenericName => " FIRST_WORD_FALL_THROUGH ", + EntityName => "FIFO16", + GenericValue => FIRST_WORD_FALL_THROUGH, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " true or false ", + TailMsg => "", + MsgSeverity => error + ); + end case; + + if ((fwft_var = '0') and ((rd_offset_int < 5) or (rd_offset_int > addr_limit_var - 4))) then + write( Message, STRING'("Attribute Syntax Error : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("ALMOST_EMPTY_OFFSET on FIFO16 is set to ") ); + write( Message, rd_offset_int); + write( Message, STRING'(". Legal values for this attribute are ") ); + write( Message, 5); + write( Message, STRING'(" to ") ); + write( Message, addr_limit_var - 4 ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + + if ((fwft_var = '0') and ((wr_offset_int < 4) or (wr_offset_int > addr_limit_var - 5))) then + write( Message, STRING'("Attribute Syntax Error : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("ALMOST_FULL_OFFSET on FIFO16 is set to ") ); + write( Message, wr_offset_int); + write( Message, STRING'(". Legal values for this attribute are ") ); + write( Message, 4); + write( Message, STRING'(" to ") ); + write( Message, addr_limit_var - 5 ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + + if ((fwft_var = '1') and ((rd_offset_int < 6) or (rd_offset_int > addr_limit_var - 3))) then + write( Message, STRING'("Attribute Syntax Error : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("ALMOST_EMPTY_OFFSET on FIFO16 is set to ") ); + write( Message, rd_offset_int); + write( Message, STRING'(". Legal values for this attribute are ") ); + write( Message, 6); + write( Message, STRING'(" to ") ); + write( Message, addr_limit_var - 3 ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + + if ((fwft_var = '1') and ((wr_offset_int < 4) or (wr_offset_int > addr_limit_var - 5))) then + write( Message, STRING'("Attribute Syntax Error : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("ALMOST_FULL_OFFSET on FIFO16 is set to ") ); + write( Message, wr_offset_int); + write( Message, STRING'(". Legal values for this attribute are ") ); + write( Message, 4); + write( Message, STRING'(" to ") ); + write( Message, addr_limit_var - 5 ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + + + addr_limit <= addr_limit_var; + fwft <= fwft_var; + ae_empty <= ae_empty_var; + first_time := false; + end if; + wait; + end process prcs_initialize; + +--#################################################################### +--##### CR 182616 ##### +--#################################################################### + prcs_rst_rdin_wrin:process(RST_dly, RDEN_dly, WREN_dly) + begin + if(RST_dly = '1') then + if(RDEN_dly = '1') then + assert false + report "Warning : RDEN on FIFO16 is high when RST is high. RDEN should be low during reset." + severity Warning; + end if; + + if(WREN_dly = '1') then + assert false + report "Warning : WREN on FIFO16 is high when RST is high. WREN should be low during reset." + severity Warning; + end if; + end if; + end process prcs_rst_rdin_wrin; +------------------------------------------- + prcs_3clkrst_readwrite:process(RDCLK_dly, WRCLK_dly) + variable rst_rdckreg_var : std_logic_vector (2 downto 0) := (others => '0'); + variable rst_wrckreg_var : std_logic_vector (2 downto 0) := (others => '0'); + begin + if(rising_edge(RDCLK_dly)) then + rst_rdckreg_var(2) := RST_dly and rst_rdckreg_var(1); + rst_rdckreg_var(1) := RST_dly and rst_rdckreg_var(0); + rst_rdckreg_var(0) := RST_dly; + end if; + + if(rising_edge(WRCLK_dly)) then + rst_wrckreg_var(2) := RST_dly and rst_wrckreg_var(1); + rst_wrckreg_var(1) := RST_dly and rst_wrckreg_var(0); + rst_wrckreg_var(0) := RST_dly; + end if; + + rst_rdckreg <= rst_rdckreg_var; + rst_wrckreg <= rst_wrckreg_var; + end process prcs_3clkrst_readwrite; + + prcs_2clkrst:process(RST_dly) + begin + rst_rdclk_flag <= '0'; + rst_wrclk_flag <= '0'; + + if(falling_edge(RST_dly)) then + if((rst_rdckreg(2) ='0') or (rst_rdckreg(1) ='0') or (rst_rdckreg(0) ='0')) then + assert false + report "Error : RST signal on FIFO16 stays high for less than three RDCLK clock cycles. RST has to stay high for more than three RDCLK clock cycles" + severity Error; + rst_rdclk_flag <= '1'; + end if; + if((rst_wrckreg(2) ='0') or (rst_wrckreg(1) ='0') or (rst_wrckreg(0) ='0')) then + assert false + report "Error : RST signal on FIFO16 stays high for less than three WRCLK clock cycles. RST has to stay high for more than three WRCLK clock cycles" + severity Error; + rst_wrclk_flag <= '1'; + end if; + end if; + end process prcs_2clkrst; + +--#################################################################### +--##### Read ##### +--#################################################################### + prcs_read:process(RDCLK_dly, RST_dly, GSR_dly, update_from_write_prcs, rst_rdclk_flag, rst_wrclk_flag) + variable first_time : boolean := true; + variable rd_addr_var : integer := 0; + variable wr_addr_var : integer := 0; + variable rdcount_var : integer := 0; + + variable rd_flag_var : std_ulogic := '0'; + variable wr_flag_var : std_ulogic := '0'; + + variable rdcount_flag_var : std_ulogic := '0'; + + variable rd_offset_stdlogic : std_logic_vector (ALMOST_EMPTY_OFFSET'length-1 downto 0); + variable rd_offset_int : integer := 0; + + variable do_in : std_logic_vector(MSB_MAX_DO downto 0) := (others => 'X'); + variable dop_in : std_logic_vector(MSB_MAX_DOP downto 0) := (others => 'X'); + + variable almostempty_int : std_ulogic_vector(3 downto 0) := (others => '1'); + variable empty_int : std_ulogic_vector(3 downto 0) := (others => '1'); + variable empty_ram : std_ulogic_vector(3 downto 0) := (others => '1'); + + variable addr_limit_var : integer := 0; + + variable wr1_addr_var : integer := 0; + variable wr1_flag_var : std_ulogic := '0'; + variable rd_prefetch_var : integer := 0; + variable rd_prefetch_flag_var : std_ulogic := '0'; + +-- CR 195129 fix from verilog (may not be necessary for vhdl) +-- Added ren_var/wren_var to remember the old val of RDEN_dly/WREN_dly + + variable rden_var : std_ulogic := '0'; + variable wren_var : std_ulogic := '0'; + + begin + if((GSR_dly = '1') or (RST_dly = '1'))then + rd_addr <= 0; + rd_flag <= '0'; + + rd_addr_var := 0; + wr_addr_var := 0; + wr1_addr_var := 0; + rd_prefetch_var := 0; + + rdcount_var := 0; + + rd_flag_var := '0'; + wr_flag_var := '0'; + wr1_flag_var := '0'; + rd_prefetch_flag_var := '0'; + + rdcount_flag_var := '0'; + + empty_int := (others => '1'); + almostempty_int := (others => '1'); + empty_ram := (others => '1'); + + ALMOSTEMPTY_zd <= '1'; + EMPTY_zd <= '1'; + RDERR_zd <= '0'; + RDCOUNT_zd <= (others => '0'); + + if(GSR_dly = '1') then + DO_zd((D_W -1) downto 0) <= (others => '0'); + DOP_zd((P_W -1) downto 0) <= (others => '0'); + end if; + + elsif ((rst_rdclk_flag = '1') or (rst_wrclk_flag = '1'))then + + rd_addr <= 0; + rd_flag <= '0'; + + rd_addr_var := 0; + wr_addr_var := 0; + wr1_addr_var := 0; + rd_prefetch_var := 0; + + rdcount_var := 0; + + rd_flag_var := '0'; + wr_flag_var := '0'; + wr1_flag_var := '0'; + rd_prefetch_flag_var := '0'; + + rdcount_flag_var := '0'; + + empty_int := (others => '1'); + almostempty_int := (others => '1'); + empty_ram := (others => '1'); + + ALMOSTEMPTY_zd <= 'X'; + EMPTY_zd <= 'X'; + RDERR_zd <= 'X'; + RDCOUNT_zd <= (others => 'X'); + + DO_zd((D_W -1) downto 0) <= (others => 'X'); + DOP_zd((P_W -1) downto 0) <= (others => 'X'); + + elsif ((GSR_dly = '0') and (RST_dly = '0'))then + + rden_var := RDEN_dly; + wren_var := WREN_dly; + + if(rising_edge(RDCLK_dly)) then + + rd_offset_stdlogic := To_StdLogicVector(ALMOST_EMPTY_OFFSET); + rd_offset_int := SLV_TO_INT(rd_offset_stdlogic); + + rd_flag_var := rd_flag; + wr_flag_var := wr_flag; + + rd_addr_var := rd_addr; + wr_addr_var := wr_addr; + + rdcount_var := SLV_TO_INT(RDCOUNT_zd); + rdcount_flag_var := rdcount_flag; + + if(fwft = '0') then + addr_limit_var := addr_limit; + if((rden_var = '1') and (rd_addr_var /= rdcount_var)) then + DO_zd <= do_in; + DOP_zd <= dop_in; + rd_addr_var := (rd_addr_var + 1) mod addr_limit; + if(rd_addr_var = 0) then + rd_flag_var := NOT rd_flag_var; + end if; + end if; + if (((rd_addr_var = rdcount_var) and (empty_ram(3) = '0')) or + ((rden_var = '1') and (empty_ram(1) = '0'))) then + do_in((D_W-1) downto 0) := MEM((((rdcount_var)*D_W)+(D_W -1)) downto ((rdcount_var)*D_W)); + dop_in((P_W-1) downto 0) := MEMP((((rdcount_var)*P_W)+(P_W -1)) downto ((rdcount_var)*P_W)); + rdcount_var := (rdcount_var + 1) mod addr_limit; + + if(rdcount_var = 0) then + rdcount_flag_var := NOT rdcount_flag_var; + end if; + end if; +----------------- FP -------------------------------- + elsif(fwft = '1') then + if((rden_var = '1') and (rd_addr_var /= rd_prefetch_var)) then + rd_prefetch_var := (rd_prefetch_var + 1) mod addr_limit; + if(rd_prefetch_var = 0) then + rd_prefetch_flag_var := NOT rd_prefetch_flag_var; + end if; + end if; + if((rd_prefetch_var = rd_addr_var) and (rd_addr_var /= rdcount_var)) then + DO_zd <= do_in; + DOP_zd <= dop_in; + rd_addr_var := (rd_addr_var + 1) mod addr_limit; + if(rd_addr_var = 0) then + rd_flag_var := NOT rd_flag_var; + end if; + end if; + if(((rd_addr_var = rdcount_var) and (empty_ram(3) = '0')) or + ((rden_var = '1') and (empty_ram(1) = '0')) or + ((rden_var = '0') and (empty_ram(1) = '0') and (rd_addr_var = rdcount_var))) then + do_in((D_W-1) downto 0) := MEM((((rdcount_var)*D_W)+(D_W -1)) downto ((rdcount_var)*D_W)); + dop_in((P_W-1) downto 0) := MEMP((((rdcount_var)*P_W)+(P_W -1)) downto ((rdcount_var)*P_W)); + rdcount_var := (rdcount_var + 1) mod addr_limit; + if(rdcount_var = 0) then + rdcount_flag_var := NOT rdcount_flag_var; + end if; + end if; + end if; --- end if(fwft = '1') + + + ALMOSTEMPTY_zd <= almostempty_int(3); + if((((rdcount_var + ae_empty) >= wr_addr_var) and (rdcount_flag_var = wr_flag_var)) or (((rdcount_var + ae_empty) >= (wr_addr_var + addr_limit)) and (rdcount_flag_var /= wr_flag_var))) then + almostempty_int(3) := '1'; + almostempty_int(2) := '1'; + almostempty_int(1) := '1'; + almostempty_int(0) := '1'; + elsif(almostempty_int(2) = '0') then + almostempty_int(3) := almostempty_int(0); + almostempty_int(0) := '0'; + end if; + + if(fwft = '0') then + if((rdcount_var = rd_addr_var) and (rdcount_flag_var = rd_flag_var)) then + EMPTY_zd <= '1'; + else + EMPTY_zd <= '0'; + end if; + elsif(fwft = '1') then + if((rd_prefetch_var = rd_addr_var) and (rd_prefetch_flag_var = rd_flag_var)) then + EMPTY_zd <= '1'; + else + EMPTY_zd <= '0'; + end if; + end if; + + if((rdcount_var = wr_addr_var) and (rdcount_flag_var = wr_flag_var)) then + empty_ram(2) := '1'; + empty_ram(1) := '1'; + empty_ram(0) := '1'; + else + empty_ram(2) := empty_ram(1); + empty_ram(1) := empty_ram(0); + empty_ram(0) := '0'; + end if; + + if((rdcount_var = wr1_addr_var) and (rdcount_flag_var = wr1_flag_var)) then + empty_ram(3) := '1'; + else + empty_ram(3) := '0'; + end if; + + wr1_addr_var := wr_addr; + wr1_flag_var := wr_flag; + + if (not (rst_rdclk_flag or rst_wrclk_flag) = '1') then + RDCOUNT_zd <= CONV_STD_LOGIC_VECTOR(rdcount_var, MAX_RDCOUNT); + end if; + + if((rden_var = '1') and (EMPTY_zd = '1')) then + RDERR_zd <= '1'; +-- elsif(rden_var = '0') then + else + RDERR_zd <= '0'; + end if; -- end ((rden_var = '1') and (empty_int /= '1')) + + update_from_read_prcs <= NOT update_from_read_prcs; + + end if; -- end (rising_edge(RDCLK_dly)) + + end if; -- end (GSR_dly = 1) + + if(update_from_write_prcs'event) then + wr_addr_var := wr_addr; + wr_flag_var := wr_flag; + if((((rdcount_var + ae_empty) < wr_addr_var) and (rdcount_flag_var = wr_flag_var)) or + (((rdcount_var + ae_empty) < ( wr_addr_var + addr_limit)) and (rdcount_flag_var /= wr_flag_var))) then + if(wren_var = '1') then + almostempty_int(2) := almostempty_int(1); + almostempty_int(1) := '0'; + end if; + else + almostempty_int(2) := '1'; + almostempty_int(1) := '1'; + end if; + end if; + + rd_addr <= rd_addr_var; + rd_flag <= rd_flag_var; + rdcount_flag <= rdcount_flag_var; + + + end process prcs_read; + +--#################################################################### +--##### Write ##### +--#################################################################### + prcs_write:process(WRCLK_dly, RST_dly, GSR_dly, update_from_read_prcs, rst_rdclk_flag, rst_wrclk_flag) + variable first_time : boolean := true; + variable wr_addr_var : integer := 0; + variable rd_addr_var : integer := 0; + variable rdcount_var : integer := 0; + variable wrcount_var : integer := 0; + + variable rd_flag_var : std_ulogic := '0'; + variable wr_flag_var : std_ulogic := '0'; + + variable rdcount_flag_var : std_ulogic := '0'; + + variable wr_offset_stdlogic : std_logic_vector (ALMOST_FULL_OFFSET'length-1 downto 0); + variable wr_offset_int : integer := 0; + + variable almostfull_int : std_ulogic_vector(3 downto 0) := (others => '0'); + variable full_int : std_ulogic_vector(3 downto 0) := (others => '0'); + +-- CR 195129 fix from verilog (may not be necessary for vhdl) +-- Added ren_var/wren_var to remember the old val of RDEN_dly/WREN_dly + + variable rden_var : std_ulogic := '0'; + variable wren_var : std_ulogic := '0'; + + begin + if ((GSR_dly = '1') or (RST_dly = '1'))then + wr_addr_var := 0; + wr_addr <= 0; + wr_flag <= '0'; + + wr_addr_var := 0; + rd_addr_var := 0; + rdcount_var := 0; + wrcount_var := 0; + + rd_flag_var := '0'; + wr_flag_var := '0'; + + rdcount_flag_var := '0'; + + full_int := (others => '0'); + almostfull_int := (others => '0'); + + if ((GSR_dly = '1') or (RST_dly = '1'))then + ALMOSTFULL_zd <= '0'; + FULL_zd <= '0'; + WRERR_zd <= '0'; + WRCOUNT_zd <= (others => '0'); + else + ALMOSTFULL_zd <= 'X'; + FULL_zd <= 'X'; + WRERR_zd <= 'X'; + WRCOUNT_zd <= (others => 'X'); + end if; + + elsif((GSR_dly = '0') and (RST_dly = '0'))then + rden_var := RDEN_dly; + wren_var := WREN_dly; + + if(rising_edge(WRCLK_dly)) then + + wr_offset_stdlogic := To_StdLogicVector(ALMOST_FULL_OFFSET); + wr_offset_int := SLV_TO_INT(wr_offset_stdlogic); + + rd_flag_var := rd_flag; + wr_flag_var := wr_flag; + + rd_addr_var := rd_addr; + wr_addr_var := wr_addr; + + rdcount_var := SLV_TO_INT(RDCOUNT_zd); + rdcount_flag_var := rdcount_flag; + + if((wren_var = '1') and (full_int(1)= '0') and (RST_dly = '0'))then + MEM((((wr_addr_var)*D_W) +(D_W-1)) downto ((wr_addr_var)*D_W)) <= DI_dly((D_W -1) downto 0); + MEMP((((wr_addr_var)*P_W) +(P_W-1)) downto ((wr_addr_var)*P_W)) <= DIP_dly((P_W -1) downto 0); + + wr_addr_var := (wr_addr_var + 1) mod addr_limit; + + if(wr_addr_var = 0) then + wr_flag_var := NOT wr_flag_var; + end if; + end if; -- if((wren_var = '1') and (FULL_zd = '0') .... + + if((wren_var = '1') and (full_int(1) = '1')) then + WRERR_zd <= '1'; + else + WRERR_zd <= '0'; + end if; + + ALMOSTFULL_zd <= almostfull_int(3); + if((((rdcount_var + addr_limit) <= (wr_addr_var + wr_offset_int)) and (rdcount_flag_var = wr_flag_var)) or ((rdcount_var <= (wr_addr_var + wr_offset_int)) and (rdcount_flag_var /= wr_flag_var))) then + almostfull_int(3) := '1'; + almostfull_int(2) := '1'; + almostfull_int(1) := '1'; + almostfull_int(0) := '1'; + elsif(almostfull_int(2) = '0') then + almostfull_int(3) := almostfull_int(0); + almostfull_int(0) := '0'; + end if; + + + FULL_zd <= full_int(1); + if((rdcount_var = wr_addr_var) and (rdcount_flag_var /= wr_flag_var)) then + full_int(1) := '1'; + full_int(0) := '1'; + else + full_int(1) := full_int(0); + full_int(0) := '0'; + end if; + + update_from_write_prcs <= NOT update_from_write_prcs; + + WRCOUNT_zd <= CONV_STD_LOGIC_VECTOR( wr_addr_var, MAX_WRCOUNT); + + wr_addr <= wr_addr_var; + wr_flag <= wr_flag_var; + + end if; -- if(rising(WRCLK_dly)) + + end if; -- if(GSR_dly = '1')) + + + if(update_from_read_prcs'event) then + rdcount_var := SLV_TO_INT(RDCOUNT_zd); + rdcount_flag_var := rdcount_flag; + if((((rdcount_var + addr_limit) > (wr_addr_var + wr_offset_int)) and (rdcount_flag_var = wr_flag_var)) or ((rdcount_var > (wr_addr_var + wr_offset_int)) and (rdcount_flag_var /= wr_flag_var))) then +-- if(rden_var = '1') then +-- replaced the above line with line below +-- fp -- 09_10_03 + + if(((rden_var = '1') and (EMPTY_zd = '0')) or ((((rd_addr_var + 1) mod addr_limit) = rdcount_var) and (almostfull_int(1) = '1'))) then + almostfull_int(2) := almostfull_int(1); + almostfull_int(1) := '0'; + end if; + else + almostfull_int(2) := '1'; + almostfull_int(1) := '1'; + end if; + end if; + + end process prcs_write; + + + -- matching HW behavior to pull up the unused output bits + prcs_x_1_output: process (WRCOUNT_zd, RDCOUNT_zd, DO_zd, DOP_zd) + begin -- process prcs_x_1_output + + case DATA_WIDTH is + when 4 => + WRCOUNT_OUT_zd <= WRCOUNT_zd; + RDCOUNT_OUT_zd <= RDCOUNT_zd; + DO_OUT_zd(3 downto 0) <= DO_zd(3 downto 0); + when 9 => + WRCOUNT_OUT_zd(10 downto 0) <= WRCOUNT_zd(10 downto 0); + RDCOUNT_OUT_zd(10 downto 0) <= RDCOUNT_zd(10 downto 0); + DO_OUT_zd(7 downto 0) <= DO_zd(7 downto 0); + DOP_OUT_zd(0 downto 0) <= DOP_zd(0 downto 0); + when 18 => + WRCOUNT_OUT_zd(9 downto 0) <= WRCOUNT_zd(9 downto 0); + RDCOUNT_OUT_zd(9 downto 0) <= RDCOUNT_zd(9 downto 0); + DO_OUT_zd(15 downto 0) <= DO_zd(15 downto 0); + DOP_OUT_zd(1 downto 0) <= DOP_zd(1 downto 0); + when 36 => + WRCOUNT_OUT_zd(8 downto 0) <= WRCOUNT_zd(8 downto 0); + RDCOUNT_OUT_zd(8 downto 0) <= RDCOUNT_zd(8 downto 0); + DO_OUT_zd(31 downto 0) <= DO_zd(31 downto 0); + DOP_OUT_zd(3 downto 0) <= DOP_zd(3 downto 0); + when others => + WRCOUNT_OUT_zd <= WRCOUNT_zd; + RDCOUNT_OUT_zd <= RDCOUNT_zd; + DO_OUT_zd <= DO_zd; + end case; + end process prcs_x_1_output; + + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(ALMOSTEMPTY_zd, ALMOSTFULL_zd, DO_OUT_zd, DOP_OUT_zd, + EMPTY_zd, FULL_zd, RDCOUNT_OUT_zd, RDERR_zd, + WRCOUNT_OUT_zd, WRERR_zd) + begin + ALMOSTEMPTY <= ALMOSTEMPTY_zd after SYNC_PATH_DELAY; + ALMOSTFULL <= ALMOSTFULL_zd after SYNC_PATH_DELAY; + DO <= DO_OUT_zd after SYNC_PATH_DELAY; + DOP <= DOP_OUT_zd after SYNC_PATH_DELAY; + EMPTY <= EMPTY_zd after SYNC_PATH_DELAY; + FULL <= FULL_zd after SYNC_PATH_DELAY; + RDCOUNT <= RDCOUNT_OUT_zd after SYNC_PATH_DELAY; + RDERR <= RDERR_zd after SYNC_PATH_DELAY; + WRCOUNT <= WRCOUNT_OUT_zd after SYNC_PATH_DELAY; + WRERR <= WRERR_zd after SYNC_PATH_DELAY; + end process prcs_output; +--#################################################################### + + +end FIFO16_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/frame_ecc_virtex4.vhd,v 1.5 2004/07/26 18:37:21 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / +-- /___/ /\ Filename : FRAME_ECC_VIRTEX4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:03 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL FRAME_ECC_VIRTEX4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FRAME_ECC_VIRTEX4 is + port( + ERROR : out std_ulogic; + SYNDROME : out std_logic_vector(11 downto 0); + SYNDROMEVALID : out std_ulogic + ); + +end FRAME_ECC_VIRTEX4; + +architecture FRAME_ECC_VIRTEX4_V of FRAME_ECC_VIRTEX4 is + +begin +end FRAME_ECC_VIRTEX4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/gt11clk_mgt.vhd,v 1.7 2004/08/31 13:40:21 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 11-Gigabit Transceiver Clock +-- /___/ /\ Filename : GT11CLK_MGT.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:03 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT11CLK_MGT ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity GT11CLK_MGT is + generic ( + SYNCLK1OUTEN : string := "ENABLE"; + SYNCLK2OUTEN : string := "DISABLE" + ); + + port ( + SYNCLK1OUT : out std_ulogic; + SYNCLK2OUT : out std_ulogic; + + MGTCLKN : in std_ulogic; + MGTCLKP : in std_ulogic + ); +end GT11CLK_MGT; + +architecture GT11CLK_MGT_V of GT11CLK_MGT is +signal mgtclk_out : std_ulogic; +begin + gen_mgtclk_out : process + begin + if ((MGTCLKP = '1') and (MGTCLKN = '0')) then + mgtclk_out <= MGTCLKP; + elsif ((MGTCLKP = '0') and (MGTCLKN = '1')) then + mgtclk_out <= MGTCLKP; + end if; + wait on MGTCLKN, MGTCLKP; + end process; + + VitalBehavior : process + variable first_time : boolean := true; + + + begin + if (first_time = true) then + if((SYNCLK1OUTEN = "ENABLE") or (SYNCLK1OUTEN = "enable")) then + elsif((SYNCLK1OUTEN = "DISABLE") or (SYNCLK1OUTEN = "disable")) then + else + assert FALSE report "Error : SYNCLK1OUTEN = is not ENABLE, DISABLE." severity warning; + end if; + + if((SYNCLK2OUTEN = "ENABLE") or (SYNCLK2OUTEN = "enable")) then + elsif((SYNCLK2OUTEN = "DISABLE") or (SYNCLK2OUTEN = "disable")) then + else + assert FALSE report "Error : SYNCLK2OUTEN = is not ENABLE, DISABLE." severity warning; + end if; + first_time := false; + end if; + wait; + end process VitalBehavior; + + schedule_outputs : process + begin + if ((SYNCLK1OUTEN = "ENABLE") or (SYNCLK1OUTEN = "enable")) then + SYNCLK1OUT <= mgtclk_out; + elsif((SYNCLK1OUTEN = "DISABLE") or (SYNCLK1OUTEN = "disable")) then + SYNCLK1OUT <= 'Z'; + else + end if; + + if ((SYNCLK2OUTEN = "ENABLE") or (SYNCLK2OUTEN = "enable")) then + SYNCLK2OUT <= mgtclk_out; + elsif((SYNCLK2OUTEN = "DISABLE") or (SYNCLK2OUTEN = "disable")) then + SYNCLK2OUT <= 'Z'; + else + end if; + + wait on mgtclk_out; + end process schedule_outputs; +end GT11CLK_MGT_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/gt11clk.vhd,v 1.3 2004/08/31 13:40:21 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 11-Gigabit Transceiver Clock +-- /___/ /\ Filename : GT11CLK.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:03 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL GT11CLK ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity GT11CLK is +generic ( + REFCLKSEL : string := "MGTCLK"; + SYNCLK1OUTEN : string := "ENABLE"; + SYNCLK2OUTEN : string := "DISABLE" + ); + +port ( + SYNCLK1OUT : out std_ulogic; + SYNCLK2OUT : out std_ulogic; + + MGTCLKN : in std_ulogic; + MGTCLKP : in std_ulogic; + REFCLK : in std_ulogic; + RXBCLK : in std_ulogic; + SYNCLK1IN : in std_ulogic; + SYNCLK2IN : in std_ulogic + ); +end GT11CLK; + +architecture GT11CLK_V of GT11CLK is +signal mgtclk_out : std_ulogic; +signal mux_out : std_ulogic; + +begin + + gen_mgtclk_out : process + begin + if ((MGTCLKP = '1') and (MGTCLKN = '0')) then + mgtclk_out <= MGTCLKP; + elsif ((MGTCLKP = '0') and (MGTCLKN = '1')) then + mgtclk_out <= MGTCLKP; + end if; + wait on MGTCLKN, MGTCLKP; + end process; + + VitalBehavior : process + variable first_time : boolean := true; + begin + if (first_time = true) then + if((REFCLKSEL = "MGTCLK") or (REFCLKSEL = "mgtclk")) then + elsif((REFCLKSEL = "SYNCLK1IN") or (REFCLKSEL = "synclk1in")) then + elsif((REFCLKSEL = "SYNCLK2IN") or (REFCLKSEL = "synclk2in")) then + elsif((REFCLKSEL = "REFCLK") or (REFCLKSEL = "grefclk")) then + elsif((REFCLKSEL = "RXBCLK") or (REFCLKSEL = "rxbclk")) then + else + assert FALSE report "Error : REFCLKSEL = is not MGTCLK, SYNCLK1IN, SYNCLK2IN, REFCLK, RXBCLK." severity error; + end if; + + if((SYNCLK1OUTEN = "ENABLE") or (SYNCLK1OUTEN = "enable")) then + elsif((SYNCLK1OUTEN = "DISABLE") or (SYNCLK1OUTEN = "disable")) then + else + assert FALSE report "Error : SYNCLK1OUTEN = is not ENABLE, DISABLE." severity error; + end if; + + if((SYNCLK2OUTEN = "ENABLE") or (SYNCLK2OUTEN = "enable")) then + elsif((SYNCLK2OUTEN = "DISABLE") or (SYNCLK2OUTEN = "disable")) then + else + assert FALSE report "Error : SYNCLK2OUTEN = is not ENABLE, DISABLE." severity error; + end if; + first_time := false; + end if; + + if (mgtclk_out'event) then + if((REFCLKSEL = "MGTCLK") or (REFCLKSEL = "mgtclk")) then + mux_out <= mgtclk_out; + end if; + end if; + + if (SYNCLK1IN'event) then + if((REFCLKSEL = "SYNCLK1IN") or (REFCLKSEL = "synclk1in")) then + mux_out <= SYNCLK1IN; + end if; + end if; + + if (SYNCLK2IN'event) then + if((REFCLKSEL = "SYNCLK2IN") or (REFCLKSEL = "synclk2in")) then + mux_out <= SYNCLK2IN; + end if; + end if; + + if (REFCLK'event) then + if((REFCLKSEL = "REFCLK") or (REFCLKSEL = "refclk")) then + mux_out <= REFCLK; + end if; + end if; + + if (RXBCLK'event) then + if((REFCLKSEL = "RXBCLK") or (REFCLKSEL = "RXBCLK")) then + mux_out <= RXBCLK; + end if; + end if; + wait on mgtclk_out, SYNCLK1IN, SYNCLK2IN, REFCLK, RXBCLK; + end process VitalBehavior; + + schedule_outputs : process + begin + if ((SYNCLK1OUTEN = "ENABLE") or (SYNCLK1OUTEN = "enable")) then + SYNCLK1OUT <= mux_out; + elsif((SYNCLK1OUTEN = "DISABLE") or (SYNCLK1OUTEN = "disable")) then + SYNCLK1OUT <= 'Z'; + else + end if; + + if ((SYNCLK2OUTEN = "ENABLE") or (SYNCLK2OUTEN = "enable")) then + SYNCLK2OUT <= mux_out; + elsif((SYNCLK2OUTEN = "DISABLE") or (SYNCLK2OUTEN = "disable")) then + SYNCLK2OUT <= 'Z'; + else + end if; + + wait on mux_out; + end process schedule_outputs; +end GT11CLK_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/icap_virtex4.vhd,v 1.5 2004/04/29 21:21:50 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Internal Configuration Access Port for Virtex4 +-- /___/ /\ Filename : ICAP_VIRTEX4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:04 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL ICAP_VIRTEX4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +entity ICAP_VIRTEX4 is + generic( + ICAP_WIDTH : string := "X8" + ); + + + port( + BUSY : out std_ulogic; + O : out std_logic_vector(31 downto 0); + + CE : in std_ulogic; + CLK : in std_ulogic; + I : in std_logic_vector(31 downto 0); + WRITE : in std_ulogic + ); + +end ICAP_VIRTEX4; + +architecture ICAP_VIRTEX4_V of ICAP_VIRTEX4 is + +begin +end ICAP_VIRTEX4_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / Dual Data Rate Input D Flip-Flop +-- /___/ /\ Filename : IDDR.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:18:20 PST 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IDDR ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + + +library unisim; +use unisim.vpkg.all; + +entity IDDR is + + generic( + + DDR_CLK_EDGE : string := "OPPOSITE_EDGE"; + INIT_Q1 : bit := '0'; + INIT_Q2 : bit := '0'; + SRTYPE : string := "SYNC" + ); + + port( + Q1 : out std_ulogic; + Q2 : out std_ulogic; + + C : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); + +end IDDR; + +architecture IDDR_V OF IDDR is + + + constant SYNC_PATH_DELAY : time := 100 ps; + + signal C_ipd : std_ulogic := 'X'; + signal CE_ipd : std_ulogic := 'X'; + signal D_ipd : std_ulogic := 'X'; + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := 'X'; + signal R_ipd : std_ulogic := 'X'; + signal S_ipd : std_ulogic := 'X'; + + signal C_dly : std_ulogic := 'X'; + signal CE_dly : std_ulogic := 'X'; + signal D_dly : std_ulogic := 'X'; + signal GSR_dly : std_ulogic := 'X'; + signal R_dly : std_ulogic := 'X'; + signal S_dly : std_ulogic := 'X'; + + signal Q1_zd : std_ulogic := 'X'; + signal Q2_zd : std_ulogic := 'X'; + + signal Q1_viol : std_ulogic := 'X'; + signal Q2_viol : std_ulogic := 'X'; + + signal Q1_o_reg : std_ulogic := 'X'; + signal Q2_o_reg : std_ulogic := 'X'; + signal Q3_o_reg : std_ulogic := 'X'; + signal Q4_o_reg : std_ulogic := 'X'; + + signal ddr_clk_edge_type : integer := -999; + signal sr_type : integer := -999; +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + C_dly <= C after 0 ps; + CE_dly <= CE after 0 ps; + D_dly <= D after 0 ps; + GSR_dly <= GSR after 0 ps; + R_dly <= R after 0 ps; + S_dly <= S after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + + begin + if((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then + ddr_clk_edge_type <= 1; + elsif((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then + ddr_clk_edge_type <= 2; + elsif((DDR_CLK_EDGE = "SAME_EDGE_PIPELINED") or (DDR_CLK_EDGE = "same_edge_pipelined")) then + ddr_clk_edge_type <= 3; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DDR_CLK_EDGE ", + EntityName => "/IDDR", + GenericValue => DDR_CLK_EDGE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " OPPOSITE_EDGE or SAME_EDGE or SAME_EDGE_PIPELINED.", + TailMsg => "", + MsgSeverity => ERROR + ); + end if; + + if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then + sr_type <= 1; + elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then + sr_type <= 2; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRTYPE ", + EntityName => "/IDDR", + GenericValue => SRTYPE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " ASYNC or SYNC. ", + TailMsg => "", + MsgSeverity => ERROR + ); + end if; + + wait; + end process prcs_init; +--#################################################################### +--##### q1_q2_q3_q4 reg ##### +--#################################################################### + prcs_q1q2q3q4_reg:process(C_dly, D_dly, GSR_dly, R_dly, S_dly) + variable Q1_var : std_ulogic := TO_X01(INIT_Q1); + variable Q2_var : std_ulogic := TO_X01(INIT_Q2); + variable Q3_var : std_ulogic := TO_X01(INIT_Q1); + variable Q4_var : std_ulogic := TO_X01(INIT_Q2); + begin + if(GSR_dly = '1') then + Q1_var := TO_X01(INIT_Q1); + Q3_var := TO_X01(INIT_Q1); + Q2_var := TO_X01(INIT_Q2); + Q4_var := TO_X01(INIT_Q2); + elsif(GSR_dly = '0') then + case sr_type is + when 1 => + if(R_dly = '1') then + Q1_var := '0'; + Q2_var := '0'; + Q3_var := '0'; + Q4_var := '0'; + elsif((R_dly = '0') and (S_dly = '1')) then + Q1_var := '1'; + Q2_var := '1'; + Q3_var := '1'; + Q4_var := '1'; + elsif((R_dly = '0') and (S_dly = '0')) then + if(CE_dly = '1') then + if(rising_edge(C_dly)) then + Q3_var := Q1_var; + Q1_var := D_dly; + Q4_var := Q2_var; + end if; + if(falling_edge(C_dly)) then + Q2_var := D_dly; + end if; + end if; + end if; + + when 2 => + if(rising_edge(C_dly)) then + if(R_dly = '1') then + Q1_var := '0'; + Q3_var := '0'; + Q4_var := '0'; + elsif((R_dly = '0') and (S_dly = '1')) then + Q1_var := '1'; + Q3_var := '1'; + Q4_var := '1'; + elsif((R_dly = '0') and (S_dly = '0')) then + if(CE_dly = '1') then + Q3_var := Q1_var; + Q1_var := D_dly; + Q4_var := Q2_var; + end if; + end if; + end if; + + if(falling_edge(C_dly)) then + if(R_dly = '1') then + Q2_var := '0'; + elsif((R_dly = '0') and (S_dly = '1')) then + Q2_var := '1'; + elsif((R_dly = '0') and (S_dly = '0')) then + if(CE_dly = '1') then + Q2_var := D_dly; + end if; + end if; + end if; + + when others => + null; + end case; + end if; + + q1_o_reg <= Q1_var; + q2_o_reg <= Q2_var; + q3_o_reg <= Q3_var; + q4_o_reg <= Q4_var; + + end process prcs_q1q2q3q4_reg; +--#################################################################### +--##### q1 & q2 mux ##### +--#################################################################### + prcs_q1q2_mux:process(q1_o_reg, q2_o_reg, q3_o_reg, q4_o_reg) + begin + case ddr_clk_edge_type is + when 1 => + Q1_zd <= q1_o_reg; + Q2_zd <= q2_o_reg; + when 2 => + Q1_zd <= q1_o_reg; + Q2_zd <= q4_o_reg; + when 3 => + Q1_zd <= q3_o_reg; + Q2_zd <= q4_o_reg; + when others => + null; + end case; + end process prcs_q1q2_mux; +--#################################################################### + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(Q1_zd, Q2_zd) + begin + Q1 <= Q1_zd after SYNC_PATH_DELAY; + Q2 <= Q2_zd after SYNC_PATH_DELAY; + end process prcs_output; +--#################################################################### + + +end IDDR_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / Input Delay Controller +-- /___/ /\ Filename : IDELAYCTRL.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:18:20 PST 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 09/12/06 - intialized output # 234140 +-- 04/10/07 - CR 436682 fix, disable activity when rst is high +-- End Revision + +----- CELL IDELAYCTRL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + + +library unisim; +use unisim.vpkg.all; + +entity IDELAYCTRL is + + port( + RDY : out std_ulogic; + + REFCLK : in std_ulogic; + RST : in std_ulogic + ); + +end IDELAYCTRL; + +architecture IDELAYCTRL_V OF IDELAYCTRL is + + + constant SYNC_PATH_DELAY : time := 100 ps; + + signal REFCLK_ipd : std_ulogic := 'X'; + signal RST_ipd : std_ulogic := 'X'; + + signal GSR_dly : std_ulogic := '0'; + signal REFCLK_dly : std_ulogic := 'X'; + signal RST_dly : std_ulogic := 'X'; + + signal RDY_zd : std_ulogic := '0'; + signal RDY_viol : std_ulogic := 'X'; + +-- taken from DCM_adv + signal period : time := 0 ps; +-- CR 234140 + signal lost : std_ulogic := '1'; + signal lost_r : std_ulogic := '0'; + signal lost_f : std_ulogic := '0'; + signal clock_negedge, clock_posedge, clock : std_ulogic; + signal temp1 : boolean := false; + signal temp2 : boolean := false; + signal clock_low, clock_high : std_ulogic := '0'; + + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + REFCLK_dly <= REFCLK after 0 ps; + RST_dly <= RST after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### RDY ##### +--#################################################################### + prcs_rdy:process(RST_dly, lost) + begin + if((RST_dly = '1') or (lost = '1')) then + RDY_zd <= '0'; +-- CR 436682 fix +-- elsif((RST_dly'event) and (RST_dly = '0') and (lost = '0')) then + elsif((RST_dly = '0') and (lost = '0')) then + RDY_zd <= '1'; + end if; + end process prcs_rdy; +--#################################################################### +--##### prcs_determine_period ##### +--#################################################################### + prcs_determine_period : process + variable clock_edge_previous : time := 0 ps; + variable clock_edge_current : time := 0 ps; + begin + if (RST_dly = '0' ) then + if (rising_edge(REFCLK_dly)) then + clock_edge_previous := clock_edge_current; + clock_edge_current := NOW; + if (period /= 0 ps and ((clock_edge_current - clock_edge_previous) <= (1.5 * period))) then + period <= NOW - clock_edge_previous; + elsif (period /= 0 ps and ((NOW - clock_edge_previous) > (1.5 * period))) then + period <= 0 ps; + elsif ((period = 0 ps) and (clock_edge_previous /= 0 ps)) then + period <= NOW - clock_edge_previous; + end if; + end if; + end if; + wait on REFCLK_dly; + end process prcs_determine_period; + +--#################################################################### +--##### prcs_clock_lost_checker ##### +--#################################################################### + prcs_clock_lost_checker : process + variable clock_low, clock_high : std_ulogic := '0'; + + begin + if (rising_edge(REFCLK_dly)) then + clock_low := '0'; + clock_high := '1'; + clock_posedge <= '0'; + clock_negedge <= '1'; + end if; + + if (falling_edge(REFCLK_dly)) then + clock_high := '0'; + clock_low := '1'; + clock_posedge <= '1'; + clock_negedge <= '0'; + end if; + wait on REFCLK_dly; + end process prcs_clock_lost_checker; + +--#################################################################### +--##### prcs_set_reset_lost_r ##### +--#################################################################### + prcs_set_reset_lost_r : process + begin + if (rising_edge(REFCLK_dly)) then + if (period /= 0 ps) then + lost_r <= '0'; + end if; + wait for (period * 9.1)/10; + if ((clock_low /= '1') and (clock_posedge /= '1')) then + lost_r <= '1'; + end if; + end if; + wait on REFCLK_dly; + end process prcs_set_reset_lost_r; + +--#################################################################### +--##### prcs_assign_lost ##### +--#################################################################### + prcs_assign_lost : process + begin + if (lost_r'event) then + lost <= lost_r; + end if; + if (lost_f'event) then + lost <= lost_f; + end if; + wait on lost_r, lost_f; + end process prcs_assign_lost; + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(RDY_zd) + begin + RDY <= RDY_zd after SYNC_PATH_DELAY; + end process prcs_output; +--#################################################################### + + +end IDELAYCTRL_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / Input Delay Line +-- /___/ /\ Filename : IDELAY.vhd +-- \ \ / \ Timestamp : Thu Mar 17 16:56:02 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 03/17/05 - Changed SIM_TAPDELAY_VALUE to 75 ps from 78 ps -- CR 204824 --FP +-- 06/14/05 - Fixed VitalPathDelay constructs -- CR 209786 --FP +-- 08/08/05 - Made tap count to wrap around -- CR 213995 --FP +-- 07/18/06 - CR 234556 fix. Added SIM_DELAY_D --FP +-- 12/29/06 - CR 430648 Simprim fix. For fixed/default, delay is annotated via sdf. +-- End Revision +----- CELL IDELAY ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + + +library unisim; +use unisim.vpkg.all; + +entity IDELAY is + + generic( + + IOBDELAY_TYPE : string := "DEFAULT"; + IOBDELAY_VALUE : integer := 0 + ); + + port( + O : out std_ulogic; + + C : in std_ulogic; + CE : in std_ulogic; + I : in std_ulogic; + INC : in std_ulogic; + RST : in std_ulogic + ); + +end IDELAY; + +architecture IDELAY_V OF IDELAY is + + constant SIM_TAPDELAY_VALUE : integer := 75; + + --------------------------------------------------------- + -- Function str_2_int converts string to integer + --------------------------------------------------------- + function str_2_int(str: in string ) return integer is + variable int : integer; + variable val : integer := 0; + variable neg_flg : boolean := false; + variable is_it_int : boolean := true; + begin + int := 0; + val := 0; + is_it_int := true; + neg_flg := false; + + for i in 1 to str'length loop + case str(i) is + when '-' + => + if(i = 1) then + neg_flg := true; + val := -1; + end if; + when '1' + => val := 1; + when '2' + => val := 2; + when '3' + => val := 3; + when '4' + => val := 4; + when '5' + => val := 5; + when '6' + => val := 6; + when '7' + => val := 7; + when '8' + => val := 8; + when '9' + => val := 9; + when '0' + => val := 0; + when others + => is_it_int := false; + end case; + if(val /= -1) then + int := int *10 + val; + end if; + val := 0; + end loop; + if(neg_flg) then + int := int * (-1); + end if; + + if(NOT is_it_int) then + int := -9999; + end if; + return int; + end; +----------------------------------------------------------- + + constant SYNC_PATH_DELAY : time := 0 ps; + + constant MIN_TAP_COUNT : integer := 0; + constant MAX_TAP_COUNT : integer := 63; + + signal C_ipd : std_ulogic := 'X'; + signal CE_ipd : std_ulogic := 'X'; + signal GSR_ipd : std_ulogic := 'X'; + signal I_ipd : std_ulogic := 'X'; + signal INC_ipd : std_ulogic := 'X'; + signal RST_ipd : std_ulogic := 'X'; + + signal C_dly : std_ulogic := 'X'; + signal CE_dly : std_ulogic := 'X'; + signal GSR_dly : std_ulogic := '0'; + signal I_dly : std_ulogic := 'X'; + signal INC_dly : std_ulogic := 'X'; + signal RST_dly : std_ulogic := 'X'; + + signal O_zd : std_ulogic := 'X'; + signal O_viol : std_ulogic := 'X'; + + signal TapCount : integer := 0; + signal IsTapDelay : boolean := true; + signal IsTapFixed : boolean := false; + signal IsTapDefault : boolean := false; + signal Delay : time := 0 ps; + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + C_dly <= C after 0 ps; + CE_dly <= CE after 0 ps; + I_dly <= I after 0 ps; + INC_dly <= INC after 0 ps; + RST_dly <= RST after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + variable TapCount_var : integer := 0; + variable IsTapDelay_var : boolean := true; + variable IsTapFixed_var : boolean := false; + variable IsTapDefault_var : boolean := false; + begin +-- if((IOBDELAY_VALUE = "OFF") or (IOBDELAY_VALUE = "off")) then +-- IsTapDelay_var := false; +-- elsif((IOBDELAY_VALUE = "ON") or (IOBDELAY_VALUE = "on")) then +-- IsTapDelay_var := false; +-- else +-- TapCount_var := str_2_int(IOBDELAY_VALUE); + TapCount_var := IOBDELAY_VALUE; + If((TapCount_var >= 0) and (TapCount_var <= 63)) then + IsTapDelay_var := true; + + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " IOBDELAY_VALUE ", + EntityName => "/IOBDELAY_VALUE", + GenericValue => IOBDELAY_VALUE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " OFF, 1, 2, ..., 62, 63 ", + TailMsg => "", + MsgSeverity => failure + ); + end if; +-- end if; + + if(IsTapDelay_var) then + if((IOBDELAY_TYPE = "FIXED") or (IOBDELAY_TYPE = "fixed")) then + IsTapFixed_var := true; + elsif((IOBDELAY_TYPE = "VARIABLE") or (IOBDELAY_TYPE = "variable")) then + IsTapFixed_var := false; + elsif((IOBDELAY_TYPE = "DEFAULT") or (IOBDELAY_TYPE = "default")) then + IsTapDefault_var := true; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " IOBDELAY_TYPE ", + EntityName => "/IOBDELAY_TYPE", + GenericValue => IOBDELAY_TYPE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " FIXED or VARIABLE ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + end if; + + IsTapDelay <= IsTapDelay_var; + IsTapFixed <= IsTapFixed_var; + IsTapDefault <= IsTapDefault_var; + TapCount <= TapCount_var; + + wait; + end process prcs_init; +--#################################################################### +--##### CALCULATE DELAY ##### +--#################################################################### + prcs_refclk:process(C_dly, GSR_dly, RST_dly) + variable TapCount_var : integer :=0; + variable FIRST_TIME : boolean :=true; + variable BaseTime_var : time := 1 ps ; + variable delay_var : time := 0 ps ; + begin + if(IsTapDelay) then + if((GSR_dly = '1') or (FIRST_TIME))then + TapCount_var := TapCount; + Delay <= TapCount_var * SIM_TAPDELAY_VALUE * BaseTime_var; + FIRST_TIME := false; + elsif(GSR_dly = '0') then + if(rising_edge(C_dly)) then + if(RST_dly = '1') then + TapCount_var := TapCount; + elsif((RST_dly = '0') and (CE_dly = '1')) then +-- CR fix CR 213995 + if(INC_dly = '1') then + if (TapCount_var < MAX_TAP_COUNT) then + TapCount_var := TapCount_var + 1; + else + TapCount_var := MIN_TAP_COUNT; + end if; + elsif(INC_dly = '0') then + if (TapCount_var > MIN_TAP_COUNT) then + TapCount_var := TapCount_var - 1; + else + TapCount_var := MAX_TAP_COUNT; + end if; + + end if; -- INC_dly + end if; -- RST_dly + Delay <= TapCount_var * SIM_TAPDELAY_VALUE * BaseTime_var; + end if; -- C_dly + end if; -- GSR_dly + + end if; -- IsTapDelay + end process prcs_refclk; + + +--#################################################################### +--##### DELAY INPUT ##### +--#################################################################### + prcs_i:process(I_dly) + begin + if(IsTapFixed) then + O_zd <= transport I_dly after (TapCount *SIM_TAPDELAY_VALUE * 1 ps); + else + O_zd <= transport I_dly after delay; + end if; + end process prcs_i; + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(O_zd) + begin + O <= O_zd after SYNC_PATH_DELAY; + end process prcs_output; +--#################################################################### + + +end IDELAY_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / Source Synchronous Input Deserializer +-- /___/ /\ Filename : ISERDES.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:18:20 PST 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 05/29/06 - CR 232324 -- Added timing checks for SR/REV wrt negedge CLKDIV +-- 07/19/06 - CR 234556 fix. Added sim_DELAY_D, sim_SETUP_D_CLK and sim_HOLD_D_CLK --FP +-- 10/13/06 - CR 426606 fix +-- 08/29/07 - CR 447556 Fixed attribute INTERFACE_TYPE to be case insensitive +-- 09/10/07 - CR 447760 Added Strict DRC for BITSLIP and INTERFACE_TYPE combinations +-- End Revision +----- CELL ISERDES ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_arith.all; + + +library unisim; +use unisim.vpkg.all; +use unisim.vcomponents.all; + +--//////////////////////////////////////////////////////////// +--////////////////////////// BSCNTRL ///////////////////////// +--//////////////////////////////////////////////////////////// +entity bscntrl is + generic( + SRTYPE : string; + INIT_BITSLIPCNT : bit_vector(3 downto 0) + ); + port( + CLKDIV_INT : out std_ulogic; + MUXC : out std_ulogic; + + BITSLIP : in std_ulogic; + C23 : in std_ulogic; + C45 : in std_ulogic; + C67 : in std_ulogic; + CLK : in std_ulogic; + CLKDIV : in std_ulogic; + DATA_RATE : in std_ulogic; + GSR : in std_ulogic; + R : in std_ulogic; + SEL : in std_logic_vector (1 downto 0) + ); + +end bscntrl; + +architecture bscntrl_V of bscntrl is +-- constant DELAY_FFBSC : time := 300 ns; +-- constant DELAY_MXBSC : time := 60 ns; + constant DELAY_FFBSC : time := 300 ps; + constant DELAY_MXBSC : time := 60 ps; + + signal AttrSRtype : integer := 0; + + signal q1 : std_ulogic := 'X'; + signal q2 : std_ulogic := 'X'; + signal q3 : std_ulogic := 'X'; + signal mux : std_ulogic := 'X'; + signal qhc1 : std_ulogic := 'X'; + signal qhc2 : std_ulogic := 'X'; + signal qlc1 : std_ulogic := 'X'; + signal qlc2 : std_ulogic := 'X'; + signal qr1 : std_ulogic := 'X'; + signal qr2 : std_ulogic := 'X'; + signal mux1 : std_ulogic := 'X'; + signal clkdiv_zd : std_ulogic := 'X'; + +begin +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + begin + + if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then + AttrSrtype <= 0; + elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then + AttrSrtype <= 1; + end if; + + wait; + end process prcs_init; +--#################################################################### +--##### Divide by 2 - 8 counter ##### +--#################################################################### + prcs_div_2_8_cntr:process(qr2, CLK, GSR) + variable clkdiv_int_var : std_ulogic := TO_X01(INIT_BITSLIPCNT(0)); + variable q1_var : std_ulogic := TO_X01(INIT_BITSLIPCNT(1)); + variable q2_var : std_ulogic := TO_X01(INIT_BITSLIPCNT(2)); + variable q3_var : std_ulogic := TO_X01(INIT_BITSLIPCNT(3)); + begin + if(GSR = '1') then + clkdiv_int_var := TO_X01(INIT_BITSLIPCNT(0)); + q1_var := TO_X01(INIT_BITSLIPCNT(1)); + q2_var := TO_X01(INIT_BITSLIPCNT(2)); + q3_var := TO_X01(INIT_BITSLIPCNT(3)); + elsif(GSR = '0') then + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if(qr2 = '1') then + clkdiv_int_var := '0'; + q1_var := '0'; + q2_var := '0'; + q3_var := '0'; + elsif (qhc1 = '1') then + clkdiv_int_var := clkdiv_int_var; + q1_var := q1_var; + q2_var := q2_var; + q3_var := q3_var; + else + if(rising_edge(CLK)) then + q3_var := q2_var; + q2_var :=( NOT((NOT clkdiv_int_var) and (NOT q2_var)) and q1_var); + q1_var := clkdiv_int_var; + clkdiv_int_var := mux; + end if; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(CLK)) then + if(qr2 = '1') then + clkdiv_int_var := '0'; + q1_var := '0'; + q2_var := '0'; + q3_var := '0'; + elsif (qhc1 = '1') then + clkdiv_int_var := clkdiv_int_var; + q1_var := q1_var; + q2_var := q2_var; + q3_var := q3_var; + else + q3_var := q2_var; + q2_var :=( NOT((NOT clkdiv_int_var) and (NOT q2_var)) and q1_var); + q1_var := clkdiv_int_var; + clkdiv_int_var := mux; + end if; + end if; + + when others => + null; + end case; + + + end if; + + q1 <= q1_var after DELAY_FFBSC; + q2 <= q2_var after DELAY_FFBSC; + q3 <= q3_var after DELAY_FFBSC; + clkdiv_zd <= clkdiv_int_var after DELAY_FFBSC; + + end process prcs_div_2_8_cntr; +--#################################################################### +--##### Divider selections and 4:1 selector mux ##### +--#################################################################### + prcs_mux_sel:process(sel, c23 , c45 , c67 , clkdiv_zd , q1 , q2 , q3) + begin + case sel is + when "00" => + mux <= NOT (clkdiv_zd or (c23 and q1)) after DELAY_MXBSC; + when "01" => + mux <= NOT (q1 or (c45 and q2)) after DELAY_MXBSC; + when "10" => + mux <= NOT (q2 or (c67 and q3)) after DELAY_MXBSC; + when "11" => + mux <= NOT (q3) after DELAY_MXBSC; + when others => + mux <= NOT (clkdiv_zd or (c23 and q1)) after DELAY_MXBSC; + end case; + end process prcs_mux_sel; +--#################################################################### +--##### Bitslip control logic ##### +--#################################################################### + prcs_logictrl:process(qr1, clkdiv) + begin + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if(qr1 = '1') then + qlc1 <= '0' after DELAY_FFBSC; + qlc2 <= '0' after DELAY_FFBSC; + elsif(bitslip = '0') then + qlc1 <= qlc1 after DELAY_FFBSC; + qlc2 <= '0' after DELAY_FFBSC; + else + if(rising_edge(clkdiv)) then + qlc1 <= NOT qlc1 after DELAY_FFBSC; + qlc2 <= (bitslip and mux1) after DELAY_FFBSC; + end if; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(clkdiv)) then + if(qr1 = '1') then + qlc1 <= '0' after DELAY_FFBSC; + qlc2 <= '0' after DELAY_FFBSC; + elsif(bitslip = '0') then + qlc1 <= qlc1 after DELAY_FFBSC; + qlc2 <= '0' after DELAY_FFBSC; + else + qlc1 <= NOT qlc1 after DELAY_FFBSC; + qlc2 <= (bitslip and mux1) after DELAY_FFBSC; + end if; + end if; + when others => + null; + end case; + end process prcs_logictrl; + +--#################################################################### +--##### Mux to select between sdr "0" and ddr "1" ##### +--#################################################################### + prcs_sdr_ddr_mux:process(qlc1, DATA_RATE) + begin + case DATA_RATE is + when '0' => + mux1 <= qlc1 after DELAY_MXBSC; + when '1' => + mux1 <= '1' after DELAY_MXBSC; + when others => + null; + end case; + end process prcs_sdr_ddr_mux; + +--#################################################################### +--##### qhc1 and qhc2 ##### +--#################################################################### + prcs_qhc1_qhc2:process(qr2, CLK) + begin +-- FP TMP -- should CLK and q2 have to be rising_edge + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if(qr2 = '1') then + qhc1 <= '0' after DELAY_FFBSC; + qhc2 <= '0' after DELAY_FFBSC; + elsif(rising_edge(CLK)) then + qhc1 <= (qlc2 and (NOT qhc2)) after DELAY_FFBSC; + qhc2 <= qlc2 after DELAY_FFBSC; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(CLK)) then + if(qr2 = '1') then + qhc1 <= '0' after DELAY_FFBSC; + qhc2 <= '0' after DELAY_FFBSC; + else + qhc1 <= (qlc2 and (NOT qhc2)) after DELAY_FFBSC; + qhc2 <= qlc2 after DELAY_FFBSC; + end if; + end if; + + when others => + null; + end case; + + end process prcs_qhc1_qhc2; + +--#################################################################### +--##### Mux drives ctrl lines of mux in front of 2nd rnk FFs #### +--#################################################################### + prcs_muxc:process(mux1, DATA_RATE) + begin + case DATA_RATE is + when '0' => + muxc <= mux1 after DELAY_MXBSC; + when '1' => + muxc <= '0' after DELAY_MXBSC; + when others => + null; + end case; + end process prcs_muxc; + +--#################################################################### +--##### Asynchronous set flops ##### +--#################################################################### + prcs_qr1:process(R, CLKDIV) + begin +-- FP TMP -- should CLKDIV and R have to be rising_edge + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if(R = '1') then + qr1 <= '1' after DELAY_FFBSC; + elsif(rising_edge(CLKDIV)) then + qr1 <= '0' after DELAY_FFBSC; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(CLKDIV)) then + if(R = '1') then + qr1 <= '1' after DELAY_FFBSC; + else + qr1 <= '0' after DELAY_FFBSC; + end if; + end if; + + when others => + null; + end case; + end process prcs_qr1; +---------------------------------------------------------------------- + prcs_qr2:process(R, CLK) + begin +-- FP TMP -- should CLK and R have to be rising_edge + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if(R = '1') then + qr2 <= '1' after DELAY_FFBSC; + elsif(rising_edge(CLK)) then + qr2 <= qr1 after DELAY_FFBSC; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(CLK)) then + if(R = '1') then + qr2 <= '1' after DELAY_FFBSC; + else + qr2 <= qr1 after DELAY_FFBSC; + end if; + end if; + + when others => + null; + end case; + end process prcs_qr2; +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(clkdiv_zd) + begin + CLKDIV_INT <= clkdiv_zd; + end process prcs_output; +--#################################################################### +end bscntrl_V; + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_arith.all; + + +library unisim; +use unisim.vpkg.all; +use unisim.vcomponents.all; + +--//////////////////////////////////////////////////////////// +--//////////////////////// ICE MODULE //////////////////////// +--//////////////////////////////////////////////////////////// + +entity ice_module is + generic( + SRTYPE : string; + INIT_CE : bit_vector(1 downto 0) + ); + port( + ICE : out std_ulogic; + + CE1 : in std_ulogic; + CE2 : in std_ulogic; + GSR : in std_ulogic; + NUM_CE : in std_ulogic; + CLKDIV : in std_ulogic; + R : in std_ulogic + ); +end ice_module; + +architecture ice_V of ice_module is +-- constant DELAY_FFICE : time := 300 ns; +-- constant DELAY_MXICE : time := 60 ns; + constant DELAY_FFICE : time := 300 ps; + constant DELAY_MXICE : time := 60 ps; + + signal AttrSRtype : integer := 0; + + signal ce1r : std_ulogic := 'X'; + signal ce2r : std_ulogic := 'X'; + signal cesel : std_logic_vector(1 downto 0) := (others => 'X'); + + signal ice_zd : std_ulogic := 'X'; + +begin + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + begin + + if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then + AttrSrtype <= 0; + elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then + AttrSrtype <= 1; + end if; + + wait; + end process prcs_init; + +--################################################################### +--##### update cesel ##### +--################################################################### + + cesel <= NUM_CE & CLKDIV; + +--#################################################################### +--##### registers ##### +--#################################################################### + prcs_reg:process(CLKDIV, GSR) + variable ce1r_var : std_ulogic := TO_X01(INIT_CE(1)); + variable ce2r_var : std_ulogic := TO_X01(INIT_CE(0)); + begin + if(GSR = '1') then + ce1r_var := TO_X01(INIT_CE(1)); + ce2r_var := TO_X01(INIT_CE(0)); + elsif(GSR = '0') then + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if(R = '1') then + ce1r_var := '0'; + ce2r_var := '0'; + elsif(rising_edge(CLKDIV)) then + ce1r_var := ce1; + ce2r_var := ce2; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(CLKDIV)) then + if(R = '1') then + ce1r_var := '0'; + ce2r_var := '0'; + else + ce1r_var := ce1; + ce2r_var := ce2; + end if; + end if; + + when others => + null; + + end case; + end if; + + ce1r <= ce1r_var after DELAY_FFICE; + ce2r <= ce2r_var after DELAY_FFICE; + + end process prcs_reg; +--#################################################################### +--##### Output mux ##### +--#################################################################### + prcs_mux:process(cesel, ce1, ce1r, ce2r) + begin + case cesel is + when "00" => + ice_zd <= ce1; + when "01" => + ice_zd <= ce1; +-- 426606 + when "10" => + ice_zd <= ce2r; + when "11" => + ice_zd <= ce1r; + when others => + null; + end case; + end process prcs_mux; + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(ice_zd) + begin + ICE <= ice_zd; + end process prcs_output; +end ice_V; + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_arith.all; + + +library unisim; +use unisim.vpkg.all; +use unisim.vcomponents.all; +use unisim.vcomponents.all; + +----- CELL ISERDES ----- +--//////////////////////////////////////////////////////////// +--////////////////////////// ISERDES ///////////////////////// +--//////////////////////////////////////////////////////////// + +entity ISERDES is + + generic( + + DDR_CLK_EDGE : string := "SAME_EDGE_PIPELINED"; + INIT_BITSLIPCNT : bit_vector(3 downto 0) := "0000"; + INIT_CE : bit_vector(1 downto 0) := "00"; + INIT_RANK1_PARTIAL: bit_vector(4 downto 0) := "00000"; + INIT_RANK2 : bit_vector(5 downto 0) := "000000"; + INIT_RANK3 : bit_vector(5 downto 0) := "000000"; + SERDES : boolean := TRUE; + SRTYPE : string := "ASYNC"; + + BITSLIP_ENABLE : boolean := false; + DATA_RATE : string := "DDR"; + DATA_WIDTH : integer := 4; + INIT_Q1 : bit := '0'; + INIT_Q2 : bit := '0'; + INIT_Q3 : bit := '0'; + INIT_Q4 : bit := '0'; + INTERFACE_TYPE : string := "MEMORY"; + IOBDELAY : string := "NONE"; + IOBDELAY_TYPE : string := "DEFAULT"; + IOBDELAY_VALUE : integer := 0; + NUM_CE : integer := 2; + SERDES_MODE : string := "MASTER"; + SRVAL_Q1 : bit := '0'; + SRVAL_Q2 : bit := '0'; + SRVAL_Q3 : bit := '0'; + SRVAL_Q4 : bit := '0' + ); + + port( + O : out std_ulogic; + Q1 : out std_ulogic; + Q2 : out std_ulogic; + Q3 : out std_ulogic; + Q4 : out std_ulogic; + Q5 : out std_ulogic; + Q6 : out std_ulogic; + SHIFTOUT1 : out std_ulogic; + SHIFTOUT2 : out std_ulogic; + + BITSLIP : in std_ulogic; + CE1 : in std_ulogic; + CE2 : in std_ulogic; + CLK : in std_ulogic; + CLKDIV : in std_ulogic; + D : in std_ulogic; + DLYCE : in std_ulogic; + DLYINC : in std_ulogic; + DLYRST : in std_ulogic; + OCLK : in std_ulogic; + REV : in std_ulogic; + SHIFTIN1 : in std_ulogic; + SHIFTIN2 : in std_ulogic; + SR : in std_ulogic + ); + +end ISERDES; + +architecture ISERDES_V OF ISERDES is + +component bscntrl + generic ( + SRTYPE : string; + INIT_BITSLIPCNT : bit_vector(3 downto 0) + ); + port( + CLKDIV_INT : out std_ulogic; + MUXC : out std_ulogic; + + BITSLIP : in std_ulogic; + C23 : in std_ulogic; + C45 : in std_ulogic; + C67 : in std_ulogic; + CLK : in std_ulogic; + CLKDIV : in std_ulogic; + DATA_RATE : in std_ulogic; + GSR : in std_ulogic; + R : in std_ulogic; + SEL : in std_logic_vector (1 downto 0) + ); +end component; + +component ice_module + generic( + SRTYPE : string; + INIT_CE : bit_vector(1 downto 0) + ); + port( + ICE : out std_ulogic; + + CE1 : in std_ulogic; + CE2 : in std_ulogic; + GSR : in std_ulogic; + NUM_CE : in std_ulogic; + CLKDIV : in std_ulogic; + R : in std_ulogic + ); +end component; + +component IDELAY + generic( + IOBDELAY_VALUE : integer := 0; + IOBDELAY_TYPE : string := "DEFAULT" + ); + + port( + O : out std_ulogic; + + C : in std_ulogic; + CE : in std_ulogic; + + I : in std_ulogic; + INC : in std_ulogic; + RST : in std_ulogic + ); +end component; + +-- constant DELAY_FFINP : time := 300 ns; +-- constant DELAY_MXINP1 : time := 60 ns; +-- constant DELAY_MXINP2 : time := 120 ns; +-- constant DELAY_OCLKDLY : time := 750 ns; + + constant SYNC_PATH_DELAY : time := 100 ps; + + constant DELAY_FFINP : time := 300 ps; + constant DELAY_MXINP1 : time := 60 ps; + constant DELAY_MXINP2 : time := 120 ps; + constant DELAY_OCLKDLY : time := 750 ps; + + constant MAX_DATAWIDTH : integer := 4; + + signal BITSLIP_ipd : std_ulogic := 'X'; + signal CE1_ipd : std_ulogic := 'X'; + signal CE2_ipd : std_ulogic := 'X'; + signal CLK_ipd : std_ulogic := 'X'; + signal CLKDIV_ipd : std_ulogic := 'X'; + signal D_ipd : std_ulogic := 'X'; + signal DLYCE_ipd : std_ulogic := 'X'; + signal DLYINC_ipd : std_ulogic := 'X'; + signal DLYRST_ipd : std_ulogic := 'X'; + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := 'X'; + signal OCLK_ipd : std_ulogic := 'X'; + signal REV_ipd : std_ulogic := 'X'; + signal SR_ipd : std_ulogic := 'X'; + signal SHIFTIN1_ipd : std_ulogic := 'X'; + signal SHIFTIN2_ipd : std_ulogic := 'X'; + + signal BITSLIP_dly : std_ulogic := 'X'; + signal CE1_dly : std_ulogic := 'X'; + signal CE2_dly : std_ulogic := 'X'; + signal CLK_dly : std_ulogic := 'X'; + signal CLKDIV_dly : std_ulogic := 'X'; + signal D_dly : std_ulogic := 'X'; + signal DLYCE_dly : std_ulogic := 'X'; + signal DLYINC_dly : std_ulogic := 'X'; + signal DLYRST_dly : std_ulogic := 'X'; + signal GSR_dly : std_ulogic := 'X'; + signal OCLK_dly : std_ulogic := 'X'; + signal REV_dly : std_ulogic := 'X'; + signal SR_dly : std_ulogic := 'X'; + signal SHIFTIN1_dly : std_ulogic := 'X'; + signal SHIFTIN2_dly : std_ulogic := 'X'; + + + signal O_zd : std_ulogic := 'X'; + signal Q1_zd : std_ulogic := 'X'; + signal Q2_zd : std_ulogic := 'X'; + signal Q3_zd : std_ulogic := 'X'; + signal Q4_zd : std_ulogic := 'X'; + signal Q5_zd : std_ulogic := 'X'; + signal Q6_zd : std_ulogic := 'X'; + signal SHIFTOUT1_zd : std_ulogic := 'X'; + signal SHIFTOUT2_zd : std_ulogic := 'X'; + + signal O_viol : std_ulogic := 'X'; + signal Q1_viol : std_ulogic := 'X'; + signal Q2_viol : std_ulogic := 'X'; + signal Q3_viol : std_ulogic := 'X'; + signal Q4_viol : std_ulogic := 'X'; + signal Q5_viol : std_ulogic := 'X'; + signal Q6_viol : std_ulogic := 'X'; + signal SHIFTOUT1_viol : std_ulogic := 'X'; + signal SHIFTOUT2_viol : std_ulogic := 'X'; + + signal AttrSerdes : std_ulogic := 'X'; + signal AttrMode : std_ulogic := 'X'; + signal AttrDataRate : std_ulogic := 'X'; + signal AttrDataWidth : std_logic_vector(3 downto 0) := (others => 'X'); + signal AttrInterfaceType : std_ulogic := 'X'; + signal AttrBitslipEnable : std_ulogic := 'X'; + signal AttrNumCe : std_ulogic := 'X'; + signal AttrDdrClkEdge : std_logic_vector(1 downto 0) := (others => 'X'); + signal AttrSRtype : integer := 0; + signal AttrIobDelay : integer := 0; + + signal sel1 : std_logic_vector(1 downto 0) := (others => 'X'); + signal selrnk3 : std_logic_vector(3 downto 0) := (others => 'X'); + signal bsmux : std_logic_vector(2 downto 0) := (others => 'X'); + signal cntr : std_logic_vector(4 downto 0) := (others => 'X'); + + signal q1rnk1 : std_ulogic := 'X'; + signal q2nrnk1 : std_ulogic := 'X'; + signal q5rnk1 : std_ulogic := 'X'; + signal q6rnk1 : std_ulogic := 'X'; + signal q6prnk1 : std_ulogic := 'X'; + + signal q1prnk1 : std_ulogic := 'X'; + signal q2prnk1 : std_ulogic := 'X'; + signal q3rnk1 : std_ulogic := 'X'; + signal q4rnk1 : std_ulogic := 'X'; + + signal dataq5rnk1 : std_ulogic := 'X'; + signal dataq6rnk1 : std_ulogic := 'X'; + + signal dataq3rnk1 : std_ulogic := 'X'; + signal dataq4rnk1 : std_ulogic := 'X'; + + signal oclkmux : std_ulogic := '0'; + signal memmux : std_ulogic := '0'; + signal q2pmux : std_ulogic := '0'; + + signal clkdiv_int : std_ulogic := '0'; + signal clkdivmux : std_ulogic := '0'; + + signal q1rnk2 : std_ulogic := 'X'; + signal q2rnk2 : std_ulogic := 'X'; + signal q3rnk2 : std_ulogic := 'X'; + signal q4rnk2 : std_ulogic := 'X'; + signal q5rnk2 : std_ulogic := 'X'; + signal q6rnk2 : std_ulogic := 'X'; + signal dataq1rnk2 : std_ulogic := 'X'; + signal dataq2rnk2 : std_ulogic := 'X'; + signal dataq3rnk2 : std_ulogic := 'X'; + signal dataq4rnk2 : std_ulogic := 'X'; + signal dataq5rnk2 : std_ulogic := 'X'; + signal dataq6rnk2 : std_ulogic := 'X'; + + signal muxc : std_ulogic := 'X'; + + signal q1rnk3 : std_ulogic := 'X'; + signal q2rnk3 : std_ulogic := 'X'; + signal q3rnk3 : std_ulogic := 'X'; + signal q4rnk3 : std_ulogic := 'X'; + signal q5rnk3 : std_ulogic := 'X'; + signal q6rnk3 : std_ulogic := 'X'; + + signal c23 : std_ulogic := 'X'; + signal c45 : std_ulogic := 'X'; + signal c67 : std_ulogic := 'X'; + signal sel : std_logic_vector(1 downto 0) := (others => 'X'); + + signal ice : std_ulogic := 'X'; + signal datain : std_ulogic := 'X'; + signal idelay_out : std_ulogic := 'X'; + + signal CLKN_dly : std_ulogic := '0'; + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + BITSLIP_dly <= BITSLIP after 0 ps; + CE1_dly <= CE1 after 0 ps; + CE2_dly <= CE2 after 0 ps; + CLK_dly <= CLK after 0 ps; + CLKDIV_dly <= CLKDIV after 0 ps; + D_dly <= D after 0 ps; + DLYCE_dly <= DLYCE after 0 ps; + DLYINC_dly <= DLYINC after 0 ps; + DLYRST_dly <= DLYRST after 0 ps; + GSR_dly <= GSR after 0 ps; + OCLK_dly <= OCLK after 0 ps; + REV_dly <= REV after 0 ps; + SHIFTIN1_dly <= SHIFTIN1 after 0 ps; + SHIFTIN2_dly <= SHIFTIN2 after 0 ps; + SR_dly <= SR after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + variable AttrSerdes_var : std_ulogic := 'X'; + variable AttrMode_var : std_ulogic := 'X'; + variable AttrDataRate_var : std_ulogic := 'X'; + variable AttrDataWidth_var : std_logic_vector(3 downto 0) := (others => 'X'); + variable AttrInterfaceType_var : std_ulogic := 'X'; + variable AttrBitslipEnable_var : std_ulogic := 'X'; + variable AttrDdrClkEdge_var : std_logic_vector(1 downto 0) := (others => 'X'); + variable AttrIobDelay_var : integer := 0; + + begin + + --------CR 447760 DRC -- BITSLIP - INTERFACE_TYPE combination ------------------ + + if((INTERFACE_TYPE = "MEMORY") and (BITSLIP_ENABLE = TRUE)) then + assert false + report "Attribute Syntax Error: BITSLIP_ENABLE is currently set to TRUE when INTERFACE_TYPE is set to MEMORY. This is an invalid configuration." + severity Failure; + elsif((INTERFACE_TYPE = "NETWORKING") and (BITSLIP_ENABLE = FALSE)) then + assert false + report "Attribute Syntax Error: BITSLIP_ENABLE is currently set to FALSE when INTERFACE_TYPE is set to NETWORKING. If BITSLIP is not intended to be used, please set BITSLIP_ENABLE to TRUE and tie the BITSLIP port to ground." + severity Failure; + end if; + + -------------------- SERDES validity check -------------------- + if(SERDES = true) then + AttrSerdes_var := '1'; + else + AttrSerdes_var := '0'; + end if; + + ------------- SERDES_MODE validity check -------------------- + if((SERDES_MODE = "MASTER") or (SERDES_MODE = "master")) then + AttrMode_var := '0'; + elsif((SERDES_MODE = "SLAVE") or (SERDES_MODE = "slave")) then + AttrMode_var := '1'; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => "SERDES_MODE ", + EntityName => "/ISERDES", + GenericValue => SERDES_MODE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " MASTER or SLAVE.", + TailMsg => "", + MsgSeverity => FAILURE + ); + end if; + + ------------------ DATA_RATE validity check ------------------ + if((DATA_RATE = "DDR") or (DATA_RATE = "ddr")) then + AttrDataRate_var := '0'; + elsif((DATA_RATE = "SDR") or (DATA_RATE = "sdr")) then + AttrDataRate_var := '1'; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DATA_RATE ", + EntityName => "/ISERDES", + GenericValue => DATA_RATE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " DDR or SDR. ", + TailMsg => "", + MsgSeverity => Failure + ); + end if; + + ------------------ DATA_WIDTH validity check ------------------ + if((DATA_WIDTH = 2) or (DATA_WIDTH = 3) or (DATA_WIDTH = 4) or + (DATA_WIDTH = 5) or (DATA_WIDTH = 6) or (DATA_WIDTH = 7) or + (DATA_WIDTH = 8) or (DATA_WIDTH = 10)) then + AttrDataWidth_var := CONV_STD_LOGIC_VECTOR(DATA_WIDTH, MAX_DATAWIDTH); + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DATA_WIDTH ", + EntityName => "/ISERDES", + GenericValue => DATA_WIDTH, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 2, 3, 4, 5, 6, 7, 8, or 10 ", + TailMsg => "", + MsgSeverity => Failure + ); + end if; + ------------ DATA_WIDTH /DATA_RATE combination check ------------ + if((DATA_RATE = "DDR") or (DATA_RATE = "ddr")) then + case (DATA_WIDTH) is + when 4|6|8|10 => null; + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DATA_WIDTH ", + EntityName => "/ISERDES", + GenericValue => DATA_WIDTH, + Unit => "", + ExpectedValueMsg => " The Legal values for DDR mode are ", + ExpectedGenericValue => " 4, 6, 8, or 10 ", + TailMsg => "", + MsgSeverity => Failure + ); + end case; + end if; + + if((DATA_RATE = "SDR") or (DATA_RATE = "sdr")) then + case (DATA_WIDTH) is + when 2|3|4|5|6|7|8 => null; + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DATA_WIDTH ", + EntityName => "/ISERDES", + GenericValue => DATA_WIDTH, + Unit => "", + ExpectedValueMsg => " The Legal values for SDR mode are ", + ExpectedGenericValue => " 2, 3, 4, 5, 6, 7 or 8", + TailMsg => "", + MsgSeverity => Failure + ); + end case; + end if; + ---------------- INTERFACE_TYPE validity check --------------- + if((INTERFACE_TYPE = "MEMORY") or (INTERFACE_TYPE = "memory")) then + AttrInterfaceType_var := '0'; + elsif((INTERFACE_TYPE = "NETWORKING") or (INTERFACE_TYPE = "networking")) then + AttrInterfaceType_var := '1'; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => "INTERFACE_TYPE ", + EntityName => "/ISERDES", + GenericValue => INTERFACE_TYPE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " MEMORY or NETWORKING.", + TailMsg => "", + MsgSeverity => FAILURE + ); + end if; + + ---------------- BITSLIP_ENABLE validity check ------------------- + if(BITSLIP_ENABLE = false) then + AttrBitslipEnable_var := '0'; + elsif(BITSLIP_ENABLE = true) then + AttrBitslipEnable_var := '1'; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " BITSLIP_ENABLE ", + EntityName => "/ISERDES", + GenericValue => BITSLIP_ENABLE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " TRUE or FALSE ", + TailMsg => "", + MsgSeverity => Failure + ); + end if; + + ---------------- NUM_CE validity check ------------------- + case NUM_CE is + when 1 => + AttrNumCe <= '0'; + when 2 => + AttrNumCe <= '1'; + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " NUM_CE ", + EntityName => "/ISERDES", + GenericValue => NUM_CE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 1 or 2 ", + TailMsg => "", + MsgSeverity => Failure + ); + end case; + ---------------- IOBDELAY validity check ------------------- + if((IOBDELAY = "NONE") or (IOBDELAY = "none")) then + AttrIobDelay_var := 0; + elsif((IOBDELAY = "IBUF") or (IOBDELAY = "ibuf")) then + AttrIobDelay_var := 1; + elsif((IOBDELAY = "IFD") or (IOBDELAY = "ifd")) then + AttrIobDelay_var := 2; + elsif((IOBDELAY = "BOTH") or (IOBDELAY = "both")) then + AttrIobDelay_var := 3; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " IOBDELAY ", + EntityName => "/ISERDES", + GenericValue => IOBDELAY, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " NONE or IBUF or IFD or BOTH ", + TailMsg => "", + MsgSeverity => Failure + ); + end if; + ------------ IOBDELAY_VALUE validity check ----------------- + ------------ IOBDELAY_TYPE validity check ----------------- +-- +-- +-- + ------------------ DDR_CLK_EDGE validity check ------------------ + if((DDR_CLK_EDGE = "SAME_EDGE_PIPELINED") or (DDR_CLK_EDGE = "same_edge_pipelined")) then + AttrDdrClkEdge_var := "00"; + elsif((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then + AttrDdrClkEdge_var := "01"; + elsif((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then + AttrDdrClkEdge_var := "10"; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DDR_CLK_EDGE ", + EntityName => "/ISERDES", + GenericValue => DDR_CLK_EDGE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " SAME_EDGE_PIPELINED or SAME_EDGE or OPPOSITE_EDGE ", + TailMsg => "", + MsgSeverity => Failure + ); + end if; + ------------------ DATA_RATE validity check ------------------ + if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then + AttrSrtype <= 0; + elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then + AttrSrtype <= 1; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRTYPE ", + EntityName => "/ISERDES", + GenericValue => SRTYPE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " ASYNC or SYNC. ", + TailMsg => "", + MsgSeverity => ERROR + ); + end if; +--------------------------------------------------------------------- + + AttrSerdes <= AttrSerdes_var; + AttrMode <= AttrMode_var; + AttrDataRate <= AttrDataRate_var; + AttrDataWidth <= AttrDataWidth_var; + AttrInterfaceType <= AttrInterfaceType_var; + AttrBitslipEnable <= AttrBitslipEnable_var; + AttrDdrClkEdge <= AttrDdrClkEdge_var; + AttrIobDelay <= AttrIobDelay_var; + + sel1 <= AttrMode_var & AttrDataRate_var; + selrnk3 <= AttrSerdes_var & AttrBitslipEnable_var & AttrDdrClkEdge_var; + cntr <= AttrDataRate_var & AttrDataWidth_var; + + wait; + end process prcs_init; + +--################################################################### +--##### SHIFTOUT1 and SHIFTOUT2 ##### +--################################################################### + + SHIFTOUT2_zd <= q5rnk1; + SHIFTOUT1_zd <= q6rnk1; + +--################################################################### +--##### q1rnk1 reg ##### +--################################################################### + prcs_Q1_rnk1:process(CLK_dly, GSR_dly, REV_dly, SR_dly) + variable q1rnk1_var : std_ulogic := TO_X01(INIT_Q1); + begin + if(GSR_dly = '1') then + q1rnk1_var := TO_X01(INIT_Q1); + elsif(GSR_dly = '0') then + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q1) = '1')))) then + q1rnk1_var := TO_X01(SRVAL_Q1); + elsif(REV_dly = '1') then + q1rnk1_var := not TO_X01(SRVAL_Q1); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(ice = '1') then + if(rising_edge(CLK_dly)) then + q1rnk1_var := datain; + end if; + end if; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(CLK_dly)) then + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q1) = '1')))) then + q1rnk1_var := TO_X01(SRVAL_Q1); + Elsif(REV_dly = '1') then + q1rnk1_var := not TO_X01(SRVAL_Q1); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(ice = '1') then + q1rnk1_var := datain; + end if; + end if; + end if; + + when others => + null; + + end case; + end if; + + q1rnk1 <= q1rnk1_var after DELAY_FFINP; + + end process prcs_Q1_rnk1; +--################################################################### +--##### q5rnk1, q6rnk1 and q6prnk1 reg ##### +--################################################################### + prcs_Q5Q6Q6p_rnk1:process(CLK_dly, GSR_dly, SR_dly) + variable q5rnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(2)); + variable q6rnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(1)); + variable q6prnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(0)); + begin + if(GSR_dly = '1') then + q5rnk1_var := TO_X01(INIT_RANK1_PARTIAL(2)); + q6rnk1_var := TO_X01(INIT_RANK1_PARTIAL(1)); + q6prnk1_var := TO_X01(INIT_RANK1_PARTIAL(0)); + elsif(GSR_dly = '0') then + case AttrSRtype is + when 0 => + --------- // async SET/RESET -- Not full featured FFs + if(SR_dly = '1') then + q5rnk1_var := '0'; + q6rnk1_var := '0'; + q6prnk1_var := '0'; + elsif(SR_dly = '0') then + if(rising_edge(CLK_dly)) then + q5rnk1_var := dataq5rnk1; + q6rnk1_var := dataq6rnk1; + q6prnk1_var := q6rnk1; + end if; + end if; + + when 1 => + --------- // sync SET/RESET -- Not full featured FFs + if(rising_edge(CLK_dly)) then + if(SR_dly = '1') then + q5rnk1_var := '0'; + q6rnk1_var := '0'; + q6prnk1_var := '0'; + elsif(SR_dly = '0') then + q5rnk1_var := dataq5rnk1; + q6rnk1_var := dataq6rnk1; + q6prnk1_var := q6rnk1; + end if; + end if; + + when others => + null; + + end case; + end if; + + q5rnk1 <= q5rnk1_var after DELAY_FFINP; + q6rnk1 <= q6rnk1_var after DELAY_FFINP; + q6prnk1 <= q6prnk1_var after DELAY_FFINP; + + end process prcs_Q5Q6Q6p_rnk1; +--################################################################### +--##### q2nrnk1 reg ##### +--################################################################### + prcs_Q2_rnk1:process(CLK_dly, GSR_dly, SR_dly, REV_dly) + variable q2nrnk1_var : std_ulogic := TO_X01(INIT_Q2); + begin + if(GSR_dly = '1') then + q2nrnk1_var := TO_X01(INIT_Q2); + elsif(GSR_dly = '0') then + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q2) = '1')))) then + q2nrnk1_var := TO_X01(SRVAL_Q2); + elsif(REV_dly = '1') then + q2nrnk1_var := not TO_X01(SRVAL_Q2); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(ice = '1') then + if(falling_edge(CLK_dly)) then + q2nrnk1_var := datain; + end if; + end if; + end if; + + when 1 => + --------------- // sync SET/RESET + if(falling_edge(CLK_dly)) then + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q2) = '1')))) then + q2nrnk1_var := TO_X01(SRVAL_Q2); + elsif(REV_dly = '1') then + q2nrnk1_var := not TO_X01(SRVAL_Q2); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(ice = '1') then + q2nrnk1_var := datain; + end if; + end if; + end if; + + when others => + null; + + end case; + end if; + + q2nrnk1 <= q2nrnk1_var after DELAY_FFINP; + + end process prcs_Q2_rnk1; +--################################################################### +--##### q2prnk1 reg ##### +--################################################################### + prcs_Q2p_rnk1:process(q2pmux, GSR_dly, REV_dly, SR_dly) + variable q2prnk1_var : std_ulogic := TO_X01(INIT_Q4); + begin + if(GSR_dly = '1') then + q2prnk1_var := TO_X01(INIT_Q4); + elsif(GSR_dly = '0') then + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q4) = '1')))) then + q2prnk1_var := TO_X01(SRVAL_Q4); + elsif(REV_dly = '1') then + q2prnk1_var := not TO_X01(SRVAL_Q4); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(ice = '1') then + if(rising_edge(q2pmux)) then + q2prnk1_var := q2nrnk1; + end if; + end if; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(q2pmux)) then + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q4) = '1')))) then + q2prnk1_var := TO_X01(SRVAL_Q4); + elsif(REV_dly = '1') then + q2prnk1_var := not TO_X01(SRVAL_Q4); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(ice = '1') then + q2prnk1_var := q2nrnk1; + end if; + end if; + end if; + + when others => + null; + + end case; + end if; + + q2prnk1 <= q2prnk1_var after DELAY_FFINP; + + end process prcs_Q2p_rnk1; +--################################################################### +--##### q1prnk1 reg ##### +--################################################################### + prcs_Q1p_rnk1:process(memmux, GSR_dly, REV_dly, SR_dly) + variable q1prnk1_var : std_ulogic := TO_X01(INIT_Q3); + begin + if(GSR_dly = '1') then + q1prnk1_var := TO_X01(INIT_Q3); + elsif(GSR_dly = '0') then + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q3) = '1')))) then + q1prnk1_var := TO_X01(SRVAL_Q3); + elsif(REV_dly = '1') then + q1prnk1_var := not TO_X01(SRVAL_Q3); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(ice = '1') then + if(rising_edge(memmux)) then + q1prnk1_var := q1rnk1; + end if; + end if; + end if; + + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(memmux)) then + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q3) = '1')))) then + q1prnk1_var := TO_X01(SRVAL_Q3); + elsif(REV_dly = '1') then + q1prnk1_var := not TO_X01(SRVAL_Q3); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(ice = '1') then + q1prnk1_var := q1rnk1; + end if; + end if; + end if; + + when others => + null; + + end case; + end if; + + q1prnk1 <= q1prnk1_var after DELAY_FFINP; + + end process prcs_Q1p_rnk1; +--################################################################### +--##### q3rnk1 and q4rnk1 reg ##### +--################################################################### + prcs_Q3Q4_rnk1:process(memmux, GSR_dly, SR_dly) + variable q3rnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(4)); + variable q4rnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(3)); + begin + if(GSR_dly = '1') then + q3rnk1_var := TO_X01(INIT_RANK1_PARTIAL(4)); + q4rnk1_var := TO_X01(INIT_RANK1_PARTIAL(3)); + elsif(GSR_dly = '0') then + case AttrSRtype is + when 0 => + -------- // async SET/RESET -- not fully featured FFs + if(SR_dly = '1') then + q3rnk1_var := '0'; + q4rnk1_var := '0'; + elsif(SR_dly = '0') then + if(rising_edge(memmux)) then + q3rnk1_var := dataq3rnk1; + q4rnk1_var := dataq4rnk1; + end if; + end if; + + when 1 => + -------- // sync SET/RESET -- not fully featured FFs + if(rising_edge(memmux)) then + if(SR_dly = '1') then + q3rnk1_var := '0'; + q4rnk1_var := '0'; + elsif(SR_dly = '0') then + q3rnk1_var := dataq3rnk1; + q4rnk1_var := dataq4rnk1; + end if; + end if; + + when others => + null; + + end case; + end if; + + q3rnk1 <= q3rnk1_var after DELAY_FFINP; + q4rnk1 <= q4rnk1_var after DELAY_FFINP; + + end process prcs_Q3Q4_rnk1; +--################################################################### +--##### clock mux -- oclkmux with delay element ##### +--################################################################### +-- prcs_oclkmux:process(OCLK_dly) +-- begin +-- case AttrOclkDelay is +-- when '0' => +-- oclkmux <= OCLK_dly after DELAY_MXINP1; +-- when '1' => +-- oclkmux <= OCLK_dly after DELAY_OCLKDLY; +-- when others => +-- oclkmux <= OCLK_dly after DELAY_MXINP1; +-- end case; +-- end process prcs_oclkmux; +-- +-- +-- +--/////////////////////////////////////////////////////////////////// +--// Mux elements for the 1st Rank +--/////////////////////////////////////////////////////////////////// +--################################################################### +--##### memmux -- 4 clock muxes in first rank ##### +--################################################################### + prcs_memmux:process(CLK_dly, OCLK_dly) + begin + case AttrInterfaceType is + when '0' => + memmux <= OCLK_dly after DELAY_MXINP1; + when '1' => + memmux <= CLK_dly after DELAY_MXINP1; + when others => + memmux <= OCLK_dly after DELAY_MXINP1; + end case; + end process prcs_memmux; + +--################################################################### +--##### q2pmux -- Optional inverter for q2p (4th flop in rank1) +--################################################################### + prcs_q2pmux:process(memmux) + begin + case AttrInterfaceType is + when '0' => + q2pmux <= not memmux after DELAY_MXINP1; + when '1' => + q2pmux <= memmux after DELAY_MXINP1; + when others => + q2pmux <= memmux after DELAY_MXINP1; + end case; + end process prcs_q2pmux; +--################################################################### +--##### data input muxes for q3q4 and q5q6 ##### +--################################################################### + prcs_Q3Q4_mux:process(q1prnk1, q2prnk1, q3rnk1, SHIFTIN1_dly, SHIFTIN2_dly) + begin + case sel1 is + when "00" => + dataq3rnk1 <= q1prnk1 after DELAY_MXINP1; + dataq4rnk1 <= q2prnk1 after DELAY_MXINP1; + when "01" => + dataq3rnk1 <= q1prnk1 after DELAY_MXINP1; + dataq4rnk1 <= q3rnk1 after DELAY_MXINP1; + when "10" => + dataq3rnk1 <= SHIFTIN2_dly after DELAY_MXINP1; + dataq4rnk1 <= SHIFTIN1_dly after DELAY_MXINP1; + when "11" => + dataq3rnk1 <= SHIFTIN1_dly after DELAY_MXINP1; + dataq4rnk1 <= q3rnk1 after DELAY_MXINP1; + when others => + dataq3rnk1 <= q1prnk1 after DELAY_MXINP1; + dataq4rnk1 <= q2prnk1 after DELAY_MXINP1; + end case; + + end process prcs_Q3Q4_mux; +---------------------------------------------------------------------- + prcs_Q5Q6_mux:process(q3rnk1, q4rnk1, q5rnk1) + begin + case AttrDataRate is + when '0' => + dataq5rnk1 <= q3rnk1 after DELAY_MXINP1; + dataq6rnk1 <= q4rnk1 after DELAY_MXINP1; + when '1' => + dataq5rnk1 <= q4rnk1 after DELAY_MXINP1; + dataq6rnk1 <= q5rnk1 after DELAY_MXINP1; + when others => + dataq5rnk1 <= q4rnk1 after DELAY_MXINP1; + dataq6rnk1 <= q5rnk1 after DELAY_MXINP1; + end case; + end process prcs_Q5Q6_mux; + + + +---//////////////////////////////////////////////////////////////////// +--- 2nd rank of registors +---//////////////////////////////////////////////////////////////////// + +--################################################################### +--##### clkdivmux to choose between clkdiv_int or CLKDIV ##### +--################################################################### + prcs_clkdivmux:process(clkdiv_int, CLKDIV_dly) + begin + case AttrBitslipEnable is + when '0' => + clkdivmux <= CLKDIV_dly after DELAY_MXINP1; + when '1' => + clkdivmux <= clkdiv_int after DELAY_MXINP1; + when others => + clkdivmux <= CLKDIV_dly after DELAY_MXINP1; + end case; + end process prcs_clkdivmux; + +--################################################################### +--##### q1rnk2, q2rnk2, q3rnk2,q4rnk2 ,q5rnk2 and q6rnk2 reg ##### +--################################################################### + prcs_Q1Q2Q3Q4Q5Q6_rnk2:process(clkdivmux, GSR_dly, SR_dly) + variable q1rnk2_var : std_ulogic := TO_X01(INIT_RANK2(0)); + variable q2rnk2_var : std_ulogic := TO_X01(INIT_RANK2(1)); + variable q3rnk2_var : std_ulogic := TO_X01(INIT_RANK2(2)); + variable q4rnk2_var : std_ulogic := TO_X01(INIT_RANK2(3)); + variable q5rnk2_var : std_ulogic := TO_X01(INIT_RANK2(4)); + variable q6rnk2_var : std_ulogic := TO_X01(INIT_RANK2(5)); + begin + if(GSR_dly = '1') then + q1rnk2_var := TO_X01(INIT_RANK2(0)); + q2rnk2_var := TO_X01(INIT_RANK2(1)); + q3rnk2_var := TO_X01(INIT_RANK2(2)); + q4rnk2_var := TO_X01(INIT_RANK2(3)); + q5rnk2_var := TO_X01(INIT_RANK2(4)); + q6rnk2_var := TO_X01(INIT_RANK2(5)); + elsif(GSR_dly = '0') then + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if(SR_dly = '1') then + q1rnk2_var := '0'; + q2rnk2_var := '0'; + q3rnk2_var := '0'; + q4rnk2_var := '0'; + q5rnk2_var := '0'; + q6rnk2_var := '0'; + elsif(SR_dly = '0') then + if(rising_edge(clkdivmux)) then + q1rnk2_var := dataq1rnk2; + q2rnk2_var := dataq2rnk2; + q3rnk2_var := dataq3rnk2; + q4rnk2_var := dataq4rnk2; + q5rnk2_var := dataq5rnk2; + q6rnk2_var := dataq6rnk2; + end if; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(clkdivmux)) then + if(SR_dly = '1') then + q1rnk2_var := '0'; + q2rnk2_var := '0'; + q3rnk2_var := '0'; + q4rnk2_var := '0'; + q5rnk2_var := '0'; + q6rnk2_var := '0'; + elsif(SR_dly = '0') then + q1rnk2_var := dataq1rnk2; + q2rnk2_var := dataq2rnk2; + q3rnk2_var := dataq3rnk2; + q4rnk2_var := dataq4rnk2; + q5rnk2_var := dataq5rnk2; + q6rnk2_var := dataq6rnk2; + end if; + end if; + when others => + null; + end case; + end if; + + q1rnk2 <= q1rnk2_var after DELAY_FFINP; + q2rnk2 <= q2rnk2_var after DELAY_FFINP; + q3rnk2 <= q3rnk2_var after DELAY_FFINP; + q4rnk2 <= q4rnk2_var after DELAY_FFINP; + q5rnk2 <= q5rnk2_var after DELAY_FFINP; + q6rnk2 <= q6rnk2_var after DELAY_FFINP; + + end process prcs_Q1Q2Q3Q4Q5Q6_rnk2; + +--################################################################### +--##### update bitslip mux ##### +--################################################################### + + bsmux <= AttrBitslipEnable & AttrDataRate & muxc; + +--################################################################### +--##### Data mux for 2nd rank of registers ###### +--################################################################### + prcs_Q1Q2Q3Q4Q5Q6_rnk2_mux:process(bsmux, q1rnk1, q1prnk1, q2prnk1, + q3rnk1, q4rnk1, q5rnk1, q6rnk1, q6prnk1) + begin + case bsmux is + when "000" | "001" => + dataq1rnk2 <= q2prnk1 after DELAY_MXINP2; + dataq2rnk2 <= q1prnk1 after DELAY_MXINP2; + dataq3rnk2 <= q4rnk1 after DELAY_MXINP2; + dataq4rnk2 <= q3rnk1 after DELAY_MXINP2; + dataq5rnk2 <= q6rnk1 after DELAY_MXINP2; + dataq6rnk2 <= q5rnk1 after DELAY_MXINP2; + when "100" => + dataq1rnk2 <= q2prnk1 after DELAY_MXINP2; + dataq2rnk2 <= q1prnk1 after DELAY_MXINP2; + dataq3rnk2 <= q4rnk1 after DELAY_MXINP2; + dataq4rnk2 <= q3rnk1 after DELAY_MXINP2; + dataq5rnk2 <= q6rnk1 after DELAY_MXINP2; + dataq6rnk2 <= q5rnk1 after DELAY_MXINP2; + when "101" => + dataq1rnk2 <= q1prnk1 after DELAY_MXINP2; + dataq2rnk2 <= q4rnk1 after DELAY_MXINP2; + dataq3rnk2 <= q3rnk1 after DELAY_MXINP2; + dataq4rnk2 <= q6rnk1 after DELAY_MXINP2; + dataq5rnk2 <= q5rnk1 after DELAY_MXINP2; + dataq6rnk2 <= q6prnk1 after DELAY_MXINP2; + when "010" | "011" | "110" | "111" => + dataq1rnk2 <= q1rnk1 after DELAY_MXINP2; + dataq2rnk2 <= q1prnk1 after DELAY_MXINP2; + dataq3rnk2 <= q3rnk1 after DELAY_MXINP2; + dataq4rnk2 <= q4rnk1 after DELAY_MXINP2; + dataq5rnk2 <= q5rnk1 after DELAY_MXINP2; + dataq6rnk2 <= q6rnk1 after DELAY_MXINP2; + when others => + dataq1rnk2 <= q2prnk1 after DELAY_MXINP2; + dataq2rnk2 <= q1prnk1 after DELAY_MXINP2; + dataq3rnk2 <= q4rnk1 after DELAY_MXINP2; + dataq4rnk2 <= q3rnk1 after DELAY_MXINP2; + dataq5rnk2 <= q6rnk1 after DELAY_MXINP2; + dataq6rnk2 <= q5rnk1 after DELAY_MXINP2; + end case; + end process prcs_Q1Q2Q3Q4Q5Q6_rnk2_mux; + +---//////////////////////////////////////////////////////////////////// +--- 3rd rank of registors +---//////////////////////////////////////////////////////////////////// + +--################################################################### +--##### q1rnk3, q2rnk3, q3rnk3, q4rnk3, q5rnk3 and q6rnk3 reg ##### +--################################################################### + prcs_Q1Q2Q3Q4Q5Q6_rnk3:process(CLKDIV_dly, GSR_dly, SR_dly) + variable q1rnk3_var : std_ulogic := TO_X01(INIT_RANK3(0)); + variable q2rnk3_var : std_ulogic := TO_X01(INIT_RANK3(1)); + variable q3rnk3_var : std_ulogic := TO_X01(INIT_RANK3(2)); + variable q4rnk3_var : std_ulogic := TO_X01(INIT_RANK3(3)); + variable q5rnk3_var : std_ulogic := TO_X01(INIT_RANK3(4)); + variable q6rnk3_var : std_ulogic := TO_X01(INIT_RANK3(5)); + begin + if(GSR_dly = '1') then + q1rnk3_var := TO_X01(INIT_RANK3(0)); + q2rnk3_var := TO_X01(INIT_RANK3(1)); + q3rnk3_var := TO_X01(INIT_RANK3(2)); + q4rnk3_var := TO_X01(INIT_RANK3(3)); + q5rnk3_var := TO_X01(INIT_RANK3(4)); + q6rnk3_var := TO_X01(INIT_RANK3(5)); + elsif(GSR_dly = '0') then + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if(SR_dly = '1') then + q1rnk3_var := '0'; + q2rnk3_var := '0'; + q3rnk3_var := '0'; + q4rnk3_var := '0'; + q5rnk3_var := '0'; + q6rnk3_var := '0'; + elsif(SR_dly = '0') then + if(rising_edge(CLKDIV_dly)) then + q1rnk3_var := q1rnk2; + q2rnk3_var := q2rnk2; + q3rnk3_var := q3rnk2; + q4rnk3_var := q4rnk2; + q5rnk3_var := q5rnk2; + q6rnk3_var := q6rnk2; + end if; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(CLKDIV_dly)) then + if(SR_dly = '1') then + q1rnk3_var := '0'; + q2rnk3_var := '0'; + q3rnk3_var := '0'; + q4rnk3_var := '0'; + q5rnk3_var := '0'; + q6rnk3_var := '0'; + elsif(SR_dly = '0') then + q1rnk3_var := q1rnk2; + q2rnk3_var := q2rnk2; + q3rnk3_var := q3rnk2; + q4rnk3_var := q4rnk2; + q5rnk3_var := q5rnk2; + q6rnk3_var := q6rnk2; + end if; + end if; + when others => + null; + end case; + end if; + + q1rnk3 <= q1rnk3_var after DELAY_FFINP; + q2rnk3 <= q2rnk3_var after DELAY_FFINP; + q3rnk3 <= q3rnk3_var after DELAY_FFINP; + q4rnk3 <= q4rnk3_var after DELAY_FFINP; + q5rnk3 <= q5rnk3_var after DELAY_FFINP; + q6rnk3 <= q6rnk3_var after DELAY_FFINP; + + end process prcs_Q1Q2Q3Q4Q5Q6_rnk3; + +---//////////////////////////////////////////////////////////////////// +--- Outputs +---//////////////////////////////////////////////////////////////////// + prcs_Q1Q2_rnk3_mux:process(q1rnk1, q1prnk1, q1rnk2, q1rnk3, + q2nrnk1, q2prnk1, q2rnk2, q2rnk3) + begin + case selrnk3 is + when "0000" | "0100" | "0X00" => + Q1_zd <= q1prnk1 after DELAY_MXINP1; + Q2_zd <= q2prnk1 after DELAY_MXINP1; + when "0001" | "0101" | "0X01" => + Q1_zd <= q1rnk1 after DELAY_MXINP1; + Q2_zd <= q2prnk1 after DELAY_MXINP1; + when "0010" | "0110" | "0X10" => + Q1_zd <= q1rnk1 after DELAY_MXINP1; + Q2_zd <= q2nrnk1 after DELAY_MXINP1; + when "1000" | "1001" | "1010" | "1011" | "10X0" | "10X1" | + "100X" | "101X" | "10XX" => + Q1_zd <= q1rnk2 after DELAY_MXINP1; + Q2_zd <= q2rnk2 after DELAY_MXINP1; + when "1100" | "1101" | "1110" | "1111" | "11X0" | "11X1" | + "110X" | "111X" | "11XX" => + Q1_zd <= q1rnk3 after DELAY_MXINP1; + Q2_zd <= q2rnk3 after DELAY_MXINP1; + when others => + Q1_zd <= q1rnk2 after DELAY_MXINP1; + Q2_zd <= q2rnk2 after DELAY_MXINP1; + end case; + end process prcs_Q1Q2_rnk3_mux; +-------------------------------------------------------------------- + prcs_Q3Q4Q5Q6_rnk3_mux:process(q3rnk2, q3rnk3, q4rnk2, q4rnk3, + q5rnk2, q5rnk3, q6rnk2, q6rnk3) + begin + case AttrBitslipEnable is + when '0' => + Q3_zd <= q3rnk2 after DELAY_MXINP1; + Q4_zd <= q4rnk2 after DELAY_MXINP1; + Q5_zd <= q5rnk2 after DELAY_MXINP1; + Q6_zd <= q6rnk2 after DELAY_MXINP1; + when '1' => + Q3_zd <= q3rnk3 after DELAY_MXINP1; + Q4_zd <= q4rnk3 after DELAY_MXINP1; + Q5_zd <= q5rnk3 after DELAY_MXINP1; + Q6_zd <= q6rnk3 after DELAY_MXINP1; + when others => + Q3_zd <= q3rnk2 after DELAY_MXINP1; + Q4_zd <= q4rnk2 after DELAY_MXINP1; + Q5_zd <= q5rnk2 after DELAY_MXINP1; + Q6_zd <= q6rnk2 after DELAY_MXINP1; + end case; + end process prcs_Q3Q4Q5Q6_rnk3_mux; +---------------------------------------------------------------------- +----------- Inverted CLK ----------------------------------------- +---------------------------------------------------------------------- + + CLKN_dly <= not CLK_dly; + +---------------------------------------------------------------------- +----------- Instant BSCNTRL -------------------------------------- +---------------------------------------------------------------------- + INST_BSCNTRL : BSCNTRL + generic map ( + SRTYPE => SRTYPE, + INIT_BITSLIPCNT => INIT_BITSLIPCNT + ) + port map ( + CLKDIV_INT => clkdiv_int, + MUXC => muxc, + + BITSLIP => BITSLIP_dly, + C23 => c23, + C45 => c45, + C67 => c67, + CLK => CLKN_dly, + CLKDIV => CLKDIV_dly, + DATA_RATE => AttrDataRate, + GSR => GSR_dly, + R => SR_dly, + SEL => sel + ); + +--################################################################### +--##### Set value of the counter in BSCNTRL ##### +--################################################################### + prcs_bscntrl_cntr:process + begin + wait for 10 ps; + case cntr is + when "00100" => + c23<='0'; c45<='0'; c67<='0'; sel<="00"; + when "00110" => + c23<='1'; c45<='0'; c67<='0'; sel<="00"; + when "01000" => + c23<='0'; c45<='0'; c67<='0'; sel<="01"; + when "01010" => + c23<='0'; c45<='1'; c67<='0'; sel<="01"; + when "10010" => + c23<='0'; c45<='0'; c67<='0'; sel<="00"; + when "10011" => + c23<='1'; c45<='0'; c67<='0'; sel<="00"; + when "10100" => + c23<='0'; c45<='0'; c67<='0'; sel<="01"; + when "10101" => + c23<='0'; c45<='1'; c67<='0'; sel<="01"; + when "10110" => + c23<='0'; c45<='0'; c67<='0'; sel<="10"; + when "10111" => + c23<='0'; c45<='0'; c67<='1'; sel<="10"; + when "11000" => + c23<='0'; c45<='0'; c67<='0'; sel<="11"; + when others => + assert FALSE + report "Error : DATA_WIDTH or DATA_RATE has illegal values." + severity failure; + end case; + wait on cntr, c23, c45, c67, sel; + + end process prcs_bscntrl_cntr; + +---------------------------------------------------------------------- +----------- Instant Clock Enable Circuit ------------------------- +---------------------------------------------------------------------- + INST_ICE : ICE_MODULE + generic map ( + SRTYPE => SRTYPE, + INIT_CE => INIT_CE + ) + port map ( + ICE => ice, + + CE1 => CE1_dly, + CE2 => CE2_dly, + GSR => GSR_dly, + NUM_CE => AttrNumCe, + CLKDIV => CLKDIV_dly, + R => SR_dly + ); +---------------------------------------------------------------------- +----------- Instant IDELAY --------------------------------------- +---------------------------------------------------------------------- + INST_IDELAY : IDELAY + generic map ( + IOBDELAY_VALUE => IOBDELAY_VALUE, + IOBDELAY_TYPE => IOBDELAY_TYPE + ) + port map ( + O => idelay_out, + + C => CLKDIV_dly, + CE => DLYCE_dly, + + I => D_dly, + INC => DLYINC_dly, + RST => DLYRST_dly + ); + +--################################################################### +--##### IOBDELAY -- Delay input Data ##### +--################################################################### + prcs_d_delay:process(D_dly, idelay_out) + begin + case AttrIobDelay is + when 0 => + O_zd <= D_dly; + datain <= D_dly; + when 1 => + O_zd <= idelay_out; + datain <= D_dly; + when 2 => + O_zd <= D_dly; + datain <= idelay_out; + when 3 => + O_zd <= idelay_out; + datain <= idelay_out; + when others => + null; + end case; + end process prcs_d_delay; + +--#################################################################### + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(O_zd, Q1_zd, Q2_zd, Q3_zd, Q4_zd, Q5_zd, Q6_zd, + SHIFTOUT1_zd, SHIFTOUT2_zd) + begin + O <= O_zd; + Q1 <= Q1_zd after SYNC_PATH_DELAY; + Q2 <= Q2_zd after SYNC_PATH_DELAY; + Q3 <= Q3_zd after SYNC_PATH_DELAY; + Q4 <= Q4_zd after SYNC_PATH_DELAY; + Q5 <= Q5_zd after SYNC_PATH_DELAY; + Q6 <= Q6_zd after SYNC_PATH_DELAY; + SHIFTOUT1 <= SHIFTOUT1_zd after SYNC_PATH_DELAY; + SHIFTOUT2 <= SHIFTOUT2_zd after SYNC_PATH_DELAY; + end process prcs_output; +--#################################################################### + + +end ISERDES_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Jtag TAP contorller +-- / / +-- /___/ /\ Filename : JTAG_SIM_VIRTEX4.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:18:21 PST 2004 +-- \___\/\___\ +-- +-- Revision: +-- 08/26/04 - Initial version. +-- 07/09/05 - CR 211337 BSCAN_VIRTEX4 Reset is active on the "+" TCK when in State TLRST +-- 07/20/05 - CR 212040 Added Timing +-- End Revision + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.Vital_Primitives.all; +use IEEE.Vital_Timing.all; + + +library unisim; +use unisim.vpkg.all; +use unisim.Vcomponents.all; + +entity JTAG_SIM_VIRTEX4_SUBMOD is + + generic( + PART_NAME : string; + IRLength : integer + ); + + port( + TDO : out std_ulogic; + + TCK : in std_ulogic; + TDI : in std_ulogic; + TMS : in std_ulogic + ); + +end JTAG_SIM_VIRTEX4_SUBMOD; + +architecture JTAG_SIM_VIRTEX4_SUBMOD_V OF JTAG_SIM_VIRTEX4_SUBMOD is + + + TYPE JtagTapState is (TestLogicReset, RunTestIdle,SelectDRScan, CaptureDR, + ShiftDR, Exit1DR, PauseDR, Exit2DR, UPdateDR, + SelectIRScan, CaptureIR, ShiftIR, Exit1IR, PauseIR, + Exit2IR, UPdateIR); + + +------------------------------------------------------------------------------- +----------------- Virtex4 Specific Constants --------------------------------- +------------------------------------------------------------------------------- + + TYPE JtagInstructionType is (UNKNOWN, IR_CAPTURE, BYPASS, IDCODE, USER1, USER2, USER3, USER4); + + TYPE PartType is (LX15, LX25, LX40, LX60, LX80, LX100, LX160, LX200, + SX25, SX35, SX55, + FX12, FX20, FX40, FX60, FX100, FX140, FX200); + + constant IRLengthMax : integer := 14; + constant IDLength : integer := 32; + constant RevBitsLength : integer := 4; + + constant IR_CAPTURE_VAL : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111010001"; + constant BYPASS_INSTR : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111111111"; + constant IDCODE_INSTR : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111001001"; + constant USER1_INSTR : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111000010"; + constant USER2_INSTR : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111000011"; + constant USER3_INSTR : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111100010"; + constant USER4_INSTR : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111100011"; + + + +-------------------------------------------------------- + + constant DELAY_SIG : time := 1 ps; + + constant Xon : boolean := true; + constant MsgOn : boolean := true; + + signal ticd_TCK : VitalDelayType := 0.0 ns; + + signal tisd_TDI_TCK : VitalDelayType := 0.0 ns; + signal tisd_TMS_TCK : VitalDelayType := 0.0 ns; + + signal tsetup_TMS_TCK_posedge_posedge : VitalDelayType := 1.0 ns; + signal tsetup_TMS_TCK_negedge_posedge : VitalDelayType := 1.0 ns; + + signal tsetup_TDI_TCK_posedge_posedge : VitalDelayType := 1.0 ns; + signal tsetup_TDI_TCK_negedge_posedge : VitalDelayType := 1.0 ns; + + signal thold_TMS_TCK_posedge_posedge : VitalDelayType := 2.0 ns; + signal thold_TMS_TCK_negedge_posedge : VitalDelayType := 2.0 ns; + + signal thold_TDI_TCK_posedge_posedge : VitalDelayType := 2.0 ns; + signal thold_TDI_TCK_negedge_posedge : VitalDelayType := 2.0 ns; + + signal tpd_TCK_TDO : VitalDelayType01 := (6.0 ns, 6.0 ns); + + signal CurrentState : JtagTapState := TestLogicReset; + signal JtagInstruction : JtagInstructionType := IDCODE; + + signal jtag_state_name : JtagTapState := TestLogicReset; + signal jtag_instruction_name : JtagInstructionType := IDCODE; + + signal TCK_ipd : std_ulogic := 'X'; + signal TDI_ipd : std_ulogic := 'X'; + signal TMS_ipd : std_ulogic := 'X'; + signal TRST_ipd : std_ulogic := 'X'; + + + signal TCK_dly : std_ulogic := 'X'; + signal TDI_dly : std_ulogic := 'X'; + signal TMS_dly : std_ulogic := 'X'; + signal TRST_dly : std_ulogic := '0'; + + signal TDO_zd : std_ulogic := 'X'; + signal TDO_viol : std_ulogic := 'X'; + +----------- signal declaration ------------------- + + signal CaptureDR_sig : std_ulogic := '0'; + signal RESET_sig : std_ulogic := '0'; + signal ShiftDR_sig : std_ulogic := '0'; + signal UpdateDR_sig : std_ulogic := '0'; + + signal ClkIR_active : std_ulogic := '0'; + + signal ClkIR_sig : std_ulogic := '0'; + signal ClkID_sig : std_ulogic := '0'; + signal ShiftIR_sig : std_ulogic := 'X'; + signal UpdateIR_sig : std_ulogic := 'X'; + signal ClkUpdateIR_sig : std_ulogic := '0'; + signal IRcontent_sig : std_logic_vector ((IRLength -1) downto 0) := (others => 'X'); + signal IDCODEval_sig : std_logic_vector ((IDLength -1) downto 0) := (others => 'X'); + + signal BypassReg : std_ulogic := '0'; + signal BYPASS_sig : std_ulogic := '0'; + signal IDCODE_sig : std_ulogic := '0'; + signal USER1_sig : std_ulogic := '0'; + signal USER2_sig : std_ulogic := '0'; + signal USER3_sig : std_ulogic := '0'; + signal USER4_sig : std_ulogic := '0'; + + signal TDO_latch : std_ulogic := 'Z'; + + signal Tlrst_sig : std_ulogic := '1'; + signal TlrstN_sig : std_ulogic := '1'; + + signal IRegLastBit_sig : std_ulogic := '0'; + signal IDregLastBit_sig : std_ulogic := '0'; + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + TCK_dly <= TCK after 0 ps; + TDI_dly <= TDI after 0 ps; + TMS_dly <= TMS after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + variable PartName_var : PartType; + variable IDCODE_str : std_ulogic_vector ((IDLength -1) downto 0) := (others => 'X'); + begin + if((PART_NAME = "LX15") or (PART_NAME = "lx15")) then + PartName_var := LX15; + IDCODE_str((IDLength - RevBitsLength -1) downto 0) := X"1658093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "LX25") or (PART_NAME = "lx25")) then + PartName_var := LX25; + IDCODE_str((IDLength - RevBitsLength -1) downto 0) := X"167C093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "LX40") or (PART_NAME = "lx40")) then + PartName_var := LX40; + IDCODE_str((IDLength - RevBitsLength -1) downto 0) := X"16A4093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "LX60") or (PART_NAME = "lx60")) then + PartName_var := LX60; + IDCODE_str((IDLength - RevBitsLength -1) downto 0) := X"16B4093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "LX80") or (PART_NAME = "lx80")) then + PartName_var := LX80; + IDCODE_str((IDLength - RevBitsLength -1) downto 0) := X"16D8093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "LX100") or (PART_NAME = "lx100")) then + PartName_var := LX100; + IDCODE_str((IDLength - RevBitsLength -1) downto 0) := X"1700093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "LX160") or (PART_NAME = "lx160")) then + PartName_var := LX160; + IDCODE_str((IDLength - RevBitsLength -1) downto 0) := X"1718093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "LX200") or (PART_NAME = "lx200")) then + PartName_var := LX200; + IDCODE_str((IDLength - RevBitsLength -1) downto 0) := X"1734093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "SX25") or (PART_NAME = "sx25")) then + PartName_var := SX25; + IDCODE_str((IDLength - RevBitsLength -1) downto 0) := X"2068093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "SX35") or (PART_NAME = "sx35")) then + PartName_var := SX35; + IDCODE_str((IDLength - RevBitsLength -1) downto 0) := X"2088093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "SX55") or (PART_NAME = "sx55")) then + PartName_var := SX55; + IDCODE_str((IDLength - RevBitsLength -1) downto 0) := X"20B0093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "FX12") or (PART_NAME = "fx12")) then + PartName_var := FX12; + IDCODE_str((IDLength - RevBitsLength -1) downto 0) := X"1E58093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "FX20") or (PART_NAME = "fx20")) then + PartName_var := FX20; + IDCODE_str((IDLength - RevBitsLength -1) downto 0) := X"1E64093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "FX40") or (PART_NAME = "fx40")) then + PartName_var := FX40; + IDCODE_str((IDLength - RevBitsLength -1) downto 0) := X"1E8C093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "FX60") or (PART_NAME = "fx60")) then + PartName_var := FX60; + IDCODE_str((IDLength - RevBitsLength -1) downto 0) := X"1EB4093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "FX100") or (PART_NAME = "fx100")) then + PartName_var := FX100; + IDCODE_str((IDLength - RevBitsLength -1) downto 0) := X"1EE4093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "FX140") or (PART_NAME = "fx140")) then + PartName_var := FX140; + IDCODE_str((IDLength - RevBitsLength -1) downto 0) := X"1F14093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "FX200") or (PART_NAME = "fx200")) then + PartName_var := FX200; + IDCODE_str((IDLength - RevBitsLength -1) downto 0) := X"1F44093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + else + assert false + report "Attribute Syntax Error: The allowed values for PART_NAME are LX15, LX25, LX40, LX60, LX80, LX100, LX160, LX200, SX25, SX35, SX55, FX12, FX20, FX40, FX60, FX100, FX140 or FX200" + severity Failure; + end if; + + wait; + + end process prcs_init; +--#################################################################### +--##### JtagTapSM ##### +--#################################################################### + prcs_JtagTapSM:process(TCK_dly, TRST_dly) + begin + + if(TRST_dly = '1') then + CurrentState <= TestLogicReset; + elsif(TRST_dly = '0') then + if(rising_edge(TCK_dly)) then + case CurrentState is + ------------------------------- + ---- Reset path --------------- + ------------------------------- + when TestLogicReset => + if(TMS_dly = '0') then + CurrentState <= RunTestIdle; + end if; + when RunTestIdle => + if(TMS_dly = '1') then + CurrentState <= SelectDRScan; + end if; + ------------------------------- + ------ DR path --------------- + ------------------------------- + when SelectDRScan => + if(TMS_dly = '0') then + CurrentState <= CaptureDR; + elsif(TMS_dly = '1') then + CurrentState <= SelectIRScan; + end if; + when CaptureDR => + if(TMS_dly = '0') then + CurrentState <= ShiftDR; + elsif(TMS_dly = '1') then + CurrentState <= Exit1DR; + end if; + when ShiftDR => + if(TMS_dly = '1') then + CurrentState <= Exit1DR; + end if; + + if(IRcontent_sig = BYPASS_INSTR((IRLength -1) downto 0)) then + BypassReg <= TDI_dly; + end if; + + when Exit1DR => + if(TMS_dly = '0') then + CurrentState <= PauseDR; + elsif(TMS_dly = '1') then + CurrentState <= UpdateDR; + end if; + when PauseDR => + if(TMS_dly = '1') then + CurrentState <= Exit2DR; + end if; + when Exit2DR => + if(TMS_dly = '0') then + CurrentState <= ShiftDR; + elsif(TMS_dly = '1') then + CurrentState <= UpdateDR; + end if; + when UpdateDR => + if(TMS_dly = '0') then + CurrentState <= RunTestIdle; + elsif(TMS_dly = '1') then + CurrentState <= SelectDRScan; + end if; + ------------------------------- + ------ IR path --------------- + ------------------------------- + when SelectIRScan => + if(TMS_dly = '0') then + CurrentState <= CaptureIR; + elsif(TMS_dly = '1') then + CurrentState <= TestLogicReset; + end if; + when CaptureIR => + if(TMS_dly = '0') then + CurrentState <= ShiftIR; + elsif(TMS_dly = '1') then + CurrentState <= Exit1IR; + end if; + when ShiftIR => + if(TMS_dly = '1') then + CurrentState <= Exit1IR; + end if; + when Exit1IR => + if(TMS_dly = '0') then + CurrentState <= PauseIR; + elsif(TMS_dly = '1') then + CurrentState <= UpdateIR; + end if; + when PauseIR => + if(TMS_dly = '1') then + CurrentState <= Exit2IR; + end if; + when Exit2IR => + if(TMS_dly = '0') then + CurrentState <= ShiftIR; + elsif(TMS_dly = '1') then + CurrentState <= UpdateIR; + end if; + when UpdateIR => + if(TMS_dly = '0') then + CurrentState <= RunTestIdle; + elsif(TMS_dly = '1') then + CurrentState <= SelectDRScan; + end if; + end case; + end if; + end if; + end process prcs_JtagTapSM; + +--#################################################################### +--##### CurrentState ##### +--#################################################################### + + prcs_CurrentState:process(TCK_dly, CurrentState, TRST_dly) + begin + + ClkIR_sig <= '1'; + + if(TRST_dly = '1') then + CaptureDR_sig <= '0'; + ShiftDR_sig <= '0'; + UpdateDR_sig <= '0'; + ShiftIR_sig <= '0'; + UpdateIR_sig <= '0'; + elsif(TRST_dly = '0') then + + case CurrentState is + + when TestLogicReset => + Tlrst_sig <= '1' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + + when CaptureDR => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '1' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + + when ShiftDR => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '1' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + + when UpdateDR => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '1' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + + when CaptureIR => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + ClkIR_sig <= TCK_dly; + + + when ShiftIR => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '1' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + ClkIR_sig <= TCK_dly; + + when UpdateIR => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '1' after DELAY_SIG; + + when others => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + end case; + end if; + + end process prcs_CurrentState; + +------------- ?? TCK NEGATIVE EDGE activities ---------- + + prcs_ClkIR:process(TCK_dly) + begin +-- ClkIR_sig <= ShiftIR_sig and TCK_dly; + CLkUpdateIR_sig <= UpdateIR_sig and not TCK_dly; + end process prcs_ClkIR; + + prcs_ClkID:process(TCK_dly) + begin + ClkID_sig <= IDCODE_sig and TCK_dly; + end process prcs_ClkID; + + prcs_glblsigs:process(TCK_dly, UpdateDR_sig) + begin + if(falling_edge(TCK_dly)) then + JTAG_CAPTURE_GLBL <= CaptureDR_sig; + -- CR 211337 Reset should go high as soon as it gets to State Trlst + -- JTAG_RESET_GLBL <= Tlrst_sig; + JTAG_SHIFT_GLBL <= ShiftDR_sig; + JTAG_UPDATE_GLBL <= UpdateDR_sig; + TlrstN_sig <= Tlrst_sig; + end if; + + if(falling_edge(UpdateDR_sig))then + JTAG_UPDATE_GLBL <= UpdateDR_sig; + end if; + + end process prcs_glblsigs; + +-- CR 211337 + prcs_reset:process(Tlrst_sig) + begin + JTAG_RESET_GLBL <= Tlrst_sig; + end process prcs_reset; +--#################################################################### +--##### JtagIR ##### +--#################################################################### + prcs_JtagIR:process(ClkIR_sig, ClkUpdateIR_sig, ShiftIR_sig, TlrstN_sig, TRST_dly) + variable NextIRreg : std_logic_vector ((IRLength -1) downto 0) := IR_CAPTURE_VAL((IRLength -1) downto 0); + variable ir_int : std_logic_vector ((IRLength -1) downto 0) := IR_CAPTURE_VAL((IRLength -1) downto 0); + begin + NextIRreg((IRLength -1) downto 0) := (TDI_dly & ir_int((IRLength -1) downto 1)); + + if((TRST_dly = '1') or (TlrstN_sig = '1'))then + IRcontent_sig((IRLength -1) downto 0) <= IDCODE_INSTR((IRLength -1) downto 0); -- IDCODE instruction is loaded into IR reg. + IRegLastBit_sig <= ir_int(0); + elsif((TRST_dly = '0') and (TlrstN_sig = '0')) then + if(rising_edge(ClkIR_sig)) then + if(ShiftIR_sig = '1') then + ir_int((IRLength -1) downto 0) := NextIRreg((IRLength -1) downto 0); + IRegLastBit_sig <= ir_int(0); + else + ir_int := IR_CAPTURE_VAL((IRLength -1) downto 0); + IRegLastBit_sig <= ir_int(0); + end if; + end if; + if(rising_edge(ClkUpdateIR_sig)) then + if(UpdateIR_sig = '1') then + IRcontent_sig <= ir_int; + end if; + end if; + end if; + end process prcs_JtagIR; +--#################################################################### +--##### JtagDecodeIR ##### +--#################################################################### + prcs_JtagDecodeIR:process(IRcontent_sig) + begin + if(IRcontent_sig((IRLength -1) downto 0) = IR_CAPTURE_VAL((IRLength-1) downto 0)) then + JTagInstruction <= IR_CAPTURE; + + elsif(IRcontent_sig((IRLength -1) downto 0) = BYPASS_INSTR((IRLength-1) downto 0)) then + JTagInstruction <= BYPASS; + BYPASS_sig <= '1'; + IDCODE_sig <= '0'; + USER1_sig <= '0'; + USER2_sig <= '0'; + USER3_sig <= '0'; + USER4_sig <= '0'; + + elsif(IRcontent_sig((IRLength -1) downto 0) = IDCODE_INSTR((IRLength-1) downto 0)) then + JTagInstruction <= IDCODE; + BYPASS_sig <= '0'; + IDCODE_sig <= '1'; + USER1_sig <= '0'; + USER2_sig <= '0'; + USER3_sig <= '0'; + USER4_sig <= '0'; + + elsif(IRcontent_sig((IRLength -1) downto 0) = USER1_INSTR((IRLength-1) downto 0)) then + JTagInstruction <= USER1; + BYPASS_sig <= '0'; + IDCODE_sig <= '0'; + USER1_sig <= '1'; + USER2_sig <= '0'; + USER3_sig <= '0'; + USER4_sig <= '0'; + + elsif(IRcontent_sig((IRLength -1) downto 0) = USER2_INSTR((IRLength-1) downto 0)) then + JTagInstruction <= USER2; + BYPASS_sig <= '0'; + IDCODE_sig <= '0'; + USER1_sig <= '0'; + USER2_sig <= '1'; + USER3_sig <= '0'; + USER4_sig <= '0'; + + elsif(IRcontent_sig((IRLength -1) downto 0) = USER3_INSTR((IRLength-1) downto 0)) then + JTagInstruction <= USER3; + BYPASS_sig <= '0'; + IDCODE_sig <= '0'; + USER1_sig <= '0'; + USER2_sig <= '0'; + USER3_sig <= '1'; + USER4_sig <= '0'; + + elsif(IRcontent_sig((IRLength -1) downto 0) = USER4_INSTR((IRLength-1) downto 0)) then + JTagInstruction <= USER4; + BYPASS_sig <= '0'; + IDCODE_sig <= '0'; + USER1_sig <= '0'; + USER2_sig <= '0'; + USER3_sig <= '0'; + USER4_sig <= '1'; + + else + JTagInstruction <= UNKNOWN; + NULL; + end if; + end process prcs_JtagDecodeIR; +--#################################################################### +--##### JtagIDCODE ##### +--#################################################################### + prcs_JtagIDCODE:process(ClkID_sig) + variable IDreg : bit_vector ((IDLength -1) downto 0); + begin + if(rising_edge(ClkID_sig)) then + if(ShiftDR_sig = '1') then + IDreg := IDreg sra 1; + IDreg(IDLength -1) := TO_BIT(TDI_dly); + else + IDreg := TO_BITVECTOR(IDCODEval_sig); + end if; + end if; + + IDregLastBit_sig <= TO_STDULOGIC(IDreg(0)); + + end process prcs_JtagIDCODE; +--#################################################################### +--#################################################################### +--##### JtagSetGlobalSignals ##### +--#################################################################### + prcs_JtagSetGlobalSignals:process(ClkUpdateIR_sig, Tlrst_sig, USER1_sig, USER2_sig, USER3_sig, USER4_sig) + begin + if(rising_edge(USER1_sig)) then + JTAG_SEL1_GLBL <= '1'; + JTAG_SEL2_GLBL <= '0'; + JTAG_SEL3_GLBL <= '0'; + JTAG_SEL4_GLBL <= '0'; + elsif(rising_edge(USER2_sig)) then + JTAG_SEL1_GLBL <= '0'; + JTAG_SEL2_GLBL <= '1'; + JTAG_SEL3_GLBL <= '0'; + JTAG_SEL4_GLBL <= '0'; + elsif(rising_edge(USER3_sig)) then + JTAG_SEL1_GLBL <= '0'; + JTAG_SEL2_GLBL <= '0'; + JTAG_SEL3_GLBL <= '1'; + JTAG_SEL4_GLBL <= '0'; + elsif(rising_edge(USER4_sig)) then + JTAG_SEL1_GLBL <= '0'; + JTAG_SEL2_GLBL <= '0'; + JTAG_SEL3_GLBL <= '0'; + JTAG_SEL4_GLBL <= '1'; + elsif(rising_edge(ClkUpdateIR_sig)) then + JTAG_SEL1_GLBL <= '0'; + JTAG_SEL2_GLBL <= '0'; + JTAG_SEL3_GLBL <= '0'; + JTAG_SEL4_GLBL <= '0'; + elsif(rising_edge(Tlrst_sig)) then + JTAG_SEL1_GLBL <= '0'; + JTAG_SEL2_GLBL <= '0'; + JTAG_SEL3_GLBL <= '0'; + JTAG_SEL4_GLBL <= '0'; + end if; + + end process prcs_JtagSetGlobalSignals; + +--#################################################################### + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + + jtag_state_name <= CurrentState; + jtag_instruction_name <= JtagInstruction; + + JTAG_TCK_GLBL <= TCK_dly; + JTAG_TDI_GLBL <= TDI_dly; + JTAG_TMS_GLBL <= TMS_dly; + JTAG_TRST_GLBL <= TRST_dly; + + TDO_latch <= BypassReg + when ((CurrentState = ShiftDR) and (IRcontent_sig=BYPASS_INSTR((IRLength -1) downto 0))) + else IRegLastBit_sig + when (CurrentState = ShiftIR) + else IDregLastBit_sig + when ((CurrentState = ShiftDR) and (IRcontent_sig=IDCODE_INSTR((IRLength -1) downto 0))) + else JTAG_USER_TDO1_GLBL + when ((CurrentState = ShiftDR) and (IRcontent_sig=USER1_INSTR((IRLength -1) downto 0))) + else JTAG_USER_TDO2_GLBL + when ((CurrentState = ShiftDR) and (IRcontent_sig=USER2_INSTR((IRLength -1) downto 0))) + else JTAG_USER_TDO3_GLBL + when ((CurrentState = ShiftDR) and (IRcontent_sig=USER3_INSTR((IRLength -1) downto 0))) + else JTAG_USER_TDO4_GLBL + when ((CurrentState = ShiftDR) and (IRcontent_sig=USER4_INSTR((IRLength -1) downto 0))) + else 'Z'; + +-- CR 212040 -- added timing +-- prcs_TDO:process(TCK_dly) +-- begin +-- if(falling_edge(TCK_dly)) then +-- TDO <= TDO_latch; +-- end if; +-- end process prcs_TDO; + +--#################################################################### +--##### Timing ##### +--#################################################################### + VITALBehavior : process (TCK_dly, TDI_dly, TMS_dly) + + variable PInfo_TCK : VitalPeriodDataType := VitalPeriodDataInit; + variable Pviol_TCK : std_ulogic := '0'; + + variable Tmkr_TDI_TCK_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tviol_TDI_TCK_posedge : std_ulogic := '0'; + + variable Tmkr_TMS_TCK_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tviol_TMS_TCK_posedge : std_ulogic := '0'; + + variable Violation : std_ulogic := '0'; + + variable TDO_GlitchData : VitalGlitchDataType; + + + begin + VitalSetupHoldCheck ( + Violation => Tviol_TDI_TCK_posedge, + TimingData => Tmkr_TDI_TCK_posedge, + TestSignal => TDI_dly, + TestSignalName => "TDI", + TestDelay => tisd_TDI_TCK, + RefSignal => TCK_dly, + RefSignalName => "TCK", + RefDelay => ticd_TCK, + SetupHigh => tsetup_TDI_TCK_posedge_posedge, + SetupLow => tsetup_TDI_TCK_negedge_posedge, + HoldLow => thold_TDI_TCK_posedge_posedge, + HoldHigh => thold_TDI_TCK_negedge_posedge, + CheckEnabled => TO_X01(TRST_dly) = '0', + RefTransition => 'R', + HeaderMsg => "/X_JTAG_SIM_VIRTEX4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + VitalSetupHoldCheck ( + Violation => Tviol_TMS_TCK_posedge, + TimingData => Tmkr_TMS_TCK_posedge, + TestSignal => TMS_dly, + TestSignalName => "TMS", + TestDelay => tisd_TMS_TCK, + RefSignal => TCK_dly, + RefSignalName => "TCK", + RefDelay => ticd_TCK, + SetupHigh => tsetup_TMS_TCK_posedge_posedge, + SetupLow => tsetup_TMS_TCK_negedge_posedge, + HoldLow => thold_TMS_TCK_posedge_posedge, + HoldHigh => thold_TMS_TCK_negedge_posedge, + CheckEnabled => TO_X01(TRST_dly) = '0', + RefTransition => 'R', + HeaderMsg => "/X_JTAG_SIM_VIRTEX4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + VitalPathDelay01 ( + OutSignal => TDO, + GlitchData => TDO_GlitchData, + OutSignalName => "TDO", + OutTemp => TDO_latch, + Paths => (0 => (TCK_dly'last_event, tpd_TCK_TDO, TRST_dly = '0')), + Mode => VitalTransport, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end process; + + + +--#################################################################### +--#################################################################### + + +end JTAG_SIM_VIRTEX4_SUBMOD_V; + + +----- CELL JTAG_SIM_VIRTEX4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.vpkg.all; +use unisim.Vcomponents.all; + +entity JTAG_SIM_VIRTEX4 is + + generic( + PART_NAME : string := "LX15" + ); + + port( + TDO : out std_ulogic; + + TCK : in std_ulogic; + TDI : in std_ulogic; + TMS : in std_ulogic + ); + +end JTAG_SIM_VIRTEX4; + +architecture JTAG_SIM_VIRTEX4_V OF JTAG_SIM_VIRTEX4 is + + component JTAG_SIM_VIRTEX4_SUBMOD + generic( + PART_NAME : string; + IRLength : integer + ); + + port( + TDO : out std_ulogic; + + TCK : in std_ulogic; + TDI : in std_ulogic; + TMS : in std_ulogic + ); + end component; + + signal TCK_ipd : std_ulogic := 'X'; + signal TDI_ipd : std_ulogic := 'X'; + signal TMS_ipd : std_ulogic := 'X'; + signal TRST_ipd : std_ulogic := 'X'; + + + signal TCK_dly : std_ulogic := 'X'; + signal TDI_dly : std_ulogic := 'X'; + signal TMS_dly : std_ulogic := 'X'; + signal TRST_dly : std_ulogic := '0'; + + signal TDO_zd : std_ulogic := 'X'; + signal TDO_viol : std_ulogic := 'X'; + + signal TDO1_zd : std_ulogic := 'X'; + signal TDO2_zd : std_ulogic := 'X'; + + signal IRLen10, IRLen14 : boolean := false; + + + + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + TCK_dly <= TCK after 0 ps; + TDI_dly <= TDI after 0 ps; + TMS_dly <= TMS after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + + +--#################################################################### +--##### Initialization ##### +--#################################################################### + prcs_init:process + begin + if((PART_NAME = "LX15") or (PART_NAME = "lx15") or + (PART_NAME = "LX25") or (PART_NAME = "lx25") or + (PART_NAME = "LX40") or (PART_NAME = "lx40") or + (PART_NAME = "LX60") or (PART_NAME = "lx60") or + (PART_NAME = "LX80") or (PART_NAME = "lx80") or + (PART_NAME = "LX100") or (PART_NAME = "lx100") or + (PART_NAME = "LX200") or (PART_NAME = "lx200") or + (PART_NAME = "SX25") or (PART_NAME = "sx25") or + (PART_NAME = "SX35") or (PART_NAME = "sx35") or + (PART_NAME = "SX55") or (PART_NAME = "sx55") or + (PART_NAME = "FX12") or (PART_NAME = "fx12") or + (PART_NAME = "FX20") or (PART_NAME = "fx20")) then + IRLen10 <= true; + elsif((PART_NAME = "FX40") or (PART_NAME = "fx40") or + (PART_NAME = "FX60") or (PART_NAME = "fx60") or + (PART_NAME = "FX100") or (PART_NAME = "fx100") or + (PART_NAME = "FX140") or (PART_NAME = "fx140") or + (PART_NAME = "FX200") or (PART_NAME = "fx200")) then + IRLen14 <= true; + end if; + + wait; + + end process prcs_init; + +--#################################################################### +--##### Generate ##### +--#################################################################### + G1: if((PART_NAME = "LX15") or (PART_NAME = "lx15") or + (PART_NAME = "LX25") or (PART_NAME = "lx25") or + (PART_NAME = "LX40") or (PART_NAME = "lx40") or + (PART_NAME = "LX60") or (PART_NAME = "lx60") or + (PART_NAME = "LX80") or (PART_NAME = "lx80") or + (PART_NAME = "LX100") or (PART_NAME = "lx100") or + (PART_NAME = "LX200") or (PART_NAME = "lx200") or + (PART_NAME = "SX25") or (PART_NAME = "sx25") or + (PART_NAME = "SX35") or (PART_NAME = "sx35") or + (PART_NAME = "SX55") or (PART_NAME = "sx55") or + (PART_NAME = "FX12") or (PART_NAME = "fx12") or + (PART_NAME = "FX20") or (PART_NAME = "fx20")) generate + + JTAG_INST : JTAG_SIM_VIRTEX4_SUBMOD + generic map ( + PART_NAME => PART_NAME, + IRLength => 10 + ) + port map ( + TDO => TDO1_zd, + TCK => TCK_dly, + TDI => TDI_dly, + TMS => TMS_dly + ); + + end generate; + + G2: if((PART_NAME = "FX40") or (PART_NAME = "fx40") or + (PART_NAME = "FX60") or (PART_NAME = "fx60") or + (PART_NAME = "FX100") or (PART_NAME = "fx100") or + (PART_NAME = "FX140") or (PART_NAME = "fx140") or + (PART_NAME = "FX200") or (PART_NAME = "fx200")) generate + + JTAG_INST : JTAG_SIM_VIRTEX4_SUBMOD + generic map ( + PART_NAME => PART_NAME, + IRLength => 14 + ) + port map ( + TDO => TDO2_zd, + TCK => TCK_dly, + TDI => TDI_dly, + TMS => TMS_dly + ); + + end generate; + + + +--#################################################################### + + TDO <= TDO1_zd when IRLen10 else + TDO2_zd when IRLen14; + + +end JTAG_SIM_VIRTEX4_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / Dual Data Rate Output D Flip-Flop +-- /___/ /\ Filename : ODDR.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:18:20 PST 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL ODDR ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + + +library unisim; +use unisim.vpkg.all; + +entity ODDR is + + generic( + + DDR_CLK_EDGE : string := "OPPOSITE_EDGE"; + INIT : bit := '0'; + SRTYPE : string := "SYNC" + ); + + port( + Q : out std_ulogic; + + C : in std_ulogic; + CE : in std_ulogic; + D1 : in std_ulogic; + D2 : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); + +end ODDR; + +architecture ODDR_V OF ODDR is + + + constant SYNC_PATH_DELAY : time := 100 ps; + + signal C_ipd : std_ulogic := 'X'; + signal CE_ipd : std_ulogic := 'X'; + signal D1_ipd : std_ulogic := 'X'; + signal D2_ipd : std_ulogic := 'X'; + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := 'X'; + signal R_ipd : std_ulogic := 'X'; + signal S_ipd : std_ulogic := 'X'; + + signal C_dly : std_ulogic := 'X'; + signal CE_dly : std_ulogic := 'X'; + signal D1_dly : std_ulogic := 'X'; + signal D2_dly : std_ulogic := 'X'; + signal GSR_dly : std_ulogic := 'X'; + signal R_dly : std_ulogic := 'X'; + signal S_dly : std_ulogic := 'X'; + + signal Q_zd : std_ulogic := 'X'; + + signal Q_viol : std_ulogic := 'X'; + + signal ddr_clk_edge_type : integer := -999; + signal sr_type : integer := -999; + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + C_dly <= C after 0 ps; + CE_dly <= CE after 0 ps; + D1_dly <= D1 after 0 ps; + D2_dly <= D2 after 0 ps; + GSR_dly <= GSR after 0 ps; + R_dly <= R after 0 ps; + S_dly <= S after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + + begin + if((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then + ddr_clk_edge_type <= 1; + elsif((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then + ddr_clk_edge_type <= 2; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DDR_CLK_EDGE ", + EntityName => "/ODDR", + GenericValue => DDR_CLK_EDGE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " OPPOSITE_EDGE or SAME_EDGE.", + TailMsg => "", + MsgSeverity => ERROR + ); + end if; + + if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then + sr_type <= 1; + elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then + sr_type <= 2; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRTYPE ", + EntityName => "/ODDR", + GenericValue => SRTYPE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " ASYNC or SYNC. ", + TailMsg => "", + MsgSeverity => ERROR + ); + end if; + + wait; + end process prcs_init; +--#################################################################### +--##### q1_q2_q3 reg ##### +--#################################################################### + prcs_q1q2q3_reg:process(C_dly, GSR_dly, R_dly, S_dly) + variable Q1_var : std_ulogic := TO_X01(INIT); + variable Q2_posedge_var : std_ulogic := TO_X01(INIT); + begin + if(GSR_dly = '1') then + Q1_var := TO_X01(INIT); + Q2_posedge_var := TO_X01(INIT); + elsif(GSR_dly = '0') then + case sr_type is + when 1 => + if(R_dly = '1') then + Q1_var := '0'; + Q2_posedge_var := '0'; + elsif((R_dly = '0') and (S_dly = '1')) then + Q1_var := '1'; + Q2_posedge_var := '1'; + elsif((R_dly = '0') and (S_dly = '0')) then + if(CE_dly = '1') then + if(rising_edge(C_dly)) then + Q1_var := D1_dly; + Q2_posedge_var := D2_dly; + end if; + if(falling_edge(C_dly)) then + case ddr_clk_edge_type is + when 1 => + Q1_var := D2_dly; + when 2 => + Q1_var := Q2_posedge_var; + when others => + null; + end case; + end if; + end if; + end if; + + when 2 => + if(rising_edge(C_dly)) then + if(R_dly = '1') then + Q1_var := '0'; + Q2_posedge_var := '0'; + elsif((R_dly = '0') and (S_dly = '1')) then + Q1_var := '1'; + Q2_posedge_var := '1'; + elsif((R_dly = '0') and (S_dly = '0')) then + if(CE_dly = '1') then + Q1_var := D1_dly; + Q2_posedge_var := D2_dly; + end if; + end if; + end if; + + if(falling_edge(C_dly)) then + if(R_dly = '1') then + Q1_var := '0'; + elsif((R_dly = '0') and (S_dly = '1')) then + Q1_var := '1'; + elsif((R_dly = '0') and (S_dly = '0')) then + if(CE_dly = '1') then + case ddr_clk_edge_type is + when 1 => + Q1_var := D2_dly; + when 2 => + Q1_var := Q2_posedge_var; + when others => + null; + end case; + end if; + end if; + end if; + + when others => + null; + end case; + end if; + + Q_zd <= Q1_var; + + end process prcs_q1q2q3_reg; +--#################################################################### + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(Q_zd) + begin + Q <= Q_zd after SYNC_PATH_DELAY; + end process prcs_output; +--#################################################################### + + +end ODDR_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / Source Synchronous Output Serializer +-- /___/ /\ Filename : OSERDES.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:18:21 PST 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 01/23/06 - 223369 fixed Vital delays from CLK to OQ +-- 05/29/06 - CR 232324 -- Added timing checks for REV/SR wrt negedge CLKDIV +-- 08/08/06 - CR 225414 -- Added 100 ps delay to data inputs to resolve +-- race condition when data/clk change at the same time. +-- 01/08/08 - CR 458156 -- enabled TRISTATE_WIDTH to be 1 in DDR mode. +-- End Revision + +----- CELL OSERDES ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_arith.all; + + +library unisim; +use unisim.vpkg.all; + +entity PLG is + + generic( + + SRTYPE : string; + + INIT_LOADCNT : bit_vector(3 downto 0) + ); + + port( + LOAD : out std_ulogic; + + C23 : in std_ulogic; + C45 : in std_ulogic; + C67 : in std_ulogic; + CLK : in std_ulogic; + CLKDIV : in std_ulogic; + RST : in std_ulogic; + SEL : in std_logic_vector (1 downto 0) + ); + +end PLG; + +architecture PLG_V OF PLG is + + + constant DELAY_FFDCNT : time := 1 ps; + constant DELAY_MXDCNT : time := 1 ps; + constant DELAY_FFRST : time := 145 ps; + + constant MSB_SEL : integer := 1; + + signal CLK_ipd : std_ulogic := 'X'; + signal CLKDIV_ipd : std_ulogic := 'X'; + signal C23_ipd : std_ulogic := 'X'; + signal C45_ipd : std_ulogic := 'X'; + signal C67_ipd : std_ulogic := 'X'; + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := 'X'; + signal RST_ipd : std_ulogic := 'X'; + signal SEL_ipd : std_logic_vector(1 downto 0) := (others => 'X'); + + signal CLK_dly : std_ulogic := 'X'; + signal CLKDIV_dly : std_ulogic := 'X'; + signal C23_dly : std_ulogic := 'X'; + signal C45_dly : std_ulogic := 'X'; + signal C67_dly : std_ulogic := 'X'; + signal GSR_dly : std_ulogic := 'X'; + signal RST_dly : std_ulogic := 'X'; + signal SEL_dly : std_logic_vector(1 downto 0) := (others => 'X'); + + signal q0 : std_ulogic := 'X'; + signal q1 : std_ulogic := 'X'; + signal q2 : std_ulogic := 'X'; + signal q3 : std_ulogic := 'X'; + + signal qhr : std_ulogic := 'X'; + signal qlr : std_ulogic := 'X'; + + signal mux : std_ulogic := 'X'; + + signal load_zd : std_ulogic := 'X'; + + signal AttrSRtype : std_ulogic := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + C23_dly <= C23 after 0 ps; + C45_dly <= C45 after 0 ps; + C67_dly <= C67 after 0 ps; + CLK_dly <= CLK after 0 ps; + CLKDIV_dly <= CLKDIV after 0 ps; + GSR_dly <= GSR after 0 ps; + RST_dly <= RST after 0 ps; + SEL_dly <= SEL after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + begin + if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then + AttrSRtype <= '1'; + elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then + AttrSRtype <= '0'; + end if; + + wait; + end process prcs_init; +--#################################################################### +--##### Counter ##### +--#################################################################### + prcs_ff_cntr:process(qhr, CLK, GSR) + variable q3_var : std_ulogic := TO_X01(INIT_LOADCNT(3)); + variable q2_var : std_ulogic := TO_X01(INIT_LOADCNT(2)); + variable q1_var : std_ulogic := TO_X01(INIT_LOADCNT(1)); + variable q0_var : std_ulogic := TO_X01(INIT_LOADCNT(0)); + begin + if(GSR = '1') then + q3_var := TO_X01(INIT_LOADCNT(3)); + q2_var := TO_X01(INIT_LOADCNT(2)); + q1_var := TO_X01(INIT_LOADCNT(1)); + q0_var := TO_X01(INIT_LOADCNT(0)); + elsif(GSR = '0') then + case AttrSRtype is + when '1' => + --------------- // async SET/RESET + if(qhr = '1') then + q0_var := '0'; + q1_var := '0'; + q2_var := '0'; + q3_var := '0'; + else + if(rising_edge(CLK)) then + q3_var := q2_var; + q2_var :=( NOT((NOT q0_var) and (NOT q2_var)) and q1_var); + q1_var := q0_var; + q0_var := mux; + end if; + end if; + + when '0' => + --------------- // sync SET/RESET + if(rising_edge(CLK)) then + if(qhr = '1') then + q0_var := '0'; + q1_var := '0'; + q2_var := '0'; + q3_var := '0'; + else + q3_var := q2_var; + q2_var :=( NOT((NOT q0_var) and (NOT q2_var)) and q1_var); + q1_var := q0_var; + q0_var := mux; + end if; + end if; + + when others => + null; + end case; + + q0 <= q0_var after DELAY_FFDCNT; + q1 <= q1_var after DELAY_FFDCNT; + q2 <= q2_var after DELAY_FFDCNT; + q3 <= q3_var after DELAY_FFDCNT; + + end if; + end process prcs_ff_cntr; +--#################################################################### +--##### mux signal ##### +--#################################################################### + prcs_mux_sel:process(sel, c23, c45, c67, q0, q1, q2, q3) + begin + case sel is + when "00" => + mux <= ((not q0) and (not(c23 and q1))) after DELAY_MXDCNT; + when "01" => + mux <= ((not q1) and (not(c45 and q2))) after DELAY_MXDCNT; + when "10" => + mux <= ((not q2) and (not(c67 and q3))) after DELAY_MXDCNT; + when "11" => + mux <= (not (q3)) after DELAY_MXDCNT; + when others => + mux <= '0' after DELAY_MXDCNT; + end case; + end process prcs_mux_sel; +--#################################################################### +--##### load signal ##### +--#################################################################### + prcs_load_sel:process(sel, c23, c45, c67, q0, q1, q2, q3) + begin + case sel is + when "00" => + load_zd <= q0 after DELAY_MXDCNT; + when "01" => + load_zd <= (q0 and q1) after DELAY_MXDCNT; + when "10" => + load_zd <= (q0 and q2) after DELAY_MXDCNT; + when "11" => + load_zd <= (q0 and q3) after DELAY_MXDCNT; + when others => + load_zd <= '0' after DELAY_MXDCNT; + end case; + end process prcs_load_sel; +--#################################################################### +--##### Low/High speed FFs ##### +--#################################################################### + prcs_lowspeed:process(clkdiv, rst) + begin + case AttrSRtype is + when '1' => + --------------- // async SET/RESET + if(rst = '1') then + qlr <= '1' after DELAY_FFRST; + else + if(rising_edge(clkdiv)) then + qlr <= '0' after DELAY_FFRST; + end if; + end if; + + when '0' => + --------------- // sync SET/RESET + if(rising_edge(clkdiv)) then + if(rst = '1') then + qlr <= '1' after DELAY_FFRST; + else + qlr <= '0' after DELAY_FFRST; + end if; + end if; + when others => + null; + end case; + end process prcs_lowspeed; +---------------------------------------------------------------------- + prcs_highspeed:process(clk, rst) + begin + case AttrSRtype is + when '1' => + --------------- // async SET/RESET + if(rst = '1') then + qhr <= '1' after DELAY_FFDCNT; + else + if(rising_edge(clk)) then + qhr <= qlr after DELAY_FFDCNT; + end if; + end if; + + when '0' => + --------------- // sync SET/RESET + if(rising_edge(clk)) then + if(rst = '1') then + qhr <= '1' after DELAY_FFDCNT; + else + qhr <= qlr after DELAY_FFDCNT; + end if; + end if; + when others => + null; + end case; + end process prcs_highspeed; + + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(load_zd) + begin + load <= load_zd; + end process prcs_output; +--#################################################################### + + +end PLG_V; + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_arith.all; + + +library unisim; +use unisim.vpkg.all; + +entity IOOUT is + + generic( + + SERDES : boolean := TRUE; + SERDES_MODE : string := "MASTER"; + DATA_RATE_OQ : string := "DDR"; + DATA_WIDTH : integer := 4; + DDR_CLK_EDGE : string := "SAME_EDGE"; + INIT_OQ : bit := '0'; + SRVAL_OQ : bit := '1'; + INIT_ORANK1 : bit_vector(5 downto 0) := "000000"; + INIT_ORANK2_PARTIAL : bit_vector(3 downto 0) := "0000"; + INIT_LOADCNT : bit_vector(3 downto 0) := "0000"; + + SRTYPE : string := "ASYNC" + ); + + port( + OQ : out std_ulogic; + LOAD : out std_ulogic; + SHIFTOUT1 : out std_ulogic; + SHIFTOUT2 : out std_ulogic; + + C : in std_ulogic; + CLKDIV : in std_ulogic; + D1 : in std_ulogic; + D2 : in std_ulogic; + D3 : in std_ulogic; + D4 : in std_ulogic; + D5 : in std_ulogic; + D6 : in std_ulogic; + OCE : in std_ulogic; + REV : in std_ulogic; + SR : in std_ulogic; + SHIFTIN1 : in std_ulogic; + SHIFTIN2 : in std_ulogic + ); + +end IOOUT; + +architecture IOOUT_V OF IOOUT is + +component PLG + generic( + SRTYPE : string; + INIT_LOADCNT : bit_vector(3 downto 0) + ); + port( + LOAD : out std_ulogic; + + C23 : in std_ulogic; + C45 : in std_ulogic; + C67 : in std_ulogic; + CLK : in std_ulogic; + CLKDIV : in std_ulogic; + RST : in std_ulogic; + SEL : in std_logic_vector (1 downto 0) + ); + +end component; + + constant DELAY_FFD : time := 1 ps; + constant DELAY_FFCD : time := 1 ps; + constant DELAY_MXD : time := 1 ps; + constant DELAY_MXR1 : time := 1 ps; + + constant SWALLOW_PULSE : time := 2 ps; + + constant MAX_DATAWIDTH : integer := 4; + + signal C_ipd : std_ulogic := 'X'; + signal CLKDIV_ipd : std_ulogic := 'X'; + signal D1_ipd : std_ulogic := 'X'; + signal D2_ipd : std_ulogic := 'X'; + signal D3_ipd : std_ulogic := 'X'; + signal D4_ipd : std_ulogic := 'X'; + signal D5_ipd : std_ulogic := 'X'; + signal D6_ipd : std_ulogic := 'X'; + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := 'X'; + signal OCE_ipd : std_ulogic := 'X'; + signal REV_ipd : std_ulogic := 'X'; + signal SR_ipd : std_ulogic := 'X'; + signal SHIFTIN1_ipd : std_ulogic := 'X'; + signal SHIFTIN2_ipd : std_ulogic := 'X'; + + signal C_dly : std_ulogic := 'X'; + signal CLKDIV_dly : std_ulogic := 'X'; + signal D1_dly : std_ulogic := 'X'; + signal D2_dly : std_ulogic := 'X'; + signal D3_dly : std_ulogic := 'X'; + signal D4_dly : std_ulogic := 'X'; + signal D5_dly : std_ulogic := 'X'; + signal D6_dly : std_ulogic := 'X'; + signal GSR_dly : std_ulogic := 'X'; + signal OCE_dly : std_ulogic := 'X'; + signal REV_dly : std_ulogic := 'X'; + signal SR_dly : std_ulogic := 'X'; + signal SHIFTIN1_dly : std_ulogic := 'X'; + signal SHIFTIN2_dly : std_ulogic := 'X'; + + signal OQ_zd : std_ulogic := TO_X01(INIT_OQ); + signal LOAD_zd : std_ulogic := 'X'; + signal SHIFTOUT1_zd : std_ulogic := 'X'; + signal SHIFTOUT2_zd : std_ulogic := 'X'; + + signal AttrDataRateOQ : std_ulogic := 'X'; + signal AttrDataRateTQ : std_logic_vector(1 downto 0) := (others => 'X'); + signal AttrDataWidth : std_logic_vector(3 downto 0) := (others => 'X'); + signal AttrTriStateWidth : std_logic_vector(1 downto 0) := (others => 'X'); + signal AttrMode : std_ulogic := 'X'; + signal AttrDdrClkEdge : std_ulogic := 'X'; + + signal AttrSRtype : std_logic_vector(5 downto 0) := (others => '1'); + + signal AttrSerdes : std_ulogic := 'X'; + + signal d1r : std_ulogic := 'X'; + signal d2r : std_ulogic := 'X'; + signal d3r : std_ulogic := 'X'; + signal d4r : std_ulogic := 'X'; + signal d5r : std_ulogic := 'X'; + signal d6r : std_ulogic := 'X'; + + signal d1rnk2 : std_ulogic := 'X'; + signal d2rnk2 : std_ulogic := 'X'; + signal d2nrnk2 : std_ulogic := 'X'; + signal d3rnk2 : std_ulogic := 'X'; + signal d4rnk2 : std_ulogic := 'X'; + signal d5rnk2 : std_ulogic := 'X'; + signal d6rnk2 : std_ulogic := 'X'; + + signal data1 : std_ulogic := 'X'; + signal data2 : std_ulogic := 'X'; + signal data3 : std_ulogic := 'X'; + signal data4 : std_ulogic := 'X'; + signal data5 : std_ulogic := 'X'; + signal data6 : std_ulogic := 'X'; + + signal ddr_data : std_ulogic := 'X'; + signal odata_edge : std_ulogic := 'X'; + signal sdata_edge : std_ulogic := 'X'; + + signal c23 : std_ulogic := 'X'; + signal c45 : std_ulogic := 'X'; + signal c67 : std_ulogic := 'X'; + + signal sel : std_logic_vector(1 downto 0) := (others => 'X'); + + signal C2p : std_ulogic := 'X'; + signal C3 : std_ulogic := 'X'; + + signal loadint : std_ulogic := 'X'; + + signal seloq : std_logic_vector(3 downto 0) := (others => 'X'); + + signal oqsr : std_ulogic := 'X'; + + signal oqrev : std_ulogic := 'X'; + + signal sel1_4 : std_logic_vector(2 downto 0) := (others => 'X'); + signal sel5_6 : std_logic_vector(3 downto 0) := (others => 'X'); + + signal plgcnt : std_logic_vector(4 downto 0) := (others => 'X'); + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + C_dly <= C after 0 ps; + CLKDIV_dly <= CLKDIV after 0 ps; + D1_dly <= D1 after 0 ps; + D2_dly <= D2 after 0 ps; + D3_dly <= D3 after 0 ps; + D4_dly <= D4 after 0 ps; + D5_dly <= D5 after 0 ps; + D6_dly <= D6 after 0 ps; + GSR_dly <= GSR after 0 ps; + OCE_dly <= OCE after 0 ps; + REV_dly <= REV after 0 ps; + SR_dly <= SR after 0 ps; + SHIFTIN1_dly <= SHIFTIN1 after 0 ps; + SHIFTIN2_dly <= SHIFTIN2 after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + variable AttrDataRateOQ_var : std_ulogic := 'X'; + variable AttrDataWidth_var : std_logic_vector(3 downto 0) := (others => 'X'); + variable AttrMode_var : std_ulogic := 'X'; + variable AttrDdrClkEdge_var : std_ulogic := 'X'; + variable AttrSerdes_var : std_ulogic := 'X'; + + begin + -------------------- SERDES validity check -------------------- + if(SERDES = true) then + AttrSerdes_var := '1'; + else + AttrSerdes_var := '0'; + end if; + + ------------ SERDES_MODE validity check -------------------- + if((SERDES_MODE = "MASTER") or (SERDES_MODE = "master")) then + AttrMode_var := '0'; + elsif((SERDES_MODE = "SLAVE") or (SERDES_MODE = "slave")) then + AttrMode_var := '1'; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => "SERDES_MODE ", + EntityName => "/IOOUT", + GenericValue => SERDES_MODE, + Unit => "", + ExpectedValueMsg => " The legal values for this attribute are ", + ExpectedGenericValue => " MASTER or SLAVE.", + TailMsg => "", + MsgSeverity => FAILURE + ); + end if; + + ------------------ DATA_RATE validity check ------------------ + + if((DATA_RATE_OQ = "DDR") or (DATA_RATE_OQ = "ddr")) then + AttrDataRateOQ_var := '0'; + elsif((DATA_RATE_OQ = "SDR") or (DATA_RATE_OQ = "sdr")) then + AttrDataRateOQ_var := '1'; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DATA_RATE_OQ ", + EntityName => "/IOOUT", + GenericValue => DATA_RATE_OQ, + Unit => "", + ExpectedValueMsg => " The legal values for this attribute are ", + ExpectedGenericValue => " DDR or SDR. ", + TailMsg => "", + MsgSeverity => Failure + ); + end if; + + ------------------ DATA_WIDTH validity check ------------------ + if((DATA_WIDTH = 2) or (DATA_WIDTH = 3) or (DATA_WIDTH = 4) or + (DATA_WIDTH = 5) or (DATA_WIDTH = 6) or (DATA_WIDTH = 7) or + (DATA_WIDTH = 8) or (DATA_WIDTH = 10)) then + AttrDataWidth_var := CONV_STD_LOGIC_VECTOR(DATA_WIDTH, MAX_DATAWIDTH); + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DATA_WIDTH ", + EntityName => "/IOOUT", + GenericValue => DATA_WIDTH, + Unit => "", + ExpectedValueMsg => " The legal values for this attribute are ", + ExpectedGenericValue => " 2, 3, 4, 5, 6, 7, 8, or 10 ", + TailMsg => "", + MsgSeverity => Failure + ); + end if; + ------------ DATA_WIDTH /DATA_RATE combination check ------------ + if((DATA_RATE_OQ = "DDR") or (DATA_RATE_OQ = "ddr")) then + case (DATA_WIDTH) is + when 4|6|8|10 => null; + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DATA_WIDTH ", + EntityName => "/IOOUT", + GenericValue => DATA_WIDTH, + Unit => "", + ExpectedValueMsg => " The legal values for this attribute in DDR mode are ", + ExpectedGenericValue => " 4, 6, 8, or 10 ", + TailMsg => "", + MsgSeverity => Failure + ); + end case; + end if; + + if((DATA_RATE_OQ = "SDR") or (DATA_RATE_OQ = "sdr")) then + case (DATA_WIDTH) is + when 2|3|4|5|6|7|8 => null; + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DATA_WIDTH ", + EntityName => "/IOOUT", + GenericValue => DATA_WIDTH, + Unit => "", + ExpectedValueMsg => " The legal values for this attribute in SDR mode are ", + ExpectedGenericValue => " 2, 3, 4, 5, 6, 7 or 8.", + TailMsg => "", + MsgSeverity => Failure + ); + end case; + end if; + + ------------------ DDR_CLK_EDGE validity check ------------------ + + if((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then + AttrDdrClkEdge_var := '1'; + elsif((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then + AttrDdrClkEdge_var := '0'; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DDR_CLK_EDGE ", + EntityName => "/IOOUT", + GenericValue => DDR_CLK_EDGE, + Unit => "", + ExpectedValueMsg => " The legal values for this attribute are ", + ExpectedGenericValue => " SAME_EDGE or OPPOSITE_EDGE ", + TailMsg => "", + MsgSeverity => Failure + ); + end if; + ------------------ DATA_RATE validity check ------------------ + if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then + AttrSRtype <= (others => '1'); + elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then + AttrSRtype <= (others => '0'); + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRTYPE ", + EntityName => "/IOOUT", + GenericValue => SRTYPE, + Unit => "", + ExpectedValueMsg => " The legal values for this attribute are ", + ExpectedGenericValue => " ASYNC or SYNC. ", + TailMsg => "", + MsgSeverity => ERROR + ); + end if; + + AttrSerdes <= AttrSerdes_var; + AttrMode <= AttrMode_var; + AttrDataRateOQ <= AttrDataRateOQ_var; + AttrDataWidth <= AttrDataWidth_var; + AttrDdrClkEdge <= AttrDdrClkEdge_var; + + plgcnt <= AttrDataRateOQ_var & AttrDataWidth_var; + + wait; + end process prcs_init; +--################################################################### +--##### Concurrent exe ##### +--################################################################### + C2p <= (C_dly and AttrDdrClkEdge) or + ((not C_dly) and (not AttrDdrClkEdge)); + C3 <= not C2p; + sel1_4 <= AttrSerdes & loadint & AttrDataRateOQ; + sel5_6 <= AttrSerdes & AttrMode & loadint & AttrDataRateOQ; + LOAD_zd <= loadint; + seloq <= OCE_dly & AttrDataRateOQ & oqsr & oqrev; + + oqsr <= ((AttrSRtype(1) and SR_dly and not (TO_X01(SRVAL_OQ))) + or + (AttrSRtype(1) and REV_dly and (TO_X01(SRVAL_OQ)))); + + oqrev <= ((AttrSRtype(1) and SR_dly and (TO_X01(SRVAL_OQ))) + or + (AttrSRtype(1) and REV_dly and not (TO_X01(SRVAL_OQ)))); + + SHIFTOUT1_zd <= d3rnk2 and AttrMode; + SHIFTOUT2_zd <= d4rnk2 and AttrMode; +--################################################################### +--##### q1rnk2 reg ##### +--################################################################### + prcs_D1_rnk2:process(C_dly, GSR_dly, REV_dly, SR_dly) + variable d1rnk2_var : std_ulogic := TO_X01(INIT_OQ); + variable FIRST_TIME : boolean := true; + begin + if((GSR_dly = '1') or (FIRST_TIME)) then + d1rnk2_var := TO_X01(INIT_OQ); + FIRST_TIME := false; + elsif(GSR_dly = '0') then + case AttrSRtype(1) is + when '1' => + --------------- // async SET/RESET + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_OQ) = '1')))) then + d1rnk2_var := TO_X01(SRVAL_OQ); + elsif(REV_dly = '1') then + d1rnk2_var := not TO_X01(SRVAL_OQ); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(OCE = '1') then + if(rising_edge(C_dly)) then + d1rnk2_var := data1; + end if; + elsif(OCE = '0') then + if(rising_edge(C_dly)) then + d1rnk2_var := OQ_zd; + end if; + end if; + end if; + + when '0' => + --------------- // sync SET/RESET + if(rising_edge(C_dly)) then + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_OQ) = '1')))) then + d1rnk2_var := TO_X01(SRVAL_OQ); + elsif(REV_dly = '1') then + d1rnk2_var := not TO_X01(SRVAL_OQ); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(OCE = '1') then + d1rnk2_var := data1; + elsif(OCE = '0') then + d1rnk2_var := OQ_zd; + end if; + end if; + end if; + + when others => + null; + + end case; + end if; + + d1rnk2 <= d1rnk2_var after DELAY_FFD; + + end process prcs_D1_rnk2; +--################################################################### +--##### d2rnk2 reg ##### +--################################################################### + prcs_D2_rnk2:process(C2p, GSR_dly, REV_dly, SR_dly) + variable d2rnk2_var : std_ulogic := TO_X01(INIT_OQ); + variable FIRST_TIME : boolean := true; + begin + if((GSR_dly = '1') or (FIRST_TIME)) then + d2rnk2_var := TO_X01(INIT_OQ); + FIRST_TIME := false; + elsif(GSR_dly = '0') then + case AttrSRtype(1) is + when '1' => + --------------- // async SET/RESET + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_OQ) = '1')))) then + d2rnk2_var := TO_X01(SRVAL_OQ); + elsif(REV_dly = '1') then + d2rnk2_var := not TO_X01(SRVAL_OQ); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(OCE = '1') then + if(rising_edge(C2p)) then + d2rnk2_var := data2; + end if; + elsif(OCE = '0') then + if(rising_edge(C2p)) then + d2rnk2_var := OQ_zd; + end if; + end if; + end if; + + when '0' => + --------------- // sync SET/RESET + if(rising_edge(C2p)) then + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_OQ) = '1')))) then + d2rnk2_var := TO_X01(SRVAL_OQ); + elsif(REV_dly = '1') then + d2rnk2_var := not TO_X01(SRVAL_OQ); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(OCE = '1') then + d2rnk2_var := data2; + elsif(OCE = '0') then + d2rnk2_var := OQ_zd; + end if; + end if; + end if; + + when others => + null; + + end case; + end if; + + d2rnk2 <= d2rnk2_var after DELAY_FFD; + + end process prcs_D2_rnk2; +--################################################################### +--##### d2nrnk2 reg ##### +--################################################################### + prcs_D2_nrnk2:process(C3, GSR_dly, REV_dly, SR_dly) + variable d2nrnk2_var : std_ulogic := TO_X01(INIT_OQ); + variable FIRST_TIME : boolean := true; + begin + if((GSR_dly = '1') or (FIRST_TIME)) then + d2nrnk2_var := TO_X01(INIT_OQ); + FIRST_TIME := false; + elsif(GSR_dly = '0') then + case AttrSRtype(1) is + when '1' => + --------------- // async SET/RESET + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_OQ) = '1')))) then + d2nrnk2_var := TO_X01(SRVAL_OQ); + elsif(REV_dly = '1') then + d2nrnk2_var := not TO_X01(SRVAL_OQ); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(OCE = '1') then + if(rising_edge(C3)) then + d2nrnk2_var := d2rnk2; + end if; + elsif(OCE = '0') then + if(rising_edge(C3)) then + d2nrnk2_var := OQ_zd; + end if; + end if; + end if; + + when '0' => + --------------- // sync SET/RESET + if(rising_edge(C3)) then + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_OQ) = '1')))) then + d2nrnk2_var := TO_X01(SRVAL_OQ); + elsif(REV_dly = '1') then + d2nrnk2_var := not TO_X01(SRVAL_OQ); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(OCE = '1') then + d2nrnk2_var := d2rnk2; + elsif(OCE = '0') then + d2nrnk2_var := OQ_zd; + end if; + end if; + end if; + + when others => + null; + + end case; + end if; + + d2nrnk2 <= d2nrnk2_var after DELAY_FFD; + + end process prcs_D2_nrnk2; +--################################################################### +--##### d3rnk2, d4rnk2, d5rnk2 and d6rnk2 ##### +--################################################################### + prcs_D3D4D5D6_rnk2:process(C_dly, GSR_dly, SR_dly) + variable d6rnk2_var : std_ulogic := TO_X01(INIT_ORANK2_PARTIAL(3)); + variable d5rnk2_var : std_ulogic := TO_X01(INIT_ORANK2_PARTIAL(2)); + variable d4rnk2_var : std_ulogic := TO_X01(INIT_ORANK2_PARTIAL(1)); + variable d3rnk2_var : std_ulogic := TO_X01(INIT_ORANK2_PARTIAL(0)); + variable FIRST_TIME : boolean := true; + + begin + if((GSR_dly = '1') or (FIRST_TIME)) then + d6rnk2_var := TO_X01(INIT_ORANK2_PARTIAL(3)); + d5rnk2_var := TO_X01(INIT_ORANK2_PARTIAL(2)); + d4rnk2_var := TO_X01(INIT_ORANK2_PARTIAL(1)); + d3rnk2_var := TO_X01(INIT_ORANK2_PARTIAL(0)); + FIRST_TIME := false; + elsif(GSR_dly = '0') then + case AttrSRtype(2) is + when '1' => + --------- // async SET/RESET -- Not full featured FFs + if(SR_dly = '1') then + d6rnk2_var := '0'; + d5rnk2_var := '0'; + d4rnk2_var := '0'; + d3rnk2_var := '0'; + elsif(SR_dly = '0') then + if(rising_edge(C_dly)) then + d6rnk2_var := data6; + d5rnk2_var := data5; + d4rnk2_var := data4; + d3rnk2_var := data3; + end if; + end if; + + when '0' => + --------- // sync SET/RESET -- Not full featured FFs + if(rising_edge(C_dly)) then + if(SR_dly = '1') then + d6rnk2_var := '0'; + d5rnk2_var := '0'; + d4rnk2_var := '0'; + d3rnk2_var := '0'; + elsif(SR_dly = '0') then + d6rnk2_var := data6; + d5rnk2_var := data5; + d4rnk2_var := data4; + d3rnk2_var := data3; + end if; + end if; + + when others => + null; + + end case; + end if; + + d6rnk2 <= d6rnk2_var after DELAY_FFD; + d5rnk2 <= d5rnk2_var after DELAY_FFD; + d4rnk2 <= d4rnk2_var after DELAY_FFD; + d3rnk2 <= d3rnk2_var after DELAY_FFD; + + end process prcs_D3D4D5D6_rnk2; + +--////////////////////////////////////////////////////////////////// +--// First rank of FF for input data // +--////////////////////////////////////////////////////////////////// + +--################################################################### +--##### d1r, d2r, d3r, d4r, d5r and d6r ##### +--################################################################### + prcs_D1D2D3D4D5D6_r:process(CLKDIV_dly, GSR_dly, SR_dly) + variable d6r_var : std_ulogic := TO_X01(INIT_ORANK1(5)); + variable d5r_var : std_ulogic := TO_X01(INIT_ORANK1(4)); + variable d4r_var : std_ulogic := TO_X01(INIT_ORANK1(3)); + variable d3r_var : std_ulogic := TO_X01(INIT_ORANK1(2)); + variable d2r_var : std_ulogic := TO_X01(INIT_ORANK1(1)); + variable d1r_var : std_ulogic := TO_X01(INIT_ORANK1(0)); + variable FIRST_TIME : boolean := true; + + begin + if((GSR_dly = '1') or (FIRST_TIME)) then + d6r_var := TO_X01(INIT_ORANK1(5)); + d5r_var := TO_X01(INIT_ORANK1(4)); + d4r_var := TO_X01(INIT_ORANK1(3)); + d3r_var := TO_X01(INIT_ORANK1(2)); + d2r_var := TO_X01(INIT_ORANK1(1)); + d1r_var := TO_X01(INIT_ORANK1(0)); + FIRST_TIME := false; + elsif(GSR_dly = '0') then + case AttrSRtype(3) is + when '1' => + --------- // async SET/RESET -- Not full featured FFs + if(SR_dly = '1') then + d6r_var := '0'; + d5r_var := '0'; + d4r_var := '0'; + d3r_var := '0'; + d2r_var := '0'; + d1r_var := '0'; + elsif(SR_dly = '0') then + if(rising_edge(CLKDIV_dly)) then + d6r_var := D6_dly; + d5r_var := D5_dly; + d4r_var := D4_dly; + d3r_var := D3_dly; + d2r_var := D2_dly; + d1r_var := D1_dly; + end if; + end if; + + when '0' => + --------- // sync SET/RESET -- Not full featured FFs + if(rising_edge(CLKDIV_dly)) then + if(SR_dly = '1') then + d6r_var := '0'; + d5r_var := '0'; + d4r_var := '0'; + d3r_var := '0'; + d2r_var := '0'; + d1r_var := '0'; + elsif(SR_dly = '0') then + d6r_var := D6_dly; + d5r_var := D5_dly; + d4r_var := D4_dly; + d3r_var := D3_dly; + d2r_var := D2_dly; + d1r_var := D1_dly; + end if; + end if; + + when others => + null; + + end case; + end if; + + d6r <= d6r_var after DELAY_FFCD; + d5r <= d5r_var after DELAY_FFCD; + d4r <= d4r_var after DELAY_FFCD; + d3r <= d3r_var after DELAY_FFCD; + d2r <= d2r_var after DELAY_FFCD; + d1r <= d1r_var after DELAY_FFCD; + + end process prcs_D1D2D3D4D5D6_r; + +--################################################################### +--##### Muxes for 2nd rank of FFS ##### +--################################################################### + prcs_data1234_mux:process(sel1_4, d1r, d2r, d3r, d4r, d2rnk2, + d3rnk2, d4rnk2, d5rnk2, d6rnk2) + + begin + case sel1_4 is + when "100" => + data1 <= d3rnk2 after DELAY_MXR1; + data2 <= d4rnk2 after DELAY_MXR1; + data3 <= d5rnk2 after DELAY_MXR1; + data4 <= d6rnk2 after DELAY_MXR1; + when "110" => + data1 <= d1r after DELAY_MXR1; + data2 <= d2r after DELAY_MXR1; + data3 <= d3r after DELAY_MXR1; + data4 <= d4r after DELAY_MXR1; + when "101" => + data1 <= d2rnk2 after DELAY_MXR1; + data2 <= d3rnk2 after DELAY_MXR1; + data3 <= d4rnk2 after DELAY_MXR1; + data4 <= d5rnk2 after DELAY_MXR1; + when "111" => + data1 <= d1r after DELAY_MXR1; + data2 <= d2r after DELAY_MXR1; + data3 <= d3r after DELAY_MXR1; + data4 <= d4r after DELAY_MXR1; + when others => + data1 <= d3rnk2 after DELAY_MXR1; + data2 <= d4rnk2 after DELAY_MXR1; + data3 <= d5rnk2 after DELAY_MXR1; + data4 <= d6rnk2 after DELAY_MXR1; + end case; + + end process prcs_data1234_mux; + +---------------------------------------------------------------------- + + prcs_data56_mux:process(sel5_6, d5r, d6r, d6rnk2, SHIFTIN1_dly, + SHIFTIN2_dly ) + + begin + case sel5_6 is + when "1000" => + data5 <= SHIFTIN1_dly after DELAY_MXR1; + data6 <= SHIFTIN2_dly after DELAY_MXR1; + when "1010" => + data5 <= d5r after DELAY_MXR1; + data6 <= d6r after DELAY_MXR1; + when "1001" => + data5 <= d6rnk2 after DELAY_MXR1; + data6 <= SHIFTIN1_dly after DELAY_MXR1; + when "1011" => + data5 <= d5r after DELAY_MXR1; + data6 <= d6r after DELAY_MXR1; + when "1100" => + data5 <= '0' after DELAY_MXR1; + data6 <= '0' after DELAY_MXR1; + when "1110" => + data5 <= d5r after DELAY_MXR1; + data6 <= d6r after DELAY_MXR1; + when "1101" => + data5 <= d6rnk2 after DELAY_MXR1; + data6 <= '0' after DELAY_MXR1; + when "1111" => + data5 <= d5r after DELAY_MXR1; + data6 <= d6r after DELAY_MXR1; + + when others => + data5 <= SHIFTIN1_dly after DELAY_MXR1; + data6 <= SHIFTIN2_dly after DELAY_MXR1; + end case; + + end process prcs_data56_mux; +--################################################################### +--##### sdata_edge ###### +--################################################################### + prcs_sdata:process(C_dly, C3, d1rnk2, d2nrnk2) + begin + sdata_edge <= ((d1rnk2 and C_dly) or (d2nrnk2 and C3)) after DELAY_MXD; + end process prcs_sdata; + +--################################################################### +--##### odata_edge ##### +--################################################################### + prcs_odata:process(C_dly, d1rnk2, d2rnk2) + begin + case C_dly is + when '0' => + odata_edge <= d2rnk2 after DELAY_MXD; + when '1' => + odata_edge <= d1rnk2 after DELAY_MXD; + when others => + odata_edge <= d2rnk2 after DELAY_MXD; + end case; + end process prcs_odata; +--################################################################### +--##### ddr_data ###### +--################################################################### + prcs_ddrdata:process(ddr_data, sdata_edge, odata_edge, AttrDdrClkEdge) + begin + ddr_data <= ((odata_edge and (not AttrDdrClkEdge)) or + (sdata_edge and AttrDdrClkEdge)) after DELAY_MXD; + end process prcs_ddrdata; + +---//////////////////////////////////////////////////////////////////// +--- Outputs +---//////////////////////////////////////////////////////////////////// + prcs_OQ_mux:process(seloq, d1rnk2, ddr_data, OQ_zd, GSR_dly) + + variable FIRST_TIME : boolean := true; + + begin + if((GSR_dly = '1') or (FIRST_TIME)) then + OQ_zd <= TO_X01(INIT_OQ); + FIRST_TIME := false; + elsif(GSR_dly = '0') then + case seloq is + when "0001" | "0101"| "1001" | "1101" | + "0X01" | "1X01"| "XX01" | "X001" | + "X101" + => + OQ_zd <= '1' after DELAY_MXD; + + when "0010" | "0110"| "1010" | "1110" | + "0X10" | "1X10"| "XX10" | "X010" | + "X110" + => + OQ_zd <= '0' after DELAY_MXD; + + when "0011" | "0111"| "1011" | "1111" | + "0X11" | "1X11"| "XX11" | "X011" | + "X111" + => + OQ_zd <= '0' after DELAY_MXD; + + when "0000" => + OQ_zd <= OQ_zd after DELAY_MXD; + + when "0100" => + OQ_zd <= OQ_zd after DELAY_MXD; + + when "1000" => + OQ_zd <= ddr_data after DELAY_MXD; + + when "1100" => + OQ_zd <= d1rnk2 after DELAY_MXD; + + when others => +-- CR 192533 the below "now > DEALY_MXD" is added since +-- the INIT value of OQ_zd is getting wiped off by ddr_data=X at time 0. +-- At time 0, seloq is XXXX + if(now > DELAY_MXD) then + OQ_zd <= ddr_data after DELAY_MXD; + end if; + + end case; + + end if; + + end process prcs_OQ_mux; +---------------------------------------------------------------------- +----------- Instant PLG -------------------------------------- +---------------------------------------------------------------------- + INST_PLG : PLG + generic map ( + SRTYPE => SRTYPE, + INIT_LOADCNT => INIT_LOADCNT + ) + port map ( + LOAD => loadint, + + C23 => c23, + C45 => c45, + C67 => c67, + CLK => C_dly, + CLKDIV => CLKDIV_dly, + RST => SR_dly, + SEL => sel + ); + +--################################################################### +--##### Set value of the counter in PLG ##### +--################################################################### + prcs_plg_plgcnt:process + begin + wait for 10 ps; + case plgcnt is + when "00100" => + c23<='0'; c45<='0'; c67<='0'; sel<="00"; + when "00110" => + c23<='1'; c45<='0'; c67<='0'; sel<="00"; + when "01000" => + c23<='0'; c45<='0'; c67<='0'; sel<="01"; + when "01010" => + c23<='0'; c45<='1'; c67<='0'; sel<="01"; + when "10010" => + c23<='0'; c45<='0'; c67<='0'; sel<="00"; + when "10011" => + c23<='1'; c45<='0'; c67<='0'; sel<="00"; + when "10100" => + c23<='0'; c45<='0'; c67<='0'; sel<="01"; + when "10101" => + c23<='0'; c45<='1'; c67<='0'; sel<="01"; + when "10110" => + c23<='0'; c45<='0'; c67<='0'; sel<="10"; + when "10111" => + c23<='0'; c45<='0'; c67<='1'; sel<="10"; + when "11000" => + c23<='0'; c45<='0'; c67<='0'; sel<="11"; + when others => + assert FALSE + report "WARNING : DATA_WIDTH or DATA_RATE has illegal values." + severity Warning; + end case; + wait; + end process prcs_plg_plgcnt; + + +--#################################################################### + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(OQ_zd, LOAD_zd, SHIFTOUT1_zd, SHIFTOUT2_zd) + begin + OQ <= OQ_zd; + LOAD <= LOAD_zd; + SHIFTOUT1 <= SHIFTOUT1_zd; + SHIFTOUT2 <= SHIFTOUT2_zd; + end process prcs_output; +--#################################################################### + + +end IOOUT_V; + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_arith.all; + + +library unisim; +use unisim.vpkg.all; + +entity IOT is + + generic( + + DATA_RATE_TQ : string; + TRISTATE_WIDTH : integer := 1; + DDR_CLK_EDGE : string := "SAME_EDGE"; + INIT_TQ : bit := '0'; + INIT_TRANK1 : bit_vector(3 downto 0) := "0000"; + SRVAL_TQ : bit := '1'; + + SRTYPE : string := "ASYNC" + ); + + port( + TQ : out std_ulogic; + + C : in std_ulogic; + CLKDIV : in std_ulogic; + LOAD : in std_ulogic; + REV : in std_ulogic; + SR : in std_ulogic; + T1 : in std_ulogic; + T2 : in std_ulogic; + T3 : in std_ulogic; + T4 : in std_ulogic; + TCE : in std_ulogic + ); + +end IOT; + +architecture IOT_V OF IOT is + + + constant GSR_PULSE_TIME : time := 1 ns; + + constant DELAY_FFD : time := 1 ps; + constant DELAY_MXD : time := 1 ps; + constant DELAY_ZERO : time := 0 ps; + constant DELAY_ONE : time := 1 ps; + constant SWALLOW_PULSE : time := 2 ps; + + constant MAX_DATAWIDTH : integer := 4; + + signal C_ipd : std_ulogic := 'X'; + signal CLKDIV_ipd : std_ulogic := 'X'; + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := 'X'; + signal LOAD_ipd : std_ulogic := 'X'; + signal T1_ipd : std_ulogic := 'X'; + signal T2_ipd : std_ulogic := 'X'; + signal T3_ipd : std_ulogic := 'X'; + signal T4_ipd : std_ulogic := 'X'; + signal TCE_ipd : std_ulogic := 'X'; + signal REV_ipd : std_ulogic := 'X'; + signal SR_ipd : std_ulogic := 'X'; + + signal C_dly : std_ulogic := 'X'; + signal CLKDIV_dly : std_ulogic := 'X'; + signal GSR_dly : std_ulogic := 'X'; + signal LOAD_dly : std_ulogic := 'X'; + signal T1_dly : std_ulogic := 'X'; + signal T2_dly : std_ulogic := 'X'; + signal T3_dly : std_ulogic := 'X'; + signal T4_dly : std_ulogic := 'X'; + signal TCE_dly : std_ulogic := 'X'; + signal REV_dly : std_ulogic := 'X'; + signal SR_dly : std_ulogic := 'X'; + + signal TQ_zd : std_ulogic := TO_X01(INIT_TQ); + + signal AttrDataRateTQ : std_logic_vector(1 downto 0) := (others => 'X'); + signal AttrTriStateWidth : std_logic_vector(1 downto 0) := (others => 'X'); + signal AttrDdrClkEdge : std_ulogic := 'X'; + + signal AttrSRtype : std_logic_vector(1 downto 0) := (others => '1'); + + signal t1r : std_ulogic := 'X'; + signal t2r : std_ulogic := 'X'; + signal t3r : std_ulogic := 'X'; + signal t4r : std_ulogic := 'X'; + + signal qt1 : std_ulogic := 'X'; + signal qt2 : std_ulogic := 'X'; + signal qt2n : std_ulogic := 'X'; + + signal data1 : std_ulogic := 'X'; + signal data2 : std_ulogic := 'X'; + + signal sdata_edge : std_ulogic := 'X'; + signal odata_edge : std_ulogic := 'X'; + signal ddr_data : std_ulogic := 'X'; + + signal C2p : std_ulogic := 'X'; + signal C3 : std_ulogic := 'X'; + + signal tqsel : std_logic_vector(6 downto 0) := (others => 'X'); + signal tqsr : std_ulogic := 'X'; + signal tqrev : std_ulogic := 'X'; + + signal sel : std_logic_vector(4 downto 0) := (others => 'X'); + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + C_dly <= C after 0 ps; + CLKDIV_dly <= CLKDIV after 0 ps; + GSR_dly <= GSR after 0 ps; + LOAD_dly <= LOAD after 0 ps; + REV_dly <= REV after 0 ps; + SR_dly <= SR after 0 ps; + T1_dly <= T1 after 0 ps; + T2_dly <= T2 after 0 ps; + T3_dly <= T3 after 0 ps; + T4_dly <= T4 after 0 ps; + TCE_dly <= TCE after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + variable AttrDataRateTQ_var : std_logic_vector(1 downto 0) := (others => 'X'); + variable AttrTriStateWidth_var : std_logic_vector(1 downto 0) := (others => 'X'); + variable AttrDdrClkEdge_var : std_ulogic := 'X'; + + begin + + ------------------ DATA_RATE_TQ validity check ------------------ +-- FP check with Paul + if((DATA_RATE_TQ = "BUF") or (DATA_RATE_TQ = "buf")) then + AttrDataRateTQ_var := "00"; + elsif((DATA_RATE_TQ = "SDR") or (DATA_RATE_TQ = "sdr")) then + AttrDataRateTQ_var := "01"; + elsif((DATA_RATE_TQ = "DDR") or (DATA_RATE_TQ = "ddr")) then + AttrDataRateTQ_var := "10"; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DATA_RATE_TQ ", + EntityName => "/X_IOOUT", + GenericValue => DATA_RATE_TQ, + Unit => "", + ExpectedValueMsg => " The legal values for this attribute are ", + ExpectedGenericValue => " BUF, SDR or DDR. ", + TailMsg => "", + MsgSeverity => Failure + ); + end if; + + + ------------------ TRISTATE_WIDTH validity check ------------------ + if((TRISTATE_WIDTH = 1) or (TRISTATE_WIDTH = 2) or (TRISTATE_WIDTH = 4)) then + case TRISTATE_WIDTH is + when 1 => AttrTriStateWidth_var := "00"; + when 2 => AttrTriStateWidth_var := "01"; + when 4 => AttrTriStateWidth_var := "10"; + when others => + null; + end case; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " TRISTATE_WIDTH ", + EntityName => "/IOT", + GenericValue => TRISTATE_WIDTH, + Unit => "", + ExpectedValueMsg => " The legal values for this attribute are ", + ExpectedGenericValue => " 1, 2 or 4 ", + TailMsg => "", + MsgSeverity => Failure + ); + end if; + + ------------ TRISTATE_WIDTH /DATA_RATE combination check ------------ +-- CR 458156 -- enabled TRISTATE_WIDTH to be 1 in DDR mode. + if((DATA_RATE_TQ = "DDR") or (DATA_RATE_TQ = "ddr")) then + case (TRISTATE_WIDTH) is + when 1|2|4 => null; + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " TRISTATE_WIDTH ", + EntityName => "/IOT", + GenericValue => TRISTATE_WIDTH, + Unit => "", + ExpectedValueMsg => " The legal values for this attribute in DDR mode are ", + ExpectedGenericValue => "1, 2 or 4", + TailMsg => "", + MsgSeverity => Failure + ); + end case; + end if; + + if((DATA_RATE_TQ = "SDR") or (DATA_RATE_TQ = "sdr")) then + case (TRISTATE_WIDTH) is + when 1 => null; + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " TRISTATE_WIDTH ", + EntityName => "/IOT", + GenericValue => TRISTATE_WIDTH, + Unit => "", + ExpectedValueMsg => " The legal value for this attribute in SDR mode is", + ExpectedGenericValue => " 1. ", + TailMsg => "", + MsgSeverity => Failure + ); + end case; + end if; + + if((DATA_RATE_TQ = "BUF") or (DATA_RATE_TQ = "buf")) then + case (TRISTATE_WIDTH) is + when 1 => null; + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " TRISTATE_WIDTH ", + EntityName => "/IOT", + GenericValue => TRISTATE_WIDTH, + Unit => "", + ExpectedValueMsg => " The legal value for this attribute in BUF mode is", + ExpectedGenericValue => " 1. ", + TailMsg => "", + MsgSeverity => Failure + ); + end case; + end if; + + ------------------ DDR_CLK_EDGE validity check ------------------ + + if((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then + AttrDdrClkEdge_var := '1'; + elsif((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then + AttrDdrClkEdge_var := '0'; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DDR_CLK_EDGE ", + EntityName => "/IOT", + GenericValue => DDR_CLK_EDGE, + Unit => "", + ExpectedValueMsg => " The legal values for this attribute are ", + ExpectedGenericValue => " SAME_EDGE or OPPOSITE_EDGE ", + TailMsg => "", + MsgSeverity => Failure + ); + end if; + ------------------ DATA_RATE validity check ------------------ + if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then + AttrSRtype <= (others => '1'); + elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then + AttrSRtype <= (others => '0'); + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRTYPE ", + EntityName => "/IOT", + GenericValue => SRTYPE, + Unit => "", + ExpectedValueMsg => " The legal values for this attribute are ", + ExpectedGenericValue => " ASYNC or SYNC. ", + TailMsg => "", + MsgSeverity => ERROR + ); + end if; +--------------------------------------------------------------------- + AttrDataRateTQ <= AttrDataRateTQ_var; + AttrTriStateWidth <= AttrTriStateWidth_var; + AttrDdrClkEdge <= AttrDdrClkEdge_var; + wait; + end process prcs_init; +--################################################################### +--##### Concurrent exe ##### +--################################################################### + C2p <= (C_dly and AttrDdrClkEdge) or + ((not C_dly) and (not AttrDdrClkEdge)); + C3 <= not C2p; + + tqsel <= TCE & AttrDataRateTQ & AttrTriStateWidth & tqsr & tqrev; + + sel <= load & AttrDataRateTQ & AttrTriStateWidth; + + tqsr <= ((AttrSRtype(1) and SR_dly and not (TO_X01(SRVAL_TQ))) + or + (AttrSRtype(1) and REV_dly and (TO_X01(SRVAL_TQ)))); + + tqrev <= ((AttrSRtype(1) and SR_dly and (TO_X01(SRVAL_TQ))) + or + (AttrSRtype(1) and REV_dly and not (TO_X01(SRVAL_TQ)))); + +--################################################################### +--##### qt1 reg ##### +--################################################################### + prcs_qt1_reg:process(C_dly, GSR_dly, REV_dly, SR_dly) + variable qt1_var : std_ulogic := TO_X01(INIT_TQ); + variable FIRST_TIME : boolean := true; + begin + if((GSR_dly = '1') or (FIRST_TIME)) then + qt1_var := TO_X01(INIT_TQ); + FIRST_TIME := false; + elsif(GSR_dly = '0') then + case AttrSRtype(1) is + when '1' => + --------------- // async SET/RESET + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_TQ) = '1')))) then + qt1_var := TO_X01(SRVAL_TQ); + elsif(REV_dly = '1') then + qt1_var := not TO_X01(SRVAL_TQ); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(TCE_dly = '1') then + if(rising_edge(C_dly)) then + qt1_var := data1; + end if; + end if; + end if; + + when '0' => + --------------- // sync SET/RESET + if(rising_edge(C_dly)) then + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_TQ) = '1')))) then + qt1_var := TO_X01(SRVAL_TQ); + elsif(REV_dly = '1') then + qt1_var := not TO_X01(SRVAL_TQ); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(TCE_dly = '1') then + qt1_var := data1; + end if; + end if; + end if; + + when others => + null; + + end case; + end if; + + qt1 <= qt1_var after DELAY_FFD; + + end process prcs_qt1_reg; +--################################################################### +--##### qt2 reg ##### +--################################################################### + prcs_qt2_reg:process(C2p, GSR_dly, REV_dly, SR_dly) + variable qt2_var : std_ulogic := TO_X01(INIT_TQ); + variable FIRST_TIME : boolean := true; + begin + if((GSR_dly = '1') or (FIRST_TIME)) then + qt2_var := TO_X01(INIT_TQ); + FIRST_TIME := false; + elsif(GSR_dly = '0') then + case AttrSRtype(1) is + when '1' => + --------------- // async SET/RESET + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_TQ) = '1')))) then + qt2_var := TO_X01(SRVAL_TQ); + elsif(REV_dly = '1') then + qt2_var := not TO_X01(SRVAL_TQ); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(TCE_dly = '1') then + if(rising_edge(C2p)) then + qt2_var := data2; + end if; + end if; + end if; + + when '0' => + --------------- // sync SET/RESET + if(rising_edge(C2p)) then + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_TQ) = '1')))) then + qt2_var := TO_X01(SRVAL_TQ); + elsif(REV_dly = '1') then + qt2_var := not TO_X01(SRVAL_TQ); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(TCE_dly = '1') then + qt2_var := data2; + end if; + end if; + end if; + + when others => + null; + + end case; + end if; + + qt2 <= qt2_var after DELAY_FFD; + + end process prcs_qt2_reg; + +--################################################################### +--##### qt2n reg ##### +--################################################################### + prcs_qt2n_reg:process(C3, GSR_dly, REV_dly, SR_dly) + variable qt2n_var : std_ulogic := TO_X01(INIT_TQ); + variable FIRST_TIME : boolean := true; + begin + if((GSR_dly = '1') or (FIRST_TIME)) then + qt2n_var := TO_X01(INIT_TQ); + FIRST_TIME := false; + elsif(GSR_dly = '0') then + case AttrSRtype(1) is + when '1' => + --------------- // async SET/RESET + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_TQ) = '1')))) then + qt2n_var := TO_X01(SRVAL_TQ); + elsif(REV_dly = '1') then + qt2n_var := not TO_X01(SRVAL_TQ); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(TCE_dly = '1') then + if(rising_edge(C3)) then + qt2n_var := qt2; + end if; + end if; + end if; + + when '0' => + --------------- // sync SET/RESET + if(rising_edge(C3)) then + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_TQ) = '1')))) then + qt2n_var := TO_X01(SRVAL_TQ); + elsif(REV_dly = '1') then + qt2n_var := not TO_X01(SRVAL_TQ); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(TCE_dly = '1') then + qt2n_var := qt2; + end if; + end if; + end if; + + when others => + null; + + end case; + end if; + + qt2n <= qt2n_var after DELAY_FFD; + + end process prcs_qt2n_reg; + +--################################################################### +--##### t1r, t2r, t3r and tr4 ##### +--################################################################### + prcs_t1rt2rt3rt4r_rnk1:process(CLKDIV_dly, GSR_dly, SR_dly) + variable t1r_var : std_ulogic := TO_X01(INIT_TRANK1(0)); + variable t2r_var : std_ulogic := TO_X01(INIT_TRANK1(1)); + variable t3r_var : std_ulogic := TO_X01(INIT_TRANK1(2)); + variable t4r_var : std_ulogic := TO_X01(INIT_TRANK1(3)); + variable FIRST_TIME : boolean := true; + + begin + if((GSR_dly = '1') or (FIRST_TIME)) then + t1r_var := TO_X01(INIT_TRANK1(0)); + t2r_var := TO_X01(INIT_TRANK1(1)); + t3r_var := TO_X01(INIT_TRANK1(2)); + t4r_var := TO_X01(INIT_TRANK1(3)); + FIRST_TIME := false; + elsif(GSR_dly = '0') then + case AttrSRtype(1) is + when '1' => + --------- // async SET/RESET -- Not full featured FFs + if(SR_dly = '1') then + t1r_var := '0'; + t2r_var := '0'; + t3r_var := '0'; + t4r_var := '0'; + elsif(SR_dly = '0') then + if(rising_edge(CLKDIV_dly)) then + t1r_var := T1_dly; + t2r_var := T2_dly; + t3r_var := T3_dly; + t4r_var := T4_dly; + end if; + end if; + + when '0' => + --------- // sync SET/RESET -- Not full featured FFs + if(rising_edge(C_dly)) then + if(SR_dly = '1') then + t1r_var := '0'; + t2r_var := '0'; + t3r_var := '0'; + t4r_var := '0'; + elsif(SR_dly = '0') then + t1r_var := T1_dly; + t2r_var := T2_dly; + t3r_var := T3_dly; + t4r_var := T4_dly; + end if; + end if; + + when others => + null; + + end case; + end if; + + t1r <= t1r_var after DELAY_FFD; + t2r <= t2r_var after DELAY_FFD; + t3r <= t3r_var after DELAY_FFD; + t4r <= t4r_var after DELAY_FFD; + + end process prcs_t1rt2rt3rt4r_rnk1; + +--################################################################### +--##### Muxes for tristate outputs ##### +--################################################################### + prcs_data1_mux:process(sel, T1_dly, t1r, t3r) + begin + if (now > GSR_PULSE_TIME) then + case sel is + when "00000" | "10000" | "X0000" | + "00100" | "10100" | "X0100" | + "01001" | "11001" => + data1 <= T1_dly after DELAY_MXD; + when "01010" => + data1 <= t3r after DELAY_MXD; + when "11010" => + data1 <= t1r after DELAY_MXD; +-- CR 458156 -- allow/enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings, + when "01000" | "11000" | "X1000" => + when others => + assert FALSE + report "WARNING : DATA_RATE_TQ and/or TRISTATE_WIDTH have illegal values." + severity Warning; + end case; + end if; + end process prcs_data1_mux; +--------------------------------------------------------------- + prcs_data2_mux:process(sel, T2_dly, t2r, t4r) + begin + if (now > GSR_PULSE_TIME) then + case sel is + when "00000" | "00100" | "10000" | + "10100" | "X0000" | "X0100" | + "00X00" | "10X00" | "X0X00" | + "01001" | "11001" | "X1001" => + data2 <= T2_dly after DELAY_MXD; + when "01010" => + data2 <= t4r after DELAY_MXD; + when "11010" => + data2 <= t2r after DELAY_MXD; +-- CR 458156 -- allow/enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings, + when "01000" | "11000" | "X1000" => + when others => + assert FALSE + report "WARNING : DATA_RATE_TQ and/or TRISTATE_WIDTH have illegal values." + severity Warning; + end case; + end if; + end process prcs_data2_mux; + +--################################################################### +--##### sdata_edge ###### +--################################################################### + prcs_sdata:process(C_dly, C3, qt1, qt2n) + begin + sdata_edge <= ((qt1 and C_dly) or (qt2n and C3)) after DELAY_MXD; + end process prcs_sdata; + +--################################################################### +--##### odata_edge ##### +--################################################################### + prcs_odata:process(C_dly, qt1, qt2) + begin + case C_dly is + when '0' => + odata_edge <= qt2 after DELAY_MXD; + when '1' => + odata_edge <= qt1 after DELAY_MXD; + when others => + odata_edge <= '0' after DELAY_ZERO; + end case; + end process prcs_odata; +--################################################################### +--##### ddr_data ###### +--################################################################### + prcs_ddrdata:process(ddr_data, sdata_edge, odata_edge, AttrDdrClkEdge) + begin + ddr_data <= ((odata_edge and (not AttrDdrClkEdge)) or + (sdata_edge and AttrDdrClkEdge)) after DELAY_ONE; + end process prcs_ddrdata; + +---//////////////////////////////////////////////////////////////////// +--- Outputs +---//////////////////////////////////////////////////////////////////// + prcs_TQ_mux:process(tqsel, data1, ddr_data, qt1, GSR_dly) + + variable FIRST_TIME : boolean := true; + + begin + if((GSR_dly = '1') or (FIRST_TIME)) then + TQ_zd <= TO_X01(INIT_TQ); + FIRST_TIME := false; + elsif(GSR_dly = '0') then + if((tqsel(5 downto 4) = "01") and (tqsel(1 downto 0) = "01")) then + TQ_zd <= '1' after DELAY_ONE; + elsif((tqsel(5 downto 4) = "10") and (tqsel(1 downto 0) = "01")) then + TQ_zd <= '1' after DELAY_ONE; + elsif((tqsel(5 downto 4) = "01") and (tqsel(1 downto 0) = "10")) then + TQ_zd <= '0' after DELAY_ONE; + elsif((tqsel(5 downto 4) = "10") and (tqsel(1 downto 0) = "10")) then + TQ_zd <= '0' after DELAY_ONE; + elsif((tqsel(5 downto 4) = "01") and (tqsel(1 downto 0) = "11")) then + TQ_zd <= '0' after DELAY_ONE; + elsif((tqsel(5 downto 4) = "10") and (tqsel(1 downto 0) = "11")) then + TQ_zd <= '0' after DELAY_ONE; + elsif(tqsel(5 downto 2) = "0000") then + TQ_zd <= data1 after DELAY_ONE; + else + + case tqsel is +-- when "-01--01" | "-10--01" => +-- TQ_zd <= '1' after DELAY_ONE; +-- when "-01--10" | "-10--10" | "-01--11" | "-10--11" => +-- TQ_zd <= '0' after DELAY_ONE; +-- when "-----11" => +-- TQ_zd <= '0' after DELAY_ONE; +-- when "-0000--" => +-- TQ_zd <= data1 after DELAY_ONE; + when "0010000" | "0100100" | "0101000" => + TQ_zd <= TQ_zd after DELAY_ONE; + when "1010000" => + TQ_zd <= qt1 after DELAY_ONE; + when "1100100" | "1101000" => + TQ_zd <= ddr_data after DELAY_ONE; + when others => + TQ_zd <= ddr_data after DELAY_ONE; + end case; + end if; + end if; + end process prcs_TQ_mux; +--#################################################################### + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(TQ_zd, GSR_dly) + variable FIRST_TIME : boolean := true; + begin + TQ <= TQ_zd after SWALLOW_PULSE; + end process prcs_output; +--#################################################################### + + +end IOT_V; + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_arith.all; + + +library unisim; +use unisim.vpkg.all; + +----- CELL OSERDES ----- +-- //////////////////////////////////////////////////////////// +-- //////////////////////// OSERDES ///////////////////////// +-- //////////////////////////////////////////////////////////// + +entity OSERDES is + + generic( + + DDR_CLK_EDGE : string := "SAME_EDGE"; + INIT_LOADCNT : bit_vector(3 downto 0) := "0000"; + INIT_ORANK1 : bit_vector(5 downto 0) := "000000"; + INIT_ORANK2_PARTIAL : bit_vector(3 downto 0) := "0000"; + INIT_TRANK1 : bit_vector(3 downto 0) := "0000"; + SERDES : boolean := TRUE; + SRTYPE : string := "ASYNC"; + + DATA_RATE_OQ : string := "DDR"; + DATA_RATE_TQ : string := "DDR"; + DATA_WIDTH : integer := 4; + INIT_OQ : bit := '0'; + INIT_TQ : bit := '0'; + SERDES_MODE : string := "MASTER"; + SRVAL_OQ : bit := '0'; + SRVAL_TQ : bit := '0'; + TRISTATE_WIDTH : integer := 4 + ); + + + port( + OQ : out std_ulogic; + SHIFTOUT1 : out std_ulogic; + SHIFTOUT2 : out std_ulogic; + TQ : out std_ulogic; + + CLK : in std_ulogic; + CLKDIV : in std_ulogic; + D1 : in std_ulogic; + D2 : in std_ulogic; + D3 : in std_ulogic; + D4 : in std_ulogic; + D5 : in std_ulogic; + D6 : in std_ulogic; + OCE : in std_ulogic; + REV : in std_ulogic; + SHIFTIN1 : in std_ulogic; + SHIFTIN2 : in std_ulogic; + SR : in std_ulogic; + T1 : in std_ulogic; + T2 : in std_ulogic; + T3 : in std_ulogic; + T4 : in std_ulogic; + TCE : in std_ulogic + ); + +end OSERDES; + +architecture OSERDES_V OF OSERDES is + + +component IOOUT + generic( + SERDES : boolean; + SERDES_MODE : string; + DATA_RATE_OQ : string; + DATA_WIDTH : integer; + DDR_CLK_EDGE : string; + INIT_OQ : bit; + SRVAL_OQ : bit; + INIT_ORANK1 : bit_vector(5 downto 0); + INIT_ORANK2_PARTIAL : bit_vector(3 downto 0); + INIT_LOADCNT : bit_vector(3 downto 0); + SRTYPE : string + + ); + port( + OQ : out std_ulogic; + LOAD : out std_ulogic; + SHIFTOUT1 : out std_ulogic; + SHIFTOUT2 : out std_ulogic; + + C : in std_ulogic; + CLKDIV : in std_ulogic; + D1 : in std_ulogic; + D2 : in std_ulogic; + D3 : in std_ulogic; + D4 : in std_ulogic; + D5 : in std_ulogic; + D6 : in std_ulogic; + OCE : in std_ulogic; + REV : in std_ulogic; + SR : in std_ulogic; + SHIFTIN1 : in std_ulogic; + SHIFTIN2 : in std_ulogic + ); + +end component; + +component IOT + generic( + DATA_RATE_TQ : string; + TRISTATE_WIDTH : integer; + DDR_CLK_EDGE : string; + INIT_TQ : bit; + INIT_TRANK1 : bit_vector(3 downto 0); + SRVAL_TQ : bit; + SRTYPE : string + ); + port( + TQ : out std_ulogic; + + C : in std_ulogic; + CLKDIV : in std_ulogic; + LOAD : in std_ulogic; + REV : in std_ulogic; + SR : in std_ulogic; + T1 : in std_ulogic; + T2 : in std_ulogic; + T3 : in std_ulogic; + T4 : in std_ulogic; + TCE : in std_ulogic + ); + +end component; + + constant SYNC_PATH_DELAY : time := 100 ps; + + signal load_int : std_ulogic := 'X'; + + signal CLK_ipd : std_ulogic := 'X'; + signal CLKDIV_ipd : std_ulogic := 'X'; + signal D1_ipd : std_ulogic := 'X'; + signal D2_ipd : std_ulogic := 'X'; + signal D3_ipd : std_ulogic := 'X'; + signal D4_ipd : std_ulogic := 'X'; + signal D5_ipd : std_ulogic := 'X'; + signal D6_ipd : std_ulogic := 'X'; + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := 'X'; + signal OCE_ipd : std_ulogic := 'X'; + signal REV_ipd : std_ulogic := 'X'; + signal SR_ipd : std_ulogic := 'X'; + signal SHIFTIN1_ipd : std_ulogic := 'X'; + signal SHIFTIN2_ipd : std_ulogic := 'X'; + signal TCE_ipd : std_ulogic := 'X'; + signal T1_ipd : std_ulogic := 'X'; + signal T2_ipd : std_ulogic := 'X'; + signal T3_ipd : std_ulogic := 'X'; + signal T4_ipd : std_ulogic := 'X'; + + signal CLK_dly : std_ulogic := 'X'; + signal CLKDIV_dly : std_ulogic := 'X'; + signal D1_dly : std_ulogic := 'X'; + signal D2_dly : std_ulogic := 'X'; + signal D3_dly : std_ulogic := 'X'; + signal D4_dly : std_ulogic := 'X'; + signal D5_dly : std_ulogic := 'X'; + signal D6_dly : std_ulogic := 'X'; + signal GSR_dly : std_ulogic := 'X'; + signal OCE_dly : std_ulogic := 'X'; + signal REV_dly : std_ulogic := 'X'; + signal SR_dly : std_ulogic := 'X'; + signal SHIFTIN1_dly : std_ulogic := 'X'; + signal SHIFTIN2_dly : std_ulogic := 'X'; + signal TCE_dly : std_ulogic := 'X'; + signal T1_dly : std_ulogic := 'X'; + signal T2_dly : std_ulogic := 'X'; + signal T3_dly : std_ulogic := 'X'; + signal T4_dly : std_ulogic := 'X'; + + signal CLKD : std_ulogic := 'X'; + signal CLKDIVD : std_ulogic := 'X'; + + signal OQ_zd : std_ulogic := 'X'; + signal SHIFTOUT1_zd : std_ulogic := 'X'; + signal SHIFTOUT2_zd : std_ulogic := 'X'; + signal TQ_zd : std_ulogic := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + CLK_dly <= CLK after 0 ps; + CLKDIV_dly <= CLKDIV after 0 ps; + D1_dly <= D1 after 100 ps; + D2_dly <= D2 after 100 ps; + D3_dly <= D3 after 100 ps; + D4_dly <= D4 after 100 ps; + D5_dly <= D5 after 100 ps; + D6_dly <= D6 after 100 ps; + GSR_dly <= GSR after 0 ps; + OCE_dly <= OCE after 0 ps; + REV_dly <= REV after 0 ps; + SHIFTIN1_dly <= SHIFTIN1 after 0 ps; + SHIFTIN2_dly <= SHIFTIN2 after 0 ps; + SR_dly <= SR after 0 ps; + T1_dly <= T1 after 100 ps; + T2_dly <= T2 after 100 ps; + T3_dly <= T3 after 100 ps; + T4_dly <= T4 after 100 ps; + TCE_dly <= TCE after 0 ps; + + +-- Delay the clock 100 ps to match the HW + CLKD <= CLK_dly after 0 ps; + CLKDIVD <= CLKDIV_dly after 0 ps; +------------------------------------------------------------------ +----------- Instant IOOUT ----------------------------------- +------------------------------------------------------------------ + INST_IOOUT: IOOUT + generic map ( + SERDES => SERDES, + SERDES_MODE => SERDES_MODE, + DATA_RATE_OQ => DATA_RATE_OQ, + DATA_WIDTH => DATA_WIDTH, + DDR_CLK_EDGE => DDR_CLK_EDGE, + INIT_OQ => INIT_OQ, + SRVAL_OQ => SRVAL_OQ, + INIT_ORANK1 => INIT_ORANK1, + INIT_ORANK2_PARTIAL => INIT_ORANK2_PARTIAL, + INIT_LOADCNT => INIT_LOADCNT, + SRTYPE => SRTYPE + ) + port map ( + OQ => OQ_zd, + LOAD => LOAD_int, + SHIFTOUT1 => SHIFTOUT1_zd, + SHIFTOUT2 => SHIFTOUT2_zd, + C => CLKD, + CLKDIV => CLKDIVD, + D1 => D1_dly, + D2 => D2_dly, + D3 => D3_dly, + D4 => D4_dly, + D5 => D5_dly, + D6 => D6_dly, + OCE => OCE_dly, + REV => REV_dly, + SR => SR_dly, + SHIFTIN1 => SHIFTIN1_dly, + SHIFTIN2 => SHIFTIN2_dly + ); +------------------------------------------------------------------ +----------- Instant TRI_OUT ---------------------------------- +------------------------------------------------------------------ + INST_IOT: IOT + generic map ( + DATA_RATE_TQ => DATA_RATE_TQ, + TRISTATE_WIDTH => TRISTATE_WIDTH, + DDR_CLK_EDGE => DDR_CLK_EDGE, + INIT_TQ => INIT_TQ, + INIT_TRANK1 => INIT_TRANK1, + SRVAL_TQ => SRVAL_TQ, + SRTYPE => SRTYPE + ) + port map ( + TQ => TQ_zd, + + C => CLKD, + CLKDIV => CLKDIVD, + LOAD => LOAD_int, + REV => REV_dly, + SR => SR_dly, + T1 => T1_dly, + T2 => T2_dly, + T3 => T3_dly, + T4 => T4_dly, + TCE => TCE_dly + ); + +--#################################################################### + + prcs_output:process + begin + OQ <= OQ_zd after SYNC_PATH_DELAY; + SHIFTOUT1 <= SHIFTOUT1_zd after SYNC_PATH_DELAY; + SHIFTOUT2 <= SHIFTOUT2_zd after SYNC_PATH_DELAY; + TQ <= TQ_zd after SYNC_PATH_DELAY; + wait on OQ_zd, SHIFTOUT1_zd, SHIFTOUT2_zd, TQ_zd; + end process prcs_output; + +end OSERDES_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / Phase-Matched Clock Divider +-- /___/ /\ Filename : PMCD.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:18:21 PST 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 06/20/07 - generate clka1d2 clka1d4 clka1d8 in same block to remove delta delay (CR440337) +-- End Revision + +----- CELL PMCD ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + + +library unisim; +use unisim.vpkg.all; + +entity PMCD is + + generic( + EN_REL : boolean := FALSE; + RST_DEASSERT_CLK : string := "CLKA" + ); + + port( + CLKA1 : out std_ulogic; + CLKA1D2 : out std_ulogic; + CLKA1D4 : out std_ulogic; + CLKA1D8 : out std_ulogic; + CLKB1 : out std_ulogic; + CLKC1 : out std_ulogic; + CLKD1 : out std_ulogic; + + CLKA : in std_ulogic; + CLKB : in std_ulogic; + CLKC : in std_ulogic; + CLKD : in std_ulogic; + REL : in std_ulogic; + RST : in std_ulogic + ); + +end PMCD; + +architecture PMCD_V OF PMCD is + + + constant SYNC_PATH_DELAY : time := 100 ps; + + signal CLKA_ipd : std_ulogic := 'X'; + signal CLKB_ipd : std_ulogic := 'X'; + signal CLKC_ipd : std_ulogic := 'X'; + signal CLKD_ipd : std_ulogic := 'X'; + + signal REL_ipd : std_ulogic := 'X'; + signal RST_ipd : std_ulogic := 'X'; + + signal CLKA_dly : std_ulogic := 'X'; + signal CLKB_dly : std_ulogic := 'X'; + signal CLKC_dly : std_ulogic := 'X'; + signal CLKD_dly : std_ulogic := 'X'; + + signal REL_dly : std_ulogic := 'X'; + signal RST_dly : std_ulogic := 'X'; + + signal CLKA1_zd : std_ulogic := 'X'; + signal CLKA1D2_zd : std_ulogic := 'X'; + signal CLKA1D4_zd : std_ulogic := 'X'; + signal CLKA1D8_zd : std_ulogic := 'X'; + signal CLKB1_zd : std_ulogic := 'X'; + signal CLKC1_zd : std_ulogic := 'X'; + signal CLKD1_zd : std_ulogic := 'X'; + + signal rel_clk_sel : integer := 0; + signal rst_active : boolean := true; + signal r1_out : std_ulogic := '0'; + signal rdiv_out : std_ulogic := '0'; + signal active_clk : std_ulogic := 'X'; + + signal Violation_CLKA1 : std_ulogic := '0'; + signal Violation_CLKB1 : std_ulogic := '0'; + signal Violation_CLKC1 : std_ulogic := '0'; + signal Violation_CLKD1 : std_ulogic := '0'; + + signal GSR_dly : std_ulogic := '0'; + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + CLKA_dly <= CLKA after 0 ps; + CLKB_dly <= CLKB after 0 ps; + CLKC_dly <= CLKC after 0 ps; + CLKD_dly <= CLKD after 0 ps; + REL_dly <= REL after 0 ps; + RST_dly <= RST after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + variable FIRST_TIME : boolean := true; + begin + if((RST_DEASSERT_CLK = "clka") or (RST_DEASSERT_CLK = "CLKA")) then + rel_clk_sel <= 1; + elsif((RST_DEASSERT_CLK = "clkb") or (RST_DEASSERT_CLK = "CLKB")) then + rel_clk_sel <= 2; + elsif((RST_DEASSERT_CLK = "clkc") or (RST_DEASSERT_CLK = "CLKC")) then + rel_clk_sel <= 3; + elsif((RST_DEASSERT_CLK = "clkd") or (RST_DEASSERT_CLK = "CLKD")) then + rel_clk_sel <= 4; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " RST_DEASSERT_CLK ", + EntityName => "/PMCD", + GenericValue => RST_DEASSERT_CLK, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " CLKA, CLKB, CLKC or CLKD ", + TailMsg => "", + MsgSeverity => ERROR + ); + end if; + + if(EN_REL = true) then + rst_active <= false; + elsif(EN_REL = false) then + rst_active <= true; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " EN_REL ", + EntityName => "/PMCD", + GenericValue => EN_REL, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => "True or False", + TailMsg => "", + MsgSeverity => ERROR + ); + end if; + wait; + end process prcs_init; +--#################################################################### +--##### CLKA ##### +--#################################################################### + prcs_clka:process(CLKA_dly, r1_out, rdiv_out, GSR_dly) + variable first_time : boolean := true; + begin + if(GSR_dly = '1') then + CLKA1_zd <= '0'; + CLKA1D2_zd <= '0'; + CLKA1D4_zd <= '0'; + CLKA1D8_zd <= '0'; + elsif(GSR_dly = '0') then + + if((first_time) and ((CLKA_dly = '0') or CLKA_dly = '1')) then + CLKA1_zd <= CLKA_dly; + CLKA1D2_zd <= CLKA_dly; + CLKA1D4_zd <= CLKA_dly; + CLKA1D8_zd <= CLKA_dly; + first_time := false; + end if; + + if(r1_out = '0') then + CLKA1_zd <= CLKA_dly; + elsif (r1_out = '1') then + CLKA1_zd <= '0'; + end if; + + if(rdiv_out = '1') then + CLKA1D2_zd <= '0'; + CLKA1D4_zd <= '0'; + CLKA1D8_zd <= '0'; + elsif(rdiv_out = '0') then + if(rising_edge(CLKA_dly)) then + CLKA1D2_zd <= NOT CLKA1D2_zd; + if (CLKA1D2_zd = '0') then + CLKA1D4_zd <= NOT CLKA1D4_zd; + if (CLKA1D4_zd = '0') then + CLKA1D8_zd <= NOT CLKA1D8_zd; + end if; + end if; + end if; + end if; + end if; + end process prcs_clka; +--#################################################################### +--##### CLKB ##### +--#################################################################### + prcs_clkb:process(CLKB_dly, r1_out, GSR_dly) + variable first_time : boolean := true; + begin + if((GSR_dly = '1') or (r1_out = '1')) then + CLKB1_zd <= '0'; + elsif ((GSR_dly = '0') and (r1_out = '0')) then + CLKB1_zd <= CLKB_dly; + end if; + end process prcs_clkb; +--#################################################################### +--##### CLKC ##### +--#################################################################### + prcs_clkc:process(CLKC_dly, r1_out, GSR_dly) + variable first_time : boolean := true; + begin + if((GSR_dly = '1') or (r1_out = '1')) then + CLKC1_zd <= '0'; + elsif ((GSR_dly = '0') and (r1_out = '0')) then + CLKC1_zd <= CLKC_dly; + end if; + end process prcs_clkc; +--#################################################################### +--##### CLKD ##### +--#################################################################### + prcs_clkd:process(CLKD_dly, r1_out, GSR_dly) + variable first_time : boolean := true; + begin + if((GSR_dly = '1') or (r1_out = '1')) then + CLKD1_zd <= '0'; + elsif ((GSR_dly = '0') and (r1_out = '0')) then + CLKD1_zd <= CLKD_dly; + end if; + end process prcs_clkd; +--#################################################################### +--##### RST CLK SEL ##### +--#################################################################### + prcs_rel_clk_mux:process(CLKA_dly, CLKB_dly, CLKC_dly, CLKD_dly) + begin + case rel_clk_sel is + when 1 => active_clk <= CLKA_dly; + when 2 => active_clk <= CLKB_dly; + when 3 => active_clk <= CLKC_dly; + when 4 => active_clk <= CLKD_dly; + when others => null; + end case; + end process prcs_rel_clk_mux; + +--#################################################################### +--##### RELEASE SIGNAL ##### +--#################################################################### + prcs_act_rel:process(active_clk, REL_dly, RST_dly, GSR_dly) + variable released : boolean := false; + variable r1_released : boolean := false; + variable rdiv_released : boolean := false; + variable start_rel_clk_count : boolean := false; + variable rel_clk_count : integer := 0; + variable path_1_clk_count : integer := 0; + variable path_1 : std_ulogic := '0'; + variable path_2 : std_ulogic := '0'; + + begin + if((GSR_dly = '1') or (RST_dly = '1')) then + released := false; + r1_released := false; + rdiv_released := false; + rel_clk_count := 0; + start_rel_clk_count := false; + r1_out <= '1'; + rdiv_out <= '1'; + path_1_clk_count := 0; + path_1 := '1'; + path_2 := '1'; + elsif ((GSR_dly = '0') and (RST_dly = '0')) then + if(rst_active) then + if(not released) then + if(rising_edge(active_clk)) then + start_rel_clk_count := true; + end if; + if(active_clk'event and start_rel_clk_count) then + rel_clk_count := rel_clk_count + 1; + end if; + if(rel_clk_count >= 1) then + rdiv_out <= '0'; + end if; + if(rel_clk_count >= 2) then + r1_out <= '0'; + released := true; + end if; + end if; + elsif(not rst_active) then + if(not r1_released) then + if(rising_edge(active_clk)) then + start_rel_clk_count := true; + end if; + if(active_clk'event and start_rel_clk_count) then + rel_clk_count := rel_clk_count + 1; + end if; + if(rel_clk_count >= 2) then + r1_out <= '0'; + r1_released := true; + end if; + end if; + if(not rdiv_released) then + if(rising_edge(active_clk)) then + path_1_clk_count := path_1_clk_count + 1; + if(path_1_clk_count >= 1) then + path_1 := '0'; + end if; + end if; + + if(rising_edge(REL_dly)) then + path_2 := '0'; + end if; + + if((path_1 = '0') and (path_2 = '0')) then + rdiv_out <= '0'; + rdiv_released := true; + end if; + end if; + end if; + end if; + end process prcs_act_rel; +--#################################################################### + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(CLKA1_zd, CLKA1D2_zd, CLKA1D4_zd, CLKA1D8_zd, + CLKB1_zd, CLKC1_zd, CLKD1_zd) + begin + CLKA1 <= CLKA1_zd after SYNC_PATH_DELAY; + CLKA1D2 <= CLKA1D2_zd after SYNC_PATH_DELAY; + CLKA1D4 <= CLKA1D4_zd after SYNC_PATH_DELAY; + CLKA1D8 <= CLKA1D8_zd after SYNC_PATH_DELAY; + + CLKB1 <= CLKB1_zd after SYNC_PATH_DELAY; + + CLKC1 <= CLKC1_zd after SYNC_PATH_DELAY; + + CLKD1 <= CLKD1_zd after SYNC_PATH_DELAY; + + end process prcs_output; +--#################################################################### + + +end PMCD_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +-- /___/ /\ Filename : RAMB16.vhd +-- \ \ / \ Timestamp : Thu Mar 17 16:56:02 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 03/17/05 - Added EN_ECC_READ/WRITE -- affects tim sim model only -- CR 204627 --FP +-- 05/24/05 - Fixed CR 200506 --FP +-- 08/25/05 - Fixed CR 215294 --FP -- Added Message for unequal WEs in WF mode +-- 11/15/05 - Fixed CR 219497 --FP -- made collision functions inout -- ncsim issue +-- 01/05/06 - Fixed CR 223161 --FP -- propagated INIT values. +-- 02/06/06 - Fixed CR 223097 --FP -- CASCADE/NO_CHANGE message. +-- 05/19/06 - Fixed CR 231750 --FP -- Added timing arcs for Cascadein to output. +-- 06/30/06 - Fixed CR 231750 --FP -- Added timing checks for CLK to Cascadein. +-- 07/10/06 - Added 2 dimensional memory array feature. +-- 01/24/07 - Added support of memory file to initialize memory and parity (CR 431584). +-- 02/13/07 - Fixed register output in cascaded mode (CR 433819). +-- 03/05/07 - Fixed inverted clock (CR 434198). +-- 03/13/07 - Removed attribute INITP_FILE (CR 436003). +-- 04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812). +-- 04/01/08 - Fixed delta delay problem on inputs (CR470144). +-- End Revision + +----- CELL RAMB16 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library STD; +use STD.TEXTIO.all; + +library unisim; +use unisim.vpkg.all; + +entity RAMB16 is + + generic ( + + DOA_REG : integer := 0 ; + DOB_REG : integer := 0 ; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + INIT_FILE : string := "NONE"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INVERT_CLK_DOA_REG : boolean := false; + INVERT_CLK_DOB_REG : boolean := false; + + RAM_EXTENSION_A : string := "NONE"; + RAM_EXTENSION_B : string := "NONE"; + + READ_WIDTH_A : integer := 0; + READ_WIDTH_B : integer := 0; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST"; + + WRITE_WIDTH_A : integer := 0; + WRITE_WIDTH_B : integer := 0 + ); + + port( + CASCADEOUTA : out std_ulogic; + CASCADEOUTB : out std_ulogic; + DOA : out std_logic_vector (31 downto 0); + DOB : out std_logic_vector (31 downto 0); + DOPA : out std_logic_vector (3 downto 0); + DOPB : out std_logic_vector (3 downto 0); + + ADDRA : in std_logic_vector (14 downto 0); + ADDRB : in std_logic_vector (14 downto 0); + CASCADEINA : in std_ulogic; + CASCADEINB : in std_ulogic; + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector (31 downto 0); + DIB : in std_logic_vector (31 downto 0); + DIPA : in std_logic_vector (3 downto 0); + DIPB : in std_logic_vector (3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector (3 downto 0); + WEB : in std_logic_vector (3 downto 0) + ); + +end RAMB16; + +architecture RAMB16_V of RAMB16 is + + component ARAMB36_INTERNAL + generic + ( + BRAM_MODE : string := "TRUE_DUAL_PORT"; + BRAM_SIZE : integer := 36; + DOA_REG : integer := 0; + DOB_REG : integer := 0; + INIT_A : bit_vector := X"000000000000000000"; + INIT_B : bit_vector := X"000000000000000000"; + RAM_EXTENSION_A : string := "NONE"; + RAM_EXTENSION_B : string := "NONE"; + READ_WIDTH_A : integer := 0; + READ_WIDTH_B : integer := 0; + SIM_COLLISION_CHECK : string := "ALL"; + SRVAL_A : bit_vector := X"000000000000000000"; + SRVAL_B : bit_vector := X"000000000000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST"; + WRITE_WIDTH_A : integer := 0; + WRITE_WIDTH_B : integer := 0; + EN_ECC_READ : boolean := FALSE; + EN_ECC_SCRUB : boolean := FALSE; + EN_ECC_WRITE : boolean := FALSE; + INIT_FILE : string := "NONE"; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + CASCADEOUTLATA : out std_ulogic; + CASCADEOUTLATB : out std_ulogic; + CASCADEOUTREGA : out std_ulogic; + CASCADEOUTREGB : out std_ulogic; + DBITERR : out std_ulogic; + DOA : out std_logic_vector(63 downto 0); + DOB : out std_logic_vector(63 downto 0); + DOPA : out std_logic_vector(7 downto 0); + DOPB : out std_logic_vector(7 downto 0); + ECCPARITY : out std_logic_vector(7 downto 0); + SBITERR : out std_ulogic; + + ADDRA : in std_logic_vector(15 downto 0); + ADDRB : in std_logic_vector(15 downto 0); + CASCADEINLATA : in std_ulogic; + CASCADEINLATB : in std_ulogic; + CASCADEINREGA : in std_ulogic; + CASCADEINREGB : in std_ulogic; + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(63 downto 0); + DIB : in std_logic_vector(63 downto 0); + DIPA : in std_logic_vector(7 downto 0); + DIPB : in std_logic_vector(7 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + REGCLKA : in std_ulogic; + REGCLKB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(7 downto 0); + WEB : in std_logic_vector(7 downto 0) + ); + end component; + + + constant SYNC_PATH_DELAY : time := 100 ps; + signal GND_4 : std_logic_vector(3 downto 0) := (others => '0'); + signal GND_32 : std_logic_vector(31 downto 0) := (others => '0'); + signal OPEN_4 : std_logic_vector(3 downto 0); + signal OPEN_32 : std_logic_vector(31 downto 0); + signal doa_dly : std_logic_vector(31 downto 0) := (others => '0'); + signal dob_dly : std_logic_vector(31 downto 0) := (others => '0'); + signal dopa_dly : std_logic_vector(3 downto 0) := (others => '0'); + signal dopb_dly : std_logic_vector(3 downto 0) := (others => '0'); + signal cascadeouta_dly : std_ulogic := '0'; + signal cascadeoutb_dly : std_ulogic := '0'; + signal cascadeoutlata_out : std_ulogic := '0'; + signal cascadeoutlatb_out : std_ulogic := '0'; + signal cascadeoutrega_out : std_ulogic := '0'; + signal cascadeoutregb_out : std_ulogic := '0'; + signal addra_int : std_logic_vector(15 downto 0) := (others => '0'); + signal addrb_int : std_logic_vector(15 downto 0) := (others => '0'); + signal wea_int : std_logic_vector(7 downto 0) := (others => '0'); + signal web_int : std_logic_vector(7 downto 0) := (others => '0'); + signal clka_tmp : std_ulogic := '0'; + signal clkb_tmp : std_ulogic := '0'; + signal regclka_tmp : std_ulogic := '0'; + signal regclkb_tmp : std_ulogic := '0'; + signal dia_tmp : std_logic_vector(31 downto 0) := (others => '0'); + signal dib_tmp : std_logic_vector(31 downto 0) := (others => '0'); + signal dipa_tmp : std_logic_vector(3 downto 0) := (others => '0'); + signal dipb_tmp : std_logic_vector(3 downto 0) := (others => '0'); + signal ena_tmp : std_ulogic := '0'; + signal enb_tmp : std_ulogic := '0'; + signal ssra_tmp : std_ulogic := '0'; + signal ssrb_tmp : std_ulogic := '0'; + signal cascadeina_tmp : std_ulogic := '0'; + signal cascadeinb_tmp : std_ulogic := '0'; + signal regcea_tmp : std_ulogic := '0'; + signal regceb_tmp : std_ulogic := '0'; + + + function Invert_CLK ( + invert_clk_do_reg : boolean; + do_reg : integer; + clk : std_ulogic) + return std_ulogic is variable out_clk : std_ulogic; + begin + + if (do_reg = 1 and invert_clk_do_reg = TRUE) then + out_clk := not clk; + else + out_clk := clk; + end if; + + return out_clk; + + end; + + + function Temp_BIT ( + clk : std_ulogic) + return std_ulogic is variable out_clk : std_ulogic; + begin + + out_clk := clk; + return out_clk; + + end; + + + function Temp_BUS ( + d_in : std_logic_vector) + return std_logic_vector is variable d_out : std_logic_vector(d_in'length-1 downto 0); + begin + + d_out := d_in; + return d_out; + + end; + + +begin + + prcs_clk: process + + begin + + if((INVERT_CLK_DOA_REG = true) and (DOA_REG /= 1 )) then + assert false + report "Attribute Syntax Error: When INVERT_CLK_DOA_REG is set to TRUE, then DOA_REG has to be set to 1." + severity Failure; + end if; + + if((INVERT_CLK_DOB_REG = true) and (DOB_REG /= 1 )) then + assert false + report "Attribute Syntax Error: When INVERT_CLK_DOB_REG is set to TRUE, then DOB_REG has to be set to 1." + severity Failure; + end if; + + if((INVERT_CLK_DOA_REG /= TRUE) and (INVERT_CLK_DOA_REG /= FALSE)) then + assert false + report "Attribute Syntax Error : The allowed boolean values for INVERT_CLK_DOA_REG are TRUE or FALSE" + severity Failure; + end if; + + if((INVERT_CLK_DOB_REG /= TRUE) and (INVERT_CLK_DOB_REG /= FALSE)) then + assert false + report "Attribute Syntax Error : The allowed boolean values for INVERT_CLK_DOB_REG are TRUE or FALSE" + severity Failure; + end if; + + wait; + + end process prcs_clk; + + + prcs_cascadea: process (cascadeoutrega_out, cascadeoutlata_out) + + begin + + if (DOA_REG = 1) then + cascadeouta_dly <= cascadeoutrega_out; + else + cascadeouta_dly <= cascadeoutlata_out; + end if; + + end process prcs_cascadea; + + + prcs_cascadeb: process (cascadeoutregb_out, cascadeoutlatb_out) + + begin + if (DOB_REG = 1) then + cascadeoutb_dly <= cascadeoutregb_out; + else + cascadeoutb_dly <= cascadeoutlatb_out; + end if; + + end process prcs_cascadeb; + + + addra_int <= ADDRA(14) & '0' & ADDRA(13 downto 0); + addrb_int <= ADDRB(14) & '0' & ADDRB(13 downto 0); + wea_int <= WEA & WEA; + web_int <= WEB & WEB; + regclka_tmp <= Invert_CLK(INVERT_CLK_DOA_REG, DOA_REG, CLKA); + regclkb_tmp <= Invert_CLK(INVERT_CLK_DOB_REG, DOB_REG, CLKB); + clka_tmp <= Temp_BIT(CLKA); + clkb_tmp <= Temp_BIT(CLKB); + dia_tmp <= Temp_BUS(DIA); + dib_tmp <= Temp_BUS(DIB); + dipa_tmp <= Temp_BUS(DIPA); + dipb_tmp <= Temp_BUS(DIPB); + cascadeina_tmp <= Temp_BIT(CASCADEINA); + cascadeinb_tmp <= Temp_BIT(CASCADEINB); + ena_tmp <= Temp_BIT(ENA); + enb_tmp <= Temp_BIT(ENB); + ssra_tmp <= Temp_BIT(SSRA); + ssrb_tmp <= Temp_BIT(SSRB); + regcea_tmp <= Temp_BIT(REGCEA); + regceb_tmp <= Temp_BIT(REGCEB); + +RAMB16_inst : ARAMB36_INTERNAL + generic map ( + + DOA_REG => DOA_REG, + DOB_REG => DOB_REG, + INIT_A => INIT_A, + INIT_B => INIT_B, + INIT_FILE => INIT_FILE, + + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SRVAL_A => SRVAL_A, + SRVAL_B => SRVAL_B, + WRITE_MODE_A => WRITE_MODE_A, + WRITE_MODE_B => WRITE_MODE_B, + BRAM_MODE => "TRUE_DUAL_PORT", + BRAM_SIZE => 16, + RAM_EXTENSION_A => RAM_EXTENSION_A, + RAM_EXTENSION_B => RAM_EXTENSION_B, + READ_WIDTH_A => READ_WIDTH_A, + READ_WIDTH_B => READ_WIDTH_B, + WRITE_WIDTH_A => WRITE_WIDTH_A, + WRITE_WIDTH_B => WRITE_WIDTH_B + + ) + port map ( + ADDRA => addra_int, + ADDRB => addrb_int, + CLKA => clka_tmp, + CLKB => clkb_tmp, + DIA(31 downto 0) => dia_tmp, + DIA(63 downto 32) => GND_32, + DIB(31 downto 0) => dib_tmp, + DIB(63 downto 32) => GND_32, + DIPA(3 downto 0) => dipa_tmp, + DIPA(7 downto 4) => GND_4, + DIPB(3 downto 0) => dipb_tmp, + DIPB(7 downto 4) => GND_4, + ENA => ena_tmp, + ENB => enb_tmp, + SSRA => ssra_tmp, + SSRB => ssrb_tmp, + WEA => wea_int, + WEB => web_int, + DOA(31 downto 0) => doa_dly, + DOA(63 downto 32) => OPEN_32, + DOB(31 downto 0) => dob_dly, + DOB(63 downto 32) => OPEN_32, + DOPA(3 downto 0) => dopa_dly, + DOPA(7 downto 4) => OPEN_4, + DOPB(3 downto 0) => dopb_dly, + DOPB(7 downto 4) => OPEN_4, + CASCADEOUTLATA => cascadeoutlata_out, + CASCADEOUTLATB => cascadeoutlatb_out, + CASCADEOUTREGA => cascadeoutrega_out, + CASCADEOUTREGB => cascadeoutregb_out, + CASCADEINLATA => cascadeina_tmp, + CASCADEINLATB => cascadeinb_tmp, + CASCADEINREGA => cascadeina_tmp, + CASCADEINREGB => cascadeinb_tmp, + REGCLKA => regclka_tmp, + REGCLKB => regclkb_tmp, + REGCEA => regcea_tmp, + REGCEB => regceb_tmp + ); + + + prcs_output_wtiming: process (doa_dly, dob_dly, dopa_dly, dopb_dly, cascadeouta_dly, cascadeoutb_dly) + begin -- process prcs_output_wtiming + + CASCADEOUTA <= cascadeouta_dly after SYNC_PATH_DELAY; + CASCADEOUTB <= cascadeoutb_dly after SYNC_PATH_DELAY; + DOA <= doa_dly after SYNC_PATH_DELAY; + DOPA <= dopa_dly after SYNC_PATH_DELAY; + DOB <= dob_dly after SYNC_PATH_DELAY; + DOPB <= dopb_dly after SYNC_PATH_DELAY; + + end process prcs_output_wtiming; + +end RAMB16_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/ramb32_s64_ecc.vhd,v 1.8 2005/03/17 19:51:15 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Ramb32_s64_ecc +-- /___/ /\ Filename : ramb32_s64_ecc.vhd +-- \ \ / \ Timestamp : Tue Mar 1 14:57:54 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 03/04/05 - Add generic DO_REG and SIM_COLLISION_CHECK to pass to RAMB16. +-- Add register to output for the latency. (CR 204569) +-- 03/16/05 - Change parameter WRITE_MODE_A and WRITE_MODE_B to READ_FIRST. +-- End Revision + +----- CELL RAMB32_S64_ECC ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.vpkg.all; +use unisim.VCOMPONENTS.all; + +entity RAMB32_S64_ECC is + +generic( + DO_REG : integer := 0 ; + SIM_COLLISION_CHECK : string := "ALL" + ); + +port ( + DO : out std_logic_vector(63 downto 0); + STATUS : out std_logic_vector(1 downto 0); + + DI : in std_logic_vector(63 downto 0); + RDADDR : in std_logic_vector(8 downto 0); + RDCLK : in std_ulogic; + RDEN : in std_ulogic; + SSR : in std_ulogic; + WRADDR : in std_logic_vector(8 downto 0); + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); +end RAMB32_S64_ECC; + +-- Architecture body -- + +architecture RAMB32_S64_ECC_V of RAMB32_S64_ECC is + + +-- Input/Output Pin signals + + signal do_ram16low : std_logic_vector(31 downto 0); + signal do_ram16up : std_logic_vector(31 downto 0); + signal dopa_ram16low : std_logic_vector(3 downto 0); + signal dopa_ram16up : std_logic_vector(3 downto 0); + signal STATUS_out : std_logic_vector(1 downto 0); + signal tmp41 : std_logic_vector(3 downto 0) :="1111"; + signal tmp640 : std_logic_vector(63 downto 0) := (others=>'0'); + signal tmp40 : std_logic_vector(3 downto 0) :="0000"; + signal tmp0 : std_logic :='0'; + signal tmp1 : std_logic :='1'; + signal ADDRA_tmp : std_logic_vector(14 downto 0) := "1XXXXXXXXX00000"; + signal ADDRB_tmp : std_logic_vector(14 downto 0) := "1XXXXXXXXX00000"; + signal DIB_up : std_logic_vector(31 downto 0); + signal DIB_low : std_logic_vector(31 downto 0); + signal DIPB_up : std_logic_vector(3 downto 0); + signal DIPB_low : std_logic_vector(3 downto 0); + signal DIA_tmp : std_logic_vector(31 downto 0) := (others=>'0'); + signal DO_tmp : std_logic_vector(63 downto 0) := (others=>'0'); + + +begin + + DO(63 downto 0) <= DO_tmp(63 downto 0); + + DO_OUT_P : process (RDCLK) + begin + if (RDCLK'event and RDCLK='1') then + DO_tmp(13 downto 0) <= do_ram16low(13 downto 0); + DO_tmp(14) <= dopa_ram16low(1); + DO_tmp(15) <= dopa_ram16low(3); + DO_tmp(29 downto 16) <= do_ram16low(29 downto 16); + DO_tmp(30) <= dopa_ram16low(0); + DO_tmp(31) <= dopa_ram16low(2); + + DO_tmp(32) <= dopa_ram16up(0); + DO_tmp(33) <= dopa_ram16up(2); + DO_tmp(47 downto 34) <= do_ram16up(15 downto 2); + DO_tmp(48) <= dopa_ram16up(1); + DO_tmp(49) <= dopa_ram16up(3); + DO_tmp(63 downto 50) <= do_ram16up(31 downto 18); + end if; + end process DO_OUT_P; + + ADDR_IN_P : process (RDADDR, WRADDR) + begin + ADDRA_tmp(4 downto 0) <= "00000"; + ADDRA_tmp(13 downto 5) <= RDADDR(8 downto 0); + ADDRA_tmp(14) <= '1'; + ADDRB_tmp(4 downto 0) <= "00000"; + ADDRB_tmp(13 downto 5) <= WRADDR(8 downto 0); + ADDRB_tmp(14) <= '1'; + end process ADDR_IN_P; + + DATA_IN_P : process(DI) + begin + DIB_low(13 downto 0) <= DI(13 downto 0); + DIB_low(15 downto 14) <= "00"; + DIPB_low(1) <= DI(14); + DIPB_low(3) <= DI(15); + DIB_low(29 downto 16) <= DI(29 downto 16); + DIB_low(31 downto 30) <= "00"; + DIPB_low(0) <= DI(30); + DIPB_low(2) <= DI(31); + + DIPB_up(0) <= DI(32); + DIPB_up(2) <= DI(33); + DIB_up(1 downto 0) <= "00"; + DIB_up(15 downto 2) <= DI(47 downto 34); + DIPB_up(1) <= DI(48); + DIPB_up(3) <= DI(49); + DIB_up(17 downto 16) <= "00"; + DIB_up(31 downto 18) <= DI(63 downto 50); + end process DATA_IN_P; + + + STATUS <= "00"; + + + RAMB16_LOWER : RAMB16 + generic map ( + READ_WIDTH_A => 36, + WRITE_WIDTH_A => 36, + READ_WIDTH_B => 36, + WRITE_WIDTH_B => 36, + WRITE_MODE_A => "READ_FIRST", + WRITE_MODE_B => "READ_FIRST", + INIT_A => "000000000000000000000000000000000000", + SRVAL_A => "000000000000000000000000000000000000", + INIT_B => "000000000000000000000000000000000000", + SRVAL_B => "000000000000000000000000000000000000", + DOA_REG => DO_REG, + DOB_REG => 0, + INVERT_CLK_DOA_REG => FALSE, + INVERT_CLK_DOB_REG => FALSE, + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK + ) + port map ( + ADDRA => ADDRA_tmp, + ADDRB => ADDRB_tmp, + DIA => DIA_tmp, + DIB => DIB_low, + DIPA => tmp40, + DIPB => DIPB_low, + ENA => RDEN, + ENB => WREN, + WEA => tmp40, + WEB => tmp41, + SSRA => SSR, + SSRB => tmp0, + CLKA => RDCLK, + CLKB => WRCLK, + REGCEA => tmp1, + REGCEB => tmp0, + CASCADEINA => tmp0, + CASCADEINB => tmp0, + DOA => do_ram16low(31 downto 0), + DOB => open, + DOPA => dopa_ram16low(3 downto 0), + DOPB => open, + CASCADEOUTA => open, + CASCADEOUTB => open + + ); + + + RAMB16_UPPER : RAMB16 + generic map ( + READ_WIDTH_A => 36, + WRITE_WIDTH_A => 36, + READ_WIDTH_B => 36, + WRITE_WIDTH_B => 36, + WRITE_MODE_A => "READ_FIRST", + WRITE_MODE_B => "READ_FIRST", + INIT_A => "000000000000000000000000000000000000", + SRVAL_A => "000000000000000000000000000000000000", + INIT_B => "000000000000000000000000000000000000", + SRVAL_B => "000000000000000000000000000000000000", + DOA_REG => DO_REG, + DOB_REG => 0, + INVERT_CLK_DOA_REG => FALSE, + INVERT_CLK_DOB_REG => FALSE, + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK + ) + port map ( + ADDRA => ADDRA_tmp, + ADDRB => ADDRB_tmp, + DIA => DIA_tmp, + DIB => DIB_up, + DIPA => tmp40, + DIPB => DIPB_up, + ENA => RDEN, + ENB => WREN, + WEA => tmp40, + WEB => tmp41, + SSRA => SSR, + SSRB => tmp0, + CLKA => RDCLK, + CLKB => WRCLK, + REGCEA => tmp1, + REGCEB => tmp0, + CASCADEINA => tmp0, + CASCADEINB => tmp0, + DOA => do_ram16up(31 downto 0), + DOB => open, + DOPA => dopa_ram16up(3 downto 0), + DOPB => open, + CASCADEOUTA => open, + CASCADEOUTB => open + ); + +end RAMB32_S64_ECC_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/startbuf_virtex4.vhd,v 1.5 2004/04/08 18:46:30 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / User Interface to Global Clock, Reset and 3-State Controls for VIRTEX4 +-- /___/ /\ Filename : STARTBUF_VIRTEX4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:05 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL STARTBUF_VIRTEX4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity STARTBUF_VIRTEX4 is + port( + EOSOUT : out std_ulogic; + GSROUT : out std_ulogic; + GTSOUT : out std_ulogic; + CLKIN : in std_ulogic := 'X'; + GSRIN : in std_ulogic := 'X'; + GTSIN : in std_ulogic := 'X'; + USRCCLKOIN : in std_ulogic := 'X'; + USRCCLKTSIN : in std_ulogic := 'X'; + USRDONEOIN : in std_ulogic := 'X'; + USRDONETSIN : in std_ulogic := 'X' + +); + +end STARTBUF_VIRTEX4; + +architecture STARTBUF_VIRTEX4_V of STARTBUF_VIRTEX4 is + +begin + + + GSROUT <= GSRIN; + GTSOUT <= GTSIN; + + +end STARTBUF_VIRTEX4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/startup_virtex4.vhd,v 1.5 2004/04/08 18:46:30 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / User Interface to Global Clock, Reset and 3-State Controls for VIRTEX4 +-- /___/ /\ Filename : STARTUP_VIRTEX4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:05 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL STARTUP_VIRTEX4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity STARTUP_VIRTEX4 is + port( + EOS : out std_ulogic; + + CLK : in std_ulogic := 'X'; + GSR : in std_ulogic := 'X'; + GTS : in std_ulogic := 'X'; + USRCCLKO : in std_ulogic := 'X'; + USRCCLKTS : in std_ulogic := 'X'; + USRDONEO : in std_ulogic := 'X'; + USRDONETS : in std_ulogic := 'X' + ); + +end STARTUP_VIRTEX4; + +architecture STARTUP_VIRTEX4_V of STARTUP_VIRTEX4 is + +begin +end STARTUP_VIRTEX4_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/VITAL/Attic/usr_access_virtex4.vhd,v 1.5 2004/04/08 18:46:30 patrickp Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / +-- /___/ /\ Filename : USR_ACCESS_VIRTEX4.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:05 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL USR_ACCESS_VIRTEX4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity USR_ACCESS_VIRTEX4 is + port( + DATA : out std_logic_vector(31 downto 0); + DATAVALID : out std_ulogic + ); + +end USR_ACCESS_VIRTEX4; + +architecture USR_ACCESS_VIRTEX4_V of USR_ACCESS_VIRTEX4 is + +begin +end USR_ACCESS_VIRTEX4_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / Dual Data Rate Input D Flip-Flop +-- /___/ /\ Filename : IDDR2.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:18:20 PST 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL IDDR2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + + +library unisim; +use unisim.vpkg.all; + +entity IDDR2 is + + generic( + + DDR_ALIGNMENT : string := "NONE"; + INIT_Q0 : bit := '0'; + INIT_Q1 : bit := '0'; + SRTYPE : string := "SYNC" + ); + + port( + Q0 : out std_ulogic; + Q1 : out std_ulogic; + + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); + +end IDDR2; + +architecture IDDR2_V OF IDDR2 is + + + constant SYNC_PATH_DELAY : time := 100 ps; + + signal C0_ipd : std_ulogic := 'X'; + signal C1_ipd : std_ulogic := 'X'; + signal CE_ipd : std_ulogic := 'X'; + signal D_ipd : std_ulogic := 'X'; + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := 'X'; + signal R_ipd : std_ulogic := 'X'; + signal S_ipd : std_ulogic := 'X'; + + signal C0_dly : std_ulogic := 'X'; + signal C1_dly : std_ulogic := 'X'; + signal CE_dly : std_ulogic := 'X'; + signal D_dly : std_ulogic := 'X'; + signal GSR_dly : std_ulogic := 'X'; + signal R_dly : std_ulogic := 'X'; + signal S_dly : std_ulogic := 'X'; + + signal Q0_zd : std_ulogic := 'X'; + signal Q1_zd : std_ulogic := 'X'; + + signal Q0_viol : std_ulogic := 'X'; + signal Q1_viol : std_ulogic := 'X'; + + signal q0_o_reg : std_ulogic := 'X'; + signal q0_c1_o_reg : std_ulogic := 'X'; + signal q1_o_reg : std_ulogic := 'X'; + signal q1_c0_o_reg : std_ulogic := 'X'; + + signal ddr_alignment_type : integer := -999; + signal sr_type : integer := -999; + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + C0_dly <= C0 after 0 ps; + C1_dly <= C1 after 0 ps; + CE_dly <= CE after 0 ps; + D_dly <= D after 0 ps; + GSR_dly <= GSR after 0 ps; + R_dly <= R after 0 ps; + S_dly <= S after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + + begin + if((DDR_ALIGNMENT = "NONE") or (DDR_ALIGNMENT = "none")) then + ddr_alignment_type <= 1; + elsif((DDR_ALIGNMENT = "C0") or (DDR_ALIGNMENT = "c0")) then + ddr_alignment_type <= 2; + elsif((DDR_ALIGNMENT = "C1") or (DDR_ALIGNMENT = "c1")) then + ddr_alignment_type <= 3; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error ", + GenericName => " DDR_ALIGNMENT ", + EntityName => "/IDDR2", + GenericValue => DDR_ALIGNMENT, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " NONE or C0 or C1.", + TailMsg => "", + MsgSeverity => ERROR + ); + end if; + + if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then + sr_type <= 1; + elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then + sr_type <= 2; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error ", + GenericName => " SRTYPE ", + EntityName => "/IDDR2", + GenericValue => SRTYPE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " ASYNC or SYNC. ", + TailMsg => "", + MsgSeverity => ERROR + ); + end if; + + wait; + end process prcs_init; +--#################################################################### +--##### functionality ##### +--#################################################################### + prcs_func_reg:process(C0_dly, C1_dly, D_dly, GSR_dly, R_dly, S_dly) + variable FIRST_TIME : boolean := true; + variable q0_out_var : std_ulogic := TO_X01(INIT_Q0); + variable q1_out_var : std_ulogic := TO_X01(INIT_Q1); + variable q0_c1_out_var : std_ulogic := TO_X01(INIT_Q0); + variable q1_c0_out_var : std_ulogic := TO_X01(INIT_Q1); + begin + if((GSR_dly = '1') or (FIRST_TIME)) then + q0_out_var := TO_X01(INIT_Q0); + q1_out_var := TO_X01(INIT_Q1); + q0_c1_out_var := TO_X01(INIT_Q0); + q1_c0_out_var := TO_X01(INIT_Q1); + FIRST_TIME := false; + else + case sr_type is + when 1 => + if(R_dly = '1') then + q0_out_var := '0'; + q1_out_var := '0'; + q1_c0_out_var := '0'; + q0_c1_out_var := '0'; + elsif((R_dly = '0') and (S_dly = '1')) then + q0_out_var := '1'; + q1_out_var := '1'; + q1_c0_out_var := '1'; + q0_c1_out_var := '1'; + elsif((R_dly = '0') and (S_dly = '0')) then + if(CE_dly = '1') then + if(rising_edge(C0_dly)) then + q0_out_var := D_dly; + q1_c0_out_var := q1_out_var; + end if; + if(rising_edge(C1_dly)) then + q1_out_var := D_dly; + q0_c1_out_var := q0_out_var; + end if; + end if; + end if; + + when 2 => + if(rising_edge(C0_dly)) then + if(R_dly = '1') then + q0_out_var := '0'; + q1_c0_out_var := '0'; + elsif((R_dly = '0') and (S_dly = '1')) then + q0_out_var := '1'; + q1_c0_out_var := '1'; + elsif((R_dly = '0') and (S_dly = '0')) then + if(CE_dly = '1') then + q0_out_var := D_dly; + q1_c0_out_var := q1_out_var; + end if; + end if; + end if; + + if(rising_edge(C1_dly)) then + if(R_dly = '1') then + q1_out_var := '0'; + q0_c1_out_var := '0'; + elsif((R_dly = '0') and (S_dly = '1')) then + q1_out_var := '1'; + q0_c1_out_var := '1'; + elsif((R_dly = '0') and (S_dly = '0')) then + if(CE_dly = '1') then + q1_out_var := D_dly; + q0_c1_out_var := q0_out_var; + end if; + end if; + end if; + + when others => + null; + end case; + end if; + + q0_o_reg <= q0_out_var; + q1_o_reg <= q1_out_var; + q0_c1_o_reg <= q0_c1_out_var; + q1_c0_o_reg <= q1_c0_out_var; + + end process prcs_func_reg; +--#################################################################### +--##### output mux ##### +--#################################################################### + prcs_output_mux:process(q0_o_reg, q1_o_reg, q0_c1_o_reg, q1_c0_o_reg) + begin + case ddr_alignment_type is + when 1 => + Q0_zd <= q0_o_reg; + Q1_zd <= q1_o_reg; + when 2 => + Q0_zd <= q0_o_reg; + Q1_zd <= q1_c0_o_reg; + when 3 => + Q0_zd <= q0_c1_o_reg; + Q1_zd <= q1_o_reg; + when others => + null; + end case; + end process prcs_output_mux; +--#################################################################### + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(Q0_zd, Q1_zd) + begin + Q0 <= Q0_zd after SYNC_PATH_DELAY; + Q1 <= Q1_zd after SYNC_PATH_DELAY; + end process prcs_output; +--#################################################################### + + +end IDDR2_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / 18X18 Signed Multiplier +-- /___/ /\ Filename : MULT18X18SIO.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:18:19 PST 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 07/25/05 - Added CLK_dly to the sensitivity list +-- 08/29/05 - Added rest of the signals to the sensitivity list to avoid false +-- - Setup/Hold violations at initial stages +-- End Revision + +----- CELL MULT18X18SIO ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_SIGNED.all; +use IEEE.STD_LOGIC_ARITH.all; + + +library unisim; +use unisim.vpkg.all; + +entity MULT18X18SIO is + + generic ( + + AREG : integer := 1; + BREG : integer := 1; + B_INPUT : string := "DIRECT"; + + PREG : integer := 1 + ); + + port ( + BCOUT : out std_logic_vector (17 downto 0); + P : out std_logic_vector (35 downto 0); + + A : in std_logic_vector (17 downto 0); + B : in std_logic_vector (17 downto 0); + BCIN : in std_logic_vector (17 downto 0); + CEA : in std_ulogic; + CEB : in std_ulogic; + CEP : in std_ulogic; + CLK : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + RSTP : in std_ulogic + ); + +end MULT18X18SIO; + + +architecture MULT18X18SIO_V of MULT18X18SIO is + + constant MAX_P : integer := 36; + constant MAX_BCOUT : integer := 36; + constant MAX_BCIN : integer := 18; + constant MAX_B : integer := 18; + constant MAX_A : integer := 18; + + constant MSB_P : integer := 35; + constant MSB_BCOUT : integer := 17; + constant MSB_BCIN : integer := 17; + constant MSB_B : integer := 17; + constant MSB_A : integer := 17; + + signal A_ipd : std_logic_vector(MSB_A downto 0) := (others => '0' ); + signal B_ipd : std_logic_vector(MSB_B downto 0) := (others => '0' ); + signal BCIN_ipd : std_logic_vector(MSB_BCIN downto 0) := (others => '0' ); + signal CEA_ipd : std_ulogic := 'X'; + signal CEB_ipd : std_ulogic := 'X'; + signal CEP_ipd : std_ulogic := 'X'; + signal CLK_ipd : std_ulogic := 'X'; + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := 'X'; + signal RSTA_ipd : std_ulogic := 'X'; + signal RSTB_ipd : std_ulogic := 'X'; + signal RSTP_ipd : std_ulogic := 'X'; + + signal A_dly : std_logic_vector(MSB_A downto 0) := (others => '0' ); + signal B_dly : std_logic_vector(MSB_B downto 0) := (others => '0' ); + signal BCIN_dly : std_logic_vector(MSB_BCIN downto 0) := (others => '0' ); + signal CEA_dly : std_ulogic := 'X'; + signal CEB_dly : std_ulogic := 'X'; + signal CEP_dly : std_ulogic := 'X'; + signal CLK_dly : std_ulogic := 'X'; + signal GSR_dly : std_ulogic := 'X'; + signal RSTA_dly : std_ulogic := 'X'; + signal RSTB_dly : std_ulogic := 'X'; + signal RSTP_dly : std_ulogic := 'X'; + + + --- Internal Signal Declarations + + signal qa_o_reg1 : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal qa_o_mux : std_logic_vector(MSB_A downto 0) := (others => '0'); + + signal b_o_mux : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal qb_o_reg1 : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal qb_o_mux : std_logic_vector(MSB_B downto 0) := (others => '0'); + + signal mult_o_int : std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0'); + + signal qp_o_reg : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal qp_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); + + signal BCOUT_zd : std_logic_vector(MSB_BCOUT downto 0) := (others => '0'); + signal P_zd : std_logic_vector(MSB_P downto 0) := (others => '0'); + +begin + + A_dly <= A after 0 ps; + B_dly <= B after 0 ps; + BCIN_dly <= BCIN after 0 ps; + CEA_dly <= CEA after 0 ps; + CEB_dly <= CEB after 0 ps; + CEP_dly <= CEP after 0 ps; + CLK_dly <= CLK after 0 ps; + RSTA_dly <= RSTA after 0 ps; + RSTB_dly <= RSTB after 0 ps; + RSTP_dly <= RSTP after 0 ps; + GSR_dly <= GSR after 0 ps; + + +--#################################################################### +--##### Input Register A with 1 level of registers and a mux ##### +--#################################################################### + prcs_qa_1lvl:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qa_o_reg1 <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTA_dly = '1') then + qa_o_reg1 <= ( others => '0'); + elsif ((RSTA_dly = '0') and (CEA_dly = '1')) then + qa_o_reg1 <= A_dly; + end if; + end if; + end if; + end process prcs_qa_1lvl; + +---------------------------------------------------------------------- + + prcs_qa_o_mux:process(A_dly, qa_o_reg1) + begin + case AREG is + when 0 => qa_o_mux <= A_dly; + when 1 => qa_o_mux <= qa_o_reg1; + when others => + assert false + report "Attribute Syntax Error: The allowed values for AREG are 0 or 1" + severity Failure; + end case; + end process prcs_qa_o_mux; + +--#################################################################### +--##### Input Register B with two levels of registers and a mux ### +--#################################################################### + prcs_b_in:process(B_dly, BCIN_dly) + begin + if(B_INPUT ="DIRECT") then + b_o_mux <= B_dly; + elsif(B_INPUT ="CASCADE") then + b_o_mux <= BCIN_dly; + else + assert false + report "Attribute Syntax Error: The allowed values for B_INPUT are DIRECT or CASCADE." + severity Failure; + end if; + end process prcs_b_in; +------------------------------------------------------------------ + prcs_qb_1lvl:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qb_o_reg1 <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTB_dly = '1') then + qb_o_reg1 <= ( others => '0'); + elsif ((RSTB_dly = '0') and (CEB_dly = '1')) then + qb_o_reg1 <= b_o_mux; + end if; + end if; + end if; + end process prcs_qb_1lvl; +------------------------------------------------------------------ + prcs_qb_o_mux:process(b_o_mux, qb_o_reg1) + begin + case BREG is + when 0 => qb_o_mux <= b_o_mux; + when 1 => qb_o_mux <= qb_o_reg1; + when others => + assert false + report "Attribute Syntax Error: The allowed values for BREG are 0 or 1 " + severity Failure; + end case; + + end process prcs_qb_o_mux; +--#################################################################### +--##### Multiply ##### +--#################################################################### + prcs_mult:process(qa_o_mux, qb_o_mux) + begin + mult_o_int <= qa_o_mux * qb_o_mux; + end process prcs_mult; +--#################################################################### +--##### Output P ##### +--#################################################################### + prcs_qp_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qp_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTP_dly = '1') then + qp_o_reg <= ( others => '0'); + elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then + qp_o_reg <= mult_o_int; + end if; + end if; + end if; + end process prcs_qp_reg; +------------------------------------------------------------------ + prcs_qp_mux:process(mult_o_int, qp_o_reg) + begin + case PREG is + when 0 => qp_o_mux <= mult_o_int; + when 1 => qp_o_mux <= qp_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for PREG are 0 or 1" + severity Failure; + end case; + + end process prcs_qp_mux; +--#################################################################### +--##### ZERO_DELAY_OUTPUTS ##### +--#################################################################### + prcs_zero_delay_outputs:process(qb_o_mux, qp_o_mux) + begin + BCOUT_zd <= qb_o_mux; + P_zd <= qp_o_mux; + end process prcs_zero_delay_outputs; + + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_outputs:process(BCOUT_zd, P_zd) + begin + BCOUT <= BCOUT_zd; + P <= P_zd; + end process prcs_outputs; + +end MULT18X18SIO_V ; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / Dual Data Rate Output D Flip-Flop +-- /___/ /\ Filename : ODDR2.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:18:20 PST 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL ODDR2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + + +library unisim; +use unisim.vpkg.all; + +entity ODDR2 is + + generic( + + DDR_ALIGNMENT : string := "NONE"; + INIT : bit := '0'; + SRTYPE : string := "SYNC" + ); + + port( + Q : out std_ulogic; + + C0 : in std_ulogic; + C1 : in std_ulogic; + CE : in std_ulogic; + D0 : in std_ulogic; + D1 : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); + +end ODDR2; + +architecture ODDR2_V OF ODDR2 is + + + constant SYNC_PATH_DELAY : time := 100 ps; + + signal C0_ipd : std_ulogic := 'X'; + signal C1_ipd : std_ulogic := 'X'; + signal CE_ipd : std_ulogic := 'X'; + signal D0_ipd : std_ulogic := 'X'; + signal D1_ipd : std_ulogic := 'X'; + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := 'X'; + signal R_ipd : std_ulogic := 'X'; + signal S_ipd : std_ulogic := 'X'; + + signal C0_dly : std_ulogic := 'X'; + signal C1_dly : std_ulogic := 'X'; + signal CE_dly : std_ulogic := 'X'; + signal D0_dly : std_ulogic := 'X'; + signal D1_dly : std_ulogic := 'X'; + signal GSR_dly : std_ulogic := 'X'; + signal R_dly : std_ulogic := 'X'; + signal S_dly : std_ulogic := 'X'; + + signal Q_zd : std_ulogic := 'X'; + + signal Q_viol : std_ulogic := 'X'; + + signal ddr_alignment_type : integer := -999; + signal sr_type : integer := -999; + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + C0_dly <= C0 after 0 ps; + C1_dly <= C1 after 0 ps; + CE_dly <= CE after 0 ps; + D0_dly <= D0 after 0 ps; + D1_dly <= D1 after 0 ps; + GSR_dly <= GSR after 0 ps; + R_dly <= R after 0 ps; + S_dly <= S after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + + begin + if((DDR_ALIGNMENT = "NONE") or (DDR_ALIGNMENT = "none")) then + ddr_alignment_type <= 1; + elsif((DDR_ALIGNMENT = "C0") or (DDR_ALIGNMENT = "c0")) then + ddr_alignment_type <= 2; + elsif((DDR_ALIGNMENT = "C1") or (DDR_ALIGNMENT = "c1")) then + ddr_alignment_type <= 3; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error :", + GenericName => " DDR_ALIGNMENT ", + EntityName => "/ODDR2", + GenericValue => DDR_ALIGNMENT, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " NONE, C0 or C1.", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then + sr_type <= 1; + elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then + sr_type <= 2; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error :", + GenericName => " SRTYPE ", + EntityName => "/ODDR2", + GenericValue => SRTYPE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " ASYNC or SYNC. ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + wait; + end process prcs_init; +--#################################################################### +--##### functionality ##### +--#################################################################### + prcs_func_reg:process(C0_dly, C1_dly, GSR_dly, R_dly, S_dly) + variable FIRST_TIME : boolean := true; + variable q_var : std_ulogic := TO_X01(INIT); + variable q_d0_c1_out_var : std_ulogic := TO_X01(INIT); + variable q_d1_c0_out_var : std_ulogic := TO_X01(INIT); + begin + if((GSR_dly = '1') or (FIRST_TIME)) then + q_var := TO_X01(INIT); + q_d0_c1_out_var := TO_X01(INIT); + q_d1_c0_out_var := TO_X01(INIT); + FIRST_TIME := false; + else + case sr_type is + when 1 => + if(R_dly = '1') then + q_var := '0'; + q_d0_c1_out_var := '0'; + q_d1_c0_out_var := '0'; + elsif((R_dly = '0') and (S_dly = '1')) then + q_var := '1'; + q_d0_c1_out_var := '1'; + q_d1_c0_out_var := '1'; + elsif((R_dly = '0') and (S_dly = '0')) then + if(CE_dly = '1') then + if(rising_edge(C0_dly)) then + if(ddr_alignment_type = 3) then + q_var := q_d0_c1_out_var; + else + q_var := D0_dly; + if(ddr_alignment_type = 2) then + q_d1_c0_out_var := D1_dly; + end if; + end if; + end if; + if(rising_edge(C1_dly)) then + if(ddr_alignment_type = 2) then + q_var := q_d1_c0_out_var; + else + q_var := D1_dly; + if(ddr_alignment_type = 3) then + q_d0_c1_out_var := D0_dly; + end if; + end if; + end if; + end if; + end if; + + when 2 => + if(rising_edge(C0_dly)) then + if(R_dly = '1') then + q_var := '0'; + q_d1_c0_out_var := '0'; + elsif((R_dly = '0') and (S_dly = '1')) then + q_var := '1'; + q_d1_c0_out_var := '1'; + elsif((R_dly = '0') and (S_dly = '0')) then + if(CE_dly = '1') then + if(ddr_alignment_type = 3) then + q_var := q_d0_c1_out_var; + else + q_var := D0_dly; + if(ddr_alignment_type = 2) then + q_d1_c0_out_var := D1_dly; + end if; + end if; + end if; + end if; + end if; + + if(rising_edge(C1_dly)) then + if(R_dly = '1') then + q_var := '0'; + q_d0_c1_out_var := '0'; + elsif((R_dly = '0') and (S_dly = '1')) then + q_var := '1'; + q_d0_c1_out_var := '1'; + elsif((R_dly = '0') and (S_dly = '0')) then + if(CE_dly = '1') then + if(ddr_alignment_type = 2) then + q_var := q_d1_c0_out_var; + else + q_var := D1_dly; + if(ddr_alignment_type = 3) then + q_d0_c1_out_var := D0_dly; + end if; + end if; + end if; + end if; + end if; + + when others => + null; + end case; + end if; + + Q_zd <= q_var; + + end process prcs_func_reg; +--#################################################################### + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(Q_zd) + begin + Q <= Q_zd after SYNC_PATH_DELAY; + end process prcs_output; +--#################################################################### + + +end ODDR2_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/spartan4/VITAL/Attic/startup_spartan3e.vhd,v 1.4 2004/09/10 06:25:13 fphillip Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / User Interface to Global Clock, Reset and 3-State Controls for SPARTAN3E +-- /___/ /\ Filename : STARTUP_SPARTAN3E.vhd +-- \ \ / \ Timestamp : Tue Jul 27 21:56:59 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 07/27/04 - Initial version. + +----- CELL STARTUP_SPARTAN3E ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity STARTUP_SPARTAN3E is + port( + CLK : in std_ulogic := 'X'; + GSR : in std_ulogic := 'X'; + GTS : in std_ulogic := 'X'; + MBT : in std_ulogic := 'X' + ); +end STARTUP_SPARTAN3E; + +architecture STARTUP_SPARTAN3E_V of STARTUP_SPARTAN3E is +constant MINIMUM_PULSE_LOW : time := 300 ns; +begin + prcs_mbt:process(MBT) + variable disable_mbt : boolean := false; + variable init_time, min_time : time := 0 ps; + begin + if(not disable_mbt) then + if(MBT = '0') then + if(now /= 0 ns ) then + init_time := now; + end if; + elsif(MBT = '1') then + min_time := now - init_time; + if(min_time >= MINIMUM_PULSE_LOW) then + assert false + report "Soft Boot has been initiated." + severity note; + + disable_mbt := true; + end if; + end if; + end if; -- if (not disable_mbt) + end process prcs_mbt; +end STARTUP_SPARTAN3E_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/afifo36_internal.vhd,v 1.16.6.1 2008/04/28 22:33:55 wloo Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2005 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : This is not an user primitive. +-- / / Xilinx Functional Simulation Library Component 36K-Bit FIFO +-- /___/ /\ Filename : AFIFO36_INTERNAL.vhd +-- \ \ / \ Timestamp : Tues October 18 08:18:20 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 10/18/05 - Initial version. +-- 06/13/06 - Fixed out of range error (CR 232285). Fixed almostfull flag in +-- sync mode (CR 232931). +-- 10/16/06 - Fixed the unused bits of wrcount and rdcount to match the hardware (CR 426347). +-- 11/15/06 - Fixed SBITERR and DBITERR in synchronous mode (CR 429311). +-- 11/20/06 - Fixed WRCOUNT and RDCOUNT (CR 429310). +-- 01/24/07 - Removed DRC warning for RST in ECC mode (CR 432367). +-- 06/14/07 - Implemented high performace version of the model. +-- 10/26/07 - Changed wren_dly to wren_var to fix FULL flag (CR 452554). +-- 04/28/08 - Fixed sbiterr and dbiterr outputs deassertion (CR 470460). +-- End Revision + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_arith.all; + +library STD; +use STD.TEXTIO.ALL; + +library unisim; +use unisim.vpkg.all; +use unisim.vcomponents.all; + +entity AFIFO36_INTERNAL is + + generic( + + ALMOST_FULL_OFFSET : bit_vector := X"0080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"0080"; + DATA_WIDTH : integer := 4; + DO_REG : integer := 1; + EN_ECC_READ : boolean := FALSE; + EN_ECC_WRITE : boolean := FALSE; + EN_SYN : boolean := FALSE; + FIFO_SIZE : integer := 36; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + SIM_MODE : string := "SAFE" + ); + + port( + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DBITERR : out std_ulogic; + DO : out std_logic_vector (63 downto 0); + DOP : out std_logic_vector (7 downto 0); + ECCPARITY : out std_logic_vector (7 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (12 downto 0); + RDERR : out std_ulogic; + SBITERR : out std_ulogic; + WRCOUNT : out std_logic_vector (12 downto 0); + WRERR : out std_ulogic; + + DI : in std_logic_vector (63 downto 0); + DIP : in std_logic_vector (7 downto 0); + RDCLK : in std_ulogic; + RDRCLK : in std_ulogic; + RDEN : in std_ulogic; + RST : in std_ulogic; + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); + +end AFIFO36_INTERNAL; + +-- architecture body -- + +architecture AFIFO36_INTERNAL_V of AFIFO36_INTERNAL is + + + function GetMemoryDepth ( + rdwr_width : in integer; + func_fifo_size : in integer + ) return integer is + variable func_mem_depth : integer; + begin + case rdwr_width is + when 4 => if (func_fifo_size = 18) then + func_mem_depth := 4096; + else + func_mem_depth := 8192; + end if; + when 9 => if (func_fifo_size = 18) then + func_mem_depth := 2048; + else + func_mem_depth := 4096; + end if; + when 18 => if (func_fifo_size = 18) then + func_mem_depth := 1024; + else + func_mem_depth := 2048; + end if; + when 36 => if (func_fifo_size = 18) then + func_mem_depth := 512; + else + func_mem_depth := 1024; + end if; + when 72 => if (func_fifo_size = 18) then + func_mem_depth := 0; + else + func_mem_depth := 512; + end if; + when others => func_mem_depth := 8192; + end case; + return func_mem_depth; + end; + + function GetMemoryDepthP ( + rdwr_width : in integer; + func_fifo_size : in integer + ) return integer is + variable func_memp_depth : integer; + begin + case rdwr_width is + when 9 => if (func_fifo_size = 18) then + func_memp_depth := 2048; + else + func_memp_depth := 4096; + end if; + when 18 => if (func_fifo_size = 18) then + func_memp_depth := 1024; + else + func_memp_depth := 2048; + end if; + when 36 => if (func_fifo_size = 18) then + func_memp_depth := 512; + else + func_memp_depth := 1024; + end if; + when 72 => if (func_fifo_size = 18) then + func_memp_depth := 0; + else + func_memp_depth := 512; + end if; + when others => func_memp_depth := 8192; + end case; + return func_memp_depth; + end; + + + function GetWidth ( + rdwr_width : in integer + ) return integer is + variable func_width : integer; + begin + case rdwr_width is + when 4 => func_width := 4; + when 9 => func_width := 8; + when 18 => func_width := 16; + when 36 => func_width := 32; + when 72 => func_width := 64; + when others => func_width := 64; + end case; + return func_width; + end; + + + function GetWidthp ( + rdwr_widthp : in integer + ) return integer is + variable func_widthp : integer; + begin + case rdwr_widthp is + when 9 => func_widthp := 1; + when 18 => func_widthp := 2; + when 36 => func_widthp := 4; + when 72 => func_widthp := 8; + when others => func_widthp := 8; + end case; + return func_widthp; + end; + + constant MAX_DO : integer := 64; + constant MAX_DOP : integer := 8; + constant MAX_RDCOUNT : integer := 13; + constant MAX_WRCOUNT : integer := 13; + constant MSB_MAX_DO : integer := 63; + constant MSB_MAX_DOP : integer := 7; + constant MSB_MAX_RDCOUNT : integer := 12; + constant MSB_MAX_WRCOUNT : integer := 12; + + constant MAX_DI : integer := 64; + constant MAX_DIP : integer := 8; + constant MSB_MAX_DI : integer := 63; + constant MSB_MAX_DIP : integer := 7; + + constant MAX_LATENCY_EMPTY : integer := 3; + constant MAX_LATENCY_FULL : integer := 3; + + constant mem_depth : integer := GetMemoryDepth(DATA_WIDTH, FIFO_SIZE); + constant memp_depth : integer := GetMemoryDepthP(DATA_WIDTH, FIFO_SIZE); + constant mem_width : integer := GetWidth(DATA_WIDTH); + constant memp_width : integer := GetWidthp(DATA_WIDTH); + + type Two_D_array_type is array ((mem_depth - 1) downto 0) of std_logic_vector((mem_width - 1) downto 0); + type Two_D_parity_array_type is array ((memp_depth - 1) downto 0) of std_logic_vector((memp_width -1) downto 0); + + signal mem : Two_D_array_type; + signal memp : Two_D_parity_array_type; + + signal DI_ipd : std_logic_vector(MSB_MAX_DI downto 0) := (others => 'X'); + signal DIP_ipd : std_logic_vector(MSB_MAX_DIP downto 0) := (others => 'X'); + signal GSR_ipd : std_ulogic := 'X'; + signal RDCLK_ipd : std_ulogic := 'X'; + signal RDEN_ipd : std_ulogic := 'X'; + signal RST_ipd : std_ulogic := 'X'; + signal WRCLK_ipd : std_ulogic := 'X'; + signal WREN_ipd : std_ulogic := 'X'; + + signal DI_dly : std_logic_vector(MSB_MAX_DI downto 0) := (others => 'X'); + signal DIP_dly : std_logic_vector(MSB_MAX_DIP downto 0) := (others => 'X'); + signal GSR_dly : std_ulogic; + signal RDCLK_dly : std_ulogic := 'X'; + signal RDEN_dly : std_ulogic := 'X'; + signal RST_dly : std_ulogic := 'X'; + signal WRCLK_dly : std_ulogic := 'X'; + signal WREN_dly : std_ulogic := 'X'; + + signal DO_zd : std_logic_vector(MSB_MAX_DO downto 0) := (others => '0'); + signal DOP_zd : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + signal ALMOSTEMPTY_zd : std_logic := '1'; + signal ALMOSTFULL_zd : std_logic := '0'; + signal EMPTY_zd : std_logic := '1'; + signal FULL_zd : std_logic := '0'; + signal RDCOUNT_zd : std_logic_vector(MSB_MAX_RDCOUNT downto 0) := (others => '0'); + signal RDERR_zd : std_logic := '0'; + signal WRCOUNT_zd : std_logic_vector(MSB_MAX_WRCOUNT downto 0) := (others => '0'); + signal WRERR_zd : std_logic := '0'; + signal RDCOUNT_OUT_zd : std_logic_vector(MSB_MAX_RDCOUNT downto 0) := (others => '1'); + signal WRCOUNT_OUT_zd : std_logic_vector(MSB_MAX_WRCOUNT downto 0) := (others => '1'); + signal DO_OUT_zd : std_logic_vector(MSB_MAX_DO downto 0) := (others => 'X'); + signal DOP_OUT_zd : std_logic_vector(MSB_MAX_DOP downto 0) := (others => 'X'); + signal DO_OUTREG_zd : std_logic_vector(MSB_MAX_DO downto 0) := (others => '0'); + signal DOP_OUTREG_zd : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + signal DO_OUT_MUX_zd : std_logic_vector(MSB_MAX_DO downto 0) := (others => '0'); + signal DOP_OUT_MUX_zd : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + + --- Internal Signal Declarations + + signal RST_META : std_ulogic := '0'; + + signal DefDelay : time := 10 ps; + + signal addr_limit : integer := 0; + signal addr_limit_fast : integer := 0; + signal wr_addr : integer := 0; + signal wr_addr_fast : integer := 0; + signal rd_addr : integer := 0; + signal rd_addr_fast : integer := 0; + signal rd_addr_range : integer := 0; + signal wr_addr_range : integer := 0; + + signal rd_flag : std_logic := '0'; + signal wr_flag : std_logic := '0'; + signal awr_flag : std_logic := '0'; + + signal rdcount_flag : std_logic := '0'; + + signal almostempty_limit : real := 0.0; + signal almostfull_limit : real := 0.0; + + signal violation : std_ulogic := '0'; + + signal fwft : std_logic := 'X'; + + signal update_from_write_prcs : std_logic := '0'; + signal update_from_read_prcs : std_logic := '0'; + signal update_from_write_prcs_sync : std_logic := '0'; + signal update_from_read_prcs_sync : std_logic := '0'; + + signal ae_empty : integer := 0; + signal ae_full : integer := 0; + signal ae_empty_fast : integer := 0; + signal ae_full_fast : integer := 0; + +-- CR 182616 fix + signal rst_rdckreg : std_logic_vector (2 downto 0) := (others => '0'); + signal rst_wrckreg : std_logic_vector (2 downto 0) := (others => '0'); + signal sync : std_logic := 'X'; + signal sbiterr_zd : std_logic := '0'; + signal dbiterr_zd : std_logic := '0'; +-- signal sbiterr_out_out : std_ulogic := '0'; +-- signal dbiterr_out_out : std_ulogic := '0'; + signal ECCPARITY_zd : std_logic_vector(MSB_MAX_DOP downto 0) := (others => 'X'); + signal rst_rdclk_flag : std_logic := '0'; + signal rst_wrclk_flag : std_logic := '0'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + + DI_dly <= DI after 0 ps; + DIP_dly <= DIP after 0 ps; + GSR_dly <= GSR after 0 ps; + RDCLK_dly <= RDCLK after 0 ps; + RDEN_dly <= RDEN after 0 ps; + RST_dly <= RST after 0 ps; + WRCLK_dly <= WRCLK after 0 ps; + WREN_dly <= WREN after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + + --------------------------------------------------------------------------- + -- SAFE mode + --------------------------------------------------------------------------- + + safe_mode : if (SIM_MODE = "SAFE") generate + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_initialize:process + variable first_time : boolean := true; + variable addr_limit_var : integer := 0; + variable fwft_var : std_ulogic := 'X'; + variable rd_offset_stdlogic : std_logic_vector (ALMOST_EMPTY_OFFSET'length-1 downto 0); + variable rd_offset_int : integer := 0; + variable wr_offset_stdlogic : std_logic_vector (ALMOST_FULL_OFFSET'length-1 downto 0); + variable wr_offset_int : integer := 0; + variable Message : LINE; + variable ae_empty_var : integer := 0; + variable ae_full_var : integer := 0; + + begin + if (first_time) then + + if (SIM_MODE /= "FAST" and SIM_MODE /= "SAFE") then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " SIM_MODE ", + EntityName => "AFIFO36_INTERNAL", + GenericValue => SIM_MODE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " FAST or SAFE ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + + case EN_SYN is + when TRUE => sync <= '1'; + when FALSE => sync <= '0'; + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error ", + GenericName => " EN_SYN ", + EntityName => "AFIFO36_INTERNAL", + GenericValue => EN_SYN, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " TRUE or FALSE ", + TailMsg => "", + MsgSeverity => failure + ); + end case; + + + case DATA_WIDTH is + when 4 => if (FIFO_SIZE = 36) then + addr_limit_var := 8192; + else + addr_limit_var := 4096; + end if; + when 9 => if (FIFO_SIZE = 36) then + addr_limit_var := 4096; + else + addr_limit_var := 2048; + end if; + when 18 => if (FIFO_SIZE = 36) then + addr_limit_var := 2048; + else + addr_limit_var := 1024; + end if; + when 36 => if (FIFO_SIZE = 36) then + addr_limit_var := 1024; + else + addr_limit_var := 512; + end if; + when 72 => + addr_limit_var := 512; + + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error ", + GenericName => " DATA_WIDTH ", + EntityName => "AFIFO36_INTERNAL", + GenericValue => DATA_WIDTH, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 4, 9, 18, 36 and 72 ", + TailMsg => "", + MsgSeverity => failure + ); + end case; + + rd_offset_stdlogic := To_StdLogicVector(ALMOST_EMPTY_OFFSET); + rd_offset_int := SLV_TO_INT(rd_offset_stdlogic); + + wr_offset_stdlogic := To_StdLogicVector(ALMOST_FULL_OFFSET); + wr_offset_int := SLV_TO_INT(wr_offset_stdlogic); + + case FIRST_WORD_FALL_THROUGH is + when TRUE => + fwft_var := '1'; + ae_empty_var := rd_offset_int - 2; + ae_full_var := wr_offset_int; + when FALSE => + fwft_var := '0'; + if (EN_SYN = FALSE) then + ae_empty_var := rd_offset_int - 1; + ae_full_var := wr_offset_int; + else + ae_empty_var := rd_offset_int; + ae_full_var := wr_offset_int; + end if; + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error ", + GenericName => " FIRST_WORD_FALL_THROUGH ", + EntityName => "AFIFO36_INTERNAL", + GenericValue => FIRST_WORD_FALL_THROUGH, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " true or false ", + TailMsg => "", + MsgSeverity => failure + ); + end case; + + + if (EN_SYN = FALSE) then + + if (fwft_var = '0') then + + if ((rd_offset_int < 5) or (rd_offset_int > addr_limit_var - 5)) then + write( Message, STRING'("Attribute Syntax Error : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("ALMOST_EMPTY_OFFSET on AFIFO36_INTERNAL is set to ") ); + write( Message, rd_offset_int); + write( Message, STRING'(". Legal values for this attribute are ") ); + write( Message, 5); + write( Message, STRING'(" to ") ); + write( Message, addr_limit_var - 5 ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + + if ((wr_offset_int < 4) or (wr_offset_int > addr_limit_var - 5)) then + write( Message, STRING'("Attribute Syntax Error : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("ALMOST_FULL_OFFSET on AFIFO36_INTERNAL is set to ") ); + write( Message, wr_offset_int); + write( Message, STRING'(". Legal values for this attribute are ") ); + write( Message, 4); + write( Message, STRING'(" to ") ); + write( Message, addr_limit_var - 5 ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + + else + + if ((rd_offset_int < 6) or (rd_offset_int > addr_limit_var - 4)) then + write( Message, STRING'("Attribute Syntax Error : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("ALMOST_EMPTY_OFFSET on AFIFO36_INTERNAL is set to ") ); + write( Message, rd_offset_int); + write( Message, STRING'(". Legal values for this attribute are ") ); + write( Message, 6); + write( Message, STRING'(" to ") ); + write( Message, addr_limit_var - 4 ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + + if ((wr_offset_int < 4) or (wr_offset_int > addr_limit_var - 5)) then + write( Message, STRING'("Attribute Syntax Error : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("ALMOST_FULL_OFFSET on AFIFO36_INTERNAL is set to ") ); + write( Message, wr_offset_int); + write( Message, STRING'(". Legal values for this attribute are ") ); + write( Message, 4); + write( Message, STRING'(" to ") ); + write( Message, addr_limit_var - 5 ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + + end if; + + else + + if ((fwft_var = '0') and ((rd_offset_int < 1) or (rd_offset_int > addr_limit_var - 2))) then + write( Message, STRING'("Attribute Syntax Error : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("ALMOST_EMPTY_OFFSET on AFIFO36_INTERNAL is set to ") ); + write( Message, rd_offset_int); + write( Message, STRING'(". Legal values for this attribute are ") ); + write( Message, 1); + write( Message, STRING'(" to ") ); + write( Message, addr_limit_var - 2 ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + + if ((fwft_var = '0') and ((wr_offset_int < 1) or (wr_offset_int > addr_limit_var - 2))) then + write( Message, STRING'("Attribute Syntax Error : ") ); + write( Message, STRING'("The attribute ") ); + write( Message, STRING'("ALMOST_FULL_OFFSET on AFIFO36_INTERNAL is set to ") ); + write( Message, wr_offset_int); + write( Message, STRING'(". Legal values for this attribute are ") ); + write( Message, 1); + write( Message, STRING'(" to ") ); + write( Message, addr_limit_var - 2 ); + ASSERT FALSE REPORT Message.ALL SEVERITY Failure; + DEALLOCATE (Message); + end if; + + end if; + + + if(fwft_var = '1' and EN_SYN = TRUE) then + assert false + report "DRC Error : First word fall through is not supported in synchronous mode on AFIFO36_INTERNAL." + severity failure; + end if; + + + if(EN_SYN = FALSE and DO_REG = 0) then + assert false + report "DRC Error : DO_REG = 0 is invalid when EN_SYN is set to FALSE on AFIFO36_INTERNAL." + severity failure; + end if; + + + if (not (EN_ECC_WRITE = TRUE or EN_ECC_WRITE = FALSE)) then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error ", + GenericName => " EN_ECC_WRITE ", + EntityName => "AFIFO36_INTERNAL", + GenericValue => EN_ECC_WRITE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " true or false ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + + if (not (EN_ECC_READ = TRUE or EN_ECC_READ = FALSE)) then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error ", + GenericName => " EN_ECC_READ ", + EntityName => "AFIFO36_INTERNAL", + GenericValue => EN_ECC_READ, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " true or false ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + + if ((EN_ECC_WRITE = TRUE or EN_ECC_READ = TRUE) and DATA_WIDTH /= 72) then + assert false + report "DRC Error : The attribute DATA_WIDTH must be set to 72 when AFIFO36_INTERNAL is configured in the ECC mode." + severity failure; + end if; + + + addr_limit <= addr_limit_var; + fwft <= fwft_var; + ae_full <= ae_full_var; + ae_empty <= ae_empty_var; + first_time := false; + end if; + wait; + end process prcs_initialize; + +--#################################################################### +--##### CR 182616 ##### +--#################################################################### + prcs_rst_rdin_wrin:process(RST_dly, RDEN_dly, WREN_dly) + begin + if(RST_dly = '1') then + if(RDEN_dly = '1') then + assert false + report "Warning : RDEN on AFIFO36_INTERNAL is high when RST is high. RDEN should be low during reset." + severity Warning; + end if; + + if(WREN_dly = '1') then + assert false + report "Warning : WREN on AFIFO36_INTERNAL is high when RST is high. WREN should be low during reset." + severity Warning; + end if; + end if; + end process prcs_rst_rdin_wrin; +------------------------------------------- + + prcs_3clkrst_readwrite:process(RDCLK_dly, WRCLK_dly) + variable rst_rdckreg_var : std_logic_vector (2 downto 0) := (others => '0'); + variable rst_wrckreg_var : std_logic_vector (2 downto 0) := (others => '0'); + begin + if(rising_edge(RDCLK_dly)) then + rst_rdckreg_var(2) := RST_dly and rst_rdckreg_var(1); + rst_rdckreg_var(1) := RST_dly and rst_rdckreg_var(0); + rst_rdckreg_var(0) := RST_dly; + end if; + + if(rising_edge(WRCLK_dly)) then + rst_wrckreg_var(2) := RST_dly and rst_wrckreg_var(1); + rst_wrckreg_var(1) := RST_dly and rst_wrckreg_var(0); + rst_wrckreg_var(0) := RST_dly; + end if; + + rst_rdckreg <= rst_rdckreg_var; + rst_wrckreg <= rst_wrckreg_var; + end process prcs_3clkrst_readwrite; + + prcs_2clkrst:process(RST_dly) + begin + rst_rdclk_flag <= '0'; + rst_wrclk_flag <= '0'; + + if(falling_edge(RST_dly)) then + if((rst_rdckreg(2) ='0') or (rst_rdckreg(1) ='0') or (rst_rdckreg(0) ='0')) then + assert false + report "Error : RST signal on AFIFO36_INTERNAL stays high for less than three RDCLK clock cycles. RST has to stay high for more than three RDCLK clock cycles" + severity Error; + rst_rdclk_flag <= '1'; + end if; + + if((rst_wrckreg(2) ='0') or (rst_wrckreg(1) ='0') or (rst_wrckreg(0) ='0')) then + assert false + report "Error : RST signal on AFIFO36_INTERNAL stays high for less than three WRCLK clock cycles. RST has to stay high for more than three WRCLK clock cycles" + severity Error; + rst_wrclk_flag <= '1'; + end if; + + end if; + + + end process prcs_2clkrst; + +--#################################################################### +--##### Read ##### +--#################################################################### + prcs_read:process(RDCLK_dly, RST_dly, GSR_dly, update_from_write_prcs, update_from_write_prcs_sync, rst_rdclk_flag, rst_wrclk_flag) + variable first_time : boolean := true; + variable rd_addr_var : integer := 0; + variable wr_addr_var : integer := 0; + variable rdcount_var : integer := 0; + + variable rd_flag_var : std_ulogic := '0'; + variable wr_flag_var : std_ulogic := '0'; + variable awr_flag_var : std_ulogic := '0'; + + variable rdcount_flag_var : std_ulogic := '0'; + + variable do_in : std_logic_vector(MSB_MAX_DO downto 0) := (others => '0'); + variable dop_in : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + + variable almostempty_int : std_ulogic_vector(3 downto 0) := (others => '1'); + variable empty_int : std_ulogic_vector(3 downto 0) := (others => '1'); + variable empty_ram : std_ulogic_vector(3 downto 0) := (others => '1'); + + variable addr_limit_var : integer := 0; + + variable wr1_addr_var : integer := 0; + variable wr1_flag_var : std_ulogic := '0'; + variable rd_prefetch_var : integer := 0; + variable rd_prefetch_flag_var : std_ulogic := '0'; + +-- CR 195129 fix from verilog (may not be necessary for vhdl) +-- Added ren_var/wren_var to remember the old val of RDEN_dly/WREN_dly + + variable rden_var : std_ulogic := '0'; + variable wren_var : std_ulogic := '0'; + + variable do_buf : std_logic_vector(MSB_MAX_DO downto 0) := (others => '0'); + variable dop_buf : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + variable dopr_ecc : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + variable tmp_syndrome_int : integer; + variable syndrome : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + variable ecc_bit_position : std_logic_vector(71 downto 0) := (others => '0'); + variable di_dly_ecc_corrected : std_logic_vector(MSB_MAX_DO downto 0) := (others => '0'); + variable dip_dly_ecc_corrected : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + variable sbiterr_out : std_ulogic := '0'; + variable dbiterr_out : std_ulogic := '0'; + variable sbiterr_out_out_var : std_ulogic := '0'; + variable dbiterr_out_out_var : std_ulogic := '0'; + variable DO_OUTREG_var: std_logic_vector(MSB_MAX_DO downto 0) := (others => '0'); + variable DOP_OUTREG_var : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + + begin + if((GSR_dly = '1') or (RST_dly = '1')) then + rd_addr <= 0; + rd_flag <= '0'; + + rd_addr_var := 0; + wr_addr_var := 0; + wr1_addr_var := 0; + rd_prefetch_var := 0; + + rdcount_var := 0; + + rd_flag_var := '0'; + wr_flag_var := '0'; + awr_flag_var := '0'; + wr1_flag_var := '0'; + rd_prefetch_flag_var := '0'; + + rdcount_flag_var := '0'; + + empty_int := (others => '1'); + almostempty_int := (others => '1'); + empty_ram := (others => '1'); + + sbiterr_zd <= '0'; + dbiterr_zd <= '0'; + + ALMOSTEMPTY_zd <= '1'; + EMPTY_zd <= '1'; + RDERR_zd <= '0'; + RDCOUNT_zd <= (others => '0'); + + if(GSR_dly = '1') then + DO_zd((mem_width -1) downto 0) <= (others => '0'); + DO_OUTREG_zd((mem_width -1) downto 0) <= (others => '0'); + if (DATA_WIDTH /= 4) then + DOP_zd((memp_width -1) downto 0) <= (others => '0'); + DOP_OUTREG_zd((memp_width -1) downto 0) <= (others => '0'); + end if; + end if; + + elsif ((rst_rdclk_flag = '1') or (rst_wrclk_flag = '1'))then + + rd_addr <= 0; + rd_flag <= '0'; + + rd_addr_var := 0; + wr_addr_var := 0; + wr1_addr_var := 0; + rd_prefetch_var := 0; + + rdcount_var := 0; + + rd_flag_var := '0'; + wr_flag_var := '0'; + awr_flag_var := '0'; + wr1_flag_var := '0'; + rd_prefetch_flag_var := '0'; + + rdcount_flag_var := '0'; + + empty_int := (others => '1'); + almostempty_int := (others => '1'); + empty_ram := (others => '1'); + + ALMOSTEMPTY_zd <= 'X'; + EMPTY_zd <= 'X'; + RDERR_zd <= 'X'; + RDCOUNT_zd <= (others => 'X'); + + sbiterr_zd <= 'X'; + dbiterr_zd <= 'X'; + + DO_zd((mem_width -1) downto 0) <= (others => 'X'); + DO_OUTREG_zd((mem_width -1) downto 0) <= (others => 'X'); + + if (DATA_WIDTH /= 4) then + DOP_zd((memp_width -1) downto 0) <= (others => 'X'); + DOP_OUTREG_zd((memp_width -1) downto 0) <= (others => 'X'); + end if; + + elsif ((GSR_dly = '0') and (RST_dly = '0'))then + + rden_var := RDEN_dly; + wren_var := WREN_dly; + + if(rising_edge(RDCLK_dly)) then + + rd_flag_var := rd_flag; + wr_flag_var := wr_flag; + awr_flag_var := awr_flag; + + rd_addr_var := rd_addr; + wr_addr_var := wr_addr; + + rdcount_var := SLV_TO_INT(RDCOUNT_zd); + rdcount_flag_var := rdcount_flag; + + + if (sync = '1') then + + DO_OUTREG_var := DO_zd; + DOP_OUTREG_var := DOP_zd; + + if (RDEN_dly = '1') then + + if (EMPTY_zd = '0') then + + do_buf(mem_width-1 downto 0) := mem(rdcount_var); + dop_buf(memp_width-1 downto 0) := memp(rdcount_var); + + -- ECC decode + if (EN_ECC_READ = TRUE) then + -- regenerate parity + dopr_ecc(0) := do_buf(0) xor do_buf(1) xor do_buf(3) xor do_buf(4) xor do_buf(6) xor do_buf(8) + xor do_buf(10) xor do_buf(11) xor do_buf(13) xor do_buf(15) xor do_buf(17) xor do_buf(19) + xor do_buf(21) xor do_buf(23) xor do_buf(25) xor do_buf(26) xor do_buf(28) + xor do_buf(30) xor do_buf(32) xor do_buf(34) xor do_buf(36) xor do_buf(38) + xor do_buf(40) xor do_buf(42) xor do_buf(44) xor do_buf(46) xor do_buf(48) + xor do_buf(50) xor do_buf(52) xor do_buf(54) xor do_buf(56) xor do_buf(57) xor do_buf(59) + xor do_buf(61) xor do_buf(63); + + dopr_ecc(1) := do_buf(0) xor do_buf(2) xor do_buf(3) xor do_buf(5) xor do_buf(6) xor do_buf(9) + xor do_buf(10) xor do_buf(12) xor do_buf(13) xor do_buf(16) xor do_buf(17) + xor do_buf(20) xor do_buf(21) xor do_buf(24) xor do_buf(25) xor do_buf(27) xor do_buf(28) + xor do_buf(31) xor do_buf(32) xor do_buf(35) xor do_buf(36) xor do_buf(39) + xor do_buf(40) xor do_buf(43) xor do_buf(44) xor do_buf(47) xor do_buf(48) + xor do_buf(51) xor do_buf(52) xor do_buf(55) xor do_buf(56) xor do_buf(58) xor do_buf(59) + xor do_buf(62) xor do_buf(63); + + dopr_ecc(2) := do_buf(1) xor do_buf(2) xor do_buf(3) xor do_buf(7) xor do_buf(8) xor do_buf(9) + xor do_buf(10) xor do_buf(14) xor do_buf(15) xor do_buf(16) xor do_buf(17) + xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25) xor do_buf(29) + xor do_buf(30) xor do_buf(31) xor do_buf(32) xor do_buf(37) xor do_buf(38) xor do_buf(39) + xor do_buf(40) xor do_buf(45) xor do_buf(46) xor do_buf(47) xor do_buf(48) + xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56) + xor do_buf(60) xor do_buf(61) xor do_buf(62) xor do_buf(63); + + dopr_ecc(3) := do_buf(4) xor do_buf(5) xor do_buf(6) xor do_buf(7) xor do_buf(8) xor do_buf(9) + xor do_buf(10) xor do_buf(18) xor do_buf(19) + xor do_buf(20) xor do_buf(21) xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25) + xor do_buf(33) xor do_buf(34) xor do_buf(35) xor do_buf(36) xor do_buf(37) xor do_buf(38) xor do_buf(39) + xor do_buf(40) xor do_buf(49) + xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56); + + dopr_ecc(4) := do_buf(11) xor do_buf(12) xor do_buf(13) xor do_buf(14) xor do_buf(15) xor do_buf(16) xor do_buf(17) xor do_buf(18) xor do_buf(19) + xor do_buf(20) xor do_buf(21) xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25) + xor do_buf(41) xor do_buf(42) xor do_buf(43) xor do_buf(44) xor do_buf(45) xor do_buf(46) xor do_buf(47) xor do_buf(48) xor do_buf(49) + xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56); + + + dopr_ecc(5) := do_buf(26) xor do_buf(27) xor do_buf(28) xor do_buf(29) + xor do_buf(30) xor do_buf(31) xor do_buf(32) xor do_buf(33) xor do_buf(34) xor do_buf(35) xor do_buf(36) xor do_buf(37) xor do_buf(38) + xor do_buf(39) xor do_buf(40) xor do_buf(41) xor do_buf(42) xor do_buf(43) xor do_buf(44) xor do_buf(45) xor do_buf(46) xor do_buf(47) + xor do_buf(48) xor do_buf(49) xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56); + + dopr_ecc(6) := do_buf(57) xor do_buf(58) xor do_buf(59) + xor do_buf(60) xor do_buf(61) xor do_buf(62) xor do_buf(63); + + dopr_ecc(7) := dop_buf(0) xor dop_buf(1) xor dop_buf(2) xor dop_buf(3) xor dop_buf(4) xor dop_buf(5) xor dop_buf(6) + xor do_buf(0) xor do_buf(1) xor do_buf(2) xor do_buf(3) xor do_buf(4) xor do_buf(5) xor do_buf(6) xor do_buf(7) xor do_buf(8) xor do_buf(9) + xor do_buf(10) xor do_buf(11) xor do_buf(12) xor do_buf(13) xor do_buf(14) xor do_buf(15) xor do_buf(16) xor do_buf(17) xor do_buf(18) + xor do_buf(19) xor do_buf(20) xor do_buf(21) xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25) xor do_buf(26) xor do_buf(27) + xor do_buf(28) xor do_buf(29) xor do_buf(30) xor do_buf(31) xor do_buf(32) xor do_buf(33) xor do_buf(34) xor do_buf(35) xor do_buf(36) + xor do_buf(37) xor do_buf(38) xor do_buf(39) xor do_buf(40) xor do_buf(41) xor do_buf(42) xor do_buf(43) xor do_buf(44) xor do_buf(45) + xor do_buf(46) xor do_buf(47) xor do_buf(48) xor do_buf(49) xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) + xor do_buf(55) xor do_buf(56) xor do_buf(57) xor do_buf(58) xor do_buf(59) xor do_buf(60) xor do_buf(61) xor do_buf(62) xor do_buf(63); + + syndrome := dopr_ecc xor dop_buf; + + if (syndrome /= "00000000") then + + if (syndrome(7) = '1') then -- dectect single bit error + + ecc_bit_position := do_buf(63 downto 57) & dop_buf(6) & do_buf(56 downto 26) & dop_buf(5) & do_buf(25 downto 11) & dop_buf(4) & do_buf(10 downto 4) & dop_buf(3) & do_buf(3 downto 1) & dop_buf(2) & do_buf(0) & dop_buf(1 downto 0) & dop_buf(7); + + tmp_syndrome_int := SLV_TO_INT(syndrome(6 downto 0)); + ecc_bit_position(tmp_syndrome_int) := not ecc_bit_position(tmp_syndrome_int); -- correct single bit error in the output + + di_dly_ecc_corrected := ecc_bit_position(71 downto 65) & ecc_bit_position(63 downto 33) & ecc_bit_position(31 downto 17) & ecc_bit_position(15 downto 9) & ecc_bit_position(7 downto 5) & ecc_bit_position(3); -- correct single bit error in the memory + + do_buf := di_dly_ecc_corrected; + + dip_dly_ecc_corrected := ecc_bit_position(0) & ecc_bit_position(64) & ecc_bit_position(32) & ecc_bit_position(16) & ecc_bit_position(8) & ecc_bit_position(4) & ecc_bit_position(2 downto 1); -- correct single bit error in the parity memory + + dop_buf := dip_dly_ecc_corrected; + + dbiterr_out_out_var := '0'; -- latch out in sync mode + sbiterr_out_out_var := '1'; + + elsif (syndrome(7) = '0') then -- double bit error + sbiterr_out_out_var := '0'; + dbiterr_out_out_var := '1'; + end if; + else + dbiterr_out_out_var := '0'; + sbiterr_out_out_var := '0'; + end if; + end if; + + DO_zd <= do_buf; + DOP_zd <= dop_buf; + + rdcount_var := (rdcount_var + 1) mod addr_limit; + + if (rdcount_var = 0) then + rdcount_flag_var := not rdcount_flag_var; + end if; + + end if; + end if; + + + if (RDEN_dly = '1' and EMPTY_zd = '1') then + RDERR_zd <= '1'; + else + RDERR_zd <= '0'; + end if; + + + if (WREN_dly = '1') then + EMPTY_zd <= '0'; + elsif (rdcount_var = wr_addr_var and rdcount_flag_var = wr_flag_var) then + EMPTY_zd <= '1'; + end if; + + if((((rdcount_var + ae_empty) >= wr_addr_var) and (rdcount_flag_var = wr_flag_var)) or (((rdcount_var + ae_empty) >= (wr_addr_var + addr_limit)) and (rdcount_flag_var /= wr_flag_var))) then + ALMOSTEMPTY_zd <= '1'; + end if; + + update_from_read_prcs_sync <= not update_from_read_prcs_sync; + + elsif (sync = '0') then + + dbiterr_out_out_var := dbiterr_out; -- reg out in async mode + sbiterr_out_out_var := sbiterr_out; + + if(fwft = '0') then + addr_limit_var := addr_limit; + if((rden_var = '1') and (rd_addr_var /= rdcount_var)) then + DO_zd <= do_in; + if (DATA_WIDTH /= 4) then + DOP_zd <= dop_in; + end if; + rd_addr_var := (rd_addr_var + 1) mod addr_limit; + if(rd_addr_var = 0) then + rd_flag_var := NOT rd_flag_var; + end if; + end if; + if (((rd_addr_var = rdcount_var) and (empty_ram(3) = '0')) or + ((rden_var = '1') and (empty_ram(1) = '0'))) then + do_buf(mem_width-1 downto 0) := mem(rdcount_var); + dop_buf(memp_width-1 downto 0) := memp(rdcount_var); + + + -- ECC decode + if (EN_ECC_READ = TRUE) then + -- regenerate parity + dopr_ecc(0) := do_buf(0) xor do_buf(1) xor do_buf(3) xor do_buf(4) xor do_buf(6) xor do_buf(8) + xor do_buf(10) xor do_buf(11) xor do_buf(13) xor do_buf(15) xor do_buf(17) xor do_buf(19) + xor do_buf(21) xor do_buf(23) xor do_buf(25) xor do_buf(26) xor do_buf(28) + xor do_buf(30) xor do_buf(32) xor do_buf(34) xor do_buf(36) xor do_buf(38) + xor do_buf(40) xor do_buf(42) xor do_buf(44) xor do_buf(46) xor do_buf(48) + xor do_buf(50) xor do_buf(52) xor do_buf(54) xor do_buf(56) xor do_buf(57) xor do_buf(59) + xor do_buf(61) xor do_buf(63); + + dopr_ecc(1) := do_buf(0) xor do_buf(2) xor do_buf(3) xor do_buf(5) xor do_buf(6) xor do_buf(9) + xor do_buf(10) xor do_buf(12) xor do_buf(13) xor do_buf(16) xor do_buf(17) + xor do_buf(20) xor do_buf(21) xor do_buf(24) xor do_buf(25) xor do_buf(27) xor do_buf(28) + xor do_buf(31) xor do_buf(32) xor do_buf(35) xor do_buf(36) xor do_buf(39) + xor do_buf(40) xor do_buf(43) xor do_buf(44) xor do_buf(47) xor do_buf(48) + xor do_buf(51) xor do_buf(52) xor do_buf(55) xor do_buf(56) xor do_buf(58) xor do_buf(59) + xor do_buf(62) xor do_buf(63); + + dopr_ecc(2) := do_buf(1) xor do_buf(2) xor do_buf(3) xor do_buf(7) xor do_buf(8) xor do_buf(9) + xor do_buf(10) xor do_buf(14) xor do_buf(15) xor do_buf(16) xor do_buf(17) + xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25) xor do_buf(29) + xor do_buf(30) xor do_buf(31) xor do_buf(32) xor do_buf(37) xor do_buf(38) xor do_buf(39) + xor do_buf(40) xor do_buf(45) xor do_buf(46) xor do_buf(47) xor do_buf(48) + xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56) + xor do_buf(60) xor do_buf(61) xor do_buf(62) xor do_buf(63); + + dopr_ecc(3) := do_buf(4) xor do_buf(5) xor do_buf(6) xor do_buf(7) xor do_buf(8) xor do_buf(9) + xor do_buf(10) xor do_buf(18) xor do_buf(19) + xor do_buf(20) xor do_buf(21) xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25) + xor do_buf(33) xor do_buf(34) xor do_buf(35) xor do_buf(36) xor do_buf(37) xor do_buf(38) xor do_buf(39) + xor do_buf(40) xor do_buf(49) + xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56); + + dopr_ecc(4) := do_buf(11) xor do_buf(12) xor do_buf(13) xor do_buf(14) xor do_buf(15) xor do_buf(16) xor do_buf(17) xor do_buf(18) xor do_buf(19) + xor do_buf(20) xor do_buf(21) xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25) + xor do_buf(41) xor do_buf(42) xor do_buf(43) xor do_buf(44) xor do_buf(45) xor do_buf(46) xor do_buf(47) xor do_buf(48) xor do_buf(49) + xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56); + + + dopr_ecc(5) := do_buf(26) xor do_buf(27) xor do_buf(28) xor do_buf(29) + xor do_buf(30) xor do_buf(31) xor do_buf(32) xor do_buf(33) xor do_buf(34) xor do_buf(35) xor do_buf(36) xor do_buf(37) xor do_buf(38) + xor do_buf(39) xor do_buf(40) xor do_buf(41) xor do_buf(42) xor do_buf(43) xor do_buf(44) xor do_buf(45) xor do_buf(46) xor do_buf(47) + xor do_buf(48) xor do_buf(49) xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56); + + dopr_ecc(6) := do_buf(57) xor do_buf(58) xor do_buf(59) + xor do_buf(60) xor do_buf(61) xor do_buf(62) xor do_buf(63); + + dopr_ecc(7) := dop_buf(0) xor dop_buf(1) xor dop_buf(2) xor dop_buf(3) xor dop_buf(4) xor dop_buf(5) xor dop_buf(6) + xor do_buf(0) xor do_buf(1) xor do_buf(2) xor do_buf(3) xor do_buf(4) xor do_buf(5) xor do_buf(6) xor do_buf(7) xor do_buf(8) xor do_buf(9) + xor do_buf(10) xor do_buf(11) xor do_buf(12) xor do_buf(13) xor do_buf(14) xor do_buf(15) xor do_buf(16) xor do_buf(17) xor do_buf(18) + xor do_buf(19) xor do_buf(20) xor do_buf(21) xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25) xor do_buf(26) xor do_buf(27) + xor do_buf(28) xor do_buf(29) xor do_buf(30) xor do_buf(31) xor do_buf(32) xor do_buf(33) xor do_buf(34) xor do_buf(35) xor do_buf(36) + xor do_buf(37) xor do_buf(38) xor do_buf(39) xor do_buf(40) xor do_buf(41) xor do_buf(42) xor do_buf(43) xor do_buf(44) xor do_buf(45) + xor do_buf(46) xor do_buf(47) xor do_buf(48) xor do_buf(49) xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) + xor do_buf(55) xor do_buf(56) xor do_buf(57) xor do_buf(58) xor do_buf(59) xor do_buf(60) xor do_buf(61) xor do_buf(62) xor do_buf(63); + + syndrome := dopr_ecc xor dop_buf; + + if (syndrome /= "00000000") then + + if (syndrome(7) = '1') then -- dectect single bit error + + ecc_bit_position := do_buf(63 downto 57) & dop_buf(6) & do_buf(56 downto 26) & dop_buf(5) & do_buf(25 downto 11) & dop_buf(4) & do_buf(10 downto 4) & dop_buf(3) & do_buf(3 downto 1) & dop_buf(2) & do_buf(0) & dop_buf(1 downto 0) & dop_buf(7); + + tmp_syndrome_int := SLV_TO_INT(syndrome(6 downto 0)); + ecc_bit_position(tmp_syndrome_int) := not ecc_bit_position(tmp_syndrome_int); -- correct single bit error in the output + + di_dly_ecc_corrected := ecc_bit_position(71 downto 65) & ecc_bit_position(63 downto 33) & ecc_bit_position(31 downto 17) & ecc_bit_position(15 downto 9) & ecc_bit_position(7 downto 5) & ecc_bit_position(3); -- correct single bit error in the memory + + do_buf := di_dly_ecc_corrected; + + dip_dly_ecc_corrected := ecc_bit_position(0) & ecc_bit_position(64) & ecc_bit_position(32) & ecc_bit_position(16) & ecc_bit_position(8) & ecc_bit_position(4) & ecc_bit_position(2 downto 1); -- correct single bit error in the parity memory + + dop_buf := dip_dly_ecc_corrected; + + dbiterr_out := '0'; -- reg out in async mode + sbiterr_out := '1'; + + elsif (syndrome(7) = '0') then -- double bit error + sbiterr_out := '0'; + dbiterr_out := '1'; + end if; + else + dbiterr_out := '0'; + sbiterr_out := '0'; + end if; + end if; + + + do_in := do_buf; + dop_in := dop_buf; + + + rdcount_var := (rdcount_var + 1) mod addr_limit; + + if(rdcount_var = 0) then + rdcount_flag_var := NOT rdcount_flag_var; + end if; + + end if; + + elsif(fwft = '1') then + if((rden_var = '1') and (rd_addr_var /= rd_prefetch_var)) then + rd_prefetch_var := (rd_prefetch_var + 1) mod addr_limit; + if(rd_prefetch_var = 0) then + rd_prefetch_flag_var := NOT rd_prefetch_flag_var; + end if; + end if; + if((rd_prefetch_var = rd_addr_var) and (rd_addr_var /= rdcount_var)) then + DO_zd <= do_in; + if (DATA_WIDTH /= 4) then + DOP_zd <= dop_in; + end if; + rd_addr_var := (rd_addr_var + 1) mod addr_limit; + if(rd_addr_var = 0) then + rd_flag_var := NOT rd_flag_var; + end if; + end if; + if(((rd_addr_var = rdcount_var) and (empty_ram(3) = '0')) or + ((rden_var = '1') and (empty_ram(1) = '0')) or + ((rden_var = '0') and (empty_ram(1) = '0') and (rd_addr_var = rdcount_var))) then + do_buf(mem_width-1 downto 0) := mem(rdcount_var); + dop_buf(memp_width-1 downto 0) := memp(rdcount_var); + + -- ECC decode + if (EN_ECC_READ = TRUE) then + -- regenerate parity + dopr_ecc(0) := do_buf(0) xor do_buf(1) xor do_buf(3) xor do_buf(4) xor do_buf(6) xor do_buf(8) + xor do_buf(10) xor do_buf(11) xor do_buf(13) xor do_buf(15) xor do_buf(17) xor do_buf(19) + xor do_buf(21) xor do_buf(23) xor do_buf(25) xor do_buf(26) xor do_buf(28) + xor do_buf(30) xor do_buf(32) xor do_buf(34) xor do_buf(36) xor do_buf(38) + xor do_buf(40) xor do_buf(42) xor do_buf(44) xor do_buf(46) xor do_buf(48) + xor do_buf(50) xor do_buf(52) xor do_buf(54) xor do_buf(56) xor do_buf(57) xor do_buf(59) + xor do_buf(61) xor do_buf(63); + + dopr_ecc(1) := do_buf(0) xor do_buf(2) xor do_buf(3) xor do_buf(5) xor do_buf(6) xor do_buf(9) + xor do_buf(10) xor do_buf(12) xor do_buf(13) xor do_buf(16) xor do_buf(17) + xor do_buf(20) xor do_buf(21) xor do_buf(24) xor do_buf(25) xor do_buf(27) xor do_buf(28) + xor do_buf(31) xor do_buf(32) xor do_buf(35) xor do_buf(36) xor do_buf(39) + xor do_buf(40) xor do_buf(43) xor do_buf(44) xor do_buf(47) xor do_buf(48) + xor do_buf(51) xor do_buf(52) xor do_buf(55) xor do_buf(56) xor do_buf(58) xor do_buf(59) + xor do_buf(62) xor do_buf(63); + + dopr_ecc(2) := do_buf(1) xor do_buf(2) xor do_buf(3) xor do_buf(7) xor do_buf(8) xor do_buf(9) + xor do_buf(10) xor do_buf(14) xor do_buf(15) xor do_buf(16) xor do_buf(17) + xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25) xor do_buf(29) + xor do_buf(30) xor do_buf(31) xor do_buf(32) xor do_buf(37) xor do_buf(38) xor do_buf(39) + xor do_buf(40) xor do_buf(45) xor do_buf(46) xor do_buf(47) xor do_buf(48) + xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56) + xor do_buf(60) xor do_buf(61) xor do_buf(62) xor do_buf(63); + + dopr_ecc(3) := do_buf(4) xor do_buf(5) xor do_buf(6) xor do_buf(7) xor do_buf(8) xor do_buf(9) + xor do_buf(10) xor do_buf(18) xor do_buf(19) + xor do_buf(20) xor do_buf(21) xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25) + xor do_buf(33) xor do_buf(34) xor do_buf(35) xor do_buf(36) xor do_buf(37) xor do_buf(38) xor do_buf(39) + xor do_buf(40) xor do_buf(49) + xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56); + + dopr_ecc(4) := do_buf(11) xor do_buf(12) xor do_buf(13) xor do_buf(14) xor do_buf(15) xor do_buf(16) xor do_buf(17) xor do_buf(18) xor do_buf(19) + xor do_buf(20) xor do_buf(21) xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25) + xor do_buf(41) xor do_buf(42) xor do_buf(43) xor do_buf(44) xor do_buf(45) xor do_buf(46) xor do_buf(47) xor do_buf(48) xor do_buf(49) + xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56); + + + dopr_ecc(5) := do_buf(26) xor do_buf(27) xor do_buf(28) xor do_buf(29) + xor do_buf(30) xor do_buf(31) xor do_buf(32) xor do_buf(33) xor do_buf(34) xor do_buf(35) xor do_buf(36) xor do_buf(37) xor do_buf(38) + xor do_buf(39) xor do_buf(40) xor do_buf(41) xor do_buf(42) xor do_buf(43) xor do_buf(44) xor do_buf(45) xor do_buf(46) xor do_buf(47) + xor do_buf(48) xor do_buf(49) xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) xor do_buf(55) xor do_buf(56); + + dopr_ecc(6) := do_buf(57) xor do_buf(58) xor do_buf(59) + xor do_buf(60) xor do_buf(61) xor do_buf(62) xor do_buf(63); + + dopr_ecc(7) := dop_buf(0) xor dop_buf(1) xor dop_buf(2) xor dop_buf(3) xor dop_buf(4) xor dop_buf(5) xor dop_buf(6) + xor do_buf(0) xor do_buf(1) xor do_buf(2) xor do_buf(3) xor do_buf(4) xor do_buf(5) xor do_buf(6) xor do_buf(7) xor do_buf(8) xor do_buf(9) + xor do_buf(10) xor do_buf(11) xor do_buf(12) xor do_buf(13) xor do_buf(14) xor do_buf(15) xor do_buf(16) xor do_buf(17) xor do_buf(18) + xor do_buf(19) xor do_buf(20) xor do_buf(21) xor do_buf(22) xor do_buf(23) xor do_buf(24) xor do_buf(25) xor do_buf(26) xor do_buf(27) + xor do_buf(28) xor do_buf(29) xor do_buf(30) xor do_buf(31) xor do_buf(32) xor do_buf(33) xor do_buf(34) xor do_buf(35) xor do_buf(36) + xor do_buf(37) xor do_buf(38) xor do_buf(39) xor do_buf(40) xor do_buf(41) xor do_buf(42) xor do_buf(43) xor do_buf(44) xor do_buf(45) + xor do_buf(46) xor do_buf(47) xor do_buf(48) xor do_buf(49) xor do_buf(50) xor do_buf(51) xor do_buf(52) xor do_buf(53) xor do_buf(54) + xor do_buf(55) xor do_buf(56) xor do_buf(57) xor do_buf(58) xor do_buf(59) xor do_buf(60) xor do_buf(61) xor do_buf(62) xor do_buf(63); + + syndrome := dopr_ecc xor dop_buf; + + if (syndrome /= "00000000") then + + if (syndrome(7) = '1') then -- dectect single bit error + + ecc_bit_position := do_buf(63 downto 57) & dop_buf(6) & do_buf(56 downto 26) & dop_buf(5) & do_buf(25 downto 11) & dop_buf(4) & do_buf(10 downto 4) & dop_buf(3) & do_buf(3 downto 1) & dop_buf(2) & do_buf(0) & dop_buf(1 downto 0) & dop_buf(7); + + tmp_syndrome_int := SLV_TO_INT(syndrome(6 downto 0)); + ecc_bit_position(tmp_syndrome_int) := not ecc_bit_position(tmp_syndrome_int); -- correct single bit error in the output + + di_dly_ecc_corrected := ecc_bit_position(71 downto 65) & ecc_bit_position(63 downto 33) & ecc_bit_position(31 downto 17) & ecc_bit_position(15 downto 9) & ecc_bit_position(7 downto 5) & ecc_bit_position(3); -- correct single bit error in the memory + + do_buf := di_dly_ecc_corrected; + + dip_dly_ecc_corrected := ecc_bit_position(0) & ecc_bit_position(64) & ecc_bit_position(32) & ecc_bit_position(16) & ecc_bit_position(8) & ecc_bit_position(4) & ecc_bit_position(2 downto 1); -- correct single bit error in the parity memory + + dop_buf := dip_dly_ecc_corrected; + + dbiterr_out := '0'; + sbiterr_out := '1'; + + elsif (syndrome(7) = '0') then -- double bit error + sbiterr_out := '0'; + dbiterr_out := '1'; + end if; + + else + dbiterr_out := '0'; + sbiterr_out := '0'; + end if; + end if; + + + do_in := do_buf; + dop_in := dop_buf; + + + rdcount_var := (rdcount_var + 1) mod addr_limit; + + if(rdcount_var = 0) then + rdcount_flag_var := NOT rdcount_flag_var; + end if; + + end if; + + end if; --- end if(fwft = '1') + + + ALMOSTEMPTY_zd <= almostempty_int(3); + + if((((rdcount_var + ae_empty) >= wr_addr_var) and (rdcount_flag_var = awr_flag_var)) or (((rdcount_var + ae_empty) >= (wr_addr_var + addr_limit)) and (rdcount_flag_var /= awr_flag_var))) then + almostempty_int(3) := '1'; + almostempty_int(2) := '1'; + almostempty_int(1) := '1'; + almostempty_int(0) := '1'; + elsif(almostempty_int(2) = '0') then + -- added to match verilog + if (rdcount_var <= rdcount_var + ae_empty or rdcount_flag_var /= awr_flag_var) then + almostempty_int(3) := almostempty_int(0); + almostempty_int(0) := '0'; + end if; + end if; + + if(fwft = '0') then + if((rdcount_var = rd_addr_var) and (rdcount_flag_var = rd_flag_var)) then + EMPTY_zd <= '1'; + else + EMPTY_zd <= '0'; + end if; + elsif(fwft = '1') then + if((rd_prefetch_var = rd_addr_var) and (rd_prefetch_flag_var = rd_flag_var)) then + EMPTY_zd <= '1'; + else + EMPTY_zd <= '0'; + end if; + end if; + + if((rdcount_var = wr_addr_var) and (rdcount_flag_var = awr_flag_var)) then + empty_ram(2) := '1'; + empty_ram(1) := '1'; + empty_ram(0) := '1'; + else + empty_ram(2) := empty_ram(1); + empty_ram(1) := empty_ram(0); + empty_ram(0) := '0'; + end if; + + if((rdcount_var = wr1_addr_var) and (rdcount_flag_var = wr1_flag_var)) then + empty_ram(3) := '1'; + else + empty_ram(3) := '0'; + end if; + + wr1_addr_var := wr_addr; + wr1_flag_var := awr_flag; + + if((rden_var = '1') and (EMPTY_zd = '1')) then + RDERR_zd <= '1'; + else + RDERR_zd <= '0'; + end if; -- end ((rden_var = '1') and (empty_int /= '1')) + + update_from_read_prcs <= NOT update_from_read_prcs; + + end if; + + end if; -- end (rising_edge(RDCLK_dly)) + + end if; -- end (GSR_dly = 1) + + + + if(update_from_write_prcs_sync'event) then + wr_addr_var := wr_addr; + wr_flag_var := wr_flag; + if((((rdcount_var + ae_empty) < wr_addr_var) and (rdcount_flag_var = wr_flag_var)) or + (((rdcount_var + ae_empty) < (wr_addr_var + addr_limit)) and (rdcount_flag_var /= wr_flag_var))) then + if(rdcount_var <= rdcount_var + ae_empty or rdcount_flag_var /= wr_flag_var) then + almostempty_zd <= '0'; + end if; + end if; + end if; + + + if(update_from_write_prcs'event) then + wr_addr_var := wr_addr; + wr_flag_var := wr_flag; + awr_flag_var := awr_flag; + + if((((rdcount_var + ae_empty) < wr_addr_var) and (rdcount_flag_var = awr_flag_var)) or + (((rdcount_var + ae_empty) < ( wr_addr_var + addr_limit)) and (rdcount_flag_var /= awr_flag_var))) then + if(wren_var = '1') then + almostempty_int(2) := almostempty_int(1); + almostempty_int(1) := '0'; + end if; + else + almostempty_int(2) := '1'; + almostempty_int(1) := '1'; + end if; + end if; + + + if (not (rst_rdclk_flag or rst_wrclk_flag) = '1') then + RDCOUNT_zd <= CONV_STD_LOGIC_VECTOR(rdcount_var, MAX_RDCOUNT); + dbiterr_zd <= dbiterr_out_out_var; -- reg out in async mode + sbiterr_zd <= sbiterr_out_out_var; + end if; + + rd_addr <= rd_addr_var; + rd_flag <= rd_flag_var; + rdcount_flag <= rdcount_flag_var; + DO_OUTREG_zd <= DO_OUTREG_var; + DOP_OUTREG_zd <= DOP_OUTREG_var; + + end process prcs_read; + +--#################################################################### +--##### Write ##### +--#################################################################### + prcs_write:process(WRCLK_dly, RST_dly, GSR_dly, update_from_read_prcs, update_from_read_prcs_sync, rst_rdclk_flag, rst_wrclk_flag) + variable first_time : boolean := true; + variable wr_addr_var : integer := 0; + variable rd_addr_var : integer := 0; + variable rdcount_var : integer := 0; + variable wrcount_var : integer := 0; + + variable rd_flag_var : std_ulogic := '0'; + variable wr_flag_var : std_ulogic := '0'; + variable awr_flag_var : std_ulogic := '0'; + + variable rdcount_flag_var : std_ulogic := '0'; + + variable almostfull_int : std_ulogic_vector(3 downto 0) := (others => '0'); + variable full_int : std_ulogic_vector(3 downto 0) := (others => '0'); + +-- CR 195129 fix from verilog (may not be necessary for vhdl) +-- Added ren_var/wren_var to remember the old val of RDEN_dly/WREN_dly + + variable rden_var : std_ulogic := '0'; + variable wren_var : std_ulogic := '0'; + variable dip_ecc : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + variable dip_dly_ecc : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + variable ALMOSTFULL_var : std_ulogic := '0'; + + begin + if ((GSR_dly = '1') or (RST_dly = '1') or (rst_rdclk_flag = '1') or (rst_wrclk_flag = '1'))then + wr_addr_var := 0; + wr_addr <= 0; + wr_flag <= '0'; + awr_flag <= '0'; + + wr_addr_var := 0; + rd_addr_var := 0; + rdcount_var := 0; + wrcount_var := 0; + ALMOSTFULL_var := '0'; + + rd_flag_var := '0'; + wr_flag_var := '0'; + awr_flag_var := '0'; + + rdcount_flag_var := '0'; + + full_int := (others => '0'); + almostfull_int := (others => '0'); + + if ((GSR_dly = '1') or (RST_dly = '1'))then + ALMOSTFULL_zd <= '0'; + FULL_zd <= '0'; + WRERR_zd <= '0'; + WRCOUNT_zd <= (others => '0'); + else + ALMOSTFULL_zd <= 'X'; + FULL_zd <= 'X'; + WRERR_zd <= 'X'; + WRCOUNT_zd <= (others => 'X'); + eccparity_zd <= (others => 'X'); + end if; + + elsif((GSR_dly = '0') and (RST_dly = '0'))then + rden_var := RDEN_dly; + wren_var := WREN_dly; + + if(rising_edge(WRCLK_dly)) then + + rd_flag_var := rd_flag; + wr_flag_var := wr_flag; + awr_flag_var := awr_flag; + + rd_addr_var := rd_addr; + wr_addr_var := wr_addr; + + rdcount_var := SLV_TO_INT(RDCOUNT_zd); + rdcount_flag_var := rdcount_flag; + + if (sync = '1') then + if(wren_dly = '1') then + if (full_zd= '0') then + + -- ECC encode + if (EN_ECC_WRITE = TRUE) then + + -- regenerate parity + dip_ecc(0) := di_dly(0) xor di_dly(1) xor di_dly(3) xor di_dly(4) xor di_dly(6) xor di_dly(8) + xor di_dly(10) xor di_dly(11) xor di_dly(13) xor di_dly(15) xor di_dly(17) xor di_dly(19) + xor di_dly(21) xor di_dly(23) xor di_dly(25) xor di_dly(26) xor di_dly(28) + xor di_dly(30) xor di_dly(32) xor di_dly(34) xor di_dly(36) xor di_dly(38) + xor di_dly(40) xor di_dly(42) xor di_dly(44) xor di_dly(46) xor di_dly(48) + xor di_dly(50) xor di_dly(52) xor di_dly(54) xor di_dly(56) xor di_dly(57) xor di_dly(59) + xor di_dly(61) xor di_dly(63); + + dip_ecc(1) := di_dly(0) xor di_dly(2) xor di_dly(3) xor di_dly(5) xor di_dly(6) xor di_dly(9) + xor di_dly(10) xor di_dly(12) xor di_dly(13) xor di_dly(16) xor di_dly(17) + xor di_dly(20) xor di_dly(21) xor di_dly(24) xor di_dly(25) xor di_dly(27) xor di_dly(28) + xor di_dly(31) xor di_dly(32) xor di_dly(35) xor di_dly(36) xor di_dly(39) + xor di_dly(40) xor di_dly(43) xor di_dly(44) xor di_dly(47) xor di_dly(48) + xor di_dly(51) xor di_dly(52) xor di_dly(55) xor di_dly(56) xor di_dly(58) xor di_dly(59) + xor di_dly(62) xor di_dly(63); + + dip_ecc(2) := di_dly(1) xor di_dly(2) xor di_dly(3) xor di_dly(7) xor di_dly(8) xor di_dly(9) + xor di_dly(10) xor di_dly(14) xor di_dly(15) xor di_dly(16) xor di_dly(17) + xor di_dly(22) xor di_dly(23) xor di_dly(24) xor di_dly(25) xor di_dly(29) + xor di_dly(30) xor di_dly(31) xor di_dly(32) xor di_dly(37) xor di_dly(38) xor di_dly(39) + xor di_dly(40) xor di_dly(45) xor di_dly(46) xor di_dly(47) xor di_dly(48) + xor di_dly(53) xor di_dly(54) xor di_dly(55) xor di_dly(56) + xor di_dly(60) xor di_dly(61) xor di_dly(62) xor di_dly(63); + + dip_ecc(3) := di_dly(4) xor di_dly(5) xor di_dly(6) xor di_dly(7) xor di_dly(8) xor di_dly(9) + xor di_dly(10) xor di_dly(18) xor di_dly(19) + xor di_dly(20) xor di_dly(21) xor di_dly(22) xor di_dly(23) xor di_dly(24) xor di_dly(25) + xor di_dly(33) xor di_dly(34) xor di_dly(35) xor di_dly(36) xor di_dly(37) xor di_dly(38) xor di_dly(39) + xor di_dly(40) xor di_dly(49) + xor di_dly(50) xor di_dly(51) xor di_dly(52) xor di_dly(53) xor di_dly(54) xor di_dly(55) xor di_dly(56); + + dip_ecc(4) := di_dly(11) xor di_dly(12) xor di_dly(13) xor di_dly(14) xor di_dly(15) xor di_dly(16) xor di_dly(17) xor di_dly(18) xor di_dly(19) + xor di_dly(20) xor di_dly(21) xor di_dly(22) xor di_dly(23) xor di_dly(24) xor di_dly(25) + xor di_dly(41) xor di_dly(42) xor di_dly(43) xor di_dly(44) xor di_dly(45) xor di_dly(46) xor di_dly(47) xor di_dly(48) xor di_dly(49) + xor di_dly(50) xor di_dly(51) xor di_dly(52) xor di_dly(53) xor di_dly(54) xor di_dly(55) xor di_dly(56); + + + dip_ecc(5) := di_dly(26) xor di_dly(27) xor di_dly(28) xor di_dly(29) + xor di_dly(30) xor di_dly(31) xor di_dly(32) xor di_dly(33) xor di_dly(34) xor di_dly(35) xor di_dly(36) xor di_dly(37) xor di_dly(38) + xor di_dly(39) xor di_dly(40) xor di_dly(41) xor di_dly(42) xor di_dly(43) xor di_dly(44) xor di_dly(45) xor di_dly(46) xor di_dly(47) + xor di_dly(48) xor di_dly(49) xor di_dly(50) xor di_dly(51) xor di_dly(52) xor di_dly(53) xor di_dly(54) xor di_dly(55) xor di_dly(56); + + dip_ecc(6) := di_dly(57) xor di_dly(58) xor di_dly(59) + xor di_dly(60) xor di_dly(61) xor di_dly(62) xor di_dly(63); + + dip_ecc(7) := dip_ecc(0) xor dip_ecc(1) xor dip_ecc(2) xor dip_ecc(3) xor dip_ecc(4) xor dip_ecc(5) xor dip_ecc(6) + xor di_dly(0) xor di_dly(1) xor di_dly(2) xor di_dly(3) xor di_dly(4) xor di_dly(5) xor di_dly(6) xor di_dly(7) xor di_dly(8) xor di_dly(9) + xor di_dly(10) xor di_dly(11) xor di_dly(12) xor di_dly(13) xor di_dly(14) xor di_dly(15) xor di_dly(16) xor di_dly(17) xor di_dly(18) + xor di_dly(19) xor di_dly(20) xor di_dly(21) xor di_dly(22) xor di_dly(23) xor di_dly(24) xor di_dly(25) xor di_dly(26) xor di_dly(27) + xor di_dly(28) xor di_dly(29) xor di_dly(30) xor di_dly(31) xor di_dly(32) xor di_dly(33) xor di_dly(34) xor di_dly(35) xor di_dly(36) + xor di_dly(37) xor di_dly(38) xor di_dly(39) xor di_dly(40) xor di_dly(41) xor di_dly(42) xor di_dly(43) xor di_dly(44) xor di_dly(45) + xor di_dly(46) xor di_dly(47) xor di_dly(48) xor di_dly(49) xor di_dly(50) xor di_dly(51) xor di_dly(52) xor di_dly(53) xor di_dly(54) + xor di_dly(55) xor di_dly(56) xor di_dly(57) xor di_dly(58) xor di_dly(59) xor di_dly(60) xor di_dly(61) xor di_dly(62) xor di_dly(63); + + ECCPARITY_zd <= dip_ecc; + + dip_dly_ecc := dip_ecc; -- only 64 bits width + + else + + dip_dly_ecc := dip_dly; -- only 64 bits width + + end if; + + mem(wr_addr_var) <= DI_dly(mem_width-1 downto 0); + memp(wr_addr_var) <= dip_dly_ecc(memp_width-1 downto 0); + + wr_addr_var := (wr_addr_var + 1) mod addr_limit; + + if(wr_addr_var = 0) then + wr_flag_var := NOT wr_flag_var; + end if; + + end if; + end if; + + + if ((WREN_dly = '1') and (FULL_zd = '1')) then + WRERR_zd <= '1'; + else + WRERR_zd <= '0'; + end if; + + + if (rden_dly = '1') then + full_zd <= '0'; + elsif (rdcount_var = wr_addr_var and rdcount_flag_var /= wr_flag_var) then + full_zd <= '1'; + end if; + + update_from_write_prcs_sync <= NOT update_from_write_prcs_sync; + + if((((rdcount_var + addr_limit) <= (wr_addr_var + ae_full)) and (rdcount_flag_var = wr_flag_var)) or ((rdcount_var <= (wr_addr_var + ae_full)) and (rdcount_flag_var /= wr_flag_var))) then + almostfull_zd <= '1'; + end if; + + + elsif (sync = '0') then + + if((wren_var = '1') and (full_zd = '0'))then + + -- ECC encode + if (EN_ECC_WRITE = TRUE) then + + -- regenerate parity + dip_ecc(0) := di_dly(0) xor di_dly(1) xor di_dly(3) xor di_dly(4) xor di_dly(6) xor di_dly(8) + xor di_dly(10) xor di_dly(11) xor di_dly(13) xor di_dly(15) xor di_dly(17) xor di_dly(19) + xor di_dly(21) xor di_dly(23) xor di_dly(25) xor di_dly(26) xor di_dly(28) + xor di_dly(30) xor di_dly(32) xor di_dly(34) xor di_dly(36) xor di_dly(38) + xor di_dly(40) xor di_dly(42) xor di_dly(44) xor di_dly(46) xor di_dly(48) + xor di_dly(50) xor di_dly(52) xor di_dly(54) xor di_dly(56) xor di_dly(57) xor di_dly(59) + xor di_dly(61) xor di_dly(63); + + dip_ecc(1) := di_dly(0) xor di_dly(2) xor di_dly(3) xor di_dly(5) xor di_dly(6) xor di_dly(9) + xor di_dly(10) xor di_dly(12) xor di_dly(13) xor di_dly(16) xor di_dly(17) + xor di_dly(20) xor di_dly(21) xor di_dly(24) xor di_dly(25) xor di_dly(27) xor di_dly(28) + xor di_dly(31) xor di_dly(32) xor di_dly(35) xor di_dly(36) xor di_dly(39) + xor di_dly(40) xor di_dly(43) xor di_dly(44) xor di_dly(47) xor di_dly(48) + xor di_dly(51) xor di_dly(52) xor di_dly(55) xor di_dly(56) xor di_dly(58) xor di_dly(59) + xor di_dly(62) xor di_dly(63); + + dip_ecc(2) := di_dly(1) xor di_dly(2) xor di_dly(3) xor di_dly(7) xor di_dly(8) xor di_dly(9) + xor di_dly(10) xor di_dly(14) xor di_dly(15) xor di_dly(16) xor di_dly(17) + xor di_dly(22) xor di_dly(23) xor di_dly(24) xor di_dly(25) xor di_dly(29) + xor di_dly(30) xor di_dly(31) xor di_dly(32) xor di_dly(37) xor di_dly(38) xor di_dly(39) + xor di_dly(40) xor di_dly(45) xor di_dly(46) xor di_dly(47) xor di_dly(48) + xor di_dly(53) xor di_dly(54) xor di_dly(55) xor di_dly(56) + xor di_dly(60) xor di_dly(61) xor di_dly(62) xor di_dly(63); + + dip_ecc(3) := di_dly(4) xor di_dly(5) xor di_dly(6) xor di_dly(7) xor di_dly(8) xor di_dly(9) + xor di_dly(10) xor di_dly(18) xor di_dly(19) + xor di_dly(20) xor di_dly(21) xor di_dly(22) xor di_dly(23) xor di_dly(24) xor di_dly(25) + xor di_dly(33) xor di_dly(34) xor di_dly(35) xor di_dly(36) xor di_dly(37) xor di_dly(38) xor di_dly(39) + xor di_dly(40) xor di_dly(49) + xor di_dly(50) xor di_dly(51) xor di_dly(52) xor di_dly(53) xor di_dly(54) xor di_dly(55) xor di_dly(56); + + dip_ecc(4) := di_dly(11) xor di_dly(12) xor di_dly(13) xor di_dly(14) xor di_dly(15) xor di_dly(16) xor di_dly(17) xor di_dly(18) xor di_dly(19) + xor di_dly(20) xor di_dly(21) xor di_dly(22) xor di_dly(23) xor di_dly(24) xor di_dly(25) + xor di_dly(41) xor di_dly(42) xor di_dly(43) xor di_dly(44) xor di_dly(45) xor di_dly(46) xor di_dly(47) xor di_dly(48) xor di_dly(49) + xor di_dly(50) xor di_dly(51) xor di_dly(52) xor di_dly(53) xor di_dly(54) xor di_dly(55) xor di_dly(56); + + + dip_ecc(5) := di_dly(26) xor di_dly(27) xor di_dly(28) xor di_dly(29) + xor di_dly(30) xor di_dly(31) xor di_dly(32) xor di_dly(33) xor di_dly(34) xor di_dly(35) xor di_dly(36) xor di_dly(37) xor di_dly(38) + xor di_dly(39) xor di_dly(40) xor di_dly(41) xor di_dly(42) xor di_dly(43) xor di_dly(44) xor di_dly(45) xor di_dly(46) xor di_dly(47) + xor di_dly(48) xor di_dly(49) xor di_dly(50) xor di_dly(51) xor di_dly(52) xor di_dly(53) xor di_dly(54) xor di_dly(55) xor di_dly(56); + + dip_ecc(6) := di_dly(57) xor di_dly(58) xor di_dly(59) + xor di_dly(60) xor di_dly(61) xor di_dly(62) xor di_dly(63); + + dip_ecc(7) := dip_ecc(0) xor dip_ecc(1) xor dip_ecc(2) xor dip_ecc(3) xor dip_ecc(4) xor dip_ecc(5) xor dip_ecc(6) + xor di_dly(0) xor di_dly(1) xor di_dly(2) xor di_dly(3) xor di_dly(4) xor di_dly(5) xor di_dly(6) xor di_dly(7) xor di_dly(8) xor di_dly(9) + xor di_dly(10) xor di_dly(11) xor di_dly(12) xor di_dly(13) xor di_dly(14) xor di_dly(15) xor di_dly(16) xor di_dly(17) xor di_dly(18) + xor di_dly(19) xor di_dly(20) xor di_dly(21) xor di_dly(22) xor di_dly(23) xor di_dly(24) xor di_dly(25) xor di_dly(26) xor di_dly(27) + xor di_dly(28) xor di_dly(29) xor di_dly(30) xor di_dly(31) xor di_dly(32) xor di_dly(33) xor di_dly(34) xor di_dly(35) xor di_dly(36) + xor di_dly(37) xor di_dly(38) xor di_dly(39) xor di_dly(40) xor di_dly(41) xor di_dly(42) xor di_dly(43) xor di_dly(44) xor di_dly(45) + xor di_dly(46) xor di_dly(47) xor di_dly(48) xor di_dly(49) xor di_dly(50) xor di_dly(51) xor di_dly(52) xor di_dly(53) xor di_dly(54) + xor di_dly(55) xor di_dly(56) xor di_dly(57) xor di_dly(58) xor di_dly(59) xor di_dly(60) xor di_dly(61) xor di_dly(62) xor di_dly(63); + + ECCPARITY_zd <= dip_ecc; + + dip_dly_ecc := dip_ecc; -- only 64 bits width + + else + + dip_dly_ecc := dip_dly; -- only 64 bits width + + end if; + + mem(wr_addr_var) <= DI_dly(mem_width-1 downto 0); + if (DATA_WIDTH >= 9) then + memp(wr_addr_var) <= dip_dly_ecc(memp_width-1 downto 0); + end if; + + wr_addr_var := (wr_addr_var + 1) mod addr_limit; + + if(wr_addr_var = 0) then + awr_flag_var := NOT awr_flag_var; + end if; + + if(wr_addr_var = addr_limit - 1) then + wr_flag_var := NOT wr_flag_var; + end if; + + end if; -- if((wren_var = '1') and (FULL_zd = '0') .... + + if((wren_var = '1') and (full_zd = '1')) then + WRERR_zd <= '1'; + else + WRERR_zd <= '0'; + end if; + + ALMOSTFULL_var := almostfull_int(3); + + if((((rdcount_var + addr_limit) <= (wr_addr_var + ae_full)) and (rdcount_flag_var = awr_flag_var)) or ((rdcount_var <= (wr_addr_var + ae_full)) and (rdcount_flag_var /= awr_flag_var))) then + almostfull_int(3) := '1'; + almostfull_int(2) := '1'; + almostfull_int(1) := '1'; + almostfull_int(0) := '1'; + elsif(almostfull_int(2) = '0') then + if (wr_addr_var <= wr_addr_var + ae_full or rdcount_flag_var = awr_flag_var) then + + almostfull_int(3) := almostfull_int(0); + almostfull_int(0) := '0'; + + end if; + end if; + + if (wren_var = '1' or full_zd = '1') then + full_zd <= full_int(1); + end if; + + if(((rdcount_var = wr_addr_var) or (rdcount_var - 1 = wr_addr_var or rdcount_var + addr_limit - 1 = wr_addr_var)) and ALMOSTFULL_var = '1') then + full_int(1) := '1'; + full_int(0) := '1'; + else + full_int(1) := full_int(0); + full_int(0) := '0'; + end if; + + update_from_write_prcs <= NOT update_from_write_prcs; + ALMOSTFULL_zd <= ALMOSTFULL_var; + + end if; -- if (sync) + + WRCOUNT_zd <= CONV_STD_LOGIC_VECTOR( wr_addr_var, MAX_WRCOUNT); + + wr_addr <= wr_addr_var; + wr_flag <= wr_flag_var; + awr_flag <= awr_flag_var; + + end if; -- if(rising(WRCLK_dly)) + + end if; -- if(GSR_dly = '1')) + + + if(update_from_read_prcs_sync'event) then + rdcount_var := SLV_TO_INT(RDCOUNT_zd); + rdcount_flag_var := rdcount_flag; + if((((rdcount_var + addr_limit) > (wr_addr_var + ae_full)) and (rdcount_flag_var = wr_flag_var)) or ((rdcount_var > (wr_addr_var + ae_full)) and (rdcount_flag_var /= wr_flag_var))) then + if (wr_addr_var <= wr_addr_var + ae_full or rdcount_flag_var = wr_flag_var) then + ALMOSTFULL_zd <= '0'; + end if; + end if; + end if; + + if(update_from_read_prcs'event) then + rdcount_var := SLV_TO_INT(RDCOUNT_zd); + rdcount_flag_var := rdcount_flag; + + if((((rdcount_var + addr_limit) > (wr_addr_var + ae_full)) and (rdcount_flag_var = awr_flag_var)) or ((rdcount_var > (wr_addr_var + ae_full)) and (rdcount_flag_var /= awr_flag_var))) then + + if(((rden_var = '1') and (EMPTY_zd = '0')) or ((((rd_addr_var + 1) mod addr_limit) = rdcount_var) and (almostfull_int(1) = '1'))) then + almostfull_int(2) := almostfull_int(1); + almostfull_int(1) := '0'; + end if; + else + almostfull_int(2) := '1'; + almostfull_int(1) := '1'; + end if; + end if; + + end process prcs_write; + + + outmux: process (DO_zd, DOP_zd, DO_OUTREG_zd, DOP_OUTREG_zd) + begin -- process outmux_clka + + if (sync = '1') then + + case DO_REG is + when 0 => + DO_OUT_MUX_zd <= DO_zd; + DOP_OUT_MUX_zd <= DOP_zd; + when 1 => + DO_OUT_MUX_zd <= DO_OUTREG_zd; + DOP_OUT_MUX_zd <= DOP_OUTREG_zd; + when others => assert false + report "Attribute Syntax Error: The allowed integer values for DO_REG are 0 or 1." + severity Failure; + end case; + + else + DO_OUT_MUX_zd <= DO_zd; + DOP_OUT_MUX_zd <= DOP_zd; + end if; + + end process outmux; + + + -- matching HW behavior to pull up and X the unused output bits + prcs_x_1_output: process (WRCOUNT_zd, RDCOUNT_zd, DO_OUT_MUX_zd, DOP_OUT_MUX_zd, RST_dly, GSR_dly, rst_rdclk_flag, rst_wrclk_flag) + begin -- process prcs_x_1_output + + if((GSR_dly = '1') or (RST_dly = '1')) then + RDCOUNT_OUT_zd <= (others => '0'); + WRCOUNT_OUT_zd <= (others => '0'); + elsif ((rst_rdclk_flag = '1') or (rst_wrclk_flag = '1'))then + RDCOUNT_OUT_zd <= (others => 'X'); + WRCOUNT_OUT_zd <= (others => 'X'); + else + + if (FIFO_SIZE = 18) then + + case DATA_WIDTH is + when 4 => + WRCOUNT_OUT_zd(12 downto 0) <= '1' & WRCOUNT_zd(11 downto 0); + RDCOUNT_OUT_zd(12 downto 0) <= '1' & RDCOUNT_zd(11 downto 0); + DO_OUT_zd(3 downto 0) <= DO_OUT_MUX_zd(3 downto 0); + when 9 => + WRCOUNT_OUT_zd(12 downto 0) <= "11" & WRCOUNT_zd(10 downto 0); + RDCOUNT_OUT_zd(12 downto 0) <= "11" & RDCOUNT_zd(10 downto 0); + DO_OUT_zd(7 downto 0) <= DO_OUT_MUX_zd(7 downto 0); + DOP_OUT_zd(0 downto 0) <= DOP_OUT_MUX_zd(0 downto 0); + when 18 => + WRCOUNT_OUT_zd(12 downto 0) <= "111" & WRCOUNT_zd(9 downto 0); + RDCOUNT_OUT_zd(12 downto 0) <= "111" & RDCOUNT_zd(9 downto 0); + DO_OUT_zd(15 downto 0) <= DO_OUT_MUX_zd(15 downto 0); + DOP_OUT_zd(1 downto 0) <= DOP_OUT_MUX_zd(1 downto 0); + when 36 => + WRCOUNT_OUT_zd(12 downto 0) <= "1111" & WRCOUNT_zd(8 downto 0); + RDCOUNT_OUT_zd(12 downto 0) <= "1111" & RDCOUNT_zd(8 downto 0); + DO_OUT_zd(31 downto 0) <= DO_OUT_MUX_zd(31 downto 0); + DOP_OUT_zd(3 downto 0) <= DOP_OUT_MUX_zd(3 downto 0); + when others => + WRCOUNT_OUT_zd <= WRCOUNT_zd; + RDCOUNT_OUT_zd <= RDCOUNT_zd; + DO_OUT_zd <= DO_OUT_MUX_zd; + end case; + + else + + case DATA_WIDTH is + when 4 => + WRCOUNT_OUT_zd(12 downto 0) <= WRCOUNT_zd(12 downto 0); + RDCOUNT_OUT_zd(12 downto 0) <= RDCOUNT_zd(12 downto 0); + DO_OUT_zd(3 downto 0) <= DO_OUT_MUX_zd(3 downto 0); + when 9 => + WRCOUNT_OUT_zd(12 downto 0) <= '1' & WRCOUNT_zd(11 downto 0); + RDCOUNT_OUT_zd(12 downto 0) <= '1' & RDCOUNT_zd(11 downto 0); + DO_OUT_zd(7 downto 0) <= DO_OUT_MUX_zd(7 downto 0); + DOP_OUT_zd(0 downto 0) <= DOP_OUT_MUX_zd(0 downto 0); + when 18 => + WRCOUNT_OUT_zd(12 downto 0) <= "11" & WRCOUNT_zd(10 downto 0); + RDCOUNT_OUT_zd(12 downto 0) <= "11" & RDCOUNT_zd(10 downto 0); + DO_OUT_zd(15 downto 0) <= DO_OUT_MUX_zd(15 downto 0); + DOP_OUT_zd(1 downto 0) <= DOP_OUT_MUX_zd(1 downto 0); + when 36 => + WRCOUNT_OUT_zd(12 downto 0) <= "111" & WRCOUNT_zd(9 downto 0); + RDCOUNT_OUT_zd(12 downto 0) <= "111" & RDCOUNT_zd(9 downto 0); + DO_OUT_zd(31 downto 0) <= DO_OUT_MUX_zd(31 downto 0); + DOP_OUT_zd(3 downto 0) <= DOP_OUT_MUX_zd(3 downto 0); + when 72 => + WRCOUNT_OUT_zd(12 downto 0) <= "1111" & WRCOUNT_zd(8 downto 0); + RDCOUNT_OUT_zd(12 downto 0) <= "1111" & RDCOUNT_zd(8 downto 0); + DO_OUT_zd(63 downto 0) <= DO_OUT_MUX_zd(63 downto 0); + DOP_OUT_zd(7 downto 0) <= DOP_OUT_MUX_zd(7 downto 0); + when others => + WRCOUNT_OUT_zd <= WRCOUNT_zd; + RDCOUNT_OUT_zd <= RDCOUNT_zd; + DO_OUT_zd <= DO_OUT_MUX_zd; + end case; + + end if; + + end if; + + end process prcs_x_1_output; + + + end generate; + +------------------------------------------------------------------------------- +-- FAST mode +------------------------------------------------------------------------------- + + fast_mode : if (SIM_MODE = "FAST") generate + + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_initialize:process + variable first_time : boolean := true; + variable addr_limit_var : integer := 0; + variable fwft_var : std_ulogic := 'X'; + variable rd_offset_stdlogic : std_logic_vector (ALMOST_EMPTY_OFFSET'length-1 downto 0); + variable rd_offset_int : integer := 0; + variable wr_offset_stdlogic : std_logic_vector (ALMOST_FULL_OFFSET'length-1 downto 0); + variable wr_offset_int : integer := 0; + variable Message : LINE; + variable ae_empty_var : integer := 0; + variable ae_full_var : integer := 0; + + begin + if (first_time) then + + if (SIM_MODE /= "FAST" and SIM_MODE /= "SAFE") then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " SIM_MODE ", + EntityName => "AFIFO36_INTERNAL", + GenericValue => SIM_MODE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " FAST or SAFE ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + + case EN_SYN is + when TRUE => sync <= '1'; + when FALSE => sync <= '0'; + when others => + end case; + + + case DATA_WIDTH is + when 4 => if (FIFO_SIZE = 36) then + addr_limit_var := 8192; + else + addr_limit_var := 4096; + end if; + when 9 => if (FIFO_SIZE = 36) then + addr_limit_var := 4096; + else + addr_limit_var := 2048; + end if; + when 18 => if (FIFO_SIZE = 36) then + addr_limit_var := 2048; + else + addr_limit_var := 1024; + end if; + when 36 => if (FIFO_SIZE = 36) then + addr_limit_var := 1024; + else + addr_limit_var := 512; + end if; + when 72 => + addr_limit_var := 512; + + when others => + end case; + + rd_offset_stdlogic := To_StdLogicVector(ALMOST_EMPTY_OFFSET); + rd_offset_int := SLV_TO_INT(rd_offset_stdlogic); + + wr_offset_stdlogic := To_StdLogicVector(ALMOST_FULL_OFFSET); + wr_offset_int := SLV_TO_INT(wr_offset_stdlogic); + + case FIRST_WORD_FALL_THROUGH is + when TRUE => + fwft_var := '1'; + ae_empty_var := rd_offset_int - 2; + ae_full_var := wr_offset_int; + when FALSE => + fwft_var := '0'; + if (EN_SYN = FALSE) then + ae_empty_var := rd_offset_int - 1; + ae_full_var := wr_offset_int; + else + ae_empty_var := rd_offset_int; + ae_full_var := wr_offset_int; + end if; + when others => + end case; + + + addr_limit_fast <= addr_limit_var; + fwft <= fwft_var; + ae_full_fast <= ae_full_var; + ae_empty_fast <= ae_empty_var; + first_time := false; + end if; + wait; + end process prcs_initialize; + + +--#################################################################### +--##### Read ##### +--#################################################################### + prcs_read:process(RDCLK_dly, RST_dly, GSR_dly, update_from_write_prcs, update_from_write_prcs_sync, rst_rdclk_flag, rst_wrclk_flag) + variable first_time : boolean := true; + variable rd_addr_var : integer := 0; + variable wr_addr_var : integer := 0; + variable rdcount_var : integer := 0; + + variable rd_flag_var : std_ulogic := '0'; + variable wr_flag_var : std_ulogic := '0'; + variable awr_flag_var : std_ulogic := '0'; + + variable rdcount_flag_var : std_ulogic := '0'; + + variable do_in : std_logic_vector(MSB_MAX_DO downto 0) := (others => '0'); + variable dop_in : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + + variable almostempty_int : std_ulogic_vector(3 downto 0) := (others => '1'); + variable empty_int : std_ulogic_vector(3 downto 0) := (others => '1'); + variable empty_ram : std_ulogic_vector(3 downto 0) := (others => '1'); + + variable addr_limit_var : integer := 0; + + variable wr1_addr_var : integer := 0; + variable wr1_flag_var : std_ulogic := '0'; + variable rd_prefetch_var : integer := 0; + variable rd_prefetch_flag_var : std_ulogic := '0'; + +-- CR 195129 fix from verilog (may not be necessary for vhdl) +-- Added ren_var/wren_var to remember the old val of RDEN_dly/WREN_dly + + variable rden_var : std_ulogic := '0'; + variable wren_var : std_ulogic := '0'; + + variable do_buf : std_logic_vector(MSB_MAX_DO downto 0) := (others => '0'); + variable dop_buf : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + variable dopr_ecc : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + variable tmp_syndrome_int : integer; + variable syndrome : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + variable ecc_bit_position : std_logic_vector(71 downto 0) := (others => '0'); + variable di_dly_ecc_corrected : std_logic_vector(MSB_MAX_DO downto 0) := (others => '0'); + variable dip_dly_ecc_corrected : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + variable sbiterr_out : std_ulogic := '0'; + variable dbiterr_out : std_ulogic := '0'; + variable sbiterr_out_out_var : std_ulogic := '0'; + variable dbiterr_out_out_var : std_ulogic := '0'; + variable DO_OUTREG_var: std_logic_vector(MSB_MAX_DO downto 0) := (others => '0'); + variable DOP_OUTREG_var : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + + begin + if((GSR_dly = '1') or (RST_dly = '1')) then + rd_addr_fast <= 0; + rd_flag <= '0'; + + rd_addr_var := 0; + wr_addr_var := 0; + wr1_addr_var := 0; + rd_prefetch_var := 0; + + rdcount_var := 0; + + rd_flag_var := '0'; + wr_flag_var := '0'; + awr_flag_var := '0'; + wr1_flag_var := '0'; + rd_prefetch_flag_var := '0'; + + rdcount_flag_var := '0'; + + empty_int := (others => '1'); + almostempty_int := (others => '1'); + empty_ram := (others => '1'); + + sbiterr_zd <= '0'; + dbiterr_zd <= '0'; + + ALMOSTEMPTY_zd <= '1'; + EMPTY_zd <= '1'; + RDERR_zd <= '0'; + RDCOUNT_zd <= (others => '0'); + + if(GSR_dly = '1') then + DO_zd((mem_width -1) downto 0) <= (others => '0'); + DO_OUTREG_zd((mem_width -1) downto 0) <= (others => '0'); + if (DATA_WIDTH /= 4) then + DOP_zd((memp_width -1) downto 0) <= (others => '0'); + DOP_OUTREG_zd((memp_width -1) downto 0) <= (others => '0'); + end if; + end if; + + elsif ((rst_rdclk_flag = '1') or (rst_wrclk_flag = '1'))then + + rd_addr_fast <= 0; + rd_flag <= '0'; + + rd_addr_var := 0; + wr_addr_var := 0; + wr1_addr_var := 0; + rd_prefetch_var := 0; + + rdcount_var := 0; + + rd_flag_var := '0'; + wr_flag_var := '0'; + awr_flag_var := '0'; + wr1_flag_var := '0'; + rd_prefetch_flag_var := '0'; + + rdcount_flag_var := '0'; + + empty_int := (others => '1'); + almostempty_int := (others => '1'); + empty_ram := (others => '1'); + + ALMOSTEMPTY_zd <= 'X'; + EMPTY_zd <= 'X'; + RDERR_zd <= 'X'; + RDCOUNT_zd <= (others => 'X'); + + sbiterr_zd <= 'X'; + dbiterr_zd <= 'X'; + + DO_zd((mem_width -1) downto 0) <= (others => 'X'); + DO_OUTREG_zd((mem_width -1) downto 0) <= (others => 'X'); + + if (DATA_WIDTH /= 4) then + DOP_zd((memp_width -1) downto 0) <= (others => 'X'); + DOP_OUTREG_zd((memp_width -1) downto 0) <= (others => 'X'); + end if; + + elsif ((GSR_dly = '0') and (RST_dly = '0'))then + + rden_var := RDEN_dly; + wren_var := WREN_dly; + + if(rising_edge(RDCLK_dly)) then + + rd_flag_var := rd_flag; + wr_flag_var := wr_flag; + awr_flag_var := awr_flag; + + rd_addr_var := rd_addr_fast; + wr_addr_var := wr_addr_fast; + + rdcount_var := SLV_TO_INT(RDCOUNT_zd); + rdcount_flag_var := rdcount_flag; + + + if (sync = '1') then + + DO_OUTREG_var := DO_zd; + DOP_OUTREG_var := DOP_zd; + + if (RDEN_dly = '1') then + + if (EMPTY_zd = '0') then + + DO_zd(mem_width-1 downto 0) <= mem(rdcount_var); + DOP_zd(memp_width-1 downto 0) <= memp(rdcount_var); + + rdcount_var := (rdcount_var + 1) mod addr_limit_fast; + + if (rdcount_var = 0) then + rdcount_flag_var := not rdcount_flag_var; + end if; + + end if; + end if; + + + if (RDEN_dly = '1' and EMPTY_zd = '1') then + RDERR_zd <= '1'; + else + RDERR_zd <= '0'; + end if; + + + if (WREN_dly = '1') then + EMPTY_zd <= '0'; + elsif (rdcount_var = wr_addr_var and rdcount_flag_var = wr_flag_var) then + EMPTY_zd <= '1'; + end if; + + if((((rdcount_var + ae_empty_fast) >= wr_addr_var) and (rdcount_flag_var = wr_flag_var)) or (((rdcount_var + ae_empty_fast) >= (wr_addr_var + addr_limit_fast)) and (rdcount_flag_var /= wr_flag_var))) then + ALMOSTEMPTY_zd <= '1'; + end if; + + update_from_read_prcs_sync <= not update_from_read_prcs_sync; + + elsif (sync = '0') then + + dbiterr_out_out_var := dbiterr_out; -- reg out in async mode + sbiterr_out_out_var := sbiterr_out; + + if(fwft = '0') then + addr_limit_var := addr_limit_fast; + if((rden_var = '1') and (rd_addr_var /= rdcount_var)) then + DO_zd <= do_in; + if (DATA_WIDTH /= 4) then + DOP_zd <= dop_in; + end if; + rd_addr_var := (rd_addr_var + 1) mod addr_limit_fast; + if(rd_addr_var = 0) then + rd_flag_var := NOT rd_flag_var; + end if; + end if; + if (((rd_addr_var = rdcount_var) and (empty_ram(3) = '0')) or + ((rden_var = '1') and (empty_ram(1) = '0'))) then + do_in(mem_width-1 downto 0) := mem(rdcount_var); + dop_in(memp_width-1 downto 0) := memp(rdcount_var); + + rdcount_var := (rdcount_var + 1) mod addr_limit_fast; + + if(rdcount_var = 0) then + rdcount_flag_var := NOT rdcount_flag_var; + end if; + + end if; + + elsif(fwft = '1') then + if((rden_var = '1') and (rd_addr_var /= rd_prefetch_var)) then + rd_prefetch_var := (rd_prefetch_var + 1) mod addr_limit_fast; + if(rd_prefetch_var = 0) then + rd_prefetch_flag_var := NOT rd_prefetch_flag_var; + end if; + end if; + if((rd_prefetch_var = rd_addr_var) and (rd_addr_var /= rdcount_var)) then + DO_zd <= do_in; + if (DATA_WIDTH /= 4) then + DOP_zd <= dop_in; + end if; + rd_addr_var := (rd_addr_var + 1) mod addr_limit_fast; + if(rd_addr_var = 0) then + rd_flag_var := NOT rd_flag_var; + end if; + end if; + if(((rd_addr_var = rdcount_var) and (empty_ram(3) = '0')) or + ((rden_var = '1') and (empty_ram(1) = '0')) or + ((rden_var = '0') and (empty_ram(1) = '0') and (rd_addr_var = rdcount_var))) then + do_in(mem_width-1 downto 0) := mem(rdcount_var); + dop_in(memp_width-1 downto 0) := memp(rdcount_var); + + rdcount_var := (rdcount_var + 1) mod addr_limit_fast; + + if(rdcount_var = 0) then + rdcount_flag_var := NOT rdcount_flag_var; + end if; + + end if; + + end if; --- end if(fwft = '1') + + + ALMOSTEMPTY_zd <= almostempty_int(3); + + if((((rdcount_var + ae_empty_fast) >= wr_addr_var) and (rdcount_flag_var = awr_flag_var)) or (((rdcount_var + ae_empty_fast) >= (wr_addr_var + addr_limit_fast)) and (rdcount_flag_var /= awr_flag_var))) then + almostempty_int(3) := '1'; + almostempty_int(2) := '1'; + almostempty_int(1) := '1'; + almostempty_int(0) := '1'; + elsif(almostempty_int(2) = '0') then + -- added to match verilog + if (rdcount_var <= rdcount_var + ae_empty_fast or rdcount_flag_var /= awr_flag_var) then + almostempty_int(3) := almostempty_int(0); + almostempty_int(0) := '0'; + end if; + end if; + + if(fwft = '0') then + if((rdcount_var = rd_addr_var) and (rdcount_flag_var = rd_flag_var)) then + EMPTY_zd <= '1'; + else + EMPTY_zd <= '0'; + end if; + elsif(fwft = '1') then + if((rd_prefetch_var = rd_addr_var) and (rd_prefetch_flag_var = rd_flag_var)) then + EMPTY_zd <= '1'; + else + EMPTY_zd <= '0'; + end if; + end if; + + if((rdcount_var = wr_addr_var) and (rdcount_flag_var = awr_flag_var)) then + empty_ram(2) := '1'; + empty_ram(1) := '1'; + empty_ram(0) := '1'; + else + empty_ram(2) := empty_ram(1); + empty_ram(1) := empty_ram(0); + empty_ram(0) := '0'; + end if; + + if((rdcount_var = wr1_addr_var) and (rdcount_flag_var = wr1_flag_var)) then + empty_ram(3) := '1'; + else + empty_ram(3) := '0'; + end if; + + wr1_addr_var := wr_addr_fast; + wr1_flag_var := awr_flag; + + if((rden_var = '1') and (EMPTY_zd = '1')) then + RDERR_zd <= '1'; + else + RDERR_zd <= '0'; + end if; -- end ((rden_var = '1') and (empty_int /= '1')) + + update_from_read_prcs <= NOT update_from_read_prcs; + + end if; + + end if; -- end (rising_edge(RDCLK_dly)) + + end if; -- end (GSR_dly = 1) + + + + if(update_from_write_prcs_sync'event) then + wr_addr_var := wr_addr_fast; + wr_flag_var := wr_flag; + if((((rdcount_var + ae_empty_fast) < wr_addr_var) and (rdcount_flag_var = wr_flag_var)) or + (((rdcount_var + ae_empty_fast) < (wr_addr_var + addr_limit_fast)) and (rdcount_flag_var /= wr_flag_var))) then + if(rdcount_var <= rdcount_var + ae_empty_fast or rdcount_flag_var /= wr_flag_var) then + almostempty_zd <= '0'; + end if; + end if; + end if; + + + if(update_from_write_prcs'event) then + wr_addr_var := wr_addr_fast; + wr_flag_var := wr_flag; + awr_flag_var := awr_flag; + + if((((rdcount_var + ae_empty_fast) < wr_addr_var) and (rdcount_flag_var = awr_flag_var)) or + (((rdcount_var + ae_empty_fast) < ( wr_addr_var + addr_limit_fast)) and (rdcount_flag_var /= awr_flag_var))) then + if(wren_var = '1') then + almostempty_int(2) := almostempty_int(1); + almostempty_int(1) := '0'; + end if; + else + almostempty_int(2) := '1'; + almostempty_int(1) := '1'; + end if; + end if; + + + if (not (rst_rdclk_flag or rst_wrclk_flag) = '1') then + RDCOUNT_zd <= CONV_STD_LOGIC_VECTOR(rdcount_var, MAX_RDCOUNT); + dbiterr_zd <= dbiterr_out_out_var; -- reg out in async mode + sbiterr_zd <= sbiterr_out_out_var; + end if; + + rd_addr_fast <= rd_addr_var; + rd_flag <= rd_flag_var; + rdcount_flag <= rdcount_flag_var; + DO_OUTREG_zd <= DO_OUTREG_var; + DOP_OUTREG_zd <= DOP_OUTREG_var; + + end process prcs_read; + +--#################################################################### +--##### Write ##### +--#################################################################### + prcs_write:process(WRCLK_dly, RST_dly, GSR_dly, update_from_read_prcs, update_from_read_prcs_sync, rst_rdclk_flag, rst_wrclk_flag) + variable first_time : boolean := true; + variable wr_addr_var : integer := 0; + variable rd_addr_var : integer := 0; + variable rdcount_var : integer := 0; + variable wrcount_var : integer := 0; + + variable rd_flag_var : std_ulogic := '0'; + variable wr_flag_var : std_ulogic := '0'; + variable awr_flag_var : std_ulogic := '0'; + + variable rdcount_flag_var : std_ulogic := '0'; + + variable almostfull_int : std_ulogic_vector(3 downto 0) := (others => '0'); + variable full_int : std_ulogic_vector(3 downto 0) := (others => '0'); + +-- CR 195129 fix from verilog (may not be necessary for vhdl) +-- Added ren_var/wren_var to remember the old val of RDEN_dly/WREN_dly + + variable rden_var : std_ulogic := '0'; + variable wren_var : std_ulogic := '0'; + variable dip_ecc : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + variable dip_dly_ecc : std_logic_vector(MSB_MAX_DOP downto 0) := (others => '0'); + variable ALMOSTFULL_var : std_ulogic := '0'; + + begin + if ((GSR_dly = '1') or (RST_dly = '1') or (rst_rdclk_flag = '1') or (rst_wrclk_flag = '1'))then + wr_addr_var := 0; + wr_addr_fast <= 0; + wr_flag <= '0'; + awr_flag <= '0'; + + wr_addr_var := 0; + rd_addr_var := 0; + rdcount_var := 0; + wrcount_var := 0; + ALMOSTFULL_var := '0'; + + rd_flag_var := '0'; + wr_flag_var := '0'; + awr_flag_var := '0'; + + rdcount_flag_var := '0'; + + full_int := (others => '0'); + almostfull_int := (others => '0'); + + if ((GSR_dly = '1') or (RST_dly = '1'))then + ALMOSTFULL_zd <= '0'; + FULL_zd <= '0'; + WRERR_zd <= '0'; + WRCOUNT_zd <= (others => '0'); + else + ALMOSTFULL_zd <= 'X'; + FULL_zd <= 'X'; + WRERR_zd <= 'X'; + WRCOUNT_zd <= (others => 'X'); + eccparity_zd <= (others => 'X'); + end if; + + elsif((GSR_dly = '0') and (RST_dly = '0'))then + rden_var := RDEN_dly; + wren_var := WREN_dly; + + if(rising_edge(WRCLK_dly)) then + + rd_flag_var := rd_flag; + wr_flag_var := wr_flag; + awr_flag_var := awr_flag; + + rd_addr_var := rd_addr_fast; + wr_addr_var := wr_addr_fast; + + rdcount_var := SLV_TO_INT(RDCOUNT_zd); + rdcount_flag_var := rdcount_flag; + + if (sync = '1') then + if(wren_dly = '1') then + if (full_zd= '0') then + + mem(wr_addr_var) <= DI_dly(mem_width-1 downto 0); + memp(wr_addr_var) <= dip_dly_ecc(memp_width-1 downto 0); + + wr_addr_var := (wr_addr_var + 1) mod addr_limit_fast; + + if(wr_addr_var = 0) then + wr_flag_var := NOT wr_flag_var; + end if; + + end if; + end if; + + + if ((WREN_dly = '1') and (FULL_zd = '1')) then + WRERR_zd <= '1'; + else + WRERR_zd <= '0'; + end if; + + + if (rden_dly = '1') then + full_zd <= '0'; + elsif (rdcount_var = wr_addr_var and rdcount_flag_var /= wr_flag_var) then + full_zd <= '1'; + end if; + + update_from_write_prcs_sync <= NOT update_from_write_prcs_sync; + + if((((rdcount_var + addr_limit_fast) <= (wr_addr_var + ae_full_fast)) and (rdcount_flag_var = wr_flag_var)) or ((rdcount_var <= (wr_addr_var + ae_full_fast)) and (rdcount_flag_var /= wr_flag_var))) then + almostfull_zd <= '1'; + end if; + + + elsif (sync = '0') then + + if((wren_var = '1') and (full_zd = '0'))then + + mem(wr_addr_var) <= DI_dly(mem_width-1 downto 0); + if (DATA_WIDTH >= 9) then + memp(wr_addr_var) <= dip_dly_ecc(memp_width-1 downto 0); + end if; + + wr_addr_var := (wr_addr_var + 1) mod addr_limit_fast; + + if(wr_addr_var = 0) then + awr_flag_var := NOT awr_flag_var; + end if; + + if(wr_addr_var = addr_limit_fast - 1) then + wr_flag_var := NOT wr_flag_var; + end if; + + end if; -- if((wren_var = '1') and (FULL_zd = '0') .... + + if((wren_var = '1') and (full_zd = '1')) then + WRERR_zd <= '1'; + else + WRERR_zd <= '0'; + end if; + + ALMOSTFULL_var := almostfull_int(3); + + if((((rdcount_var + addr_limit_fast) <= (wr_addr_var + ae_full_fast)) and (rdcount_flag_var = awr_flag_var)) or ((rdcount_var <= (wr_addr_var + ae_full_fast)) and (rdcount_flag_var /= awr_flag_var))) then + almostfull_int(3) := '1'; + almostfull_int(2) := '1'; + almostfull_int(1) := '1'; + almostfull_int(0) := '1'; + elsif(almostfull_int(2) = '0') then + if (wr_addr_var <= wr_addr_var + ae_full_fast or rdcount_flag_var = awr_flag_var) then + + almostfull_int(3) := almostfull_int(0); + almostfull_int(0) := '0'; + + end if; + end if; + + if (wren_var = '1' or full_zd = '1') then + full_zd <= full_int(1); + end if; + + if(((rdcount_var = wr_addr_var) or (rdcount_var - 1 = wr_addr_var or rdcount_var + addr_limit_fast - 1 = wr_addr_var)) and ALMOSTFULL_var = '1') then + full_int(1) := '1'; + full_int(0) := '1'; + else + full_int(1) := full_int(0); + full_int(0) := '0'; + end if; + + update_from_write_prcs <= NOT update_from_write_prcs; + ALMOSTFULL_zd <= ALMOSTFULL_var; + + end if; -- if (sync) + + WRCOUNT_zd <= CONV_STD_LOGIC_VECTOR( wr_addr_var, MAX_WRCOUNT); + + wr_addr_fast <= wr_addr_var; + wr_flag <= wr_flag_var; + awr_flag <= awr_flag_var; + + end if; -- if(rising(WRCLK_dly)) + + end if; -- if(GSR_dly = '1')) + + + if(update_from_read_prcs_sync'event) then + rdcount_var := SLV_TO_INT(RDCOUNT_zd); + rdcount_flag_var := rdcount_flag; + if((((rdcount_var + addr_limit_fast) > (wr_addr_var + ae_full_fast)) and (rdcount_flag_var = wr_flag_var)) or ((rdcount_var > (wr_addr_var + ae_full_fast)) and (rdcount_flag_var /= wr_flag_var))) then + if (wr_addr_var <= wr_addr_var + ae_full_fast or rdcount_flag_var = wr_flag_var) then + ALMOSTFULL_zd <= '0'; + end if; + end if; + end if; + + if(update_from_read_prcs'event) then + rdcount_var := SLV_TO_INT(RDCOUNT_zd); + rdcount_flag_var := rdcount_flag; + + if((((rdcount_var + addr_limit_fast) > (wr_addr_var + ae_full_fast)) and (rdcount_flag_var = awr_flag_var)) or ((rdcount_var > (wr_addr_var + ae_full_fast)) and (rdcount_flag_var /= awr_flag_var))) then + + if(((rden_var = '1') and (EMPTY_zd = '0')) or ((((rd_addr_var + 1) mod addr_limit_fast) = rdcount_var) and (almostfull_int(1) = '1'))) then + almostfull_int(2) := almostfull_int(1); + almostfull_int(1) := '0'; + end if; + else + almostfull_int(2) := '1'; + almostfull_int(1) := '1'; + end if; + end if; + + end process prcs_write; + + + outmux: process (DO_zd, DOP_zd, DO_OUTREG_zd, DOP_OUTREG_zd) + begin -- process outmux_clka + + if (sync = '1') then + + case DO_REG is + when 0 => + DO_OUT_zd <= DO_zd; + DOP_OUT_zd <= DOP_zd; + when 1 => + DO_OUT_zd <= DO_OUTREG_zd; + DOP_OUT_zd <= DOP_OUTREG_zd; + when others => + end case; + + else + DO_OUT_zd <= DO_zd; + DOP_OUT_zd <= DOP_zd; + end if; + + end process outmux; + + + -- matching HW behavior to pull up and X the unused output bits + prcs_x_1_output: process (WRCOUNT_zd, RDCOUNT_zd, RST_dly, GSR_dly) + begin -- process prcs_x_1_output + + if ((GSR_dly = '1') or (RST_dly = '1')) then + RDCOUNT_OUT_zd <= (others => '0'); + WRCOUNT_OUT_zd <= (others => '0'); + else + RDCOUNT_OUT_zd <= RDCOUNT_zd; + WRCOUNT_OUT_zd <= WRCOUNT_zd; + end if; + + end process prcs_x_1_output; + + + end generate; + + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(ALMOSTEMPTY_zd, ALMOSTFULL_zd, DO_OUT_zd, DOP_OUT_zd, + EMPTY_zd, FULL_zd, RDCOUNT_OUT_zd, RDERR_zd, + WRCOUNT_OUT_zd, WRERR_zd, sbiterr_zd, dbiterr_zd) + begin + ALMOSTEMPTY <= ALMOSTEMPTY_zd; + ALMOSTFULL <= ALMOSTFULL_zd; + DO <= DO_OUT_zd; + DOP <= DOP_OUT_zd; + EMPTY <= EMPTY_zd; + FULL <= FULL_zd; + RDCOUNT <= RDCOUNT_OUT_zd; + RDERR <= RDERR_zd; + WRCOUNT <= WRCOUNT_OUT_zd; + WRERR <= WRERR_zd; + ECCPARITY <= ECCPARITY_zd; + SBITERR <= sbiterr_zd; + DBITERR <= dbiterr_zd; + end process prcs_output; +--#################################################################### + + +end AFIFO36_INTERNAL_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/aramb36_internal.vhd,v 1.28.12.1 2008/02/21 00:26:06 wloo Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2005 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : This is not an user primitive. +-- / / Xilinx Functional Simulation Library Component 32K-Bit Data and 4K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : ARAMB36_INTERNAL.vhd +-- \ \ / \ Timestamp : Tues October 18 16:43:59 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 10/18/05 - Initial version. +-- 12/14/05 - Clean up generic checking. +-- 05/30/06 - Added collision feature support. +-- 07/10/06 - Added 2 dimensional memory array support for Virtex 4 block ram. +-- 08/21/06 - Fixed the collision error message when the address is unknown (CR 233726/344429). +-- 10/09/06 - Fixed collision case when READ_WIDTH_A/B = 16 (CR 424558). +-- 11/01/06 - Fixed collision (CR 427720). +-- 11/02/06 - Fixed sbiterr and dbiterr of ECC (CR 427509). +-- 12/06/06 - Added DRC to prevent usage of EN_ECC_SCRUB = TRUE (CR 427875). +-- 12/07/06 - Updated functional warning for Virtex 4 byte write feature (CR 428207). +-- 01/02/07 - Fixed parity bit for Virtex 4 byte write feature (CR 431583). +-- 01/04/07 - Added support of memory file to initialize memory and parity (CR 431584). +-- 02/21/07 - Added attribute check for SIM_COLLISION_CHECK (CR 433445). +-- 03/01/07 - Fixed attribute check for SIM_COLLISION_CHECK (CR 435304). +-- 03/14/07 - Removed attribute INITP_FILE (CR 436003). +-- 03/28/07 - Disabled V4 byte write warning when READ_WIDTH_* = 0 (CR 429400). +-- 04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812). +-- 06/14/07 - Implemented high performace version of the model. +-- 06/20/07 - Fixed collision address when cascaded block rams (CR 440250). +-- 08/15/07 - Updated SSR as not supported feature in output register mode for ramb16 (CR 445314). +-- 08/17/07 - Supported new memory file format (SLIB_M2.3). +-- 09/18/07 - Fixed DRC check for V4 ramb16 (CR 448739). +-- 10/01/07 - Added conditional statement for SSRA in cascade mode (CR 449340). +-- 02/20/08 - Updated collison address when cascaded block rams (CR 451722). +-- End Revision + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_SIGNED.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_TEXTIO.all; + +library STD; +use STD.TEXTIO.all; + +library unisim; +use unisim.vcomponents.all; +use unisim.vpkg.all; + +entity ARAMB36_INTERNAL is + + generic ( + + BRAM_MODE : string := "TRUE_DUAL_PORT"; + BRAM_SIZE : integer := 36; + DOA_REG : integer := 0; + DOB_REG : integer := 0; + EN_ECC_READ : boolean := FALSE; + EN_ECC_SCRUB : boolean := FALSE; + EN_ECC_WRITE : boolean := FALSE; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000000000000"; + INIT_B : bit_vector := X"000000000000000000"; + INIT_FILE : string := "NONE"; + RAM_EXTENSION_A : string := "NONE"; + RAM_EXTENSION_B : string := "NONE"; + READ_WIDTH_A : integer := 0; + READ_WIDTH_B : integer := 0; + SETUP_ALL : time := 1000 ps; + SETUP_READ_FIRST : time := 3000 ps; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL_A : bit_vector := X"000000000000000000"; + SRVAL_B : bit_vector := X"000000000000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST"; + WRITE_WIDTH_A : integer := 0; + WRITE_WIDTH_B : integer := 0 + + ); + + port ( + + CASCADEOUTLATA : out std_ulogic; + CASCADEOUTLATB : out std_ulogic; + CASCADEOUTREGA : out std_ulogic; + CASCADEOUTREGB : out std_ulogic; + DBITERR : out std_ulogic; + DOA : out std_logic_vector(63 downto 0); + DOB : out std_logic_vector(63 downto 0); + DOPA : out std_logic_vector(7 downto 0); + DOPB : out std_logic_vector(7 downto 0); + ECCPARITY : out std_logic_vector(7 downto 0); + SBITERR : out std_ulogic; + + ADDRA : in std_logic_vector(15 downto 0); + ADDRB : in std_logic_vector(15 downto 0); + CASCADEINLATA : in std_ulogic; + CASCADEINLATB : in std_ulogic; + CASCADEINREGA : in std_ulogic; + CASCADEINREGB : in std_ulogic; + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(63 downto 0); + DIB : in std_logic_vector(63 downto 0); + DIPA : in std_logic_vector(7 downto 0); + DIPB : in std_logic_vector(7 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + REGCLKA : in std_ulogic; + REGCLKB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(7 downto 0); + WEB : in std_logic_vector(7 downto 0) + + ); +end ARAMB36_INTERNAL; + +-- Architecture body -- + +architecture ARAMB36_INTERNAL_V of ARAMB36_INTERNAL is + + signal ADDRA_dly : std_logic_vector(15 downto 0) := (others => 'X'); + signal CLKA_dly : std_ulogic := 'X'; + signal DIA_dly : std_logic_vector(63 downto 0) := (others => 'X'); + signal DIPA_dly : std_logic_vector(7 downto 0) := (others => 'X'); + signal ENA_dly : std_ulogic := 'X'; + signal REGCEA_dly : std_ulogic := 'X'; + signal SSRA_dly : std_ulogic := 'X'; + signal WEA_dly : std_logic_vector(7 downto 0) := (others => 'X'); + signal CASCADEINLATA_dly : std_ulogic := 'X'; + signal CASCADEINREGA_dly : std_ulogic := 'X'; + signal ADDRB_dly : std_logic_vector(15 downto 0) := (others => 'X'); + signal CLKB_dly : std_ulogic := 'X'; + signal DIB_dly : std_logic_vector(63 downto 0) := (others => 'X'); + signal DIPB_dly : std_logic_vector(7 downto 0) := (others => 'X'); + signal ENB_dly : std_ulogic := 'X'; + signal REGCEB_dly : std_ulogic := 'X'; + signal REGCLKA_dly : std_ulogic := 'X'; + signal REGCLKB_dly : std_ulogic := 'X'; + signal SSRB_dly : std_ulogic := 'X'; + signal WEB_dly : std_logic_vector(7 downto 0) := (others => 'X'); + signal CASCADEINLATB_dly : std_ulogic := 'X'; + signal CASCADEINREGB_dly : std_ulogic := 'X'; + + signal sbiterr_out : std_logic := '0'; + signal dbiterr_out : std_logic := '0'; + signal sbiterr_outreg : std_logic := '0'; + signal dbiterr_outreg : std_logic := '0'; + signal sbiterr_out_out : std_logic := '0'; + signal dbiterr_out_out : std_logic := '0'; + signal doa_out : std_logic_vector(63 downto 0) := (others => '0'); + signal dopa_out : std_logic_vector(7 downto 0) := (others => '0'); + signal doa_outreg : std_logic_vector(63 downto 0) := (others => '0'); + signal dopa_outreg : std_logic_vector(7 downto 0) := (others => '0'); + signal dob_outreg : std_logic_vector(63 downto 0) := (others => '0'); + signal dopb_outreg : std_logic_vector(7 downto 0) := (others => '0'); + signal dob_out : std_logic_vector(63 downto 0) := (others => '0'); + signal dopb_out : std_logic_vector(7 downto 0) := (others => '0'); + + signal doa_out_mux : std_logic_vector(63 downto 0) := (others => '0'); + signal dopa_out_mux : std_logic_vector(7 downto 0) := (others => '0'); + signal doa_outreg_mux : std_logic_vector(63 downto 0) := (others => '0'); + signal dopa_outreg_mux : std_logic_vector(7 downto 0) := (others => '0'); + signal dob_outreg_mux : std_logic_vector(63 downto 0) := (others => '0'); + signal dopb_outreg_mux : std_logic_vector(7 downto 0) := (others => '0'); + signal dob_out_mux : std_logic_vector(63 downto 0) := (others => '0'); + signal dopb_out_mux : std_logic_vector(7 downto 0) := (others => '0'); + + signal doa_out_out : std_logic_vector(63 downto 0) := (others => '0'); + signal dopa_out_out : std_logic_vector(7 downto 0) := (others => '0'); + signal dob_out_out : std_logic_vector(63 downto 0) := (others => '0'); + signal dopb_out_out : std_logic_vector(7 downto 0) := (others => '0'); + signal addra_dly_15_reg : std_logic := '0'; + signal addrb_dly_15_reg : std_logic := '0'; + signal addra_dly_15_reg1 : std_logic := '0'; + signal addrb_dly_15_reg1 : std_logic := '0'; + signal cascade_a : std_logic_vector(1 downto 0) := (others => '0'); + signal cascade_b : std_logic_vector(1 downto 0) := (others => '0'); + signal GSR_dly : std_ulogic := 'X'; + signal eccparity_out : std_logic_vector(7 downto 0) := (others => 'X'); + signal SRVAL_A_STD : std_logic_vector(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A); + signal SRVAL_B_STD : std_logic_vector(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B); + signal INIT_A_STD : std_logic_vector(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A); + signal INIT_B_STD : std_logic_vector(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B); + signal di_x : std_logic_vector(63 downto 0) := (others => 'X'); + + function GetWidestWidth ( + wr_width_a : in integer; + rd_width_a : in integer; + wr_width_b : in integer; + rd_width_b : in integer + ) return integer is + variable func_widest_width : integer; + begin + if ((wr_width_a >= wr_width_b) and (wr_width_a >= rd_width_a) and (wr_width_a >= rd_width_b)) then + func_widest_width := wr_width_a; + elsif ((wr_width_b >= wr_width_a) and (wr_width_b >= rd_width_a) and (wr_width_b >= rd_width_b)) then + func_widest_width := wr_width_b; + elsif ((rd_width_a >= wr_width_a) and (rd_width_a >= wr_width_b) and (rd_width_a >= rd_width_b)) then + func_widest_width := rd_width_a; + elsif ((rd_width_b >= wr_width_a) and (rd_width_b >= wr_width_b) and (rd_width_b >= rd_width_a)) then + func_widest_width := rd_width_b; + end if; + return func_widest_width; + end; + + + function GetWidth ( + rdwr_width : in integer + ) return integer is + variable func_width : integer; + begin + case rdwr_width is + when 1 => func_width := 1; + when 2 => func_width := 2; + when 4 => func_width := 4; + when 9 => func_width := 8; + when 18 => func_width := 16; + when 36 => func_width := 32; + when 72 => func_width := 64; + when others => func_width := 1; + end case; + return func_width; + end; + + + function GetWidthINITF ( + rdwr_width_initf : in integer + ) return integer is + variable func_width_initf : integer; + begin + case rdwr_width_initf is + when 1 => func_width_initf := 4; + when 2 => func_width_initf := 4; + when 4 => func_width_initf := 4; + when 9 => func_width_initf := 12; + when 18 => func_width_initf := 20; + when 36 => func_width_initf := 36; + when 72 => func_width_initf := 72; + when others => func_width_initf := 1; + end case; + return func_width_initf; + end; + + + function GetWidthp ( + rdwr_widthp : in integer + ) return integer is + variable func_widthp : integer; + begin + case rdwr_widthp is + when 9 => func_widthp := 1; + when 18 => func_widthp := 2; + when 36 => func_widthp := 4; + when 72 => func_widthp := 8; +-- when others => func_widthp := 1; + when others => func_widthp := 0; + end case; + return func_widthp; + end; + + + function GetWidthpINITF ( + rdwr_widthp_initf : in integer + ) return integer is + variable func_widthp_initf : integer; + begin + case rdwr_widthp_initf is + when 9 => func_widthp_initf := 4; + when 18 => func_widthp_initf := 4; + when 36 => func_widthp_initf := 4; + when 72 => func_widthp_initf := 8; + when others => func_widthp_initf := 1; + end case; + return func_widthp_initf; + end; + + + function GetWidthpTmpWidthp ( + rdwr_tmp_widthp : in integer + ) return integer is + variable func_widthp_tmp : integer; + begin + case rdwr_tmp_widthp is + when 1 | 2 | 4 => func_widthp_tmp := 0; + when 9 => func_widthp_tmp := 1; + when 18 => func_widthp_tmp := 2; + when 36 => func_widthp_tmp := 4; + when 72 => func_widthp_tmp := 8; + when others => func_widthp_tmp := 8; + end case; + return func_widthp_tmp; + end; + + + function GetMemoryDepth ( + rdwr_width : in integer; + func_bram_size : in integer + ) return integer is + variable func_mem_depth : integer; + begin + case rdwr_width is + when 1 => if (func_bram_size = 18) then + func_mem_depth := 16384; + else + func_mem_depth := 32768; + end if; + when 2 => if (func_bram_size = 18) then + func_mem_depth := 8192; + else + func_mem_depth := 16384; + end if; + when 4 => if (func_bram_size = 18) then + func_mem_depth := 4096; + else + func_mem_depth := 8192; + end if; + when 9 => if (func_bram_size = 18) then + func_mem_depth := 2048; + else + func_mem_depth := 4096; + end if; + when 18 => if (func_bram_size = 18) then + func_mem_depth := 1024; + else + func_mem_depth := 2048; + end if; + when 36 => if (func_bram_size = 18) then + func_mem_depth := 512; + else + func_mem_depth := 1024; + end if; + when 72 => if (func_bram_size = 18) then + func_mem_depth := 0; + else + func_mem_depth := 512; + end if; + when others => func_mem_depth := 32768; + end case; + return func_mem_depth; + end; + + + function GetMemoryDepthP ( + rdwr_width : in integer; + func_bram_size : in integer + ) return integer is + variable func_memp_depth : integer; + begin + case rdwr_width is + when 9 => if (func_bram_size = 18) then + func_memp_depth := 2048; + else + func_memp_depth := 4096; + end if; + when 18 => if (func_bram_size = 18) then + func_memp_depth := 1024; + else + func_memp_depth := 2048; + end if; + when 36 => if (func_bram_size = 18) then + func_memp_depth := 512; + else + func_memp_depth := 1024; + end if; + when 72 => if (func_bram_size = 18) then + func_memp_depth := 0; + else + func_memp_depth := 512; + end if; + when others => func_memp_depth := 4096; + end case; + return func_memp_depth; + end; + + + function GetAddrBitLSB ( + rdwr_width : in integer + ) return integer is + variable func_lsb : integer; + begin + case rdwr_width is + when 1 => func_lsb := 0; + when 2 => func_lsb := 1; + when 4 => func_lsb := 2; + when 9 => func_lsb := 3; + when 18 => func_lsb := 4; + when 36 => func_lsb := 5; + when 72 => func_lsb := 6; + when others => func_lsb := 10; + end case; + return func_lsb; + end; + + + function GetAddrBit124 ( + rdwr_width : in integer; + w_width : in integer + ) return integer is + variable func_widest_width : integer; + begin + case rdwr_width is + when 1 => case w_width is + when 2 => func_widest_width := 0; + when 4 => func_widest_width := 1; + when 9 => func_widest_width := 2; + when 18 => func_widest_width := 3; + when 36 => func_widest_width := 4; + when 72 => func_widest_width := 5; + when others => func_widest_width := 10; + end case; + when 2 => case w_width is + when 4 => func_widest_width := 1; + when 9 => func_widest_width := 2; + when 18 => func_widest_width := 3; + when 36 => func_widest_width := 4; + when 72 => func_widest_width := 5; + when others => func_widest_width := 10; + end case; + when 4 => case w_width is + when 9 => func_widest_width := 2; + when 18 => func_widest_width := 3; + when 36 => func_widest_width := 4; + when 72 => func_widest_width := 5; + when others => func_widest_width := 10; + end case; + when others => func_widest_width := 10; + end case; + return func_widest_width; + end; + + + function GetAddrBit8 ( + rdwr_width : in integer; + w_width : in integer + ) return integer is + variable func_widest_width : integer; + begin + case rdwr_width is + when 9 => case w_width is + when 18 => func_widest_width := 3; + when 36 => func_widest_width := 4; + when 72 => func_widest_width := 5; + when others => func_widest_width := 10; + end case; + when others => func_widest_width := 10; + end case; + return func_widest_width; + end; + + + function GetAddrBit16 ( + rdwr_width : in integer; + w_width : in integer + ) return integer is + variable func_widest_width : integer; + begin + case rdwr_width is + when 18 => case w_width is + when 36 => func_widest_width := 4; + when 72 => func_widest_width := 5; + when others => func_widest_width := 10; + end case; + when others => func_widest_width := 10; + end case; + return func_widest_width; + end; + + + function GetAddrBit32 ( + rdwr_width : in integer; + w_width : in integer + ) return integer is + variable func_widest_width : integer; + begin + case rdwr_width is + when 36 => case w_width is + when 72 => func_widest_width := 5; + when others => func_widest_width := 10; + end case; + when others => func_widest_width := 10; + end case; + return func_widest_width; + end; + + --------------------------------------------------------------------------- + -- Function SLV_X_TO_HEX returns a hex string version of the std_logic_vector + -- argument. + --------------------------------------------------------------------------- + function SLV_X_TO_HEX ( + SLV : in std_logic_vector; + string_length : in integer + ) return string is + + variable i : integer := 1; + variable j : integer := 1; + variable STR : string(string_length downto 1); + variable nibble : std_logic_vector(3 downto 0) := "0000"; + variable full_nibble_count : integer := 0; + variable remaining_bits : integer := 0; + + begin + full_nibble_count := SLV'length/4; + remaining_bits := SLV'length mod 4; + for i in 1 to full_nibble_count loop + nibble := SLV(((4*i) - 1) downto ((4*i) - 4)); + if (((nibble(0) xor nibble(1) xor nibble (2) xor nibble(3)) /= '1') and + (nibble(0) xor nibble(1) xor nibble (2) xor nibble(3)) /= '0') then + STR(j) := 'x'; + elsif (nibble = "0000") then + STR(j) := '0'; + elsif (nibble = "0001") then + STR(j) := '1'; + elsif (nibble = "0010") then + STR(j) := '2'; + elsif (nibble = "0011") then + STR(j) := '3'; + elsif (nibble = "0100") then + STR(j) := '4'; + elsif (nibble = "0101") then + STR(j) := '5'; + elsif (nibble = "0110") then + STR(j) := '6'; + elsif (nibble = "0111") then + STR(j) := '7'; + elsif (nibble = "1000") then + STR(j) := '8'; + elsif (nibble = "1001") then + STR(j) := '9'; + elsif (nibble = "1010") then + STR(j) := 'a'; + elsif (nibble = "1011") then + STR(j) := 'b'; + elsif (nibble = "1100") then + STR(j) := 'c'; + elsif (nibble = "1101") then + STR(j) := 'd'; + elsif (nibble = "1110") then + STR(j) := 'e'; + elsif (nibble = "1111") then + STR(j) := 'f'; + end if; + j := j + 1; + end loop; + + if (remaining_bits /= 0) then + nibble := "0000"; + nibble((remaining_bits -1) downto 0) := SLV((SLV'length -1) downto (SLV'length - remaining_bits)); + if (((nibble(0) xor nibble(1) xor nibble (2) xor nibble(3)) /= '1') and + (nibble(0) xor nibble(1) xor nibble (2) xor nibble(3)) /= '0') then + STR(j) := 'x'; + elsif (nibble = "0000") then + STR(j) := '0'; + elsif (nibble = "0001") then + STR(j) := '1'; + elsif (nibble = "0010") then + STR(j) := '2'; + elsif (nibble = "0011") then + STR(j) := '3'; + elsif (nibble = "0100") then + STR(j) := '4'; + elsif (nibble = "0101") then + STR(j) := '5'; + elsif (nibble = "0110") then + STR(j) := '6'; + elsif (nibble = "0111") then + STR(j) := '7'; + elsif (nibble = "1000") then + STR(j) := '8'; + elsif (nibble = "1001") then + STR(j) := '9'; + elsif (nibble = "1010") then + STR(j) := 'a'; + elsif (nibble = "1011") then + STR(j) := 'b'; + elsif (nibble = "1100") then + STR(j) := 'c'; + elsif (nibble = "1101") then + STR(j) := 'd'; + elsif (nibble = "1110") then + STR(j) := 'e'; + elsif (nibble = "1111") then + STR(j) := 'f'; + end if; + end if; + return STR; + end SLV_X_TO_HEX; + + constant widest_width : integer := GetWidestWidth(WRITE_WIDTH_A, READ_WIDTH_A, WRITE_WIDTH_B, READ_WIDTH_B); + constant mem_depth : integer := GetMemoryDepth(widest_width, BRAM_SIZE); + constant memp_depth : integer := GetMemoryDepthP(widest_width, BRAM_SIZE); + constant width : integer := GetWidth(widest_width); + constant widthp : integer := GetWidthp(widest_width); + constant width_initf : integer := GetWidthINITF(widest_width); + constant widthp_initf : integer := GetWidthpINITF(widest_width); + constant wa_width : integer := GetWidth(WRITE_WIDTH_A); + constant wb_width : integer := GetWidth(WRITE_WIDTH_B); + constant ra_width : integer := GetWidth(READ_WIDTH_A); + constant rb_width : integer := GetWidth(READ_WIDTH_B); + constant wa_widthp : integer := GetWidthp(WRITE_WIDTH_A); + constant wb_widthp : integer := GetWidthp(WRITE_WIDTH_B); + constant ra_widthp : integer := GetWidthp(READ_WIDTH_A); + constant rb_widthp : integer := GetWidthp(READ_WIDTH_B); + constant r_addra_lbit_124 : integer := GetAddrBitLSB(READ_WIDTH_A); + constant r_addrb_lbit_124 : integer := GetAddrBitLSB(READ_WIDTH_B); + constant w_addra_lbit_124 : integer := GetAddrBitLSB(WRITE_WIDTH_A); + constant w_addrb_lbit_124 : integer := GetAddrBitLSB(WRITE_WIDTH_B); + constant w_addra_bit_124 : integer := GetAddrBit124(WRITE_WIDTH_A, widest_width); + constant r_addra_bit_124 : integer := GetAddrBit124(READ_WIDTH_A, widest_width); + constant w_addrb_bit_124 : integer := GetAddrBit124(WRITE_WIDTH_B, widest_width); + constant r_addrb_bit_124 : integer := GetAddrBit124(READ_WIDTH_B, widest_width); + constant w_addra_bit_8 : integer := GetAddrBit8(WRITE_WIDTH_A, widest_width); + constant r_addra_bit_8 : integer := GetAddrBit8(READ_WIDTH_A, widest_width); + constant w_addrb_bit_8 : integer := GetAddrBit8(WRITE_WIDTH_B, widest_width); + constant r_addrb_bit_8 : integer := GetAddrBit8(READ_WIDTH_B, widest_width); + constant w_addra_bit_16 : integer := GetAddrBit16(WRITE_WIDTH_A, widest_width); + constant r_addra_bit_16 : integer := GetAddrBit16(READ_WIDTH_A, widest_width); + constant w_addrb_bit_16 : integer := GetAddrBit16(WRITE_WIDTH_B, widest_width); + constant r_addrb_bit_16 : integer := GetAddrBit16(READ_WIDTH_B, widest_width); + constant w_addra_bit_32 : integer := GetAddrBit32(WRITE_WIDTH_A, widest_width); + constant r_addra_bit_32 : integer := GetAddrBit32(READ_WIDTH_A, widest_width); + constant w_addrb_bit_32 : integer := GetAddrBit32(WRITE_WIDTH_B, widest_width); + constant r_addrb_bit_32 : integer := GetAddrBit32(READ_WIDTH_B, widest_width); + constant col_addr_lsb : integer := GetAddrBitLSB(widest_width); + constant tmp_widthp : integer := GetWidthpTmpWidthp(widest_width); + + type Two_D_array_type_tmp_mem is array ((mem_depth - 1) downto 0) of std_logic_vector((widest_width - 1) downto 0); + + type Two_D_array_type is array ((mem_depth - 1) downto 0) of std_logic_vector((width - 1) downto 0); + type Two_D_parity_array_type is array ((memp_depth - 1) downto 0) of std_logic_vector((widthp -1) downto 0); + + type Two_D_array_type_initf is array ((mem_depth - 1) downto 0) of std_logic_vector((width_initf - 1) downto 0); + type Two_D_parity_array_type_initf is array ((memp_depth - 1) downto 0) of std_logic_vector((widthp_initf -1) downto 0); + + + function slv_to_two_D_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_array_type is + variable two_D_array : two_D_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1) loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_array(i) := intermediate; + end loop; + return two_D_array; + end; + + + function slv_to_two_D_parity_array( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector + ) + return two_D_parity_array_type is + variable two_D_parity_array : two_D_parity_array_type; + variable intermediate : std_logic_vector((slv_width - 1) downto 0); + begin + for i in 0 to (slv_length - 1)loop + intermediate := SLV(((i*slv_width) + (slv_width - 1)) downto (i* slv_width)); + two_D_parity_array(i) := intermediate; + end loop; + return two_D_parity_array; + end; + + + function two_D_mem_initf( + slv_width : integer + ) + return two_D_array_type_tmp_mem is + + variable input_initf_tmp : Two_D_array_type_initf; + variable input_initf : Two_D_array_type_tmp_mem; + file int_infile : text; + variable data_line, data_line_tmp, out_data_line : line; + variable i : integer := 0; + variable good_data : boolean := false; + variable ignore_line : boolean := false; + variable char_tmp : character; + variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0'); + variable open_status : file_open_status; + + begin + + if (INIT_FILE /= "NONE") then + + file_open(open_status, int_infile, INIT_FILE, read_mode); + + while not endfile(int_infile) loop + + readline(int_infile, data_line); + + while (data_line /= null and data_line'length > 0) loop + + if (data_line(data_line'low to data_line'low + 1) = "//") then + deallocate(data_line); + + elsif (data_line(data_line'low to data_line'low + 1) = "/*") then + deallocate(data_line); + ignore_line := true; + + elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then + deallocate(data_line); + ignore_line := false; + + + elsif (ignore_line = false and data_line(data_line'low) = '@') then + read(data_line, char_tmp); + hread(data_line, init_addr_slv, good_data); + + i := SLV_TO_INT(init_addr_slv); + + elsif (ignore_line = false) then + + hread(data_line, input_initf_tmp(i), good_data); + input_initf(i)(slv_width - 1 downto 0) := input_initf_tmp(i)(slv_width - 1 downto 0); + + if (good_data = true) then + i := i + 1; + end if; + else + deallocate(data_line); + + end if; + + end loop; + + end loop; + + end if; + + return input_initf; + + end; + + + function two_D_mem_init( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector; + temp_mem : two_D_array_type_tmp_mem + ) + return two_D_array_type is + variable two_D_array_mem_init : two_D_array_type; + begin + if (INIT_FILE = "NONE") then + two_D_array_mem_init := slv_to_two_D_array(slv_length, slv_width, SLV); + else + + for i in 0 to (slv_length - 1) loop + two_D_array_mem_init(i)(slv_width-1 downto 0) := temp_mem(i)(slv_width-1 downto 0); + end loop; + + end if; + return two_D_array_mem_init; + end; + + + function two_D_mem_initp( + slv_length : integer; + slv_width : integer; + SLV : in std_logic_vector; + temp_mem : two_D_array_type_tmp_mem; + mem_width : integer + ) + return two_D_parity_array_type is + variable two_D_array_mem_initp : two_D_parity_array_type; + begin + if (INIT_FILE = "NONE") then + two_D_array_mem_initp := slv_to_two_D_parity_array(slv_length, slv_width, SLV); + else + + if (slv_width > 0) then + + for i in 0 to (slv_length - 1) loop + two_D_array_mem_initp(i)(slv_width-1 downto 0) := temp_mem(i)(mem_width + slv_width - 1 downto mem_width); + end loop; + + end if; + end if; + return two_D_array_mem_initp; + end; + + + + function fn_dip_ecc ( + encode : in std_logic; + di_in : in std_logic_vector (63 downto 0); + dip_in : in std_logic_vector (7 downto 0) + ) return std_logic_vector is + variable fn_dip_ecc : std_logic_vector (7 downto 0); + begin + + fn_dip_ecc(0) := di_in(0) xor di_in(1) xor di_in(3) xor di_in(4) xor di_in(6) xor di_in(8) + xor di_in(10) xor di_in(11) xor di_in(13) xor di_in(15) xor di_in(17) xor di_in(19) + xor di_in(21) xor di_in(23) xor di_in(25) xor di_in(26) xor di_in(28) + xor di_in(30) xor di_in(32) xor di_in(34) xor di_in(36) xor di_in(38) + xor di_in(40) xor di_in(42) xor di_in(44) xor di_in(46) xor di_in(48) + xor di_in(50) xor di_in(52) xor di_in(54) xor di_in(56) xor di_in(57) xor di_in(59) + xor di_in(61) xor di_in(63); + + fn_dip_ecc(1) := di_in(0) xor di_in(2) xor di_in(3) xor di_in(5) xor di_in(6) xor di_in(9) + xor di_in(10) xor di_in(12) xor di_in(13) xor di_in(16) xor di_in(17) + xor di_in(20) xor di_in(21) xor di_in(24) xor di_in(25) xor di_in(27) xor di_in(28) + xor di_in(31) xor di_in(32) xor di_in(35) xor di_in(36) xor di_in(39) + xor di_in(40) xor di_in(43) xor di_in(44) xor di_in(47) xor di_in(48) + xor di_in(51) xor di_in(52) xor di_in(55) xor di_in(56) xor di_in(58) xor di_in(59) + xor di_in(62) xor di_in(63); + + fn_dip_ecc(2) := di_in(1) xor di_in(2) xor di_in(3) xor di_in(7) xor di_in(8) xor di_in(9) + xor di_in(10) xor di_in(14) xor di_in(15) xor di_in(16) xor di_in(17) + xor di_in(22) xor di_in(23) xor di_in(24) xor di_in(25) xor di_in(29) + xor di_in(30) xor di_in(31) xor di_in(32) xor di_in(37) xor di_in(38) xor di_in(39) + xor di_in(40) xor di_in(45) xor di_in(46) xor di_in(47) xor di_in(48) + xor di_in(53) xor di_in(54) xor di_in(55) xor di_in(56) + xor di_in(60) xor di_in(61) xor di_in(62) xor di_in(63); + + fn_dip_ecc(3) := di_in(4) xor di_in(5) xor di_in(6) xor di_in(7) xor di_in(8) xor di_in(9) + xor di_in(10) xor di_in(18) xor di_in(19) + xor di_in(20) xor di_in(21) xor di_in(22) xor di_in(23) xor di_in(24) xor di_in(25) + xor di_in(33) xor di_in(34) xor di_in(35) xor di_in(36) xor di_in(37) xor di_in(38) xor di_in(39) + xor di_in(40) xor di_in(49) + xor di_in(50) xor di_in(51) xor di_in(52) xor di_in(53) xor di_in(54) xor di_in(55) xor di_in(56); + + fn_dip_ecc(4) := di_in(11) xor di_in(12) xor di_in(13) xor di_in(14) xor di_in(15) xor di_in(16) xor di_in(17) + xor di_in(18) xor di_in(19) xor di_in(20) xor di_in(21) xor di_in(22) xor di_in(23) xor di_in(24) + xor di_in(25) xor di_in(41) xor di_in(42) xor di_in(43) xor di_in(44) xor di_in(45) xor di_in(46) + xor di_in(47) xor di_in(48) xor di_in(49) xor di_in(50) xor di_in(51) xor di_in(52) xor di_in(53) + xor di_in(54) xor di_in(55) xor di_in(56); + + + fn_dip_ecc(5) := di_in(26) xor di_in(27) xor di_in(28) xor di_in(29) + xor di_in(30) xor di_in(31) xor di_in(32) xor di_in(33) xor di_in(34) xor di_in(35) xor di_in(36) + xor di_in(37) xor di_in(38) xor di_in(39) xor di_in(40) xor di_in(41) xor di_in(42) xor di_in(43) + xor di_in(44) xor di_in(45) xor di_in(46) xor di_in(47) xor di_in(48) xor di_in(49) xor di_in(50) + xor di_in(51) xor di_in(52) xor di_in(53) xor di_in(54) xor di_in(55) xor di_in(56); + + fn_dip_ecc(6) := di_in(57) xor di_in(58) xor di_in(59) + xor di_in(60) xor di_in(61) xor di_in(62) xor di_in(63); + + if (encode = '1') then + + fn_dip_ecc(7) := fn_dip_ecc(0) xor fn_dip_ecc(1) xor fn_dip_ecc(2) xor fn_dip_ecc(3) xor fn_dip_ecc(4) xor fn_dip_ecc(5) + xor fn_dip_ecc(6) xor di_in(0) xor di_in(1) xor di_in(2) xor di_in(3) xor di_in(4) xor di_in(5) + xor di_in(6) xor di_in(7) xor di_in(8) xor di_in(9) xor di_in(10) xor di_in(11) xor di_in(12) + xor di_in(13) xor di_in(14) xor di_in(15) xor di_in(16) xor di_in(17) xor di_in(18) xor di_in(19) + xor di_in(20) xor di_in(21) xor di_in(22) xor di_in(23) xor di_in(24) xor di_in(25) xor di_in(26) + xor di_in(27) xor di_in(28) xor di_in(29) xor di_in(30) xor di_in(31) xor di_in(32) xor di_in(33) + xor di_in(34) xor di_in(35) xor di_in(36) xor di_in(37) xor di_in(38) xor di_in(39) xor di_in(40) + xor di_in(41) xor di_in(42) xor di_in(43) xor di_in(44) xor di_in(45) xor di_in(46) xor di_in(47) + xor di_in(48) xor di_in(49) xor di_in(50) xor di_in(51) xor di_in(52) xor di_in(53) xor di_in(54) + xor di_in(55) xor di_in(56) xor di_in(57) xor di_in(58) xor di_in(59) xor di_in(60) xor di_in(61) + xor di_in(62) xor di_in(63); + + else + + fn_dip_ecc(7) := dip_in(0) xor dip_in(1) xor dip_in(2) xor dip_in(3) xor dip_in(4) xor dip_in(5) + xor dip_in(6) xor di_in(0) xor di_in(1) xor di_in(2) xor di_in(3) xor di_in(4) xor di_in(5) + xor di_in(6) xor di_in(7) xor di_in(8) xor di_in(9) xor di_in(10) xor di_in(11) xor di_in(12) + xor di_in(13) xor di_in(14) xor di_in(15) xor di_in(16) xor di_in(17) xor di_in(18) xor di_in(19) + xor di_in(20) xor di_in(21) xor di_in(22) xor di_in(23) xor di_in(24) xor di_in(25) xor di_in(26) + xor di_in(27) xor di_in(28) xor di_in(29) xor di_in(30) xor di_in(31) xor di_in(32) xor di_in(33) + xor di_in(34) xor di_in(35) xor di_in(36) xor di_in(37) xor di_in(38) xor di_in(39) xor di_in(40) + xor di_in(41) xor di_in(42) xor di_in(43) xor di_in(44) xor di_in(45) xor di_in(46) xor di_in(47) + xor di_in(48) xor di_in(49) xor di_in(50) xor di_in(51) xor di_in(52) xor di_in(53) xor di_in(54) + xor di_in(55) xor di_in(56) xor di_in(57) xor di_in(58) xor di_in(59) xor di_in(60) xor di_in(61) + xor di_in(62) xor di_in(63); + end if; + + return fn_dip_ecc; + + end fn_dip_ecc; + + + procedure prcd_chk_for_col_msg ( + constant wea_tmp : in std_ulogic; + constant web_tmp : in std_ulogic; + constant addra_tmp : in std_logic_vector (15 downto 0); + constant addrb_tmp : in std_logic_vector (15 downto 0); + variable col_wr_wr_msg : inout std_ulogic; + variable col_wra_rdb_msg : inout std_ulogic; + variable col_wrb_rda_msg : inout std_ulogic + ) is + + variable string_length_1 : integer; + variable string_length_2 : integer; + variable message : LINE; + constant MsgSeverity : severity_level := Error; + + begin + + if ((SIM_COLLISION_CHECK = "ALL" or SIM_COLLISION_CHECK = "WARNING_ONLY") + and (not(((WRITE_MODE_B = "READ_FIRST" and web_tmp = '1' and wea_tmp = '0') and (not(rising_edge(clka_dly) and (not(rising_edge(clkb_dly)))))) + or ((WRITE_MODE_A = "READ_FIRST" and wea_tmp = '1' and web_tmp = '0') and (not(rising_edge(clkb_dly) and (not(rising_edge(clka_dly))))))))) then + + if ((addra_tmp'length mod 4) = 0) then + string_length_1 := addra_tmp'length/4; + elsif ((addra_tmp'length mod 4) > 0) then + string_length_1 := addra_tmp'length/4 + 1; + end if; + if ((addrb_tmp'length mod 4) = 0) then + string_length_2 := addrb_tmp'length/4; + elsif ((addrb_tmp'length mod 4) > 0) then + string_length_2 := addrb_tmp'length/4 + 1; + end if; + + if (wea_tmp = '1' and web_tmp = '1' and col_wr_wr_msg = '1') then + Write ( message, STRING'(" Memory Collision Error on ARAMB36_INTERNAL :")); + Write ( message, STRING'(ARAMB36_INTERNAL'path_name)); + Write ( message, STRING'(" at simulation time ")); + Write ( message, now); + Write ( message, STRING'(".")); + Write ( message, LF ); + Write ( message, STRING'(" A write was requested to the same address simultaneously at both Port A and Port B of the RAM.")); + Write ( message, STRING'(" The contents written to the RAM at address location ")); + Write ( message, SLV_X_TO_HEX(addra_tmp, string_length_1)); + Write ( message, STRING'(" (hex) ")); + Write ( message, STRING'("of Port A and address location ")); + Write ( message, SLV_X_TO_HEX(addrb_tmp, string_length_2)); + Write ( message, STRING'(" (hex) ")); + Write ( message, STRING'("of Port B are unknown. ")); + ASSERT FALSE REPORT message.ALL SEVERITY MsgSeverity; + DEALLOCATE (message); + col_wr_wr_msg := '0'; + + elsif (wea_tmp = '1' and web_tmp = '0' and col_wra_rdb_msg = '1') then + Write ( message, STRING'(" Memory Collision Error on ARAMB36_INTERNAL :")); + Write ( message, STRING'(ARAMB36_INTERNAL'path_name)); + Write ( message, STRING'(" at simulation time ")); + Write ( message, now); + Write ( message, STRING'(".")); + Write ( message, LF ); + Write ( message, STRING'(" A read was performed on address ")); + Write ( message, SLV_X_TO_HEX(addrb_tmp, string_length_2)); + Write ( message, STRING'(" (hex) ")); + Write ( message, STRING'("of port B while a write was requested to the same address on Port A. ")); + Write ( message, STRING'(" The write will be successful however the read value on port B is unknown until the next CLKB cycle. ")); + ASSERT FALSE REPORT message.ALL SEVERITY MsgSeverity; + DEALLOCATE (message); + col_wra_rdb_msg := '0'; + + elsif (wea_tmp = '0' and web_tmp = '1' and col_wrb_rda_msg = '1') then + Write ( message, STRING'(" Memory Collision Error on ARAMB36_INTERNAL :")); + Write ( message, STRING'(ARAMB36_INTERNAL'path_name)); + Write ( message, STRING'(" at simulation time ")); + Write ( message, now); + Write ( message, STRING'(".")); + Write ( message, LF ); + Write ( message, STRING'(" A read was performed on address ")); + Write ( message, SLV_X_TO_HEX(addra_tmp, string_length_1)); + Write ( message, STRING'(" (hex) ")); + Write ( message, STRING'("of port A while a write was requested to the same address on Port B. ")); + Write ( message, STRING'(" The write will be successful however the read value on port A is unknown until the next CLKA cycle. ")); + ASSERT FALSE REPORT message.ALL SEVERITY MsgSeverity; + DEALLOCATE (message); + col_wrb_rda_msg := '0'; + + end if; + + end if; + + end prcd_chk_for_col_msg; + + + procedure prcd_write_ram ( + constant we : in std_logic; + constant di : in std_logic_vector; + constant dip : in std_logic; + variable mem_proc : inout std_logic_vector; + variable memp_proc : inout std_logic + ) is + + alias di_tmp : std_logic_vector (di'length-1 downto 0) is di; + alias mem_proc_tmp : std_logic_vector (mem_proc'length-1 downto 0) is mem_proc; + + begin + if (we = '1') then + mem_proc_tmp := di_tmp; + + if (width >= 8) then + memp_proc := dip; + end if; + end if; + end prcd_write_ram; + + + procedure prcd_write_ram_col ( + constant we_o : in std_logic; + constant we : in std_logic; + constant di : in std_logic_vector; + constant dip : in std_logic; + variable mem_proc : inout std_logic_vector; + variable memp_proc : inout std_logic + ) is + + alias di_tmp : std_logic_vector (di'length-1 downto 0) is di; + alias mem_proc_tmp : std_logic_vector (mem_proc'length-1 downto 0) is mem_proc; + variable i : integer := 0; + + begin + if (we = '1') then + + for i in 0 to di'length-1 loop + if ((mem_proc_tmp(i) /= 'X') or (not(we = we_o and we = '1'))) then + mem_proc_tmp(i) := di_tmp(i); + end if; + end loop; + + if (width >= 8 and ((memp_proc /= 'X') or (not(we = we_o and we = '1')))) then + memp_proc := dip; + end if; + + end if; + end prcd_write_ram_col; + + + procedure prcd_x_buf ( + constant wr_rd_mode : in std_logic_vector (1 downto 0); + constant do_uindex : in integer; + constant do_lindex : in integer; + constant dop_index : in integer; + constant do_ltmp : in std_logic_vector (63 downto 0); + variable do_tmp : inout std_logic_vector (63 downto 0); + constant dop_ltmp : in std_logic_vector (7 downto 0); + variable dop_tmp : inout std_logic_vector (7 downto 0) + ) is + + variable i : integer; + + begin + if (wr_rd_mode = "01") then + for i in do_lindex to do_uindex loop + if (do_ltmp(i) = 'X') then + do_tmp(i) := 'X'; + end if; + end loop; + + if (dop_ltmp(dop_index) = 'X') then + dop_tmp(dop_index) := 'X'; + end if; + + else + do_tmp(do_lindex + 7 downto do_lindex) := do_ltmp(do_lindex + 7 downto do_lindex); + dop_tmp(dop_index) := dop_ltmp(dop_index); + end if; + + end prcd_x_buf; + + + procedure prcd_rd_ram_a ( + constant addra_tmp : in std_logic_vector (15 downto 0); + variable doa_tmp : inout std_logic_vector (63 downto 0); + variable dopa_tmp : inout std_logic_vector (7 downto 0); + constant mem : in Two_D_array_type; + constant memp : in Two_D_parity_array_type + ) is + variable prcd_tmp_addra_dly_depth : integer; + variable prcd_tmp_addra_dly_width : integer; + + begin + + case ra_width is + + when 1 | 2 | 4 => if (ra_width >= width) then + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_lbit_124)); + doa_tmp(ra_width-1 downto 0) := mem(prcd_tmp_addra_dly_depth); + else + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_124 + 1)); + prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_124 downto r_addra_lbit_124)); + doa_tmp(ra_width-1 downto 0) := mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * ra_width) + ra_width - 1 downto prcd_tmp_addra_dly_width * ra_width); + end if; + + when 8 => if (ra_width >= width) then + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 3)); + doa_tmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth); + dopa_tmp(0 downto 0) := memp(prcd_tmp_addra_dly_depth); + else + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_8 + 1)); + prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_8 downto 3)); + doa_tmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 8) + 7 downto prcd_tmp_addra_dly_width * 8); + dopa_tmp(0 downto 0) := memp(prcd_tmp_addra_dly_depth)(prcd_tmp_addra_dly_width downto prcd_tmp_addra_dly_width); + end if; + + when 16 => if (ra_width >= width) then + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4)); + doa_tmp(15 downto 0) := mem(prcd_tmp_addra_dly_depth); + dopa_tmp(1 downto 0) := memp(prcd_tmp_addra_dly_depth); + else + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_16 + 1)); + prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_16 downto 4)); + doa_tmp(15 downto 0) := mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 15 downto prcd_tmp_addra_dly_width * 16); + dopa_tmp(1 downto 0) := memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2) + 1 downto prcd_tmp_addra_dly_width * 2); + end if; + + when 32 => if (ra_width >= width) then + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 5)); + doa_tmp(31 downto 0) := mem(prcd_tmp_addra_dly_depth); + dopa_tmp(3 downto 0) := memp(prcd_tmp_addra_dly_depth); + end if; + + when 64 => if (ra_width >= width) then + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 6)); + doa_tmp(63 downto 0) := mem(prcd_tmp_addra_dly_depth); + dopa_tmp(7 downto 0) := memp(prcd_tmp_addra_dly_depth); + end if; + + when others => null; + + end case; + + end prcd_rd_ram_a; + + + procedure prcd_rd_ram_b ( + constant addrb_tmp : in std_logic_vector (15 downto 0); + variable dob_tmp : inout std_logic_vector (63 downto 0); + variable dopb_tmp : inout std_logic_vector (7 downto 0); + constant mem : in Two_D_array_type; + constant memp : in Two_D_parity_array_type + ) is + variable prcd_tmp_addrb_dly_depth : integer; + variable prcd_tmp_addrb_dly_width : integer; + + begin + + case rb_width is + + when 1 | 2 | 4 => if (rb_width >= width) then + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_lbit_124)); + dob_tmp(rb_width-1 downto 0) := mem(prcd_tmp_addrb_dly_depth); + else + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_124 + 1)); + prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_124 downto r_addrb_lbit_124)); + dob_tmp(rb_width-1 downto 0) := mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * rb_width) + rb_width - 1 downto prcd_tmp_addrb_dly_width * rb_width); + end if; + + when 8 => if (rb_width >= width) then + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 3)); + dob_tmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth); + dopb_tmp(0 downto 0) := memp(prcd_tmp_addrb_dly_depth); + else + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_8 + 1)); + prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_8 downto 3)); + dob_tmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 8) + 7 downto prcd_tmp_addrb_dly_width * 8); + dopb_tmp(0 downto 0) := memp(prcd_tmp_addrb_dly_depth)(prcd_tmp_addrb_dly_width downto prcd_tmp_addrb_dly_width); + end if; + + when 16 => if (rb_width >= width) then + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4)); + dob_tmp(15 downto 0) := mem(prcd_tmp_addrb_dly_depth); + dopb_tmp(1 downto 0) := memp(prcd_tmp_addrb_dly_depth); + else + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_16 + 1)); + prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_16 downto 4)); + dob_tmp(15 downto 0) := mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 15 downto prcd_tmp_addrb_dly_width * 16); + dopb_tmp(1 downto 0) := memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2) + 1 downto prcd_tmp_addrb_dly_width * 2); + end if; + + when 32 => if (rb_width >= width) then + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 5)); + dob_tmp(31 downto 0) := mem(prcd_tmp_addrb_dly_depth); + dopb_tmp(3 downto 0) := memp(prcd_tmp_addrb_dly_depth); + end if; + + when others => null; + + end case; + + end prcd_rd_ram_b; + + + procedure prcd_col_wr_ram_a ( + constant seq : in std_logic_vector (1 downto 0); + constant web_tmp : in std_logic_vector (7 downto 0); + constant wea_tmp : in std_logic_vector (7 downto 0); + constant dia_tmp : in std_logic_vector (63 downto 0); + constant dipa_tmp : in std_logic_vector (7 downto 0); + constant addrb_tmp : in std_logic_vector (15 downto 0); + constant addra_tmp : in std_logic_vector (15 downto 0); + variable mem : inout Two_D_array_type; + variable memp : inout Two_D_parity_array_type; + variable col_wr_wr_msg : inout std_ulogic; + variable col_wra_rdb_msg : inout std_ulogic; + variable col_wrb_rda_msg : inout std_ulogic + ) is + variable prcd_tmp_addra_dly_depth : integer; + variable prcd_tmp_addra_dly_width : integer; + variable junk : std_ulogic; + + begin + + case wa_width is + + when 1 | 2 | 4 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wa_width > wb_width) or seq = "10") then + if (wa_width >= width) then + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_lbit_124)); + prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(wa_width-1 downto 0), '0', mem(prcd_tmp_addra_dly_depth), junk); + else + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_124 + 1)); + prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_124 downto w_addra_lbit_124)); + prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(wa_width-1 downto 0), '0', mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * wa_width) + wa_width - 1 downto (prcd_tmp_addra_dly_width * wa_width)), junk); + end if; + + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + end if; + + when 8 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wa_width > wb_width) or seq = "10") then + if (wa_width >= width) then + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 3)); + prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth), memp(prcd_tmp_addra_dly_depth)(0)); + else + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_8 + 1)); + prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_8 downto 3)); + prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 8) + 7 downto (prcd_tmp_addra_dly_width * 8)), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width))); + end if; + + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + end if; + + when 16 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wa_width > wb_width) or seq = "10") then + if (wa_width >= width) then + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4)); + prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0)); + else + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_16 + 1)); + prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_16 downto 4)); + prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 7 downto (prcd_tmp_addra_dly_width * 16)), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2))); + end if; + + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + if (wa_width >= width) then + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4)); + prcd_write_ram_col (web_tmp(1), wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1)); + else + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_16 + 1)); + prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_16 downto 4)); + prcd_write_ram_col (web_tmp(1), wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 15 downto (prcd_tmp_addra_dly_width * 16) + 8), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2) + 1)); + end if; + + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + end if; + + when 32 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wa_width > wb_width) or seq = "10") then + + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 5)); + prcd_write_ram_col (web_tmp(0), wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0)); + + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + prcd_write_ram_col (web_tmp(1), wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1)); + + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + prcd_write_ram_col (web_tmp(2), wea_tmp(2), dia_tmp(23 downto 16), dipa_tmp(2), mem(prcd_tmp_addra_dly_depth)(23 downto 16), memp(prcd_tmp_addra_dly_depth)(2)); + + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(2), web_tmp(2), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + prcd_write_ram_col (web_tmp(3), wea_tmp(3), dia_tmp(31 downto 24), dipa_tmp(3), mem(prcd_tmp_addra_dly_depth)(31 downto 24), memp(prcd_tmp_addra_dly_depth)(3)); + + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(3), web_tmp(3), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + end if; + when 64 => null; +-- prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 6)); +-- prcd_write_ram_col ('0', '1', dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0)); +---- if (seq = "00") +---- prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp); +-- +-- prcd_write_ram_col ('0', '1', dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1)); +---- if (seq = "00") +---- prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp); +-- +-- prcd_write_ram_col ('0', '1', dia_tmp(23 downto 16), dipa_tmp(2), mem(prcd_tmp_addra_dly_depth)(23 downto 16), memp(prcd_tmp_addra_dly_depth)(2)); +---- if (seq = "00") +---- prcd_chk_for_col_msg (wea_tmp(2), web_tmp(2), addra_tmp, addrb_tmp); +-- +-- prcd_write_ram_col ('0', '1', dia_tmp(31 downto 24), dipa_tmp(3), mem(prcd_tmp_addra_dly_depth)(31 downto 24), memp(prcd_tmp_addra_dly_depth)(3)); +---- if (seq = "00") +---- prcd_chk_for_col_msg (wea_tmp(3), web_tmp(3), addra_tmp, addrb_tmp); +-- +-- prcd_write_ram_col ('0', '1', dia_tmp(39 downto 32), dipa_tmp(4), mem(prcd_tmp_addra_dly_depth)(39 downto 32), memp(prcd_tmp_addra_dly_depth)(4)); +---- if (seq = "00") +---- prcd_chk_for_col_msg (wea_tmp(4), web_tmp(4), addra_tmp, addrb_tmp); +-- +-- prcd_write_ram_col ('0', '1', dia_tmp(47 downto 40), dipa_tmp(5), mem(prcd_tmp_addra_dly_depth)(47 downto 40), memp(prcd_tmp_addra_dly_depth)(5)); +---- if (seq = "00") +---- prcd_chk_for_col_msg (wea_tmp(5), web_tmp(5), addra_tmp, addrb_tmp); +-- +-- prcd_write_ram_col ('0', '1', dia_tmp(55 downto 48), dipa_tmp(6), mem(prcd_tmp_addra_dly_depth)(55 downto 48), memp(prcd_tmp_addra_dly_depth)(6)); +---- if (seq = "00") +---- prcd_chk_for_col_msg (wea_tmp(6), web_tmp(6), addra_tmp, addrb_tmp); +-- +-- prcd_write_ram_col ('0', '1', dia_tmp(63 downto 56), dipa_tmp(7), mem(prcd_tmp_addra_dly_depth)(63 downto 56), memp(prcd_tmp_addra_dly_depth)(7)); +---- if (seq = "00") +---- prcd_chk_for_col_msg (wea_tmp(7), web_tmp(7), addra_tmp, addrb_tmp); +-- + when others => null; + + end case; + + end prcd_col_wr_ram_a; + + + procedure prcd_col_wr_ram_b ( + constant seq : in std_logic_vector (1 downto 0); + constant wea_tmp : in std_logic_vector (7 downto 0); + constant web_tmp : in std_logic_vector (7 downto 0); + constant dib_tmp : in std_logic_vector (63 downto 0); + constant dipb_tmp : in std_logic_vector (7 downto 0); + constant addra_tmp : in std_logic_vector (15 downto 0); + constant addrb_tmp : in std_logic_vector (15 downto 0); + variable mem : inout Two_D_array_type; + variable memp : inout Two_D_parity_array_type; + variable col_wr_wr_msg : inout std_ulogic; + variable col_wra_rdb_msg : inout std_ulogic; + variable col_wrb_rda_msg : inout std_ulogic + ) is + variable prcd_tmp_addrb_dly_depth : integer; + variable prcd_tmp_addrb_dly_width : integer; + variable junk : std_ulogic; + + begin + + case wb_width is + + when 1 | 2 | 4 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wb_width > wa_width) or seq = "10") then + if (wb_width >= width) then + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_lbit_124)); + prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(wb_width-1 downto 0), '0', mem(prcd_tmp_addrb_dly_depth), junk); + else + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_124 + 1)); + prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_124 downto w_addrb_lbit_124)); + prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(wb_width-1 downto 0), '0', mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * wb_width) + wb_width - 1 downto (prcd_tmp_addrb_dly_width * wb_width)), junk); + end if; + + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + end if; + + when 8 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wb_width > wa_width) or seq = "10") then + if (wb_width >= width) then + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 3)); + prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth), memp(prcd_tmp_addrb_dly_depth)(0)); + else + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_8 + 1)); + prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_8 downto 3)); + prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 8) + 7 downto (prcd_tmp_addrb_dly_width * 8)), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width))); + end if; + + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + end if; + + when 16 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wb_width > wa_width) or seq = "10") then + if (wb_width >= width) then + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4)); + prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0)); + else + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_16 + 1)); + prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_16 downto 4)); + prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 7 downto (prcd_tmp_addrb_dly_width * 16)), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2))); + end if; + + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + if (wb_width >= width) then + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4)); + prcd_write_ram_col (wea_tmp(1), web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1)); + else + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_16 + 1)); + prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_16 downto 4)); + prcd_write_ram_col (wea_tmp(1), web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 15 downto (prcd_tmp_addrb_dly_width * 16) + 8), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2) + 1)); + end if; + + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + end if; + when 32 => if (not(wea_tmp(0) = '1' and web_tmp(0) = '1' and wb_width > wa_width) or seq = "10") then + + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 5)); + prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0)); + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + prcd_write_ram_col (wea_tmp(1), web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1)); + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + prcd_write_ram_col (wea_tmp(2), web_tmp(2), dib_tmp(23 downto 16), dipb_tmp(2), mem(prcd_tmp_addrb_dly_depth)(23 downto 16), memp(prcd_tmp_addrb_dly_depth)(2)); + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(2), web_tmp(2), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + prcd_write_ram_col (wea_tmp(3), web_tmp(3), dib_tmp(31 downto 24), dipb_tmp(3), mem(prcd_tmp_addrb_dly_depth)(31 downto 24), memp(prcd_tmp_addrb_dly_depth)(3)); + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(3), web_tmp(3), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + end if; + when 64 => + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 6)); + prcd_write_ram_col (wea_tmp(0), web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0)); + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(0), web_tmp(0), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + prcd_write_ram_col (wea_tmp(1), web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1)); + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(1), web_tmp(1), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + prcd_write_ram_col (wea_tmp(2), web_tmp(2), dib_tmp(23 downto 16), dipb_tmp(2), mem(prcd_tmp_addrb_dly_depth)(23 downto 16), memp(prcd_tmp_addrb_dly_depth)(2)); + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(2), web_tmp(2), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + prcd_write_ram_col (wea_tmp(3), web_tmp(3), dib_tmp(31 downto 24), dipb_tmp(3), mem(prcd_tmp_addrb_dly_depth)(31 downto 24), memp(prcd_tmp_addrb_dly_depth)(3)); + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(3), web_tmp(3), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + prcd_write_ram_col (wea_tmp(4), web_tmp(4), dib_tmp(39 downto 32), dipb_tmp(4), mem(prcd_tmp_addrb_dly_depth)(39 downto 32), memp(prcd_tmp_addrb_dly_depth)(4)); + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(4), web_tmp(4), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + prcd_write_ram_col (wea_tmp(5), web_tmp(5), dib_tmp(47 downto 40), dipb_tmp(5), mem(prcd_tmp_addrb_dly_depth)(47 downto 40), memp(prcd_tmp_addrb_dly_depth)(5)); + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(5), web_tmp(5), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + prcd_write_ram_col (wea_tmp(6), web_tmp(6), dib_tmp(55 downto 48), dipb_tmp(6), mem(prcd_tmp_addrb_dly_depth)(55 downto 48), memp(prcd_tmp_addrb_dly_depth)(6)); + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(6), web_tmp(6), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + prcd_write_ram_col (wea_tmp(7), web_tmp(7), dib_tmp(63 downto 56), dipb_tmp(7), mem(prcd_tmp_addrb_dly_depth)(63 downto 56), memp(prcd_tmp_addrb_dly_depth)(7)); + if (seq = "00") then + prcd_chk_for_col_msg (wea_tmp(7), web_tmp(7), addra_tmp, addrb_tmp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + end if; + + when others => null; + + end case; + + end prcd_col_wr_ram_b; + + + procedure prcd_col_rd_ram_a ( + constant viol_type_tmp : in std_logic_vector (1 downto 0); + constant seq : in std_logic_vector (1 downto 0); + constant web_tmp : in std_logic_vector (7 downto 0); + constant wea_tmp : in std_logic_vector (7 downto 0); + constant addra_tmp : in std_logic_vector (15 downto 0); + variable doa_tmp : inout std_logic_vector (63 downto 0); + variable dopa_tmp : inout std_logic_vector (7 downto 0); + constant mem : in Two_D_array_type; + constant memp : in Two_D_parity_array_type; + constant wr_mode_a_tmp : in std_logic_vector (1 downto 0) + + ) is + variable prcd_tmp_addra_dly_depth : integer; + variable prcd_tmp_addra_dly_width : integer; + variable junk : std_ulogic; + variable doa_ltmp : std_logic_vector (63 downto 0); + variable dopa_ltmp : std_logic_vector (7 downto 0); + + begin + + doa_ltmp := (others => '0'); + dopa_ltmp := (others => '0'); + + case ra_width is + + when 1 | 2 | 4 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then + + if (ra_width >= width) then + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_lbit_124)); + doa_ltmp(ra_width-1 downto 0) := mem(prcd_tmp_addra_dly_depth); + else + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_124 + 1)); + prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_124 downto r_addra_lbit_124)); + doa_ltmp(ra_width-1 downto 0) := mem(prcd_tmp_addra_dly_depth)(((prcd_tmp_addra_dly_width * ra_width) + ra_width - 1) downto (prcd_tmp_addra_dly_width * ra_width)); + + end if; + prcd_x_buf (wr_mode_a_tmp, 3, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end if; + + when 8 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then + + if (ra_width >= width) then + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 3)); + doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth); + dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(0); + else + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_8 + 1)); + prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_8 downto 3)); + doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(((prcd_tmp_addra_dly_width * 8) + 7) downto (prcd_tmp_addra_dly_width * 8)); + dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(prcd_tmp_addra_dly_width); + end if; + prcd_x_buf (wr_mode_a_tmp, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + + end if; + + when 16 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then + + if (ra_width >= width) then + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4)); + doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(7 downto 0); + dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(0); + else + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_16 + 1)); + prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_16 downto 4)); + + doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(((prcd_tmp_addra_dly_width * 16) + 7) downto (prcd_tmp_addra_dly_width * 16)); + dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(prcd_tmp_addra_dly_width * 2); + end if; + prcd_x_buf (wr_mode_a_tmp, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + + end if; + + if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and web_tmp(1) = '1' and wea_tmp(1) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(1) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(1) /= '1')) then + + if (ra_width >= width) then + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4)); + doa_ltmp(15 downto 8) := mem(prcd_tmp_addra_dly_depth)(15 downto 8); + dopa_ltmp(1) := memp(prcd_tmp_addra_dly_depth)(1); + else + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto r_addra_bit_16 + 1)); + prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(r_addra_bit_16 downto 4)); + + doa_ltmp(15 downto 8) := mem(prcd_tmp_addra_dly_depth)(((prcd_tmp_addra_dly_width * 16) + 15) downto ((prcd_tmp_addra_dly_width * 16) + 8)); + dopa_ltmp(1) := memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2) + 1); + end if; + prcd_x_buf (wr_mode_a_tmp, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + + end if; + + when 32 => if (ra_width >= width) then + + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 5)); + + if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then + + doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(7 downto 0); + dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(0); + prcd_x_buf (wr_mode_a_tmp, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + + end if; + + if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and web_tmp(1) = '1' and wea_tmp(1) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(1) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(1) /= '1')) then + + doa_ltmp(15 downto 8) := mem(prcd_tmp_addra_dly_depth)(15 downto 8); + dopa_ltmp(1) := memp(prcd_tmp_addra_dly_depth)(1); + prcd_x_buf (wr_mode_a_tmp, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + + end if; + + if ((web_tmp(2) = '1' and wea_tmp(2) = '1') or (seq = "01" and web_tmp(2) = '1' and wea_tmp(2) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(2) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(2) /= '1')) then + + doa_ltmp(23 downto 16) := mem(prcd_tmp_addra_dly_depth)(23 downto 16); + dopa_ltmp(2) := memp(prcd_tmp_addra_dly_depth)(2); + prcd_x_buf (wr_mode_a_tmp, 23, 16, 2, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + + end if; + + if ((web_tmp(3) = '1' and wea_tmp(3) = '1') or (seq = "01" and web_tmp(3) = '1' and wea_tmp(3) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(3) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(3) /= '1')) then + + doa_ltmp(31 downto 24) := mem(prcd_tmp_addra_dly_depth)(31 downto 24); + dopa_ltmp(3) := memp(prcd_tmp_addra_dly_depth)(3); + prcd_x_buf (wr_mode_a_tmp, 31, 24, 3, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + + end if; + + end if; + + when 64 => + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 6)); + + if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and web_tmp(0) = '1' and wea_tmp(0) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(0) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(0) /= '1')) then + + doa_ltmp(7 downto 0) := mem(prcd_tmp_addra_dly_depth)(7 downto 0); + dopa_ltmp(0) := memp(prcd_tmp_addra_dly_depth)(0); + prcd_x_buf (wr_mode_a_tmp, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + + end if; + + if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and web_tmp(1) = '1' and wea_tmp(1) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(1) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(1) /= '1')) then + + doa_ltmp(15 downto 8) := mem(prcd_tmp_addra_dly_depth)(15 downto 8); + dopa_ltmp(1) := memp(prcd_tmp_addra_dly_depth)(1); + prcd_x_buf (wr_mode_a_tmp, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + + end if; + + if ((web_tmp(2) = '1' and wea_tmp(2) = '1') or (seq = "01" and web_tmp(2) = '1' and wea_tmp(2) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(2) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(2) /= '1')) then + + doa_ltmp(23 downto 16) := mem(prcd_tmp_addra_dly_depth)(23 downto 16); + dopa_ltmp(2) := memp(prcd_tmp_addra_dly_depth)(2); + prcd_x_buf (wr_mode_a_tmp, 23, 16, 2, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + + end if; + + if ((web_tmp(3) = '1' and wea_tmp(3) = '1') or (seq = "01" and web_tmp(3) = '1' and wea_tmp(3) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(3) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(3) /= '1')) then + + doa_ltmp(31 downto 24) := mem(prcd_tmp_addra_dly_depth)(31 downto 24); + dopa_ltmp(3) := memp(prcd_tmp_addra_dly_depth)(3); + prcd_x_buf (wr_mode_a_tmp, 31, 24, 3, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + + end if; + + if ((web_tmp(4) = '1' and wea_tmp(4) = '1') or (seq = "01" and web_tmp(4) = '1' and wea_tmp(4) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(4) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(4) /= '1')) then + + doa_ltmp(39 downto 32) := mem(prcd_tmp_addra_dly_depth)(39 downto 32); + dopa_ltmp(4) := memp(prcd_tmp_addra_dly_depth)(4); + prcd_x_buf (wr_mode_a_tmp, 39, 32, 4, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + + end if; + + if ((web_tmp(5) = '1' and wea_tmp(5) = '1') or (seq = "01" and web_tmp(5) = '1' and wea_tmp(5) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(5) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(5) /= '1')) then + + doa_ltmp(47 downto 40) := mem(prcd_tmp_addra_dly_depth)(47 downto 40); + dopa_ltmp(5) := memp(prcd_tmp_addra_dly_depth)(5); + prcd_x_buf (wr_mode_a_tmp, 47, 40, 5, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + + end if; + + if ((web_tmp(6) = '1' and wea_tmp(6) = '1') or (seq = "01" and web_tmp(6) = '1' and wea_tmp(6) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(6) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(6) /= '1')) then + + doa_ltmp(55 downto 48) := mem(prcd_tmp_addra_dly_depth)(55 downto 48); + dopa_ltmp(6) := memp(prcd_tmp_addra_dly_depth)(6); + prcd_x_buf (wr_mode_a_tmp, 55, 48, 6, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + + end if; + + if ((web_tmp(7) = '1' and wea_tmp(7) = '1') or (seq = "01" and web_tmp(7) = '1' and wea_tmp(7) = '0' and viol_type_tmp = "10") or (seq = "01" and WRITE_MODE_A /= "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST") or (seq = "01" and WRITE_MODE_A = "READ_FIRST" and WRITE_MODE_B /= "READ_FIRST" and web_tmp(7) = '1') or (seq = "11" and WRITE_MODE_A = "WRITE_FIRST" and web_tmp(7) /= '1')) then + + doa_ltmp(63 downto 56) := mem(prcd_tmp_addra_dly_depth)(63 downto 56); + dopa_ltmp(7) := memp(prcd_tmp_addra_dly_depth)(7); + prcd_x_buf (wr_mode_a_tmp, 63, 56, 7, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + + end if; + + when others => null; + + end case; + + end prcd_col_rd_ram_a; + + + procedure prcd_col_rd_ram_b ( + constant viol_type_tmp : in std_logic_vector (1 downto 0); + constant seq : in std_logic_vector (1 downto 0); + constant wea_tmp : in std_logic_vector (7 downto 0); + constant web_tmp : in std_logic_vector (7 downto 0); + constant addrb_tmp : in std_logic_vector (15 downto 0); + variable dob_tmp : inout std_logic_vector (63 downto 0); + variable dopb_tmp : inout std_logic_vector (7 downto 0); + constant mem : in Two_D_array_type; + constant memp : in Two_D_parity_array_type; + constant wr_mode_b_tmp : in std_logic_vector (1 downto 0) + + ) is + variable prcd_tmp_addrb_dly_depth : integer; + variable prcd_tmp_addrb_dly_width : integer; + variable junk : std_ulogic; + variable dob_ltmp : std_logic_vector (63 downto 0); + variable dopb_ltmp : std_logic_vector (7 downto 0); + + begin + + dob_ltmp := (others => '0'); + dopb_ltmp := (others => '0'); + + case rb_width is + + when 1 | 2 | 4 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then + + if (rb_width >= width) then + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_lbit_124)); + dob_ltmp(rb_width-1 downto 0) := mem(prcd_tmp_addrb_dly_depth); + else + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_124 + 1)); + prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_124 downto r_addrb_lbit_124)); + dob_ltmp(rb_width-1 downto 0) := mem(prcd_tmp_addrb_dly_depth)(((prcd_tmp_addrb_dly_width * rb_width) + rb_width - 1) downto (prcd_tmp_addrb_dly_width * rb_width)); + end if; + prcd_x_buf (wr_mode_b_tmp, 3, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end if; + + when 8 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then + + if (rb_width >= width) then + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 3)); + dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth); + dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(0); + else + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_8 + 1)); + prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_8 downto 3)); + dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(((prcd_tmp_addrb_dly_width * 8) + 7) downto (prcd_tmp_addrb_dly_width * 8)); + dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(prcd_tmp_addrb_dly_width); + end if; + prcd_x_buf (wr_mode_b_tmp, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end if; + + when 16 => if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then + + if (rb_width >= width) then + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4)); + dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(7 downto 0); + dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(0); + else + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_16 + 1)); + prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_16 downto 4)); + + dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(((prcd_tmp_addrb_dly_width * 16) + 7) downto (prcd_tmp_addrb_dly_width * 16)); + dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(prcd_tmp_addrb_dly_width * 2); + end if; + prcd_x_buf (wr_mode_b_tmp, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end if; + + + if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and wea_tmp(1) = '1' and web_tmp(1) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(1) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(1) /= '1')) then + + if (rb_width >= width) then + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4)); + dob_ltmp(15 downto 8) := mem(prcd_tmp_addrb_dly_depth)(15 downto 8); + dopb_ltmp(1) := memp(prcd_tmp_addrb_dly_depth)(1); + else + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto r_addrb_bit_16 + 1)); + prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(r_addrb_bit_16 downto 4)); + + dob_ltmp(15 downto 8) := mem(prcd_tmp_addrb_dly_depth)(((prcd_tmp_addrb_dly_width * 16) + 15) downto ((prcd_tmp_addrb_dly_width * 16) + 8)); + dopb_ltmp(1) := memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2) + 1); + end if; + prcd_x_buf (wr_mode_b_tmp, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end if; + + when 32 => if (rb_width >= width) then + + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 5)); + + if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then + + dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(7 downto 0); + dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(0); + prcd_x_buf (wr_mode_b_tmp, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end if; + + if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and wea_tmp(1) = '1' and web_tmp(1) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(1) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(1) /= '1')) then + + dob_ltmp(15 downto 8) := mem(prcd_tmp_addrb_dly_depth)(15 downto 8); + dopb_ltmp(1) := memp(prcd_tmp_addrb_dly_depth)(1); + prcd_x_buf (wr_mode_b_tmp, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end if; + + if ((web_tmp(2) = '1' and wea_tmp(2) = '1') or (seq = "01" and wea_tmp(2) = '1' and web_tmp(2) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(2) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(2) /= '1')) then + + dob_ltmp(23 downto 16) := mem(prcd_tmp_addrb_dly_depth)(23 downto 16); + dopb_ltmp(2) := memp(prcd_tmp_addrb_dly_depth)(2); + prcd_x_buf (wr_mode_b_tmp, 23, 16, 2, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end if; + + if ((web_tmp(3) = '1' and wea_tmp(3) = '1') or (seq = "01" and wea_tmp(3) = '1' and web_tmp(3) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(3) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(3) /= '1')) then + + dob_ltmp(31 downto 24) := mem(prcd_tmp_addrb_dly_depth)(31 downto 24); + dopb_ltmp(3) := memp(prcd_tmp_addrb_dly_depth)(3); + prcd_x_buf (wr_mode_b_tmp, 31, 24, 3, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end if; + + end if; + + when 64 => + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 6)); + + if ((web_tmp(0) = '1' and wea_tmp(0) = '1') or (seq = "01" and wea_tmp(0) = '1' and web_tmp(0) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(0) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(0) /= '1')) then + + dob_ltmp(7 downto 0) := mem(prcd_tmp_addrb_dly_depth)(7 downto 0); + dopb_ltmp(0) := memp(prcd_tmp_addrb_dly_depth)(0); + prcd_x_buf (wr_mode_b_tmp, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end if; + + if ((web_tmp(1) = '1' and wea_tmp(1) = '1') or (seq = "01" and wea_tmp(1) = '1' and web_tmp(1) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(1) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(1) /= '1')) then + + dob_ltmp(15 downto 8) := mem(prcd_tmp_addrb_dly_depth)(15 downto 8); + dopb_ltmp(1) := memp(prcd_tmp_addrb_dly_depth)(1); + prcd_x_buf (wr_mode_b_tmp, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end if; + + if ((web_tmp(2) = '1' and wea_tmp(2) = '1') or (seq = "01" and wea_tmp(2) = '1' and web_tmp(2) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(2) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(2) /= '1')) then + + dob_ltmp(23 downto 16) := mem(prcd_tmp_addrb_dly_depth)(23 downto 16); + dopb_ltmp(2) := memp(prcd_tmp_addrb_dly_depth)(2); + prcd_x_buf (wr_mode_b_tmp, 23, 16, 2, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end if; + + if ((web_tmp(3) = '1' and wea_tmp(3) = '1') or (seq = "01" and wea_tmp(3) = '1' and web_tmp(3) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(3) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(3) /= '1')) then + + dob_ltmp(31 downto 24) := mem(prcd_tmp_addrb_dly_depth)(31 downto 24); + dopb_ltmp(3) := memp(prcd_tmp_addrb_dly_depth)(3); + prcd_x_buf (wr_mode_b_tmp, 31, 24, 3, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end if; + + if ((web_tmp(4) = '1' and wea_tmp(4) = '1') or (seq = "01" and wea_tmp(4) = '1' and web_tmp(4) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(4) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(4) /= '1')) then + + dob_ltmp(39 downto 32) := mem(prcd_tmp_addrb_dly_depth)(39 downto 32); + dopb_ltmp(4) := memp(prcd_tmp_addrb_dly_depth)(4); + prcd_x_buf (wr_mode_b_tmp, 39, 32, 4, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end if; + + if ((web_tmp(5) = '1' and wea_tmp(5) = '1') or (seq = "01" and wea_tmp(5) = '1' and web_tmp(5) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(5) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(5) /= '1')) then + + dob_ltmp(47 downto 40) := mem(prcd_tmp_addrb_dly_depth)(47 downto 40); + dopb_ltmp(5) := memp(prcd_tmp_addrb_dly_depth)(5); + prcd_x_buf (wr_mode_b_tmp, 47, 40, 5, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end if; + + if ((web_tmp(6) = '1' and wea_tmp(6) = '1') or (seq = "01" and wea_tmp(6) = '1' and web_tmp(6) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(6) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(6) /= '1')) then + + dob_ltmp(55 downto 48) := mem(prcd_tmp_addrb_dly_depth)(55 downto 48); + dopb_ltmp(6) := memp(prcd_tmp_addrb_dly_depth)(6); + prcd_x_buf (wr_mode_b_tmp, 55, 48, 6, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end if; + + if ((web_tmp(7) = '1' and wea_tmp(7) = '1') or (seq = "01" and wea_tmp(7) = '1' and web_tmp(7) = '0' and viol_type_tmp = "11") or (seq = "01" and WRITE_MODE_B /= "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST") or (seq = "01" and WRITE_MODE_B = "READ_FIRST" and WRITE_MODE_A /= "READ_FIRST" and wea_tmp(7) = '1') or (seq = "11" and WRITE_MODE_B = "WRITE_FIRST" and wea_tmp(7) /= '1')) then + + dob_ltmp(63 downto 56) := mem(prcd_tmp_addrb_dly_depth)(63 downto 56); + dopb_ltmp(7) := memp(prcd_tmp_addrb_dly_depth)(7); + prcd_x_buf (wr_mode_b_tmp, 63, 56, 7, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end if; + + when others => null; + + end case; + + end prcd_col_rd_ram_b; + + + procedure prcd_wr_ram_a ( + constant wea_tmp : in std_logic_vector (7 downto 0); + constant dia_tmp : in std_logic_vector (63 downto 0); + constant dipa_tmp : in std_logic_vector (7 downto 0); + constant addra_tmp : in std_logic_vector (15 downto 0); + variable mem : inout Two_D_array_type; + variable memp : inout Two_D_parity_array_type; + constant syndrome_tmp : in std_logic_vector (7 downto 0) + ) is + variable prcd_tmp_addra_dly_depth : integer; + variable prcd_tmp_addra_dly_width : integer; + variable junk : std_ulogic; + + begin + + case wa_width is + + when 1 | 2 | 4 => + if (wa_width >= width) then + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_lbit_124)); + prcd_write_ram (wea_tmp(0), dia_tmp(wa_width-1 downto 0), '0', mem(prcd_tmp_addra_dly_depth), junk); + else + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_124 + 1)); + prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_124 downto w_addra_lbit_124)); + prcd_write_ram (wea_tmp(0), dia_tmp(wa_width-1 downto 0), '0', mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * wa_width) + wa_width - 1 downto (prcd_tmp_addra_dly_width * wa_width)), junk); + end if; + + when 8 => + if (wa_width >= width) then + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 3)); + prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth), memp(prcd_tmp_addra_dly_depth)(0)); + else + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_8 + 1)); + prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_8 downto 3)); + prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 8) + 7 downto (prcd_tmp_addra_dly_width * 8)), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width))); + end if; + + when 16 => + if (wa_width >= width) then + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 4)); + prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0)); + prcd_write_ram (wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1)); + else + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto w_addra_bit_16 + 1)); + prcd_tmp_addra_dly_width := SLV_TO_INT(addra_tmp(w_addra_bit_16 downto 4)); + prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 7 downto (prcd_tmp_addra_dly_width * 16)), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2))); + prcd_write_ram (wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 16) + 15 downto (prcd_tmp_addra_dly_width * 16) + 8), memp(prcd_tmp_addra_dly_depth)((prcd_tmp_addra_dly_width * 2) + 1)); + end if; + + when 32 => + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 5)); + + prcd_write_ram (wea_tmp(0), dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0)); + prcd_write_ram (wea_tmp(1), dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1)); + prcd_write_ram (wea_tmp(2), dia_tmp(23 downto 16), dipa_tmp(2), mem(prcd_tmp_addra_dly_depth)(23 downto 16), memp(prcd_tmp_addra_dly_depth)(2)); + prcd_write_ram (wea_tmp(3), dia_tmp(31 downto 24), dipa_tmp(3), mem(prcd_tmp_addra_dly_depth)(31 downto 24), memp(prcd_tmp_addra_dly_depth)(3)); + + when 64 => if (syndrome_tmp /= "00000000" and syndrome_tmp(7) = '1' and EN_ECC_SCRUB = TRUE) then + + prcd_tmp_addra_dly_depth := SLV_TO_INT(addra_tmp(14 downto 6)); + prcd_write_ram ('1', dia_tmp(7 downto 0), dipa_tmp(0), mem(prcd_tmp_addra_dly_depth)(7 downto 0), memp(prcd_tmp_addra_dly_depth)(0)); + prcd_write_ram ('1', dia_tmp(15 downto 8), dipa_tmp(1), mem(prcd_tmp_addra_dly_depth)(15 downto 8), memp(prcd_tmp_addra_dly_depth)(1)); + prcd_write_ram ('1', dia_tmp(23 downto 16), dipa_tmp(2), mem(prcd_tmp_addra_dly_depth)(23 downto 16), memp(prcd_tmp_addra_dly_depth)(2)); + prcd_write_ram ('1', dia_tmp(31 downto 24), dipa_tmp(3), mem(prcd_tmp_addra_dly_depth)(31 downto 24), memp(prcd_tmp_addra_dly_depth)(3)); + prcd_write_ram ('1', dia_tmp(39 downto 32), dipa_tmp(4), mem(prcd_tmp_addra_dly_depth)(39 downto 32), memp(prcd_tmp_addra_dly_depth)(4)); + prcd_write_ram ('1', dia_tmp(47 downto 40), dipa_tmp(5), mem(prcd_tmp_addra_dly_depth)(47 downto 40), memp(prcd_tmp_addra_dly_depth)(5)); + prcd_write_ram ('1', dia_tmp(55 downto 48), dipa_tmp(6), mem(prcd_tmp_addra_dly_depth)(55 downto 48), memp(prcd_tmp_addra_dly_depth)(6)); + prcd_write_ram ('1', dia_tmp(63 downto 56), dipa_tmp(7), mem(prcd_tmp_addra_dly_depth)(63 downto 56), memp(prcd_tmp_addra_dly_depth)(7)); + + end if; + + when others => null; + + end case; + + end prcd_wr_ram_a; + + + procedure prcd_wr_ram_b ( + constant web_tmp : in std_logic_vector (7 downto 0); + constant dib_tmp : in std_logic_vector (63 downto 0); + constant dipb_tmp : in std_logic_vector (7 downto 0); + constant addrb_tmp : in std_logic_vector (15 downto 0); + variable mem : inout Two_D_array_type; + variable memp : inout Two_D_parity_array_type + ) is + variable prcd_tmp_addrb_dly_depth : integer; + variable prcd_tmp_addrb_dly_width : integer; + variable junk : std_ulogic; + + begin + + case wb_width is + + when 1 | 2 | 4 => + if (wb_width >= width) then + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_lbit_124)); + prcd_write_ram (web_tmp(0), dib_tmp(wb_width-1 downto 0), '0', mem(prcd_tmp_addrb_dly_depth), junk); + else + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_124 + 1)); + prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_124 downto w_addrb_lbit_124)); + prcd_write_ram (web_tmp(0), dib_tmp(wb_width-1 downto 0), '0', mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * wb_width) + wb_width - 1 downto (prcd_tmp_addrb_dly_width * wb_width)), junk); + end if; + + when 8 => + if (wb_width >= width) then + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 3)); + prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth), memp(prcd_tmp_addrb_dly_depth)(0)); + else + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_8 + 1)); + prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_8 downto 3)); + prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 8) + 7 downto (prcd_tmp_addrb_dly_width * 8)), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width))); + end if; + + when 16 => + if (wb_width >= width) then + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 4)); + prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0)); + prcd_write_ram (web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1)); + else + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto w_addrb_bit_16 + 1)); + prcd_tmp_addrb_dly_width := SLV_TO_INT(addrb_tmp(w_addrb_bit_16 downto 4)); + prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 7 downto (prcd_tmp_addrb_dly_width * 16)), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2))); + prcd_write_ram (web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 16) + 15 downto (prcd_tmp_addrb_dly_width * 16) + 8), memp(prcd_tmp_addrb_dly_depth)((prcd_tmp_addrb_dly_width * 2) + 1)); + end if; + + when 32 => + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 5)); + prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0)); + prcd_write_ram (web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1)); + prcd_write_ram (web_tmp(2), dib_tmp(23 downto 16), dipb_tmp(2), mem(prcd_tmp_addrb_dly_depth)(23 downto 16), memp(prcd_tmp_addrb_dly_depth)(2)); + prcd_write_ram (web_tmp(3), dib_tmp(31 downto 24), dipb_tmp(3), mem(prcd_tmp_addrb_dly_depth)(31 downto 24), memp(prcd_tmp_addrb_dly_depth)(3)); + + when 64 => + prcd_tmp_addrb_dly_depth := SLV_TO_INT(addrb_tmp(14 downto 6)); + prcd_write_ram (web_tmp(0), dib_tmp(7 downto 0), dipb_tmp(0), mem(prcd_tmp_addrb_dly_depth)(7 downto 0), memp(prcd_tmp_addrb_dly_depth)(0)); + prcd_write_ram (web_tmp(1), dib_tmp(15 downto 8), dipb_tmp(1), mem(prcd_tmp_addrb_dly_depth)(15 downto 8), memp(prcd_tmp_addrb_dly_depth)(1)); + prcd_write_ram (web_tmp(2), dib_tmp(23 downto 16), dipb_tmp(2), mem(prcd_tmp_addrb_dly_depth)(23 downto 16), memp(prcd_tmp_addrb_dly_depth)(2)); + prcd_write_ram (web_tmp(3), dib_tmp(31 downto 24), dipb_tmp(3), mem(prcd_tmp_addrb_dly_depth)(31 downto 24), memp(prcd_tmp_addrb_dly_depth)(3)); + prcd_write_ram (web_tmp(4), dib_tmp(39 downto 32), dipb_tmp(4), mem(prcd_tmp_addrb_dly_depth)(39 downto 32), memp(prcd_tmp_addrb_dly_depth)(4)); + prcd_write_ram (web_tmp(5), dib_tmp(47 downto 40), dipb_tmp(5), mem(prcd_tmp_addrb_dly_depth)(47 downto 40), memp(prcd_tmp_addrb_dly_depth)(5)); + prcd_write_ram (web_tmp(6), dib_tmp(55 downto 48), dipb_tmp(6), mem(prcd_tmp_addrb_dly_depth)(55 downto 48), memp(prcd_tmp_addrb_dly_depth)(6)); + prcd_write_ram (web_tmp(7), dib_tmp(63 downto 56), dipb_tmp(7), mem(prcd_tmp_addrb_dly_depth)(63 downto 56), memp(prcd_tmp_addrb_dly_depth)(7)); + + when others => null; + + end case; + + end prcd_wr_ram_b; + + + procedure prcd_col_ecc_read ( + + variable do_tmp : inout std_logic_vector (63 downto 0); + variable dop_tmp : inout std_logic_vector (7 downto 0); + constant addr_tmp : in std_logic_vector (15 downto 0); + variable dbiterr_tmp : inout std_logic; + variable sbiterr_tmp : inout std_logic; + variable mem : inout Two_D_array_type; + variable memp : inout Two_D_parity_array_type; + variable prcd_syndrome : inout std_logic_vector (7 downto 0) + ) is + + variable prcd_ecc_bit_position : std_logic_vector (71 downto 0); + variable prcd_dopr_ecc : std_logic_vector (7 downto 0); + variable prcd_di_dly_ecc_corrected : std_logic_vector (63 downto 0); + variable prcd_dip_dly_ecc_corrected : std_logic_vector (7 downto 0); + variable prcd_tmp_syndrome_int : integer := 0; + + begin + + prcd_dopr_ecc := fn_dip_ecc('0', do_tmp, dop_tmp); + + prcd_syndrome := prcd_dopr_ecc xor dop_tmp; + + if (prcd_syndrome /= "00000000") then + + if (prcd_syndrome(7) = '1') then -- dectect single bit error + + prcd_ecc_bit_position := do_tmp(63 downto 57) & dop_tmp(6) & do_tmp(56 downto 26) & dop_tmp(5) & do_tmp(25 downto 11) & dop_tmp(4) & do_tmp(10 downto 4) & dop_tmp(3) & do_tmp(3 downto 1) & dop_tmp(2) & do_tmp(0) & dop_tmp(1 downto 0) & dop_tmp(7); + + prcd_tmp_syndrome_int := SLV_TO_INT(prcd_syndrome(6 downto 0)); + prcd_ecc_bit_position(prcd_tmp_syndrome_int) := not prcd_ecc_bit_position(prcd_tmp_syndrome_int); -- correct single bit error in the output + + prcd_di_dly_ecc_corrected := prcd_ecc_bit_position(71 downto 65) & prcd_ecc_bit_position(63 downto 33) & prcd_ecc_bit_position(31 downto 17) & prcd_ecc_bit_position(15 downto 9) & prcd_ecc_bit_position(7 downto 5) & prcd_ecc_bit_position(3); -- correct single bit error in the memory + + do_tmp := prcd_di_dly_ecc_corrected; + + prcd_dip_dly_ecc_corrected := prcd_ecc_bit_position(0) & prcd_ecc_bit_position(64) & prcd_ecc_bit_position(32) & prcd_ecc_bit_position(16) & prcd_ecc_bit_position(8) & prcd_ecc_bit_position(4) & prcd_ecc_bit_position(2 downto 1); -- correct single bit error in the parity memory + + dop_tmp := prcd_dip_dly_ecc_corrected; + + dbiterr_tmp := '0'; + sbiterr_tmp := '1'; + + elsif (prcd_syndrome(7) = '0') then -- double bit error + sbiterr_tmp := '0'; + dbiterr_tmp := '1'; + end if; + else + dbiterr_tmp := '0'; + sbiterr_tmp := '0'; + end if; + + if (ssra_dly = '1') then -- ssra reset + dbiterr_tmp := '0'; + sbiterr_tmp := '0'; + end if; + + if (prcd_syndrome /= "00000000" and prcd_syndrome(7) = '1' and EN_ECC_SCRUB = TRUE) then + prcd_wr_ram_a ("11111111", prcd_di_dly_ecc_corrected, prcd_dip_dly_ecc_corrected, addr_tmp, mem, memp, prcd_syndrome); + end if; + + end prcd_col_ecc_read; + + + begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + addra_dly <= ADDRA after 0 ps; + addrb_dly <= ADDRB after 0 ps; + cascadeinlata_dly <= CASCADEINLATA after 0 ps; + cascadeinlatb_dly <= CASCADEINLATB after 0 ps; + cascadeinrega_dly <= CASCADEINREGA after 0 ps; + cascadeinregb_dly <= CASCADEINREGB after 0 ps; + clka_dly <= CLKA after 0 ps; + clkb_dly <= CLKB after 0 ps; + dia_dly <= DIA after 0 ps; + dib_dly <= DIB after 0 ps; + dipa_dly <= DIPA after 0 ps; + dipb_dly <= DIPB after 0 ps; + ena_dly <= ENA after 0 ps; + enb_dly <= ENB after 0 ps; + regcea_dly <= REGCEA after 0 ps; + regceb_dly <= REGCEB after 0 ps; + ssra_dly <= SSRA after 0 ps; + ssrb_dly <= SSRB after 0 ps; + wea_dly <= WEA after 0 ps; + web_dly <= WEB after 0 ps; + gsr_dly <= GSR after 0 ps; + regclka_dly <= REGCLKA after 0 ps; + regclkb_dly <= REGCLKB after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + + --------------------------------------------------------------------------- + -- SAFE mode + --------------------------------------------------------------------------- + + safe_mode : if (SIM_MODE = "SAFE") generate + + prcs_clk: process (clka_dly, clkb_dly, gsr_dly) + + variable mem_slv : std_logic_vector(32767 downto 0) := To_StdLogicVector(INIT_7F) & + To_StdLogicVector(INIT_7E) & + To_StdLogicVector(INIT_7D) & + To_StdLogicVector(INIT_7C) & + To_StdLogicVector(INIT_7B) & + To_StdLogicVector(INIT_7A) & + To_StdLogicVector(INIT_79) & + To_StdLogicVector(INIT_78) & + To_StdLogicVector(INIT_77) & + To_StdLogicVector(INIT_76) & + To_StdLogicVector(INIT_75) & + To_StdLogicVector(INIT_74) & + To_StdLogicVector(INIT_73) & + To_StdLogicVector(INIT_72) & + To_StdLogicVector(INIT_71) & + To_StdLogicVector(INIT_70) & + To_StdLogicVector(INIT_6F) & + To_StdLogicVector(INIT_6E) & + To_StdLogicVector(INIT_6D) & + To_StdLogicVector(INIT_6C) & + To_StdLogicVector(INIT_6B) & + To_StdLogicVector(INIT_6A) & + To_StdLogicVector(INIT_69) & + To_StdLogicVector(INIT_68) & + To_StdLogicVector(INIT_67) & + To_StdLogicVector(INIT_66) & + To_StdLogicVector(INIT_65) & + To_StdLogicVector(INIT_64) & + To_StdLogicVector(INIT_63) & + To_StdLogicVector(INIT_62) & + To_StdLogicVector(INIT_61) & + To_StdLogicVector(INIT_60) & + To_StdLogicVector(INIT_5F) & + To_StdLogicVector(INIT_5E) & + To_StdLogicVector(INIT_5D) & + To_StdLogicVector(INIT_5C) & + To_StdLogicVector(INIT_5B) & + To_StdLogicVector(INIT_5A) & + To_StdLogicVector(INIT_59) & + To_StdLogicVector(INIT_58) & + To_StdLogicVector(INIT_57) & + To_StdLogicVector(INIT_56) & + To_StdLogicVector(INIT_55) & + To_StdLogicVector(INIT_54) & + To_StdLogicVector(INIT_53) & + To_StdLogicVector(INIT_52) & + To_StdLogicVector(INIT_51) & + To_StdLogicVector(INIT_50) & + To_StdLogicVector(INIT_4F) & + To_StdLogicVector(INIT_4E) & + To_StdLogicVector(INIT_4D) & + To_StdLogicVector(INIT_4C) & + To_StdLogicVector(INIT_4B) & + To_StdLogicVector(INIT_4A) & + To_StdLogicVector(INIT_49) & + To_StdLogicVector(INIT_48) & + To_StdLogicVector(INIT_47) & + To_StdLogicVector(INIT_46) & + To_StdLogicVector(INIT_45) & + To_StdLogicVector(INIT_44) & + To_StdLogicVector(INIT_43) & + To_StdLogicVector(INIT_42) & + To_StdLogicVector(INIT_41) & + To_StdLogicVector(INIT_40) & + To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable memp_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INITP_0F) & + To_StdLogicVector(INITP_0E) & + To_StdLogicVector(INITP_0D) & + To_StdLogicVector(INITP_0C) & + To_StdLogicVector(INITP_0B) & + To_StdLogicVector(INITP_0A) & + To_StdLogicVector(INITP_09) & + To_StdLogicVector(INITP_08) & + To_StdLogicVector(INITP_07) & + To_StdLogicVector(INITP_06) & + To_StdLogicVector(INITP_05) & + To_StdLogicVector(INITP_04) & + To_StdLogicVector(INITP_03) & + To_StdLogicVector(INITP_02) & + To_StdLogicVector(INITP_01) & + To_StdLogicVector(INITP_00); + + variable tmp_mem : Two_D_array_type_tmp_mem := two_D_mem_initf(widest_width); + variable mem : Two_D_array_type := two_D_mem_init(mem_depth, width, mem_slv, tmp_mem); + variable memp : Two_D_parity_array_type := two_D_mem_initp(memp_depth, widthp, memp_slv, tmp_mem, width); + variable tmp_addra_dly_depth : integer; + variable tmp_addra_dly_width : integer; + variable tmp_addrb_dly_depth : integer; + variable tmp_addrb_dly_width : integer; + variable junk1 : std_logic; + variable wr_mode_a : std_logic_vector(1 downto 0) := "00"; + variable wr_mode_b : std_logic_vector(1 downto 0) := "00"; + variable tmp_syndrome_int : integer; + variable doa_buf : std_logic_vector(63 downto 0) := (others => '0'); + variable dob_buf : std_logic_vector(63 downto 0) := (others => '0'); + variable dopa_buf : std_logic_vector(7 downto 0) := (others => '0'); + variable dopb_buf : std_logic_vector(7 downto 0) := (others => '0'); + variable syndrome : std_logic_vector(7 downto 0) := (others => '0'); + variable dopr_ecc : std_logic_vector(7 downto 0) := (others => '0'); + variable dia_dly_ecc_corrected : std_logic_vector(63 downto 0) := (others => '0'); + variable dipa_dly_ecc_corrected : std_logic_vector(7 downto 0) := (others => '0'); + variable dip_ecc : std_logic_vector(7 downto 0) := (others => '0'); + variable dipb_dly_ecc : std_logic_vector(7 downto 0) := (others => '0'); + variable ecc_bit_position : std_logic_vector(71 downto 0) := (others => '0'); + variable addra_dly_15_reg_var : std_logic := '0'; + variable addrb_dly_15_reg_var : std_logic := '0'; + variable addra_dly_15_reg_bram_var : std_logic := '0'; + variable addrb_dly_15_reg_bram_var : std_logic := '0'; + variable FIRST_TIME : boolean := true; + + variable curr_time : time := 0 ps; + variable prev_time : time := 0 ps; + variable viol_time : integer := 0; + variable viol_type : std_logic_vector(1 downto 0) := (others => '0'); + variable message : line; + variable dip_ecc_col : std_logic_vector (7 downto 0) := (others => '0'); + variable dbiterr_out_var : std_ulogic := '0'; + variable sbiterr_out_var : std_ulogic := '0'; + + variable dia_reg_dly : std_logic_vector(63 downto 0) := (others => '0'); + variable dipa_reg_dly : std_logic_vector(7 downto 0) := (others => '0'); + variable wea_reg_dly : std_logic_vector(7 downto 0) := (others => '0'); + variable addra_reg_dly : std_logic_vector(15 downto 0) := (others => '0'); + variable dib_reg_dly : std_logic_vector(63 downto 0) := (others => '0'); + variable dipb_reg_dly : std_logic_vector(7 downto 0) := (others => '0'); + variable web_reg_dly : std_logic_vector(7 downto 0) := (others => '0'); + variable addrb_reg_dly : std_logic_vector(15 downto 0) := (others => '0'); + variable col_wr_wr_msg : std_ulogic := '1'; + variable col_wra_rdb_msg : std_ulogic := '1'; + variable col_wrb_rda_msg : std_ulogic := '1'; + variable addr_col : std_logic := '0'; + + begin -- process prcs_clka + + if (FIRST_TIME) then + + if (SIM_MODE /= "FAST" and SIM_MODE /= "SAFE") then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " SIM_MODE ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => SIM_MODE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " FAST or SAFE ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + case READ_WIDTH_A is + when 0 | 1 | 2 | 4 | 9 | 18 => null; + when 36 => if (BRAM_SIZE = 18 and BRAM_MODE = "TRUE_DUAL_PORT") then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " READ_WIDTH_A ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => READ_WIDTH_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", + TailMsg => "", + MsgSeverity => failure + ); + end if; + when 72 => if (BRAM_SIZE = 18) then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " READ_WIDTH_A ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => READ_WIDTH_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", + TailMsg => "", + MsgSeverity => failure + ); + elsif ((BRAM_SIZE = 16 or BRAM_SIZE = 36) and BRAM_MODE = "TRUE_DUAL_PORT") then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " READ_WIDTH_A ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => READ_WIDTH_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", + TailMsg => "", + MsgSeverity => failure + ); + end if; + when others => if (BRAM_SIZE = 18) then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " READ_WIDTH_A ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => READ_WIDTH_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", + TailMsg => "", + MsgSeverity => failure + ); + elsif (BRAM_SIZE = 16 or BRAM_SIZE = 36) then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " READ_WIDTH_A ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => READ_WIDTH_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", + TailMsg => "", + MsgSeverity => failure + ); + end if; + end case; + + + case READ_WIDTH_B is + when 0 | 1 | 2 | 4 | 9 | 18 => null; + when 36 => if (BRAM_SIZE = 18 and BRAM_MODE = "TRUE_DUAL_PORT") then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " READ_WIDTH_B ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => READ_WIDTH_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", + TailMsg => "", + MsgSeverity => failure + ); + end if; + when 72 => if (BRAM_SIZE = 18) then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " READ_WIDTH_B ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => READ_WIDTH_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", + TailMsg => "", + MsgSeverity => failure + ); + elsif ((BRAM_SIZE = 16 or BRAM_SIZE = 36) and BRAM_MODE = "TRUE_DUAL_PORT") then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " READ_WIDTH_B ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => READ_WIDTH_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", + TailMsg => "", + MsgSeverity => failure + ); + end if; + when others => if (BRAM_SIZE = 18) then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " READ_WIDTH_B ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => READ_WIDTH_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", + TailMsg => "", + MsgSeverity => failure + ); + elsif (BRAM_SIZE = 16 or BRAM_SIZE = 36) then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " READ_WIDTH_B ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => READ_WIDTH_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", + TailMsg => "", + MsgSeverity => failure + ); + end if; + end case; + + + case WRITE_WIDTH_A is + when 0 | 1 | 2 | 4 | 9 | 18 => null; + when 36 => if (BRAM_SIZE = 18 and BRAM_MODE = "TRUE_DUAL_PORT") then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " WRITE_WIDTH_A ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => WRITE_WIDTH_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", + TailMsg => "", + MsgSeverity => failure + ); + end if; + when 72 => if (BRAM_SIZE = 18) then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " WRITE_WIDTH_A ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => WRITE_WIDTH_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", + TailMsg => "", + MsgSeverity => failure + ); + elsif ((BRAM_SIZE = 16 or BRAM_SIZE = 36) and BRAM_MODE = "TRUE_DUAL_PORT") then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " WRITE_WIDTH_A ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => WRITE_WIDTH_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", + TailMsg => "", + MsgSeverity => failure + ); + end if; + when others => if (BRAM_SIZE = 18) then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " WRITE_WIDTH_A ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => WRITE_WIDTH_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", + TailMsg => "", + MsgSeverity => failure + ); + elsif (BRAM_SIZE = 16 or BRAM_SIZE = 36) then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " WRITE_WIDTH_A ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => WRITE_WIDTH_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", + TailMsg => "", + MsgSeverity => failure + ); + end if; + end case; + + + case WRITE_WIDTH_B is + when 0 | 1 | 2 | 4 | 9 | 18 => null; + when 36 => if (BRAM_SIZE = 18 and BRAM_MODE = "TRUE_DUAL_PORT") then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " WRITE_WIDTH_B ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => WRITE_WIDTH_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", + TailMsg => "", + MsgSeverity => failure + ); + end if; + when 72 => if (BRAM_SIZE = 18) then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " WRITE_WIDTH_B ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => WRITE_WIDTH_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", + TailMsg => "", + MsgSeverity => failure + ); + elsif ((BRAM_SIZE = 16 or BRAM_SIZE = 36) and BRAM_MODE = "TRUE_DUAL_PORT") then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " WRITE_WIDTH_B ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => WRITE_WIDTH_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", + TailMsg => "", + MsgSeverity => failure + ); + end if; + when others => if (BRAM_SIZE = 18) then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " WRITE_WIDTH_B ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => WRITE_WIDTH_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9 or 18.", + TailMsg => "", + MsgSeverity => failure + ); + elsif (BRAM_SIZE = 16 or BRAM_SIZE = 36) then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " WRITE_WIDTH_B ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => WRITE_WIDTH_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", + TailMsg => "", + MsgSeverity => failure + ); + end if; + end case; + + + if (not(EN_ECC_READ = TRUE or EN_ECC_READ = FALSE)) then + + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " EN_ECC_READ ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => EN_ECC_READ, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " TRUE or FALSE ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + if (not(EN_ECC_WRITE = TRUE or EN_ECC_WRITE = FALSE)) then + + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " EN_ECC_WRITE ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => EN_ECC_WRITE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " TRUE or FALSE ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + if (EN_ECC_SCRUB = TRUE) then + assert false + report "DRC Error : The attribute EN_ECC_SCRUB = TRUE is not supported on ARAMB36_INTERNAL instance." + severity failure; + end if; + + if (not(EN_ECC_SCRUB = TRUE or EN_ECC_SCRUB = FALSE)) then + + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " EN_ECC_SCRUB ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => EN_ECC_SCRUB, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " TRUE or FALSE ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + + if (EN_ECC_READ = FALSE and EN_ECC_SCRUB = TRUE) then + assert false + report "DRC Error : The attribute EN_ECC_SCRUB = TRUE is vaild only if the attribute EN_ECC_READ set to TRUE on ARAMB36_INTERNAL instance." + severity failure; + end if; + + + if (READ_WIDTH_A = 0 and READ_WIDTH_B = 0) then + assert false + report "Attribute Syntax Error : Attributes READ_WIDTH_A and READ_WIDTH_B on ARAMB36_INTERNAL instance, both can not be 0." + severity failure; + end if; + + + if (WRITE_MODE_A = "WRITE_FIRST") then + wr_mode_a := "00"; + elsif (WRITE_MODE_A = "READ_FIRST") then + wr_mode_a := "01"; + elsif (WRITE_MODE_A = "NO_CHANGE") then + wr_mode_a := "10"; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " WRITE_MODE_A ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + if (WRITE_MODE_B = "WRITE_FIRST") then + wr_mode_b := "00"; + elsif (WRITE_MODE_B = "READ_FIRST") then + wr_mode_b := "01"; + elsif (WRITE_MODE_B = "NO_CHANGE") then + wr_mode_b := "10"; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " WRITE_MODE_B ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + + if (RAM_EXTENSION_A = "UPPER") then + cascade_a <= "11"; + elsif (RAM_EXTENSION_A = "LOWER") then + cascade_a <= "01"; + elsif (RAM_EXTENSION_A= "NONE") then + cascade_a <= "00"; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " RAM_EXTENSION_A ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => RAM_EXTENSION_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " NONE, LOWER or UPPER ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + + if (RAM_EXTENSION_B = "UPPER") then + cascade_b <= "11"; + elsif (RAM_EXTENSION_B = "LOWER") then + cascade_b <= "01"; + elsif (RAM_EXTENSION_B= "NONE") then + cascade_b <= "00"; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " RAM_EXTENSION_B ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => RAM_EXTENSION_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " NONE, LOWER or UPPER ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + + if( ((RAM_EXTENSION_A = "LOWER") or (RAM_EXTENSION_A = "UPPER")) and (READ_WIDTH_A /= 1)) then + assert false + report "Attribute Syntax Error: If RAM_EXTENSION_A is set to either LOWER or UPPER, then READ_WIDTH_A has to be set to 1." + severity Failure; + end if; + + if( ((RAM_EXTENSION_A = "LOWER") or (RAM_EXTENSION_A = "UPPER")) and (WRITE_WIDTH_A /= 1)) then + assert false + report "Attribute Syntax Error: If RAM_EXTENSION_A is set to either LOWER or UPPER, then WRITE_WIDTH_A has to be set to 1." + severity Failure; + end if; + + if( ((RAM_EXTENSION_B = "LOWER") or (RAM_EXTENSION_B = "UPPER")) and (READ_WIDTH_B /= 1)) then + assert false + report "Attribute Syntax Error: If RAM_EXTENSION_B is set to either LOWER or UPPER, then READ_WIDTH_B has to be set to 1." + severity Failure; + end if; + + if( ((RAM_EXTENSION_B = "LOWER") or (RAM_EXTENSION_B = "UPPER")) and (WRITE_WIDTH_B /= 1)) then + assert false + report "Attribute Syntax Error: If RAM_EXTENSION_B is set to either LOWER or UPPER, then WRITE_WIDTH_B has to be set to 1." + severity Failure; + end if; + + + if (not ((SIM_COLLISION_CHECK = "NONE") or (SIM_COLLISION_CHECK = "WARNING_ONLY") or (SIM_COLLISION_CHECK = "GENERATE_X_ONLY") or (SIM_COLLISION_CHECK = "ALL"))) then + GenericValueCheckMessage + (HeaderMsg => "Attribute Syntax Error", + GenericName => "SIM_COLLISION_CHECK", + EntityName => "ARAMB36_INTERNAL", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => "Legal Values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY", + ExpectedGenericValue => "", + TailMsg => "", + MsgSeverity => error + ); + end if; + + end if; + + + if (rising_edge(clka_dly)) then + + if (ena_dly = '1') then + prev_time := curr_time; + curr_time := now; + addra_reg_dly := addra_dly; + wea_reg_dly := wea_dly; + dia_reg_dly := dia_dly; + dipa_reg_dly := dipa_dly; + end if; + + end if; + + if (rising_edge(clkb_dly)) then + + if (enb_dly = '1') then + prev_time := curr_time; + curr_time := now; + addrb_reg_dly := addrb_dly; + web_reg_dly := web_dly; + dib_reg_dly := dib_dly; + dipb_reg_dly := dipb_dly; + end if; + + end if; + + if (gsr_dly = '1' or FIRST_TIME) then + + doa_out(ra_width-1 downto 0) <= INIT_A_STD(ra_width-1 downto 0); + + if (ra_width >= 8) then + dopa_out(ra_widthp-1 downto 0) <= INIT_A_STD((ra_width+ra_widthp)-1 downto ra_width); + end if; + + dob_out(rb_width-1 downto 0) <= INIT_B_STD(rb_width-1 downto 0); + + if (rb_width >= 8) then + dopb_out(rb_widthp-1 downto 0) <= INIT_B_STD((rb_width+rb_widthp)-1 downto rb_width); + end if; + + dbiterr_out <= '0'; + sbiterr_out <= '0'; + + FIRST_TIME := false; + + elsif (gsr_dly = '0') then + + if (rising_edge(clka_dly)) then + if (cascade_a(1) = '1') then + addra_dly_15_reg_bram_var := not addra_dly(15); + else + addra_dly_15_reg_bram_var := addra_dly(15); + end if; + end if; + + if (rising_edge(clkb_dly)) then + if (cascade_b(1) = '1') then + addrb_dly_15_reg_bram_var := not addrb_dly(15); + else + addrb_dly_15_reg_bram_var := addrb_dly(15); + end if; + end if; + + if (rising_edge(clka_dly) or rising_edge(clkb_dly)) then + + if ((cascade_a = "00" or (addra_dly_15_reg_bram_var = '0' and cascade_a /= "00")) or (cascade_b = "00" or (addrb_dly_15_reg_bram_var = '0' and cascade_b /= "00"))) then + +------------------------------------------------------------------------------- +-- Collision starts +------------------------------------------------------------------------------- + + if (SIM_COLLISION_CHECK /= "NONE") then + + + if (curr_time - prev_time = 0 ps) then + viol_time := 1; + elsif (curr_time - prev_time <= SETUP_READ_FIRST) then + viol_time := 2; + end if; + + + if (ena_dly = '0' or enb_dly = '0') then + viol_time := 0; + end if; + + + if ((WRITE_WIDTH_A <= 9 and wea_dly(0) = '0') or (WRITE_WIDTH_A = 18 and wea_dly(1 downto 0) = "00") or ((WRITE_WIDTH_A = 36 or WRITE_WIDTH_A = 72) and wea_dly(3 downto 0) = "0000")) then + if ((WRITE_WIDTH_B <= 9 and web_dly(0) = '0') or (WRITE_WIDTH_B = 18 and web_dly(1 downto 0) = "00") or (WRITE_WIDTH_B = 36 and web_dly(3 downto 0) = "0000") or (WRITE_WIDTH_B = 72 and web_dly(7 downto 0) = "00000000")) then + viol_time := 0; + end if; + end if; + + + if (viol_time /= 0) then +--lool + if (cascade_a(0) = '1' or cascade_b(0) = '1') then + if (addra_dly(15 downto col_addr_lsb) = addrb_dly(15 downto col_addr_lsb)) then + addr_col := '1'; + else + addr_col := '0'; + end if; + else + if (addra_dly(14 downto col_addr_lsb) = addrb_dly(14 downto col_addr_lsb)) then + addr_col := '1'; + else + addr_col := '0'; + end if; + end if; + + + if (rising_edge(clka_dly) and rising_edge(clkb_dly)) then +-- if (addra_dly(15 downto col_addr_lsb) = addrb_dly(15 downto col_addr_lsb)) then + if (addr_col = '1') then + + viol_type := "01"; + + prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp); + prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp); + + prcd_col_wr_ram_a ("00", web_dly, wea_dly, di_x, di_x(7 downto 0), addrb_dly, addra_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + prcd_col_wr_ram_b ("00", wea_dly, web_dly, di_x, di_x(7 downto 0), addra_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + + prcd_col_rd_ram_a (viol_type, "01", web_dly, wea_dly, addra_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a); + prcd_col_rd_ram_b (viol_type, "01", wea_dly, web_dly, addrb_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b); + + prcd_col_wr_ram_a ("10", web_dly, wea_dly, dia_dly, dipa_dly, addrb_dly, addra_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + + if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE and enb_dly = '1') then + + dip_ecc_col := fn_dip_ecc('1', dib_dly, dipb_dly); + eccparity_out <= dip_ecc_col; + prcd_col_wr_ram_b ("10", wea_dly, web_dly, dib_dly, dip_ecc_col, addra_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + + else + + prcd_col_wr_ram_b ("10", wea_dly, web_dly, dib_dly, dipb_dly, addra_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + + end if; + + if (wr_mode_a /= "01") then + prcd_col_rd_ram_a (viol_type, "11", web_dly, wea_dly, addra_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a); + end if; + + if (wr_mode_b /= "01") then + prcd_col_rd_ram_b (viol_type, "11", wea_dly, web_dly, addrb_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b); + end if; + + if (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE) then + prcd_col_ecc_read (doa_buf, dopa_buf, addra_dly, dbiterr_out_var, sbiterr_out_var, mem, memp, syndrome); + end if; + + else + viol_time := 0; + + end if; + + elsif (rising_edge(clka_dly) and (not(rising_edge(clkb_dly)))) then +-- if (addra_dly(15 downto col_addr_lsb) = addrb_dly(15 downto col_addr_lsb)) then + if (addr_col = '1') then + + viol_type := "10"; + + prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp); + + prcd_col_wr_ram_a ("00", web_reg_dly, wea_dly, di_x, di_x(7 downto 0), addrb_reg_dly, addra_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + prcd_col_wr_ram_b ("00", wea_dly, web_reg_dly, di_x, di_x(7 downto 0), addra_dly, addrb_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + + prcd_col_rd_ram_a (viol_type, "01", web_reg_dly, wea_dly, addra_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a); + prcd_col_rd_ram_b (viol_type, "01", wea_dly, web_reg_dly, addrb_reg_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b); + + prcd_col_wr_ram_a ("10", web_reg_dly, wea_dly, dia_dly, dipa_dly, addrb_reg_dly, addra_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + + if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE and enb_dly = '1') then + + dip_ecc_col := fn_dip_ecc('1', dib_reg_dly, dipb_reg_dly); + eccparity_out <= dip_ecc_col; + prcd_col_wr_ram_b ("10", wea_dly, web_reg_dly, dib_reg_dly, dip_ecc_col, addra_dly, addrb_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + + else + + prcd_col_wr_ram_b ("10", wea_dly, web_reg_dly, dib_reg_dly, dipb_reg_dly, addra_dly, addrb_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + + end if; + + if (wr_mode_a /= "01") then + prcd_col_rd_ram_a (viol_type, "11", web_reg_dly, wea_dly, addra_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a); + end if; + + if (wr_mode_b /= "01") then + prcd_col_rd_ram_b (viol_type, "11", wea_dly, web_reg_dly, addrb_reg_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b); + end if; + + if (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE) then + prcd_col_ecc_read (doa_buf, dopa_buf, addra_dly, dbiterr_out_var, sbiterr_out_var, mem, memp, syndrome); + end if; + + else + viol_time := 0; + + end if; + + elsif ((not(rising_edge(clka_dly))) and rising_edge(clkb_dly)) then +-- if (addra_dly(15 downto col_addr_lsb) = addrb_dly(15 downto col_addr_lsb)) then + if (addr_col = '1') then + + viol_type := "11"; + + prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp); + + prcd_col_wr_ram_a ("00", web_dly, wea_reg_dly, di_x, di_x(7 downto 0), addrb_dly, addra_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + prcd_col_wr_ram_b ("00", wea_reg_dly, web_dly, di_x, di_x(7 downto 0), addra_reg_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + + prcd_col_rd_ram_a (viol_type, "01", web_dly, wea_reg_dly, addra_reg_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a); + prcd_col_rd_ram_b (viol_type, "01", wea_reg_dly, web_dly, addrb_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b); + + prcd_col_wr_ram_a ("10", web_dly, wea_reg_dly, dia_reg_dly, dipa_reg_dly, addrb_dly, addra_reg_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + + if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE and enb_dly = '1') then + + dip_ecc_col := fn_dip_ecc('1', dib_dly, dipb_dly); + eccparity_out <= dip_ecc_col; + prcd_col_wr_ram_b ("10", wea_reg_dly, web_dly, dib_dly, dip_ecc_col, addra_reg_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + + else + + prcd_col_wr_ram_b ("10", wea_reg_dly, web_dly, dib_dly, dipb_dly, addra_reg_dly, addrb_dly, mem, memp, col_wr_wr_msg, col_wra_rdb_msg, col_wrb_rda_msg); + + end if; + + if (wr_mode_a /= "01") then + prcd_col_rd_ram_a (viol_type, "11", web_dly, wea_reg_dly, addra_reg_dly, doa_buf, dopa_buf, mem, memp, wr_mode_a); + end if; + + if (wr_mode_b /= "01") then + prcd_col_rd_ram_b (viol_type, "11", wea_reg_dly, web_dly, addrb_dly, dob_buf, dopb_buf, mem, memp, wr_mode_b); + end if; + + if (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE) then + prcd_col_ecc_read (doa_buf, dopa_buf, addra_reg_dly, dbiterr_out_var, sbiterr_out_var, mem, memp, syndrome); + end if; + + else + viol_time := 0; + + end if; + end if; + + if (SIM_COLLISION_CHECK = "WARNING_ONLY") then + viol_time := 0; + end if; + + end if; + end if; +------------------------------------------------------------------------------- +-- end collision +------------------------------------------------------------------------------- + + end if; + +------------------------------------------------------------------------------- +-- Port A +------------------------------------------------------------------------------- + if (rising_edge(clka_dly)) then + + if (ssra_dly = '1' and BRAM_MODE = "ECC") then + assert false + report "DRC Warning : SET/RESET (SSR) is not supported in ECC mode." + severity Warning; + end if; + + if (ssra_dly = '1' and BRAM_SIZE = 16 and DOA_REG = 1) then + assert false + report "DRC Error : SET/RESET (SSR) is not supported when optional output registers are used." + severity Failure; + end if; + + -- registering addra_dly(15) the second time + if (regcea_dly = '1') then + addra_dly_15_reg1 <= addra_dly_15_reg_var; + end if; + + + -- registering addra[15) + if (ena_dly = '1' and (wr_mode_a /= "10" or wea_dly(0) = '0' or ssra_dly = '1')) then + if (cascade_a(1) = '1') then + addra_dly_15_reg_var := not addra_dly(15); + else + addra_dly_15_reg_var := addra_dly(15); + end if; + end if; + + + addra_dly_15_reg <= addra_dly_15_reg_var; + + + if (gsr_dly = '0' and ena_dly = '1' and (cascade_a = "00" or (addra_dly_15_reg_bram_var = '0' and cascade_a /= "00"))) then + + if (ssra_dly = '1' and DOA_REG = 0) then + + doa_buf(ra_width-1 downto 0) := SRVAL_A_STD(ra_width-1 downto 0); + doa_out(ra_width-1 downto 0) <= SRVAL_A_STD(ra_width-1 downto 0); + + if (ra_width >= 8) then + dopa_buf(ra_widthp-1 downto 0) := SRVAL_A_STD((ra_width+ra_widthp)-1 downto ra_width); + dopa_out(ra_widthp-1 downto 0) <= SRVAL_A_STD((ra_width+ra_widthp)-1 downto ra_width); + end if; + + end if; + + if (viol_time = 0) then + -- read for rf + if ((wr_mode_a = "01" and (ssra_dly = '0' or DOA_REG = 1)) or (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE)) then + prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp); + + -- ECC decode -- only port A + if (BRAM_MODE = "ECC" and EN_ECC_READ = TRUE) then + + dopr_ecc := fn_dip_ecc('0', doa_buf, dopa_buf); + + syndrome := dopr_ecc xor dopa_buf; + + if (syndrome /= "00000000") then + + if (syndrome(7) = '1') then -- dectect single bit error + + ecc_bit_position := doa_buf(63 downto 57) & dopa_buf(6) & doa_buf(56 downto 26) & dopa_buf(5) & doa_buf(25 downto 11) & dopa_buf(4) & doa_buf(10 downto 4) & dopa_buf(3) & doa_buf(3 downto 1) & dopa_buf(2) & doa_buf(0) & dopa_buf(1 downto 0) & dopa_buf(7); + + tmp_syndrome_int := SLV_TO_INT(syndrome(6 downto 0)); + ecc_bit_position(tmp_syndrome_int) := not ecc_bit_position(tmp_syndrome_int); -- correct single bit error in the output + + dia_dly_ecc_corrected := ecc_bit_position(71 downto 65) & ecc_bit_position(63 downto 33) & ecc_bit_position(31 downto 17) & ecc_bit_position(15 downto 9) & ecc_bit_position(7 downto 5) & ecc_bit_position(3); -- correct single bit error in the memory + + doa_buf := dia_dly_ecc_corrected; + + dipa_dly_ecc_corrected := ecc_bit_position(0) & ecc_bit_position(64) & ecc_bit_position(32) & ecc_bit_position(16) & ecc_bit_position(8) & ecc_bit_position(4) & ecc_bit_position(2 downto 1); -- correct single bit error in the parity memory + + dopa_buf := dipa_dly_ecc_corrected; + + dbiterr_out_var := '0'; + sbiterr_out_var := '1'; + + elsif (syndrome(7) = '0') then -- double bit error + sbiterr_out_var := '0'; + dbiterr_out_var := '1'; + end if; + else + dbiterr_out_var := '0'; + sbiterr_out_var := '0'; + end if; + + if (ssra_dly = '1') then -- ssra reset + dbiterr_out_var := '0'; + sbiterr_out_var := '0'; + end if; + + end if; + end if; + + + + if (syndrome /= "00000000" and syndrome(7) = '1' and EN_ECC_SCRUB = TRUE) then + prcd_wr_ram_a ("11111111", dia_dly_ecc_corrected, dipa_dly_ecc_corrected, addra_dly, mem, memp, syndrome); + else + prcd_wr_ram_a (wea_dly, dia_dly, dipa_dly, addra_dly, mem, memp, syndrome); + end if; + + + if ((wr_mode_a /= "01" and (ssra_dly = '0' or DOA_REG = 1)) and (not(BRAM_MODE = "ECC" and EN_ECC_READ = TRUE))) then + prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp); + end if; + + + end if; + end if; + end if; + +------------------------------------------------------------------------------- +-- Port B +------------------------------------------------------------------------------- + + if (rising_edge(clkb_dly)) then + + -- DRC + if (ssrb_dly = '1' and BRAM_MODE = "ECC") then + assert false + report "DRC Warning : SET/RESET (SSR) is not supported in ECC mode." + severity Warning; + end if; + + if (ssrb_dly = '1' and BRAM_SIZE = 16 and DOB_REG = 1) then + assert false + report "DRC Error : SET/RESET (SSR) is not supported when optional output registers are used." + severity Failure; + end if; + + + -- registering addrb_dly(15) the second time + if (regceb_dly = '1') then + addrb_dly_15_reg1 <= addrb_dly_15_reg_var; + end if; + + + -- registering addrb(15) + if (enb_dly = '1' and (wr_mode_b /= "10" or web_dly(0) = '0' or ssrb_dly = '1')) then + if (cascade_b(1) = '1') then + addrb_dly_15_reg_var := not addrb_dly(15); + else + addrb_dly_15_reg_var := addrb_dly(15); + end if; + end if; + + + addrb_dly_15_reg <= addrb_dly_15_reg_var; + + if (gsr_dly = '0' and enb_dly = '1' and (cascade_b = "00" or (addrb_dly_15_reg_bram_var = '0' and cascade_b /= "00"))) then + + if (ssrb_dly = '1' and DOB_REG = 0) then + + dob_buf(rb_width-1 downto 0) := SRVAL_B_STD(rb_width-1 downto 0); + dob_out(rb_width-1 downto 0) <= SRVAL_B_STD(rb_width-1 downto 0); + + if (rb_width >= 8) then + dopb_buf(rb_widthp-1 downto 0) := SRVAL_B_STD((rb_width+rb_widthp)-1 downto rb_width); + dopb_out(rb_widthp-1 downto 0) <= SRVAL_B_STD((rb_width+rb_widthp)-1 downto rb_width); + end if; + + end if; + + dip_ecc := fn_dip_ecc('1', dib_dly, dipb_dly); + + eccparity_out <= dip_ecc; + + if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE) then + dipb_dly_ecc := dip_ecc; + else + dipb_dly_ecc := dipb_dly; + end if; + + + if (viol_time = 0) then + + if (wr_mode_b = "01" and (ssrb_dly = '0' or DOB_REG = 1)) then + prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp); + end if; + + if (BRAM_MODE = "ECC" and EN_ECC_WRITE = TRUE) then + prcd_wr_ram_b (web_dly, dib_dly, dipb_dly_ecc, addrb_dly, mem, memp); + else + prcd_wr_ram_b (web_dly, dib_dly, dipb_dly, addrb_dly, mem, memp); + end if; + + + if (wr_mode_b /= "01" and (ssrb_dly = '0' or DOB_REG = 1)) then + prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp); + end if; + + end if; + end if; + end if; + + + if (ena_dly = '1' and (rising_edge(clka_dly) or viol_time /= 0)) then + if ((ssra_dly = '0' or DOA_REG = 1) and (wr_mode_a /= "10" or (WRITE_WIDTH_A <= 9 and wea_dly(0) = '0') or (WRITE_WIDTH_A = 18 and wea_dly(1 downto 0) = "00") or ((WRITE_WIDTH_A = 36 or WRITE_WIDTH_A = 72) and wea_dly(3 downto 0) = "0000"))) then + + -- Virtex4 feature + if (wr_mode_a = "00" and BRAM_SIZE = 16) then + + if ((WRITE_WIDTH_A = 18 and not(wea_dly(1 downto 0) = "00" or wea_dly(1 downto 0) = "11")) or (WRITE_WIDTH_A = 36 and not(wea_dly(3 downto 0) = "0000" or wea_dly(3 downto 0) = "1111"))) then + + if (WRITE_WIDTH_A /= READ_WIDTH_A) then + + doa_buf(ra_width-1 downto 0) := di_x(ra_width-1 downto 0); + + if (READ_WIDTH_A >= 9) then + dopa_buf(ra_widthp-1 downto 0) := di_x(ra_widthp-1 downto 0); + + end if; + + if (READ_WIDTH_A /= 0) then + + Write ( Message, STRING'(" Functional warning at simulation time ")); + Write ( Message, STRING'("( ")); + Write ( Message, now); + Write ( Message, STRING'(") : ")); + Write ( Message, STRING'("ARAMB36_INTERNAL ")); + Write ( Message, STRING'("( ")); + Write ( Message, STRING'(ARAMB36_INTERNAL'path_name)); + Write ( Message, STRING'(") ")); + Write ( Message, STRING'(" port A is in WRITE_FIRST mode with parameter WRITE_WIDTH_A = ")); + Write ( Message, INTEGER'(WRITE_WIDTH_A)); + Write ( Message, STRING'(", which is different from READ_WIDTH_A = ")); + Write ( Message, INTEGER'(READ_WIDTH_A)); + Write ( Message, STRING'(". The write will be successful however the read value of all bits on port A")); + Write ( Message, STRING'(" is unknown until the next CLKA cycle and all bits of WEA is set to all 1s or 0s. ")); + Write ( Message, LF ); + ASSERT FALSE REPORT Message.ALL SEVERITY warning; + DEALLOCATE (Message); + + end if; + + elsif (WRITE_WIDTH_A = 18) then + + for i in 0 to 1 loop + + if (wea_dly(i) = '0') then + doa_buf(((8*(i+1))-1) downto 8*i) := di_x(((8*(i+1))-1) downto 8*i); + dopa_buf(i downto i) := di_x(i downto i); + end if; + + end loop; + + if (READ_WIDTH_A /= 0) then + + Write ( Message, STRING'(" Functional warning at simulation time ")); + Write ( Message, STRING'("( ")); + Write ( Message, now); + Write ( Message, STRING'(") : ")); + Write ( Message, STRING'("ARAMB36_INTERNAL ")); + Write ( Message, STRING'("( ")); + Write ( Message, STRING'(ARAMB36_INTERNAL'path_name)); + Write ( Message, STRING'(") ")); + Write ( Message, STRING'(" port A is in WRITE_FIRST mode. The write will be successful,")); + Write ( Message, STRING'(" however DOA shows only the enabled newly written byte(s).")); + Write ( Message, STRING'(" The other byte values on DOA are unknown until the next CLKA cycle and")); + Write ( Message, STRING'(" all bits of WEA is set to all 1s or 0s. ")); + Write ( Message, LF ); + ASSERT FALSE REPORT Message.ALL SEVERITY warning; + DEALLOCATE (Message); + + end if; + + elsif (WRITE_WIDTH_A = 36) then + + for i in 0 to 3 loop + + if (wea_dly(i) = '0') then + doa_buf(((8*(i+1))-1) downto 8*i) := di_x(((8*(i+1))-1) downto 8*i); + dopa_buf(i downto i) := di_x(i downto i); + end if; + + end loop; + + if (READ_WIDTH_A /= 0) then + + Write ( Message, STRING'(" Functional warning at simulation time ")); + Write ( Message, STRING'("( ")); + Write ( Message, now); + Write ( Message, STRING'(") : ")); + Write ( Message, STRING'("ARAMB36_INTERNAL ")); + Write ( Message, STRING'("( ")); + Write ( Message, STRING'(ARAMB36_INTERNAL'path_name)); + Write ( Message, STRING'(") ")); + Write ( Message, STRING'(" port A is in WRITE_FIRST mode. The write will be successful,")); + Write ( Message, STRING'(" however DOA shows only the enabled newly written byte(s).")); + Write ( Message, STRING'(" The other byte values on DOA are unknown until the next CLKA cycle and")); + Write ( Message, STRING'(" all bits of WEA is set to all 1s or 0s. ")); + Write ( Message, LF ); + ASSERT FALSE REPORT Message.ALL SEVERITY warning; + DEALLOCATE (Message); + + end if; + + end if; + + end if; + end if; + + doa_out <= doa_buf; + dopa_out <= dopa_buf; + end if; + end if; + + if (enb_dly = '1' and (rising_edge(clkb_dly) or viol_time /= 0)) then + if ((ssrb_dly = '0' or DOB_REG = 1) and (wr_mode_b /= "10" or (WRITE_WIDTH_B <= 9 and web_dly(0) = '0') or (WRITE_WIDTH_B = 18 and web_dly(1 downto 0) = "00") or (WRITE_WIDTH_B = 36 and web_dly(3 downto 0) = "0000") or (WRITE_WIDTH_B = 72 and web_dly(7 downto 0) = "00000000"))) then + + -- Virtex4 feature + if (wr_mode_b = "00" and BRAM_SIZE = 16) then + + if ((WRITE_WIDTH_B = 18 and not(web_dly(1 downto 0) = "00" or web_dly(1 downto 0) = "11")) or (WRITE_WIDTH_B = 36 and not(web_dly(3 downto 0) = "0000" or web_dly(3 downto 0) = "1111"))) then + + if (WRITE_WIDTH_B /= READ_WIDTH_B) then + + dob_buf(rb_width-1 downto 0) := di_x(rb_width-1 downto 0); + + if (READ_WIDTH_B >= 9) then + dopb_buf(rb_widthp-1 downto 0) := di_x(rb_widthp-1 downto 0); + + end if; + + if (READ_WIDTH_B /= 0) then + + Write ( Message, STRING'(" Functional warning at simulation time ")); + Write ( Message, STRING'("( ")); + Write ( Message, now); + Write ( Message, STRING'(") : ")); + Write ( Message, STRING'("ARAMB36_INTERNAL ")); + Write ( Message, STRING'("( ")); + Write ( Message, STRING'(ARAMB36_INTERNAL'path_name)); + Write ( Message, STRING'(") ")); + Write ( Message, STRING'(" port B is in WRITE_FIRST mode with parameter WRITE_WIDTH_B = ")); + Write ( Message, INTEGER'(WRITE_WIDTH_B)); + Write ( Message, STRING'(", which is different from READ_WIDTH_B = ")); + Write ( Message, INTEGER'(READ_WIDTH_B)); + Write ( Message, STRING'(". The write will be successful however the read value of all bits on port B")); + Write ( Message, STRING'(" is unknown until the next CLKB cycle and all bits of WEB is set to all 1s or 0s. ")); + Write ( Message, LF ); + ASSERT FALSE REPORT Message.ALL SEVERITY warning; + DEALLOCATE (Message); + + end if; + + elsif (WRITE_WIDTH_B = 18) then + + for i in 0 to 1 loop + + if (web_dly(i) = '0') then + dob_buf(((8*(i+1))-1) downto 8*i) := di_x(((8*(i+1))-1) downto 8*i); + dopb_buf(i downto i) := di_x(i downto i); + end if; + + end loop; + + if (READ_WIDTH_B /= 0) then + + Write ( Message, STRING'(" Functional warning at simulation time ")); + Write ( Message, STRING'("( ")); + Write ( Message, now); + Write ( Message, STRING'(") : ")); + Write ( Message, STRING'("ARAMB36_INTERNAL ")); + Write ( Message, STRING'("( ")); + Write ( Message, STRING'(ARAMB36_INTERNAL'path_name)); + Write ( Message, STRING'(") ")); + Write ( Message, STRING'(" port B is in WRITE_FIRST mode. The write will be successful,")); + Write ( Message, STRING'(" however DOB shows only the enabled newly written byte(s).")); + Write ( Message, STRING'(" The other byte values on DOB are unknown until the next CLKB cycle and")); + Write ( Message, STRING'(" all bits of WEB is set to all 1s or 0s. ")); + Write ( Message, LF ); + ASSERT FALSE REPORT Message.ALL SEVERITY warning; + DEALLOCATE (Message); + + end if; + + elsif (WRITE_WIDTH_B = 36) then + + for i in 0 to 3 loop + + if (web_dly(i) = '0') then + dob_buf(((8*(i+1))-1) downto 8*i) := di_x(((8*(i+1))-1) downto 8*i); + dopb_buf(i downto i) := di_x(i downto i); + end if; + + end loop; + + if (READ_WIDTH_B /= 0) then + + Write ( Message, STRING'(" Functional warning at simulation time ")); + Write ( Message, STRING'("( ")); + Write ( Message, now); + Write ( Message, STRING'(") : ")); + Write ( Message, STRING'("ARAMB36_INTERNAL ")); + Write ( Message, STRING'("( ")); + Write ( Message, STRING'(ARAMB36_INTERNAL'path_name)); + Write ( Message, STRING'(") ")); + Write ( Message, STRING'(" port B is in WRITE_FIRST mode. The write will be successful,")); + Write ( Message, STRING'(" however DOB shows only the enabled newly written byte(s).")); + Write ( Message, STRING'(" The other byte values on DOB are unknown until the next CLKB cycle and")); + Write ( Message, STRING'(" all bits of WEB is set to all 1s or 0s. ")); + Write ( Message, LF ); + ASSERT FALSE REPORT Message.ALL SEVERITY warning; + DEALLOCATE (Message); + + end if; + + end if; + + end if; + end if; + + dob_out <= dob_buf; + dopb_out <= dopb_buf; + end if; + end if; + + viol_time := 0; + viol_type := "00"; + col_wr_wr_msg := '1'; + col_wra_rdb_msg := '1'; + col_wrb_rda_msg := '1'; + dbiterr_out <= dbiterr_out_var; + sbiterr_out <= sbiterr_out_var; + + end if; + end if; + + end process prcs_clk; + + + outreg_clka: process (regclka_dly, gsr_dly) + variable FIRST_TIME : boolean := true; + + begin -- process outreg_clka + + if (rising_edge(regclka_dly) or rising_edge(gsr_dly) or FIRST_TIME) then + + if (DOA_REG = 1) then + + if (gsr_dly = '1' or FIRST_TIME) then + + dbiterr_outreg <= '0'; + sbiterr_outreg <= '0'; + + doa_outreg(ra_width-1 downto 0) <= INIT_A_STD(ra_width-1 downto 0); + + if (ra_width >= 8) then + dopa_outreg(ra_widthp-1 downto 0) <= INIT_A_STD((ra_width+ra_widthp)-1 downto ra_width); + end if; + + FIRST_TIME := false; + + elsif (gsr_dly = '0') then + + dbiterr_outreg <= dbiterr_out; + sbiterr_outreg <= sbiterr_out; + + if (regcea_dly = '1') then + if (ssra_dly = '1') then + + doa_outreg(ra_width-1 downto 0) <= SRVAL_A_STD(ra_width-1 downto 0); + + if (ra_width >= 8) then + dopa_outreg(ra_widthp-1 downto 0) <= SRVAL_A_STD((ra_width+ra_widthp)-1 downto ra_width); + end if; + + elsif (ssra_dly = '0') then + + doa_outreg <= doa_out; + dopa_outreg <= dopa_out; + + end if; + end if; + end if; + end if; + + end if; + end process outreg_clka; + + + cascade_a_mux: process (clka_dly, cascadeinlata_dly, addra_dly_15_reg, doa_out, dopa_out) + begin -- process cascade_a_mux + + if (rising_edge(clka_dly) or cascadeinlata_dly'event or addra_dly_15_reg'event or doa_out'event or dopa_out'event) then + if (cascade_a(1) = '1' and addra_dly_15_reg = '1') then + doa_out_mux(0) <= cascadeinlata_dly; + else + doa_out_mux <= doa_out; + dopa_out_mux <= dopa_out; + end if; + end if; + + end process cascade_a_mux; + + cascade_a_muxreg: process (regclka_dly, cascadeinrega_dly, addra_dly_15_reg1, doa_outreg, dopa_outreg) + begin -- process cascade_a_muxreg + + if (rising_edge(regclka_dly) or cascadeinrega_dly'event or addra_dly_15_reg1'event or doa_outreg'event or dopa_outreg'event) then + if (cascade_a(1) = '1' and addra_dly_15_reg1 = '1') then + doa_outreg_mux(0) <= cascadeinrega_dly; + else + doa_outreg_mux <= doa_outreg; + dopa_outreg_mux <= dopa_outreg; + end if; + end if; + + end process cascade_a_muxreg; + + + outmux_clka: process (doa_out_mux, dopa_out_mux, doa_outreg_mux, dopa_outreg_mux, dbiterr_out, dbiterr_outreg, sbiterr_out, sbiterr_outreg) + begin -- process outmux_clka + + case DOA_REG is + when 0 => + dbiterr_out_out <= dbiterr_out; + sbiterr_out_out <= sbiterr_out; + doa_out_out <= doa_out_mux; + dopa_out_out <= dopa_out_mux; + when 1 => + dbiterr_out_out <= dbiterr_outreg; + sbiterr_out_out <= sbiterr_outreg; + doa_out_out <= doa_outreg_mux; + dopa_out_out <= dopa_outreg_mux; + when others => assert false + report "Attribute Syntax Error: The allowed integer values for DOA_REG are 0 or 1." + severity Failure; + end case; + + end process outmux_clka; + + + outreg_clkb: process (regclkb_dly, gsr_dly) + variable FIRST_TIME : boolean := true; + + begin -- process outreg_clkb + + if (rising_edge(regclkb_dly) or rising_edge(gsr_dly) or FIRST_TIME) then + + if (DOB_REG = 1) then + + if (gsr_dly = '1' or FIRST_TIME) then + dob_outreg(rb_width-1 downto 0) <= INIT_B_STD(rb_width-1 downto 0); + + if (rb_width >= 8) then + dopb_outreg(rb_widthp-1 downto 0) <= INIT_B_STD((rb_width+rb_widthp)-1 downto rb_width); + end if; + + FIRST_TIME := false; + + elsif (gsr_dly = '0') then + + if (regceb_dly = '1') then + if (ssrb_dly = '1') then + + dob_outreg(rb_width-1 downto 0) <= SRVAL_B_STD(rb_width-1 downto 0); + + if (rb_width >= 8) then + dopb_outreg(rb_widthp-1 downto 0) <= SRVAL_B_STD((rb_width+rb_widthp)-1 downto rb_width); + end if; + + elsif (ssrb_dly = '0') then + + dob_outreg <= dob_out; + dopb_outreg <= dopb_out; + + end if; + end if; + end if; + end if; + + end if; + end process outreg_clkb; + + + cascade_b_mux: process (clkb_dly, cascadeinlatb_dly, addrb_dly_15_reg, dob_out, dopb_out) + begin -- process cascade_b_mux + + if (rising_edge(clkb_dly) or cascadeinlatb_dly'event or addrb_dly_15_reg'event or dob_out'event or dopb_out'event) then + if (cascade_b(1) = '1' and addrb_dly_15_reg = '1') then + dob_out_mux(0) <= cascadeinlatb_dly; + else + dob_out_mux <= dob_out; + dopb_out_mux <= dopb_out; + end if; + end if; + + end process cascade_b_mux; + + cascade_b_muxreg: process (regclkb_dly, cascadeinregb_dly, addrb_dly_15_reg1, dob_outreg, dopb_outreg) + begin -- process cascade_b_muxreg + + if (rising_edge(regclkb_dly) or cascadeinregb_dly'event or addrb_dly_15_reg1'event or dob_outreg'event or dopb_outreg'event) then + if (cascade_b(1) = '1' and addrb_dly_15_reg1 = '1') then + dob_outreg_mux(0) <= cascadeinregb_dly; + else + dob_outreg_mux <= dob_outreg; + dopb_outreg_mux <= dopb_outreg; + end if; + end if; + + end process cascade_b_muxreg; + + + outmux_clkb: process (dob_out_mux, dopb_out_mux, dob_outreg_mux, dopb_outreg_mux) + begin -- process outmux_clkb + + case DOB_REG is + when 0 => + dob_out_out <= dob_out_mux; + dopb_out_out <= dopb_out_mux; + when 1 => + dob_out_out <= dob_outreg_mux; + dopb_out_out <= dopb_outreg_mux; + when others => assert false + report "Attribute Syntax Error: The allowed integer values for DOB_REG are 0 or 1." + severity Failure; + end case; + + end process outmux_clkb; + + + end generate; + +------------------------------------------------------------------------------- +-- FAST mode +------------------------------------------------------------------------------- + + fast_mode : if (SIM_MODE = "FAST") generate + + + prcs_clk: process (clka_dly, clkb_dly, gsr_dly) + + variable mem_slv : std_logic_vector(32767 downto 0) := To_StdLogicVector(INIT_7F) & + To_StdLogicVector(INIT_7E) & + To_StdLogicVector(INIT_7D) & + To_StdLogicVector(INIT_7C) & + To_StdLogicVector(INIT_7B) & + To_StdLogicVector(INIT_7A) & + To_StdLogicVector(INIT_79) & + To_StdLogicVector(INIT_78) & + To_StdLogicVector(INIT_77) & + To_StdLogicVector(INIT_76) & + To_StdLogicVector(INIT_75) & + To_StdLogicVector(INIT_74) & + To_StdLogicVector(INIT_73) & + To_StdLogicVector(INIT_72) & + To_StdLogicVector(INIT_71) & + To_StdLogicVector(INIT_70) & + To_StdLogicVector(INIT_6F) & + To_StdLogicVector(INIT_6E) & + To_StdLogicVector(INIT_6D) & + To_StdLogicVector(INIT_6C) & + To_StdLogicVector(INIT_6B) & + To_StdLogicVector(INIT_6A) & + To_StdLogicVector(INIT_69) & + To_StdLogicVector(INIT_68) & + To_StdLogicVector(INIT_67) & + To_StdLogicVector(INIT_66) & + To_StdLogicVector(INIT_65) & + To_StdLogicVector(INIT_64) & + To_StdLogicVector(INIT_63) & + To_StdLogicVector(INIT_62) & + To_StdLogicVector(INIT_61) & + To_StdLogicVector(INIT_60) & + To_StdLogicVector(INIT_5F) & + To_StdLogicVector(INIT_5E) & + To_StdLogicVector(INIT_5D) & + To_StdLogicVector(INIT_5C) & + To_StdLogicVector(INIT_5B) & + To_StdLogicVector(INIT_5A) & + To_StdLogicVector(INIT_59) & + To_StdLogicVector(INIT_58) & + To_StdLogicVector(INIT_57) & + To_StdLogicVector(INIT_56) & + To_StdLogicVector(INIT_55) & + To_StdLogicVector(INIT_54) & + To_StdLogicVector(INIT_53) & + To_StdLogicVector(INIT_52) & + To_StdLogicVector(INIT_51) & + To_StdLogicVector(INIT_50) & + To_StdLogicVector(INIT_4F) & + To_StdLogicVector(INIT_4E) & + To_StdLogicVector(INIT_4D) & + To_StdLogicVector(INIT_4C) & + To_StdLogicVector(INIT_4B) & + To_StdLogicVector(INIT_4A) & + To_StdLogicVector(INIT_49) & + To_StdLogicVector(INIT_48) & + To_StdLogicVector(INIT_47) & + To_StdLogicVector(INIT_46) & + To_StdLogicVector(INIT_45) & + To_StdLogicVector(INIT_44) & + To_StdLogicVector(INIT_43) & + To_StdLogicVector(INIT_42) & + To_StdLogicVector(INIT_41) & + To_StdLogicVector(INIT_40) & + To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00); + + variable memp_slv : std_logic_vector(4095 downto 0) := To_StdLogicVector(INITP_0F) & + To_StdLogicVector(INITP_0E) & + To_StdLogicVector(INITP_0D) & + To_StdLogicVector(INITP_0C) & + To_StdLogicVector(INITP_0B) & + To_StdLogicVector(INITP_0A) & + To_StdLogicVector(INITP_09) & + To_StdLogicVector(INITP_08) & + To_StdLogicVector(INITP_07) & + To_StdLogicVector(INITP_06) & + To_StdLogicVector(INITP_05) & + To_StdLogicVector(INITP_04) & + To_StdLogicVector(INITP_03) & + To_StdLogicVector(INITP_02) & + To_StdLogicVector(INITP_01) & + To_StdLogicVector(INITP_00); + + variable tmp_mem : Two_D_array_type_tmp_mem := two_D_mem_initf(widest_width); + variable mem : Two_D_array_type := two_D_mem_init(mem_depth, width, mem_slv, tmp_mem); + variable memp : Two_D_parity_array_type := two_D_mem_initp(memp_depth, widthp, memp_slv, tmp_mem, width); + variable tmp_addra_dly_depth : integer; + variable tmp_addra_dly_width : integer; + variable tmp_addrb_dly_depth : integer; + variable tmp_addrb_dly_width : integer; + variable junk1 : std_logic; + variable wr_mode_a : std_logic_vector(1 downto 0) := "00"; + variable wr_mode_b : std_logic_vector(1 downto 0) := "00"; + variable tmp_syndrome_int : integer; + variable doa_buf : std_logic_vector(63 downto 0) := (others => '0'); + variable dob_buf : std_logic_vector(63 downto 0) := (others => '0'); + variable dopa_buf : std_logic_vector(7 downto 0) := (others => '0'); + variable dopb_buf : std_logic_vector(7 downto 0) := (others => '0'); + variable syndrome : std_logic_vector(7 downto 0) := (others => '0'); + variable dopr_ecc : std_logic_vector(7 downto 0) := (others => '0'); + variable dia_dly_ecc_corrected : std_logic_vector(63 downto 0) := (others => '0'); + variable dipa_dly_ecc_corrected : std_logic_vector(7 downto 0) := (others => '0'); + variable dip_ecc : std_logic_vector(7 downto 0) := (others => '0'); + variable dipb_dly_ecc : std_logic_vector(7 downto 0) := (others => '0'); + variable ecc_bit_position : std_logic_vector(71 downto 0) := (others => '0'); + variable addra_dly_15_reg_var : std_logic := '0'; + variable addrb_dly_15_reg_var : std_logic := '0'; + variable addra_dly_15_reg_bram_var : std_logic := '0'; + variable addrb_dly_15_reg_bram_var : std_logic := '0'; + variable FIRST_TIME : boolean := true; + + variable curr_time : time := 0 ps; + variable prev_time : time := 0 ps; + variable viol_time : integer := 0; + variable viol_type : std_logic_vector(1 downto 0) := (others => '0'); + variable message : line; + variable dip_ecc_col : std_logic_vector (7 downto 0) := (others => '0'); + variable dbiterr_out_var : std_ulogic := '0'; + variable sbiterr_out_var : std_ulogic := '0'; + + variable dia_reg_dly : std_logic_vector(63 downto 0) := (others => '0'); + variable dipa_reg_dly : std_logic_vector(7 downto 0) := (others => '0'); + variable wea_reg_dly : std_logic_vector(7 downto 0) := (others => '0'); + variable addra_reg_dly : std_logic_vector(15 downto 0) := (others => '0'); + variable dib_reg_dly : std_logic_vector(63 downto 0) := (others => '0'); + variable dipb_reg_dly : std_logic_vector(7 downto 0) := (others => '0'); + variable web_reg_dly : std_logic_vector(7 downto 0) := (others => '0'); + variable addrb_reg_dly : std_logic_vector(15 downto 0) := (others => '0'); + variable col_wr_wr_msg : std_ulogic := '1'; + variable col_wra_rdb_msg : std_ulogic := '1'; + variable col_wrb_rda_msg : std_ulogic := '1'; + + + begin -- process prcs_clka + + + if (FIRST_TIME) then + + + if (SIM_MODE /= "FAST" and SIM_MODE /= "SAFE") then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " SIM_MODE ", + EntityName => "ARAMB36_INTERNAL", + GenericValue => SIM_MODE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " FAST or SAFE ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + + if (WRITE_MODE_A = "WRITE_FIRST") then + wr_mode_a := "00"; + elsif (WRITE_MODE_A = "READ_FIRST") then + wr_mode_a := "01"; + elsif (WRITE_MODE_A = "NO_CHANGE") then + wr_mode_a := "10"; + end if; + + if (WRITE_MODE_B = "WRITE_FIRST") then + wr_mode_b := "00"; + elsif (WRITE_MODE_B = "READ_FIRST") then + wr_mode_b := "01"; + elsif (WRITE_MODE_B = "NO_CHANGE") then + wr_mode_b := "10"; + end if; + + end if; + + + if (gsr_dly = '1' or FIRST_TIME) then + + doa_out(ra_width-1 downto 0) <= INIT_A_STD(ra_width-1 downto 0); + + if (ra_width >= 8) then + dopa_out(ra_widthp-1 downto 0) <= INIT_A_STD((ra_width+ra_widthp)-1 downto ra_width); + end if; + + dob_out(rb_width-1 downto 0) <= INIT_B_STD(rb_width-1 downto 0); + + if (rb_width >= 8) then + dopb_out(rb_widthp-1 downto 0) <= INIT_B_STD((rb_width+rb_widthp)-1 downto rb_width); + end if; + + dbiterr_out <= '0'; + sbiterr_out <= '0'; + + FIRST_TIME := false; + + end if; + +------------------------------------------------------------------------------- +-- Port A +------------------------------------------------------------------------------- + if (rising_edge(clka_dly)) then + + if (gsr_dly = '0' and ena_dly = '1') then + + if (ssra_dly = '1' and DOA_REG = 0) then + + doa_buf(ra_width-1 downto 0) := SRVAL_A_STD(ra_width-1 downto 0); + doa_out(ra_width-1 downto 0) <= SRVAL_A_STD(ra_width-1 downto 0); + + if (ra_width >= 8) then + dopa_buf(ra_widthp-1 downto 0) := SRVAL_A_STD((ra_width+ra_widthp)-1 downto ra_width); + dopa_out(ra_widthp-1 downto 0) <= SRVAL_A_STD((ra_width+ra_widthp)-1 downto ra_width); + end if; + + end if; + + -- read for rf + if ((wr_mode_a = "01" and (ssra_dly = '0' or DOA_REG = 1))) then + prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp); + end if; + + + prcd_wr_ram_a (wea_dly, dia_dly, dipa_dly, addra_dly, mem, memp, syndrome); + + + if ((wr_mode_a /= "01" and (ssra_dly = '0' or DOA_REG = 1))) then + prcd_rd_ram_a (addra_dly, doa_buf, dopa_buf, mem, memp); + end if; + + + if ((ssra_dly = '0' or DOA_REG = 1) and (wr_mode_a /= "10" or (WRITE_WIDTH_A <= 9 and wea_dly(0) = '0') or (WRITE_WIDTH_A = 18 and wea_dly(1 downto 0) = "00") or ((WRITE_WIDTH_A = 36 or WRITE_WIDTH_A = 72) and wea_dly(3 downto 0) = "0000"))) then + + doa_out <= doa_buf; + dopa_out <= dopa_buf; + + end if; + + end if; + end if; + + +------------------------------------------------------------------------------- +-- Port B +------------------------------------------------------------------------------- + + if (rising_edge(clkb_dly)) then + + + if (gsr_dly = '0' and enb_dly = '1') then + + if (ssrb_dly = '1' and DOB_REG = 0) then + + dob_buf(rb_width-1 downto 0) := SRVAL_B_STD(rb_width-1 downto 0); + dob_out(rb_width-1 downto 0) <= SRVAL_B_STD(rb_width-1 downto 0); + + if (rb_width >= 8) then + dopb_buf(rb_widthp-1 downto 0) := SRVAL_B_STD((rb_width+rb_widthp)-1 downto rb_width); + dopb_out(rb_widthp-1 downto 0) <= SRVAL_B_STD((rb_width+rb_widthp)-1 downto rb_width); + end if; + + end if; + + + if (wr_mode_b = "01" and (ssrb_dly = '0' or DOB_REG = 1)) then + prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp); + end if; + + prcd_wr_ram_b (web_dly, dib_dly, dipb_dly, addrb_dly, mem, memp); + + if (wr_mode_b /= "01" and (ssrb_dly = '0' or DOB_REG = 1)) then + prcd_rd_ram_b (addrb_dly, dob_buf, dopb_buf, mem, memp); + end if; + + + if ((ssrb_dly = '0' or DOB_REG = 1) and (wr_mode_b /= "10" or (WRITE_WIDTH_B <= 9 and web_dly(0) = '0') or (WRITE_WIDTH_B = 18 and web_dly(1 downto 0) = "00") or (WRITE_WIDTH_B = 36 and web_dly(3 downto 0) = "0000") or (WRITE_WIDTH_B = 72 and web_dly(7 downto 0) = "00000000"))) then + + dob_out <= dob_buf; + dopb_out <= dopb_buf; + end if; + + end if; + end if; + + end process prcs_clk; + + + outreg_clka: process (regclka_dly, gsr_dly) + variable FIRST_TIME : boolean := true; + + begin -- process outreg_clka + + if (rising_edge(regclka_dly) or rising_edge(gsr_dly) or FIRST_TIME) then + + if (DOA_REG = 1) then + + if (gsr_dly = '1' or FIRST_TIME) then + + dbiterr_outreg <= '0'; + sbiterr_outreg <= '0'; + + doa_outreg(ra_width-1 downto 0) <= INIT_A_STD(ra_width-1 downto 0); + + if (ra_width >= 8) then + dopa_outreg(ra_widthp-1 downto 0) <= INIT_A_STD((ra_width+ra_widthp)-1 downto ra_width); + end if; + + FIRST_TIME := false; + + elsif (gsr_dly = '0') then + + if (regcea_dly = '1') then + if (ssra_dly = '1') then + + doa_outreg(ra_width-1 downto 0) <= SRVAL_A_STD(ra_width-1 downto 0); + + if (ra_width >= 8) then + dopa_outreg(ra_widthp-1 downto 0) <= SRVAL_A_STD((ra_width+ra_widthp)-1 downto ra_width); + end if; + + elsif (ssra_dly = '0') then + + doa_outreg <= doa_out; + dopa_outreg <= dopa_out; + + end if; + end if; + end if; + end if; + + end if; + end process outreg_clka; + + + outmux_clka: process (doa_out, dopa_out, doa_outreg, dopa_outreg) + begin -- process outmux_clka + + case DOA_REG is + when 0 => + doa_out_out <= doa_out; + dopa_out_out <= dopa_out; + when 1 => + doa_out_out <= doa_outreg_mux; + dopa_out_out <= dopa_outreg_mux; + when others => + end case; + + end process outmux_clka; + + + outreg_clkb: process (regclkb_dly, gsr_dly) + variable FIRST_TIME : boolean := true; + + begin -- process outreg_clkb + + if (rising_edge(regclkb_dly) or rising_edge(gsr_dly) or FIRST_TIME) then + + if (DOB_REG = 1) then + + if (gsr_dly = '1' or FIRST_TIME) then + dob_outreg(rb_width-1 downto 0) <= INIT_B_STD(rb_width-1 downto 0); + + if (rb_width >= 8) then + dopb_outreg(rb_widthp-1 downto 0) <= INIT_B_STD((rb_width+rb_widthp)-1 downto rb_width); + end if; + + FIRST_TIME := false; + + elsif (gsr_dly = '0') then + + if (regceb_dly = '1') then + if (ssrb_dly = '1') then + + dob_outreg(rb_width-1 downto 0) <= SRVAL_B_STD(rb_width-1 downto 0); + + if (rb_width >= 8) then + dopb_outreg(rb_widthp-1 downto 0) <= SRVAL_B_STD((rb_width+rb_widthp)-1 downto rb_width); + end if; + + elsif (ssrb_dly = '0') then + + dob_outreg <= dob_out; + dopb_outreg <= dopb_out; + + end if; + end if; + end if; + end if; + + end if; + end process outreg_clkb; + + + outmux_clkb: process (dob_out, dopb_out, dob_outreg, dopb_outreg) + begin -- process outmux_clkb + + case DOB_REG is + when 0 => + dob_out_out <= dob_out; + dopb_out_out <= dopb_out; + when 1 => + dob_out_out <= dob_outreg; + dopb_out_out <= dopb_outreg; + when others => + end case; + + end process outmux_clkb; + + + end generate; + + +------------------------------------------------------------------------------- +-- Output +------------------------------------------------------------------------------- + + prcs_output: process (doa_out_out, dopa_out_out, dob_out_out, dopb_out_out, eccparity_out, + dbiterr_out_out, sbiterr_out_out, doa_out_mux(0), dob_out_mux(0), + doa_outreg_mux(0), dob_outreg_mux(0)) + begin -- process prcs_output + + DOA <= doa_out_out; + DOPA <= dopa_out_out; + DOB <= dob_out_out; + DOPB <= dopb_out_out; + ECCPARITY <= eccparity_out; + DBITERR <= dbiterr_out_out; + SBITERR <= sbiterr_out_out; + CASCADEOUTLATA <= doa_out_mux(0); + CASCADEOUTLATB <= dob_out_mux(0); + CASCADEOUTREGA <= doa_outreg_mux(0); + CASCADEOUTREGB <= dob_outreg_mux(0); + + end process prcs_output; + + +end ARAMB36_INTERNAL_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Boundary Scan Logic Control Circuit for VIRTEX5 +-- /___/ /\ Filename : BSCAN_VIRTEX5.v +-- \ \ / \ Timestamp : Fri Jun 03 08:17:58 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 06/03/05 - Initial version. + +----- CELL BSCAN_VIRTEX5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.vcomponents.all; +entity BSCAN_VIRTEX5 is + generic( + JTAG_CHAIN : integer := 1 + ); + + port( + CAPTURE : out std_ulogic := 'H'; + DRCK : out std_ulogic := 'H'; + RESET : out std_ulogic := 'H'; + SEL : out std_ulogic := 'L'; + SHIFT : out std_ulogic := 'L'; + TDI : out std_ulogic := 'L'; + UPDATE : out std_ulogic := 'L'; + + TDO : in std_ulogic := 'X' + ); + +end BSCAN_VIRTEX5; + +architecture BSCAN_VIRTEX5_V of BSCAN_VIRTEX5 is + +signal SEL_zd : std_ulogic := '0'; +signal UPDATE_zd : std_ulogic := '0'; + +begin + +--#################################################################### +--##### Initialization ### +--#################################################################### + prcs_init:process + begin + if((JTAG_CHAIN /= 1) and (JTAG_CHAIN /= 2) and (JTAG_CHAIN /= 3) + and (JTAG_CHAIN /= 4)) then + assert false + report "Attribute Syntax Error: The allowed values for JTAG_CHAIN are 1, 2, 3 or 4" + severity Failure; + end if; + wait; + end process prcs_init; + +-- synopsys translate_off + +--#################################################################### +--##### jtag_select ### +--#################################################################### + prcs_jtag_select:process (JTAG_SEL1_GLBL, JTAG_SEL2_GLBL, JTAG_SEL3_GLBL, JTAG_SEL4_GLBL) + begin + if(JTAG_CHAIN = 1) then + SEL_zd <= JTAG_SEL1_GLBL; + elsif(JTAG_CHAIN = 2) then + SEL_zd <= JTAG_SEL2_GLBL; + elsif(JTAG_CHAIN = 3) then + SEL_zd <= JTAG_SEL3_GLBL; + elsif(JTAG_CHAIN = 4) then + SEL_zd <= JTAG_SEL4_GLBL; + end if; + + end process prcs_jtag_select; + +--#################################################################### +--##### USER_TDO ### +--#################################################################### + prcs_jtag_UserTDO:process (TDO) + begin + if(JTAG_CHAIN = 1) then + JTAG_USER_TDO1_GLBL <= TDO; + elsif(JTAG_CHAIN = 2) then + JTAG_USER_TDO2_GLBL <= TDO; + elsif(JTAG_CHAIN = 3) then + JTAG_USER_TDO3_GLBL <= TDO; + elsif(JTAG_CHAIN = 4) then + JTAG_USER_TDO4_GLBL <= TDO; + end if; + + end process prcs_jtag_UserTDO; +--#################################################################### + + CAPTURE <= JTAG_CAPTURE_GLBL; + DRCK <= ((SEL_zd and not JTAG_SHIFT_GLBL and not JTAG_CAPTURE_GLBL) or + (SEL_zd and JTAG_SHIFT_GLBL and JTAG_TCK_GLBL) or + (SEL_zd and JTAG_CAPTURE_GLBL and JTAG_TCK_GLBL)); + TDI <= JTAG_TDI_GLBL; + SEL <= SEL_zd; + SHIFT <= JTAG_SHIFT_GLBL; + UPDATE <= JTAG_UPDATE_GLBL; + RESET <= JTAG_RESET_GLBL; + +-- synopsys translate_on + +end BSCAN_VIRTEX5_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/bufgmux_ctrl.vhd,v 1.2 2006/03/11 00:19:54 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Global Clock Mux Buffer +-- /___/ /\ Filename : BUFGMUX_CTRL.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:17:58 PST 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/10/06 - Initial version. +-- end Revision + +----- CELL BUFGMUX_CTRL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_arith.all; + +library unisim; +use unisim.vpkg.all; +use unisim.vcomponents.all; + +entity BUFGMUX_CTRL is + + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + S : in std_ulogic + ); + +end BUFGMUX_CTRL; + + +architecture BUFGMUX_CTRL_V OF BUFGMUX_CTRL is + + + signal SigPullUp : std_ulogic := '1'; + signal SigPullDown : std_ulogic := '0'; + signal NOT_S : std_ulogic := 'X'; + +begin + + NOT_S <= NOT S; + +---------------------------------------------------------------------- +----------- Instant BUFGCTRL ------------------------------------- +---------------------------------------------------------------------- + INST_BUFGCTRL : BUFGCTRL + generic map ( + INIT_OUT => 0, + PRESELECT_I0 => true, + PRESELECT_I1 => false + ) + port map ( + O => O, + + CE0 => SigPullUp, + CE1 => SigPullUp, + I0 => I0, + I1 => I1, + IGNORE0 => SigPullDown, + IGNORE1 => SigPullDown, + S0 => NOT_S, + S1 => S + ); +end BUFGMUX_CTRL_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Register State Capture for Bitstream Readback for VIRTEX5 +-- /___/ /\ Filename : CAPTURE_VIRTEX5.vhd +-- \ \ / \ Timestamp : Thu Jun 2 10:57:03 PDT 2005 +-- \___\/\___\ +-- +-- Revision: +-- 06/03/05 - Initial version. + +----- CELL CAPTURE_VIRTEX5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CAPTURE_VIRTEX5 is + generic( + ONESHOT : boolean := true + ); + port( + CAP : in std_ulogic; + CLK : in std_ulogic + ); + +end CAPTURE_VIRTEX5; + +architecture CAPTURE_VIRTEX5_V of CAPTURE_VIRTEX5 is + +begin +end CAPTURE_VIRTEX5_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Function Simulation Library Component +-- / / Fast Carry Logic with Look Ahead +-- /___/ /\ Filename : CARRY4.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:18:19 PST 2004 +-- \___\/\___\ +-- Revision: +-- 04/11/05 - Initial version. +-- 05/06/05 - Unused CYINT or CI pin need grounded instead of open (CR207752) +-- 05/31/05 - Change pin order, remove connection check for CYINT and CI. +-- End Revision + +----- CELL CARRY4 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CARRY4 is + + port( + CO : out std_logic_vector(3 downto 0); + O : out std_logic_vector(3 downto 0); + + CI : in std_ulogic; + CYINIT : in std_ulogic; + DI : in std_logic_vector(3 downto 0); + S : in std_logic_vector(3 downto 0) + ); + +end CARRY4; + +architecture CARRY4_V OF CARRY4 is + + signal ci_or_cyinit : std_ulogic; + signal CO_out : std_logic_vector(3 downto 0); +begin + + O <= S xor ( CO_out(2 downto 0) & ci_or_cyinit ); + CO <= CO_out; + + CO_out(0) <= ci_or_cyinit when S(0) = '1' else DI(0); + CO_out(1) <= CO_out(0) when S(1) = '1' else DI(1); + CO_out(2) <= CO_out(1) when S(2) = '1' else DI(2); + CO_out(3) <= CO_out(2) when S(3) = '1' else DI(3); + ci_or_cyinit <= CI or CYINIT; + +-- ci_sel : process (CYINIT , CI) +-- begin +-- if(CYINIT = 'U' or CYINIT = 'Z' or CYINIT = 'X') then +-- assert FALSE report +-- "Error : CARRY4 instance detects CYINIT unconnected. Only one of CI and CYINIT inputs can be used and other one need grounded." +-- severity failure; +-- elsif (CI = 'U' or CI = 'Z' or CI = 'X') then +-- assert FALSE report +-- "Error : CARRY4 instance detects CI unconnected. Only one of CI and CYINIT inputs can be used and other one need grounded." +-- severity failure; +-- else +-- ci_or_cyinit <= CI or CYINIT; +-- end if; +-- +-- end process ci_sel; + +end CARRY4_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/cfglut5.vhd,v 1.3 2006/04/21 23:37:23 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input Dynamically Reconfigurable Look-Up-Table with Carry and Clock Enable +-- /___/ /\ Filename : CFGLUT5.vhd +-- \ \ / \ Timestamp : +-- \___\/\___\ +-- +-- Revision: +-- 12/28/05 - Initial version. +-- 04/13/06 - Add address declaration. (CR229735) +-- End Revision + +----- CELL CFGLUT5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity CFGLUT5 is + + generic ( + INIT : bit_vector := X"00000000" + ); + + port ( + CDO : out STD_ULOGIC; + O5 : out STD_ULOGIC; + O6 : out STD_ULOGIC; + + CDI : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + I0 : in STD_ULOGIC; + I1 : in STD_ULOGIC; + I2 : in STD_ULOGIC; + I3 : in STD_ULOGIC; + I4 : in STD_ULOGIC + ); +end CFGLUT5; + +architecture CFGLUT5_V of CFGLUT5 is + signal SHIFT_REG : std_logic_vector (31 downto 0) := To_StdLogicVector(INIT); + signal o6_slv : std_logic_vector (4 downto 0) ; + signal o5_slv : std_logic_vector (3 downto 0) ; + signal o6_addr : integer := 0; + signal o5_addr : integer := 0; +begin + + o6_slv <= I4 & I3 & I2 & I1 & I0; + o5_slv <= I3 & I2 & I1 & I0; + o6_addr <= SLV_TO_INT(o6_slv(4 downto 0)); + o5_addr <= SLV_TO_INT(o5_slv(3 downto 0)); + O6 <= SHIFT_REG(o6_addr); + O5 <= SHIFT_REG(o5_addr); + CDO <= SHIFT_REG(31); + + WriteBehavior : process + variable FIRST_TIME : boolean := TRUE; + begin + + if (FIRST_TIME) then + wait until ((CE = '1' or CE = '0') and + (CLK'last_value = '0' or CLK'last_value = '1') and + (CLK = '0' or CLK = '1')); + FIRST_TIME := FALSE; + end if; + + if (CLK'event AND CLK = '1') then + if (CE = '1') then + SHIFT_REG(31 downto 0) <= (SHIFT_REG(30 downto 0) & CDI) after 100 ps; + end if ; + end if; + + wait on CLK; + + end process WriteBehavior; + +end CFGLUT5_V; + + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2006 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Cyclic Redundancy Check 32-bit Input Simulation Model +-- /___/ /\ Filename : CRC32.vhd +-- \ \ / \ Timestamp : Fri Jun 18 10:57:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 12/20/05 - Initial version. +-- 12/20/05 - Added functionality +-- 01/09/06 - Added Timing +-- 08/02/06 - CR#233833 - Remove GSR declaration +-- 08/18/06 - CR#421781 - CRCOUT initialized to 0 when GSR is high +-- 07/24/07 - CR#442758 - Use CRCCLK instead of crcclk_int in always block +-- 08/16/07 - CR#446564 - Add data_width as part of process block sensitivity list +-- 10/22/07 - CR#452418 - Add all to process sensitivity list +-- 11/21/07 - CR#454853 - POLYNOMIAL is not a user attribute +-- End Revision +------------------------------------------------------------------------------- + +----- CELL CRC32 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_SIGNED.all; +use IEEE.STD_LOGIC_ARITH.all; + +library STD; +use STD.TEXTIO.all; + + +library unisim; +use unisim.vcomponents.all; +use unisim.vpkg.all; + +entity CRC32 is + generic ( + CRC_INIT : bit_vector := X"FFFFFFFF" + ); + port ( + CRCOUT : out std_logic_vector(31 downto 0); + + CRCCLK : in std_ulogic; + CRCDATAVALID : in std_ulogic; + CRCDATAWIDTH : in std_logic_vector(2 downto 0); + CRCIN : in std_logic_vector(31 downto 0); + CRCRESET : in std_ulogic + ); +end CRC32; + + architecture CRC32_V of CRC32 is + + signal data_in_32 : std_logic_vector(7 downto 0); + signal data_in_24 : std_logic_vector(7 downto 0); + signal data_in_16 : std_logic_vector(7 downto 0); + signal data_in_8 : std_logic_vector(7 downto 0); + signal data_width : std_logic_vector(2 downto 0); + signal data_valid : std_logic; + signal crcd : std_logic_vector(31 downto 0); + signal crcreg : std_logic_vector(31 downto 0); + + signal crcgen_out_32 : std_logic_vector(31 downto 0); + signal crcgen_out_24 : std_logic_vector(31 downto 0); + signal crcgen_out_16 : std_logic_vector(31 downto 0); + signal crcgen_out_8 : std_logic_vector(31 downto 0); + +-- signal crcclk_int : std_logic; + signal crcreset_int : std_logic; + + signal crc_initial : std_logic_vector(31 downto 0); + signal poly_val : std_logic_vector(31 downto 0); + + signal zero_24 : std_logic_vector(23 downto 0); + signal zero_16 : std_logic_vector(15 downto 0); + signal zero_8 : std_logic_vector(7 downto 0); + + signal GSR_dly : std_logic; + signal CRCOUT_zd : std_logic_vector(31 downto 0) := ( others => '0'); + + constant POLYNOMIAL : bit_vector := X"04C11DB7"; + + begin + + GSR_dly <= GSR after 0 ps; + + crcreset_int <= CRCRESET; +-- crcclk_int <= CRCCLK; + + crc_initial <= To_StdLogicVector(CRC_INIT); + poly_val <= To_StdLogicVector(POLYNOMIAL); + + zero_24 <= "000000000000000000000000"; + zero_16 <= "0000000000000000"; + zero_8 <= "00000000"; + + + OUTPUT_CALC: process(GSR_dly,crcreg) + begin + if(GSR_dly = '1') then + CRCOUT_zd <= (others => '0'); + elsif(GSR_dly = '0') then + CRCOUT_zd <= (not(crcreg(24)) & not(crcreg(25)) & not(crcreg(26)) & not(crcreg(27)) & not(crcreg(28)) & not(crcreg(29)) & not(crcreg(30)) & not(crcreg(31)) & not(crcreg(16)) & not(crcreg(17)) & not(crcreg(18)) & not(crcreg(19)) & not(crcreg(20)) & not(crcreg(21)) & not(crcreg(22)) & not(crcreg(23)) & not(crcreg(8)) & not(crcreg(9)) & not(crcreg(10)) & not(crcreg(11)) & not(crcreg(12)) & not(crcreg(13)) & not(crcreg(14)) & not(crcreg(15)) & not(crcreg(0)) & not(crcreg(1)) & not(crcreg(2)) & not(crcreg(3)) & not(crcreg(4)) & not(crcreg(5)) & not(crcreg(6)) & not(crcreg(7))); + end if; + end process; + + LOCK_DATA_IN: process(CRCCLK) + begin + if (rising_edge(CRCCLK)) then + data_in_8 <= CRCIN(31 downto 24); + data_in_16 <= CRCIN(23 downto 16); + data_in_24 <= CRCIN(15 downto 8); + data_in_32 <= CRCIN(7 downto 0); + data_valid <= CRCDATAVALID; + data_width <= CRCDATAWIDTH; + end if; + end process; + + + -- Select between CRC8, CRC16, CRC24, CRC32 based on CRCDATAWIDTH + + SELECT_DATA_IN: process(crcgen_out_8,crcgen_out_16,crcgen_out_24,crcgen_out_32,crcd,data_width) + begin + case data_width is + when "000" => crcd <= crcgen_out_8; + when "001" => crcd <= crcgen_out_16; + when "010" => crcd <= crcgen_out_24; + when "011" => crcd <= crcgen_out_32; + when others => crcd <= crcgen_out_8; + end case; + end process; + + -- 32-bit CRC internal register + + INT_REG: process(CRCCLK) + begin + if (rising_edge(CRCCLK)) then + if (crcreset_int = '1') then + crcreg <= crc_initial; + elsif (data_valid /= '1') then + crcreg <= crcreg; + else + crcreg <= crcd; + end if; + end if; + end process; + + --CRC Generator Logic + + CRC_GEN: process(crcreg, CRCIN, data_width,data_in_8,data_in_16, data_in_24,data_in_32) + variable msg : std_logic_vector(40 downto 0); + + variable concat_data_8 : std_logic_vector(31 downto 0); + variable concat_data_16 : std_logic_vector(31 downto 0); + variable concat_data_24 : std_logic_vector(31 downto 0); + variable concat_data_32 : std_logic_vector(31 downto 0); + + + begin + + --CRC-8 + + if (data_width = "000") then + + concat_data_8 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & zero_24; + + msg(31 downto 0) := crcreg xor concat_data_8; + msg(40 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8); + + for i in 0 to 7 loop + msg(40 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1); + if (msg(40) = '1') then + msg(39 downto 8) := msg(39 downto 8) xor poly_val; + end if; + end loop; + crcgen_out_8 <= msg(39 downto 8); + + --CRC-16 + + elsif (data_width = "001") then + + concat_data_16 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0)& data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & zero_16; + + msg(31 downto 0) := crcreg xor concat_data_16; + msg(40 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8); + + for i in 0 to 15 loop + msg(40 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1); + if (msg(40) = '1') then + msg(39 downto 8) := msg(39 downto 8) xor poly_val; + end if; + end loop; + crcgen_out_16 <= msg(39 downto 8); + + --CRC-24 + + elsif (data_width = "010") then + + concat_data_24 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0) & data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & data_in_24(0) & data_in_24(1) & data_in_24(2) & data_in_24(3) & data_in_24(4) & data_in_24(5) & data_in_24(6) & data_in_24(7) & zero_8; + + msg(31 downto 0) := crcreg xor concat_data_24; + msg(40 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8); + + for i in 0 to 23 loop + msg(40 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1); + if (msg(40) = '1') then + msg(39 downto 8) := msg(39 downto 8) xor poly_val; + end if; + end loop; + crcgen_out_24 <= msg(39 downto 8); + + + --CRC-32 + + elsif (data_width = "011") then + concat_data_32 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0) & data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & data_in_24(0) & data_in_24(1) & data_in_24(2) & data_in_24(3) & data_in_24(4) & data_in_24(5) & data_in_24(6) & data_in_24(7) & data_in_32(0) & data_in_32(1) & data_in_32(2) & data_in_32(3) & data_in_32(4) & data_in_32(5) & data_in_32(6) & data_in_32(7); + + msg(31 downto 0) := crcreg xor concat_data_32; + msg(40 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8); + + for i in 0 to 31 loop + msg(40 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1); + if (msg(40) = '1') then + msg(39 downto 8) := msg(39 downto 8) xor poly_val; + end if; + end loop; + crcgen_out_32 <= msg(39 downto 8); + + end if; + end process; + + UNISIM_OUT: process (CRCOUT_zd) + begin + CRCOUT <= CRCOUT_zd after 100 ps; + end process; + +end CRC32_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2005 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Cyclic Redundancy Check 64-bit Input Simulation Model +-- /___/ /\ Filename : CRC64.vhd +-- \ \ / \ Timestamp : Fri Jun 18 10:57:01 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 12/20/05 - Initial version. +-- 12/20/05 - Added functionality +-- 08/02/06 - CR#233833 - Remove GSR declaration +-- 08/18/06 - CR#421781 - CRCOUT initialized to 0 when GSR is high +-- 07/24/07 - CR#442758 - Use CRCCLK instead of crcclk_int in always block +-- 08/16/07 - CR#446564 - Add data_width as part of process block sensitivity list +-- 10/22/07 - CR#452418 - Add all to process sensitivity list +-- 11/21/07 - CR#454853 - POLYNOMIAL is not a user attribute +-- End Revision +------------------------------------------------------------------------------- + +----- CELL CRC64 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_SIGNED.all; +use IEEE.STD_LOGIC_ARITH.all; + +library STD; +use STD.TEXTIO.all; + + +library unisim; +use unisim.vcomponents.all; +use unisim.vpkg.all; + +entity CRC64 is + generic ( + CRC_INIT : bit_vector := X"FFFFFFFF" + ); + port ( + CRCOUT : out std_logic_vector(31 downto 0); + + CRCCLK : in std_ulogic; + CRCDATAVALID : in std_ulogic; + CRCDATAWIDTH : in std_logic_vector(2 downto 0); + CRCIN : in std_logic_vector(63 downto 0); + CRCRESET : in std_ulogic + ); +end CRC64; + + architecture CRC64_V of CRC64 is + + signal data_in_64 : std_logic_vector(7 downto 0); + signal data_in_56 : std_logic_vector(7 downto 0); + signal data_in_48 : std_logic_vector(7 downto 0); + signal data_in_40 : std_logic_vector(7 downto 0); + + signal data_in_32 : std_logic_vector(7 downto 0); + signal data_in_24 : std_logic_vector(7 downto 0); + signal data_in_16 : std_logic_vector(7 downto 0); + signal data_in_8 : std_logic_vector(7 downto 0); + + signal data_width : std_logic_vector(2 downto 0); + signal data_valid : std_ulogic; + signal crcd : std_logic_vector(31 downto 0); + signal crcreg : std_logic_vector(31 downto 0); + + signal crcgen_out_64 : std_logic_vector(31 downto 0); + signal crcgen_out_56 : std_logic_vector(31 downto 0); + signal crcgen_out_48 : std_logic_vector(31 downto 0); + signal crcgen_out_40 : std_logic_vector(31 downto 0); + + signal crcgen_out_32 : std_logic_vector(31 downto 0); + signal crcgen_out_24 : std_logic_vector(31 downto 0); + signal crcgen_out_16 : std_logic_vector(31 downto 0); + signal crcgen_out_8 : std_logic_vector(31 downto 0); + +-- signal crcclk_int : std_ulogic; + signal crcreset_int : std_ulogic; + + signal crc_initial : std_logic_vector(31 downto 0); + signal poly_val : std_logic_vector(31 downto 0); + + signal zero_56 : std_logic_vector(55 downto 0); + signal zero_48 : std_logic_vector(47 downto 0); + signal zero_40 : std_logic_vector(39 downto 0); + signal zero_32 : std_logic_vector(31 downto 0); + signal zero_24 : std_logic_vector(23 downto 0); + signal zero_16 : std_logic_vector(15 downto 0); + signal zero_8 : std_logic_vector(7 downto 0); + + signal GSR_dly : std_ulogic; + signal CRCOUT_zd : std_logic_vector(31 downto 0) := ( others => '0'); + + constant POLYNOMIAL : bit_vector := X"04C11DB7"; + + begin + + GSR_dly <= GSR after 0 ps; + + crcreset_int <= CRCRESET; +-- crcclk_int <= CRCCLK; + + crc_initial <= To_StdLogicVector(CRC_INIT); + poly_val <= To_StdLogicVector(POLYNOMIAL); + + zero_56 <= "00000000000000000000000000000000000000000000000000000000"; + zero_48 <= "000000000000000000000000000000000000000000000000"; + zero_40 <= "0000000000000000000000000000000000000000"; + zero_32 <= "00000000000000000000000000000000"; + zero_24 <= "000000000000000000000000"; + zero_16 <= "0000000000000000"; + zero_8 <= "00000000"; + + + OUTPUT_CALC: process(GSR_dly,crcreg) + begin + if(GSR_dly = '1') then + CRCOUT_zd <= (others => '0'); + elsif(GSR_dly = '0') then + CRCOUT_zd <= (not(crcreg(24)) & not(crcreg(25)) & not(crcreg(26)) & not(crcreg(27)) & not(crcreg(28)) & not(crcreg(29)) & not(crcreg(30)) & not(crcreg(31)) & not(crcreg(16)) & not(crcreg(17)) & not(crcreg(18)) & not(crcreg(19)) & not(crcreg(20)) & not(crcreg(21)) & not(crcreg(22)) & not(crcreg(23)) & not(crcreg(8)) & not(crcreg(9)) & not(crcreg(10)) & not(crcreg(11)) & not(crcreg(12)) & not(crcreg(13)) & not(crcreg(14)) & not(crcreg(15)) & not(crcreg(0)) & not(crcreg(1)) & not(crcreg(2)) & not(crcreg(3)) & not(crcreg(4)) & not(crcreg(5)) & not(crcreg(6)) & not(crcreg(7))); + end if; + end process; + + LOCK_DATA_IN: process(CRCCLK) + begin + if (rising_edge(CRCCLK)) then + data_in_8 <= CRCIN(63 downto 56); + data_in_16 <= CRCIN(55 downto 48); + data_in_24 <= CRCIN(47 downto 40); + data_in_32 <= CRCIN(39 downto 32); + data_in_40 <= CRCIN(31 downto 24); + data_in_48 <= CRCIN(23 downto 16); + data_in_56 <= CRCIN(15 downto 8); + data_in_64 <= CRCIN(7 downto 0); + data_valid <= CRCDATAVALID; + data_width <= CRCDATAWIDTH; + end if; + end process; + + -- Select between CRC8, CRC16, CRC24, CRC32, CRC40, CRC48, CRC56, CRC64 based on CRCDATAWIDTH + + SELECT_DATA_IN: process(crcgen_out_8,crcgen_out_16,crcgen_out_24,crcgen_out_32,crcgen_out_40,crcgen_out_48,crcgen_out_56,crcgen_out_64,crcd,data_width) + begin + case data_width is + when "000" => crcd <= crcgen_out_8; + when "001" => crcd <= crcgen_out_16; + when "010" => crcd <= crcgen_out_24; + when "011" => crcd <= crcgen_out_32; + when "100" => crcd <= crcgen_out_40; + when "101" => crcd <= crcgen_out_48; + when "110" => crcd <= crcgen_out_56; + when "111" => crcd <= crcgen_out_64; + when others => crcd <= crcgen_out_8; + end case; + end process; + + -- 32-bit CRC internal register + + INT_REG: process(CRCCLK) + begin + if (rising_edge(CRCCLK)) then + if (crcreset_int = '1') then + crcreg <= crc_initial; + elsif (data_valid /= '1') then + crcreg <= crcreg; + else + crcreg <= crcd; + end if; + end if; + end process; + + --CRC Generator Logic + + CRC_GEN: process(crcreg, CRCIN, data_width,data_in_8,data_in_16, data_in_24,data_in_32,data_in_40, data_in_48, data_in_56, data_in_64) + variable msg : std_logic_vector(72 downto 0); + + variable concat_data_8 : std_logic_vector(63 downto 0); + variable concat_data_16 : std_logic_vector(63 downto 0); + variable concat_data_24 : std_logic_vector(63 downto 0); + variable concat_data_32 : std_logic_vector(63 downto 0); + + variable concat_data_40 : std_logic_vector(63 downto 0); + variable concat_data_48 : std_logic_vector(63 downto 0); + variable concat_data_56 : std_logic_vector(63 downto 0); + variable concat_data_64 : std_logic_vector(63 downto 0); + + begin + + --CRC-8 + + if (data_width = "000") then + + concat_data_8 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & zero_56; + + msg(63 downto 0) := (crcreg & zero_32) xor concat_data_8; + msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8); + + for i in 0 to 7 loop + msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1); + if (msg(72) = '1') then + msg(71 downto 40) := msg(71 downto 40) xor poly_val; + end if; + end loop; + crcgen_out_8 <= msg(71 downto 40); + + --CRC-16 + + elsif (data_width = "001") then + + concat_data_16 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0)& data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & zero_48; + + msg(63 downto 0) := (crcreg & zero_32) xor concat_data_16; + msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8); + + for i in 0 to 15 loop + msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1); + if (msg(72) = '1') then + msg(71 downto 40) := msg(71 downto 40) xor poly_val; + end if; + end loop; + crcgen_out_16 <= msg(71 downto 40); + + --CRC-24 + + elsif (data_width = "010") then + + concat_data_24 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0) & data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & data_in_24(0) & data_in_24(1) & data_in_24(2) & data_in_24(3) & data_in_24(4) & data_in_24(5) & data_in_24(6) & data_in_24(7) & zero_40; + + msg(63 downto 0) := (crcreg & zero_32) xor concat_data_24; + msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8); + + for i in 0 to 23 loop + msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1); + if (msg(72) = '1') then + msg(71 downto 40) := msg(71 downto 40) xor poly_val; + end if; + end loop; + crcgen_out_24 <= msg(71 downto 40); + + + --CRC-32 + + elsif (data_width = "011") then + concat_data_32 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0) & data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & data_in_24(0) & data_in_24(1) & data_in_24(2) & data_in_24(3) & data_in_24(4) & data_in_24(5) & data_in_24(6) & data_in_24(7) & data_in_32(0) & data_in_32(1) & data_in_32(2) & data_in_32(3) & data_in_32(4) & data_in_32(5) & data_in_32(6) & data_in_32(7) & zero_32; + + msg(63 downto 0) := (crcreg & zero_32) xor concat_data_32; + msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8); + + for i in 0 to 31 loop + msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1); + if (msg(72) = '1') then + msg(71 downto 40) := msg(71 downto 40) xor poly_val; + end if; + end loop; + crcgen_out_32 <= msg(71 downto 40); + + -- CRC-40 + + elsif (data_width = "100") then + concat_data_40 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0) & data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & data_in_24(0) & data_in_24(1) & data_in_24(2) & data_in_24(3) & data_in_24(4) & data_in_24(5) & data_in_24(6) & data_in_24(7) & data_in_32(0) & data_in_32(1) & data_in_32(2) & data_in_32(3) & data_in_32(4) & data_in_32(5) & data_in_32(6) & data_in_32(7) & data_in_40(0) & data_in_40(1) & data_in_40(2) & data_in_40(3) & data_in_40(4) & data_in_40(5) & data_in_40(6) & data_in_40(7) & zero_24; + + msg(63 downto 0) := (crcreg & zero_32) xor concat_data_40; + msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8); + + for i in 0 to 39 loop + msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1); + if (msg(72) = '1') then + msg(71 downto 40) := msg(71 downto 40) xor poly_val; + end if; + end loop; + crcgen_out_40 <= msg(71 downto 40); + + --CRC-48 + + elsif (data_width = "101") then + + concat_data_48 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0) & data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & data_in_24(0) & data_in_24(1) & data_in_24(2) & data_in_24(3) & data_in_24(4) & data_in_24(5) & data_in_24(6) & data_in_24(7) & data_in_32(0) & data_in_32(1) & data_in_32(2) & data_in_32(3) & data_in_32(4) & data_in_32(5) & data_in_32(6) & data_in_32(7) & data_in_40(0) & data_in_40(1) & data_in_40(2) & data_in_40(3) & data_in_40(4) & data_in_40(5) & data_in_40(6) & data_in_40(7) & data_in_48(0) & data_in_48(1) & data_in_48(2) & data_in_48(3) & data_in_48(4) & data_in_48(5) & data_in_48(6) & data_in_48(7) & zero_16; + + msg(63 downto 0) := (crcreg & zero_32) xor concat_data_48; + msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8); + + for i in 0 to 47 loop + msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1); + if (msg(72) = '1') then + msg(71 downto 40) := msg(71 downto 40) xor poly_val; + end if; + end loop; + crcgen_out_48 <= msg(71 downto 40); + + --CRC-56 + + elsif (data_width = "110") then + + concat_data_56 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0) & data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & data_in_24(0) & data_in_24(1) & data_in_24(2) & data_in_24(3) & data_in_24(4) & data_in_24(5) & data_in_24(6) & data_in_24(7) & data_in_32(0) & data_in_32(1) & data_in_32(2) & data_in_32(3) & data_in_32(4) & data_in_32(5) & data_in_32(6) & data_in_32(7) & data_in_40(0) & data_in_40(1) & data_in_40(2) & data_in_40(3) & data_in_40(4) & data_in_40(5) & data_in_40(6) & data_in_40(7) & data_in_48(0) & data_in_48(1) & data_in_48(2) & data_in_48(3) & data_in_48(4) & data_in_48(5) & data_in_48(6) & data_in_48(7) & data_in_56(0) & data_in_56(1) & data_in_56(2) & data_in_56(3) & data_in_56(4) & data_in_56(5) & data_in_56(6) & data_in_56(7) & zero_8; + + msg(63 downto 0) := (crcreg & zero_32) xor concat_data_56; + msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8); + + for i in 0 to 55 loop + msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1); + if (msg(72) = '1') then + msg(71 downto 40) := msg(71 downto 40) xor poly_val; + end if; + end loop; + crcgen_out_56 <= msg(71 downto 40); + + --CRC-64 + + elsif (data_width = "111")then + concat_data_64 := data_in_8(0) & data_in_8(1) & data_in_8(2) & data_in_8(3) & data_in_8(4) & data_in_8(5) & data_in_8(6) & data_in_8(7) & data_in_16(0) & data_in_16(1) & data_in_16(2) & data_in_16(3) & data_in_16(4) & data_in_16(5) & data_in_16(6) & data_in_16(7) & data_in_24(0) & data_in_24(1) & data_in_24(2) & data_in_24(3) & data_in_24(4) & data_in_24(5) & data_in_24(6) & data_in_24(7) & data_in_32(0) & data_in_32(1) & data_in_32(2) & data_in_32(3) & data_in_32(4) & data_in_32(5) & data_in_32(6) & data_in_32(7) & data_in_40(0) & data_in_40(1) & data_in_40(2) & data_in_40(3) & data_in_40(4) & data_in_40(5) & data_in_40(6) & data_in_40(7) & data_in_48(0) & data_in_48(1) & data_in_48(2) & data_in_48(3) & data_in_48(4) & data_in_48(5) & data_in_48(6) & data_in_48(7) & data_in_56(0) & data_in_56(1) & data_in_56(2) & data_in_56(3) & data_in_56(4) & data_in_56(5) & data_in_56(6) & data_in_56(7) & data_in_64(0) & data_in_64(1) & data_in_64(2) & data_in_64(3) & data_in_64(4) & data_in_64(5) & data_in_64(6) & data_in_64(7); + + msg(63 downto 0) := (crcreg & zero_32) xor concat_data_64; + msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 8); + + for i in 0 to 63 loop + msg(72 downto 0) := To_StdLogicVector((To_bitvector(msg)) sll 1); + if (msg(72) = '1') then + msg(71 downto 40) := msg(71 downto 40) xor poly_val; + end if; + end loop; + crcgen_out_64 <= msg(71 downto 40); + + + end if; + + + end process; + + UNISIM_OUT: process (CRCOUT_zd) + begin + CRCOUT <= CRCOUT_zd after 100 ps; + end process; + +end CRC64_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / 18X18 Signed Multiplier Followed by Three-Input Adder plus ALU with Pipeline Registers +-- /___/ /\ Filename : DSP48E.vhd +-- \ \ / \ Timestamp : Mon Mar 28 22:50:04 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 03/28/05 - Initial version. +-- 05/26/05 - BTrack 191 mult not valid in TWO24/FOUR12/USE_MULT=NONE. +-- 06/16/05 - Added MULTSIGNIN/OUT pins and functionality +-- 09/29/05 - Made xyz muxes to be sensitive to carryinsel when recovering from invalid opmode/carryinsel +-- 10/05/05 - Added more valid DRC check entries. +-- 10/25/05 - CR 219047 +-- 11/03/05 - Added two DRC checks -- ARITHMETIC and LOGIC +-- 11/07/05 - 'X'ed out carrycascout in LOGIC modes (like the carryout) +-- 11/21/05 - 'X'ed out pattern detect signals when in illegal opmodes. +-- 02/28/06 - CR 225886 -- USE_MULT check updates. +-- 02/28/06 - CR 226267 -- Changed USE_MULT default to MULT_S. +-- 05/20/06 - CR 230656 -- Disabled RSTP timing check during GSR. +-- 05/29/06 - CR 232187 -- Corrected multcarryinreg CASE statement +-- 05/29/06 - CR 232275 -- Corrected PREG/multsignout_o_mux +-- 10/29/06 - CR 424959 -- Corrected unisim false violation warnings +-- 12/10/06 - CR 429825 -- Added Timing Checks for CARRYCASCIN. +-- 02/20/07 - CR 434192 -- Fixed RSTALUMODE issue +-- 06/11/07 - Added SIM_MODE -- FAST/SAFE feature +-- 06/29/07 - CR 438456 -- Added DRC to output X when USE_MULT=MULT_S is set and not using the multiplier opmode through muxX +-- 08/06/07 - CR 445673 -- Fixed CARRYCASCOUT registered mode issue +-- 10/01/07 - CR 448147 -- Fixed error introduced by 438456 +-- 10/10/07 - CR 451453 -- DRC warning +-- 10/15/07 - CR 444150 -- DRC check enhancements for OPMODEREG/CARRYINSELREG +-- 11/06/07 - CR 451178 -- DRC warning enhancement +-- 02/06/08 - CR 455601 -- DRC relax for OPMODEREG/CARRYINSELREG +-- End Revision +----- CELL DSP48E ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_SIGNED.all; +use IEEE.STD_LOGIC_ARITH.all; + +library STD; +use STD.TEXTIO.all; + + +library unisim; +use unisim.vpkg.all; + +entity DSP48E is + + generic( + + SIM_MODE : string := "SAFE"; + + ACASCREG : integer := 1; + ALUMODEREG : integer := 1; + AREG : integer := 1; + AUTORESET_PATTERN_DETECT : boolean := FALSE; + AUTORESET_PATTERN_DETECT_OPTINV : string := "MATCH"; + A_INPUT : string := "DIRECT"; + BCASCREG : integer := 1; + BREG : integer := 1; + B_INPUT : string := "DIRECT"; + CARRYINREG : integer := 1; + CARRYINSELREG : integer := 1; + CREG : integer := 1; + MASK : bit_vector := X"3FFFFFFFFFFF"; + MREG : integer := 1; + MULTCARRYINREG : integer := 1; + OPMODEREG : integer := 1; + PATTERN : bit_vector := X"000000000000"; + PREG : integer := 1; + SEL_MASK : string := "MASK"; + SEL_PATTERN : string := "PATTERN"; + SEL_ROUNDING_MASK : string := "SEL_MASK"; + USE_MULT : string := "MULT_S"; + USE_PATTERN_DETECT : string := "NO_PATDET"; + USE_SIMD : string := "ONE48" + ); + + port( + ACOUT : out std_logic_vector(29 downto 0); + BCOUT : out std_logic_vector(17 downto 0); + CARRYCASCOUT : out std_ulogic; + CARRYOUT : out std_logic_vector(3 downto 0); + MULTSIGNOUT : out std_ulogic; + OVERFLOW : out std_ulogic; + P : out std_logic_vector(47 downto 0); + PATTERNBDETECT : out std_ulogic; + PATTERNDETECT : out std_ulogic; + PCOUT : out std_logic_vector(47 downto 0); + UNDERFLOW : out std_ulogic; + + A : in std_logic_vector(29 downto 0); + ACIN : in std_logic_vector(29 downto 0); + ALUMODE : in std_logic_vector(3 downto 0); + B : in std_logic_vector(17 downto 0); + BCIN : in std_logic_vector(17 downto 0); + C : in std_logic_vector(47 downto 0); + CARRYCASCIN : in std_ulogic; + CARRYIN : in std_ulogic; + CARRYINSEL : in std_logic_vector(2 downto 0); + CEA1 : in std_ulogic; + CEA2 : in std_ulogic; + CEALUMODE : in std_ulogic; + CEB1 : in std_ulogic; + CEB2 : in std_ulogic; + CEC : in std_ulogic; + CECARRYIN : in std_ulogic; + CECTRL : in std_ulogic; + CEM : in std_ulogic; + CEMULTCARRYIN : in std_ulogic; + CEP : in std_ulogic; + CLK : in std_ulogic; + MULTSIGNIN : in std_ulogic; + OPMODE : in std_logic_vector(6 downto 0); + PCIN : in std_logic_vector(47 downto 0); + RSTA : in std_ulogic; + RSTALLCARRYIN : in std_ulogic; + RSTALUMODE : in std_ulogic; + RSTB : in std_ulogic; + RSTC : in std_ulogic; + RSTCTRL : in std_ulogic; + RSTM : in std_ulogic; + RSTP : in std_ulogic + ); + +end DSP48E; + +-- architecture body -- + +architecture DSP48E_V of DSP48E is + + procedure invalid_opmode_preg_msg( OPMODE : IN string ; + CARRYINSEL : IN string ) is + variable Message : line; + begin + Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); + Write ( Message, OPMODE); + Write ( Message, string'(" with CARRYINSEL ")); + Write ( Message, CARRYINSEL); + Write ( Message, string'(" to DSP48E instance ")); + Write ( Message, string'("requires attribute PREG set to 1.")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end invalid_opmode_preg_msg; + + procedure invalid_opmode_preg_msg_logic( OPMODE : IN string ) is + variable Message : line; + begin + Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); + Write ( Message, OPMODE); + Write ( Message, string'(" to DSP48E instance ")); + Write ( Message, string'("requires attribute PREG set to 1.")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end invalid_opmode_preg_msg_logic; + + procedure invalid_opmode_mreg_msg( OPMODE : IN string ; + CARRYINSEL : IN string ) is + variable Message : line; + begin + Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); + Write ( Message, OPMODE); + Write ( Message, string'(" with CARRYINSEL ")); + Write ( Message, CARRYINSEL); + Write ( Message, string'(" to DSP48E instance ")); + Write ( Message, string'("requires attribute MREG set to 1.")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end invalid_opmode_mreg_msg; + + procedure invalid_opmode_no_mreg_msg( OPMODE : IN string ; + CARRYINSEL : IN string ) is + variable Message : line; + begin + Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); + Write ( Message, OPMODE); + Write ( Message, string'(" with CARRYINSEL ")); + Write ( Message, CARRYINSEL); + Write ( Message, string'(" to DSP48E instance ")); + Write ( Message, string'("requires attribute MREG set to 0.")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end invalid_opmode_no_mreg_msg; + + + + TYPE AluFuntionType is (INVALID_ALU, ADD_ALU, ADD_XY_NOTZ_ALU, NOT_XYZC_ALU, SUBTRACT_ALU, NOT_ALU, + AND_ALU, OR_ALU, XOR_ALU, NAND_ALU, NOR_ALU, + XNOR_ALU, X_AND_NOT_Z_ALU, NOT_X_OR_Z_ALU, X_OR_NOT_Z_ALU, + X_NOR_Z_ALU, NOT_X_AND_Z_ALU); + + constant SYNC_PATH_DELAY : time := 100 ps; + + constant MAX_ACOUT : integer := 30; + constant MAX_BCOUT : integer := 18; + constant MAX_CARRYOUT : integer := 4; + constant MAX_P : integer := 48; + constant MAX_PCOUT : integer := 48; + + constant MAX_A : integer := 30; + constant MAX_ACIN : integer := 30; + constant MAX_ALUMODE : integer := 4; + constant MAX_A_MULT : integer := 25; + constant MAX_B : integer := 18; + constant MAX_B_MULT : integer := 18; + constant MAX_BCIN : integer := 18; + constant MAX_C : integer := 48; + constant MAX_CARRYINSEL : integer := 3; + constant MAX_OPMODE : integer := 7; + constant MAX_PCIN : integer := 48; + + constant MAX_ALU_FULL : integer := 48; + constant MAX_ALU_HALF : integer := 24; + constant MAX_ALU_QUART : integer := 12; + + constant MSB_ACOUT : integer := MAX_ACOUT - 1; + constant MSB_BCOUT : integer := MAX_BCOUT - 1; + constant MSB_CARRYOUT : integer := MAX_CARRYOUT - 1; + constant MSB_P : integer := MAX_P - 1; + constant MSB_PCOUT : integer := MAX_PCOUT - 1; + + + constant MSB_A : integer := MAX_A - 1; + constant MSB_ACIN : integer := MAX_ACIN - 1; + constant MSB_ALUMODE : integer := MAX_ALUMODE - 1; + constant MSB_A_MULT : integer := MAX_A_MULT - 1; + constant MSB_B : integer := MAX_B - 1; + constant MSB_B_MULT : integer := MAX_B_MULT - 1; + constant MSB_BCIN : integer := MAX_BCIN - 1; + constant MSB_C : integer := MAX_C - 1; + constant MSB_CARRYINSEL : integer := MAX_CARRYINSEL - 1; + constant MSB_OPMODE : integer := MAX_OPMODE - 1; + constant MSB_PCIN : integer := MAX_PCIN - 1; + + constant MSB_ALU_FULL : integer := MAX_ALU_FULL - 1; + constant MSB_ALU_HALF : integer := MAX_ALU_HALF - 1; + constant MSB_ALU_QUART : integer := MAX_ALU_QUART - 1; + + constant SHIFT_MUXZ : integer := 17; + + signal A_ipd : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal ACIN_ipd : std_logic_vector(MSB_ACIN downto 0) := (others => '0'); + signal ALUMODE_ipd : std_logic_vector(MSB_ALUMODE downto 0) := (others => '0'); + signal B_ipd : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal BCIN_ipd : std_logic_vector(MSB_BCIN downto 0) := (others => '0'); + signal C_ipd : std_logic_vector(MSB_C downto 0) := (others => '0'); + signal CARRYCASCIN_ipd : std_logic := '0'; + signal CARRYIN_ipd : std_logic := '0'; + signal CARRYINSEL_ipd : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0'); + signal CEA1_ipd : std_logic := '0'; + signal CEA2_ipd : std_logic := '0'; + signal CEALUMODE_ipd : std_logic := '0'; + signal CEB1_ipd : std_logic := '0'; + signal CEB2_ipd : std_logic := '0'; + signal CEC_ipd : std_logic := '0'; + signal CECARRYIN_ipd : std_logic := '0'; + signal CECTRL_ipd : std_logic := '0'; + signal CEM_ipd : std_logic := '0'; + signal CEMULTCARRYIN_ipd : std_logic := '0'; + signal CEP_ipd : std_logic := '0'; + signal CLK_ipd : std_logic := '0'; + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := '0'; + signal MULTSIGNIN_ipd : std_logic := '0'; + signal OPMODE_ipd : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); + signal PCIN_ipd : std_logic_vector(MSB_PCIN downto 0) := (others => '0'); + signal RSTA_ipd : std_logic := '0'; + signal RSTALLCARRYIN_ipd : std_logic := '0'; + signal RSTALUMODE_ipd : std_logic := '0'; + signal RSTB_ipd : std_logic := '0'; + signal RSTC_ipd : std_logic := '0'; + signal RSTCTRL_ipd : std_logic := '0'; + signal RSTM_ipd : std_logic := '0'; + signal RSTP_ipd : std_logic := '0'; + + signal A_dly : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal ACIN_dly : std_logic_vector(MSB_ACIN downto 0) := (others => '0'); + signal ALUMODE_dly : std_logic_vector(MSB_ALUMODE downto 0) := (others => '0'); + signal B_dly : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal BCIN_dly : std_logic_vector(MSB_BCIN downto 0) := (others => '0'); + signal C_dly : std_logic_vector(MSB_C downto 0) := (others => '0'); + signal CARRYCASCIN_dly : std_logic := '0'; + signal CARRYIN_dly : std_logic := '0'; + signal CARRYINSEL_dly : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0'); + signal CEA1_dly : std_logic := '0'; + signal CEA2_dly : std_logic := '0'; + signal CEALUMODE_dly : std_logic := '0'; + signal CEB1_dly : std_logic := '0'; + signal CEB2_dly : std_logic := '0'; + signal CEC_dly : std_logic := '0'; + signal CECARRYIN_dly : std_logic := '0'; + signal CECTRL_dly : std_logic := '0'; + signal CEM_dly : std_logic := '0'; + signal CEMULTCARRYIN_dly : std_logic := '0'; + signal CEP_dly : std_logic := '0'; + signal CLK_dly : std_logic := '0'; + signal GSR_dly : std_logic := '0'; + signal MULTSIGNIN_dly : std_logic := '0'; + signal OPMODE_dly : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); + signal PCIN_dly : std_logic_vector(MSB_PCIN downto 0) := (others => '0'); + signal RSTA_dly : std_logic := '0'; + signal RSTALLCARRYIN_dly : std_logic := '0'; + signal RSTALUMODE_dly : std_logic := '0'; + signal RSTB_dly : std_logic := '0'; + signal RSTC_dly : std_logic := '0'; + signal RSTCTRL_dly : std_logic := '0'; + signal RSTM_dly : std_logic := '0'; + signal RSTP_dly : std_logic := '0'; + + + signal ACOUT_zd : std_logic_vector(MSB_ACOUT downto 0) := (others => '0'); + signal BCOUT_zd : std_logic_vector(MSB_BCOUT downto 0) := (others => '0'); + signal CARRYCASCOUT_zd : std_logic := '0'; + signal CARRYOUT_zd : std_logic_vector(MSB_CARRYOUT downto 0) := (others => '0'); + signal OVERFLOW_zd : std_logic := '0'; + signal P_zd : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal PATTERNBDETECT_zd : std_logic := '0'; + signal PATTERNDETECT_zd : std_logic := '0'; + signal PCOUT_zd : std_logic_vector(MSB_PCOUT downto 0) := (others => '0'); + signal UNDERFLOW_zd : std_logic := '0'; + signal MULTSIGNOUT_zd : std_logic; + + --- Internal Signal Declarations + signal a_o_mux : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal qa_o_reg1 : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal qa_o_reg2 : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal qa_o_mux : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal qacout_o_mux : std_logic_vector(MSB_ACOUT downto 0) := (others => '0'); + + signal b_o_mux : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal qb_o_reg1 : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal qb_o_reg2 : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal qb_o_mux : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal qbcout_o_mux : std_logic_vector(MSB_BCOUT downto 0) := (others => '0'); + + signal qc_o_reg : std_logic_vector(MSB_C downto 0) := (others => '0'); + signal qc_o_mux : std_logic_vector(MSB_C downto 0) := (others => '0'); + + signal mult_o_int : std_logic_vector((MSB_A_MULT + MSB_B_MULT + 1) downto 0) := (others => '0'); + signal mult_o_reg : std_logic_vector((MSB_A_MULT + MSB_B_MULT + 1) downto 0) := (others => '0'); + signal mult_o_mux : std_logic_vector((MSB_A_MULT + MSB_B_MULT + 1) downto 0) := (others => '0'); + + signal opmode_o_reg : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); + signal opmode_o_mux : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); + + signal muxx_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal muxy_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal muxz_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); + + signal carryinsel_o_reg : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0'); + signal carryinsel_o_mux : std_logic_vector(MSB_CARRYINSEL downto 0) := (others => '0'); + + signal qcarryin_o_reg0 : std_logic := '0'; + signal carryin_o_mux0 : std_logic := '0'; + signal qcarryin_o_reg7 : std_logic := '0'; + signal carryin_o_mux7 : std_logic := '0'; + + signal carryin_o_mux : std_logic := '0'; + + signal qp_o_reg : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal qp_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); + + signal reg_p_int : std_logic_vector(47 downto 0) := (others => '0'); + signal p_o_int : std_logic_vector(47 downto 0) := (others => '0'); + + signal output_x_sig : std_logic := '0'; + + signal RST_META : std_logic := '0'; + + signal DefDelay : time := 10 ps; + + signal opmode_valid_flg : boolean := true; + signal alumode_valid_flg : boolean := true; + + signal AluFunction : AluFuntionType := INVALID_ALU; + + signal alumode_o_reg : std_logic_vector(MSB_ALUMODE downto 0) := (others => '0'); + signal alumode_o_mux : std_logic_vector(MSB_ALUMODE downto 0) := (others => '0'); + + signal carrycascout_o : std_logic := '0'; + signal carrycascout_o_reg : std_logic := '0'; + signal carrycascout_o_mux : std_logic := '0'; + signal carryout_o : std_logic_vector(MSB_CARRYOUT downto 0) := (others => '0'); + signal carryout_o_reg : std_logic_vector(MSB_CARRYOUT downto 0) := (others => '0'); + signal carryout_o_mux : std_logic_vector(MSB_CARRYOUT downto 0) := (others => '0'); + signal carryout_x_o : std_logic_vector(MSB_CARRYOUT downto 0) := (others => 'X'); + signal overflow_o : std_logic := '0'; + signal pdetb_o : std_logic := '0'; + signal pdetb_o_reg1 : std_logic := '0'; + signal pdetb_o_reg2 : std_logic := '0'; + signal pdet_o : std_logic := '0'; + signal pdet_o_reg1 : std_logic := '0'; + signal pdet_o_reg2 : std_logic := '0'; + signal underflow_o : std_logic := '0'; + + signal alu_o : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal pattern_qp : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal mask_qp : std_logic_vector(MSB_P downto 0) := (others => '0'); + + signal multsignout_o_reg : std_logic; + signal multsignout_o_mux : std_logic; + signal multsignout_o_opmode : std_logic; + + signal OPMODE_NUMBER : integer := -1; + + signal ping_opmode_drc_check : std_logic := '0'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + + A_dly <= A after 0 ps; + ACIN_dly <= ACIN after 0 ps; + ALUMODE_dly <= ALUMODE after 0 ps; + B_dly <= B after 0 ps; + BCIN_dly <= BCIN after 0 ps; + C_dly <= C after 0 ps; + CARRYCASCIN_dly <= CARRYCASCIN after 0 ps; + CARRYIN_dly <= CARRYIN after 0 ps; + CARRYINSEL_dly <= CARRYINSEL after 0 ps; + CEA1_dly <= CEA1 after 0 ps; + CEA2_dly <= CEA2 after 0 ps; + CEALUMODE_dly <= CEALUMODE after 0 ps; + CEB1_dly <= CEB1 after 0 ps; + CEB2_dly <= CEB2 after 0 ps; + CEC_dly <= CEC after 0 ps; + CECARRYIN_dly <= CECARRYIN after 0 ps; + CECTRL_dly <= CECTRL after 0 ps; + CEM_dly <= CEM after 0 ps; + CEMULTCARRYIN_dly <= CEMULTCARRYIN after 0 ps; + CEP_dly <= CEP after 0 ps; + CLK_dly <= CLK after 0 ps; + MULTSIGNIN_dly <= MULTSIGNIN after 0 ps; + OPMODE_dly <= OPMODE after 0 ps; + PCIN_dly <= PCIN after 0 ps; + RSTA_dly <= RSTA after 0 ps; + RSTALLCARRYIN_dly <= RSTALLCARRYIN after 0 ps; + RSTALUMODE_dly <= RSTALUMODE after 0 ps; + RSTB_dly <= RSTB after 0 ps; + RSTC_dly <= RSTC after 0 ps; + RSTCTRL_dly <= RSTCTRL after 0 ps; + RSTM_dly <= RSTM after 0 ps; + RSTP_dly <= RSTP after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +standard_model : if (SIM_MODE = "SAFE") generate +--#################################################################### +--##### Initialization ### +--#################################################################### + prcs_init:process + begin + +----------- Checks for AREG ---------------------- + case AREG is + when 0|1|2 => + when others => + assert false + report "Attribute Syntax Error: The allowed values for AREG are 0 or 1 or 2" + severity Failure; + end case; + +----------- Checks for ACASCREG and (ACASCREG vs AREG) ---------------------- + + case AREG is + when 0 => if(AREG /= ACASCREG) then + assert false + report "Attribute Syntax Error : The attribute ACASCREG on DSP48E has to be set to 0 when attribute AREG = 0." + severity Failure; + end if; + when 1 => if(AREG /= ACASCREG) then + assert false + report "Attribute Syntax Error : The attribute ACASCREG on DSP48E has to be set to 1 when attribute AREG = 1." + severity Failure; + end if; + when 2 => if((AREG /= ACASCREG) and ((AREG-1) /= ACASCREG))then + assert false + report "Attribute Syntax Error : The attribute ACASCREG on DSP48E has to be set to either 2 or 1 when attribute AREG = 2." + severity Failure; + end if; + when others => null; + end case; + +----------- Checks for BREG ---------------------- + case BREG is + when 0|1|2 => + when others => + assert false + report "Attribute Syntax Error: The allowed values for BREG are 0 or 1 or 2" + severity Failure; + end case; + +----------- Checks for BCASCREG and (BCASCREG vs BREG) ---------------------- + + case BREG is + when 0 => if(BREG /= BCASCREG) then + assert false + report "Attribute Syntax Error : The attribute BCASCREG on DSP48E has to be set to 0 when attribute BREG = 0." + severity Failure; + end if; + when 1 => if(BREG /= BCASCREG) then + assert false + report "Attribute Syntax Error : The attribute BCASCREG on DSP48E has to be set to 1 when attribute BREG = 1." + severity Failure; + end if; + when 2 => if((BREG /= BCASCREG) and ((BREG-1) /= BCASCREG))then + assert false + report "Attribute Syntax Error : The attribute BCASCREG on DSP48E has to be set to either 2 or 1 when attribute BREG = 2." + severity Failure; + end if; + when others => null; + end case; + +----------- Check for AUTORESET_OVER_UNDER_FLOW ---------------------- + +-- case AUTORESET_OVER_UNDER_FLOW is +-- when true | false => null; +-- when others => +-- assert false +-- report "Attribute Syntax Error: The allowed values for AUTORESET_OVER_UNDER_FLOW are true or fasle" +-- severity Failure; +-- end case; + +----------- Check for AUTORESET_PATTERN_DETECT ---------------------- + + case AUTORESET_PATTERN_DETECT is + when true | false => null; + when others => + assert false + report "Attribute Syntax Error: The allowed values for AUTORESET_PATTERN_DETECT are true or fasle" + severity Failure; + end case; + +----------- Check for AUTORESET_PATTERN_DETECT_OPTINV ---------------------- + + if((AUTORESET_PATTERN_DETECT_OPTINV /="MATCH") and (AUTORESET_PATTERN_DETECT_OPTINV /="NOT_MATCH")) then + assert false + report "Attribute Syntax Error: The allowed values for AUTORESET_PATTERN_DETECT_OPTINV are MATCH or NOT_MATCH." + severity Failure; + end if; + +----------- Check for USE_MULT ---------------------- + + if((USE_MULT /="NONE") and (USE_MULT /="MULT") and + (USE_MULT /="MULT_S")) then + assert false + report "Attribute Syntax Error: The allowed values for USE_MULT are NONE, MULT or MULT_S." + severity Failure; + elsif((USE_MULT ="MULT") and (MREG /= 0)) then + assert false + report "Attribute Syntax Error: The attribute USE_MULT on DSP48 is set to MULT. This requires attribute MREG to be set to 0." + severity Failure; + elsif((USE_MULT ="MULT_S") and (MREG /= 1)) then + assert false + report "Attribute Syntax Error: The attribute USE_MULT on DSP48 is set to MULT_S. This requires attribute MREG to be set to 1." + severity Failure; + end if; + +----------- Check for USE_PATTERN_DETECT ---------------------- + + if((USE_PATTERN_DETECT /="PATDET") and (USE_PATTERN_DETECT /="NO_PATDET")) then + assert false + report "Attribute Syntax Error: The allowed values for USE_PATTERN_DETECT are PATDET or NO_PATDET." + severity Failure; + end if; + +--********************************************************* +--*** ADDITIONAL DRC +--********************************************************* +-- CR 219407 -- (1) + if((AUTORESET_PATTERN_DETECT = TRUE) and (USE_PATTERN_DETECT = "NO_PATDET")) then + assert false + report "Attribute Syntax Error : The attribute USE_PATTERN_DETECT on DSP48E instance must be set to PATDET in order to use AUTORESET_PATTERN_DETECT equals TRUE. Failure to do so could make timing reports inaccurate. " + severity Warning; + end if; +------------------------------------------------------------ + ping_opmode_drc_check <= '1' after 100010 ps; +------------------------------------------------------------ + + wait; + end process prcs_init; +--#################################################################### +--##### Input Register A with two levels of registers and a mux ### +--#################################################################### + prcs_a_in:process(A_dly, ACIN_dly) + begin + if(A_INPUT ="DIRECT") then + a_o_mux <= A_dly; + elsif(A_INPUT ="CASCADE") then + a_o_mux <= ACIN_dly; + else + assert false + report "Attribute Syntax Error: The allowed values for A_INPUT are DIRECT or CASCADE." + severity Failure; + end if; + end process prcs_a_in; +------------------------------------------------------------------ + prcs_qa_2lvl:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qa_o_reg1 <= ( others => '0'); + qa_o_reg2 <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTA_dly = '1') then + qa_o_reg1 <= ( others => '0'); + qa_o_reg2 <= ( others => '0'); + elsif (RSTA_dly = '0') then + case AREG is + when 1 => + if(CEA2_dly = '1') then + qa_o_reg2 <= a_o_mux; + end if; + when 2 => + if(CEA1_dly = '1') then + qa_o_reg1 <= a_o_mux; + end if; + if(CEA2_dly = '1') then + qa_o_reg2 <= qa_o_reg1; + end if; + when others => null; + end case; + end if; + end if; + end if; + end process prcs_qa_2lvl; +------------------------------------------------------------------ + prcs_qa_o_mux:process(a_o_mux, qa_o_reg2) + begin + case AREG is + when 0 => qa_o_mux <= a_o_mux; + when 1|2 => qa_o_mux <= qa_o_reg2; + when others => + assert false + report "Attribute Syntax Error: The allowed values for AREG are 0 or 1 or 2" + severity Failure; + end case; + end process prcs_qa_o_mux; +------------------------------------------------------------------ + prcs_qacout_o_mux:process(qa_o_mux, qa_o_reg1) + begin + case ACASCREG is + when 1 => case AREG is + when 2 => qacout_o_mux <= qa_o_reg1; + when others => qacout_o_mux <= qa_o_mux; + end case; + when others => qacout_o_mux <= qa_o_mux; + end case; + + end process prcs_qacout_o_mux; +--#################################################################### +--##### Input Register B with two levels of registers and a mux ### +--#################################################################### + prcs_b_in:process(B_dly, BCIN_dly) + begin + if(B_INPUT ="DIRECT") then + b_o_mux <= B_dly; + elsif(B_INPUT ="CASCADE") then + b_o_mux <= BCIN_dly; + else + assert false + report "Attribute Syntax Error: The allowed values for B_INPUT are DIRECT or CASCADE." + severity Failure; + end if; + + end process prcs_b_in; +------------------------------------------------------------------ + prcs_qb_2lvl:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qb_o_reg1 <= ( others => '0'); + qb_o_reg2 <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTB_dly = '1') then + qb_o_reg1 <= ( others => '0'); + qb_o_reg2 <= ( others => '0'); + elsif (RSTB_dly = '0') then + case BREG is + when 1 => + if(CEB2_dly = '1') then + qb_o_reg2 <= b_o_mux; + end if; + when 2 => + if(CEB1_dly = '1') then + qb_o_reg1 <= b_o_mux; + end if; + if(CEB2_dly = '1') then + qb_o_reg2 <= qb_o_reg1; + end if; + when others => null; + end case; + end if; + end if; + end if; + end process prcs_qb_2lvl; +------------------------------------------------------------------ + prcs_qb_o_mux:process(b_o_mux, qb_o_reg2) + begin + case BREG is + when 0 => qb_o_mux <= b_o_mux; + when 1|2 => qb_o_mux <= qb_o_reg2; + when others => + assert false + report "Attribute Syntax Error: The allowed values for BREG are 0 or 1 or 2 " + severity Failure; + end case; + + end process prcs_qb_o_mux; +------------------------------------------------------------------ + prcs_qbcout_o_mux:process(qb_o_mux, qb_o_reg1) + begin + case BCASCREG is + when 1 => case BREG is + when 2 => qbcout_o_mux <= qb_o_reg1; + when others => qbcout_o_mux <= qb_o_mux; + end case; + when others => qbcout_o_mux <= qb_o_mux; + end case; + end process prcs_qbcout_o_mux; + +--#################################################################### +--##### Input Register C with 0, 1, level of registers ##### +--#################################################################### + prcs_qc_1lvl:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qc_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTC_dly = '1') then + qc_o_reg <= ( others => '0'); + elsif ((RSTC_dly = '0') and (CEC_dly = '1')) then + qc_o_reg <= C_dly; + end if; + end if; + end if; + end process prcs_qc_1lvl; +------------------------------------------------------------------ + prcs_qc_o_mux:process(C_dly, qc_o_reg) + begin + case CREG is + when 0 => qc_o_mux <= C_dly; + when 1 => qc_o_mux <= qc_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for CREG are 0 or 1" + severity Failure; + end case; + end process prcs_qc_o_mux; + +--#################################################################### +--################### 25x18 Multiplier ###################### +--#################################################################### +-- +-- 05/26/05 -- FP -- Added warning for invalid mult when USE_MULT=NONE +-- SIMD=FOUR12 and SIMD=TWO24 +-- Made mult_o to be "X" +-- + prcs_mult:process(qa_o_mux, qb_o_mux) + begin + if(USE_MULT /= "NONE") then + mult_o_int <= qa_o_mux(MSB_A_MULT downto 0) * qb_o_mux (MSB_B_MULT downto 0); + end if; + end process prcs_mult; +------------------------------------------------------------------ + prcs_mult_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + mult_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTM_dly = '1') then + mult_o_reg <= ( others => '0'); + elsif ((RSTM_dly = '0') and (CEM_dly = '1')) then + mult_o_reg <= mult_o_int; + end if; + end if; + end if; + end process prcs_mult_reg; +------------------------------------------------------------------ + prcs_mult_mux:process(mult_o_reg, mult_o_int) + begin + case MREG is + when 0 => mult_o_mux <= mult_o_int; + when 1 => mult_o_mux <= mult_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for MREG are 0 or 1" + severity Failure; + end case; + end process prcs_mult_mux; + +--#################################################################### +--##### OpMode ##### +--#################################################################### + prcs_opmode_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + opmode_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTCTRL_dly = '1') then + opmode_o_reg <= ( others => '0'); + elsif ((RSTCTRL_dly = '0') and (CECTRL_dly = '1')) then + opmode_o_reg <= OPMODE_dly; + end if; + end if; + end if; + end process prcs_opmode_reg; +------------------------------------------------------------------ + prcs_opmode_mux:process(opmode_o_reg, OPMODE_dly) + begin + case OPMODEREG is + when 0 => opmode_o_mux <= OPMODE_dly; + when 1 => opmode_o_mux <= opmode_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for OPMODEREG are 0 or 1" + severity Failure; + end case; + end process prcs_opmode_mux; +--#################################################################### +--##### MUX_XYZ ##### +--#################################################################### + prcs_mux_xyz:process(opmode_o_mux, qp_o_mux, qa_o_mux, qb_o_mux, mult_o_mux, + qc_o_mux, PCIN_dly, output_x_sig) + begin + if(output_x_sig = '1') then + muxx_o_mux(MSB_P downto 0) <= ( others => 'X'); + muxy_o_mux(MSB_P downto 0) <= ( others => 'X'); + muxz_o_mux(MSB_P downto 0) <= ( others => 'X'); + elsif(output_x_sig = '0') then + --MUX_X ----- + case opmode_o_mux(1 downto 0) is + when "00" => muxx_o_mux <= ( others => '0'); + -- FP ?? sign extend needed from 43rd bit to 48th bit + when "01" => muxx_o_mux((MSB_A_MULT + MSB_B_MULT +1) downto 0) <= mult_o_mux; + if(mult_o_mux(MSB_A_MULT + MSB_B_MULT + 1) = '1') then + muxx_o_mux(MSB_PCIN downto (MAX_A_MULT + MAX_B_MULT)) <= ( others => '1'); + elsif (mult_o_mux(MSB_A_MULT + MSB_B_MULT + 1) = '0') then + muxx_o_mux(MSB_PCIN downto (MAX_A_MULT + MAX_B_MULT)) <= ( others => '0'); + end if; + when "10" => muxx_o_mux <= qp_o_mux; + +-- CR 438456 & CR 448147 & CR 451453 + when "11" => if((USE_MULT = "MULT_S") and (AREG=0 or BREG=0)) then + muxx_o_mux(MSB_P downto 0) <= ( others => 'X'); + assert false + report "DRC warning: When attribute USE_MULT on DSP48E instance %m is set to MULT_S, the A:B opmode selection is not permitted when AREG or BREG=0. If the multiplier is not used, set USE_MULT = NONE. For dynamic switching between multiply and add operation, set AREG and BREG=1 or MREG=0 and USE_MULT=MULT." + severity Warning; + else + muxx_o_mux(MSB_P downto 0) <= (qa_o_mux & qb_o_mux); + end if; + + when others => null; + end case; + + --MUX_Y ----- + case opmode_o_mux(3 downto 2) is + when "00" => muxy_o_mux <= ( others => '0'); + when "01" => muxy_o_mux <= ( others => '0'); + when "10" => + if(opmode_o_mux(6 downto 4) = "100") then + muxy_o_mux <= ( others => MULTSIGNIN_dly); + else + muxy_o_mux <= ( others => '1'); + end if; + when "11" => muxy_o_mux <= qc_o_mux; + when others => null; + end case; + --MUX_Z ----- + case opmode_o_mux(6 downto 4) is + when "000" => muxz_o_mux <= ( others => '0'); + when "001" => muxz_o_mux <= PCIN_dly; + when "010" => muxz_o_mux <= qp_o_mux; + when "011" => muxz_o_mux <= qc_o_mux; + when "100" => muxz_o_mux <= qp_o_mux; -- Used for MACC extend -- multsignin + -- FP ?? better shift possible ? + when "101" => if(PCIN_dly(MSB_PCIN) = '0') then + muxz_o_mux <= ( others => '0'); + elsif(PCIN_dly(MSB_PCIN) = '1') then + muxz_o_mux <= ( others => '1'); + end if; + muxz_o_mux ((MSB_PCIN - SHIFT_MUXZ) downto 0) <= PCIN_dly(MSB_PCIN downto SHIFT_MUXZ ); + when "110" => if(qp_o_mux(MSB_P) = '0') then + muxz_o_mux <= ( others => '0'); + elsif(qp_o_mux(MSB_P) = '1') then + muxz_o_mux <= ( others => '1'); + end if; + muxz_o_mux ((MSB_P - SHIFT_MUXZ) downto 0) <= qp_o_mux(MSB_P downto SHIFT_MUXZ ); + + when "111" => null; + when others => null; + end case; + end if; + end process prcs_mux_xyz; +--#################################################################### +--##### Alumode ##### +--#################################################################### + prcs_alumode_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + alumode_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTALUMODE_dly = '1') then + alumode_o_reg <= ( others => '0'); + elsif ((RSTALUMODE_dly = '0') and (CEALUMODE_dly = '1'))then + alumode_o_reg <= ALUMODE_dly; + end if; + end if; + end if; + end process prcs_alumode_reg; +------------------------------------------------------------------ + prcs_alumode_mux:process(alumode_o_reg, ALUMODE_dly) + begin + case ALUMODEREG is + when 0 => alumode_o_mux <= ALUMODE_dly; + when 1 => alumode_o_mux <= alumode_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for ALUMODEREG are 0 or 1" + severity Failure; + end case; + end process prcs_alumode_mux; + +--#################################################################### +--##### CarryInSel ##### +--#################################################################### + prcs_carryinsel_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + carryinsel_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTCTRL_dly = '1') then + carryinsel_o_reg <= ( others => '0'); + elsif ((RSTCTRL_dly = '0') and (CECTRL_dly = '1')) then + carryinsel_o_reg <= CARRYINSEL_dly; + end if; + end if; + end if; + end process prcs_carryinsel_reg; +------------------------------------------------------------------ + prcs_carryinsel_mux:process(carryinsel_o_reg, CARRYINSEL_dly) + begin + case CARRYINSELREG is + when 0 => carryinsel_o_mux <= CARRYINSEL_dly; + when 1 => carryinsel_o_mux <= carryinsel_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for CARRYINSELREG are 0 or 1" + severity Failure; + end case; + end process prcs_carryinsel_mux; + +------------------------------------------------------------------ +-- CR 219047 (3) + + prcs_carryinsel_drc:process(carryinsel_o_mux, MULTSIGNIN_dly, opmode_o_mux) + begin + if(carryinsel_o_mux = "010") then + if(not((MULTSIGNIN_dly = 'X') or ((opmode_o_mux = "1001000") and (MULTSIGNIN_dly /= 'X')) + or ((MULTSIGNIN_dly = '0') and (CARRYCASCIN_dly = '0')))) then + assert false +-- CR 451178 -- DRC warning Enhancement + report "DRC warning : CARRYCASCIN can only be used in the current DSP48E instance if the previous DSP48E is performing a two input ADD operation, or the current DSP48E is configured in the MAC extend opmode(6:0) equals 1001000. This warning can be also triggered if OPMODEREG is set to 1 and CARRYINSELREG is set to 0 - in which case please set CARRYINSELREG to 1." + severity Warning; + end if; + end if; + end process prcs_carryinsel_drc; + +-- CR 219047 (4) + prcs_carryinsel_mac_drc:process(carryinsel_o_mux) + begin + if((carryinsel_o_mux = "110") and (MULTCARRYINREG /= MREG)) then + assert false + report "Attribute Syntax Warning : It is recommended that MREG and MULTCARRYINREG on DSP48E instance be set to the same value when using CARRYINSEL = 110 for multiply rounding. " + severity Warning; + end if; + end process prcs_carryinsel_mac_drc; + + +--#################################################################### +--##### CarryIn ##### +--#################################################################### + +------- input 0 + + prcs_carryin_reg0:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qcarryin_o_reg0 <= '0'; + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTALLCARRYIN_dly = '1') then + qcarryin_o_reg0 <= '0'; + elsif((RSTALLCARRYIN_dly = '0') and (CECARRYIN_dly = '1')) then + qcarryin_o_reg0 <= CARRYIN_dly; + end if; + end if; + end if; + end process prcs_carryin_reg0; + + prcs_carryin_mux0:process(qcarryin_o_reg0, CARRYIN_dly) + begin + case CARRYINREG is + when 0 => carryin_o_mux0 <= CARRYIN_dly; + when 1 => carryin_o_mux0 <= qcarryin_o_reg0; + when others => + assert false + report "Attribute Syntax Error: The allowed values for CARRYINREG are 0 or 1" + severity Failure; + end case; + end process prcs_carryin_mux0; + +------------------------------------------------------------------ +------- input 7 + + prcs_carryin_reg7:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qcarryin_o_reg7 <= '0'; + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTALLCARRYIN_dly = '1') then + qcarryin_o_reg7 <= '0'; + elsif((RSTALLCARRYIN_dly = '0') and (CEMULTCARRYIN_dly = '1')) then + qcarryin_o_reg7 <= qa_o_mux(24) XNOR qb_o_mux(17); + end if; + end if; + end if; + end process prcs_carryin_reg7; + + prcs_carryin_mux7:process(qa_o_mux(24), qb_o_mux(17), qcarryin_o_reg7) + begin + case MULTCARRYINREG is + when 0 => carryin_o_mux7 <= qa_o_mux(24) XNOR qb_o_mux(17); +-- CR 232187 + when 1 => carryin_o_mux7 <= qcarryin_o_reg7; + when others => + assert false + report "Attribute Syntax Error: The allowed values for MULTCARRYINREG are 0 or 1" + severity Failure; + end case; + end process prcs_carryin_mux7; + +------------------------------------------------------------------ +-- FP Check this with VV +------------------------------------------------------------------ +-- + prcs_carryin_mux:process(carryin_o_mux0, PCIN_dly(47), CARRYCASCIN_dly, carrycascout_o_mux, qp_o_mux(47), carryin_o_mux7, carryinsel_o_mux) + begin + case carryinsel_o_mux is + when "000" => carryin_o_mux <= carryin_o_mux0; + when "001" => carryin_o_mux <= NOT PCIN_dly(47); + when "010" => carryin_o_mux <= CARRYCASCIN_dly; + when "011" => carryin_o_mux <= PCIN_dly(47); + when "100" => carryin_o_mux <= carrycascout_o_mux; + when "101" => carryin_o_mux <= NOT qp_o_mux(47); + when "110" => carryin_o_mux <= carryin_o_mux7; + when "111" => carryin_o_mux <= qp_o_mux(47); + when others => null; + end case; + end process prcs_carryin_mux; +--#################################################################### +--##### ALU ##### +--#################################################################### + prcs_alu:process(muxx_o_mux, muxy_o_mux, muxz_o_mux, alumode_o_mux, opmode_o_mux, carryin_o_mux, output_x_sig) + + variable opmode_alu_var : std_logic_vector(5 downto 0) := (others => '0'); + variable alu_full_tmp : std_logic_vector(MAX_ALU_FULL downto 0) := (others => '0'); + variable alu_hlf1_tmp, alu_hlf2_tmp : std_logic_vector(MAX_ALU_HALF downto 0) := (others => '0'); + variable alu_qrt1_tmp, alu_qrt2_tmp, alu_qrt3_tmp, alu_qrt4_tmp : std_logic_vector(MAX_ALU_QUART downto 0) := (others => '0'); + + begin + if(output_x_sig = '1') then + alu_o <= (others => 'X'); + + elsif(opmode_valid_flg) then + opmode_alu_var := opmode_o_mux(3 downto 2) & alumode_o_mux; + case opmode_alu_var is + --------------------------------- + ------------- ADD --------------- + --------------------------------- + when "000000" | "010000" | "100000" | "110000" => + + AluFunction <= ADD_ALU; + alumode_valid_flg <= true; + + if((USE_SIMD = "ONE48") or (USE_SIMD = "one48")) then + alu_full_tmp := (('0'&muxz_o_mux) + + ('0'&muxx_o_mux) + + ('0'&muxy_o_mux) + carryin_o_mux); + alu_o <= alu_full_tmp(MSB_ALU_FULL downto 0); + + carrycascout_o <= alu_full_tmp(MAX_ALU_FULL); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= alu_full_tmp(MAX_ALU_FULL); + carryout_o(MSB_CARRYOUT - 1) <= 'X'; + carryout_o(MSB_CARRYOUT - 2) <= 'X'; + carryout_o(MSB_CARRYOUT - 3) <= 'X'; + end if; + + elsif((USE_SIMD = "TWO24") or (USE_SIMD = "two24")) then + alu_hlf1_tmp := (('0'&muxz_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + ('0'&muxx_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + ('0'&muxy_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + carryin_o_mux); + alu_hlf2_tmp := (('0'&muxz_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) + + ('0'&muxx_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) + + ('0'&muxy_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF)))); + alu_o <= (alu_hlf2_tmp(MSB_ALU_HALF downto 0) & alu_hlf1_tmp(MSB_ALU_HALF downto 0)) ; + + carrycascout_o <= alu_hlf2_tmp(MAX_ALU_HALF); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= alu_hlf2_tmp(MAX_ALU_HALF); + carryout_o(MSB_CARRYOUT - 1) <= 'X'; + carryout_o(MSB_CARRYOUT - 2) <= alu_hlf1_tmp(MAX_ALU_HALF); + carryout_o(MSB_CARRYOUT - 3) <= 'X'; + end if; + + elsif((USE_SIMD = "FOUR12") or (USE_SIMD = "four12")) then + alu_qrt1_tmp := (('0'&muxz_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + ('0'&muxx_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + ('0'&muxy_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + carryin_o_mux); + alu_qrt2_tmp := (('0'&muxz_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) + + ('0'&muxx_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART)))); + alu_qrt3_tmp := (('0'&muxz_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) + + ('0'&muxx_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART)))); + alu_qrt4_tmp := (('0'&muxz_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) + + ('0'&muxx_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART)))); + + alu_o <= (alu_qrt4_tmp(MSB_ALU_QUART downto 0) & alu_qrt3_tmp(MSB_ALU_QUART downto 0) & + alu_qrt2_tmp(MSB_ALU_QUART downto 0) & alu_qrt1_tmp(MSB_ALU_QUART downto 0)); + + carrycascout_o <= alu_qrt4_tmp(MAX_ALU_QUART); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= alu_qrt4_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 1) <= alu_qrt3_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 2) <= alu_qrt2_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 3) <= alu_qrt1_tmp(MAX_ALU_QUART); + end if; + + else + assert false + report "Attribute Syntax Error: The legal values for USE_SIMD are ONE48 or TWO24 or FOUR12." + severity Failure; + end if; + + --------------------------------- + ------ SUBTRACT (X + ~Z ) ---- carryin must be 1 --------------- + --------------------------------- + when "000001" | "010001" | "100001" | "110001" => + + AluFunction <= ADD_XY_NOTZ_ALU; + alumode_valid_flg <= true; + + if((USE_SIMD = "ONE48") or (USE_SIMD = "one48")) then + alu_full_tmp := NOT('0'&muxz_o_mux) + + ('0'&muxx_o_mux) + + ('0'&muxy_o_mux) + carryin_o_mux; + alu_o <= alu_full_tmp(MSB_ALU_FULL downto 0); + + carrycascout_o <= NOT alu_full_tmp(MAX_ALU_FULL); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= NOT alu_full_tmp(MAX_ALU_FULL); + carryout_o(MSB_CARRYOUT - 1) <= 'X'; + carryout_o(MSB_CARRYOUT - 2) <= 'X'; + carryout_o(MSB_CARRYOUT - 3) <= 'X'; + end if; + + elsif((USE_SIMD = "TWO24") or (USE_SIMD = "two24")) then + alu_hlf1_tmp := NOT('0'&muxz_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + ('0'&muxx_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + ('0'&muxy_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + carryin_o_mux; + alu_hlf2_tmp := NOT('0'&muxz_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) + + ('0'&muxx_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) + + ('0'&muxy_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))); + + alu_o <= (alu_hlf2_tmp(MSB_ALU_HALF downto 0) & alu_hlf1_tmp(MSB_ALU_HALF downto 0)) ; + + carrycascout_o <= NOT alu_hlf2_tmp(MAX_ALU_HALF); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= NOT alu_hlf2_tmp(MAX_ALU_HALF); + carryout_o(MSB_CARRYOUT - 1) <= 'X'; + carryout_o(MSB_CARRYOUT - 2) <= NOT alu_hlf1_tmp(MAX_ALU_HALF); + carryout_o(MSB_CARRYOUT - 3) <= 'X'; + end if; + + elsif((USE_SIMD = "FOUR12") or (USE_SIMD = "four12")) then + alu_qrt1_tmp := NOT('0'&muxz_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + ('0'&muxx_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + ('0'&muxy_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + carryin_o_mux; + alu_qrt2_tmp := NOT('0'&muxz_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) + + ('0'&muxx_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))); + alu_qrt3_tmp := NOT('0'&muxz_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) + + ('0'&muxx_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))); + alu_qrt4_tmp := NOT('0'&muxz_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) + + ('0'&muxx_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))); + + alu_o <= (alu_qrt4_tmp(MSB_ALU_QUART downto 0) & alu_qrt3_tmp(MSB_ALU_QUART downto 0) & + alu_qrt2_tmp(MSB_ALU_QUART downto 0) & alu_qrt1_tmp(MSB_ALU_QUART downto 0)); + + carrycascout_o <= NOT alu_qrt4_tmp(MAX_ALU_QUART); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= NOT alu_qrt4_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 1) <= NOT alu_qrt3_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 2) <= NOT alu_qrt2_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 3) <= NOT alu_qrt1_tmp(MAX_ALU_QUART); + end if; + + else + assert false + report "Attribute Syntax Error: The legal values for USE_SIMD are ONE48 or TWO24 or FOUR12." + severity Failure; + end if; + + --------------------------------- + ---------- NOT (X + Y + Z + C) ---------- + --------------------------------- + when "000010" | "010010" | "100010" | "110010" => + + AluFunction <= NOT_XYZC_ALU; + alumode_valid_flg <= true; + + if((USE_SIMD = "ONE48") or (USE_SIMD = "one48")) then + alu_full_tmp := NOT((('0'&muxz_o_mux) + + ('0'&muxx_o_mux) + + ('0'&muxy_o_mux) + carryin_o_mux)); + + alu_o <= alu_full_tmp(MSB_ALU_FULL downto 0); + + carrycascout_o <= NOT alu_full_tmp(MAX_ALU_FULL); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= NOT alu_full_tmp(MAX_ALU_FULL); + carryout_o(MSB_CARRYOUT - 1) <= 'X'; + carryout_o(MSB_CARRYOUT - 2) <= 'X'; + carryout_o(MSB_CARRYOUT - 3) <= 'X'; + end if; + + elsif((USE_SIMD = "TWO24") or (USE_SIMD = "two24")) then + alu_hlf1_tmp := NOT((('0'&muxz_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + ('0'&muxx_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + ('0'&muxy_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + carryin_o_mux)); + alu_hlf2_tmp := NOT((('0'&muxz_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) + + ('0'&muxx_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) + + ('0'&muxy_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))))); + + alu_o <= (alu_hlf2_tmp(MSB_ALU_HALF downto 0) & alu_hlf1_tmp(MSB_ALU_HALF downto 0)) ; + + carrycascout_o <= NOT alu_hlf2_tmp(MAX_ALU_HALF); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= NOT alu_hlf2_tmp(MAX_ALU_HALF); + carryout_o(MSB_CARRYOUT - 1) <= 'X'; + carryout_o(MSB_CARRYOUT - 2) <= NOT alu_hlf1_tmp(MAX_ALU_HALF); + carryout_o(MSB_CARRYOUT - 3) <= 'X'; + end if; + + elsif((USE_SIMD = "FOUR12") or (USE_SIMD = "four12")) then + alu_qrt1_tmp := NOT((('0'&muxz_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + ('0'&muxx_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + ('0'&muxy_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + carryin_o_mux)); + alu_qrt2_tmp := NOT((('0'&muxz_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) + + ('0'&muxx_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))))); + alu_qrt3_tmp := NOT((('0'&muxz_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) + + ('0'&muxx_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))))); + alu_qrt4_tmp := NOT((('0'&muxz_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) + + ('0'&muxx_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))))); + + alu_o <= (alu_qrt4_tmp(MSB_ALU_QUART downto 0) & alu_qrt3_tmp(MSB_ALU_QUART downto 0) & + alu_qrt2_tmp(MSB_ALU_QUART downto 0) & alu_qrt1_tmp(MSB_ALU_QUART downto 0)); + + carrycascout_o <= NOT alu_qrt4_tmp(MAX_ALU_QUART); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= NOT alu_qrt4_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 1) <= NOT alu_qrt3_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 2) <= NOT alu_qrt2_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 3) <= NOT alu_qrt1_tmp(MAX_ALU_QUART); + end if; + + else + assert false + report "Attribute Syntax Error: The legal values for USE_SIMD are ONE48 or TWO24 or FOUR12." + severity Failure; + end if; + + --------------------------------- + ------- SUBTRACT (Z - X ) ------- + --------------------------------- + when "000011" | "010011" | "100011" | "110011"=> + AluFunction <= SUBTRACT_ALU; + alumode_valid_flg <= true; + + if((USE_SIMD = "ONE48") or (USE_SIMD = "one48")) then + alu_full_tmp := (('0'&muxz_o_mux) - + (('0'&muxx_o_mux) + + ('0'&muxy_o_mux) + carryin_o_mux)); + + alu_o <= alu_full_tmp(MSB_ALU_FULL downto 0); + + carrycascout_o <= alu_full_tmp(MAX_ALU_FULL); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= NOT alu_full_tmp(MAX_ALU_FULL); + carryout_o(MSB_CARRYOUT - 1) <= 'X'; + carryout_o(MSB_CARRYOUT - 2) <= 'X'; + carryout_o(MSB_CARRYOUT - 3) <= 'X'; + end if; + + elsif((USE_SIMD = "TWO24") or (USE_SIMD = "two24")) then + alu_hlf1_tmp := (('0'&muxz_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) - + (('0'&muxx_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + ('0'&muxy_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + carryin_o_mux)); + alu_hlf2_tmp := (('0'&muxz_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) - + (('0'&muxx_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) + + ('0'&muxy_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))))); + + alu_o <= (alu_hlf2_tmp(MSB_ALU_HALF downto 0) & alu_hlf1_tmp(MSB_ALU_HALF downto 0)) ; + + carrycascout_o <= alu_hlf2_tmp(MAX_ALU_HALF); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= NOT alu_hlf2_tmp(MAX_ALU_HALF); + carryout_o(MSB_CARRYOUT - 1) <= 'X'; + carryout_o(MSB_CARRYOUT - 2) <= NOT alu_hlf1_tmp(MAX_ALU_HALF); + carryout_o(MSB_CARRYOUT - 3) <= 'X'; + end if; + + elsif((USE_SIMD = "FOUR12") or (USE_SIMD = "four12")) then + alu_qrt1_tmp := (('0'&muxz_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) - + (('0'&muxx_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + ('0'&muxy_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + carryin_o_mux)); + alu_qrt2_tmp := (('0'&muxz_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) - + (('0'&muxx_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))))); + alu_qrt3_tmp := (('0'&muxz_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) - + (('0'&muxx_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))))); + alu_qrt4_tmp := (('0'&muxz_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) - + (('0'&muxx_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))))); + + alu_o <= (alu_qrt4_tmp(MSB_ALU_QUART downto 0) & alu_qrt3_tmp(MSB_ALU_QUART downto 0) & + alu_qrt2_tmp(MSB_ALU_QUART downto 0) & alu_qrt1_tmp(MSB_ALU_QUART downto 0)); + + carrycascout_o <= alu_qrt4_tmp(MAX_ALU_QUART); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= NOT alu_qrt4_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 1) <= NOT alu_qrt3_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 2) <= NOT alu_qrt2_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 3) <= NOT alu_qrt1_tmp(MAX_ALU_QUART); + end if; + + else + assert false + report "Attribute Syntax Error: The legal values for USE_SIMD are ONE48 or TWO24 or FOUR12." + severity Failure; + end if; + + --------------------------------- + ------------- XOR --------------- + --------------------------------- + when "000100" | "000111" | "100101" | "100110" => + AluFunction <= XOR_ALU; + alumode_valid_flg <= true; + alu_o <= muxx_o_mux xor muxz_o_mux; + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + --------------------------------- + ------------- XNOR --------------- + --------------------------------- + when "000101" | "000110" | "100100" | "100111" => + AluFunction <= XNOR_ALU; + alumode_valid_flg <= true; + alu_o <= muxx_o_mux xnor muxz_o_mux; + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + --------------------------------- + ------------- AND --------------- + --------------------------------- + when "001100" => + AluFunction <= AND_ALU; + alumode_valid_flg <= true; + alu_o <= muxx_o_mux and muxz_o_mux; + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + --------------------------------- + --------- X AND (NOT Z) --------- + --------------------------------- + when "001101" => + AluFunction <= X_AND_NOT_Z_ALU; + alumode_valid_flg <= true; + alu_o <= muxx_o_mux and (not muxz_o_mux); + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + --------------------------------- + ------------- NAND --------------- + --------------------------------- + when "001110" => + AluFunction <= NAND_ALU; + alumode_valid_flg <= true; + alu_o <= muxx_o_mux nand muxz_o_mux; + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + --------------------------------- + -------- - (NOT X) OR Z --------- + --------------------------------- + when "001111" => + AluFunction <= NOT_X_OR_Z_ALU; + alumode_valid_flg <= true; + alu_o <= (not muxx_o_mux) or muxz_o_mux; + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + --------------------------------- + -------------- OR --------------- + --------------------------------- + when "101100" => + AluFunction <= OR_ALU; + alumode_valid_flg <= true; + alu_o <= muxx_o_mux or muxz_o_mux; + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + --------------------------------- + --------- X OR (NOT Z) --------- + --------------------------------- + when "101101" => + AluFunction <= X_OR_NOT_Z_ALU; + alumode_valid_flg <= true; + alu_o <= muxx_o_mux or (not muxz_o_mux); + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + --------------------------------- + ------------ X NOR Z ------------ + --------------------------------- + when "101110" => + AluFunction <= X_NOR_Z_ALU; + alumode_valid_flg <= true; + alu_o <= muxx_o_mux nor muxz_o_mux; + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + --------------------------------- + --------- (NOT X) and Z --------- + --------------------------------- + when "101111" => + AluFunction <= NOT_X_AND_Z_ALU; + alumode_valid_flg <= true; + alu_o <= (not muxx_o_mux) and muxz_o_mux; + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + + when others => + AluFunction <= INVALID_ALU; + alumode_valid_flg <= false; + + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + end case; + end if; + end process prcs_alu; +--#################################################################### +--##### CARRYOUT and CARRYCASCOUT ##### +--#################################################################### + prcs_carry_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + carryout_o_reg <= ( others => '0'); + carrycascout_o_reg <= '0'; + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if((RSTP_dly = '1') or + ((AUTORESET_PATTERN_DETECT) and ( + ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and pdet_o_reg1 = '1') or + ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and (pdet_o_reg2 = '1' and pdet_o_reg1 = '0'))) + ) + ) then + carryout_o_reg <= ( others => '0'); + carrycascout_o_reg <= '0'; + elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then + carryout_o_reg <= carryout_o; + carrycascout_o_reg <= carrycascout_o; + end if; + end if; + end if; + end process prcs_carry_reg; +------------------------------------------------------------------ + prcs_carryout_mux:process(carryout_o, carryout_o_reg) + begin + case PREG is + when 0 => carryout_o_mux <= carryout_o; + when 1 => carryout_o_mux <= carryout_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for PREG are 0 or 1" + severity Failure; + end case; + + end process prcs_carryout_mux; + +------------------------------------------------------------------ + prcs_carryout_x_o:process(carryout_o_mux) + begin + if(USE_SIMD = "ONE48") then + carryout_x_o(3) <= carryout_o_mux(3); + elsif(USE_SIMD = "TWO24") then + carryout_x_o(3) <= carryout_o_mux(3); + carryout_x_o(1) <= carryout_o_mux(1); + elsif(USE_SIMD = "FOUR12") then + carryout_x_o(3) <= carryout_o_mux(3); + carryout_x_o(2) <= carryout_o_mux(2); + carryout_x_o(1) <= carryout_o_mux(1); + carryout_x_o(0) <= carryout_o_mux(0); + end if; + end process prcs_carryout_x_o; + +------------------------------------------------------------------ + prcs_carrycascout_mux:process(carrycascout_o, carrycascout_o_reg) + begin + case PREG is + when 0 => carrycascout_o_mux <= carrycascout_o; + when 1 => carrycascout_o_mux <= carrycascout_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for PREG are 0 or 1" + severity Failure; + end case; + + end process prcs_carrycascout_mux; +------------------------------------------------------------------ +-- CR 219047 (2) + prcs_multsignout_o_opmode:process(mult_o_mux(MSB_A_MULT+MSB_B_MULT+1), opmode_o_mux(3 downto 0)) + begin + if(opmode_o_mux(3 downto 0) = "0101") then + multsignout_o_opmode <= mult_o_mux(MSB_A_MULT+MSB_B_MULT+1); + else + multsignout_o_opmode <= 'X'; + end if; + end process prcs_multsignout_o_opmode; + + prcs_multsignout_o_mux:process(multsignout_o_opmode, multsignout_o_reg) + begin + case PREG is + when 0 => multsignout_o_mux <= multsignout_o_opmode; +-- CR 232275 + when 1 => multsignout_o_mux <= multsignout_o_reg; + when others => null; +-- assert false +-- report "Attribute Syntax Error: The allowed values for PREG are 0 or 1" +-- severity Failure; + end case; + + end process prcs_multsignout_o_mux; +--#################################################################### +--#################################################################### +--#################################################################### +--##### PCOUT and MULTSIGNOUT ##### +--#################################################################### + prcs_qp_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qp_o_reg <= ( others => '0'); + multsignout_o_reg <= '0'; + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if((RSTP_dly = '1') or + ((AUTORESET_PATTERN_DETECT) and ( + ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and pdet_o_reg1 = '1') or + ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and (pdet_o_reg2 = '1' and pdet_o_reg1 = '0'))) + ) + ) then + qp_o_reg <= ( others => '0'); + multsignout_o_reg <= '0'; + elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then + qp_o_reg <= alu_o; + multsignout_o_reg <= mult_o_reg((MSB_A_MULT+MSB_B_MULT+1)); + end if; + end if; + end if; + end process prcs_qp_reg; +------------------------------------------------------------------ + prcs_qp_mux:process(alu_o, qp_o_reg) + begin + case PREG is + when 0 => qp_o_mux <= alu_o; + when 1 => qp_o_mux <= qp_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for PREG are 0 or 1" + severity Failure; + end case; + + end process prcs_qp_mux; +--#################################################################### +--##### Pattern Detector ##### +--#################################################################### + prcs_sel_pattern_detect:process(alu_o, qc_o_mux) + begin + + -- Select the pattern + if((SEL_PATTERN = "PATTERN") or (SEL_PATTERN = "pattern")) then + pattern_qp <= To_StdLogicVector(PATTERN); + elsif((SEL_PATTERN = "C") or (SEL_PATTERN = "c")) then + pattern_qp <= qc_o_mux; + else + assert false + report "Attribute Syntax Error: The attribute SEL_PATTERN on DSP48_ALU is incorrect. Legal values for this attribute are PATTERN or C" + severity Failure; + end if; + + -- Select the mask -- if ROUNDING MASK set, use rounding mode, else use SEL_MASK + if((SEL_ROUNDING_MASK = "SEL_MASK") or (SEL_ROUNDING_MASK = "sel_mask")) then + if((SEL_MASK = "MASK") or (SEL_MASK = "mask")) then + mask_qp <= To_StdLogicVector(MASK); + elsif((SEL_MASK = "C") or (SEL_MASK = "c")) then + mask_qp <= qc_o_mux; + else + assert false + report "Attribute Syntax Error: The attribute SEL_MASK on DSP48_ALU is incorrect. Legal values for this attribute are MASK or C" + severity Failure; + end if; + elsif((SEL_ROUNDING_MASK = "MODE1") or (SEL_ROUNDING_MASK = "mode1")) then + mask_qp <= To_StdLogicVector((To_bitvector( not qc_o_mux)) sla 1) ; + mask_qp (0) <= '0'; + elsif((SEL_ROUNDING_MASK = "MODE2") or (SEL_ROUNDING_MASK = "mode2")) then + mask_qp <= To_StdLogicVector((To_bitvector( not qc_o_mux)) sla 2) ; + mask_qp (1 downto 0) <= (others => '0'); + else + assert false + report "Attribute Syntax Error: The attribute SEL_ROUNDING_MASK on DSP48_ALU is incorrect. Legal values for this attribute are SEL_MASK or MODE1 or MODE2." + severity Failure; + end if; + + end process prcs_sel_pattern_detect; + + +--------------------------------------------------------------- + + prcs_pdet:process(alu_o, mask_qp, pattern_qp, GSR_dly ) + begin + if(((alu_o or mask_qp) = (pattern_qp or mask_qp)) and (GSR_dly = '0'))then + pdet_o <= '1'; + else + pdet_o <= '0'; + end if; + + if(((alu_o or mask_qp) = ((NOT pattern_qp) or mask_qp)) and (GSR_dly = '0')) then + pdetb_o <= '1'; + else + pdetb_o <= '0'; + end if; + + end process prcs_pdet; + +--------------------------------------------------------------- + + prcs_pdet_reg:process(CLK_dly, GSR_dly) + variable pdetb_reg1_var, pdetb_reg2_var, pdet_reg1_var, pdet_reg2_var : std_ulogic := '0'; + begin + if(GSR_dly = '1') then + pdetb_o_reg1 <= '0'; + pdetb_o_reg2 <= '0'; + pdet_o_reg1 <= '0'; + pdet_o_reg2 <= '0'; + + pdetb_reg1_var := '0'; + pdetb_reg2_var := '0'; + pdet_reg1_var := '0'; + pdet_reg2_var := '0'; + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if((RSTP_dly = '1') or + ((AUTORESET_PATTERN_DETECT) and ( + ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and pdet_o_reg1 = '1') or + ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and (pdet_o_reg2 = '1' and pdet_o_reg1 = '0'))) + ) + ) then + pdetb_o_reg1 <= '0'; + pdetb_o_reg2 <= '0'; + pdet_o_reg1 <= '0'; + pdet_o_reg2 <= '0'; + + pdetb_reg1_var := '0'; + pdetb_reg2_var := '0'; + pdet_reg1_var := '0'; + pdet_reg2_var := '0'; + elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then + pdetb_reg2_var := pdetb_reg1_var; + pdetb_reg1_var := pdetb_o; + + pdet_reg2_var := pdet_reg1_var; + pdet_reg1_var := pdet_o; + + pdetb_o_reg1 <= pdetb_reg1_var; + pdetb_o_reg2 <= pdetb_reg2_var; + pdet_o_reg1 <= pdet_reg1_var; + pdet_o_reg2 <= pdet_reg2_var; + + end if; + end if; + end if; + end process prcs_pdet_reg; + +--#################################################################### +--##### Underflow / Overflow ##### +--#################################################################### + prcs_uflow_oflow:process(pdet_o_reg1 , pdet_o_reg2 , pdetb_o_reg1 , pdetb_o_reg2) + begin +-- if(((AUTORESET_PATTERN_DETECT) and ( +-- ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and (pdet_o_reg1 = '1')) or +-- ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and ((pdet_o_reg2 = '1') and (pdet_o_reg1 = '0')))) +-- )) then +-- underflow_o <= '0'; +-- overflow_o <= '0'; +-- else +-- overflow_o <= pdet_o_reg2 AND (NOT pdet_o_reg1) AND (NOT pdetb_o_reg1); +-- underflow_o <= pdetb_o_reg2 AND (NOT pdet_o_reg1) AND (NOT pdetb_o_reg1); +-- end if; + if(GSR_dly = '1') then + overflow_o <= '0'; + underflow_o <= '0'; + elsif(USE_PATTERN_DETECT = "NO_PATDET") then + overflow_o <= 'X'; + underflow_o <= 'X'; + elsif(PREG = 0) then + overflow_o <= 'X'; + underflow_o <= 'X'; + elsif(PREG = 1) then + overflow_o <= pdet_o_reg2 AND (NOT pdet_o_reg1) AND (NOT pdetb_o_reg1); + underflow_o <= pdetb_o_reg2 AND (NOT pdet_o_reg1) AND (NOT pdetb_o_reg1); + end if; + + end process prcs_uflow_oflow; +--#################################################################### +--##### OPMODE DRC ##### +--#################################################################### + prcs_opmode_drc:process(ping_opmode_drc_check, alumode_o_mux, opmode_o_mux, carryinsel_o_mux) + variable Message : line; + variable invalid_opmode_flg : boolean := true; + variable opmode_valid_var : boolean := true; + variable opmode_carryinsel_var : std_logic_vector(9 downto 0) := (others => '0'); + begin + opmode_carryinsel_var := opmode_o_mux & carryinsel_o_mux(MSB_CARRYINSEL downto 0); + case alumode_o_mux(3 downto 2) is +----------------------------------------- +-- ARITHMETIC MODES DRC -- +----------------------------------------- + when "00" => + case opmode_carryinsel_var is + when "0000000000" => + OPMODE_NUMBER <= 1; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0000010000" => + OPMODE_NUMBER <= 3; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0000010010" => + OPMODE_NUMBER <= 4; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; +-- CR 455601 eased the following two + when "0000010101" => + OPMODE_NUMBER <= 50; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0000010111" => + OPMODE_NUMBER <= 50; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; +-- + when "0000011000" => + OPMODE_NUMBER <= 7; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0000011010" => + OPMODE_NUMBER <= 8; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0000011100" => + OPMODE_NUMBER <= 9; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0000101000" => + OPMODE_NUMBER <= 13; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0001000000" => + OPMODE_NUMBER <= 15; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0001010000" => + OPMODE_NUMBER <= 17; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0001010010" => + OPMODE_NUMBER <= 18; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0001011000" => + OPMODE_NUMBER <= 21; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0001011010" => + OPMODE_NUMBER <= 22; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0001011100" => + OPMODE_NUMBER <= 23; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0001100000" => + OPMODE_NUMBER <= 27; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0001100010" => + OPMODE_NUMBER <= 28; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0001100100" => + OPMODE_NUMBER <= 29; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0001110000" => + OPMODE_NUMBER <= 33; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0001110010" => + OPMODE_NUMBER <= 34; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0001110101" => + OPMODE_NUMBER <= 37; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0001110111" => + OPMODE_NUMBER <= 37; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0001111000" => + OPMODE_NUMBER <= 38; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0001111010" => + OPMODE_NUMBER <= 39; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0001111100" => + OPMODE_NUMBER <= 40; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0010000000" => + OPMODE_NUMBER <= 46; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0010010000" => + OPMODE_NUMBER <= 48; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0010010101" => + OPMODE_NUMBER <= 50; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0010010111" => + OPMODE_NUMBER <= 50; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0010011000" => + OPMODE_NUMBER <= 51; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0010011001" => + OPMODE_NUMBER <= 53; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0010011011" => + OPMODE_NUMBER <= 53; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0010101000" => + OPMODE_NUMBER <= 55; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0010101001" => + OPMODE_NUMBER <= 57; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0010101011" => + OPMODE_NUMBER <= 57; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0010101110" => + OPMODE_NUMBER <= 58; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0011000000" => + OPMODE_NUMBER <= 59; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0011010000" => + OPMODE_NUMBER <= 61; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0011010101" => + OPMODE_NUMBER <= 63; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0011010111" => + OPMODE_NUMBER <= 63; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0011011000" => + OPMODE_NUMBER <= 64; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0011011001" => + OPMODE_NUMBER <= 66; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0011011011" => + OPMODE_NUMBER <= 66; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0011100000" => + OPMODE_NUMBER <= 68; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0011100001" => + OPMODE_NUMBER <= 70; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0011100011" => + OPMODE_NUMBER <= 70; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0011110000" => + OPMODE_NUMBER <= 72; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0011110101" => + OPMODE_NUMBER <= 74; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0011110111" => + OPMODE_NUMBER <= 74; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0011110001" => + OPMODE_NUMBER <= 75; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0011110011" => + OPMODE_NUMBER <= 75; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0011111000" => + OPMODE_NUMBER <= 77; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0011111001" => + OPMODE_NUMBER <= 79; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0011111011" => + OPMODE_NUMBER <= 79; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0100000000" => + OPMODE_NUMBER <= 82; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0100000010" => + OPMODE_NUMBER <= 83; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0100010000" => + OPMODE_NUMBER <= 86; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0100010010" => + OPMODE_NUMBER <= 87; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0100011000" => + OPMODE_NUMBER <= 90; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0100011010" => + OPMODE_NUMBER <= 91; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0100011101" => + OPMODE_NUMBER <= 94; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0100011111" => + OPMODE_NUMBER <= 94; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0100101000" => + OPMODE_NUMBER <= 95; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0100101101" => + OPMODE_NUMBER <= 97; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0100101111" => + OPMODE_NUMBER <= 97; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0101000000" => + OPMODE_NUMBER <= 98; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0101000010" => + OPMODE_NUMBER <= 99; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0101010000" => + OPMODE_NUMBER <= 102; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0101011000" => + OPMODE_NUMBER <= 104; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0101011101" => + OPMODE_NUMBER <= 106; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0101011111" => + OPMODE_NUMBER <= 106; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0101100000" => + OPMODE_NUMBER <= 107; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0101100010" => + OPMODE_NUMBER <= 108; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0101100101" => + OPMODE_NUMBER <= 111; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0101100111" => + OPMODE_NUMBER <= 111; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0101110000" => + OPMODE_NUMBER <= 112; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0101110101" => + OPMODE_NUMBER <= 114; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0101110111" => + OPMODE_NUMBER <= 114; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0101111000" => + OPMODE_NUMBER <= 115; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0101111101" => + OPMODE_NUMBER <= 117; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0101111111" => + OPMODE_NUMBER <= 117; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0110000000" => + OPMODE_NUMBER <= 120; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0110000010" => + OPMODE_NUMBER <= 121; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0110000100" => + OPMODE_NUMBER <= 122; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0110010000" => + OPMODE_NUMBER <= 126; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0110010010" => + OPMODE_NUMBER <= 127; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0110010101" => + OPMODE_NUMBER <= 130; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0110010111" => + OPMODE_NUMBER <= 130; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0110011000" => + OPMODE_NUMBER <= 131; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0110011010" => + OPMODE_NUMBER <= 132; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0110011100" => + OPMODE_NUMBER <= 133; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0110101000" => + OPMODE_NUMBER <= 139; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0110101110" => + OPMODE_NUMBER <= 141; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0111000000" => + OPMODE_NUMBER <= 143; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0111000010" => + OPMODE_NUMBER <= 144; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0111000100" => + OPMODE_NUMBER <= 145; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0111010000" => + OPMODE_NUMBER <= 149; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0111010101" => + OPMODE_NUMBER <= 151; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0111010111" => + OPMODE_NUMBER <= 151; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0111011000" => + OPMODE_NUMBER <= 152; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0111100000" => + OPMODE_NUMBER <= 156; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0111100010" => + OPMODE_NUMBER <= 157; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0111110000" => + OPMODE_NUMBER <= 160; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0111111000" => + OPMODE_NUMBER <= 162; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1001000010" => + OPMODE_NUMBER <= 165; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1010000000" => + OPMODE_NUMBER <= 167; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1010010000" => + OPMODE_NUMBER <= 169; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1010010101" => + OPMODE_NUMBER <= 171; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1010010111" => + OPMODE_NUMBER <= 171; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1010011000" => + OPMODE_NUMBER <= 172; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1010011001" => + OPMODE_NUMBER <= 174; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1010011011" => + OPMODE_NUMBER <= 174; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1010101000" => + OPMODE_NUMBER <= 176; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1010101001" => + OPMODE_NUMBER <= 178; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1010101011" => + OPMODE_NUMBER <= 178; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1010101110" => + OPMODE_NUMBER <= 179; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1011000000" => + OPMODE_NUMBER <= 180; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1011010000" => + OPMODE_NUMBER <= 182; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1011010101" => + OPMODE_NUMBER <= 184; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1011010111" => + OPMODE_NUMBER <= 184; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1011011000" => + OPMODE_NUMBER <= 185; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1011011001" => + OPMODE_NUMBER <= 187; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1011011011" => + OPMODE_NUMBER <= 187; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1011100000" => + OPMODE_NUMBER <= 189; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1011100001" => + OPMODE_NUMBER <= 191; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1011100011" => + OPMODE_NUMBER <= 191; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1011110000" => + OPMODE_NUMBER <= 193; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1011110101" => + OPMODE_NUMBER <= 195; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1011110111" => + OPMODE_NUMBER <= 195; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1011110001" => + OPMODE_NUMBER <= 197; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1011110011" => + OPMODE_NUMBER <= 197; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1011111000" => + OPMODE_NUMBER <= 198; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1011111001" => + OPMODE_NUMBER <= 200; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1011111011" => + OPMODE_NUMBER <= 200; + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1100000000" => + OPMODE_NUMBER <= 203; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1100010000" => + OPMODE_NUMBER <= 205; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1100011000" => + OPMODE_NUMBER <= 207; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1100011101" => + OPMODE_NUMBER <= 209; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1100011111" => + OPMODE_NUMBER <= 209; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1100101000" => + OPMODE_NUMBER <= 210; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1100101101" => + OPMODE_NUMBER <= 212; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1100101111" => + OPMODE_NUMBER <= 212; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1101000000" => + OPMODE_NUMBER <= 213; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1101010000" => + OPMODE_NUMBER <= 215; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1101011000" => + OPMODE_NUMBER <= 217; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1101011101" => + OPMODE_NUMBER <= 219; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1101011111" => + OPMODE_NUMBER <= 219; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1101100000" => + OPMODE_NUMBER <= 220; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1101100101" => + OPMODE_NUMBER <= 222; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1101100111" => + OPMODE_NUMBER <= 222; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1101110000" => + OPMODE_NUMBER <= 223; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1101110101" => + OPMODE_NUMBER <= 225; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1101110111" => + OPMODE_NUMBER <= 225; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1101111000" => + OPMODE_NUMBER <= 226; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1101111101" => + OPMODE_NUMBER <= 228; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1101111111" => + OPMODE_NUMBER <= 228; + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), slv_to_str(carryinsel_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when others => + OPMODE_NUMBER <= -1; + if(invalid_opmode_flg = true) then + invalid_opmode_flg := false; + opmode_valid_var := false; + output_x_sig <= '1'; +-- CR 444150 + if((opmode_carryinsel_var = "0000000010") and ((OPMODEREG = 1) and (CARRYINSELREG = 0))) then + Write ( Message, string'("DRC Warning : The attribute CARRYINSELREG on DSP48E instance is set to 0. ")); + Write ( Message, string'("It is required to have CARRYINSELREG be set to 1 to match OPMODEREG, ")); + Write ( Message, string'("in order to ensure that the simulation model will match the hardware ")); + Write ( Message, string'("behavior in all use cases.")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end if; + + Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); + Write ( Message, slv_to_str(opmode_o_mux)); + Write ( Message, string'(" to DSP48E instance")); + Write ( Message, string'(" is either invalid or the CARRYINSEL ")); + Write ( Message, slv_to_str(carryinsel_o_mux)); + Write ( Message, string'(" for that specific OPMODE is invalid. ")); + Write ( Message, string'(" This error may be due to mismatch in the OPMODEREG ")); + Write ( Message, string'(" and CARRYINSELREG attribute settings.")); + Write ( Message, string'(" It is recommended that OPMODEREG and CARRYINSELREG always be set to the same value.")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end if; + end case; + when "01" | "11" => +----------------------------------------- +-- LOGIC MODES DRC -- +----------------------------------------- + case opmode_o_mux is + when "0000000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0000010" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0000011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0010000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0010010" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0010011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0100000" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0100010" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0100011" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0110000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0110010" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0110011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1010000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1010010" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1010011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1100000" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1100010" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1100011" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0001000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0001010" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0001011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0011000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0011010" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0011011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0101000" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0101010" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0101011" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0111000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "0111010" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "0111011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1011000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1011010" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1011011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "1101000" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1101010" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "1101011" => + if (PREG /= 1) then + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg_logic(slv_to_str(opmode_o_mux)); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when others => + OPMODE_NUMBER <= -1; + if(invalid_opmode_flg = true) then + invalid_opmode_flg := false; + opmode_valid_var := false; + output_x_sig <= '1'; + Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); + Write ( Message, slv_to_str(opmode_o_mux)); + Write ( Message, string'(" to DSP48E instance")); + Write ( Message, string'(" is invalid for ALU LOGIC modes.")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end if; + end case; + when others => null; + end case; + + opmode_valid_flg <= opmode_valid_var; + + end process prcs_opmode_drc; +--#################################################################### +--##### ZERO_DELAY_OUTPUTS ##### +--#################################################################### + prcs_zero_delay_outputs:process(qacout_o_mux, qbcout_o_mux, carryout_x_o, carrycascout_o_mux, + overflow_o, qp_o_mux, pdet_o, pdetb_o, + pdet_o_reg1, pdetb_o_reg1, + pdet_o_reg2, pdetb_o_reg2, + underflow_o, multsignout_o_mux, opmode_valid_flg, alumode_valid_flg) + begin + ACOUT_zd <= qacout_o_mux; + BCOUT_zd <= qbcout_o_mux; + OVERFLOW_zd <= overflow_o; + UNDERFLOW_zd <= underflow_o; + P_zd <= qp_o_mux; + PCOUT_zd <= qp_o_mux; + MULTSIGNOUT_zd <= multsignout_o_mux; + + if(((AUTORESET_PATTERN_DETECT) and ( + ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and (pdet_o_reg1 = '1')) or + ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and ((pdet_o_reg2 = '1') and (pdet_o_reg1 = '0')))) + )) then + CARRYCASCOUT_zd <= '0'; + CARRYOUT_zd <= (others => '0'); + else + CARRYCASCOUT_zd <= carrycascout_o_mux; + CARRYOUT_zd <= carryout_x_o; + end if; + + if((USE_PATTERN_DETECT = "NO_PATDET") or (not opmode_valid_flg) or (not alumode_valid_flg)) then + PATTERNBDETECT_zd <= 'X'; + PATTERNDETECT_zd <= 'X'; + elsif (PREG = 0) then + PATTERNBDETECT_zd <= pdetb_o; + PATTERNDETECT_zd <= pdet_o; + elsif(PREG = 1) then + PATTERNBDETECT_zd <= pdetb_o_reg1; + PATTERNDETECT_zd <= pdet_o_reg1; + end if; + + end process prcs_zero_delay_outputs; + +end generate; +fast_model : if (SIM_MODE = "FAST") generate +--#################################################################### +--##### Initialization ### +--#################################################################### + prcs_init:process + begin + +----------- Checks for AREG ---------------------- + case AREG is + when 0|1|2 => + when others => + assert false + report "Attribute Syntax Error: The allowed values for AREG are 0 or 1 or 2" + severity Failure; + end case; + +----------- Checks for ACASCREG and (ACASCREG vs AREG) ---------------------- + + case AREG is + when 0 => if(AREG /= ACASCREG) then + assert false + report "Attribute Syntax Error : The attribute ACASCREG on DSP48E has to be set to 0 when attribute AREG = 0." + severity Failure; + end if; + when 1 => if(AREG /= ACASCREG) then + assert false + report "Attribute Syntax Error : The attribute ACASCREG on DSP48E has to be set to 1 when attribute AREG = 1." + severity Failure; + end if; + when 2 => if((AREG /= ACASCREG) and ((AREG-1) /= ACASCREG))then + assert false + report "Attribute Syntax Error : The attribute ACASCREG on DSP48E has to be set to either 2 or 1 when attribute AREG = 2." + severity Failure; + end if; + when others => null; + end case; + +----------- Checks for BREG ---------------------- + case BREG is + when 0|1|2 => + when others => + assert false + report "Attribute Syntax Error: The allowed values for BREG are 0 or 1 or 2" + severity Failure; + end case; + +----------- Checks for BCASCREG and (BCASCREG vs BREG) ---------------------- + + case BREG is + when 0 => if(BREG /= BCASCREG) then + assert false + report "Attribute Syntax Error : The attribute BCASCREG on DSP48E has to be set to 0 when attribute BREG = 0." + severity Failure; + end if; + when 1 => if(BREG /= BCASCREG) then + assert false + report "Attribute Syntax Error : The attribute BCASCREG on DSP48E has to be set to 1 when attribute BREG = 1." + severity Failure; + end if; + when 2 => if((BREG /= BCASCREG) and ((BREG-1) /= BCASCREG))then + assert false + report "Attribute Syntax Error : The attribute BCASCREG on DSP48E has to be set to either 2 or 1 when attribute BREG = 2." + severity Failure; + end if; + when others => null; + end case; + +----------- Check for AUTORESET_OVER_UNDER_FLOW ---------------------- + +-- case AUTORESET_OVER_UNDER_FLOW is +-- when true | false => null; +-- when others => +-- assert false +-- report "Attribute Syntax Error: The allowed values for AUTORESET_OVER_UNDER_FLOW are true or fasle" +-- severity Failure; +-- end case; + +----------- Check for AUTORESET_PATTERN_DETECT ---------------------- + + case AUTORESET_PATTERN_DETECT is + when true | false => null; + when others => + assert false + report "Attribute Syntax Error: The allowed values for AUTORESET_PATTERN_DETECT are true or fasle" + severity Failure; + end case; + +----------- Check for AUTORESET_PATTERN_DETECT_OPTINV ---------------------- + + if((AUTORESET_PATTERN_DETECT_OPTINV /="MATCH") and (AUTORESET_PATTERN_DETECT_OPTINV /="NOT_MATCH")) then + assert false + report "Attribute Syntax Error: The allowed values for AUTORESET_PATTERN_DETECT_OPTINV are MATCH or NOT_MATCH." + severity Failure; + end if; + +----------- Check for USE_MULT ---------------------- + + if((USE_MULT /="NONE") and (USE_MULT /="MULT") and + (USE_MULT /="MULT_S")) then + assert false + report "Attribute Syntax Error: The allowed values for USE_MULT are NONE, MULT or MULT_S." + severity Failure; + elsif((USE_MULT ="MULT") and (MREG /= 0)) then + assert false + report "Attribute Syntax Error: The attribute USE_MULT on DSP48 is set to MULT. This requires attribute MREG to be set to 0." + severity Failure; + elsif((USE_MULT ="MULT_S") and (MREG /= 1)) then + assert false + report "Attribute Syntax Error: The attribute USE_MULT on DSP48 is set to MULT_S. This requires attribute MREG to be set to 1." + severity Failure; + end if; + +----------- Check for USE_PATTERN_DETECT ---------------------- + + if((USE_PATTERN_DETECT /="PATDET") and (USE_PATTERN_DETECT /="NO_PATDET")) then + assert false + report "Attribute Syntax Error: The allowed values for USE_PATTERN_DETECT are PATDET or NO_PATDET." + severity Failure; + end if; + +--********************************************************* +--*** ADDITIONAL DRC +--********************************************************* +-- CR 219407 -- (1) + if((AUTORESET_PATTERN_DETECT = TRUE) and (USE_PATTERN_DETECT = "NO_PATDET")) then + assert false + report "Attribute Syntax Error : The attribute USE_PATTERN_DETECT on DSP48E instance must be set to PATDET in order to use AUTORESET_PATTERN_DETECT equals TRUE. Failure to do so could make timing reports inaccurate. " + severity Warning; + end if; +------------------------------------------------------------ + ping_opmode_drc_check <= '1' after 100010 ps; +------------------------------------------------------------ + + wait; + end process prcs_init; +--#################################################################### +--##### Input Register A with two levels of registers and a mux ### +--#################################################################### + prcs_a_in:process(A_dly, ACIN_dly) + begin + if(A_INPUT ="DIRECT") then + a_o_mux <= A_dly; + elsif(A_INPUT ="CASCADE") then + a_o_mux <= ACIN_dly; + else + assert false + report "Attribute Syntax Error: The allowed values for A_INPUT are DIRECT or CASCADE." + severity Failure; + end if; + end process prcs_a_in; +------------------------------------------------------------------ + prcs_qa_2lvl:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qa_o_reg1 <= ( others => '0'); + qa_o_reg2 <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTA_dly = '1') then + qa_o_reg1 <= ( others => '0'); + qa_o_reg2 <= ( others => '0'); + elsif (RSTA_dly = '0') then + case AREG is + when 1 => + if(CEA2_dly = '1') then + qa_o_reg2 <= a_o_mux; + end if; + when 2 => + if(CEA1_dly = '1') then + qa_o_reg1 <= a_o_mux; + end if; + if(CEA2_dly = '1') then + qa_o_reg2 <= qa_o_reg1; + end if; + when others => null; + end case; + end if; + end if; + end if; + end process prcs_qa_2lvl; +------------------------------------------------------------------ + prcs_qa_o_mux:process(a_o_mux, qa_o_reg2) + begin + case AREG is + when 0 => qa_o_mux <= a_o_mux; + when 1|2 => qa_o_mux <= qa_o_reg2; + when others => + assert false + report "Attribute Syntax Error: The allowed values for AREG are 0 or 1 or 2" + severity Failure; + end case; + end process prcs_qa_o_mux; +------------------------------------------------------------------ + prcs_qacout_o_mux:process(qa_o_mux, qa_o_reg1) + begin + case ACASCREG is + when 1 => case AREG is + when 2 => qacout_o_mux <= qa_o_reg1; + when others => qacout_o_mux <= qa_o_mux; + end case; + when others => qacout_o_mux <= qa_o_mux; + end case; + + end process prcs_qacout_o_mux; +--#################################################################### +--##### Input Register B with two levels of registers and a mux ### +--#################################################################### + prcs_b_in:process(B_dly, BCIN_dly) + begin + if(B_INPUT ="DIRECT") then + b_o_mux <= B_dly; + elsif(B_INPUT ="CASCADE") then + b_o_mux <= BCIN_dly; + else + assert false + report "Attribute Syntax Error: The allowed values for B_INPUT are DIRECT or CASCADE." + severity Failure; + end if; + + end process prcs_b_in; +------------------------------------------------------------------ + prcs_qb_2lvl:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qb_o_reg1 <= ( others => '0'); + qb_o_reg2 <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTB_dly = '1') then + qb_o_reg1 <= ( others => '0'); + qb_o_reg2 <= ( others => '0'); + elsif (RSTB_dly = '0') then + case BREG is + when 1 => + if(CEB2_dly = '1') then + qb_o_reg2 <= b_o_mux; + end if; + when 2 => + if(CEB1_dly = '1') then + qb_o_reg1 <= b_o_mux; + end if; + if(CEB2_dly = '1') then + qb_o_reg2 <= qb_o_reg1; + end if; + when others => null; + end case; + end if; + end if; + end if; + end process prcs_qb_2lvl; +------------------------------------------------------------------ + prcs_qb_o_mux:process(b_o_mux, qb_o_reg2) + begin + case BREG is + when 0 => qb_o_mux <= b_o_mux; + when 1|2 => qb_o_mux <= qb_o_reg2; + when others => + assert false + report "Attribute Syntax Error: The allowed values for BREG are 0 or 1 or 2 " + severity Failure; + end case; + + end process prcs_qb_o_mux; +------------------------------------------------------------------ + prcs_qbcout_o_mux:process(qb_o_mux, qb_o_reg1) + begin + case BCASCREG is + when 1 => case BREG is + when 2 => qbcout_o_mux <= qb_o_reg1; + when others => qbcout_o_mux <= qb_o_mux; + end case; + when others => qbcout_o_mux <= qb_o_mux; + end case; + end process prcs_qbcout_o_mux; + +--#################################################################### +--##### Input Register C with 0, 1, level of registers ##### +--#################################################################### + prcs_qc_1lvl:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qc_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTC_dly = '1') then + qc_o_reg <= ( others => '0'); + elsif ((RSTC_dly = '0') and (CEC_dly = '1')) then + qc_o_reg <= C_dly; + end if; + end if; + end if; + end process prcs_qc_1lvl; +------------------------------------------------------------------ + prcs_qc_o_mux:process(C_dly, qc_o_reg) + begin + case CREG is + when 0 => qc_o_mux <= C_dly; + when 1 => qc_o_mux <= qc_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for CREG are 0 or 1" + severity Failure; + end case; + end process prcs_qc_o_mux; + +--#################################################################### +--################### 25x18 Multiplier ###################### +--#################################################################### +-- +-- 05/26/05 -- FP -- Added warning for invalid mult when USE_MULT=NONE +-- SIMD=FOUR12 and SIMD=TWO24 +-- Made mult_o to be "X" +-- + prcs_mult:process(qa_o_mux, qb_o_mux) + begin + if(USE_MULT /= "NONE") then + mult_o_int <= qa_o_mux(MSB_A_MULT downto 0) * qb_o_mux (MSB_B_MULT downto 0); + end if; + end process prcs_mult; +------------------------------------------------------------------ + prcs_mult_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + mult_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTM_dly = '1') then + mult_o_reg <= ( others => '0'); + elsif ((RSTM_dly = '0') and (CEM_dly = '1')) then + mult_o_reg <= mult_o_int; + end if; + end if; + end if; + end process prcs_mult_reg; +------------------------------------------------------------------ + prcs_mult_mux:process(mult_o_reg, mult_o_int) + begin + case MREG is + when 0 => mult_o_mux <= mult_o_int; + when 1 => mult_o_mux <= mult_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for MREG are 0 or 1" + severity Failure; + end case; + end process prcs_mult_mux; + +--#################################################################### +--##### OpMode ##### +--#################################################################### + prcs_opmode_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + opmode_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTCTRL_dly = '1') then + opmode_o_reg <= ( others => '0'); + elsif ((RSTCTRL_dly = '0') and (CECTRL_dly = '1')) then + opmode_o_reg <= OPMODE_dly; + end if; + end if; + end if; + end process prcs_opmode_reg; +------------------------------------------------------------------ + prcs_opmode_mux:process(opmode_o_reg, OPMODE_dly) + begin + case OPMODEREG is + when 0 => opmode_o_mux <= OPMODE_dly; + when 1 => opmode_o_mux <= opmode_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for OPMODEREG are 0 or 1" + severity Failure; + end case; + end process prcs_opmode_mux; +--#################################################################### +--##### MUX_XYZ ##### +--#################################################################### + prcs_mux_xyz:process(opmode_o_mux, qp_o_mux, qa_o_mux, qb_o_mux, mult_o_mux, + qc_o_mux, PCIN_dly, output_x_sig) + begin + if(output_x_sig = '1') then + muxx_o_mux(MSB_P downto 0) <= ( others => 'X'); + muxy_o_mux(MSB_P downto 0) <= ( others => 'X'); + muxz_o_mux(MSB_P downto 0) <= ( others => 'X'); + elsif(output_x_sig = '0') then + --MUX_X ----- + case opmode_o_mux(1 downto 0) is + when "00" => muxx_o_mux <= ( others => '0'); + -- FP ?? sign extend needed from 43rd bit to 48th bit + when "01" => muxx_o_mux((MSB_A_MULT + MSB_B_MULT +1) downto 0) <= mult_o_mux; + if(mult_o_mux(MSB_A_MULT + MSB_B_MULT + 1) = '1') then + muxx_o_mux(MSB_PCIN downto (MAX_A_MULT + MAX_B_MULT)) <= ( others => '1'); + elsif (mult_o_mux(MSB_A_MULT + MSB_B_MULT + 1) = '0') then + muxx_o_mux(MSB_PCIN downto (MAX_A_MULT + MAX_B_MULT)) <= ( others => '0'); + end if; + + when "10" => muxx_o_mux <= qp_o_mux; + +-- CR 438456 & CR 448147 & CR 451453 + when "11" => if((USE_MULT = "MULT_S") and (AREG=0 or BREG=0)) then + muxx_o_mux(MSB_P downto 0) <= ( others => 'X'); + assert false + report "DRC warning: When attribute USE_MULT on DSP48E instance %m is set to MULT_S, the A:B opmode selection is not permitted when AREG or BREG=0. If the multiplier is not used, set USE_MULT = NONE. For dynamic switching between multiply and add operation, set AREG and BREG=1 or MREG=0 and USE_MULT=MULT." + severity Warning; + else + muxx_o_mux(MSB_P downto 0) <= (qa_o_mux & qb_o_mux); + end if; + + when others => null; + end case; + + --MUX_Y ----- + case opmode_o_mux(3 downto 2) is + when "00" => muxy_o_mux <= ( others => '0'); + when "01" => muxy_o_mux <= ( others => '0'); + when "10" => + if(opmode_o_mux(6 downto 4) = "100") then + muxy_o_mux <= ( others => MULTSIGNIN_dly); + else + muxy_o_mux <= ( others => '1'); + end if; + when "11" => muxy_o_mux <= qc_o_mux; + when others => null; + end case; + --MUX_Z ----- + case opmode_o_mux(6 downto 4) is + when "000" => muxz_o_mux <= ( others => '0'); + when "001" => muxz_o_mux <= PCIN_dly; + when "010" => muxz_o_mux <= qp_o_mux; + when "011" => muxz_o_mux <= qc_o_mux; + when "100" => muxz_o_mux <= qp_o_mux; -- Used for MACC extend -- multsignin + -- FP ?? better shift possible ? + when "101" => if(PCIN_dly(MSB_PCIN) = '0') then + muxz_o_mux <= ( others => '0'); + elsif(PCIN_dly(MSB_PCIN) = '1') then + muxz_o_mux <= ( others => '1'); + end if; + muxz_o_mux ((MSB_PCIN - SHIFT_MUXZ) downto 0) <= PCIN_dly(MSB_PCIN downto SHIFT_MUXZ ); + when "110" => if(qp_o_mux(MSB_P) = '0') then + muxz_o_mux <= ( others => '0'); + elsif(qp_o_mux(MSB_P) = '1') then + muxz_o_mux <= ( others => '1'); + end if; + muxz_o_mux ((MSB_P - SHIFT_MUXZ) downto 0) <= qp_o_mux(MSB_P downto SHIFT_MUXZ ); + + when "111" => null; + when others => null; + end case; + end if; + end process prcs_mux_xyz; +--#################################################################### +--##### Alumode ##### +--#################################################################### + prcs_alumode_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + alumode_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTALUMODE_dly = '1') then + alumode_o_reg <= ( others => '0'); + elsif ((RSTALUMODE_dly = '0') and (CEALUMODE_dly = '1'))then + alumode_o_reg <= ALUMODE_dly; + end if; + end if; + end if; + end process prcs_alumode_reg; +------------------------------------------------------------------ + prcs_alumode_mux:process(alumode_o_reg, ALUMODE_dly) + begin + case ALUMODEREG is + when 0 => alumode_o_mux <= ALUMODE_dly; + when 1 => alumode_o_mux <= alumode_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for ALUMODEREG are 0 or 1" + severity Failure; + end case; + end process prcs_alumode_mux; + +--#################################################################### +--##### CarryInSel ##### +--#################################################################### + prcs_carryinsel_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + carryinsel_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTCTRL_dly = '1') then + carryinsel_o_reg <= ( others => '0'); + elsif ((RSTCTRL_dly = '0') and (CECTRL_dly = '1')) then + carryinsel_o_reg <= CARRYINSEL_dly; + end if; + end if; + end if; + end process prcs_carryinsel_reg; +------------------------------------------------------------------ + prcs_carryinsel_mux:process(carryinsel_o_reg, CARRYINSEL_dly) + begin + case CARRYINSELREG is + when 0 => carryinsel_o_mux <= CARRYINSEL_dly; + when 1 => carryinsel_o_mux <= carryinsel_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for CARRYINSELREG are 0 or 1" + severity Failure; + end case; + end process prcs_carryinsel_mux; + +------------------------------------------------------------------ +-- CR 219047 (3) + prcs_carryinsel_drc:process(carryinsel_o_mux, MULTSIGNIN_dly, opmode_o_mux) + begin + if(carryinsel_o_mux = "010") then + if(not((MULTSIGNIN_dly = 'X') or ((opmode_o_mux = "1001000") and (MULTSIGNIN_dly /= 'X')) + or ((MULTSIGNIN_dly = '0') and (CARRYCASCIN_dly = '0')))) then + assert false +-- CR 451178 -- DRC warning Enhancement + report "DRC warning : CARRYCASCIN can only be used in the current DSP48E instance if the previous DSP48E is performing a two input ADD operation, or the current DSP48E is configured in the MAC extend opmode(6:0) equals 1001000. This warning can be also triggered if OPMODEREG is set to 1 and CARRYINSELREG is set to 0 - in which case please set CARRYINSELREG to 1." + severity Warning; + end if; + end if; + end process prcs_carryinsel_drc; + +-- CR 219047 (4) + prcs_carryinsel_mac_drc:process(carryinsel_o_mux) + begin + if((carryinsel_o_mux = "110") and (MULTCARRYINREG /= MREG)) then + assert false + report "Attribute Syntax Warning : It is recommended that MREG and MULTCARRYINREG on DSP48E instance be set to the same value when using CARRYINSEL = 110 for multiply rounding. " + severity Warning; + end if; + end process prcs_carryinsel_mac_drc; + + +--#################################################################### +--##### CarryIn ##### +--#################################################################### + +------- input 0 + + prcs_carryin_reg0:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qcarryin_o_reg0 <= '0'; + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTALLCARRYIN_dly = '1') then + qcarryin_o_reg0 <= '0'; + elsif((RSTALLCARRYIN_dly = '0') and (CECARRYIN_dly = '1')) then + qcarryin_o_reg0 <= CARRYIN_dly; + end if; + end if; + end if; + end process prcs_carryin_reg0; + + prcs_carryin_mux0:process(qcarryin_o_reg0, CARRYIN_dly) + begin + case CARRYINREG is + when 0 => carryin_o_mux0 <= CARRYIN_dly; + when 1 => carryin_o_mux0 <= qcarryin_o_reg0; + when others => + assert false + report "Attribute Syntax Error: The allowed values for CARRYINREG are 0 or 1" + severity Failure; + end case; + end process prcs_carryin_mux0; + +------------------------------------------------------------------ +------- input 7 + + prcs_carryin_reg7:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qcarryin_o_reg7 <= '0'; + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(RSTALLCARRYIN_dly = '1') then + qcarryin_o_reg7 <= '0'; + elsif((RSTALLCARRYIN_dly = '0') and (CEMULTCARRYIN_dly = '1')) then + qcarryin_o_reg7 <= qa_o_mux(24) XNOR qb_o_mux(17); + end if; + end if; + end if; + end process prcs_carryin_reg7; + + prcs_carryin_mux7:process(qa_o_mux(24), qb_o_mux(17), qcarryin_o_reg7) + begin + case MULTCARRYINREG is + when 0 => carryin_o_mux7 <= qa_o_mux(24) XNOR qb_o_mux(17); +-- CR 232187 + when 1 => carryin_o_mux7 <= qcarryin_o_reg7; + when others => + assert false + report "Attribute Syntax Error: The allowed values for MULTCARRYINREG are 0 or 1" + severity Failure; + end case; + end process prcs_carryin_mux7; + +------------------------------------------------------------------ +-- FP Check this with VV +------------------------------------------------------------------ +-- + prcs_carryin_mux:process(carryin_o_mux0, PCIN_dly(47), CARRYCASCIN_dly, carrycascout_o_mux, qp_o_mux(47), carryin_o_mux7, carryinsel_o_mux) + begin + case carryinsel_o_mux is + when "000" => carryin_o_mux <= carryin_o_mux0; + when "001" => carryin_o_mux <= NOT PCIN_dly(47); + when "010" => carryin_o_mux <= CARRYCASCIN_dly; + when "011" => carryin_o_mux <= PCIN_dly(47); + when "100" => carryin_o_mux <= carrycascout_o_mux; + when "101" => carryin_o_mux <= NOT qp_o_mux(47); + when "110" => carryin_o_mux <= carryin_o_mux7; + when "111" => carryin_o_mux <= qp_o_mux(47); + when others => null; + end case; + end process prcs_carryin_mux; +--#################################################################### +--##### ALU ##### +--#################################################################### + prcs_alu:process(muxx_o_mux, muxy_o_mux, muxz_o_mux, alumode_o_mux, opmode_o_mux, carryin_o_mux, output_x_sig) + + variable opmode_alu_var : std_logic_vector(5 downto 0) := (others => '0'); + variable alu_full_tmp : std_logic_vector(MAX_ALU_FULL downto 0) := (others => '0'); + variable alu_hlf1_tmp, alu_hlf2_tmp : std_logic_vector(MAX_ALU_HALF downto 0) := (others => '0'); + variable alu_qrt1_tmp, alu_qrt2_tmp, alu_qrt3_tmp, alu_qrt4_tmp : std_logic_vector(MAX_ALU_QUART downto 0) := (others => '0'); + + begin + if(output_x_sig = '1') then + alu_o <= (others => 'X'); + + elsif(opmode_valid_flg) then + opmode_alu_var := opmode_o_mux(3 downto 2) & alumode_o_mux; + case opmode_alu_var is + --------------------------------- + ------------- ADD --------------- + --------------------------------- + when "000000" | "010000" | "100000" | "110000" => + + if((USE_SIMD = "ONE48") or (USE_SIMD = "one48")) then + alu_full_tmp := (('0'&muxz_o_mux) + + ('0'&muxx_o_mux) + + ('0'&muxy_o_mux) + carryin_o_mux); + alu_o <= alu_full_tmp(MSB_ALU_FULL downto 0); + + carrycascout_o <= alu_full_tmp(MAX_ALU_FULL); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= alu_full_tmp(MAX_ALU_FULL); + carryout_o(MSB_CARRYOUT - 1) <= 'X'; + carryout_o(MSB_CARRYOUT - 2) <= 'X'; + carryout_o(MSB_CARRYOUT - 3) <= 'X'; + end if; + + elsif((USE_SIMD = "TWO24") or (USE_SIMD = "two24")) then + alu_hlf1_tmp := (('0'&muxz_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + ('0'&muxx_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + ('0'&muxy_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + carryin_o_mux); + alu_hlf2_tmp := (('0'&muxz_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) + + ('0'&muxx_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) + + ('0'&muxy_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF)))); + alu_o <= (alu_hlf2_tmp(MSB_ALU_HALF downto 0) & alu_hlf1_tmp(MSB_ALU_HALF downto 0)) ; + + carrycascout_o <= alu_hlf2_tmp(MAX_ALU_HALF); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= alu_hlf2_tmp(MAX_ALU_HALF); + carryout_o(MSB_CARRYOUT - 1) <= 'X'; + carryout_o(MSB_CARRYOUT - 2) <= alu_hlf1_tmp(MAX_ALU_HALF); + carryout_o(MSB_CARRYOUT - 3) <= 'X'; + end if; + + elsif((USE_SIMD = "FOUR12") or (USE_SIMD = "four12")) then + alu_qrt1_tmp := (('0'&muxz_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + ('0'&muxx_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + ('0'&muxy_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + carryin_o_mux); + alu_qrt2_tmp := (('0'&muxz_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) + + ('0'&muxx_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART)))); + alu_qrt3_tmp := (('0'&muxz_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) + + ('0'&muxx_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART)))); + alu_qrt4_tmp := (('0'&muxz_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) + + ('0'&muxx_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART)))); + + alu_o <= (alu_qrt4_tmp(MSB_ALU_QUART downto 0) & alu_qrt3_tmp(MSB_ALU_QUART downto 0) & + alu_qrt2_tmp(MSB_ALU_QUART downto 0) & alu_qrt1_tmp(MSB_ALU_QUART downto 0)); + + carrycascout_o <= alu_qrt4_tmp(MAX_ALU_QUART); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= alu_qrt4_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 1) <= alu_qrt3_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 2) <= alu_qrt2_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 3) <= alu_qrt1_tmp(MAX_ALU_QUART); + end if; + + else + assert false + report "Attribute Syntax Error: The legal values for USE_SIMD are ONE48 or TWO24 or FOUR12." + severity Failure; + end if; + + --------------------------------- + ------ SUBTRACT (X + ~Z ) ---- carryin must be 1 --------------- + --------------------------------- + when "000001" | "010001" | "100001" | "110001" => + + if((USE_SIMD = "ONE48") or (USE_SIMD = "one48")) then + alu_full_tmp := NOT('0'&muxz_o_mux) + + ('0'&muxx_o_mux) + + ('0'&muxy_o_mux) + carryin_o_mux; + alu_o <= alu_full_tmp(MSB_ALU_FULL downto 0); + + carrycascout_o <= NOT alu_full_tmp(MAX_ALU_FULL); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= NOT alu_full_tmp(MAX_ALU_FULL); + carryout_o(MSB_CARRYOUT - 1) <= 'X'; + carryout_o(MSB_CARRYOUT - 2) <= 'X'; + carryout_o(MSB_CARRYOUT - 3) <= 'X'; + end if; + + elsif((USE_SIMD = "TWO24") or (USE_SIMD = "two24")) then + alu_hlf1_tmp := NOT('0'&muxz_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + ('0'&muxx_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + ('0'&muxy_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + carryin_o_mux; + alu_hlf2_tmp := NOT('0'&muxz_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) + + ('0'&muxx_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) + + ('0'&muxy_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))); + + alu_o <= (alu_hlf2_tmp(MSB_ALU_HALF downto 0) & alu_hlf1_tmp(MSB_ALU_HALF downto 0)) ; + + carrycascout_o <= NOT alu_hlf2_tmp(MAX_ALU_HALF); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= NOT alu_hlf2_tmp(MAX_ALU_HALF); + carryout_o(MSB_CARRYOUT - 1) <= 'X'; + carryout_o(MSB_CARRYOUT - 2) <= NOT alu_hlf1_tmp(MAX_ALU_HALF); + carryout_o(MSB_CARRYOUT - 3) <= 'X'; + end if; + + elsif((USE_SIMD = "FOUR12") or (USE_SIMD = "four12")) then + alu_qrt1_tmp := NOT('0'&muxz_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + ('0'&muxx_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + ('0'&muxy_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + carryin_o_mux; + alu_qrt2_tmp := NOT('0'&muxz_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) + + ('0'&muxx_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))); + alu_qrt3_tmp := NOT('0'&muxz_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) + + ('0'&muxx_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))); + alu_qrt4_tmp := NOT('0'&muxz_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) + + ('0'&muxx_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))); + + alu_o <= (alu_qrt4_tmp(MSB_ALU_QUART downto 0) & alu_qrt3_tmp(MSB_ALU_QUART downto 0) & + alu_qrt2_tmp(MSB_ALU_QUART downto 0) & alu_qrt1_tmp(MSB_ALU_QUART downto 0)); + + carrycascout_o <= NOT alu_qrt4_tmp(MAX_ALU_QUART); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= NOT alu_qrt4_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 1) <= NOT alu_qrt3_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 2) <= NOT alu_qrt2_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 3) <= NOT alu_qrt1_tmp(MAX_ALU_QUART); + end if; + + else + assert false + report "Attribute Syntax Error: The legal values for USE_SIMD are ONE48 or TWO24 or FOUR12." + severity Failure; + end if; + + --------------------------------- + ---------- NOT (X + Y + Z + C) ---------- + --------------------------------- + when "000010" | "010010" | "100010" | "110010" => + + if((USE_SIMD = "ONE48") or (USE_SIMD = "one48")) then + alu_full_tmp := NOT((('0'&muxz_o_mux) + + ('0'&muxx_o_mux) + + ('0'&muxy_o_mux) + carryin_o_mux)); + + alu_o <= alu_full_tmp(MSB_ALU_FULL downto 0); + + carrycascout_o <= NOT alu_full_tmp(MAX_ALU_FULL); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= NOT alu_full_tmp(MAX_ALU_FULL); + carryout_o(MSB_CARRYOUT - 1) <= 'X'; + carryout_o(MSB_CARRYOUT - 2) <= 'X'; + carryout_o(MSB_CARRYOUT - 3) <= 'X'; + end if; + + elsif((USE_SIMD = "TWO24") or (USE_SIMD = "two24")) then + alu_hlf1_tmp := NOT((('0'&muxz_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + ('0'&muxx_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + ('0'&muxy_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + carryin_o_mux)); + alu_hlf2_tmp := NOT((('0'&muxz_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) + + ('0'&muxx_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) + + ('0'&muxy_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))))); + + alu_o <= (alu_hlf2_tmp(MSB_ALU_HALF downto 0) & alu_hlf1_tmp(MSB_ALU_HALF downto 0)) ; + + carrycascout_o <= NOT alu_hlf2_tmp(MAX_ALU_HALF); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= NOT alu_hlf2_tmp(MAX_ALU_HALF); + carryout_o(MSB_CARRYOUT - 1) <= 'X'; + carryout_o(MSB_CARRYOUT - 2) <= NOT alu_hlf1_tmp(MAX_ALU_HALF); + carryout_o(MSB_CARRYOUT - 3) <= 'X'; + end if; + + elsif((USE_SIMD = "FOUR12") or (USE_SIMD = "four12")) then + alu_qrt1_tmp := NOT((('0'&muxz_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + ('0'&muxx_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + ('0'&muxy_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + carryin_o_mux)); + alu_qrt2_tmp := NOT((('0'&muxz_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) + + ('0'&muxx_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))))); + alu_qrt3_tmp := NOT((('0'&muxz_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) + + ('0'&muxx_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))))); + alu_qrt4_tmp := NOT((('0'&muxz_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) + + ('0'&muxx_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))))); + + alu_o <= (alu_qrt4_tmp(MSB_ALU_QUART downto 0) & alu_qrt3_tmp(MSB_ALU_QUART downto 0) & + alu_qrt2_tmp(MSB_ALU_QUART downto 0) & alu_qrt1_tmp(MSB_ALU_QUART downto 0)); + + carrycascout_o <= NOT alu_qrt4_tmp(MAX_ALU_QUART); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= NOT alu_qrt4_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 1) <= NOT alu_qrt3_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 2) <= NOT alu_qrt2_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 3) <= NOT alu_qrt1_tmp(MAX_ALU_QUART); + end if; + + else + assert false + report "Attribute Syntax Error: The legal values for USE_SIMD are ONE48 or TWO24 or FOUR12." + severity Failure; + end if; + + --------------------------------- + ------- SUBTRACT (Z - X ) ------- + --------------------------------- + when "000011" | "010011" | "100011" | "110011"=> + + if((USE_SIMD = "ONE48") or (USE_SIMD = "one48")) then + alu_full_tmp := (('0'&muxz_o_mux) - + (('0'&muxx_o_mux) + + ('0'&muxy_o_mux) + carryin_o_mux)); + + alu_o <= alu_full_tmp(MSB_ALU_FULL downto 0); + + carrycascout_o <= alu_full_tmp(MAX_ALU_FULL); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= NOT alu_full_tmp(MAX_ALU_FULL); + carryout_o(MSB_CARRYOUT - 1) <= 'X'; + carryout_o(MSB_CARRYOUT - 2) <= 'X'; + carryout_o(MSB_CARRYOUT - 3) <= 'X'; + end if; + + elsif((USE_SIMD = "TWO24") or (USE_SIMD = "two24")) then + alu_hlf1_tmp := (('0'&muxz_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) - + (('0'&muxx_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + ('0'&muxy_o_mux(((1*MAX_ALU_HALF)-1) downto 0)) + + carryin_o_mux)); + alu_hlf2_tmp := (('0'&muxz_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) - + (('0'&muxx_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))) + + ('0'&muxy_o_mux(((2*MAX_ALU_HALF)-1) downto (1*MAX_ALU_HALF))))); + + alu_o <= (alu_hlf2_tmp(MSB_ALU_HALF downto 0) & alu_hlf1_tmp(MSB_ALU_HALF downto 0)) ; + + carrycascout_o <= alu_hlf2_tmp(MAX_ALU_HALF); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= NOT alu_hlf2_tmp(MAX_ALU_HALF); + carryout_o(MSB_CARRYOUT - 1) <= 'X'; + carryout_o(MSB_CARRYOUT - 2) <= NOT alu_hlf1_tmp(MAX_ALU_HALF); + carryout_o(MSB_CARRYOUT - 3) <= 'X'; + end if; + + elsif((USE_SIMD = "FOUR12") or (USE_SIMD = "four12")) then + alu_qrt1_tmp := (('0'&muxz_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) - + (('0'&muxx_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + ('0'&muxy_o_mux(((1*MAX_ALU_QUART)-1) downto 0)) + + carryin_o_mux)); + alu_qrt2_tmp := (('0'&muxz_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) - + (('0'&muxx_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((2*MAX_ALU_QUART)-1) downto (1*MAX_ALU_QUART))))); + alu_qrt3_tmp := (('0'&muxz_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) - + (('0'&muxx_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((3*MAX_ALU_QUART)-1) downto (2*MAX_ALU_QUART))))); + alu_qrt4_tmp := (('0'&muxz_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) - + (('0'&muxx_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))) + + ('0'&muxy_o_mux(((4*MAX_ALU_QUART)-1) downto (3*MAX_ALU_QUART))))); + + alu_o <= (alu_qrt4_tmp(MSB_ALU_QUART downto 0) & alu_qrt3_tmp(MSB_ALU_QUART downto 0) & + alu_qrt2_tmp(MSB_ALU_QUART downto 0) & alu_qrt1_tmp(MSB_ALU_QUART downto 0)); + + carrycascout_o <= alu_qrt4_tmp(MAX_ALU_QUART); + -- if multiply operation then "X"out the carryout + if((opmode_o_mux(1 downto 0) = "01") or (opmode_o_mux(3 downto 2) = "01")) then + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + else + carryout_o(MSB_CARRYOUT - 0) <= NOT alu_qrt4_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 1) <= NOT alu_qrt3_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 2) <= NOT alu_qrt2_tmp(MAX_ALU_QUART); + carryout_o(MSB_CARRYOUT - 3) <= NOT alu_qrt1_tmp(MAX_ALU_QUART); + end if; + + else + assert false + report "Attribute Syntax Error: The legal values for USE_SIMD are ONE48 or TWO24 or FOUR12." + severity Failure; + end if; + + --------------------------------- + ------------- XOR --------------- + --------------------------------- + when "000100" | "000111" | "100101" | "100110" => + alu_o <= muxx_o_mux xor muxz_o_mux; + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + --------------------------------- + ------------- XNOR --------------- + --------------------------------- + when "000101" | "000110" | "100100" | "100111" => + alu_o <= muxx_o_mux xnor muxz_o_mux; + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + --------------------------------- + ------------- AND --------------- + --------------------------------- + when "001100" => + alu_o <= muxx_o_mux and muxz_o_mux; + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + --------------------------------- + --------- X AND (NOT Z) --------- + --------------------------------- + when "001101" => + alu_o <= muxx_o_mux and (not muxz_o_mux); + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + --------------------------------- + ------------- NAND --------------- + --------------------------------- + when "001110" => + alu_o <= muxx_o_mux nand muxz_o_mux; + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + --------------------------------- + -------- - (NOT X) OR Z --------- + --------------------------------- + when "001111" => + alu_o <= (not muxx_o_mux) or muxz_o_mux; + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + --------------------------------- + -------------- OR --------------- + --------------------------------- + when "101100" => + alu_o <= muxx_o_mux or muxz_o_mux; + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + --------------------------------- + --------- X OR (NOT Z) --------- + --------------------------------- + when "101101" => + alu_o <= muxx_o_mux or (not muxz_o_mux); + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + --------------------------------- + ------------ X NOR Z ------------ + --------------------------------- + when "101110" => + alu_o <= muxx_o_mux nor muxz_o_mux; + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + --------------------------------- + --------- (NOT X) and Z --------- + --------------------------------- + when "101111" => + alu_o <= (not muxx_o_mux) and muxz_o_mux; + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + + when others => + + carryout_o(MSB_CARRYOUT downto 0) <= (others => 'X'); + carrycascout_o <= 'X'; + + end case; + end if; + end process prcs_alu; +--#################################################################### +--##### CARRYOUT and CARRYCASCOUT ##### +--#################################################################### + prcs_carry_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + carryout_o_reg <= ( others => '0'); + carrycascout_o_reg <= '0'; + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if((RSTP_dly = '1') or + ((AUTORESET_PATTERN_DETECT) and ( + ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and pdet_o_reg1 = '1') or + ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and (pdet_o_reg2 = '1' and pdet_o_reg1 = '0'))) + ) + ) then + carryout_o_reg <= ( others => '0'); + carrycascout_o_reg <= '0'; + elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then + carryout_o_reg <= carryout_o; + carrycascout_o_reg <= carrycascout_o; + end if; + end if; + end if; + end process prcs_carry_reg; +------------------------------------------------------------------ + prcs_carryout_mux:process(carryout_o, carryout_o_reg) + begin + case PREG is + when 0 => carryout_o_mux <= carryout_o; + when 1 => carryout_o_mux <= carryout_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for PREG are 0 or 1" + severity Failure; + end case; + + end process prcs_carryout_mux; + +------------------------------------------------------------------ + prcs_carryout_x_o:process(carryout_o_mux) + begin + if(USE_SIMD = "ONE48") then + carryout_x_o(3) <= carryout_o_mux(3); + elsif(USE_SIMD = "TWO24") then + carryout_x_o(3) <= carryout_o_mux(3); + carryout_x_o(1) <= carryout_o_mux(1); + elsif(USE_SIMD = "FOUR12") then + carryout_x_o(3) <= carryout_o_mux(3); + carryout_x_o(2) <= carryout_o_mux(2); + carryout_x_o(1) <= carryout_o_mux(1); + carryout_x_o(0) <= carryout_o_mux(0); + end if; + end process prcs_carryout_x_o; + +------------------------------------------------------------------ + prcs_carrycascout_mux:process(carrycascout_o, carrycascout_o_reg) + begin + case PREG is + when 0 => carrycascout_o_mux <= carrycascout_o; + when 1 => carrycascout_o_mux <= carrycascout_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for PREG are 0 or 1" + severity Failure; + end case; + + end process prcs_carrycascout_mux; +------------------------------------------------------------------ +-- CR 219047 (2) + prcs_multsignout_o_opmode:process(mult_o_mux(MSB_A_MULT+MSB_B_MULT+1), opmode_o_mux(3 downto 0)) + begin + if(opmode_o_mux(3 downto 0) = "0101") then + multsignout_o_opmode <= mult_o_mux(MSB_A_MULT+MSB_B_MULT+1); + else + multsignout_o_opmode <= 'X'; + end if; + end process prcs_multsignout_o_opmode; + + prcs_multsignout_o_mux:process(multsignout_o_opmode, multsignout_o_reg) + begin + case PREG is + when 0 => multsignout_o_mux <= multsignout_o_opmode; +-- CR 232275 + when 1 => multsignout_o_mux <= multsignout_o_reg; + when others => null; +-- assert false +-- report "Attribute Syntax Error: The allowed values for PREG are 0 or 1" +-- severity Failure; + end case; + + end process prcs_multsignout_o_mux; +--#################################################################### +--#################################################################### +--#################################################################### +--##### PCOUT and MULTSIGNOUT ##### +--#################################################################### + prcs_qp_reg:process(CLK_dly, GSR_dly) + begin + if(GSR_dly = '1') then + qp_o_reg <= ( others => '0'); + multsignout_o_reg <= '0'; + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if((RSTP_dly = '1') or + ((AUTORESET_PATTERN_DETECT) and ( + ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and pdet_o_reg1 = '1') or + ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and (pdet_o_reg2 = '1' and pdet_o_reg1 = '0'))) + ) + ) then + qp_o_reg <= ( others => '0'); + multsignout_o_reg <= '0'; + elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then + qp_o_reg <= alu_o; + multsignout_o_reg <= mult_o_reg((MSB_A_MULT+MSB_B_MULT+1)); + end if; + end if; + end if; + end process prcs_qp_reg; +------------------------------------------------------------------ + prcs_qp_mux:process(alu_o, qp_o_reg) + begin + case PREG is + when 0 => qp_o_mux <= alu_o; + when 1 => qp_o_mux <= qp_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for PREG are 0 or 1" + severity Failure; + end case; + + end process prcs_qp_mux; +--#################################################################### +--##### Pattern Detector ##### +--#################################################################### + prcs_sel_pattern_detect:process(alu_o, qc_o_mux) + begin + + -- Select the pattern + if((SEL_PATTERN = "PATTERN") or (SEL_PATTERN = "pattern")) then + pattern_qp <= To_StdLogicVector(PATTERN); + elsif((SEL_PATTERN = "C") or (SEL_PATTERN = "c")) then + pattern_qp <= qc_o_mux; + else + assert false + report "Attribute Syntax Error: The attribute SEL_PATTERN on DSP48_ALU is incorrect. Legal values for this attribute are PATTERN or C" + severity Failure; + end if; + + -- Select the mask -- if ROUNDING MASK set, use rounding mode, else use SEL_MASK + if((SEL_ROUNDING_MASK = "SEL_MASK") or (SEL_ROUNDING_MASK = "sel_mask")) then + if((SEL_MASK = "MASK") or (SEL_MASK = "mask")) then + mask_qp <= To_StdLogicVector(MASK); + elsif((SEL_MASK = "C") or (SEL_MASK = "c")) then + mask_qp <= qc_o_mux; + else + assert false + report "Attribute Syntax Error: The attribute SEL_MASK on DSP48_ALU is incorrect. Legal values for this attribute are MASK or C" + severity Failure; + end if; + elsif((SEL_ROUNDING_MASK = "MODE1") or (SEL_ROUNDING_MASK = "mode1")) then + mask_qp <= To_StdLogicVector((To_bitvector( not qc_o_mux)) sla 1) ; + mask_qp (0) <= '0'; + elsif((SEL_ROUNDING_MASK = "MODE2") or (SEL_ROUNDING_MASK = "mode2")) then + mask_qp <= To_StdLogicVector((To_bitvector( not qc_o_mux)) sla 2) ; + mask_qp (1 downto 0) <= (others => '0'); + else + assert false + report "Attribute Syntax Error: The attribute SEL_ROUNDING_MASK on DSP48_ALU is incorrect. Legal values for this attribute are SEL_MASK or MODE1 or MODE2." + severity Failure; + end if; + + end process prcs_sel_pattern_detect; + + +--------------------------------------------------------------- + + prcs_pdet:process(alu_o, mask_qp, pattern_qp, GSR_dly ) + begin + if(((alu_o or mask_qp) = (pattern_qp or mask_qp)) and (GSR_dly = '0'))then + pdet_o <= '1'; + else + pdet_o <= '0'; + end if; + + if(((alu_o or mask_qp) = ((NOT pattern_qp) or mask_qp)) and (GSR_dly = '0')) then + pdetb_o <= '1'; + else + pdetb_o <= '0'; + end if; + + end process prcs_pdet; + +--------------------------------------------------------------- + + prcs_pdet_reg:process(CLK_dly, GSR_dly) + variable pdetb_reg1_var, pdetb_reg2_var, pdet_reg1_var, pdet_reg2_var : std_ulogic := '0'; + begin + if(GSR_dly = '1') then + pdetb_o_reg1 <= '0'; + pdetb_o_reg2 <= '0'; + pdet_o_reg1 <= '0'; + pdet_o_reg2 <= '0'; + + pdetb_reg1_var := '0'; + pdetb_reg2_var := '0'; + pdet_reg1_var := '0'; + pdet_reg2_var := '0'; + elsif (GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if((RSTP_dly = '1') or + ((AUTORESET_PATTERN_DETECT) and ( + ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and pdet_o_reg1 = '1') or + ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and (pdet_o_reg2 = '1' and pdet_o_reg1 = '0'))) + ) + ) then + pdetb_o_reg1 <= '0'; + pdetb_o_reg2 <= '0'; + pdet_o_reg1 <= '0'; + pdet_o_reg2 <= '0'; + + pdetb_reg1_var := '0'; + pdetb_reg2_var := '0'; + pdet_reg1_var := '0'; + pdet_reg2_var := '0'; + elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then + pdetb_reg2_var := pdetb_reg1_var; + pdetb_reg1_var := pdetb_o; + + pdet_reg2_var := pdet_reg1_var; + pdet_reg1_var := pdet_o; + + pdetb_o_reg1 <= pdetb_reg1_var; + pdetb_o_reg2 <= pdetb_reg2_var; + pdet_o_reg1 <= pdet_reg1_var; + pdet_o_reg2 <= pdet_reg2_var; + + end if; + end if; + end if; + end process prcs_pdet_reg; + +--#################################################################### +--##### Underflow / Overflow ##### +--#################################################################### + prcs_uflow_oflow:process(pdet_o_reg1 , pdet_o_reg2 , pdetb_o_reg1 , pdetb_o_reg2) + begin +-- if(((AUTORESET_PATTERN_DETECT) and ( +-- ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and (pdet_o_reg1 = '1')) or +-- ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and ((pdet_o_reg2 = '1') and (pdet_o_reg1 = '0')))) +-- )) then +-- underflow_o <= '0'; +-- overflow_o <= '0'; +-- else +-- overflow_o <= pdet_o_reg2 AND (NOT pdet_o_reg1) AND (NOT pdetb_o_reg1); +-- underflow_o <= pdetb_o_reg2 AND (NOT pdet_o_reg1) AND (NOT pdetb_o_reg1); +-- end if; + if(GSR_dly = '1') then + overflow_o <= '0'; + underflow_o <= '0'; + elsif(USE_PATTERN_DETECT = "NO_PATDET") then + overflow_o <= 'X'; + underflow_o <= 'X'; + elsif(PREG = 0) then + overflow_o <= 'X'; + underflow_o <= 'X'; + elsif(PREG = 1) then + overflow_o <= pdet_o_reg2 AND (NOT pdet_o_reg1) AND (NOT pdetb_o_reg1); + underflow_o <= pdetb_o_reg2 AND (NOT pdet_o_reg1) AND (NOT pdetb_o_reg1); + end if; + + end process prcs_uflow_oflow; +--#################################################################### +--##### OPMODE DRC ##### +--#################################################################### +-- prcs_opmode_drc:process(ping_opmode_drc_check, alumode_o_mux, opmode_o_mux, carryinsel_o_mux) + +-- opmode_valid_flg <= opmode_valid_var; + +-- end process prcs_opmode_drc; +--#################################################################### +--##### ZERO_DELAY_OUTPUTS ##### +--#################################################################### + prcs_zero_delay_outputs:process(qacout_o_mux, qbcout_o_mux, carryout_x_o, carrycascout_o_mux, + overflow_o, qp_o_mux, pdet_o, pdetb_o, + pdet_o_reg1, pdetb_o_reg1, + pdet_o_reg2, pdetb_o_reg2, + underflow_o, multsignout_o_mux, opmode_valid_flg, alumode_valid_flg) + begin + ACOUT_zd <= qacout_o_mux; + BCOUT_zd <= qbcout_o_mux; + OVERFLOW_zd <= overflow_o; + UNDERFLOW_zd <= underflow_o; + P_zd <= qp_o_mux; + PCOUT_zd <= qp_o_mux; + MULTSIGNOUT_zd <= multsignout_o_mux; + + if(((AUTORESET_PATTERN_DETECT) and ( + ((AUTORESET_PATTERN_DETECT_OPTINV = "MATCH") and (pdet_o_reg1 = '1')) or + ((AUTORESET_PATTERN_DETECT_OPTINV = "NOT_MATCH") and ((pdet_o_reg2 = '1') and (pdet_o_reg1 = '0')))) + )) then + CARRYCASCOUT_zd <= '0'; + CARRYOUT_zd <= (others => '0'); + else + CARRYCASCOUT_zd <= carrycascout_o_mux; + CARRYOUT_zd <= carryout_x_o; + end if; + + if((USE_PATTERN_DETECT = "NO_PATDET") or (not opmode_valid_flg) or (not alumode_valid_flg)) then + PATTERNBDETECT_zd <= 'X'; + PATTERNDETECT_zd <= 'X'; + elsif (PREG = 0) then + PATTERNBDETECT_zd <= pdetb_o; + PATTERNDETECT_zd <= pdet_o; + elsif(PREG = 1) then + PATTERNBDETECT_zd <= pdetb_o_reg1; + PATTERNDETECT_zd <= pdet_o_reg1; + end if; + + end process prcs_zero_delay_outputs; + +end generate; +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(ACOUT_zd, BCOUT_zd, CARRYCASCOUT_zd, CARRYOUT_zd, + OVERFLOW_zd, P_zd, PATTERNBDETECT_zd, PATTERNDETECT_zd, + PCOUT_zd, UNDERFLOW_zd, MULTSIGNOUT_zd) + begin + ACOUT <= ACOUT_zd after SYNC_PATH_DELAY; + BCOUT <= BCOUT_zd after SYNC_PATH_DELAY; + CARRYCASCOUT <= CARRYCASCOUT_zd after SYNC_PATH_DELAY; + CARRYOUT <= CARRYOUT_zd after SYNC_PATH_DELAY; + OVERFLOW <= OVERFLOW_zd after SYNC_PATH_DELAY; + P <= P_zd after SYNC_PATH_DELAY; + PATTERNBDETECT <= PATTERNBDETECT_zd after SYNC_PATH_DELAY; + PATTERNDETECT <= PATTERNDETECT_zd after SYNC_PATH_DELAY; + PCOUT <= PCOUT_zd after SYNC_PATH_DELAY; + UNDERFLOW <= UNDERFLOW_zd after SYNC_PATH_DELAY; + + MULTSIGNOUT <= MULTSIGNOUT_zd after SYNC_PATH_DELAY; + end process prcs_output; + + + +end DSP48E_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/fifo18_36.vhd,v 1.7 2007/06/15 21:01:09 wloo Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2005 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 18K-Bit FIFO +-- /___/ /\ Filename : FIFO18_36.vhd +-- \ \ / \ Timestamp : Tues October 18 16:43:59 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 10/18/05 - Initial version. +-- 06/14/07 - Implemented high performace version of the model. +-- End Revision + +----- CELL FIFO18_36 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity FIFO18_36 is +generic ( + + ALMOST_FULL_OFFSET : bit_vector := X"080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"080"; + DO_REG : integer := 1; + EN_SYN : boolean := FALSE; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + SIM_MODE : string := "SAFE" + + ); + +port ( + + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DO : out std_logic_vector (31 downto 0); + DOP : out std_logic_vector (3 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (8 downto 0); + RDERR : out std_ulogic; + WRCOUNT : out std_logic_vector (8 downto 0); + WRERR : out std_ulogic; + + DI : in std_logic_vector (31 downto 0); + DIP : in std_logic_vector (3 downto 0); + RDCLK : in std_ulogic; + RDEN : in std_ulogic; + RST : in std_ulogic; + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); +end FIFO18_36; + +architecture FIFO18_36_V of FIFO18_36 is + + component AFIFO36_INTERNAL + + generic( + ALMOST_FULL_OFFSET : bit_vector := X"0080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"0080"; + DATA_WIDTH : integer := 4; + DO_REG : integer := 1; + EN_ECC_READ : boolean := FALSE; + EN_ECC_WRITE : boolean := FALSE; + EN_SYN : boolean := FALSE; + FIFO_SIZE : integer := 36; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + SIM_MODE : string := "SAFE" + ); + + port( + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DBITERR : out std_ulogic; + DO : out std_logic_vector (63 downto 0); + DOP : out std_logic_vector (7 downto 0); + ECCPARITY : out std_logic_vector (7 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (12 downto 0); + RDERR : out std_ulogic; + SBITERR : out std_ulogic; + WRCOUNT : out std_logic_vector (12 downto 0); + WRERR : out std_ulogic; + + DI : in std_logic_vector (63 downto 0); + DIP : in std_logic_vector (7 downto 0); + RDCLK : in std_ulogic; + RDRCLK : in std_ulogic; + RDEN : in std_ulogic; + RST : in std_ulogic; + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); + end component; + + + constant SYNC_PATH_DELAY : time := 100 ps; + signal GND_4 : std_logic_vector(3 downto 0) := (others => '0'); + signal GND_32 : std_logic_vector(31 downto 0) := (others => '0'); + signal OPEN_4 : std_logic_vector(3 downto 0); + signal OPEN_32 : std_logic_vector(31 downto 0); + signal OPEN_8 : std_logic_vector(7 downto 0); + signal do_dly : std_logic_vector(31 downto 0) := (others => '0'); + signal dop_dly : std_logic_vector(3 downto 0) := (others => '0'); + signal almostfull_dly : std_ulogic := '0'; + signal almostempty_dly : std_ulogic := '0'; + signal empty_dly : std_ulogic := '0'; + signal full_dly : std_ulogic := '0'; + signal rderr_dly : std_ulogic := '0'; + signal wrerr_dly : std_ulogic := '0'; + signal rdcount_dly : std_logic_vector(8 downto 0) := (others => '0'); + signal wrcount_dly : std_logic_vector(8 downto 0) := (others => '0'); + + +begin + +FIFO18_36_inst : AFIFO36_INTERNAL + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DATA_WIDTH => 36, + DO_REG => DO_REG, + EN_SYN => EN_SYN, + FIFO_SIZE => 18, + SIM_MODE => SIM_MODE, + FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH + ) + + port map ( + DO(31 downto 0) => do_dly, + DO(63 downto 32) => OPEN_32, + DOP(3 downto 0) => dop_dly, + DOP(7 downto 4) => OPEN_4, + ALMOSTEMPTY => almostempty_dly, + ALMOSTFULL => almostfull_dly, + ECCPARITY => OPEN_8, + EMPTY => empty_dly, + FULL => full_dly, + RDCOUNT(8 downto 0) => rdcount_dly, + RDCOUNT(12 downto 9) => OPEN_4, + WRCOUNT(8 downto 0) => wrcount_dly, + WRCOUNT(12 downto 9) => OPEN_4, + RDERR => rderr_dly, + SBITERR => OPEN, + DBITERR => OPEN, + WRERR => wrerr_dly, + DI(31 downto 0) => DI, + DI(63 downto 32) => GND_32, + DIP(3 downto 0) => DIP, + DIP(7 downto 4) => GND_4, + WREN => WREN, + RDEN => RDEN, + RDCLK => RDCLK, + RDRCLK => RDCLK, + WRCLK => WRCLK, + RST => RST + ); + + prcs_output_wtiming: process (do_dly, dop_dly, almostempty_dly, almostfull_dly, empty_dly, full_dly, rdcount_dly, wrcount_dly, rderr_dly, wrerr_dly) + begin -- process prcs_output_wtiming + + ALMOSTEMPTY <= almostempty_dly after SYNC_PATH_DELAY; + ALMOSTFULL <= almostfull_dly after SYNC_PATH_DELAY; + empty <= empty_dly after SYNC_PATH_DELAY; + full <= full_dly after SYNC_PATH_DELAY; + DO <= do_dly after SYNC_PATH_DELAY; + DOP <= dop_dly after SYNC_PATH_DELAY; + RDCOUNT <= rdcount_dly after SYNC_PATH_DELAY; + WRCOUNT <= wrcount_dly after SYNC_PATH_DELAY; + RDERR <= rderr_dly after SYNC_PATH_DELAY; + WRERR <= wrerr_dly after SYNC_PATH_DELAY; + + end process prcs_output_wtiming; + +end FIFO18_36_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/fifo18.vhd,v 1.7 2007/06/15 21:01:09 wloo Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2005 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 18K-Bit FIFO +-- /___/ /\ Filename : FIFO18.vhd +-- \ \ / \ Timestamp : Tues October 18 16:43:59 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 10/18/05 - Initial version. +-- 06/14/07 - Implemented high performace version of the model. +-- End Revision + +----- CELL FIFO18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; +use unisim.vpkg.all; + +entity FIFO18 is +generic ( + + ALMOST_FULL_OFFSET : bit_vector := X"080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"080"; + DATA_WIDTH : integer := 4; + DO_REG : integer := 1; + EN_SYN : boolean := FALSE; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + SIM_MODE : string := "SAFE" + + ); + +port ( + + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DO : out std_logic_vector (15 downto 0); + DOP : out std_logic_vector (1 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (11 downto 0); + RDERR : out std_ulogic; + WRCOUNT : out std_logic_vector (11 downto 0); + WRERR : out std_ulogic; + + DI : in std_logic_vector (15 downto 0); + DIP : in std_logic_vector (1 downto 0); + RDCLK : in std_ulogic; + RDEN : in std_ulogic; + RST : in std_ulogic; + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); +end FIFO18; + +architecture FIFO18_V of FIFO18 is + + component AFIFO36_INTERNAL + + generic( + ALMOST_FULL_OFFSET : bit_vector := X"0080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"0080"; + DATA_WIDTH : integer := 4; + DO_REG : integer := 1; + EN_ECC_READ : boolean := FALSE; + EN_ECC_WRITE : boolean := FALSE; + EN_SYN : boolean := FALSE; + FIFO_SIZE : integer := 36; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + SIM_MODE : string := "SAFE" + ); + + port( + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DBITERR : out std_ulogic; + DO : out std_logic_vector (63 downto 0); + DOP : out std_logic_vector (7 downto 0); + ECCPARITY : out std_logic_vector (7 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (12 downto 0); + RDERR : out std_ulogic; + SBITERR : out std_ulogic; + WRCOUNT : out std_logic_vector (12 downto 0); + WRERR : out std_ulogic; + + DI : in std_logic_vector (63 downto 0); + DIP : in std_logic_vector (7 downto 0); + RDCLK : in std_ulogic; + RDRCLK : in std_ulogic; + RDEN : in std_ulogic; + RST : in std_ulogic; + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); + end component; + + + constant SYNC_PATH_DELAY : time := 100 ps; + signal GND_6 : std_logic_vector(5 downto 0) := (others => '0'); + signal GND_48 : std_logic_vector(47 downto 0) := (others => '0'); + signal OPEN_1 : std_logic_vector(0 downto 0); + signal OPEN_6 : std_logic_vector(5 downto 0); + signal OPEN_48 : std_logic_vector(47 downto 0); + signal OPEN_8 : std_logic_vector(7 downto 0); + signal do_dly : std_logic_vector(15 downto 0) := (others => '0'); + signal dop_dly : std_logic_vector(1 downto 0) := (others => '0'); + signal almostfull_dly : std_ulogic := '0'; + signal almostempty_dly : std_ulogic := '0'; + signal empty_dly : std_ulogic := '0'; + signal full_dly : std_ulogic := '0'; + signal rderr_dly : std_ulogic := '0'; + signal wrerr_dly : std_ulogic := '0'; + signal rdcount_dly : std_logic_vector(11 downto 0) := (others => '0'); + signal wrcount_dly : std_logic_vector(11 downto 0) := (others => '0'); + + +begin + +FIFO18_inst : AFIFO36_INTERNAL + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DATA_WIDTH => DATA_WIDTH, + DO_REG => DO_REG, + EN_SYN => EN_SYN, + FIFO_SIZE => 18, + SIM_MODE => SIM_MODE, + FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH + ) + + port map ( + DO(15 downto 0) => do_dly, + DO(63 downto 16) => OPEN_48, + DOP(1 downto 0) => dop_dly, + DOP(7 downto 2) => OPEN_6, + ALMOSTEMPTY => almostempty_dly, + ALMOSTFULL => almostfull_dly, + ECCPARITY => OPEN_8, + EMPTY => empty_dly, + FULL => full_dly, + RDCOUNT(11 downto 0) => rdcount_dly, + RDCOUNT(12 downto 12) => OPEN_1, + WRCOUNT(11 downto 0) => wrcount_dly, + WRCOUNT(12 downto 12) => OPEN_1, + RDERR => rderr_dly, + SBITERR => OPEN, + DBITERR => OPEN, + WRERR => wrerr_dly, + DI(15 downto 0) => DI, + DI(63 downto 16) => GND_48, + DIP(1 downto 0) => DIP, + DIP(7 downto 2) => GND_6, + WREN => WREN, + RDEN => RDEN, + RDCLK => RDCLK, + RDRCLK => RDCLK, + WRCLK => WRCLK, + RST => RST + ); + + + prcs_initialize:process + variable first_time : boolean := true; + + begin + if (first_time) then + case DATA_WIDTH is + when 4 | 9 | 18 => null; + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error ", + GenericName => " DATA_WIDTH ", + EntityName => "FIFO18", + GenericValue => DATA_WIDTH, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 4, 9 and 18 ", + TailMsg => "", + MsgSeverity => error + ); + end case; + first_time := false; + end if; + wait; + end process prcs_initialize; + + + + + prcs_output_wtiming: process (do_dly, dop_dly, almostempty_dly, almostfull_dly, empty_dly, full_dly, rdcount_dly, wrcount_dly, rderr_dly, wrerr_dly) + begin -- process prcs_output_wtiming + + ALMOSTEMPTY <= almostempty_dly after SYNC_PATH_DELAY; + ALMOSTFULL <= almostfull_dly after SYNC_PATH_DELAY; + empty <= empty_dly after SYNC_PATH_DELAY; + full <= full_dly after SYNC_PATH_DELAY; + DO <= do_dly after SYNC_PATH_DELAY; + DOP <= dop_dly after SYNC_PATH_DELAY; + RDCOUNT <= rdcount_dly after SYNC_PATH_DELAY; + WRCOUNT <= wrcount_dly after SYNC_PATH_DELAY; + RDERR <= rderr_dly after SYNC_PATH_DELAY; + WRERR <= wrerr_dly after SYNC_PATH_DELAY; + + end process prcs_output_wtiming; + +end FIFO18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/fifo36_72_exp.vhd,v 1.7 2007/06/15 21:01:09 wloo Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2005 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 36K-Bit FIFO +-- /___/ /\ Filename : FIFO36_72_EXP.vhd +-- \ \ / \ Timestamp : Tues October 18 16:43:59 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 10/18/05 - Initial version. +-- 06/14/07 - Implemented high performace version of the model. +-- End Revision + +----- CELL FIFO36_72_EXP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity FIFO36_72_EXP is +generic ( + + ALMOST_FULL_OFFSET : bit_vector := X"080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"080"; + DO_REG : integer := 1; + EN_ECC_READ : boolean := FALSE; + EN_ECC_WRITE : boolean := FALSE; + EN_SYN : boolean := FALSE; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + SIM_MODE : string := "SAFE" + + ); + +port ( + + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DBITERR : out std_ulogic; + DO : out std_logic_vector (63 downto 0); + DOP : out std_logic_vector (7 downto 0); + ECCPARITY : out std_logic_vector (7 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (12 downto 0); + RDERR : out std_ulogic; + SBITERR : out std_ulogic; + WRCOUNT : out std_logic_vector (12 downto 0); + WRERR : out std_ulogic; + + DI : in std_logic_vector (63 downto 0); + DIP : in std_logic_vector (7 downto 0); + RDCLKL : in std_ulogic; + RDCLKU : in std_ulogic; + RDEN : in std_ulogic; + RDRCLKL : in std_ulogic; + RDRCLKU : in std_ulogic; + RST : in std_ulogic; + WRCLKL : in std_ulogic; + WRCLKU : in std_ulogic; + WREN : in std_ulogic + ); +end FIFO36_72_EXP; + +architecture FIFO36_72_EXP_V of FIFO36_72_EXP is + + component AFIFO36_INTERNAL + + generic( + ALMOST_FULL_OFFSET : bit_vector := X"0080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"0080"; + DATA_WIDTH : integer := 4; + DO_REG : integer := 1; + EN_ECC_READ : boolean := FALSE; + EN_ECC_WRITE : boolean := FALSE; + EN_SYN : boolean := FALSE; + FIFO_SIZE : integer := 36; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + SIM_MODE : string := "SAFE" + ); + + port( + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DBITERR : out std_ulogic; + DO : out std_logic_vector (63 downto 0); + DOP : out std_logic_vector (7 downto 0); + ECCPARITY : out std_logic_vector (7 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (12 downto 0); + RDERR : out std_ulogic; + SBITERR : out std_ulogic; + WRCOUNT : out std_logic_vector (12 downto 0); + WRERR : out std_ulogic; + + DI : in std_logic_vector (63 downto 0); + DIP : in std_logic_vector (7 downto 0); + RDCLK : in std_ulogic; + RDRCLK : in std_ulogic; + RDEN : in std_ulogic; + RST : in std_ulogic; + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); + end component; + + + constant SYNC_PATH_DELAY : time := 100 ps; + signal do_dly : std_logic_vector(63 downto 0) := (others => '0'); + signal dop_dly : std_logic_vector(7 downto 0) := (others => '0'); + signal almostfull_dly : std_ulogic := '0'; + signal almostempty_dly : std_ulogic := '0'; + signal empty_dly : std_ulogic := '0'; + signal full_dly : std_ulogic := '0'; + signal rderr_dly : std_ulogic := '0'; + signal wrerr_dly : std_ulogic := '0'; + signal rdcount_dly : std_logic_vector(12 downto 0) := (others => '0'); + signal wrcount_dly : std_logic_vector(12 downto 0) := (others => '0'); + signal sbiterr_dly : std_ulogic := '0'; + signal dbiterr_dly : std_ulogic := '0'; + signal eccparity_dly : std_logic_vector(7 downto 0) := (others => '0'); + +begin + +FIFO36_72_EXP_inst : AFIFO36_INTERNAL + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DATA_WIDTH => 72, + DO_REG => DO_REG, + EN_ECC_READ => EN_ECC_READ, + EN_ECC_WRITE => EN_ECC_WRITE, + EN_SYN => EN_SYN, + SIM_MODE => SIM_MODE, + FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH + ) + + port map ( + DO => do_dly, + DOP => dop_dly, + ALMOSTEMPTY => almostempty_dly, + ALMOSTFULL => almostfull_dly, + ECCPARITY => eccparity_dly, + EMPTY => empty_dly, + FULL => full_dly, + RDCOUNT => rdcount_dly, + WRCOUNT => wrcount_dly, + RDERR => rderr_dly, + SBITERR => sbiterr_dly, + DBITERR => dbiterr_dly, + WRERR => wrerr_dly, + DI => DI, + DIP => DIP, + WREN => WREN, + RDEN => RDEN, + RDCLK => RDCLKL, + RDRCLK => RDRCLKL, + WRCLK => WRCLKL, + RST => RST + ); + + prcs_output_wtiming: process (do_dly, dop_dly, almostempty_dly, almostfull_dly, + empty_dly, full_dly, rdcount_dly, wrcount_dly, rderr_dly, + wrerr_dly, eccparity_dly, sbiterr_dly, dbiterr_dly) + begin -- process prcs_output_wtiming + + ALMOSTEMPTY <= almostempty_dly after SYNC_PATH_DELAY; + ALMOSTFULL <= almostfull_dly after SYNC_PATH_DELAY; + empty <= empty_dly after SYNC_PATH_DELAY; + full <= full_dly after SYNC_PATH_DELAY; + DO <= do_dly after SYNC_PATH_DELAY; + DOP <= dop_dly after SYNC_PATH_DELAY; + RDCOUNT <= rdcount_dly after SYNC_PATH_DELAY; + WRCOUNT <= wrcount_dly after SYNC_PATH_DELAY; + RDERR <= rderr_dly after SYNC_PATH_DELAY; + WRERR <= wrerr_dly after SYNC_PATH_DELAY; + ECCPARITY <= eccparity_dly after SYNC_PATH_DELAY; + SBITERR <= sbiterr_dly after SYNC_PATH_DELAY; + DBITERR <= dbiterr_dly after SYNC_PATH_DELAY; + + end process prcs_output_wtiming; + +end FIFO36_72_EXP_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/fifo36_72.vhd,v 1.9 2007/06/15 21:01:09 wloo Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2005 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 36K-Bit FIFO +-- /___/ /\ Filename : FIFO36_72.vhd +-- \ \ / \ Timestamp : Tues October 18 16:43:59 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 10/18/05 - Initial version. +-- 06/14/07 - Implemented high performace version of the model. +-- End Revision + +----- CELL FIFO36_72 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity FIFO36_72 is +generic ( + + ALMOST_FULL_OFFSET : bit_vector := X"080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"080"; + DO_REG : integer := 1; + EN_ECC_READ : boolean := FALSE; + EN_ECC_WRITE : boolean := FALSE; + EN_SYN : boolean := FALSE; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + SIM_MODE : string := "SAFE" + + ); + +port ( + + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DBITERR : out std_ulogic; + DO : out std_logic_vector (63 downto 0); + DOP : out std_logic_vector (7 downto 0); + ECCPARITY : out std_logic_vector (7 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (8 downto 0); + RDERR : out std_ulogic; + SBITERR : out std_ulogic; + WRCOUNT : out std_logic_vector (8 downto 0); + WRERR : out std_ulogic; + + DI : in std_logic_vector (63 downto 0); + DIP : in std_logic_vector (7 downto 0); + RDCLK : in std_ulogic; + RDEN : in std_ulogic; + RST : in std_ulogic; + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); +end FIFO36_72; + +architecture FIFO36_72_V of FIFO36_72 is + + component AFIFO36_INTERNAL + + generic( + ALMOST_FULL_OFFSET : bit_vector := X"0080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"0080"; + DATA_WIDTH : integer := 4; + DO_REG : integer := 1; + EN_ECC_READ : boolean := FALSE; + EN_ECC_WRITE : boolean := FALSE; + EN_SYN : boolean := FALSE; + FIFO_SIZE : integer := 36; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + SIM_MODE : string := "SAFE" + ); + + port( + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DBITERR : out std_ulogic; + DO : out std_logic_vector (63 downto 0); + DOP : out std_logic_vector (7 downto 0); + ECCPARITY : out std_logic_vector (7 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (12 downto 0); + RDERR : out std_ulogic; + SBITERR : out std_ulogic; + WRCOUNT : out std_logic_vector (12 downto 0); + WRERR : out std_ulogic; + + DI : in std_logic_vector (63 downto 0); + DIP : in std_logic_vector (7 downto 0); + RDCLK : in std_ulogic; + RDRCLK : in std_ulogic; + RDEN : in std_ulogic; + RST : in std_ulogic; + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); + end component; + + + constant SYNC_PATH_DELAY : time := 100 ps; + signal do_dly : std_logic_vector(63 downto 0) := (others => '0'); + signal dop_dly : std_logic_vector(7 downto 0) := (others => '0'); + signal almostfull_dly : std_ulogic := '0'; + signal almostempty_dly : std_ulogic := '0'; + signal empty_dly : std_ulogic := '0'; + signal full_dly : std_ulogic := '0'; + signal rderr_dly : std_ulogic := '0'; + signal wrerr_dly : std_ulogic := '0'; + signal rdcount_dly : std_logic_vector(8 downto 0) := (others => '0'); + signal wrcount_dly : std_logic_vector(8 downto 0) := (others => '0'); + signal sbiterr_dly : std_ulogic := '0'; + signal dbiterr_dly : std_ulogic := '0'; + signal eccparity_dly : std_logic_vector(7 downto 0) := (others => '0'); + signal OPEN_4 : std_logic_vector(3 downto 0); + signal OPEN_4_1 : std_logic_vector(3 downto 0); + +begin + +FIFO36_72_inst : AFIFO36_INTERNAL + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DATA_WIDTH => 72, + DO_REG => DO_REG, + EN_ECC_READ => EN_ECC_READ, + EN_ECC_WRITE => EN_ECC_WRITE, + EN_SYN => EN_SYN, + SIM_MODE => SIM_MODE, + FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH + ) + + port map ( + DO => do_dly, + DOP => dop_dly, + ALMOSTEMPTY => almostempty_dly, + ALMOSTFULL => almostfull_dly, + ECCPARITY => eccparity_dly, + EMPTY => empty_dly, + FULL => full_dly, + RDCOUNT(8 downto 0) => rdcount_dly, + RDCOUNT(12 downto 9) => OPEN_4, + WRCOUNT(8 downto 0) => wrcount_dly, + WRCOUNT(12 downto 9) => OPEN_4_1, + RDERR => rderr_dly, + SBITERR => sbiterr_dly, + DBITERR => dbiterr_dly, + WRERR => wrerr_dly, + DI => DI, + DIP => DIP, + WREN => WREN, + RDEN => RDEN, + RDCLK => RDCLK, + RDRCLK => RDCLK, + WRCLK => WRCLK, + RST => RST + ); + + prcs_output_wtiming: process (do_dly, dop_dly, almostempty_dly, almostfull_dly, + empty_dly, full_dly, rdcount_dly, wrcount_dly, rderr_dly, + wrerr_dly, eccparity_dly, sbiterr_dly, dbiterr_dly) + begin -- process prcs_output_wtiming + + ALMOSTEMPTY <= almostempty_dly after SYNC_PATH_DELAY; + ALMOSTFULL <= almostfull_dly after SYNC_PATH_DELAY; + empty <= empty_dly after SYNC_PATH_DELAY; + full <= full_dly after SYNC_PATH_DELAY; + DO <= do_dly after SYNC_PATH_DELAY; + DOP <= dop_dly after SYNC_PATH_DELAY; + RDCOUNT <= rdcount_dly after SYNC_PATH_DELAY; + WRCOUNT <= wrcount_dly after SYNC_PATH_DELAY; + RDERR <= rderr_dly after SYNC_PATH_DELAY; + WRERR <= wrerr_dly after SYNC_PATH_DELAY; + ECCPARITY <= eccparity_dly after SYNC_PATH_DELAY; + SBITERR <= sbiterr_dly after SYNC_PATH_DELAY; + DBITERR <= dbiterr_dly after SYNC_PATH_DELAY; + + end process prcs_output_wtiming; + +end FIFO36_72_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/fifo36_exp.vhd,v 1.7 2007/06/15 21:01:09 wloo Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2005 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 36K-Bit FIFO +-- /___/ /\ Filename : FIFO36_EXP.vhd +-- \ \ / \ Timestamp : Tues October 18 16:43:59 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 10/18/05 - Initial version. +-- 06/14/07 - Implemented high performace version of the model. +-- End Revision + +----- CELL FIFO36_EXP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity FIFO36_EXP is +generic ( + + ALMOST_EMPTY_OFFSET : bit_vector := X"0080"; + ALMOST_FULL_OFFSET : bit_vector := X"0080"; + DATA_WIDTH : integer := 4; + DO_REG : integer := 1; + EN_SYN : boolean := FALSE; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + SIM_MODE : string := "SAFE" + + ); + +port ( + + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DO : out std_logic_vector (31 downto 0); + DOP : out std_logic_vector (3 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (12 downto 0); + RDERR : out std_ulogic; + WRCOUNT : out std_logic_vector (12 downto 0); + WRERR : out std_ulogic; + + DI : in std_logic_vector (31 downto 0); + DIP : in std_logic_vector (3 downto 0); + RDCLKL : in std_ulogic; + RDCLKU : in std_ulogic; + RDEN : in std_ulogic; + RDRCLKL : in std_ulogic; + RDRCLKU : in std_ulogic; + RST : in std_ulogic; + WRCLKL : in std_ulogic; + WRCLKU : in std_ulogic; + WREN : in std_ulogic + ); +end FIFO36_EXP; + +architecture FIFO36_EXP_V of FIFO36_EXP is + + component AFIFO36_INTERNAL + + generic( + ALMOST_FULL_OFFSET : bit_vector := X"0080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"0080"; + DATA_WIDTH : integer := 4; + DO_REG : integer := 1; + EN_ECC_READ : boolean := FALSE; + EN_ECC_WRITE : boolean := FALSE; + EN_SYN : boolean := FALSE; + FIFO_SIZE : integer := 36; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + SIM_MODE : string := "SAFE" + ); + + port( + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DBITERR : out std_ulogic; + DO : out std_logic_vector (63 downto 0); + DOP : out std_logic_vector (7 downto 0); + ECCPARITY : out std_logic_vector (7 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (12 downto 0); + RDERR : out std_ulogic; + SBITERR : out std_ulogic; + WRCOUNT : out std_logic_vector (12 downto 0); + WRERR : out std_ulogic; + + DI : in std_logic_vector (63 downto 0); + DIP : in std_logic_vector (7 downto 0); + RDCLK : in std_ulogic; + RDRCLK : in std_ulogic; + RDEN : in std_ulogic; + RST : in std_ulogic; + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); + end component; + + + constant SYNC_PATH_DELAY : time := 100 ps; + signal GND_4 : std_logic_vector(3 downto 0) := (others => '0'); + signal GND_32 : std_logic_vector(31 downto 0) := (others => '0'); + signal OPEN_4 : std_logic_vector(3 downto 0); + signal OPEN_32 : std_logic_vector(31 downto 0); + signal OPEN_8 : std_logic_vector(7 downto 0); + signal do_dly : std_logic_vector(31 downto 0) := (others => '0'); + signal dop_dly : std_logic_vector(3 downto 0) := (others => '0'); + signal almostfull_dly : std_ulogic := '0'; + signal almostempty_dly : std_ulogic := '0'; + signal empty_dly : std_ulogic := '0'; + signal full_dly : std_ulogic := '0'; + signal rderr_dly : std_ulogic := '0'; + signal wrerr_dly : std_ulogic := '0'; + signal rdcount_dly : std_logic_vector(12 downto 0) := (others => '0'); + signal wrcount_dly : std_logic_vector(12 downto 0) := (others => '0'); + + +begin + +FIFO36_EXP_inst : AFIFO36_INTERNAL + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DATA_WIDTH => DATA_WIDTH, + DO_REG => DO_REG, + EN_SYN => EN_SYN, + SIM_MODE => SIM_MODE, + FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH + ) + + port map ( + DO(31 downto 0) => do_dly, + DO(63 downto 32) => OPEN_32, + DOP(3 downto 0) => dop_dly, + DOP(7 downto 4) => OPEN_4, + ALMOSTEMPTY => almostempty_dly, + ALMOSTFULL => almostfull_dly, + ECCPARITY => OPEN_8, + EMPTY => empty_dly, + FULL => full_dly, + RDCOUNT => rdcount_dly, + WRCOUNT => wrcount_dly, + RDERR => rderr_dly, + SBITERR => OPEN, + DBITERR => OPEN, + WRERR => wrerr_dly, + DI(31 downto 0) => DI, + DI(63 downto 32) => GND_32, + DIP(3 downto 0) => DIP, + DIP(7 downto 4) => GND_4, + WREN => WREN, + RDEN => RDEN, + RDCLK => RDCLKL, + RDRCLK => RDRCLKL, + WRCLK => WRCLKL, + RST => RST + ); + + prcs_output_wtiming: process (do_dly, dop_dly, almostempty_dly, almostfull_dly, empty_dly, full_dly, rdcount_dly, wrcount_dly, rderr_dly, wrerr_dly) + begin -- process prcs_output_wtiming + + ALMOSTEMPTY <= almostempty_dly after SYNC_PATH_DELAY; + ALMOSTFULL <= almostfull_dly after SYNC_PATH_DELAY; + empty <= empty_dly after SYNC_PATH_DELAY; + full <= full_dly after SYNC_PATH_DELAY; + DO <= do_dly after SYNC_PATH_DELAY; + DOP <= dop_dly after SYNC_PATH_DELAY; + RDCOUNT <= rdcount_dly after SYNC_PATH_DELAY; + WRCOUNT <= wrcount_dly after SYNC_PATH_DELAY; + RDERR <= rderr_dly after SYNC_PATH_DELAY; + WRERR <= wrerr_dly after SYNC_PATH_DELAY; + + end process prcs_output_wtiming; + +end FIFO36_EXP_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/fifo36.vhd,v 1.7 2007/06/15 21:01:09 wloo Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2005 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 36K-Bit FIFO +-- /___/ /\ Filename : FIFO36.vhd +-- \ \ / \ Timestamp : Tues October 18 16:43:59 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 10/18/05 - Initial version. +-- 06/14/07 - Implemented high performace version of the model. +-- End Revision + +----- CELL FIFO36 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; +use unisim.vpkg.all; + +entity FIFO36 is +generic ( + + ALMOST_FULL_OFFSET : bit_vector := X"0080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"0080"; + DATA_WIDTH : integer := 4; + DO_REG : integer := 1; + EN_SYN : boolean := FALSE; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + SIM_MODE : string := "SAFE" + + ); + +port ( + + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DO : out std_logic_vector (31 downto 0); + DOP : out std_logic_vector (3 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (12 downto 0); + RDERR : out std_ulogic; + WRCOUNT : out std_logic_vector (12 downto 0); + WRERR : out std_ulogic; + + DI : in std_logic_vector (31 downto 0); + DIP : in std_logic_vector (3 downto 0); + RDCLK : in std_ulogic; + RDEN : in std_ulogic; + RST : in std_ulogic; + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); +end FIFO36; + +architecture FIFO36_V of FIFO36 is + + component AFIFO36_INTERNAL + + generic( + ALMOST_FULL_OFFSET : bit_vector := X"0080"; + ALMOST_EMPTY_OFFSET : bit_vector := X"0080"; + DATA_WIDTH : integer := 4; + DO_REG : integer := 1; + EN_ECC_READ : boolean := FALSE; + EN_ECC_WRITE : boolean := FALSE; + EN_SYN : boolean := FALSE; + FIFO_SIZE : integer := 36; + FIRST_WORD_FALL_THROUGH : boolean := FALSE; + SIM_MODE : string := "SAFE" + ); + + port( + ALMOSTEMPTY : out std_ulogic; + ALMOSTFULL : out std_ulogic; + DBITERR : out std_ulogic; + DO : out std_logic_vector (63 downto 0); + DOP : out std_logic_vector (7 downto 0); + ECCPARITY : out std_logic_vector (7 downto 0); + EMPTY : out std_ulogic; + FULL : out std_ulogic; + RDCOUNT : out std_logic_vector (12 downto 0); + RDERR : out std_ulogic; + SBITERR : out std_ulogic; + WRCOUNT : out std_logic_vector (12 downto 0); + WRERR : out std_ulogic; + + DI : in std_logic_vector (63 downto 0); + DIP : in std_logic_vector (7 downto 0); + RDCLK : in std_ulogic; + RDRCLK : in std_ulogic; + RDEN : in std_ulogic; + RST : in std_ulogic; + WRCLK : in std_ulogic; + WREN : in std_ulogic + ); + end component; + + + constant SYNC_PATH_DELAY : time := 100 ps; + signal GND_4 : std_logic_vector(3 downto 0) := (others => '0'); + signal GND_32 : std_logic_vector(31 downto 0) := (others => '0'); + signal OPEN_4 : std_logic_vector(3 downto 0); + signal OPEN_32 : std_logic_vector(31 downto 0); + signal OPEN_8 : std_logic_vector(7 downto 0); + signal do_dly : std_logic_vector(31 downto 0) := (others => '0'); + signal dop_dly : std_logic_vector(3 downto 0) := (others => '0'); + signal almostfull_dly : std_ulogic := '0'; + signal almostempty_dly : std_ulogic := '0'; + signal empty_dly : std_ulogic := '0'; + signal full_dly : std_ulogic := '0'; + signal rderr_dly : std_ulogic := '0'; + signal wrerr_dly : std_ulogic := '0'; + signal rdcount_dly : std_logic_vector(12 downto 0) := (others => '0'); + signal wrcount_dly : std_logic_vector(12 downto 0) := (others => '0'); + + +begin + +FIFO36_inst : AFIFO36_INTERNAL + generic map ( + ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, + ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, + DATA_WIDTH => DATA_WIDTH, + DO_REG => DO_REG, + EN_SYN => EN_SYN, + SIM_MODE => SIM_MODE, + FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH + ) + + port map ( + DO(31 downto 0) => do_dly, + DO(63 downto 32) => OPEN_32, + DOP(3 downto 0) => dop_dly, + DOP(7 downto 4) => OPEN_4, + ALMOSTEMPTY => almostempty_dly, + ALMOSTFULL => almostfull_dly, + ECCPARITY => OPEN_8, + EMPTY => empty_dly, + FULL => full_dly, + RDCOUNT => rdcount_dly, + WRCOUNT => wrcount_dly, + RDERR => rderr_dly, + SBITERR => OPEN, + DBITERR => OPEN, + WRERR => wrerr_dly, + DI(31 downto 0) => DI, + DI(63 downto 32) => GND_32, + DIP(3 downto 0) => DIP, + DIP(7 downto 4) => GND_4, + WREN => WREN, + RDEN => RDEN, + RDCLK => RDCLK, + RDRCLK => RDCLK, + WRCLK => WRCLK, + RST => RST + ); + + prcs_initialize:process + variable first_time : boolean := true; + + begin + if (first_time) then + case DATA_WIDTH is + when 4 | 9 | 18 | 36 => null; + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error ", + GenericName => " DATA_WIDTH ", + EntityName => "FIFO36", + GenericValue => DATA_WIDTH, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 4, 9, 18 and 36 ", + TailMsg => "", + MsgSeverity => error + ); + end case; + first_time := false; + end if; + wait; + end process prcs_initialize; + + + prcs_output_wtiming: process (do_dly, dop_dly, almostempty_dly, almostfull_dly, empty_dly, full_dly, rdcount_dly, wrcount_dly, rderr_dly, wrerr_dly) + begin -- process prcs_output_wtiming + + ALMOSTEMPTY <= almostempty_dly after SYNC_PATH_DELAY; + ALMOSTFULL <= almostfull_dly after SYNC_PATH_DELAY; + empty <= empty_dly after SYNC_PATH_DELAY; + full <= full_dly after SYNC_PATH_DELAY; + DO <= do_dly after SYNC_PATH_DELAY; + DOP <= dop_dly after SYNC_PATH_DELAY; + RDCOUNT <= rdcount_dly after SYNC_PATH_DELAY; + WRCOUNT <= wrcount_dly after SYNC_PATH_DELAY; + RDERR <= rderr_dly after SYNC_PATH_DELAY; + WRERR <= wrerr_dly after SYNC_PATH_DELAY; + + end process prcs_output_wtiming; + +end FIFO36_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / +-- /___/ /\ Filename : FRAME_ECC_VIRTEX5.vhd +-- \ \ / \ Timestamp : Thu Jun 2 10:57:03 PDT 2005 +-- \___\/\___\ +-- +-- Revision: +-- 06/03/05 - Initial version. + +----- CELL FRAME_ECC_VIRTEX5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity FRAME_ECC_VIRTEX5 is + port( + CRCERROR : out std_ulogic; + ECCERROR : out std_ulogic; + SYNDROME : out std_logic_vector(11 downto 0); + SYNDROMEVALID : out std_ulogic + ); + +end FRAME_ECC_VIRTEX5; + +architecture FRAME_ECC_VIRTEX5_V of FRAME_ECC_VIRTEX5 is + +begin +end FRAME_ECC_VIRTEX5_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Internal Configuration Access Port for VIRTEX5 +-- /___/ /\ Filename : ICAP_VIRTEX5.vhd +-- \ \ / \ Timestamp : Thu Jun 03 10:57:04 PDT 2005 +-- \___\/\___\ +-- +-- Revision: +-- 06/03/05 - Initial version. + +----- CELL ICAP_VIRTEX5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +entity ICAP_VIRTEX5 is + generic( + ICAP_WIDTH : string := "X8" + ); + + + port( + BUSY : out std_ulogic; + O : out std_logic_vector(31 downto 0); + + CE : in std_ulogic; + CLK : in std_ulogic; + I : in std_logic_vector(31 downto 0); + WRITE : in std_ulogic + ); + +end ICAP_VIRTEX5; + +architecture ICAP_VIRTEX5_V of ICAP_VIRTEX5 is + +begin +--#################################################################### +--##### Initialization ### +--#################################################################### + prcs_init:process + begin + if((ICAP_WIDTH /="X8") and (ICAP_WIDTH /="X16") and (ICAP_WIDTH /="X32")) then + assert false + report "Attribute Syntax Error: The allowed values for ICAP_WIDTH are X8, X16 or X32." + severity Failure; + end if; + + wait; + end process prcs_init; +end ICAP_VIRTEX5_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / Input Dual Data-Rate Register with Dual Clock inputs. +-- /___/ /\ Filename : IDDR_2CLK.vhd +-- \ \ / \ Timestamp : Mon Jun 26 08:18:20 PST 2006 +-- \___\/\___\ +-- +-- Revision: +-- 06/26/06 - Initial version. +-- 05/15/07 - CR 438883 fix +-- End Revision + + +----- CELL IDDR_2CLK ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + + +library unisim; +use unisim.vpkg.all; + +entity IDDR_2CLK is + + generic( + + DDR_CLK_EDGE : string := "OPPOSITE_EDGE"; + INIT_Q1 : bit := '0'; + INIT_Q2 : bit := '0'; + SRTYPE : string := "SYNC" + ); + + port( + Q1 : out std_ulogic; + Q2 : out std_ulogic; + + C : in std_ulogic; + CB : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); + +end IDDR_2CLK; + +architecture IDDR_2CLK_V OF IDDR_2CLK is + + + constant SYNC_PATH_DELAY : time := 100 ps; + + signal C_ipd : std_ulogic := 'X'; + signal CB_ipd : std_ulogic := 'X'; + signal CE_ipd : std_ulogic := 'X'; + signal D_ipd : std_ulogic := 'X'; + signal GSR_ipd : std_ulogic := '0'; + signal R_ipd : std_ulogic := 'X'; + signal S_ipd : std_ulogic := 'X'; + + signal C_dly : std_ulogic := 'X'; + signal CB_dly : std_ulogic := 'X'; + signal CE_C_dly : std_ulogic := 'X'; + signal CE_CB_dly : std_ulogic := 'X'; + signal D_C_dly : std_ulogic := 'X'; + signal D_CB_dly : std_ulogic := 'X'; + signal GSR_dly : std_ulogic := '0'; + signal R_dly : std_ulogic := 'X'; + signal S_dly : std_ulogic := 'X'; + signal R_C_dly : std_ulogic := 'X'; + signal R_CB_dly : std_ulogic := 'X'; + signal S_C_dly : std_ulogic := 'X'; + signal S_CB_dly : std_ulogic := 'X'; + + signal Q1_zd : std_ulogic := 'X'; + signal Q2_zd : std_ulogic := 'X'; + + signal Q1_viol : std_ulogic := 'X'; + signal Q2_viol : std_ulogic := 'X'; + + signal Q1_o_reg : std_ulogic := 'X'; + signal Q2_o_reg : std_ulogic := 'X'; + signal Q3_o_reg : std_ulogic := 'X'; + signal Q4_o_reg : std_ulogic := 'X'; + + signal ddr_clk_edge_type : integer := -999; + signal sr_type : integer := -999; +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + C_dly <= C after 0 ps; + CB_dly <= CB after 0 ps; + CE_C_dly <= CE after 0 ps; + CE_CB_dly <= CE after 0 ps; + D_C_dly <= D after 0 ps; + D_CB_dly <= D after 0 ps; + GSR_dly <= '0' after 0 ps; + R_dly <= R after 0 ps; + R_C_dly <= R after 0 ps; + R_CB_dly <= R after 0 ps; + S_dly <= S after 0 ps; + S_C_dly <= S after 0 ps; + S_CB_dly <= S after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + + begin + if((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then + ddr_clk_edge_type <= 1; + elsif((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then + ddr_clk_edge_type <= 2; + elsif((DDR_CLK_EDGE = "SAME_EDGE_PIPELINED") or (DDR_CLK_EDGE = "same_edge_pipelined")) then + ddr_clk_edge_type <= 3; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DDR_CLK_EDGE ", + EntityName => "/IDDR_2CLK", + GenericValue => DDR_CLK_EDGE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " OPPOSITE_EDGE or SAME_EDGE or SAME_EDGE_PIPELINED.", + TailMsg => "", + MsgSeverity => ERROR + ); + end if; + + if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then + sr_type <= 1; + elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then + sr_type <= 2; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " SRTYPE ", + EntityName => "/IDDR_2CLK", + GenericValue => SRTYPE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " ASYNC or SYNC. ", + TailMsg => "", + MsgSeverity => ERROR + ); + end if; + + wait; + end process prcs_init; +--#################################################################### +--##### q1_q2_q3_q4 reg ##### +--#################################################################### + prcs_q1q2q3q4_reg:process(C_dly, CB_dly, GSR_dly, R_dly, S_dly) + variable Q1_var : std_ulogic := TO_X01(INIT_Q1); + variable Q2_var : std_ulogic := TO_X01(INIT_Q2); + variable Q3_var : std_ulogic := TO_X01(INIT_Q1); + variable Q4_var : std_ulogic := TO_X01(INIT_Q2); + begin + if(GSR_dly = '1') then + Q1_var := TO_X01(INIT_Q1); + Q3_var := TO_X01(INIT_Q1); + Q2_var := TO_X01(INIT_Q2); + Q4_var := TO_X01(INIT_Q2); + elsif(GSR_dly = '0') then + case sr_type is + when 1 => + if(R_dly = '1') then + Q1_var := '0'; + Q2_var := '0'; + Q3_var := '0'; + Q4_var := '0'; + elsif((R_dly = '0') and (S_dly = '1')) then + Q1_var := '1'; + Q2_var := '1'; + Q3_var := '1'; + Q4_var := '1'; + elsif((R_dly = '0') and (S_dly = '0')) then + if(rising_edge(C_dly)) then + if(CE_C_dly = '1') then + Q3_var := Q1_var; + Q1_var := D_C_dly; + Q4_var := Q2_var; + end if; + end if; + if(rising_edge(CB_dly)) then + if(CE_CB_dly = '1') then + Q2_var := D_CB_dly; + end if; + end if; + end if; + + when 2 => + if(rising_edge(C_dly)) then + if(R_C_dly = '1') then + Q1_var := '0'; + Q3_var := '0'; + Q4_var := '0'; + elsif((R_C_dly = '0') and (S_C_dly = '1')) then + Q1_var := '1'; + Q3_var := '1'; + Q4_var := '1'; + elsif((R_C_dly = '0') and (S_C_dly = '0')) then + if(CE_C_dly = '1') then + Q3_var := Q1_var; + Q1_var := D_C_dly; + Q4_var := Q2_var; + end if; + end if; + end if; + + if(rising_edge(CB_dly)) then + if(R_CB_dly = '1') then + Q2_var := '0'; + elsif((R_CB_dly = '0') and (S_CB_dly = '1')) then + Q2_var := '1'; + elsif((R_CB_dly = '0') and (S_CB_dly = '0')) then + if(CE_CB_dly = '1') then + Q2_var := D_CB_dly; + end if; + end if; + end if; + + when others => + null; + end case; + end if; + + q1_o_reg <= Q1_var; + q2_o_reg <= Q2_var; + q3_o_reg <= Q3_var; + q4_o_reg <= Q4_var; + + end process prcs_q1q2q3q4_reg; +--#################################################################### +--##### q1 & q2 mux ##### +--#################################################################### + prcs_q1q2_mux:process(q1_o_reg, q2_o_reg, q3_o_reg, q4_o_reg) + begin + case ddr_clk_edge_type is + when 1 => + Q1_zd <= q1_o_reg; + Q2_zd <= q2_o_reg; + when 2 => + Q1_zd <= q1_o_reg; + Q2_zd <= q4_o_reg; + when 3 => + Q1_zd <= q3_o_reg; + Q2_zd <= q4_o_reg; + when others => + null; + end case; + end process prcs_q1q2_mux; +--#################################################################### + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(Q1_zd, Q2_zd) + begin + Q1 <= Q1_zd after SYNC_PATH_DELAY; + Q2 <= Q2_zd after SYNC_PATH_DELAY; + end process prcs_output; +--#################################################################### + + +end IDDR_2CLK_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / Input and/or Output Fixed or Variable Delay Element +-- /___/ /\ Filename : IODELAY.vhd +-- \ \ / \ Timestamp : Wed Aug 10 16:51:05 PDT 2005 +-- \___\/\___\ +-- +-- Revision: +-- 08/10/05 - Initial version. +-- 01/11/06 - Changed Equation for CALC_TAPDELAY -- FP +-- 03/10/06 - CR 227041 -- Added path delays -- FP +-- 06/04/06 - Made the model independent of T pin (except in DELAY_SRC=IO mode) -- FP +-- 07/21/06 - CR 234556 fix. Added SIM_DELAY_D to Simprims -- FP +-- 01/03/07 - For unisims, the fixed Delay value is taken from the sdf. +-- 03/26/07 - CR 436199 HIGH_PERFORMANCE_MODE default change -- FP +-- 05/03/07 - CR 438921 SIGNAL_PATTERN addition -- FP +-- 06/11/07 - CR 437230 -- added delay buffer chain +-- 08/29/07 - CR 445561 -- Replaced D_IOBDELAY_OFFSET with D_IODELAY_OFFSET +-- End Revision + +----- CELL IODELAY ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + + +library unisim; +use unisim.vpkg.all; + +entity IODELAY is + + generic( + + DELAY_SRC : string := "I"; + HIGH_PERFORMANCE_MODE : boolean := true; + IDELAY_TYPE : string := "DEFAULT"; + IDELAY_VALUE : integer := 0; + ODELAY_VALUE : integer := 0; + REFCLK_FREQUENCY : real := 200.0; + SIGNAL_PATTERN : string := "DATA" + ); + + port( + DATAOUT : out std_ulogic; + + C : in std_ulogic; + CE : in std_ulogic; + DATAIN : in std_ulogic; + IDATAIN : in std_ulogic; + INC : in std_ulogic; + ODATAIN : in std_ulogic; + RST : in std_ulogic; + T : in std_ulogic + ); + +end IODELAY; + +architecture IODELAY_V OF IODELAY is + + constant ILEAK_ADJUST : real := 1.0; + constant D_IODELAY_OFFSET : real := 0.0; + +----------------------------------------------------------- + + constant MAX_IDELAY_COUNT : integer := 63; + constant MIN_IDELAY_COUNT : integer := 0; + constant MAX_ODELAY_COUNT : integer := 63; + constant MIN_ODELAY_COUNT : integer := 0; + + constant MAX_REFCLK_FREQUENCY : real := 225.0; + constant MIN_REFCLK_FREQUENCY : real := 175.0; + + + signal C_ipd : std_ulogic := 'X'; + signal CE_ipd : std_ulogic := 'X'; + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := 'X'; + signal DATAIN_ipd : std_ulogic := 'X'; + signal IDATAIN_ipd : std_ulogic := 'X'; + signal INC_ipd : std_ulogic := 'X'; + signal ODATAIN_ipd : std_ulogic := 'X'; + signal RST_ipd : std_ulogic := 'X'; + signal T_ipd : std_ulogic := 'X'; + + signal C_dly : std_ulogic := 'X'; + signal CE_dly : std_ulogic := 'X'; + signal GSR_dly : std_ulogic := '0'; + signal DATAIN_dly : std_ulogic := 'X'; + signal IDATAIN_dly : std_ulogic := 'X'; + signal INC_dly : std_ulogic := 'X'; + signal ODATAIN_dly : std_ulogic := 'X'; + signal RST_dly : std_ulogic := 'X'; + signal T_dly : std_ulogic := 'X'; + + signal IDATAOUT_delayed : std_ulogic := 'X'; +-- signal IDATAOUT_zd : std_ulogic := 'X'; +-- signal IDATAOUT_viol : std_ulogic := 'X'; + + signal ODATAOUT_delayed : std_ulogic := 'X'; +-- signal ODATAOUT_zd : std_ulogic := 'X'; +-- signal ODATAOUT_viol : std_ulogic := 'X'; + + signal DATAOUT_zd : std_ulogic := 'X'; +-- signal DATAOUT_viol : std_ulogic := 'X'; + + signal iDelay : time := 0.0 ps; + signal oDelay : time := 0.0 ps; + + signal data_mux : std_ulogic := 'X'; + signal Violation : std_ulogic := '0'; + + signal OneTapDelay : time := 0.0 ps; + signal idelay_count : integer := IDELAY_VALUE; + signal odelay_count : integer := 0; + signal tap_out : std_ulogic := 'X'; + + signal delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3, + delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7, + delay_chain_8, delay_chain_9, delay_chain_10, delay_chain_11, + delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15, + delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19, + delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23, + delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27, + delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31, + delay_chain_32, delay_chain_33, delay_chain_34, delay_chain_35, + delay_chain_36, delay_chain_37, delay_chain_38, delay_chain_39, + delay_chain_40, delay_chain_41, delay_chain_42, delay_chain_43, + delay_chain_44, delay_chain_45, delay_chain_46, delay_chain_47, + delay_chain_48, delay_chain_49, delay_chain_50, delay_chain_51, + delay_chain_52, delay_chain_53, delay_chain_54, delay_chain_55, + delay_chain_56, delay_chain_57, delay_chain_58, delay_chain_59, + delay_chain_60, delay_chain_61, delay_chain_62, delay_chain_63 : std_ulogic; + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + C_dly <= C after 0 ps; + CE_dly <= CE after 0 ps; + DATAIN_dly <= DATAIN after 0 ps; + IDATAIN_dly <= IDATAIN after 0 ps; + INC_dly <= INC after 0 ps; + ODATAIN_dly <= ODATAIN after 0 ps; + RST_dly <= RST after 0 ps; + T_dly <= T after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + variable TapCount_var : integer := 0; + variable IsTapDelay_var : boolean := true; + variable idelaytypefixed_var : boolean := false; + variable idelaytypedefault_var : boolean := false; + variable CALC_TAPDELAY : real := 0.0; + begin + -------- SIGNAL_PATTERN check + if((SIGNAL_PATTERN /= "CLOCK") and (SIGNAL_PATTERN /= "DATA"))then + assert false + report "Attribute Syntax Error: Legal values for SIGNAL_PATTERN are DATA or CLOCK" + severity Failure; + end if; + + -------- HIGH_PERFORMANCE_MODE check + + case HIGH_PERFORMANCE_MODE is + when true | false => null; + when others => + assert false + report "Attribute Syntax Error: The attribute HIGH_PERFORMANCE_MODE on IODELAY must be set to either true or false." + severity Failure; + end case; + + -------- IDELAY_TYPE check + + if(IDELAY_TYPE = "FIXED") then + idelaytypefixed_var := true; + elsif(IDELAY_TYPE = "VARIABLE") then + idelaytypefixed_var := false; + elsif(IDELAY_TYPE = "DEFAULT") then + idelaytypedefault_var := true; + idelaytypefixed_var := false; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " IDELAY_TYPE ", + EntityName => "/IODELAY", + GenericValue => IDELAY_TYPE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " DEFAULT, FIXED or VARIABLE ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + -------- IDELAY_VALUE check + + if((IDELAY_VALUE < MIN_IDELAY_COUNT) or (ODELAY_VALUE > MAX_IDELAY_COUNT)) then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " IDELAY_VALUE ", + EntityName => "/IODELAY", + GenericValue => IDELAY_VALUE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, ..., 62, 63 ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + -------- ODELAY_VALUE check + + if((ODELAY_VALUE < MIN_ODELAY_COUNT) or (ODELAY_VALUE > MAX_ODELAY_COUNT)) then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " ODELAY_VALUE ", + EntityName => "/IODELAY", + GenericValue => ODELAY_VALUE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, ..., 62, 63 ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + -------- REFCLK_FREQUENCY check + + if((REFCLK_FREQUENCY < MIN_REFCLK_FREQUENCY) or (REFCLK_FREQUENCY > MAX_REFCLK_FREQUENCY)) then + assert false + report "Attribute Syntax Error: Legal values for REFCLK_FREQUENCY are 175.0 to 225.0" + severity Failure; + end if; + + odelay_count <= ODELAY_VALUE; + CALC_TAPDELAY := ((1.0/REFCLK_FREQUENCY) * (1.0/64.0) * ILEAK_ADJUST * 1000000.0) + D_IODELAY_OFFSET ; + OneTapDelay <= CALC_TAPDELAY * 1.0 ps; + wait; + end process prcs_init; +--#################################################################### +--##### CALCULATE iDelay ##### +--#################################################################### + prcs_calc_idelay:process(C_dly, GSR_dly, RST_dly) + variable idelay_count_var : integer :=0; + variable FIRST_TIME : boolean :=true; + variable BaseTime_var : time := 1 ps ; +-- variable CALC_TAPDELAY : real := 0.0; + begin + if(IDELAY_TYPE = "VARIABLE") then + if((GSR_dly = '1') or (FIRST_TIME))then + idelay_count_var := IDELAY_VALUE; +-- CALC_TAPDELAY := ((1.0/REFCLK_FREQUENCY) * (1.0/64.0) * ILEAK_ADJUST * 1000000.0) + D_IODELAY_OFFSET ; +-- iDelay <= real(idelay_count_var) * CALC_TAPDELAY * BaseTime_var; + FIRST_TIME := false; + elsif(GSR_dly = '0') then + if(rising_edge(C_dly)) then + if(RST_dly = '1') then + idelay_count_var := IDELAY_VALUE; + elsif((RST_dly = '0') and (CE_dly = '1')) then + if(INC_dly = '1') then + if (idelay_count_var < MAX_IDELAY_COUNT) then + idelay_count_var := idelay_count_var + 1; + else + idelay_count_var := MIN_IDELAY_COUNT; + end if; + elsif(INC_dly = '0') then + if (idelay_count_var > MIN_IDELAY_COUNT) then + idelay_count_var := idelay_count_var - 1; + else + idelay_count_var := MAX_IDELAY_COUNT; + end if; + + end if; -- INC_dly + end if; -- RST_dly +-- iDelay <= real(idelay_count_var) * CALC_TAPDELAY * BaseTime_var; + idelay_count <= idelay_count_var; + end if; -- C_dly + end if; -- GSR_dly + + end if; -- IDELAY_TYPE + end process prcs_calc_idelay; +--#################################################################### +--##### SELECT IDATA_MUX ##### +--#################################################################### + prcs_data_mux:process(DATAIN_dly, IDATAIN_dly, ODATAIN_dly, T_dly) + begin + if(DELAY_SRC = "I") then + data_mux <= IDATAIN_dly; + elsif(DELAY_SRC = "O") then + data_mux <= ODATAIN_dly; + elsif(DELAY_SRC = "IO") then + data_mux <= (IDATAIN_dly and T_dly) or (ODATAIN_dly and (not T_dly)); + elsif(DELAY_SRC = "DATAIN") then + data_mux <= DATAIN_dly; + else + assert false + report "Attribute Syntax Error : Legal values for DELAY_SRC on IODELAY instance are I, O, IO or DATAIN." + severity Failure; + end if; + end process prcs_data_mux; +--#################################################################### +--##### DELAY BUFFERS ##### +--#################################################################### +delay_chain_0 <= transport data_mux; +delay_chain_1 <= transport delay_chain_0 after OneTapDelay; +delay_chain_2 <= transport delay_chain_1 after OneTapDelay; +delay_chain_3 <= transport delay_chain_2 after OneTapDelay; +delay_chain_4 <= transport delay_chain_3 after OneTapDelay; +delay_chain_5 <= transport delay_chain_4 after OneTapDelay; +delay_chain_6 <= transport delay_chain_5 after OneTapDelay; +delay_chain_7 <= transport delay_chain_6 after OneTapDelay; +delay_chain_8 <= transport delay_chain_7 after OneTapDelay; +delay_chain_9 <= transport delay_chain_8 after OneTapDelay; +delay_chain_10 <= transport delay_chain_9 after OneTapDelay; +delay_chain_11 <= transport delay_chain_10 after OneTapDelay; +delay_chain_12 <= transport delay_chain_11 after OneTapDelay; +delay_chain_13 <= transport delay_chain_12 after OneTapDelay; +delay_chain_14 <= transport delay_chain_13 after OneTapDelay; +delay_chain_15 <= transport delay_chain_14 after OneTapDelay; +delay_chain_16 <= transport delay_chain_15 after OneTapDelay; +delay_chain_17 <= transport delay_chain_16 after OneTapDelay; +delay_chain_18 <= transport delay_chain_17 after OneTapDelay; +delay_chain_19 <= transport delay_chain_18 after OneTapDelay; +delay_chain_20 <= transport delay_chain_19 after OneTapDelay; +delay_chain_21 <= transport delay_chain_20 after OneTapDelay; +delay_chain_22 <= transport delay_chain_21 after OneTapDelay; +delay_chain_23 <= transport delay_chain_22 after OneTapDelay; +delay_chain_24 <= transport delay_chain_23 after OneTapDelay; +delay_chain_25 <= transport delay_chain_24 after OneTapDelay; +delay_chain_26 <= transport delay_chain_25 after OneTapDelay; +delay_chain_27 <= transport delay_chain_26 after OneTapDelay; +delay_chain_28 <= transport delay_chain_27 after OneTapDelay; +delay_chain_29 <= transport delay_chain_28 after OneTapDelay; +delay_chain_30 <= transport delay_chain_29 after OneTapDelay; +delay_chain_31 <= transport delay_chain_30 after OneTapDelay; +delay_chain_32 <= transport delay_chain_31 after OneTapDelay; +delay_chain_33 <= transport delay_chain_32 after OneTapDelay; +delay_chain_34 <= transport delay_chain_33 after OneTapDelay; +delay_chain_35 <= transport delay_chain_34 after OneTapDelay; +delay_chain_36 <= transport delay_chain_35 after OneTapDelay; +delay_chain_37 <= transport delay_chain_36 after OneTapDelay; +delay_chain_38 <= transport delay_chain_37 after OneTapDelay; +delay_chain_39 <= transport delay_chain_38 after OneTapDelay; +delay_chain_40 <= transport delay_chain_39 after OneTapDelay; +delay_chain_41 <= transport delay_chain_40 after OneTapDelay; +delay_chain_42 <= transport delay_chain_41 after OneTapDelay; +delay_chain_43 <= transport delay_chain_42 after OneTapDelay; +delay_chain_44 <= transport delay_chain_43 after OneTapDelay; +delay_chain_45 <= transport delay_chain_44 after OneTapDelay; +delay_chain_46 <= transport delay_chain_45 after OneTapDelay; +delay_chain_47 <= transport delay_chain_46 after OneTapDelay; +delay_chain_48 <= transport delay_chain_47 after OneTapDelay; +delay_chain_49 <= transport delay_chain_48 after OneTapDelay; +delay_chain_50 <= transport delay_chain_49 after OneTapDelay; +delay_chain_51 <= transport delay_chain_50 after OneTapDelay; +delay_chain_52 <= transport delay_chain_51 after OneTapDelay; +delay_chain_53 <= transport delay_chain_52 after OneTapDelay; +delay_chain_54 <= transport delay_chain_53 after OneTapDelay; +delay_chain_55 <= transport delay_chain_54 after OneTapDelay; +delay_chain_56 <= transport delay_chain_55 after OneTapDelay; +delay_chain_57 <= transport delay_chain_56 after OneTapDelay; +delay_chain_58 <= transport delay_chain_57 after OneTapDelay; +delay_chain_59 <= transport delay_chain_58 after OneTapDelay; +delay_chain_60 <= transport delay_chain_59 after OneTapDelay; +delay_chain_61 <= transport delay_chain_60 after OneTapDelay; +delay_chain_62 <= transport delay_chain_61 after OneTapDelay; +delay_chain_63 <= transport delay_chain_62 after OneTapDelay; + +--#################################################################### +--##### Assign Tap Delays ##### +--#################################################################### + prcs_AssignDelays:process + begin + if(((DELAY_SRC = "IO") and (T_dly = '1')) or (DELAY_SRC = "I") or (DELAY_SRC = "DATAIN")) then + case idelay_count is + when 0 => tap_out <= delay_chain_0; + when 1 => tap_out <= delay_chain_1; + when 2 => tap_out <= delay_chain_2; + when 3 => tap_out <= delay_chain_3; + when 4 => tap_out <= delay_chain_4; + when 5 => tap_out <= delay_chain_5; + when 6 => tap_out <= delay_chain_6; + when 7 => tap_out <= delay_chain_7; + when 8 => tap_out <= delay_chain_8; + when 9 => tap_out <= delay_chain_9; + when 10 => tap_out <= delay_chain_10; + when 11 => tap_out <= delay_chain_11; + when 12 => tap_out <= delay_chain_12; + when 13 => tap_out <= delay_chain_13; + when 14 => tap_out <= delay_chain_14; + when 15 => tap_out <= delay_chain_15; + when 16 => tap_out <= delay_chain_16; + when 17 => tap_out <= delay_chain_17; + when 18 => tap_out <= delay_chain_18; + when 19 => tap_out <= delay_chain_19; + when 20 => tap_out <= delay_chain_20; + when 21 => tap_out <= delay_chain_21; + when 22 => tap_out <= delay_chain_22; + when 23 => tap_out <= delay_chain_23; + when 24 => tap_out <= delay_chain_24; + when 25 => tap_out <= delay_chain_25; + when 26 => tap_out <= delay_chain_26; + when 27 => tap_out <= delay_chain_27; + when 28 => tap_out <= delay_chain_28; + when 29 => tap_out <= delay_chain_29; + when 30 => tap_out <= delay_chain_30; + when 31 => tap_out <= delay_chain_31; + when 32 => tap_out <= delay_chain_32; + when 33 => tap_out <= delay_chain_33; + when 34 => tap_out <= delay_chain_34; + when 35 => tap_out <= delay_chain_35; + when 36 => tap_out <= delay_chain_36; + when 37 => tap_out <= delay_chain_37; + when 38 => tap_out <= delay_chain_38; + when 39 => tap_out <= delay_chain_39; + when 40 => tap_out <= delay_chain_40; + when 41 => tap_out <= delay_chain_41; + when 42 => tap_out <= delay_chain_42; + when 43 => tap_out <= delay_chain_43; + when 44 => tap_out <= delay_chain_44; + when 45 => tap_out <= delay_chain_45; + when 46 => tap_out <= delay_chain_46; + when 47 => tap_out <= delay_chain_47; + when 48 => tap_out <= delay_chain_48; + when 49 => tap_out <= delay_chain_49; + when 50 => tap_out <= delay_chain_50; + when 51 => tap_out <= delay_chain_51; + when 52 => tap_out <= delay_chain_52; + when 53 => tap_out <= delay_chain_53; + when 54 => tap_out <= delay_chain_54; + when 55 => tap_out <= delay_chain_55; + when 56 => tap_out <= delay_chain_56; + when 57 => tap_out <= delay_chain_57; + when 58 => tap_out <= delay_chain_58; + when 59 => tap_out <= delay_chain_59; + when 60 => tap_out <= delay_chain_60; + when 61 => tap_out <= delay_chain_61; + when 62 => tap_out <= delay_chain_62; + when 63 => tap_out <= delay_chain_63; + when others => + tap_out <= delay_chain_0; + end case; + elsif(((DELAY_SRC = "IO") and (T_dly = '0')) or (DELAY_SRC = "O")) then + case odelay_count is + when 0 => tap_out <= delay_chain_0; + when 1 => tap_out <= delay_chain_1; + when 2 => tap_out <= delay_chain_2; + when 3 => tap_out <= delay_chain_3; + when 4 => tap_out <= delay_chain_4; + when 5 => tap_out <= delay_chain_5; + when 6 => tap_out <= delay_chain_6; + when 7 => tap_out <= delay_chain_7; + when 8 => tap_out <= delay_chain_8; + when 9 => tap_out <= delay_chain_9; + when 10 => tap_out <= delay_chain_10; + when 11 => tap_out <= delay_chain_11; + when 12 => tap_out <= delay_chain_12; + when 13 => tap_out <= delay_chain_13; + when 14 => tap_out <= delay_chain_14; + when 15 => tap_out <= delay_chain_15; + when 16 => tap_out <= delay_chain_16; + when 17 => tap_out <= delay_chain_17; + when 18 => tap_out <= delay_chain_18; + when 19 => tap_out <= delay_chain_19; + when 20 => tap_out <= delay_chain_20; + when 21 => tap_out <= delay_chain_21; + when 22 => tap_out <= delay_chain_22; + when 23 => tap_out <= delay_chain_23; + when 24 => tap_out <= delay_chain_24; + when 25 => tap_out <= delay_chain_25; + when 26 => tap_out <= delay_chain_26; + when 27 => tap_out <= delay_chain_27; + when 28 => tap_out <= delay_chain_28; + when 29 => tap_out <= delay_chain_29; + when 30 => tap_out <= delay_chain_30; + when 31 => tap_out <= delay_chain_31; + when 32 => tap_out <= delay_chain_32; + when 33 => tap_out <= delay_chain_33; + when 34 => tap_out <= delay_chain_34; + when 35 => tap_out <= delay_chain_35; + when 36 => tap_out <= delay_chain_36; + when 37 => tap_out <= delay_chain_37; + when 38 => tap_out <= delay_chain_38; + when 39 => tap_out <= delay_chain_39; + when 40 => tap_out <= delay_chain_40; + when 41 => tap_out <= delay_chain_41; + when 42 => tap_out <= delay_chain_42; + when 43 => tap_out <= delay_chain_43; + when 44 => tap_out <= delay_chain_44; + when 45 => tap_out <= delay_chain_45; + when 46 => tap_out <= delay_chain_46; + when 47 => tap_out <= delay_chain_47; + when 48 => tap_out <= delay_chain_48; + when 49 => tap_out <= delay_chain_49; + when 50 => tap_out <= delay_chain_50; + when 51 => tap_out <= delay_chain_51; + when 52 => tap_out <= delay_chain_52; + when 53 => tap_out <= delay_chain_53; + when 54 => tap_out <= delay_chain_54; + when 55 => tap_out <= delay_chain_55; + when 56 => tap_out <= delay_chain_56; + when 57 => tap_out <= delay_chain_57; + when 58 => tap_out <= delay_chain_58; + when 59 => tap_out <= delay_chain_59; + when 60 => tap_out <= delay_chain_60; + when 61 => tap_out <= delay_chain_61; + when 62 => tap_out <= delay_chain_62; + when 63 => tap_out <= delay_chain_63; + when others => + tap_out <= delay_chain_0; + end case; + end if; + wait on T_dly, idelay_count, odelay_count, delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3, + delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7, + delay_chain_8, delay_chain_9, delay_chain_10, delay_chain_11, + delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15, + delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19, + delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23, + delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27, + delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31, + delay_chain_32, delay_chain_33, delay_chain_34, delay_chain_35, + delay_chain_36, delay_chain_37, delay_chain_38, delay_chain_39, + delay_chain_40, delay_chain_41, delay_chain_42, delay_chain_43, + delay_chain_44, delay_chain_45, delay_chain_46, delay_chain_47, + delay_chain_48, delay_chain_49, delay_chain_50, delay_chain_51, + delay_chain_52, delay_chain_53, delay_chain_54, delay_chain_55, + delay_chain_56, delay_chain_57, delay_chain_58, delay_chain_59, + delay_chain_60, delay_chain_61, delay_chain_62, delay_chain_63; + + end process prcs_AssignDelays; + +--#################################################################### +--##### CALCULATE oDelay ##### +--#################################################################### + prcs_calc_odelay:process(C_dly, GSR_dly, RST_dly) + variable odelay_count_var : integer :=0; + variable FIRST_TIME : boolean :=true; + variable BaseTime_var : time := 1 ps ; + variable CALC_TAPDELAY : real := 0.0; + begin + if((GSR_dly = '1') or (FIRST_TIME))then + odelay_count_var := ODELAY_VALUE; + CALC_TAPDELAY := ((1.0/REFCLK_FREQUENCY) * (1.0/64.0) * ILEAK_ADJUST * 1000000.0) + D_IODELAY_OFFSET ; + oDelay <= real(odelay_count_var) * CALC_TAPDELAY * BaseTime_var; + FIRST_TIME := false; + end if; + + end process prcs_calc_odelay; + +--#################################################################### +--##### OUTPUT TAP ##### +--#################################################################### + prcs_tapout:process(tap_out) + begin + DATAOUT_zd <= tap_out ; + end process prcs_tapout; + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(DATAOUT_zd) + begin + DATAOUT <= DATAOUT_zd ; + end process prcs_output; + + +end IODELAY_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 2005 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / Source Synchronous Input Deserializer +-- /___/ /\ Filename : ISERDES_NODELAY.vhd +-- \ \ / \ Timestamp : Fri Oct 21 16:11:37 PDT 2005 +-- \___\/\___\ +-- +-- Revision: +-- 10/21/05 - Initial version. +-- 05/29/06 - CR 232324 -- Added Rec/Rem RST wrt negedge CLKDIV +-- 06/16/06 - Added new port CLKB +-- 10/13/06 - CR 426606 +-- 03/02/07 - CR 435001 changed module names to bscntrl_nodelay and ice_module_nodelay_nodelay +-- 08/29/07 - CR 447556 Fixed attribute INTERFACE_TYPE to be case insensitive +-- 09/10/07 - CR 447760 Added Strict DRC for BITSLIP and INTERFACE_TYPE combinations +-- 12/03/07 - CR 454107 Added DRC warnings for INTERFACE_TYPE, DATA_RATE and DATA_WIDTH combinations +-- End Revision +----- CELL ISERDES_NODELAY ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_arith.all; + + +library unisim; +use unisim.vpkg.all; +use unisim.vcomponents.all; + +--//////////////////////////////////////////////////////////// +--////////////////////////// BSCNTRL_NODELAY ///////////////////////// +--//////////////////////////////////////////////////////////// +entity bscntrl_nodelay is + generic( + SRTYPE : string; + INIT_BITSLIPCNT : bit_vector(3 downto 0) + ); + port( + CLKDIV_INT : out std_ulogic; + MUXC : out std_ulogic; + + BITSLIP : in std_ulogic; + C23 : in std_ulogic; + C45 : in std_ulogic; + C67 : in std_ulogic; + CLK : in std_ulogic; + CLKDIV : in std_ulogic; + DATA_RATE : in std_ulogic; + GSR : in std_ulogic; + R : in std_ulogic; + SEL : in std_logic_vector (1 downto 0) + ); + +end bscntrl_nodelay; + +architecture bscntrl_nodelay_V of bscntrl_nodelay is +-- constant DELAY_FFBSC : time := 300 ns; +-- constant DELAY_MXBSC : time := 60 ns; + constant DELAY_FFBSC : time := 300 ps; + constant DELAY_MXBSC : time := 60 ps; + + signal AttrSRtype : integer := 0; + + signal q1 : std_ulogic := 'X'; + signal q2 : std_ulogic := 'X'; + signal q3 : std_ulogic := 'X'; + signal mux : std_ulogic := 'X'; + signal qhc1 : std_ulogic := 'X'; + signal qhc2 : std_ulogic := 'X'; + signal qlc1 : std_ulogic := 'X'; + signal qlc2 : std_ulogic := 'X'; + signal qr1 : std_ulogic := 'X'; + signal qr2 : std_ulogic := 'X'; + signal mux1 : std_ulogic := 'X'; + signal clkdiv_zd : std_ulogic := 'X'; + +begin +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + begin + + if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then + AttrSrtype <= 0; + elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then + AttrSrtype <= 1; + end if; + + wait; + end process prcs_init; +--#################################################################### +--##### Divide by 2 - 8 counter ##### +--#################################################################### + prcs_div_2_8_cntr:process(qr2, CLK, GSR) + variable clkdiv_int_var : std_ulogic := TO_X01(INIT_BITSLIPCNT(0)); + variable q1_var : std_ulogic := TO_X01(INIT_BITSLIPCNT(1)); + variable q2_var : std_ulogic := TO_X01(INIT_BITSLIPCNT(2)); + variable q3_var : std_ulogic := TO_X01(INIT_BITSLIPCNT(3)); + begin + if(GSR = '1') then + clkdiv_int_var := TO_X01(INIT_BITSLIPCNT(0)); + q1_var := TO_X01(INIT_BITSLIPCNT(1)); + q2_var := TO_X01(INIT_BITSLIPCNT(2)); + q3_var := TO_X01(INIT_BITSLIPCNT(3)); + elsif(GSR = '0') then + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if(qr2 = '1') then + clkdiv_int_var := '0'; + q1_var := '0'; + q2_var := '0'; + q3_var := '0'; + elsif (qhc1 = '1') then + clkdiv_int_var := clkdiv_int_var; + q1_var := q1_var; + q2_var := q2_var; + q3_var := q3_var; + else + if(rising_edge(CLK)) then + q3_var := q2_var; + q2_var :=( NOT((NOT clkdiv_int_var) and (NOT q2_var)) and q1_var); + q1_var := clkdiv_int_var; + clkdiv_int_var := mux; + end if; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(CLK)) then + if(qr2 = '1') then + clkdiv_int_var := '0'; + q1_var := '0'; + q2_var := '0'; + q3_var := '0'; + elsif (qhc1 = '1') then + clkdiv_int_var := clkdiv_int_var; + q1_var := q1_var; + q2_var := q2_var; + q3_var := q3_var; + else + q3_var := q2_var; + q2_var :=( NOT((NOT clkdiv_int_var) and (NOT q2_var)) and q1_var); + q1_var := clkdiv_int_var; + clkdiv_int_var := mux; + end if; + end if; + + when others => + null; + end case; + + + end if; + + q1 <= q1_var after DELAY_FFBSC; + q2 <= q2_var after DELAY_FFBSC; + q3 <= q3_var after DELAY_FFBSC; + clkdiv_zd <= clkdiv_int_var after DELAY_FFBSC; + + end process prcs_div_2_8_cntr; +--#################################################################### +--##### Divider selections and 4:1 selector mux ##### +--#################################################################### + prcs_mux_sel:process(sel, c23 , c45 , c67 , clkdiv_zd , q1 , q2 , q3) + begin + case sel is + when "00" => + mux <= NOT (clkdiv_zd or (c23 and q1)) after DELAY_MXBSC; + when "01" => + mux <= NOT (q1 or (c45 and q2)) after DELAY_MXBSC; + when "10" => + mux <= NOT (q2 or (c67 and q3)) after DELAY_MXBSC; + when "11" => + mux <= NOT (q3) after DELAY_MXBSC; + when others => + mux <= NOT (clkdiv_zd or (c23 and q1)) after DELAY_MXBSC; + end case; + end process prcs_mux_sel; +--#################################################################### +--##### Bitslip control logic ##### +--#################################################################### + prcs_logictrl:process(qr1, clkdiv) + begin + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if(qr1 = '1') then + qlc1 <= '0' after DELAY_FFBSC; + qlc2 <= '0' after DELAY_FFBSC; + elsif(bitslip = '0') then + qlc1 <= qlc1 after DELAY_FFBSC; + qlc2 <= '0' after DELAY_FFBSC; + else + if(rising_edge(clkdiv)) then + qlc1 <= NOT qlc1 after DELAY_FFBSC; + qlc2 <= (bitslip and mux1) after DELAY_FFBSC; + end if; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(clkdiv)) then + if(qr1 = '1') then + qlc1 <= '0' after DELAY_FFBSC; + qlc2 <= '0' after DELAY_FFBSC; + elsif(bitslip = '0') then + qlc1 <= qlc1 after DELAY_FFBSC; + qlc2 <= '0' after DELAY_FFBSC; + else + qlc1 <= NOT qlc1 after DELAY_FFBSC; + qlc2 <= (bitslip and mux1) after DELAY_FFBSC; + end if; + end if; + when others => + null; + end case; + end process prcs_logictrl; + +--#################################################################### +--##### Mux to select between sdr "0" and ddr "1" ##### +--#################################################################### + prcs_sdr_ddr_mux:process(qlc1, DATA_RATE) + begin + case DATA_RATE is + when '0' => + mux1 <= qlc1 after DELAY_MXBSC; + when '1' => + mux1 <= '1' after DELAY_MXBSC; + when others => + null; + end case; + end process prcs_sdr_ddr_mux; + +--#################################################################### +--##### qhc1 and qhc2 ##### +--#################################################################### + prcs_qhc1_qhc2:process(qr2, CLK) + begin +-- FP TMP -- should CLK and q2 have to be rising_edge + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if(qr2 = '1') then + qhc1 <= '0' after DELAY_FFBSC; + qhc2 <= '0' after DELAY_FFBSC; + elsif(rising_edge(CLK)) then + qhc1 <= (qlc2 and (NOT qhc2)) after DELAY_FFBSC; + qhc2 <= qlc2 after DELAY_FFBSC; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(CLK)) then + if(qr2 = '1') then + qhc1 <= '0' after DELAY_FFBSC; + qhc2 <= '0' after DELAY_FFBSC; + else + qhc1 <= (qlc2 and (NOT qhc2)) after DELAY_FFBSC; + qhc2 <= qlc2 after DELAY_FFBSC; + end if; + end if; + + when others => + null; + end case; + + end process prcs_qhc1_qhc2; + +--#################################################################### +--##### Mux drives ctrl lines of mux in front of 2nd rnk FFs #### +--#################################################################### + prcs_muxc:process(mux1, DATA_RATE) + begin + case DATA_RATE is + when '0' => + muxc <= mux1 after DELAY_MXBSC; + when '1' => + muxc <= '0' after DELAY_MXBSC; + when others => + null; + end case; + end process prcs_muxc; + +--#################################################################### +--##### Asynchronous set flops ##### +--#################################################################### + prcs_qr1:process(R, CLKDIV) + begin +-- FP TMP -- should CLKDIV and R have to be rising_edge + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if(R = '1') then + qr1 <= '1' after DELAY_FFBSC; + elsif(rising_edge(CLKDIV)) then + qr1 <= '0' after DELAY_FFBSC; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(CLKDIV)) then + if(R = '1') then + qr1 <= '1' after DELAY_FFBSC; + else + qr1 <= '0' after DELAY_FFBSC; + end if; + end if; + + when others => + null; + end case; + end process prcs_qr1; +---------------------------------------------------------------------- + prcs_qr2:process(R, CLK) + begin +-- FP TMP -- should CLK and R have to be rising_edge + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if(R = '1') then + qr2 <= '1' after DELAY_FFBSC; + elsif(rising_edge(CLK)) then + qr2 <= qr1 after DELAY_FFBSC; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(CLK)) then + if(R = '1') then + qr2 <= '1' after DELAY_FFBSC; + else + qr2 <= qr1 after DELAY_FFBSC; + end if; + end if; + + when others => + null; + end case; + end process prcs_qr2; +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(clkdiv_zd) + begin + CLKDIV_INT <= clkdiv_zd; + end process prcs_output; +--#################################################################### +end bscntrl_nodelay_V; + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_arith.all; + + +library unisim; +use unisim.vpkg.all; +use unisim.vcomponents.all; + +--//////////////////////////////////////////////////////////// +--///////////////// ICE_MODULE_NODELAY /////////////////////// +--//////////////////////////////////////////////////////////// + +entity ice_module_nodelay is + generic( + SRTYPE : string; + INIT_CE : bit_vector(1 downto 0) + ); + port( + ICE : out std_ulogic; + + CE1 : in std_ulogic; + CE2 : in std_ulogic; + GSR : in std_ulogic; + NUM_CE : in std_ulogic; + CLKDIV : in std_ulogic; + R : in std_ulogic + ); +end ice_module_nodelay; + +architecture ice_module_nodelay_V of ice_module_nodelay is +-- constant DELAY_FFICE : time := 300 ns; +-- constant DELAY_MXICE : time := 60 ns; + constant DELAY_FFICE : time := 300 ps; + constant DELAY_MXICE : time := 60 ps; + + signal AttrSRtype : integer := 0; + + signal ce1r : std_ulogic := 'X'; + signal ce2r : std_ulogic := 'X'; + signal cesel : std_logic_vector(1 downto 0) := (others => 'X'); + + signal ice_zd : std_ulogic := 'X'; + +begin + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + begin + + if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then + AttrSrtype <= 0; + elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then + AttrSrtype <= 1; + end if; + + wait; + end process prcs_init; + +--################################################################### +--##### update cesel ##### +--################################################################### + + cesel <= NUM_CE & CLKDIV; + +--#################################################################### +--##### registers ##### +--#################################################################### + prcs_reg:process(CLKDIV, GSR) + variable ce1r_var : std_ulogic := TO_X01(INIT_CE(1)); + variable ce2r_var : std_ulogic := TO_X01(INIT_CE(0)); + begin + if(GSR = '1') then + ce1r_var := TO_X01(INIT_CE(1)); + ce2r_var := TO_X01(INIT_CE(0)); + elsif(GSR = '0') then + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if(R = '1') then + ce1r_var := '0'; + ce2r_var := '0'; + elsif(rising_edge(CLKDIV)) then + ce1r_var := ce1; + ce2r_var := ce2; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(CLKDIV)) then + if(R = '1') then + ce1r_var := '0'; + ce2r_var := '0'; + else + ce1r_var := ce1; + ce2r_var := ce2; + end if; + end if; + + when others => + null; + + end case; + end if; + + ce1r <= ce1r_var after DELAY_FFICE; + ce2r <= ce2r_var after DELAY_FFICE; + + end process prcs_reg; +--#################################################################### +--##### Output mux ##### +--#################################################################### + prcs_mux:process(cesel, ce1, ce1r, ce2r) + begin + case cesel is + when "00" => + ice_zd <= ce1; + when "01" => + ice_zd <= ce1; +-- 426606 + when "10" => + ice_zd <= ce2r; + when "11" => + ice_zd <= ce1r; + when others => + null; + end case; + end process prcs_mux; + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(ice_zd) + begin + ICE <= ice_zd; + end process prcs_output; +end ice_module_nodelay_V; + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_arith.all; + +library STD; +use STD.TEXTIO.all; + + +library unisim; +use unisim.vpkg.all; +use unisim.vcomponents.all; +use unisim.vcomponents.all; + +----- CELL ISERDES_NODELAY ----- +--//////////////////////////////////////////////////////////// +--////////////////////////// ISERDES_NODELAY ///////////////////////// +--//////////////////////////////////////////////////////////// + +entity ISERDES_NODELAY is + + generic( + + + BITSLIP_ENABLE : boolean := false; + DATA_RATE : string := "DDR"; + DATA_WIDTH : integer := 4; + INIT_Q1 : bit := '0'; + INIT_Q2 : bit := '0'; + INIT_Q3 : bit := '0'; + INIT_Q4 : bit := '0'; + INTERFACE_TYPE : string := "MEMORY"; + NUM_CE : integer := 2; + SERDES_MODE : string := "MASTER" + ); + + port( + Q1 : out std_ulogic; + Q2 : out std_ulogic; + Q3 : out std_ulogic; + Q4 : out std_ulogic; + Q5 : out std_ulogic; + Q6 : out std_ulogic; + SHIFTOUT1 : out std_ulogic; + SHIFTOUT2 : out std_ulogic; + + BITSLIP : in std_ulogic; + CE1 : in std_ulogic; + CE2 : in std_ulogic; + CLK : in std_ulogic; + CLKB : in std_ulogic; + CLKDIV : in std_ulogic; + D : in std_ulogic; + OCLK : in std_ulogic; + RST : in std_ulogic; + SHIFTIN1 : in std_ulogic; + SHIFTIN2 : in std_ulogic + ); + +end ISERDES_NODELAY; + +architecture ISERDES_NODELAY_V OF ISERDES_NODELAY is + +component bscntrl_nodelay + generic ( + SRTYPE : string; + INIT_BITSLIPCNT : bit_vector(3 downto 0) + ); + port( + CLKDIV_INT : out std_ulogic; + MUXC : out std_ulogic; + + BITSLIP : in std_ulogic; + C23 : in std_ulogic; + C45 : in std_ulogic; + C67 : in std_ulogic; + CLK : in std_ulogic; + CLKDIV : in std_ulogic; + DATA_RATE : in std_ulogic; + GSR : in std_ulogic; + R : in std_ulogic; + SEL : in std_logic_vector (1 downto 0) + ); +end component; + +component ice_module_nodelay + generic( + SRTYPE : string; + INIT_CE : bit_vector(1 downto 0) + ); + port( + ICE : out std_ulogic; + + CE1 : in std_ulogic; + CE2 : in std_ulogic; + GSR : in std_ulogic; + NUM_CE : in std_ulogic; + CLKDIV : in std_ulogic; + R : in std_ulogic + ); +end component; + + + constant SRVAL_Q1 : bit := '0'; + constant SRVAL_Q2 : bit := '0'; + constant SRVAL_Q3 : bit := '0'; + constant SRVAL_Q4 : bit := '0'; + + constant DDR_CLK_EDGE : string := "SAME_EDGE_PIPELINED"; + constant INIT_BITSLIPCNT : bit_vector(3 downto 0) := "0000"; + constant INIT_CE : bit_vector(1 downto 0) := "00"; + constant INIT_RANK1_PARTIAL : bit_vector(4 downto 0) := "00000"; + constant INIT_RANK2 : bit_vector(5 downto 0) := "000000"; + constant INIT_RANK3 : bit_vector(5 downto 0) := "000000"; + constant SERDES : boolean := TRUE; + constant SRTYPE : string := "ASYNC"; + +-- constant DELAY_FFINP : time := 300 ns; +-- constant DELAY_MXINP1 : time := 60 ns; +-- constant DELAY_MXINP2 : time := 120 ns; +-- constant DELAY_OCLKDLY : time := 750 ns; + + constant SYNC_PATH_DELAY : time := 100 ps; + + constant DELAY_FFINP : time := 300 ps; + constant DELAY_MXINP1 : time := 60 ps; + constant DELAY_MXINP2 : time := 120 ps; + constant DELAY_OCLKDLY : time := 750 ps; + + constant MAX_DATAWIDTH : integer := 4; + + signal BITSLIP_ipd : std_ulogic := 'X'; + signal CE1_ipd : std_ulogic := 'X'; + signal CE2_ipd : std_ulogic := 'X'; + signal CLK_ipd : std_ulogic := 'X'; + signal CLKB_ipd : std_ulogic := 'X'; + signal CLKDIV_ipd : std_ulogic := 'X'; + signal D_ipd : std_ulogic := 'X'; + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := 'X'; + signal OCLK_ipd : std_ulogic := 'X'; + signal RST_ipd : std_ulogic := 'X'; + signal SHIFTIN1_ipd : std_ulogic := 'X'; + signal SHIFTIN2_ipd : std_ulogic := 'X'; + + signal BITSLIP_dly : std_ulogic := 'X'; + signal CE1_dly : std_ulogic := 'X'; + signal CE2_dly : std_ulogic := 'X'; + signal CLK_dly : std_ulogic := 'X'; + signal CLKB_dly : std_ulogic := 'X'; + signal CLKDIV_dly : std_ulogic := 'X'; + signal D_dly : std_ulogic := 'X'; + signal GSR_dly : std_ulogic := 'X'; + signal OCLK_dly : std_ulogic := 'X'; + signal RST_dly : std_ulogic := 'X'; + signal SHIFTIN1_dly : std_ulogic := 'X'; + signal SHIFTIN2_dly : std_ulogic := 'X'; + + signal REV_dly : std_ulogic := '0'; + signal SR_dly : std_ulogic := '0'; + + signal Q1_zd : std_ulogic := 'X'; + signal Q2_zd : std_ulogic := 'X'; + signal Q3_zd : std_ulogic := 'X'; + signal Q4_zd : std_ulogic := 'X'; + signal Q5_zd : std_ulogic := 'X'; + signal Q6_zd : std_ulogic := 'X'; + signal SHIFTOUT1_zd : std_ulogic := 'X'; + signal SHIFTOUT2_zd : std_ulogic := 'X'; + + signal Q1_viol : std_ulogic := 'X'; + signal Q2_viol : std_ulogic := 'X'; + signal Q3_viol : std_ulogic := 'X'; + signal Q4_viol : std_ulogic := 'X'; + signal Q5_viol : std_ulogic := 'X'; + signal Q6_viol : std_ulogic := 'X'; + signal SHIFTOUT1_viol : std_ulogic := 'X'; + signal SHIFTOUT2_viol : std_ulogic := 'X'; + + signal AttrSerdes : std_ulogic := 'X'; + signal AttrMode : std_ulogic := 'X'; + signal AttrDataRate : std_ulogic := 'X'; + signal AttrDataWidth : std_logic_vector(3 downto 0) := (others => 'X'); + signal AttrInterfaceType : std_ulogic := 'X'; + signal AttrBitslipEnable : std_ulogic := 'X'; + signal AttrNumCe : std_ulogic := 'X'; + signal AttrDdrClkEdge : std_logic_vector(1 downto 0) := (others => 'X'); + signal AttrSRtype : integer := 0; + signal AttrIobDelay : integer := 0; + + signal sel1 : std_logic_vector(1 downto 0) := (others => 'X'); + signal selrnk3 : std_logic_vector(3 downto 0) := (others => 'X'); + signal bsmux : std_logic_vector(2 downto 0) := (others => 'X'); + signal cntr : std_logic_vector(4 downto 0) := (others => 'X'); + + signal q1rnk1 : std_ulogic := 'X'; + signal q2nrnk1 : std_ulogic := 'X'; + signal q5rnk1 : std_ulogic := 'X'; + signal q6rnk1 : std_ulogic := 'X'; + signal q6prnk1 : std_ulogic := 'X'; + + signal q1prnk1 : std_ulogic := 'X'; + signal q2prnk1 : std_ulogic := 'X'; + signal q3rnk1 : std_ulogic := 'X'; + signal q4rnk1 : std_ulogic := 'X'; + + signal dataq5rnk1 : std_ulogic := 'X'; + signal dataq6rnk1 : std_ulogic := 'X'; + + signal dataq3rnk1 : std_ulogic := 'X'; + signal dataq4rnk1 : std_ulogic := 'X'; + + signal oclkmux : std_ulogic := '0'; + signal memmux : std_ulogic := '0'; + signal q2pmux : std_ulogic := '0'; + + signal clkdiv_int : std_ulogic := '0'; + signal clkdivmux : std_ulogic := '0'; + + signal q1rnk2 : std_ulogic := 'X'; + signal q2rnk2 : std_ulogic := 'X'; + signal q3rnk2 : std_ulogic := 'X'; + signal q4rnk2 : std_ulogic := 'X'; + signal q5rnk2 : std_ulogic := 'X'; + signal q6rnk2 : std_ulogic := 'X'; + signal dataq1rnk2 : std_ulogic := 'X'; + signal dataq2rnk2 : std_ulogic := 'X'; + signal dataq3rnk2 : std_ulogic := 'X'; + signal dataq4rnk2 : std_ulogic := 'X'; + signal dataq5rnk2 : std_ulogic := 'X'; + signal dataq6rnk2 : std_ulogic := 'X'; + + signal muxc : std_ulogic := 'X'; + + signal q1rnk3 : std_ulogic := 'X'; + signal q2rnk3 : std_ulogic := 'X'; + signal q3rnk3 : std_ulogic := 'X'; + signal q4rnk3 : std_ulogic := 'X'; + signal q5rnk3 : std_ulogic := 'X'; + signal q6rnk3 : std_ulogic := 'X'; + + signal c23 : std_ulogic := 'X'; + signal c45 : std_ulogic := 'X'; + signal c67 : std_ulogic := 'X'; + signal sel : std_logic_vector(1 downto 0) := (others => 'X'); + + signal ice : std_ulogic := 'X'; + signal datain : std_ulogic := 'X'; + signal idelay_out : std_ulogic := 'X'; + + signal CLKN_dly : std_ulogic := '0'; + + procedure CR454107_msg(INTERFACE_TYPE : IN string; + DATA_RATE : IN string; + DATA_WIDTH : IN integer) is + + variable Message : line; + begin + Write (Message, string'("DRC Warning : The combination of INTERFACE_TYPE, DATA_RATE and DATA_WIDTH values on X_ISERDES_NODELAY component is not recommended.")); + Write (Message, LF); + Write (Message, string'("The current settings are: INTERFACE_TYPE = ")); + Write (Message, INTERFACE_TYPE); + Write (Message, string'(", DATA_RATE = ")); + Write (Message, DATA_RATE ); + Write (Message, string'(" and DATA_WIDTH = ")); + Write (Message, DATA_WIDTH ); + Write (Message, LF); + Write (Message, string'("The recommended combinations of values are :")); + Write (Message, LF); + Write (Message, string'("NETWORKING SDR 2, 3, 4, 5, 6, 7, 8")); + Write (Message, LF); + Write (Message, string'("NETWORKING DDR 4, 6, 8, 10")); + Write (Message, LF); + Write (Message, string'("MEMORY SDR None")); + Write (Message, LF); + Write (Message, string'("MEMORY DDR 4")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end CR454107_msg; +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + BITSLIP_dly <= BITSLIP after 0 ps; + CE1_dly <= CE1 after 0 ps; + CE2_dly <= CE2 after 0 ps; + CLK_dly <= CLK after 0 ps; + CLKB_dly <= CLKB after 0 ps; + CLKDIV_dly <= CLKDIV after 0 ps; + D_dly <= D after 0 ps; + GSR_dly <= GSR after 0 ps; + OCLK_dly <= OCLK after 0 ps; + RST_dly <= RST after 0 ps; + SHIFTIN1_dly <= SHIFTIN1 after 0 ps; + SHIFTIN2_dly <= SHIFTIN2 after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + + SR_dly <= RST_dly; + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + variable AttrSerdes_var : std_ulogic := 'X'; + variable AttrMode_var : std_ulogic := 'X'; + variable AttrDataRate_var : std_ulogic := 'X'; + variable AttrDataWidth_var : std_logic_vector(3 downto 0) := (others => 'X'); + variable AttrInterfaceType_var : std_ulogic := 'X'; + variable AttrBitslipEnable_var : std_ulogic := 'X'; + variable AttrDdrClkEdge_var : std_logic_vector(1 downto 0) := (others => 'X'); + variable AttrIobDelay_var : integer := 0; + + begin + --------CR 454107 DRC Warning -- INTERFACE_TYPE / DATA_RATE / DATA_WIDTH combinations ------------------ + if (INTERFACE_TYPE = "NETWORKING") then + if(DATA_RATE = "SDR")then + case (DATA_WIDTH) is + when 2|3|4|5|6|7|8 => null; + when others => CR454107_msg(INTERFACE_TYPE, DATA_RATE, DATA_WIDTH); + end case; + elsif(DATA_RATE = "DDR")then + case (DATA_WIDTH) is + when 4|6|8|10 => null; + when others => CR454107_msg(INTERFACE_TYPE, DATA_RATE, DATA_WIDTH); + end case; + end if; + elsif (INTERFACE_TYPE = "MEMORY") then + if(DATA_RATE = "DDR")then + case (DATA_WIDTH) is + when 4 => null; + when others => CR454107_msg(INTERFACE_TYPE, DATA_RATE, DATA_WIDTH); + end case; + elsif(DATA_RATE = "SDR")then + CR454107_msg(INTERFACE_TYPE, DATA_RATE, DATA_WIDTH); + end if; + end if; + + --------CR 447760 DRC -- BITSLIP - INTERFACE_TYPE combination ------------------ + + if((INTERFACE_TYPE = "MEMORY") and (BITSLIP_ENABLE = TRUE)) then + assert false + report "Attribute Syntax Error: BITSLIP_ENABLE is currently set to TRUE when INTERFACE_TYPE is set to MEMORY. This is an invalid configuration." + severity Failure; + elsif((INTERFACE_TYPE = "NETWORKING") and (BITSLIP_ENABLE = FALSE)) then + assert false + report "Attribute Syntax Error: BITSLIP_ENABLE is currently set to FALSE when INTERFACE_TYPE is set to NETWORKING. If BITSLIP is not intended to be used, please set BITSLIP_ENABLE to TRUE and tie the BITSLIP port to ground." + severity Failure; + end if; + + -------------------- SERDES validity check -------------------- + if(SERDES = true) then + AttrSerdes_var := '1'; + else + AttrSerdes_var := '0'; + end if; + + ------------- SERDES_MODE validity check -------------------- + if((SERDES_MODE = "MASTER") or (SERDES_MODE = "master")) then + AttrMode_var := '0'; + elsif((SERDES_MODE = "SLAVE") or (SERDES_MODE = "slave")) then + AttrMode_var := '1'; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => "SERDES_MODE ", + EntityName => "/ISERDES_NODELAY", + GenericValue => SERDES_MODE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " MASTER or SLAVE.", + TailMsg => "", + MsgSeverity => FAILURE + ); + end if; + + ------------------ DATA_RATE validity check ------------------ + if((DATA_RATE = "DDR") or (DATA_RATE = "ddr")) then + AttrDataRate_var := '0'; + elsif((DATA_RATE = "SDR") or (DATA_RATE = "sdr")) then + AttrDataRate_var := '1'; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DATA_RATE ", + EntityName => "/ISERDES_NODELAY", + GenericValue => DATA_RATE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " DDR or SDR. ", + TailMsg => "", + MsgSeverity => Failure + ); + end if; + + ------------------ DATA_WIDTH validity check ------------------ + if((DATA_WIDTH = 2) or (DATA_WIDTH = 3) or (DATA_WIDTH = 4) or + (DATA_WIDTH = 5) or (DATA_WIDTH = 6) or (DATA_WIDTH = 7) or + (DATA_WIDTH = 8) or (DATA_WIDTH = 10)) then + AttrDataWidth_var := CONV_STD_LOGIC_VECTOR(DATA_WIDTH, MAX_DATAWIDTH); + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DATA_WIDTH ", + EntityName => "/ISERDES_NODELAY", + GenericValue => DATA_WIDTH, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 2, 3, 4, 5, 6, 7, 8, or 10 ", + TailMsg => "", + MsgSeverity => Failure + ); + end if; + ------------ DATA_WIDTH /DATA_RATE combination check ------------ + if((DATA_RATE = "DDR") or (DATA_RATE = "ddr")) then + case (DATA_WIDTH) is + when 4|6|8|10 => null; + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DATA_WIDTH ", + EntityName => "/ISERDES_NODELAY", + GenericValue => DATA_WIDTH, + Unit => "", + ExpectedValueMsg => " The Legal values for DDR mode are ", + ExpectedGenericValue => " 4, 6, 8, or 10 ", + TailMsg => "", + MsgSeverity => Failure + ); + end case; + end if; + + if((DATA_RATE = "SDR") or (DATA_RATE = "sdr")) then + case (DATA_WIDTH) is + when 2|3|4|5|6|7|8 => null; + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DATA_WIDTH ", + EntityName => "/ISERDES_NODELAY", + GenericValue => DATA_WIDTH, + Unit => "", + ExpectedValueMsg => " The Legal values for SDR mode are ", + ExpectedGenericValue => " 2, 3, 4, 5, 6, 7 or 8", + TailMsg => "", + MsgSeverity => Failure + ); + end case; + end if; + ---------------- INTERFACE_TYPE validity check --------------- + if((INTERFACE_TYPE = "MEMORY") or (INTERFACE_TYPE = "memory")) then + AttrInterfaceType_var := '0'; + elsif((INTERFACE_TYPE = "NETWORKING") or (INTERFACE_TYPE = "networking")) then + AttrInterfaceType_var := '1'; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => "INTERFACE_TYPE ", + EntityName => "/ISERDES_NODELAY", + GenericValue => INTERFACE_TYPE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " MEMORY or NETWORKING.", + TailMsg => "", + MsgSeverity => FAILURE + ); + end if; + + ---------------- BITSLIP_ENABLE validity check ------------------- + if(BITSLIP_ENABLE = false) then + AttrBitslipEnable_var := '0'; + elsif(BITSLIP_ENABLE = true) then + AttrBitslipEnable_var := '1'; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " BITSLIP_ENABLE ", + EntityName => "/ISERDES_NODELAY", + GenericValue => BITSLIP_ENABLE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " TRUE or FALSE ", + TailMsg => "", + MsgSeverity => Failure + ); + end if; + + ---------------- NUM_CE validity check ------------------- + case NUM_CE is + when 1 => + AttrNumCe <= '0'; + when 2 => + AttrNumCe <= '1'; + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " NUM_CE ", + EntityName => "/ISERDES_NODELAY", + GenericValue => NUM_CE, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 1 or 2 ", + TailMsg => "", + MsgSeverity => Failure + ); + end case; +-- +-- +-- + ------------------ DDR_CLK_EDGE validity check ------------------ + AttrDdrClkEdge_var := "00"; + +-- if((DDR_CLK_EDGE = "SAME_EDGE_PIPELINED") or (DDR_CLK_EDGE = "same_edge_pipelined")) then +-- AttrDdrClkEdge_var := "00"; +-- elsif((DDR_CLK_EDGE = "SAME_EDGE") or (DDR_CLK_EDGE = "same_edge")) then +-- AttrDdrClkEdge_var := "01"; +-- elsif((DDR_CLK_EDGE = "OPPOSITE_EDGE") or (DDR_CLK_EDGE = "opposite_edge")) then +-- AttrDdrClkEdge_var := "10"; +-- else +-- GenericValueCheckMessage +-- ( HeaderMsg => " Attribute Syntax Warning ", +-- GenericName => " DDR_CLK_EDGE ", +-- EntityName => "/ISERDES_NODELAY", +-- GenericValue => DDR_CLK_EDGE, +-- Unit => "", +-- ExpectedValueMsg => " The Legal values for this attribute are ", +-- ExpectedGenericValue => " SAME_EDGE_PIPELINED or SAME_EDGE or OPPOSITE_EDGE ", +-- TailMsg => "", +-- MsgSeverity => Failure +-- ); +-- end if; + ------------------ DATA_RATE validity check ------------------ + AttrSrtype <= 0; + +-- if((SRTYPE = "ASYNC") or (SRTYPE = "async")) then +-- AttrSrtype <= 0; +-- elsif((SRTYPE = "SYNC") or (SRTYPE = "sync")) then +-- AttrSrtype <= 1; +-- else +-- GenericValueCheckMessage +-- ( HeaderMsg => " Attribute Syntax Warning ", +-- GenericName => " SRTYPE ", +-- EntityName => "/ISERDES_NODELAY", +-- GenericValue => SRTYPE, +-- Unit => "", +-- ExpectedValueMsg => " The Legal values for this attribute are ", +-- ExpectedGenericValue => " ASYNC or SYNC. ", +-- TailMsg => "", +-- MsgSeverity => ERROR +-- ); +-- end if; +--------------------------------------------------------------------- + + AttrSerdes <= AttrSerdes_var; + AttrMode <= AttrMode_var; + AttrDataRate <= AttrDataRate_var; + AttrDataWidth <= AttrDataWidth_var; + AttrInterfaceType <= AttrInterfaceType_var; + AttrBitslipEnable <= AttrBitslipEnable_var; + AttrDdrClkEdge <= AttrDdrClkEdge_var; + AttrIobDelay <= AttrIobDelay_var; + + sel1 <= AttrMode_var & AttrDataRate_var; + selrnk3 <= AttrSerdes_var & AttrBitslipEnable_var & AttrDdrClkEdge_var; + cntr <= AttrDataRate_var & AttrDataWidth_var; + + wait; + end process prcs_init; + +--################################################################### +--##### SHIFTOUT1 and SHIFTOUT2 ##### +--################################################################### + + SHIFTOUT2_zd <= q5rnk1; + SHIFTOUT1_zd <= q6rnk1; + +--################################################################### +--##### SHIFTOUT1 and SHIFTOUT2 ##### +--################################################################### + + datain <= D_dly; + +--################################################################### +--##### q1rnk1 reg ##### +--################################################################### + prcs_Q1_rnk1:process(CLK_dly, GSR_dly, REV_dly, SR_dly) + variable q1rnk1_var : std_ulogic := TO_X01(INIT_Q1); + begin + if(GSR_dly = '1') then + q1rnk1_var := TO_X01(INIT_Q1); + elsif(GSR_dly = '0') then + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q1) = '1')))) then + q1rnk1_var := TO_X01(SRVAL_Q1); + elsif(REV_dly = '1') then + q1rnk1_var := not TO_X01(SRVAL_Q1); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(ice = '1') then + if(rising_edge(CLK_dly)) then + q1rnk1_var := datain; + end if; + end if; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(CLK_dly)) then + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q1) = '1')))) then + q1rnk1_var := TO_X01(SRVAL_Q1); + Elsif(REV_dly = '1') then + q1rnk1_var := not TO_X01(SRVAL_Q1); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(ice = '1') then + q1rnk1_var := datain; + end if; + end if; + end if; + + when others => + null; + + end case; + end if; + + q1rnk1 <= q1rnk1_var after DELAY_FFINP; + + end process prcs_Q1_rnk1; +--################################################################### +--##### q5rnk1, q6rnk1 and q6prnk1 reg ##### +--################################################################### + prcs_Q5Q6Q6p_rnk1:process(CLK_dly, GSR_dly, SR_dly) + variable q5rnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(2)); + variable q6rnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(1)); + variable q6prnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(0)); + begin + if(GSR_dly = '1') then + q5rnk1_var := TO_X01(INIT_RANK1_PARTIAL(2)); + q6rnk1_var := TO_X01(INIT_RANK1_PARTIAL(1)); + q6prnk1_var := TO_X01(INIT_RANK1_PARTIAL(0)); + elsif(GSR_dly = '0') then + case AttrSRtype is + when 0 => + --------- // async SET/RESET -- Not full featured FFs + if(SR_dly = '1') then + q5rnk1_var := '0'; + q6rnk1_var := '0'; + q6prnk1_var := '0'; + elsif(SR_dly = '0') then + if(rising_edge(CLK_dly)) then + q5rnk1_var := dataq5rnk1; + q6rnk1_var := dataq6rnk1; + q6prnk1_var := q6rnk1; + end if; + end if; + + when 1 => + --------- // sync SET/RESET -- Not full featured FFs + if(rising_edge(CLK_dly)) then + if(SR_dly = '1') then + q5rnk1_var := '0'; + q6rnk1_var := '0'; + q6prnk1_var := '0'; + elsif(SR_dly = '0') then + q5rnk1_var := dataq5rnk1; + q6rnk1_var := dataq6rnk1; + q6prnk1_var := q6rnk1; + end if; + end if; + + when others => + null; + + end case; + end if; + + q5rnk1 <= q5rnk1_var after DELAY_FFINP; + q6rnk1 <= q6rnk1_var after DELAY_FFINP; + q6prnk1 <= q6prnk1_var after DELAY_FFINP; + + end process prcs_Q5Q6Q6p_rnk1; +--################################################################### +--##### q2nrnk1 reg ##### +--################################################################### + prcs_Q2_rnk1:process(CLKB_dly, GSR_dly, SR_dly, REV_dly) + variable q2nrnk1_var : std_ulogic := TO_X01(INIT_Q2); + begin + if(GSR_dly = '1') then + q2nrnk1_var := TO_X01(INIT_Q2); + elsif(GSR_dly = '0') then + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q2) = '1')))) then + q2nrnk1_var := TO_X01(SRVAL_Q2); + elsif(REV_dly = '1') then + q2nrnk1_var := not TO_X01(SRVAL_Q2); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(ice = '1') then + if(rising_edge(CLKB_dly)) then + q2nrnk1_var := datain; + end if; + end if; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(CLKB_dly)) then + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q2) = '1')))) then + q2nrnk1_var := TO_X01(SRVAL_Q2); + elsif(REV_dly = '1') then + q2nrnk1_var := not TO_X01(SRVAL_Q2); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(ice = '1') then + q2nrnk1_var := datain; + end if; + end if; + end if; + + when others => + null; + + end case; + end if; + + q2nrnk1 <= q2nrnk1_var after DELAY_FFINP; + + end process prcs_Q2_rnk1; +--################################################################### +--##### q2prnk1 reg ##### +--################################################################### + prcs_Q2p_rnk1:process(q2pmux, GSR_dly, REV_dly, SR_dly) + variable q2prnk1_var : std_ulogic := TO_X01(INIT_Q4); + begin + if(GSR_dly = '1') then + q2prnk1_var := TO_X01(INIT_Q4); + elsif(GSR_dly = '0') then + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q4) = '1')))) then + q2prnk1_var := TO_X01(SRVAL_Q4); + elsif(REV_dly = '1') then + q2prnk1_var := not TO_X01(SRVAL_Q4); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(ice = '1') then + if(rising_edge(q2pmux)) then + q2prnk1_var := q2nrnk1; + end if; + end if; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(q2pmux)) then + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q4) = '1')))) then + q2prnk1_var := TO_X01(SRVAL_Q4); + elsif(REV_dly = '1') then + q2prnk1_var := not TO_X01(SRVAL_Q4); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(ice = '1') then + q2prnk1_var := q2nrnk1; + end if; + end if; + end if; + + when others => + null; + + end case; + end if; + + q2prnk1 <= q2prnk1_var after DELAY_FFINP; + + end process prcs_Q2p_rnk1; +--################################################################### +--##### q1prnk1 reg ##### +--################################################################### + prcs_Q1p_rnk1:process(memmux, GSR_dly, REV_dly, SR_dly) + variable q1prnk1_var : std_ulogic := TO_X01(INIT_Q3); + begin + if(GSR_dly = '1') then + q1prnk1_var := TO_X01(INIT_Q3); + elsif(GSR_dly = '0') then + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q3) = '1')))) then + q1prnk1_var := TO_X01(SRVAL_Q3); + elsif(REV_dly = '1') then + q1prnk1_var := not TO_X01(SRVAL_Q3); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(ice = '1') then + if(rising_edge(memmux)) then + q1prnk1_var := q1rnk1; + end if; + end if; + end if; + + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(memmux)) then + if((SR_dly = '1') and (not ((REV_dly = '1') and (TO_X01(SRVAL_Q3) = '1')))) then + q1prnk1_var := TO_X01(SRVAL_Q3); + elsif(REV_dly = '1') then + q1prnk1_var := not TO_X01(SRVAL_Q3); + elsif((SR_dly = '0') and (REV_dly = '0')) then + if(ice = '1') then + q1prnk1_var := q1rnk1; + end if; + end if; + end if; + + when others => + null; + + end case; + end if; + + q1prnk1 <= q1prnk1_var after DELAY_FFINP; + + end process prcs_Q1p_rnk1; +--################################################################### +--##### q3rnk1 and q4rnk1 reg ##### +--################################################################### + prcs_Q3Q4_rnk1:process(memmux, GSR_dly, SR_dly) + variable q3rnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(4)); + variable q4rnk1_var : std_ulogic := TO_X01(INIT_RANK1_PARTIAL(3)); + begin + if(GSR_dly = '1') then + q3rnk1_var := TO_X01(INIT_RANK1_PARTIAL(4)); + q4rnk1_var := TO_X01(INIT_RANK1_PARTIAL(3)); + elsif(GSR_dly = '0') then + case AttrSRtype is + when 0 => + -------- // async SET/RESET -- not fully featured FFs + if(SR_dly = '1') then + q3rnk1_var := '0'; + q4rnk1_var := '0'; + elsif(SR_dly = '0') then + if(rising_edge(memmux)) then + q3rnk1_var := dataq3rnk1; + q4rnk1_var := dataq4rnk1; + end if; + end if; + + when 1 => + -------- // sync SET/RESET -- not fully featured FFs + if(rising_edge(memmux)) then + if(SR_dly = '1') then + q3rnk1_var := '0'; + q4rnk1_var := '0'; + elsif(SR_dly = '0') then + q3rnk1_var := dataq3rnk1; + q4rnk1_var := dataq4rnk1; + end if; + end if; + + when others => + null; + + end case; + end if; + + q3rnk1 <= q3rnk1_var after DELAY_FFINP; + q4rnk1 <= q4rnk1_var after DELAY_FFINP; + + end process prcs_Q3Q4_rnk1; +--################################################################### +--##### clock mux -- oclkmux with delay element ##### +--################################################################### +-- prcs_oclkmux:process(OCLK_dly) +-- begin +-- case AttrOclkDelay is +-- when '0' => +-- oclkmux <= OCLK_dly after DELAY_MXINP1; +-- when '1' => +-- oclkmux <= OCLK_dly after DELAY_OCLKDLY; +-- when others => +-- oclkmux <= OCLK_dly after DELAY_MXINP1; +-- end case; +-- end process prcs_oclkmux; +-- +-- +-- +--/////////////////////////////////////////////////////////////////// +--// Mux elements for the 1st Rank +--/////////////////////////////////////////////////////////////////// +--################################################################### +--##### memmux -- 4 clock muxes in first rank ##### +--################################################################### + prcs_memmux:process(CLK_dly, OCLK_dly) + begin + case AttrInterfaceType is + when '0' => + memmux <= OCLK_dly after DELAY_MXINP1; + when '1' => + memmux <= CLK_dly after DELAY_MXINP1; + when others => + memmux <= OCLK_dly after DELAY_MXINP1; + end case; + end process prcs_memmux; + +--################################################################### +--##### q2pmux -- Optional inverter for q2p (4th flop in rank1) +--################################################################### + prcs_q2pmux:process(memmux) + begin + case AttrInterfaceType is + when '0' => + q2pmux <= not memmux after DELAY_MXINP1; + when '1' => + q2pmux <= memmux after DELAY_MXINP1; + when others => + q2pmux <= memmux after DELAY_MXINP1; + end case; + end process prcs_q2pmux; +--################################################################### +--##### data input muxes for q3q4 and q5q6 ##### +--################################################################### + prcs_Q3Q4_mux:process(q1prnk1, q2prnk1, q3rnk1, SHIFTIN1_dly, SHIFTIN2_dly) + begin + case sel1 is + when "00" => + dataq3rnk1 <= q1prnk1 after DELAY_MXINP1; + dataq4rnk1 <= q2prnk1 after DELAY_MXINP1; + when "01" => + dataq3rnk1 <= q1prnk1 after DELAY_MXINP1; + dataq4rnk1 <= q3rnk1 after DELAY_MXINP1; + when "10" => + dataq3rnk1 <= SHIFTIN2_dly after DELAY_MXINP1; + dataq4rnk1 <= SHIFTIN1_dly after DELAY_MXINP1; + when "11" => + dataq3rnk1 <= SHIFTIN1_dly after DELAY_MXINP1; + dataq4rnk1 <= q3rnk1 after DELAY_MXINP1; + when others => + dataq3rnk1 <= q1prnk1 after DELAY_MXINP1; + dataq4rnk1 <= q2prnk1 after DELAY_MXINP1; + end case; + + end process prcs_Q3Q4_mux; +---------------------------------------------------------------------- + prcs_Q5Q6_mux:process(q3rnk1, q4rnk1, q5rnk1) + begin + case AttrDataRate is + when '0' => + dataq5rnk1 <= q3rnk1 after DELAY_MXINP1; + dataq6rnk1 <= q4rnk1 after DELAY_MXINP1; + when '1' => + dataq5rnk1 <= q4rnk1 after DELAY_MXINP1; + dataq6rnk1 <= q5rnk1 after DELAY_MXINP1; + when others => + dataq5rnk1 <= q4rnk1 after DELAY_MXINP1; + dataq6rnk1 <= q5rnk1 after DELAY_MXINP1; + end case; + end process prcs_Q5Q6_mux; + + + +---//////////////////////////////////////////////////////////////////// +--- 2nd rank of registors +---//////////////////////////////////////////////////////////////////// + +--################################################################### +--##### clkdivmux to choose between clkdiv_int or CLKDIV ##### +--################################################################### + prcs_clkdivmux:process(clkdiv_int, CLKDIV_dly) + begin + case AttrBitslipEnable is + when '0' => + clkdivmux <= CLKDIV_dly after DELAY_MXINP1; + when '1' => + clkdivmux <= clkdiv_int after DELAY_MXINP1; + when others => + clkdivmux <= CLKDIV_dly after DELAY_MXINP1; + end case; + end process prcs_clkdivmux; + +--################################################################### +--##### q1rnk2, q2rnk2, q3rnk2,q4rnk2 ,q5rnk2 and q6rnk2 reg ##### +--################################################################### + prcs_Q1Q2Q3Q4Q5Q6_rnk2:process(clkdivmux, GSR_dly, SR_dly) + variable q1rnk2_var : std_ulogic := TO_X01(INIT_RANK2(0)); + variable q2rnk2_var : std_ulogic := TO_X01(INIT_RANK2(1)); + variable q3rnk2_var : std_ulogic := TO_X01(INIT_RANK2(2)); + variable q4rnk2_var : std_ulogic := TO_X01(INIT_RANK2(3)); + variable q5rnk2_var : std_ulogic := TO_X01(INIT_RANK2(4)); + variable q6rnk2_var : std_ulogic := TO_X01(INIT_RANK2(5)); + begin + if(GSR_dly = '1') then + q1rnk2_var := TO_X01(INIT_RANK2(0)); + q2rnk2_var := TO_X01(INIT_RANK2(1)); + q3rnk2_var := TO_X01(INIT_RANK2(2)); + q4rnk2_var := TO_X01(INIT_RANK2(3)); + q5rnk2_var := TO_X01(INIT_RANK2(4)); + q6rnk2_var := TO_X01(INIT_RANK2(5)); + elsif(GSR_dly = '0') then + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if(SR_dly = '1') then + q1rnk2_var := '0'; + q2rnk2_var := '0'; + q3rnk2_var := '0'; + q4rnk2_var := '0'; + q5rnk2_var := '0'; + q6rnk2_var := '0'; + elsif(SR_dly = '0') then + if(rising_edge(clkdivmux)) then + q1rnk2_var := dataq1rnk2; + q2rnk2_var := dataq2rnk2; + q3rnk2_var := dataq3rnk2; + q4rnk2_var := dataq4rnk2; + q5rnk2_var := dataq5rnk2; + q6rnk2_var := dataq6rnk2; + end if; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(clkdivmux)) then + if(SR_dly = '1') then + q1rnk2_var := '0'; + q2rnk2_var := '0'; + q3rnk2_var := '0'; + q4rnk2_var := '0'; + q5rnk2_var := '0'; + q6rnk2_var := '0'; + elsif(SR_dly = '0') then + q1rnk2_var := dataq1rnk2; + q2rnk2_var := dataq2rnk2; + q3rnk2_var := dataq3rnk2; + q4rnk2_var := dataq4rnk2; + q5rnk2_var := dataq5rnk2; + q6rnk2_var := dataq6rnk2; + end if; + end if; + when others => + null; + end case; + end if; + + q1rnk2 <= q1rnk2_var after DELAY_FFINP; + q2rnk2 <= q2rnk2_var after DELAY_FFINP; + q3rnk2 <= q3rnk2_var after DELAY_FFINP; + q4rnk2 <= q4rnk2_var after DELAY_FFINP; + q5rnk2 <= q5rnk2_var after DELAY_FFINP; + q6rnk2 <= q6rnk2_var after DELAY_FFINP; + + end process prcs_Q1Q2Q3Q4Q5Q6_rnk2; + +--################################################################### +--##### update bitslip mux ##### +--################################################################### + + bsmux <= AttrBitslipEnable & AttrDataRate & muxc; + +--################################################################### +--##### Data mux for 2nd rank of registers ###### +--################################################################### + prcs_Q1Q2Q3Q4Q5Q6_rnk2_mux:process(bsmux, q1rnk1, q1prnk1, q2prnk1, + q3rnk1, q4rnk1, q5rnk1, q6rnk1, q6prnk1) + begin + case bsmux is + when "000" | "001" => + dataq1rnk2 <= q2prnk1 after DELAY_MXINP2; + dataq2rnk2 <= q1prnk1 after DELAY_MXINP2; + dataq3rnk2 <= q4rnk1 after DELAY_MXINP2; + dataq4rnk2 <= q3rnk1 after DELAY_MXINP2; + dataq5rnk2 <= q6rnk1 after DELAY_MXINP2; + dataq6rnk2 <= q5rnk1 after DELAY_MXINP2; + when "100" => + dataq1rnk2 <= q2prnk1 after DELAY_MXINP2; + dataq2rnk2 <= q1prnk1 after DELAY_MXINP2; + dataq3rnk2 <= q4rnk1 after DELAY_MXINP2; + dataq4rnk2 <= q3rnk1 after DELAY_MXINP2; + dataq5rnk2 <= q6rnk1 after DELAY_MXINP2; + dataq6rnk2 <= q5rnk1 after DELAY_MXINP2; + when "101" => + dataq1rnk2 <= q1prnk1 after DELAY_MXINP2; + dataq2rnk2 <= q4rnk1 after DELAY_MXINP2; + dataq3rnk2 <= q3rnk1 after DELAY_MXINP2; + dataq4rnk2 <= q6rnk1 after DELAY_MXINP2; + dataq5rnk2 <= q5rnk1 after DELAY_MXINP2; + dataq6rnk2 <= q6prnk1 after DELAY_MXINP2; + when "010" | "011" | "110" | "111" => + dataq1rnk2 <= q1rnk1 after DELAY_MXINP2; + dataq2rnk2 <= q1prnk1 after DELAY_MXINP2; + dataq3rnk2 <= q3rnk1 after DELAY_MXINP2; + dataq4rnk2 <= q4rnk1 after DELAY_MXINP2; + dataq5rnk2 <= q5rnk1 after DELAY_MXINP2; + dataq6rnk2 <= q6rnk1 after DELAY_MXINP2; + when others => + dataq1rnk2 <= q2prnk1 after DELAY_MXINP2; + dataq2rnk2 <= q1prnk1 after DELAY_MXINP2; + dataq3rnk2 <= q4rnk1 after DELAY_MXINP2; + dataq4rnk2 <= q3rnk1 after DELAY_MXINP2; + dataq5rnk2 <= q6rnk1 after DELAY_MXINP2; + dataq6rnk2 <= q5rnk1 after DELAY_MXINP2; + end case; + end process prcs_Q1Q2Q3Q4Q5Q6_rnk2_mux; + +---//////////////////////////////////////////////////////////////////// +--- 3rd rank of registors +---//////////////////////////////////////////////////////////////////// + +--################################################################### +--##### q1rnk3, q2rnk3, q3rnk3, q4rnk3, q5rnk3 and q6rnk3 reg ##### +--################################################################### + prcs_Q1Q2Q3Q4Q5Q6_rnk3:process(CLKDIV_dly, GSR_dly, SR_dly) + variable q1rnk3_var : std_ulogic := TO_X01(INIT_RANK3(0)); + variable q2rnk3_var : std_ulogic := TO_X01(INIT_RANK3(1)); + variable q3rnk3_var : std_ulogic := TO_X01(INIT_RANK3(2)); + variable q4rnk3_var : std_ulogic := TO_X01(INIT_RANK3(3)); + variable q5rnk3_var : std_ulogic := TO_X01(INIT_RANK3(4)); + variable q6rnk3_var : std_ulogic := TO_X01(INIT_RANK3(5)); + begin + if(GSR_dly = '1') then + q1rnk3_var := TO_X01(INIT_RANK3(0)); + q2rnk3_var := TO_X01(INIT_RANK3(1)); + q3rnk3_var := TO_X01(INIT_RANK3(2)); + q4rnk3_var := TO_X01(INIT_RANK3(3)); + q5rnk3_var := TO_X01(INIT_RANK3(4)); + q6rnk3_var := TO_X01(INIT_RANK3(5)); + elsif(GSR_dly = '0') then + case AttrSRtype is + when 0 => + --------------- // async SET/RESET + if(SR_dly = '1') then + q1rnk3_var := '0'; + q2rnk3_var := '0'; + q3rnk3_var := '0'; + q4rnk3_var := '0'; + q5rnk3_var := '0'; + q6rnk3_var := '0'; + elsif(SR_dly = '0') then + if(rising_edge(CLKDIV_dly)) then + q1rnk3_var := q1rnk2; + q2rnk3_var := q2rnk2; + q3rnk3_var := q3rnk2; + q4rnk3_var := q4rnk2; + q5rnk3_var := q5rnk2; + q6rnk3_var := q6rnk2; + end if; + end if; + + when 1 => + --------------- // sync SET/RESET + if(rising_edge(CLKDIV_dly)) then + if(SR_dly = '1') then + q1rnk3_var := '0'; + q2rnk3_var := '0'; + q3rnk3_var := '0'; + q4rnk3_var := '0'; + q5rnk3_var := '0'; + q6rnk3_var := '0'; + elsif(SR_dly = '0') then + q1rnk3_var := q1rnk2; + q2rnk3_var := q2rnk2; + q3rnk3_var := q3rnk2; + q4rnk3_var := q4rnk2; + q5rnk3_var := q5rnk2; + q6rnk3_var := q6rnk2; + end if; + end if; + when others => + null; + end case; + end if; + + q1rnk3 <= q1rnk3_var after DELAY_FFINP; + q2rnk3 <= q2rnk3_var after DELAY_FFINP; + q3rnk3 <= q3rnk3_var after DELAY_FFINP; + q4rnk3 <= q4rnk3_var after DELAY_FFINP; + q5rnk3 <= q5rnk3_var after DELAY_FFINP; + q6rnk3 <= q6rnk3_var after DELAY_FFINP; + + end process prcs_Q1Q2Q3Q4Q5Q6_rnk3; + +---//////////////////////////////////////////////////////////////////// +--- Outputs +---//////////////////////////////////////////////////////////////////// + prcs_Q1Q2_rnk3_mux:process(q1rnk1, q1prnk1, q1rnk2, q1rnk3, + q2nrnk1, q2prnk1, q2rnk2, q2rnk3) + begin + case selrnk3 is + when "0000" | "0100" | "0X00" => + Q1_zd <= q1prnk1 after DELAY_MXINP1; + Q2_zd <= q2prnk1 after DELAY_MXINP1; + when "0001" | "0101" | "0X01" => + Q1_zd <= q1rnk1 after DELAY_MXINP1; + Q2_zd <= q2prnk1 after DELAY_MXINP1; + when "0010" | "0110" | "0X10" => + Q1_zd <= q1rnk1 after DELAY_MXINP1; + Q2_zd <= q2nrnk1 after DELAY_MXINP1; + when "1000" | "1001" | "1010" | "1011" | "10X0" | "10X1" | + "100X" | "101X" | "10XX" => + Q1_zd <= q1rnk2 after DELAY_MXINP1; + Q2_zd <= q2rnk2 after DELAY_MXINP1; + when "1100" | "1101" | "1110" | "1111" | "11X0" | "11X1" | + "110X" | "111X" | "11XX" => + Q1_zd <= q1rnk3 after DELAY_MXINP1; + Q2_zd <= q2rnk3 after DELAY_MXINP1; + when others => + Q1_zd <= q1rnk2 after DELAY_MXINP1; + Q2_zd <= q2rnk2 after DELAY_MXINP1; + end case; + end process prcs_Q1Q2_rnk3_mux; +-------------------------------------------------------------------- + prcs_Q3Q4Q5Q6_rnk3_mux:process(q3rnk2, q3rnk3, q4rnk2, q4rnk3, + q5rnk2, q5rnk3, q6rnk2, q6rnk3) + begin + case AttrBitslipEnable is + when '0' => + Q3_zd <= q3rnk2 after DELAY_MXINP1; + Q4_zd <= q4rnk2 after DELAY_MXINP1; + Q5_zd <= q5rnk2 after DELAY_MXINP1; + Q6_zd <= q6rnk2 after DELAY_MXINP1; + when '1' => + Q3_zd <= q3rnk3 after DELAY_MXINP1; + Q4_zd <= q4rnk3 after DELAY_MXINP1; + Q5_zd <= q5rnk3 after DELAY_MXINP1; + Q6_zd <= q6rnk3 after DELAY_MXINP1; + when others => + Q3_zd <= q3rnk2 after DELAY_MXINP1; + Q4_zd <= q4rnk2 after DELAY_MXINP1; + Q5_zd <= q5rnk2 after DELAY_MXINP1; + Q6_zd <= q6rnk2 after DELAY_MXINP1; + end case; + end process prcs_Q3Q4Q5Q6_rnk3_mux; +---------------------------------------------------------------------- +----------- Inverted CLK ----------------------------------------- +---------------------------------------------------------------------- + + CLKN_dly <= not CLK_dly; + +---------------------------------------------------------------------- +----------- Instant BSCNTRL_NODELAY ------------------------------ +---------------------------------------------------------------------- + INST_BSCNTRL_NODELAY : BSCNTRL_NODELAY + generic map ( + SRTYPE => SRTYPE, + INIT_BITSLIPCNT => INIT_BITSLIPCNT + ) + port map ( + CLKDIV_INT => clkdiv_int, + MUXC => muxc, + + BITSLIP => BITSLIP_dly, + C23 => c23, + C45 => c45, + C67 => c67, + CLK => CLKN_dly, + CLKDIV => CLKDIV_dly, + DATA_RATE => AttrDataRate, + GSR => GSR_dly, + R => SR_dly, + SEL => sel + ); + +--################################################################### +--##### Set value of the counter in BSCNTRL_NODELAY ##### +--################################################################### + prcs_bscntrl_nodelay_cntr:process + begin + wait for 10 ps; + case cntr is + when "00100" => + c23<='0'; c45<='0'; c67<='0'; sel<="00"; + when "00110" => + c23<='1'; c45<='0'; c67<='0'; sel<="00"; + when "01000" => + c23<='0'; c45<='0'; c67<='0'; sel<="01"; + when "01010" => + c23<='0'; c45<='1'; c67<='0'; sel<="01"; + when "10010" => + c23<='0'; c45<='0'; c67<='0'; sel<="00"; + when "10011" => + c23<='1'; c45<='0'; c67<='0'; sel<="00"; + when "10100" => + c23<='0'; c45<='0'; c67<='0'; sel<="01"; + when "10101" => + c23<='0'; c45<='1'; c67<='0'; sel<="01"; + when "10110" => + c23<='0'; c45<='0'; c67<='0'; sel<="10"; + when "10111" => + c23<='0'; c45<='0'; c67<='1'; sel<="10"; + when "11000" => + c23<='0'; c45<='0'; c67<='0'; sel<="11"; + when others => + assert FALSE + report "Error : DATA_WIDTH or DATA_RATE has illegal values." + severity failure; + end case; + wait on cntr, c23, c45, c67, sel; + + end process prcs_bscntrl_nodelay_cntr; + +---------------------------------------------------------------------- +----------- Instant Clock Enable Circuit ------------------------- +---------------------------------------------------------------------- + INST_ICE : ICE_MODULE_NODELAY + generic map ( + SRTYPE => SRTYPE, + INIT_CE => INIT_CE + ) + port map ( + ICE => ice, + + CE1 => CE1_dly, + CE2 => CE2_dly, + GSR => GSR_dly, + NUM_CE => AttrNumCe, + CLKDIV => CLKDIV_dly, + R => SR_dly + ); +---------------------------------------------------------------------- +----------- Instant IDELAY --------------------------------------- +---------------------------------------------------------------------- +-- INST_IDELAY : IDELAY +-- generic map ( +-- IOBDELAY_VALUE => IOBDELAY_VALUE, +-- IOBDELAY_TYPE => IOBDELAY_TYPE +-- ) +-- port map ( +-- O => idelay_out, +-- +-- C => CLKDIV_dly, +-- CE => DLYCE_dly, +-- +-- I => D_dly, +-- INC => DLYINC_dly, +-- RST => DLYRST_dly +-- ); +-- +--################################################################### +--##### IOBDELAY -- Delay input Data ##### +--################################################################### +-- prcs_d_delay:process(D_dly, idelay_out) +-- begin +-- case AttrIobDelay is +-- when 0 => +-- O_zd <= D_dly; +-- datain <= D_dly; +-- when 1 => +-- O_zd <= idelay_out; +-- datain <= D_dly; +-- when 2 => +-- O_zd <= D_dly; +-- datain <= idelay_out; +-- when 3 => +-- O_zd <= idelay_out; +-- datain <= idelay_out; +-- when others => +-- null; +-- end case; +-- end process prcs_d_delay; + +--#################################################################### + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(Q1_zd, Q2_zd, Q3_zd, Q4_zd, Q5_zd, Q6_zd, + SHIFTOUT1_zd, SHIFTOUT2_zd) + begin + Q1 <= Q1_zd after SYNC_PATH_DELAY; + Q2 <= Q2_zd after SYNC_PATH_DELAY; + Q3 <= Q3_zd after SYNC_PATH_DELAY; + Q4 <= Q4_zd after SYNC_PATH_DELAY; + Q5 <= Q5_zd after SYNC_PATH_DELAY; + Q6 <= Q6_zd after SYNC_PATH_DELAY; + SHIFTOUT1 <= SHIFTOUT1_zd after SYNC_PATH_DELAY; + SHIFTOUT2 <= SHIFTOUT2_zd after SYNC_PATH_DELAY; + end process prcs_output; +--#################################################################### + + +end ISERDES_NODELAY_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2005 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Jtag TAP contorller +-- / / +-- /___/ /\ Filename : JTAG_SIM_VIRTEX5.vhd +-- \ \ / \ Timestamp : Thu Nov 10 17:26:14 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 11/10/05 - Initial version. +-- End Revision + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Primitives.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.vpkg.all; +use unisim.Vcomponents.all; + + + +entity JTAG_SIM_VIRTEX5_SUBMOD is + + generic( + PART_NAME : string; + IRLength : integer + ); + + port( + TDO : out std_ulogic; + + TCK : in std_ulogic; + TDI : in std_ulogic; + TMS : in std_ulogic + ); + +end JTAG_SIM_VIRTEX5_SUBMOD; + +architecture JTAG_SIM_VIRTEX5_SUBMOD_V OF JTAG_SIM_VIRTEX5_SUBMOD is + + + TYPE JtagTapState is (TestLogicReset, RunTestIdle,SelectDRScan, CaptureDR, + ShiftDR, Exit1DR, PauseDR, Exit2DR, UPdateDR, + SelectIRScan, CaptureIR, ShiftIR, Exit1IR, PauseIR, + Exit2IR, UPdateIR); + + +------------------------------------------------------------------------------- +----------------- Virtex4 Specific Constants --------------------------------- +------------------------------------------------------------------------------- + + TYPE JtagInstructionType is (UNKNOWN, IR_CAPTURE, BYPASS, IDCODE, USER1, USER2, USER3, USER4); + + TYPE PartType is (LX30, LX50, LX85, LX110, LX220, LX330, + LX30T, LX50T, LX85T, LX110T, LX220T, LX330T); + + constant IRLengthMax : integer := 14; + constant IDLength : integer := 32; + constant RevBitsLength : integer := 4; + + constant IR_CAPTURE_VAL : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111010001"; + constant BYPASS_INSTR : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111111111"; + constant IDCODE_INSTR : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111001001"; + constant USER1_INSTR : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111000010"; + constant USER2_INSTR : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111000011"; + constant USER3_INSTR : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111100010"; + constant USER4_INSTR : std_logic_vector ((IRLengthMax -1) downto 0) := "11111111100011"; + + + +-------------------------------------------------------- + + constant DELAY_SIG : time := 1 ps; + + constant Xon : boolean := true; + constant MsgOn : boolean := true; + + signal ticd_TCK : VitalDelayType := 0.0 ns; + + signal tisd_TDI_TCK : VitalDelayType := 0.0 ns; + signal tisd_TMS_TCK : VitalDelayType := 0.0 ns; + + signal tsetup_TMS_TCK_posedge_posedge : VitalDelayType := 1.0 ns; + signal tsetup_TMS_TCK_negedge_posedge : VitalDelayType := 1.0 ns; + + signal tsetup_TDI_TCK_posedge_posedge : VitalDelayType := 1.0 ns; + signal tsetup_TDI_TCK_negedge_posedge : VitalDelayType := 1.0 ns; + + signal thold_TMS_TCK_posedge_posedge : VitalDelayType := 2.0 ns; + signal thold_TMS_TCK_negedge_posedge : VitalDelayType := 2.0 ns; + + signal thold_TDI_TCK_posedge_posedge : VitalDelayType := 2.0 ns; + signal thold_TDI_TCK_negedge_posedge : VitalDelayType := 2.0 ns; + + signal tpd_TCK_TDO : VitalDelayType01 := (6.0 ns, 6.0 ns); + + signal CurrentState : JtagTapState := TestLogicReset; + signal JtagInstruction : JtagInstructionType := IDCODE; + + signal jtag_state_name : JtagTapState := TestLogicReset; + signal jtag_instruction_name : JtagInstructionType := IDCODE; + + signal TCK_ipd : std_ulogic := 'X'; + signal TDI_ipd : std_ulogic := 'X'; + signal TMS_ipd : std_ulogic := 'X'; + signal TRST_ipd : std_ulogic := 'X'; + + + signal TCK_dly : std_ulogic := 'X'; + signal TDI_dly : std_ulogic := 'X'; + signal TMS_dly : std_ulogic := 'X'; + signal TRST_dly : std_ulogic := '0'; + + signal TDO_zd : std_ulogic := 'X'; + signal TDO_viol : std_ulogic := 'X'; + +----------- signal declaration ------------------- + + signal CaptureDR_sig : std_ulogic := '0'; + signal RESET_sig : std_ulogic := '0'; + signal ShiftDR_sig : std_ulogic := '0'; + signal UpdateDR_sig : std_ulogic := '0'; + + signal ClkIR_active : std_ulogic := '0'; + + signal ClkIR_sig : std_ulogic := '0'; + signal ClkID_sig : std_ulogic := '0'; + signal ShiftIR_sig : std_ulogic := 'X'; + signal UpdateIR_sig : std_ulogic := 'X'; + signal ClkUpdateIR_sig : std_ulogic := '0'; + signal IRcontent_sig : std_logic_vector ((IRLength -1) downto 0) := (others => 'X'); + signal IDCODEval_sig : std_logic_vector ((IDLength -1) downto 0) := (others => 'X'); + + signal BypassReg : std_ulogic := '0'; + signal BYPASS_sig : std_ulogic := '0'; + signal IDCODE_sig : std_ulogic := '0'; + signal USER1_sig : std_ulogic := '0'; + signal USER2_sig : std_ulogic := '0'; + signal USER3_sig : std_ulogic := '0'; + signal USER4_sig : std_ulogic := '0'; + + signal TDO_latch : std_ulogic := 'Z'; + + signal Tlrst_sig : std_ulogic := '1'; + signal TlrstN_sig : std_ulogic := '1'; + + signal IRegLastBit_sig : std_ulogic := '0'; + signal IDregLastBit_sig : std_ulogic := '0'; + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + TCK_dly <= TCK after 0 ps; + TDI_dly <= TDI after 0 ps; + TMS_dly <= TMS after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + variable PartName_var : PartType; + variable IDCODE_str : std_ulogic_vector ((IDLength -1) downto 0) := (others => 'X'); + begin + if((PART_NAME = "LX30") or (PART_NAME = "lx30")) then + PartName_var := LX30; + IDCODE_str := X"0286E093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "LX50") or (PART_NAME = "lx50")) then + PartName_var := LX50; + IDCODE_str := X"02896093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "LX85") or (PART_NAME = "lx85")) then + PartName_var := LX85; + IDCODE_str := X"028AE093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "LX110") or (PART_NAME = "lx110")) then + PartName_var := LX110; + IDCODE_str := X"028D6093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "LX220") or (PART_NAME = "lx220")) then + PartName_var := LX220; + IDCODE_str := X"0290C093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "LX330") or (PART_NAME = "lx330")) then + PartName_var := LX330; + IDCODE_str := X"0295C093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "LX30T") or (PART_NAME = "lx30t")) then + PartName_var := LX30T; + IDCODE_str := X"02A6E093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "LX50T") or (PART_NAME = "lx50t")) then + PartName_var := LX50T; + IDCODE_str := X"02A96093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "LX85T") or (PART_NAME = "lx85t")) then + PartName_var := LX85T; + IDCODE_str := X"02AAE093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "LX110T") or (PART_NAME = "lx110t")) then + PartName_var := LX110T; + IDCODE_str := X"02AD6093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "LX220T") or (PART_NAME = "lx220t")) then + PartName_var := LX220T; + IDCODE_str := X"02B0C093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "LX330T") or (PART_NAME = "lx330t")) then + PartName_var := LX330T; + IDCODE_str := X"02B5C093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + else + assert false + report "Attribute Syntax Error: The allowed values for PART_NAME are LX30, LX50, LX85, LX110, LX220, LX330, LX30T, LX50T, LX85T, LX110T, LX220T or LX330T" + severity Failure; + end if; + + wait; + + end process prcs_init; +--#################################################################### +--##### JtagTapSM ##### +--#################################################################### + prcs_JtagTapSM:process(TCK_dly, TRST_dly) + begin + + if(TRST_dly = '1') then + CurrentState <= TestLogicReset; + elsif(TRST_dly = '0') then + if(rising_edge(TCK_dly)) then + case CurrentState is + ------------------------------- + ---- Reset path --------------- + ------------------------------- + when TestLogicReset => + if(TMS_dly = '0') then + CurrentState <= RunTestIdle; + end if; + when RunTestIdle => + if(TMS_dly = '1') then + CurrentState <= SelectDRScan; + end if; + ------------------------------- + ------ DR path --------------- + ------------------------------- + when SelectDRScan => + if(TMS_dly = '0') then + CurrentState <= CaptureDR; + elsif(TMS_dly = '1') then + CurrentState <= SelectIRScan; + end if; + when CaptureDR => + if(TMS_dly = '0') then + CurrentState <= ShiftDR; + elsif(TMS_dly = '1') then + CurrentState <= Exit1DR; + end if; + when ShiftDR => + if(TMS_dly = '1') then + CurrentState <= Exit1DR; + end if; + + if(IRcontent_sig = BYPASS_INSTR((IRLength -1) downto 0)) then + BypassReg <= TDI_dly; + end if; + + when Exit1DR => + if(TMS_dly = '0') then + CurrentState <= PauseDR; + elsif(TMS_dly = '1') then + CurrentState <= UpdateDR; + end if; + when PauseDR => + if(TMS_dly = '1') then + CurrentState <= Exit2DR; + end if; + when Exit2DR => + if(TMS_dly = '0') then + CurrentState <= ShiftDR; + elsif(TMS_dly = '1') then + CurrentState <= UpdateDR; + end if; + when UpdateDR => + if(TMS_dly = '0') then + CurrentState <= RunTestIdle; + elsif(TMS_dly = '1') then + CurrentState <= SelectDRScan; + end if; + ------------------------------- + ------ IR path --------------- + ------------------------------- + when SelectIRScan => + if(TMS_dly = '0') then + CurrentState <= CaptureIR; + elsif(TMS_dly = '1') then + CurrentState <= TestLogicReset; + end if; + when CaptureIR => + if(TMS_dly = '0') then + CurrentState <= ShiftIR; + elsif(TMS_dly = '1') then + CurrentState <= Exit1IR; + end if; + when ShiftIR => + if(TMS_dly = '1') then + CurrentState <= Exit1IR; + end if; + when Exit1IR => + if(TMS_dly = '0') then + CurrentState <= PauseIR; + elsif(TMS_dly = '1') then + CurrentState <= UpdateIR; + end if; + when PauseIR => + if(TMS_dly = '1') then + CurrentState <= Exit2IR; + end if; + when Exit2IR => + if(TMS_dly = '0') then + CurrentState <= ShiftIR; + elsif(TMS_dly = '1') then + CurrentState <= UpdateIR; + end if; + when UpdateIR => + if(TMS_dly = '0') then + CurrentState <= RunTestIdle; + elsif(TMS_dly = '1') then + CurrentState <= SelectDRScan; + end if; + end case; + end if; + end if; + end process prcs_JtagTapSM; + +--#################################################################### +--##### CurrentState ##### +--#################################################################### + + prcs_CurrentState:process(TCK_dly, CurrentState, TRST_dly) + begin + + ClkIR_sig <= '1'; + + if(TRST_dly = '1') then + CaptureDR_sig <= '0'; + ShiftDR_sig <= '0'; + UpdateDR_sig <= '0'; + ShiftIR_sig <= '0'; + UpdateIR_sig <= '0'; + elsif(TRST_dly = '0') then + + case CurrentState is + + when TestLogicReset => + Tlrst_sig <= '1' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + + when CaptureDR => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '1' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + + when ShiftDR => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '1' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + + when UpdateDR => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '1' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + + when CaptureIR => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + ClkIR_sig <= TCK_dly; + + + when ShiftIR => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '1' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + ClkIR_sig <= TCK_dly; + + when UpdateIR => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '1' after DELAY_SIG; + + when others => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + end case; + end if; + + end process prcs_CurrentState; + +------------- ?? TCK NEGATIVE EDGE activities ---------- + + prcs_ClkIR:process(TCK_dly) + begin +-- ClkIR_sig <= ShiftIR_sig and TCK_dly; + CLkUpdateIR_sig <= UpdateIR_sig and not TCK_dly; + end process prcs_ClkIR; + + prcs_ClkID:process(TCK_dly) + begin + ClkID_sig <= IDCODE_sig and TCK_dly; + end process prcs_ClkID; + + prcs_glblsigs:process(TCK_dly, UpdateDR_sig) + begin + if(falling_edge(TCK_dly)) then + JTAG_CAPTURE_GLBL <= CaptureDR_sig; + -- CR 211337 Reset should go high as soon as it gets to State Trlst + -- JTAG_RESET_GLBL <= Tlrst_sig; + JTAG_SHIFT_GLBL <= ShiftDR_sig; + JTAG_UPDATE_GLBL <= UpdateDR_sig; + TlrstN_sig <= Tlrst_sig; + end if; + + if(falling_edge(UpdateDR_sig))then + JTAG_UPDATE_GLBL <= UpdateDR_sig; + end if; + + end process prcs_glblsigs; + +-- CR 211337 + prcs_reset:process(Tlrst_sig) + begin + JTAG_RESET_GLBL <= Tlrst_sig; + end process prcs_reset; +--#################################################################### +--##### JtagIR ##### +--#################################################################### + prcs_JtagIR:process(ClkIR_sig, ClkUpdateIR_sig, ShiftIR_sig, TlrstN_sig, TRST_dly) + variable NextIRreg : std_logic_vector ((IRLength -1) downto 0) := IR_CAPTURE_VAL((IRLength -1) downto 0); + variable ir_int : std_logic_vector ((IRLength -1) downto 0) := IR_CAPTURE_VAL((IRLength -1) downto 0); + begin + NextIRreg((IRLength -1) downto 0) := (TDI_dly & ir_int((IRLength -1) downto 1)); + + if((TRST_dly = '1') or (TlrstN_sig = '1'))then + IRcontent_sig((IRLength -1) downto 0) <= IDCODE_INSTR((IRLength -1) downto 0); -- IDCODE instruction is loaded into IR reg. + IRegLastBit_sig <= ir_int(0); + elsif((TRST_dly = '0') and (TlrstN_sig = '0')) then + if(rising_edge(ClkIR_sig)) then + if(ShiftIR_sig = '1') then + ir_int((IRLength -1) downto 0) := NextIRreg((IRLength -1) downto 0); + IRegLastBit_sig <= ir_int(0); + else + ir_int := IR_CAPTURE_VAL((IRLength -1) downto 0); + IRegLastBit_sig <= ir_int(0); + end if; + end if; + if(rising_edge(ClkUpdateIR_sig)) then + if(UpdateIR_sig = '1') then + IRcontent_sig <= ir_int; + end if; + end if; + end if; + end process prcs_JtagIR; +--#################################################################### +--##### JtagDecodeIR ##### +--#################################################################### + prcs_JtagDecodeIR:process(IRcontent_sig) + begin + if(IRcontent_sig((IRLength -1) downto 0) = IR_CAPTURE_VAL((IRLength-1) downto 0)) then + JTagInstruction <= IR_CAPTURE; + + elsif(IRcontent_sig((IRLength -1) downto 0) = BYPASS_INSTR((IRLength-1) downto 0)) then + JTagInstruction <= BYPASS; + BYPASS_sig <= '1'; + IDCODE_sig <= '0'; + USER1_sig <= '0'; + USER2_sig <= '0'; + USER3_sig <= '0'; + USER4_sig <= '0'; + + elsif(IRcontent_sig((IRLength -1) downto 0) = IDCODE_INSTR((IRLength-1) downto 0)) then + JTagInstruction <= IDCODE; + BYPASS_sig <= '0'; + IDCODE_sig <= '1'; + USER1_sig <= '0'; + USER2_sig <= '0'; + USER3_sig <= '0'; + USER4_sig <= '0'; + + elsif(IRcontent_sig((IRLength -1) downto 0) = USER1_INSTR((IRLength-1) downto 0)) then + JTagInstruction <= USER1; + BYPASS_sig <= '0'; + IDCODE_sig <= '0'; + USER1_sig <= '1'; + USER2_sig <= '0'; + USER3_sig <= '0'; + USER4_sig <= '0'; + + elsif(IRcontent_sig((IRLength -1) downto 0) = USER2_INSTR((IRLength-1) downto 0)) then + JTagInstruction <= USER2; + BYPASS_sig <= '0'; + IDCODE_sig <= '0'; + USER1_sig <= '0'; + USER2_sig <= '1'; + USER3_sig <= '0'; + USER4_sig <= '0'; + + elsif(IRcontent_sig((IRLength -1) downto 0) = USER3_INSTR((IRLength-1) downto 0)) then + JTagInstruction <= USER3; + BYPASS_sig <= '0'; + IDCODE_sig <= '0'; + USER1_sig <= '0'; + USER2_sig <= '0'; + USER3_sig <= '1'; + USER4_sig <= '0'; + + elsif(IRcontent_sig((IRLength -1) downto 0) = USER4_INSTR((IRLength-1) downto 0)) then + JTagInstruction <= USER4; + BYPASS_sig <= '0'; + IDCODE_sig <= '0'; + USER1_sig <= '0'; + USER2_sig <= '0'; + USER3_sig <= '0'; + USER4_sig <= '1'; + + else + JTagInstruction <= UNKNOWN; + NULL; + end if; + end process prcs_JtagDecodeIR; +--#################################################################### +--##### JtagIDCODE ##### +--#################################################################### + prcs_JtagIDCODE:process(ClkID_sig) + variable IDreg : bit_vector ((IDLength -1) downto 0); + begin + if(rising_edge(ClkID_sig)) then + if(ShiftDR_sig = '1') then + IDreg := IDreg sra 1; + IDreg(IDLength -1) := TO_BIT(TDI_dly); + else + IDreg := TO_BITVECTOR(IDCODEval_sig); + end if; + end if; + + IDregLastBit_sig <= TO_STDULOGIC(IDreg(0)); + + end process prcs_JtagIDCODE; +--#################################################################### +--#################################################################### +--##### JtagSetGlobalSignals ##### +--#################################################################### + prcs_JtagSetGlobalSignals:process(ClkUpdateIR_sig, Tlrst_sig, USER1_sig, USER2_sig, USER3_sig, USER4_sig) + begin + if(rising_edge(USER1_sig)) then + JTAG_SEL1_GLBL <= '1'; + JTAG_SEL2_GLBL <= '0'; + JTAG_SEL3_GLBL <= '0'; + JTAG_SEL4_GLBL <= '0'; + elsif(rising_edge(USER2_sig)) then + JTAG_SEL1_GLBL <= '0'; + JTAG_SEL2_GLBL <= '1'; + JTAG_SEL3_GLBL <= '0'; + JTAG_SEL4_GLBL <= '0'; + elsif(rising_edge(USER3_sig)) then + JTAG_SEL1_GLBL <= '0'; + JTAG_SEL2_GLBL <= '0'; + JTAG_SEL3_GLBL <= '1'; + JTAG_SEL4_GLBL <= '0'; + elsif(rising_edge(USER4_sig)) then + JTAG_SEL1_GLBL <= '0'; + JTAG_SEL2_GLBL <= '0'; + JTAG_SEL3_GLBL <= '0'; + JTAG_SEL4_GLBL <= '1'; + elsif(rising_edge(ClkUpdateIR_sig)) then + JTAG_SEL1_GLBL <= '0'; + JTAG_SEL2_GLBL <= '0'; + JTAG_SEL3_GLBL <= '0'; + JTAG_SEL4_GLBL <= '0'; + elsif(rising_edge(Tlrst_sig)) then + JTAG_SEL1_GLBL <= '0'; + JTAG_SEL2_GLBL <= '0'; + JTAG_SEL3_GLBL <= '0'; + JTAG_SEL4_GLBL <= '0'; + end if; + + end process prcs_JtagSetGlobalSignals; + +--#################################################################### + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + + jtag_state_name <= CurrentState; + jtag_instruction_name <= JtagInstruction; + + JTAG_TCK_GLBL <= TCK_dly; + JTAG_TDI_GLBL <= TDI_dly; + JTAG_TMS_GLBL <= TMS_dly; + JTAG_TRST_GLBL <= TRST_dly; + + TDO_latch <= BypassReg + when ((CurrentState = ShiftDR) and (IRcontent_sig=BYPASS_INSTR((IRLength -1) downto 0))) + else IRegLastBit_sig + when (CurrentState = ShiftIR) + else IDregLastBit_sig + when ((CurrentState = ShiftDR) and (IRcontent_sig=IDCODE_INSTR((IRLength -1) downto 0))) + else JTAG_USER_TDO1_GLBL + when ((CurrentState = ShiftDR) and (IRcontent_sig=USER1_INSTR((IRLength -1) downto 0))) + else JTAG_USER_TDO2_GLBL + when ((CurrentState = ShiftDR) and (IRcontent_sig=USER2_INSTR((IRLength -1) downto 0))) + else JTAG_USER_TDO3_GLBL + when ((CurrentState = ShiftDR) and (IRcontent_sig=USER3_INSTR((IRLength -1) downto 0))) + else JTAG_USER_TDO4_GLBL + when ((CurrentState = ShiftDR) and (IRcontent_sig=USER4_INSTR((IRLength -1) downto 0))) + else 'Z'; + +-- CR 212040 -- added timing +-- prcs_TDO:process(TCK_dly) +-- begin +-- if(falling_edge(TCK_dly)) then +-- TDO <= TDO_latch; +-- end if; +-- end process prcs_TDO; + +--#################################################################### +--##### Timing ##### +--#################################################################### + VITALBehavior : process (TCK_dly, TDI_dly, TMS_dly) + + variable PInfo_TCK : VitalPeriodDataType := VitalPeriodDataInit; + variable Pviol_TCK : std_ulogic := '0'; + + variable Tmkr_TDI_TCK_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tviol_TDI_TCK_posedge : std_ulogic := '0'; + + variable Tmkr_TMS_TCK_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tviol_TMS_TCK_posedge : std_ulogic := '0'; + + variable Violation : std_ulogic := '0'; + + variable TDO_GlitchData : VitalGlitchDataType; + + + begin + VitalSetupHoldCheck ( + Violation => Tviol_TDI_TCK_posedge, + TimingData => Tmkr_TDI_TCK_posedge, + TestSignal => TDI_dly, + TestSignalName => "TDI", + TestDelay => tisd_TDI_TCK, + RefSignal => TCK_dly, + RefSignalName => "TCK", + RefDelay => ticd_TCK, + SetupHigh => tsetup_TDI_TCK_posedge_posedge, + SetupLow => tsetup_TDI_TCK_negedge_posedge, + HoldLow => thold_TDI_TCK_posedge_posedge, + HoldHigh => thold_TDI_TCK_negedge_posedge, + CheckEnabled => TO_X01(TRST_dly) = '0', + RefTransition => 'R', + HeaderMsg => "/X_JTAG_SIM_VIRTEX5", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + VitalSetupHoldCheck ( + Violation => Tviol_TMS_TCK_posedge, + TimingData => Tmkr_TMS_TCK_posedge, + TestSignal => TMS_dly, + TestSignalName => "TMS", + TestDelay => tisd_TMS_TCK, + RefSignal => TCK_dly, + RefSignalName => "TCK", + RefDelay => ticd_TCK, + SetupHigh => tsetup_TMS_TCK_posedge_posedge, + SetupLow => tsetup_TMS_TCK_negedge_posedge, + HoldLow => thold_TMS_TCK_posedge_posedge, + HoldHigh => thold_TMS_TCK_negedge_posedge, + CheckEnabled => TO_X01(TRST_dly) = '0', + RefTransition => 'R', + HeaderMsg => "/X_JTAG_SIM_VIRTEX5", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + VitalPathDelay01 ( + OutSignal => TDO, + GlitchData => TDO_GlitchData, + OutSignalName => "TDO", + OutTemp => TDO_latch, + Paths => (0 => (TCK_dly'last_event, tpd_TCK_TDO, TRST_dly = '0')), + Mode => VitalTransport, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end process; + + + +--#################################################################### +--#################################################################### + + +end JTAG_SIM_VIRTEX5_SUBMOD_V; + + +----- CELL JTAG_SIM_VIRTEX5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.vpkg.all; +use unisim.Vcomponents.all; + +entity JTAG_SIM_VIRTEX5 is + + generic( + PART_NAME : string := "LX50" + ); + + port( + TDO : out std_ulogic; + + TCK : in std_ulogic; + TDI : in std_ulogic; + TMS : in std_ulogic + ); + +end JTAG_SIM_VIRTEX5; + +architecture JTAG_SIM_VIRTEX5_V OF JTAG_SIM_VIRTEX5 is + + component JTAG_SIM_VIRTEX5_SUBMOD + generic( + PART_NAME : string; + IRLength : integer + ); + + port( + TDO : out std_ulogic; + + TCK : in std_ulogic; + TDI : in std_ulogic; + TMS : in std_ulogic + ); + end component; + + signal TCK_ipd : std_ulogic := 'X'; + signal TDI_ipd : std_ulogic := 'X'; + signal TMS_ipd : std_ulogic := 'X'; + signal TRST_ipd : std_ulogic := 'X'; + + + signal TCK_dly : std_ulogic := 'X'; + signal TDI_dly : std_ulogic := 'X'; + signal TMS_dly : std_ulogic := 'X'; + signal TRST_dly : std_ulogic := '0'; + + signal TDO_zd : std_ulogic := 'X'; + signal TDO_viol : std_ulogic := 'X'; + + signal TDO1_zd : std_ulogic := 'X'; + signal TDO2_zd : std_ulogic := 'X'; + + signal IRLen10, IRLen14 : boolean := false; + + + + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + TCK_dly <= TCK after 0 ps; + TDI_dly <= TDI after 0 ps; + TMS_dly <= TMS after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + + +--#################################################################### +--##### Initialization ##### +--#################################################################### + prcs_init:process + begin + if((PART_NAME = "LX30") or (PART_NAME = "lx30") or + (PART_NAME = "LX50") or (PART_NAME = "lx50") or + (PART_NAME = "LX85") or (PART_NAME = "lx85") or + (PART_NAME = "LX110") or (PART_NAME = "lx110") or + (PART_NAME = "LX220") or (PART_NAME = "lx220") or + (PART_NAME = "LX330") or (PART_NAME = "lx330") or + (PART_NAME = "LX30T") or (PART_NAME = "lx30t") or + (PART_NAME = "LX50T") or (PART_NAME = "lx50t") or + (PART_NAME = "LX85T") or (PART_NAME = "lx85t") or + (PART_NAME = "LX110T") or (PART_NAME = "lx110t") or + (PART_NAME = "LX220T") or (PART_NAME = "lx220t") or + (PART_NAME = "LX330T") or (PART_NAME = "lx330t")) then + IRLen10 <= true; + elsif((PART_NAME = "FX40") or (PART_NAME = "fx40") or + (PART_NAME = "FX60") or (PART_NAME = "fx60") or + (PART_NAME = "FX100") or (PART_NAME = "fx100") or + (PART_NAME = "FX140") or (PART_NAME = "fx140") or + (PART_NAME = "FX200") or (PART_NAME = "fx200")) then + IRLen14 <= true; + end if; + + wait; + + end process prcs_init; + +--#################################################################### +--##### Generate ##### +--#################################################################### + G1: if((PART_NAME = "LX30") or (PART_NAME = "lx30") or + (PART_NAME = "LX50") or (PART_NAME = "lx50") or + (PART_NAME = "LX85") or (PART_NAME = "lx85") or + (PART_NAME = "LX110") or (PART_NAME = "lx110") or + (PART_NAME = "LX220") or (PART_NAME = "lx220") or + (PART_NAME = "LX330") or (PART_NAME = "lx330") or + (PART_NAME = "LX30T") or (PART_NAME = "lx30t") or + (PART_NAME = "LX50T") or (PART_NAME = "lx50t") or + (PART_NAME = "LX85T") or (PART_NAME = "lx85t") or + (PART_NAME = "LX110T") or (PART_NAME = "lx110t") or + (PART_NAME = "LX220T") or (PART_NAME = "lx220t") or + (PART_NAME = "LX330T") or (PART_NAME = "lx330t")) generate + + JTAG_INST : JTAG_SIM_VIRTEX5_SUBMOD + generic map ( + PART_NAME => PART_NAME, + IRLength => 10 + ) + port map ( + TDO => TDO1_zd, + TCK => TCK_dly, + TDI => TDI_dly, + TMS => TMS_dly + ); + + end generate; + + G2: if((PART_NAME = "FX40") or (PART_NAME = "fx40") or + (PART_NAME = "FX60") or (PART_NAME = "fx60") or + (PART_NAME = "FX100") or (PART_NAME = "fx100") or + (PART_NAME = "FX140") or (PART_NAME = "fx140") or + (PART_NAME = "FX200") or (PART_NAME = "fx200")) generate + + JTAG_INST : JTAG_SIM_VIRTEX5_SUBMOD + generic map ( + PART_NAME => PART_NAME, + IRLength => 14 + ) + port map ( + TDO => TDO2_zd, + TCK => TCK_dly, + TDI => TDI_dly, + TMS => TMS_dly + ); + + end generate; + + + +--#################################################################### + + TDO <= TDO1_zd when IRLen10 else + TDO2_zd when IRLen14; + + +end JTAG_SIM_VIRTEX5_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / +-- /___/ /\ Filename : KEY_CLEAR.vhd +-- \ \ / \ Timestamp : Wed Aug 17 17:14:41 PDT 2005 +-- \___\/\___\ +-- +-- Revision: +-- 08/17/05 - Initial version. +-- End Revision: + +----- CELL KEY_CLEAR ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity KEY_CLEAR is + port( + KEYCLEARB : in std_ulogic + ); + +end KEY_CLEAR; + +architecture KEY_CLEAR_V of KEY_CLEAR is + +begin +end KEY_CLEAR_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/lut5_d.vhd,v 1.2 2006/03/11 00:55:40 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input Look-Up-Table with Dual Output +-- /___/ /\ Filename : lut5_d.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:02 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 03/15/05 - Modified to handle the address unknown case. +-- 03/10/06 - Change d to df in function lut4_mux4f and replace TO_INTEGER to +-- SLV_TO_INT. (CR 226842) +-- End Revision + +----- CELL LUT5_D ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity LUT5_D is + generic( + INIT : bit_vector := X"00000000" + ); + + port( + LO : out std_ulogic; + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end LUT5_D; + +architecture LUT5_D_V of LUT5_D is + +function lut6_mux8 (d : std_logic_vector(7 downto 0); s : std_logic_vector(2 downto 0)) + return std_logic is + + variable lut6_mux8_o : std_logic; + function lut4_mux4f (df : std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) ) + return std_logic is + + variable lut4_mux4_f : std_logic; + begin + + if (((sf(1) xor sf(0)) = '1') or ((sf(1) xor sf(0)) = '0')) then + lut4_mux4_f := df(SLV_TO_INT(sf)); + elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0' + and (df(0) xor df(2)) = '0') then + lut4_mux4_f := df(0); + elsif ((sf(1) = '0') and (df(0) = df(1))) then + lut4_mux4_f := df(0); + elsif ((sf(1) = '1') and (df(2) = df(3))) then + lut4_mux4_f := df(2); + elsif ((sf(0) = '0') and (df(0) = df(2))) then + lut4_mux4_f := df(0); + elsif ((sf(0) = '1') and (df(1) = df(3))) then + lut4_mux4_f := df(1); + else + lut4_mux4_f := 'X'; + end if; + + return (lut4_mux4_f); + + end function lut4_mux4f; + begin + + if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then + lut6_mux8_o := d(SLV_TO_INT(s)); + else + lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) & + lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2))); + end if; + + return (lut6_mux8_o); + + end function lut6_mux8; + +function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) ) + return std_logic is + + variable lut4_mux4_o : std_logic; + begin + + if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then + lut4_mux4_o := d(SLV_TO_INT(s)); + elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0' + and (d(0) xor d(2)) = '0') then + lut4_mux4_o := d(0); + elsif ((s(1) = '0') and (d(0) = d(1))) then + lut4_mux4_o := d(0); + elsif ((s(1) = '1') and (d(2) = d(3))) then + lut4_mux4_o := d(2); + elsif ((s(0) = '0') and (d(0) = d(2))) then + lut4_mux4_o := d(0); + elsif ((s(0) = '1') and (d(1) = d(3))) then + lut4_mux4_o := d(1); + else + lut4_mux4_o := 'X'; + end if; + + return (lut4_mux4_o); + + end function lut4_mux4; + + constant INIT_reg : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT); + +begin + + + lut_p : process (I0, I1, I2, I3, I4) + variable I_reg : std_logic_vector(4 downto 0); + variable O_out : std_ulogic; + begin + + I_reg := TO_STDLOGICVECTOR(I4 & I3 & I2 & I1 & I0); + + if ((I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I4 xor I3 xor I2 xor I1 xor I0) = '0') then + O_out := INIT_reg(SLV_TO_INT(I_reg)); + else + + O_out := lut4_mux4 ( + (lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))), + I_reg(4 downto 3)); + + end if; + LO <= O_out; + O <= O_out; + end process; +end LUT5_D_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/lut5_l.vhd,v 1.2 2006/03/11 00:55:40 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input Look-Up-Table with General Output +-- /___/ /\ Filename : lut5_l.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:02 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 03/15/05 - Modified to handle the address unknown case. +-- 03/10/06 - Change d to df in function lut4_mux4f and replace TO_INTEGER to +-- SLV_TO_INT. (CR 226842) +-- End Revision + +----- CELL LUT5_L ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity LUT5_L is + generic( + INIT : bit_vector := X"00000000" + ); + + port( + LO : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end LUT5_L; + +architecture LUT5_L_V of LUT5_L is + +function lut6_mux8 (d : std_logic_vector(7 downto 0); s : std_logic_vector(2 downto 0)) + return std_logic is + + variable lut6_mux8_o : std_logic; + function lut4_mux4f (df : std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) ) + return std_logic is + + variable lut4_mux4_f : std_logic; + begin + + if (((sf(1) xor sf(0)) = '1') or ((sf(1) xor sf(0)) = '0')) then + lut4_mux4_f := df(SLV_TO_INT(sf)); + elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0' + and (df(0) xor df(2)) = '0') then + lut4_mux4_f := df(0); + elsif ((sf(1) = '0') and (df(0) = df(1))) then + lut4_mux4_f := df(0); + elsif ((sf(1) = '1') and (df(2) = df(3))) then + lut4_mux4_f := df(2); + elsif ((sf(0) = '0') and (df(0) = df(2))) then + lut4_mux4_f := df(0); + elsif ((sf(0) = '1') and (df(1) = df(3))) then + lut4_mux4_f := df(1); + else + lut4_mux4_f := 'X'; + end if; + + return (lut4_mux4_f); + + end function lut4_mux4f; + begin + + if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then + lut6_mux8_o := d(SLV_TO_INT(s)); + else + lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) & + lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2))); + end if; + + return (lut6_mux8_o); + + end function lut6_mux8; + +function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) ) + return std_logic is + + variable lut4_mux4_o : std_logic; + begin + + if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then + lut4_mux4_o := d(SLV_TO_INT(s)); + elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0' + and (d(0) xor d(2)) = '0') then + lut4_mux4_o := d(0); + elsif ((s(1) = '0') and (d(0) = d(1))) then + lut4_mux4_o := d(0); + elsif ((s(1) = '1') and (d(2) = d(3))) then + lut4_mux4_o := d(2); + elsif ((s(0) = '0') and (d(0) = d(2))) then + lut4_mux4_o := d(0); + elsif ((s(0) = '1') and (d(1) = d(3))) then + lut4_mux4_o := d(1); + else + lut4_mux4_o := 'X'; + end if; + + return (lut4_mux4_o); + + end function lut4_mux4; + + constant INIT_reg : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT); +begin + + lut_p : process (I0, I1, I2, I3, I4) + variable INIT_reg : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT); + variable I_reg : std_logic_vector(4 downto 0); + begin + + I_reg := TO_STDLOGICVECTOR(I4 & I3 & I2 & I1 & I0); + + if ((I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I4 xor I3 xor I2 xor I1 xor I0) = '0') then + LO <= INIT_reg(SLV_TO_INT(I_reg)); + else + + LO <= lut4_mux4 ( + (lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))), + I_reg(4 downto 3)); + + end if; + end process; +end LUT5_L_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/lut5.vhd,v 1.3 2006/03/11 00:55:40 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 5-input Look-Up-Table with General Output +-- /___/ /\ Filename : LUT5.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:02 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 03/15/05 - Modified to handle the address unknown case. +-- 03/10/06 - Change d to df in function lut4_mux4f and replace TO_INTEGER to +-- SLV_TO_INT. (CR 226842) +-- End Revision + +----- CELL LUT5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity LUT5 is + generic( + INIT : bit_vector := X"00000000" + ); + + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic + ); +end LUT5; + +architecture LUT5_V of LUT5 is + +function lut6_mux8 (d : std_logic_vector(7 downto 0); s : std_logic_vector(2 downto 0)) + return std_logic is + + variable lut6_mux8_o : std_logic; + function lut4_mux4f (df : std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) ) + return std_logic is + + variable lut4_mux4_f : std_logic; + begin + + if (((sf(1) xor sf(0)) = '1') or ((sf(1) xor sf(0)) = '0')) then + lut4_mux4_f := df(SLV_TO_INT(sf)); + elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0' + and (df(0) xor df(2)) = '0') then + lut4_mux4_f := df(0); + elsif ((sf(1) = '0') and (df(0) = df(1))) then + lut4_mux4_f := df(0); + elsif ((sf(1) = '1') and (df(2) = df(3))) then + lut4_mux4_f := df(2); + elsif ((sf(0) = '0') and (df(0) = df(2))) then + lut4_mux4_f := df(0); + elsif ((sf(0) = '1') and (df(1) = df(3))) then + lut4_mux4_f := df(1); + else + lut4_mux4_f := 'X'; + end if; + + return (lut4_mux4_f); + + end function lut4_mux4f; + begin + + if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then + lut6_mux8_o := d(SLV_TO_INT(s)); + else + lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) & + lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2))); + end if; + + return (lut6_mux8_o); + + end function lut6_mux8; + +function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) ) + return std_logic is + + variable lut4_mux4_o : std_logic; + begin + + if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then + lut4_mux4_o := d(SLV_TO_INT(s)); + elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0' + and (d(0) xor d(2)) = '0') then + lut4_mux4_o := d(0); + elsif ((s(1) = '0') and (d(0) = d(1))) then + lut4_mux4_o := d(0); + elsif ((s(1) = '1') and (d(2) = d(3))) then + lut4_mux4_o := d(2); + elsif ((s(0) = '0') and (d(0) = d(2))) then + lut4_mux4_o := d(0); + elsif ((s(0) = '1') and (d(1) = d(3))) then + lut4_mux4_o := d(1); + else + lut4_mux4_o := 'X'; + end if; + + return (lut4_mux4_o); + + end function lut4_mux4; + + constant INIT_reg : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT); +begin + + lut_p : process (I0, I1, I2, I3, I4) + variable I_reg : std_logic_vector(4 downto 0); + begin + + I_reg := TO_STDLOGICVECTOR(I4 & I3 & I2 & I1 & I0); + + if ((I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I4 xor I3 xor I2 xor I1 xor I0) = '0') then + O <= INIT_reg(SLV_TO_INT(I_reg)); + else + + O <= lut4_mux4 ( + (lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))), + I_reg(4 downto 3)); + + end if; + end process; +end LUT5_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/lut6_2.vhd,v 1.1 2006/08/24 00:12:26 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 6-input Look-Up-Table with Two General Outputs +-- /___/ /\ Filename : LUT6_2.vhd +-- \ \ / \ Timestamp : +-- \___\/\___\ +-- +-- Revision: +-- 08/09/06 - Initial version. +-- End Revision + +----- CELL LUT6_2 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity LUT6_2 is + generic( + INIT : bit_vector := X"0000000000000000" + ); + + port( + O5 : out std_ulogic; + O6 : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic + ); +end LUT6_2; + +architecture LUT6_2_V of LUT6_2 is + +function lut6_mux8 (d : std_logic_vector(7 downto 0); s : std_logic_vector(2 downto 0)) + return std_logic is + + variable lut6_mux8_o : std_logic; + function lut4_mux4f (df : std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) ) + return std_logic is + + variable lut4_mux4_f : std_logic; + begin + + if (((sf(1) xor sf(0)) = '1') or ((sf(1) xor sf(0)) = '0')) then + lut4_mux4_f := df(SLV_TO_INT(sf)); + elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0' + and (df(0) xor df(2)) = '0') then + lut4_mux4_f := df(0); + elsif ((sf(1) = '0') and (df(0) = df(1))) then + lut4_mux4_f := df(0); + elsif ((sf(1) = '1') and (df(2) = df(3))) then + lut4_mux4_f := df(2); + elsif ((sf(0) = '0') and (df(0) = df(2))) then + lut4_mux4_f := df(0); + elsif ((sf(0) = '1') and (df(1) = df(3))) then + lut4_mux4_f := df(1); + else + lut4_mux4_f := 'X'; + end if; + + return (lut4_mux4_f); + + end function lut4_mux4f; + begin + + if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then + lut6_mux8_o := d(SLV_TO_INT(s)); + else + lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) & + lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2))); + end if; + + return (lut6_mux8_o); + + end function lut6_mux8; + +function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) ) + return std_logic is + + variable lut4_mux4_o : std_logic; + begin + + if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then + lut4_mux4_o := d(SLV_TO_INT(s)); + elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0' + and (d(0) xor d(2)) = '0') then + lut4_mux4_o := d(0); + elsif ((s(1) = '0') and (d(0) = d(1))) then + lut4_mux4_o := d(0); + elsif ((s(1) = '1') and (d(2) = d(3))) then + lut4_mux4_o := d(2); + elsif ((s(0) = '0') and (d(0) = d(2))) then + lut4_mux4_o := d(0); + elsif ((s(0) = '1') and (d(1) = d(3))) then + lut4_mux4_o := d(1); + else + lut4_mux4_o := 'X'; + end if; + + return (lut4_mux4_o); + + end function lut4_mux4; + + constant INIT_reg : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT); + constant init_l : std_logic_vector(31 downto 0) := INIT_reg(31 downto 0); + constant init_h : std_logic_vector(31 downto 0) := INIT_reg(63 downto 32); +begin + + lut_p : process (I0, I1, I2, I3, I4, I5) + variable I_reg : std_logic_vector(4 downto 0); + variable o_l : std_ulogic; + variable o_h : std_ulogic; + begin + + I_reg := TO_STDLOGICVECTOR(I4 & I3 & I2 & I1 & I0); + + if ((I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I4 xor I3 xor I2 xor I1 xor I0) = '0') then + o_l := init_l(SLV_TO_INT(I_reg)); + o_h := init_h(SLV_TO_INT(I_reg)); + else + o_l := lut4_mux4 ( + (lut6_mux8 ( init_l(31 downto 24), I_reg(2 downto 0)) & + lut6_mux8 ( init_l(23 downto 16), I_reg(2 downto 0)) & + lut6_mux8 ( init_l(15 downto 8), I_reg(2 downto 0)) & + lut6_mux8 ( init_l(7 downto 0), I_reg(2 downto 0))), + I_reg(4 downto 3)); + + o_h := lut4_mux4 ( + (lut6_mux8 ( init_h(31 downto 24), I_reg(2 downto 0)) & + lut6_mux8 ( init_h(23 downto 16), I_reg(2 downto 0)) & + lut6_mux8 ( init_h(15 downto 8), I_reg(2 downto 0)) & + lut6_mux8 ( init_h(7 downto 0), I_reg(2 downto 0))), + I_reg(4 downto 3)); + + end if; + + O5 <= o_l; + if (I5 = '1') then + O6 <= o_h; + elsif (I5 = '0') then + O6 <= o_l; + else + if (o_h = '0' and o_l = '0') then + O6 <= '0'; + elsif (o_h = '1' and o_l = '1') then + O6 <= '1'; + else + O6 <= 'X'; + end if; + end if; + + end process; +end LUT6_2_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/lut6_d.vhd,v 1.5 2006/03/23 18:56:36 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 6-input Look-Up-Table with Dural Output +-- /___/ /\ Filename : lut6_d.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:02 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 03/15/05 - Modified to handle the address unknown case. +-- 03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842) +-- End Revision + +----- CELL LUT6_D ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity LUT6_D is + generic( + INIT : bit_vector := X"0000000000000000" + ); + + port( + LO : out std_ulogic; + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic + ); +end LUT6_D; + +architecture LUT6_D_V of LUT6_D is + +function lut6_mux8 (d : std_logic_vector(7 downto 0); s : std_logic_vector(2 downto 0) ) + return std_logic is + variable lut6_mux8_o : std_logic; + function lut4_mux4f (df : std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) ) + return std_logic is + + variable lut4_mux4_f : std_logic; + begin + + if (((sf(1) xor sf(0)) = '1') or ((sf(1) xor sf(0)) = '0')) then + lut4_mux4_f := df(SLV_TO_INT(sf)); + elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0' + and (df(0) xor df(2)) = '0') then + lut4_mux4_f := df(0); + elsif ((sf(1) = '0') and (df(0) = df(1))) then + lut4_mux4_f := df(0); + elsif ((sf(1) = '1') and (df(2) = df(3))) then + lut4_mux4_f := df(2); + elsif ((sf(0) = '0') and (df(0) = df(2))) then + lut4_mux4_f := df(0); + elsif ((sf(0) = '1') and (df(1) = df(3))) then + lut4_mux4_f := df(1); + else + lut4_mux4_f := 'X'; + end if; + + return (lut4_mux4_f); + + end function lut4_mux4f; + begin + + if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then + lut6_mux8_o := d(SLV_TO_INT(s)); + else + lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) & + lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2))); + end if; + + return (lut6_mux8_o); + + end function lut6_mux8; + + constant INIT_reg : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT); +begin + + lut_p : process (I0, I1, I2, I3, I4, I5) + variable I_reg : std_logic_vector(5 downto 0); + variable O_out : std_ulogic; + begin + + I_reg := TO_STDLOGICVECTOR(I5 & I4 & I3 & I2 & I1 & I0); + + if ((I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '0') then + O_out := INIT_reg(SLV_TO_INT(I_reg)); + else + + O_out := lut6_mux8 ( + (lut6_mux8 ( INIT_reg(63 downto 56), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(55 downto 48), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(47 downto 40), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(39 downto 32), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))), + I_reg(5 downto 3)); + + end if; + O <= O_out; + LO <= O_out; + end process; +end LUT6_D_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/lut6_l.vhd,v 1.5 2006/03/23 18:56:36 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 6-input Look-Up-Table with Local Output +-- /___/ /\ Filename : lut6_l.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:02 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 03/15/05 - Modified to handle the address unknown case. +-- 03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842) +-- End Revision + +----- CELL LUT6_L ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity LUT6_L is + generic( + INIT : bit_vector := X"0000000000000000" + ); + + port( + LO : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic + ); +end LUT6_L; + +architecture LUT6_L_V of LUT6_L is + +function lut6_mux8 (d : std_logic_vector(7 downto 0); s : std_logic_vector(2 downto 0) ) + return std_logic is + variable lut6_mux8_o : std_logic; + function lut4_mux4f (df : std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) ) + return std_logic is + + variable lut4_mux4_f : std_logic; + begin + + if (((sf(1) xor sf(0)) = '1') or ((sf(1) xor sf(0)) = '0')) then + lut4_mux4_f := df(SLV_TO_INT(sf)); + elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0' + and (df(0) xor df(2)) = '0') then + lut4_mux4_f := df(0); + elsif ((sf(1) = '0') and (df(0) = df(1))) then + lut4_mux4_f := df(0); + elsif ((sf(1) = '1') and (df(2) = df(3))) then + lut4_mux4_f := df(2); + elsif ((sf(0) = '0') and (df(0) = df(2))) then + lut4_mux4_f := df(0); + elsif ((sf(0) = '1') and (df(1) = df(3))) then + lut4_mux4_f := df(1); + else + lut4_mux4_f := 'X'; + end if; + + return (lut4_mux4_f); + + end function lut4_mux4f; + + begin + + if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then + lut6_mux8_o := d(SLV_TO_INT(s)); + else + lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) & + lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2))); + end if; + + return (lut6_mux8_o); + + end function lut6_mux8; + + constant INIT_reg : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT); +begin + + lut_p : process (I0, I1, I2, I3, I4, I5) + variable I_reg : std_logic_vector(5 downto 0); + begin + + I_reg := TO_STDLOGICVECTOR(I5 & I4 & I3 & I2 & I1 & I0); + + if ((I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '0') then + LO <= INIT_reg(SLV_TO_INT(I_reg)); + else + + LO <= lut6_mux8 ( + (lut6_mux8 ( INIT_reg(63 downto 56), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(55 downto 48), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(47 downto 40), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(39 downto 32), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))), + I_reg(5 downto 3)); + + end if; + end process; +end LUT6_L_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/lut6.vhd,v 1.6 2006/03/23 18:56:36 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 6-input Look-Up-Table with General Output +-- /___/ /\ Filename : LUT6.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:02 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. +-- 03/15/05 - Modified to handle the address unknown case. +-- 03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842) +-- End Revision + +----- CELL LUT6 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity LUT6 is + generic( + INIT : bit_vector := X"0000000000000000" + ); + + port( + O : out std_ulogic; + + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic + ); +end LUT6; + +architecture LUT6_V of LUT6 is + +function lut6_mux8 (d : std_logic_vector(7 downto 0); s : std_logic_vector(2 downto 0) ) + return std_logic is + variable lut6_mux8_o : std_logic; + function lut4_mux4f (df : std_logic_vector(3 downto 0); sf : std_logic_vector(1 downto 0) ) + return std_logic is + + variable lut4_mux4_f : std_logic; + begin + + if (((sf(1) xor sf(0)) = '1') or ((sf(1) xor sf(0)) = '0')) then + lut4_mux4_f := df(SLV_TO_INT(sf)); + elsif ((df(0) xor df(1)) = '0' and (df(2) xor df(3)) = '0' + and (df(0) xor df(2)) = '0') then + lut4_mux4_f := df(0); + elsif ((sf(1) = '0') and (df(0) = df(1))) then + lut4_mux4_f := df(0); + elsif ((sf(1) = '1') and (df(2) = df(3))) then + lut4_mux4_f := df(2); + elsif ((sf(0) = '0') and (df(0) = df(2))) then + lut4_mux4_f := df(0); + elsif ((sf(0) = '1') and (df(1) = df(3))) then + lut4_mux4_f := df(1); + else + lut4_mux4_f := 'X'; + end if; + + return (lut4_mux4_f); + + end function lut4_mux4f; + begin + + if ((s(2) xor s(1) xor s(0)) = '1' or (s(2) xor s(1) xor s(0)) = '0') then + lut6_mux8_o := d(SLV_TO_INT(s)); + else + lut6_mux8_o := lut4_mux4f(('0' & '0' & lut4_mux4f(d(7 downto 4), s(1 downto 0)) & + lut4_mux4f(d(3 downto 0), s(1 downto 0))), ('0' & s(2))); + end if; + + return (lut6_mux8_o); + + end function lut6_mux8; + + constant INIT_reg : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT); +begin + + lut_p : process (I0, I1, I2, I3, I4, I5) + variable I_reg : std_logic_vector(5 downto 0); + begin + + I_reg := TO_STDLOGICVECTOR(I5 & I4 & I3 & I2 & I1 & I0); + + if ((I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '1' or (I5 xor I4 xor I3 xor I2 xor I1 xor I0) = '0') then + O <= INIT_reg(SLV_TO_INT(I_reg)); + else + + O <= lut6_mux8 ( + (lut6_mux8 ( INIT_reg(63 downto 56), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(55 downto 48), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(47 downto 40), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(39 downto 32), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(31 downto 24), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(23 downto 16), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(15 downto 8), I_reg(2 downto 0)) & + lut6_mux8 ( INIT_reg(7 downto 0), I_reg(2 downto 0))), + I_reg(5 downto 3)); + + end if; + end process; +end LUT6_V; + + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Phase Lock Loop Clock +-- /___/ /\ Filename : PLL_ADV.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:18:19 PST 2004 +-- \___\/\___\ +-- Revision: +-- 07/11/05 - Initial version. +-- 10/14/05 - Add REL pin. +-- 11/16/05 - Add PMCD related generics. +-- 12/02/05 - Change parameter default values. +-- 01/03/06 - Change RST_DEASSER_CLK value to CLKIN1 and CLKFB (BT#735). +-- 01/13/06 - Add DRP and PMCD logic. (CR 222944) +-- 02/17/06 - Add support for -360.0 to +360.0 phase shift. (CR225765) +-- 03/17/96 - Reduce lock time by MD (CR 224502). +-- 07/19/06 - Remove first 4 clkvco_lk cycle generation (CR234931). +-- 08/08/06 - Fix real2int when less than 1 (CR 236219). +-- 08/23/06 - Use clkout_en_tmp to generate clkout_en0. (CR422250) +-- 09/19/06 - Fix real2int with time method and md_product update (CR 424286). +-- 09/27/06 - Add error check for RESET_ON_LOSS_OF_LOCK (CR 425255) +-- - Check rst when generating clkfb_tst (CR 425185). +-- 11/10/06 - Keep 3 digits for real in duty cycle check function. (CR 428703). +-- 01/12/07 - Add CLKOUT_DESKEW_ADJUST parameters (CR 432189). +-- 04/09/07 - Enhance error message for RESET_ON_LOSS_OF_LOCK (CR 437405). +-- 05/22/07 - Add setup check for REL (438781). +-- 06/8/07 - Generate clkfb_tst when GSR=0; Add clkx_edgei after DRP write(CR441293). +-- - Chang VCOCLK_FREQ_MAX and VCOCLK_FREQ_MIN to generic for unisim (BT1485). +-- 06/20/07 - Add CLKFBIN pulse width check (BT1476). +-- 06/28/07 - Initial DRP memory (CR 434042), Error message improve (CR 438250). +-- 08/02/07 - Remove numbers from CLKOUT DESKEW_ADJUST check for unisim (CR443161). +-- 08/21/07 - Not check CLKIN period when PMCD mode set (445101). +-- Fix DUTY_CYCLE_MAX formula in case of divider larger than O_MAX_HT_LT (CR445945). +-- Add warning if phase shift over pll ability (63 vco) (CR446037). +-- 09/20/07 - Seperate fb_delay and delay_edge to handle 0 fb_delay (CR448938) +-- 10/23/07 - Add warnings to initial phase shift calculation (CR448965) +-- 11/01/07 - Remove zero check for CLKOUTx dly register bit15-8 (CR434042) +-- 01/18/08 - Generate vco clk with period_vco/2 as high time and period_vco - high time as +-- low time (CR458475). +-- 03/06/08 - Change max vco freq from 1100Mhz to 1440 Mhz (CR469212). +-- 03/11/08 - Not check clkinsel_in change with RST=0 if clkinsel_in change from X to +-- handle the time 0 X value caused by sdf delay. (CR469589). +-- 03/27/08 - Add period_vco_cmp_cnt and period_vco_md_rm to spread acuminated rounded error +-- of period_vco/2 during M*D CLKIN cycles instead of last cycle. (CR470494). +-- 06/06/08 - Change default values of CLKIN_FREQ_MAX, CLKIN_FREQ_MIN, +-- CLKPFD_FREQ_MIN and REF_CLK_JITTER_MAX (CR469212). +-- 06/23/08 - Assign clkind_ht with clkind_hti when DRP write. +-- Same for clkind_lt. (CR475182) +-- 07/10/08 - Calculate clklt first instead of clkht in clkout_hl_para_drp (CR476560). +-- End Revision + +----- CELL PLL_ADV ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +library STD; +use STD.TEXTIO.all; + + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity PLL_ADV is +generic ( + + BANDWIDTH : string := "OPTIMIZED"; + CLKFBOUT_DESKEW_ADJUST : string := "NONE"; + CLKFBOUT_MULT : integer := 1; + CLKFBOUT_PHASE : real := 0.0; + CLKIN1_PERIOD : real := 0.000; + CLKIN2_PERIOD : real := 0.000; + CLKOUT0_DESKEW_ADJUST : string := "NONE"; + CLKOUT0_DIVIDE : integer := 1; + CLKOUT0_DUTY_CYCLE : real := 0.5; + CLKOUT0_PHASE : real := 0.0; + CLKOUT1_DESKEW_ADJUST : string := "NONE"; + CLKOUT1_DIVIDE : integer := 1; + CLKOUT1_DUTY_CYCLE : real := 0.5; + CLKOUT1_PHASE : real := 0.0; + CLKOUT2_DESKEW_ADJUST : string := "NONE"; + CLKOUT2_DIVIDE : integer := 1; + CLKOUT2_DUTY_CYCLE : real := 0.5; + CLKOUT2_PHASE : real := 0.0; + CLKOUT3_DESKEW_ADJUST : string := "NONE"; + CLKOUT3_DIVIDE : integer := 1; + CLKOUT3_DUTY_CYCLE : real := 0.5; + CLKOUT3_PHASE : real := 0.0; + CLKOUT4_DESKEW_ADJUST : string := "NONE"; + CLKOUT4_DIVIDE : integer := 1; + CLKOUT4_DUTY_CYCLE : real := 0.5; + CLKOUT4_PHASE : real := 0.0; + CLKOUT5_DESKEW_ADJUST : string := "NONE"; + CLKOUT5_DIVIDE : integer := 1; + CLKOUT5_DUTY_CYCLE : real := 0.5; + CLKOUT5_PHASE : real := 0.0; + COMPENSATION : string := "SYSTEM_SYNCHRONOUS"; + DIVCLK_DIVIDE : integer := 1; + EN_REL : boolean := FALSE; + PLL_PMCD_MODE : boolean := FALSE; + REF_JITTER : real := 0.100; + RESET_ON_LOSS_OF_LOCK : boolean := FALSE; + RST_DEASSERT_CLK : string := "CLKIN1" + + ); +port ( + CLKFBDCM : out std_ulogic := '0'; + CLKFBOUT : out std_ulogic := '0'; + CLKOUT0 : out std_ulogic := '0'; + CLKOUT1 : out std_ulogic := '0'; + CLKOUT2 : out std_ulogic := '0'; + CLKOUT3 : out std_ulogic := '0'; + CLKOUT4 : out std_ulogic := '0'; + CLKOUT5 : out std_ulogic := '0'; + CLKOUTDCM0 : out std_ulogic := '0'; + CLKOUTDCM1 : out std_ulogic := '0'; + CLKOUTDCM2 : out std_ulogic := '0'; + CLKOUTDCM3 : out std_ulogic := '0'; + CLKOUTDCM4 : out std_ulogic := '0'; + CLKOUTDCM5 : out std_ulogic := '0'; + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic := '0'; + LOCKED : out std_ulogic := '0'; + CLKFBIN : in std_ulogic; + CLKIN1 : in std_ulogic; + CLKIN2 : in std_ulogic; + CLKINSEL : in std_ulogic; + DADDR : in std_logic_vector(4 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + REL : in std_ulogic; + RST : in std_ulogic + ); +end PLL_ADV; + + +-- Architecture body -- + +architecture PLL_ADV_V of PLL_ADV is + + --------------------------------------------------------------------------- + -- Function SLV_TO_INT converts a std_logic_vector TO INTEGER + --------------------------------------------------------------------------- + function SLV_TO_INT(SLV: in std_logic_vector + ) return integer is + + variable int : integer; + begin + int := 0; + for i in SLV'high downto SLV'low loop + int := int * 2; + if SLV(i) = '1' then + int := int + 1; + end if; + end loop; + return int; + end; + + --------------------------------------------------------------------------- + -- Function ADDR_IS_VALID checks for the validity of the argument. A FALSE + -- is returned if any argument bit is other than a '0' or '1'. + --------------------------------------------------------------------------- + function ADDR_IS_VALID ( + SLV : in std_logic_vector + ) return boolean is + + variable IS_VALID : boolean := TRUE; + + begin + for I in SLV'high downto SLV'low loop + if (SLV(I) /= '0' AND SLV(I) /= '1') then + IS_VALID := FALSE; + end if; + end loop; + return IS_VALID; + end ADDR_IS_VALID; + + function int2real( int_in : in integer) return real is + variable conline1 : line; + variable rl_value : real; + variable tmpv1 : real; + variable tmpv2 : real := 1.0; + variable tmpi : integer; + begin + tmpi := int_in; + write (conline1, tmpi); + write (conline1, string'(".0 ")); + write (conline1, tmpv2); + read (conline1, tmpv1); + rl_value := tmpv1; + return rl_value; + DEALLOCATE(conline1); + end int2real; + + function real2int( real_in : in real) return integer is + variable int_value : integer; + variable int_value1 : integer; + variable tmps : time := 1 ps; + variable tmps1 : real; + + begin + if (real_in < 1.00000 and real_in > -1.00000) then + int_value1 := 0; + else + tmps := real_in * 1 ns; + int_value := tmps / 1 ns; + tmps1 := int2real (int_value); + if ( tmps1 > real_in) then + int_value1 := int_value - 1 ; + else + int_value1 := int_value; + end if; + end if; + return int_value1; + end real2int; + + + procedure clkout_dly_cal (clkout_dly : out std_logic_vector(5 downto 0); + clkpm_sel : out std_logic_vector(2 downto 0); + clkdiv : in integer; + clk_ps : in real; + clk_ps_name : in string ) + is + variable clk_dly_rl : real; + variable clk_dly_rem : real; + variable clk_dly_int : integer; + variable clk_dly_int_rl : real; + variable clkdiv_real : real; + variable clkpm_sel_rl : real; + variable clk_ps_rl : real; + variable Message : line; + begin + + clkdiv_real := int2real(clkdiv); + if (clk_ps < 0.0) then + clk_dly_rl := (360.0 + clk_ps) * clkdiv_real / 360.0; + else + clk_dly_rl := clk_ps * clkdiv_real / 360.0; + end if; + clk_dly_int := real2int (clk_dly_rl); + + if (clk_dly_int > 63) then + Write ( Message, string'(" Warning : Attribute ")); + Write ( Message, clk_ps_name ); + Write ( Message, string'(" of PLL_ADV is set to ")); + Write ( Message, clk_ps); + Write ( Message, string'(". Required phase shifting can not be reached since it is over the maximum phase shifting ability of PLL_ADV")); + Write ( Message, '.' & LF ); + assert false report Message.all severity error; + DEALLOCATE (Message); + clkout_dly := "111111"; + else + clkout_dly := STD_LOGIC_VECTOR(TO_UNSIGNED(clk_dly_int, 6)); + end if; + + clk_dly_int_rl := int2real (clk_dly_int); + clk_dly_rem := clk_dly_rl - clk_dly_int_rl; + + if (clk_dly_rem < 0.125) then + clkpm_sel := "000"; + clkpm_sel_rl := 0.0; + elsif (clk_dly_rem >= 0.125 and clk_dly_rem < 0.25) then + clkpm_sel(2 downto 0) := "001"; + clkpm_sel_rl := 1.0; + elsif (clk_dly_rem >= 0.25 and clk_dly_rem < 0.375) then + clkpm_sel := "010"; + clkpm_sel_rl := 2.0; + elsif (clk_dly_rem >= 0.375 and clk_dly_rem < 0.5) then + clkpm_sel := "011"; + clkpm_sel_rl := 3.0; + elsif (clk_dly_rem >= 0.5 and clk_dly_rem < 0.625) then + clkpm_sel := "100"; + clkpm_sel_rl := 4.0; + elsif (clk_dly_rem >= 0.625 and clk_dly_rem < 0.75) then + clkpm_sel := "101"; + clkpm_sel_rl := 5.0; + elsif (clk_dly_rem >= 0.75 and clk_dly_rem < 0.875) then + clkpm_sel := "110"; + clkpm_sel_rl := 6.0; + elsif (clk_dly_rem >= 0.875 ) then + clkpm_sel := "111"; + clkpm_sel_rl := 7.0; + end if; + + if (clk_ps < 0.0) then + clk_ps_rl := (clk_dly_int_rl + 0.125 * clkpm_sel_rl) * 360.0 / clkdiv_real - 360.0; + else + clk_ps_rl := (clk_dly_int_rl + 0.125 * clkpm_sel_rl) * 360.0 / clkdiv_real; + end if; + + if (((clk_ps_rl- clk_ps) > 0.001) or ((clk_ps_rl- clk_ps) < -0.001)) then + Write ( Message, string'(" Warning : Attribute ")); + Write ( Message, clk_ps_name ); + Write ( Message, string'(" of PLL_ADV is set to ")); + Write ( Message, clk_ps); + Write ( Message, string'(". Real phase shifting is ")); + Write ( Message, clk_ps_rl); + Write ( Message, string'(". Required phase shifting can not be reached")); + Write ( Message, '.' & LF ); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + end procedure clkout_dly_cal; + +procedure clk_out_para_cal (clk_ht : out std_logic_vector(6 downto 0); + clk_lt : out std_logic_vector(6 downto 0); + clk_nocnt : out std_ulogic; + clk_edge : out std_ulogic; + CLKOUT_DIVIDE : in integer; + CLKOUT_DUTY_CYCLE : in real ) + is + variable tmp_value : real; + variable tmp_value0 : real; + variable tmp_value_l: real; + variable tmp_value2 : real; + variable tmp_value1 : integer; + variable clk_lt_tmp : real; + variable clk_ht_i : integer; + variable clk_lt_i : integer; + variable CLKOUT_DIVIDE_real : real; + constant O_MAX_HT_LT_real : real := 64.0; + begin + CLKOUT_DIVIDE_real := int2real(CLKOUT_DIVIDE); + tmp_value := CLKOUT_DIVIDE_real * CLKOUT_DUTY_CYCLE; + tmp_value0 := tmp_value * 2.0; + tmp_value1 := real2int(tmp_value0) mod 2; + tmp_value2 := CLKOUT_DIVIDE_real - tmp_value; + + if ((tmp_value) >= O_MAX_HT_LT_real) then + clk_lt_tmp := 64.0; + clk_lt := "1000000"; + else + if (tmp_value < 1.0) then + clk_lt := "0000001"; + clk_lt_tmp := 1.0; + else + if (tmp_value1 /= 0) then + clk_lt_i := real2int(tmp_value) + 1; + else + clk_lt_i := real2int(tmp_value); + end if; + clk_lt := STD_LOGIC_VECTOR(TO_UNSIGNED(clk_lt_i, 7)); + clk_lt_tmp := int2real(clk_lt_i); + end if; + end if; + + tmp_value_l := CLKOUT_DIVIDE_real - clk_lt_tmp; + + if ( tmp_value_l >= O_MAX_HT_LT_real) then + clk_ht := "1000000"; + else + clk_ht_i := real2int(tmp_value_l); + clk_ht := STD_LOGIC_VECTOR(TO_UNSIGNED(clk_ht_i, 7)); + end if; + + if (CLKOUT_DIVIDE = 1) then + clk_nocnt := '1'; + else + clk_nocnt := '0'; + end if; + + if (tmp_value < 1.0) then + clk_edge := '1'; + elsif (tmp_value1 /= 0) then + clk_edge := '1'; + else + clk_edge := '0'; + end if; + + end procedure clk_out_para_cal; + + procedure clkout_pm_cal ( clk_ht1 : out integer ; + clk_div : out integer; + clk_div1 : out integer; + clk_ht : in std_logic_vector(6 downto 0); + clk_lt : in std_logic_vector(6 downto 0); + clk_nocnt : in std_ulogic; + clk_edge : in std_ulogic ) + is + variable clk_div_tmp : integer; + begin + if (clk_nocnt = '1') then + clk_div := 1; + clk_div1 := 1; + clk_ht1 := 1; + else + if (clk_edge = '1') then + clk_ht1 := 2 * SLV_TO_INT(clk_ht) + 1; + else + clk_ht1 := 2 * SLV_TO_INT(clk_ht); + end if; + clk_div_tmp := SLV_TO_INT(clk_ht) + SLV_TO_INT(clk_lt); + clk_div := clk_div_tmp; + clk_div1 := 2 * clk_div_tmp - 1; + end if; + + end procedure clkout_pm_cal; + + procedure clkout_delay_para_drp ( clkout_dly : out std_logic_vector(5 downto 0); + clk_nocnt : out std_ulogic; + clk_edge : out std_ulogic; + di_in : in std_logic_vector(15 downto 0); + daddr_in : in std_logic_vector(4 downto 0); + di_str : string ( 1 to 16); + daddr_str : string ( 1 to 5)) + is + variable Message : line; + begin + clkout_dly := di_in(5 downto 0); + clk_nocnt := di_in(6); + clk_edge := di_in(7); + end procedure clkout_delay_para_drp; + +procedure clkout_hl_para_drp ( clk_lt : out std_logic_vector(6 downto 0) ; + clk_ht : out std_logic_vector(6 downto 0) ; + clkpm_sel : out std_logic_vector(2 downto 0) ; + di_in : in std_logic_vector(15 downto 0); + daddr_in : in std_logic_vector(4 downto 0); + di_str : string ( 1 to 16); + daddr_str : string ( 1 to 5)) + is + variable Message : line; + begin + if (di_in(12) /= '1') then + Write ( Message, string'(" Error : PLL_ADV input DI(15 downto 0) is set to")); + Write ( Message, di_str); + Write ( Message, string'(" at address DADDR = ")); + Write ( Message, daddr_str ); + Write ( Message, string'(". The bit 12 need to be set to 1.")); + Write ( Message, '.' & LF ); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + + if ( di_in(5 downto 0) = "000000") then + clk_lt := "1000000"; + else + clk_lt := ( '0' & di_in(5 downto 0)); + end if; + if ( di_in(11 downto 6) = "000000") then + clk_ht := "1000000"; + else + clk_ht := ( '0' & di_in(11 downto 6)); + end if; + clkpm_sel := di_in(15 downto 13); +end procedure clkout_hl_para_drp; + + function clkout_duty_chk (CLKOUT_DIVIDE : in integer; + CLKOUT_DUTY_CYCLE : in real; + CLKOUT_DUTY_CYCLE_N : in string) + return std_ulogic is + constant O_MAX_HT_LT_real : real := 64.0; + variable CLKOUT_DIVIDE_real : real; + variable CLK_DUTY_CYCLE_MIN : real; + variable CLK_DUTY_CYCLE_MIN_rnd : real; + variable CLK_DUTY_CYCLE_MAX : real; + variable CLK_DUTY_CYCLE_STEP : real; + variable clk_duty_tmp_int : integer; + variable duty_cycle_valid : std_ulogic; + variable tmp_duty_value : real; + variable tmp_j : real; + variable Message : line; + variable step_round_tmp : integer; + variable step_round_tmp1 : real; + + begin + CLKOUT_DIVIDE_real := int2real(CLKOUT_DIVIDE); + step_round_tmp := 1000 /CLKOUT_DIVIDE; + step_round_tmp1 := int2real(step_round_tmp); + if (CLKOUT_DIVIDE_real > O_MAX_HT_LT_real) then + CLK_DUTY_CYCLE_MIN := (CLKOUT_DIVIDE_real - O_MAX_HT_LT_real)/CLKOUT_DIVIDE_real; + CLK_DUTY_CYCLE_MAX := (O_MAX_HT_LT_real + 0.5)/CLKOUT_DIVIDE_real; + CLK_DUTY_CYCLE_MIN_rnd := CLK_DUTY_CYCLE_MIN; + else + if (CLKOUT_DIVIDE = 1) then + CLK_DUTY_CYCLE_MIN_rnd := 0.0; + CLK_DUTY_CYCLE_MIN := 0.0; + else + CLK_DUTY_CYCLE_MIN_rnd := step_round_tmp1 / 1000.00; + CLK_DUTY_CYCLE_MIN := 1.0 / CLKOUT_DIVIDE_real; + end if; + CLK_DUTY_CYCLE_MAX := 1.0; + end if; + + if ((CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_MAX) or (CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd)) then + Write ( Message, string'(" Attribute Syntax Warning : ")); + Write ( Message, CLKOUT_DUTY_CYCLE_N); + Write ( Message, string'(" is set to ")); + Write ( Message, CLKOUT_DUTY_CYCLE); + Write ( Message, string'(" and is not in the allowed range ")); + Write ( Message, CLK_DUTY_CYCLE_MIN); + Write ( Message, string'(" to ")); + Write ( Message, CLK_DUTY_CYCLE_MAX); + Write ( Message, '.' & LF ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + end if; + + CLK_DUTY_CYCLE_STEP := 0.5 / CLKOUT_DIVIDE_real; + tmp_j := 0.0; + duty_cycle_valid := '0'; + clk_duty_tmp_int := 0; + for j in 0 to (2 * CLKOUT_DIVIDE ) loop + tmp_duty_value := CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * tmp_j; + if (abs(tmp_duty_value - CLKOUT_DUTY_CYCLE) < 0.001 and (tmp_duty_value <= CLK_DUTY_CYCLE_MAX)) then + duty_cycle_valid := '1'; + end if; + tmp_j := tmp_j + 1.0; + end loop; + + if (duty_cycle_valid /= '1') then + Write ( Message, string'(" Attribute Syntax Warning : ")); + Write ( Message, CLKOUT_DUTY_CYCLE_N); + Write ( Message, string'(" = ")); + Write ( Message, CLKOUT_DUTY_CYCLE); + Write ( Message, string'(" which is not an allowed value. Allowed value s are: ")); + Write ( Message, LF ); + tmp_j := 0.0; + for j in 0 to (2 * CLKOUT_DIVIDE ) loop + tmp_duty_value := CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * tmp_j; + if ( (tmp_duty_value <= CLK_DUTY_CYCLE_MAX) and (tmp_duty_value < 1.0)) then + Write ( Message, tmp_duty_value); + Write ( Message, LF ); + end if; + tmp_j := tmp_j + 1.0; + end loop; + assert false report Message.all severity warning; + DEALLOCATE (Message); + end if; + return duty_cycle_valid; + end function clkout_duty_chk; + +-- Input/Output Pin signals + + constant VCOCLK_FREQ_MAX : real := 1440.0; + constant VCOCLK_FREQ_MIN : real := 400.0; + constant VCOCLK_FREQ_TARGET : real := 800.0; + constant CLKIN_FREQ_MAX : real := 710.0; + constant CLKIN_FREQ_MIN : real := 19.0; + constant CLKPFD_FREQ_MAX : real := 550.0; + constant CLKPFD_FREQ_MIN : real := 19.0; + constant O_MAX_HT_LT : integer := 64; + constant REF_CLK_JITTER_MAX : time := 1000 ps; + constant REF_CLK_JITTER_SCALE : real := 0.1; + constant MAX_FEEDBACK_DELAY : time := 10 ns; + constant MAX_FEEDBACK_DELAY_SCALE : real := 1.0; + + constant PLL_LOCK_TIME : integer := 7; + + signal CLKIN1_ipd : std_ulogic; + signal CLKIN2_ipd : std_ulogic; + signal CLKFBIN_ipd : std_ulogic; + signal RST_ipd : std_ulogic; + signal REL_ipd : std_ulogic; + signal CLKINSEL_ipd : std_ulogic; + signal DADDR_ipd : std_logic_vector(4 downto 0); + signal DI_ipd : std_logic_vector(15 downto 0); + signal DWE_ipd : std_ulogic; + signal DEN_ipd : std_ulogic; + signal DCLK_ipd : std_ulogic; + signal GSR : std_ulogic := '0'; + signal CLKOUT0_out : std_ulogic := '0'; + signal CLKOUT1_out : std_ulogic := '0'; + signal CLKOUT2_out : std_ulogic := '0'; + signal CLKOUT3_out : std_ulogic := '0'; + signal CLKOUT4_out : std_ulogic := '0'; + signal CLKOUT5_out : std_ulogic := '0'; + signal CLKFBOUT_out : std_ulogic := '0'; + signal LOCKED_out : std_ulogic := '0'; + signal do_out : std_logic_vector(15 downto 0); + signal DRDY_out : std_ulogic := '0'; + signal CLKIN1_dly : std_ulogic; + signal CLKIN2_dly : std_ulogic; + signal CLKFBIN_dly : std_ulogic; + signal RST_dly : std_ulogic; + signal REL_dly : std_ulogic; + signal CLKINSEL_dly : std_ulogic; + signal DADDR_dly : std_logic_vector(4 downto 0); + signal DI_dly : std_logic_vector(15 downto 0); + signal DWE_dly : std_ulogic; + signal DEN_dly : std_ulogic; + signal DCLK_dly : std_ulogic; + + signal di_in : std_logic_vector (15 downto 0); + signal dwe_in : std_ulogic := '0'; + signal den_in : std_ulogic := '0'; + signal dclk_in : std_ulogic := '0'; + signal rst_in : std_ulogic := '0'; + signal rst_input : std_ulogic := '0'; + signal rel_in : std_ulogic := '0'; + signal clkfb_in : std_ulogic := '0'; + signal clkin1_in : std_ulogic := '0'; + signal clkin1_in_dly : std_ulogic := '0'; + signal clkin2_in : std_ulogic := '0'; + signal clkinsel_in : std_ulogic := '0'; + signal clkinsel_tmp : std_ulogic := '0'; + signal daddr_in : std_logic_vector(4 downto 0); + signal daddr_in_lat : integer := 0; + signal drp_lock : std_ulogic := '0'; + signal drp_lock1 : std_ulogic := '0'; + type drp_array is array (31 downto 0) of std_logic_vector(15 downto 0); + signal dr_sram : drp_array; + + signal clk0in : std_ulogic := '0'; + signal clk1in : std_ulogic := '0'; + signal clk2in : std_ulogic := '0'; + signal clk3in : std_ulogic := '0'; + signal clk4in : std_ulogic := '0'; + signal clk5in : std_ulogic := '0'; + signal clkfbm1in : std_ulogic := '0'; + signal clk0_out : std_ulogic := '0'; + signal clk1_out : std_ulogic := '0'; + signal clk2_out : std_ulogic := '0'; + signal clk3_out : std_ulogic := '0'; + signal clk4_out : std_ulogic := '0'; + signal clk5_out : std_ulogic := '0'; + signal clkfb_out : std_ulogic := '0'; + signal clkfbm1_out : std_ulogic := '0'; + signal clkout_en : std_ulogic := '0'; + signal clkout_en1 : std_ulogic := '0'; + signal clkout_en0 : std_ulogic := '0'; + signal clkout_en0_tmp : std_ulogic := '0'; + signal clkout_cnt : integer := 0; + signal clkin_cnt : integer := 0; + signal clkin_lock_cnt : integer := 0; + signal clkout_en_time : integer := PLL_LOCK_TIME + 2; + signal locked_en_time : integer := 0; + signal lock_cnt_max : integer := 0; + signal clkvco_lk : std_ulogic := '0'; + signal clkvco_lk_rst : std_ulogic := '0'; + signal clkvco_free : std_ulogic := '0'; + signal clkvco : std_ulogic := '0'; + signal fbclk_tmp : std_ulogic := '0'; + + signal rst_in1 : std_ulogic := '0'; + signal rst_unlock : std_ulogic := '0'; + signal rst_on_loss : std_ulogic := '0'; + signal rst_edge : time := 0 ps; + signal rst_ht : time := 0 ps; + signal fb_delay_found : std_ulogic := '0'; + signal fb_delay_found_tmp : std_ulogic := '0'; + signal clkfb_tst : std_ulogic := '0'; + constant fb_delay_max : time := MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE; + signal fb_delay : time := 0 ps; + signal clkvco_delay : time := 0 ps; + signal val_tmp : time := 0 ps; + signal clkin_edge : time := 0 ps; + signal delay_edge : time := 0 ps; + + type real_array_usr is array (4 downto 0) of time; + signal clkin_period : real_array_usr := (others => 2.0 ns); + signal period_vco : time := 0.000 ns; + signal period_vco_rm : integer := 0; + signal period_vco_cmp_cnt : integer := 0; + signal clkvco_tm_cnt : integer := 0; + signal period_vco_cmp_flag : integer := 0; + signal period_vco1 : time := 0.000 ns; + signal period_vco2 : time := 0.000 ns; + signal period_vco3 : time := 0.000 ns; + signal period_vco4 : time := 0.000 ns; + signal period_vco5 : time := 0.000 ns; + signal period_vco6 : time := 0.000 ns; + signal period_vco7 : time := 0.000 ns; + signal period_vco_half : time := 0.000 ns; + signal period_vco_half1 : time := 0.000 ns; + signal period_vco_half_rm : time := 0.000 ns; + constant period_vco_max : time := 1 ns * 1000 / VCOCLK_FREQ_MIN; + constant period_vco_min : time := 1 ns * 1000 / VCOCLK_FREQ_MAX; + constant period_vco_target : time := 1 ns * 1000 / VCOCLK_FREQ_TARGET; + constant period_vco_target_half : time := 1 ns * 500 / VCOCLK_FREQ_TARGET; + signal period_fb : time := 0.000 ns; + signal period_avg : time := 0.000 ns; + + signal clkvco_freq_init_chk : real := 0.0; + signal clkfb_stop_max : integer := 3; + signal clkin_stop_max : integer := DIVCLK_DIVIDE + 1; + signal md_product : integer := CLKFBOUT_MULT * DIVCLK_DIVIDE; + signal m_product : integer := CLKFBOUT_MULT; + signal m_product2 : integer := CLKFBOUT_MULT / 2; + + signal pll_locked_delay : time := 0 ps; + signal clkin_dly_t : time := 0 ps; + signal clkfb_dly_t : time := 0 ps; + signal clkpll : std_ulogic := '0'; + signal clkpll_dly : std_ulogic := '0'; + signal clkfb_in_dly : std_ulogic := '0'; + signal pll_unlock : std_ulogic := '0'; + signal pll_locked_tm : std_ulogic := '0'; + signal pll_locked_tmp1 : std_ulogic := '0'; + signal pll_locked_tmp2 : std_ulogic := '0'; + signal lock_period : std_ulogic := '0'; + signal pll_lock_tm: std_ulogic := '0'; + signal unlock_recover : std_ulogic := '0'; + signal clkin_stopped : std_ulogic := '0'; + signal clkin_stopped_p : std_ulogic := '0'; + signal clkin_stopped_n : std_ulogic := '0'; + signal clkstop_cnt_p : integer := 0; + signal clkstop_cnt_n : integer := 0; + signal clkfbstop_cnt_p : integer := 0; + signal clkfbstop_cnt_n : integer := 0; + signal clkfb_stopped : std_ulogic := '0'; + signal clkfb_stopped_p : std_ulogic := '0'; + signal clkfb_stopped_n : std_ulogic := '0'; + signal clkpll_jitter_unlock : std_ulogic := '0'; + signal clkin_jit : time := 0 ps; + constant ref_jitter_max_tmp : time := REF_CLK_JITTER_MAX; + + signal clka1_out : std_ulogic := '0'; + signal clkb1_out : std_ulogic := '0'; + signal clka1d2_out : std_ulogic := '0'; + signal clka1d4_out : std_ulogic := '0'; + signal clka1d8_out : std_ulogic := '0'; + signal clkdiv_rel_rst : std_ulogic := '0'; + signal qrel_o_reg1 : std_ulogic := '0'; + signal qrel_o_reg2 : std_ulogic := '0'; + signal qrel_o_reg3 : std_ulogic := '0'; + signal rel_o_mux_sel : std_ulogic := '0'; + signal pmcd_mode : std_ulogic := '0'; + signal rel_rst_o : std_ulogic := '0'; + signal rel_o_mux_clk : std_ulogic := '0'; + signal rel_o_mux_clk_tmp : std_ulogic := '0'; + signal clka1_in : std_ulogic := '0'; + signal clkb1_in : std_ulogic := '0'; + signal clkout0_out_out : std_ulogic := '0'; + signal clkout1_out_out : std_ulogic := '0'; + signal clkout2_out_out : std_ulogic := '0'; + signal clkout3_out_out : std_ulogic := '0'; + signal clkout4_out_out : std_ulogic := '0'; + signal clkout5_out_out : std_ulogic := '0'; + signal clkfbout_out_out : std_ulogic := '0'; + signal clk0ps_en : std_ulogic := '0'; + signal clk1ps_en : std_ulogic := '0'; + signal clk2ps_en : std_ulogic := '0'; + signal clk3ps_en : std_ulogic := '0'; + signal clk4ps_en : std_ulogic := '0'; + signal clk5ps_en : std_ulogic := '0'; + signal clkfbm1ps_en : std_ulogic := '0'; + signal clkout_mux : std_logic_vector (7 downto 0) := X"00"; + signal clk0pm_sel : integer := 0; + signal clk1pm_sel : integer := 0; + signal clk2pm_sel : integer := 0; + signal clk3pm_sel : integer := 0; + signal clk4pm_sel : integer := 0; + signal clk5pm_sel : integer := 0; + signal clkfbm1pm_sel : integer := 0; + signal clkfbm1pm_rl : real := 0.0; + signal clk0_edge : std_ulogic := '0'; + signal clk1_edge : std_ulogic := '0'; + signal clk2_edge : std_ulogic := '0'; + signal clk3_edge : std_ulogic := '0'; + signal clk4_edge : std_ulogic := '0'; + signal clk5_edge : std_ulogic := '0'; + signal clkfbm1_edge : std_ulogic := '0'; + signal clkind_edge : std_ulogic := '0'; + signal clk0_nocnt : std_ulogic := '0'; + signal clk1_nocnt : std_ulogic := '0'; + signal clk2_nocnt : std_ulogic := '0'; + signal clk3_nocnt : std_ulogic := '0'; + signal clk4_nocnt : std_ulogic := '0'; + signal clk5_nocnt : std_ulogic := '0'; + signal clkfbm1_nocnt : std_ulogic := '0'; + signal clkind_nocnt : std_ulogic := '0'; + signal clk0_dly_cnt : integer := 0; + signal clk1_dly_cnt : integer := 0; + signal clk2_dly_cnt : integer := 0; + signal clk3_dly_cnt : integer := 0; + signal clk4_dly_cnt : integer := 0; + signal clk5_dly_cnt : integer := 0; + signal clkfbm1_dly_cnt : integer := 0; + signal clk0_ht : std_logic_vector (6 downto 0) := "0000000"; + signal clk1_ht : std_logic_vector (6 downto 0) := "0000000"; + signal clk2_ht : std_logic_vector (6 downto 0) := "0000000"; + signal clk3_ht : std_logic_vector (6 downto 0) := "0000000"; + signal clk4_ht : std_logic_vector (6 downto 0) := "0000000"; + signal clk5_ht : std_logic_vector (6 downto 0) := "0000000"; + signal clkfbm1_ht : std_logic_vector (6 downto 0) := "0000000"; + signal clk0_lt : std_logic_vector (6 downto 0) := "0000000"; + signal clk1_lt : std_logic_vector (6 downto 0) := "0000000"; + signal clk2_lt : std_logic_vector (6 downto 0) := "0000000"; + signal clk3_lt : std_logic_vector (6 downto 0) := "0000000"; + signal clk4_lt : std_logic_vector (6 downto 0) := "0000000"; + signal clk5_lt : std_logic_vector (6 downto 0) := "0000000"; + signal clkfbm1_lt : std_logic_vector (6 downto 0) := "0000000"; + signal clkout0_dly : integer := 0; + signal clkout1_dly : integer := 0; + signal clkout2_dly : integer := 0; + signal clkout3_dly : integer := 0; + signal clkout4_dly : integer := 0; + signal clkout5_dly : integer := 0; + signal clkfbm1_dly : integer := 0; + signal clkind_ht : std_logic_vector (6 downto 0) := "0000000"; + signal clkind_lt : std_logic_vector (6 downto 0) := "0000000"; + signal clk0_ht1 : integer := 0; + signal clk1_ht1 : integer := 0; + signal clk2_ht1 : integer := 0; + signal clk3_ht1 : integer := 0; + signal clk4_ht1 : integer := 0; + signal clk5_ht1 : integer := 0; + signal clkfbm1_ht1 : integer := 0; + signal clk0_cnt : integer := 0; + signal clk1_cnt : integer := 0; + signal clk2_cnt : integer := 0; + signal clk3_cnt : integer := 0; + signal clk4_cnt : integer := 0; + signal clk5_cnt : integer := 0; + signal clkfbm1_cnt : integer := 0; + signal clk0_div : integer := 0; + signal clk1_div : integer := 0; + signal clk2_div : integer := 0; + signal clk3_div : integer := 0; + signal clk4_div : integer := 0; + signal clk5_div : integer := 0; + signal clkfbm1_div : integer := 1; + signal clk0_div1 : integer := 0; + signal clk1_div1 : integer := 0; + signal clk2_div1 : integer := 0; + signal clk3_div1 : integer := 0; + signal clk4_div1 : integer := 0; + signal clk5_div1 : integer := 0; + signal clkfbm1_div1 : integer := 0; + signal clkind_div : integer := 0; + +begin + + CLKOUT0 <= clkout0_out_out; + CLKOUT1 <= clkout1_out_out; + CLKOUT2 <= clkout2_out_out; + CLKOUT3 <= clkout3_out_out; + CLKOUT4 <= clkout4_out_out; + CLKOUT5 <= clkout5_out_out; + CLKFBOUT <= clkfbout_out_out; + CLKOUTDCM0 <= clkout0_out_out; + CLKOUTDCM1 <= clkout1_out_out; + CLKOUTDCM2 <= clkout2_out_out; + CLKOUTDCM3 <= clkout3_out_out; + CLKOUTDCM4 <= clkout4_out_out; + CLKOUTDCM5 <= clkout5_out_out; + CLKFBDCM <= clkfbout_out_out; + + DO <= do_out(15 downto 0); + DRDY <= DRDY_out; + LOCKED <= locked_out; + + clkin1_in <= CLKIN1; + clkin2_in <= CLKIN2; + clkinsel_in <= CLKINSEL; + clkfb_in <= CLKFBIN; + rst_input <= RST; + rel_in <= REL; + clkin1_in_dly <= CLKIN1; + daddr_in(4 downto 0) <= DADDR(4 downto 0); + di_in(15 downto 0) <= DI(15 downto 0); + dwe_in <= DWE; + den_in <= DEN; + dclk_in <= DCLK; + + INIPROC : process + variable Message : line; + variable con_line : line; + variable tmpvalue : real; + variable chk_ok : std_ulogic; + variable tmp_string : string(1 to 18); + variable skipspace : character; + variable CLK_DUTY_CYCLE_MIN : real; + variable CLK_DUTY_CYCLE_MAX : real; + variable CLK_DUTY_CYCLE_STEP : real; + variable O_MAX_HT_LT_real : real; + variable duty_cycle_valid : std_ulogic; + variable CLKOUT0_DIVIDE_real : real; + variable CLKOUT1_DIVIDE_real : real; + variable CLKOUT2_DIVIDE_real : real; + variable CLKOUT3_DIVIDE_real : real; + variable CLKOUT4_DIVIDE_real : real; + variable CLKOUT5_DIVIDE_real : real; + variable tmp_j : real; + variable tmp_duty_value : real; + variable clk_ht_i : std_logic_vector(5 downto 0); + variable clk_lt_i : std_logic_vector(5 downto 0); + variable clk_nocnt_i : std_ulogic; + variable clk_edge_i : std_ulogic; + begin + if((COMPENSATION /= "INTERNAL") and (COMPENSATION /= "internal") and + (COMPENSATION /= "EXTERNAL") and (COMPENSATION /= "external") and + (COMPENSATION /= "SYSTEM_SYNCHRONOUS") and (COMPENSATION /= "system_synchronous") and + (COMPENSATION /= "SOURCE_SYNCHRONOUS") and (COMPENSATION /= "source_synchronous") and + (COMPENSATION /= "DCM2PLL") and (COMPENSATION /= "dcm2pll") and + (COMPENSATION /= "PLL2DCM") and (COMPENSATION /= "pll2dcm")) then + assert FALSE report "Attribute Syntax Error : COMPENSATION is not INTERNAL, EXTERNAL, SYSTEM_SYNCHRONOUS, SOURCE_SYNCHRONOUS , DCM2PLL, PLL2DCM." severity error; + end if; + + if((BANDWIDTH /= "HIGH") and (BANDWIDTH /= "high") and + (BANDWIDTH /= "LOW") and (BANDWIDTH /= "low") and + (BANDWIDTH /= "OPTIMIZED") and (BANDWIDTH /= "optimized")) then + assert FALSE report "Attribute Syntax Error : BANDWIDTH is not HIGH, LOW, OPTIMIZED." severity error; + end if; + + if ((CLKOUT0_DESKEW_ADJUST /= "NONE") and (CLKOUT0_DESKEW_ADJUST /= "none") + and (CLKOUT0_DESKEW_ADJUST /= "PPC") and (CLKOUT0_DESKEW_ADJUST /= "ppc") + ) then + assert FALSE report "Error : CLKOUT0_DESKEW_ADJUST is not NONE or PPC." severity error; + end if; + + if ((CLKOUT1_DESKEW_ADJUST /= "NONE") and (CLKOUT1_DESKEW_ADJUST /= "none") + and (CLKOUT1_DESKEW_ADJUST /= "PPC") and (CLKOUT1_DESKEW_ADJUST /= "ppc") + ) then + assert FALSE report "Error : CLKOUT1_DESKEW_ADJUST is not NONE or PPC." severity error; + end if; + + if ((CLKOUT2_DESKEW_ADJUST /= "NONE") and (CLKOUT2_DESKEW_ADJUST /= "none") + and (CLKOUT2_DESKEW_ADJUST /= "PPC") and (CLKOUT2_DESKEW_ADJUST /= "ppc") + ) then + assert FALSE report "Error : CLKOUT2_DESKEW_ADJUST is not NONE or PPC." severity error; + end if; + + if ((CLKOUT3_DESKEW_ADJUST /= "NONE") and (CLKOUT3_DESKEW_ADJUST /= "none") + and (CLKOUT3_DESKEW_ADJUST /= "PPC") and (CLKOUT3_DESKEW_ADJUST /= "ppc") + ) then + assert FALSE report "Error : CLKOUT3_DESKEW_ADJUST is not NONE or PPC." severity error; + end if; + + if ((CLKOUT4_DESKEW_ADJUST /= "NONE") and (CLKOUT4_DESKEW_ADJUST /= "none") + and (CLKOUT4_DESKEW_ADJUST /= "PPC") and (CLKOUT4_DESKEW_ADJUST /= "ppc") + ) then + assert FALSE report "Error : CLKOUT4_DESKEW_ADJUST is not NONE or PPC." severity error; + end if; + + if ((CLKOUT5_DESKEW_ADJUST /= "NONE") and (CLKOUT5_DESKEW_ADJUST /= "none") + and (CLKOUT5_DESKEW_ADJUST /= "PPC") and (CLKOUT5_DESKEW_ADJUST /= "ppc") + ) then + assert FALSE report "Error : CLKOUT5_DESKEW_ADJUST is not NONE or PPC." severity error; + end if; + + if ((CLKFBOUT_DESKEW_ADJUST /= "NONE") and (CLKFBOUT_DESKEW_ADJUST /= "none") + and (CLKFBOUT_DESKEW_ADJUST /= "PPC") and (CLKFBOUT_DESKEW_ADJUST /= "ppc") + ) then + assert FALSE report "Error : CLKFBOUT_DESKEW_ADJUST is not NONE or PPC." severity error; + end if; + + case PLL_PMCD_MODE is + when TRUE => pmcd_mode <= '1'; + when FALSE => pmcd_mode <= '0'; + when others => assert FALSE report "Attribute Syntax Error : PLL_PMCD_MODE is not TRUE or FALSE." severity error; + end case; + + case CLKOUT0_DIVIDE is + when 1 to 128 => NULL ; + when others => assert FALSE report "Attribute Syntax Error : CLKOUT0_DIVIDE is not in range 1...128." severity error; + end case; + + if ((CLKOUT0_PHASE < -360.0) or (CLKOUT0_PHASE > 360.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT0_PHASE is not in range -360.0 to 360.0" severity error; + elsif (pmcd_mode = '1' and CLKOUT0_PHASE /= 0.0) then + assert FALSE report "Attribute Syntax Error : CLKOUT0_PHASE need set to 0.0 when attribute PLL_PMCD_MODE is set to TRUE." severity error; + end if; + + if ((CLKOUT0_DUTY_CYCLE < 0.0) or (CLKOUT0_DUTY_CYCLE > 1.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT0_DUTY_CYCLE is not real in range 0.0 to 1.0 pecentage."severity error; + elsif (pmcd_mode = '1' and CLKOUT0_DUTY_CYCLE /= 0.5) then + assert FALSE report "Attribute Syntax Error : CLKOUT0_DUTY_CYCLE need set to 0.5 when attribute PLL_PMCD_MODE is set to TRUE." severity error; + end if; + + case CLKOUT1_DIVIDE is + when 1 to 128 => NULL ; + when others => assert FALSE report "Attribute Syntax Error : CLKOUT1_DIVIDE is not in range 1...128." severity error; + end case; + + if ((CLKOUT1_PHASE < -360.0) or (CLKOUT1_PHASE > 360.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT1_PHASE is not in range -360.0 to 360.0" severity error; + elsif (pmcd_mode = '1' and CLKOUT1_PHASE /= 0.0) then + assert FALSE report "Attribute Syntax Error : CLKOUT1_PHASE need set to 0.0 when attribute PLL_PMCD_MODE is set to TRUE." severity error; + end if; + + if ((CLKOUT1_DUTY_CYCLE < 0.0) or (CLKOUT1_DUTY_CYCLE > 1.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT1_DUTY_CYCLE is not real in range 0.0 to 1.0 pecentage."severity error; + elsif (pmcd_mode = '1' and CLKOUT1_DUTY_CYCLE /= 0.5) then + assert FALSE report "Attribute Syntax Error : CLKOUT1_DUTY_CYCLE need set to 0.5 when attribute PLL_PMCD_MODE is set to TRUE." severity error; + end if; + + case CLKOUT2_DIVIDE is + when 1 to 128 => NULL ; + when others => assert FALSE report "Attribute Syntax Error : CLKOUT2_DIVIDE is not in range 1...128." severity error; + end case; + + if ((CLKOUT2_PHASE < -360.0) or (CLKOUT2_PHASE > 360.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT2_PHASE is not in range -360.0 to 360.0" severity error; + elsif (pmcd_mode = '1' and CLKOUT2_PHASE /= 0.0) then + assert FALSE report "Attribute Syntax Error : CLKOUT2_PHASE need set to 0.0 when attribute PLL_PMCD_MODE is set to TRUE." severity error; + end if; + + if ((CLKOUT2_DUTY_CYCLE < 0.0) or (CLKOUT2_DUTY_CYCLE > 1.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT2_DUTY_CYCLE is not real in range 0.0 to 1.0 pecentage."severity error; + elsif (pmcd_mode = '1' and CLKOUT2_DUTY_CYCLE /= 0.5) then + assert FALSE report "Attribute Syntax Error : CLKOUT2_DUTY_CYCLE need set to 0.5 when attribute PLL_PMCD_MODE is set to TRUE." severity error; + end if; + + + case CLKOUT3_DIVIDE is + when 1 to 128 => NULL ; + when others => assert FALSE report "Attribute Syntax Error : CLKOUT3_DIVIDE is not in range 1...128." severity error; + end case; + + if ((CLKOUT3_PHASE < -360.0) or (CLKOUT3_PHASE > 360.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT3_PHASE is not in range -360.0 to 360.0" severity error; + elsif (pmcd_mode = '1' and CLKOUT3_PHASE /= 0.0) then + assert FALSE report "Attribute Syntax Error : CLKOUT3_PHASE need set to 0.0 when attribute PLL_PMCD_MODE is set to TRUE." severity error; + end if; + + if ((CLKOUT3_DUTY_CYCLE < 0.0) or (CLKOUT3_DUTY_CYCLE > 1.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT3_DUTY_CYCLE is not real in range 0.0 to 1.0 pecentage."severity error; + elsif (pmcd_mode = '1' and CLKOUT3_DUTY_CYCLE /= 0.5) then + assert FALSE report "Attribute Syntax Error : CLKOUT3_DUTY_CYCLE need set to 0.5 when attribute PLL_PMCD_MODE is set to TRUE." severity error; + end if; + + + case CLKOUT4_DIVIDE is + when 1 to 128 => NULL ; + when others => assert FALSE report "Attribute Syntax Error : CLKOUT4_DIVIDE is not in range 1...128." severity error; + end case; + + if ((CLKOUT4_PHASE < -360.0) or (CLKOUT4_PHASE > 360.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT4_PHASE is not in range -360.0 to 360.0" severity error; + end if; + + if ((CLKOUT4_DUTY_CYCLE < 0.0) or (CLKOUT4_DUTY_CYCLE > 1.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT4_DUTY_CYCLE is not real in range 0.0 to 1.0 pecentage."severity error; + end if; + + case CLKOUT5_DIVIDE is + when 1 to 128 => NULL ; + when others => assert FALSE report "Attribute Syntax Error : CLKOUT5_DIVIDE is not in range 1...128." severity error; + end case; + + if ((CLKOUT5_PHASE < -360.0) or (CLKOUT5_PHASE > 360.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT5_PHASE is not in range 360.0 to 360.0" severity error; + end if; + + if ((CLKOUT5_DUTY_CYCLE < 0.0) or (CLKOUT5_DUTY_CYCLE > 1.0)) then + assert FALSE report "Attribute Syntax Error : CLKOUT5_DUTY_CYCLE is not real in range 0.0 to 1.0 pecentage."severity error; + end if; + + + case CLKFBOUT_MULT is + when 1 to 74 => NULL; + when others => assert FALSE report "Attribute Syntax Error : CLKFBOUT_MULT is not in range 1...74." severity error; + end case; + + if ( CLKFBOUT_PHASE < -360.0 or CLKFBOUT_PHASE > 360.0 ) then + assert FALSE report "Attribute Syntax Error : CLKFBOUT_PHASE is not in range -360.0 to 360.0" severity error; + elsif (pmcd_mode = '1' and CLKFBOUT_PHASE /= 0.0) then + assert FALSE report "Attribute Syntax Error : CLKFBOUT_PHASE need set to 0.0 when attribute PLL_PMCD_MODE is set to TRUE." severity error; + end if; + + case DIVCLK_DIVIDE is + when 1 to 52 => NULL; + + when others => assert FALSE report "Attribute Syntax Error : DIVCLK_DIVIDE is not in range 1...52." severity error; + end case; + + if ((REF_JITTER < 0.0) or (REF_JITTER > 0.999)) then + assert FALSE report "Attribute Syntax Error : REF_JITTER is not in range 0.0 ... 1.0." severity error; + end if; + + if (((CLKIN1_PERIOD < 1.0) or (CLKIN1_PERIOD > 52.630)) and (pmcd_mode = '0') and (CLKINSEL = '1')) then + assert FALSE report "Attribute Syntax Error : CLKIN1_PERIOD is not in range 1.0 ... 52.630" severity error; + end if; + + if (((CLKIN2_PERIOD < 1.0) or (CLKIN2_PERIOD > 52.630)) and (pmcd_mode = '0') and (CLKINSEL = '0')) then + assert FALSE report "Attribute Syntax Error : CLKIN2_PERIOD is not in range 1.0 ... 52.630" severity error; + end if; + + case RESET_ON_LOSS_OF_LOCK is + when FALSE => rst_on_loss <= '0'; +-- when TRUE => rst_on_loss <= '1'; + when others => assert FALSE report " Attribute Syntax Error : generic RESET_ON_LOSS_OF_LOCK must be set to FALSE for PLL_ADV to function correctly. Please correct the setting for the attribute and re-run the simulation." severity error; + end case; + + write (con_line, O_MAX_HT_LT); + write (con_line, string'(".0 ")); + write (con_line, CLKOUT0_DIVIDE); + write (con_line, string'(".0 ")); + write (con_line, CLKOUT1_DIVIDE); + write (con_line, string'(".0 ")); + write (con_line, CLKOUT2_DIVIDE); + write (con_line, string'(".0 ")); + write (con_line, CLKOUT3_DIVIDE); + write (con_line, string'(".0 ")); + write (con_line, CLKOUT4_DIVIDE); + write (con_line, string'(".0 ")); + write (con_line, CLKOUT5_DIVIDE); + write (con_line, string'(".0 ")); + read (con_line, tmpvalue); + O_MAX_HT_LT_real := tmpvalue; + read (con_line, skipspace); + read (con_line, tmpvalue); + CLKOUT0_DIVIDE_real := tmpvalue; + read (con_line, skipspace); + read (con_line, tmpvalue); + CLKOUT1_DIVIDE_real := tmpvalue; + read (con_line, skipspace); + read (con_line, tmpvalue); + CLKOUT2_DIVIDE_real := tmpvalue; + read (con_line, skipspace); + read (con_line, tmpvalue); + CLKOUT3_DIVIDE_real := tmpvalue; + read (con_line, skipspace); + read (con_line, tmpvalue); + CLKOUT4_DIVIDE_real := tmpvalue; + read (con_line, skipspace); + read (con_line, tmpvalue); + CLKOUT5_DIVIDE_real := tmpvalue; + DEALLOCATE (con_line); + + chk_ok := clkout_duty_chk (CLKOUT0_DIVIDE, CLKOUT0_DUTY_CYCLE, "CLKOUT0_DUTY_CYCLE"); + chk_ok := clkout_duty_chk (CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE, "CLKOUT1_DUTY_CYCLE"); + chk_ok := clkout_duty_chk (CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE, "CLKOUT2_DUTY_CYCLE"); + chk_ok := clkout_duty_chk (CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE, "CLKOUT3_DUTY_CYCLE"); + chk_ok := clkout_duty_chk (CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE, "CLKOUT4_DUTY_CYCLE"); + chk_ok := clkout_duty_chk (CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE, "CLKOUT5_DUTY_CYCLE"); + + locked_en_time <= md_product + clkout_en_time + 2; + lock_cnt_max <= md_product + clkout_en_time + 6 + 2; + +--------PMCD -------------- + + if (RST_DEASSERT_CLK = "CLKIN1") then + rel_o_mux_sel <= '1'; + elsif (RST_DEASSERT_CLK = "CLKFBIN") then + rel_o_mux_sel <= '0'; + else + assert false report "Attribute Syntax Error : The attribute RST_DEASSERT_CLK on PLL_ADV should be CLKIN1 or CLKFBIN." severity error; + end if; + + case EN_REL is + when FALSE => clkdiv_rel_rst <= '0'; + when TRUE => clkdiv_rel_rst <= '1'; + when others => assert false report "Attribute Syntax Error : The attribute EN_REL on PLL_ADV should be TRUE or FALSE." severity error; + end case; + + wait; + end process INIPROC; + + +-- +-- PMCD function +-- + +-- *** Clocks MUX +-- rel_o_mux_clk_tmp <= clkin1_in when rel_o_mux_sel = '1' else clkfb_in; + rel_o_mux_clk_tmp <= clkin1_in_dly when rel_o_mux_sel = '1' else clkfb_in; + rel_o_mux_clk <= rel_o_mux_clk_tmp when (pmcd_mode = '1') else '0'; + clka1_in <= clkin1_in when (pmcd_mode = '1') else '0'; + clkb1_in <= clkfb_in when (pmcd_mode = '1') else '0'; + +--*** Rel and Rst + rel_rst_P : process(rel_o_mux_clk, rst_input) + begin + if (rst_input = '1') then + qrel_o_reg1 <= '1'; + qrel_o_reg2 <= '1'; + else + if (rising_edge(rel_o_mux_clk)) then + qrel_o_reg1 <= '0'; + end if; + + if (falling_edge(rel_o_mux_clk)) then + qrel_o_reg2 <= qrel_o_reg1; + end if; + end if; + end process; + + qrel_o_reg3_P : process ( rel_in, rst_input) + begin + if (rst_input = '1') then + qrel_o_reg3 <= '1'; + elsif (rising_edge(rel_in)) then + qrel_o_reg3 <= '0'; + end if; + end process; + + rel_rst_o <= (qrel_o_reg3 or qrel_o_reg1) when clkdiv_rel_rst = '1' else qrel_o_reg1; + +--*** CLKA + clka1_out_P : process (clka1_in, qrel_o_reg2) + begin + if (qrel_o_reg2 = '1') then + clka1_out <= '0'; + elsif (qrel_o_reg2 = '0') then + clka1_out <= clka1_in; + end if; + end process; + +---** CLKB + clkb1_out_P : process (clkb1_in, qrel_o_reg2) + begin + if (qrel_o_reg2 = '1') then + clkb1_out <= '0'; + elsif (qrel_o_reg2 = '0') then + clkb1_out <= clkb1_in; + end if; + end process; + +--*** Clock divider + clka1d2_out_P : process(clka1_in, rel_rst_o) + begin + if (rel_rst_o = '1') then + clka1d2_out <= '0'; + elsif (rising_edge(clka1_in)) then + clka1d2_out <= not clka1d2_out; + end if; + end process; + + clka1d4_out_P : process (clka1d2_out, rel_rst_o) + begin + if (rel_rst_o = '1') then + clka1d4_out <= '0'; + elsif (rising_edge(clka1d2_out)) then + clka1d4_out <= not clka1d4_out; + end if; + end process; + + clka1d8_out_P : process (clka1d4_out, rel_rst_o) + begin + if (rel_rst_o = '1') then + clka1d8_out <= '0'; + elsif (rising_edge(clka1d4_out)) then + clka1d8_out <= not clka1d8_out; + end if; + end process; + + clkout5_out_out <= '0' when (pmcd_mode = '1') else clkout5_out; + clkout4_out_out <= '0' when (pmcd_mode = '1') else clkout4_out; + clkout3_out_out <= clka1_out when (pmcd_mode = '1') else clkout3_out; + clkout2_out_out <= clka1d2_out when (pmcd_mode = '1') else clkout2_out; + clkout1_out_out <= clka1d4_out when (pmcd_mode = '1') else clkout1_out; + clkout0_out_out <= clka1d8_out when (pmcd_mode = '1') else clkout0_out; + clkfbout_out_out <= clkb1_out when (pmcd_mode = '1') else clkfb_out; + +-- +-- PLL function start +-- + + clkinsel_tmp <= clkinsel_in after 1 ps; + + clkinsel_p : process + variable period_clkin : real; + variable clkvco_freq_init_chk : real; + variable Message : line; + variable tmpreal1 : real; + variable tmpreal2 : real; + begin + if (NOW > 1 ps and rst_in = '0' and (clkinsel_tmp = '0' or clkinsel_tmp = '1')) then + assert false report + "Input Error : PLL input clock can only be switched when RST=1. CLKINSEL is changed when RST low, should be changed at RST high." + severity error; + end if; + + if (NOW = 0 ps) then + wait for 1 ps; + end if; + + if ( clkinsel_in='1') then + period_clkin := CLKIN1_PERIOD; + else + period_clkin := CLKIN2_PERIOD; + end if; + + tmpreal1 := int2real(CLKFBOUT_MULT); + tmpreal2 := int2real(DIVCLK_DIVIDE); + clkvco_freq_init_chk := (tmpreal1 / ( period_clkin * tmpreal2)) * 1000.0; + + if ((clkvco_freq_init_chk > VCOCLK_FREQ_MAX) or (clkvco_freq_init_chk < VCOCLK_FREQ_MIN)) then + Write ( Message, string'(" Attribute Syntax Error : The calculation of VCO frequency=")); + Write ( Message, clkvco_freq_init_chk); + Write ( Message, string'(" Mhz. This exceeds the permitted VCO frequency range of ")); + Write ( Message, VCOCLK_FREQ_MIN); + Write ( Message, string'(" MHz to ")); + Write ( Message, VCOCLK_FREQ_MAX); + Write ( Message, string'(" MHz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT / (DIVCLK_DIVIDE * CLKIN_PERIOD).")); + Write ( Message, string'(" Please adjust the attributes to the permitted VCO frequency range.")); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + + wait on clkinsel_in; + end process; + + clkpll <= clkin1_in when clkinsel_in = '1' else clkin2_in; + + RST_SYNC_P : process (clkpll, rst_input) + begin + if (rst_input = '1') then + rst_in1 <= '1'; + elsif (rising_edge (clkpll)) then + rst_in1 <= rst_input; + end if; + end process; + + rst_in <= rst_in1 or rst_unlock; + + RST_ON_LOSS_P : process (pll_unlock) + begin + if (rising_edge(pll_unlock)) then + if (rst_on_loss = '1' and locked_out = '1') then + rst_unlock <= '1', '0' after 10 ns; + end if; + end if; + end process; + + RST_PW_P : process (rst_input) + variable rst_edge : time := 0 ps; + variable rst_ht : time := 0 ps; + begin + if (rising_edge(rst_input)) then + rst_edge := NOW; + elsif (falling_edge(rst_input)) then + rst_ht := NOW - rst_edge; + if (rst_ht < 10 ns and rst_ht > 0 ps) then + assert false report + "Input Error : RST must be asserted at least for 10 ns." + severity error; + end if; + end if; + end process; + +---- +---- DRP port read and write +---- + + do_out <= dr_sram(daddr_in_lat); + + DRP_PROC : process + variable address : integer; + variable valid_daddr : boolean := false; + variable Message : line; + variable di_str : string (1 to 16); + variable daddr_str : string ( 1 to 5); + variable first_time : boolean := true; + variable clk_ht : std_logic_vector (6 downto 0); + variable tmp_ht : std_logic_vector (6 downto 0); + variable clk_lt : std_logic_vector (6 downto 0); + variable tmp_lt : std_logic_vector (6 downto 0); + variable clk_nocnt : std_ulogic; + variable clk_edge : std_ulogic; + variable clkout_dly : std_logic_vector (5 downto 0); + variable clkpm_sel : std_logic_vector (2 downto 0); + variable tmpx : std_logic_vector (7 downto 0); + variable clk0_hti : std_logic_vector (6 downto 0); + variable clk1_hti : std_logic_vector (6 downto 0); + variable clk2_hti : std_logic_vector (6 downto 0); + variable clk3_hti : std_logic_vector (6 downto 0); + variable clk4_hti : std_logic_vector (6 downto 0); + variable clk5_hti : std_logic_vector (6 downto 0); + variable clkfbm1_hti : std_logic_vector (6 downto 0); + variable clk0_lti : std_logic_vector (6 downto 0); + variable clk1_lti : std_logic_vector (6 downto 0); + variable clk2_lti : std_logic_vector (6 downto 0); + variable clk3_lti : std_logic_vector (6 downto 0); + variable clk4_lti : std_logic_vector (6 downto 0); + variable clk5_lti : std_logic_vector (6 downto 0); + variable clkfbm1_lti : std_logic_vector (6 downto 0); + variable clk0_nocnti : std_ulogic; + variable clk1_nocnti : std_ulogic; + variable clk2_nocnti : std_ulogic; + variable clk3_nocnti : std_ulogic; + variable clk4_nocnti : std_ulogic; + variable clk5_nocnti : std_ulogic; + variable clkfbm1_nocnti : std_ulogic; + variable clk0_edgei : std_ulogic; + variable clk1_edgei : std_ulogic; + variable clk2_edgei : std_ulogic; + variable clk3_edgei : std_ulogic; + variable clk4_edgei : std_ulogic; + variable clk5_edgei : std_ulogic; + variable clkfbm1_edgei : std_ulogic; + variable clkout0_dlyi : std_logic_vector (5 downto 0); + variable clkout1_dlyi : std_logic_vector (5 downto 0); + variable clkout2_dlyi : std_logic_vector (5 downto 0); + variable clkout3_dlyi : std_logic_vector (5 downto 0); + variable clkout4_dlyi : std_logic_vector (5 downto 0); + variable clkout5_dlyi : std_logic_vector (5 downto 0); + variable clkfbm1_dlyi : std_logic_vector (5 downto 0); + variable clk0pm_seli : std_logic_vector (2 downto 0); + variable clk1pm_seli : std_logic_vector (2 downto 0); + variable clk2pm_seli : std_logic_vector (2 downto 0); + variable clk3pm_seli : std_logic_vector (2 downto 0); + variable clk4pm_seli : std_logic_vector (2 downto 0); + variable clk5pm_seli : std_logic_vector (2 downto 0); + variable clkfbm1pm_seli : std_logic_vector (2 downto 0); + variable clk_ht1 : integer; + variable clk_div : integer; + variable clk_div1 : integer; + variable clkind_hti : std_logic_vector (6 downto 0); + variable clkind_lti : std_logic_vector (6 downto 0); + variable clkind_nocnti : std_ulogic; + variable clkind_edgei : std_ulogic; + variable pll_cp : std_logic_vector (3 downto 0); + variable pll_res : std_logic_vector (3 downto 0); + variable pll_lfhf : std_logic_vector (1 downto 0); + variable pll_cpres : std_logic_vector (1 downto 0) := "01"; + variable tmpadd : std_logic_vector (4 downto 0); + begin + + if (first_time = true) then + clk_out_para_cal (clk_ht, clk_lt, clk_nocnt, clk_edge, CLKOUT0_DIVIDE, CLKOUT0_DUTY_CYCLE); + clk0_hti := clk_ht; + clk0_lti := clk_lt; + clk0_nocnti := clk_nocnt; + clk0_edgei := clk_edge; + clk0_ht <= clk0_hti; + clk0_lt <= clk0_lti; + clk0_nocnt <= clk0_nocnti; + clk0_edge <= clk0_edgei; + + clk_out_para_cal (clk_ht, clk_lt, clk_nocnt, clk_edge, CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE); + clk1_hti := clk_ht; + clk1_lti := clk_lt; + clk1_nocnti := clk_nocnt; + clk1_edgei := clk_edge; + clk1_ht <= clk1_hti; + clk1_lt <= clk1_lti; + clk1_nocnt <= clk1_nocnti; + clk1_edge <= clk1_edgei; + + clk_out_para_cal (clk_ht, clk_lt, clk_nocnt, clk_edge, CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE); + clk2_hti := clk_ht; + clk2_lti := clk_lt; + clk2_nocnti := clk_nocnt; + clk2_edgei := clk_edge; + clk2_ht <= clk2_hti; + clk2_lt <= clk2_lti; + clk2_nocnt <= clk2_nocnti; + clk2_edge <= clk2_edgei; + + clk_out_para_cal (clk_ht, clk_lt, clk_nocnt, clk_edge, CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE); + clk3_hti := clk_ht; + clk3_lti := clk_lt; + clk3_nocnti := clk_nocnt; + clk3_edgei := clk_edge; + clk3_ht <= clk3_hti; + clk3_lt <= clk3_lti; + clk3_nocnt <= clk3_nocnti; + clk3_edge <= clk3_edgei; + + clk_out_para_cal (clk_ht, clk_lt, clk_nocnt, clk_edge, CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE); + clk4_hti := clk_ht; + clk4_lti := clk_lt; + clk4_nocnti := clk_nocnt; + clk4_edgei := clk_edge; + clk4_ht <= clk4_hti; + clk4_lt <= clk4_lti; + clk4_nocnt <= clk4_nocnti; + clk4_edge <= clk4_edgei; + + clk_out_para_cal (clk_ht, clk_lt, clk_nocnt, clk_edge, CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE); + clk5_hti := clk_ht; + clk5_lti := clk_lt; + clk5_nocnti := clk_nocnt; + clk5_edgei := clk_edge; + clk5_ht <= clk5_hti; + clk5_lt <= clk5_lti; + clk5_nocnt <= clk5_nocnti; + clk5_edge <= clk5_edgei; + + clk_out_para_cal (clk_ht, clk_lt, clk_nocnt, clk_edge, CLKFBOUT_MULT, 0.50); + clkfbm1_hti := clk_ht; + clkfbm1_lti := clk_lt; + clkfbm1_nocnti := clk_nocnt; + clkfbm1_edgei := clk_edge; + clkfbm1_ht <= clkfbm1_hti; + clkfbm1_lt <= clkfbm1_lti; + clkfbm1_nocnt <= clkfbm1_nocnti; + clkfbm1_edge <= clkfbm1_edgei; + + clk_out_para_cal (clk_ht, clk_lt, clk_nocnt, clk_edge, DIVCLK_DIVIDE, 0.50); + clkind_hti := clk_ht; + clkind_lti := clk_lt; + clkind_nocnti := clk_nocnt; + clkind_edgei := clk_edge; + clkind_ht <= clkind_hti; + clkind_lt <= clkind_lti; + + clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk0_hti, clk0_lti, clk0_nocnti, clk0_edgei); + clk0_ht1 <= clk_ht1; + clk0_div <= clk_div; + clk0_div1 <= clk_div1; + clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk1_hti, clk1_lti, clk1_nocnti, clk1_edgei); + clk1_ht1 <= clk_ht1; + clk1_div <= clk_div; + clk1_div1 <= clk_div1; + clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk2_hti, clk2_lti, clk2_nocnti, clk2_edgei); + clk2_ht1 <= clk_ht1; + clk2_div <= clk_div; + clk2_div1 <= clk_div1; + clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk3_hti, clk3_lti, clk3_nocnti, clk3_edgei); + clk3_ht1 <= clk_ht1; + clk3_div <= clk_div; + clk3_div1 <= clk_div1; + clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk4_hti, clk4_lti, clk4_nocnti, clk4_edgei); + clk4_ht1 <= clk_ht1; + clk4_div <= clk_div; + clk4_div1 <= clk_div1; + clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk5_hti, clk5_lti, clk5_nocnti, clk5_edgei); + clk5_ht1 <= clk_ht1; + clk5_div <= clk_div; + clk5_div1 <= clk_div1; + clkout_pm_cal(clk_ht1, clk_div, clk_div1, clkfbm1_hti, clkfbm1_lti, clkfbm1_nocnti, clkfbm1_edgei); + clkfbm1_ht1 <= clk_ht1; + clkfbm1_div <= clk_div; + clkfbm1_div1 <= clk_div1; + clkout_pm_cal(clk_ht1, clk_div, clk_div1, clkind_hti, clkind_lti, clkind_nocnti, '0'); + clkind_div <= clk_div; + + clkout_dly_cal (clkout_dly, clkpm_sel, CLKOUT0_DIVIDE, CLKOUT0_PHASE, "CLKOUT0_PHASE"); + clkout0_dly <= SLV_TO_INT(clkout_dly); + clk0pm_sel <= SLV_TO_INT(clkpm_sel); + clkout0_dlyi := clkout_dly; + clk0pm_seli := clkpm_sel; + + clkout_dly_cal (clkout_dly, clkpm_sel, CLKOUT1_DIVIDE, CLKOUT1_PHASE, "CLKOUT1_PHASE"); + clkout1_dly <= SLV_TO_INT(clkout_dly); + clk1pm_sel <= SLV_TO_INT(clkpm_sel); + clkout1_dlyi := clkout_dly; + clk1pm_seli := clkpm_sel; + + clkout_dly_cal (clkout_dly, clkpm_sel, CLKOUT2_DIVIDE, CLKOUT2_PHASE, "CLKOUT2_PHASE"); + clkout2_dly <= SLV_TO_INT(clkout_dly); + clk2pm_sel <= SLV_TO_INT(clkpm_sel); + clkout2_dlyi := clkout_dly; + clk2pm_seli := clkpm_sel; + clkout_dly_cal (clkout_dly, clkpm_sel, CLKOUT3_DIVIDE, CLKOUT3_PHASE, "CLKOUT3_PHASE"); + clkout3_dly <= SLV_TO_INT(clkout_dly); + clk3pm_sel <= SLV_TO_INT(clkpm_sel); + clkout3_dlyi := clkout_dly; + clk3pm_seli := clkpm_sel; + clkout_dly_cal (clkout_dly, clkpm_sel, CLKOUT4_DIVIDE, CLKOUT4_PHASE, "CLKOUT4_PHASE"); + clkout4_dly <= SLV_TO_INT(clkout_dly); + clk4pm_sel <= SLV_TO_INT(clkpm_sel); + clkout4_dlyi := clkout_dly; + clk4pm_seli := clkpm_sel; + clkout_dly_cal (clkout_dly, clkpm_sel, CLKOUT5_DIVIDE, CLKOUT5_PHASE, "CLKOUT5_PHASE"); + clkout5_dly <= SLV_TO_INT(clkout_dly); + clk5pm_sel <= SLV_TO_INT(clkpm_sel); + clkout5_dlyi := clkout_dly; + clk5pm_seli := clkpm_sel; + clkout_dly_cal (clkout_dly, clkpm_sel, CLKFBOUT_MULT, CLKFBOUT_PHASE, "CLKFBOUT_PHASE"); + clkfbm1_dly <= SLV_TO_INT(clkout_dly); + clkfbm1pm_sel <= SLV_TO_INT(clkpm_sel); + clkfbm1_dlyi := clkout_dly; + clkfbm1pm_seli := clkpm_sel; + + case CLKFBOUT_MULT is +when 1 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1101"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0101"; pll_res := "1111"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0101"; pll_res := "1111"; pll_lfhf := "11"; end if; +when 2 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1110"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "1111"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1110"; pll_res := "1111"; pll_lfhf := "11"; end if; +when 3 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0110"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "0111"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0110"; pll_res := "0101"; pll_lfhf := "11"; end if; +when 4 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1101"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0111"; pll_res := "1001"; pll_lfhf := "11"; end if; +when 5 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "0101"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1101"; pll_res := "1001"; pll_lfhf := "11"; end if; +when 6 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "0101"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0111"; pll_res := "0001"; pll_lfhf := "11"; end if; +when 7 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1001"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1100"; pll_res := "0001"; pll_lfhf := "11"; end if; +when 8 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1110"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1111"; pll_res := "1110"; pll_lfhf := "11"; end if; +when 9 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1110"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1110"; pll_res := "0001"; pll_lfhf := "11"; end if; +when 10 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "0001"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1111"; pll_res := "0001"; pll_lfhf := "11"; end if; +when 11 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "0001"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1101"; pll_res := "0110"; pll_lfhf := "11"; end if; +when 12 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "0110"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1110"; pll_res := "0110"; pll_lfhf := "11"; end if; +when 13 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "0110"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1110"; pll_res := "0110"; pll_lfhf := "11"; end if; +when 14 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "0110"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1111"; pll_res := "0110"; pll_lfhf := "11"; end if; +when 15 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "1010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1110"; pll_res := "1010"; pll_lfhf := "11"; end if; +when 16 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "1010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1110"; pll_res := "1010"; pll_lfhf := "11"; end if; +when 17 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1111"; pll_res := "1010"; pll_lfhf := "11"; end if; +when 18 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1111"; pll_res := "1010"; pll_lfhf := "11"; end if; +when 19 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1111"; pll_res := "1010"; pll_lfhf := "11"; end if;when 20 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1100"; pll_res := "1100"; pll_lfhf := "11"; end if; +when 21 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1100"; pll_res := "1100"; pll_lfhf := "11"; end if; +when 22 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1101"; pll_res := "1100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1101"; pll_res := "1100"; pll_lfhf := "11"; end if; +when 23 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1101"; pll_res := "1100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1101"; pll_res := "1100"; pll_lfhf := "11"; end if; +when 24 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1101"; pll_res := "1100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0111"; pll_res := "0010"; pll_lfhf := "11"; end if; +when 25 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "1100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1110"; pll_res := "1100"; pll_lfhf := "11"; end if; +when 26 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "1100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1110"; pll_res := "1100"; pll_lfhf := "11"; end if; +when 27 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1111"; pll_res := "1100"; pll_lfhf := "11"; end if; +when 28 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "1100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1100"; pll_res := "0010"; pll_lfhf := "11"; end if; +when 29 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "1100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1100"; pll_res := "0010"; pll_lfhf := "11"; end if; +when 30 => if (BANDWIDTH = "LOW") then pll_cp := "0001"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1110"; pll_res := "1100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1100"; pll_res := "0010"; pll_lfhf := "11"; end if; +when 31 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1100"; pll_res := "0010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1100"; pll_res := "0010"; pll_lfhf := "11"; end if; +when 32 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1100"; pll_res := "0010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "1100"; pll_res := "0010"; pll_lfhf := "11"; end if; +when 33 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "1111"; pll_res := "1010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; end if; +when 34 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0111"; pll_res := "0010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; end if; +when 35 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0111"; pll_res := "0010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; end if; +when 36 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0111"; pll_res := "0010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; end if; +when 37 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0110"; pll_res := "0010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; end if; +when 38 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0110"; pll_res := "0010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; end if;when 39 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; end if; +when 40 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0011"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 41 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0011"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 42 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0011"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 43 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0011"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 44 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0100"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0011"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 45 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0011"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 46 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0011"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 47 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0101"; pll_res := "0010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 48 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0101"; pll_res := "0010"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 49 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 50 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 51 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 52 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 53 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 54 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 55 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11"; end if; +when 56 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0011"; pll_res := "0100"; pll_lfhf := "11"; end if; +when 57 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if;when 58 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 59 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 60 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 61 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 62 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 63 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if; +when 64 => if (BANDWIDTH = "LOW") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "HIGH") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; + elsif (BANDWIDTH = "OPTIMIZED") then pll_cp := "0010"; pll_res := "1000"; pll_lfhf := "11"; end if; +when others => NULL; + end case; + + tmpx := ('X' & 'X' & 'X' & 'X' & 'X' & 'X' & 'X' & 'X' ); + tmpadd := "11100"; + address := slv_to_int(tmpadd); + dr_sram(address) <= (tmpx(7 downto 0) & clk0_edgei & clk0_nocnti & clkout0_dlyi(5 downto 0)); + tmpadd := "11011"; + address := slv_to_int(tmpadd); + dr_sram(address) <= (clk0pm_seli(2 downto 0) & '1' & clk0_hti(5 downto 0) & clk0_lti(5 downto 0)); + tmpadd := "11010"; + address := slv_to_int(tmpadd); + dr_sram(address) <= (tmpx(7 downto 0) & clk1_edgei & clk1_nocnti & clkout1_dlyi(5 downto 0)); + tmpadd := "11001"; + address := slv_to_int(tmpadd); + dr_sram(address) <= (clk1pm_seli(2 downto 0) & '1' & clk1_hti(5 downto 0) & clk1_lti(5 downto 0)); + tmpadd := "10111"; + address := slv_to_int(tmpadd); + dr_sram(address) <= (tmpx(7 downto 0) & clk2_edgei & clk2_nocnti & clkout2_dlyi(5 downto 0)); + tmpadd := "10110"; + address := slv_to_int(tmpadd); + dr_sram(address) <= (clk2pm_seli(2 downto 0) & '1' & clk2_hti(5 downto 0) & clk2_lti(5 downto 0)); + tmpadd := "10101"; + address := slv_to_int(tmpadd); + dr_sram(address) <= (tmpx(7 downto 0) & clk3_edgei & clk3_nocnti & clkout3_dlyi(5 downto 0)); + tmpadd := "10100"; + address := slv_to_int(tmpadd); + dr_sram(address) <= (clk3pm_seli(2 downto 0) & '1' & clk3_hti(5 downto 0) & clk3_lti(5 downto 0)); + tmpadd := "10011"; + address := slv_to_int(tmpadd); + dr_sram(address) <= (tmpx(7 downto 0) & clk4_edgei & clk4_nocnti & clkout4_dlyi(5 downto 0)); + tmpadd := "10010"; + address := slv_to_int(tmpadd); + dr_sram(address) <= (clk4pm_seli(2 downto 0) & '1' & clk4_hti(5 downto 0) & clk4_lti(5 downto 0)); + tmpadd := "01111"; + address := slv_to_int(tmpadd); + dr_sram(address) <= (tmpx(7 downto 0) & clk5_edgei & clk5_nocnti & clkout5_dlyi(5 downto 0)); + tmpadd := "01110"; + address := slv_to_int(tmpadd); + dr_sram(address) <= (clk5pm_seli(2 downto 0) & '1' & clk5_hti(5 downto 0) & clk5_lti(5 downto 0)); + tmpadd := "01101"; + address := slv_to_int(tmpadd); + dr_sram(address) <= (tmpx(7 downto 0) & clkfbm1_edgei & clkfbm1_nocnti & clkfbm1_dlyi(5 downto 0)); + tmpadd := "01100"; + address := slv_to_int(tmpadd); + dr_sram(address) <= (clkfbm1pm_seli(2 downto 0) & '1' & clkfbm1_hti(5 downto 0) & clkfbm1_lti(5 downto 0)); + tmpadd := "00110"; + address := slv_to_int(tmpadd); + dr_sram(address) <= (tmpx(1 downto 0) & clkind_edgei & clkind_nocnti & clkind_hti(5 downto 0) & clkind_lti(5 downto 0)); + tmpadd := "00001"; + address := slv_to_int(tmpadd); + dr_sram(address) <= (tmpx(7 downto 0) & pll_lfhf & pll_cpres & pll_cp); + tmpadd := "00000"; + address := slv_to_int(tmpadd); + dr_sram(address) <= (tmpx(5 downto 0) & pll_res & tmpx(5 downto 0)); + + first_time := false; + + end if; + + + if (GSR = '1') then + drp_lock <= '0'; + elsif (rising_edge(dclk_in)) then + if (den_in = '1') then + valid_daddr := addr_is_valid(daddr_in); + if (valid_daddr) then + address := slv_to_int(daddr_in); + daddr_in_lat <= address; + end if; + + if (drp_lock = '1') then + assert false report " Warning : DEN is high at PLL_ADV before DRDY high . Need wait for DRDY signal before next read/write operation through DRP. " severity warning; + else + drp_lock <= '1'; + end if; + + if (valid_daddr and ( address = 6 or address = 0 or address = 1 or ((address >= 12 and + address <= 28) and address /= 16 and address /= 17 and + address /= 24))) then + else + Write ( Message, string'(" Warning : Address DADDR=")); + Write ( Message, address); + Write ( Message, string'(" on the PLL_ADV instance is unsupported") ); + Write ( Message, '.' & LF ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + end if; + + if (dwe_in = '1') then + if (rst_input = '1') then + if (valid_daddr and ( address = 6 or address = 0 or address = 1 or ((address >= 12 and + address <= 28) and address /= 16 and address /= 17 and + address /= 24))) then + dr_sram(address) <= di_in; + di_str := SLV_TO_STR(di_in); + end if; + + if (daddr_in = "11100") then + daddr_str := "11100"; + clkout_delay_para_drp (clkout_dly, clk_nocnt, clk_edge, di_in, daddr_in, di_str, daddr_str); + clkout0_dly <= SLV_TO_INT(clkout_dly); + clk0_nocnt <= clk_nocnt; + clk0_nocnti := clk_nocnt; + clk0_edgei := clk_edge; + clk0_edge <= clk_edge; + end if; + + if (daddr_in = "11011") then + daddr_str := "11011"; + clkout_hl_para_drp (clk_lt, clk_ht, clkpm_sel, di_in, daddr_in, di_str, daddr_str); + clk0_lt <= clk_lt; + clk0_ht <= clk_ht; + clk0_lti := clk_lt; + clk0_hti := clk_ht; + clk0pm_sel <= SLV_TO_INT(clkpm_sel); + end if; + + if (daddr_in = "11010") then + daddr_str := "11010"; + clkout_delay_para_drp (clkout_dly, clk_nocnt, clk_edge, di_in, daddr_in, di_str, daddr_str); + clkout1_dly <= SLV_TO_INT(clkout_dly); + clk1_nocnt <= clk_nocnt; + clk1_nocnti := clk_nocnt; + clk1_edgei := clk_edge; + clk1_edge <= clk_edge; + end if; + + + if (daddr_in = "11001") then + daddr_str := "11001"; + clkout_hl_para_drp (clk_lt, clk_ht, clkpm_sel, di_in, daddr_in, di_str, daddr_str); + clk1_lt <= clk_lt; + clk1_ht <= clk_ht; + clk1_lti := clk_lt; + clk1_hti := clk_ht; + clk1pm_sel <= SLV_TO_INT(clkpm_sel); + end if; + + if (daddr_in = "10111") then + daddr_str := "10111"; + clkout_delay_para_drp (clkout_dly, clk_nocnt, clk_edge, di_in, daddr_in, di_str, daddr_str); + clkout2_dly <= SLV_TO_INT(clkout_dly); + clk2_nocnt <= clk_nocnt; + clk2_nocnti := clk_nocnt; + clk2_edgei := clk_edge; + clk2_edge <= clk_edge; + end if; + + if (daddr_in = "10110") then + daddr_str := "10110"; + clkout_hl_para_drp (clk_lt, clk_ht, clkpm_sel, di_in, daddr_in, di_str, daddr_str); + clk2_lt <= clk_lt; + clk2_ht <= clk_ht; + clk2_lti := clk_lt; + clk2_hti := clk_ht; + clk2pm_sel <= SLV_TO_INT(clkpm_sel); + end if; + + if (daddr_in = "10101") then + daddr_str := "10101"; + clkout_delay_para_drp (clkout_dly, clk_nocnt, clk_edge, di_in, daddr_in, di_str, daddr_str); + clkout3_dly <= SLV_TO_INT(clkout_dly); + clk3_nocnt <= clk_nocnt; + clk3_nocnti := clk_nocnt; + clk3_edgei := clk_edge; + clk3_edge <= clk_edge; + end if; + + if (daddr_in = "10100") then + daddr_str := "10100"; + clkout_hl_para_drp (clk_lt, clk_ht, clkpm_sel, di_in, daddr_in, di_str, daddr_str); + clk3_lt <= clk_lt; + clk3_ht <= clk_ht; + clk3_lti := clk_lt; + clk3_hti := clk_ht; + clk3pm_sel <= SLV_TO_INT(clkpm_sel); + end if; + + if (daddr_in = "10011") then + daddr_str := "10011"; + clkout_delay_para_drp (clkout_dly, clk_nocnt, clk_edge, di_in, daddr_in, di_str, daddr_str); + clkout4_dly <= SLV_TO_INT(clkout_dly); + clk4_nocnt <= clk_nocnt; + clk4_nocnti := clk_nocnt; + clk4_edgei := clk_edge; + clk4_edge <= clk_edge; + end if; + + if (daddr_in = "10010") then + daddr_str := "10010"; + clkout_hl_para_drp (clk_lt, clk_ht, clkpm_sel, di_in, daddr_in, di_str, daddr_str); + clk4_lt <= clk_lt; + clk4_ht <= clk_ht; + clk4_lti := clk_lt; + clk4_hti := clk_ht; + clk4pm_sel <= SLV_TO_INT(clkpm_sel); + end if; + + if (daddr_in = "01111") then + daddr_str := "01111"; + clkout_delay_para_drp (clkout_dly, clk_nocnt, clk_edge, di_in, daddr_in, di_str, daddr_str); + clkout5_dly <= SLV_TO_INT(clkout_dly); + clk5_nocnt <= clk_nocnt; + clk5_nocnti := clk_nocnt; + clk5_edgei := clk_edge; + clk5_edge <= clk_edge; + end if; + + if (daddr_in = "01110") then + daddr_str := "01110"; + clkout_hl_para_drp (clk_lt, clk_ht, clkpm_sel, di_in, daddr_in, di_str, daddr_str); + clk5_lt <= clk_lt; + clk5_lti := clk_lt; + clk5_ht <= clk_ht; + clk5_hti := clk_ht; + clk5pm_sel <= SLV_TO_INT(clkpm_sel); + end if; + + if (daddr_in = "01101") then + daddr_str := "01101"; + clkout_delay_para_drp (clkout_dly, clk_nocnt, clk_edge, di_in, daddr_in, di_str, daddr_str); + clkfbm1_dly <= SLV_TO_INT(clkout_dly); + clkfbm1_nocnt <= clk_nocnt; + clkfbm1_nocnti := clk_nocnt; + clkfbm1_edge <= clk_edge; + clkfbm1_edgei := clk_edge; + end if; + + if (daddr_in = "01100") then + daddr_str := "01100"; + clkout_hl_para_drp (clk_lt, clk_ht, clkpm_sel, di_in, daddr_in, di_str, daddr_str); + clkfbm1_lt <= clk_lt; + clkfbm1_lti := clk_lt; + clkfbm1_ht <= clk_ht; + clkfbm1_hti := clk_ht; + clkfbm1pm_sel <= SLV_TO_INT(clkpm_sel); + end if; + + if (daddr_in = "00110") then + clkind_lti := ('0' & di_in(11 downto 6)); + clkind_hti := ('0' & di_in(5 downto 0)); + clkind_lt <= clkind_lti; + clkind_ht <= clkind_hti; + clkind_nocnti := di_in(12); + clkind_edgei := di_in(13); + end if; + + clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk0_hti, clk0_lti, clk0_nocnti, clk0_edgei); + clk0_ht1 <= clk_ht1; + clk0_div <= clk_div; + clk0_div1 <= clk_div1; + clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk1_hti, clk1_lti, clk1_nocnti, clk1_edgei); + clk1_ht1 <= clk_ht1; + clk1_div <= clk_div; + clk1_div1 <= clk_div1; + clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk2_hti, clk2_lti, clk2_nocnti, clk2_edgei); + clk2_ht1 <= clk_ht1; + clk2_div <= clk_div; + clk2_div1 <= clk_div1; + clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk3_hti, clk3_lti, clk3_nocnti, clk3_edgei); + clk3_ht1 <= clk_ht1; + clk3_div <= clk_div; + clk3_div1 <= clk_div1; + clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk4_hti, clk4_lti, clk4_nocnti, clk4_edgei); + clk4_ht1 <= clk_ht1; + clk4_div <= clk_div; + clk4_div1 <= clk_div1; + clkout_pm_cal(clk_ht1, clk_div, clk_div1, clk5_hti, clk5_lti, clk5_nocnti, clk5_edgei); + clk5_ht1 <= clk_ht1; + clk5_div <= clk_div; + clk5_div1 <= clk_div1; + clkout_pm_cal(clk_ht1, clk_div, clk_div1, clkfbm1_hti, clkfbm1_lti, clkfbm1_nocnti, clkfbm1_edgei); + clkfbm1_ht1 <= clk_ht1; + clkfbm1_div <= clk_div; + clkfbm1_div1 <= clk_div1; + clkout_pm_cal(clk_ht1, clk_div, clk_div1, clkind_hti, clkind_lti, clkind_nocnti, '0'); + clkind_div <= clk_div; + if (clk_div > 52 or (clk_div < 1 and clkind_nocnti = '0')) then + assert false report " Input Error : The sum of DI[11:6] and DI[5:0] Address DADDR=00110 is input clock divider of PLL_ADV and over the 1 to 52 range." severity error; + end if; + + else + assert false report " Error : RST is low at PLL_ADV. RST need to be high when change X_PLL_ADV paramters through DRP. " severity error; + end if; -- end rst + + end if; --DWE + end if; --DEN + + if ( drp_lock = '1') then + drp_lock <= '0'; + drp_lock1 <= '1'; + end if; + if (drp_lock1 = '1') then + drp_lock1 <= '0'; + drdy_out <= '1'; + end if; + if (drdy_out = '1') then + drdy_out <= '0'; + end if; + end if; -- end GSR + + wait on dclk_in, GSR; + +end process; + + + CLOCK_PERIOD_P : process (clkpll, rst_in) + variable clkin_edge_previous : time := 0 ps; + variable clkin_edge_current : time := 0 ps; + begin + if (rst_in = '1') then + clkin_period(0) <= period_vco_target; + clkin_period(1) <= period_vco_target; + clkin_period(2) <= period_vco_target; + clkin_period(3) <= period_vco_target; + clkin_period(4) <= period_vco_target; + clkin_jit <= 0 ps; + clkin_lock_cnt <= 0; + pll_locked_tm <= '0'; + pll_locked_tmp1 <= '0'; + lock_period <= '0'; + clkout_en0_tmp <= '0'; + unlock_recover <= '0'; + clkin_edge_previous := 0 ps; + elsif (rising_edge(clkpll)) then + clkin_edge_current := NOW; + clkin_period(4) <= clkin_period(3); + clkin_period(3) <= clkin_period(2); + clkin_period(2) <= clkin_period(1); + clkin_period(1) <= clkin_period(0); + if (clkin_edge_previous /= 0 ps and clkin_stopped_p = '0' and clkin_stopped_n = '0') then + clkin_period(0) <= clkin_edge_current - clkin_edge_previous; + end if; + + if (pll_unlock = '0') then + clkin_jit <= clkin_edge_current - clkin_edge_previous - clkin_period(0); + else + clkin_jit <= 0 ps; + end if; + + clkin_edge_previous := clkin_edge_current; + + if ( pll_unlock = '0' and (clkin_lock_cnt < lock_cnt_max) and fb_delay_found = '1' ) then + clkin_lock_cnt <= clkin_lock_cnt + 1; + elsif (pll_unlock = '1' and rst_on_loss = '0' and pll_locked_tmp1 = '1' ) then + clkin_lock_cnt <= locked_en_time; + unlock_recover <= '1'; + end if; + + if ( clkin_lock_cnt >= PLL_LOCK_TIME and pll_unlock = '0') then + pll_locked_tm <= '1'; + end if; + + if ( clkin_lock_cnt = 6 ) then + lock_period <= '1'; + end if; + + if (clkin_lock_cnt >= clkout_en_time) then + clkout_en0_tmp <= '1'; + end if; + + if (clkin_lock_cnt >= locked_en_time) then + pll_locked_tmp1 <= '1'; + end if; + + if (unlock_recover = '1' and clkin_lock_cnt >= lock_cnt_max) then + unlock_recover <= '0'; + end if; + + end if; + end process; + + CLKOUT_EN_P : process + begin + if (clkout_en0_tmp = '0') then + clkout_en0 <= '0'; + else + wait until (falling_edge(clkpll)); + clkout_en0 <= clkout_en0_tmp after (clkin_period(0)/2.0); + end if; + wait on clkout_en0_tmp; + end process; + + PLL_LOCK_P1 : process (pll_locked_tmp1, rst_in) + begin + if (rst_in = '1') then + pll_locked_tmp2 <= '0'; + elsif (pll_locked_tmp1 = '0') then + pll_locked_tmp2 <= pll_locked_tmp1; + else +-- wait until (rising_edge(clkvco)); + pll_locked_tmp2 <= pll_locked_tmp1 after pll_locked_delay; + end if; + end process; + + locked_out <= '1' when pll_locked_tm = '1' and pll_locked_tmp2 ='1' and pll_unlock = '0' + and unlock_recover = '0' else '0'; + + CLOCK_PERIOD_AVG_P : process (clkin_period(0), clkin_period(1), clkin_period(2), + clkin_period(3), clkin_period(4), period_avg) + variable period_avg_tmp : time := 0.000 ps; + variable clkin_period_tmp0 : time := 0.000 ps; + begin + clkin_period_tmp0 := clkin_period(0); + if (clkin_period_tmp0 /= period_avg) then + period_avg_tmp := (clkin_period(0) + clkin_period(1) + clkin_period(2) + + clkin_period(3) + clkin_period(4))/5.0; + period_avg <= period_avg_tmp; + end if; + end process; + + CLOCK_PERIOD_UPDATE_P : process (period_avg, clkind_div, clkfbm1_div) + variable period_fb_tmp : time; + variable period_vco_tmp : time; + variable tmpreal : real; + variable tmpreal1: real; + variable period_vco_rm_tmp : integer; + variable period_vco_rm_tmp1 : integer; + begin + md_product <= clkfbm1_div * clkind_div; + m_product <= clkfbm1_div; + m_product2 <= clkfbm1_div / 2; + period_fb_tmp := clkind_div * period_avg; + period_vco_tmp := period_fb_tmp / clkfbm1_div; + period_vco_rm_tmp1 := period_fb_tmp / 1 ps; + period_vco_rm_tmp := period_vco_rm_tmp1 mod clkfbm1_div; + period_vco_rm <= period_vco_rm_tmp; + if (period_vco_rm > 1) then + if (period_vco_rm > m_product2) then + period_vco_cmp_cnt <= (m_product / (m_product - period_vco_rm)) - 1; + period_vco_cmp_flag <= 2; + else + period_vco_cmp_cnt <= (m_product / period_vco_rm) - 1; + period_vco_cmp_flag <= 1; + end if; + else + period_vco_cmp_cnt <= 0; + period_vco_cmp_flag <= 0; + end if; + + period_vco_half <= period_vco_tmp /2; + period_vco_half1 <= ((period_vco_tmp /2) / 1 ps + 1) * 1 ps; + period_vco_half_rm <= period_vco_tmp - (period_vco_tmp /2); + pll_locked_delay <= period_fb_tmp * clkfbm1_div; + clkin_dly_t <= period_avg * clkind_div + period_avg * 1.25; + clkfb_dly_t <= period_fb_tmp * 2.25; + period_fb <= period_fb_tmp; + period_vco <= period_vco_tmp; + period_vco1 <= period_vco_tmp / 8.0; + period_vco2 <= period_vco_tmp / 4.0; + period_vco3 <= period_vco_tmp * 3.0 / 8.0; + period_vco4 <= period_vco_tmp / 2.0; + period_vco5 <= period_vco_tmp * 5.0 / 8.0; + period_vco6 <= period_vco_tmp * 3.0 / 4.0; + period_vco7 <= period_vco_tmp * 7.0 / 8.0; + end process; + + clkvco_lk_rst <= '1' when ( rst_in = '1' or pll_unlock = '1' or pll_locked_tm = '0') else '0'; + + CLKVCO_LK_P : process + variable clkvco_rm_cnt : integer; + begin + if ( clkvco_lk_rst = '1') then + clkvco_lk <= '0'; + else + if (rising_edge(clkpll)) then + if (pll_locked_tm = '1') then + clkvco_lk <= '1'; + clkvco_rm_cnt := 0; + if ( period_vco_cmp_flag = 1) then + for I in 2 to m_product loop + wait for (period_vco_half); + clkvco_lk <= '0'; + if ( clkvco_rm_cnt = 1) then + wait for (period_vco_half1); + clkvco_lk <= '1'; + else + wait for (period_vco_half_rm); + clkvco_lk <= '1'; + end if; + + if ( clkvco_rm_cnt = period_vco_cmp_cnt) then + clkvco_rm_cnt := 0; + else + clkvco_rm_cnt := clkvco_rm_cnt + 1; + end if; + end loop; + elsif ( period_vco_cmp_flag = 2) then + for I in 2 to m_product loop + wait for (period_vco_half); + clkvco_lk <= '0'; + if ( clkvco_rm_cnt = 1) then + wait for (period_vco_half_rm); + clkvco_lk <= '1'; + else + wait for (period_vco_half1); + clkvco_lk <= '1'; + end if; + + if ( clkvco_rm_cnt = period_vco_cmp_cnt) then + clkvco_rm_cnt := 0; + else + clkvco_rm_cnt := clkvco_rm_cnt + 1; + end if; + end loop; + else + for I in 2 to md_product loop + wait for (period_vco_half); + clkvco_lk <= '0'; + + wait for (period_vco_half_rm); + clkvco_lk <= '1'; + end loop; + end if; + wait for (period_vco_half); + clkvco_lk <= '0'; + end if; + end if; + end if; + wait on clkpll, rst_in , pll_unlock; + end process; + + CLKVCO_DLY_CAL_P : process ( period_vco, fb_delay, clkfbm1_dly, clkfbm1pm_rl) + variable val_tmp : integer; + variable val_tmp2 : integer; + variable val_tmp3 : integer; + variable fbm1_comp_delay : integer; + variable fbm1_comp_delay_rl : real; + variable period_vco_i : integer; + variable period_vco_rl : real; + variable dly_tmp : integer; + variable tmp_rl : real; + begin + if (fb_delay /= 0 ps and period_vco /= 0 ps) then + period_vco_i := period_vco * 1 / 1 ps; + period_vco_rl := int2real(period_vco_i); + tmp_rl := int2real(clkfbm1_dly); + val_tmp := period_vco_i * md_product; + fbm1_comp_delay_rl := period_vco_rl *(tmp_rl + clkfbm1pm_rl ); + fbm1_comp_delay := real2int(fbm1_comp_delay_rl); + val_tmp2 := fb_delay * 1 / 1 ps; + dly_tmp := val_tmp2 + fbm1_comp_delay; + if ( dly_tmp < val_tmp) then + clkvco_delay <= (val_tmp - dly_tmp) * 1 ps; + else + clkvco_delay <= (val_tmp - dly_tmp mod val_tmp) * 1 ps; + end if; + end if; + end process; + + CLKFB_PS_P : process (clkfbm1pm_sel) + begin + case (clkfbm1pm_sel) is + when 0 => clkfbm1pm_rl <= 0.0; + when 1 => clkfbm1pm_rl <= 0.125; + when 2 => clkfbm1pm_rl <= 0.25; + when 3 => clkfbm1pm_rl <= 0.375; + when 4 => clkfbm1pm_rl <= 0.50; + when 5 => clkfbm1pm_rl <= 0.625; + when 6 => clkfbm1pm_rl <= 0.75; + when 7 => clkfbm1pm_rl <= 0.875; + when others => clkfbm1pm_rl <= 0.0; + end case; + end process; + + CLKVCO_FREE_P : process + begin + if (pmcd_mode /= '1' and pll_locked_tm = '0') then + wait for period_vco_target_half; + clkvco_free <= not clkvco_free; + end if; + wait on clkvco_free; + end process; + + CLKVCO_GEN_P : process ( pll_locked_tm, clkvco_lk, clkvco_free) + begin + if (pll_locked_tm = '1') then + clkvco <= transport clkvco_lk after clkvco_delay; + else + clkvco <= transport clkvco_free after clkvco_delay; + end if; + end process; + + clkout_en <= clkout_en0 after clkvco_delay; + + + CLKOUT_MUX_P : process (clkvco, clkout_en, rst_in) + begin + if (rst_in = '1') then + clkout_mux <= "00000000"; + elsif (clkout_en = '1') then + clkout_mux(0) <= clkvco; + clkout_mux(1) <= transport clkvco after (period_vco1); + clkout_mux(2) <= transport clkvco after (period_vco2); + clkout_mux(3) <= transport clkvco after (period_vco3); + clkout_mux(4) <= transport clkvco after (period_vco4); + clkout_mux(5) <= transport clkvco after (period_vco5); + clkout_mux(6) <= transport clkvco after (period_vco6); + clkout_mux(7) <= transport clkvco after (period_vco7); + end if; + end process; + + clk0in <= clkout_mux(clk0pm_sel); + clk1in <= clkout_mux(clk1pm_sel); + clk2in <= clkout_mux(clk2pm_sel); + clk3in <= clkout_mux(clk3pm_sel); + clk4in <= clkout_mux(clk4pm_sel); + clk5in <= clkout_mux(clk5pm_sel); + clkfbm1in <= clkout_mux(clkfbm1pm_sel); + + clk0ps_en <= clkout_en when clk0_dly_cnt = clkout0_dly else '0'; + clk1ps_en <= clkout_en when clk1_dly_cnt = clkout1_dly else '0'; + clk2ps_en <= clkout_en when clk2_dly_cnt = clkout2_dly else '0'; + clk3ps_en <= clkout_en when clk3_dly_cnt = clkout3_dly else '0'; + clk4ps_en <= clkout_en when clk4_dly_cnt = clkout4_dly else '0'; + clk5ps_en <= clkout_en when clk5_dly_cnt = clkout5_dly else '0'; + clkfbm1ps_en <= clkout_en when clkfbm1_dly_cnt = clkfbm1_dly else '0'; + + CLK_DLY_CNT_P : process(clk0in, clk1in, clk2in, clk3in, clk4in, clk5in, clkfbm1in, + rst_in) + begin + if (rst_in = '1') then + clk0_dly_cnt <= 0; + clk1_dly_cnt <= 0; + clk2_dly_cnt <= 0; + clk3_dly_cnt <= 0; + clk4_dly_cnt <= 0; + clk5_dly_cnt <= 0; + clkfbm1_dly_cnt <= 0; + else + if (falling_edge(clk0in)) then + if ((clk0_dly_cnt < clkout0_dly) and clkout_en = '1') then + clk0_dly_cnt <= clk0_dly_cnt + 1; + end if; + end if; + + if (falling_edge(clk1in)) then + if ((clk1_dly_cnt < clkout1_dly) and clkout_en = '1') then + clk1_dly_cnt <= clk1_dly_cnt + 1; + end if; + end if; + + if (falling_edge(clk2in)) then + if ((clk2_dly_cnt < clkout2_dly) and clkout_en = '1') then + clk2_dly_cnt <= clk2_dly_cnt + 1; + end if; + end if; + + if (falling_edge(clk3in)) then + if ((clk3_dly_cnt < clkout3_dly) and clkout_en = '1') then + clk3_dly_cnt <= clk3_dly_cnt + 1; + end if; + end if; + + if (falling_edge(clk4in)) then + if ((clk4_dly_cnt < clkout4_dly) and clkout_en = '1') then + clk4_dly_cnt <= clk4_dly_cnt + 1; + end if; + end if; + + if (falling_edge(clk5in)) then + if ((clk5_dly_cnt < clkout5_dly) and clkout_en = '1') then + clk5_dly_cnt <= clk5_dly_cnt + 1; + end if; + end if; + + if (falling_edge(clkfbm1in)) then + if ((clkfbm1_dly_cnt < clkfbm1_dly) and clkout_en = '1') then + clkfbm1_dly_cnt <= clkfbm1_dly_cnt + 1; + end if; + end if; + + end if; + end process; + + + CLK0_GEN_P : process (clk0in, rst_in) + begin + if (rst_in = '1') then + clk0_cnt <= 0; + clk0_out <= '0'; + else + if (rising_edge(clk0in) or falling_edge(clk0in)) then + if (clk0ps_en = '1') then + + if (clk0_cnt < clk0_div1) then + clk0_cnt <= clk0_cnt + 1; + else + clk0_cnt <= 0; + end if; + + if (clk0_cnt < clk0_ht1) then + clk0_out <= '1'; + else + clk0_out <= '0'; + end if; + else + clk0_out <= '0'; + clk0_cnt <= 0; + end if; + end if; + end if; + end process; + + CLK1_GEN_P : process (clk1in, rst_in) + begin + if (rst_in = '1') then + clk1_cnt <= 0; + clk1_out <= '0'; + else + if (rising_edge(clk1in) or falling_edge(clk1in)) then + if (clk1ps_en = '1') then + if (clk1_cnt < clk1_div1) then + clk1_cnt <= clk1_cnt + 1; + else + clk1_cnt <= 0; + end if; + + if (clk1_cnt < clk1_ht1) then + clk1_out <= '1'; + else + clk1_out <= '0'; + end if; + else + clk1_out <= '0'; + clk1_cnt <= 0; + end if; + end if; + end if; + end process; + + + CLK2_GEN_P : process (clk2in, rst_in) + begin + if (rst_in = '1') then + clk2_cnt <= 0; + clk2_out <= '0'; + else + if (rising_edge(clk2in) or falling_edge(clk2in)) then + if (clk2ps_en = '1') then + if (clk2_cnt < clk2_div1) then + clk2_cnt <= clk2_cnt + 1; + else + clk2_cnt <= 0; + end if; + + if (clk2_cnt < clk2_ht1) then + clk2_out <= '1'; + else + clk2_out <= '0'; + end if; + else + clk2_out <= '0'; + clk2_cnt <= 0; + end if; + end if; + end if; + end process; + + + CLK3_GEN_P : process (clk3in, rst_in) + begin + if (rst_in = '1') then + clk3_cnt <= 0; + clk3_out <= '0'; + else + if (rising_edge(clk3in) or falling_edge(clk3in)) then + if (clk3ps_en = '1') then + if (clk3_cnt < clk3_ht1) then + clk3_out <= '1'; + else + clk3_out <= '0'; + end if; + + if (clk3_cnt < clk3_div1) then + clk3_cnt <= clk3_cnt + 1; + else + clk3_cnt <= 0; + end if; + else + clk3_out <= '0'; + clk3_cnt <= 0; + end if; + end if; + end if; + end process; + + + CLK4_GEN_P : process (clk4in, rst_in) + begin + if (rst_in = '1') then + clk4_cnt <= 0; + clk4_out <= '0'; + else + if (rising_edge(clk4in) or falling_edge(clk4in)) then + if (clk4ps_en = '1') then + if (clk4_cnt < clk4_div1) then + clk4_cnt <= clk4_cnt + 1; + else + clk4_cnt <= 0; + end if; + + if (clk4_cnt < clk4_ht1) then + clk4_out <= '1'; + else + clk4_out <= '0'; + end if; + else + clk4_out <= '0'; + clk4_cnt <= 0; + end if; + end if; + end if; + end process; + + + CLK5_GEN_P : process (clk5in, rst_in) + begin + if (rst_in = '1') then + clk5_cnt <= 0; + clk5_out <= '0'; + else + if (rising_edge(clk5in) or falling_edge(clk5in)) then + if (clk5ps_en = '1') then + if (clk5_cnt < clk5_div1) then + clk5_cnt <= clk5_cnt + 1; + else + clk5_cnt <= 0; + end if; + + if (clk5_cnt < clk5_ht1) then + clk5_out <= '1'; + else + clk5_out <= '0'; + end if; + else + clk5_out <= '0'; + clk5_cnt <= 0; + end if; + end if; + end if; + end process; + + + CLKFB_GEN_P : process (clkfbm1in, rst_in) + begin + if (rst_in = '1') then + clkfbm1_cnt <= 0; + clkfbm1_out <= '0'; + else + if (rising_edge(clkfbm1in) or falling_edge(clkfbm1in)) then + if (clkfbm1ps_en = '1') then + if (clkfbm1_cnt < clkfbm1_div1) then + clkfbm1_cnt <= clkfbm1_cnt + 1; + else + clkfbm1_cnt <= 0; + end if; + + if (clkfbm1_cnt < clkfbm1_ht1) then + clkfbm1_out <= '1'; + else + clkfbm1_out <= '0'; + end if; + else + clkfbm1_out <= '0'; + clkfbm1_cnt <= 0; + end if; + end if; + end if; + end process; + + + clkout0_out <= transport clk0_out when fb_delay_found = '1' else clkfb_tst; + clkout1_out <= transport clk1_out when fb_delay_found = '1' else clkfb_tst; + clkout2_out <= transport clk2_out when fb_delay_found = '1' else clkfb_tst; + clkout3_out <= transport clk3_out when fb_delay_found = '1' else clkfb_tst; + clkout4_out <= transport clk4_out when fb_delay_found = '1' else clkfb_tst; + clkout5_out <= transport clk5_out when fb_delay_found = '1' else clkfb_tst; + clkfb_out <= transport clkfbm1_out when fb_delay_found = '1' else clkfb_tst; + +-- +-- determine feedback delay +-- + + CLKFB_TST_P : process (clkpll, rst_in1) + begin + if (rst_in1 = '1') then + clkfb_tst <= '0'; + elsif (rising_edge(clkpll)) then + if (fb_delay_found_tmp = '0' and GSR = '0') then + clkfb_tst <= '1'; + else + clkfb_tst <= '0'; + end if; + end if; + end process; + + FB_DELAY_CAL_P0 : process (clkfb_tst, rst_in1) + begin + if (rst_in1 = '1') then + delay_edge <= 0 ps; + elsif (rising_edge(clkfb_tst)) then + delay_edge <= NOW; + end if; + end process; + + FB_DELAY_CAL_P : process (clkfb_in, rst_in1) + variable delay_edge1 : time := 0 ps; + variable fb_delay_tmp : time := 0 ps; + variable Message : line; + begin + if (rst_in1 = '1') then + fb_delay <= 0 ps; + fb_delay_found_tmp <= '0'; + delay_edge1 := 0 ps; + fb_delay_tmp := 0 ps; + elsif (clkfb_in'event and clkfb_in = '1') then + if (fb_delay_found_tmp = '0') then + if (delay_edge /= 0 ps) then + delay_edge1 := NOW; + fb_delay_tmp := delay_edge1 - delay_edge; + else + fb_delay_tmp := 0 ps; + end if; + fb_delay <= fb_delay_tmp; + fb_delay_found_tmp <= '1'; + if (rst_in1 = '0' and fb_delay_tmp > fb_delay_max) then + Write ( Message, string'(" Warning : The feedback delay is ")); + Write ( Message, fb_delay_tmp); + Write ( Message, string'(". It is over the maximun value ")); + Write ( Message, fb_delay_max); + Write ( Message, '.' & LF ); + assert false report Message.all severity warning; + DEALLOCATE (Message); + end if; + end if; + end if; + end process; + + fb_delay_found <= fb_delay_found_tmp after clkvco_delay when rst_in1 = '0' else '0'; + +-- +-- generate unlock signal +-- + + clkpll_dly <= transport clkpll after clkin_dly_t; + clkfb_in_dly <= transport clkfb_in after clkfb_dly_t when (pmcd_mode /= '1') else '0'; + + CLKINSTOP_CNT_P : process (clkpll_dly, clkpll, rst_in) + begin + + if (rst_in = '1' or clkpll = '0') then + clkstop_cnt_p <= 0; + clkin_stopped_p <= '0'; + elsif ( rising_edge (clkpll_dly) ) then + if (fb_delay_found = '1' and pll_locked_tmp2 = '1') then + if (clkpll_jitter_unlock = '0' and clkpll = '1') then + clkstop_cnt_p <= clkstop_cnt_p + 1; + else + clkstop_cnt_p <= 0; + end if; + + if (clkstop_cnt_p > clkin_stop_max) then + clkin_stopped_p <= '1'; + else + clkin_stopped_p <= '0'; + end if; + else + clkstop_cnt_p <= 0; + clkin_stopped_p <= '0'; + end if; + end if; + end process; + + CLKINSTOP_CNT_N : process (clkpll_dly, clkpll, rst_in) + begin + + if (rst_in = '1' or clkpll = '1') then + clkstop_cnt_n <= 0; + clkin_stopped_n <= '0'; + elsif ( rising_edge (clkpll_dly) ) then + if (fb_delay_found = '1' and pll_locked_tmp2 = '1') then + if (clkpll_jitter_unlock = '0' and clkpll = '0') then + clkstop_cnt_n <= clkstop_cnt_n + 1; + else + clkstop_cnt_n <= 0; + end if; + + if (clkstop_cnt_n > clkin_stop_max) then + clkin_stopped_n <= '1'; + else + clkin_stopped_n <= '0'; + end if; + else + clkstop_cnt_n <= 0; + clkin_stopped_n <= '0'; + end if; + end if; + end process; + + CLKFBSTOP_CNT_PROC : process (clkfb_in_dly, clkfb_in, rst_in) + begin + if (rst_in = '1' or clkfb_in = '0') then + clkfbstop_cnt_p <= 0; + clkfb_stopped_p <= '0'; + elsif ( rising_edge (clkfb_in_dly) ) then + if (fb_delay_found = '1' and pll_locked_tmp2 = '1') then + if (clkpll_jitter_unlock = '0' and clkfb_in = '1') then + clkfbstop_cnt_p <= clkfbstop_cnt_p + 1; + else + clkfbstop_cnt_p <= 0; + end if; + + if (clkfbstop_cnt_p > clkfb_stop_max) then + clkfb_stopped_p <= '1'; + else + clkfb_stopped_p <= '0'; + end if; + else + clkfbstop_cnt_p <= 0; + clkfb_stopped_p <= '0'; + end if; + end if; + end process; + + CLKFBSTOP_CNT_N_PROC : process (clkfb_in_dly, clkfb_in, rst_in) + begin + + if (rst_in = '1' or clkfb_in = '1') then + clkfbstop_cnt_n <= 0; + clkfb_stopped_n <= '0'; + elsif ( rising_edge (clkfb_in_dly) ) then + if (fb_delay_found = '1' and pll_locked_tmp2 = '1') then + if (clkpll_jitter_unlock = '0' and clkfb_in = '0') then + clkfbstop_cnt_n <= clkfbstop_cnt_n + 1; + else + clkfbstop_cnt_n <= 0; + end if; + + if (clkfbstop_cnt_n > clkfb_stop_max) then + clkfb_stopped_n <= '1'; + else + clkfb_stopped_n <= '0'; + end if; + else + clkfbstop_cnt_n <= 0; + clkfb_stopped_n <= '0'; + end if; + end if; + end process; + + CLK_JITTER_P : process (clkin_jit, rst_in) + begin + if (rst_in = '1') then + clkpll_jitter_unlock <= '0'; + else + if ( locked_out = '1' and clkfb_stopped = '0' and clkin_stopped = '0') then + if (ABS(clkin_jit) > ref_jitter_max_tmp) then + clkpll_jitter_unlock <= '1'; + else + clkpll_jitter_unlock <= '0'; + end if; + else + clkpll_jitter_unlock <= '0'; + end if; + end if; + end process; + + clkin_stopped <= '1' when (clkin_stopped_p = '1' or clkin_stopped_n = '1') else '0'; + clkfb_stopped <= '1' when (clkfb_stopped_p = '1' or clkfb_stopped_n = '1') else '0'; + + pll_unlock <= clkin_stopped or clkfb_stopped or clkpll_jitter_unlock; + + + +end PLL_ADV_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/pll_base.vhd,v 1.3 2006/01/07 00:13:03 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Phase Lock Loop Clock +-- /___/ /\ Filename : PLL_BASE.vhd +-- \ \ / \ Timestamp : +-- \___\/\___\ +-- Revision: +-- 12/02/05 - Initial version. +-- End Revision + + +----- CELL PLL_BASE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_SIGNED.all; +use IEEE.STD_LOGIC_ARITH.all; + +library unisim; +use unisim.vpkg.all; +use unisim.VCOMPONENTS.all; + +entity PLL_BASE is +generic ( + BANDWIDTH : string := "OPTIMIZED"; + CLKFBOUT_MULT : integer := 1; + CLKFBOUT_PHASE : real := 0.0; + CLKIN_PERIOD : real := 0.000; + CLKOUT0_DIVIDE : integer := 1; + CLKOUT0_DUTY_CYCLE : real := 0.5; + CLKOUT0_PHASE : real := 0.0; + CLKOUT1_DIVIDE : integer := 1; + CLKOUT1_DUTY_CYCLE : real := 0.5; + CLKOUT1_PHASE : real := 0.0; + CLKOUT2_DIVIDE : integer := 1; + CLKOUT2_DUTY_CYCLE : real := 0.5; + CLKOUT2_PHASE : real := 0.0; + CLKOUT3_DIVIDE : integer := 1; + CLKOUT3_DUTY_CYCLE : real := 0.5; + CLKOUT3_PHASE : real := 0.0; + CLKOUT4_DIVIDE : integer := 1; + CLKOUT4_DUTY_CYCLE : real := 0.5; + CLKOUT4_PHASE : real := 0.0; + CLKOUT5_DIVIDE : integer := 1; + CLKOUT5_DUTY_CYCLE : real := 0.5; + CLKOUT5_PHASE : real := 0.0; + COMPENSATION : string := "SYSTEM_SYNCHRONOUS"; + DIVCLK_DIVIDE : integer := 1; + REF_JITTER : real := 0.100; + RESET_ON_LOSS_OF_LOCK : boolean := FALSE + + + ); + +port ( + CLKFBOUT : out std_ulogic; + CLKOUT0 : out std_ulogic; + CLKOUT1 : out std_ulogic; + CLKOUT2 : out std_ulogic; + CLKOUT3 : out std_ulogic; + CLKOUT4 : out std_ulogic; + CLKOUT5 : out std_ulogic; + LOCKED : out std_ulogic; + + CLKFBIN : in std_ulogic; + CLKIN : in std_ulogic; + RST : in std_ulogic + ); +end PLL_BASE; + +-- Architecture body -- + +architecture PLL_BASE_V of PLL_BASE is + +signal h1 : std_ulogic := '1'; +signal z1 : std_ulogic := '0'; +signal z5 : std_logic_vector(4 downto 0) := "00000"; +signal z16 : std_logic_vector(15 downto 0) := "0000000000000000"; +signal OPEN0 : std_ulogic; +signal OPEN1 : std_ulogic; +signal OPEN2 : std_ulogic; +signal OPEN3 : std_ulogic; +signal OPEN4 : std_ulogic; +signal OPEN5 : std_ulogic; +signal OPEN6 : std_ulogic; +signal OPEN7 : std_ulogic; +signal OPEN16 : std_logic_vector(15 downto 0); + +begin +-- PLL_ADV Instantiation (port map, generic map) + +PLL_ADV_inst : PLL_ADV + generic map ( + BANDWIDTH => BANDWIDTH, + CLKFBOUT_MULT => CLKFBOUT_MULT, + CLKFBOUT_PHASE => CLKFBOUT_PHASE, + CLKIN1_PERIOD => CLKIN_PERIOD, + CLKIN2_PERIOD => 10.0, + CLKOUT0_DIVIDE => CLKOUT0_DIVIDE, + CLKOUT0_DUTY_CYCLE => CLKOUT0_DUTY_CYCLE, + CLKOUT0_PHASE => CLKOUT0_PHASE, + CLKOUT1_DIVIDE => CLKOUT1_DIVIDE, + CLKOUT1_DUTY_CYCLE => CLKOUT1_DUTY_CYCLE, + CLKOUT1_PHASE => CLKOUT1_PHASE, + CLKOUT2_DIVIDE => CLKOUT2_DIVIDE, + CLKOUT2_DUTY_CYCLE => CLKOUT2_DUTY_CYCLE, + CLKOUT2_PHASE => CLKOUT2_PHASE, + CLKOUT3_DIVIDE => CLKOUT3_DIVIDE, + CLKOUT3_DUTY_CYCLE => CLKOUT3_DUTY_CYCLE, + CLKOUT3_PHASE => CLKOUT3_PHASE, + CLKOUT4_DIVIDE => CLKOUT4_DIVIDE, + CLKOUT4_DUTY_CYCLE => CLKOUT4_DUTY_CYCLE, + CLKOUT4_PHASE => CLKOUT4_PHASE, + CLKOUT5_DIVIDE => CLKOUT5_DIVIDE, + CLKOUT5_DUTY_CYCLE => CLKOUT5_DUTY_CYCLE, + CLKOUT5_PHASE => CLKOUT5_PHASE, + COMPENSATION => COMPENSATION, + DIVCLK_DIVIDE => DIVCLK_DIVIDE, + EN_REL => FALSE, + PLL_PMCD_MODE => FALSE, + REF_JITTER => REF_JITTER, + RESET_ON_LOSS_OF_LOCK => RESET_ON_LOSS_OF_LOCK, + RST_DEASSERT_CLK => "CLKIN1" +) +port map ( + CLKFBDCM => OPEN6, + CLKFBOUT => CLKFBOUT, + CLKOUT0 => CLKOUT0, + CLKOUT1 => CLKOUT1, + CLKOUT2 => CLKOUT2, + CLKOUT3 => CLKOUT3, + CLKOUT4 => CLKOUT4, + CLKOUT5 => CLKOUT5, + CLKOUTDCM0 => OPEN0, + CLKOUTDCM1 => OPEN1, + CLKOUTDCM2 => OPEN2, + CLKOUTDCM3 => OPEN3, + CLKOUTDCM4 => OPEN4, + CLKOUTDCM5 => OPEN5, + DO => OPEN16, + DRDY => OPEN7, + LOCKED => LOCKED, + CLKFBIN => CLKFBIN, + CLKIN1 => CLKIN, + CLKIN2 => z1, + CLKINSEL => h1, + DADDR => z5, + DCLK => z1, + DEN => z1, + DI => z16, + DWE => z1, + REL => z1, + RST => RST +); + +end PLL_BASE_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ram128x1d.vhd,v 1.3 2005/10/07 18:35:24 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Dual Port Synchronous RAM 128-Deep by 1-Wide +-- /___/ /\ Filename : RAM128X1D.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:49 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/15/05 - Initial version. +-- 09/21/05 - Use SLV_TO_INT to decode the address. (CR 217651) +-- End Revision + +----- CELL RAM128X1D ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM128X1D is + generic ( + INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000" + ); + + port ( + DPO : out std_ulogic; + SPO : out std_ulogic; + + A : in std_logic_vector(6 downto 0); + D : in std_ulogic; + DPRA : in std_logic_vector(6 downto 0); + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM128X1D; + +architecture RAM128X1D_V of RAM128X1D is + signal MEM : std_ulogic_vector( 128 downto 0 ) := ('X' & TO_STDULOGICVECTOR(INIT)); + +begin + + ReadBehavior : process(A, DPRA, MEM) + variable Index_SP : integer := 128; + variable Index_DP : integer := 128; + begin + Index_SP := SLV_TO_INT(SLV => A); + Index_DP := SLV_TO_INT(SLV => DPRA); + SPO <= MEM(Index_SP); + DPO <= MEM(Index_DP); + end process ReadBehavior; + + WriteBehavior : process(WCLK) + variable Index_SP : integer := 128; + begin + Index_SP := SLV_TO_INT(SLV => A ); + if ((WE = '1') and (wclk'event) and (wclk'last_value = '0') and (wclk = '1')) then + MEM(Index_SP) <= D after 100 ps; + end if; + end process WriteBehavior; + +end RAM128X1D_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ram256x1s.vhd,v 1.3 2005/10/07 18:35:24 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Static Synchronous RAM 256-Deep by 1-Wide +-- /___/ /\ Filename : RAM256X1S.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:49 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/15/05 - Initial version. +-- 09/21/05 - Use SLV_TO_INT to decode the address. (CR 217651) +-- End Revision + +----- CELL RAM256X1S ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library UNISIM; +use UNISIM.VPKG.all; + +entity RAM256X1S is + generic ( + INIT : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + + port ( + O : out std_ulogic; + + A : in std_logic_vector(7 downto 0); + D : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM256X1S; + +architecture RAM256X1S_V of RAM256X1S is + signal MEM : std_ulogic_vector( 256 downto 0 ) := ('X' & TO_STDULOGICVECTOR(INIT)); + +begin + + ReadBehavior : process(A, MEM) + variable Index : integer := 256; + + begin + Index := SLV_TO_INT(SLV => A); + O <= MEM(Index); + end process ReadBehavior; + + WriteBehavior : process(WCLK) + variable Index : integer := 256; + begin + Index := SLV_TO_INT(SLV => A); + if ((WE = '1') and (wclk'event) and (wclk'last_value = '0') and (wclk = '1')) then + MEM(Index) <= D after 100 ps; + end if; + end process WriteBehavior; + +end RAM256X1S_V; + + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ram32m.vhd,v 1.2 2007/02/12 23:25:30 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Function Simulation Library Component +-- / / Static Synchronous RAM 32-Deep by 8-Wide +-- /___/ /\ Filename : RAM32M.vhd +-- \ \ / \ Timestamp : +-- \___\/\___\ +-- +-- Revision: +-- 03/23/06 - Initial version. +-- 02/12/07 - Change MEM_a in QB_P process to MEM_b (CR 434008) +-- End Revision + +----- CELL RAM32M ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity RAM32M is + generic ( + INIT_A : bit_vector(63 downto 0) := X"0000000000000000"; + INIT_B : bit_vector(63 downto 0) := X"0000000000000000"; + INIT_C : bit_vector(63 downto 0) := X"0000000000000000"; + INIT_D : bit_vector(63 downto 0) := X"0000000000000000" + ); + + port ( + DOA : out std_logic_vector (1 downto 0); + DOB : out std_logic_vector (1 downto 0); + DOC : out std_logic_vector (1 downto 0); + DOD : out std_logic_vector (1 downto 0); + + ADDRA : in std_logic_vector(4 downto 0); + ADDRB : in std_logic_vector(4 downto 0); + ADDRC : in std_logic_vector(4 downto 0); + ADDRD : in std_logic_vector(4 downto 0); + DIA : in std_logic_vector (1 downto 0); + DIB : in std_logic_vector (1 downto 0); + DIC : in std_logic_vector (1 downto 0); + DID : in std_logic_vector (1 downto 0); + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM32M; + +architecture RAM32M_V of RAM32M is + + signal MEM_a : std_logic_vector( 65 downto 0 ) := ("XX" & To_StdLogicVector(INIT_A) ); + signal MEM_b : std_logic_vector( 65 downto 0 ) := ("XX" & To_StdLogicVector(INIT_B) ); + signal MEM_c : std_logic_vector( 65 downto 0 ) := ("XX" & To_StdLogicVector(INIT_C) ); + signal MEM_d : std_logic_vector( 65 downto 0 ) := ("XX" & To_StdLogicVector(INIT_D) ); +begin + + QA_P : process ( ADDRA, MEM_a) + variable Index_a : integer := 32; + begin + Index_a := 2 * SLV_TO_INT(SLV => ADDRA); + DOA(0) <= MEM_a(Index_a); + DOA(1) <= MEM_a(Index_a + 1); + end process QA_P; + + QB_P : process ( ADDRB, MEM_b) + variable Index_b : integer := 32; + begin + Index_b := 2 * SLV_TO_INT(SLV => ADDRB); + DOB(0) <= MEM_b(Index_b); + DOB(1) <= MEM_b(Index_b + 1); + end process QB_P; + + QC_P : process ( ADDRC, MEM_c) + variable Index_c : integer := 32; + begin + Index_c := 2 * SLV_TO_INT(SLV => ADDRC); + DOC(0) <= MEM_c(Index_c); + DOC(1) <= MEM_c(Index_c + 1); + end process QC_P; + + QD_P : process ( ADDRD, MEM_d) + variable Index_d : integer := 32; + begin + Index_d := 2 * SLV_TO_INT(SLV => ADDRD); + DOD(0) <= MEM_d(Index_d); + DOD(1) <= MEM_d(Index_d + 1); + end process QD_P; + + VITALWriteBehavior : process(WCLK) + variable Index : integer := 32 ; + begin + if (rising_edge(WCLK)) then + if (WE = '1') then + Index := 2 * SLV_TO_INT(SLV => ADDRD); + MEM_a(Index) <= DIA(0) after 100 ps; + MEM_a(Index+1) <= DIA(1) after 100 ps; + MEM_b(Index) <= DIB(0) after 100 ps; + MEM_b(Index+1) <= DIB(1) after 100 ps; + MEM_c(Index) <= DIC(0) after 100 ps; + MEM_c(Index+1) <= DIC(1) after 100 ps; + MEM_d(Index) <= DID(0) after 100 ps; + MEM_d(Index+1) <= DID(1) after 100 ps; + end if; + end if; + end process VITALWriteBehavior; + +end RAM32M_V; + +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ram64m.vhd,v 1.1 2006/03/28 22:24:21 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Function Simulation Library Component +-- / / Static Synchronous RAM 64-Deep by 4-Wide +-- /___/ /\ Filename : RAM64M.vhd +-- \ \ / \ Timestamp : +-- \___\/\___\ +-- +-- Revision: +-- 03/23/06 - Initial version. +-- End Revision + +----- CELL RAM64M ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity RAM64M is + generic ( + INIT_A : bit_vector(63 downto 0) := X"0000000000000000"; + INIT_B : bit_vector(63 downto 0) := X"0000000000000000"; + INIT_C : bit_vector(63 downto 0) := X"0000000000000000"; + INIT_D : bit_vector(63 downto 0) := X"0000000000000000" + ); + + port ( + DOA : out std_ulogic; + DOB : out std_ulogic; + DOC : out std_ulogic; + DOD : out std_ulogic; + + ADDRA : in std_logic_vector(5 downto 0); + ADDRB : in std_logic_vector(5 downto 0); + ADDRC : in std_logic_vector(5 downto 0); + ADDRD : in std_logic_vector(5 downto 0); + DIA : in std_ulogic; + DIB : in std_ulogic; + DIC : in std_ulogic; + DID : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic + ); +end RAM64M; + +architecture RAM64M_V of RAM64M is + + signal MEM_a : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT_A) ); + signal MEM_b : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT_B) ); + signal MEM_c : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT_C) ); + signal MEM_d : std_logic_vector( 64 downto 0 ) := ('X' & To_StdLogicVector(INIT_D) ); +begin + + DOA <= MEM_a(SLV_TO_INT(SLV => ADDRA)); + DOB <= MEM_b(SLV_TO_INT(SLV => ADDRB)); + DOC <= MEM_c(SLV_TO_INT(SLV => ADDRC)); + DOD <= MEM_d(SLV_TO_INT(SLV => ADDRD)); + + VITALWriteBehavior : process(WCLK) + variable Index : integer := 64 ; + begin + if (rising_edge(WCLK)) then + if (WE = '1') then + Index := SLV_TO_INT(SLV => ADDRD); + MEM_a(Index) <= DIA after 100 ps; + MEM_b(Index) <= DIB after 100 ps; + MEM_c(Index) <= DIC after 100 ps; + MEM_d(Index) <= DID after 100 ps; + end if; + end if; + end process VITALWriteBehavior; + +end RAM64M_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ramb18sdp.vhd,v 1.12 2007/06/15 21:01:09 wloo Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2005 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB18SDP.vhd +-- \ \ / \ Timestamp : Tues October 18 16:43:59 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 10/18/05 - Initial version. +-- 01/04/07 - Added support of memory file to initialize memory and parity (CR 431584). +-- 03/14/07 - Removed attribute INITP_FILE (CR 436003). +-- 04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812). +-- 06/14/07 - Implemented high performace version of the model. +-- End Revision + +----- CELL RAMB18SDP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity RAMB18SDP is +generic ( + + DO_REG : integer := 0; + INIT : bit_vector := X"000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_FILE : string := "NONE"; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL : bit_vector := X"000000000" + + ); + +port ( + + DO : out std_logic_vector(31 downto 0); + DOP : out std_logic_vector(3 downto 0); + + DI : in std_logic_vector(31 downto 0); + DIP : in std_logic_vector(3 downto 0); + RDADDR : in std_logic_vector(8 downto 0); + RDCLK : in std_ulogic; + RDEN : in std_ulogic; + REGCE : in std_ulogic; + SSR : in std_ulogic; + WE : in std_logic_vector(3 downto 0); + WRADDR : in std_logic_vector(8 downto 0); + WRCLK : in std_ulogic; + WREN : in std_ulogic + + ); +end RAMB18SDP; + +architecture RAMB18SDP_V of RAMB18SDP is + + component ARAMB36_INTERNAL + generic + ( + BRAM_MODE : string := "TRUE_DUAL_PORT"; + BRAM_SIZE : integer := 36; + DOA_REG : integer := 0; + DOB_REG : integer := 0; + INIT_A : bit_vector := X"000000000000000000"; + INIT_B : bit_vector := X"000000000000000000"; + RAM_EXTENSION_A : string := "NONE"; + RAM_EXTENSION_B : string := "NONE"; + READ_WIDTH_A : integer := 0; + READ_WIDTH_B : integer := 0; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL_A : bit_vector := X"000000000000000000"; + SRVAL_B : bit_vector := X"000000000000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST"; + WRITE_WIDTH_A : integer := 0; + WRITE_WIDTH_B : integer := 0; + INIT_FILE : string := "NONE"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + CASCADEOUTLATA : out std_ulogic; + CASCADEOUTLATB : out std_ulogic; + CASCADEOUTREGA : out std_ulogic; + CASCADEOUTREGB : out std_ulogic; + DBITERR : out std_ulogic; + DOA : out std_logic_vector(63 downto 0); + DOB : out std_logic_vector(63 downto 0); + DOPA : out std_logic_vector(7 downto 0); + DOPB : out std_logic_vector(7 downto 0); + ECCPARITY : out std_logic_vector(7 downto 0); + SBITERR : out std_ulogic; + + ADDRA : in std_logic_vector(15 downto 0); + ADDRB : in std_logic_vector(15 downto 0); + CASCADEINLATA : in std_ulogic; + CASCADEINLATB : in std_ulogic; + CASCADEINREGA : in std_ulogic; + CASCADEINREGB : in std_ulogic; + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(63 downto 0); + DIB : in std_logic_vector(63 downto 0); + DIPA : in std_logic_vector(7 downto 0); + DIPB : in std_logic_vector(7 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + REGCLKA : in std_ulogic; + REGCLKB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(7 downto 0); + WEB : in std_logic_vector(7 downto 0) + ); + end component; + + + constant SYNC_PATH_DELAY : time := 100 ps; + signal we_int : std_logic_vector(7 downto 0) := (others => '0'); + signal addra_int : std_logic_vector(15 downto 0) := (others => '0'); + signal addrb_int : std_logic_vector(15 downto 0) := (others => '0'); + signal GND : std_ulogic := '0'; + signal GND_4 : std_logic_vector(3 downto 0) := (others => '0'); + signal GND_8 : std_logic_vector(7 downto 0) := (others => '0'); + signal GND_32 : std_logic_vector(31 downto 0) := (others => '0'); + signal GND_64 : std_logic_vector(63 downto 0) := (others => '0'); + signal OPEN_4 : std_logic_vector(3 downto 0); + signal OPEN_8 : std_logic_vector(7 downto 0); + signal OPEN_32 : std_logic_vector(31 downto 0); + signal OPEN_64 : std_logic_vector(63 downto 0); + signal do_dly : std_logic_vector(31 downto 0) := (others => '0'); + signal dop_dly : std_logic_vector(3 downto 0) := (others => '0'); + signal eccparity_dly : std_logic_vector(7 downto 0) := (others => '0'); + signal dbiterr_dly : std_ulogic := '0'; + signal sbiterr_dly : std_ulogic := '0'; + +begin + + addra_int <= "00" & RDADDR & "00000"; + addrb_int <= "00" & WRADDR & "00000"; + we_int <= WE & WE; + +-- RAMB18SDP_INTERNAL Instantiation + +RAMB18SDP_inst : ARAMB36_INTERNAL + generic map ( + + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + + INIT_A => INIT, + INIT_B => INIT, + INIT_FILE => INIT_FILE, + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_MODE => SIM_MODE, + SRVAL_A => SRVAL, + SRVAL_B => SRVAL, + WRITE_MODE_A => "READ_FIRST", + WRITE_MODE_B => "READ_FIRST", + BRAM_MODE => "SIMPLE_DUAL_PORT", + BRAM_SIZE => 18, + DOA_REG => DO_REG, + DOB_REG => DO_REG, + READ_WIDTH_A => 36, + READ_WIDTH_B => 36, + WRITE_WIDTH_A => 36, + WRITE_WIDTH_B => 36 + ) + + port map ( + ADDRA => addra_int, + ADDRB => addrb_int, + CLKA => RDCLK, + CLKB => WRCLK, + DIA => GND_64, + DIB(63 downto 32) => GND_32, + DIB(31 downto 0) => DI, + DIPA => GND_8, + DIPB(7 downto 4) => GND_4, + DIPB(3 downto 0) => DIP, + + ENA => RDEN, + ENB => WREN, + SSRA => SSR, + SSRB => GND, + WEA => GND_8, + WEB => we_int, + DOA(31 downto 0) => do_dly, + DOA(63 downto 32) => OPEN_32, + DOB => OPEN_64, + DOPA(3 downto 0) => dop_dly, + DOPA(7 downto 4) => OPEN_4, + DOPB => OPEN_8, + CASCADEOUTLATA => OPEN, + CASCADEOUTLATB => OPEN, + CASCADEOUTREGA => OPEN, + CASCADEOUTREGB => OPEN, + CASCADEINLATA => GND, + CASCADEINLATB => GND, + CASCADEINREGA => GND, + CASCADEINREGB => GND, + REGCLKA => RDCLK, + REGCLKB => GND, + REGCEA => REGCE, + REGCEB => GND, + DBITERR => OPEN, + SBITERR => OPEN, + ECCPARITY => OPEN + ); + + prcs_output_wtiming: process (do_dly, dop_dly) + begin -- process prcs_output_wtiming + + DO <= do_dly after SYNC_PATH_DELAY; + DOP <= dop_dly after SYNC_PATH_DELAY; + + end process prcs_output_wtiming; + + +end RAMB18SDP_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ramb18.vhd,v 1.13 2007/06/15 21:01:09 wloo Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2005 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB18.vhd +-- \ \ / \ Timestamp : Tues October 18 16:43:59 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 10/18/05 - Initial version. +-- 01/04/07 - Added support of memory file to initialize memory and parity (CR 431584). +-- 03/14/07 - Removed attribute INITP_FILE (CR 436003). +-- 04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812). +-- 06/14/07 - Implemented high performace version of the model. +-- End Revision + +----- CELL RAMB18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity RAMB18 is +generic ( + + DOA_REG : integer := 0; + DOB_REG : integer := 0; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"00000"; + INIT_B : bit_vector := X"00000"; + INIT_FILE : string := "NONE"; + READ_WIDTH_A : integer := 0; + READ_WIDTH_B : integer := 0; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL_A : bit_vector := X"00000"; + SRVAL_B : bit_vector := X"00000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST"; + WRITE_WIDTH_A : integer := 0; + WRITE_WIDTH_B : integer := 0 + + ); + +port ( + + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPA : out std_logic_vector(1 downto 0); + DOPB : out std_logic_vector(1 downto 0); + + ADDRA : in std_logic_vector(13 downto 0); + ADDRB : in std_logic_vector(13 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPA : in std_logic_vector(1 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(1 downto 0); + WEB : in std_logic_vector(1 downto 0) + + ); +end RAMB18; + +architecture RAMB18_V of RAMB18 is + + component ARAMB36_INTERNAL + generic + ( + BRAM_MODE : string := "TRUE_DUAL_PORT"; + BRAM_SIZE : integer := 36; + DOA_REG : integer := 0; + DOB_REG : integer := 0; + INIT_A : bit_vector := X"000000000000000000"; + INIT_B : bit_vector := X"000000000000000000"; + RAM_EXTENSION_A : string := "NONE"; + RAM_EXTENSION_B : string := "NONE"; + READ_WIDTH_A : integer := 0; + READ_WIDTH_B : integer := 0; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL_A : bit_vector := X"000000000000000000"; + SRVAL_B : bit_vector := X"000000000000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST"; + WRITE_WIDTH_A : integer := 0; + WRITE_WIDTH_B : integer := 0; + INIT_FILE : string := "NONE"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + CASCADEOUTLATA : out std_ulogic; + CASCADEOUTLATB : out std_ulogic; + CASCADEOUTREGA : out std_ulogic; + CASCADEOUTREGB : out std_ulogic; + DBITERR : out std_ulogic; + DOA : out std_logic_vector(63 downto 0); + DOB : out std_logic_vector(63 downto 0); + DOPA : out std_logic_vector(7 downto 0); + DOPB : out std_logic_vector(7 downto 0); + ECCPARITY : out std_logic_vector(7 downto 0); + SBITERR : out std_ulogic; + + ADDRA : in std_logic_vector(15 downto 0); + ADDRB : in std_logic_vector(15 downto 0); + CASCADEINLATA : in std_ulogic; + CASCADEINLATB : in std_ulogic; + CASCADEINREGA : in std_ulogic; + CASCADEINREGB : in std_ulogic; + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(63 downto 0); + DIB : in std_logic_vector(63 downto 0); + DIPA : in std_logic_vector(7 downto 0); + DIPB : in std_logic_vector(7 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + REGCLKA : in std_ulogic; + REGCLKB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(7 downto 0); + WEB : in std_logic_vector(7 downto 0) + ); + end component; + + constant SYNC_PATH_DELAY : time := 100 ps; + signal wea_int : std_logic_vector(7 downto 0) := (others => '0'); + signal web_int : std_logic_vector(7 downto 0) := (others => '0'); + signal addra_int : std_logic_vector(15 downto 0) := (others => '0'); + signal addrb_int : std_logic_vector(15 downto 0) := (others => '0'); + signal GND : std_ulogic := '0'; + signal GND_6 : std_logic_vector(5 downto 0) := (others => '0'); + signal GND_48 : std_logic_vector(47 downto 0) := (others => '0'); + signal OPEN_6 : std_logic_vector(5 downto 0); + signal OPEN_48 : std_logic_vector(47 downto 0); + signal doa_dly : std_logic_vector(15 downto 0) := (others => '0'); + signal dob_dly : std_logic_vector(15 downto 0) := (others => '0'); + signal dopa_dly : std_logic_vector(1 downto 0) := (others => '0'); + signal dopb_dly : std_logic_vector(1 downto 0) := (others => '0'); + +begin + + addra_int <= "00" & ADDRA; + addrb_int <= "00" & ADDRB; + wea_int <= WEA & WEA & WEA & WEA; + web_int <= WEB & WEB & WEB & WEB; + +-- RAMB18_INTERNAL Instantiation + +RAMB18_inst : ARAMB36_INTERNAL + generic map ( + + DOA_REG => DOA_REG, + DOB_REG => DOB_REG, + INIT_A => INIT_A, + INIT_B => INIT_B, + INIT_FILE => INIT_FILE, + + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_MODE => SIM_MODE, + SRVAL_A => SRVAL_A, + SRVAL_B => SRVAL_B, + WRITE_MODE_A => WRITE_MODE_A, + WRITE_MODE_B => WRITE_MODE_B, + BRAM_MODE => "TRUE_DUAL_PORT", + BRAM_SIZE => 18, + READ_WIDTH_A => READ_WIDTH_A, + READ_WIDTH_B => READ_WIDTH_B, + WRITE_WIDTH_A => WRITE_WIDTH_A, + WRITE_WIDTH_B => WRITE_WIDTH_B + ) + + port map ( + ADDRA => addra_int, + ADDRB => addrb_int, + CLKA => CLKA, + CLKB => CLKB, + DIA(15 downto 0) => DIA, + DIA(63 downto 16) => GND_48, + DIB(15 downto 0) => DIB, + DIB(63 downto 16) => GND_48, + DIPA(1 downto 0) => DIPA, + DIPA(7 downto 2) => GND_6, + DIPB(1 downto 0) => DIPB, + DIPB(7 downto 2) => GND_6, + ENA => ENA, + ENB => ENB, + SSRA => SSRA, + SSRB => SSRB, + WEA => wea_int, + web => web_int, + DOA(15 downto 0) => DOA_dly, + DOA(63 downto 16) => OPEN_48, + DOB(15 downto 0) => DOB_dly, + DOB(63 downto 16) => OPEN_48, + DOPA(1 downto 0) => DOPA_dly, + DOPA(7 downto 2) => OPEN_6, + DOPB(1 downto 0) => DOPB_dly, + DOPB(7 downto 2) => OPEN_6, + REGCLKA => CLKA, + REGCLKB => CLKB, + REGCEA => REGCEA, + REGCEB => REGCEB, + CASCADEOUTLATA => OPEN, + CASCADEOUTLATB => OPEN, + CASCADEOUTREGA => OPEN, + CASCADEOUTREGB => OPEN, + CASCADEINLATA => GND, + CASCADEINLATB => GND, + CASCADEINREGA => GND, + CASCADEINREGB => GND + ); + + prcs_output_wtiming: process (doa_dly, dob_dly, dopa_dly, dopb_dly) + begin -- process prcs_output_wtiming + + DOA <= doa_dly after SYNC_PATH_DELAY; + DOPA <= dopa_dly after SYNC_PATH_DELAY; + DOB <= dob_dly after SYNC_PATH_DELAY; + DOPB <= dopb_dly after SYNC_PATH_DELAY; + + end process prcs_output_wtiming; + +end RAMB18_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ramb36_exp.vhd,v 1.11 2007/06/15 21:01:09 wloo Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2005 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 32K-Bit Data and 4K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB36_EXP.vhd +-- \ \ / \ Timestamp : Tues October 18 16:43:59 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 10/18/05 - Initial version. +-- 01/04/07 - Added support of memory file to initialize memory and parity (CR 431584). +-- 03/14/07 - Removed attribute INITP_FILE (CR 436003). +-- 04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812). +-- 06/14/07 - Implemented high performace version of the model. +-- End Revision + +----- CELL RAMB36_EXP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity RAMB36_EXP is +generic ( + + DOA_REG : integer := 0; + DOB_REG : integer := 0; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + INIT_FILE : string := "NONE"; + RAM_EXTENSION_A : string := "NONE"; + RAM_EXTENSION_B : string := "NONE"; + READ_WIDTH_A : integer := 0; + READ_WIDTH_B : integer := 0; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST"; + WRITE_WIDTH_A : integer := 0; + WRITE_WIDTH_B : integer := 0 + + ); + +port ( + + CASCADEOUTLATA : out std_ulogic; + CASCADEOUTLATB : out std_ulogic; + CASCADEOUTREGA : out std_ulogic; + CASCADEOUTREGB : out std_ulogic; + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + + ADDRAL : in std_logic_vector(15 downto 0); + ADDRAU : in std_logic_vector(14 downto 0); + ADDRBL : in std_logic_vector(15 downto 0); + ADDRBU : in std_logic_vector(14 downto 0); + CASCADEINLATA : in std_ulogic; + CASCADEINLATB : in std_ulogic; + CASCADEINREGA : in std_ulogic; + CASCADEINREGB : in std_ulogic; + CLKAL : in std_ulogic; + CLKAU : in std_ulogic; + CLKBL : in std_ulogic; + CLKBU : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENAL : in std_ulogic; + ENAU : in std_ulogic; + ENBL : in std_ulogic; + ENBU : in std_ulogic; + REGCEAL : in std_ulogic; + REGCEAU : in std_ulogic; + REGCEBL : in std_ulogic; + REGCEBU : in std_ulogic; + REGCLKAL : in std_ulogic; + REGCLKAU : in std_ulogic; + REGCLKBL : in std_ulogic; + REGCLKBU : in std_ulogic; + SSRAL : in std_ulogic; + SSRAU : in std_ulogic; + SSRBL : in std_ulogic; + SSRBU : in std_ulogic; + WEAL : in std_logic_vector(3 downto 0); + WEAU : in std_logic_vector(3 downto 0); + WEBL : in std_logic_vector(7 downto 0); + WEBU : in std_logic_vector(7 downto 0) + + ); +end RAMB36_EXP; + +architecture RAMB36_EXP_V of RAMB36_EXP is + + component ARAMB36_INTERNAL + generic + ( + BRAM_MODE : string := "TRUE_DUAL_PORT"; + BRAM_SIZE : integer := 36; + DOA_REG : integer := 0; + DOB_REG : integer := 0; + INIT_A : bit_vector := X"000000000000000000"; + INIT_B : bit_vector := X"000000000000000000"; + RAM_EXTENSION_A : string := "NONE"; + RAM_EXTENSION_B : string := "NONE"; + READ_WIDTH_A : integer := 0; + READ_WIDTH_B : integer := 0; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL_A : bit_vector := X"000000000000000000"; + SRVAL_B : bit_vector := X"000000000000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST"; + WRITE_WIDTH_A : integer := 0; + WRITE_WIDTH_B : integer := 0; + INIT_FILE : string := "NONE"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + CASCADEOUTLATA : out std_ulogic; + CASCADEOUTLATB : out std_ulogic; + CASCADEOUTREGA : out std_ulogic; + CASCADEOUTREGB : out std_ulogic; + DBITERR : out std_ulogic; + DOA : out std_logic_vector(63 downto 0); + DOB : out std_logic_vector(63 downto 0); + DOPA : out std_logic_vector(7 downto 0); + DOPB : out std_logic_vector(7 downto 0); + ECCPARITY : out std_logic_vector(7 downto 0); + SBITERR : out std_ulogic; + + ADDRA : in std_logic_vector(15 downto 0); + ADDRB : in std_logic_vector(15 downto 0); + CASCADEINLATA : in std_ulogic; + CASCADEINLATB : in std_ulogic; + CASCADEINREGA : in std_ulogic; + CASCADEINREGB : in std_ulogic; + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(63 downto 0); + DIB : in std_logic_vector(63 downto 0); + DIPA : in std_logic_vector(7 downto 0); + DIPB : in std_logic_vector(7 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + REGCLKA : in std_ulogic; + REGCLKB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(7 downto 0); + WEB : in std_logic_vector(7 downto 0) + ); + end component; + + + constant SYNC_PATH_DELAY : time := 100 ps; + signal GND_4 : std_logic_vector(3 downto 0) := (others => '0'); + signal GND_32 : std_logic_vector(31 downto 0) := (others => '0'); + signal OPEN_4 : std_logic_vector(3 downto 0); + signal OPEN_32 : std_logic_vector(31 downto 0); + signal doa_dly : std_logic_vector(31 downto 0) := (others => '0'); + signal dob_dly : std_logic_vector(31 downto 0) := (others => '0'); + signal dopa_dly : std_logic_vector(3 downto 0) := (others => '0'); + signal dopb_dly : std_logic_vector(3 downto 0) := (others => '0'); + signal cascadeoutlata_dly : std_ulogic := '0'; + signal cascadeoutlatb_dly : std_ulogic := '0'; + signal cascadeoutrega_dly : std_ulogic := '0'; + signal cascadeoutregb_dly : std_ulogic := '0'; + +begin + + +RAMB36_EXP_inst : ARAMB36_INTERNAL + generic map ( + + DOA_REG => DOA_REG, + DOB_REG => DOB_REG, + INIT_A => INIT_A, + INIT_B => INIT_B, + INIT_FILE => INIT_FILE, + + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INIT_40 => INIT_40, + INIT_41 => INIT_41, + INIT_42 => INIT_42, + INIT_43 => INIT_43, + INIT_44 => INIT_44, + INIT_45 => INIT_45, + INIT_46 => INIT_46, + INIT_47 => INIT_47, + INIT_48 => INIT_48, + INIT_49 => INIT_49, + INIT_4A => INIT_4A, + INIT_4B => INIT_4B, + INIT_4C => INIT_4C, + INIT_4D => INIT_4D, + INIT_4E => INIT_4E, + INIT_4F => INIT_4F, + INIT_50 => INIT_50, + INIT_51 => INIT_51, + INIT_52 => INIT_52, + INIT_53 => INIT_53, + INIT_54 => INIT_54, + INIT_55 => INIT_55, + INIT_56 => INIT_56, + INIT_57 => INIT_57, + INIT_58 => INIT_58, + INIT_59 => INIT_59, + INIT_5A => INIT_5A, + INIT_5B => INIT_5B, + INIT_5C => INIT_5C, + INIT_5D => INIT_5D, + INIT_5E => INIT_5E, + INIT_5F => INIT_5F, + INIT_60 => INIT_60, + INIT_61 => INIT_61, + INIT_62 => INIT_62, + INIT_63 => INIT_63, + INIT_64 => INIT_64, + INIT_65 => INIT_65, + INIT_66 => INIT_66, + INIT_67 => INIT_67, + INIT_68 => INIT_68, + INIT_69 => INIT_69, + INIT_6A => INIT_6A, + INIT_6B => INIT_6B, + INIT_6C => INIT_6C, + INIT_6D => INIT_6D, + INIT_6E => INIT_6E, + INIT_6F => INIT_6F, + INIT_70 => INIT_70, + INIT_71 => INIT_71, + INIT_72 => INIT_72, + INIT_73 => INIT_73, + INIT_74 => INIT_74, + INIT_75 => INIT_75, + INIT_76 => INIT_76, + INIT_77 => INIT_77, + INIT_78 => INIT_78, + INIT_79 => INIT_79, + INIT_7A => INIT_7A, + INIT_7B => INIT_7B, + INIT_7C => INIT_7C, + INIT_7D => INIT_7D, + INIT_7E => INIT_7E, + INIT_7F => INIT_7F, + + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INITP_08 => INITP_08, + INITP_09 => INITP_09, + INITP_0A => INITP_0A, + INITP_0B => INITP_0B, + INITP_0C => INITP_0C, + INITP_0D => INITP_0D, + INITP_0E => INITP_0E, + INITP_0F => INITP_0F, + + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_MODE => SIM_MODE, + SRVAL_A => SRVAL_A, + SRVAL_B => SRVAL_B, + WRITE_MODE_A => WRITE_MODE_A, + WRITE_MODE_B => WRITE_MODE_B, + BRAM_MODE => "TRUE_DUAL_PORT", + BRAM_SIZE => 36, + RAM_EXTENSION_A => RAM_EXTENSION_A, + RAM_EXTENSION_B => RAM_EXTENSION_B, + READ_WIDTH_A => READ_WIDTH_A, + READ_WIDTH_B => READ_WIDTH_B, + WRITE_WIDTH_A => WRITE_WIDTH_A, + WRITE_WIDTH_B => WRITE_WIDTH_B + ) + + port map ( + ADDRA => ADDRAL, + ADDRB => ADDRBL, + CLKA => CLKAL, + CLKB => CLKBL, + DIA(31 downto 0) => DIA, + DIA(63 downto 32) => GND_32, + DIB(31 downto 0) => DIB, + DIB(63 downto 32) => GND_32, + DIPA(3 downto 0) => DIPA, + DIPA(7 downto 4) => GND_4, + DIPB(3 downto 0) => DIPB, + DIPB(7 downto 4) => GND_4, + ENA => ENAL, + ENB => ENBL, + SSRA => SSRAL, + SSRB => SSRBL, + WEA(3 downto 0) => WEAL, + WEA(7 downto 4) => GND_4, + WEB => WEBL, + DOA(31 downto 0) => doa_dly, + DOA(63 downto 32) => OPEN_32, + DOB(31 downto 0) => dob_dly, + DOB(63 downto 32) => OPEN_32, + DOPA(3 downto 0) => dopa_dly, + DOPA(7 downto 4) => OPEN_4, + DOPB(3 downto 0) => dopb_dly, + DOPB(7 downto 4) => OPEN_4, + CASCADEOUTLATA => cascadeoutlata_dly, + CASCADEOUTLATB => cascadeoutlatb_dly, + CASCADEOUTREGA => cascadeoutrega_dly, + CASCADEOUTREGB => cascadeoutregb_dly, + CASCADEINLATA => CASCADEINLATA, + CASCADEINLATB => CASCADEINLATB, + CASCADEINREGA => CASCADEINREGA, + CASCADEINREGB => CASCADEINREGB, + REGCLKA => REGCLKAL, + REGCLKB => REGCLKBL, + REGCEA => REGCEAL, + REGCEB => REGCEBL + ); + + prcs_output_wtiming: process (doa_dly, dob_dly, dopa_dly, dopb_dly, cascadeoutlata_dly, cascadeoutlatb_dly, cascadeoutrega_dly, cascadeoutregb_dly ) + begin -- process prcs_output_wtiming + + CASCADEOUTREGA <= cascadeoutrega_dly after SYNC_PATH_DELAY; + CASCADEOUTREGB <= cascadeoutregb_dly after SYNC_PATH_DELAY; + CASCADEOUTLATA <= cascadeoutlata_dly after SYNC_PATH_DELAY; + CASCADEOUTLATB <= cascadeoutlatb_dly after SYNC_PATH_DELAY; + DOA <= doa_dly after SYNC_PATH_DELAY; + DOPA <= dopa_dly after SYNC_PATH_DELAY; + DOB <= dob_dly after SYNC_PATH_DELAY; + DOPB <= dopb_dly after SYNC_PATH_DELAY; + + end process prcs_output_wtiming; + +end RAMB36_EXP_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ramb36sdp_exp.vhd,v 1.12 2007/06/15 21:01:09 wloo Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2005 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 32K-Bit Data and 4K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB36SDP_EXP.vhd +-- \ \ / \ Timestamp : Tues October 18 16:43:59 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 10/18/05 - Initial version. +-- 01/04/07 - Added support of memory file to initialize memory and parity (CR 431584). +-- 03/14/07 - Removed attribute INITP_FILE (CR 436003). +-- 04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812). +-- 06/14/07 - Implemented high performace version of the model. +-- End Revision + +----- CELL RAMB36SDP_EXP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity RAMB36SDP_EXP is +generic ( + + DO_REG : integer := 0; + EN_ECC_READ : boolean := FALSE; + EN_ECC_SCRUB : boolean := FALSE; + EN_ECC_WRITE : boolean := FALSE; + INIT : bit_vector := X"000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_FILE : string := "NONE"; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL : bit_vector := X"000000000000000000" + + ); + +port ( + + DBITERR : out std_ulogic; + DO : out std_logic_vector(63 downto 0); + DOP : out std_logic_vector(7 downto 0); + ECCPARITY : out std_logic_vector(7 downto 0); + SBITERR : out std_ulogic; + + DI : in std_logic_vector(63 downto 0); + DIP : in std_logic_vector(7 downto 0); + RDADDRL : in std_logic_vector(15 downto 0); + RDADDRU : in std_logic_vector(14 downto 0); + RDCLKL : in std_ulogic; + RDCLKU : in std_ulogic; + RDENU : in std_ulogic; + RDENL : in std_ulogic; + RDRCLKL : in std_ulogic; + RDRCLKU : in std_ulogic; + REGCEL : in std_ulogic; + REGCEU : in std_ulogic; + SSRL : in std_ulogic; + SSRU : in std_ulogic; + WEL : in std_logic_vector(7 downto 0); + WEU : in std_logic_vector(7 downto 0); + WRADDRL : in std_logic_vector(15 downto 0); + WRADDRU : in std_logic_vector(14 downto 0); + WRCLKL : in std_ulogic; + WRCLKU : in std_ulogic; + WRENL : in std_ulogic; + WRENU : in std_ulogic + + ); +end RAMB36SDP_EXP; + +architecture RAMB36SDP_EXP_V of RAMB36SDP_EXP is + + component ARAMB36_INTERNAL + generic + ( + BRAM_MODE : string := "TRUE_DUAL_PORT"; + BRAM_SIZE : integer := 36; + DOA_REG : integer := 0; + DOB_REG : integer := 0; + INIT_A : bit_vector := X"000000000000000000"; + INIT_B : bit_vector := X"000000000000000000"; + RAM_EXTENSION_A : string := "NONE"; + RAM_EXTENSION_B : string := "NONE"; + READ_WIDTH_A : integer := 0; + READ_WIDTH_B : integer := 0; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL_A : bit_vector := X"000000000000000000"; + SRVAL_B : bit_vector := X"000000000000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST"; + WRITE_WIDTH_A : integer := 0; + WRITE_WIDTH_B : integer := 0; + EN_ECC_READ : boolean := FALSE; + EN_ECC_SCRUB : boolean := FALSE; + EN_ECC_WRITE : boolean := FALSE; + INIT_FILE : string := "NONE"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + CASCADEOUTLATA : out std_ulogic; + CASCADEOUTLATB : out std_ulogic; + CASCADEOUTREGA : out std_ulogic; + CASCADEOUTREGB : out std_ulogic; + DBITERR : out std_ulogic; + DOA : out std_logic_vector(63 downto 0); + DOB : out std_logic_vector(63 downto 0); + DOPA : out std_logic_vector(7 downto 0); + DOPB : out std_logic_vector(7 downto 0); + ECCPARITY : out std_logic_vector(7 downto 0); + SBITERR : out std_ulogic; + + ADDRA : in std_logic_vector(15 downto 0); + ADDRB : in std_logic_vector(15 downto 0); + CASCADEINLATA : in std_ulogic; + CASCADEINLATB : in std_ulogic; + CASCADEINREGA : in std_ulogic; + CASCADEINREGB : in std_ulogic; + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(63 downto 0); + DIB : in std_logic_vector(63 downto 0); + DIPA : in std_logic_vector(7 downto 0); + DIPB : in std_logic_vector(7 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + REGCLKA : in std_ulogic; + REGCLKB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(7 downto 0); + WEB : in std_logic_vector(7 downto 0) + ); + end component; + + + function GENERICS_STR_BRAM_MODE ( + IN_STR1 : in boolean; + IN_STR2 : in boolean + ) return string is + begin + if (IN_STR1 = TRUE or IN_STR2 = TRUE) then + return "ECC"; + else + return "SIMPLE_DUAL_PORT"; + end if; + end GENERICS_STR_BRAM_MODE; + + + constant SYNC_PATH_DELAY : time := 100 ps; + signal GND : std_ulogic := '0'; + signal GND_8 : std_logic_vector(7 downto 0) := (others => '0'); + signal GND_64 : std_logic_vector(63 downto 0) := (others => '0'); + signal OPEN_8 : std_logic_vector(7 downto 0); + signal OPEN_64 : std_logic_vector(63 downto 0); + signal do_dly : std_logic_vector(63 downto 0) := (others => '0'); + signal dop_dly : std_logic_vector(7 downto 0) := (others => '0'); + signal eccparity_dly : std_logic_vector(7 downto 0) := (others => '0'); + signal dbiterr_dly : std_ulogic := '0'; + signal sbiterr_dly : std_ulogic := '0'; + +begin + +RAMB36SDP_EXP_inst : ARAMB36_INTERNAL + generic map ( + + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INIT_40 => INIT_40, + INIT_41 => INIT_41, + INIT_42 => INIT_42, + INIT_43 => INIT_43, + INIT_44 => INIT_44, + INIT_45 => INIT_45, + INIT_46 => INIT_46, + INIT_47 => INIT_47, + INIT_48 => INIT_48, + INIT_49 => INIT_49, + INIT_4A => INIT_4A, + INIT_4B => INIT_4B, + INIT_4C => INIT_4C, + INIT_4D => INIT_4D, + INIT_4E => INIT_4E, + INIT_4F => INIT_4F, + INIT_50 => INIT_50, + INIT_51 => INIT_51, + INIT_52 => INIT_52, + INIT_53 => INIT_53, + INIT_54 => INIT_54, + INIT_55 => INIT_55, + INIT_56 => INIT_56, + INIT_57 => INIT_57, + INIT_58 => INIT_58, + INIT_59 => INIT_59, + INIT_5A => INIT_5A, + INIT_5B => INIT_5B, + INIT_5C => INIT_5C, + INIT_5D => INIT_5D, + INIT_5E => INIT_5E, + INIT_5F => INIT_5F, + INIT_60 => INIT_60, + INIT_61 => INIT_61, + INIT_62 => INIT_62, + INIT_63 => INIT_63, + INIT_64 => INIT_64, + INIT_65 => INIT_65, + INIT_66 => INIT_66, + INIT_67 => INIT_67, + INIT_68 => INIT_68, + INIT_69 => INIT_69, + INIT_6A => INIT_6A, + INIT_6B => INIT_6B, + INIT_6C => INIT_6C, + INIT_6D => INIT_6D, + INIT_6E => INIT_6E, + INIT_6F => INIT_6F, + INIT_70 => INIT_70, + INIT_71 => INIT_71, + INIT_72 => INIT_72, + INIT_73 => INIT_73, + INIT_74 => INIT_74, + INIT_75 => INIT_75, + INIT_76 => INIT_76, + INIT_77 => INIT_77, + INIT_78 => INIT_78, + INIT_79 => INIT_79, + INIT_7A => INIT_7A, + INIT_7B => INIT_7B, + INIT_7C => INIT_7C, + INIT_7D => INIT_7D, + INIT_7E => INIT_7E, + INIT_7F => INIT_7F, + + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INITP_08 => INITP_08, + INITP_09 => INITP_09, + INITP_0A => INITP_0A, + INITP_0B => INITP_0B, + INITP_0C => INITP_0C, + INITP_0D => INITP_0D, + INITP_0E => INITP_0E, + INITP_0F => INITP_0F, + + INIT_A => INIT, + INIT_B => INIT, + INIT_FILE => INIT_FILE, + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_MODE => SIM_MODE, + SRVAL_A => SRVAL, + SRVAL_B => SRVAL, + WRITE_MODE_A => "READ_FIRST", + WRITE_MODE_B => "READ_FIRST", + BRAM_MODE => GENERICS_STR_BRAM_MODE(EN_ECC_WRITE, EN_ECC_READ), + EN_ECC_READ => EN_ECC_READ, + EN_ECC_WRITE => EN_ECC_WRITE, + EN_ECC_SCRUB => EN_ECC_SCRUB, + DOA_REG => DO_REG, + DOB_REG => DO_REG, + READ_WIDTH_A => 72, + READ_WIDTH_B => 72, + WRITE_WIDTH_A => 72, + WRITE_WIDTH_B => 72 + ) + + port map ( + ADDRA => RDADDRL, + ADDRB => WRADDRL, + CLKA => RDCLKL, + CLKB => WRCLKL, + DIA => GND_64, + DIB => DI, + DIPA => GND_8, + DIPB => DIP, + ENA => RDENL, + ENB => WRENL, + SSRA => SSRL, + SSRB => GND, + WEA => GND_8, + WEB => WEL, + DOA => do_dly, + DOB => OPEN_64, + DOPA => dop_dly, + DOPB => OPEN_8, + CASCADEOUTLATA => OPEN, + CASCADEOUTLATB => OPEN, + CASCADEOUTREGA => OPEN, + CASCADEOUTREGB => OPEN, + CASCADEINLATA => GND, + CASCADEINLATB => GND, + CASCADEINREGA => GND, + CASCADEINREGB => GND, + REGCLKA => RDRCLKL, + REGCLKB => GND, + REGCEA => REGCEL, + REGCEB => GND, + DBITERR => dbiterr_dly, + SBITERR => sbiterr_dly, + ECCPARITY => eccparity_dly + ); + + prcs_output_wtiming: process (do_dly, dop_dly, eccparity_dly, dbiterr_dly, sbiterr_dly) + begin -- process prcs_output_wtiming + + DBITERR <= dbiterr_dly after SYNC_PATH_DELAY; + SBITERR <= sbiterr_dly after SYNC_PATH_DELAY; + ECCPARITY <= eccparity_dly after SYNC_PATH_DELAY; + DO <= do_dly after SYNC_PATH_DELAY; + DOP <= dop_dly after SYNC_PATH_DELAY; + + end process prcs_output_wtiming; + +end RAMB36SDP_EXP_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ramb36sdp.vhd,v 1.13 2007/06/15 21:01:09 wloo Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2005 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 32K-Bit Data and 4K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB36SDP.vhd +-- \ \ / \ Timestamp : Tues October 18 16:43:59 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 10/18/05 - Initial version. +-- 01/04/07 - Added support of memory file to initialize memory and parity (CR 431584). +-- 03/14/07 - Removed attribute INITP_FILE (CR 436003). +-- 04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812). +-- 06/14/07 - Implemented high performace version of the model. +-- End Revision + +----- CELL RAMB36SDP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity RAMB36SDP is +generic ( + + DO_REG : integer := 0; + EN_ECC_READ : boolean := FALSE; + EN_ECC_SCRUB : boolean := FALSE; + EN_ECC_WRITE : boolean := FALSE; + INIT : bit_vector := X"000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_FILE : string := "NONE"; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL : bit_vector := X"000000000000000000" + + ); + +port ( + + DBITERR : out std_ulogic; + DO : out std_logic_vector(63 downto 0); + DOP : out std_logic_vector(7 downto 0); + ECCPARITY : out std_logic_vector(7 downto 0); + SBITERR : out std_ulogic; + + DI : in std_logic_vector(63 downto 0); + DIP : in std_logic_vector(7 downto 0); + RDADDR : in std_logic_vector(8 downto 0); + RDCLK : in std_ulogic; + RDEN : in std_ulogic; + REGCE : in std_ulogic; + SSR : in std_ulogic; + WE : in std_logic_vector(7 downto 0); + WRADDR : in std_logic_vector(8 downto 0); + WRCLK : in std_ulogic; + WREN : in std_ulogic + + ); +end RAMB36SDP; + +architecture RAMB36SDP_V of RAMB36SDP is + + component ARAMB36_INTERNAL + generic + ( + BRAM_MODE : string := "TRUE_DUAL_PORT"; + BRAM_SIZE : integer := 36; + DOA_REG : integer := 0; + DOB_REG : integer := 0; + INIT_A : bit_vector := X"000000000000000000"; + INIT_B : bit_vector := X"000000000000000000"; + RAM_EXTENSION_A : string := "NONE"; + RAM_EXTENSION_B : string := "NONE"; + READ_WIDTH_A : integer := 0; + READ_WIDTH_B : integer := 0; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL_A : bit_vector := X"000000000000000000"; + SRVAL_B : bit_vector := X"000000000000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST"; + WRITE_WIDTH_A : integer := 0; + WRITE_WIDTH_B : integer := 0; + EN_ECC_READ : boolean := FALSE; + EN_ECC_SCRUB : boolean := FALSE; + EN_ECC_WRITE : boolean := FALSE; + INIT_FILE : string := "NONE"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + CASCADEOUTLATA : out std_ulogic; + CASCADEOUTLATB : out std_ulogic; + CASCADEOUTREGA : out std_ulogic; + CASCADEOUTREGB : out std_ulogic; + DBITERR : out std_ulogic; + DOA : out std_logic_vector(63 downto 0); + DOB : out std_logic_vector(63 downto 0); + DOPA : out std_logic_vector(7 downto 0); + DOPB : out std_logic_vector(7 downto 0); + ECCPARITY : out std_logic_vector(7 downto 0); + SBITERR : out std_ulogic; + + ADDRA : in std_logic_vector(15 downto 0); + ADDRB : in std_logic_vector(15 downto 0); + CASCADEINLATA : in std_ulogic; + CASCADEINLATB : in std_ulogic; + CASCADEINREGA : in std_ulogic; + CASCADEINREGB : in std_ulogic; + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(63 downto 0); + DIB : in std_logic_vector(63 downto 0); + DIPA : in std_logic_vector(7 downto 0); + DIPB : in std_logic_vector(7 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + REGCLKA : in std_ulogic; + REGCLKB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(7 downto 0); + WEB : in std_logic_vector(7 downto 0) + ); + end component; + + + function GENERICS_STR_BRAM_MODE ( + IN_STR1 : in boolean; + IN_STR2 : in boolean + ) return string is + begin + if (IN_STR1 = TRUE or IN_STR2 = TRUE) then + return "ECC"; + else + return "SIMPLE_DUAL_PORT"; + end if; + end GENERICS_STR_BRAM_MODE; + + + constant SYNC_PATH_DELAY : time := 100 ps; + signal addra_int : std_logic_vector(15 downto 0) := (others => '0'); + signal addrb_int : std_logic_vector(15 downto 0) := (others => '0'); + signal GND : std_ulogic := '0'; + signal GND_8 : std_logic_vector(7 downto 0) := (others => '0'); + signal GND_64 : std_logic_vector(63 downto 0) := (others => '0'); + signal OPEN_8 : std_logic_vector(7 downto 0); + signal OPEN_64 : std_logic_vector(63 downto 0); + signal do_dly : std_logic_vector(63 downto 0) := (others => '0'); + signal dop_dly : std_logic_vector(7 downto 0) := (others => '0'); + signal eccparity_dly : std_logic_vector(7 downto 0) := (others => '0'); + signal dbiterr_dly : std_ulogic := '0'; + signal sbiterr_dly : std_ulogic := '0'; + +begin + + addra_int <= '0' & RDADDR & "000000"; + addrb_int <= '0' & WRADDR & "000000"; + +RAMB36SDP_inst : ARAMB36_INTERNAL + generic map ( + + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INIT_40 => INIT_40, + INIT_41 => INIT_41, + INIT_42 => INIT_42, + INIT_43 => INIT_43, + INIT_44 => INIT_44, + INIT_45 => INIT_45, + INIT_46 => INIT_46, + INIT_47 => INIT_47, + INIT_48 => INIT_48, + INIT_49 => INIT_49, + INIT_4A => INIT_4A, + INIT_4B => INIT_4B, + INIT_4C => INIT_4C, + INIT_4D => INIT_4D, + INIT_4E => INIT_4E, + INIT_4F => INIT_4F, + INIT_50 => INIT_50, + INIT_51 => INIT_51, + INIT_52 => INIT_52, + INIT_53 => INIT_53, + INIT_54 => INIT_54, + INIT_55 => INIT_55, + INIT_56 => INIT_56, + INIT_57 => INIT_57, + INIT_58 => INIT_58, + INIT_59 => INIT_59, + INIT_5A => INIT_5A, + INIT_5B => INIT_5B, + INIT_5C => INIT_5C, + INIT_5D => INIT_5D, + INIT_5E => INIT_5E, + INIT_5F => INIT_5F, + INIT_60 => INIT_60, + INIT_61 => INIT_61, + INIT_62 => INIT_62, + INIT_63 => INIT_63, + INIT_64 => INIT_64, + INIT_65 => INIT_65, + INIT_66 => INIT_66, + INIT_67 => INIT_67, + INIT_68 => INIT_68, + INIT_69 => INIT_69, + INIT_6A => INIT_6A, + INIT_6B => INIT_6B, + INIT_6C => INIT_6C, + INIT_6D => INIT_6D, + INIT_6E => INIT_6E, + INIT_6F => INIT_6F, + INIT_70 => INIT_70, + INIT_71 => INIT_71, + INIT_72 => INIT_72, + INIT_73 => INIT_73, + INIT_74 => INIT_74, + INIT_75 => INIT_75, + INIT_76 => INIT_76, + INIT_77 => INIT_77, + INIT_78 => INIT_78, + INIT_79 => INIT_79, + INIT_7A => INIT_7A, + INIT_7B => INIT_7B, + INIT_7C => INIT_7C, + INIT_7D => INIT_7D, + INIT_7E => INIT_7E, + INIT_7F => INIT_7F, + + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INITP_08 => INITP_08, + INITP_09 => INITP_09, + INITP_0A => INITP_0A, + INITP_0B => INITP_0B, + INITP_0C => INITP_0C, + INITP_0D => INITP_0D, + INITP_0E => INITP_0E, + INITP_0F => INITP_0F, + + INIT_A => INIT, + INIT_B => INIT, + INIT_FILE => INIT_FILE, + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_MODE => SIM_MODE, + SRVAL_A => SRVAL, + SRVAL_B => SRVAL, + WRITE_MODE_A => "READ_FIRST", + WRITE_MODE_B => "READ_FIRST", + BRAM_MODE => GENERICS_STR_BRAM_MODE(EN_ECC_WRITE, EN_ECC_READ), + EN_ECC_READ => EN_ECC_READ, + EN_ECC_WRITE => EN_ECC_WRITE, + EN_ECC_SCRUB => EN_ECC_SCRUB, + DOA_REG => DO_REG, + DOB_REG => DO_REG, + READ_WIDTH_A => 72, + READ_WIDTH_B => 72, + WRITE_WIDTH_A => 72, + WRITE_WIDTH_B => 72 + ) + + port map ( + ADDRA => addra_int, + ADDRB => addrb_int, + CLKA => RDCLK, + CLKB => WRCLK, + DIA => GND_64, + DIB => DI, + DIPA => GND_8, + DIPB => DIP, + ENA => RDEN, + ENB => WREN, + SSRA => SSR, + SSRB => GND, + WEA => GND_8, + WEB => WE, + DOA => do_dly, + DOB => OPEN_64, + DOPA => dop_dly, + DOPB => OPEN_8, + CASCADEOUTLATA => OPEN, + CASCADEOUTLATB => OPEN, + CASCADEOUTREGA => OPEN, + CASCADEOUTREGB => OPEN, + CASCADEINLATA => GND, + CASCADEINLATB => GND, + CASCADEINREGA => GND, + CASCADEINREGB => GND, + REGCLKA => RDCLK, + REGCLKB => GND, + REGCEA => REGCE, + REGCEB => GND, + DBITERR => dbiterr_dly, + SBITERR => sbiterr_dly, + ECCPARITY => eccparity_dly + ); + + prcs_output_wtiming: process (do_dly, dop_dly, eccparity_dly, dbiterr_dly, sbiterr_dly) + begin -- process prcs_output_wtiming + + DBITERR <= dbiterr_dly after SYNC_PATH_DELAY; + SBITERR <= sbiterr_dly after SYNC_PATH_DELAY; + ECCPARITY <= eccparity_dly after SYNC_PATH_DELAY; + DO <= do_dly after SYNC_PATH_DELAY; + DOP <= dop_dly after SYNC_PATH_DELAY; + + end process prcs_output_wtiming; + +end RAMB36SDP_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/ramb36.vhd,v 1.12 2007/06/15 21:01:09 wloo Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2005 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 32K-Bit Data and 4K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB36.vhd +-- \ \ / \ Timestamp : Tues October 18 16:43:59 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 10/18/05 - Initial version. +-- 01/04/07 - Added support of memory file to initialize memory and parity (CR 431584). +-- 03/14/07 - Removed attribute INITP_FILE (CR 436003). +-- 04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812). +-- 06/14/07 - Implemented high performace version of the model. +-- End Revision + +----- CELL RAMB36 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity RAMB36 is +generic ( + + DOA_REG : integer := 0; + DOB_REG : integer := 0; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + INIT_FILE : string := "NONE"; + RAM_EXTENSION_A : string := "NONE"; + RAM_EXTENSION_B : string := "NONE"; + READ_WIDTH_A : integer := 0; + READ_WIDTH_B : integer := 0; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST"; + WRITE_WIDTH_A : integer := 0; + WRITE_WIDTH_B : integer := 0 + + ); + +port ( + + CASCADEOUTLATA : out std_ulogic; + CASCADEOUTLATB : out std_ulogic; + CASCADEOUTREGA : out std_ulogic; + CASCADEOUTREGB : out std_ulogic; + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + + ADDRA : in std_logic_vector(15 downto 0); + ADDRB : in std_logic_vector(15 downto 0); + CASCADEINLATA : in std_ulogic; + CASCADEINLATB : in std_ulogic; + CASCADEINREGA : in std_ulogic; + CASCADEINREGB : in std_ulogic; + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(3 downto 0); + WEB : in std_logic_vector(3 downto 0) + + ); +end RAMB36; + +architecture RAMB36_V of RAMB36 is + + component ARAMB36_INTERNAL + generic + ( + BRAM_MODE : string := "TRUE_DUAL_PORT"; + BRAM_SIZE : integer := 36; + DOA_REG : integer := 0; + DOB_REG : integer := 0; + INIT_A : bit_vector := X"000000000000000000"; + INIT_B : bit_vector := X"000000000000000000"; + RAM_EXTENSION_A : string := "NONE"; + RAM_EXTENSION_B : string := "NONE"; + READ_WIDTH_A : integer := 0; + READ_WIDTH_B : integer := 0; + SIM_COLLISION_CHECK : string := "ALL"; + SIM_MODE : string := "SAFE"; + SRVAL_A : bit_vector := X"000000000000000000"; + SRVAL_B : bit_vector := X"000000000000000000"; + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST"; + WRITE_WIDTH_A : integer := 0; + WRITE_WIDTH_B : integer := 0; + INIT_FILE : string := "NONE"; + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port + ( + CASCADEOUTLATA : out std_ulogic; + CASCADEOUTLATB : out std_ulogic; + CASCADEOUTREGA : out std_ulogic; + CASCADEOUTREGB : out std_ulogic; + DBITERR : out std_ulogic; + DOA : out std_logic_vector(63 downto 0); + DOB : out std_logic_vector(63 downto 0); + DOPA : out std_logic_vector(7 downto 0); + DOPB : out std_logic_vector(7 downto 0); + ECCPARITY : out std_logic_vector(7 downto 0); + SBITERR : out std_ulogic; + + ADDRA : in std_logic_vector(15 downto 0); + ADDRB : in std_logic_vector(15 downto 0); + CASCADEINLATA : in std_ulogic; + CASCADEINLATB : in std_ulogic; + CASCADEINREGA : in std_ulogic; + CASCADEINREGB : in std_ulogic; + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(63 downto 0); + DIB : in std_logic_vector(63 downto 0); + DIPA : in std_logic_vector(7 downto 0); + DIPB : in std_logic_vector(7 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + REGCLKA : in std_ulogic; + REGCLKB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(7 downto 0); + WEB : in std_logic_vector(7 downto 0) + ); + end component; + + + constant SYNC_PATH_DELAY : time := 100 ps; + signal GND_4 : std_logic_vector(3 downto 0) := (others => '0'); + signal GND_32 : std_logic_vector(31 downto 0) := (others => '0'); + signal OPEN_4 : std_logic_vector(3 downto 0); + signal OPEN_32 : std_logic_vector(31 downto 0); + signal doa_dly : std_logic_vector(31 downto 0) := (others => '0'); + signal dob_dly : std_logic_vector(31 downto 0) := (others => '0'); + signal dopa_dly : std_logic_vector(3 downto 0) := (others => '0'); + signal dopb_dly : std_logic_vector(3 downto 0) := (others => '0'); + signal cascadeoutlata_dly : std_ulogic := '0'; + signal cascadeoutlatb_dly : std_ulogic := '0'; + signal cascadeoutrega_dly : std_ulogic := '0'; + signal cascadeoutregb_dly : std_ulogic := '0'; + +begin + +RAMB36_inst : ARAMB36_INTERNAL + generic map ( + + DOA_REG => DOA_REG, + DOB_REG => DOB_REG, + INIT_A => INIT_A, + INIT_B => INIT_B, + INIT_FILE => INIT_FILE, + + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INIT_40 => INIT_40, + INIT_41 => INIT_41, + INIT_42 => INIT_42, + INIT_43 => INIT_43, + INIT_44 => INIT_44, + INIT_45 => INIT_45, + INIT_46 => INIT_46, + INIT_47 => INIT_47, + INIT_48 => INIT_48, + INIT_49 => INIT_49, + INIT_4A => INIT_4A, + INIT_4B => INIT_4B, + INIT_4C => INIT_4C, + INIT_4D => INIT_4D, + INIT_4E => INIT_4E, + INIT_4F => INIT_4F, + INIT_50 => INIT_50, + INIT_51 => INIT_51, + INIT_52 => INIT_52, + INIT_53 => INIT_53, + INIT_54 => INIT_54, + INIT_55 => INIT_55, + INIT_56 => INIT_56, + INIT_57 => INIT_57, + INIT_58 => INIT_58, + INIT_59 => INIT_59, + INIT_5A => INIT_5A, + INIT_5B => INIT_5B, + INIT_5C => INIT_5C, + INIT_5D => INIT_5D, + INIT_5E => INIT_5E, + INIT_5F => INIT_5F, + INIT_60 => INIT_60, + INIT_61 => INIT_61, + INIT_62 => INIT_62, + INIT_63 => INIT_63, + INIT_64 => INIT_64, + INIT_65 => INIT_65, + INIT_66 => INIT_66, + INIT_67 => INIT_67, + INIT_68 => INIT_68, + INIT_69 => INIT_69, + INIT_6A => INIT_6A, + INIT_6B => INIT_6B, + INIT_6C => INIT_6C, + INIT_6D => INIT_6D, + INIT_6E => INIT_6E, + INIT_6F => INIT_6F, + INIT_70 => INIT_70, + INIT_71 => INIT_71, + INIT_72 => INIT_72, + INIT_73 => INIT_73, + INIT_74 => INIT_74, + INIT_75 => INIT_75, + INIT_76 => INIT_76, + INIT_77 => INIT_77, + INIT_78 => INIT_78, + INIT_79 => INIT_79, + INIT_7A => INIT_7A, + INIT_7B => INIT_7B, + INIT_7C => INIT_7C, + INIT_7D => INIT_7D, + INIT_7E => INIT_7E, + INIT_7F => INIT_7F, + + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + INITP_08 => INITP_08, + INITP_09 => INITP_09, + INITP_0A => INITP_0A, + INITP_0B => INITP_0B, + INITP_0C => INITP_0C, + INITP_0D => INITP_0D, + INITP_0E => INITP_0E, + INITP_0F => INITP_0F, + + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + SIM_MODE => SIM_MODE, + SRVAL_A => SRVAL_A, + SRVAL_B => SRVAL_B, + WRITE_MODE_A => WRITE_MODE_A, + WRITE_MODE_B => WRITE_MODE_B, + BRAM_MODE => "TRUE_DUAL_PORT", + BRAM_SIZE => 36, + RAM_EXTENSION_A => RAM_EXTENSION_A, + RAM_EXTENSION_B => RAM_EXTENSION_B, + READ_WIDTH_A => READ_WIDTH_A, + READ_WIDTH_B => READ_WIDTH_B, + WRITE_WIDTH_A => WRITE_WIDTH_A, + WRITE_WIDTH_B => WRITE_WIDTH_B + + ) + port map ( + ADDRA => ADDRA, + ADDRB => ADDRB, + CLKA => CLKA, + CLKB => CLKB, + DIA(31 downto 0) => DIA, + DIA(63 downto 32) => GND_32, + DIB(31 downto 0) => DIB, + DIB(63 downto 32) => GND_32, + DIPA(3 downto 0) => DIPA, + DIPA(7 downto 4) => GND_4, + DIPB(3 downto 0) => DIPB, + DIPB(7 downto 4) => GND_4, + ENA => ENA, + ENB => ENB, + SSRA => SSRA, + SSRB => SSRB, + WEA(3 downto 0) => WEA, + WEA(7 downto 4) => GND_4, + WEB(3 downto 0) => WEB, + WEB(7 downto 4) => GND_4, + DOA(31 downto 0) => doa_dly, + DOA(63 downto 32) => OPEN_32, + DOB(31 downto 0) => dob_dly, + DOB(63 downto 32) => OPEN_32, + DOPA(3 downto 0) => dopa_dly, + DOPA(7 downto 4) => OPEN_4, + DOPB(3 downto 0) => dopb_dly, + DOPB(7 downto 4) => OPEN_4, + CASCADEOUTLATA => cascadeoutlata_dly, + CASCADEOUTLATB => cascadeoutlatb_dly, + CASCADEOUTREGA => cascadeoutrega_dly, + CASCADEOUTREGB => cascadeoutregb_dly, + CASCADEINLATA => CASCADEINLATA, + CASCADEINLATB => CASCADEINLATB, + CASCADEINREGA => CASCADEINREGA, + CASCADEINREGB => CASCADEINREGB, + REGCLKA => CLKA, + REGCLKB => CLKB, + REGCEA => REGCEA, + REGCEB => REGCEB + ); + + prcs_output_wtiming: process (doa_dly, dob_dly, dopa_dly, dopb_dly, cascadeoutlata_dly, cascadeoutlatb_dly, cascadeoutrega_dly, cascadeoutregb_dly ) + begin -- process prcs_output_wtiming + + CASCADEOUTREGA <= cascadeoutrega_dly after SYNC_PATH_DELAY; + CASCADEOUTREGB <= cascadeoutregb_dly after SYNC_PATH_DELAY; + CASCADEOUTLATA <= cascadeoutlata_dly after SYNC_PATH_DELAY; + CASCADEOUTLATB <= cascadeoutlatb_dly after SYNC_PATH_DELAY; + DOA <= doa_dly after SYNC_PATH_DELAY; + DOPA <= dopa_dly after SYNC_PATH_DELAY; + DOB <= dob_dly after SYNC_PATH_DELAY; + DOPB <= dopb_dly after SYNC_PATH_DELAY; + + end process prcs_output_wtiming; + +end RAMB36_V; +------------------------------------------------------------------------------/ +-- Copyright (c) 1995/2005 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------/ +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Function Simulation Library Component +-- / / Configuration Simulation Model +-- /___/ /\ Filename : sim_config_v5.vhd +-- \ \ / \ Timestamp : +-- \___\/\___\ +-- +-- Revision: +-- 07/23/07 - Initial version. +-- End Revision + + +----- CELL SIM_CONFIG_V5 ----- +library IEEE; +use IEEE.std_logic_1164.all; + + + + +library STD; +use STD.TEXTIO.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity SIM_CONFIG_V5 is + generic ( + + DEVICE_ID : bit_vector := X"00000000" + + ); + + port ( + BUSY : out std_ulogic := '0'; + CSOB : out std_ulogic := '1'; + DONE : inout std_ulogic := '0'; + CCLK : in std_ulogic := '0'; + CSB : in std_ulogic := '0'; + D : inout std_logic_vector(31 downto 0); + DCMLOCK : in std_ulogic := '0'; + INITB : inout std_ulogic := 'H'; + M : in std_logic_vector(2 downto 0) := "000"; + PROGB : in std_ulogic := '0'; + RDWRB : in std_ulogic := '0' + ); + + + +end SIM_CONFIG_V5; + + +architecture SIM_CONFIG_V5_V of SIM_CONFIG_V5 is + +function crc_next ( + crc_currf : in std_logic_vector(31 downto 0); + crc_inputf : in std_logic_vector(36 downto 0) + ) return std_logic_vector + is + variable x : std_logic_vector(31 downto 0); + variable m : std_logic_vector(36 downto 0); + variable bcc_next : std_logic_vector(31 downto 0); + begin + m := crc_inputf; + x := crc_inputf(31 downto 0) xor crc_currf(31 downto 0); + + bcc_next(31) := m(32) xor m(36) xor x(31) xor x(30) xor x(29) xor x(28) xor x(27) xor x(24) xor x(20) xor x(19) xor x(18) xor x(15) xor x(13) xor x(11) xor x(10) xor x(9) xor x(8) xor x(6) xor x(5) xor x(1) xor x(0); + + bcc_next(30) := m(35) xor x(31) xor x(30) xor x(29) xor x(28) xor x(27) xor x(26) xor x(23) xor x(19) xor x(18) xor x(17) xor x(14) xor x(12) xor x(10) xor x(9) xor x(8) xor x(7) xor x(5) xor x(4) xor x(0); + + bcc_next(29) := m(34) xor x(30) xor x(29) xor x(28) xor x(27) xor x(26) xor x(25) xor x(22) xor x(18) xor x(17) xor x(16) xor x(13) xor x(11) xor x(9) xor x(8) xor x(7) xor x(6) xor x(4) xor x(3); + + bcc_next(28) := m(33) xor x(29) xor x(28) xor x(27) xor x(26) xor x(25) xor x(24) xor x(21) xor x(17) xor x(16) xor x(15) xor x(12) xor x(10) xor x(8) xor x(7) xor x(6) xor x(5) xor x(3) xor x(2); + + bcc_next(27) := m(32) xor x(28) xor x(27) xor x(26) xor x(25) xor x(24) xor x(23) xor x(20) xor x(16) xor x(15) xor x(14) xor x(11) xor x(9) xor x(7) xor x(6) xor x(5) xor x(4) xor x(2) xor x(1); + + bcc_next(26) := x(31) xor x(27) xor x(26) xor x(25) xor x(24) xor x(23) xor x(22) xor x(19) xor x(15) xor x(14) xor x(13) xor x(10) xor x(8) xor x(6) xor x(5) xor x(4) xor x(3) xor x(1) xor x(0); + + bcc_next(25) := m(32) xor m(36) xor x(31) xor x(29) xor x(28) xor x(27) xor x(26) xor x(25) xor x(23) xor x(22) xor x(21) xor x(20) xor x(19) xor x(15) xor x(14) xor x(12) xor x(11) xor x(10) xor x(8) xor x(7) xor x(6) xor x(4) xor x(3) xor x(2) xor x(1); + + bcc_next(24) := m(35) xor x(31) xor x(30) xor x(28) xor x(27) xor x(26) xor x(25) xor x(24) xor x(22) xor x(21) xor x(20) xor x(19) xor x(18) xor x(14) xor x(13) xor x(11) xor x(10) xor x(9) xor x(7) xor x(6) xor x(5) xor x(3) xor x(2) xor x(1) xor x(0); + + bcc_next(23) := m(32) xor m(34) xor m(36) xor x(31) xor x(28) xor x(26) xor x(25) xor x(23) xor x(21) xor x(17) xor x(15) xor x(12) xor x(11) xor x(4) xor x(2); + + bcc_next(22) := m(32) xor m(33) xor m(35) xor m(36) xor x(29) xor x(28) xor x(25) xor x(22) xor x(19) xor x(18) xor x(16) xor x(15) xor x(14) xor x(13) xor x(9) xor x(8) xor x(6) xor x(5) xor x(3) xor x(0); + + bcc_next(21) := m(34) xor m(35) xor m(36) xor x(30) xor x(29) xor x(21) xor x(20) xor x(19) xor x(17) xor x(14) xor x(12) xor x(11) xor x(10) xor x(9) xor x(7) xor x(6) xor x(4) xor x(2) xor x(1) xor x(0); + + bcc_next(20) := m(32) xor m(33) xor m(34) xor m(35) xor m(36) xor x(31) xor x(30) xor x(27) xor x(24) xor x(16) xor x(15) xor x(3); + + bcc_next(19) := m(32) xor m(33) xor m(34) xor m(35) xor x(31) xor x(30) xor x(29) xor x(26) xor x(23) xor x(15) xor x(14) xor x(2); + + bcc_next(18) := m(33) xor m(34) xor m(36) xor x(27) xor x(25) xor x(24) xor x(22) xor x(20) xor x(19) xor x(18) xor x(15) xor x(14) xor x(11) xor x(10) xor x(9) xor x(8) xor x(6) xor x(5) xor x(0); + + bcc_next(17) := m(33) xor m(35) xor m(36) xor x(31) xor x(30) xor x(29) xor x(28) xor x(27) xor x(26) xor x(23) xor x(21) xor x(20) xor x(17) xor x(15) xor x(14) xor x(11) xor x(7) xor x(6) xor x(4) xor x(1) xor x(0); + + bcc_next(16) := m(32) xor m(34) xor m(35) xor x(30) xor x(29) xor x(28) xor x(27) xor x(26) xor x(25) xor x(22) xor x(20) xor x(19) xor x(16) xor x(14) xor x(13) xor x(10) xor x(6) xor x(5) xor x(3) xor x(0); + + bcc_next(15) := m(33) xor m(34) xor x(31) xor x(29) xor x(28) xor x(27) xor x(26) xor x(25) xor x(24) xor x(21) xor x(19) xor x(18) xor x(15) xor x(13) xor x(12) xor x(9) xor x(5) xor x(4) xor x(2); + + bcc_next(14) := m(32) xor m(33) xor x(30) xor x(28) xor x(27) xor x(26) xor x(25) xor x(24) xor x(23) xor x(20) xor x(18) xor x(17) xor x(14) xor x(12) xor x(11) xor x(8) xor x(4) xor x(3) xor x(1); + + bcc_next(13) := m(36) xor x(30) xor x(28) xor x(26) xor x(25) xor x(23) xor x(22) xor x(20) xor x(18) xor x(17) xor x(16) xor x(15) xor x(9) xor x(8) xor x(7) xor x(6) xor x(5) xor x(3) xor x(2) xor x(1); + + bcc_next(12) := m(32) xor m(35) xor m(36) xor x(31) xor x(30) xor x(28) xor x(25) xor x(22) xor x(21) xor x(20) xor x(18) xor x(17) xor x(16) xor x(14) xor x(13) xor x(11) xor x(10) xor x(9) xor x(7) xor x(4) xor x(2); + + bcc_next(11) := m(32) xor m(34) xor m(35) xor m(36) xor x(28) xor x(21) xor x(18) xor x(17) xor x(16) xor x(12) xor x(11) xor x(5) xor x(3) xor x(0); + + bcc_next(10) := m(33) xor m(34) xor m(35) xor x(31) xor x(27) xor x(20) xor x(17) xor x(16) xor x(15) xor x(11) xor x(10) xor x(4) xor x(2); + + bcc_next(9) := m(33) xor m(34) xor m(36) xor x(31) xor x(29) xor x(28) xor x(27) xor x(26) xor x(24) xor x(20) xor x(18) xor x(16) xor x(14) xor x(13) xor x(11) xor x(8) xor x(6) xor x(5) xor x(3) xor x(0); + + bcc_next(8) := m(33) xor m(35) xor m(36) xor x(31) xor x(29) xor x(26) xor x(25) xor x(24) xor x(23) xor x(20) xor x(18) xor x(17) xor x(12) xor x(11) xor x(9) xor x(8) xor x(7) xor x(6) xor x(4) xor x(2) xor x(1) xor x(0); + + bcc_next(7) := m(32) xor m(34) xor m(35) xor x(30) xor x(28) xor x(25) xor x(24) xor x(23) xor x(22) xor x(19) xor x(17) xor x(16) xor x(11) xor x(10) xor x(8) xor x(7) xor x(6) xor x(5) xor x(3) xor x(1) xor x(0); + + bcc_next(6) := m(32) xor m(33) xor m(34) xor m(36) xor x(30) xor x(28) xor x(23) xor x(22) xor x(21) xor x(20) xor x(19) xor x(16) xor x(13) xor x(11) xor x(8) xor x(7) xor x(4) xor x(2) xor x(1); + + bcc_next(5) := m(33) xor m(35) xor m(36) xor x(30) xor x(28) xor x(24) xor x(22) xor x(21) xor x(13) xor x(12) xor x(11) xor x(9) xor x(8) xor x(7) xor x(5) xor x(3); + + bcc_next(4) := m(34) xor m(35) xor m(36) xor x(31) xor x(30) xor x(28) xor x(24) xor x(23) xor x(21) xor x(19) xor x(18) xor x(15) xor x(13) xor x(12) xor x(9) xor x(7) xor x(5) xor x(4) xor x(2) xor x(1) xor x(0); + + bcc_next(3) := m(32) xor m(33) xor m(34) xor m(35) xor m(36) xor x(31) xor x(28) xor x(24) xor x(23) xor x(22) xor x(19) xor x(17) xor x(15) xor x(14) xor x(13) xor x(12) xor x(10) xor x(9) xor x(5) xor x(4) xor x(3); + + bcc_next(2) := m(32) xor m(33) xor m(34) xor m(35) xor x(31) xor x(30) xor x(27) xor x(23) xor x(22) xor x(21) xor x(18) xor x(16) xor x(14) xor x(13) xor x(12) xor x(11) xor x(9) xor x(8) xor x(4) xor x(3) xor x(2); + + bcc_next(1) := m(32) xor m(33) xor m(34) xor x(31) xor x(30) xor x(29) xor x(26) xor x(22) xor x(21) xor x(20) xor x(17) xor x(15) xor x(13) xor x(12) xor x(11) xor x(10) xor x(8) xor x(7) xor x(3) xor x(2) xor x(1); + + bcc_next(0) := m(32) xor m(33) xor x(31) xor x(30) xor x(29) xor x(28) xor x(25) xor x(21) xor x(20) xor x(19) xor x(16) xor x(14) xor x(12) xor x(11) xor x(10) xor x(9) xor x(7) xor x(6) xor x(2) xor x(1) xor x(0); + + return bcc_next; + +end crc_next; + +function bit_revers8 ( din8 : in std_logic_vector(7 downto 0)) + return std_logic_vector is + variable bit_rev8 : std_logic_vector(7 downto 0); + begin + bit_rev8(0) := din8(7); + bit_rev8(1) := din8(6); + bit_rev8(2) := din8(5); + bit_rev8(3) := din8(4); + bit_rev8(4) := din8(3); + bit_rev8(5) := din8(2); + bit_rev8(6) := din8(1); + bit_rev8(7) := din8(0); + + return bit_rev8; + end bit_revers8; + + constant cfg_Tprog : time := 300000 ps; -- min PROG must be low, 300 ns + constant cfg_Tpl : time := 100000 ps; -- max program latency us. + constant STARTUP_PH0 : std_logic_vector(2 downto 0) := "000"; + constant STARTUP_PH1 : std_logic_vector(2 downto 0) := "001"; + constant STARTUP_PH2 : std_logic_vector(2 downto 0) := "010"; + constant STARTUP_PH3 : std_logic_vector(2 downto 0) := "011"; + constant STARTUP_PH4 : std_logic_vector(2 downto 0) := "100"; + constant STARTUP_PH5 : std_logic_vector(2 downto 0) := "101"; + constant STARTUP_PH6 : std_logic_vector(2 downto 0) := "110"; + constant STARTUP_PH7 : std_logic_vector(2 downto 0) := "111"; + signal GSR : std_ulogic := '1'; + signal GTS : std_ulogic := '1'; + signal GWE : std_ulogic := '0'; + signal cclk_in : std_ulogic; + signal init_b_in : std_ulogic; + signal prog_b_in : std_ulogic; + signal rdwr_b_in : std_ulogic; + signal init_b_out : std_ulogic := '1'; + signal done_o : std_ulogic := '0'; + signal por_b : std_ulogic := '0'; + signal m_in : std_logic_vector (2 downto 0) ; + signal d_in : std_logic_vector (31 downto 0) ; + signal d_out : std_logic_vector (31 downto 0) ; + signal busy_out : std_ulogic; + signal cso_b_out : std_ulogic; + signal csi_b_in : std_ulogic; + signal d_out_en : std_ulogic; + signal dcm_locked : std_ulogic; + signal init_b_t : std_ulogic; + signal prog_b_t : std_ulogic; + signal bus_en : std_ulogic; + signal desync_flag : std_ulogic; + signal crc_rst : std_ulogic; + + signal prog_pulse_low_edge : time := 0 ps; + signal prog_pulse_low : time := 0 ps; + signal mode_sample_flag : std_ulogic := '0'; + signal buswid_flag_init : std_ulogic := '0'; + signal buswid_flag : std_ulogic := '0'; + signal buswidth : std_logic_vector (1 downto 0) := "00"; + signal pack_in_reg : std_logic_vector (31 downto 0) := X"00000000"; + signal reg_addr : std_logic_vector (4 downto 0) ; + signal new_data_in_flag : std_ulogic := '0'; + signal wr_flag : std_ulogic := '0'; + signal rd_flag : std_ulogic := '0'; + signal cmd_wr_flag : std_ulogic := '0'; + signal cmd_reg_new_flag : std_ulogic := '0'; + signal cmd_rd_flag : std_ulogic := '0'; + signal bus_sync_flag : std_ulogic := '0'; + signal conti_data_flag : std_ulogic := '0'; + signal wr_cnt : integer := 0; + signal conti_data_cnt : integer := 0; + signal rd_data_cnt : integer := 0; + signal abort_cnt : integer := 0; + signal st_state : std_logic_vector (2 downto 0) := STARTUP_PH0; + signal startup_begin_flag : std_ulogic := '0'; + signal startup_end_flag : std_ulogic := '0'; + signal crc_ck : std_ulogic := '0'; + signal crc_err_flag : std_ulogic := '0'; + signal crc_err_flag_tot : std_ulogic; + signal crc_err_flag_reg : std_ulogic := '0'; + signal crc_en : std_ulogic; + signal crc_curr : std_logic_vector (31 downto 0) := X"00000000"; + signal gwe_out : std_ulogic := '0'; + signal gts_out : std_ulogic := '1'; + signal outbus : std_logic_vector (7 downto 0) := "00000000"; + signal busy_o : std_ulogic := '0'; + signal tmp_val1 : std_logic_vector (31 downto 0) ; + signal ctl0_reg : std_logic_vector (31 downto 0) := "X0XXXXXXXXXXXXXXXXXXX001X0000XX1"; + signal cor0_reg : std_logic_vector (31 downto 0) := "00000X0000000000X011111111101100"; + signal cor1_reg : std_logic_vector (31 downto 0) := X"00000000"; + signal wbstar_reg : std_logic_vector (31 downto 0) := X"00000000"; + signal timer_reg : std_logic_vector (31 downto 0) := X"00000000"; + signal bootsts_reg : std_logic_vector (31 downto 0) := X"00000000"; + signal crc_reg : std_logic_vector (31 downto 0) ; + signal far_reg : std_logic_vector (31 downto 0) ; + signal fdri_reg : std_logic_vector (31 downto 0) ; + signal mask_reg : std_logic_vector (31 downto 0) ; + signal lout_reg : std_logic_vector (31 downto 0) ; + signal mfwr_reg : std_logic_vector (31 downto 0) ; + signal cbc_reg : std_logic_vector (31 downto 0) ; + signal idcode_reg : std_logic_vector (31 downto 0) ; + signal csob_reg : std_logic_vector (31 downto 0) ; + signal ctl1_reg : std_logic_vector (31 downto 0) ; + signal axss_reg : std_logic_vector (31 downto 0) ; + signal cmd_reg : std_logic_vector (4 downto 0) ; + signal mode_pin_in : std_logic_vector (2 downto 0) := "000"; + signal mode_reg : std_logic_vector (2 downto 0) ; + signal crc_reset : std_ulogic := '0'; + signal gsr_set : std_ulogic := '0'; + signal gts_usr_b : std_ulogic := '1'; + signal done_pin_drv : std_ulogic := '0'; + + signal shutdown_set : std_ulogic := '0'; + signal desynch_set : std_ulogic := '0'; + signal done_cycle_reg : std_logic_vector (2 downto 0) ; + signal gts_cycle_reg : std_logic_vector (2 downto 0) ; + signal gwe_cycle_reg : std_logic_vector (2 downto 0) ; + signal init_pin : std_ulogic; + signal init_rst : std_ulogic := '0'; + signal init_complete : std_ulogic; + signal nx_st_state : std_logic_vector (2 downto 0) := "000"; + signal ghigh_b : std_ulogic := '0'; + signal gts_cfg_b : std_ulogic := '0'; + signal eos_startup : std_ulogic := '0'; + signal startup_set : std_ulogic := '0'; + signal startup_set_pulse : std_logic_vector (1 downto 0) := "00"; + signal abort_out_en : std_ulogic := '0'; + signal tmp_dword : std_logic_vector (31 downto 0) ; + signal id_error_flag : std_ulogic := '0'; + signal iprog_b : std_ulogic := '1'; + signal i_init_b_cmd : std_ulogic := '1'; + signal i_init_b : std_ulogic := '0'; + signal abort_flag_wr : std_ulogic := '0'; + signal abort_flag_rd : std_ulogic := '0'; + signal abort_status : std_logic_vector (7 downto 0) := "00000000"; + signal persist_en : std_ulogic := '0'; + signal rst_sync : std_ulogic := '0'; + signal abort_dis : std_ulogic := '0'; + signal lock_cycle_reg : std_logic_vector (2 downto 0) := "000"; + signal rbcrc_no_pin : std_ulogic := '0'; + signal abort_flag_rst : std_ulogic := '0'; + signal gsr_st_out : std_ulogic := '1'; + signal gsr_cmd_out : std_ulogic := '0'; + signal gsr_cmd_out_pulse : std_ulogic := '0'; + signal d_o_en : std_ulogic := '0'; + signal stat_reg : std_logic_vector (31 downto 0) ; + signal rst_intl : std_ulogic; + signal rw_en : std_ulogic; + signal gsr_out : std_ulogic; + signal cfgerr_b_flag : std_ulogic; + signal abort_flag : std_ulogic; + signal downcont_cnt : integer := 0; +-- signal rst_en : std_ulogic := '1'; + signal rst_en : std_ulogic := '0'; + signal prog_b_a : std_ulogic := '1'; + signal csbo_flag : std_ulogic := '0'; + signal crc_bypass : std_ulogic := '0'; + signal csi_sync : std_ulogic := '0'; + signal rd_sw_en : std_ulogic := '0'; + signal csbo_cnt : integer := 0; + signal rd_reg_addr : std_logic_vector (4 downto 0) := "00000"; + signal init_b_p : std_ulogic := '0'; + signal done_in : std_ulogic := '0'; + +begin + INITB <= (not crc_err_flag_tot) when mode_sample_flag = '1' else init_b_out when init_b_out ='0' else 'H'; + + DONE <= done_o; + done_in <= DONE; + + BUSY <= busy_out; + CSOB <= cso_b_out; + cclk_in <= CCLK; + csi_b_in <= CSB; + + d_in <= D; + D <= d_out when d_out_en = '1' else "HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH"; + dcm_locked <= DCMLOCK; + + init_b_in <= INITB; + m_in <= M; + prog_b_in <= PROGB; + rdwr_b_in <= RDWRB; + + INIPROC : process + begin + if (DEVICE_ID = X"00000000") then + assert FALSE report "Attribute Syntax Error : The attribute DEVICE_ID on SIM_CONFIG_V5 is not set." severity error; + end if; + wait; + end process; + + GSR <= gsr_out; + GTS <= gts_out; + GWE <= gwe_out; + busy_out <= busy_o; + cfgerr_b_flag <= rw_en and not crc_err_flag_tot; + crc_err_flag_tot <= id_error_flag or crc_err_flag_reg; + d_out(7 downto 0) <= abort_status when (abort_out_en = '1') else outbus; + d_out_en <= d_o_en; + cso_b_out <= '0' when (csbo_flag= '1') else '1'; + crc_en <= '1'; + + process (csi_b_in, abort_flag) begin + if (csi_b_in = '1') then + busy_o <= '1'; + else + if (abort_flag = '1') then + busy_o <= '1'; + else + busy_o <= '0'; + end if; + end if; + end process; + + process (abort_out_en, csi_b_in, rdwr_b_in, rd_flag ) begin + if (abort_out_en = '1') then + d_o_en <= '1'; + else + d_o_en <= rdwr_b_in and (not csi_b_in) and rd_flag; + end if; + end process; + + + init_b_t <= init_b_in and i_init_b_cmd; + + process (rst_en, init_rst, prog_b_in, iprog_b) + begin + if (init_rst = '1') then + init_b_out <= '0'; + else + if ((rst_en = '1' and prog_b_in = '0') or iprog_b = '0' ) then + init_b_out <= '0'; + elsif ((rst_en = '1' and prog_b_in = '1') or iprog_b = '1') then + init_b_out <= '1' after cfg_Tpl; + end if; + end if; +-- wait on rst_en, init_rst, prog_b_in, iprog_b; + end process; + + process begin + if (rising_edge(id_error_flag)) then + init_rst <= '1'; + init_rst <= '0' after cfg_Tprog; + end if; + wait on id_error_flag; + end process; + + process + variable rst_en_v : std_ulogic; + begin + if (prog_b_in'event and prog_b_in = '0') then + rst_en_v := '0'; + rst_en <= '0'; + wait for cfg_Tprog; + wait for 1 ps; + rst_en_v := '1'; + rst_en <= '1'; + end if; + if (rst_en_v = '1') then + if (prog_pulse_low = cfg_Tprog) then + prog_b_a <= '0'; + prog_b_a <= '1' after 500 ps; + else + prog_b_a <= prog_b_in; + end if; + else + prog_b_a <= '1'; + end if; + wait on prog_b_in, prog_pulse_low; + end process; + + process begin + por_b <= '0'; + por_b <= '1' after 400 ns; + wait; + end process; + + prog_b_t <= prog_b_a and iprog_b and por_b; + + rst_intl <= '0' when (prog_b_t = '0' ) else '1'; + + process (init_b_t, prog_b_t) + variable Message : line; + begin + if (falling_edge (prog_b_t)) then + mode_sample_flag <= '0'; + elsif (init_b_t'event and init_b_t = '1') then + if (mode_sample_flag = '0') then + if(prog_b_t = '1') then + mode_pin_in <= m_in; + mode_sample_flag <= '1' after 1 ps; + if (m_in /= "110") then + Write ( Message, string'(" Error: input M is ")); + Write ( Message, string'(SLV_TO_STR(m_in))); + Write ( Message, string'(" . Only Slave SelectMAP mode M=110 supported on SIM_CONFIG_V5.")); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + elsif (NOW > 0 ps) then + assert false report "Error: PROGB is not high when INITB goes high on SIM_CONFIG_V5." severity error; + end if; + end if; + end if; + end process; + + process (m_in) begin + if (mode_sample_flag = '1' and persist_en = '1') then + assert false report "Error : Mode pine M[2:0] changed after rising edge of INITB on SIM_CONFIG_V5." severity error; + end if; + end process; + + prog_pulse_P : process (prog_b_in) + variable prog_pulse_low_v : time; +-- variable prog_pulse_low : time; + variable Message : line; + begin + if (falling_edge (prog_b_in)) then + prog_pulse_low_edge <= NOW; + else + if (NOW > 0 ps ) then + prog_pulse_low_v := NOW - prog_pulse_low_edge; + prog_pulse_low <= NOW - prog_pulse_low_edge; + if (prog_pulse_low_v < cfg_Tprog ) then + Write ( Message, string'(" Error: Low time of PROGB is less than required minimum Tprogram time ")); + Write ( Message, prog_pulse_low_v); + Write ( Message, string'(" .")); + assert false report Message.all severity error; + DEALLOCATE(Message); + end if; + end if; + end if; + end process; + + bus_en <= '1' when (mode_sample_flag = '1' and csi_b_in = '0') else '0'; + + process (cclk_in, rst_intl) + variable tmp_byte : std_logic_vector (7 downto 0); + begin + if (rst_intl = '0') then + buswid_flag_init <= '0'; + buswid_flag <= '0'; + buswidth <= "00"; + elsif (rising_edge(cclk_in)) then + if (buswid_flag = '0') then + if (bus_en = '1' and rdwr_b_in = '0') then + tmp_byte := bit_revers8(d_in(7 downto 0)); + if (buswid_flag_init = '0') then + if (tmp_byte = X"BB") then + buswid_flag_init <= '1'; + end if; + else + if (tmp_byte = X"11") then + buswid_flag <= '1'; + buswidth <= "01"; + elsif (tmp_byte = X"22") then + buswid_flag <= '1'; + buswidth <= "10"; + elsif (tmp_byte = X"44") then + buswid_flag <= '1'; + buswidth <= "11"; + else + buswid_flag <= '0'; + buswidth <= "00"; + buswid_flag_init <= '0'; + assert false report + "Error : BUS Width Auto Dection did not find 0x11 or 0x22 or 0x44 on D(7:0) followed 0xBB on SIM_CONFIG_V5." + severity error; + end if; + end if; + end if; + end if; + end if; + end process; + + rw_en <= '1' when (bus_en = '1' and buswid_flag = '1') else '0'; + desync_flag <= (not rst_intl) or desynch_set or crc_err_flag or id_error_flag; + + process (cclk_in) begin + if (rising_edge(cclk_in)) then + csi_sync <= csi_b_in; + end if; + end process; + + process (cclk_in, rdwr_b_in) begin + if (rdwr_b_in = '0') then + rd_sw_en <= '0'; + elsif (rising_edge(cclk_in)) then + if (csi_sync = '1' and rdwr_b_in = '1') then + rd_sw_en <= '1'; + end if; + end if; + end process; + + + bus_sync_p : process (cclk_in, desync_flag) + variable tmp_byte : std_logic_vector (7 downto 0); + variable tmp_word : std_logic_vector (15 downto 0); + variable tmp_dword : std_logic_vector (31 downto 0); + begin + if (desync_flag = '1') then + pack_in_reg <= X"00000000"; + new_data_in_flag <= '0'; + bus_sync_flag <= '0'; + wr_cnt <= 0; + wr_flag <= '0'; + rd_flag <= '0'; + elsif (rising_edge(cclk_in)) then + if (rw_en = '1' ) then + if (rdwr_b_in = '0') then + wr_flag <= '1'; + rd_flag <= '0'; + if (buswidth = "01") then + tmp_byte := bit_revers8(d_in(7 downto 0)); + if (bus_sync_flag = '0') then + if (pack_in_reg(23 downto 16) = X"AA" and pack_in_reg(15 downto 8) = X"99" + and pack_in_reg(7 downto 0) = X"55" and tmp_byte = X"66") then + bus_sync_flag <= '1'; + new_data_in_flag <= '0'; + wr_cnt <= 0; + else + pack_in_reg(31 downto 24) <= pack_in_reg(23 downto 16); + pack_in_reg(23 downto 16) <= pack_in_reg(15 downto 8); + pack_in_reg(15 downto 8) <= pack_in_reg(7 downto 0); + pack_in_reg(7 downto 0) <= tmp_byte; + end if; + else + if (wr_cnt = 0) then + pack_in_reg(31 downto 24) <= tmp_byte; + new_data_in_flag <= '0'; + wr_cnt <= 1; + elsif (wr_cnt = 1) then + pack_in_reg(23 downto 16) <= tmp_byte; + new_data_in_flag <= '0'; + wr_cnt <= 2; + elsif (wr_cnt = 2) then + pack_in_reg(15 downto 8) <= tmp_byte; + new_data_in_flag <= '0'; + wr_cnt <= 3; + elsif (wr_cnt = 3) then + pack_in_reg(7 downto 0) <= tmp_byte; + new_data_in_flag <= '1'; + wr_cnt <= 0; + end if; + end if; + elsif (buswidth = "10") then + tmp_word := bit_revers8(d_in(15 downto 8)) & bit_revers8(d_in(7 downto 0)); + if (bus_sync_flag = '0') then + if (pack_in_reg(15 downto 0) = X"AA99" and tmp_word = X"5566") then + wr_cnt <= 0; + bus_sync_flag <= '1'; + new_data_in_flag <= '0'; + else + pack_in_reg(31 downto 16) <= pack_in_reg(15 downto 0); + pack_in_reg(15 downto 0) <= tmp_word; + new_data_in_flag <= '0'; + wr_cnt <= 0; + end if; + else + if (wr_cnt = 0) then + pack_in_reg(31 downto 16) <= tmp_word; + new_data_in_flag <= '0'; + wr_cnt <= 1; + elsif (wr_cnt = 1) then + pack_in_reg(15 downto 0) <= tmp_word; + new_data_in_flag <= '1'; + wr_cnt <= 0; + end if; + end if; + elsif (buswidth = "11" ) then + tmp_dword := bit_revers8(d_in(31 downto 24)) & bit_revers8(d_in(23 downto 16)) & + bit_revers8(d_in(15 downto 8)) & bit_revers8(d_in(7 downto 0)); + pack_in_reg(31 downto 0) <= tmp_dword; + if (bus_sync_flag = '0') then + if (tmp_dword = X"AA995566") then + bus_sync_flag <= '1'; + new_data_in_flag <= '0'; + end if; + else + pack_in_reg(31 downto 0) <= tmp_dword; + new_data_in_flag <= '1'; + end if; + end if; -- end buswidth check + else + wr_flag <= '0'; + new_data_in_flag <= '0'; + if (rd_sw_en = '1') then + rd_flag <= '1'; + end if; + end if; -- end rdwr check + else + wr_flag <= '0'; + rd_flag <= '0'; + new_data_in_flag <= '0'; + end if; + end if; + end process; + + pack_decode_p : process (cclk_in, rst_intl) + variable tmp_v : std_logic_vector(5 downto 0); + variable tmp_v27 : std_logic_vector(26 downto 0); + variable tmp_v11 : std_logic_vector(10 downto 0); + variable tmp_v1 : std_logic_vector(27 downto 0); + variable tmp_v2 : std_logic_vector(31 downto 0); + variable tmp_v3 : std_logic_vector(27 downto 0); + variable message_line : line; +-- variable csbo_cnt : integer := 0; + variable crc_new : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + variable crc_input : std_logic_vector(36 downto 0) := "0000000000000000000000000000000000000"; + begin + if (rst_intl = '0') then + conti_data_flag <= '0'; + conti_data_cnt <= 0; + cmd_wr_flag <= '0'; + cmd_rd_flag <= '0'; + id_error_flag <= '0'; + crc_curr <= X"00000000"; + crc_ck <= '0'; + csbo_cnt <= 0; + csbo_flag <= '0'; + downcont_cnt <= 0; + rd_data_cnt <= 0; + elsif (falling_edge(cclk_in)) then + if (crc_reset = '1' ) then + crc_reg <= X"00000000"; + crc_ck <= '0'; + crc_curr <= X"00000000"; + end if; + if (crc_ck = '1') then + crc_curr <= X"00000000"; + end if; + if (desynch_set = '1' or crc_err_flag = '1') then + conti_data_flag <= '0'; + conti_data_cnt <= 0; + cmd_wr_flag <= '0'; + cmd_rd_flag <= '0'; + cmd_reg_new_flag <= '0'; + crc_ck <= '0'; + csbo_cnt <= 0; + csbo_flag <= '0'; + downcont_cnt <= 0; + rd_data_cnt <= 0; + end if; + + if (new_data_in_flag = '1' and wr_flag = '1') then + if (conti_data_flag = '1' ) then + case (reg_addr) is + when "00000" => crc_reg <= pack_in_reg; + crc_ck <= '1'; + when "00001" => far_reg <= pack_in_reg; + when "00010" => fdri_reg <= pack_in_reg; + when "00100" => cmd_reg <= pack_in_reg(4 downto 0); + when "00101" => ctl0_reg <= (pack_in_reg and mask_reg) or (ctl0_reg and not mask_reg); + when "00110" => mask_reg <= pack_in_reg; + when "01000" => lout_reg <= pack_in_reg; + when "01001" => cor0_reg <= pack_in_reg; + when "01010" => mfwr_reg <= pack_in_reg; +-- when "01101" => cbc_reg <= pack_in_reg; + when "01100" => idcode_reg <= pack_in_reg; + tmp_v1 := pack_in_reg(27 downto 0); + tmp_v2 := TO_STDLOGICVECTOR(DEVICE_ID); + tmp_v3 := tmp_v2(27 downto 0); +-- if (pack_in_reg(27 downto 0) /= DEVICE_ID(27 downto 0)) then + if (tmp_v1 /= tmp_v3) then + id_error_flag <= '1'; + write(message_line, string'("Error : written value to IDCODE register is ")); + write(message_line, string'(SLV_TO_STR(tmp_v1))); + write(message_line, string'(" which does not match DEVICE ID ")); + write(message_line, string'(SLV_TO_STR(tmp_v2))); + write(message_line, string'(".")); + assert false report message_line.all severity error; + DEALLOCATE(message_line); + else + id_error_flag <= '0'; + end if; + when "01101" => axss_reg <= pack_in_reg; + when "01110" => cor1_reg <= pack_in_reg; + when "01111" => csob_reg <= pack_in_reg; + when "10000" => wbstar_reg <= pack_in_reg; + when "10001" => timer_reg <= pack_in_reg; + when "11000" => ctl1_reg <= (pack_in_reg and mask_reg) or (ctl1_reg and not mask_reg); + when others => NULL; + end case; + + if (reg_addr /= "00000") then + crc_ck <= '0'; + end if; + + if (reg_addr = "00100") then + cmd_reg_new_flag <= '1'; + else + cmd_reg_new_flag <= '0'; + end if; + + if (crc_en = '1') then + if (reg_addr = "00100" and pack_in_reg(4 downto 0) = "00111") then + crc_curr(31 downto 0) <= X"00000000"; + else + if ( reg_addr /= "00011" and reg_addr /= "00111" and reg_addr /= "10110" and + reg_addr /= "01000" and reg_addr /= "00000") then + crc_input(36 downto 0) := reg_addr(4 downto 0) & pack_in_reg(31 downto 0); + crc_new(31 downto 0) := crc_next(crc_curr, crc_input); + crc_curr(31 downto 0) <= crc_new; + end if; + end if; + end if; + + if (conti_data_cnt = 1) then + conti_data_cnt <= 0; + else + conti_data_cnt <= conti_data_cnt - 1; + end if; + elsif (conti_data_flag = '0' ) then + if ( downcont_cnt >= 1) then + if (crc_en = '1') then + crc_input(36 downto 0) := "00010" & pack_in_reg; + crc_new(31 downto 0) := crc_next(crc_curr, crc_input); + crc_curr(31 downto 0) <= crc_new; + end if; + end if; + + if (pack_in_reg(31 downto 29) = "010" and downcont_cnt = 0 ) then + cmd_rd_flag <= '0'; + cmd_wr_flag <= '0'; + conti_data_flag <= '0'; + conti_data_cnt <= 0; + tmp_v27 := pack_in_reg(26 downto 0); + downcont_cnt <= SLV_TO_INT(SLV=>tmp_v27); + elsif (pack_in_reg(31 downto 29) = "001") then + if (pack_in_reg(28 downto 27) = "01" and downcont_cnt = 0) then + if (pack_in_reg(10 downto 0) /= "00000000000") then + cmd_rd_flag <= '1'; + cmd_wr_flag <= '0'; + rd_data_cnt <= 4; + conti_data_cnt <= 0; + conti_data_flag <= '0'; + rd_reg_addr <= pack_in_reg(17 downto 13); + end if; + elsif (pack_in_reg(28 downto 27) = "10" and downcont_cnt = 0) then + if (pack_in_reg(17 downto 13) = "01111") then + csob_reg <= pack_in_reg; + csbo_cnt <= SLV_TO_INT(SLV=>pack_in_reg(10 downto 0)); + csbo_flag <= '1'; + conti_data_flag <= '0'; + reg_addr <= pack_in_reg(17 downto 13); + cmd_wr_flag <= '1'; + conti_data_cnt <= 0; + elsif (pack_in_reg(10 downto 0) /= "00000000000") then + cmd_rd_flag <= '0'; + cmd_wr_flag <= '1'; + conti_data_flag <= '1'; + tmp_v11 := pack_in_reg(10 downto 0); + conti_data_cnt <= SLV_TO_INT(SLV=>tmp_v11); + reg_addr <= pack_in_reg(17 downto 13); + end if; + else + cmd_wr_flag <= '0'; + conti_data_flag <= '0'; + conti_data_cnt <= 0; + end if; + end if; + cmd_reg_new_flag <= '0'; + crc_ck <= '0'; + end if; -- if (conti_data_flag = '0' ) + if (csbo_cnt /= 0 ) then + if (csbo_flag = '1') then + csbo_cnt <= csbo_cnt - 1; + end if; + else + csbo_flag <= '0'; + end if; + + if (conti_data_cnt = 1 ) then + conti_data_flag <= '0'; + end if; + + end if; + + if (rw_en = '1') then + if (rd_data_cnt = 1) then + rd_data_cnt <= 0; + elsif (rd_data_cnt = 0 and rd_flag = '1') then + cmd_rd_flag <= '0'; + elsif (cmd_rd_flag = '1' and rd_flag = '1') then + rd_data_cnt <= rd_data_cnt - 1; + end if; + + if (downcont_cnt >= 1 and conti_data_flag = '0' and new_data_in_flag = '1' and wr_flag = '1') then + downcont_cnt <= downcont_cnt - 1; + end if; + end if; + + if (crc_ck = '1') then + crc_ck <= '0'; + end if; + end if; + end process; + + rd_back_p : process ( cclk_in, rst_intl) begin + if (rst_intl = '0') then + outbus <= "00000000"; + elsif (rising_edge(cclk_in)) then + if (cmd_rd_flag = '1' and rdwr_b_in = '1' and csi_b_in = '0') then + case (rd_reg_addr) is + when "00000" => if (rd_data_cnt = 1) then + outbus <= crc_reg(7 downto 0); + elsif (rd_data_cnt = 2) then + outbus <= crc_reg(15 downto 8); + elsif (rd_data_cnt = 3) then + outbus <= crc_reg(23 downto 16); + elsif (rd_data_cnt = 4) then + outbus <= crc_reg(31 downto 24); + end if; + when "00111" => if (rd_data_cnt = 1) then + outbus <= stat_reg(7 downto 0); + elsif (rd_data_cnt = 2) then + outbus <= stat_reg(15 downto 8); + elsif (rd_data_cnt = 3) then + outbus <= stat_reg(23 downto 16); + elsif (rd_data_cnt = 4) then + outbus <= stat_reg(31 downto 24); + end if; + when "01100" => if (rd_data_cnt = 1) then + outbus <= idcode_reg(7 downto 0); + elsif (rd_data_cnt = 2) then + outbus <= idcode_reg(15 downto 8); + elsif (rd_data_cnt = 3) then + outbus <= idcode_reg(23 downto 16); + elsif (rd_data_cnt = 4) then + outbus <= idcode_reg(31 downto 24); + end if; + when others => NULL; + end case; + else + outbus <= "00000000"; + end if; + end if; + end process; + + crc_rst <= crc_reset or not rst_intl; + + process ( cclk_in, crc_rst ) begin + if (crc_rst = '1') then + crc_err_flag <= '0'; + elsif (rising_edge(cclk_in)) then + if (crc_ck = '1') then + if (crc_bypass = '1') then + if (crc_reg(15 downto 0) /= X"DEFC") then + crc_err_flag <= '1'; + else + crc_err_flag <= '0'; + end if; + else + if (crc_curr(31 downto 0) /= crc_reg(31 downto 0)) then + crc_err_flag <= '1'; + else + crc_err_flag <= '0'; + end if; + end if; + else + crc_err_flag <= '0'; + end if; + end if; + end process; + + process ( crc_err_flag, rst_intl, bus_sync_flag) begin + if (rst_intl = '0') then + crc_err_flag_reg <= '0'; + elsif (rising_edge(crc_err_flag)) then + crc_err_flag_reg <= '1'; + elsif (rising_edge(bus_sync_flag)) then + crc_err_flag_reg <= '0'; + end if; + end process; + + + process (cclk_in, rst_intl) begin + if (rst_intl = '0') then + startup_set <= '0'; + crc_reset <= '0'; + gsr_cmd_out <= '0'; + shutdown_set <= '0'; + desynch_set <= '0'; + ghigh_b <= '0'; + elsif (rising_edge(cclk_in)) then + if (cmd_reg_new_flag = '1') then + if (cmd_reg = "00011") then + ghigh_b <= '1'; + elsif (cmd_reg = "01000") then + ghigh_b <= '0'; + end if; + + if (cmd_reg = "00101") then + startup_set <= '1'; + end if; + + if (cmd_reg = "00111") then + crc_reset <= '1'; + end if; + + if (cmd_reg = "01010") then + gsr_cmd_out <= '1'; + end if; + + if (cmd_reg = "01011") then + shutdown_set <= '1'; + end if; + + if (cmd_reg = "01101") then + desynch_set <= '1'; + end if; + + if (cmd_reg = "01111") then + iprog_b <= '0'; + i_init_b_cmd <= '0'; + iprog_b <= '1' after cfg_Tprog; + i_init_b_cmd <= '1' after (cfg_Tprog + cfg_Tpl); + end if; + else + startup_set <= '0'; + crc_reset <= '0'; + gsr_cmd_out <= '0'; + shutdown_set <= '0'; + desynch_set <= '0'; + end if; + end if; + end process; + + startup_set_pulse_p : process begin + if (rw_en = '0') then + startup_set_pulse <= "00"; + elsif (rising_edge(startup_set)) then + if (startup_set_pulse = "00") then + startup_set_pulse <= "01"; + end if; + elsif (rising_edge(desynch_set)) then + if (startup_set_pulse = "01") then + startup_set_pulse <= "11"; + wait until (rising_edge(cclk_in )); + startup_set_pulse <= "00"; + end if; + end if; + wait on startup_set, desynch_set, rw_en; + end process; + + + gsr_cmd_out_pulse_p : process begin + if (rw_en = '0') then + gsr_cmd_out_pulse <= '0'; + elsif (rising_edge(gsr_cmd_out)) then + gsr_cmd_out_pulse <= '1'; + wait until (rising_edge(cclk_in )); + wait until (rising_edge(cclk_in )); + gsr_cmd_out_pulse <= '0'; + end if; + wait on gsr_cmd_out, rw_en; + end process; + + + process (ctl0_reg) begin + if (ctl0_reg(9) = '1') then + abort_dis <= '1'; + else + abort_dis <= '0'; + end if; + if (ctl0_reg(3) = '1') then + persist_en <= '1'; + else + persist_en <= '0'; + end if; + if (ctl0_reg(0) = '1') then + gts_usr_b <= '1'; + else + gts_usr_b <= '0'; + end if; + end process; + + process (cor0_reg) + begin + done_cycle_reg <= cor0_reg(14 downto 12); + lock_cycle_reg <= cor0_reg(8 downto 6); + gts_cycle_reg <= cor0_reg(5 downto 3); + gwe_cycle_reg <= cor0_reg(2 downto 0); + + if (cor0_reg(24) = '1') then + done_pin_drv <= '1'; + else + done_pin_drv <= '0'; + end if; + if (cor0_reg(28) = '1') then + crc_bypass <= '1'; + else + crc_bypass <= '0'; + end if; + end process; + + process (cor1_reg) begin + rbcrc_no_pin <= cor1_reg(8); + end process; + + stat_reg(26 downto 25) <= buswidth; + stat_reg(20 downto 18) <= st_state; + stat_reg(16) <= '0'; + stat_reg(15) <= id_error_flag; + stat_reg(14) <= DONE; + stat_reg(13) <= '1' when (done_o /= '0') else '0'; + stat_reg(12) <= INITB; + stat_reg(11) <= mode_sample_flag; + stat_reg(10 downto 8) <= mode_pin_in; + stat_reg(7) <= ghigh_b; + stat_reg(6) <= gwe_out; + stat_reg(5) <= gts_cfg_b; + stat_reg(4) <= eos_startup; + stat_reg(3) <= 'X'; + stat_reg(2) <= dcm_locked; + stat_reg(1) <= 'X'; + stat_reg(0) <= crc_err_flag_reg; + + + st_state_p : process ( cclk_in, rst_intl) begin + if (rst_intl = '0') then + st_state <= STARTUP_PH0; + startup_begin_flag <= '0'; + startup_end_flag <= '0'; + elsif (rising_edge(cclk_in)) then + if (nx_st_state = STARTUP_PH1) then + startup_begin_flag <= '1'; + startup_end_flag <= '0'; + elsif (st_state = STARTUP_PH7) then + startup_end_flag <= '1'; + startup_begin_flag <= '0'; + end if; + if ((lock_cycle_reg = "111") or (dcm_locked = '1') or (st_state /= lock_cycle_reg)) then + st_state <= nx_st_state; + else + st_state <= st_state; + end if; + end if; + end process; + + nx_st_state_p : process (st_state, startup_set_pulse, done_in ) begin + if ((( st_state = done_cycle_reg) and (done_in /= '0')) or ( st_state /= done_cycle_reg)) then + case (st_state) is + when STARTUP_PH0 => if (startup_set_pulse = "11" ) then + nx_st_state <= STARTUP_PH1; + else + nx_st_state <= STARTUP_PH0; + end if; + when STARTUP_PH1 => nx_st_state <= STARTUP_PH2; + + when STARTUP_PH2 => nx_st_state <= STARTUP_PH3; + + when STARTUP_PH3 => nx_st_state <= STARTUP_PH4; + + when STARTUP_PH4 => nx_st_state <= STARTUP_PH5; + + when STARTUP_PH5 => nx_st_state <= STARTUP_PH6; + + when STARTUP_PH6 => nx_st_state <= STARTUP_PH7; + + when STARTUP_PH7 => nx_st_state <= STARTUP_PH0; + when others => NULL; + end case; + end if; + end process; + + start_out_p : process ( cclk_in, rst_intl ) begin + if (rst_intl = '0') then + gwe_out <= '0'; + gts_out <= '1'; + eos_startup <= '0'; + gsr_st_out <= '1'; + done_o <= '0'; + elsif (rising_edge(cclk_in)) then + + if (nx_st_state = done_cycle_reg) then + if (done_in /= '0' or done_pin_drv = '1') then + done_o <= '1'; + else + done_o <= 'H'; + end if; + else + if (done_in /= '0') then + done_o <= '1'; + end if; + end if; + + if (st_state = gwe_cycle_reg and DONE /= '0') then + gwe_out <= '1'; + end if; + if (st_state = gts_cycle_reg and DONE /= '0') then + gts_out <= '0'; + end if; + if (st_state = STARTUP_PH6 and DONE /= '0') then + gsr_st_out <= '0'; + end if; + if (st_state = STARTUP_PH7 and DONE /= '0') then + eos_startup <= '1'; + end if; + end if; + end process; + + gsr_out <= gsr_st_out or gsr_cmd_out; + + process (rdwr_b_in , rst_intl, abort_flag_rst , csi_b_in) + begin + if (rst_intl = '0' or abort_flag_rst = '1' or csi_b_in = '1') then + abort_flag_wr <= '0'; + elsif (rising_edge(rdwr_b_in)) then + if (abort_dis = '0' and csi_b_in = '0') then + if (NOW /= 0 ps) then + abort_flag_wr <= '1'; + assert false report " Warning : RDWRB changes when CS_B low, which causes Configuration abort on SIM_CONFIG_V5." + severity warning; + end if; + else + abort_flag_wr <= '0'; + end if; + end if; + end process; + + + process ( rdwr_b_in, rst_intl, abort_flag_rst, csi_b_in) begin + if (rst_intl = '0' or csi_b_in = '1' or abort_flag_rst = '1') then + abort_flag_rd <= '0'; + elsif (falling_edge(rdwr_b_in)) then + if (abort_dis = '0' and csi_b_in = '0') then + if (NOW /= 0 ps) then + abort_flag_rd <= '1'; + assert false report " Warning : RDWRB changes when CS_B low, which causes Configuration abort on SIM_CONFIG_V5." + severity warning; + end if; + else + abort_flag_rd <= '0'; + end if; + end if; + end process; + + abort_flag <= abort_flag_wr or abort_flag_rd; + + process ( cclk_in, rst_intl) begin + if (rst_intl = '0') then + abort_cnt <= 0; + abort_out_en <= '0'; + elsif (rising_edge(cclk_in)) then + if ( abort_flag = '1' ) then + if (abort_cnt < 4) then + abort_cnt <= abort_cnt + 1; + abort_out_en <= '1'; + else + abort_flag_rst <= '1'; + end if; + else + abort_cnt <= 0; + abort_out_en <= '0'; + abort_flag_rst <= '0'; + end if; + + if (abort_cnt = 0) then + abort_status <= (cfgerr_b_flag & bus_sync_flag & "011111"); + abort_status <= (cfgerr_b_flag & bus_sync_flag & "011111"); + elsif (abort_cnt = 1) then + abort_status <= (cfgerr_b_flag & "1001111"); + elsif (abort_cnt = 2) then + abort_status <= (cfgerr_b_flag & "0001111"); + elsif (abort_cnt = 3) then + abort_status <= (cfgerr_b_flag & "0011111"); + end if; + end if; + end process; + +end SIM_CONFIG_V5_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/rainier/VITAL/Attic/srlc32e.vhd,v 1.3 2005/04/22 20:21:58 yanx Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 32-Bit Shift Register Look-Up-Table with Carry and Clock Enable +-- /___/ /\ Filename : SRLC32E.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:56:58 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/15/04 - Initial version. +-- 04/22/05 - Change input A type from ulogic vector to logic vector. +-- End Revision + +----- CELL SRLC32E ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity SRLC32E is + + generic ( + INIT : bit_vector := X"00000000" + ); + + port ( + Q : out STD_ULOGIC; + Q31 : out STD_ULOGIC; + + A : in STD_LOGIC_VECTOR (4 downto 0); + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + D : in STD_ULOGIC + ); +end SRLC32E; + +architecture SRLC32E_V of SRLC32E is + signal SHIFT_REG : std_logic_vector (31 downto 0) := To_StdLogicVector(INIT); +begin + + Q <= SHIFT_REG(TO_INTEGER(UNSIGNED(A))); + Q31 <= SHIFT_REG(31); + + + WriteBehavior : process + + variable FIRST_TIME : boolean := TRUE; + + begin + + if (FIRST_TIME) then + wait until ((CE = '1' or CE = '0') and + (CLK'last_value = '0' or CLK'last_value = '1') and + (CLK = '0' or CLK = '1')); + FIRST_TIME := FALSE; + end if; + + if (CLK'event AND CLK = '1') then + if (CE = '1') then + SHIFT_REG(31 downto 0) <= (SHIFT_REG(30 downto 0) & D) after 100 ps; + end if ; + end if; + + wait on CLK; + + end process WriteBehavior; +end SRLC32E_V; + + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / User Interface to Global Clock, Reset and 3-State Controls for VIRTEX5 +-- /___/ /\ Filename : STARTUP_VIRTEX5.vhd +-- \ \ / \ Timestamp : Thu Jun 2 10:57:05 PDT 2005 +-- \___\/\___\ +-- +-- Revision: +-- 06/02/05 - Initial version. + +----- CELL STARTUP_VIRTEX5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity STARTUP_VIRTEX5 is + port( + CFGCLK : out std_ulogic; + CFGMCLK : out std_ulogic; + DINSPI : out std_ulogic; + EOS : out std_ulogic; + TCKSPI : out std_ulogic; + + CLK : in std_ulogic := 'X'; + GSR : in std_ulogic := 'X'; + GTS : in std_ulogic := 'X'; + USRCCLKO : in std_ulogic := 'X'; + USRCCLKTS : in std_ulogic := 'X'; + USRDONEO : in std_ulogic := 'X'; + USRDONETS : in std_ulogic := 'X' + ); + +end STARTUP_VIRTEX5; + +architecture STARTUP_VIRTEX5_V of STARTUP_VIRTEX5 is + +begin +end STARTUP_VIRTEX5_V; +------------------------------------------------------------------------------ +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / +-- /___/ /\ Filename : SYSMON.vhd +-- \ \ / \ Timestamp : +-- \___\/\___\ +-- Revision: +-- 03/24/06 - Initial version. +-- 06/26/06 - remove SIM_MONITOR_FILE from file definition (CR 234006). +-- 08/04/06 - Change tmp_dr_ram_out out range from 83 to 87 (CR235676). +-- Add 100 ps delay to output (CR235566). +-- 08/30/06 - GSR only reset DRP port (CR 422678). +-- 09/06/06 - Add internal 1 ns reset at time 0 (422678). +-- 09/07/06 - Match verilog model: alarm_update pulse etc. (CR 424061). +-- 09/26/06 - Update error messages; Make unipolar same as bipolar for external channels; +-- - etc. (CR426629). +-- 10/26/06 - Add tipd for analog channel although not used (CR423564). +-- 10/30/06 - Match HW timing (CR 428185) +-- 12/13/06 - Reset eoc_out_temp1 when calibration channel (CR430923) +-- Change INIT_42 to 0800 (CR 429642). +-- End Revision + +----- CELL SYSMON ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_SIGNED.all; +use IEEE.NUMERIC_STD.all; + +library STD; +use STD.TEXTIO.all; + + + + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity SYSMON is + +generic ( + + + INIT_40 : bit_vector := X"0000"; + INIT_41 : bit_vector := X"0000"; + INIT_42 : bit_vector := X"0800"; + INIT_43 : bit_vector := X"0000"; + INIT_44 : bit_vector := X"0000"; + INIT_45 : bit_vector := X"0000"; + INIT_46 : bit_vector := X"0000"; + INIT_47 : bit_vector := X"0000"; + INIT_48 : bit_vector := X"0000"; + INIT_49 : bit_vector := X"0000"; + INIT_4A : bit_vector := X"0000"; + INIT_4B : bit_vector := X"0000"; + INIT_4C : bit_vector := X"0000"; + INIT_4D : bit_vector := X"0000"; + INIT_4E : bit_vector := X"0000"; + INIT_4F : bit_vector := X"0000"; + INIT_50 : bit_vector := X"0000"; + INIT_51 : bit_vector := X"0000"; + INIT_52 : bit_vector := X"0000"; + INIT_53 : bit_vector := X"0000"; + INIT_54 : bit_vector := X"0000"; + INIT_55 : bit_vector := X"0000"; + INIT_56 : bit_vector := X"0000"; + INIT_57 : bit_vector := X"0000"; + SIM_MONITOR_FILE : string := "design.txt" + ); + +port ( + ALM : out std_logic_vector(2 downto 0); + BUSY : out std_ulogic; + CHANNEL : out std_logic_vector(4 downto 0); + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + EOC : out std_ulogic; + EOS : out std_ulogic; + JTAGBUSY : out std_ulogic; + JTAGLOCKED : out std_ulogic; + JTAGMODIFIED : out std_ulogic; + OT : out std_ulogic; + + CONVST : in std_ulogic; + CONVSTCLK : in std_ulogic; + DADDR : in std_logic_vector(6 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + RESET : in std_ulogic; + VAUXN : in std_logic_vector(15 downto 0); + VAUXP : in std_logic_vector(15 downto 0); + VN : in std_ulogic; + VP : in std_ulogic + ); + + + +end SYSMON; + + +architecture SYSMON_V of SYSMON is + + --------------------------------------------------------------------------- + -- Function SLV_TO_INT converts a std_logic_vector TO INTEGER + --------------------------------------------------------------------------- + function SLV_TO_INT(SLV: in std_logic_vector + ) return integer is + + variable int : integer; + begin + int := 0; + for i in SLV'high downto SLV'low loop + int := int * 2; + if SLV(i) = '1' then + int := int + 1; + end if; + end loop; + return int; + end; + + + --------------------------------------------------------------------------- + -- Function ADDR_IS_VALID checks for the validity of the argument. A FALSE + -- is returned if any argument bit is other than a '0' or '1'. + --------------------------------------------------------------------------- + function ADDR_IS_VALID ( + SLV : in std_logic_vector + ) return boolean is + + variable IS_VALID : boolean := TRUE; + + begin + for I in SLV'high downto SLV'low loop + if (SLV(I) /= '0' AND SLV(I) /= '1') then + IS_VALID := FALSE; + end if; + end loop; + return IS_VALID; + end ADDR_IS_VALID; + + --------------------------------------------------------------------------- + -- Function SLV_TO_STR returns a string version of the std_logic_vector + -- argument. + --------------------------------------------------------------------------- + function SLV_TO_STR ( + SLV : in std_logic_vector + ) return string is + + variable j : integer := SLV'length; + variable STR : string (SLV'length downto 1); + begin + for I in SLV'high downto SLV'low loop + case SLV(I) is + when '0' => STR(J) := '0'; + when '1' => STR(J) := '1'; + when 'X' => STR(J) := 'X'; + when 'U' => STR(J) := 'U'; + when others => STR(J) := 'X'; + end case; + J := J - 1; + end loop; + return STR; + end SLV_TO_STR; + + function int2real( int_in : in integer) return real is + variable conline1 : line; + variable rl_value : real; + variable tmpv1 : real; + variable tmpv2 : real := 1.0; + variable tmpi : integer; + begin + tmpi := int_in; + write (conline1, tmpi); + write (conline1, string'(".0 ")); + write (conline1, tmpv2); + read (conline1, tmpv1); + rl_value := tmpv1; + return rl_value; + DEALLOCATE(conline1); + end int2real; + + + function real2int( real_in : in real) return integer is + variable int_value : integer; + variable tmpt : time; + variable tmpt1 : time; + variable tmpa : real; + variable tmpr : real; + variable int_out : integer; + begin + tmpa := abs(real_in); + tmpt := tmpa * 1 ps; + int_value := (tmpt / 1 ps ) * 1; + tmpt1 := int_value * 1 ps; + tmpr := int2real(int_value); + + if ( real_in < 0.0000) then + if (tmpr > tmpa) then + int_out := 1 - int_value; + else + int_out := -int_value; + end if; + else + if (tmpr > tmpa) then + int_out := int_value - 1; + else + int_out := int_value; + end if; + end if; + return int_out; + end real2int; + + + FUNCTION To_Upper ( CONSTANT val : IN String + ) RETURN STRING IS + VARIABLE result : string (1 TO val'LENGTH) := val; + VARIABLE ch : character; + BEGIN + FOR i IN 1 TO val'LENGTH LOOP + ch := result(i); + EXIT WHEN ((ch = NUL) OR (ch = nul)); + IF ( ch >= 'a' and ch <= 'z') THEN + result(i) := CHARACTER'VAL( CHARACTER'POS(ch) + - CHARACTER'POS('a') + + CHARACTER'POS('A') ); + END IF; + END LOOP; + RETURN result; + END To_Upper; + + procedure get_token(buf : inout LINE; token : out string; + token_len : out integer) + is + variable index : integer := buf'low; + variable tk_index : integer := 0; + variable old_buf : LINE := buf; + BEGIN + while ((index <= buf' high) and ((buf(index) = ' ') or + (buf(index) = HT))) loop + index := index + 1; + end loop; + + while((index <= buf'high) and ((buf(index) /= ' ') and + (buf(index) /= HT))) loop + tk_index := tk_index + 1; + token(tk_index) := buf(index); + index := index + 1; + end loop; + + token_len := tk_index; + + buf := new string'(old_buf(index to old_buf'high)); + old_buf := NULL; + END; + + procedure skip_blanks(buf : inout LINE) + is + variable index : integer := buf'low; + variable old_buf : LINE := buf; + BEGIN + while ((index <= buf' high) and ((buf(index) = ' ') or + (buf(index) = HT))) loop + index := index + 1; + end loop; + buf := new string'(old_buf(index to old_buf'high)); + old_buf := NULL; + END; + + procedure infile_format + is + variable message_line : line; + begin + + write(message_line, string'("***** SYSMON Simulation Analog Data File Format ******")); + writeline(output, message_line); + write(message_line, string'("NAME: design.txt or user file name passed with generic sim_monitor_file")); + writeline(output, message_line); + write(message_line, string'("FORMAT: First line is header line. Valid column name are: TIME TEMP VCCINT VCCAUX VP VN VAUXP[0] VAUXN[0] ....")); + writeline(output, message_line); + write(message_line, string'("TIME must be in first column.")); + writeline(output, message_line); + write(message_line, string'("Time value need to be integer in ns scale")); + writeline(output, message_line); + write(message_line, string'("Analog value need to be real and contain a decimal point '.', zero should be 0.0, 3 should be 3.0")); + writeline(output, message_line); + write(message_line, string'("Each line including header line can not have extra space after the last character/digit.")); + writeline(output, message_line); + write(message_line, string'("Each data line must have same number of columns as the header line.")); + writeline(output, message_line); + write(message_line, string'("Comment line start with -- or //")); + writeline(output, message_line); + write(message_line, string'("Example:")); + writeline(output, message_line); + write(message_line, string'("TIME TEMP VCCINT VP VN VAUXP[0] VAUXN[0]")); + writeline(output, message_line); + write(message_line, string'("000 125.6 1.0 0.7 0.4 0.3 0.6")); + writeline(output, message_line); + write(message_line, string'("200 25.6 0.8 0.5 0.3 0.8 0.2")); + writeline(output, message_line); + + end infile_format; + + type REG_FILE is array (integer range <>) of + std_logic_vector(15 downto 0); + signal dr_sram : REG_FILE(16#40# to 16#57#) := + ( + 16#40# => TO_STDLOGICVECTOR(INIT_40), + 16#41# => TO_STDLOGICVECTOR(INIT_41), + 16#42# => TO_STDLOGICVECTOR(INIT_42), + 16#43# => TO_STDLOGICVECTOR(INIT_43), + 16#44# => TO_STDLOGICVECTOR(INIT_44), + 16#45# => TO_STDLOGICVECTOR(INIT_45), + 16#46# => TO_STDLOGICVECTOR(INIT_46), + 16#47# => TO_STDLOGICVECTOR(INIT_47), + 16#48# => TO_STDLOGICVECTOR(INIT_48), + 16#49# => TO_STDLOGICVECTOR(INIT_49), + 16#4A# => TO_STDLOGICVECTOR(INIT_4A), + 16#4B# => TO_STDLOGICVECTOR(INIT_4B), + 16#4C# => TO_STDLOGICVECTOR(INIT_4C), + 16#4D# => TO_STDLOGICVECTOR(INIT_4D), + 16#4E# => TO_STDLOGICVECTOR(INIT_4E), + 16#4F# => TO_STDLOGICVECTOR(INIT_4F), + 16#50# => TO_STDLOGICVECTOR(INIT_50), + 16#51# => TO_STDLOGICVECTOR(INIT_51), + 16#52# => TO_STDLOGICVECTOR(INIT_52), + 16#53# => TO_STDLOGICVECTOR(INIT_53), + 16#54# => TO_STDLOGICVECTOR(INIT_54), + 16#55# => TO_STDLOGICVECTOR(INIT_55), + 16#56# => TO_STDLOGICVECTOR(INIT_56), + 16#57# => TO_STDLOGICVECTOR(INIT_57) + ); + + signal ot_sf_limit_low_reg : unsigned(15 downto 0) := "1010111001000000"; --X"AE40"; + type adc_statetype is (INIT_STATE, ACQ_STATE, CONV_STATE, + ADC_PRE_END, END_STATE, SINGLE_SEQ_STATE); + type ANALOG_DATA is array (0 to 31) of real; + type DR_data_reg is array (0 to 63) of + std_logic_vector(15 downto 0); + type ACC_ARRAY is array (0 to 31) of integer; + type int_array is array(0 to 31) of integer; + type seq_array is array(32 downto 0 ) of integer; + + signal ot_limit_reg : UNSIGNED(15 downto 0) := "1100011110000000"; + signal adc_state : adc_statetype := CONV_STATE; + signal next_state : adc_statetype; + signal cfg_reg0 : std_logic_vector(15 downto 0) := "0000000000000000"; + signal cfg_reg0_adc : std_logic_vector(15 downto 0) := "0000000000000000"; + signal cfg_reg0_seq : std_logic_vector(15 downto 0) := "0000000000000000"; + signal cfg_reg1 : std_logic_vector(15 downto 0) := "0000000000000000"; + signal cfg_reg1_init : std_logic_vector(15 downto 0) := "0000000000000000"; + signal cfg_reg2 : std_logic_vector(15 downto 0) := "0000000000000000"; + signal seq1_0 : std_logic_vector(1 downto 0) := "00"; + signal curr_seq1_0 : std_logic_vector(1 downto 0) := "00"; + signal curr_seq1_0_lat : std_logic_vector(1 downto 0) := "00"; + signal busy_r : std_ulogic := '0'; + signal busy_r_rst : std_ulogic := '0'; + signal busy_rst : std_ulogic := '0'; + signal busy_conv : std_ulogic := '0'; + signal busy_out_tmp : std_ulogic := '0'; + signal busy_out_dly : std_ulogic := '0'; + signal busy_out_sync : std_ulogic := '0'; + signal busy_out_low_edge : std_ulogic := '0'; + signal shorten_acq : integer := 1; + signal busy_seq_rst : std_ulogic := '0'; + signal busy_sync1 : std_ulogic := '0'; + signal busy_sync2 : std_ulogic := '0'; + signal busy_sync_fall : std_ulogic := '0'; + signal busy_sync_rise : std_ulogic := '0'; + signal cal_chan_update : std_ulogic := '0'; + signal first_cal_chan : std_ulogic := '0'; + signal seq_reset_flag : std_ulogic := '0'; + signal seq_reset_flag_dly : std_ulogic := '0'; + signal seq_reset_dly : std_ulogic := '0'; + signal seq_reset_busy_out : std_ulogic := '0'; + signal rst_in_not_seq : std_ulogic := '0'; + signal rst_in_out : std_ulogic := '0'; + signal rst_lock_early : std_ulogic := '0'; + signal conv_count : integer := 0; + signal acq_count : integer := 1; + signal do_out_rdtmp : std_logic_vector(15 downto 0); + signal rst_in1 : std_ulogic := '0'; + signal rst_in2 : std_ulogic := '0'; + signal int_rst : std_ulogic := '1'; + signal rst_input_t : std_ulogic := '0'; + signal rst_in : std_ulogic := '0'; + signal ot_en : std_logic := '1'; + signal curr_clkdiv_sel : std_logic_vector(7 downto 0) + := "00000000"; + signal curr_clkdiv_sel_int : integer := 0; + signal adcclk : std_ulogic := '0'; + signal adcclk_div1 : std_ulogic := '0'; + signal sysclk : std_ulogic := '0'; + signal curr_adc_resl : std_logic_vector(2 downto 0) := "010"; + signal nx_seq : std_logic_vector(15 downto 0) := "0000000000000000"; + signal curr_seq : std_logic_vector(15 downto 0) := "0000000000000000"; + signal acq_cnt : integer := 0; + signal acq_chan : std_logic_vector(4 downto 0) := "00000"; + signal acq_chan_index : integer := 0; + signal acq_chan_lat : std_logic_vector(4 downto 0) := "00000"; + signal curr_chan : std_logic_vector(4 downto 0) := "00000"; + signal curr_chan_dly : std_logic_vector(4 downto 0) := "00000"; + signal curr_chan_lat : std_logic_vector(4 downto 0) := "00000"; + signal curr_avg_set : std_logic_vector(1 downto 0) := "00"; + signal acq_avg : std_logic_vector(1 downto 0) := "00"; + signal curr_e_c : std_logic:= '0'; + signal acq_e_c : std_logic:= '0'; + signal acq_b_u : std_logic:= '0'; + signal curr_b_u : std_logic:= '0'; + signal acq_acqsel : std_logic:= '0'; + signal curr_acq : std_logic:= '0'; + signal seq_cnt : integer := 0; + signal busy_rst_cnt : integer := 0; + signal adc_s1_flag : std_ulogic := '0'; + signal adc_convst : std_ulogic := '0'; + signal conv_start : std_ulogic := '0'; + signal conv_end : std_ulogic := '0'; + signal eos_en : std_ulogic := '0'; + signal eos_tmp_en : std_ulogic := '0'; + signal seq_cnt_en : std_ulogic := '0'; + signal eoc_en : std_ulogic := '0'; + signal eoc_en_delay : std_ulogic := '0'; + signal eoc_out_tmp : std_ulogic := '0'; + signal eos_out_tmp : std_ulogic := '0'; + signal eoc_out_tmp1 : std_ulogic := '0'; + signal eos_out_tmp1 : std_ulogic := '0'; + signal eoc_up_data : std_ulogic := '0'; + signal eoc_up_alarm : std_ulogic := '0'; + signal conv_time : integer := 17; + signal conv_time_cal_1 : integer := 69; + signal conv_time_cal : integer := 69; + signal conv_result : std_logic_vector(15 downto 0) := "0000000000000000"; + signal conv_result_reg : std_logic_vector(15 downto 0) := "0000000000000000"; + signal data_written : std_logic_vector(15 downto 0) := "0000000000000000"; + signal conv_result_int : integer := 0; + signal conv_result_int_resl : integer := 0; + signal analog_in_uni : ANALOG_DATA :=(others=>0.0); + signal analog_in_diff : ANALOG_DATA :=(others=>0.0); + signal analog_in : ANALOG_DATA :=(others=>0.0); + signal analog_in_comm : ANALOG_DATA :=(others=>0.0); + signal chan_val_tmp : ANALOG_DATA :=(others=>0.0); + signal chan_valn_tmp : ANALOG_DATA :=(others=>0.0); + signal data_reg : DR_data_reg + :=( 36 to 39 => "1111111111111111", + others=>"0000000000000000"); + signal tmp_data_reg_out : std_logic_vector(15 downto 0) := "0000000000000000"; + signal tmp_dr_sram_out : std_logic_vector(15 downto 0) := "0000000000000000"; + signal seq_chan_reg1 : std_logic_vector(15 downto 0) := "0000000000000000"; + signal seq_chan_reg2 : std_logic_vector(15 downto 0) := "0000000000000000"; + signal seq_acq_reg1 : std_logic_vector(15 downto 0) := "0000000000000000"; + signal seq_acq_reg2 : std_logic_vector(15 downto 0) := "0000000000000000"; + signal seq_avg_reg1 : std_logic_vector(15 downto 0) := "0000000000000000"; + signal seq_avg_reg2 : std_logic_vector(15 downto 0) := "0000000000000000"; + signal seq_du_reg1 : std_logic_vector(15 downto 0) := "0000000000000000"; + signal seq_du_reg2 : std_logic_vector(15 downto 0) := "0000000000000000"; + signal seq_count : integer := 1; + signal seq_count_en : std_ulogic := '0'; + signal conv_acc : ACC_ARRAY :=(others=>0); + signal conv_avg_count : ACC_ARRAY :=(others=>0); + signal conv_acc_vec : std_logic_vector (20 downto 1); + signal conv_acc_result : std_logic_vector(15 downto 0); + signal seq_status_avg : integer := 0; + signal curr_chan_index : integer := 0; + signal curr_chan_index_lat : integer := 0; + signal conv_avg_cnt : int_array :=(others=>0); + signal analog_mux_in : real := 0.0; + signal adc_temp_result : real := 0.0; + signal adc_intpwr_result : real := 0.0; + signal adc_ext_result : real := 0.0; + signal seq_reset : std_ulogic := '0'; + signal seq_en : std_ulogic := '0'; + signal seq_en_drp : std_ulogic := '0'; + signal seq_en_init : std_ulogic := '0'; + signal seq_en_dly : std_ulogic := '0'; + signal seq_num : integer := 0; + signal seq_mem : seq_array :=(others=>0); + signal adc_seq_reset : std_ulogic := '0'; + signal adc_seq_en : std_ulogic := '0'; + signal adc_seq_reset_dly : std_ulogic := '0'; + signal adc_seq_en_dly : std_ulogic := '0'; + signal adc_seq_reset_hold : std_ulogic := '0'; + signal adc_seq_en_hold : std_ulogic := '0'; + signal rst_lock : std_ulogic := '1'; + signal sim_file_flag : std_ulogic := '0'; + signal gsr_in : std_ulogic := '0'; + signal convstclk_in : std_ulogic := '0'; + signal convst_raw_in : std_ulogic := '0'; + signal convst_in : std_ulogic := '0'; + signal dclk_in : std_ulogic := '0'; + signal den_in : std_ulogic := '0'; + signal rst_input : std_ulogic := '0'; + signal dwe_in : std_ulogic := '0'; + signal di_in : std_logic_vector(15 downto 0) := "0000000000000000"; + signal daddr_in : std_logic_vector(6 downto 0) := "0000000"; + signal daddr_in_lat : std_logic_vector(6 downto 0) := "0000000"; + signal daddr_in_lat_int : integer := 0; + signal drdy_out_tmp1 : std_ulogic := '0'; + signal drdy_out_tmp2 : std_ulogic := '0'; + signal drdy_out_tmp3 : std_ulogic := '0'; + signal drp_update : std_ulogic := '0'; + signal alarm_en : std_logic_vector(2 downto 0) := "111"; + signal alarm_update : std_ulogic := '0'; + signal adcclk_tmp : std_ulogic := '0'; + signal ot_out_reg : std_ulogic := '0'; + signal alarm_out_reg : std_logic_vector(2 downto 0) := "000"; + signal conv_end_reg_read : std_logic_vector(3 downto 0) := "0000"; + signal busy_reg_read : std_ulogic := '0'; + signal single_chan_conv_end : std_ulogic := '0'; + signal first_acq : std_ulogic := '1'; + signal conv_start_cont : std_ulogic := '0'; + signal conv_start_sel : std_ulogic := '0'; + signal reset_conv_start : std_ulogic := '0'; + signal reset_conv_start_tmp : std_ulogic := '0'; + signal busy_r_rst_done : std_ulogic := '0'; + signal op_count : integer := 15; + + +-- Input/Output Pin signals + + signal DI_ipd : std_logic_vector(15 downto 0); + signal DADDR_ipd : std_logic_vector(6 downto 0); + signal DEN_ipd : std_ulogic; + signal DWE_ipd : std_ulogic; + signal DCLK_ipd : std_ulogic; + signal CONVSTCLK_ipd : std_ulogic; + signal RESET_ipd : std_ulogic; + signal CONVST_ipd : std_ulogic; + + signal do_out : std_logic_vector(15 downto 0) := "0000000000000000"; + signal drdy_out : std_ulogic := '0'; + signal ot_out : std_ulogic := '0'; + signal alarm_out : std_logic_vector(2 downto 0) := "000"; + signal channel_out : std_logic_vector(4 downto 0) := "00000"; + signal eoc_out : std_ulogic := '0'; + signal eos_out : std_ulogic := '0'; + signal busy_out : std_ulogic := '0'; + + signal DI_dly : std_logic_vector(15 downto 0); + signal DADDR_dly : std_logic_vector(6 downto 0); + signal DEN_dly : std_ulogic; + signal DWE_dly : std_ulogic; + signal DCLK_dly : std_ulogic; + signal CONVSTCLK_dly : std_ulogic; + signal RESET_dly : std_ulogic; + signal CONVST_dly : std_ulogic; + +begin + + BUSY <= busy_out after 100 ps; + DRDY <= drdy_out after 100 ps; + EOC <= eoc_out after 100 ps; + EOS <= eos_out after 100 ps; + OT <= ot_out after 100 ps; + DO <= do_out after 100 ps; + CHANNEL <= channel_out after 100 ps; + ALM <= alarm_out after 100 ps; + + convst_raw_in <= CONVST; + convstclk_in <= CONVSTCLK; + dclk_in <= DCLK; + den_in <= DEN; + rst_input <= RESET; + dwe_in <= DWE; + di_in <= Di; + daddr_in <= DADDR; + + gsr_in <= GSR; + convst_in <= '1' when (convst_raw_in = '1' or convstclk_in = '1') else '0'; + JTAGLOCKED <= '0'; + JTAGMODIFIED <= '0'; + JTAGBUSY <= '0'; + + DEFAULT_CHECK : process + variable init40h_tmp : std_logic_vector(15 downto 0); + variable init41h_tmp : std_logic_vector(15 downto 0); + variable init42h_tmp : std_logic_vector(15 downto 0); + variable init4eh_tmp : std_logic_vector(15 downto 0); + variable init40h_tmp_chan : integer; + variable init42h_tmp_clk : integer; + variable tmp_value : std_logic_vector(7 downto 0); + begin + init40h_tmp := TO_STDLOGICVECTOR(INIT_40); + init40h_tmp_chan := SLV_TO_INT(SLV=>init40h_tmp(4 downto 0)); + init41h_tmp := TO_STDLOGICVECTOR(INIT_41); + init42h_tmp := TO_STDLOGICVECTOR(INIT_42); + tmp_value := init42h_tmp(15 downto 8); + init42h_tmp_clk := SLV_TO_INT(SLV=>tmp_value); + init4eh_tmp := TO_STDLOGICVECTOR(INIT_4E); + + if ((init41h_tmp(13 downto 12)="11") and (init40h_tmp(8)='1') and (init40h_tmp_chan /= 3 ) and (init40h_tmp_chan < 16)) then + assert false report " Attribute Syntax warning : The attribute INIT_40 bit[8] must be set to 0 on SYSMON. Long acquistion mode is only allowed for external channels." + severity warning; + end if; + + if ((init41h_tmp(13 downto 12) /="11") and (init4eh_tmp(10 downto 0) /= "00000000000") and (init4eh_tmp(15 downto 12) /= "0000")) then + assert false report " Attribute Syntax warning : The attribute INIT_4E Bit[15:12] and bit[10:0] must be set to 0. Long acquistion mode is only allowed for external channels." + severity warning; + end if; + + if ((init41h_tmp(13 downto 12)="11") and (init40h_tmp(9) = '1') and (init40h_tmp(4 downto 0) /= "00011") and (init40h_tmp_chan < 16)) then + assert false report " Attribute Syntax warning : The attribute INIT_40 bit[9] must be set to 0 on SYSMON. Event mode timing can only be used with external channels, and only in single channel mode." + severity warning; + end if; + + if ((init41h_tmp(13 downto 12)="11") and (init40h_tmp(13 downto 12) /= "00") and (INIT_48 /=X"0000") and (INIT_49 /= X"0000")) then + assert false report " Attribute Syntax warning : The attribute INIT_48 and INIT_49 must be set to 0000h in single channel mode and averaging enabled." + severity warning; + end if; + + if (init42h_tmp(1 downto 0) /= "00") then + assert false report + " Attribute Syntax Error : The attribute INIT_42 Bit[1:0] must be set to 00." + severity Error; + end if; + + if (init42h_tmp_clk < 8) then + assert false report + " Attribute Syntax Error : The attribute INIT_42 Bit[15:8] is the ADC Clock divider and must be equal or greater than 8." + severity failure; + end if; + + if (INIT_43 /= "0000000000000000") then + assert false report + " Warning : The attribute INIT_43 must be set to 0000." + severity warning; + end if; + + if (INIT_44 /= "0000000000000000") then + assert false report + " Warning : The attribute INIT_44 must be set to 0000." + severity warning; + end if; + + if (INIT_45 /= "0000000000000000") then + assert false report + " Warning : The attribute INIT_45 must be set to 0000." + severity warning; + end if; + + if (INIT_46 /= "0000000000000000") then + assert false report + " Warning : The attribute INIT_46 must be set to 0000." + severity warning; + end if; + + if (INIT_47 /= "0000000000000000") then + assert false report + " Warning : The attribute INIT_47 must be set to 0000." + severity warning; + end if; + + wait; + end process; + + + curr_chan_index <= SLV_TO_INT(curr_chan); + curr_chan_index_lat <= SLV_TO_INT(curr_chan_lat); + + CHEK_COMM_P : process( busy_r ) + variable Message : line; + begin + if (busy_r'event and busy_r = '1' ) then + if (rst_in = '0' and acq_b_u = '0' and ((acq_chan_index = 3) or (acq_chan_index >= 16 and acq_chan_index <= 31))) then + if ( chan_valn_tmp(acq_chan_index) > chan_val_tmp(acq_chan_index)) then + Write ( Message, string'("Input File Warning: The N input for external channel ")); + Write ( Message, acq_chan_index); + Write ( Message, string'(" must be smaller than P input when in unipolar mode (P=")); + Write ( Message, chan_val_tmp(acq_chan_index)); + Write ( Message, string'(" N=")); + Write ( Message, chan_valn_tmp(acq_chan_index)); + Write ( Message, string'(") for SYSMON.")); + assert false report Message.all severity warning; + DEALLOCATE (Message); + end if; + + if (( chan_valn_tmp(acq_chan_index) > 0.5) or (chan_valn_tmp(acq_chan_index) < 0.0)) then + Write ( Message, string'("Input File Warning: The N input for external channel ")); + Write ( Message, acq_chan_index); + Write ( Message, string'(" should be between 0V to 0.5V when in unipolar mode (N=")); + Write ( Message, chan_valn_tmp(acq_chan_index)); + Write ( Message, string'(") for SYSMON.")); + assert false report Message.all severity warning; + DEALLOCATE (Message); + end if; + + end if; + end if; + end process; + + busy_mkup_p : process( dclk_in, rst_in_out) + begin + if (rst_in_out = '1') then + busy_rst <= '1'; + rst_lock <= '1'; + rst_lock_early <= '1'; + busy_rst_cnt <= 0; + elsif (rising_edge(dclk_in)) then + if (rst_lock = '1') then + if (busy_rst_cnt < 29) then + busy_rst_cnt <= busy_rst_cnt + 1; + if ( busy_rst_cnt = 26) then + rst_lock_early <= '0'; + end if; + else + busy_rst <= '0'; + rst_lock <= '0'; + end if; + end if; + end if; + end process; + + busy_out_p : process (busy_rst, busy_conv, rst_lock) + begin + if (rst_lock = '1') then + busy_out <= busy_rst; + else + busy_out <= busy_conv; + end if; + end process; + + busy_conv_p : process (dclk_in, rst_in) + begin + if (rst_in = '1') then + busy_conv <= '0'; + cal_chan_update <= '0'; + elsif (rising_edge(dclk_in)) then + if (seq_reset_flag = '1' and curr_clkdiv_sel_int <= 3) then + busy_conv <= busy_seq_rst; + elsif (busy_sync_fall = '1') then + busy_conv <= '0'; + elsif (busy_sync_rise = '1') then + busy_conv <= '1'; + end if; + + if (conv_count = 21 and curr_chan = "01000" ) then + cal_chan_update <= '1'; + else + cal_chan_update <= '0'; + end if; + end if; + end process; + + busy_sync_p : process (dclk_in, rst_lock) + begin + if (rst_lock = '1') then + busy_sync1 <= '0'; + busy_sync2 <= '0'; + elsif (rising_edge (dclk_in)) then + busy_sync1 <= busy_r; + busy_sync2 <= busy_sync1; + end if; + end process; + + busy_sync_fall <= '1' when (busy_r = '0' and busy_sync1 = '1') else '0'; + busy_sync_rise <= '1' when (busy_sync1 = '1' and busy_sync2 = '0') else '0'; + + busy_seq_rst_p : process + variable tmp_uns_div : unsigned(7 downto 0); + begin + if (falling_edge(busy_out) or rising_edge(busy_r)) then + if (seq_reset_flag = '1' and seq1_0 = "00" and curr_clkdiv_sel_int <= 3) then + wait until (rising_edge(dclk_in)); + wait until (rising_edge(dclk_in)); + wait until (rising_edge(dclk_in)); + wait until (rising_edge(dclk_in)); + wait until (rising_edge(dclk_in)); + busy_seq_rst <= '1'; + elsif (seq_reset_flag = '1' and seq1_0 /= "00" and curr_clkdiv_sel_int <= 3) then + wait until (rising_edge(dclk_in)); + wait until (rising_edge(dclk_in)); + wait until (rising_edge(dclk_in)); + wait until (rising_edge(dclk_in)); + wait until (rising_edge(dclk_in)); + wait until (rising_edge(dclk_in)); + wait until (rising_edge(dclk_in)); + busy_seq_rst <= '1'; + else + busy_seq_rst <= '0'; + end if; + end if; + wait on busy_out, busy_r; + end process; + + chan_out_p : process(busy_out, rst_in_out, cal_chan_update) + begin + if (rst_in_out = '1') then + channel_out <= "00000"; + elsif (rising_edge(busy_out) or rising_edge(cal_chan_update)) then + if ( busy_out = '1' and cal_chan_update = '1') then + channel_out <= "01000"; + end if; + elsif (falling_edge(busy_out)) then + channel_out <= curr_chan; + curr_chan_lat <= curr_chan; + end if; + end process; + + INT_RST_GEN_P : process + begin + int_rst <= '1'; + wait until (rising_edge(dclk_in)); + wait until (rising_edge(dclk_in)); + int_rst <= '0'; + wait; + end process; + + rst_input_t <= rst_input or int_rst; + + RST_DE_SYNC_P: process(dclk_in, rst_input_t) + begin + if (rst_input_t = '1') then + rst_in2 <= '1'; + rst_in1 <= '1'; + elsif (dclk_in'event and dclk_in='1') then + rst_in2 <= rst_in1; + rst_in1 <= rst_input_t; + end if; + end process; + + rst_in_not_seq <= rst_in2; + rst_in <= rst_in2 or seq_reset_dly; + rst_in_out <= rst_in2 or seq_reset_busy_out; + + seq_reset_dly_p : process + begin + if (rising_edge(seq_reset)) then + wait until rising_edge(dclk_in); + wait until rising_edge(dclk_in); + seq_reset_dly <= '1'; + wait until rising_edge(dclk_in); + wait until falling_edge(dclk_in); + seq_reset_busy_out <= '1'; + wait until rising_edge(dclk_in); + wait until rising_edge(dclk_in); + wait until rising_edge(dclk_in); + seq_reset_dly <= '0'; + seq_reset_busy_out <= '0'; + end if; + wait on seq_reset, dclk_in; + end process; + + + seq_reset_flag_p : process (seq_reset_dly, busy_r) + begin + if (rising_edge(seq_reset_dly)) then + seq_reset_flag <= '1'; + elsif (rising_edge(busy_r)) then + seq_reset_flag <= '0'; + end if; + end process; + + seq_reset_flag_dly_p : process (seq_reset_flag, busy_out) + begin + if (rising_edge(seq_reset_flag)) then + seq_reset_flag_dly <= '1'; + elsif (rising_edge(busy_out)) then + seq_reset_flag_dly <= '0'; + end if; + end process; + + first_cal_chan_p : process ( busy_out) + begin + if (rising_edge(busy_out )) then + if (seq_reset_flag_dly = '1' and acq_chan = "01000" and seq1_0 = "00") then + first_cal_chan <= '1'; + else + first_cal_chan <= '0'; + end if; + end if; + end process; + + + ADC_SM: process (adcclk, rst_in, sim_file_flag) + begin + if (sim_file_flag = '1') then + adc_state <= INIT_STATE; + elsif (rst_in = '1' or rst_lock_early = '1') then + adc_state <= INIT_STATE; + elsif (adcclk'event and adcclk = '1') then + adc_state <= next_state; + end if; + end process; + + next_state_p : process (adc_state, eos_en, conv_start , conv_end, curr_seq1_0_lat) + begin + case (adc_state) is + when INIT_STATE => next_state <= ACQ_STATE; + + when ACQ_STATE => if (conv_start = '1') then + next_state <= CONV_STATE; + else + next_state <= ACQ_STATE; + end if; + + when CONV_STATE => if (conv_end = '1') then + next_state <= END_STATE; + else + next_state <= CONV_STATE; + end if; + + when END_STATE => if (curr_seq1_0_lat = "01") then + if (eos_en = '1') then + next_state <= SINGLE_SEQ_STATE; + else + next_state <= ACQ_STATE; + end if; + else + next_state <= ACQ_STATE; + end if; + + when SINGLE_SEQ_STATE => next_state <= INIT_STATE; + + when others => next_state <= INIT_STATE; + end case; + end process; + + seq_en_init_p : process + begin + seq_en_init <= '0'; + if (cfg_reg1_init(13 downto 12) /= "11" ) then + wait for 20 ps; + seq_en_init <= '1'; + wait for 150 ps; + seq_en_init <= '0'; + end if; + wait; + end process; + + + seq_en <= seq_en_init or seq_en_drp; + + DRPORT_DO_OUT_P : process(dclk_in, gsr_in) + variable message : line; + variable di_str : string (16 downto 1); + variable daddr_str : string (7 downto 1); + variable di_40 : std_logic_vector(4 downto 0); + variable valid_daddr : boolean := false; + variable address : integer; + variable tmp_value : integer := 0; + variable tmp_value1 : std_logic_vector (7 downto 0); + begin + + if (gsr_in = '1') then + drdy_out <= '0'; + daddr_in_lat <= "0000000"; + do_out <= "0000000000000000"; + elsif (rising_edge(dclk_in)) then + if (den_in = '1') then + valid_daddr := addr_is_valid(daddr_in); + if (valid_daddr) then + address := slv_to_int(daddr_in); + if ( (address > 88 or + (address >= 13 and address <= 15) + or (address >= 39 and address <= 63))) then + Write ( Message, string'(" Invalid Input Warning : The DADDR ")); + Write ( Message, string'(SLV_TO_STR(daddr_in))); + Write ( Message, string'(" is not defined. The data in this location is invalid.")); + assert false report Message.all severity warning; + DEALLOCATE(Message); + end if; + end if; + + if (drdy_out_tmp1 = '1' or drdy_out_tmp2 = '1' or drdy_out_tmp3 = '1') then + drdy_out_tmp1 <= '0'; + else + drdy_out_tmp1 <= '1'; + end if; + daddr_in_lat <= daddr_in; + else + drdy_out_tmp1 <= '0'; + end if; + + drdy_out_tmp2 <= drdy_out_tmp1; + drdy_out_tmp3 <= drdy_out_tmp2; + drdy_out <= drdy_out_tmp3; + + if (drdy_out_tmp3 = '1') then + do_out <= do_out_rdtmp; + end if; + +-- write all available daddr addresses + + if (dwe_in = '1' and den_in = '1') then + if (valid_daddr) then + dr_sram(address) <= di_in; + end if; + + if ( address = 42 and di_in( 1 downto 0) /= "00") then + Write ( Message, string'(" Invalid Input Error : The DI bit[1:0] ")); + Write ( Message, bit_vector'(TO_BITVECTOR(di_in(1 downto 0)))); + Write ( Message, string'(" at DADDR ")); + Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in))); + Write ( Message, string'(" of SYSMON is invalid. These must be set to 00.")); + assert false report Message.all severity error; + end if; + + tmp_value1 := di_in(15 downto 8) ; + tmp_value := SLV_TO_INT(SLV=>tmp_value1); + + if ( address = 42 and tmp_value < 8) then + Write ( Message, string'(" Invalid Input Error : The DI bit[15:8] ")); + Write ( Message, bit_vector'(TO_BITVECTOR(di_in(15 downto 8)))); + Write ( Message, string'(" at DADDR ")); + Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in))); + Write ( Message, string'(" of SYSMON is invalid. Bit[15:8] of Control Register 42h is the ADC Clock divider and must be equal or greater than 8.")); + assert false report Message.all severity failure; + end if; + + if ( (address >= 43 and address <= 47) and di_in(15 downto 0) /= "0000000000000000") then + Write ( Message, string'(" Invalid Input Error : The DI value ")); + Write ( Message, bit_vector'(TO_BITVECTOR(di_in))); + Write ( Message, string'(" at DADDR ")); + Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in))); + Write ( Message, string'(" of SYSMON is invalid. These must be set to 0000.")); + assert false report Message.all severity error; + DEALLOCATE(Message); + end if; + + tmp_value := SLV_TO_INT(SLV=>di_in(4 downto 0)); + + if (address = 40) then + + if (((tmp_value = 6) or ( tmp_value = 7) or ((tmp_value >= 10) and (tmp_value <= 15)))) then + Write ( Message, string'(" Invalid Input Warning : The DI bit[4:0] at DADDR ")); + Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in))); + Write ( Message, string'(" is ")); + Write ( Message, bit_vector'(TO_BITVECTOR(di_in(4 downto 0)))); + Write ( Message, string'(", which is invalid analog channel.")); + assert false report Message.all severity warning; + DEALLOCATE(Message); + end if; + + if ((cfg_reg1(13 downto 12)="11") and (di_in(8)='1') and (tmp_value /= 3) and (tmp_value < 16)) then + Write ( Message, string'(" Invalid Input Warning : The DI value is ")); + Write ( Message, bit_vector'(TO_BITVECTOR(di_in))); + Write ( Message, string'(" at DADDR ")); + Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in))); + Write ( Message, string'(". Bit[8] of DI must be set to 0. Long acquistion mode is only allowed for external channels.")); + assert false report Message.all severity warning; + DEALLOCATE(Message); + end if; + + if ((cfg_reg1(13 downto 12)="11") and (di_in(9)='1') and (tmp_value /= 3) and (tmp_value < 16)) then + Write ( Message, string'(" Invalid Input Warning : The DI value is ")); + Write ( Message, bit_vector'(TO_BITVECTOR(di_in))); + Write ( Message, string'(" at DADDR ")); + Write ( Message, bit_vector'(TO_BITVECTOR(daddr_in))); + Write ( Message, string'(". Bit[9] of DI must be set to 0. Event mode timing can only be used with external channels.")); + assert false report Message.all severity warning; + DEALLOCATE(Message); + end if; + + if ((cfg_reg1(13 downto 12)="11") and (di_in(13 downto 12)/="00") and (seq_chan_reg1 /= X"0000") and (seq_chan_reg2 /= X"0000")) then + Write ( Message, string'(" Invalid Input Warning : The Control Regiter 48h and 49h are ")); + Write ( Message, bit_vector'(TO_BITVECTOR(seq_chan_reg1))); + Write ( Message, string'(" and ")); + Write ( Message, bit_vector'(TO_BITVECTOR(seq_chan_reg2))); + Write ( Message, string'(". Those registers should be set to 0000h in single channel mode and averaging enabled.")); + assert false report Message.all severity warning; + DEALLOCATE(Message); + end if; + end if; + + tmp_value := SLV_TO_INT(SLV=>cfg_reg0(4 downto 0)); + + if (address = 41) then + + if ((di_in(13 downto 12)="11") and (cfg_reg0(8)='1') and (tmp_value /= 3) and (tmp_value < 16)) then + Write ( Message, string'(" Invalid Input Warning : The Control Regiter 40h value is ")); + Write ( Message, bit_vector'(TO_BITVECTOR(cfg_reg0))); + Write ( Message, string'(". Bit[8] of Control Regiter 40h must be set to 0. Long acquistion mode is only allowed for external channels.")); + assert false report Message.all severity warning; + DEALLOCATE(Message); + end if; + + if ((di_in(13 downto 12)="11") and (cfg_reg0(9)='1') and (tmp_value /= 3) and (tmp_value < 16)) then + Write ( Message, string'(" Invalid Input Warning : The Control Regiter 40h value is ")); + Write ( Message, bit_vector'(TO_BITVECTOR(cfg_reg0))); + Write ( Message, string'(". Bit[9] of Control Regiter 40h must be set to 0. Event mode timing can only be used with external channels.")); + assert false report Message.all severity warning; + DEALLOCATE(Message); + end if; + + if ((di_in(13 downto 12) /= "11") and (seq_acq_reg1(10 downto 0) /= "00000000000") and (seq_acq_reg1(15 downto 12) /= "0000")) then + Write ( Message, string'(" Invalid Input Warning : The Control Regiter 4Eh is ")); + Write ( Message, bit_vector'(TO_BITVECTOR(seq_acq_reg1))); + Write ( Message, string'(". Bit[15:12] and bit[10:0] of this register must be set to 0. Long acquistion mode is only allowed for external channels.")); + assert false report Message.all severity warning; + DEALLOCATE(Message); + end if; + + if ((di_in(13 downto 12) = "11") and (cfg_reg0(13 downto 12) /= "00") and (seq_chan_reg1 /= X"0000") and (seq_chan_reg2 /= X"0000")) then + Write ( Message, string'(" Invalid Input Warning : The Control Regiter 48h and 49h are ")); + Write ( Message, bit_vector'(TO_BITVECTOR(seq_chan_reg1))); + Write ( Message, string'(" and ")); + Write ( Message, bit_vector'(TO_BITVECTOR(seq_chan_reg2))); + Write ( Message, string'(". Those registers should be set to 0000h in single channel mode and averaging enabled.")); + assert false report Message.all severity warning; + DEALLOCATE(Message); + end if; + end if; + end if; + + + + if (daddr_in = "1000001" ) then + if (dwe_in = '1' and den_in = '1') then + + if (di_in(13 downto 12) /= cfg_reg1(13 downto 12)) then + seq_reset <= '1'; + else + seq_reset <= '0'; + end if; + + if (di_in(13 downto 12) /= "11" ) then + seq_en_drp <= '1'; + else + seq_en_drp <= '0'; + end if; + else + seq_reset <= '0'; + seq_en_drp <= '0'; + end if; + else + seq_reset <= '0'; + seq_en_drp <= '0'; + end if; + end if; + end process; + + tmp_dr_sram_out <= dr_sram(daddr_in_lat_int) when (daddr_in_lat_int >= 64 and + daddr_in_lat_int <= 87) else "0000000000000000"; + + tmp_data_reg_out <= data_reg(daddr_in_lat_int) when (daddr_in_lat_int >= 0 and + daddr_in_lat_int <= 38) else "0000000000000000"; + + do_out_rdtmp_p : process( daddr_in_lat, tmp_data_reg_out, tmp_dr_sram_out ) + variable Message : line; + variable valid_daddr : boolean := false; + begin + valid_daddr := addr_is_valid(daddr_in_lat); + daddr_in_lat_int <= slv_to_int(daddr_in_lat); + if (valid_daddr) then + if ((daddr_in_lat_int > 88) or + (daddr_in_lat_int >= 13 and daddr_in_lat_int <= 15) + or (daddr_in_lat_int >= 39 and daddr_in_lat_int <= 63)) then + do_out_rdtmp <= "XXXXXXXXXXXXXXXX"; + end if; + + if ((daddr_in_lat_int >= 0 and daddr_in_lat_int <= 12) or + (daddr_in_lat_int >= 16 and daddr_in_lat_int <= 38)) then + + do_out_rdtmp <= tmp_data_reg_out; + + elsif (daddr_in_lat_int >= 64 and daddr_in_lat_int <= 87) then + + do_out_rdtmp <= tmp_dr_sram_out; + end if; + end if; + end process; + +-- end DRP RAM + + + cfg_reg0 <= dr_sram(16#40#); + cfg_reg1 <= dr_sram(16#41#); + cfg_reg2 <= dr_sram(16#42#); + seq_chan_reg1 <= dr_sram(16#48#); + seq_chan_reg2 <= dr_sram(16#49#); + seq_avg_reg1 <= dr_sram(16#4A#); + seq_avg_reg2 <= dr_sram(16#4B#); + seq_du_reg1 <= dr_sram(16#4C#); + seq_du_reg2 <= dr_sram(16#4D#); + seq_acq_reg1 <= dr_sram(16#4E#); + seq_acq_reg2 <= dr_sram(16#4F#); + + seq1_0 <= cfg_reg1(13 downto 12); + + drp_update_p : process + variable seq_bits : std_logic_vector( 1 downto 0); + begin + if (rst_in = '1') then + wait until (rising_edge(dclk_in)); + wait until (rising_edge(dclk_in)); + seq_bits := seq1_0; + elsif (rising_edge(drp_update)) then + seq_bits := curr_seq1_0; + end if; + + if (rising_edge(drp_update) or (rst_in = '1')) then + if (seq_bits = "00") then + alarm_en <= "000"; + ot_en <= '1'; + else + ot_en <= not cfg_reg1(0); + alarm_en <= not cfg_reg1(3 downto 1); + end if; + end if; + wait on drp_update, rst_in; + end process; + + +-- Clock divider, generate and adcclk + + sysclk_p : process(dclk_in) + begin + if (rising_edge(dclk_in)) then + sysclk <= not sysclk; + end if; + end process; + + + curr_clkdiv_sel_int_p : process (curr_clkdiv_sel) + begin + curr_clkdiv_sel_int <= SLV_TO_INT(curr_clkdiv_sel); + end process; + + clk_count_p : process(dclk_in) + variable clk_count : integer := -1; + begin + + if (rising_edge(dclk_in)) then + if (curr_clkdiv_sel_int > 2 ) then + if (clk_count >= curr_clkdiv_sel_int - 1) then + clk_count := 0; + else + clk_count := clk_count + 1; + end if; + + if (clk_count > (curr_clkdiv_sel_int/2) - 1) then + adcclk_tmp <= '1'; + else + adcclk_tmp <= '0'; + end if; + else + adcclk_tmp <= not adcclk_tmp; + end if; + end if; + end process; + + curr_clkdiv_sel <= cfg_reg2(15 downto 8); + adcclk_div1 <= '0' when (curr_clkdiv_sel_int > 1) else '1'; + adcclk <= not sysclk when adcclk_div1 = '1' else adcclk_tmp; + +-- end clock divider + +-- latch configuration registers + acq_latch_p : process ( seq1_0, adc_s1_flag, curr_seq, cfg_reg0_adc, rst_in) + begin + if ((seq1_0 = "01" and adc_s1_flag = '0') or seq1_0 = "10") then + acq_acqsel <= curr_seq(8); + elsif (seq1_0 = "11") then + acq_acqsel <= cfg_reg0_adc(8); + else + acq_acqsel <= '0'; + end if; + + if (rst_in = '0') then + if (seq1_0 /= "11" and adc_s1_flag = '0') then + acq_avg <= curr_seq(13 downto 12); + acq_chan <= curr_seq(4 downto 0); + acq_b_u <= curr_seq(10); + else + acq_avg <= cfg_reg0_adc(13 downto 12); + acq_chan <= cfg_reg0_adc(4 downto 0); + acq_b_u <= cfg_reg0_adc(10); + end if; + end if; + end process; + + acq_chan_index <= SLV_TO_INT(acq_chan); + + conv_end_reg_read_P : process ( adcclk, rst_in) + begin + if (rst_in = '1') then + conv_end_reg_read <= "0000"; + elsif (rising_edge(adcclk)) then + conv_end_reg_read(3 downto 1) <= conv_end_reg_read(2 downto 0); + conv_end_reg_read(0) <= single_chan_conv_end or conv_end; + end if; + end process; + +-- synch to DCLK + busy_reg_read_P : process ( dclk_in, rst_in) + begin + if (rst_in = '1') then + busy_reg_read <= '1'; + elsif (rising_edge(dclk_in)) then + busy_reg_read <= not conv_end_reg_read(2); + end if; + end process; + + cfg_reg0_adc_P : process + variable first_after_reset : std_ulogic := '1'; + begin + if (rst_in='1') then + cfg_reg0_seq <= X"0000"; + cfg_reg0_adc <= X"0000"; + acq_e_c <= '0'; + first_after_reset := '1'; + elsif (falling_edge(busy_reg_read) or falling_edge(rst_in)) then + wait until (rising_edge(dclk_in)); + wait until (rising_edge(dclk_in)); + wait until (rising_edge(dclk_in)); + if (first_after_reset = '1') then + first_after_reset := '0'; + cfg_reg0_adc <= cfg_reg0; + cfg_reg0_seq <= cfg_reg0; + else + cfg_reg0_adc <= cfg_reg0_seq; + cfg_reg0_seq <= cfg_reg0; + end if; + acq_e_c <= cfg_reg0(9); + end if; + wait on busy_reg_read, rst_in; + end process; + + busy_r_p : process(conv_start, busy_r_rst, rst_in) + begin + if (rst_in = '1') then + busy_r <= '0'; + elsif (rising_edge(conv_start) and rst_lock = '0') then + busy_r <= '1'; + elsif (rising_edge(busy_r_rst)) then + busy_r <= '0'; + end if; + end process; + + curr_seq1_0_p : process( busy_out) + begin + if (falling_edge( busy_out)) then + if (adc_s1_flag = '1') then + curr_seq1_0 <= "00"; + else + curr_seq1_0 <= seq1_0; + end if; + end if; + end process; + + start_conv_p : process ( conv_start, rst_in) + variable Message : line; + begin + if (rst_in = '1') then + analog_mux_in <= 0.0; + curr_chan <= "00000"; + elsif (rising_edge(conv_start)) then + if ( ((acq_chan_index = 3) or (acq_chan_index >= 16 and acq_chan_index <= 31))) then + analog_mux_in <= analog_in_diff(acq_chan_index); + else + analog_mux_in <= analog_in_uni(acq_chan_index); + end if; + curr_chan <= acq_chan; + curr_seq1_0_lat <= curr_seq1_0; + + if (acq_chan_index = 6 or acq_chan_index = 7 or (acq_chan_index >= 10 and acq_chan_index <= 15)) then + Write ( Message, string'(" Invalid Input Warning : The analog channel ")); + Write ( Message, acq_chan_index); + Write ( Message, string'(" to SYSMON is invalid.")); + assert false report Message.all severity warning; + end if; + + if ((seq1_0 = "01" and adc_s1_flag = '0') or seq1_0 = "10" or seq1_0 = "00") then + curr_avg_set <= curr_seq(13 downto 12); + curr_b_u <= curr_seq(10); + curr_e_c <= '0'; + curr_acq <= curr_seq(8); + else + curr_avg_set <= acq_avg; + curr_b_u <= acq_b_u; + curr_e_c <= cfg_reg0(9); + curr_acq <= cfg_reg0(8); + end if; + end if; + + end process; + +-- end latch configuration registers + +-- sequence control + + seq_en_dly <= seq_en after 1 ps; + + seq_num_p : process(seq_en_dly) + variable seq_num_tmp : integer := 0; + variable si_tmp : integer := 0; + variable si : integer := 0; + begin + if (rising_edge(seq_en_dly)) then + if (seq1_0 = "01" or seq1_0 = "10") then + seq_num_tmp := 0; + for I in 0 to 15 loop + si := I; + if (seq_chan_reg1(si) = '1') then + seq_num_tmp := seq_num_tmp + 1; + seq_mem(seq_num_tmp) <= si; + end if; + end loop; + for I in 16 to 31 loop + si := I; + si_tmp := si-16; + if (seq_chan_reg2(si_tmp) = '1') then + seq_num_tmp := seq_num_tmp + 1; + seq_mem(seq_num_tmp) <= si; + end if; + end loop; + seq_num <= seq_num_tmp; + elsif (seq1_0 = "00") then + seq_num <= 4; + seq_mem(1) <= 0; + seq_mem(2) <= 8; + seq_mem(3) <= 9; + seq_mem(4) <= 10; + end if; + end if; + end process; + + + curr_seq_p : process(seq_count, seq_en_dly) + variable seq_curr_i : std_logic_vector(4 downto 0); + variable seq_curr_index : integer; + variable tmp_value : integer; + variable curr_seq_tmp : std_logic_vector(15 downto 0); + begin + if (seq_count'event or falling_edge(seq_en_dly)) then + seq_curr_index := seq_mem(seq_count); + seq_curr_i := STD_LOGIC_VECTOR(TO_UNSIGNED(seq_curr_index, 5)); + curr_seq_tmp := "0000000000000000"; + if (seq_curr_index >= 0 and seq_curr_index <= 15) then + curr_seq_tmp(2 downto 0) := seq_curr_i(2 downto 0); + curr_seq_tmp(4 downto 3) := "01"; + curr_seq_tmp(8) := seq_acq_reg1(seq_curr_index); + curr_seq_tmp(10) := seq_du_reg1(seq_curr_index); + if (seq1_0 = "00") then + curr_seq_tmp(13 downto 12) := "01"; + elsif (seq_avg_reg1(seq_curr_index) = '1') then + curr_seq_tmp(13 downto 12) := cfg_reg0(13 downto 12); + else + curr_seq_tmp(13 downto 12) := "00"; + end if; + if (seq_curr_index >= 0 and seq_curr_index <= 7) then + curr_seq_tmp(4 downto 3) := "01"; + else + curr_seq_tmp(4 downto 3) := "00"; + end if; + elsif (seq_curr_index >= 16 and seq_curr_index <= 31) then + tmp_value := seq_curr_index -16; + curr_seq_tmp(4 downto 0) := seq_curr_i; + curr_seq_tmp(8) := seq_acq_reg2(tmp_value); + curr_seq_tmp(10) := seq_du_reg2(tmp_value); + if (seq_avg_reg2(tmp_value) = '1') then + curr_seq_tmp(13 downto 12) := cfg_reg0(13 downto 12); + else + curr_seq_tmp(13 downto 12) := "00"; + end if; + end if; + curr_seq <= curr_seq_tmp; + end if; + end process; + + eos_en_p : process (adcclk, rst_in) + begin + if (rst_in = '1') then + seq_count <= 1; + eos_en <= '0'; + elsif (rising_edge(adcclk)) then + if ((seq_count = seq_num ) and (adc_state = CONV_STATE and next_state = END_STATE) + and (curr_seq1_0_lat /= "11") and rst_lock = '0') then + eos_tmp_en <= '1'; + else + eos_tmp_en <= '0'; + end if; + + if ((eos_tmp_en = '1') and (seq_status_avg = 0)) then + eos_en <= '1'; + else + eos_en <= '0'; + end if; + + if (eos_tmp_en = '1' or curr_seq1_0_lat = "11") then + seq_count <= 1; + elsif (seq_count_en = '1' ) then + if (seq_count >= 32) then + seq_count <= 1; + else + seq_count <= seq_count +1; + end if; + end if; + end if; + end process; + +-- end sequence control + +-- Acquisition + + busy_out_dly <= busy_out after 10 ps; + + short_acq_p : process(adc_state, rst_in, first_acq) + begin + if (rst_in = '1') then + shorten_acq <= 0; + elsif (adc_state'event or first_acq'event) then + if ((busy_out_dly = '0') and (adc_state=ACQ_STATE) and (first_acq='1')) then + shorten_acq <= 1; + else + shorten_acq <= 0; + end if; + end if; + end process; + + acq_count_p : process (adcclk, rst_in) + begin + if (rst_in = '1') then + acq_count <= 1; + first_acq <= '1'; + elsif (rising_edge(adcclk)) then + if (adc_state = ACQ_STATE and rst_lock = '0' and acq_e_c = '0') then + first_acq <= '0'; + + if (acq_acqsel = '1') then + if (acq_count <= 11) then + acq_count <= acq_count + 1 + shorten_acq; + end if; + else + if (acq_count <= 4) then + acq_count <= acq_count + 1 + shorten_acq; + end if; + end if; + + if (next_state = CONV_STATE) then + if ((acq_acqsel = '1' and acq_count < 10) or (acq_acqsel = '0' and acq_count < 4)) then + assert false report "Warning: Acquisition time not enough for SYSMON." + severity warning; + end if; + end if; + else + if (first_acq = '1') then + acq_count <= 1; + else + acq_count <= 0; + end if; + end if; + end if; + end process; + + conv_start_con_p: process(adc_state, acq_acqsel, acq_count) + begin + if (adc_state = ACQ_STATE) then + if (rst_lock = '0') then + if ((seq_reset_flag = '0' or (seq_reset_flag = '1' and curr_clkdiv_sel_int > 3)) + and ((acq_acqsel = '1' and acq_count > 10) or (acq_acqsel = '0' and acq_count > 4))) then + conv_start_cont <= '1'; + else + conv_start_cont <= '0'; + end if; + end if; + else + conv_start_cont <= '0'; + end if; + end process; + + conv_start_sel <= convst_in when (acq_e_c = '1') else conv_start_cont; + reset_conv_start_tmp <= '1' when (conv_count=2) else '0'; + reset_conv_start <= rst_in or reset_conv_start_tmp; + + conv_start_p : process(conv_start_sel, reset_conv_start) + begin + if (reset_conv_start ='1') then + conv_start <= '0'; + elsif (rising_edge(conv_start_sel)) then + conv_start <= '1'; + end if; + end process; + +-- end acquisition + + +-- Conversion + conv_result_p : process (adc_state, next_state, curr_chan, curr_chan_index, analog_mux_in, curr_b_u) + variable conv_result_int_i : integer := 0; + variable conv_result_int_tmp : integer := 0; + variable conv_result_int_tmp_rl : real := 0.0; + variable adc_analog_tmp : real := 0.0; + begin + if ((adc_state = CONV_STATE and next_state = END_STATE) or adc_state = END_STATE) then + if (curr_chan = "00000") then -- temperature conversion + adc_analog_tmp := (analog_mux_in + 273.0) * 130.0382; + adc_temp_result <= adc_analog_tmp; + if (adc_analog_tmp >= 65535.0) then + conv_result_int_i := 65535; + elsif (adc_analog_tmp < 0.0) then + conv_result_int_i := 0; + else + conv_result_int_tmp := real2int(adc_analog_tmp); + conv_result_int_tmp_rl := int2real(conv_result_int_tmp); + if (adc_analog_tmp - conv_result_int_tmp_rl > 0.9999) then + conv_result_int_i := conv_result_int_tmp + 1; + else + conv_result_int_i := conv_result_int_tmp; + end if; + end if; + conv_result_int <= conv_result_int_i; + conv_result <= STD_LOGIC_VECTOR(TO_UNSIGNED(conv_result_int_i, 16)); + elsif (curr_chan = "00001" or curr_chan = "00010") then -- internal power conversion + adc_analog_tmp := analog_mux_in * 65536.0 / 3.0; + adc_intpwr_result <= adc_analog_tmp; + if (adc_analog_tmp >= 65535.0) then + conv_result_int_i := 65535; + elsif (adc_analog_tmp < 0.0) then + conv_result_int_i := 0; + else + conv_result_int_tmp := real2int(adc_analog_tmp); + conv_result_int_tmp_rl := int2real(conv_result_int_tmp); + if (adc_analog_tmp - conv_result_int_tmp_rl > 0.9999) then + conv_result_int_i := conv_result_int_tmp + 1; + else + conv_result_int_i := conv_result_int_tmp; + end if; + end if; + conv_result_int <= conv_result_int_i; + conv_result <= STD_LOGIC_VECTOR(TO_UNSIGNED(conv_result_int_i, 16)); + elsif ((curr_chan = "00011") or ((curr_chan_index >= 16) and (curr_chan_index <= 31))) then + adc_analog_tmp := (analog_mux_in) * 65536.0; + adc_ext_result <= adc_analog_tmp; + if (curr_b_u = '1') then + if (adc_analog_tmp > 32767.0) then + conv_result_int_i := 32767; + elsif (adc_analog_tmp < -32768.0) then + conv_result_int_i := -32768; + else + conv_result_int_tmp := real2int(adc_analog_tmp); + conv_result_int_tmp_rl := int2real(conv_result_int_tmp); + if (adc_analog_tmp - conv_result_int_tmp_rl > 0.9999) then + conv_result_int_i := conv_result_int_tmp + 1; + else + conv_result_int_i := conv_result_int_tmp; + end if; + end if; + conv_result_int <= conv_result_int_i; + conv_result <= STD_LOGIC_VECTOR(TO_SIGNED(conv_result_int_i, 16)); + else + if (adc_analog_tmp > 65535.0) then + conv_result_int_i := 65535; + elsif (adc_analog_tmp < 0.0) then + conv_result_int_i := 0; + else + conv_result_int_tmp := real2int(adc_analog_tmp); + conv_result_int_tmp_rl := int2real(conv_result_int_tmp); + if (adc_analog_tmp - conv_result_int_tmp_rl > 0.9999) then + conv_result_int_i := conv_result_int_tmp + 1; + else + conv_result_int_i := conv_result_int_tmp; + end if; + end if; + conv_result_int <= conv_result_int_i; + conv_result <= STD_LOGIC_VECTOR(TO_UNSIGNED(conv_result_int_i, 16)); + end if; + else + conv_result_int <= 0; + conv_result <= "0000000000000000"; + end if; + end if; + + end process; + + + conv_count_p : process (adcclk, rst_in) + begin + if (rst_in = '1') then + conv_count <= 6; + conv_end <= '0'; + seq_status_avg <= 0; + busy_r_rst <= '0'; + busy_r_rst_done <= '0'; + for i in 0 to 31 loop + conv_avg_count(i) <= 0; -- array of integer + end loop; + single_chan_conv_end <= '0'; + elsif (rising_edge(adcclk)) then + if (adc_state = ACQ_STATE) then + if (busy_r_rst_done = '0') then + busy_r_rst <= '1'; + else + busy_r_rst <= '0'; + end if; + busy_r_rst_done <= '1'; + end if; + + if (adc_state = ACQ_STATE and conv_start = '1') then + conv_count <= 0; + conv_end <= '0'; + elsif (adc_state = CONV_STATE ) then + busy_r_rst_done <= '0'; + conv_count <= conv_count + 1; + + if (((curr_chan /= "01000" ) and (conv_count = conv_time )) or + ((curr_chan = "01000") and (conv_count = conv_time_cal_1) and (first_cal_chan = '1')) + or ((curr_chan = "01000") and (conv_count = conv_time_cal) and (first_cal_chan = '0'))) then + conv_end <= '1'; + else + conv_end <= '0'; + end if; + else + conv_end <= '0'; + conv_count <= 0; + end if; + + single_chan_conv_end <= '0'; + if ( (conv_count = conv_time) or (conv_count = 44)) then + single_chan_conv_end <= '1'; + end if; + + if (adc_state = CONV_STATE and next_state = END_STATE and rst_lock = '0') then + case curr_avg_set is + when "00" => eoc_en <= '1'; + conv_avg_count(curr_chan_index) <= 0; + when "01" => + if (conv_avg_count(curr_chan_index) = 15) then + eoc_en <= '1'; + conv_avg_count(curr_chan_index) <= 0; + seq_status_avg <= seq_status_avg - 1; + else + eoc_en <= '0'; + if (conv_avg_count(curr_chan_index) = 0) then + seq_status_avg <= seq_status_avg + 1; + end if; + conv_avg_count(curr_chan_index) <= conv_avg_count(curr_chan_index) + 1; + end if; + when "10" => + if (conv_avg_count(curr_chan_index) = 63) then + eoc_en <= '1'; + conv_avg_count(curr_chan_index) <= 0; + seq_status_avg <= seq_status_avg - 1; + else + eoc_en <= '0'; + if (conv_avg_count(curr_chan_index) = 0) then + seq_status_avg <= seq_status_avg + 1; + end if; + conv_avg_count(curr_chan_index) <= conv_avg_count(curr_chan_index) + 1; + end if; + when "11" => + if (conv_avg_count(curr_chan_index) = 255) then + eoc_en <= '1'; + conv_avg_count(curr_chan_index) <= 0; + seq_status_avg <= seq_status_avg - 1; + else + eoc_en <= '0'; + if (conv_avg_count(curr_chan_index) = 0) then + seq_status_avg <= seq_status_avg + 1; + end if; + conv_avg_count(curr_chan_index) <= conv_avg_count(curr_chan_index) + 1; + end if; + when others => eoc_en <= '0'; + end case; + else + eoc_en <= '0'; + end if; + + if (adc_state = END_STATE) then + conv_result_reg <= conv_result; + end if; + end if; + end process; + +-- end conversion + + +-- average + + conv_acc_result_p : process(adcclk, rst_in) + variable conv_acc_vec : std_logic_vector(23 downto 0); + variable conv_acc_vec_int : integer; + begin + if (rst_in = '1') then + for j in 0 to 31 loop + conv_acc(j) <= 0; + end loop; + conv_acc_result <= "0000000000000000"; + elsif (rising_edge(adcclk)) then + if (adc_state = CONV_STATE and next_state = END_STATE) then + if (curr_avg_set /= "00" and rst_lock /= '1') then + conv_acc(curr_chan_index) <= conv_acc(curr_chan_index) + conv_result_int; + else + conv_acc(curr_chan_index) <= 0; + end if; + elsif (eoc_en = '1') then + conv_acc_vec_int := conv_acc(curr_chan_index); + if ((curr_b_u = '1') and (((curr_chan_index >= 16) and (curr_chan_index <= 31)) + or (curr_chan_index = 3))) then + conv_acc_vec := STD_LOGIC_VECTOR(TO_SIGNED(conv_acc_vec_int, 24)); + else + conv_acc_vec := STD_LOGIC_VECTOR(TO_UNSIGNED(conv_acc_vec_int, 24)); + end if; + case curr_avg_set(1 downto 0) is + when "00" => conv_acc_result <= "0000000000000000"; + when "01" => conv_acc_result <= conv_acc_vec(19 downto 4); + when "10" => conv_acc_result <= conv_acc_vec(21 downto 6); + when "11" => conv_acc_result <= conv_acc_vec(23 downto 8); + when others => conv_acc_result <= "0000000000000000"; + end case; + conv_acc(curr_chan_index) <= 0; + end if; + end if; + end process; + +-- end average + +-- single sequence + adc_s1_flag_p : process(adcclk, rst_in) + begin + if (rst_in = '1') then + adc_s1_flag <= '0'; + elsif (rising_edge(adcclk)) then + if (adc_state = SINGLE_SEQ_STATE) then + adc_s1_flag <= '1'; + end if; + end if; + end process; + + +-- end state + eos_eoc_p: process(adcclk, rst_in) + begin + if (rst_in = '1') then + seq_count_en <= '0'; + eos_out_tmp <= '0'; + eoc_out_tmp <= '0'; + elsif (rising_edge(adcclk)) then + if ((adc_state = CONV_STATE and next_state = END_STATE) and (curr_seq1_0_lat /= "11") + and (rst_lock = '0')) then + seq_count_en <= '1'; + else + seq_count_en <= '0'; + end if; + + if (rst_lock = '0') then + eos_out_tmp <= eos_en; + eoc_en_delay <= eoc_en; + eoc_out_tmp <= eoc_en_delay; + else + eos_out_tmp <= '0'; + eoc_en_delay <= '0'; + eoc_out_tmp <= '0'; + end if; + end if; + end process; + + data_reg_p : process(eoc_out, rst_in_not_seq) + variable tmp_uns1 : unsigned(15 downto 0); + variable tmp_uns2 : unsigned(15 downto 0); + variable tmp_uns3 : unsigned(15 downto 0); + begin + if (rst_in_not_seq = '1') then + for k in 32 to 39 loop + if (k >= 36) then + data_reg(k) <= "1111111111111111"; + else + data_reg(k) <= "0000000000000000"; + end if; + end loop; + elsif (rising_edge(eoc_out)) then + if ( rst_lock = '0') then + if ((curr_chan_index >= 0 and curr_chan_index <= 3) or + (curr_chan_index >= 16 and curr_chan_index <= 31)) then + if (curr_avg_set = "00") then + data_reg(curr_chan_index) <= conv_result_reg; + else + data_reg(curr_chan_index) <= conv_acc_result; + end if; + end if; + if (curr_chan_index = 4) then + data_reg(curr_chan_index) <= X"D555"; + end if; + if (curr_chan_index = 5) then + data_reg(curr_chan_index) <= X"0000"; + end if; + if (curr_chan_index = 0 or curr_chan_index = 1 or curr_chan_index = 2) then + tmp_uns2 := UNSIGNED(data_reg(32 + curr_chan_index)); + tmp_uns3 := UNSIGNED(data_reg(36 + curr_chan_index)); + if (curr_avg_set = "00") then + tmp_uns1 := UNSIGNED(conv_result_reg); + if (tmp_uns1 > tmp_uns2) then + data_reg(32 + curr_chan_index) <= conv_result_reg; + end if; + if (tmp_uns1 < tmp_uns3) then + data_reg(36 + curr_chan_index) <= conv_result_reg; + end if; + else + tmp_uns1 := UNSIGNED(conv_acc_result); + if (tmp_uns1 > tmp_uns2) then + data_reg(32 + curr_chan_index) <= conv_acc_result; + end if; + if (tmp_uns1 < tmp_uns3) then + data_reg(36 + curr_chan_index) <= conv_acc_result; + end if; + end if; + end if; + end if; + end if; + end process; + + data_written_p : process(busy_r, rst_in_not_seq) + begin + if (rst_in_not_seq = '1') then + data_written <= X"0000"; + elsif (falling_edge(busy_r)) then + if (curr_avg_set = "00") then + data_written <= conv_result_reg; + else + data_written <= conv_acc_result; + end if; + end if; + end process; + +-- eos and eoc + + eoc_out_tmp1_p : process (eoc_out_tmp, eoc_out, rst_in) + begin + if (rst_in = '1') then + eoc_out_tmp1 <= '0'; + elsif (rising_edge(eoc_out)) then + eoc_out_tmp1 <= '0'; + elsif (rising_edge(eoc_out_tmp)) then + if (curr_chan /= "01000") then + eoc_out_tmp1 <= '1'; + else + eoc_out_tmp1 <= '0'; + end if; + end if; + end process; + + eos_out_tmp1_p : process (eos_out_tmp, eos_out, rst_in) + begin + if (rst_in = '1') then + eos_out_tmp1 <= '0'; + elsif (rising_edge(eos_out)) then + eos_out_tmp1 <= '0'; + elsif (rising_edge(eos_out_tmp)) then + eos_out_tmp1 <= '1'; + end if; + end process; + + busy_out_low_edge <= '1' when (busy_out='0' and busy_out_sync='1') else '0'; + + eoc_eos_out_p : process (dclk_in, rst_in) + begin + if (rst_in = '1') then + op_count <= 15; + busy_out_sync <= '0'; + drp_update <= '0'; + alarm_update <= '0'; + eoc_out <= '0'; + eos_out <= '0'; + elsif ( rising_edge(dclk_in)) then + busy_out_sync <= busy_out; + if (op_count = 3) then + drp_update <= '1'; + else + drp_update <= '0'; + end if; + if (op_count = 5 and eoc_out_tmp1 = '1') then + alarm_update <= '1'; + else + alarm_update <= '0'; + end if; + if (op_count = 9 ) then + eoc_out <= eoc_out_tmp1; + else + eoc_out <= '0'; + end if; + if (op_count = 9) then + eos_out <= eos_out_tmp1; + else + eos_out <= '0'; + end if; + if (busy_out_low_edge = '1') then + op_count <= 0; + elsif (op_count < 15) then + op_count <= op_count +1; + end if; + end if; + end process; + +-- end eos and eoc + + +-- alarm + + alm_reg_p : process(alarm_update, rst_in_not_seq ) + variable tmp_unsig1 : unsigned(15 downto 0); + variable tmp_unsig2 : unsigned(15 downto 0); + variable tmp_unsig3 : unsigned(15 downto 0); + begin + if (rst_in_not_seq = '1') then + ot_out_reg <= '0'; + alarm_out_reg <= "000"; + elsif (rising_edge(alarm_update)) then + if (rst_lock = '0') then + if (curr_chan_lat = "00000") then + tmp_unsig1 := UNSIGNED(data_written); + tmp_unsig2 := UNSIGNED(dr_sram(16#57#)); + if (tmp_unsig1 >= ot_limit_reg) then + ot_out_reg <= '1'; + elsif (((tmp_unsig1 < tmp_unsig2) and (curr_seq1_0_lat /= "00")) or + ((curr_seq1_0_lat = "00") and (tmp_unsig1 < ot_sf_limit_low_reg))) then + ot_out_reg <= '0'; + end if; + tmp_unsig2 := UNSIGNED(dr_sram(16#50#)); + tmp_unsig3 := UNSIGNED(dr_sram(16#54#)); + if ( tmp_unsig1 > tmp_unsig2) then + alarm_out_reg(0) <= '1'; + elsif (tmp_unsig1 <= tmp_unsig3) then + alarm_out_reg(0) <= '0'; + end if; + end if; + tmp_unsig1 := UNSIGNED(data_written); + tmp_unsig2 := UNSIGNED(dr_sram(16#51#)); + tmp_unsig3 := UNSIGNED(dr_sram(16#55#)); + if (curr_chan_lat = "00001") then + if ((tmp_unsig1 > tmp_unsig2) or (tmp_unsig1 < tmp_unsig3)) then + alarm_out_reg(1) <= '1'; + else + alarm_out_reg(1) <= '0'; + end if; + end if; + tmp_unsig1 := UNSIGNED(data_written); + tmp_unsig2 := UNSIGNED(dr_sram(16#52#)); + tmp_unsig3 := UNSIGNED(dr_sram(16#56#)); + if (curr_chan_lat = "00010") then + if ((tmp_unsig1 > tmp_unsig2) or (tmp_unsig1 < tmp_unsig3)) then + alarm_out_reg(2) <= '1'; + else + alarm_out_reg(2) <= '0'; + end if; + end if; + end if; + end if; + end process; + + + alm_p : process(ot_out_reg, ot_en, alarm_out_reg, alarm_en) + begin + ot_out <= ot_out_reg and ot_en; + alarm_out(0) <= alarm_out_reg(0) and alarm_en(0); + alarm_out(1) <= alarm_out_reg(1) and alarm_en(1); + alarm_out(2) <= alarm_out_reg(2) and alarm_en(2); + end process; + +-- end alarm + + + READFILE_P : process + file in_file : text; + variable open_status : file_open_status; + variable in_buf : line; + variable str_token : string(1 to 12); + variable str_token_in : string(1 to 12); + variable str_token_tmp : string(1 to 12); + variable next_time : time := 0 ps; + variable pre_time : time := 0 ps; + variable time_val : integer := 0; + variable a1 : real; + + variable commentline : boolean := false; + variable HeaderFound : boolean := false; + variable read_ok : boolean := false; + variable token_len : integer; + variable HeaderCount : integer := 0; + + variable vals : ANALOG_DATA := (others => 0.0); + variable valsn : ANALOG_DATA := (others => 0.0); + variable inchannel : integer := 0 ; + type int_a is array (0 to 41) of integer; + variable index_to_channel : int_a := (others => -1); + variable low : integer := -1; + variable low2 : integer := -1; + variable sim_file_flag1 : std_ulogic := '0'; + variable file_line : integer := 0; + + type channm_array is array (0 to 31 ) of string(1 to 12); + constant chanlist_p : channm_array := ( + 0 => "TEMP" & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL, + 1 => "VCCINT" & NUL & NUL & NUL & NUL & NUL & NUL, + 2 => "VCCAUX" & NUL & NUL & NUL & NUL & NUL & NUL, + 3 => "VP" & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL, + 4 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & + NUL & NUL, + 5 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & + NUL & NUL, + 6 => "xxxxxxxxxxxx", + 7 => "xxxxxxxxxxxx", + 8 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & + NUL & NUL, + 9 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & + NUL & NUL, + 10 => "xxxxxxxxxxxx", + 11 => "xxxxxxxxxxxx", + 12 => "xxxxxxxxxxxx", + 13 => "xxxxxxxxxxxx", + 14 => "xxxxxxxxxxxx", + 15 => "xxxxxxxxxxxx", + 16 => "VAUXP[0]" & NUL & NUL & NUL & NUL, + 17 => "VAUXP[1]" & NUL & NUL & NUL & NUL, + 18 => "VAUXP[2]" & NUL & NUL & NUL & NUL, + 19 => "VAUXP[3]" & NUL & NUL & NUL & NUL, + 20 => "VAUXP[4]" & NUL & NUL & NUL & NUL, + 21 => "VAUXP[5]" & NUL & NUL & NUL & NUL, + 22 => "VAUXP[6]" & NUL & NUL & NUL & NUL, + 23 => "VAUXP[7]" & NUL & NUL & NUL & NUL, + 24 => "VAUXP[8]" & NUL & NUL & NUL & NUL, + 25 => "VAUXP[9]" & NUL & NUL & NUL & NUL, + 26 => "VAUXP[10]" & NUL & NUL & NUL, + 27 => "VAUXP[11]" & NUL & NUL & NUL, + 28 => "VAUXP[12]" & NUL & NUL & NUL, + 29 => "VAUXP[13]" & NUL & NUL & NUL, + 30 => "VAUXP[14]" & NUL & NUL & NUL, + 31 => "VAUXP[15]" & NUL & NUL & NUL + ); + + constant chanlist_n : channm_array := ( + 0 => "xxxxxxxxxxxx", + 1 => "xxxxxxxxxxxx", + 2 => "xxxxxxxxxxxx", + 3 => "VN" & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL, + 4 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & + NUL & NUL, + 5 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & + NUL & NUL, + 6 => "xxxxxxxxxxxx", + 7 => "xxxxxxxxxxxx", + 8 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & + NUL & NUL, + 9 => NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & + NUL & NUL, + 10 => "xxxxxxxxxxxx", + 11 => "xxxxxxxxxxxx", + 12 => "xxxxxxxxxxxx", + 13 => "xxxxxxxxxxxx", + 14 => "xxxxxxxxxxxx", + 15 => "xxxxxxxxxxxx", + 16 => "VAUXN[0]" & NUL & NUL & NUL & NUL, + 17 => "VAUXN[1]" & NUL & NUL & NUL & NUL, + 18 => "VAUXN[2]" & NUL & NUL & NUL & NUL, + 19 => "VAUXN[3]" & NUL & NUL & NUL & NUL, + 20 => "VAUXN[4]" & NUL & NUL & NUL & NUL, + 21 => "VAUXN[5]" & NUL & NUL & NUL & NUL, + 22 => "VAUXN[6]" & NUL & NUL & NUL & NUL, + 23 => "VAUXN[7]" & NUL & NUL & NUL & NUL, + 24 => "VAUXN[8]" & NUL & NUL & NUL & NUL, + 25 => "VAUXN[9]" & NUL & NUL & NUL & NUL, + 26 => "VAUXN[10]" & NUL & NUL & NUL, + 27 => "VAUXN[11]" & NUL & NUL & NUL, + 28 => "VAUXN[12]" & NUL & NUL & NUL, + 29 => "VAUXN[13]" & NUL & NUL & NUL, + 30 => "VAUXN[14]" & NUL & NUL & NUL, + 31 => "VAUXN[15]" & NUL & NUL & NUL + ); + + begin + + file_open(open_status, in_file, SIM_MONITOR_FILE, read_mode); + if (open_status /= open_ok) then + assert false report + "*** Warning: The analog data file for SYSMON was not found. Use the SIM_MONITOR_FILE generic to specify the input analog data file name or use default name: design.txt. " + severity warning; + sim_file_flag1 := '1'; + sim_file_flag <= '1'; + end if; + + if ( sim_file_flag1 = '0') then + while (not endfile(in_file) and (not HeaderFound)) loop + commentline := false; + readline(in_file, in_buf); + file_line := file_line + 1; + if (in_buf'LENGTH > 0 ) then + skip_blanks(in_buf); + + low := in_buf'low; + low2 := in_buf'low+2; + if ( low2 <= in_buf'high) then + if ((in_buf(in_buf'low to in_buf'low+1) = "//" ) or + (in_buf(in_buf'low to in_buf'low+1) = "--" )) then + commentline := true; + end if; + + while((in_buf'LENGTH > 0 ) and (not commentline)) loop + HeaderFound := true; + get_token(in_buf, str_token_in, token_len); + str_token_tmp := To_Upper(str_token_in); + if (str_token_tmp(1 to 4) = "TEMP") then + str_token := "TEMP" & NUL & NUL & NUL & NUL & NUL + & NUL & NUL & NUL; + else + str_token := str_token_tmp; + end if; + + if(token_len > 0) then + HeaderCount := HeaderCount + 1; + end if; + + if (HeaderCount=1) then + if (str_token(1 to token_len) /= "TIME") then + infile_format; + assert false report + " Analog Data File Error : No TIME label is found in the input file for SYSMON." + severity failure; + end if; + elsif (HeaderCount > 1) then + inchannel := -1; + for i in 0 to 31 loop + if (chanlist_p(i) = str_token) then + inchannel := i; + index_to_channel(headercount) := i; + end if; + end loop; + if (inchannel = -1) then + for i in 0 to 31 loop + if ( chanlist_n(i) = str_token) then + inchannel := i; + index_to_channel(headercount) := i+32; + end if; + end loop; + end if; + if (inchannel = -1 and token_len >0) then + infile_format; + assert false report + "Analog Data File Error : No valid channel name in the input file for SYSMON. Valid names: TEMP VCCINT VCCAUX VP VN VAUXP[1] VAUXN[1] ....." + severity failure; + end if; + else + infile_format; + assert false report + "Analog Data File Error : NOT found header in the input file for SYSMON. The header is: TIME TEMP VCCINT VCCAUX VP VN VAUXP[1] VAUXN[1] ..." + severity failure; + end if; + + str_token_in := NUL & NUL & NUL & NUL & NUL & NUL & NUL & NUL & + NUL & NUL & NUL & NUL; + end loop; + end if; + end if; + end loop; + +----- Read Values + while (not endfile(in_file)) loop + commentline := false; + readline(in_file, in_buf); + file_line := file_line + 1; + if (in_buf'length > 0) then + skip_blanks(in_buf); + + if (in_buf'low < in_buf'high) then + if((in_buf(in_buf'low to in_buf'low+1) = "//" ) or + (in_buf(in_buf'low to in_buf'low+1) = "--" )) then + commentline := true; + end if; + + if(not commentline and in_buf'length > 0) then + for i IN 1 to HeaderCount Loop + if ( i=1) then + read(in_buf, time_val, read_ok); + if (not read_ok) then + infile_format; + assert false report + " Analog Data File Error : The time value should be integer in ns scale and the last time value needs bigger than simulation time." + severity failure; + end if; + next_time := time_val * 1 ns; + else + read(in_buf, a1, read_ok); + if (not read_ok) then + assert false report + "*** Analog Data File Error: The data type should be REAL, e.g. 3.0 0.0 -0.5 " + severity failure; + end if; + inchannel:= index_to_channel(i); + if (inchannel >= 32) then + valsn(inchannel-32):=a1; + else + vals(inchannel):=a1; + end if; + end if; + end loop; -- i loop + + if ( now < next_time) then + wait for ( next_time - now ); + end if; + for i in 0 to 31 loop + chan_val_tmp(i) <= vals(i); + chan_valn_tmp(i) <= valsn(i); + analog_in_diff(i) <= vals(i)-valsn(i); + analog_in_uni(i) <= vals(i); + end loop; + end if; + end if; + end if; + end loop; -- while loop + file_close(in_file); + end if; + wait; + end process READFILE_P; + + + +end SYSMON_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / +-- /___/ /\ Filename : USR_ACCESS_VIRTEX5.vhd +-- \ \ / \ Timestamp : Thu Apr 8 10:57:05 PDT 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL USR_ACCESS_VIRTEX5 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity USR_ACCESS_VIRTEX5 is + port( + CFGCLK : out std_ulogic; + DATA : out std_logic_vector(31 downto 0); + DATAVALID : out std_ulogic + ); + +end USR_ACCESS_VIRTEX5; + +architecture USR_ACCESS_VIRTEX5_V of USR_ACCESS_VIRTEX5 is + +begin +end USR_ACCESS_VIRTEX5_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Boundary Scan Logic Control Circuit for SPARTAN3A +-- /___/ /\ Filename : BSCAN_SPARTAN3A.vhd +-- \ \ / \ Timestamp : Tue Jul 5 16:58:04 PDT 2005 +-- \___\/\___\ +-- +-- Revision: +-- 07/05/05 - Initial version. +-- 01/24/06 - CR 224623, added TCK and TMS ports +-- End Revision + +----- CELL BSCAN_SPARTAN3A ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.vcomponents.all; + +entity BSCAN_SPARTAN3A is + + port( + CAPTURE : out std_ulogic := 'H'; + DRCK1 : out std_ulogic := 'L'; + DRCK2 : out std_ulogic := 'L'; + RESET : out std_ulogic := 'L'; + SEL1 : out std_ulogic := 'L'; + SEL2 : out std_ulogic := 'L'; + SHIFT : out std_ulogic := 'L'; + TCK : out std_ulogic := 'L'; + TDI : out std_ulogic := 'L'; + TMS : out std_ulogic := 'L'; + UPDATE : out std_ulogic := 'L'; + + TDO1 : in std_ulogic := 'X'; + TDO2 : in std_ulogic := 'X' + ); +end BSCAN_SPARTAN3A; + + +-- architecture body + +architecture BSCAN_SPARTAN3A_V of BSCAN_SPARTAN3A is + + + + signal TDO1_dly : std_ulogic := '0'; + signal TDO2_dly : std_ulogic := '0'; + +begin + + TDO1_dly <= TDO1 after 0 ps; + TDO2_dly <= TDO2 after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + + +-- synopsys translate_off + + CAPTURE <= JTAG_CAPTURE_GLBL ; + +--#################################################################### +--##### jtag_select ### +--#################################################################### + DRCK1 <= ((JTAG_SEL1_GLBL and not JTAG_SHIFT_GLBL and not JTAG_CAPTURE_GLBL) + or + (JTAG_SEL1_GLBL and JTAG_SHIFT_GLBL and JTAG_TCK_GLBL) + or + (JTAG_SEL1_GLBL and JTAG_CAPTURE_GLBL and JTAG_TCK_GLBL)); + DRCK2 <= ((JTAG_SEL2_GLBL and not JTAG_SHIFT_GLBL and not JTAG_CAPTURE_GLBL) + or + (JTAG_SEL2_GLBL and JTAG_SHIFT_GLBL and JTAG_TCK_GLBL) + or + (JTAG_SEL2_GLBL and JTAG_CAPTURE_GLBL and JTAG_TCK_GLBL)); + RESET <= JTAG_RESET_GLBL ; + SEL1 <= JTAG_SEL1_GLBL; + SEL2 <= JTAG_SEL2_GLBL; + SHIFT <= JTAG_SHIFT_GLBL; + TCK <= JTAG_TCK_GLBL; + TDI <= JTAG_TDI_GLBL; + TMS <= JTAG_TMS_GLBL; + UPDATE <= JTAG_UPDATE_GLBL; + + JTAG_USER_TDO1_GLBL <= TDO1; + JTAG_USER_TDO2_GLBL <= TDO2; + +-- synopsys translate_on + + +end BSCAN_SPARTAN3A_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Register State Capture for Bitstream Readback for SPARTAN3 +-- /___/ /\ Filename : CAPTURE_SPARTAN3A.vhd +-- \ \ / \ Timestamp : Tue Jul 5 15:01:35 PDT 2005 +-- \___\/\___\ +-- +-- Revision: +-- 07/05/05 - Initial version. + +----- CELL CAPTURE_SPARTAN3A ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity CAPTURE_SPARTAN3A is + generic( + ONESHOT : boolean := true + ); + port( + CAP : in std_ulogic; + CLK : in std_ulogic + ); +end CAPTURE_SPARTAN3A; + +architecture CAPTURE_SPARTAN3A_V of CAPTURE_SPARTAN3A is +begin +end CAPTURE_SPARTAN3A_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Device DNA Data Access Port +-- /___/ /\ Filename : DNA_PORT.vhd +-- \ \ / \ Timestamp : Mon Oct 10 15:21:52 PDT 2005 +-- \___\/\___\ +-- +-- Revision: +-- 10/10/05 - Initial version +-- 06/04/08 - CR 472697 -- added check for SIM_DNA_VALUE +-- End Revision + +----- CELL DNA_PORT ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.vpkg.all; + +entity DNA_PORT is + generic( + + SIM_DNA_VALUE : bit_vector := X"000000000000000" + ); + + port( + DOUT : out std_ulogic; + + CLK : in std_ulogic; + DIN : in std_ulogic; + READ : in std_ulogic; + SHIFT : in std_ulogic + ); + +end DNA_PORT; + +architecture DNA_PORT_V of DNA_PORT is + + +----------------------------------------------------------- +----------------------------------------------------------- + function eval_init ( + sim_dna_val : in bit_vector; + msb : in integer + ) return std_logic_vector is + variable ret_sim_dna_val : std_logic_vector (msb downto 0); + variable tmp_sim_dna_val : std_logic_vector ((sim_dna_val'length-1) downto 0); + begin + if (sim_dna_val'length >= msb ) then +-- ret_sim_dna_val(msb downto 0) := To_stdLogicVector(sim_dna_val((sim_dna_val'length-msb-1) to (sim_dna_val'length-1))); + tmp_sim_dna_val((sim_dna_val'length-1) downto 0) := To_stdLogicVector(sim_dna_val); + ret_sim_dna_val(msb downto 0) := tmp_sim_dna_val(msb downto 0); + + else + ret_sim_dna_val := (others => '0'); + ret_sim_dna_val((sim_dna_val'length-1) downto 0) := To_stdLogicVector(sim_dna_val); + end if; + + return ret_sim_dna_val(msb downto 0); + end; +----------------------------------------------------------- +----------------------------------------------------------- + + constant MAX_DNA_BITS : integer := 57; + constant MSB_DNA_BITS : integer := (MAX_DNA_BITS - 1); + + constant SYNC_PATH_DELAY : time := 100 ps; + + signal CLK_ipd : std_ulogic := 'X'; + signal DIN_ipd : std_ulogic := 'X'; + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := '0'; + signal READ_ipd : std_ulogic := 'X'; + signal SHIFT_ipd : std_ulogic := 'X'; + + signal CLK_dly : std_ulogic := 'X'; + signal DIN_dly : std_ulogic := 'X'; + signal GSR_dly : std_ulogic := '0'; + signal READ_dly : std_ulogic := 'X'; + signal SHIFT_dly : std_ulogic := 'X'; + + signal DOUT_zd : std_ulogic := 'X'; + + signal dna_val : std_logic_vector(MSB_DNA_BITS downto 0) := eval_init(SIM_DNA_VALUE, MSB_DNA_BITS); + + signal Violation : std_ulogic := '0'; + +begin + --------------------- + -- INPUT PATH DELAYs + -------------------- + + CLK_dly <= CLK after 0 ps; + DIN_dly <= DIN after 0 ps; + READ_dly <= READ after 0 ps; + SHIFT_dly <= SHIFT after 0 ps; + GSR_dly <= GSR after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialization ### +--#################################################################### + prcs_init:process + begin + if(dna_val(MSB_DNA_BITS downto (MSB_DNA_BITS -1)) /= "10") then + assert false + report "Attribute Syntax Warning: SIM_DNA_VALUE bits [56:55] on component DNA_PORT do not match the expected value ""10"". The simulation will not exactly model the hardware behavior, as detailed in the Spartan-3 Generation FPGA User Guide." + severity warning; + end if; + wait; + end process prcs_init; + +--#################################################################### +--##### READ ### +--#################################################################### + prcs_read:process(CLK_dly, GSR_dly, READ_dly, SHIFT_dly) + begin + if(GSR_dly = '1') then + dna_val(0) <= '0'; + elsif(GSR_dly = '0') then + if(rising_edge(CLK_dly)) then + if(READ_dly = '1') then + dna_val(MSB_DNA_BITS downto 0) <= eval_init(SIM_DNA_VALUE, MSB_DNA_BITS); + dna_val(0) <= '1'; + elsif(READ_dly = '0') then + if(SHIFT_dly = '1') then + dna_val <= DIN_dly & dna_val(MSB_DNA_BITS downto 1); + end if; -- SHIFT_dly = '1' + end if; -- READ_dly = '1' + end if; -- rising_edge(CLK_dly) + end if; -- GSR_dly = '1' + end process prcs_read; + +--#################################################################### +--##### Update Zero Delay Output ##### +--#################################################################### + +DOUT_zd <= dna_val(0); + + + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(DOUT_zd) + begin + DOUT <= DOUT_zd after SYNC_PATH_DELAY; + end process prcs_output; + +end DNA_PORT_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / Dynamically Adjustable Input Delay Buffer +-- /___/ /\ Filename : IBUF_DLY_ADJ.vhd +-- \ \ / \ Timestamp : Tue Apr 19 08:18:20 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 04/19/05 - Initial version. +-- 06/30/06 - CR 233887 -- Corrected generic ordering +-- 08/08/07 - CR 439320 -- Simprim fix -- Added attributes SIM_DELAY0, ... SIM_DELAY16 to fix timing issues +-- 09/11/07 - CR 447604 -- When S[2:0]=0, it should correlate to 1 tap +-- End Revision + + +----- CELL IBUF_DLY_ADJ ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + + +library unisim; +use unisim.vpkg.all; + +entity IBUF_DLY_ADJ is + + generic( + + DELAY_OFFSET : string := "OFF"; + IOSTANDARD : string := "DEFAULT" + ); + + port( + O : out std_ulogic; + + I : in std_ulogic; + S : in std_logic_vector (2 downto 0) + ); + +end IBUF_DLY_ADJ; + +architecture IBUF_DLY_ADJ_V OF IBUF_DLY_ADJ is + + constant SIM_TAPDELAY_VALUE : integer := 200; + constant SPECTRUM_OFFSET_DELAY : time := 1600 ps; + + --------------------------------------------------------- + -- Function str_2_int converts string to integer + --------------------------------------------------------- + function str_2_int(str: in string ) return integer is + variable int : integer; + variable val : integer := 0; + variable neg_flg : boolean := false; + variable is_it_int : boolean := true; + begin + int := 0; + val := 0; + is_it_int := true; + neg_flg := false; + + for i in 1 to str'length loop + case str(i) is + when '-' + => + if(i = 1) then + neg_flg := true; + val := -1; + end if; + when '1' + => val := 1; + when '2' + => val := 2; + when '3' + => val := 3; + when '4' + => val := 4; + when '5' + => val := 5; + when '6' + => val := 6; + when '7' + => val := 7; + when '8' + => val := 8; + when '9' + => val := 9; + when '0' + => val := 0; + when others + => is_it_int := false; + end case; + if(val /= -1) then + int := int *10 + val; + end if; + val := 0; + end loop; + if(neg_flg) then + int := int * (-1); + end if; + + if(NOT is_it_int) then + int := -9999; + end if; + return int; + end; +----------------------------------------------------------- + + constant MAX_S : integer := 3; + constant MAX_TAP : integer := 7; + constant MIN_TAP : integer := 0; + + constant MSB_S : integer := MAX_S -1; + constant LSB_S : integer := 0; + + constant SYNC_PATH_DELAY : time := 0 ps; + + + signal O_zd : std_ulogic := 'X'; + signal O_viol : std_ulogic := 'X'; + + signal I_ipd : std_ulogic := 'X'; + signal S_ipd : std_logic_vector(MSB_S downto LSB_S); + + signal INITIAL_DELAY : time := 0 ps; + signal DELAY : time := 0 ps; + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + I_ipd <= I after 0 ps; + S_ipd <= S after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + variable TapCount_var : integer := 0; + variable IsTapDelay_var : boolean := true; + variable IsTapFixed_var : boolean := false; + variable IsTapDefault_var : boolean := false; + begin + if((DELAY_OFFSET /= "ON") and (DELAY_OFFSET /= "on") and + (DELAY_OFFSET /= "OFF") and (DELAY_OFFSET /= "off")) then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DELAY_OFFSET ", + EntityName => "/IBUF_DLY_ADJ", + GenericValue => DELAY_OFFSET, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " ON or OFF ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + if((DELAY_OFFSET = "ON") or (DELAY_OFFSET = "on")) then +-- CR 447604 +-- INITIAL_DELAY <= SPECTRUM_OFFSET_DELAY; + INITIAL_DELAY <= SPECTRUM_OFFSET_DELAY + (SIM_TAPDELAY_VALUE * 1 ps); + else +-- INITIAL_DELAY <= 0 ps; + INITIAL_DELAY <= SIM_TAPDELAY_VALUE * 1 ps; + end if; + wait; + end process prcs_init; +--#################################################################### +--##### CALCULATE DELAY ##### +--#################################################################### + prcs_s:process(S_ipd) + variable TapCount_var : integer := 0; + variable FIRST_TIME : boolean :=true; + variable BaseTime_var : time := 1 ps ; + variable delay_var : time := 0 ps ; + variable S_int_var : integer := 0; + begin + S_int_var := SLV_TO_INT(S_ipd); + + if((S_int_var >= MIN_TAP) and (S_int_var <= MAX_TAP)) then + Delay <= S_int_var * SIM_TAPDELAY_VALUE * BaseTime_var + INITIAL_DELAY; + end if; + end process prcs_s; + +--#################################################################### +--##### DELAY INPUT ##### +--#################################################################### + prcs_i:process(I_ipd) + begin + O_zd <= transport I_ipd after delay; + end process prcs_i; + + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(O_zd) + begin + O <= O_zd after SYNC_PATH_DELAY; + end process prcs_output; +--#################################################################### + + +end IBUF_DLY_ADJ_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / Dynamically Adjustable Differential Input Delay Buffer +-- /___/ /\ Filename : IBUFDS_DLY_ADJ.vhd +-- \ \ / \ Timestamp : Tue Apr 19 08:18:20 PST 2005 +-- \___\/\___\ +-- +-- Revision: +-- 04/19/05 - Initial version. +-- 06/30/06 - CR 233887 -- Corrected generic ordering +-- 08/08/07 - CR 439320 -- Simprim fix -- Added attributes SIM_DELAY0, ... SIM_DELAY16 to fix timing issues +-- 09/11/07 - CR 447604 -- When S[2:0]=0, it should correlate to 1 tap +-- End Revision +----- CELL IBUFDS_DLY_ADJ ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + + +library unisim; +use unisim.vpkg.all; + +entity IBUFDS_DLY_ADJ is + + generic( + + DELAY_OFFSET : string := "OFF"; + DIFF_TERM : boolean := FALSE; + IOSTANDARD : string := "DEFAULT" + ); + + port( + O : out std_ulogic; + + I : in std_ulogic; + IB : in std_ulogic; + S : in std_logic_vector (2 downto 0) + ); + +end IBUFDS_DLY_ADJ; + +architecture IBUFDS_DLY_ADJ_V OF IBUFDS_DLY_ADJ is + + constant SIM_TAPDELAY_VALUE : integer := 200; + constant SPECTRUM_OFFSET_DELAY : time := 1600 ps; + + --------------------------------------------------------- + -- Function str_2_int converts string to integer + --------------------------------------------------------- + function str_2_int(str: in string ) return integer is + variable int : integer; + variable val : integer := 0; + variable neg_flg : boolean := false; + variable is_it_int : boolean := true; + begin + int := 0; + val := 0; + is_it_int := true; + neg_flg := false; + + for i in 1 to str'length loop + case str(i) is + when '-' + => + if(i = 1) then + neg_flg := true; + val := -1; + end if; + when '1' + => val := 1; + when '2' + => val := 2; + when '3' + => val := 3; + when '4' + => val := 4; + when '5' + => val := 5; + when '6' + => val := 6; + when '7' + => val := 7; + when '8' + => val := 8; + when '9' + => val := 9; + when '0' + => val := 0; + when others + => is_it_int := false; + end case; + if(val /= -1) then + int := int *10 + val; + end if; + val := 0; + end loop; + if(neg_flg) then + int := int * (-1); + end if; + + if(NOT is_it_int) then + int := -9999; + end if; + return int; + end; +----------------------------------------------------------- + + + constant MAX_S : integer := 3; + constant MAX_TAP : integer := 7; + constant MIN_TAP : integer := 0; + + constant MSB_S : integer := MAX_S -1; + constant LSB_S : integer := 0; + + constant SYNC_PATH_DELAY : time := 0 ps; + + + signal O_zd : std_ulogic := 'X'; + signal O_viol : std_ulogic := 'X'; + + signal I_int : std_ulogic := 'X'; + + signal I_ipd : std_ulogic := 'X'; + signal IB_ipd : std_ulogic := 'X'; + signal S_ipd : std_logic_vector(MSB_S downto LSB_S); + + signal INITIAL_DELAY : time := 0 ps; + signal DELAY : time := 0 ps; + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + I_ipd <= I after 0 ps; + IB_ipd <= IB after 0 ps; + S_ipd <= S after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + variable TapCount_var : integer := 0; + variable IsTapDelay_var : boolean := true; + variable IsTapFixed_var : boolean := false; + variable IsTapDefault_var : boolean := false; + begin + if((DELAY_OFFSET /= "ON") and (DELAY_OFFSET /= "on") and + (DELAY_OFFSET /= "OFF") and (DELAY_OFFSET /= "off")) then + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Warning ", + GenericName => " DELAY_OFFSET ", + EntityName => "/IBUFDS_DLY_ADJ", + GenericValue => DELAY_OFFSET, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " ON or OFF ", + TailMsg => "", + MsgSeverity => failure + ); + end if; + + if((DELAY_OFFSET = "ON") or (DELAY_OFFSET = "on")) then +-- CR 447604 +-- INITIAL_DELAY <= SPECTRUM_OFFSET_DELAY; + INITIAL_DELAY <= SPECTRUM_OFFSET_DELAY + (SIM_TAPDELAY_VALUE * 1 ps); + else +-- INITIAL_DELAY <= 0 ps; + INITIAL_DELAY <= SIM_TAPDELAY_VALUE * 1 ps; + end if; + wait; + end process prcs_init; +--#################################################################### +--##### CALCULATE DELAY ##### +--#################################################################### + prcs_s:process(S_ipd) + variable TapCount_var : integer := 0; + variable FIRST_TIME : boolean :=true; + variable BaseTime_var : time := 1 ps ; + variable delay_var : time := 0 ps ; + variable S_int_var : integer := 0; + begin + S_int_var := SLV_TO_INT(S_ipd); + + if((S_int_var >= MIN_TAP) and (S_int_var <= MAX_TAP)) then + Delay <= S_int_var * SIM_TAPDELAY_VALUE * BaseTime_var + INITIAL_DELAY; + end if; + end process prcs_s; + + VitalBehavior : process (I_ipd, IB_ipd) + begin + if ((I_ipd = '1') and (IB_ipd = '0')) then + I_int <= TO_X01(I_ipd); + elsif ((I_ipd = '0') and (IB_ipd = '1')) then + I_int <= TO_X01(I_ipd); + end if; + end process; + +--#################################################################### +--##### DELAY INPUT ##### +--#################################################################### + prcs_i:process(I_int) + begin + O_zd <= transport I_int after delay; + end process prcs_i; + + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(O_zd) + begin + O <= O_zd after SYNC_PATH_DELAY; + end process prcs_output; +--#################################################################### + + +end IBUFDS_DLY_ADJ_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Internal Configuration Access Port for Spartan3A +-- /___/ /\ Filename : ICAP_SPARTAN3A.vhd +-- \ \ / \ Timestamp : Wed Jul 6 18:07:07 PDT 2005 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL ICAP_SPARTAN3A ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +entity ICAP_SPARTAN3A is + + port( + BUSY : out std_ulogic; + O : out std_logic_vector(7 downto 0); + + CE : in std_ulogic; + CLK : in std_ulogic; + I : in std_logic_vector(7 downto 0); + WRITE : in std_ulogic + ); + +end ICAP_SPARTAN3A; + +architecture ICAP_SPARTAN3A_V of ICAP_SPARTAN3A is + +begin +end ICAP_SPARTAN3A_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Jtag TAP contorller for SPARTAN3A +-- / / +-- /___/ /\ Filename : JTAG_SIM_SPARTAN3A.vhd +-- \ \ / \ Timestamp : Mon Aug 8 18:09:16 PDT 2005 +-- \___\/\___\ +-- +-- Revision: +-- 08/08/05 - Initial version. +-- End Revision + +----- CELL JTAG_SIM_SPARTAN3A ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; + +library unisim; +use unisim.vpkg.all; +use unisim.Vcomponents.all; + + + +entity JTAG_SIM_SPARTAN3A is + + generic( + PART_NAME : string := "3S200A" + ); + + port( + TDO : out std_ulogic; + + TCK : in std_ulogic; + TDI : in std_ulogic; + TMS : in std_ulogic + ); + +end JTAG_SIM_SPARTAN3A; + +architecture JTAG_SIM_SPARTAN3A_V OF JTAG_SIM_SPARTAN3A is + + + TYPE JtagTapState is (TestLogicReset, RunTestIdle,SelectDRScan, CaptureDR, + ShiftDR, Exit1DR, PauseDR, Exit2DR, UPdateDR, + SelectIRScan, CaptureIR, ShiftIR, Exit1IR, PauseIR, + Exit2IR, UPdateIR); + + +------------------------------------------------------------------------------- +----------------- Virtex4 Specific Constants --------------------------------- +------------------------------------------------------------------------------- + + TYPE JtagInstructionType is (UNKNOWN, IR_CAPTURE, BYPASS, IDCODE, USER1, USER2, USER3, USER4); + + TYPE PartType is (XC3S200A, XC3S400A, XC3S700A, XC3S1400A, XC3S1800A); + + constant IRLength : integer := 6; + constant IDLength : integer := 32; + + constant IR_CAPTURE_VAL : std_logic_vector ((IRLength -1) downto 0) := "010001"; + + constant BYPASS_INSTR : std_logic_vector ((IRLength -1) downto 0) := "111111"; + constant IDCODE_INSTR : std_logic_vector ((IRLength -1) downto 0) := "001001"; + constant USER1_INSTR : std_logic_vector ((IRLength -1) downto 0) := "000010"; + constant USER2_INSTR : std_logic_vector ((IRLength -1) downto 0) := "000011"; + constant USER3_INSTR : std_logic_vector ((IRLength -1) downto 0) := "XXXXXX"; + constant USER4_INSTR : std_logic_vector ((IRLength -1) downto 0) := "ZXXXXX"; + +-------------------------------------------------------- + + constant DELAY_SIG : time := 1 ps; + + constant Xon : boolean := true; + constant MsgOn : boolean := true; + + signal ticd_TCK : VitalDelayType := 0.0 ns; + + signal tisd_TDI_TCK : VitalDelayType := 0.0 ns; + signal tisd_TMS_TCK : VitalDelayType := 0.0 ns; + + signal tsetup_TMS_TCK_posedge_posedge : VitalDelayType := 1.0 ns; + signal tsetup_TMS_TCK_negedge_posedge : VitalDelayType := 1.0 ns; + + signal tsetup_TDI_TCK_posedge_posedge : VitalDelayType := 1.0 ns; + signal tsetup_TDI_TCK_negedge_posedge : VitalDelayType := 1.0 ns; + + signal thold_TMS_TCK_posedge_posedge : VitalDelayType := 2.0 ns; + signal thold_TMS_TCK_negedge_posedge : VitalDelayType := 2.0 ns; + + signal thold_TDI_TCK_posedge_posedge : VitalDelayType := 2.0 ns; + signal thold_TDI_TCK_negedge_posedge : VitalDelayType := 2.0 ns; + + signal tpd_TCK_TDO : VitalDelayType01 := (6.0 ns, 6.0 ns); + + signal CurrentState : JtagTapState := TestLogicReset; + signal JtagInstruction : JtagInstructionType := IDCODE; + + signal TCK_ipd : std_ulogic := 'X'; + signal TDI_ipd : std_ulogic := 'X'; + signal TMS_ipd : std_ulogic := 'X'; + signal TRST_ipd : std_ulogic := '0'; + + + signal TCK_dly : std_ulogic := 'X'; + signal TDI_dly : std_ulogic := 'X'; + signal TMS_dly : std_ulogic := 'X'; + signal TRST_dly : std_ulogic := '0'; + + signal TDO_zd : std_ulogic := 'X'; + signal TDO_viol : std_ulogic := 'X'; + +----------- signal declaration ------------------- + + signal CaptureDR_sig : std_ulogic := '0'; + signal RESET_sig : std_ulogic := '0'; + signal ShiftDR_sig : std_ulogic := '0'; + signal UpdateDR_sig : std_ulogic := '0'; + + signal ClkIR_active : std_ulogic := '0'; + + signal ClkIR_sig : std_ulogic := '0'; + signal ClkID_sig : std_ulogic := '0'; + signal ShiftIR_sig : std_ulogic := 'X'; + signal UpdateIR_sig : std_ulogic := 'X'; + signal ClkUpdateIR_sig : std_ulogic := '0'; + signal IRcontent_sig : std_logic_vector ((IRLength -1) downto 0) := (others => 'X'); + signal IDCODEval_sig : std_logic_vector ((IDLength -1) downto 0) := (others => 'X'); + + signal BypassReg : std_ulogic := '0'; + signal BYPASS_sig : std_ulogic := '0'; + signal IDCODE_sig : std_ulogic := '0'; + signal USER1_sig : std_ulogic := '0'; + signal USER2_sig : std_ulogic := '0'; + signal USER3_sig : std_ulogic := '0'; + signal USER4_sig : std_ulogic := '0'; + + signal TDO_latch : std_ulogic := 'Z'; + + signal Tlrst_sig : std_ulogic := '1'; + signal TlrstN_sig : std_ulogic := '1'; + + signal IRegLastBit_sig : std_ulogic := '0'; + signal IDregLastBit_sig : std_ulogic := '0'; + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + TCK_dly <= TCK after 0 ps; + TDI_dly <= TDI after 0 ps; + TMS_dly <= TMS after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialize ##### +--#################################################################### + prcs_init:process + variable PartName_var : PartType; + variable IDCODE_str : bit_vector ((IDLength -1) downto 0) ; + begin + if((PART_NAME = "3S200A") or (PART_NAME = "3s200a")) then + PartName_var := XC3S200A; + IDCODE_str := X"02218093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "3S400A") or (PART_NAME = "3s400a")) then + PartName_var := XC3S400A; + IDCODE_str := X"02220093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "3S700A") or (PART_NAME = "3s700a")) then + PartName_var := XC3S700A; + IDCODE_str := X"02228093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "3S1400A") or (PART_NAME = "3s1400a")) then + PartName_var := XC3S1400A; + IDCODE_str := X"02230093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + elsif((PART_NAME = "3S1800A") or (PART_NAME = "3s1800a")) then + PartName_var := XC3S1800A; + IDCODE_str := X"0224c093"; + IDCODEval_sig <= To_StdLogicVector(IDCODE_str); + else + assert false + report "Attribute Syntax Error: The allowed values for PART_NAME are 3S200A, 3S400A, 3S700A, 3S1400A or 3S1800A" + severity Failure; + end if; + + wait; + + end process prcs_init; +--#################################################################### +--##### JtagTapSM ##### +--#################################################################### + prcs_JtagTapSM:process(TCK_dly, TRST_dly) + begin + + if(TRST_dly = '1') then + CurrentState <= TestLogicReset; + elsif(TRST_dly = '0') then + if(rising_edge(TCK_dly)) then + case CurrentState is + ------------------------------- + ---- Reset path --------------- + ------------------------------- + when TestLogicReset => + if(TMS_dly = '0') then + CurrentState <= RunTestIdle; + end if; + when RunTestIdle => + if(TMS_dly = '1') then + CurrentState <= SelectDRScan; + end if; + ------------------------------- + ------ DR path --------------- + ------------------------------- + when SelectDRScan => + if(TMS_dly = '0') then + CurrentState <= CaptureDR; + elsif(TMS_dly = '1') then + CurrentState <= SelectIRScan; + end if; + when CaptureDR => + if(TMS_dly = '0') then + CurrentState <= ShiftDR; + elsif(TMS_dly = '1') then + CurrentState <= Exit1DR; + end if; + when ShiftDR => + if(TMS_dly = '1') then + CurrentState <= Exit1DR; + end if; + + if(IRcontent_sig = BYPASS_INSTR) then + BypassReg <= TDI_dly; + end if; + + when Exit1DR => + if(TMS_dly = '0') then + CurrentState <= PauseDR; + elsif(TMS_dly = '1') then + CurrentState <= UpdateDR; + end if; + when PauseDR => + if(TMS_dly = '1') then + CurrentState <= Exit2DR; + end if; + when Exit2DR => + if(TMS_dly = '0') then + CurrentState <= ShiftDR; + elsif(TMS_dly = '1') then + CurrentState <= UpdateDR; + end if; + when UpdateDR => + if(TMS_dly = '0') then + CurrentState <= RunTestIdle; + elsif(TMS_dly = '1') then + CurrentState <= SelectDRScan; + end if; + ------------------------------- + ------ IR path --------------- + ------------------------------- + when SelectIRScan => + if(TMS_dly = '0') then + CurrentState <= CaptureIR; + elsif(TMS_dly = '1') then + CurrentState <= TestLogicReset; + end if; + when CaptureIR => + if(TMS_dly = '0') then + CurrentState <= ShiftIR; + elsif(TMS_dly = '1') then + CurrentState <= Exit1IR; + end if; + when ShiftIR => + if(TMS_dly = '1') then + CurrentState <= Exit1IR; + end if; + when Exit1IR => + if(TMS_dly = '0') then + CurrentState <= PauseIR; + elsif(TMS_dly = '1') then + CurrentState <= UpdateIR; + end if; + when PauseIR => + if(TMS_dly = '1') then + CurrentState <= Exit2IR; + end if; + when Exit2IR => + if(TMS_dly = '0') then + CurrentState <= ShiftIR; + elsif(TMS_dly = '1') then + CurrentState <= UpdateIR; + end if; + when UpdateIR => + if(TMS_dly = '0') then + CurrentState <= RunTestIdle; + elsif(TMS_dly = '1') then + CurrentState <= SelectDRScan; + end if; + end case; + end if; + end if; + end process prcs_JtagTapSM; + +--#################################################################### +--##### CurrentState ##### +--#################################################################### + + prcs_CurrentState:process(TCK_dly, CurrentState, TRST_dly) + begin + + ClkIR_sig <= '1'; + + if(TRST_dly = '1') then + CaptureDR_sig <= '0'; + ShiftDR_sig <= '0'; + UpdateDR_sig <= '0'; + ShiftIR_sig <= '0'; + UpdateIR_sig <= '0'; + elsif(TRST_dly = '0') then + + case CurrentState is + + when TestLogicReset => + Tlrst_sig <= '1' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + + when CaptureDR => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '1' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + + when ShiftDR => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '1' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + + when UpdateDR => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '1' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + + when CaptureIR => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + ClkIR_sig <= TCK_dly; + + + when ShiftIR => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '1' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + ClkIR_sig <= TCK_dly; + + when UpdateIR => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '1' after DELAY_SIG; + + when others => + Tlrst_sig <= '0' after DELAY_SIG; + CaptureDR_sig <= '0' after DELAY_SIG; + ShiftDR_sig <= '0' after DELAY_SIG; + UpdateDR_sig <= '0' after DELAY_SIG; + ShiftIR_sig <= '0' after DELAY_SIG; + UpdateIR_sig <= '0' after DELAY_SIG; + end case; + end if; + + end process prcs_CurrentState; + +------------- ?? TCK NEGATIVE EDGE activities ---------- + + prcs_ClkIR:process(TCK_dly) + begin +-- ClkIR_sig <= ShiftIR_sig and TCK_dly; + CLkUpdateIR_sig <= UpdateIR_sig and not TCK_dly; + end process prcs_ClkIR; + + prcs_ClkID:process(TCK_dly) + begin + ClkID_sig <= IDCODE_sig and TCK_dly; + end process prcs_ClkID; + + prcs_glblsigs:process(TCK_dly, UpdateDR_sig) + begin + if(falling_edge(TCK_dly)) then + JTAG_CAPTURE_GLBL <= CaptureDR_sig; + -- CR 211337 Reset should go high as soon as it gets to State Trlst + -- JTAG_RESET_GLBL <= Tlrst_sig; + JTAG_SHIFT_GLBL <= ShiftDR_sig; + JTAG_UPDATE_GLBL <= UpdateDR_sig; + TlrstN_sig <= Tlrst_sig; + end if; + + if(falling_edge(UpdateDR_sig))then + JTAG_UPDATE_GLBL <= UpdateDR_sig; + end if; + + end process prcs_glblsigs; + +-- CR 211337 + prcs_reset:process(Tlrst_sig) + begin + JTAG_RESET_GLBL <= Tlrst_sig; + end process prcs_reset; + +--#################################################################### +--##### JtagIR ##### +--#################################################################### + prcs_JtagIR:process(ClkIR_sig, ClkUpdateIR_sig, ShiftIR_sig, TlrstN_sig, TRST_dly) + variable NextIRreg : std_logic_vector ((IRLength -1) downto 0) := IR_CAPTURE_VAL; + variable ir_int : std_logic_vector ((IRLength -1) downto 0) := IR_CAPTURE_VAL; + begin + NextIRreg((IRLength -1) downto 0) := (TDI_dly & ir_int((IRLength -1) downto 1)); + + if((TRST_dly = '1') or (TlrstN_sig = '1'))then + IRcontent_sig((IRLength -1) downto 0) <= IDCODE_INSTR; -- IDCODE instruction is loaded into IR reg. + IRegLastBit_sig <= ir_int(0); + elsif((TRST_dly = '0') and (TlrstN_sig = '0')) then + if(rising_edge(ClkIR_sig)) then + if(ShiftIR_sig = '1') then + ir_int((IRLength -1) downto 0) := NextIRreg((IRLength -1) downto 0); + IRegLastBit_sig <= ir_int(0); + else + ir_int := IR_CAPTURE_VAL ; + IRegLastBit_sig <= ir_int(0); + end if; + end if; + if(rising_edge(ClkUpdateIR_sig)) then + if(UpdateIR_sig = '1') then + IRcontent_sig <= ir_int; + end if; + end if; + end if; + end process prcs_JtagIR; +--#################################################################### +--##### JtagDecodeIR ##### +--#################################################################### + prcs_JtagDecodeIR:process(IRcontent_sig) + begin + case IRcontent_sig is + + when IR_CAPTURE_VAL => + JTagInstruction <= IR_CAPTURE; + + when BYPASS_INSTR => + JTagInstruction <= BYPASS; + BYPASS_sig <= '1'; + IDCODE_sig <= '0'; + USER1_sig <= '0'; + USER2_sig <= '0'; + USER3_sig <= '0'; + USER4_sig <= '0'; + + when IDCODE_INSTR => + JTagInstruction <= IDCODE; + BYPASS_sig <= '0'; + IDCODE_sig <= '1'; + USER1_sig <= '0'; + USER2_sig <= '0'; + USER3_sig <= '0'; + USER4_sig <= '0'; + + when USER1_INSTR => + JTagInstruction <= USER1; + BYPASS_sig <= '0'; + IDCODE_sig <= '0'; + USER1_sig <= '1'; + USER2_sig <= '0'; + USER3_sig <= '0'; + USER4_sig <= '0'; + + when USER2_INSTR => + JTagInstruction <= USER2; + BYPASS_sig <= '0'; + IDCODE_sig <= '0'; + USER1_sig <= '0'; + USER2_sig <= '1'; + USER3_sig <= '0'; + USER4_sig <= '0'; + + when USER3_INSTR => + JTagInstruction <= USER3; + BYPASS_sig <= '0'; + IDCODE_sig <= '0'; + USER1_sig <= '0'; + USER2_sig <= '0'; + USER3_sig <= '1'; + USER4_sig <= '0'; + + when USER4_INSTR => + JTagInstruction <= USER4; + BYPASS_sig <= '0'; + IDCODE_sig <= '0'; + USER1_sig <= '0'; + USER2_sig <= '0'; + USER3_sig <= '0'; + USER4_sig <= '1'; + when others => + JTagInstruction <= UNKNOWN; + NULL; + end case; + end process prcs_JtagDecodeIR; +--#################################################################### +--##### JtagIDCODE ##### +--#################################################################### + prcs_JtagIDCODE:process(ClkID_sig) + variable IDreg : bit_vector ((IDLength -1) downto 0); + begin + if(rising_edge(ClkID_sig)) then + if(ShiftDR_sig = '1') then + IDreg := IDreg sra 1; + IDreg(IDLength -1) := TO_BIT(TDI_dly); + else + IDreg := TO_BITVECTOR(IDCODEval_sig); + end if; + end if; + + IDregLastBit_sig <= TO_STDULOGIC(IDreg(0)); + + end process prcs_JtagIDCODE; +--#################################################################### +--#################################################################### +--##### JtagSetGlobalSignals ##### +--#################################################################### + prcs_JtagSetGlobalSignals:process(ClkUpdateIR_sig, Tlrst_sig, USER1_sig, USER2_sig, USER3_sig, USER4_sig) + begin + if(rising_edge(USER1_sig)) then + JTAG_SEL1_GLBL <= '1'; + JTAG_SEL2_GLBL <= '0'; + JTAG_SEL3_GLBL <= '0'; + JTAG_SEL4_GLBL <= '0'; + elsif(rising_edge(USER2_sig)) then + JTAG_SEL1_GLBL <= '0'; + JTAG_SEL2_GLBL <= '1'; + JTAG_SEL3_GLBL <= '0'; + JTAG_SEL4_GLBL <= '0'; + elsif(rising_edge(USER3_sig)) then + JTAG_SEL1_GLBL <= '0'; + JTAG_SEL2_GLBL <= '0'; + JTAG_SEL3_GLBL <= '1'; + JTAG_SEL4_GLBL <= '0'; + elsif(rising_edge(USER4_sig)) then + JTAG_SEL1_GLBL <= '0'; + JTAG_SEL2_GLBL <= '0'; + JTAG_SEL3_GLBL <= '0'; + JTAG_SEL4_GLBL <= '1'; + elsif(rising_edge(ClkUpdateIR_sig)) then + JTAG_SEL1_GLBL <= '0'; + JTAG_SEL2_GLBL <= '0'; + JTAG_SEL3_GLBL <= '0'; + JTAG_SEL4_GLBL <= '0'; + elsif(rising_edge(Tlrst_sig)) then + JTAG_SEL1_GLBL <= '0'; + JTAG_SEL2_GLBL <= '0'; + JTAG_SEL3_GLBL <= '0'; + JTAG_SEL4_GLBL <= '0'; + end if; + + end process prcs_JtagSetGlobalSignals; + +--#################################################################### + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + + JTAG_TCK_GLBL <= TCK_dly; + JTAG_TDI_GLBL <= TDI_dly; + JTAG_TMS_GLBL <= TMS_dly; + JTAG_TRST_GLBL <= TRST_dly; + + TDO_latch <= BypassReg + when ((CurrentState = ShiftDR) and (IRcontent_sig=BYPASS_INSTR)) + else IRegLastBit_sig + when (CurrentState = ShiftIR) + else IDregLastBit_sig + when ((CurrentState = ShiftDR) and (IRcontent_sig=IDCODE_INSTR)) + else JTAG_USER_TDO1_GLBL + when ((CurrentState = ShiftDR) and (IRcontent_sig=USER1_INSTR)) + else JTAG_USER_TDO2_GLBL + when ((CurrentState = ShiftDR) and (IRcontent_sig=USER2_INSTR)) + else JTAG_USER_TDO3_GLBL + when ((CurrentState = ShiftDR) and (IRcontent_sig=USER3_INSTR)) + else JTAG_USER_TDO4_GLBL + when ((CurrentState = ShiftDR) and (IRcontent_sig=USER4_INSTR)) + else 'Z'; + +-- prcs_TDO:process(TCK_dly) +-- begin +-- if(falling_edge(TCK_dly)) then +-- TDO <= TDO_latch; +-- end if; +-- end process prcs_TDO; + +--#################################################################### +--##### Timing ##### +--#################################################################### + VITALBehavior : process (TCK_dly, TDI_dly, TMS_dly) + + variable PInfo_TCK : VitalPeriodDataType := VitalPeriodDataInit; + variable Pviol_TCK : std_ulogic := '0'; + + variable Tmkr_TDI_TCK_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tviol_TDI_TCK_posedge : std_ulogic := '0'; + + variable Tmkr_TMS_TCK_posedge : VitalTimingDataType := VitalTimingDataInit; + variable Tviol_TMS_TCK_posedge : std_ulogic := '0'; + + variable Violation : std_ulogic := '0'; + + variable TDO_GlitchData : VitalGlitchDataType; + + + begin + VitalSetupHoldCheck ( + Violation => Tviol_TDI_TCK_posedge, + TimingData => Tmkr_TDI_TCK_posedge, + TestSignal => TDI_dly, + TestSignalName => "TDI", + TestDelay => tisd_TDI_TCK, + RefSignal => TCK_dly, + RefSignalName => "TCK", + RefDelay => ticd_TCK, + SetupHigh => tsetup_TDI_TCK_posedge_posedge, + SetupLow => tsetup_TDI_TCK_negedge_posedge, + HoldLow => thold_TDI_TCK_posedge_posedge, + HoldHigh => thold_TDI_TCK_negedge_posedge, + CheckEnabled => TO_X01(TRST_dly) = '0', + RefTransition => 'R', + HeaderMsg => "/X_JTAG_SIM_VIRTEX4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + VitalSetupHoldCheck ( + Violation => Tviol_TMS_TCK_posedge, + TimingData => Tmkr_TMS_TCK_posedge, + TestSignal => TMS_dly, + TestSignalName => "TMS", + TestDelay => tisd_TMS_TCK, + RefSignal => TCK_dly, + RefSignalName => "TCK", + RefDelay => ticd_TCK, + SetupHigh => tsetup_TMS_TCK_posedge_posedge, + SetupLow => tsetup_TMS_TCK_negedge_posedge, + HoldLow => thold_TMS_TCK_posedge_posedge, + HoldHigh => thold_TMS_TCK_negedge_posedge, + CheckEnabled => TO_X01(TRST_dly) = '0', + RefTransition => 'R', + HeaderMsg => "/X_JTAG_SIM_VIRTEX4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + + if(falling_edge(TCK_dly)) then + VitalPathDelay01 ( + OutSignal => TDO, + GlitchData => TDO_GlitchData, + OutSignalName => "TDO", + OutTemp => TDO_latch, + Paths => (0 => (TCK_dly'last_event, tpd_TCK_TDO, TRST_dly = '0')), + Mode => VitalTransport, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => warning); + end if; + end process; + +--#################################################################### +--#################################################################### + + +end JTAG_SIM_SPARTAN3A_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +-- /___/ /\ Filename : RAMB16BWE_S18_S18.vhd +-- \ \ / \ Timestamp : Wed Jun 8 16:43:35 PST 2005 +-- \___\/\___\ +-- +-- Generated by : write_vhdl +-- +-- Revision: +-- 06/08/05 - Initial version. +-- End Revision + +----- CELL RAMB16BWE_S18_S18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity RAMB16BWE_S18_S18 is +generic ( + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"00000"; + INIT_B : bit_vector := X"00000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"00000"; + SRVAL_B : bit_vector := X"00000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + +port ( + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPA : out std_logic_vector(1 downto 0); + DOPB : out std_logic_vector(1 downto 0); + + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPA : in std_logic_vector(1 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(1 downto 0); + WEB : in std_logic_vector(1 downto 0) + ); +end RAMB16BWE_S18_S18; + +-- Architecture body -- + +architecture RAMB16BWE_S18_S18_V of RAMB16BWE_S18_S18 is + + signal DOA_open : std_logic_vector(15 downto 0); + signal DOB_open : std_logic_vector(15 downto 0); + signal DOPA_open : std_logic_vector(1 downto 0); + signal DOPB_open : std_logic_vector(1 downto 0); + + signal ADDRA_GND : std_logic_vector(3 downto 0) := (others => '0'); + signal ADDRB_GND : std_logic_vector(3 downto 0) := (others => '0'); + + signal DIA_GND : std_logic_vector(15 downto 0) := (others => '0'); + signal DIB_GND : std_logic_vector(15 downto 0) := (others => '0'); + + signal DIPA_GND : std_logic_vector(1 downto 0) := (others => '0'); + signal DIPB_GND : std_logic_vector(1 downto 0) := (others => '0'); + +begin +-- RAMB16BWE Instantiation (port map, generic map) +RAMB16BWE_inst : RAMB16BWE + generic map ( + DATA_WIDTH_A => 18, + DATA_WIDTH_B => 18, + + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + + INIT_A => INIT_A, + INIT_B => INIT_B, + + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + + SRVAL_A => SRVAL_A, + SRVAL_B => SRVAL_B, + + WRITE_MODE_A => WRITE_MODE_A, + WRITE_MODE_B => WRITE_MODE_B + ) +port map ( + ADDRA(13 downto 4) => ADDRA, + ADDRA(3 downto 0) => ADDRA_GND(3 downto 0), + ADDRB(13 downto 4) => ADDRB, + ADDRB(3 downto 0) => ADDRB_GND(3 downto 0), + CLKA => CLKA, + CLKB => CLKB, + DIA(15 downto 0) => DIA, + DIA(31 downto 16) => DIA_GND, + DIB(15 downto 0) => DIB, + DIB(31 downto 16) => DIB_GND, + DIPA(1 downto 0) => DIPA, + DIPA(3 downto 2) => DIPA_GND, + DIPB(1 downto 0) => DIPB, + DIPB(3 downto 2) => DIPB_GND, + ENA => ENA, + ENB => ENB, + SSRA => SSRA, + SSRB => SSRB, + WEA(0) => WEA(0), + WEA(1) => WEA(1), + WEA(2) => WEA(0), + WEA(3) => WEA(1), + WEB(0) => WEB(0), + WEB(1) => WEB(1), + WEB(2) => WEB(0), + WEB(3) => WEB(1), + DOA(15 downto 0) => DOA, + DOA(31 downto 16) => DOA_open, + DOB(15 downto 0) => DOB, + DOB(31 downto 16) => DOB_open, + DOPA(1 downto 0) => DOPA, + DOPA(3 downto 2) => DOPA_open, + DOPB(1 downto 0) => DOPB, + DOPB(3 downto 2) => DOPB_open + ); + +end RAMB16BWE_S18_S18_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +-- /___/ /\ Filename : RAMB16BWE_S18_S9.vhd +-- \ \ / \ Timestamp : Wed Jun 8 16:43:35 PST 2005 +-- \___\/\___\ +-- +-- Generated by : write_vhdl +-- +-- Revision: +-- 06/08/05 - Initial version. +-- End Revision + +----- CELL RAMB16BWE_S18_S9 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity RAMB16BWE_S18_S9 is +generic ( + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"00000"; + INIT_B : bit_vector := X"000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"00000"; + SRVAL_B : bit_vector := X"000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + +port ( + DOA : out std_logic_vector(15 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPA : out std_logic_vector(1 downto 0); + DOPB : out std_logic_vector(0 downto 0); + + ADDRA : in std_logic_vector(9 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(15 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPA : in std_logic_vector(1 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(1 downto 0); + WEB : in std_ulogic + ); +end RAMB16BWE_S18_S9; + +-- Architecture body -- + +architecture RAMB16BWE_S18_S9_V of RAMB16BWE_S18_S9 is + + signal DOA_open : std_logic_vector(15 downto 0); + signal DOB_open : std_logic_vector(23 downto 0); + signal DOPA_open : std_logic_vector(1 downto 0); + signal DOPB_open : std_logic_vector(2 downto 0); + + signal ADDRA_GND : std_logic_vector(3 downto 0) := (others => '0'); + signal ADDRB_GND : std_logic_vector(2 downto 0) := (others => '0'); + + signal DIA_GND : std_logic_vector(15 downto 0) := (others => '0'); + signal DIB_GND : std_logic_vector(23 downto 0) := (others => '0'); + + signal DIPA_GND : std_logic_vector(1 downto 0) := (others => '0'); + signal DIPB_GND : std_logic_vector(2 downto 0) := (others => '0'); + +begin +-- RAMB16BWE Instantiation (port map, generic map) +RAMB16BWE_inst : RAMB16BWE + generic map ( + DATA_WIDTH_A => 18, + DATA_WIDTH_B => 9, + + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + + INIT_A => INIT_A, + INIT_B => INIT_B, + + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + + SRVAL_A => SRVAL_A, + SRVAL_B => SRVAL_B, + + WRITE_MODE_A => WRITE_MODE_A, + WRITE_MODE_B => WRITE_MODE_B + ) +port map ( + ADDRA(13 downto 4) => ADDRA, + ADDRA(3 downto 0) => ADDRA_GND(3 downto 0), + ADDRB(13 downto 3) => ADDRB, + ADDRB(2 downto 0) => ADDRB_GND(2 downto 0), + CLKA => CLKA, + CLKB => CLKB, + DIA(15 downto 0) => DIA, + DIA(31 downto 16) => DIA_GND, + DIB(7 downto 0) => DIB, + DIB(31 downto 8) => DIB_GND, + DIPA(1 downto 0) => DIPA, + DIPA(3 downto 2) => DIPA_GND, + DIPB(0 downto 0) => DIPB, + DIPB(3 downto 1) => DIPB_GND, + ENA => ENA, + ENB => ENB, + SSRA => SSRA, + SSRB => SSRB, + WEA(0) => WEA(0), + WEA(1) => WEA(1), + WEA(2) => WEA(0), + WEA(3) => WEA(1), + WEB(0) => WEB, + WEB(1) => WEB, + WEB(2) => WEB, + WEB(3) => WEB, + DOA(15 downto 0) => DOA, + DOA(31 downto 16) => DOA_open, + DOB(7 downto 0) => DOB, + DOB(31 downto 8) => DOB_open, + DOPA(1 downto 0) => DOPA, + DOPA(3 downto 2) => DOPA_open, + DOPB(0 downto 0) => DOPB, + DOPB(3 downto 1) => DOPB_open + ); + +end RAMB16BWE_S18_S9_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +-- /___/ /\ Filename : RAMB16BWE_S18.vhd +-- \ \ / \ Timestamp : Wed Jun 8 16:43:35 PST 2005 +-- \___\/\___\ +-- +-- Generated by : write_vhdl +-- +-- Revision: +-- 06/08/05 - Initial version. +-- End Revision + +----- CELL RAMB16BWE_S18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity RAMB16BWE_S18 is +generic ( + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT : bit_vector := X"00000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SRVAL : bit_vector := X"00000"; + + WRITE_MODE : string := "WRITE_FIRST" + ); + +port ( + DO : out std_logic_vector(15 downto 0); + DOP : out std_logic_vector(1 downto 0); + + ADDR : in std_logic_vector(9 downto 0); + CLK : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DIP : in std_logic_vector(1 downto 0); + EN : in std_ulogic; + SSR : in std_ulogic; + WE : in std_logic_vector(1 downto 0) + ); +end RAMB16BWE_S18; + +-- Architecture body -- + +architecture RAMB16BWE_S18_V of RAMB16BWE_S18 is + + signal DOA_open : std_logic_vector(15 downto 0); + signal DOB_open : std_logic_vector(31 downto 0); + signal DOPA_open : std_logic_vector(1 downto 0); + signal DOPB_open : std_logic_vector(3 downto 0); + + signal ADDRA_GND : std_logic_vector(3 downto 0) := (others => '0'); + signal ADDRB_GND : std_logic_vector(13 downto 0) := (others => '0'); + + signal DIA_GND : std_logic_vector(15 downto 0) := (others => '0'); + signal DIB_GND : std_logic_vector(31 downto 0) := (others => '0'); + + signal DIPA_GND : std_logic_vector(1 downto 0) := (others => '0'); + signal DIPB_GND : std_logic_vector(3 downto 0) := (others => '0'); + + signal CLKB_GND, ENB_GND, SSRB_GND : std_ulogic := '0'; + signal WEB_GND : std_logic_vector(3 downto 0) := (others => '0'); + +begin +-- RAMB16BWE Instantiation (port map, generic map) +RAMB16BWE_inst : RAMB16BWE + generic map ( + DATA_WIDTH_A => 18, + + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + + INIT_A => INIT, + + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + + SIM_COLLISION_CHECK => "NONE", + + SRVAL_A => SRVAL, + + WRITE_MODE_A => WRITE_MODE + ) +port map ( + ADDRA(13 downto 4) => ADDR, + ADDRA(3 downto 0) => ADDRA_GND(3 downto 0), + ADDRB(13 downto 0) => ADDRB_GND(13 downto 0), + CLKA => CLK, + CLKB => CLKB_GND, + DIA(15 downto 0) => DI, + DIA(31 downto 16) => DIA_GND, + DIB(31 downto 0) => DIB_GND, + DIPA(1 downto 0) => DIP, + DIPA(3 downto 2) => DIPA_GND, + DIPB(3 downto 0) => DIPB_GND, + ENA => EN, + ENB => ENB_GND, + SSRA => SSR, + SSRB => SSRB_GND, + WEA(0) => WE(0), + WEA(1) => WE(1), + WEA(2) => WE(0), + WEA(3) => WE(1), + WEB => WEB_GND, + DOA(15 downto 0) => DO, + DOA(31 downto 16) => DOA_open, + DOB(31 downto 0) => DOB_open, + DOPA(1 downto 0) => DOP, + DOPA(3 downto 2) => DOPA_open, + DOPB(3 downto 0) => DOPB_open + ); + +end RAMB16BWE_S18_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +-- /___/ /\ Filename : RAMB16BWE_S36_S18.vhd +-- \ \ / \ Timestamp : Wed Jun 8 16:43:35 PST 2005 +-- \___\/\___\ +-- +-- Generated by : write_vhdl +-- +-- Revision: +-- 06/08/05 - Initial version. +-- End Revision + +----- CELL RAMB16BWE_S36_S18 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity RAMB16BWE_S36_S18 is +generic ( + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"00000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"00000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + +port ( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(15 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(1 downto 0); + + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(9 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(15 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(1 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(3 downto 0); + WEB : in std_logic_vector(1 downto 0) + ); +end RAMB16BWE_S36_S18; + +-- Architecture body -- + +architecture RAMB16BWE_S36_S18_V of RAMB16BWE_S36_S18 is + + signal DOB_open : std_logic_vector(15 downto 0); + signal DOPB_open : std_logic_vector(1 downto 0); + + signal ADDRA_GND : std_logic_vector(4 downto 0) := (others => '0'); + signal ADDRB_GND : std_logic_vector(3 downto 0) := (others => '0'); + + signal DIB_GND : std_logic_vector(15 downto 0) := (others => '0'); + + signal DIPB_GND : std_logic_vector(1 downto 0) := (others => '0'); + + +begin + +-- RAMB16BWE Instantiation + +RAMB16BWE_inst : RAMB16BWE + generic map ( + DATA_WIDTH_A => 36, + DATA_WIDTH_B => 18, + + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + + INIT_A => INIT_A, + INIT_B => INIT_B, + + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + + SRVAL_A => SRVAL_A, + SRVAL_B => SRVAL_B, + + WRITE_MODE_A => WRITE_MODE_A, + WRITE_MODE_B => WRITE_MODE_B + ) + port map ( + ADDRA(13 downto 5) => ADDRA, + ADDRA(4 downto 0) => ADDRA_GND(4 downto 0), + ADDRB(13 downto 4) => ADDRB, + ADDRB(3 downto 0) => ADDRB_GND(3 downto 0), + CLKA => CLKA, + CLKB => CLKB, + DIA(31 downto 0) => DIA, + DIB(15 downto 0) => DIB, + DIB(31 downto 16) => DIB_GND, + DIPA(3 downto 0) => DIPA, + DIPB(1 downto 0) => DIPB, + DIPB(3 downto 2) => DIPB_GND, + ENA => ENA, + ENB => ENB, + SSRA => SSRA, + SSRB => SSRB, + WEA(0) => WEA(0), + WEA(1) => WEA(1), + WEA(2) => WEA(2), + WEA(3) => WEA(3), + WEB(0) => WEB(0), + WEB(1) => WEB(1), + WEB(2) => WEB(0), + WEB(3) => WEB(1), + DOA(31 downto 0) => DOA, + DOB(15 downto 0) => DOB, + DOB(31 downto 16) => DOB_open, + DOPA(3 downto 0) => DOPA, + DOPB(1 downto 0) => DOPB, + DOPB(3 downto 2) => DOPB_open + + ); +end RAMB16BWE_S36_S18_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +-- /___/ /\ Filename : RAMB16BWE_S36_S36.vhd +-- \ \ / \ Timestamp : Wed Jun 8 16:43:35 PST 2005 +-- \___\/\___\ +-- +-- Generated by : write_vhdl +-- +-- Revision: +-- 06/08/05 - Initial version. +-- End Revision + +----- CELL RAMB16BWE_S36_S36 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity RAMB16BWE_S36_S36 is +generic ( + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + +port ( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(31 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(3 downto 0); + + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(8 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(31 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(3 downto 0); + WEB : in std_logic_vector(3 downto 0) + ); +end RAMB16BWE_S36_S36; + +-- Architecture body -- + +architecture RAMB16BWE_S36_S36_V of RAMB16BWE_S36_S36 is + + signal ADDRA_GND : std_logic_vector(4 downto 0) := (others => '0'); + signal ADDRB_GND : std_logic_vector(4 downto 0) := (others => '0'); + + + +begin + +-- RAMB16BWE Instantiation + +RAMB16BWE_inst : RAMB16BWE + generic map ( + DATA_WIDTH_A => 36, + DATA_WIDTH_B => 36, + + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INIT_A => INIT_A, + INIT_B => INIT_B, + + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + + SRVAL_A => SRVAL_A, + SRVAL_B => SRVAL_B, + + WRITE_MODE_A => WRITE_MODE_A, + WRITE_MODE_B => WRITE_MODE_B + ) + port map ( + ADDRA(13 downto 5) => ADDRA, + ADDRA(4 downto 0) => ADDRA_GND(4 downto 0), + ADDRB(13 downto 5) => ADDRB, + ADDRB(4 downto 0) => ADDRB_GND(4 downto 0), + CLKA => CLKA, + CLKB => CLKB, + DIA(31 downto 0) => DIA, + DIB(31 downto 0) => DIB, + DIPA(3 downto 0) => DIPA, + DIPB(3 downto 0) => DIPB, + ENA => ENA, + ENB => ENB, + SSRA => SSRA, + SSRB => SSRB, + WEA => WEA, + WEB => WEB, + DOA(31 downto 0) => DOA, + DOB(31 downto 0) => DOB, + DOPA(3 downto 0) => DOPA, + DOPB(3 downto 0) => DOPB + + ); +end RAMB16BWE_S36_S36_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +-- /___/ /\ Filename : RAMB16BWE_S36_S9.vhd +-- \ \ / \ Timestamp : Wed Jun 8 16:43:35 PST 2005 +-- \___\/\___\ +-- +-- Generated by : write_vhdl +-- +-- Revision: +-- 06/08/05 - Initial version. +-- End Revision + + +----- CELL RAMB16BWE_S36_S9 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity RAMB16BWE_S36_S9 is +generic ( + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + +port ( + DOA : out std_logic_vector(31 downto 0); + DOB : out std_logic_vector(7 downto 0); + DOPA : out std_logic_vector(3 downto 0); + DOPB : out std_logic_vector(0 downto 0); + + ADDRA : in std_logic_vector(8 downto 0); + ADDRB : in std_logic_vector(10 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector(31 downto 0); + DIB : in std_logic_vector(7 downto 0); + DIPA : in std_logic_vector(3 downto 0); + DIPB : in std_logic_vector(0 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector(3 downto 0); + WEB : in std_ulogic + ); +end RAMB16BWE_S36_S9; + +-- Architecture body -- + +architecture RAMB16BWE_S36_S9_V of RAMB16BWE_S36_S9 is + + signal DOB_open : std_logic_vector(23 downto 0); + signal DOPB_open : std_logic_vector(2 downto 0); + + signal ADDRA_GND : std_logic_vector(4 downto 0) := (others => '0'); + signal ADDRB_GND : std_logic_vector(2 downto 0) := (others => '0'); + + signal DIB_GND : std_logic_vector(23 downto 0) := (others => '0'); + signal DIPB_GND : std_logic_vector(2 downto 0) := (others => '0'); + + +begin + +-- RAMB16BWE Instantiation + +RAMB16BWE_inst : RAMB16BWE + generic map ( + DATA_WIDTH_A => 36, + DATA_WIDTH_B => 9, + + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INIT_A => INIT_A, + INIT_B => INIT_B, + + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + + SIM_COLLISION_CHECK => SIM_COLLISION_CHECK, + + SRVAL_A => SRVAL_A, + SRVAL_B => SRVAL_B, + + WRITE_MODE_A => WRITE_MODE_A, + WRITE_MODE_B => WRITE_MODE_B + ) + port map ( + ADDRA(13 downto 5) => ADDRA, + ADDRA(4 downto 0) => ADDRA_GND(4 downto 0), + ADDRB(13 downto 3) => ADDRB, + ADDRB(2 downto 0) => ADDRB_GND(2 downto 0), + CLKA => CLKA, + CLKB => CLKB, + DIA(31 downto 0) => DIA, + DIB(7 downto 0) => DIB, + DIB(31 downto 8) => DIB_GND, + DIPA(3 downto 0) => DIPA, + DIPB(0 downto 0) => DIPB, + DIPB(3 downto 1) => DIPB_GND, + ENA => ENA, + ENB => ENB, + SSRA => SSRA, + SSRB => SSRB, + WEA(0) => WEA(0), + WEA(1) => WEA(1), + WEA(2) => WEA(2), + WEA(3) => WEA(3), + WEB(0) => WEB, + WEB(1) => WEB, + WEB(2) => WEB, + WEB(3) => WEB, + DOA(31 downto 0) => DOA, + DOB(7 downto 0) => DOB, + DOB(31 downto 8) => DOB_open, + DOPA(3 downto 0) => DOPA, + DOPB(0 downto 0) => DOPB, + DOPB(3 downto 1) => DOPB_open + ); +end RAMB16BWE_S36_S9_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +-- /___/ /\ Filename : RAMB16BWE_S36.vhd +-- \ \ / \ Timestamp : Wed Jun 8 16:43:35 PST 2005 +-- \___\/\___\ +-- +-- Generated by : write_vhdl +-- +-- Revision: +-- 06/08/05 - Initial version. +-- End Revision + +----- CELL RAMB16BWE_S36 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity RAMB16BWE_S36 is +generic ( + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT : bit_vector := X"000000000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + SRVAL : bit_vector := X"000000000"; + + WRITE_MODE : string := "WRITE_FIRST" + ); + +port ( + DO : out std_logic_vector(31 downto 0); + DOP : out std_logic_vector(3 downto 0); + + ADDR : in std_logic_vector(8 downto 0); + CLK : in std_ulogic; + DI : in std_logic_vector(31 downto 0); + DIP : in std_logic_vector(3 downto 0); + EN : in std_ulogic; + SSR : in std_ulogic; + WE : in std_logic_vector(3 downto 0) + ); +end RAMB16BWE_S36; + +-- Architecture body -- + +architecture RAMB16BWE_S36_V of RAMB16BWE_S36 is + + signal ADDRA_GND : std_logic_vector(4 downto 0) := (others => '0'); + signal ADDRB_GND : std_logic_vector(13 downto 0) := (others => '0'); + + signal DOB_open : std_logic_vector(31 downto 0); + signal DOPB_open : std_logic_vector(3 downto 0); + + + signal DIB_GND : std_logic_vector(31 downto 0) := (others => '0'); + signal DIPB_GND : std_logic_vector(3 downto 0) := (others => '0'); + + signal CLKB_GND, ENB_GND, SSRB_GND : std_ulogic := '0'; + signal WEB_GND : std_logic_vector(3 downto 0) := (others => '0'); + + +begin + +-- RAMB16BWE Instantiation + +RAMB16BWE_inst : RAMB16BWE + generic map ( + DATA_WIDTH_A => 36, + DATA_WIDTH_B => 36, + + INIT_00 => INIT_00, + INIT_01 => INIT_01, + INIT_02 => INIT_02, + INIT_03 => INIT_03, + INIT_04 => INIT_04, + INIT_05 => INIT_05, + INIT_06 => INIT_06, + INIT_07 => INIT_07, + INIT_08 => INIT_08, + INIT_09 => INIT_09, + INIT_0A => INIT_0A, + INIT_0B => INIT_0B, + INIT_0C => INIT_0C, + INIT_0D => INIT_0D, + INIT_0E => INIT_0E, + INIT_0F => INIT_0F, + INIT_10 => INIT_10, + INIT_11 => INIT_11, + INIT_12 => INIT_12, + INIT_13 => INIT_13, + INIT_14 => INIT_14, + INIT_15 => INIT_15, + INIT_16 => INIT_16, + INIT_17 => INIT_17, + INIT_18 => INIT_18, + INIT_19 => INIT_19, + INIT_1A => INIT_1A, + INIT_1B => INIT_1B, + INIT_1C => INIT_1C, + INIT_1D => INIT_1D, + INIT_1E => INIT_1E, + INIT_1F => INIT_1F, + INIT_20 => INIT_20, + INIT_21 => INIT_21, + INIT_22 => INIT_22, + INIT_23 => INIT_23, + INIT_24 => INIT_24, + INIT_25 => INIT_25, + INIT_26 => INIT_26, + INIT_27 => INIT_27, + INIT_28 => INIT_28, + INIT_29 => INIT_29, + INIT_2A => INIT_2A, + INIT_2B => INIT_2B, + INIT_2C => INIT_2C, + INIT_2D => INIT_2D, + INIT_2E => INIT_2E, + INIT_2F => INIT_2F, + INIT_30 => INIT_30, + INIT_31 => INIT_31, + INIT_32 => INIT_32, + INIT_33 => INIT_33, + INIT_34 => INIT_34, + INIT_35 => INIT_35, + INIT_36 => INIT_36, + INIT_37 => INIT_37, + INIT_38 => INIT_38, + INIT_39 => INIT_39, + INIT_3A => INIT_3A, + INIT_3B => INIT_3B, + INIT_3C => INIT_3C, + INIT_3D => INIT_3D, + INIT_3E => INIT_3E, + INIT_3F => INIT_3F, + INIT_A => INIT, + + INITP_00 => INITP_00, + INITP_01 => INITP_01, + INITP_02 => INITP_02, + INITP_03 => INITP_03, + INITP_04 => INITP_04, + INITP_05 => INITP_05, + INITP_06 => INITP_06, + INITP_07 => INITP_07, + + SIM_COLLISION_CHECK => "NONE", + + SRVAL_A => SRVAL, + + WRITE_MODE_A => WRITE_MODE + ) + port map ( + ADDRA(13 downto 5) => ADDR, + ADDRA(4 downto 0) => ADDRA_GND(4 downto 0), + ADDRB(13 downto 0) => ADDRB_GND(13 downto 0), + CLKA => CLK, + CLKB => CLKB_GND, + DIA => DI, + DIB => DIB_GND, + DIPA => DIP, + DIPB => DIPB_GND, + ENA => EN, + ENB => ENB_GND, + SSRA => SSR, + SSRB => SSRB_GND, + WEA => WE, + WEB => WEB_GND, + DOA(31 downto 0) => DO, + DOB(31 downto 0) => DOB_OPEN, + DOPA => DOP, + DOPB => DOPB_OPEN + + ); +end RAMB16BWE_S36_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Timing Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +-- /___/ /\ Filename : RAMB16BWE.vhd +-- \ \ / \ Timestamp : Fri Mar 26 08:18:21 PST 2004 +-- \___\/\___\ +-- +-- Revision: +-- 03/23/04 - Initial version. + +----- CELL RAMB16BWE ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library STD; +use STD.TEXTIO.all; + + + +library unisim; +use unisim.vpkg.all; + +entity RAMB16BWE is + + generic ( + + DATA_WIDTH_A : integer := 0; + DATA_WIDTH_B : integer := 0; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector (31 downto 0); + DOB : out std_logic_vector (31 downto 0); + DOPA : out std_logic_vector (3 downto 0); + DOPB : out std_logic_vector (3 downto 0); + + ADDRA : in std_logic_vector (13 downto 0); + ADDRB : in std_logic_vector (13 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector (31 downto 0); + DIB : in std_logic_vector (31 downto 0); + DIPA : in std_logic_vector (3 downto 0); + DIPB : in std_logic_vector (3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + SSRA : in std_ulogic; + SSRB : in std_ulogic; + WEA : in std_logic_vector (3 downto 0); + WEB : in std_logic_vector (3 downto 0) + ); + +end RAMB16BWE; + +architecture RAMB16BWE_V of RAMB16BWE is + + +-- Constants + + constant MAX_ADDR: integer := 13; + + constant MAX_DI: integer := 31; + constant MAX_DIP: integer := 3; + constant MAX_WE: integer := 3; + + constant SYNC_PATH_DELAY : time := 100 ps; + + TYPE CollisionFlagType IS RECORD + active_port : integer; + read_write : boolean; + write_read : boolean; + write_write : boolean; + we : std_logic_vector(MAX_WE downto 0); + END RECORD; + + TYPE DataWidthType IS RECORD + diaw : integer; + dipaw : integer; + doaw : integer; + dopaw : integer; + dibw : integer; + dipbw : integer; + dobw : integer; + dopbw : integer; + END RECORD; + + TYPE ClsnXbufType IS RECORD + DO1_clsn : std_logic_vector(31 downto 0); + DOP1_clsn : std_logic_vector(3 downto 0); + MEM1_clsn : std_logic_vector(31 downto 0); + MEMP1_clsn : std_logic_vector(3 downto 0); + + DO2_clsn : std_logic_vector(31 downto 0); + DOP2_clsn : std_logic_vector(3 downto 0); + MEM2_clsn : std_logic_vector(31 downto 0); + MEMP2_clsn : std_logic_vector(3 downto 0); + END RECORD; + + TYPE memory_collision_type is (Read_A_Write_B, + Write_A_Read_B, + Write_A_Write_B, + Read_B_Write_A, + Write_B_Read_A, + Write_B_Write_A); + + constant SETUP_ALL : time := 1000 ps; + constant SETUP_READ_FIRST : time := 3000 ps; + +-- Procedures and Functions + +------------------------------------------------ +-- procedure ClkCollisionCheck +------------------------------------------------ +-- +-- Checks whether the time duration of rising +-- clka and clkb violates required setup time +-- between these clocks. +-- + procedure ClkCollisionCheck( + variable violation : out integer; + constant CheckEnabled : in boolean := false; + variable CLK1_time : in time := 0 ns; + variable CLK2_time : in time := 0 ns; + constant SETUP_ALL : in time := 0 ns; + constant SETUP_READ_FIRST : in time := 0 ns + ) is + + begin + + violation := 0; + if(CheckEnabled) then + if((CLK1_time > 0 ns ) and (CLK2_time > 0 ns )) then + if((CLK1_time - CLK2_time) = 0 ns ) then + violation := 3; + elsif ((CLK1_time - CLK2_time) < SETUP_ALL) then + violation := 11; + elsif ((CLK1_time - CLK2_time) < SETUP_READ_FIRST) then + violation := 12; + end if; + end if; + end if; + end ClkCollisionCheck; + +------------------------------------------------ +-- function AddrOverlapCheck +------------------------------------------------ +-- + + function AddrOverlapCheck( + d1w : in integer := 0; + d2w : in integer := 0; + addr1 : in std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + addr2 : in std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + zero_addr1 : in std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + zero_addr2 : in std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + we_segment : in integer := 0 + ) return boolean is + variable collision, port1_overlap, port2_overlap : boolean := false; + variable addr1_zero_int, addr2_zero_int, wea_index, INDEX1, INDEX2 : integer := -1; + variable tmp_addr1_zero, tmp_addr2_zero : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + variable zero_out : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + variable tmp_we : std_logic_vector(1 downto 0) := (others => '0'); + + + + + begin + INDEX1 := SLV_TO_INT(addr1(4 downto 0)); + INDEX2 := SLV_TO_INT(addr2(4 downto 0)); + + if(D1W >= D2W) then + zero_out := zero_addr1; + elsif(D1W < D2W) then + zero_out := zero_addr2; + end if; + + tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_out); + tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_out); + + addr1_zero_int := SLV_TO_INT(tmp_addr1_zero); + addr2_zero_int := SLV_TO_INT(tmp_addr2_zero); + +-- if((addr1_zero_int = addr2_zero_int) and ((INDEX1 + D1W) > we_segment * 8 ) and ((INDEX2 + D2W) > we_segment * 8 )) then + if(addr1_zero_int = addr2_zero_int) then + + case D1W is + --------- + when 1|2|4|8 => + --------- + tmp_we(1 downto 0) := addr1( 4 downto 3); + wea_index := SLV_TO_INT(tmp_we); + if(wea_index = we_segment) then + port1_overlap := true; + end if; + + --------- + when 16 => + --------- + + tmp_we(1) := addr1(4); + tmp_we(0) := '0'; + wea_index := SLV_TO_INT(tmp_we); + if(wea_index = we_segment) then + port1_overlap := true; + end if; + + tmp_we(1) := addr1(4); + tmp_we(0) := '1'; + wea_index := SLV_TO_INT(tmp_we); + if(wea_index = we_segment) then + port1_overlap := true; + end if; + + --------- + when 32 => + --------- + + port1_overlap := true; + + --------- + when others => null; + --------- + end case; + + + + case D2W is + --------- + when 1|2|4|8 => + --------- + tmp_we(1 downto 0) := addr2( 4 downto 3); + wea_index := SLV_TO_INT(tmp_we); + if(wea_index = we_segment) then + port2_overlap := true; + end if; + + --------- + when 16 => + --------- + + tmp_we(1) := addr2(4); + tmp_we(0) := '0'; + wea_index := SLV_TO_INT(tmp_we); + if(wea_index = we_segment) then + port2_overlap := true; + end if; + + tmp_we(1) := addr2(4); + tmp_we(0) := '1'; + wea_index := SLV_TO_INT(tmp_we); + if(wea_index = we_segment) then + port2_overlap := true; + end if; + + --------- + when 32 => + --------- + + port2_overlap := true; + + --------- + when others => null; + --------- + end case; + + end if; + + collision := (port1_overlap and port2_overlap); + return collision; + end; +------------------------------------------------ +-- procedure QkAddrOverlapChk +------------------------------------------------ +-- + + procedure QkAddrOverlapChk( + variable addr_overlap : out boolean; + variable data_widths : in DataWidthType; + variable addra : in std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + variable addrb : in std_logic_vector(MAX_ADDR downto 0) := (others => 'X') + ) is + variable addra_int, addrb_int, max_width : integer := -1; + variable tmp_addra_zero, tmp_addrb_zero : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + variable zero_data_out : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + variable zero_parity_out : std_logic_vector((MAX_ADDR-3) downto 0) := (others => 'X'); + + begin + addr_overlap := false; + zero_data_out := (others => '1'); + zero_parity_out := (others => '1'); + + max_width := data_widths.diaw; + + if(data_widths.doaw > max_width) then + max_width := data_widths.doaw; + end if; + + if(data_widths.dibw > max_width) then + max_width := data_widths.dibw; + end if; + + if(data_widths.dobw > max_width) then + max_width := data_widths.dobw; + end if; + + + case max_width is + + ------- + when 32 => + ------- + zero_data_out(4 downto 0) := (others => '0'); + zero_parity_out(1 downto 0) := (others => '0'); + + ------- + when 16 => + ------- + zero_data_out(3 downto 0) := (others => '0'); + zero_parity_out(0 downto 0) := (others => '0'); + + ------- + when 8 => + ------- + zero_data_out(2 downto 0) := (others => '0'); + + ------- + when 4 => + ------- + zero_data_out(1 downto 0) := (others => '0'); + + ------- + when 2 => + ------- + zero_data_out(0 downto 0) := (others => '0'); + + ------- + when others => + ------- + null; + + + end case; + + tmp_addra_zero := (addra(MAX_ADDR downto 0) and zero_data_out); + tmp_addrb_zero := (addrb(MAX_ADDR downto 0) and zero_data_out); + + addra_int := SLV_TO_INT(tmp_addra_zero); + addrb_int := SLV_TO_INT(tmp_addrb_zero); + + if(addra_int = addrb_int) then + addr_overlap := true; + end if; + + end QkAddrOverlapChk; + +------------------------------------------------ +-- procedure SameDataChk +------------------------------------------------ +-- +-- Checks whether the data written is the same +-- as in the memory, or in the case of both ports +-- writing whether the inputs are the same. +-- If true, then there is no collision +-- + procedure SameDataChk( + variable same_data : out boolean; + variable same_datap : out boolean; + constant MEM : in std_logic_vector(18431 downto 0); + constant di1 : in std_logic_vector(31 downto 0); + constant di2 : in std_logic_vector(31 downto 0); + constant dip1 : in std_logic_vector(3 downto 0); + constant dip2 : in std_logic_vector(3 downto 0); + variable addr1 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable addr2 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable addrp1 : in std_logic_vector(10 downto 0) := (others => 'X'); + variable addrp2 : in std_logic_vector(10 downto 0) := (others => 'X'); + variable wr_mode_1 : in std_logic_vector(1 downto 0) := "00"; + variable wr_mode_2 : in std_logic_vector(1 downto 0) := "00"; + constant we_segment : in integer := -1; + variable we1 : in std_ulogic := 'X'; + variable we2 : in std_ulogic := 'X'; + variable D1W : in integer := -1; + variable D1PW : in integer := -1; + variable D2W : in integer := -1; + variable D2PW : in integer := -1 + ) is + variable REM1 : integer := -1; + variable REM2 : integer := -1; + variable XOUT_BITS : integer := -1; + variable XOUT_BITS_1 : integer := -1; + variable XOUT_PBITS_1 : integer := 0; + variable INDEX, INDEXP, DATA_INDEX : integer := -1; + variable ADDRESS, ADDRESS_P, ADDRESS32_1, ADDRESS32P_1, ADDRESS32_2, ADDRESS32P_2 : integer := -1; + variable SMALL_ADDRESS32, SMALL_ADDRESS32P : integer := -1; + variable SMALL_DW : integer := -1; + + + variable TableRow : std_logic_vector(1 downto 0) := (others => '0'); + + variable cmp_d1_buf : std_logic_vector(7 downto 0) := (others => '0'); + variable cmp_d1p_buf : std_logic_vector(0 downto 0) := (others => '0'); + variable cmp_d2_buf : std_logic_vector(7 downto 0) := (others => '0'); + variable cmp_d2p_buf : std_logic_vector(0 downto 0) := (others => '0'); + variable cmp_mem_buf : std_logic_vector(7 downto 0) := (others => '0'); + variable cmp_memp_buf : std_logic_vector(0 downto 0) := (others => '0'); + + variable cmp_d1_buf32 : std_logic_vector(31 downto 0) := (others => '0'); + variable cmp_d1p_buf4 : std_logic_vector(3 downto 0) := (others => '0'); + variable cmp_d2_buf32 : std_logic_vector(31 downto 0) := (others => '0'); + variable cmp_d2p_buf4 : std_logic_vector(3 downto 0) := (others => '0'); + + variable tmp_cmp_d1_buf : std_logic_vector(7 downto 0) := (others => '0'); + variable tmp_cmp_d1p_buf : std_logic_vector(0 downto 0) := (others => '0'); + variable tmp_cmp_d2_buf : std_logic_vector(7 downto 0) := (others => '0'); + variable tmp_cmp_d2p_buf : std_logic_vector(0 downto 0) := (others => '0'); + + variable memp_fp : std_logic_vector(3 downto 0) := (others => '0'); + + begin + +-- ################################################################## +----------------------------------------------------------------------- +------------ Port 1 Active Clock ------------------------------------- +----------------------------------------------------------------------- + + same_data := false; + same_datap := false; + + if((D1W >= D2W) and (D2W < 8)) then + INDEX := SLV_TO_INT(addr2(4 downto 0)); + elsif((D2W >= D1W) and (D1W < 8)) then + INDEX := SLV_TO_INT(addr1(4 downto 0)); + else + INDEX := we_segment * 8; + end if; + + + --- Data Bits --- + + REM1 := D1W REM 8; + REM2 := D2W REM 8; + + -- find the minimum data bits to overlap + if((REM1 = 0) and (REM2 = 0)) then + XOUT_BITS := 8 ; + elsif(REM1 = 0) then + XOUT_BITS := REM2; + elsif(REM2 = 0) then + XOUT_BITS := REM1; + elsif(REM1 > REM2) then + XOUT_BITS := REM2 ; + elsif (REM1 <= REM2) then + XOUT_BITS := REM1 ; + end if; + + XOUT_BITS_1 := XOUT_BITS - 1 ; + + + if(D1W <= D2W) then + SMALL_DW := D1W; + ADDRESS := SLV_TO_INT(addr1); + SMALL_ADDRESS32:= SLV_TO_INT(addr1(4 downto 0)); + elsif(D1W > D2W) then + SMALL_DW := D2W; + ADDRESS := SLV_TO_INT(addr2); + SMALL_ADDRESS32:= SLV_TO_INT(addr2(4 downto 0)); + end if; + + if(D1PW <= D2PW) then + ADDRESS_P := SLV_TO_INT(addrp1); + SMALL_ADDRESS32P:= SLV_TO_INT(addrp1(1 downto 0)); + elsif(D1PW > D2PW) then + ADDRESS_P := SLV_TO_INT(addrp2); + SMALL_ADDRESS32P:= SLV_TO_INT(addrp2(1 downto 0)); + end if; + + INDEXP := we_segment; + + TableRow := (we1 & we2); + + cmp_d1_buf := (others => '0'); + cmp_d1p_buf := (others => '0'); + cmp_d2_buf := (others => '0'); + cmp_d2p_buf := (others => '0'); + cmp_mem_buf := (others => '0'); + cmp_memp_buf := (others => '0'); + +--================================================================================================== + ADDRESS32_1 := SLV_TO_INT(addr1(4 downto 0)); + ADDRESS32P_1 := SLV_TO_INT(addrp1(1 downto 0)); + cmp_d1_buf32(((D1W - 1) + ADDRESS32_1) downto ADDRESS32_1) := di1((D1W - 1) downto 0); + cmp_d1p_buf4(((D1PW - 1) + ADDRESS32P_1) downto ADDRESS32P_1) := dip1((D1PW - 1) downto 0); + + ADDRESS32_2 := SLV_TO_INT(addr2(4 downto 0)); + ADDRESS32P_2 := SLV_TO_INT(addrp2(1 downto 0)); + cmp_d2_buf32(((D2W - 1) + ADDRESS32_2) downto ADDRESS32_2) := di2((D2W - 1) downto 0); + cmp_d2p_buf4(((D2PW - 1) + ADDRESS32P_2) downto ADDRESS32P_2) := dip2((D2PW - 1 ) downto 0); + + case SMALL_DW is + when 1|2|4 => + cmp_mem_buf(XOUT_BITS_1 downto 0) := MEM((XOUT_BITS_1 + ADDRESS ) downto (ADDRESS)); + + tmp_cmp_d1_buf(XOUT_BITS_1 downto 0) := cmp_d1_buf32((XOUT_BITS_1 + SMALL_ADDRESS32 ) downto SMALL_ADDRESS32); + tmp_cmp_d2_buf(XOUT_BITS_1 downto 0) := cmp_d2_buf32((XOUT_BITS_1 + SMALL_ADDRESS32 ) downto SMALL_ADDRESS32); + + when 8 => + cmp_mem_buf(XOUT_BITS_1 downto 0) := MEM((XOUT_BITS_1 + ADDRESS ) downto (ADDRESS)); + cmp_memp_buf(XOUT_PBITS_1 downto 0) := MEM((XOUT_PBITS_1 + 16384 + ADDRESS_P) downto (ADDRESS_P + 16384)); + + tmp_cmp_d1_buf(XOUT_BITS_1 downto 0) := cmp_d1_buf32((XOUT_BITS_1 + SMALL_ADDRESS32 ) downto SMALL_ADDRESS32); + tmp_cmp_d1p_buf(XOUT_PBITS_1 downto 0) := cmp_d1p_buf4((XOUT_PBITS_1 + SMALL_ADDRESS32P) downto SMALL_ADDRESS32P); + + tmp_cmp_d2_buf(XOUT_BITS_1 downto 0) := cmp_d2_buf32((XOUT_BITS_1 + SMALL_ADDRESS32 ) downto SMALL_ADDRESS32); + tmp_cmp_d2p_buf(XOUT_PBITS_1 downto 0) := cmp_d2p_buf4((XOUT_PBITS_1 + SMALL_ADDRESS32P) downto SMALL_ADDRESS32P); + + when 16 => + if((we_segment = 0) or (we_segment = 2)) then + DATA_INDEX := 0; + elsif((we_segment = 1) or (we_segment = 3))then + DATA_INDEX := 1; + end if; + + cmp_mem_buf(XOUT_BITS_1 downto 0) := MEM((XOUT_BITS_1 + ADDRESS + DATA_INDEX*8 ) downto (DATA_INDEX*8 + ADDRESS)); + cmp_memp_buf(XOUT_PBITS_1 downto 0) := MEM((XOUT_PBITS_1 + 16384 + DATA_INDEX + ADDRESS_P) downto (DATA_INDEX + ADDRESS_P + 16384)); + tmp_cmp_d1_buf(XOUT_BITS_1 downto 0) := cmp_d1_buf32((XOUT_BITS_1 + we_segment*8 ) downto we_segment*8); + tmp_cmp_d1p_buf(XOUT_PBITS_1 downto 0) := cmp_d1p_buf4((XOUT_PBITS_1 + we_segment*1) downto we_segment*1); + + tmp_cmp_d2_buf(XOUT_BITS_1 downto 0) := cmp_d2_buf32((XOUT_BITS_1 + we_segment*8 ) downto we_segment*8); + tmp_cmp_d2p_buf(XOUT_PBITS_1 downto 0) := cmp_d2p_buf4((XOUT_PBITS_1 + we_segment*1) downto we_segment*1); + + when 32 => + cmp_mem_buf(XOUT_BITS_1 downto 0) := MEM((XOUT_BITS_1 + INDEX + ADDRESS ) downto (INDEX + ADDRESS)); + cmp_memp_buf(XOUT_PBITS_1 downto 0) := MEM((XOUT_PBITS_1 + 16384 + INDEXP + ADDRESS_P) downto (INDEXP + ADDRESS_P + 16384)); + + tmp_cmp_d1_buf(XOUT_BITS_1 downto 0) := cmp_d1_buf32((XOUT_BITS_1 + we_segment*8 ) downto we_segment*8); + tmp_cmp_d1p_buf(XOUT_PBITS_1 downto 0) := cmp_d1p_buf4((XOUT_PBITS_1 + we_segment*1) downto we_segment*1); + + tmp_cmp_d2_buf(XOUT_BITS_1 downto 0) := cmp_d2_buf32((XOUT_BITS_1 + we_segment*8 ) downto we_segment*8); + tmp_cmp_d2p_buf(XOUT_PBITS_1 downto 0) := cmp_d2p_buf4((XOUT_PBITS_1 + we_segment*1) downto we_segment*1); + + when others => null; + + end case; + + case TableRow is +---=============================================================================== +--- wea&web = 11 +---=============================================================================== + ---- + when "11" => + ---- + + memp_fp := MEM(( 3 + 16384 + ADDRESS_P) downto (16384 + ADDRESS_P)); + + + if((tmp_cmp_d1_buf = tmp_cmp_d2_buf) and (tmp_cmp_d2_buf = cmp_mem_buf)) then + same_data := true; + end if; + + -- Parity + if((D1PW /= 0) and (D2PW /= 0)) then + if((tmp_cmp_d1p_buf = tmp_cmp_d2p_buf) and (tmp_cmp_d2p_buf = cmp_memp_buf)) then + same_datap := true; + end if; + end if; +---=============================================================================== +--- wea&web = 01 +---=============================================================================== + ---- + when "01" => + ---- + + if(tmp_cmp_d2_buf = cmp_mem_buf) then + same_data := true; + end if; + + -- Parity + if((D1PW /= 0) and (D2PW /= 0)) then + if(tmp_cmp_d2p_buf = cmp_memp_buf) then + same_datap := true; + end if; + end if; +---=============================================================================== +--- wea&web = 10 +---=============================================================================== + ---- + when "10" => + ---- + if(tmp_cmp_d1_buf = cmp_mem_buf) then + same_data := true; + end if; + + -- Parity + if((D1PW /= 0) and (D2PW /= 0)) then + if(tmp_cmp_d1p_buf = cmp_memp_buf) then + same_datap := true; + end if; + end if; +---=============================================================================== +--- others +---=============================================================================== + + --------- + when others => + --------- + null; + end case; + + end SameDataChk; + +------------------------------------------------ +-- procedure CollisionTableRest +------------------------------------------------ +-- +-- Checks whether the time duration of rising +-- clka and clkb violates required setup time +-- between these clocks. +-- + procedure CollisionTableRest( + variable clsn_bufs : out ClsnXbufType; + variable same_data_flg : out boolean; + variable same_datap_flg : out boolean; + constant MEM : in std_logic_vector(18431 downto 0); + constant di1 : in std_logic_vector(31 downto 0); + constant di2 : in std_logic_vector(31 downto 0); + constant dip1 : in std_logic_vector(3 downto 0); + constant dip2 : in std_logic_vector(3 downto 0); + variable addr1 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable addr2 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable addrp1 : in std_logic_vector(10 downto 0) := (others => 'X'); + variable addrp2 : in std_logic_vector(10 downto 0) := (others => 'X'); + variable wr_mode_1 : in std_logic_vector(1 downto 0) := "00"; + variable wr_mode_2 : in std_logic_vector(1 downto 0) := "00"; + constant we_segment : in integer := -1; + constant violation : in integer := -1; + variable we1 : in std_ulogic := 'X'; + variable we2 : in std_ulogic := 'X'; + variable D1W : in integer := -1; + variable D1PW : in integer := -1; + variable D2W : in integer := -1; + variable D2PW : in integer := -1 + ) is + variable REM1 : integer := -1; + variable REM2 : integer := -1; + variable XOUT_BITS : integer := -1; + variable XOUT_BITS_1 : integer := -1; + variable INDEX, INDEX_P : integer := -1; + + variable TableRow : std_logic_vector(5 downto 0) := (others => '0'); + variable we1we2 : std_logic_vector(1 downto 0) := (others => '0'); + + variable same_data : boolean := false; + variable same_datap : boolean := false; + variable SAME_DATA_CHECK_DISABLED : boolean := true; + + begin + +-- ################################################################## +----------------------------------------------------------------------- +------------ Port 1 Active Clock ------------------------------------- +----------------------------------------------------------------------- + + + if((D1W >= D2W) and (D2W < 8)) then + INDEX := SLV_TO_INT(addr2(4 downto 0)); + elsif((D2W >= D1W) and (D1W < 8)) then + INDEX := SLV_TO_INT(addr1(4 downto 0)); + else + INDEX := we_segment * 8; + end if; + + + --- Data Bits --- + + REM1 := D1W REM 8; + REM2 := D2W REM 8; + + -- find the minimum data bits to overlap + if((REM1 = 0) and (REM2 = 0)) then + XOUT_BITS := 8 ; + elsif(REM1 = 0) then + XOUT_BITS := REM2; + elsif(REM2 = 0) then + XOUT_BITS := REM1; + elsif(REM1 > REM2) then + XOUT_BITS := REM2 ; + elsif (REM1 <= REM2) then + XOUT_BITS := REM1 ; + end if; + + XOUT_BITS_1 := XOUT_BITS - 1 ; + + + + --- Parity Bits --- + + -- find the minimum parity bits to overlap + + if(D1PW >= D2PW) then + INDEX_P := SLV_TO_INT(addrp2(1 downto 0)); + else + INDEX_P := SLV_TO_INT(addrp1(1 downto 0)); + end if; +--=============================================================================== +-- Same Data Check for both Data and Parity +-- If Data/Parity_Data are the same in Ports A and B, and the contents of the +-- Memory/Parity_memory are the same as the Data, then here is no collision +--=============================================================================== + + + SameDataChk( + same_data => same_data, + same_datap => same_datap, + mem => mem, + di1 => di1, + di2 => di2, + dip1 => dip1, + dip2 => dip2, + addr1 => addr1, + addr2 => addr2, + addrp1 => addrp1, + addrp2 => addrp2, + wr_mode_1 => wr_mode_1, + wr_mode_2 => wr_mode_2, + we_segment => we_segment, + we1 => we1, + we2 => we2, + D1W => D1W, + D1PW => D1PW, + D2W => D2W, + D2PW => D2PW + ); + +---=============================================================================== +---=============================================================================== +-- DEBUG +if(SAME_DATA_CHECK_DISABLED) then + same_data := false; + same_datap := false; +end if; + + same_data_flg := same_data; + same_datap_flg := same_datap; + + TableRow := (wr_mode_1 & wr_mode_2 & we1 & we2); + case TableRow is +---=============================================================================== +--- wea&web = 11 +---=============================================================================== + ---- + when "000011" | "010011" => + ---- + if((violation = 3) or (violation = 11)) then + if(not same_data) then + -- port 1 + clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + -- port 2 + clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + end if; + if(not same_datap) then + -- parity port 1 + if((D1PW /= 0) and (D2PW /= 0)) then +-- clsn_bufs.DOP1_clsn((INDEX_P + (we_segment * 1)) downto (INDEX_P + (we_segment * 1))) := (others => 'X'); + clsn_bufs.DOP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + -- parity port 2 + if((D1PW /= 0) and (D2PW /= 0)) then +-- clsn_bufs.DOP2_clsn((INDEX_P + (we_segment * 1)) downto (INDEX_P + (we_segment * 1))) := (others => 'X'); + clsn_bufs.DOP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + + end if; + + ---- + when "001011" | "011011" => + ---- + if((violation = 3) or (violation = 11)) then + if(not same_data) then + -- port 1 + clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + -- port 2 + clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + end if; + if(not same_datap) then + -- parity port 1 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + end if; + ---- + when "000111" | "010111" => + ---- + if((violation = 3) or (violation = 11) or (violation = 12)) then + if(not same_data) then + -- port 1 + clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + -- port 2 + clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + end if; + if(not same_datap) then + -- parity port 1 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + -- parity port 2 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + end if; + + ---- + when "100011" => + ---- + if((violation = 3) or (violation = 11)) then + if(not same_data) then + -- port 1 + clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + -- port 2 + clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + end if; + + if(not same_datap) then + -- parity port 1 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + -- parity port 2 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + + end if; + + ---- + when "100111" => + ---- + if((violation = 3) or (violation = 11) or (violation = 12) ) then + if(not same_data) then + -- port 1 + clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + -- port 2 + clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + end if; + + if(not same_datap) then + -- parity port 1 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + -- parity port 2 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + + end if; + ---- + when "101011" => + ---- + if((violation = 3) or (violation = 11)) then + if(not same_data) then + -- port 1 + clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + -- port 2 + clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + end if; + if(not same_datap) then + if((D1PW /= 0) and (D2PW /= 0)) then + -- parity port 1 + clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + -- parity port 2 + clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + end if; + +---=============================================================================== +--- wea&web = 01 +---=============================================================================== + ---- + when "000001" | "010001" | "100001" => + ---- + if((violation = 3) or (violation = 11)) then + if(not same_data) then + -- port 1 + clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + end if; + if(not same_datap) then + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + end if; + ---- + when "000101" | "010101" | "100101" => + ---- + if((violation = 11) or (violation = 12)) then + if(not same_data) then + -- port 1 + clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + end if; + if(not same_datap) then + -- parity port 1 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + + end if; + ---- + when "001001" | "011001" | "101001" => + ---- + if((violation = 3) or (violation = 11)) then + if(not same_data) then + -- port 1 + clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + end if; + if(not same_datap) then + -- parity port 1 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + end if; + +---=============================================================================== +--- wea&web = 10 +---=============================================================================== + + ---- + when "000010" | "000110" | "001010" => + ---- + if((violation = 3) or (violation = 11)) then + if(not same_data) then + -- port 1 + clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + end if; + if(not same_datap) then + -- parity port 1 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + end if; + ---- + when "100010" | "100110" | "101010" => + ---- + if((violation = 3) or (violation = 11)) then + if(not same_data) then + -- port 1 + clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + end if; + if(not same_datap) then + -- parity port 1 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + + end if; + +---=============================================================================== +--- others +---=============================================================================== + + --------- + when others => + --------- + null; + end case; + + end CollisionTableRest; + +------------------------------------------------ +-- procedure PreProcessWe1We2 +------------------------------------------------ +-- +-- Checks whether the time duration of rising +-- clka and clkb violates required setup time +-- between these clocks. +-- + procedure PreProcessWe1We2( + variable clsn_bufs : out ClsnXbufType; + variable clsn_Type : out CollisionFlagType; + constant memory : in std_logic_vector(18431 downto 0); + constant di1 : in std_logic_vector(31 downto 0) := (others => 'X'); + constant di2 : in std_logic_vector(31 downto 0) := (others => 'X'); + constant dip1 : in std_logic_vector(3 downto 0) := (others => 'X'); + constant dip2 : in std_logic_vector(3 downto 0) := (others => 'X'); + variable addr1 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable addr2 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable we1 : in std_logic_vector(3 downto 0) := (others => 'X'); + variable we2 : in std_logic_vector(3 downto 0) := (others => 'X'); + variable zero_read_1 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable zero_readp_1 : in std_logic_vector(10 downto 0) := (others => 'X'); + variable zero_write_1 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable zero_writep_1 : in std_logic_vector(10 downto 0) := (others => 'X'); + variable zero_read_2 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable zero_readp_2 : in std_logic_vector(10 downto 0) := (others => 'X'); + variable zero_write_2 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable zero_writep_2 : in std_logic_vector(10 downto 0) := (others => 'X'); + variable wr_mode_1 : in std_logic_vector(1 downto 0) := "00"; + variable wr_mode_2 : in std_logic_vector(1 downto 0) := "00"; + constant violation : in integer := -1; + variable DI1W : in integer := -1; + variable DIP1W : in integer := -1; + variable DI2W : in integer := -1; + variable DIP2W : in integer := -1; + variable DO1W : in integer := -1; + variable DOP1W : in integer := -1; + variable DO2W : in integer := -1; + variable DOP2W : in integer := -1 + ) is + + variable we1we2 : std_logic_vector(1 downto 0) := "XX"; + variable zero_addr1 : std_logic_vector(13 downto 0) := (others => 'X'); + variable zero_addr2 : std_logic_vector(13 downto 0) := (others => 'X'); + variable zero_parity_addr1 : std_logic_vector(10 downto 0) := (others => 'X'); + variable zero_parity_addr2 : std_logic_vector(10 downto 0) := (others => 'X'); + variable tmp_addr1_zero : std_logic_vector(13 downto 0) := (others => 'X'); + variable tmp_addr2_zero : std_logic_vector(13 downto 0) := (others => 'X'); + variable tmp_parity_addr1_zero : std_logic_vector(10 downto 0) := (others => 'X'); + variable tmp_parity_addr2_zero : std_logic_vector(10 downto 0) := (others => 'X'); + + + variable tmp_we1 : std_ulogic := 'X'; + variable tmp_we2 : std_ulogic := 'X'; + variable j : integer := 0; + + variable same_data_flg : boolean := false; + variable same_datap_flg : boolean := false; + + begin + + clsn_type.read_write := false; + clsn_type.write_read := false; + clsn_type.write_write := false; + + for i in 0 to 3 loop + we1we2 := we1(i)&we2(i); + clsn_type.we(i) := '0'; + case we1we2 is + --------- + when "00" => + --------- + null; + + --------- + when "01" => + --------- + same_data_flg := false; + same_datap_flg := false; + + zero_addr1 := zero_read_1; + zero_addr2 := zero_write_2; + + zero_parity_addr1 := zero_readp_1; + zero_parity_addr2 := zero_writep_2; + + tmp_we1 := '0'; + tmp_we2 := '1'; + + if(AddrOverlapCheck(DO1W, DI2W, addr1, addr2, zero_addr1, zero_addr2,i)) then + + tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1); + tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2); + + tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1; + tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2; + +-- FP fixed false message for DSP group 12/06/04 + + clsn_type.read_write := true; + clsn_type.we(i) := '1'; + + if((wr_mode_2 = "01")) then + clsn_type.read_write := false; + clsn_type.we(i) := '0'; + end if; + + + CollisionTableRest( + same_data_flg => same_data_flg, + same_datap_flg => same_datap_flg, + clsn_bufs => clsn_bufs, + mem => memory, + di1 => di1, + di2 => di2, + dip1 => dip1, + dip2 => dip2, + addr1 => tmp_addr1_zero, + addr2 => tmp_addr2_zero, + addrp1 => tmp_parity_addr1_zero, + addrp2 => tmp_parity_addr2_zero, + wr_mode_1 => wr_mode_1, + wr_mode_2 => wr_mode_2, + violation => violation, + we_segment => i, + we1 => tmp_we1, + we2 => tmp_we2, + D1W => DO1W, + D1PW => DOP1W, + D2W => DI2W, + D2PW => DIP2W + ); + end if; + --------- + when "10" => + --------- + same_data_flg := false; + same_datap_flg := false; + + zero_addr1 := zero_write_1; + zero_addr2 := zero_read_2; + + zero_parity_addr1 := zero_writep_1; + zero_parity_addr2 := zero_readp_2; + + tmp_we1 := '1'; + tmp_we2 := '0'; + + + if(AddrOverlapCheck(DI1W, DO2W, addr1, addr2, zero_addr1, zero_addr2,i)) then + + tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1); + tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2); + + tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1; + tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2; + + clsn_type.write_read := true; + clsn_type.we(i) := '1'; + +-- FP fixed false message for DSP group 12/06/04 +-- if((violation = 12) or (wr_mode_1 = "01")) then + if((wr_mode_1 = "01")) then + clsn_type.write_read := false; + clsn_type.we(i) := '0'; + end if; + + CollisionTableRest( + same_data_flg => same_data_flg, + same_datap_flg => same_datap_flg, + clsn_bufs => clsn_bufs, + mem => memory, + di1 => di1, + di2 => di2, + dip1 => dip1, + dip2 => dip2, + addr1 => tmp_addr1_zero, + addr2 => tmp_addr2_zero, + addrp1 => tmp_parity_addr1_zero, + addrp2 => tmp_parity_addr2_zero, + wr_mode_1 => wr_mode_1, + wr_mode_2 => wr_mode_2, + violation => violation, + we_segment => i, + we1 => tmp_we1, + we2 => tmp_we2, + D1W => DI1W, + D1PW => DIP1W, + D2W => DO2W, + D2PW => DOP2W + ); + end if; + --------- + when "11" => + --------- + same_data_flg := false; + same_datap_flg := false; + + zero_addr1 := zero_write_1; + zero_addr2 := zero_write_2; + + zero_parity_addr1 := zero_writep_1; + zero_parity_addr2 := zero_writep_2; + + tmp_we1 := '1'; + tmp_we2 := '1'; + + if(AddrOverlapCheck(DI1W, DI2W, addr1, addr2, zero_addr1, zero_addr2,i)) then + + tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1); + tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2); + + tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1; + tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2; + + if(violation = 12) then + if(wr_mode_2 = "01") then + clsn_type.write_write := true; + clsn_type.we(i) := '1'; + end if; + else + clsn_type.write_write := true; + clsn_type.we(i) := '1'; + end if; + + CollisionTableRest( + same_data_flg => same_data_flg, + same_datap_flg => same_datap_flg, + clsn_bufs => clsn_bufs, + mem => memory, + di1 => di1, + di2 => di2, + dip1 => dip1, + dip2 => dip2, + addr1 => tmp_addr1_zero, + addr2 => tmp_addr2_zero, + addrp1 => tmp_parity_addr1_zero, + addrp2 => tmp_parity_addr2_zero, + wr_mode_1 => wr_mode_1, + wr_mode_2 => wr_mode_2, + violation => violation, + we_segment => i, + we1 => tmp_we1, + we2 => tmp_we2, + D1W => DI1W, + D1PW => DIP1W, + D2W => DI2W, + D2PW => DIP2W + ); + end if; + + if((DI1W /= DO1W) or (DI2W /= DO2W)) then +--FP disabled the cross check call +-- tmp_we1 := '1'; +-- tmp_we2 := '0'; + tmp_we1 := '0'; + tmp_we2 := '0'; + + zero_addr1 := zero_write_1; + zero_addr2 := zero_read_2; + + zero_parity_addr1 := zero_writep_1; + zero_parity_addr2 := zero_readp_2; + + if(AddrOverlapCheck(DI1W, DO2W, addr1, addr2, zero_addr1, zero_addr2,i)) then + + tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1); + tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2); + + tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1; + tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2; + + CollisionTableRest( + same_data_flg => same_data_flg, + same_datap_flg => same_datap_flg, + clsn_bufs => clsn_bufs, + mem => memory, + di1 => di1, + di2 => di2, + dip1 => dip1, + dip2 => dip2, + addr1 => tmp_addr1_zero, + addr2 => tmp_addr2_zero, + addrp1 => tmp_parity_addr1_zero, + addrp2 => tmp_parity_addr2_zero, + wr_mode_1 => wr_mode_1, + wr_mode_2 => wr_mode_2, + violation => violation, + we_segment => i, + we1 => tmp_we1, + we2 => tmp_we2, + D1W => DI1W, + D1PW => DIP1W, + D2W => DO2W, + D2PW => DOP2W + ); + end if; + +--FP disabled the cross check call +-- tmp_we1 := '0'; +-- tmp_we2 := '1'; + tmp_we1 := '0'; + tmp_we2 := '0'; + + zero_addr1 := zero_read_1; + zero_addr2 := zero_write_2; + + zero_parity_addr1 := zero_readp_1; + zero_parity_addr2 := zero_writep_2; + + if(AddrOverlapCheck(DO1W, DI2W, addr1, addr2, zero_addr1, zero_addr2,i)) then + + tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1); + tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2); + + tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1; + tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2; + + CollisionTableRest( + same_data_flg => same_data_flg, + same_datap_flg => same_datap_flg, + clsn_bufs => clsn_bufs, + mem => memory, + di1 => di1, + di2 => di2, + dip1 => dip1, + dip2 => dip2, + addr1 => tmp_addr1_zero, + addr2 => tmp_addr2_zero, + addrp1 => tmp_parity_addr1_zero, + addrp2 => tmp_parity_addr2_zero, + wr_mode_1 => wr_mode_1, + wr_mode_2 => wr_mode_2, + violation => violation, + we_segment => i, + we1 => tmp_we1, + we2 => tmp_we2, + D1W => DO1W, + D1PW => DOP1W, + D2W => DI2W, + D2PW => DIP2W + ); + + end if; + end if; + + when others => + null; + + end case; + + end loop; + + end PreProcessWe1We2; +------------------------------------------------ +-- procedure Memory_Collision_Msg_ramb16 +------------------------------------------------ +-- This is almost the same procedure as the procedure for V2 ram collision +-- except that is is local to the model (since this is the only one that +-- calls this procedure + Procedure Memory_Collision_Msg_ramb16 ( + CONSTANT HeaderMsg : IN STRING := " Memory Collision Error on "; + CONSTANT EntityName : IN STRING := ""; + CONSTANT InstanceName : IN STRING := ""; + constant collision_type : in memory_collision_type; + constant address_1 : in std_logic_vector; + constant address_2 : in std_logic_vector; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := Error + + + ) IS + variable current_time : time := NOW; + variable string_length_1 : integer; + variable string_length_2 : integer; + + VARIABLE Message : LINE; + BEGIN + if ((address_1'length mod 4) = 0) then + string_length_1 := address_1'length/4; + elsif ((address_1'length mod 4) > 0) then + string_length_1 := address_1'length/4 + 1; + end if; + if ((address_2'length mod 4) = 0) then + string_length_2 := address_2'length/4; + elsif ((address_2'length mod 4) > 0) then + string_length_2 := address_2'length/4 + 1; + end if; +-- if ((collision_type = Read_A_Write_B) or (collision_type = Read_B_Write_A)) then + if ((collision_type = Read_A_Write_B) or (collision_type = Write_A_Read_B) or + (collision_type = Read_B_Write_A) or (collision_type = Write_B_Read_A)) then + Write ( Message, HeaderMsg); + Write ( Message, EntityName); + Write ( Message, STRING'(": ")); + Write ( Message, InstanceName); + Write ( Message, STRING'(" at simulation time ")); + Write ( Message, current_time); + Write ( Message, STRING'(".")); + Write ( Message, LF ); + Write ( Message, STRING'(" A read was performed on address ")); + Write ( Message, SLV_TO_HEX(address_1, string_length_1)); + Write ( Message, STRING'(" (hex) ")); +-- if (collision_type = Read_A_Write_B) then + if ((collision_type = Read_A_Write_B) or (collision_type = Write_B_Read_A))then + Write ( Message, STRING'("of port A while a write was requested to the same address on Port B ")); + Write ( Message, STRING'(" The write will be successful however the read value is unknown until the next CLKA cycle ")); +-- elsif(collision_type = Read_B_Write_A) then + elsif((collision_type = Read_B_Write_A) or (collision_type = Write_A_Read_B)) then + Write ( Message, STRING'("of port B while a write was requested to the same address on Port A ")); + Write ( Message, STRING'(" The write will be successful however the read value is unknown until the next CLKB cycle ")); + end if; + elsif ((collision_type = Write_A_Write_B) or (collision_type = Write_B_Write_A)) then + Write ( Message, HeaderMsg); + Write ( Message, EntityName); + Write ( Message, STRING'(": ")); + Write ( Message, InstanceName); + Write ( Message, STRING'(" at simulation time ")); + Write ( Message, current_time); + Write ( Message, STRING'(".")); + Write ( Message, LF ); + Write ( Message, STRING'(" A write was requested to the same address simultaneously at both Port A and Port B of the RAM.")); + Write ( Message, STRING'(" The contents written to the RAM at address location ")); + Write ( Message, SLV_TO_HEX(address_1, string_length_1)); + Write ( Message, STRING'(" (hex) ")); + Write ( Message, STRING'("of Port A and address location ")); + Write ( Message, SLV_TO_HEX(address_2, string_length_2)); + Write ( Message, STRING'(" (hex) ")); + Write ( Message, STRING'("of Port B are unknown. ")); + end if; + ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity; + + DEALLOCATE (Message); + END Memory_Collision_Msg_ramb16; + +------------------ END Procedures/Functions ------------------------------ + + signal ADDRA_ipd : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(MAX_DI downto 0) := (others => 'X'); + signal DIPA_ipd : std_logic_vector(MAX_DIP downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal SSRA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_logic_vector(MAX_WE downto 0) := (others => 'X'); + + signal ADDRB_ipd : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(MAX_DI downto 0) := (others => 'X'); + signal DIPB_ipd : std_logic_vector(MAX_DIP downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal SSRB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_logic_vector(MAX_WE downto 0) := (others => 'X'); + + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := 'X'; + + signal GSR_dly : std_ulogic := 'X'; + + signal ADDRA_dly : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + signal CLKA_dly : std_ulogic := 'X'; + signal DIA_dly : std_logic_vector(MAX_DI downto 0) := (others => 'X'); + signal DIPA_dly : std_logic_vector(MAX_DIP downto 0) := (others => 'X'); + signal ENA_dly : std_ulogic := 'X'; + signal GSR_CLKA_dly : std_ulogic := 'X'; + signal SSRA_dly : std_ulogic := 'X'; + signal WEA_dly : std_logic_vector(MAX_WE downto 0) := (others => 'X'); + + signal ADDRB_dly : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + signal CLKB_dly : std_ulogic := 'X'; + signal DIB_dly : std_logic_vector(MAX_DI downto 0) := (others => 'X'); + signal DIPB_dly : std_logic_vector(MAX_DIP downto 0) := (others => 'X'); + signal ENB_dly : std_ulogic := 'X'; + signal GSR_CLKB_dly : std_ulogic := 'X'; + signal SSRB_dly : std_ulogic := 'X'; + signal WEB_dly : std_logic_vector(MAX_WE downto 0) := (others => 'X'); + + signal DOA_viol : std_logic_vector(MAX_DI downto 0); + signal DOPA_viol : std_logic_vector(3 downto 0); + signal DOB_viol : std_logic_vector(MAX_DI downto 0); + signal DOPB_viol : std_logic_vector(3 downto 0); + + signal DIAW : integer; + signal DIAW_1 : integer; + signal DIBW : integer; + signal DIBW_1 : integer; + signal DIPAW : integer; + signal DIPAW_1 : integer; + signal DIPBW : integer; + signal DIPBW_1 : integer; + + signal DOAW : integer; + signal DOAW_1 : integer; + signal DOBW : integer; + signal DOBW_1 : integer; + signal DOPAW : integer; + signal DOPAW_1 : integer; + signal DOPBW : integer; + signal DOPBW_1 : integer; + + signal INI_A_sig : std_logic_vector (35 downto 0) := (others => 'X'); + signal INI_B_sig : std_logic_vector (35 downto 0) := (others => 'X'); + + signal SRVA_A_sig : std_logic_vector (35 downto 0) := (others => 'X'); + signal SRVA_B_sig : std_logic_vector (35 downto 0) := (others => 'X'); + +begin + --------------------- + -- INPUT PATH DELAYs + -------------------- + + ADDRA_dly <= ADDRA after 0 ps; + ADDRB_dly <= ADDRB after 0 ps; + CLKA_dly <= CLKA after 0 ps; + CLKB_dly <= CLKB after 0 ps; + DIA_dly <= DIA after 0 ps; + DIB_dly <= DIB after 0 ps; + DIPA_dly <= DIPA after 0 ps; + DIPB_dly <= DIPB after 0 ps; + ENA_dly <= ENA after 0 ps; + ENB_dly <= ENB after 0 ps; + GSR_dly <= GSR after 0 ps; + SSRA_dly <= SSRA after 0 ps; + SSRB_dly <= SSRB after 0 ps; + WEA_dly <= WEA after 0 ps; + WEB_dly <= WEB after 0 ps; + GSR_CLKA_dly <= GSR after 0 ps; + GSR_CLKB_dly <= GSR after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + + prcs_initialize:process + variable INI_A : std_logic_vector (35 downto 0) := (others => 'X'); + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (35 downto 0) := (others => 'X'); + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + + variable SRVA_A : std_logic_vector (35 downto 0) := (others => 'X'); + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (35 downto 0) := (others => 'X'); + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + + variable DIAW_var : integer; + variable DIAW_1_var : integer; + variable DIBW_var : integer; + variable DIBW_1_var : integer; + variable DIPAW_var : integer; + variable DIPAW_1_var : integer; + variable DIPBW_var : integer; + variable DIPBW_1_var : integer; + + variable DOAW_var : integer; + variable DOAW_1_var : integer; + variable DOBW_var : integer; + variable DOBW_1_var : integer; + variable DOPAW_var : integer; + variable DOPAW_1_var : integer; + variable DOPBW_var : integer; + variable DOPBW_1_var : integer; + + begin + DIPAW_var := 0; + DIPAW_1_var := -1; + DIPBW_var := 0; + DIPBW_1_var := -1; + + DOPAW_var := 0; + DOPAW_1_var := -1; + DOPBW_var := 0; + DOPBW_1_var := -1; + + +-------------------------------------------------------------------- +-- Additional Checks Added Later +-------------------------------------------------------------------- + if((DATA_WIDTH_A = 0) and (DATA_WIDTH_B = 0 )) then + assert false + report "Attribute Syntax Error: Both DATA_WIDTH_A and DATA_WIDTH_B can not be 0." + severity Failure; + end if; + + case DATA_WIDTH_A is + + when 0 => + DOAW_var := 1; + DOAW_1_var := DOAW_var -1; + DIAW_var := 1; + DIAW_1_var := DIAW_var -1; + + when 1 => + DOAW_var := 1; + DOAW_1_var := DOAW_var -1; + DIAW_var := 1; + DIAW_1_var := DIAW_var -1; + + when 2 => + DOAW_var := 2; + DOAW_1_var := DOAW_var -1; + DIAW_var := 2; + DIAW_1_var := DIAW_var -1; + + when 4 => + DOAW_var := 4; + DOAW_1_var := DOAW_var -1; + DIAW_var := 4; + DIAW_1_var := DIAW_var -1; + + when 9 => + DOAW_var := 8; + DOAW_1_var := DOAW_var -1; + DOPAW_var := 1; + DOPAW_1_var := DOPAW_var -1; + DIAW_var := 8; + DIAW_1_var := DIAW_var -1; + DIPAW_var := 1; + DIPAW_1_var := DIPAW_var -1; + + when 18 => + DOAW_var := 16; + DOAW_1_var := DOAW_var -1; + DOPAW_var := 2; + DOPAW_1_var := DOPAW_var -1; + DIAW_var := 16; + DIAW_1_var := DIAW_var -1; + DIPAW_var := 2; + DIPAW_1_var := DIPAW_var -1; + + when 36 => + DOAW_var := 32; + DOAW_1_var := DOAW_var -1; + DOPAW_var := 4; + DOPAW_1_var := DOPAW_var -1; + DIAW_var := 32; + DIAW_1_var := DIAW_var -1; + DIPAW_var := 4; + DIPAW_1_var := DIPAW_var -1; + + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " DATA_WIDTH_A ", + EntityName => "/RAMB16BWE", + GenericValue => DATA_WIDTH_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", + TailMsg => "", + MsgSeverity => failure + ); + end case; + + + case DATA_WIDTH_B is + + when 0 => + DOBW_var := 1; + DOBW_1_var := DOBW_var -1; + DIBW_var := 1; + DIBW_1_var := DIBW_var -1; + + when 1 => + DOBW_var := 1; + DOBW_1_var := DOBW_var -1; + DIBW_var := 1; + DIBW_1_var := DIBW_var -1; + + when 2 => + DOBW_var := 2; + DOBW_1_var := DOBW_var -1; + DIBW_var := 2; + DIBW_1_var := DIBW_var -1; + + when 4 => + DOBW_var := 4; + DOBW_1_var := DOBW_var -1; + DIBW_var := 4; + DIBW_1_var := DIBW_var -1; + + when 9 => + DOBW_var := 8; + DOBW_1_var := DOBW_var -1; + DOPBW_var := 1; + DOPBW_1_var := DOPBW_var -1; + DIBW_var := 8; + DIBW_1_var := DIBW_var -1; + DIPBW_var := 1; + DIPBW_1_var := DIPBW_var -1; + + when 18 => + DOBW_var := 16; + DOBW_1_var := DOBW_var -1; + DOPBW_var := 2; + DOPBW_1_var := DOPBW_var -1; + DIBW_var := 16; + DIBW_1_var := DIBW_var -1; + DIPBW_var := 2; + DIPBW_1_var := DIPBW_var -1; + + when 36 => + DOBW_var := 32; + DOBW_1_var := DOBW_var -1; + DOPBW_var := 4; + DOPBW_1_var := DOPBW_var -1; + DIBW_var := 32; + DIBW_1_var := DIBW_var -1; + DIPBW_var := 4; + DIPBW_1_var := DIPBW_var -1; + + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " DATA_WIDTH_B ", + EntityName => "/RAMB16BWE", + GenericValue => DATA_WIDTH_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", + TailMsg => "", + MsgSeverity => failure + ); + null; + + end case; + + + if (INIT_A'length > 36) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A ); + INI_A(35 downto 0) := INI_A_UNBOUND(35 downto 0); + elsif (INIT_A'length < 36) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A ); + elsif (INIT_A'length = 36) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A ); + end if; + + if (INIT_B'length > 36) then + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B ); + INI_B(35 downto 0) := INI_B_UNBOUND(35 downto 0); + elsif (INIT_B'length < 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B ); + elsif (INIT_B'length = 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B ); + end if; + + if (SRVAL_A'length > 36) then + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A ); + SRVA_A(35 downto 0) := SRVA_A_UNBOUND(35 downto 0); + elsif (SRVAL_A'length < 36) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A ); + elsif (SRVAL_A'length = 36) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A ); + end if; + + if (SRVAL_B'length > 36) then + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B ); + SRVA_B(35 downto 0) := SRVA_B_UNBOUND(35 downto 0); + elsif (SRVAL_B'length < 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B ); + elsif (SRVAL_B'length = 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B ); + end if; + + DIAW <= DIAW_var; + DIAW_1 <= DIAW_1_var; + DIBW <= DIBW_var; + DIBW_1 <= DIBW_1_var; + DIPAW <= DIPAW_var; + DIPAW_1 <= DIPAW_1_var; + DIPBW <= DIPBW_var; + DIPBW_1 <= DIPBW_1_var; + + DOAW <= DOAW_var; + DOAW_1 <= DOAW_1_var; + DOBW <= DOBW_var; + DOBW_1 <= DOBW_1_var; + DOPAW <= DOPAW_var; + DOPAW_1 <= DOPAW_1_var; + DOPBW <= DOPBW_var; + DOPBW_1 <= DOPBW_1_var; + + SRVA_A_sig <= SRVA_A; + SRVA_B_sig <= SRVA_B; + INI_A_sig <= INI_A; + INI_B_sig <= INI_B; + + wait; + end process prcs_initialize; +--------------------------------------------------------------------------------------- + VITALBehavior : process + + variable MEM : std_logic_vector(18431 downto 0) := To_StdLogicVector(INITP_07) & + To_StdLogicVector(INITP_06) & + To_StdLogicVector(INITP_05) & + To_StdLogicVector(INITP_04) & + To_StdLogicVector(INITP_03) & + To_StdLogicVector(INITP_02) & + To_StdLogicVector(INITP_01) & + To_StdLogicVector(INITP_00) & + + To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00) ; + + variable INI_A : std_logic_vector (35 downto 0) := (others => 'X'); + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (35 downto 0) := (others => 'X'); + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + + variable DIAW : integer; + variable DIAW_1 : integer; + variable DIBW : integer; + variable DIBW_1 : integer; + variable DIPAW : integer; + variable DIPAW_1 : integer; + variable DIPBW : integer; + variable DIPBW_1 : integer; + + variable DOAW : integer; + variable DOAW_1 : integer; + variable DOBW : integer; + variable DOBW_1 : integer; + variable DOPAW : integer; + variable DOPAW_1 : integer; + variable DOPBW : integer; + variable DOPBW_1 : integer; + + variable ADDRA_dly_sampled : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + variable ADDRB_dly_sampled : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + + variable ADDRESS_READ_A, ADDRESS_WRITE_A, ADDRESS_READ_B, ADDRESS_WRITE_B : integer; + variable ADDRESS_PARITY_READ_A, ADDRESS_PARITY_WRITE_A, ADDRESS_PARITY_READ_B, ADDRESS_PARITY_WRITE_B : integer; + + variable DOA_INDEX, DOPA_INDEX : integer := -1; + variable DOB_INDEX, DOPB_INDEX : integer := -1; + + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOA_zd : std_logic_vector(MAX_DI downto 0) := INI_A(MAX_DI downto 0); + variable DOA_zd_buf : std_logic_vector(MAX_DI downto 0) := INI_A(MAX_DI downto 0); + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOB_zd : std_logic_vector(MAX_DI downto 0) := INI_B(MAX_DI downto 0); + variable DOB_zd_buf : std_logic_vector(MAX_DI downto 0) := INI_B(MAX_DI downto 0); + variable DOPA_OV_LSB : integer; + variable DOPA_OV_MSB : integer; + variable DOPA_zd : std_logic_vector(3 downto 0) := INI_A(35 downto 32); + variable DOPA_zd_buf : std_logic_vector(3 downto 0) := INI_A(35 downto 32); + variable DOPB_OV_LSB : integer; + variable DOPB_OV_MSB : integer; + variable DOPB_zd : std_logic_vector(3 downto 0) := INI_B(35 downto 32); + variable DOPB_zd_buf : std_logic_vector(3 downto 0) := INI_B(35 downto 32); + variable ENA_dly_sampled : std_ulogic := 'X'; + variable ENB_dly_sampled : std_ulogic := 'X'; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVA_A : std_logic_vector (35 downto 0) := (others => 'X'); + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (35 downto 0) := (others => 'X'); + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable SSRA_dly_sampled : std_ulogic := 'X'; + variable SSRB_dly_sampled : std_ulogic := 'X'; + variable VALID_ADDRA : boolean := true; + variable VALID_ADDRB : boolean := true; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable WEA_dly_sampled : std_logic_vector(MAX_WE downto 0) := (others => 'X'); + variable WEB_dly_sampled : std_logic_vector(MAX_WE downto 0) := (others => 'X'); + variable wr_mode_a : std_logic_vector(1 downto 0) := "00"; + variable wr_mode_b : std_logic_vector(1 downto 0) := "00"; + +--FP + variable wea_index : integer := -1; + variable web_index : integer := -1; + + variable tmp_we : std_logic_vector(1 downto 0) := (others => '1'); + variable xout_we_seg1 : std_logic_vector(1 downto 0) := (others => '0'); + variable xout_we_seg2 : std_logic_vector(1 downto 0) := (others => '0'); + + variable tmp_zero_write_a : std_logic_vector(MAX_ADDR downto 0) := (others => '1'); + variable tmp_zero_read_a : std_logic_vector(MAX_ADDR downto 0) := (others => '1'); + variable tmp_zero_parity_write_a : std_logic_vector((MAX_ADDR-3) downto 0) := (others => '0'); + variable tmp_zero_parity_read_a : std_logic_vector((MAX_ADDR-3) downto 0) := (others => '0'); + + variable tmp_zero_write_b : std_logic_vector(MAX_ADDR downto 0) := (others => '1'); + variable tmp_zero_read_b : std_logic_vector(MAX_ADDR downto 0) := (others => '1'); + variable tmp_zero_parity_write_b : std_logic_vector((MAX_ADDR-3) downto 0) := (others => '0'); + variable tmp_zero_parity_read_b : std_logic_vector((MAX_ADDR-3) downto 0) := (others => '0'); + + variable zero_write_a : std_logic_vector(MAX_ADDR downto 0) := (others => '1'); + variable zero_read_a : std_logic_vector(MAX_ADDR downto 0) := (others => '1'); + variable zero_parity_write_a : std_logic_vector((MAX_ADDR-3) downto 0) := (others => '1'); + variable zero_parity_read_a : std_logic_vector((MAX_ADDR-3) downto 0) := (others => '1'); + + variable zero_write_b : std_logic_vector(MAX_ADDR downto 0) := (others => '1'); + variable zero_read_b : std_logic_vector(MAX_ADDR downto 0) := (others => '1'); + variable zero_parity_write_b : std_logic_vector((MAX_ADDR-3) downto 0) := (others => '1'); + variable zero_parity_read_b : std_logic_vector((MAX_ADDR-3) downto 0) := (others => '1'); + + + variable addra_in_14 : std_ulogic := '0'; + variable addrb_in_14 : std_ulogic := '0'; + + variable SimCollisionCheck_var : integer := 3; + variable collision_clka_clkb : integer := 0; + variable addr_overlap : boolean := false; + + variable CLKA_time : time := 0 ps; + variable CLKB_time : time := 0 ps; + + variable DOA_clsn : std_logic_vector(31 downto 0) := (others => '0'); + variable DOPA_clsn : std_logic_vector(3 downto 0) := (others => '0'); + variable DOA_clsn_sav : std_logic_vector(31 downto 0) := (others => '0'); + variable DOPA_clsn_sav : std_logic_vector(3 downto 0) := (others => '0'); + variable DOA_clsn_zero : std_logic_vector(31 downto 0) := (others => '0'); + variable DOPA_clsn_zero : std_logic_vector(3 downto 0) := (others => '0'); + + variable DOB_clsn : std_logic_vector(31 downto 0) := (others => '0'); + variable DOPB_clsn : std_logic_vector(3 downto 0) := (others => '0'); + variable DOB_clsn_sav : std_logic_vector(31 downto 0) := (others => '0'); + variable DOPB_clsn_sav : std_logic_vector(3 downto 0) := (others => '0'); + variable DOB_clsn_zero : std_logic_vector(31 downto 0) := (others => '0'); + variable DOPB_clsn_zero : std_logic_vector(3 downto 0) := (others => '0'); + + variable DOA_clsn_slice : std_logic_vector(31 downto 0) := (others => '0'); + variable DOPA_clsn_slice : std_logic_vector(3 downto 0) := (others => '0'); + variable DOB_clsn_slice : std_logic_vector(31 downto 0) := (others => '0'); + variable DOPB_clsn_slice : std_logic_vector(3 downto 0) := (others => '0'); + + variable tmp_membuf : std_logic_vector(31 downto 0) := (others => '0'); + + variable DOA_clsn_read_index, DOPA_clsn_read_index : integer := -1; + variable DOB_clsn_read_index, DOPB_clsn_read_index : integer := -1; + + variable DOA_clsn_write_index, DOPA_clsn_write_index : integer := -1; + variable DOB_clsn_write_index, DOPB_clsn_write_index : integer := -1; + + variable clsn_type : CollisionFlagType; + variable data_widths : DataWidthType; + variable clsn_xbufs : ClsnXbufType; + + variable collision_msg : memory_collision_type; + + variable Write_A_Write_B : memory_collision_type := Write_A_Write_B; + variable Read_A_Write_B : memory_collision_type := Read_A_Write_B; + variable Write_A_Read_B : memory_collision_type := Write_A_Read_B; + variable Write_B_Write_A : memory_collision_type := Write_B_Write_A; + variable Read_B_Write_A : memory_collision_type := Read_B_Write_A; + variable Write_B_Read_A : memory_collision_type := Write_B_Read_A; + + variable msg_addr1 : std_logic_vector(MAX_ADDR downto 0) := (others => '0'); + variable msg_addr2 : std_logic_vector(MAX_ADDR downto 0) := (others => '0'); + + begin + + + if (FIRST_TIME) then + + DIPAW := 0; + DIPAW_1 := -1; + DIPBW := 0; + DIPBW_1 := -1; + + DOPAW := 0; + DOPAW_1 := -1; + DOPBW := 0; + DOPBW_1 := -1; + + case DATA_WIDTH_A is + + when 0 => + DOAW := 1; + DOAW_1 := DOAW -1; + DIAW := 1; + DIAW_1 := DIAW -1; + + when 1 => + zero_read_a(13 downto 0) := (others => '1'); + DOAW := 1; + DOAW_1 := DOAW -1; + zero_write_a(13 downto 0) := (others => '1'); + DIAW := 1; + DIAW_1 := DIAW -1; + + when 2 => + zero_read_a(0 downto 0) := (others => '0'); + DOAW := 2; + DOAW_1 := DOAW -1; + zero_write_a(0 downto 0) := (others => '0'); + DIAW := 2; + DIAW_1 := DIAW -1; + + when 4 => + zero_read_a(1 downto 0) := (others => '0'); + DOAW := 4; + DOAW_1 := DOAW -1; + zero_write_a(1 downto 0) := (others => '0'); + DIAW := 4; + DIAW_1 := DIAW -1; + + when 9 => + zero_read_a(2 downto 0) := (others => '0'); + DOAW := 8; + DOAW_1 := DOAW -1; + DOPAW := 1; + DOPAW_1 := DOPAW -1; + zero_write_a(2 downto 0) := (others => '0'); + DIAW := 8; + DIAW_1 := DIAW -1; + DIPAW := 1; + DIPAW_1 := DIPAW -1; + + when 18 => + zero_read_a(3 downto 0) := (others => '0'); + zero_parity_read_a(0 downto 0) := (others => '0'); + DOAW := 16; + DOAW_1 := DOAW -1; + DOPAW := 2; + DOPAW_1 := DOPAW -1; + zero_write_a(3 downto 0) := (others => '0'); + zero_parity_write_a(0 downto 0) := (others => '0'); + DIAW := 16; + DIAW_1 := DIAW -1; + DIPAW := 2; + DIPAW_1 := DIPAW -1; + + when 36 => + zero_read_a(4 downto 0) := (others => '0'); + zero_parity_read_a(1 downto 0) := (others => '0'); + DOAW := 32; + DOAW_1 := DOAW -1; + DOPAW := 4; + DOPAW_1 := DOPAW -1; + zero_write_a(4 downto 0) := (others => '0'); + zero_parity_write_a(1 downto 0) := (others => '0'); + DIAW := 32; + DIAW_1 := DIAW -1; + DIPAW := 4; + DIPAW_1 := DIPAW -1; + + when others => + null; + + end case; + + case DATA_WIDTH_B is + + when 0 => + DOBW := 1; + DOBW_1 := DOBW -1; + DIBW := 1; + DIBW_1 := DIBW -1; + + when 1 => + zero_read_b(13 downto 0) := (others => '1'); + DOBW := 1; + DOBW_1 := DOBW -1; + zero_write_b(13 downto 0) := (others => '1'); + DIBW := 1; + DIBW_1 := DIBW -1; + + when 2 => + zero_read_b(0 downto 0) := (others => '0'); + DOBW := 2; + DOBW_1 := DOBW -1; + zero_write_b(0 downto 0) := (others => '0'); + DIBW := 2; + DIBW_1 := DIBW -1; + + when 4 => + zero_read_b(1 downto 0) := (others => '0'); + DOBW := 4; + DOBW_1 := DOBW -1; + zero_write_b(1 downto 0) := (others => '0'); + DIBW := 4; + DIBW_1 := DIBW -1; + + when 9 => + zero_read_b(2 downto 0) := (others => '0'); + DOBW := 8; + DOBW_1 := DOBW -1; + DOPBW := 1; + DOPBW_1 := DOPBW -1; + zero_write_b(2 downto 0) := (others => '0'); + DIBW := 8; + DIBW_1 := DIBW -1; + DIPBW := 1; + DIPBW_1 := DIPBW -1; + + when 18 => + zero_read_b(3 downto 0) := (others => '0'); + zero_parity_read_b(0 downto 0) := (others => '0'); + DOBW := 16; + DOBW_1 := DOBW -1; + DOPBW := 2; + DOPBW_1 := DOPBW -1; + zero_write_b(3 downto 0) := (others => '0'); + zero_parity_write_b(0 downto 0) := (others => '0'); + DIBW := 16; + DIBW_1 := DIBW -1; + DIPBW := 2; + DIPBW_1 := DIPBW -1; + + when 36 => + zero_read_b(4 downto 0) := (others => '0'); + zero_parity_read_b(1 downto 0) := (others => '0'); + DOBW := 32; + DOBW_1 := DOBW -1; + DOPBW := 4; + DOPBW_1 := DOPBW -1; + zero_write_b(4 downto 0) := (others => '0'); + zero_parity_write_b(1 downto 0) := (others => '0'); + DIBW := 32; + DIBW_1 := DIBW -1; + DIPBW := 4; + DIPBW_1 := DIPBW -1; + + when others => + null; + + end case; + + if (INIT_A'length > 36) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A ); + INI_A(35 downto 0) := INI_A_UNBOUND(35 downto 0); + elsif (INIT_A'length < 36) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A ); + elsif (INIT_A'length = 36) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A ); + end if; + + if (INIT_B'length > 36) then + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B ); + INI_B(35 downto 0) := INI_B_UNBOUND(35 downto 0); + elsif (INIT_B'length < 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B ); + elsif (INIT_B'length = 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B ); + end if; + + if (SRVAL_A'length > 36) then + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A ); + SRVA_A(35 downto 0) := SRVA_A_UNBOUND(35 downto 0); + elsif (SRVAL_A'length < 36) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A ); + elsif (SRVAL_A'length = 36) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A ); + end if; + + if (SRVAL_B'length > 36) then + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B ); + SRVA_B(35 downto 0) := SRVA_B_UNBOUND(35 downto 0); + elsif (SRVAL_B'length < 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B ); + elsif (SRVAL_B'length = 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B ); + end if; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := "00"; + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := "01"; + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := "10"; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16BWE", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := "00"; + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := "01"; + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := "10"; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16BWE", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if((SIM_COLLISION_CHECK = "ALL") or (SIM_COLLISION_CHECK = "all")) then + SimCollisionCheck_var := 3; + elsif((SIM_COLLISION_CHECK = "NONE") or (SIM_COLLISION_CHECK = "none")) then + SimCollisionCheck_var := 0; + elsif((SIM_COLLISION_CHECK = "WARNING_ONLY") or (SIM_COLLISION_CHECK = "warning_only")) then + SimCollisionCheck_var := 1; + elsif((SIM_COLLISION_CHECK = "GENERATE_X_ONLY") or (SIM_COLLISION_CHECK = "generate_x_only")) then + SimCollisionCheck_var := 2; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " SIM_COLLISION_CHECK ", + EntityName => "/RAMB16BWE", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY ", + TailMsg => "", + MsgSeverity => error + ); + end if; + + + wait until (GSR_CLKA_dly = '1' or GSR_CLKB_dly = '1' or ((CLKA_dly = '0' or CLKA_dly = '1') or (CLKB_dly = '0' or CLKB_dly = '1'))); +---################################################################################ + DOA_zd(DOAW_1 downto 0) := INI_A(DOAW_1 downto 0); + DOB_zd(DOBW_1 downto 0) := INI_B(DOBW_1 downto 0); + + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := INI_A((DOPAW_1 + DOAW) downto DOAW); + end if; + + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := INI_B((DOPBW_1 + DOBW) downto DOBW); + end if; + +----- Port A +-- DOA <= DOA_zd; +-- if(DOPAW_1 /= -1) then +-- DOPA <= DOPA_zd; +-- end if; + +----- Port B +-- DOB <= DOB_zd; +-- if(DOPBW_1 /= -1) then +-- DOPB <= DOPB_zd; +-- end if; + + data_widths.diaw := DIAW; + data_widths.dipaw := DIPAW; + data_widths.doaw := DOAW; + data_widths.dopaw := DOPAW; + + data_widths.dibw := DIBW; + data_widths.dipbw := DIPBW; + data_widths.dobw := DOBW; + data_widths.dopbw := DOPBW; + + FIRST_TIME := false; + end if; +---------------- END FIRST_TIME + +-- addra_in_14 := ADDRA_dly(14); + + if (CLKA_dly'event) then + ENA_dly_sampled := ENA_dly; + SSRA_dly_sampled := SSRA_dly; + WEA_dly_sampled := WEA_dly; + ADDRA_dly_sampled := ADDRA_dly; + end if; + +------------------------------------------------------------- + +-- addrb_in_14 := ADDRB_dly(14); + + if (CLKB_dly'event) then + ENB_dly_sampled := ENB_dly; + SSRB_dly_sampled := SSRB_dly; + WEB_dly_sampled := WEB_dly; + ADDRB_dly_sampled := ADDRB_dly; + end if; + + + +-------------------------------- A ---------------------------------------- + tmp_zero_write_a := (addra_dly_sampled(13 downto 0) and zero_write_a); + ADDRESS_WRITE_A := SLV_TO_INT(tmp_zero_write_a); + + tmp_zero_read_a := (addra_dly_sampled(13 downto 0) and zero_read_a); + ADDRESS_READ_A := SLV_TO_INT(tmp_zero_read_a); + + tmp_zero_parity_write_a(10 downto 0) := addra_dly_sampled( 13 downto 3) and zero_parity_write_a; + ADDRESS_PARITY_WRITE_A := SLV_TO_INT(tmp_zero_parity_write_a); + + tmp_zero_parity_read_a(10 downto 0) := addra_dly_sampled( 13 downto 3) and zero_parity_read_a; + ADDRESS_PARITY_READ_A := SLV_TO_INT(tmp_zero_parity_read_a); +-------------------------------- B ---------------------------------------- + tmp_zero_write_b := (addrb_dly_sampled(13 downto 0) and zero_write_b); + ADDRESS_WRITE_B := SLV_TO_INT(tmp_zero_write_b); + + tmp_zero_read_b := (addrb_dly_sampled(13 downto 0) and zero_read_b); + ADDRESS_READ_B := SLV_TO_INT(tmp_zero_read_b); + + tmp_zero_parity_write_b(10 downto 0) := addrb_dly_sampled( 13 downto 3) and zero_parity_write_b; + ADDRESS_PARITY_WRITE_B := SLV_TO_INT(tmp_zero_parity_write_b); + + tmp_zero_parity_read_b(10 downto 0) := addrb_dly_sampled( 13 downto 3) and zero_parity_read_b; + ADDRESS_PARITY_READ_B := SLV_TO_INT(tmp_zero_parity_read_b); + + +-- VALID_ADDRA := ADDR_IS_VALID(addra_dly_sampled); +-- if (VALID_ADDRA) then +-- end if; + +-- VALID_ADDRB := ADDR_IS_VALID(addrb_dly_sampled); +-- if (VALID_ADDRB) then +-- end if; + +-- DOA_INDEX / DOPA_INDEX + + if(DIAW <= DOAW) then + case DIAW is + when 1 => + case DOAW is + when 1 => DOA_INDEX := 0; + when 2 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(0 downto 0)); + when 4 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(1 downto 0)); + when 8 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(2 downto 0)); + when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(3 downto 0)); + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 0)); + when others => null; + end case; + + when 2 => + case DOAW is + when 2 => DOA_INDEX := 0; + when 4 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(1 downto 1)); + when 8 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(2 downto 1)); + when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(3 downto 1)); + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 1)); + when others => null; + end case; + + when 4 => + case DOAW is + when 4 => DOA_INDEX := 0; + when 8 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(2 downto 2)); + when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(3 downto 2)); + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 2)); + when others => null; + end case; + + when 8 => + case DOAW is + when 8 => DOA_INDEX := 0; + DOPA_INDEX := 0; + when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(3 downto 3)); + DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_write_a(0 downto 0)); + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 3)); + DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_write_a(1 downto 0)); + when others => null; + end case; + + when 16 => + case DOAW is + when 16 => DOA_INDEX := 0; + DOPA_INDEX := 0; + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 4)); + DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_write_a(1 downto 1)); + when others => null; + end case; + + when 32 => + case DOAW is + when 32 => DOA_INDEX := 0; + DOPA_INDEX := 0; + when others => null; + end case; + + when others => null; + end case; + + elsif(DIAW > DOAW) then + case DOAW is + when 1 => + case DIAW is + when 2 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(0 downto 0)); + when 4 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(1 downto 0)); + when 8 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(2 downto 0)); + when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(3 downto 0)); + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 0)); + when others => null; + end case; + when 2 => + case DIAW is + when 4 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(1 downto 1)); + when 8 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(2 downto 1)); + when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(3 downto 1)); + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 1)); + when others => null; + end case; + + when 4 => + case DIAW is + when 8 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(2 downto 2)); + when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(3 downto 2)); + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 2)); + when others => null; + end case; + when 8 => + case DIAW is + when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(3 downto 3)); + DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_read_a(0 downto 0)); + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 3)); + DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0)); + when others => null; + end case; + + when 16 => + case DIAW is + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 4)); + DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 1)); + when others => null; + end case; + + when others => null; + end case; + end if; + +-- DOB_INDEX / DOPB_INDEX + + if(DIBW <= DOBW) then + case DIBW is + when 1 => + case DOBW is + when 1 => DOB_INDEX := 0; + when 2 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(0 downto 0)); + when 4 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(1 downto 0)); + when 8 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(2 downto 0)); + when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(3 downto 0)); + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 0)); + when others => null; + end case; + + when 2 => + case DOBW is + when 2 => DOB_INDEX := 0; + when 4 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(1 downto 1)); + when 8 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(2 downto 1)); + when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(3 downto 1)); + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 1)); + when others => null; + end case; + + when 4 => + case DOBW is + when 4 => DOB_INDEX := 0; + when 8 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(2 downto 2)); + when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(3 downto 2)); + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 2)); + when others => null; + end case; + + when 8 => + case DOBW is + when 8 => DOB_INDEX := 0; + DOPB_INDEX := 0; + when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(3 downto 3)); + DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_write_b(0 downto 0)); + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 3)); + DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_write_b(1 downto 0)); + when others => null; + end case; + + when 16 => + case DOBW is + when 16 => DOB_INDEX := 0; + DOPB_INDEX := 0; + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 4)); + DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_write_b(1 downto 1)); + when others => null; + end case; + + when 32 => + case DOBW is + when 32 => DOB_INDEX := 0; + DOPB_INDEX := 0; + when others => null; + end case; + + when others => null; + end case; + + elsif(DIBW > DOBW) then + case DOBW is + when 1 => + case DIBW is + when 2 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(0 downto 0)); + when 4 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(1 downto 0)); + when 8 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(2 downto 0)); + when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(3 downto 0)); + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 0)); + when others => null; + end case; + when 2 => + case DIBW is + when 4 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(1 downto 1)); + when 8 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(2 downto 1)); + when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(3 downto 1)); + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 1)); + when others => null; + end case; + + when 4 => + case DIBW is + when 8 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(2 downto 2)); + when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(3 downto 2)); + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 2)); + when others => null; + end case; + when 8 => + case DIBW is + when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(3 downto 3)); + DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_read_b(0 downto 0)); + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 3)); + DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0)); + when others => null; + end case; + + when 16 => + case DIBW is + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 4)); + DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 1)); + when others => null; + end case; + + when others => null; + end case; + end if; + + + +----- ###################################################################################################### + + if(rising_edge(CLKA_dly)) then + CLKA_time := now; + end if; + + if(rising_edge(CLKB_dly)) then + CLKB_time := now; + end if; + + +----- ###################################################################################################### +------------------------------------------------------------------------ +------------ Port A ---------------------------------------------------- +------------------------------------------------------------------------ + if(GSR_CLKA_dly = '1') then + DOA_zd(DOAW_1 downto 0) := INI_A(DOAW_1 downto 0); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := INI_A((DOPAW_1 + DOAW) downto DOAW); + end if; + elsif(CLKA_dly'event AND CLKA_dly'last_value = '0') then + + if (ena_dly_sampled = '1') then + if (ssra_dly_sampled = '1') then + DOA_zd(DOAW_1 downto 0) := SRVA_A(DOAW_1 downto 0); + DOA_clsn_zero := (others => '0'); + DOA_clsn := (others => '0'); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := SRVA_A((DOPAW_1 + DOAW) downto DOAW); + DOPA_clsn_zero := (others => '0'); + DOPA_clsn := (others => '0'); + end if; + else +----------------------- Start COLLISION A ------------------------------ + + if(SimCollisionCheck_var /= 0) then + DOA_clsn_sav := DOA_clsn; + DOPA_clsn_sav := DOPA_clsn; + + DOA_clsn := (others => '0'); + DOPA_clsn := (others => '0'); + clsn_xbufs.DO1_clsn := (others => '0'); + clsn_xbufs.DOP1_clsn := (others => '0'); + clsn_xbufs.MEM1_clsn := (others => '0'); + clsn_xbufs.MEMP1_clsn := (others => '0'); + + clsn_xbufs.DO2_clsn := (others => '0'); + clsn_xbufs.DOP2_clsn := (others => '0'); + clsn_xbufs.MEM2_clsn := (others => '0'); + clsn_xbufs.MEMP2_clsn := (others => '0'); + + clsn_type.active_port := 1; + addr_overlap := false; + clsn_type.read_write := false; + clsn_type.write_read := false; + clsn_type.write_write := false; + +-- CLKA_time := now; + + ClkCollisionCheck( + violation => collision_clka_clkb, + CheckEnabled => ((TO_X01(ena_dly_sampled) = '1') and (TO_X01(enb_dly_sampled) = '1')), + CLK1_time => CLKA_time, + CLK2_time => CLKB_time, + SETUP_All => SETUP_ALL, + SETUP_READ_FIRST => SETUP_READ_FIRST + ); + + if(collision_clka_clkb /= 0) then + QkAddrOverlapChk( + addr_overlap => addr_overlap, + data_widths => data_widths, + addra => addra_dly_sampled, + addrb => addrb_dly_sampled + ); + end if; + + if(addr_overlap) then + PreProcessWe1We2( + clsn_bufs => clsn_xbufs, + clsn_type => clsn_type, + memory => MEM, + di1 => dia_dly, + di2 => dib_dly, + dip1 => dipa_dly, + dip2 => dipb_dly, + addr1 => addra_dly_sampled, + addr2 => addrb_dly_sampled, + we1 => wea_dly_sampled, + we2 => web_dly_sampled, + zero_read_1 => zero_read_a, + zero_readp_1 => zero_parity_read_a, + zero_write_1 => zero_write_a, + zero_writep_1 => zero_parity_write_a, + zero_read_2 => zero_read_b, + zero_readp_2 => zero_parity_read_b, + zero_write_2 => zero_write_b, + zero_writep_2 => zero_parity_write_b, + wr_mode_1 => wr_mode_a, + wr_mode_2 => wr_mode_b, + violation => collision_clka_clkb, + DI1W => DIAW, + DIP1W => DIPAW, + DI2W => DIBW, + DIP2W => DIPBW, + DO1W => DOAW, + DOP1W => DOPAW, + DO2W => DOBW, + DOP2W => DOPBW + ); + end if; + + if(clsn_type.read_write or clsn_type.write_write or clsn_type.write_read) then + + if(clsn_type.write_write) then + collision_msg := Write_A_Write_B; + msg_addr1 := tmp_zero_write_a; + msg_addr2 := tmp_zero_write_b; + elsif(clsn_type.read_write) then + collision_msg := Read_A_Write_B; + msg_addr1 := tmp_zero_read_a; + msg_addr2 := tmp_zero_write_b; + elsif(clsn_type.write_read) then + collision_msg := Write_A_Read_B; +-- msg_addr1 := tmp_zero_write_a; +-- msg_addr2 := tmp_zero_read_b; + msg_addr1 := tmp_zero_read_b; + msg_addr2 := tmp_zero_write_a; + end if; + + if(SimCollisionCheck_var = 1) then + --- Message + Memory_Collision_Msg_ramb16 + ( collision_type => collision_msg, + EntityName => "RAMB16BWE", + InstanceName => RAMB16BWE'path_name, + address_1 => msg_addr1, + address_2 => msg_addr2 + ); + + DOA_clsn := (others => '0'); + DOPA_clsn := (others => '0'); + DOA_clsn_sav := DOA_clsn; + DOPA_clsn_sav := DOPA_clsn; + + elsif(SimCollisionCheck_var = 2) then + + DOA_clsn_read_index := SLV_TO_INT(tmp_zero_read_a(4 downto 0)); + DOB_clsn_read_index := SLV_TO_INT(tmp_zero_read_b(4 downto 0)); + DOA_clsn(DOAW_1 downto 0) := clsn_xbufs.DO1_clsn((DOA_clsn_read_index+DOAW_1) downto DOA_clsn_read_index); + DOB_clsn(DOBW_1 downto 0) := clsn_xbufs.DO2_clsn((DOB_clsn_read_index+DOBW_1) downto DOB_clsn_read_index); + if(DOPAW_1 /= -1) then + DOPA_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0)); + DOPA_clsn(DOPAW_1 downto 0) := clsn_xbufs.DOP1_clsn((DOPA_clsn_read_index+DOPAW_1) downto DOPA_clsn_read_index); + end if; + + if(DOPBW_1 /= -1) then + DOPB_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0)); + DOPB_clsn(DOPBW_1 downto 0) := clsn_xbufs.DOP2_clsn((DOPB_clsn_read_index+DOPBW_1) downto DOPB_clsn_read_index); + end if; + + if(wr_mode_a = "10") then + DOA_clsn(DOAW_1 downto 0) := DOA_clsn(DOAW_1 downto 0) xor DOA_clsn_sav(DOAW_1 downto 0); + if(DOPAW_1 /= -1) then + DOPA_clsn(DOPAW_1 downto 0) := DOPA_clsn(DOPAW_1 downto 0) xor DOPA_clsn_sav(DOPAW_1 downto 0); + end if; + end if; + + if(wr_mode_b = "10") then + DOB_clsn(DOBW_1 downto 0) := DOB_clsn(DOBW_1 downto 0) xor DOB_clsn_sav(DOBW_1 downto 0); + if(DOPBW_1 /= -1) then + DOPB_clsn(DOPBW_1 downto 0) := DOPB_clsn(DOPBW_1 downto 0) xor DOPB_clsn_sav(DOPBW_1 downto 0); + end if; + end if; + + elsif(SimCollisionCheck_var = 3) then + --- Message + Memory_Collision_Msg_ramb16 + ( collision_type => collision_msg, + EntityName => "RAMB16BWE", + InstanceName => RAMB16BWE'path_name, + address_1 => msg_addr1, + address_2 => msg_addr2 + ); + + DOA_clsn_read_index := SLV_TO_INT(tmp_zero_read_a(4 downto 0)); + DOB_clsn_read_index := SLV_TO_INT(tmp_zero_read_b(4 downto 0)); + DOA_clsn(DOAW_1 downto 0) := clsn_xbufs.DO1_clsn((DOA_clsn_read_index+DOAW_1) downto DOA_clsn_read_index); + DOB_clsn(DOBW_1 downto 0) := clsn_xbufs.DO2_clsn((DOB_clsn_read_index+DOBW_1) downto DOB_clsn_read_index); + if(DOPAW_1 /= -1) then + DOPA_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0)); + DOPA_clsn(DOPAW_1 downto 0) := clsn_xbufs.DOP1_clsn((DOPA_clsn_read_index+DOPAW_1) downto DOPA_clsn_read_index); + end if; + + if(DOPBW_1 /= -1) then + DOPB_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0)); + DOPB_clsn(DOPBW_1 downto 0) := clsn_xbufs.DOP2_clsn((DOPB_clsn_read_index+DOPBW_1) downto DOPB_clsn_read_index); + end if; + + if(wr_mode_a = "10") then + DOA_clsn(DOAW_1 downto 0) := DOA_clsn(DOAW_1 downto 0) xor DOA_clsn_sav(DOAW_1 downto 0); + if(DOPAW_1 /= -1) then + DOPA_clsn(DOPAW_1 downto 0) := DOPA_clsn(DOPAW_1 downto 0) xor DOPA_clsn_sav(DOPAW_1 downto 0); + end if; + end if; + + if(wr_mode_b = "10") then + DOB_clsn(DOBW_1 downto 0) := DOB_clsn(DOBW_1 downto 0) xor DOB_clsn_sav(DOBW_1 downto 0); + if(DOPBW_1 /= -1) then + DOPB_clsn(DOPBW_1 downto 0) := DOPB_clsn(DOPBW_1 downto 0) xor DOPB_clsn_sav(DOPBW_1 downto 0); + end if; + end if; + + + end if; + + end if; + + DOA_clsn_zero := DOA_clsn; + DOPA_clsn_zero := DOPA_clsn; + if(ssrb_dly_sampled = '0') then + DOB_clsn_zero := DOB_clsn; + DOPB_clsn_zero := DOPB_clsn; + end if; + + end if; + +---------------- END COLLISION A ------------------------------ + if (wr_mode_a = "00") then + + case DIAW is + --------- + when 1|2|4|8 => + --------- + tmp_we(1 downto 0) := addra_dly_sampled( 4 downto 3); + wea_index := SLV_TO_INT(tmp_we); + if(wea_dly_sampled(wea_index) = '1') then + if(DOAW > DIAW) then + DOA_zd_buf(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto ADDRESS_READ_A); + DOA_zd_buf(((DOA_INDEX *DIAW) + DIAW_1) downto (DOA_INDEX *DIAW)) := DIA_dly(DIAW_1 downto 0); + DOA_zd(DOAW_1 downto 0) := DOA_zd_buf(DOAW_1 downto 0); + + if(DOPAW_1 /= -1) then + DOPA_zd_buf(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A)); + DOPA_zd_buf(((DOPA_INDEX *DIPAW) + DIPAW_1) downto (DOPA_INDEX *DIPAW)) := DIPA_dly(DIPAW_1 downto 0); + DOPA_zd(DOPAW_1 downto 0) := DOPA_zd_buf(DOPAW_1 downto 0); + end if; + elsif(DOAW <= DIAW) then +--FP DOA_zd(DOAW_1 downto 0) := DIA_dly(DOAW_1 downto 0); + DOA_zd(DOAW_1 downto 0) := DIA_dly((((DOA_INDEX)*DOAW)+ DOAW_1) downto ((DOA_INDEX)*DOAW)); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := DIPA_dly(DOPAW_1 downto 0); + end if; + end if; + elsif(wea_dly_sampled(wea_index) = '0') then + DOA_zd(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto (ADDRESS_READ_A)); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A)); + end if; + end if; + + --------- + when 16 => + --------- + if(DOAW > DIAW) then + DOA_zd_buf(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto ADDRESS_READ_A); + DOPA_zd_buf(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A)); + +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + + xout_we_seg1(1) := addra_dly_sampled(4); + xout_we_seg1(0) := '0'; + xout_we_seg2(1) := addra_dly_sampled(4); + xout_we_seg2(0) := '1'; + + if(wea_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= wea_dly_sampled(SLV_TO_INT(xout_we_seg2))) then + DOA_zd_buf(DOAW_1 downto 0) := (others => 'X'); + DOPA_zd_buf(DOPAW_1 downto 0) := (others => 'X'); + else + tmp_we(1) := addra_dly_sampled(4); + tmp_we(0) := '0'; + wea_index := SLV_TO_INT(tmp_we); + if(wea_dly_sampled(wea_index) = '1') then + DOA_zd_buf(((DOA_INDEX *DIAW) + (DIAW/2 - 1)) downto (DOA_INDEX *DIAW)) := DIA_dly((DIAW/2 - 1) downto 0); + DOPA_zd_buf(((DOPA_INDEX *DIPAW) + (DIPAW/2 - 1)) downto (DOPA_INDEX *DIPAW)) := DIPA_dly((DIPAW/2 - 1) downto 0); + end if; + + tmp_we(1) := addra_dly_sampled(4); + tmp_we(0) := '1'; + wea_index := SLV_TO_INT(tmp_we); + if(wea_dly_sampled(wea_index) = '1') then + DOA_zd_buf(((DOA_INDEX *DIAW) + DIAW_1) downto ((DOA_INDEX *DIAW) + DIAW/2 )) := DIA_dly(DIAW_1 downto DIAW/2); + DOPA_zd_buf(((DOPA_INDEX *DIPAW) + DIPAW_1) downto ((DOPA_INDEX *DIPAW) + DIPAW/2 )) := DIPA_dly(DIPAW_1 downto DIPAW/2); + end if; + + end if; + + DOA_zd(DOAW_1 downto 0) := DOA_zd_buf(DOAW_1 downto 0); + DOPA_zd(DOPAW_1 downto 0) := DOPA_zd_buf(DOPAW_1 downto 0); + + end if; + +------------------- + if(DOAW <= DIAW) then + DOA_zd_buf(DIAW_1 downto 0) := MEM((ADDRESS_WRITE_A + DIAW_1) downto ADDRESS_WRITE_A); + if(DOPAW_1 /= -1) then + DOPA_zd_buf(DIPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A)); + end if; +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + + xout_we_seg1(1) := addra_dly_sampled(4); + xout_we_seg1(0) := '0'; + xout_we_seg2(1) := addra_dly_sampled(4); + xout_we_seg2(0) := '1'; + + tmp_we(1) := addra_dly_sampled(4); + tmp_we(0) := '0'; + wea_index := SLV_TO_INT(tmp_we); + if(wea_dly_sampled(wea_index) = '1') then + DOA_zd_buf((DIAW/2 - 1) downto 0) := DIA_dly((DIAW/2 -1 ) downto 0); + if(DOPAW_1 /= -1) then + DOPA_zd_buf((DIPAW/2 - 1) downto 0) := DIPA_dly((DIPAW/2 -1 ) downto 0); + end if; + elsif(wea_dly_sampled(wea_index) = '0') then + if(wea_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= wea_dly_sampled(SLV_TO_INT(xout_we_seg2))) then + DOA_zd_buf((DIAW/2 - 1) downto 0) := (others => 'X'); + if(DOPAW_1 /= -1) then + DOPA_zd_buf((DIPAW/2 - 1) downto 0) := (others => 'X'); + end if; + end if; + end if; + + tmp_we(1) := addra_dly_sampled(4); + tmp_we(0) := '1'; + wea_index := SLV_TO_INT(tmp_we); + if(wea_dly_sampled(wea_index) = '1') then + DOA_zd_buf(DIAW_1 downto DIAW/2 ) := DIA_dly(DIAW_1 downto DIAW/2); + if(DOPAW_1 /= -1) then + DOPA_zd_buf(DIPAW_1 downto DIPAW/2 ) := DIPA_dly(DIPAW_1 downto DIPAW/2); + end if; + elsif(wea_dly_sampled(wea_index) = '0') then + if(wea_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= wea_dly_sampled(SLV_TO_INT(xout_we_seg2))) then + DOA_zd_buf(DIAW_1 downto DIAW/2 ) := (others => 'X'); + if(DOPAW_1 /= -1) then + DOPA_zd_buf(DIPAW_1 downto DIPAW/2 ) := (others => 'X'); + end if; + end if; + end if; + +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + if((wea_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= wea_dly_sampled(SLV_TO_INT(xout_we_seg2))) and (DOAW /= DIAW)) then + DOA_zd_buf(DIAW_1 downto 0) := (others => 'X'); + DOPA_zd_buf(DIPAW_1 downto 0) := (others => 'X'); + end if; + + DOA_zd(DOAW_1 downto 0) := DOA_zd_buf(((DOA_INDEX * DOAW) + DOAW_1) downto (DOA_INDEX * DOAW)); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := DOPA_zd_buf(((DOPA_INDEX * DOPAW) + DOPAW_1) downto (DOPA_INDEX * DOPAW)); + end if; + + end if; + + --------- + when 32 => + --------- + + for i in 0 to 3 loop + if (wea_dly_sampled(i) = '1') then + DOA_zd_buf(((DIAW/4)*(i+1) - 1) downto (DIAW/4)*i) := DIA_dly(((DIAW/4)*(i+1) - 1) downto (DIAW/4)*i); + if(DOPAW_1 /= -1) then + DOPA_zd_buf(((DIPAW/4)*(i+1) - 1) downto (DIPAW/4)*i) := DIPA_dly(((DIPAW/4)*(i+1) - 1) downto (DIPAW/4)*i); + end if; + elsif (wea_dly_sampled(i) = '0') then +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + DOA_zd_buf(((DIAW/4)*(i+1) - 1) downto (DIAW/4)*i) := (others => 'X'); + if(DOPAW_1 /= -1) then + DOPA_zd_buf(((DIPAW/4)*(i+1) - 1) downto (DIPAW/4)*i) := (others => 'X'); + end if; + end if; + end loop; + +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + if((wea_dly_sampled(0) = '0') and (wea_dly_sampled(1) = '0') and (wea_dly_sampled(2) = '0') and (wea_dly_sampled(3) = '0')) then + DOA_zd_buf(DIAW_1 downto 0) := MEM((ADDRESS_WRITE_A + DIAW_1) downto ADDRESS_WRITE_A); + if(DOPAW_1 /= -1) then + DOPA_zd_buf(DIPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A)); + end if; + + elsif(not((wea_dly_sampled(0) = '1') and (wea_dly_sampled(1) = '1') and (wea_dly_sampled(2) = '1') and (wea_dly_sampled(3) = '1'))) then + if(DOAW /= DIAW) then + DOA_zd_buf(DIAW_1 downto 0) := (others => 'X'); + if(DOPAW_1 /= -1) then + DOPA_zd_buf(DIPAW_1 downto 0) := (others => 'X'); + end if; + end if; + end if; + + DOA_zd(DOAW_1 downto 0) := DOA_zd_buf(((DOA_INDEX * DOAW) + DOAW_1) downto (DOA_INDEX * DOAW)); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := DOPA_zd_buf(((DOPA_INDEX * DOPAW) + DOPAW_1) downto (DOPA_INDEX * DOPAW)); + end if; + + when others => + null; + end case; + + elsif(wr_mode_a = "01") then + DOA_zd(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto (ADDRESS_READ_A)); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A)); + end if; + elsif(wr_mode_a = "10") then + case DIAW is + when 1|2|4|8 => + tmp_we(1 downto 0) := addra_dly_sampled( 4 downto 3); + wea_index := SLV_TO_INT(tmp_we); + if (wea_dly_sampled(wea_index) = '0') then + DOA_zd(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto (ADDRESS_READ_A)); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A)); + end if; + end if; + ---------- + when 16|32 => + ---------- + if ((wea_dly_sampled(0) = '0') and (wea_dly_sampled(1) = '0') and (wea_dly_sampled(2) = '0') and (wea_dly_sampled(3) = '0'))then + DOA_zd(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto (ADDRESS_READ_A)); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A)); + end if; + end if; + ---------- + when others => + ---------- + null; + end case; + end if; + end if; + end if; -- /* end ena_dly_sampled = '1' */ + end if; + +------------------------------------------------------------------------ +------------ Port B ---------------------------------------------------- +------------------------------------------------------------------------ + if(GSR_CLKB_dly = '1') then + DOB_zd(DOBW_1 downto 0) := INI_B(DOBW_1 downto 0); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := INI_B((DOPBW_1 + DOBW) downto DOBW); + end if; + elsif(CLKB_dly'event AND CLKB_dly'last_value = '0') then + if (enb_dly_sampled = '1') then + if (ssrb_dly_sampled = '1') then + DOB_zd(DOBW_1 downto 0) := SRVA_B(DOBW_1 downto 0); + DOB_clsn_zero := (others => '0'); + DOB_clsn := (others => '0'); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := SRVA_B((DOPBW_1 + DOBW) downto DOBW); + DOPB_clsn_zero := (others => '0'); + DOPB_clsn := (others => '0'); + end if; + else +----------------------- Start COLLISION B ------------------------------ + if(SimCollisionCheck_var /= 0) then + DOB_clsn_sav := DOB_clsn; + DOPB_clsn_sav := DOPB_clsn; + + DOB_clsn := (others => '0'); + DOPB_clsn := (others => '0'); + clsn_xbufs.DO1_clsn := (others => '0'); + clsn_xbufs.DOP1_clsn := (others => '0'); + clsn_xbufs.MEM1_clsn := (others => '0'); + clsn_xbufs.MEMP1_clsn := (others => '0'); + + clsn_xbufs.DO2_clsn := (others => '0'); + clsn_xbufs.DOP2_clsn := (others => '0'); + clsn_xbufs.MEM2_clsn := (others => '0'); + clsn_xbufs.MEMP2_clsn := (others => '0'); + + clsn_type.active_port := 2; + addr_overlap := false; + clsn_type.read_write := false; + clsn_type.write_read := false; + clsn_type.write_write := false; + +-- CLKB_time := now; + + ClkCollisionCheck( + violation => collision_clka_clkb, + CheckEnabled => ((TO_X01(ena_dly_sampled) = '1') and (TO_X01(enb_dly_sampled) = '1')), + CLK1_time => CLKB_time, + CLK2_time => CLKA_time, + SETUP_All => SETUP_ALL, + SETUP_READ_FIRST => SETUP_READ_FIRST + ); + + if(collision_clka_clkb /= 0) then + QkAddrOverlapChk( + addr_overlap => addr_overlap, + data_widths => data_widths, + addra => addra_dly_sampled, + addrb => addrb_dly_sampled + ); + end if; + + if(addr_overlap) then + PreProcessWe1We2( + clsn_bufs => clsn_xbufs, + clsn_type => clsn_type, + memory => MEM, + di1 => dib_dly, + di2 => dia_dly, + dip1 => dipb_dly, + dip2 => dipa_dly, + addr1 => addrb_dly_sampled, + addr2 => addra_dly_sampled, + we1 => web_dly_sampled, + we2 => wea_dly_sampled, + zero_read_1 => zero_read_b, + zero_readp_1 => zero_parity_read_b, + zero_write_1 => zero_write_b, + zero_writep_1 => zero_parity_write_b, + zero_read_2 => zero_read_a, + zero_readp_2 => zero_parity_read_a, + zero_write_2 => zero_write_a, + zero_writep_2 => zero_parity_write_a, + wr_mode_1 => wr_mode_b, + wr_mode_2 => wr_mode_a, + violation => collision_clka_clkb, + DI1W => DIBW, + DIP1W => DIPBW, + DI2W => DIAW, + DIP2W => DIPAW, + DO1W => DOBW, + DOP1W => DOPBW, + DO2W => DOAW, + DOP2W => DOPAW + ); + end if; + + if(clsn_type.read_write or clsn_type.write_write or clsn_type.write_read) then + + if(clsn_type.write_write) then + collision_msg := Write_B_Write_A; +-- msg_addr1 := tmp_zero_write_b; +-- msg_addr2 := tmp_zero_write_a; + msg_addr1 := tmp_zero_write_a; + msg_addr2 := tmp_zero_write_b; + elsif(clsn_type.read_write) then + collision_msg := Read_B_Write_A; + msg_addr1 := tmp_zero_read_b; + msg_addr2 := tmp_zero_write_a; + elsif(clsn_type.write_read) then + collision_msg := Write_B_Read_A; +-- msg_addr1 := tmp_zero_write_b; +-- msg_addr2 := tmp_zero_read_a; + msg_addr1 := tmp_zero_read_a; + msg_addr2 := tmp_zero_write_b; + end if; + + if(SimCollisionCheck_var = 1) then + --- Message + Memory_Collision_Msg_ramb16 + ( collision_type => collision_msg, + EntityName => "RAMB16BWE", + InstanceName => RAMB16BWE'path_name, + address_1 => msg_addr1, + address_2 => msg_addr2 + ); + + DOB_clsn := (others => '0'); + DOPB_clsn := (others => '0'); + DOB_clsn_sav := DOB_clsn; + DOPB_clsn_sav := DOPB_clsn; + + elsif(SimCollisionCheck_var = 2) then + + DOB_clsn_read_index := SLV_TO_INT(tmp_zero_read_b(4 downto 0)); + DOA_clsn_read_index := SLV_TO_INT(tmp_zero_read_a(4 downto 0)); + + DOB_clsn(DOBW_1 downto 0) := clsn_xbufs.DO1_clsn((DOB_clsn_read_index+DOBW_1) downto DOB_clsn_read_index); + DOA_clsn(DOAW_1 downto 0) := clsn_xbufs.DO2_clsn((DOA_clsn_read_index+DOAW_1) downto DOA_clsn_read_index); + + if(DOPBW_1 /= -1) then + DOPB_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0)); + DOPB_clsn(DOPBW_1 downto 0) := clsn_xbufs.DOP1_clsn((DOPB_clsn_read_index+DOPBW_1) downto DOPB_clsn_read_index); + end if; + + if(DOPAW_1 /= -1) then + DOPA_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0)); + DOPA_clsn(DOPAW_1 downto 0) := clsn_xbufs.DOP2_clsn((DOPA_clsn_read_index+DOPAW_1) downto DOPA_clsn_read_index); + end if; + + if(wr_mode_b = "10") then + DOB_clsn(DOBW_1 downto 0) := DOB_clsn(DOBW_1 downto 0) xor DOB_clsn_sav(DOBW_1 downto 0); + if(DOPBW_1 /= -1) then + DOPB_clsn(DOPBW_1 downto 0) := DOPB_clsn(DOPBW_1 downto 0) xor DOPB_clsn_sav(DOPBW_1 downto 0); + end if; + end if; + + if(wr_mode_a = "10") then + DOA_clsn(DOAW_1 downto 0) := DOA_clsn(DOAW_1 downto 0) xor DOA_clsn_sav(DOAW_1 downto 0); + if(DOPAW_1 /= -1) then + DOPA_clsn(DOPAW_1 downto 0) := DOPA_clsn(DOPAW_1 downto 0) xor DOPA_clsn_sav(DOPAW_1 downto 0); + end if; + end if; + + + elsif(SimCollisionCheck_var = 3) then + --- Message + Memory_Collision_Msg_ramb16 + ( collision_type => collision_msg, + EntityName => "RAMB16BWE", + InstanceName => RAMB16BWE'path_name, + address_1 => msg_addr1, + address_2 => msg_addr2 + ); + + + DOB_clsn_read_index := SLV_TO_INT(tmp_zero_read_b(4 downto 0)); + DOA_clsn_read_index := SLV_TO_INT(tmp_zero_read_a(4 downto 0)); + + DOB_clsn(DOBW_1 downto 0) := clsn_xbufs.DO1_clsn((DOB_clsn_read_index+DOBW_1) downto DOB_clsn_read_index); + DOA_clsn(DOAW_1 downto 0) := clsn_xbufs.DO2_clsn((DOA_clsn_read_index+DOAW_1) downto DOA_clsn_read_index); + + if(DOPBW_1 /= -1) then + DOPB_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0)); + DOPB_clsn(DOPBW_1 downto 0) := clsn_xbufs.DOP1_clsn((DOPB_clsn_read_index+DOPBW_1) downto DOPB_clsn_read_index); + end if; + + if(DOPAW_1 /= -1) then + DOPA_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0)); + DOPA_clsn(DOPAW_1 downto 0) := clsn_xbufs.DOP2_clsn((DOPA_clsn_read_index+DOPAW_1) downto DOPA_clsn_read_index); + end if; + + if(wr_mode_b = "10") then + DOB_clsn(DOBW_1 downto 0) := DOB_clsn(DOBW_1 downto 0) xor DOB_clsn_sav(DOBW_1 downto 0); + if(DOPBW_1 /= -1) then + DOPB_clsn(DOPBW_1 downto 0) := DOPB_clsn(DOPBW_1 downto 0) xor DOPB_clsn_sav(DOPBW_1 downto 0); + end if; + end if; + + if(wr_mode_a = "10") then + DOA_clsn(DOAW_1 downto 0) := DOA_clsn(DOAW_1 downto 0) xor DOA_clsn_sav(DOAW_1 downto 0); + if(DOPAW_1 /= -1) then + DOPA_clsn(DOPAW_1 downto 0) := DOPA_clsn(DOPAW_1 downto 0) xor DOPA_clsn_sav(DOPAW_1 downto 0); + end if; + end if; + + end if; + + end if; + + DOB_clsn_zero := DOB_clsn; + DOPB_clsn_zero := DOPB_clsn; + if(ssra_dly_sampled = '0') then + DOA_clsn_zero := DOA_clsn; + DOPA_clsn_zero := DOPA_clsn; + end if; + + end if; + +---------------- END COLLISION B ------------------------------ + if (wr_mode_b = "00") then + + case DIBW is + --------- + when 1|2|4|8 => + --------- + tmp_we(1 downto 0) := addrb_dly_sampled( 4 downto 3); + web_index := SLV_TO_INT(tmp_we); + if(web_dly_sampled(web_index) = '1') then + if(DOBW > DIBW) then + DOB_zd_buf(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto ADDRESS_READ_B); + DOB_zd_buf(((DOB_INDEX *DIBW) + DIBW_1) downto (DOB_INDEX *DIBW)) := DIB_dly(DIBW_1 downto 0); + DOB_zd(DOBW_1 downto 0) := DOB_zd_buf(DOBW_1 downto 0); + + if(DOPBW_1 /= -1) then + DOPB_zd_buf(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B)); + DOPB_zd_buf(((DOPB_INDEX *DIPBW) + DIPBW_1) downto (DOPB_INDEX *DIPBW)) := DIPB_dly(DIPBW_1 downto 0); + DOPB_zd(DOPBW_1 downto 0) := DOPB_zd_buf(DOPBW_1 downto 0); + end if; + elsif(DOBW <= DIBW) then +--FP DOB_zd(DOBW_1 downto 0) := DIB_dly(DOBW_1 downto 0); + DOB_zd(DOBW_1 downto 0) := DIB_dly((((DOB_INDEX)*DOBW)+ DOBW_1) downto ((DOB_INDEX)*DOBW)); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := DIPB_dly(DOPBW_1 downto 0); + end if; + end if; + elsif(web_dly_sampled(web_index) = '0') then + DOB_zd(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto (ADDRESS_READ_B)); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B)); + end if; + end if; + + --------- + when 16 => + --------- + if(DOBW > DIBW) then + DOB_zd_buf(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto ADDRESS_READ_B); + DOPB_zd_buf(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B)); +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + + xout_we_seg1(1) := addrb_dly_sampled(4); + xout_we_seg1(0) := '0'; + xout_we_seg2(1) := addrb_dly_sampled(4); + xout_we_seg2(0) := '1'; + + if(web_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= web_dly_sampled(SLV_TO_INT(xout_we_seg2))) then + DOB_zd_buf(DOBW_1 downto 0) := (others => 'X'); + DOPB_zd_buf(DOPBW_1 downto 0) := (others => 'X'); + else + tmp_we(1) := addrb_dly_sampled(4); + tmp_we(0) := '0'; + web_index := SLV_TO_INT(tmp_we); + if(web_dly_sampled(web_index) = '1') then + DOB_zd_buf(((DOB_INDEX *DIBW) + (DIBW/2 - 1)) downto (DOB_INDEX *DIBW)) := DIB_dly((DIBW/2 - 1) downto 0); + DOPB_zd_buf(((DOPB_INDEX *DIPBW) + (DIPBW/2 - 1)) downto (DOPB_INDEX *DIPBW)) := DIPB_dly((DIPBW/2 - 1) downto 0); + end if; + + tmp_we(1) := addrb_dly_sampled(4); + tmp_we(0) := '1'; + web_index := SLV_TO_INT(tmp_we); + if(web_dly_sampled(web_index) = '1') then + DOB_zd_buf(((DOB_INDEX *DIBW) + DIBW_1) downto ((DOB_INDEX *DIBW) + DIBW/2 )) := DIB_dly(DIBW_1 downto DIBW/2); + DOPB_zd_buf(((DOPB_INDEX *DIPBW) + DIPBW_1) downto ((DOPB_INDEX *DIPBW) + DIPBW/2 )) := DIPB_dly(DIPBW_1 downto DIPBW/2); + end if; + + end if; + + DOB_zd(DOBW_1 downto 0) := DOB_zd_buf(DOBW_1 downto 0); + DOPB_zd(DOPBW_1 downto 0) := DOPB_zd_buf(DOPBW_1 downto 0); + + end if; + +------------------- + if(DOBW <= DIBW) then + DOB_zd_buf(DIBW_1 downto 0) := MEM((ADDRESS_WRITE_B + DIBW_1) downto ADDRESS_WRITE_B); + if(DOPBW_1 /= -1) then + DOPB_zd_buf(DIPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B)); + end if; +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + + xout_we_seg1(1) := addrb_dly_sampled(4); + xout_we_seg1(0) := '0'; + xout_we_seg2(1) := addrb_dly_sampled(4); + xout_we_seg2(0) := '1'; + + tmp_we(1) := addrb_dly_sampled(4); + tmp_we(0) := '0'; + web_index := SLV_TO_INT(tmp_we); + if(web_dly_sampled(web_index) = '1') then + DOB_zd_buf((DIBW/2 - 1) downto 0) := DIB_dly((DIBW/2 -1 ) downto 0); + if(DOPBW_1 /= -1) then + DOPB_zd_buf((DIPBW/2 - 1) downto 0) := DIPB_dly((DIPBW/2 -1 ) downto 0); + end if; + elsif(web_dly_sampled(web_index) = '0') then + if(web_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= web_dly_sampled(SLV_TO_INT(xout_we_seg2))) then + DOB_zd_buf((DIBW/2 - 1) downto 0) := (others => 'X'); + if(DOPBW_1 /= -1) then + DOPB_zd_buf((DIPBW/2 - 1) downto 0) := (others => 'X'); + end if; + end if; + end if; + + tmp_we(1) := addrb_dly_sampled(4); + tmp_we(0) := '1'; + web_index := SLV_TO_INT(tmp_we); + if(web_dly_sampled(web_index) = '1') then + DOB_zd_buf(DIBW_1 downto DIBW/2 ) := DIB_dly(DIBW_1 downto DIBW/2); + if(DOPBW_1 /= -1) then + DOPB_zd_buf(DIPBW_1 downto DIPBW/2 ) := DIPB_dly(DIPBW_1 downto DIPBW/2); + end if; + elsif(web_dly_sampled(web_index) = '0') then + if(web_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= web_dly_sampled(SLV_TO_INT(xout_we_seg2))) then + DOB_zd_buf(DIBW_1 downto DIBW/2 ) := (others => 'X'); + if(DOPBW_1 /= -1) then + DOPB_zd_buf(DIPBW_1 downto DIPBW/2 ) := (others => 'X'); + end if; + end if; + end if; + +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + if((web_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= web_dly_sampled(SLV_TO_INT(xout_we_seg2))) and (DOBW /= DIBW)) then + DOB_zd_buf(DIBW_1 downto 0) := (others => 'X'); + DOPB_zd_buf(DIPBW_1 downto 0) := (others => 'X'); + end if; + + DOB_zd(DOBW_1 downto 0) := DOB_zd_buf(((DOB_INDEX * DOBW) + DOBW_1) downto (DOB_INDEX * DOBW)); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := DOPB_zd_buf(((DOPB_INDEX * DOPBW) + DOPBW_1) downto (DOPB_INDEX * DOPBW)); + end if; + + end if; + + --------- + when 32 => + --------- + for i in 0 to 3 loop + if (web_dly_sampled(i) = '1') then + DOB_zd_buf(((DIBW/4)*(i+1) - 1) downto (DIBW/4)*i) := DIB_dly(((DIBW/4)*(i+1) - 1) downto (DIBW/4)*i); + if(DOPBW_1 /= -1) then + DOPB_zd_buf(((DIPBW/4)*(i+1) - 1) downto (DIPBW/4)*i) := DIPB_dly(((DIPBW/4)*(i+1) - 1) downto (DIPBW/4)*i); + end if; + elsif (web_dly_sampled(i) = '0') then +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + DOB_zd_buf(((DIBW/4)*(i+1) - 1) downto (DIBW/4)*i) := (others => 'X'); + if(DOPBW_1 /= -1) then + DOPB_zd_buf(((DIPBW/4)*(i+1) - 1) downto (DIPBW/4)*i) := (others => 'X'); + end if; + end if; + end loop; +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + if((web_dly_sampled(0) = '0') and (web_dly_sampled(1) = '0') and (web_dly_sampled(2) = '0') and (web_dly_sampled(3) = '0')) then + DOB_zd_buf(DIBW_1 downto 0) := MEM((ADDRESS_WRITE_B + DIBW_1) downto ADDRESS_WRITE_B); + if(DOPBW_1 /= -1) then + DOPB_zd_buf(DIPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B)); + end if; + elsif(not((web_dly_sampled(0) = '1') and (web_dly_sampled(1) = '1') and (web_dly_sampled(2) = '1') and (web_dly_sampled(3) = '1'))) then + if(DOBW /= DIBW) then + DOB_zd_buf(DIBW_1 downto 0) := (others => 'X'); + if(DOPBW_1 /= -1) then + DOPB_zd_buf(DIPBW_1 downto 0) := (others => 'X'); + end if; + end if; + end if; + + DOB_zd(DOBW_1 downto 0) := DOB_zd_buf(((DOB_INDEX * DOBW) + DOBW_1) downto (DOB_INDEX * DOBW)); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := DOPB_zd_buf(((DOPB_INDEX * DOPBW) + DOPBW_1) downto (DOPB_INDEX * DOPBW)); + end if; + + when others => + null; + end case; + + elsif(wr_mode_b = "01") then + DOB_zd(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto (ADDRESS_READ_B)); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B)); + end if; + elsif(wr_mode_b = "10") then + case DIBW is + when 1|2|4|8 => + tmp_we(1 downto 0) := addrb_dly_sampled( 4 downto 3); + web_index := SLV_TO_INT(tmp_we); + if (web_dly_sampled(web_index) = '0') then + DOB_zd(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto (ADDRESS_READ_B)); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B)); + end if; + end if; + ---------- + when 16|32 => + ---------- + if ((web_dly_sampled(0) = '0') and (web_dly_sampled(1) = '0') and (web_dly_sampled(2) = '0') and (web_dly_sampled(3) = '0'))then + DOB_zd(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto (ADDRESS_READ_B)); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B)); + end if; + end if; + ---------- + when others => + ---------- + null; + end case; + end if; + end if; + end if; -- /* end enb_dly_sampled = '1' */ + end if; + +------------------------------------------------------------------------ +------------ Port A -- Memory Update ---------------------------------- +------------------------------------------------------------------------ + + if((GSR_CLKA_dly = '0') and rising_edge(CLKA_dly)) then + if (ena_dly_sampled = '1') then + case DIAW is + -------------- + when 1|2|4|8 => + -------------- + tmp_we(1 downto 0) := addra_dly_sampled( 4 downto 3); + wea_index := SLV_TO_INT(tmp_we); + if (wea_dly_sampled(wea_index) = '1') then + if (VALID_ADDRA) then + MEM((ADDRESS_WRITE_A + DIAW_1) downto (ADDRESS_WRITE_A)) := DIA_dly(DIAW_1 downto 0); + if(DIPAW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A)) := DIPA_dly(DIPAW_1 downto 0); + end if; + else + DOA_zd(DOAW_1 downto 0) := (others => 'X'); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := (others => 'X'); + end if; + end if; -- /* VAILD ADDRA */ + end if; -- /* wea_dly_sampled = '1' */ + + --------- + when 16 => + --------- + tmp_we(1) := addra_dly_sampled(4); + tmp_we(0) := '0'; + wea_index := SLV_TO_INT(tmp_we); + if (wea_dly_sampled(wea_index) = '1') then + if (VALID_ADDRA) then + MEM((ADDRESS_WRITE_A + DIAW/2 -1) downto (ADDRESS_WRITE_A)) := DIA_dly((DIAW/2 - 1) downto 0); + if(DIPAW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW/2 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A)) := DIPA_dly((DIPAW/2 -1) downto 0); + end if; + end if; -- /* VAILD ADDRA */ + end if; -- /* wea_dly_sampled = '1' */ + + tmp_we(0) := '1'; + wea_index := SLV_TO_INT(tmp_we); + if (wea_dly_sampled(wea_index) = '1') then + if (VALID_ADDRA) then + MEM((ADDRESS_WRITE_A + DIAW_1) downto (ADDRESS_WRITE_A + DIAW/2)) := DIA_dly(DIAW_1 downto DIAW/2); + if(DIPAW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A + DIPAW/2)) := DIPA_dly(DIPAW_1 downto DIPAW/2); + end if; + end if; -- /* VAILD ADDRA */ + end if; -- /* wea_dly_sampled = '1' */ + + --------- + when 32 => + --------- + wea_index := 0; + if (wea_dly_sampled(wea_index) = '1') then + if (VALID_ADDRA) then + MEM((ADDRESS_WRITE_A + (DIAW/4)*1 -1) downto (ADDRESS_WRITE_A)) := DIA_dly((((DIAW/4)*1) - 1) downto 0); + if(DIPAW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*1 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A)) := DIPA_dly(((DIPAW/4)*1 -1) downto 0); + end if; + end if; -- /* VAILD ADDRA */ + end if; -- /* wea_dly_sampled = '1' */ + + wea_index := 1; + if (wea_dly_sampled(wea_index) = '1') then + if (VALID_ADDRA) then + MEM((ADDRESS_WRITE_A + (DIAW/4)*2 -1) downto (ADDRESS_WRITE_A + (DIAW/4)*1)) := DIA_dly((((DIAW/4)*2) - 1) downto (DIAW/4)*1); + if(DIPAW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*2 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*1)) := DIPA_dly(((DIPAW/4)*2 -1) downto ((DIPAW/4)*1)); + end if; + end if; -- /* VAILD ADDRA */ + end if; -- /* wea_dly_sampled = '1' */ + + wea_index := 2; + if (wea_dly_sampled(wea_index) = '1') then + if (VALID_ADDRA) then + MEM((ADDRESS_WRITE_A + (DIAW/4)*3 -1) downto (ADDRESS_WRITE_A + (DIAW/4)*2)) := DIA_dly((((DIAW/4)*3) - 1) downto (DIAW/4)*2); + if(DIPAW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*3 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*2)) := DIPA_dly(((DIPAW/4)*3 -1) downto ((DIPAW/4)*2)); + end if; + end if; -- /* VAILD ADDRA */ + end if; -- /* wea_dly_sampled = '1' */ + + wea_index := 3; + if (wea_dly_sampled(wea_index) = '1') then + if (VALID_ADDRA) then + MEM((ADDRESS_WRITE_A + (DIAW/4)*4 -1) downto (ADDRESS_WRITE_A + (DIAW/4)*3)) := DIA_dly((((DIAW/4)*4) - 1) downto (DIAW/4)*3); + if(DIPAW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*4 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*3)) := DIPA_dly(((DIPAW/4)*4 -1) downto ((DIPAW/4)*3)); + end if; + end if; -- /* VAILD ADDRA */ + end if; -- /* wea_dly_sampled = '1' */ + when others => + null; + end case; + +----------------------- Start COLLISION MEMORY UPDATE A ------------------------------ + + if(SimCollisionCheck_var /= 0) then + if(clsn_type.write_write) then + tmp_membuf := (others => '0'); + DOA_clsn_write_index := SLV_TO_INT(tmp_zero_write_a(4 downto 0)); + tmp_membuf(DIAW_1 downto 0) := MEM((ADDRESS_WRITE_A + DIAW_1) downto (ADDRESS_WRITE_A)); + MEM((ADDRESS_WRITE_A + DIAW_1) downto (ADDRESS_WRITE_A)) := tmp_membuf(DIAW_1 downto 0) xor clsn_xbufs.MEM1_clsn((DOA_clsn_write_index+DIAW_1) downto DOA_clsn_write_index); + + if((DIPAW_1 /= -1) and (DIPBW_1 /= -1)) then + tmp_membuf := (others => '0'); + DOPA_clsn_write_index := SLV_TO_INT(tmp_zero_parity_write_a(1 downto 0)); + tmp_membuf(DIPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A)); + MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A)) := tmp_membuf(DIPAW_1 downto 0) xor clsn_xbufs.MEMP1_clsn((DOPA_clsn_write_index + DIPAW_1) downto DOPA_clsn_write_index); + end if; + end if; + end if; + +----------------------- END COLLISION MEMORY UPDATE A ------------------------------ + + end if; -- /* end ena_dly_sampled = '1' */ + end if; +------------------------------------------------------------------------ +------------ Port B -- Memory Update ---------------------------------- +------------------------------------------------------------------------ + + if((GSR_CLKB_dly = '0') and rising_edge(CLKB_dly)) then + if (enb_dly_sampled = '1') then + case DIBW is + -------------- + when 1|2|4|8 => + -------------- + tmp_we(1 downto 0) := addrb_dly_sampled( 4 downto 3); + web_index := SLV_TO_INT(tmp_we); + if (web_dly_sampled(web_index) = '1') then + if (VALID_ADDRB) then + MEM((ADDRESS_WRITE_B + DIBW_1) downto (ADDRESS_WRITE_B)) := DIB_dly(DIBW_1 downto 0); + if(DIPBW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B)) := DIPB_dly(DIPBW_1 downto 0); + end if; + else + DOB_zd(DOBW_1 downto 0) := (others => 'X'); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := (others => 'X'); + end if; + end if; -- /* VAILD ADDRB */ + end if; -- /* web_dly_sampled = '1' */ + + --------- + when 16 => + --------- + tmp_we(1) := addrb_dly_sampled(4); + tmp_we(0) := '0'; + web_index := SLV_TO_INT(tmp_we); + if (web_dly_sampled(web_index) = '1') then + if (VALID_ADDRB) then + MEM((ADDRESS_WRITE_B + DIBW/2 -1) downto (ADDRESS_WRITE_B)) := DIB_dly((DIBW/2 - 1) downto 0); + if(DIPBW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW/2 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B)) := DIPB_dly((DIPBW/2 -1) downto 0); + end if; + end if; -- /* VAILD ADDRB */ + end if; -- /* web_dly_sampled = '1' */ + + tmp_we(0) := '1'; + web_index := SLV_TO_INT(tmp_we); + if (web_dly_sampled(web_index) = '1') then + if (VALID_ADDRB) then + MEM((ADDRESS_WRITE_B + DIBW_1) downto (ADDRESS_WRITE_B + DIBW/2)) := DIB_dly(DIBW_1 downto DIBW/2); + if(DIPBW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B + DIPBW/2)) := DIPB_dly(DIPBW_1 downto DIPBW/2); + end if; + end if; -- /* VAILD ADDRB */ + end if; -- /* web_dly_sampled = '1' */ + + --------- + when 32 => + --------- + web_index := 0; + if (web_dly_sampled(web_index) = '1') then + if (VALID_ADDRB) then + MEM((ADDRESS_WRITE_B + (DIBW/4)*1 -1) downto (ADDRESS_WRITE_B)) := DIB_dly((((DIBW/4)*1) - 1) downto 0); + if(DIPBW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*1 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B)) := DIPB_dly(((DIPBW/4)*1 -1) downto 0); + end if; + end if; -- /* VAILD ADDRB */ + end if; -- /* web_dly_sampled = '1' */ + + web_index := 1; + if (web_dly_sampled(web_index) = '1') then + if (VALID_ADDRB) then + MEM((ADDRESS_WRITE_B + (DIBW/4)*2 -1) downto (ADDRESS_WRITE_B + (DIBW/4)*1)) := DIB_dly((((DIBW/4)*2) - 1) downto (DIBW/4)*1); + if(DIPBW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*2 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*1)) := DIPB_dly(((DIPBW/4)*2 -1) downto ((DIPBW/4)*1)); + end if; + end if; -- /* VAILD ADDRB */ + end if; -- /* web_dly_sampled = '1' */ + + web_index := 2; + if (web_dly_sampled(web_index) = '1') then + if (VALID_ADDRB) then + MEM((ADDRESS_WRITE_B + (DIBW/4)*3 -1) downto (ADDRESS_WRITE_B + (DIBW/4)*2)) := DIB_dly((((DIBW/4)*3) - 1) downto (DIBW/4)*2); + if(DIPBW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*3 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*2)) := DIPB_dly(((DIPBW/4)*3 -1) downto ((DIPBW/4)*2)); + end if; + end if; -- /* VAILD ADDRB */ + end if; -- /* web_dly_sampled = '1' */ + + web_index := 3; + if (web_dly_sampled(web_index) = '1') then + if (VALID_ADDRB) then + MEM((ADDRESS_WRITE_B + (DIBW/4)*4 -1) downto (ADDRESS_WRITE_B + (DIBW/4)*3)) := DIB_dly((((DIBW/4)*4) - 1) downto (DIBW/4)*3); + if(DIPBW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*4 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*3)) := DIPB_dly(((DIPBW/4)*4 -1) downto ((DIPBW/4)*3)); + end if; + end if; -- /* VAILD ADDRB */ + end if; -- /* web_dly_sampled = '1' */ + when others => + null; + end case; + +----------------------- Start COLLISION MEMORY UPDATE B ------------------------------ + + if(SimCollisionCheck_var /= 0) then + if(clsn_type.write_write) then + tmp_membuf := (others => '0'); + DOB_clsn_write_index := SLV_TO_INT(tmp_zero_write_b(4 downto 0)); + tmp_membuf(DIBW_1 downto 0) := MEM((ADDRESS_WRITE_B + DIBW_1) downto (ADDRESS_WRITE_B)); + MEM((ADDRESS_WRITE_B + DIBW_1) downto (ADDRESS_WRITE_B)) := tmp_membuf(DIBW_1 downto 0) xor clsn_xbufs.MEM1_clsn((DOB_clsn_write_index+DIBW_1) downto DOB_clsn_write_index); + + if((DIPBW_1 /= -1) and (DIPAW_1 /= -1)) then + tmp_membuf := (others => '0'); + DOPB_clsn_write_index := SLV_TO_INT(tmp_zero_parity_write_b(1 downto 0)); + tmp_membuf(DIPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B)); + MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B)) := tmp_membuf(DIPBW_1 downto 0) xor clsn_xbufs.MEMP1_clsn((DOPB_clsn_write_index + DIPBW_1) downto DOPB_clsn_write_index); + end if; + end if; + end if; + +----------------------- END COLLISION MEMORY UPDATE B ------------------------------ + + end if; -- /* end enb_dly_sampled = '1' */ + end if; +--======================================================================================= +----- Port A + + DOA_viol(0) <= ViolationA xor DOA_zd(0) xor DOA_clsn_zero(0); + DOA_viol(1) <= ViolationA xor DOA_zd(1) xor DOA_clsn_zero(1); + DOA_viol(2) <= ViolationA xor DOA_zd(2) xor DOA_clsn_zero(2); + DOA_viol(3) <= ViolationA xor DOA_zd(3) xor DOA_clsn_zero(3); + DOA_viol(4) <= ViolationA xor DOA_zd(4) xor DOA_clsn_zero(4); + DOA_viol(5) <= ViolationA xor DOA_zd(5) xor DOA_clsn_zero(5); + DOA_viol(6) <= ViolationA xor DOA_zd(6) xor DOA_clsn_zero(6); + DOA_viol(7) <= ViolationA xor DOA_zd(7) xor DOA_clsn_zero(7); + DOA_viol(8) <= ViolationA xor DOA_zd(8) xor DOA_clsn_zero(8); + DOA_viol(9) <= ViolationA xor DOA_zd(9) xor DOA_clsn_zero(9); + DOA_viol(10) <= ViolationA xor DOA_zd(10) xor DOA_clsn_zero(10); + DOA_viol(11) <= ViolationA xor DOA_zd(11) xor DOA_clsn_zero(11); + DOA_viol(12) <= ViolationA xor DOA_zd(12) xor DOA_clsn_zero(12); + DOA_viol(13) <= ViolationA xor DOA_zd(13) xor DOA_clsn_zero(13); + DOA_viol(14) <= ViolationA xor DOA_zd(14) xor DOA_clsn_zero(14); + DOA_viol(15) <= ViolationA xor DOA_zd(15) xor DOA_clsn_zero(15); + DOA_viol(16) <= ViolationA xor DOA_zd(16) xor DOA_clsn_zero(16); + DOA_viol(17) <= ViolationA xor DOA_zd(17) xor DOA_clsn_zero(17); + DOA_viol(18) <= ViolationA xor DOA_zd(18) xor DOA_clsn_zero(18); + DOA_viol(19) <= ViolationA xor DOA_zd(19) xor DOA_clsn_zero(19); + DOA_viol(20) <= ViolationA xor DOA_zd(20) xor DOA_clsn_zero(20); + DOA_viol(21) <= ViolationA xor DOA_zd(21) xor DOA_clsn_zero(21); + DOA_viol(22) <= ViolationA xor DOA_zd(22) xor DOA_clsn_zero(22); + DOA_viol(23) <= ViolationA xor DOA_zd(23) xor DOA_clsn_zero(23); + DOA_viol(24) <= ViolationA xor DOA_zd(24) xor DOA_clsn_zero(24); + DOA_viol(25) <= ViolationA xor DOA_zd(25) xor DOA_clsn_zero(25); + DOA_viol(26) <= ViolationA xor DOA_zd(26) xor DOA_clsn_zero(26); + DOA_viol(27) <= ViolationA xor DOA_zd(27) xor DOA_clsn_zero(27); + DOA_viol(28) <= ViolationA xor DOA_zd(28) xor DOA_clsn_zero(28); + DOA_viol(29) <= ViolationA xor DOA_zd(29) xor DOA_clsn_zero(29); + DOA_viol(30) <= ViolationA xor DOA_zd(30) xor DOA_clsn_zero(30); + DOA_viol(31) <= ViolationA xor DOA_zd(31) xor DOA_clsn_zero(31); + DOPA_viol(0) <= ViolationA xor DOPA_zd(0) xor DOPA_clsn_zero(0); + DOPA_viol(1) <= ViolationA xor DOPA_zd(1) xor DOPA_clsn_zero(1); + DOPA_viol(2) <= ViolationA xor DOPA_zd(2) xor DOPA_clsn_zero(2); + DOPA_viol(3) <= ViolationA xor DOPA_zd(3) xor DOPA_clsn_zero(3); + +----- Port B + + DOB_viol(0) <= ViolationB xor DOB_zd(0) xor DOB_clsn_zero(0); + DOB_viol(1) <= ViolationB xor DOB_zd(1) xor DOB_clsn_zero(1); + DOB_viol(2) <= ViolationB xor DOB_zd(2) xor DOB_clsn_zero(2); + DOB_viol(3) <= ViolationB xor DOB_zd(3) xor DOB_clsn_zero(3); + DOB_viol(4) <= ViolationB xor DOB_zd(4) xor DOB_clsn_zero(4); + DOB_viol(5) <= ViolationB xor DOB_zd(5) xor DOB_clsn_zero(5); + DOB_viol(6) <= ViolationB xor DOB_zd(6) xor DOB_clsn_zero(6); + DOB_viol(7) <= ViolationB xor DOB_zd(7) xor DOB_clsn_zero(7); + DOB_viol(8) <= ViolationB xor DOB_zd(8) xor DOB_clsn_zero(8); + DOB_viol(9) <= ViolationB xor DOB_zd(9) xor DOB_clsn_zero(9); + DOB_viol(10) <= ViolationB xor DOB_zd(10) xor DOB_clsn_zero(10); + DOB_viol(11) <= ViolationB xor DOB_zd(11) xor DOB_clsn_zero(11); + DOB_viol(12) <= ViolationB xor DOB_zd(12) xor DOB_clsn_zero(12); + DOB_viol(13) <= ViolationB xor DOB_zd(13) xor DOB_clsn_zero(13); + DOB_viol(14) <= ViolationB xor DOB_zd(14) xor DOB_clsn_zero(14); + DOB_viol(15) <= ViolationB xor DOB_zd(15) xor DOB_clsn_zero(15); + DOB_viol(16) <= ViolationB xor DOB_zd(16) xor DOB_clsn_zero(16); + DOB_viol(17) <= ViolationB xor DOB_zd(17) xor DOB_clsn_zero(17); + DOB_viol(18) <= ViolationB xor DOB_zd(18) xor DOB_clsn_zero(18); + DOB_viol(19) <= ViolationB xor DOB_zd(19) xor DOB_clsn_zero(19); + DOB_viol(20) <= ViolationB xor DOB_zd(20) xor DOB_clsn_zero(20); + DOB_viol(21) <= ViolationB xor DOB_zd(21) xor DOB_clsn_zero(21); + DOB_viol(22) <= ViolationB xor DOB_zd(22) xor DOB_clsn_zero(22); + DOB_viol(23) <= ViolationB xor DOB_zd(23) xor DOB_clsn_zero(23); + DOB_viol(24) <= ViolationB xor DOB_zd(24) xor DOB_clsn_zero(24); + DOB_viol(25) <= ViolationB xor DOB_zd(25) xor DOB_clsn_zero(25); + DOB_viol(26) <= ViolationB xor DOB_zd(26) xor DOB_clsn_zero(26); + DOB_viol(27) <= ViolationB xor DOB_zd(27) xor DOB_clsn_zero(27); + DOB_viol(28) <= ViolationB xor DOB_zd(28) xor DOB_clsn_zero(28); + DOB_viol(29) <= ViolationB xor DOB_zd(29) xor DOB_clsn_zero(29); + DOB_viol(30) <= ViolationB xor DOB_zd(30) xor DOB_clsn_zero(30); + DOB_viol(31) <= ViolationB xor DOB_zd(31) xor DOB_clsn_zero(31); + DOPB_viol(0) <= ViolationB xor DOPB_zd(0) xor DOPB_clsn_zero(0); + DOPB_viol(1) <= ViolationB xor DOPB_zd(1) xor DOPB_clsn_zero(1); + DOPB_viol(2) <= ViolationB xor DOPB_zd(2) xor DOPB_clsn_zero(2); + DOPB_viol(3) <= ViolationB xor DOPB_zd(3) xor DOPB_clsn_zero(3); + + wait on ADDRA_dly, ADDRB_dly, CLKA_dly, CLKB_dly, DIA_dly, DIB_dly, DIPA_dly, DIPB_dly, ENA_dly, ENB_dly, GSR_ipd, GSR_CLKA_dly, GSR_CLKB_dly, SSRA_dly, SSRB_dly, WEA_dly, WEB_dly; + end process VITALBehavior; +----- ############################################################################### + + prcs_output:process (DOA_viol, DOPA_viol, DOB_viol, DOPB_viol) + begin + DOA <= DOA_viol after SYNC_PATH_DELAY; + DOPA <= DOPA_viol after SYNC_PATH_DELAY; + DOB <= DOB_viol after SYNC_PATH_DELAY; + DOPB <= DOPB_viol after SYNC_PATH_DELAY; + end process prcs_output; + +end RAMB16BWE_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Function Simulation Library Component +-- / / Configuration Simulation Model +-- /___/ /\ Filename : sim_config_s3a.vhd +-- \ \ / \ Timestamp : +-- \___\/\___\ +-- +-- Revision: +-- 03/07/07 - Initial version. +-- 06/11/07 - Change DEVICE_ID to bit vector (CR441606). +-- End Revision + +----- CELL SIM_CONFIG_S3A ----- +library IEEE; +use IEEE.std_logic_1164.all; + + + + +library STD; +use STD.TEXTIO.all; + +library unisim; +use unisim.VPKG.all; +use unisim.VCOMPONENTS.all; + +entity SIM_CONFIG_S3A is + generic ( + + DEVICE_ID : bit_vector := X"00000000" + + ); + + port ( + CSOB : out std_ulogic := '1'; + DONE : inout std_ulogic; + CCLK : in std_ulogic := '0'; + D : inout std_logic_vector(7 downto 0); + DCMLOCK : in std_ulogic := '0'; + CSIB : in std_ulogic := '0'; + INITB : inout std_ulogic := 'H'; + M : in std_logic_vector(2 downto 0) := "000"; + PROGB : in std_ulogic := '0'; + RDWRB : in std_ulogic := '0' + ); + + + +end SIM_CONFIG_S3A; + +architecture SIM_CONFIG_S3A_V of SIM_CONFIG_S3A is + + function crc_next ( + crc_currf : in std_logic_vector(21 downto 0); + crc_inputf : in std_logic_vector(21 downto 0) + ) return std_logic_vector + is + variable i_crc : integer; + variable crc_next_v : std_logic_vector(21 downto 0); + begin + i_crc := 21; + for i in 21 downto 16 loop + crc_next_v(i_crc) := crc_currf(i_crc-1) xor crc_inputf(i_crc); + i_crc := i_crc -1; + end loop; + + crc_next_v(15) := crc_currf(14) xor crc_inputf(15) xor crc_currf(21); + + i_crc := 14; + for i in 14 downto 13 loop + crc_next_v(i_crc) := crc_currf(i_crc-1) xor crc_inputf(i_crc); + i_crc := i_crc -1; + end loop; + + crc_next_v(12) := crc_currf(11) xor crc_inputf(12) xor crc_currf(21); + + i_crc := 11; + for i in 11 downto 8 loop + crc_next_v(i_crc) := crc_currf(i_crc-1) xor crc_inputf(i_crc); + i_crc := i_crc -1; + end loop; + + crc_next_v(7) := crc_currf(6) xor crc_inputf(7) xor crc_currf(21); + + i_crc := 6; + for i in 6 downto 1 loop + crc_next_v(i_crc) := crc_currf(i_crc-1) xor crc_inputf(i_crc); + i_crc := i_crc -1; + end loop; + + crc_next_v(0) := crc_inputf(0) xor crc_currf(21); + + return crc_next_v; + end crc_next; + +function bit_revers8 ( din8 : in std_logic_vector(7 downto 0)) + return std_logic_vector is + variable bit_rev8 : std_logic_vector(7 downto 0); + begin + bit_rev8(0) := din8(7); + bit_rev8(1) := din8(6); + bit_rev8(2) := din8(5); + bit_rev8(3) := din8(4); + bit_rev8(4) := din8(3); + bit_rev8(5) := din8(2); + bit_rev8(6) := din8(1); + bit_rev8(7) := din8(0); + + return bit_rev8; + end bit_revers8; + + + constant cfg_Tprog : time := 300000 ps; -- min PROG must be low, 300 ns + constant cfg_Tpl : time := 100000 ps; -- max program latency us. + constant STARTUP_PH0 : std_logic_vector(2 downto 0) := "000"; + constant STARTUP_PH1 : std_logic_vector(2 downto 0) := "001"; + constant STARTUP_PH2 : std_logic_vector(2 downto 0) := "010"; + constant STARTUP_PH3 : std_logic_vector(2 downto 0) := "011"; + constant STARTUP_PH4 : std_logic_vector(2 downto 0) := "100"; + constant STARTUP_PH5 : std_logic_vector(2 downto 0) := "101"; + constant STARTUP_PH6 : std_logic_vector(2 downto 0) := "110"; + constant STARTUP_PH7 : std_logic_vector(2 downto 0) := "111"; + signal GSR : std_ulogic := '1'; + signal GTS : std_ulogic := '1'; + signal GWE : std_ulogic := '0'; + signal cclk_in : std_ulogic; + signal csi_b_in : std_ulogic; + signal prog_b_in : std_ulogic; + signal rdwr_b_in : std_ulogic; + signal crc_err_flag_reg : std_ulogic := '0'; + signal crc_err_flag_tot : std_ulogic; + signal mode_sample_flag : std_ulogic := '0'; + signal init_b_p : std_ulogic := '1'; + signal done_o : std_ulogic := '0'; + signal done_in : std_ulogic ; + signal por_b : std_ulogic := '0'; + signal prog_b_t : std_ulogic; + signal m_in : std_logic_vector(2 downto 0); + signal mode_pin_in : std_logic_vector(2 downto 0) := "000"; + signal d_in : std_logic_vector(7 downto 0) := "00000000"; + signal d_out : std_logic_vector(7 downto 0) := "00000000"; + signal prog_pulse_low_edge : time := 0 ps; + signal prog_pulse_low : time := 0 ps; + signal wr_cnt : integer := 0; + signal conti_data_cnt : integer := 0; + signal rd_data_cnt : integer := 0; + signal abort_cnt : integer := 0; + signal csbo_flag : std_ulogic := '0'; + signal pack_in_reg : std_logic_vector(15 downto 0) := X"0000"; + signal reg_addr : std_logic_vector(5 downto 0) := "000000"; + signal rd_reg_addr : std_logic_vector(5 downto 0) := "000000"; + signal new_data_in_flag : std_ulogic := '0'; + signal wr_flag : std_ulogic := '0'; + signal rd_flag : std_ulogic := '0'; + signal cmd_wr_flag : std_ulogic := '0'; + signal cmd_rd_flag : std_ulogic := '0'; + signal bus_sync_flag : std_ulogic := '0'; + signal csi_sync : std_ulogic := '0'; + signal rd_sw_en : std_ulogic := '0'; + signal conti_data_flag : std_ulogic := '0'; + signal conti_data_flag_set : std_ulogic := '0'; + signal st_state : std_logic_vector(2 downto 0) := STARTUP_PH0; + signal nx_st_state : std_logic_vector(2 downto 0) := STARTUP_PH0; + signal startup_begin_flag : std_ulogic := '0'; + signal startup_end_flag : std_ulogic := '0'; + signal cmd_reg_new_flag : std_ulogic := '0'; + signal far_maj_min_flag : std_ulogic := '0'; + signal crc_reset : std_ulogic := '0'; + signal crc_rst : std_ulogic := '0'; + signal crc_ck : std_ulogic := '0'; + signal crc_err_flag : std_ulogic := '0'; + signal crc_en : std_ulogic := '0'; + signal desync_flag : std_ulogic := '0'; + signal crc_curr : std_logic_vector(21 downto 0) := "0000000000000000000000"; + signal gwe_out : std_ulogic := '0'; + signal gts_out : std_ulogic := '1'; + signal d_o : std_logic_vector(7 downto 0) := "00000000"; + signal outbus : std_logic_vector(7 downto 0) := "00000000"; + signal reboot_set : std_ulogic := '0'; + signal gsr_set : std_ulogic := '0'; + signal gts_usr_b : std_ulogic := '1'; + signal done_pin_drv : std_ulogic := '0'; + signal crc_bypass : std_ulogic := '0'; + signal reset_on_err : std_ulogic := '0'; + signal sync_timeout : std_ulogic := '0'; + signal crc_reg : std_logic_vector (31 downto 0); + signal idcode_reg : std_logic_vector (31 downto 0); + signal idcode_tmp : std_logic_vector (31 downto 0); + signal far_min_reg : std_logic_vector (15 downto 0); + signal far_maj_reg : std_logic_vector (15 downto 0); + signal fdri_reg : std_logic_vector (15 downto 0); + signal fdro_reg : std_logic_vector (15 downto 0); + signal ctl_reg : std_logic_vector (15 downto 0); + signal cmd_reg : std_logic_vector (4 downto 0); + signal general1_reg : std_logic_vector (15 downto 0); + signal mask_reg : std_logic_vector (15 downto 0); + signal lout_reg : std_logic_vector (15 downto 0); + signal cor1_reg : std_logic_vector (15 downto 0); + signal cor2_reg : std_logic_vector (15 downto 0); + signal pwrdn_reg : std_logic_vector (15 downto 0); + signal flr_reg : std_logic_vector (15 downto 0); + signal snowplow_reg : std_logic_vector (15 downto 0); + signal hc_opt_reg : std_logic_vector (15 downto 0); + signal csbo_reg : std_logic_vector (15 downto 0); + signal general2_reg : std_logic_vector (15 downto 0); + signal mode_reg : std_logic_vector (15 downto 0); + signal pu_gwe_reg : std_logic_vector (15 downto 0); + signal pu_gts_reg : std_logic_vector (15 downto 0); + signal mfwr_reg : std_logic_vector (15 downto 0); + signal cclk_freq_reg : std_logic_vector (15 downto 0); + signal seu_opt_reg : std_logic_vector (15 downto 0); + signal exp_sign_reg : std_logic_vector (31 downto 0); + signal rdbk_sign_reg : std_logic_vector (31 downto 0); + signal shutdown_set : std_ulogic := '0'; + signal desynch_set : std_ulogic := '0'; + signal done_cycle_reg : std_logic_vector (2 downto 0) := "100"; + signal gts_cycle_reg : std_logic_vector (2 downto 0) := "101"; + signal gwe_cycle_reg : std_logic_vector (2 downto 0) := "110"; + signal ghigh_b : std_ulogic := '0'; + signal eos_startup : std_ulogic := '0'; + signal startup_set : std_ulogic := '0'; + signal startup_set_pulse : std_logic_vector (1 downto 0) := "00"; + signal abort_out_en : std_ulogic := '0'; + signal id_error_flag : std_ulogic := '0'; + signal iprog_b : std_ulogic := '1'; + signal abort_flag_wr : std_ulogic := '0'; + signal abort_flag_rd : std_ulogic := '0'; + signal abort_status : std_logic_vector (7 downto 0) := "00000000"; + signal persist_en : std_ulogic := '0'; + signal rst_sync : std_ulogic := '0'; + signal abort_dis: std_ulogic := '0'; + signal lock_cycle_reg : std_logic_vector (2 downto 0) := "000"; + signal rbcrc_no_pin : std_ulogic := '0'; + signal abort_flag_rst : std_ulogic := '0'; + signal gsr_st_out : std_ulogic := '1'; + signal gsr_cmd_out : std_ulogic := '0'; + signal d_o_en : std_ulogic := '0'; + signal stat_reg : std_logic_vector (15 downto 0) := X"0000"; + signal rst_intl : std_ulogic := '0'; + signal rw_en : std_ulogic := '0'; + signal gsr_out : std_ulogic; + signal cfgerr_b_flag : std_ulogic; + signal abort_flag : std_ulogic := '0'; + signal downcont : std_logic_vector (27 downto 0) := "0000000000000000000000000000"; + signal downcont_int : integer := 0; + signal type2_flag : std_ulogic := '0'; + signal rst_en : std_ulogic := '1'; + signal prog_b_a : std_ulogic := '1'; + signal csbo_b_out : std_ulogic := '1'; + signal dcm_locked : std_ulogic; + signal d_out_en : std_ulogic := '0'; + signal device_id_reg : std_logic_vector (31 downto 0) := TO_STDLOGICVECTOR(DEVICE_ID); + + +begin + + CSOB <= csbo_b_out; + INITB <= (not crc_err_flag_tot) when mode_sample_flag = '1' else init_b_p when init_b_p ='0' else 'H'; + DONE <= done_o; + done_in <= DONE; + + + cclk_in <= CCLK; + dcm_locked <= DCMLOCK; + csi_b_in <= CSIB; + d_in <= D; + D <= d_out when d_out_en = '1' else "ZZZZZZZZ"; + + m_in <= M; + prog_b_in <= PROGB; + rdwr_b_in <= RDWRB; + + + INIPROC : process + begin + if (DEVICE_ID = X"00000000") then + assert FALSE report "Attribute Syntax Error : The attribute DEVICE_ID on SIM_CONFIG_S3A is not set." severity error; + end if; + wait; + end process; + + + + GSR <= gsr_out; + GTS <= gts_out; + GWE <= gwe_out; + csbo_b_out <= '0' when (csbo_flag= '1') else '1'; + cfgerr_b_flag <= rw_en and (not id_error_flag) and (not crc_err_flag_reg); + crc_err_flag_tot <= id_error_flag or crc_err_flag_reg; + d_out <= abort_status when (abort_out_en = '1') else outbus; + d_out_en <= d_o_en; + crc_en <= '1'; + + process (abort_out_en, csi_b_in, rdwr_b_in, rd_flag) begin + if (abort_out_en='1') then + d_o_en <= '1'; + else + d_o_en <= rdwr_b_in and (not csi_b_in) and rd_flag; + end if; + end process; + + + process begin + if (prog_b_in'event and prog_b_in = '0') then + rst_en <= '0'; + wait for cfg_Tprog; + wait for 1 ps; + rst_en <= '1'; + end if; + wait on prog_b_in; + end process; + + process begin + if (rising_edge(rst_en)) then + init_b_p <= '0'; + wait until (rising_edge (prog_b_in)); + init_b_p <= '1' after cfg_Tpl; + end if; + wait on rst_en; + end process; + + + process begin + if (rst_en = '0') then + prog_b_a <= '1'; + elsif (rising_edge(rst_en)) then + if (prog_b_in = '1' and prog_pulse_low=cfg_Tprog) then + prog_b_a <= '0'; + wait for 500 ps; + prog_b_a <= '1'; + elsif (prog_b_in = '0') then + prog_b_a <= '0'; + wait until (rising_edge(prog_b_in)); + prog_b_a <= '1'; + end if; + end if; + wait on rst_en, prog_b_in; + end process; + + process + begin + por_b <= '0'; + por_b <= '1' after 400 ns; + wait; + end process; + + prog_b_t <= prog_b_a and iprog_b and por_b; + + rst_intl <= '0' when (prog_b_t='0') else '1'; + + process (INITB, prog_b_t) + variable Message : line; + begin + if (falling_edge (prog_b_t)) then + mode_sample_flag <= '0'; + elsif (rising_edge(INITB)) then + if (mode_sample_flag = '0') then + if(prog_b_t = '1') then + mode_pin_in <= m_in; + mode_sample_flag <= '1' after 1 ps; + if (m_in /= "110") then + Write ( Message, string'(" Error: input M is ")); + Write ( Message, string'(SLV_TO_STR(m_in))); + Write ( Message, string'(" . Only Slave SelectMAP mode M=110 supported on SIM_CONFIG_S3A.")); + assert false report Message.all severity error; + DEALLOCATE (Message); + end if; + elsif (NOW > 0 ps) then + assert false report "Error: PROGB is not high when INITB goes high on SIM_CONFIG_S3A." severity error; + end if; + end if; + end if; + end process; + + + process (m_in) begin + if (mode_sample_flag = '1' and persist_en = '1') then + assert false report "Error : Mode pine M[2:0] changed after rising edge of INITB on SIM_CONFIG_S3A." severity error; + end if; + end process; + + prog_pulse_P : process (prog_b_in) + variable prog_pulse_low : time; + variable Message : line; + begin + if (falling_edge (prog_b_in)) then + prog_pulse_low_edge <= NOW; + else + if (NOW > 0 ps ) then + prog_pulse_low := NOW - prog_pulse_low_edge; + if (prog_pulse_low < cfg_Tprog ) then + Write ( Message, string'(" Error: Low time of PROGB is less than required minimum Tprogram time ")); + Write ( Message, prog_pulse_low); + Write ( Message, string'(" .")); + assert false report Message.all severity error; + end if; + end if; + end if; + end process; + + + rw_en <= '1' when ((mode_sample_flag = '1') and (csi_b_in = '0')) else '0'; + desync_flag <= (not rst_intl) or desynch_set or crc_err_flag or id_error_flag; + + process (cclk_in) begin + if (rising_edge(cclk_in)) then + csi_sync <= csi_b_in; + end if; + end process; + + process (cclk_in, rdwr_b_in) begin + if (rdwr_b_in = '0') then + rd_sw_en <= '0'; + elsif (rising_edge(cclk_in)) then + if (csi_sync = '1' and rdwr_b_in = '1') then + rd_sw_en <= '1'; + end if; + end if; + end process; + + + bus_sync_p : process (cclk_in, desync_flag) + variable tmp_byte : std_logic_vector (7 downto 0); + begin + if (desync_flag = '1') then + pack_in_reg <= "0000000000000000"; + new_data_in_flag <= '0'; + bus_sync_flag <= '0'; + wr_cnt <= 0; + wr_flag <= '0'; + rd_flag <= '0'; + elsif (rising_edge(cclk_in)) then + if (rw_en = '1' ) then + if (rdwr_b_in = '0') then + wr_flag <= '1'; + rd_flag <= '0'; + tmp_byte := bit_revers8(d_in(7 downto 0)); + if (bus_sync_flag = '0') then + if (pack_in_reg(7 downto 0) = "10101010" and tmp_byte = "10011001") then + bus_sync_flag <= '1'; + new_data_in_flag <= '0'; + wr_cnt <= 0; + else + pack_in_reg(7 downto 0) <= tmp_byte; + end if; + else + if (wr_cnt = 0) then + pack_in_reg(15 downto 8) <= tmp_byte; + new_data_in_flag <= '0'; + wr_cnt <= 1; + elsif (wr_cnt = 1) then + pack_in_reg(7 downto 0) <= tmp_byte; + new_data_in_flag <= '1'; + wr_cnt <= 0; + end if; + end if; + else --rdwr_b_in <= '1' + wr_flag <= '0'; + new_data_in_flag <= '0'; + if (rd_sw_en = '1') then + rd_flag <= '1'; + end if; + end if; + else --rw_en <= '0' + wr_flag <= '0'; + rd_flag <= '0'; + new_data_in_flag <= '0'; + end if; + end if; + end process; + + pack_decode_p : process (cclk_in, rst_intl) + variable tmp_v : std_logic_vector(5 downto 0); + variable tmp_v28 : std_logic_vector(27 downto 0); + variable idcode_tmp : std_logic_vector(31 downto 0); + variable message_line : line; + variable csbo_cnt : integer := 0; + variable crc_new : std_logic_vector(21 downto 0) := "0000000000000000000000"; + variable crc_input : std_logic_vector(21 downto 0) := "0000000000000000000000"; + begin + if (rst_intl = '0') then + conti_data_flag <= '0'; + conti_data_cnt <= 0; + cmd_wr_flag <= '0'; + cmd_rd_flag <= '0'; + id_error_flag <= '0'; + far_maj_min_flag <= '0'; + cmd_reg_new_flag <= '0'; + crc_curr(21 downto 0) <= "0000000000000000000000"; + crc_ck <= '0'; + csbo_cnt := 0; + csbo_flag <= '0'; + downcont <= "0000000000000000000000000000"; + downcont_int <= 0; + rd_data_cnt <= 0; + elsif (falling_edge(cclk_in)) then + if (crc_reset = '1' ) then + crc_reg(31 downto 0) <= X"00000000"; + exp_sign_reg(31 downto 0) <= X"00000000"; + crc_ck <= '0'; + crc_curr(21 downto 0) <= "0000000000000000000000"; + end if; + if (desynch_set = '1' or crc_err_flag = '1') then + conti_data_flag <= '0'; + conti_data_cnt <= 0; + cmd_wr_flag <= '0'; + cmd_rd_flag <= '0'; + far_maj_min_flag <= '0'; + cmd_reg_new_flag <= '0'; + crc_ck <= '0'; + csbo_cnt := 0; + csbo_flag <= '0'; + downcont <= "0000000000000000000000000000"; + downcont_int <= 0; + rd_data_cnt <= 0; + end if; + + if (new_data_in_flag = '1' and wr_flag = '1') then + if (conti_data_flag = '1' ) then + if (type2_flag = '0') then + case (reg_addr) is + when "000000" => if (conti_data_cnt = 1) then + crc_reg(15 downto 0) <= pack_in_reg; + crc_ck <= '1'; + elsif (conti_data_cnt = 2) then + crc_reg(31 downto 16) <= pack_in_reg; + crc_ck <= '0'; + end if; + when "000001" => if (conti_data_cnt = 2) then + far_maj_reg <= pack_in_reg; + far_maj_min_flag <= '1'; + elsif (conti_data_cnt = 1) then + if (far_maj_min_flag = '1') then + far_min_reg <= pack_in_reg; + far_maj_min_flag <= '0'; + else + far_maj_reg <= pack_in_reg; + end if; + end if; + when "000010" => far_min_reg <= pack_in_reg; + when "000011" => fdri_reg <= pack_in_reg; + when "000101" => cmd_reg <= pack_in_reg(4 downto 0); + when "000110" => ctl_reg <= (pack_in_reg and (not mask_reg)) or (ctl_reg and mask_reg); + when "000111" => mask_reg <= pack_in_reg; + when "001001" => lout_reg <= pack_in_reg; + when "001010" => cor1_reg <= pack_in_reg; + when "001011" => cor2_reg <= pack_in_reg; + when "001100" => pwrdn_reg <= pack_in_reg; + when "001101" => flr_reg <= pack_in_reg; + when "001110" => + if (conti_data_cnt = 1) then + idcode_reg(15 downto 0) <= pack_in_reg; + idcode_tmp := (idcode_reg(31 downto 16) & pack_in_reg); + if (idcode_tmp(27 downto 0) /= device_id_reg(27 downto 0)) then + id_error_flag <= '1'; + write(message_line, string'("Error : written value to IDCODE register is ")); + write(message_line, string'(SLV_TO_STR(idcode_tmp))); + write(message_line, string'(" which does not match DEVICE ID ")); + write(message_line, string'(SLV_TO_STR(device_id_reg))); + write(message_line, string'(".")); + assert false report message_line.all severity error; + DEALLOCATE(message_line); + else + id_error_flag <= '0'; + end if; + elsif (conti_data_cnt = 2) then + idcode_reg(31 downto 16) <= pack_in_reg; + end if; + + when "001111" => snowplow_reg <= pack_in_reg; + when "010000" => hc_opt_reg <= pack_in_reg; + when "010010" => csbo_reg <= pack_in_reg; + when "010011" => general1_reg <= pack_in_reg; + when "010100" => general2_reg <= pack_in_reg; + when "010101" => mode_reg <= pack_in_reg; + when "010110" => pu_gwe_reg <= pack_in_reg; + when "010111" => pu_gts_reg <= pack_in_reg; + when "011000" => mfwr_reg <= pack_in_reg; + when "011001" => cclk_freq_reg <= pack_in_reg; + when "011010" => seu_opt_reg <= pack_in_reg; + when "011011" => if (conti_data_cnt = 1) then + exp_sign_reg(15 downto 0) <= pack_in_reg; + elsif (conti_data_cnt = 2) then + exp_sign_reg(31 downto 16) <= pack_in_reg; + end if; + when others => NULL; + end case; + + if (reg_addr = "000101") then + cmd_reg_new_flag <= '1'; + else + cmd_reg_new_flag <= '0'; + end if; + + if (crc_en = '1') then + if ((reg_addr = "000101") and (pack_in_reg(4 downto 0) = "00111")) then + + crc_curr(21 downto 0) <= "0000000000000000000000"; + else + if ((reg_addr /= "000100") and (reg_addr /= "001000") and (reg_addr /= "011100") and + (reg_addr /= "000000") and (reg_addr /= "001001") and (reg_addr /= "010010")) then + crc_input(21 downto 0) := (reg_addr(5 downto 0) & pack_in_reg); + crc_new(21 downto 0) := crc_next(crc_curr, crc_input); + crc_curr(21 downto 0) <= crc_new; + end if; + end if; + end if; + else -- type2_flag + if (conti_data_cnt = 2) then + downcont(27 downto 16) <= pack_in_reg(11 downto 0); + elsif (conti_data_cnt = 1) then + downcont(15 downto 0) <= pack_in_reg; + tmp_v28 := (downcont(27 downto 16) & pack_in_reg ); + downcont_int <= SLV_TO_INT(tmp_v28); + end if; + end if; + + if (conti_data_cnt <= 1) then + conti_data_cnt <= 0; + type2_flag <= '0'; + else + conti_data_cnt <= conti_data_cnt - 1; + end if; + else --if (conti_data_flag = '0' ) + if ( downcont_int >= 1) then + if (crc_en = '1') then + crc_input(21 downto 0) := ("000011" & pack_in_reg); --FDRI address plus data + crc_new(21 downto 0) := crc_next(crc_curr, crc_input); + crc_curr(21 downto 0) <= crc_new; + end if; + end if; + + if ((pack_in_reg(15 downto 13) /= "001") and (downcont_int = 0)) then +-- assert false report "Warning : only Type 1 Packet supported on SIM_CONFIG_S3A." +-- severity warning; + cmd_wr_flag <= '0'; + type2_flag <= '1'; + conti_data_flag <= '1'; + conti_data_cnt <= 2; + else + if ((pack_in_reg(12 downto 11) = "01") and (downcont_int = 0)) then + if (pack_in_reg(4 downto 0) /= "00000") then + cmd_rd_flag <= '1'; + cmd_wr_flag <= '0'; + tmp_v := (pack_in_reg(4 downto 0) & '0'); +-- rd_data_cnt <= SLV_TO_INT(SLV=>tmp_v); + rd_data_cnt <= 4; + conti_data_cnt <= 0; + conti_data_flag <= '0'; + rd_reg_addr <= pack_in_reg(10 downto 5); + end if; + elsif ((pack_in_reg(12 downto 11) = "10") and (downcont_int = 0)) then + if (pack_in_reg(15 downto 5) = "00110010010") then + csbo_reg <= pack_in_reg; + csbo_cnt := SLV_TO_INT(SLV=>pack_in_reg(4 downto 0)); + csbo_flag <= '1'; + conti_data_flag <= '0'; + reg_addr <= pack_in_reg(10 downto 5); + cmd_wr_flag <= '1'; + conti_data_cnt <= 0; + elsif (pack_in_reg(4 downto 0) /= "00000") then + cmd_wr_flag <= '1'; + conti_data_flag <= '1'; + conti_data_cnt <= SLV_TO_INT(SLV=>pack_in_reg(4 downto 0)); + reg_addr <= pack_in_reg(10 downto 5); + end if; + else + cmd_wr_flag <= '0'; + conti_data_flag <= '0'; + conti_data_cnt <= 0; + end if; + end if; + cmd_reg_new_flag <= '0'; + crc_ck <= '0'; + end if; -- if (conti_data_flag = '0' ) + + if (csbo_cnt /= 0 ) then + if (csbo_flag = '1') then + csbo_cnt := csbo_cnt - 1; + end if; + else + csbo_flag <= '0'; + end if; + + + if (conti_data_cnt = 1) then + conti_data_flag <= '0'; + end if; + end if; + + if (rw_en = '1') then + if (rd_data_cnt = 1) then + rd_data_cnt <= 0; + elsif (rd_data_cnt = 0 and rd_flag = '1') then + cmd_rd_flag <= '0'; + elsif ((cmd_rd_flag = '1') and (rd_flag = '1')) then + rd_data_cnt <= rd_data_cnt - 1; + end if; + + if ((downcont_int >= 1) and (conti_data_flag = '0') and (new_data_in_flag = '1') and (wr_flag = '1')) then + downcont_int <= downcont_int - 1; + end if; + end if; + end if; + end process; + + rd_back_p : process ( cclk_in, rst_intl) begin + if (rst_intl = '0') then + outbus <= "00000000"; + elsif (rising_edge(cclk_in)) then + if (cmd_rd_flag = '1' and rdwr_b_in = '1') then + case (rd_reg_addr) is + when "000000" => if (rd_data_cnt = 1) then + outbus <= crc_reg(7 downto 0); + elsif (rd_data_cnt = 2) then + outbus <= crc_reg(15 downto 8); + elsif (rd_data_cnt = 3) then + outbus <= crc_reg(23 downto 16); + elsif (rd_data_cnt = 4) then + outbus <= crc_reg(31 downto 24); + end if; + when "001000" => if (rd_data_cnt = 1) then + outbus <= stat_reg(7 downto 0); + elsif (rd_data_cnt = 2) then + outbus <= stat_reg(15 downto 8); + elsif (rd_data_cnt = 3) then + outbus <= stat_reg(7 downto 0); + elsif (rd_data_cnt = 4) then + outbus <= stat_reg(15 downto 8); + end if; + when "001110" => if (rd_data_cnt = 1) then + outbus <= idcode_reg(7 downto 0); + elsif (rd_data_cnt = 2) then + outbus <= idcode_reg(15 downto 8); + elsif (rd_data_cnt = 3) then + outbus <= idcode_reg(23 downto 16); + elsif (rd_data_cnt = 4) then + outbus <= idcode_reg(31 downto 24); + end if; + when "011011" => if (rd_data_cnt = 1) then + outbus <= exp_sign_reg(7 downto 0); + elsif (rd_data_cnt = 2) then + outbus <= exp_sign_reg(15 downto 8); + elsif (rd_data_cnt = 3) then + outbus <= exp_sign_reg(23 downto 16); + elsif (rd_data_cnt = 4) then + outbus <= exp_sign_reg(31 downto 24); + end if; + when others => NULL; + end case; + + else + outbus <= "00000000"; + end if; + + end if; + end process; + + + crc_rst <= crc_reset or (not rst_intl); + + process ( cclk_in, crc_rst ) begin + if (crc_rst = '1') then + crc_err_flag <= '0'; + elsif (rising_edge(cclk_in)) then + if (crc_ck = '1') then + if (crc_bypass = '1') then + if (crc_reg(31 downto 0) /= X"9876defc") then + crc_err_flag <= '1'; + else + crc_err_flag <= '0'; + end if; + else + if (crc_curr(21 downto 0) /= crc_reg(21 downto 0)) then + crc_err_flag <= '1'; + else + crc_err_flag <= '0'; + end if; + end if; + else + crc_err_flag <= '0'; + end if; + end if; + end process; + + process ( crc_err_flag, rst_intl, bus_sync_flag) begin + if (rst_intl = '0') then + crc_err_flag_reg <= '0'; + elsif (rising_edge(crc_err_flag)) then + crc_err_flag_reg <= '1'; + elsif (rising_edge(bus_sync_flag)) then + crc_err_flag_reg <= '0'; + end if; + end process; + + process ( cclk_in, rst_intl) begin + if (rst_intl = '0') then + startup_set <= '0'; + crc_reset <= '0'; + gsr_set <= '0'; + shutdown_set <= '0'; + desynch_set <= '0'; + reboot_set <= '0'; + ghigh_b <= '0'; + elsif (rising_edge(cclk_in)) then + if (cmd_reg_new_flag = '1') then + if (cmd_reg = "00011") then + ghigh_b <= '1'; + elsif (cmd_reg = "01000") then + ghigh_b <= '0'; + end if; + + if (cmd_reg = "00101") then + startup_set <= '1'; + end if; + if (cmd_reg = "00111") then + crc_reset <= '1'; + end if; + if (cmd_reg = "01010") then + gsr_set <= '1'; + end if; + if (cmd_reg = "01011") then + shutdown_set <= '1'; + end if; + if (cmd_reg = "01101") then + desynch_set <= '1'; + end if; + if (cmd_reg = "01110") then + reboot_set <= '1'; + end if; + else + startup_set <= '0'; + crc_reset <= '0'; + gsr_set <= '0'; + shutdown_set <= '0'; + desynch_set <= '0'; + reboot_set <= '0'; + end if; + end if; + end process; + + + startup_set_pulse_p : process begin + if (rw_en = '0') then + startup_set_pulse <= "00"; + elsif (rising_edge(startup_set)) then + if (startup_set_pulse = "00") then + startup_set_pulse <= "01"; + end if; + elsif (rising_edge(desynch_set)) then + if (startup_set_pulse = "01") then + startup_set_pulse <= "11"; + wait until (rising_edge(cclk_in )); + startup_set_pulse <= "00"; + end if; + end if; + wait on startup_set, desynch_set, rw_en; + end process; + + + process (ctl_reg) begin + if (ctl_reg(3) = '1') then + persist_en <= '1'; + else + persist_en <= '0'; + end if; + + if (ctl_reg(0) = '1') then + gts_usr_b <= '1'; + else + gts_usr_b <= '0'; + end if; + end process; + + process (cor1_reg) begin + if (cor1_reg(2) = '1') then + done_pin_drv <= '1'; + else + done_pin_drv <= '0'; + end if; + + if (cor1_reg(4) = '1') then + crc_bypass <= '1'; + else + crc_bypass <= '0'; + end if; + end process; + + process (cor2_reg) begin + if (cor2_reg(15) = '1') then + reset_on_err <= '1'; + else + reset_on_err <= '0'; + end if; + + done_cycle_reg <= cor2_reg(11 downto 9); + lock_cycle_reg <= cor2_reg(8 downto 6); + gts_cycle_reg <= cor2_reg(5 downto 3); + gwe_cycle_reg <= cor2_reg(2 downto 0); + end process; + + + stat_reg(15) <= sync_timeout; + stat_reg(14) <= '0'; + stat_reg(13) <= DONE; + stat_reg(12) <= INITB; + stat_reg(11 downto 9) <= mode_pin_in; + stat_reg(5) <= ghigh_b; + stat_reg(4) <= gwe_out; + stat_reg(3) <= gts_out; + stat_reg(2) <= dcm_locked; + stat_reg(1) <= id_error_flag; + stat_reg(0) <= crc_err_flag_reg; + + + st_state_p : process ( cclk_in, rst_intl) begin + if (rst_intl = '0') then + st_state <= STARTUP_PH0; + startup_begin_flag <= '0'; + startup_end_flag <= '0'; + elsif (rising_edge(cclk_in)) then + if (nx_st_state = STARTUP_PH1) then + startup_begin_flag <= '1'; + startup_end_flag <= '0'; + elsif (st_state = STARTUP_PH7) then + startup_end_flag <= '1'; + startup_begin_flag <= '0'; + end if; + if ((lock_cycle_reg = "111") or (dcm_locked = '1') or (st_state /= lock_cycle_reg)) then + st_state <= nx_st_state; + else + st_state <= st_state; + end if; + end if; + end process; + + nx_st_state_p : process (st_state, startup_set_pulse, done_in ) begin + if ((( st_state = done_cycle_reg) and (done_in /= '0')) or ( st_state /= done_cycle_reg)) then + case (st_state) is + when STARTUP_PH0 => if (startup_set_pulse = "11" ) then + nx_st_state <= STARTUP_PH1; + else + nx_st_state <= STARTUP_PH0; + end if; + when STARTUP_PH1 => nx_st_state <= STARTUP_PH2; + + when STARTUP_PH2 => nx_st_state <= STARTUP_PH3; + + when STARTUP_PH3 => nx_st_state <= STARTUP_PH4; + + when STARTUP_PH4 => nx_st_state <= STARTUP_PH5; + + when STARTUP_PH5 => nx_st_state <= STARTUP_PH6; + + when STARTUP_PH6 => nx_st_state <= STARTUP_PH7; + + when STARTUP_PH7 => nx_st_state <= STARTUP_PH0; + when others => NULL; + end case; + end if; + end process; + + start_out_p : process ( cclk_in, rst_intl ) begin + if (rst_intl = '0') then + gwe_out <= '0'; + gts_out <= '1'; + eos_startup <= '0'; + gsr_st_out <= '1'; + done_o <= '0'; + elsif (rising_edge(cclk_in)) then + + if (nx_st_state = done_cycle_reg) then + if (done_in /= '0' or done_pin_drv = '1') then + done_o <= '1'; + else + done_o <= 'H'; + end if; + else + if (done_in /= '0') then + done_o <= '1'; + end if; + end if; + + if (nx_st_state = gwe_cycle_reg) then + gwe_out <= '1'; + end if; + + if (nx_st_state = gts_cycle_reg) then + gts_out <= '0'; + end if; + + if (nx_st_state = STARTUP_PH6) then + gsr_st_out <= '0'; + end if; + + if (nx_st_state = STARTUP_PH7) then + eos_startup <= '1'; + end if; + + end if; + end process; + + + gsr_out <= gsr_st_out or gsr_cmd_out; + + + process (rdwr_b_in , rst_intl, abort_flag_rst , csi_b_in) + begin + if (rst_intl = '0' or abort_flag_rst = '1' or csi_b_in = '1') then + abort_flag_wr <= '0'; + elsif (rising_edge(rdwr_b_in)) then + if (abort_dis = '0' and csi_b_in = '0') then + if (NOW /= 0 ps) then + abort_flag_wr <= '1'; + assert false report " Warning : RDWRB changes when CS_B low, which causes Configuration abort on SIM_CONFIG_S3A." + severity warning; + end if; + else + abort_flag_wr <= '0'; + end if; + end if; + end process; + + process ( rdwr_b_in, rst_intl, abort_flag_rst, csi_b_in) begin + if (rst_intl = '0' or csi_b_in = '1' or abort_flag_rst = '1') then + abort_flag_rd <= '0'; + elsif (falling_edge(rdwr_b_in)) then + if (abort_dis = '0' and csi_b_in = '0') then + if (NOW /= 0 ps) then + abort_flag_rd <= '1'; + assert false report " Warning : RDWRB changes when CS_B low, which causes Configuration abort on SIM_CONFIG_S3A." + severity warning; + end if; + else + abort_flag_rd <= '0'; + end if; + end if; + end process; + + abort_flag <= abort_flag_wr or abort_flag_rd; + + + process ( cclk_in, rst_intl) begin + if (rst_intl = '0') then + abort_cnt <= 0; + abort_out_en <= '0'; + elsif (rising_edge(cclk_in)) then + if ( abort_flag = '1' ) then + if (abort_cnt < 4) then + abort_cnt <= abort_cnt + 1; + abort_out_en <= '1'; + else + abort_flag_rst <= '1'; + end if; + else + abort_cnt <= 0; + abort_out_en <= '0'; + abort_flag_rst <= '0'; + end if; + + if (abort_cnt = 0) then + abort_status <= (cfgerr_b_flag & bus_sync_flag & "011111"); + elsif (abort_cnt = 1) then + abort_status <= (cfgerr_b_flag & "1001111"); + elsif (abort_cnt = 2) then + abort_status <= (cfgerr_b_flag & "0001111"); + elsif (abort_cnt = 3) then + abort_status <= (cfgerr_b_flag & "0011111"); + end if; + end if; + end process; + +end SIM_CONFIG_S3A_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/trilogy/VITAL/Attic/spi_access.vhd,v 1.20.2.2 2008/07/09 22:30:10 robh Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2008 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Internal logic access to the Serial Peripheral Interface (SPI) PROM data +-- /___/ /\ SPI_ACCESS.vhd +-- \ \ / \ Timestamp : Fri Oct 12 10:43:26 PDT 2007 +-- \___\/\___\ +-- +-- +-- Revision: +-- 10/12/07 - Initial version +-- 06/03/08 - Fixed vcs compiler warning message about synopsys_off +-- 07/09/08 - CR476247 - shorten simulation delays. +-- Change MISO out off state from H to 1. +-- End Revision + +----- CELL SPI_ACCESS ----- + +library std; + use std.textio.all; +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.std_logic_textio.all; + use IEEE.Std_logic_unsigned.all; + use IEEE.numeric_std.all; + +---entity declarations-------------- +entity SPI_ACCESS is + generic( + + SIM_DELAY_TYPE : string := "SCALED"; + SIM_DEVICE : string := "3S1400AN"; + SIM_FACTORY_ID : bit_vector :=X"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + SIM_USER_ID : bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; + SIM_MEM_FILE : string := "NONE" + + ); + +port( + MISO : out std_ulogic; + CLK : in std_ulogic; + CSB : in std_ulogic; + MOSI : in std_ulogic + ); + +end SPI_ACCESS; + +----architecture declarations------ +architecture SPI_ACCESS_V of SPI_ACCESS is + +constant SYNC_PATH_DELAY : time := 100 ps; + +constant InstancePath : string := "SPI_ACCESS"; + +constant binary_opt : std_logic := '0'; +-- unchanged time delays +constant Tdis : TIME := 0 ps ; +constant Tv : TIME := 0 ps ; +constant Tspickh : TIME := 6800 ps ; +constant Tspickl : TIME := 6800 ps ; + +-- divided delays +constant Tspiclkl : STRING := "Tspiclkl"; +constant Tspiclkh : STRING := "Tspiclkh"; +constant TCOMP : STRING := " tCOMP"; +constant TXFR : STRING := " tXFR"; +constant TPEP : STRING := " tPEP"; +constant TP : STRING := " tP"; +constant TPE : STRING := " tPE"; +constant TSE : STRING := " tSE"; +constant TVCSL : STRING := " tVCSL"; +constant TPUW : STRING := " tPUW"; + +constant Tsck : Time := 15152 ps; -- period of 66 MHz +constant Tsck33 : Time := 30304 ps; --clk_period for 33 MHz +constant Tcs : TIME := 50 ns; -- 50 ns Minimum CSB High Time +signal scaled_flag : boolean; + +procedure validate_input( + SIM_DEVICE : in string; + accuracy : in string; + signal scal_flag : inout boolean + ) is + variable ln : Line; +begin + if (accuracy = "SCALED" ) then + scal_flag <= TRUE; + wait for 1 ps; + elsif (accuracy ="ACCURATE") then + scal_flag <= FALSE; + wait for 1 ps; + else + write(ln, string'(" Attribute Syntax Error : ")); + write(ln, string'(" SIM_DELAY_TYPE ")); + write(ln, string'( " in ")); + write(ln, InstancePath); + write(ln, string'( " The Legal values for this attribute are ACCURATE or SCALED ")); + assert false report ln.all severity failure; + DEALLOCATE (ln); + end if; + if (SIM_DEVICE /= "3S50AN")and(SIM_DEVICE /= "3S200AN")and(SIM_DEVICE /= "3S400AN")and(SIM_DEVICE /= "3S700AN")and(SIM_DEVICE /= "3S1400AN") then + write(ln, string'(" Attribute Syntax Error : The allowed values for SIM_DEVICE in ")); + write(ln, InstancePath); + write(ln, string'(" are 3S50AN, 3S200AN, 3S400AN, 3S700AN or 3S1400AN")); + assert false report ln.all severity failure; + DEALLOCATE (ln); + end if; +end validate_input ; + + + +----------------------Convert integer subroutine ------------------------------------------- +subtype SMALL_INT is INTEGER range 0 to 1; +-- synopsys synthesis_off +type tbl_type is array (STD_ULOGIC) of STD_ULOGIC; +constant tbl_BINARY : tbl_type := +('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X'); +-- synopsys synthesis_on +function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT; +-- attribute foreign of CONV_INTEGER[UNSIGNED return INTEGER]:function is "Conv_Integer_Unsigned"; +function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT is +variable tmp: STD_ULOGIC; +-- synopsys built_in SYN_FEED_THRU +-- synopsys subpgm_id 370 +begin +-- synopsys synthesis_off +tmp := tbl_BINARY(ARG); +if tmp = '1' then + return 1; +else + return 0; +end if; +-- synopsys synthesis_on +end; +----------------------------------------------------------------------------------------------------- + + +function delay_cal (DELAY_NAME : in string(1 to 8); + scaled_flag : in boolean + ) return TIME is +variable delay_time : TIME := 50 ns; +begin + case scaled_flag is + when FALSE => + case DELAY_NAME is + when "Tspiclkl" => delay_time := 6800 ps; + when "Tspiclkh" => delay_time := 6800 ps; + when " tCOMP" => delay_time := 400000 ns; -- 400 us Buffer Compare Time + when " tXFR" => delay_time := 400000 ns; -- 400 us Page to Bufer Xfer UG pg 33,34 + when " tPEP" => delay_time := 40000000 ns; -- 40 ms + when " tP" => delay_time := 6000000 ns; -- 6 ms + when " tPE" => delay_time := 35000000 ns; -- 32 ms + when " tSE" => delay_time := 500000000 ns; -- 5 s divided by 10 since num too large, loop 10x + when " tVCSL" => delay_time := 50 ns; -- 50 us + when " tPUW" => delay_time := 50 ns; -- 20000000 ns; -- 20 ms + when OTHERS => delay_time := 500000000 ns; -- maximum + end case; + when TRUE => -- arbitrary + case DELAY_NAME is + when "Tspiclkl" => delay_time := 6800 ps; + when "Tspiclkh" => delay_time := 6800 ps; + when " tCOMP" => delay_time := 500 ns; -- = tXFR + when " tXFR" => delay_time := 500 ns; -- = tCOMP + when " tPEP" => delay_time := 2500 ns; -- > tPE + tP + when " tP" => delay_time := 1000 ns; -- 2 x tCOMP + when " tPE" => delay_time := 1000 ns; -- 2 x tCOMP + when " tSE" => delay_time := 4000 ns; -- 4 x tPE + when " tVCSL" => delay_time := 50 ns; -- + when " tPUW" => delay_time := 50 ns; -- + when OTHERS => delay_time := 40000 ns; -- 10 x tSE + end case; + end case; + return delay_time; +end delay_cal; + +function device_Sel1 (SIM_DEVICE : in string + ) return std_logic is + variable status3 : std_logic; +begin + if (SIM_DEVICE = "3S50AN") then status3 := '1'; + elsif (SIM_DEVICE = "3S200AN") then status3 := '1'; + elsif (SIM_DEVICE = "3S400AN") then status3 := '1'; + elsif (SIM_DEVICE = "3S700AN") then status3 := '0'; + elsif (SIM_DEVICE = "3S1400AN") then status3 := '1' ; + else status3 := '1'; + end if; +return status3; +end device_sel1; + +function device_Sel2 (SIM_DEVICE : in string + ) return std_logic is + variable status4 : std_logic; +begin + if (SIM_DEVICE = "3S50AN") then status4 := '0'; + elsif (SIM_DEVICE = "3S200AN") then status4 := '1'; + elsif (SIM_DEVICE = "3S400AN") then status4 := '1'; + elsif (SIM_DEVICE = "3S700AN") then status4 := '0'; + elsif (SIM_DEVICE = "3S1400AN") then status4 := '0' ; + else status4 := '0'; + end if; + return status4; +end device_sel2; + +function device_Sel3 (SIM_DEVICE : in string + ) return std_logic is + variable status5 : std_logic; +begin + if (SIM_DEVICE = "3S50AN") then status5 := '0'; + elsif (SIM_DEVICE = "3S200AN") then status5 := '0'; + elsif (SIM_DEVICE = "3S400AN") then status5 := '0'; + elsif (SIM_DEVICE = "3S700AN") then status5 := '1'; + elsif (SIM_DEVICE = "3S1400AN") then status5 := '1' ; + else status5 := '0'; + end if; + return status5; +end device_sel3; + +function page_cal (SIM_DEVICE : in string + ) return integer is + variable pages : integer range 1 to 8192 := 2048; +begin + if (SIM_DEVICE = "3S50AN") then pages := 512; + elsif (SIM_DEVICE = "3S200AN") then pages := 2048; + elsif (SIM_DEVICE = "3S400AN") then pages := 2048; + elsif (SIM_DEVICE = "3S700AN") then pages := 4096; + elsif (SIM_DEVICE = "3S1400AN") then pages := 4096; + else pages := 512; + end if; + return pages; +end page_cal; + +function pageper_sector (SIM_DEVICE : in string + ) return integer is + variable page_per_sector : integer range 1 to 256 :=256; +begin + if (SIM_DEVICE = "3S50AN") then page_per_sector := 128; + elsif (SIM_DEVICE = "3S200AN") then page_per_sector := 256; + elsif (SIM_DEVICE = "3S400AN") then page_per_sector := 256; + elsif (SIM_DEVICE = "3S700AN") then page_per_sector := 256; + elsif (SIM_DEVICE = "3S1400AN") then page_per_sector := 256; + else page_per_sector := 128; + end if; + return page_per_sector; +end pageper_sector; + +function sec_tors (SIM_DEVICE : in string + ) return integer is + variable sectors : integer range 1 to 64 :=8; +begin + if (SIM_DEVICE = "3S50AN") then sectors := 4; + elsif (SIM_DEVICE = "3S200AN") then sectors := 8; + elsif (SIM_DEVICE = "3S400AN") then sectors := 8; + elsif (SIM_DEVICE = "3S700AN") then sectors := 16; + elsif (SIM_DEVICE = "3S1400AN") then sectors := 16; + else sectors := 4; + end if; + return sectors; +end sec_tors; + +function pagesize_forbuffer (SIM_DEVICE : in string + ) return integer is + variable page_size : integer range 1 to 1056 :=264; +begin + if (SIM_DEVICE = "3S50AN") then page_size := 264; + elsif (SIM_DEVICE = "3S200AN") then page_size := 264; + elsif (SIM_DEVICE = "3S400AN") then page_size := 264; + elsif (SIM_DEVICE = "3S700AN") then page_size := 264; + elsif (SIM_DEVICE = "3S1400AN") then page_size := 528; + else page_size := 264; + end if; + return page_size; +end pagesize_forbuffer; + + +function pagesize (SIM_DEVICE : in string; + binary_page : in std_logic +) return integer is +variable page_size : integer range 1 to 1056 :=264; +begin + if (SIM_DEVICE = "3S50AN") then page_size := (264 - (conv_integer(binary_page) * 8)); + elsif (SIM_DEVICE = "3S200AN") then page_size := (264 - (conv_integer(binary_page) * 8)); + elsif (SIM_DEVICE = "3S400AN") then page_size := (264 - (conv_integer(binary_page) * 8)); + elsif (SIM_DEVICE = "3S700AN") then page_size := (264 - (conv_integer(binary_page) * 8)); + elsif (SIM_DEVICE = "3S1400AN") then page_size := (528 - (conv_integer(binary_page) * 16)); + else page_size:= (264 - (conv_integer(binary_page) * 8)); + end if; + return page_size; +end pagesize; + + +function buffers ( + SIM_DEVICE : in string + ) return integer is +variable buf : integer := 2; +begin + if (SIM_DEVICE = "3S50AN") then buf := 1; + elsif (SIM_DEVICE = "3S200AN") then buf := 2; + elsif (SIM_DEVICE = "3S400AN") then buf := 2; + elsif (SIM_DEVICE = "3S700AN") then buf := 2; + elsif (SIM_DEVICE = "3S1400AN") then buf := 2; + else buf := 1; + end if; + return buf; +end buffers; + +function b_address (SIM_DEVICE : in string; + binary_opt : in std_logic + ) return integer is +variable baddress : integer range 1 to 11 := 9; +begin + if (SIM_DEVICE = "3S50AN") then baddress := (9 - (conv_integer(binary_opt) * 1)); + elsif (SIM_DEVICE = "3S200AN") then baddress := (9 - (conv_integer(binary_opt) * 1)); + elsif (SIM_DEVICE = "3S400AN") then baddress := (9 - (conv_integer(binary_opt) * 1)); + elsif (SIM_DEVICE = "3S700AN") then baddress := (9 - (conv_integer(binary_opt) * 1)); + elsif (SIM_DEVICE = "3S1400AN") then baddress := (10 -(conv_integer(binary_opt) * 1)); + else baddress := (9 - (conv_integer(binary_opt) * 1)); + end if; + return baddress; +end b_address; + +function p_address (SIM_DEVICE : in string + ) return integer is +variable paddress : integer range 1 to 14 := 11; +begin + if (SIM_DEVICE = "3S50AN") then paddress := 9; + elsif (SIM_DEVICE = "3S200AN") then paddress := 11; + elsif (SIM_DEVICE = "3S400AN") then paddress := 11; + elsif (SIM_DEVICE = "3S700AN") then paddress := 12; + elsif (SIM_DEVICE = "3S1400AN") then paddress := 12; + else paddress := 9; + end if; + return paddress; +end p_address; + +function s_address (SIM_DEVICE : in string + ) return integer is +variable saddress : integer range 1 to 6 := 3; +begin + if (SIM_DEVICE = "3S50AN") then saddress := 2; + elsif (SIM_DEVICE = "3S200AN") then saddress := 3; + elsif (SIM_DEVICE = "3S400AN") then saddress := 3; + elsif (SIM_DEVICE = "3S700AN") then saddress := 4; + elsif (SIM_DEVICE = "3S1400AN") then saddress := 4; + else saddress := 2; + end if; + return saddress; +end s_address; + +function manid (SIM_DEVICE : in string + ) return std_logic_vector is +variable man_id : std_logic_vector(31 downto 0); +begin + if (SIM_DEVICE = "3S50AN") then man_id := X"1F_22_00_00"; + elsif (SIM_DEVICE = "3S200AN") then man_id := X"1F_24_00_00"; + elsif (SIM_DEVICE = "3S400AN") then man_id := X"1F_24_00_00"; + elsif (SIM_DEVICE = "3S700AN") then man_id := X"1F_25_00_00"; + elsif (SIM_DEVICE = "3S1400AN") then man_id := X"1F_26_00_00"; + else man_id := X"1F_22_01_00"; + end if; + return man_id; +end manid; + + +function memsize (page_size : in integer range 1 to 1056; + pages : in integer range 1 to 8192 + ) return integer is +variable mem_size : integer range 1 to 69206016; +begin + mem_size := page_size * pages; + return mem_size; +end memsize; + +constant binary_page : std_logic :='0'; +signal status2 : std_logic :='1'; +signal status3 : std_logic ; +signal status4 : std_logic ; +signal status5 : std_logic ; + +------------------------------------------------ +signal TsckRp,TsckRpa , TsckRp33, TsckRpx ,TsckFp, TsckRw , TsckF , TcsR , TcsF , Tsckm , Tsim , TsckRh : time := 0 ns ; +signal TsckRpcsb , TsckFcsb : time := 0 ns ; + +signal clk_err: std_logic; +signal clk_err33: std_logic; +signal csb_err: std_logic; +signal clk_erra: std_logic; +signal backgnd_while_busy_err: std_logic; + + +------------- global signal declarations--------- + +signal MMCAR : std_logic; +signal MMPTBT : std_logic; +signal MMPTBC : std_logic; +signal B1W : std_logic; +signal B2W : std_logic; +signal BTMMPP : std_logic; +signal PE : std_logic; +signal SE : std_logic; +signal MMPPB : std_logic; +signal security_flag : std_logic:='0'; +signal tmp_reg1 : std_logic_vector(7 downto 0); +signal tmp_reg2 : std_logic_vector(7 downto 0); +signal buff_num : std_logic_vector(1 downto 0); -- buffer number +signal buff_nump : std_logic_vector(1 downto 0); -- buffer number +signal erase_flag: std_logic; -- Flag for whether command performs erase +signal cmd_name : string(1 to 40) :=" Initialize "; +signal cycle_mode : string(1 to 5) :="idle "; +signal test_33mhz : Boolean := FALSE ; -- flag to on 33 MHz +signal random : Boolean := FALSE; -- flag for random read + +------------------------------------------------------------------------------ +-- Signal ____/------\_______/---- +-- <--------------> +procedure checkclk( + signal TestSignal : in std_logic; + TestSignalName : in string; + expectedDelay : in time; + expectedDelayName : in string; + signal LastSignalRise : inout time; + signal LastSignalFall : inout time; + signal clk_err :inout std_logic; + fullPathName : in string; + signal valid :in Boolean; + signal pos_check :in Boolean; + signal neg_check :in Boolean + ) is + variable ln : Line; + variable per_flag: boolean; + +begin + +if (TestSignal'event ) then + if ((((now - LastSignalRise) < expectedDelay and pos_check )or (now - LastSignalFall < expectedDelay and neg_check)) + and (clk_err /= '1' and (valid = TRUE) and (now > expectedDelay))) then + write(ln, string'("DRC Error : In ")); + write(ln, fullPathName); + write(ln, string'(": '")); + write(ln, string'(TestSignalName)); + write(ln, string'("' high/low time violation at: ")); + write(ln, now); + write(ln, string'(", ")); + write(ln, string'(" signal width: ")); + if (now - LastSignalFall < delay_cal(Tspiclkl,scaled_flag)) then + write(ln, now - LastSignalFall); + else + write(ln, now - LastSignalRise); + end if; + write(ln, string'(" Minimum Width: ")); + write(ln, expectedDelay); + writeline(output, ln); + clk_err <= '1'; + assert false report ln.all severity warning; + DEALLOCATE (ln); + else + clk_err <= '0'; + end if; + if (TestSignal = '1' ) then + LastSignalRise <= now; + else + LastSignalFall <= now; + end if; +end if; +end checkclk; + + +procedure checkPeriod( + signal TestSignal : in std_logic; + TestSignalName : in string; + expectedDelay : in time; + expectedDelayName : in string; + signal LastSignalRise : inout time; + signal clk_err :inout std_logic; + fullPathName : in string; + signal valid :in Boolean + ) is + variable ln : Line; + variable per_flag: boolean; + +begin + +if (TestSignal'event and TestSignal = '1') then + if (now - lastSignalRise < expectedDelay) and ( lastSignalRise /= 0 ns ) and + (now > 0 ns) and (expectedDelay /= 0 ns) and (clk_err /= '1') and (valid = TRUE) then + write(ln, string'("DRC Error : In ")); + write(ln, fullPathName); + write(ln, string'(": '")); + write(ln, string'(TestSignalName)); + write(ln, string'("' Period violation at: ")); + write(ln, now); + write(ln, string'(", ")); + write(ln, string'(expectedDelayName)); + write(ln, string'(" expected: ")); + write(ln, expectedDelay); + write(ln, string'(", ")); + write(ln, string'(expectedDelayName)); + write(ln, string'(" actual: ")); + write(ln, now - lastSignalRise); + writeline(output, ln); + clk_err <= '1'; + assert false report ln.all severity warning; + DEALLOCATE (ln); + end if; + if (now - lastSignalRise > expectedDelay) and ( lastSignalRise /= 0 ns ) and + (now > 0 ns) and (expectedDelay /= 0 ns)then + clk_err <= '0'; + end if; + if (valid = FALSE) then + clk_err <= '0'; + end if; + LastSignalRise <= now; +end if; +end checkPeriod; + +procedure write_busy_message is +variable Message :line; +begin + Write ( Message, string'("DRC Error : In ")); + Write ( Message, InstancePath); + Write ( Message, string'(" access not allowed -- busy")); + assert false report Message.all severity failure; + DEALLOCATE (Message); +end write_busy_message; + + +procedure write_opcode_message is +variable Message :line; +begin + Write ( Message, string'("DRC Error : In ")); + Write ( Message, InstancePath); + Write ( Message, string'(" opcode is not supported in the simulation model")); + assert false report Message.all severity warning; + DEALLOCATE (Message); +end write_opcode_message; + + +procedure write_tpuw_message is +variable Message:line; +begin + Write ( Message, string'("DRC Error : In ")); + Write ( Message, InstancePath); + Write ( Message, string'(" write operations are not allowed before a delay of :")); + Write ( Message, delay_cal(TPUW,scaled_flag) ); + Write ( Message,string'(" ms")); + assert false report Message.all severity failure; + DEALLOCATE (Message); +end write_tpuw_message; +------------------------------------------------------------------- +------------------------------------------------------------------- + FUNCTION integer_to_bit_vector (VAL, width : INTEGER) RETURN BIT_VECTOR IS + VARIABLE result : BIT_VECTOR (width-1 downto 0) := (OTHERS=>'0'); + VARIABLE bits : INTEGER := width; + BEGIN + IF (bits > 31) THEN -- Avoid overflow errors. + bits := 31; + ELSE + ASSERT 2**bits > VAL REPORT + "Value too big FOR BIT_VECTOR width" + SEVERITY WARNING; + END IF; + FOR i IN 0 TO bits - 1 LOOP + IF ((val/(2**i)) MOD 2 = 1) THEN + result(i) := '1'; + END IF; + END LOOP; + RETURN (result); + END integer_to_bit_vector ; + + PROCEDURE removespace(VARIABLE l : IN line; pos : OUT integer) IS + BEGIN + pos := l'low; + FOR i IN l'low TO l'high LOOP + CASE l(i) IS + WHEN ' ' | ht => + pos := i + 1; + WHEN OTHERS => + EXIT; + END CASE; + END LOOP; + END; + PROCEDURE removeline(l : INOUT line; pos : integer) IS + VARIABLE tmpl : line; + BEGIN + tmpl := l; + l := NEW string'(tmpl(pos TO tmpl'high)); + deallocate(tmpl); + END; + PROCEDURE hexa_to_bit_vector(l: INOUT line; u: in integer; value: OUT bit_vector) IS + CONSTANT not_digit : integer := -999; + FUNCTION digit_value(c : character) RETURN integer IS + BEGIN + IF (c >= '0') AND (c <= '9') THEN + RETURN (character'pos(c) - character'pos('0')); + ELSIF (c >= 'a') AND (c <= 'f') THEN + RETURN (character'pos(c) - character'pos('a') + 10); + ELSIF (c >= 'A') AND (c <= 'F') THEN + RETURN (character'pos(c) - character'pos('A') + 10); + ELSE + RETURN not_digit; + END IF; + END; + VARIABLE digit : bit_vector(4 downto 1); + VARIABLE digit1 : bit_vector(u downto 1); + VARIABLE digitx : integer; + VARIABLE pos : integer; + VARIABLE t : integer := u/4; + BEGIN + removespace(l, pos); + FOR i IN pos TO l'right LOOP + digitx := digit_value(l(i)); + EXIT WHEN (digitx = not_digit) OR (digitx >= 16); + digit := integer_to_bit_vector(digitx,4); + if t >= 1 then + digit1 := digit1(u-4 downto 1) & digit; + t := t - 1; + else + end if; + pos := i + 1; + END LOOP; + value := digit1; + removeline(l, pos); + END; + +--******************************************--- +--******************************************-- +signal page : std_logic_vector(p_address(SIM_DEVICE)-1 downto 0) := (others=> '0'); +--signal temp_reg2 : std_logic_vector(7 downto 0); +--signal temp_page : std_logic_vector(p_address(SIM_DEVICE)-1 downto 0); +signal byte : integer; +---protected/locked status reg----- +signal sector : std_logic_vector(s_address(SIM_DEVICE)-1 downto 0); +type buffer1 is array(pagesize_forbuffer(SIM_DEVICE)-1 downto 0) of std_logic_vector(7 downto 0); +type buffer2 is array(pagesize_forbuffer(SIM_DEVICE)-1 downto 0) of std_logic_vector(7 downto 0); +--memory initalization-- +constant N : integer range 1 to 69206016 := memsize(pagesize_forbuffer(SIM_DEVICE),page_cal(SIM_DEVICE)); +constant M : integer := 8; +type memtype is array(N-1 downto 0) of std_logic_vector(7 downto 0); +constant p : integer := sec_tors(SIM_DEVICE); +type factory_type is array(63 downto 0 ) of std_logic_vector(7 downto 0); +signal factory_reg : factory_type; + +--security reg-- +type security_type is array(63 downto 0) of std_logic_vector(7 downto 0); +signal security_reg : security_type; + +--------------comp page address function implementation--------------- +function comp_page_addr ( paddress : in integer range 1 to 14; + binary_page : in std_logic; + page_addr0 : in std_logic_vector( 7 downto 0); + page_addr1 : in std_logic_vector( 7 downto 0); + man_id : in std_logic_vector(31 downto 0) + ) return std_logic_vector is +variable page1 : std_logic_vector((P_ADDRESS(SIM_DEVICE))-1 DOWNTO 0); +begin + case(PADDRESS) is + when 12=> + ---16mb---- + if (MAN_ID = X"1F260000") then + if (binary_page = '1') then + page1 := page_addr0(4 downto 0) & page_addr1(7 downto 1); + else + page1 := page_addr0(5 downto 0) & page_addr1(7 downto 2); + end if; + end if; + --8mb-- + if (MAN_ID = X"1F250000") then + if (binary_page = '1') then + page1 := page_addr0(3 downto 0) & page_addr1(7 downto 0); + else + page1 := page_addr0(4 downto 0) & page_addr1(7 downto 1); + end if; + end if; + ---4 mb--- + when 11=> + if (binary_page = '1') then + page1 := page_addr0(2 downto 0) & page_addr1(7 downto 0); + else + page1 := page_addr0(3 downto 0) & page_addr1(7 downto 1); + end if; + --1mb--- + when 9=> + if (binary_page ='1') then + page1 := page_addr0(0) & page_addr1(7 downto 0); + else + page1 := page_addr0(1 downto 0) & page_addr1(7 downto 1); + end if; + when others => + end case; + return page1; +end comp_page_addr; + + +---------------------------- +function comp_byte_addr + (baddress : integer range 1 to 11 ; + signal page_addr1 : in std_logic_vector( 7 downto 0); + signal byte_addr : in std_logic_vector( 7 downto 0); + binary_opt : in std_logic + ) return integer is +variable byte_ad : integer;-- range 1 to 11 := 8; +begin + case(baddress)is + when 11 => byte_ad := conv_integer(page_addr1(2 downto 0) & byte_addr) ; + when 10 => byte_ad := conv_integer(page_addr1(1 downto 0) & byte_addr) ; + when 9 => byte_ad := conv_integer(page_addr1(0) & byte_addr) ; + when others=> byte_ad := conv_integer(byte_addr) ; + end case; + return byte_ad; +end comp_byte_addr; + + +procedure compute_address ( + page : in std_logic_vector((P_ADDRESS(SIM_DEVICE))-1 DOWNTO 0); + page_size : in integer range 1 to 1056; + byte : in integer; + page_boundary_low : out integer; + page_boundary_high : out integer; + current_address : out integer; + mem_no : out integer; + binary_page : in std_logic +) is +variable temp_low : integer ; +begin + temp_low := (conv_integer(page) * pagesize(SIM_DEVICE,binary_page)); + page_boundary_low := temp_low; + page_boundary_high := temp_low + (pagesize(SIM_DEVICE,binary_page) - 1); + current_address := temp_low + byte; + --memno 10 is for memory access--- + mem_no := 10; +end compute_address; + + +procedure read_out_array + (signal CLK,CSB : in std_logic; + page_size : in integer range 1 to 1056; + mem_size : in integer range 1 to 69206016; + page_boundary_low : in integer; + page_boundary_high :in integer; + current_address : in integer; + memory : in memtype; + signal so_reg : out std_logic; + binary_page : in std_logic; + signal so_on1 : out std_logic + ) + is +variable temp_reg1 : std_logic_vector(7 downto 0); +variable temp_high : integer; +variable temp_low : integer; +variable temp_add : integer; +begin + temp_high := page_boundary_high; + temp_low := page_boundary_low; + temp_add := current_address; + temp_reg1 := memory(temp_add); + read_array_loop : loop + for i in 7 downto 0 loop + wait until (CLK'EVENT and CLK ='0') or (CSB'EVENT and CSB='1'); + exit read_array_loop when (CSB='1' ) ; + SO_reg <= temp_reg1(i); + so_on1 <= '1'; + end loop; + temp_add := temp_add + 1; + if (temp_add >= N)then -- N = size of memory + temp_add := 0; --Note that rollover occurs at end of memory, + temp_high := pagesize(SIM_DEVICE,binary_page) - 1; -- and not at the end of the page + temp_low := 0; + end if; + if (temp_add > temp_high) then-- going to next page + temp_high := temp_high + pagesize(SIM_DEVICE,binary_page); + temp_low := temp_low + pagesize(SIM_DEVICE,binary_page); + end if; + temp_reg1 := memory(temp_add); + end loop; + SO_reg <= '0'; + so_on1 <= '0'; +end read_out_array; + + +procedure transfer_to_buffer + ( + buf_type : in std_logic_vector(1 downto 0); + page_boundary_low : in integer; + memory : in memtype; + buf1 : inout buffer1; + binary_page : in std_logic; + buf2 : inout buffer2 + ) is +begin +if (buf_type = "01") then + for i in 0 to pagesize(SIM_DEVICE,binary_page)-1 LOOP + buf1(i) := memory(page_boundary_low + i); + end loop; + elsif (buf_type = "10") then + for i in 0 to pagesize(SIM_DEVICE,binary_page)-1 loop + buf2(i) := memory(page_boundary_low + i); + end loop; +end if; +end transfer_to_buffer; + + +procedure compare_with_buffer +( + buf_type : in std_logic_vector(1 downto 0); + page_boundary_low : in integer; + memory : in memtype; + buf1 : in buffer1; + buf2 : in buffer2; + binary_page : in std_logic; + signal status : out std_logic +) is +variable tmp1,tmp2 : std_logic_vector(7 downto 0); +begin + status <='0'; + if(buf_type = "01")then + for i in 0 to pagesize(SIM_DEVICE,binary_page)-1 loop + tmp1 := memory(page_boundary_low + i); + tmp2 := buf1(i); + for k in 0 to 7 loop + if(tmp1(k) /= tmp2(k) ) then + status <= '1'; + exit; + end if; + end loop; + end loop; + elsif (buf_type = "10") then + for i in 0 to pagesize(SIM_DEVICE,binary_page)-1 loop + tmp1 := memory(page_boundary_low + i); + tmp2 := buf2(i); + for k in 0 to 7 loop + if(tmp1(k) /= tmp2(k) ) then + status <= '1'; + exit; + end if; + end loop; + end loop; + end if; +end compare_with_buffer; + + +-----------write_data------------ +procedure write_data + ( current_address : inout integer; + page_boundary_low : in integer; + page_boundary_high : in integer; + buf1 : inout buffer1; + buf2 : inout buffer2; + buf_type : in std_logic_vector(1 downto 0); + signal CSB,CLK,MOSI : in std_logic + ) is +variable buf_temp_reg : std_logic_vector(7 downto 0); +variable temp :std_logic := '0'; +begin + write_loop : loop + for i in 7 downto 0 loop + wait until (CLK'EVENT and CLK ='1') or (CSB'EVENT and CSB='1'); + if (CSB='1') then + exit write_loop; + end if; + buf_temp_reg(i):=MOSI; + end loop; + if (buf_type="01") then + buf1(current_address):= buf_temp_reg; + elsif(buf_type="10") then + buf2(current_address):= buf_temp_reg; + end if; + current_address := current_address + 1; + wait for 1 ps; + if (current_address > page_boundary_high) then + current_address := page_boundary_low; + wait for 1 ps; + end if; + end loop; +end write_data; + + +procedure write_to_memory + ( + buf_type : in std_logic_vector(1 downto 0); + page : in std_logic_vector((P_ADDRESS(SIM_DEVICE))-1 DOWNTO 0); + page_size : in integer range 1 to 1056; + buf1 : in buffer1; + buf2 : in buffer2; + + page_boundary_low : in integer; + memory : inout memtype + ) is +begin +if (buf_type = "01") then + for i in 0 to page_size-1 loop + memory(page_boundary_low+i) := buf1(i); + end loop; + elsif (buf_type = "10") then + for i in 0 to page_size-1 loop + memory(page_boundary_low+i) := buf2(i); + end loop; +end if; +end write_to_memory; + + +procedure erase_page + ( + page : in std_logic_vector((P_ADDRESS(SIM_DEVICE))-1 DOWNTO 0); + page_size : in integer range 1 to 1056; + page_boundary_low : in integer; + memory : inout memtype; + binary_page : in std_logic; + page_status : out std_logic + ) is +variable buf1 : buffer1; +variable buf2 : buffer2; +begin +for i in 0 to pagesize(SIM_DEVICE,binary_page)-1 loop + memory(page_boundary_low + i ) := X"FF"; + page_status :='0'; +end loop; +end erase_page; + + +----------read_out_reg-------- +procedure read_out_reg + ( reg_type : in integer; + add : in integer; + high : in integer; + security_reg : in security_type ; + signal CSB,CLK : in std_logic; + signal so_reg : out std_logic; + signal so_on1 : out std_logic + ) is +variable temp_add : integer; +variable t_reg1 : std_logic_vector(7 downto 0); +begin + temp_add := add; + t_reg1 := security_reg(temp_add); + read_out_reg_loop : loop + for i in 7 downto 0 loop + wait until (CLK'EVENT and CLK ='0') or (CSB'EVENT and CSB='1'); + exit read_out_reg_loop when (CSB='1' ) ; + so_reg <= t_reg1(i); + so_on1 <= '1'; + end loop; + temp_add := temp_add + 1; + if ( temp_add > high)then + t_reg1 := (others => 'X' ); + else + if (reg_type=23) then + if (temp_add < 64) then + t_reg1 := security_reg(temp_add); + else + t_reg1 := factory_reg(temp_add-64); + end if; + end if; + end if; + end loop; + so_reg <= '1'; + so_on1 <= '0'; +end read_out_reg; + + +function getbyte ( + IP : in bit_vector(511 downto 0); + byte_num : in integer + ) return bit_vector is + +variable temp : bit_vector( 7 downto 0); +begin + + for i in 0 to 7 loop + temp(i) := IP((byte_num-1)*8+i); + end loop; +return temp; + +end getbyte; + +procedure read_mem_file ( + --signal memory : inout memtype; + memory : inout memtype; + inbuf : inout line + )is + file LOAD_FILE1 : text open read_mode is SIM_MEM_FILE; + variable numword : integer := 0; + variable value : bit_vector(7 downto 0); +begin + if(SIM_MEM_FILE /= "NONE")then + while not ENDFILE(LOAD_FILE1) loop + READLINE(LOAD_FILE1,inbuf); + hexa_to_bit_vector(inbuf, 8, value); + memory(numword) := to_stdlogicvector(value); + numword := numword + 1; + if(numword = (N-1)) then + exit; + end if; + end loop; + end if; +end read_mem_file; + +--******************************************--- +--******************************************-- +signal temp_reg1 : std_logic_vector(7 downto 0); +signal reset_sig : std_logic:= '0'; +signal skip : std_logic := '1'; +signal skip_be : std_logic := '0'; +signal skip_end : std_logic := '0'; +signal opcode_temp : std_logic_vector(7 downto 0) := "00000000"; +signal page_addr0 : std_logic_vector(7 downto 0) := "00000000"; +signal page_addr1 : std_logic_vector(7 downto 0) := "00000000"; +signal byte_addr : std_logic_vector(7 downto 0) := "00000000"; +signal t : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; +signal rd_data1 : std_logic_vector(7 downto 0); +signal arr_rd_dummybyte : integer := 0; +signal buff_rd_dummybyte : integer:= 0; + +signal valid : Boolean := TRUE; +signal no_test : Boolean := FALSE; +signal MIR : std_logic :='0'; +signal SRR : std_logic:='0'; +signal SRP : std_logic:='0'; +signal err_flg : std_logic:='0'; +signal mem_initialized : std_logic; +signal deep_power_down : std_logic := '0'; +signal SR : std_logic:= '0'; +signal RDYBSY_reg : std_logic :='1'; +signal foreground_op_enable : std_logic :='0'; +signal background_op_enable : std_logic:='0'; +signal status_read : std_logic :='0'; +signal so_reg : std_logic := '1'; +signal so_on : std_logic :='0'; +signal so_reg1 : std_logic := '1'; +signal so_on1 : std_logic :='0'; +signal so_reg2 : std_logic := '1'; +signal so_on2 : std_logic :='0'; +signal so_reg3 : std_logic := '1'; +signal so_on3 : std_logic :='0'; +signal status : std_logic_vector(7 downto 0):= ('1' & '0' & Device_sel3(SIM_DEVICE) & Device_sel2(SIM_DEVICE) & Device_sel1(SIM_DEVICE)& '1' & '0' & '0'); + +-----------status signal------------- + +signal status_B1C_s6 : std_logic; +signal status_B2C_s6 : std_logic; + + + signal MISO_zd : std_ulogic := '1'; + + signal CLK_ipd : std_ulogic := '0'; + signal CSB_ipd : std_ulogic := '0'; + signal MOSI_ipd : std_ulogic := '0'; + + signal CLK_dly : std_ulogic := 'X'; + signal CSB_dly : std_ulogic := 'X'; + signal csbx : std_ulogic := 'X'; + + signal MOSI_dly : std_ulogic := '0'; + signal Violation : std_ulogic := '0'; + +--**************** begin of Architecture **************--- + + +begin + + --------------------- + -- INPUT PATH DELAYs + -------------------- + + prcs_input:process(MOSI,CSB,CLK) + begin + MOSI_dly <= MOSI ; + CSB_dly <= CSB ; + CLK_dly <= CLK ; + end process prcs_input; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--comparing the opcodes-- +process(CLK_dly,MOSI_dly,CSB_dly) +begin + if ( CSB_dly ='1') then + t <="00000000000000000000000000000000"; + rd_data1 <= "00000000"; + elsif(CLK_dly = '1' and CLK_dly'event) then + t(0) <= '1'; + t(1) <= t(0); + t(2) <= t(1); + t(3) <= t(2); + t(4) <= t(3); + t(5) <= t(4); + t(6) <= t(5); + t(7) <= t(6); -- t(6) == 1 and t(7) ==0 opcode + t(8) <= t(7); + t(9) <= t(8); + t(10) <= t(9); + t(11) <= t(10); + t(12) <= t(11); + t(13) <= t(12); + t(14) <= t(13); + t(15) <= t(14); -- t(14) == 1 and t(15) ==0 page address + t(16) <= t(15); + t(17) <= t(16); + t(18) <= t(17); + t(19) <= t(18); + t(20) <= t(19); + t(21) <= t(20); + t(22) <= t(21); + t(23) <= t(22); -- t(22) == 1 and t(23) ==0 page address + t(24) <= t(23); + t(25) <= t(24); + t(26) <= t(25); + t(27) <= t(26); + t(28) <= t(27); + t(29) <= t(28); + t(30) <= t(29); + t(31) <= t(30); -- t(30) == 1 and t(31) == 0 byte address + rd_data1(0) <= MOSI_dly; + rd_data1(1) <= rd_data1(0); + rd_data1(2) <= rd_data1(1); + rd_data1(3) <= rd_data1(2); + rd_data1(4) <= rd_data1(3); + rd_data1(5) <= rd_data1(4); + rd_data1(6) <= rd_data1(5); + rd_data1(7) <= rd_data1(6); + + end if; +end process ; + +opcode_temp <= rd_data1(6) & rd_data1(5) & rd_data1(4) & rd_data1(3) & rd_data1(2) & rd_data1(1) & rd_data1(0) & MOSI_dly ; +process(CLK_dly,opcode_temp, t) +begin + if (CSB_dly = '1' ) then + page_addr0 <= "00000000"; + page_addr1 <= "00000000"; + byte_addr <= "00000000"; + + elsif ((CLK_dly = '1' and CLK_dly'event)) then + if (t(14) = '1' and t(15) = '0') then + page_addr0 <= opcode_temp; + end if; + if (t(22) = '1' and t(23) = '0') then + page_addr1 <= opcode_temp; + end if; + if (t(30) = '1' and t(31) = '0') then + byte_addr <= opcode_temp; + end if; + end if; +end process; + + +process(CLK_dly,opcode_temp, t) +variable opcode_message : string(1 to 52); +variable Message : line; +begin + if (CSB_dly = '1' ) then + skip <='1'; + arr_rd_dummybyte <= 0; --not used in their code + buff_rd_dummybyte <= 0; + MMCAR <='0'; + MMPTBT <='0'; --Main Memory Page To Buffer 1 Transfer + MMPTBC <='0';--Main Memory Page To Buffer 1 Compare + B1W <='0'; -- Buffer 1 Write + B2W <='0'; + BTMMPP <= '0' ;--Buffer 1 To Main Memory Page Prog With Built-In Erase + PE<='0'; -- Page Erase + SE <='0'; -- Sector Erase + MMPPB<='0'; -- Main Memory Page Prog. Through Buffer 1 + SR<='0' ; -- Status Register Read + MIR<='0'; -- Manufecturing ID Read + SRR<='0'; -- Security Register Read + SRP<='0'; -- Secturity Register Program + backgnd_while_busy_err<='0'; + elsif (CLK_dly = '1' and CLK_dly'event) then + if (t(6) = '1' and t(7) = '0' ) then + if(foreground_op_enable='0')then + Write ( Message, string'("DRC Error : In ")); + Write ( Message, InstancePath); + Write ( Message, string'(" No opcode is allowed. ")); + Write ( Message, delay_cal(TVCSL,scaled_flag) ); + Write ( Message, string'( "delay is required before device can be selected")); + assert false report Message.all severity warning; + DEALLOCATE (Message); + elsif(cycle_mode="MODE0")then + Write ( Message, string'("DRC Error : In ")); + Write ( Message, InstancePath); + Write ( Message, string'( " must drive CSB LOW while CLK is HIGH.")); + assert false report Message.all severity failure; + DEALLOCATE (Message); + else + case opcode_temp is + when X"03" => + cmd_name <="Random Read "; + random <= TRUE; + if(RDYBSY_reg='0')then + backgnd_while_busy_err<='1'; + write_busy_message; + else + skip <='0'; + arr_rd_dummybyte <= 0; + MMCAR <='1'; + end if; + when X"0B" => + cmd_name<="Main Memory Continuous Array Read "; + random <= FALSE; + if(RDYBSY_reg='0')then + backgnd_while_busy_err<='1'; + write_busy_message; + else + skip <='0'; + arr_rd_dummybyte <= 1; + MMCAR <='1'; + end if; + when X"53" => + cmd_name<="Main Memory Page To Buffer 1 Transfer "; + if(background_op_enable='0') then + write_tpuw_message; + elsif(RDYBSY_reg='0')then + backgnd_while_busy_err<='1'; + write_busy_message; + else + buff_num <= "01"; -- buffer 1 + MMPTBT <='1'; --Main Memory Page To Buffer 1 Transfer + end if; + when X"55" => + cmd_name<="Main Memory Page To Buffer Transfer "; + if(buffers(SIM_DEVICE) = 1 )then + write_opcode_message; + elsif(background_op_enable='0') then + write_tpuw_message; + elsif(RDYBSY_reg='0')then + backgnd_while_busy_err<='1'; + write_busy_message; + else + buff_num <= "10"; --buffer 2 + MMPTBT<='1'; --Main Memory Page To Buffer 2 Transfer + end if; + when X"60" => + cmd_name<="Main Memory Page To Buffer 1 Compare "; + if(background_op_enable='0') then + write_tpuw_message; + elsif(RDYBSY_reg='0')then + backgnd_while_busy_err<='1'; + write_busy_message; + else + buff_num <= "01"; -- buffer 1 + MMPTBC <='1';--Main Memory Page To Buffer Compare + end if; + when X"61" => + cmd_name<="Main Memory Page To Buffer 2 Compare "; + if(buffers(SIM_DEVICE) = 1 )then + write_opcode_message; + elsif(background_op_enable='0') then + write_tpuw_message; + elsif(RDYBSY_reg='0')then + backgnd_while_busy_err<='1'; + write_busy_message; + else + buff_num <= "10"; --buffer 2 + MMPTBC <='1';--Main Memory Page To Buffer Compare + end if; + when X"84" => + cmd_name <= "Buffer 1 Write "; + buff_num<= "01"; -- use buffer 1 + B1W <='1'; -- Buffer 1 Write + when X"87" => + cmd_name<="Buffer 2 Write "; + if(buffers(SIM_DEVICE) = 1 )then + write_opcode_message; + else + buff_num<= "10"; -- use buffer 2 + B2W <='1'; -- Buffer 2 Write + end if; + when X"83" => + cmd_name <="Buffer 1 To Main Memory Page Prog Erase "; + if(background_op_enable='0') then + write_tpuw_message; + elsif(RDYBSY_reg='0')then + backgnd_while_busy_err<='1'; + write_busy_message; + else + erase_flag <= '1'; + buff_nump<= "01"; -- use buffer 1 + BTMMPP <= '1' ;--Buffer 1 To Main Memory Page Prog With Built-In Erase + end if; + when X"86" => + cmd_name <="Buffer 2 To Main Memory Page Prog Erase "; + if(buffers(SIM_DEVICE) = 1 )then + write_opcode_message; + elsif(background_op_enable='0') then + write_tpuw_message; + elsif(RDYBSY_reg='0')then + backgnd_while_busy_err<='1'; + write_busy_message; + else + erase_flag <= '1'; + buff_nump<= "10"; -- use buffer 2 + BTMMPP <= '1';-- t(14) == 1 and t(15) ==0 page address --Buffer 2 To + -- Main Memory Page Prog With Built-In Erase + end if; + when X"88" => + cmd_name <="Buffer 1 To Main Memory Page Prog "; + if(background_op_enable='0') then + write_tpuw_message; + elsif(RDYBSY_reg='0')then + backgnd_while_busy_err<='1'; + write_busy_message; + else + erase_flag <= '0'; + buff_nump<= "01"; -- use buffer 1 + BTMMPP<='1';--- t(14) == 1 and t(15) ==0 page address -Buffer 1 To + --Main Memory Page Prog Without Built-In Erase + end if; + when X"89" => + cmd_name <="Buffer 2 To Main Memory Page Prog "; + if(buffers(SIM_DEVICE) = 1 )then + write_opcode_message; + elsif(background_op_enable='0') then + write_tpuw_message; + elsif(RDYBSY_reg='0')then + backgnd_while_busy_err<='1'; + write_busy_message; + else + erase_flag <= '0'; + buff_nump<= "10"; -- use buffer 2 + BTMMPP<='1' ;--Buffer 2 To Main Memory Page Prog Without Built-In Erase + end if; + when X"81" => + cmd_name <="Page Erase "; + if(background_op_enable='0') then + write_tpuw_message; + elsif(RDYBSY_reg='0')then + backgnd_while_busy_err<='1'; + write_busy_message; + else + PE<='1'; -- Page Erase + end if; + when X"82" => + cmd_name <="Main Memory Page Prog. Through Buffer 1 "; + if(background_op_enable='0') then + write_tpuw_message; + elsif(RDYBSY_reg='0')then + backgnd_while_busy_err<='1'; + write_busy_message; + else + buff_num <= "01"; + MMPPB<='1'; -- Main Memory Page Prog. Through Buffer 1 + end if; + when X"7C" => + cmd_name <="Sector Erase "; + if(background_op_enable='0') then + write_tpuw_message; + elsif(RDYBSY_reg='0')then + backgnd_while_busy_err<='1'; + write_busy_message; + else + SE <='1'; -- Sector Erase + end if; + when X"85" => + cmd_name <="Main Memory Page Prog. Through Buffer 2 "; + if(buffers(SIM_DEVICE) = 1 )then + write_opcode_message; + elsif(background_op_enable='0') then + write_tpuw_message; + elsif(RDYBSY_reg='0')then + backgnd_while_busy_err<='1'; + write_busy_message; + else + buff_num <= "10"; + MMPPB<='1' ; -- Main Memory Page Prog. Through Buffer 2 + end if; + when X"D7" => + cmd_name <="Status Register Read "; + skip <='0'; + SR<='1'; -- Status Register Read + when X"9F" => + cmd_name <="Manufacturer ID Read "; + skip <='0'; + MIR<='1'; -- Manufacturing ID Read + when X"9B" => + cmd_name <="Security Register Program "; + if(background_op_enable='0') then + write_tpuw_message; + elsif(RDYBSY_reg='0')then + backgnd_while_busy_err<='1'; + write_busy_message; + else + SRP<='1'; -- 4-Byte Opcode Starting From 9B this is for Security register program + end if; + when X"77" => + cmd_name <="Security Register Read "; + if(RDYBSY_reg='0')then + backgnd_while_busy_err<='1'; + write_busy_message; + else + SRR<='1'; -- Security Register Read + end if; + when others => + if (opcode_temp=X"D2" or opcode_temp=X"E8" or opcode_temp=X"D4" or opcode_temp=X"D6" or + opcode_temp=X"D1" or opcode_temp=X"D3" or opcode_temp=X"54" or opcode_temp=X"56" or + opcode_temp=X"52" or opcode_temp=X"59" or opcode_temp=X"68" or opcode_temp=X"50" or + opcode_temp=X"B9" or opcode_temp=X"AB" or opcode_temp=X"3D" or opcode_temp=X"80" or + opcode_temp=X"A6" or opcode_temp=X"58" or opcode_temp=X"30" or opcode_temp=X"35" or + opcode_temp=X"9A" or opcode_temp=X"32" ) then + write_opcode_message; + else + Write ( Message, string'("DRC Error : In ")); + Write ( Message, InstancePath); + Write ( Message, string'(" opcode is not recognized ")); + assert false report Message.all severity failure; + DEALLOCATE (Message); + end if; + end case; + end if; + end if; + end if; +end process; + +------------------------------------------------------------------------------------- +----------------------------------------Main Process -------------------------------- +process(CLK_dly,CSB_dly) +begin + if(CSB_dly='0' and CSB_dly'event)then + if (CLK_dly = '0') then + skip_be <= '1'; + cycle_mode <= "MODE0"; + else + skip_be <= '0'; + cycle_mode <= "MODE3"; + end if; + elsif(CSB_dly='1') then + cycle_mode <= "idle "; + end if; +end process ; +skip_end <= skip_be and skip; +background_op_enable <= '1' after delay_cal(TPUW,scaled_flag) ; +reset_sig <= '0', '1' after 1 ns; +process +variable tbuffer1 : buffer1; +variable tbuffer2 : buffer2; +variable inbuf : line; +variable word : string(1 to 8); +variable i : integer; +---------- +variable inbuf1 : line; +variable numword1 : integer := 0; +variable value1 : bit_vector(7 downto 0); + +variable jerase : integer; + --------------- +variable inbuf2 : line; +variable outbuf12 : line; +variable numword2 : integer := 0; +variable value2 : bit_vector(7 downto 0); +--------------------- +variable inbuf3 : line; +variable numword3 : integer := 0; +variable value3 : bit_vector(7 downto 0); +------------------ +variable MMPPB_mem_page : std_logic_vector(p_address(SIM_DEVICE)-1 downto 0); +variable MMPPB_buf_page : std_logic_vector(p_address(SIM_DEVICE)-1 downto 0); +variable buf_temp_reg1 : std_logic_vector(7 downto 0); +variable message1 : string(1 to 45); +variable message2 : string(1 to 30); +variable current_address : integer; +variable page_boundary_low : integer := 0; +variable page_boundary_high : integer; +variable mem_no : integer; +variable memory : memtype; +-- variable security_reg : security_type; + +-- variable binary_page : std_logic; +variable never_set : std_logic := '0'; +variable temp_page_status : std_logic; +variable buffer_number : integer; +variable page_status : std_logic_vector(page_cal(SIM_DEVICE)-1 downto 0); +variable Message : line; +variable value_fact : bit_vector(511 downto 0); +variable value_user : bit_vector(511 downto 0); + +begin + +if (foreground_op_enable = '0') then ---- Enable foreground op_codes +wait on reset_sig ; +wait for 1 ps; +for i in 0 to (memsize(pagesize(SIM_DEVICE,binary_page),page_cal(SIM_DEVICE))-1) loop +memory(i) := (others=>'1'); +end loop; + +mem_initialized <= '0'; +wait for 1 ps; +If(SIM_MEM_FILE /= "NONE") then + read_mem_file(memory,inbuf); +mem_initialized <= '1'; +end if; +wait for 1 ps; +if (mem_initialized = '1') then + for j in 0 to page_cal(SIM_DEVICE)-1 loop + page_status(j) := '1'; -- memory was initialized, so, Pages are Not Erased. + end loop; + else + for j in 0 to page_cal(SIM_DEVICE)-1 loop + page_status(j) := '0'; + end loop; + +end if; +wait for 1 ps; + +---------------initialization of factory reg------------ + +wait for 1 ps; +--hexa_to_bit_vector(SIM_FACTORY_ID, 512, value_fact); +--hexa_to_bit_vector(SIM_USER_ID, 512, value_user); +for j in 0 to 63 loop +-- factory_reg(j) <= To_stdlogicvector(getbyte(to_bitvector(SIM_FACTORY_ID),j+1)); +-- security_reg(j) <= To_stdlogicvector(getbyte(to_bitvector(SIM_USER_ID),j+1)); + factory_reg(j) <= To_stdlogicvector(getbyte(SIM_FACTORY_ID,j+1)); + security_reg(j) <= To_stdlogicvector(getbyte(SIM_USER_ID,j+1)); + wait for 1 ps; + security_flag <='0'; + if(security_reg(j) /= X"FF")then + security_flag <= '1'; + end if; +end loop; + +wait for 1 ps; + + +--************************** +--wait for delay_cal(TVCSL,scaled_flag); +foreground_op_enable <= '1' ; ---- Enable foreground op_codes +end if; +--************************** + + wait on t(31); +if(MMCAR='1' and t(31) = '1')then + if (random=TRUE) then + test_33mhz <= TRUE; + wait for 1 ps; + end if; + compute_address(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),pagesize(SIM_DEVICE,binary_page), + comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr,binary_page), + page_boundary_low,page_boundary_high,current_address,mem_no,binary_page); + if (arr_rd_dummybyte = 1) then + for j in 1 to 8 loop + wait until CLK_dly'event and CLK_dly ='1'; + end loop; + end if; + read_out_array(CLK_dly,CSB_dly,pagesize(SIM_DEVICE,binary_page),memsize(pagesize(SIM_DEVICE,binary_page),page_cal(SIM_DEVICE)),page_boundary_low, + page_boundary_high,current_address,memory,so_reg,binary_page,so_on); + test_33mhz <= FALSE ; -- leave the test on long enough to capture an error + wait for 1 ps; +elsif(MMPTBT='1'and t(31) = '1')then + test_33mhz <= TRUE; -- test for 33 Mhz + compute_address(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),pagesize(SIM_DEVICE,binary_page), + comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr,binary_page),page_boundary_low, + page_boundary_high, current_address,mem_no,binary_page); + if (CSB_dly ='0')then + wait until CSB_dly'event and CSB_dly ='1'; + end if; + RDYBSY_reg <= '0'; --SIM_DEVICE is busy + status(7) <= '0'; + transfer_to_buffer(buff_num, page_boundary_low,memory,tbuffer1,binary_page,tbuffer2); + wait for 1 ps; + RDYBSY_reg <= '1' after delay_cal(TXFR,scaled_flag); + status(7) <= '1' after delay_cal(TXFR,scaled_flag); + test_33mhz <= FALSE after delay_cal(TXFR,scaled_flag) ; + wait for 1 ps; +elsif(MMPTBC='1' and t(31) = '1')then + compute_address(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),pagesize(SIM_DEVICE,binary_page), + comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr,binary_page), + page_boundary_low,page_boundary_high, current_address,mem_no,binary_page); + if (CSB_dly ='0')then + wait until CSB_dly'event and CSB_dly = '1'; + end if; + RDYBSY_reg <= '0'; --device is busy + status(7) <= '0'; + wait for 1 ps; --assignments won't take hold without a delay + compare_with_buffer(buff_num,page_boundary_low,memory,tbuffer1,tbuffer2,binary_page,status_B1C_s6); + wait for 1 ps; + RDYBSY_reg <= '1'after delay_cal(TCOMP,scaled_flag); -- device is now ready + status(7) <= '1' after delay_cal(TCOMP,scaled_flag); + status(6) <= status_B1C_s6 after delay_cal(TCOMP,scaled_flag); + wait for 1 ps; +elsif(B1W='1' and t(31) = '1')then + byte <= comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr,binary_page); + compute_address(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),pagesize(SIM_DEVICE,binary_page), + comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr,binary_page), + page_boundary_low,page_boundary_high, current_address,mem_no,binary_page); + write_data(current_address,page_boundary_low,page_boundary_high,tbuffer1,tbuffer2,"01",CSB_dly,CLK_dly,MOSI_dly); +elsif(B2W='1' and t(31) = '1')then + byte <= comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr,binary_page); + compute_address(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),pagesize(SIM_DEVICE,binary_page), + comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr,binary_page), + page_boundary_low,page_boundary_high, current_address,mem_no,binary_page); + write_data(current_address,page_boundary_low,page_boundary_high,tbuffer1,tbuffer2,"10",CSB_dly,CLK_dly,MOSI_dly); +elsif(BTMMPP='1'and t(31) = '1')then + compute_address(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),pagesize(SIM_DEVICE,binary_page), + comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr,binary_page), + page_boundary_low,page_boundary_high, current_address,mem_no,binary_page); + if (CSB_dly ='0')then + wait until CSB_dly'event and CSB_dly ='1'; + end if; + RDYBSY_reg <= '0'; -- device is busy + status(7) <= '0'; + write_to_memory(buff_nump,comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)), + pagesize(SIM_DEVICE,binary_page),tbuffer1,tbuffer2,page_boundary_low,memory); + if (erase_flag = '0') then + if (page_status(conv_integer(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0, + page_addr1,manid(SIM_DEVICE)))) = '1') then --page is not erased + Write ( Message, string'("DRC Error : In ")); + Write ( Message, InstancePath); + Write ( Message, string'(" trying to write into a Page which is not erased")); + assert false report Message.all severity failure; + DEALLOCATE (Message); + end if; + wait for 1 ps; + RDYBSY_reg <= '1' after delay_cal(TP,scaled_flag); -- device is now ready + status(7) <= '1' after delay_cal(TP,scaled_flag); + wait for 1 ps; + else + page_status(conv_integer(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)))) := '1'; + wait for 1 ps; + RDYBSY_reg <= '1' after delay_cal(TPEP,scaled_flag) ; -- device is now ready + status(7) <= '1' after delay_cal(TPEP,scaled_flag) ; + wait for 1 ps; + end if; +elsif(MMPPB='1' and t(31)='1' and RDYBSY_reg='1')then + MMPPB_mem_page := comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)); + -- page value has been stored for main memory page program + MMPPB_buf_page := (others=>'0');--buffer has zero pages + compute_address(MMPPB_buf_page,pagesize(SIM_DEVICE,binary_page),comp_byte_addr(b_address(SIM_DEVICE,binary_opt), + page_addr1,byte_addr,binary_page),page_boundary_low,page_boundary_high,current_address,mem_no,binary_page); + write_data(current_address,page_boundary_low,page_boundary_high,tbuffer1,tbuffer2,buff_num,CSB_dly,CLK_dly,MOSI_dly); + -- this will write to buffer -- it will proceed to next step, when, posedge of CSB. + -- This is complicated, and, hence, explained here: At posedge of CSB, the write_data will get disabled. + -- At this time, writing to buffer needs to stop, and, writing into memory should start. + + compute_address(MMPPB_mem_page,pagesize(SIM_DEVICE,binary_page),comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr, + binary_page),page_boundary_low,page_boundary_high,current_address,mem_no,binary_page); + RDYBSY_reg <= '0'; -- device is busy + status(7) <='0'; + write_to_memory(buff_num,comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)), + pagesize(SIM_DEVICE,binary_page),tbuffer1,tbuffer2,page_boundary_low,memory); + page_status(conv_integer(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)))) := '1'; + wait for 1 ps; + RDYBSY_reg <= '1' after delay_cal(TPEP,scaled_flag) ; -- device is now ready + status(7) <= '1' after delay_cal(TPEP,scaled_flag); + wait for 1 ps; +----------------page erase------------------ + +elsif (PE = '1')then + compute_address(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),pagesize(SIM_DEVICE,binary_page), + comp_byte_addr(b_address(SIM_DEVICE,binary_opt),page_addr1,byte_addr,binary_page),page_boundary_low,page_boundary_high, + current_address,mem_no,binary_page); + if (CSB_dly ='0')then + wait until CSB_dly'event and CSB_dly='1'; + end if; + RDYBSY_reg <= '0'; --device is busy + status(7) <= '0'; + erase_page(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)), + pagesize(SIM_DEVICE,binary_page),page_boundary_low,memory,binary_page,temp_page_status); + page_status(conv_integer(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)))) := temp_page_status; + wait for 1 ps; + RDYBSY_reg <= '1' after delay_cal(TPE,scaled_flag) ; --device is now ready + status(7) <= '1' after delay_cal(TPE,scaled_flag) ; + wait for 1 ps; +----------------sector erase------------------ + +elsif (SE = '1')then + compute_address(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)),pagesize(SIM_DEVICE,binary_page), + comp_byte_addr(b_address(SIM_DEVICE,binary_page),page_addr1,byte_addr,binary_page),page_boundary_low, + page_boundary_high,current_address,mem_no,binary_page); + if (CSB_dly ='0')then + wait until CSB_dly'event and CSB_dly = '1'; + end if; + RDYBSY_reg <= '0'; --device is busy + status(7) <= '0'; + --******************************-- + if (conv_integer(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE))) < 8 ) then + page_boundary_low := 0; + jerase := page_boundary_low; + loop_sectorerase: loop + if (jerase < page_boundary_low+8*pagesize(SIM_DEVICE,binary_page) ) then + erase_page(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)), + pagesize(SIM_DEVICE,binary_page),jerase,memory,binary_page,temp_page_status); -- erase 8 pages, i.e. a block + page_status(conv_integer(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)))) := temp_page_status; + jerase := jerase+pagesize(SIM_DEVICE,binary_page); + else + exit loop_sectorerase; -------------sector Eraseexit ---------------------- + end if; + end loop; + for j in 0 to 7 loop -- erase_page will only change the status of one-page + page_status(j) := '0'; + end loop; + --************************************---- + elsif (comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)) < pageper_sector(SIM_DEVICE)) then + page_boundary_low := 8*pagesize(SIM_DEVICE,binary_page); + jerase := page_boundary_low; + loop_sector1erase : loop + if (jerase < page_boundary_low+((pageper_sector(SIM_DEVICE)-8)*pagesize(SIM_DEVICE,binary_page)) ) then + erase_page(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)), + pagesize(SIM_DEVICE,binary_page),jerase,memory,binary_page,temp_page_status); --erase 248/120 pages, i.e. a block + page_status(conv_integer(comp_page_addr(p_address(SIM_DEVICE),binary_page, + page_addr0,page_addr1,manid(SIM_DEVICE)))) := temp_page_status; + jerase := jerase+pagesize(SIM_DEVICE,binary_page); + else + exit loop_sector1erase; -----------sector1 Eraseexit ------------------------ + end if; + end loop; + for j in 8 to pageper_sector(SIM_DEVICE)-1 loop --erase_page will only change the status of one-page + page_status(j) := '0'; + end loop; + --**************************** + else + page((p_address(SIM_DEVICE)- s_address(SIM_DEVICE))-1) <= '0'; + jerase := page_boundary_low; + loop_sector2erase : loop + if (jerase < page_boundary_low+(pageper_sector(SIM_DEVICE)*pagesize(SIM_DEVICE,binary_page))) then + erase_page(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)), + pagesize(SIM_DEVICE,binary_page),jerase,memory,binary_page,temp_page_status); --erase 256/128 pages, i.e. a block + page_status(conv_integer(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)))) := temp_page_status; + jerase := jerase +pagesize(SIM_DEVICE,binary_page); + else + exit loop_sector2erase; ----------sector2 Eraseexit ------------------------ + end if; + end loop; + for j in 0 to pageper_sector(SIM_DEVICE)-1 loop + page_status(conv_integer(comp_page_addr(p_address(SIM_DEVICE),binary_page,page_addr0,page_addr1,manid(SIM_DEVICE)))+j) := '0'; + end loop; + end if; + wait for 1 ps; + RDYBSY_reg <= '1' after delay_cal(TSE,scaled_flag) ; --device is now ready + status(7) <= '1' after delay_cal(TSE,scaled_flag) ; +elsif(SRR='1' and t(31)='1')then + read_out_reg(23,0,127,security_reg,CSB_dly,CLK_dly,so_reg,so_on); +elsif(SRP ='1' and t(31)='1' and page_addr0=X"00" and page_addr1= X"00" and byte_addr = X"00" )then + current_address :=0; + page_boundary_low :=0; + page_boundary_high := 63; + write_data(current_address,page_boundary_low,page_boundary_high,tbuffer1,tbuffer2,"01",CSB_dly,CLK_dly,MOSI_dly); + -- this will write to buffer + -- it will proceed to next step, when, posedge of CSB. + -- This is complicated, and, hence, explained here: + -- At posedge of CSB, the write_data will get disabled. + -- At this time, writing to buffer needs to stop, and, + -- writing into memory should start. + --writing in to security_reg + if (security_flag = '0') then --Security Register has not been programmed before + for j in 0 to 63 loop + security_reg(j) <= tbuffer1(j); + end loop; + security_flag <= '1'; + RDYBSY_reg <= '0'; --device is busy + status(7) <= '0'; + wait for 1 ps; + RDYBSY_reg <= '1' after delay_cal(TP,scaled_flag) ; --device is now ready + status(7) <= '1' after delay_cal(TP,scaled_flag) ; + wait for 1 ps; + else + Write ( Message, string'("DRC Error : In ")); + Write ( Message, InstancePath); + Write ( Message, string'(" Security register can only be programmed once")); + assert false report Message.all severity failure; + DEALLOCATE (Message); + end if; +end if; +end process; + +--------------------status register read-------- +process + variable j_tmp : integer := 8; +begin + wait on SR ; + if( SR = '1' ) then + status_read <='1';--reading status reg + -- for i in 0 to 7 loop + -- wait until CLK_dly'event and CLK_dly='0'; + -- so_reg1 <= '1'; -- the reg is set to one when data is invalid + -- so_on1 <= '1'; + -- end loop; + status_loop : loop + wait until ((CLK_dly'event and CLK_dly ='0') or (CSB_dly'event and CSB_dly='1')); + if(CSB_dly='1') then + j_tmp:=0; + exit status_loop; + end if; + if(j_tmp > 0)then + j_tmp := j_tmp - 1; + else + j_tmp := 7; + end if; + so_reg1 <= status(j_tmp); + so_on1 <= '1'; + end loop; + so_on1 <= '0'; + status_read <='0'; + end if; +end process; + +------------manufacturing ID----------- +process --(MIR)--,MANID(SIM_DEVICE)) + variable j : integer:= 32 ; + variable m_id : std_logic_vector(31 downto 0):= manid(SIM_DEVICE); +begin +wait on MIR; + if(MIR='1')then + MIR_loop : loop + wait until ((CLK_dly'event and CLK_dly ='0') or (CSB_dly'event and CSB_dly='1')); + exit MIR_loop when CSB_dly = '1'; + if(J > 0)then + SO_reg2 <= m_id(j-1); + so_on2 <= '1'; + J := J - 1; + elsif( j = 0) then + So_on2 <= '1'; + So_reg2 <= 'X'; -- only if the cs extends more than available man ID + end if; + end loop; + so_on2 <= '0'; + So_reg2 <= '0'; + end if; +end process; + + ------------------------ CLK check +checkPeriod ( CLK_dly , "CLK" , Tsck , "Tsck" , TsckRp , clk_err , InstancePath, valid ) ; +checkPeriod ( CLK_dly , "CLK" , Tsck33 , "Tsck" , TsckRp33, clk_err33 , InstancePath, test_33mhz ) ; +checkclk ( CLK_dly , "CLK" , Tspickh , "Tsck" ,TsckRpx , TsckFp , clk_erra , InstancePath, valid, valid, valid ) ; +checkclk ( CSB_dly , "CSB" , Tcs , "Tsck" ,TsckRpcsb , TsckFcsb , csb_err , InstancePath, valid, valid, no_test) ; +validate_input(SIM_DEVICE, SIM_DELAY_TYPE , scaled_flag); -- validates inputs and set scaled_flag + +process(so_on1,so_reg1,so_on2,so_reg2,so_reg, so_on) +begin + if(so_on1='1')then + MISO_zd <= so_reg1 after SYNC_PATH_DELAY; + elsif(so_on2='1')then + MISO_zd <= so_reg2 after SYNC_PATH_DELAY; + elsif (so_on='1') then + MISO_zd <= so_reg after SYNC_PATH_DELAY; + else + MISO_zd <= '1' after Tdis; + end if; +end process; + +--#################################################################### +--##### TIMING CHECKS & OUTPUT ##### +--#################################################################### + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(MISO_zd) + begin + MISO <= MISO_zd ; + end process prcs_output; + + +end SPI_ACCESS_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / User Interface to Global Clock, Reset and 3-State Controls for SPARTAN3A +-- /___/ /\ Filename : STARTUP_SPARTAN3A.vhd +-- \ \ / \ Timestamp : Tue Jul 5 15:01:35 PDT 2005 +-- \___\/\___\ +-- +-- Revision: +-- 07/05/05 - Initial version. + +----- CELL STARTUP_SPARTAN3A ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity STARTUP_SPARTAN3A is + port( + CLK : in std_ulogic := 'X'; + GSR : in std_ulogic := 'X'; + GTS : in std_ulogic := 'X' + ); +end STARTUP_SPARTAN3A; + +architecture STARTUP_SPARTAN3A_V of STARTUP_SPARTAN3A is +begin +end STARTUP_SPARTAN3A_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Multifunctional, Cascadable, 48-bit Output Arithmetic Block +-- /___/ /\ Filename : DSP48A.vhd +-- \ \ / \ Timestamp : Mon Mar 20 17:25:10 PST 2006 +-- \___\/\___\ +-- +-- Revision: +-- 03/25/06 - Initial version. +-- 09/22/06 - fixed CR 421339 +-- 01/17/07 - fixed CR 431766 +-- End Revision +----- CELL DSP48A ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_SIGNED.all; +use IEEE.STD_LOGIC_ARITH.all; + +library STD; +use STD.TEXTIO.all; + + +library unisim; +use unisim.vpkg.all; + +entity DSP48A is + + generic( + + A0REG : integer := 0; + A1REG : integer := 1; + B0REG : integer := 0; + B1REG : integer := 1; + CARRYINREG : integer := 1; + CARRYINSEL : string := "CARRYIN"; + CREG : integer := 1; + DREG : integer := 1; + MREG : integer := 1; + OPMODEREG : integer := 1; + PREG : integer := 1; + RSTTYPE : string := "SYNC" + ); + + port( + BCOUT : out std_logic_vector(17 downto 0); + CARRYOUT : out std_ulogic; + P : out std_logic_vector(47 downto 0); + PCOUT : out std_logic_vector(47 downto 0); + + A : in std_logic_vector(17 downto 0); + B : in std_logic_vector(17 downto 0); + + C : in std_logic_vector(47 downto 0); + CARRYIN : in std_ulogic; + CEA : in std_ulogic; + CEB : in std_ulogic; + CEC : in std_ulogic; + CECARRYIN : in std_ulogic; + CED : in std_ulogic; + CEM : in std_ulogic; + CEOPMODE : in std_ulogic; + CEP : in std_ulogic; + CLK : in std_ulogic; + D : in std_logic_vector(17 downto 0); + OPMODE : in std_logic_vector(7 downto 0); + PCIN : in std_logic_vector(47 downto 0); + RSTA : in std_ulogic; + RSTB : in std_ulogic; + RSTC : in std_ulogic; + RSTCARRYIN : in std_ulogic; + RSTD : in std_ulogic; + RSTM : in std_ulogic; + RSTOPMODE : in std_ulogic; + RSTP : in std_ulogic + ); + +end DSP48A; + +-- architecture body -- + +architecture DSP48A_V of DSP48A is + + procedure invalid_opmode_preg_msg( OPMODE : IN string ; + CARRYINSEL : IN string ) is + variable Message : line; + begin + Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); + Write ( Message, OPMODE); + Write ( Message, string'(" with CARRYINSEL ")); + Write ( Message, CARRYINSEL); + Write ( Message, string'(" to DSP48A instance ")); + Write ( Message, string'("requires attribute PREG set to 1.")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end invalid_opmode_preg_msg; + + procedure invalid_opmode_mreg_msg( OPMODE : IN string ; + CARRYINSEL : IN string ) is + variable Message : line; + begin + Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); + Write ( Message, OPMODE); + Write ( Message, string'(" with CARRYINSEL ")); + Write ( Message, CARRYINSEL); + Write ( Message, string'(" to DSP48A instance ")); + Write ( Message, string'("requires attribute MREG set to 1.")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end invalid_opmode_mreg_msg; + + procedure invalid_opmode_no_mreg_msg( OPMODE : IN string ; + CARRYINSEL : IN string ) is + variable Message : line; + begin + Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); + Write ( Message, OPMODE); + Write ( Message, string'(" with CARRYINSEL ")); + Write ( Message, CARRYINSEL); + Write ( Message, string'(" to DSP48A instance ")); + Write ( Message, string'("requires attribute MREG set to 0.")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end invalid_opmode_no_mreg_msg; + + + + + constant SYNC_PATH_DELAY : time := 100 ps; + + constant MAX_ACCUM : integer := 48; + constant MAX_BCOUT : integer := 18; + constant MAX_P : integer := 48; + constant MAX_PCOUT : integer := 48; + constant MSB_ACCUM : integer := MAX_ACCUM - 1; + constant MSB_BCOUT : integer := MAX_BCOUT - 1; + constant MSB_P : integer := MAX_P - 1; + constant MSB_PCOUT : integer := MAX_PCOUT - 1; + + constant MAX_A : integer := 18; + constant MAX_B : integer := 18; + constant MAX_BCIN : integer := 18; + constant MAX_C : integer := 48; + constant MAX_D : integer := 18; + constant MAX_PREADD : integer := 18; + constant MAX_OPMODE : integer := 8; + constant MAX_PCIN : integer := 48; + constant MSB_A : integer := MAX_A - 1; + constant MSB_B : integer := MAX_B - 1; + constant MSB_BCIN : integer := MAX_BCIN - 1; + constant MSB_C : integer := MAX_C - 1; + constant MSB_D : integer := MAX_D - 1; + constant MSB_PREADD : integer := MAX_PREADD - 1; + constant MSB_OPMODE : integer := MAX_OPMODE - 1; + constant MSB_PCIN : integer := MAX_PCIN - 1; + + + constant SHIFT_MUXZ : integer := 17; + + signal A_ipd : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal B_ipd : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal BCIN_ipd : std_logic_vector(MSB_BCIN downto 0) := (others => '0'); + signal C_ipd : std_logic_vector(MSB_C downto 0) := (others => '0'); + signal CARRYIN_ipd : std_ulogic := '0'; + signal CEA_ipd : std_ulogic := '0'; + signal CEB_ipd : std_ulogic := '0'; + signal CEC_ipd : std_ulogic := '0'; + signal CECARRYIN_ipd : std_ulogic := '0'; + signal CED_ipd : std_ulogic := '0'; + signal CEM_ipd : std_ulogic := '0'; + signal CEOPMODE_ipd : std_ulogic := '0'; + signal CEP_ipd : std_ulogic := '0'; + signal CLK_ipd : std_ulogic := '0'; + signal D_ipd : std_logic_vector(MSB_D downto 0) := (others => '0'); + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := '0'; + signal OPMODE_ipd : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); + signal PCIN_ipd : std_logic_vector(MSB_PCIN downto 0) := (others => '0'); + signal RSTA_ipd : std_ulogic := '0'; + signal RSTB_ipd : std_ulogic := '0'; + signal RSTC_ipd : std_ulogic := '0'; + signal RSTCARRYIN_ipd : std_ulogic := '0'; + signal RSTD_ipd : std_ulogic := '0'; + signal RSTM_ipd : std_ulogic := '0'; + signal RSTOPMODE_ipd : std_ulogic := '0'; + signal RSTP_ipd : std_ulogic := '0'; + + signal A_dly : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal B_dly : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal BCIN_dly : std_logic_vector(MSB_BCIN downto 0) := (others => '0'); + signal C_dly : std_logic_vector(MSB_C downto 0) := (others => '0'); + signal CARRYIN_dly : std_ulogic := '0'; + signal CEA_dly : std_ulogic := '0'; + signal CEB_dly : std_ulogic := '0'; + signal CEC_dly : std_ulogic := '0'; + signal CECARRYIN_dly : std_ulogic := '0'; + signal CED_dly : std_ulogic := '0'; + signal CEM_dly : std_ulogic := '0'; + signal CEOPMODE_dly : std_ulogic := '0'; + signal CEP_dly : std_ulogic := '0'; + signal CLK_dly : std_ulogic := '0'; + signal D_dly : std_logic_vector(MSB_D downto 0) := (others => '0'); + signal GSR_dly : std_ulogic := '0'; + signal OPMODE_dly : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); + signal PCIN_dly : std_logic_vector(MSB_PCIN downto 0) := (others => '0'); + signal RSTA_dly : std_ulogic := '0'; + signal RSTB_dly : std_ulogic := '0'; + signal RSTC_dly : std_ulogic := '0'; + signal RSTCARRYIN_dly : std_ulogic := '0'; + signal RSTD_dly : std_ulogic := '0'; + signal RSTM_dly : std_ulogic := '0'; + signal RSTOPMODE_dly : std_ulogic := '0'; + signal RSTP_dly : std_ulogic := '0'; + + + signal BCOUT_zd : std_logic_vector(MSB_BCOUT downto 0) := (others => '0'); + signal CARRYOUT_zd : std_ulogic := '0'; + signal P_zd : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal PCOUT_zd : std_logic_vector(MSB_PCOUT downto 0) := (others => '0'); + + --- Internal Signal Declarations + signal qa_o_reg1 : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal qa_o_reg2 : std_logic_vector(MSB_A downto 0) := (others => '0'); + signal qa_o_mux : std_logic_vector(MSB_A downto 0) := (others => '0'); + + signal b_o_mux : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal qb_o_reg1 : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal qb_o_reg2 : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal qb_o_mux0 : std_logic_vector(MSB_B downto 0) := (others => '0'); + signal qb_o_mux : std_logic_vector(MSB_B downto 0) := (others => '0'); + + signal qc_o_reg : std_logic_vector(MSB_C downto 0) := (others => '0'); + signal qc_o_mux : std_logic_vector(MSB_C downto 0) := (others => '0'); + + signal qd_o_reg : std_logic_vector(MSB_D downto 0) := (others => '0'); + signal qd_o_mux : std_logic_vector(MSB_D downto 0) := (others => '0'); + + signal preadd : std_logic_vector(MSB_PREADD downto 0) := (others => '0'); + signal mux_preadd : std_logic_vector(MSB_PREADD downto 0) := (others => '0'); + + signal mult_o_int : std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0'); + signal mult_o_reg : std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0'); + signal mult_o_mux : std_logic_vector((MSB_A + MSB_B + 1) downto 0) := (others => '0'); + + signal opmode_o_reg : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); + signal opmode_o_mux : std_logic_vector(MSB_OPMODE downto 0) := (others => '0'); + + signal muxx_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal muxy_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal muxz_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); + + signal subtract_o_reg : std_ulogic := '0'; + signal subtract_o_mux : std_ulogic := '0'; + + signal carryinsel_o_reg : std_ulogic := '0'; + signal carryinsel_o_mux : std_ulogic := '0'; + + signal qcarryin_o_reg1 : std_ulogic := '0'; + signal carryin0_o_mux : std_ulogic := '0'; + signal carryin1_o_mux : std_ulogic := '0'; + signal carryin2_o_mux : std_ulogic := '0'; + + signal qcarryin_o_reg2 : std_ulogic := '0'; + + signal carryin_o_mux : std_ulogic := '0'; + + signal accum_o : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal qp_o_reg : std_logic_vector(MSB_P downto 0) := (others => '0'); + signal qp_o_mux : std_logic_vector(MSB_P downto 0) := (others => '0'); + + signal add_i_int : std_logic_vector(47 downto 0) := (others => '0'); + signal add_o_int : std_logic_vector(47 downto 0) := (others => '0'); + + signal reg_p_int : std_logic_vector(47 downto 0) := (others => '0'); + signal p_o_int : std_logic_vector(47 downto 0) := (others => '0'); + + signal subtract1_o_int : std_ulogic := '0'; + signal carryinsel1_o_int : std_logic_vector(1 downto 0) := (others => '0'); + signal carry1_o_int : std_ulogic := '0'; + signal carry2_o_int : std_ulogic := '0'; + + + signal output_x_sig : std_ulogic := '0'; + + signal RST_META : std_ulogic := '0'; + + signal DefDelay : time := 10 ps; + + signal rst_async_flag : std_ulogic := '0'; + signal carryinsel_attr : std_ulogic := '0'; + + signal opmode_valid_flg : boolean := true; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + + A_dly <= A after 0 ps; + B_dly <= B after 0 ps; + + C_dly <= C after 0 ps; + CARRYIN_dly <= CARRYIN after 0 ps; + CEA_dly <= CEA after 0 ps; + CEB_dly <= CEB after 0 ps; + CEC_dly <= CEC after 0 ps; + CECARRYIN_dly <= CECARRYIN after 0 ps; + CED_dly <= CED after 0 ps; + CEM_dly <= CEM after 0 ps; + CEOPMODE_dly <= CEOPMODE after 0 ps; + CEP_dly <= CEP after 0 ps; + CLK_dly <= CLK after 0 ps; + D_dly <= D after 0 ps; + OPMODE_dly <= OPMODE after 0 ps; + PCIN_dly <= PCIN after 0 ps; + RSTA_dly <= RSTA after 0 ps; + RSTB_dly <= RSTB after 0 ps; + RSTC_dly <= RSTC after 0 ps; + RSTCARRYIN_dly <= RSTCARRYIN after 0 ps; + RSTD_dly <= RSTD after 0 ps; + RSTM_dly <= RSTM after 0 ps; + RSTOPMODE_dly <= RSTOPMODE after 0 ps; + RSTP_dly <= RSTP after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + +--#################################################################### +--##### Initialization ### +--#################################################################### + prcs_init:process + begin + +-------- A0REG/A1REG & B0REG/B1REG ------ + + if((A0REG /= 0) and (A0REG /= 1 )) then + assert false + report "Attribute Syntax Error: Legal values for attribute A0REG on instance DSP48A are 0 or 1." + severity Failure; + end if; + + if((A1REG /= 0) and (A1REG /= 1 )) then + assert false + report "Attribute Syntax Error: Legal values for attribute A1REG on instance DSP48A are 0 or 1." + severity Failure; + end if; + + if((B0REG /= 0) and (B0REG /= 1 )) then + assert false + report "Attribute Syntax Error: Legal values for attribute B0REG on instance DSP48A are 0 or 1." + severity Failure; + end if; + + if((B1REG /= 0) and (B1REG /= 1 )) then + assert false + report "Attribute Syntax Error: Legal values for attribute B1REG on instance DSP48A are 0 or 1." + severity Failure; + end if; + +-------- RSTTYPE ---------- + + if((RSTTYPE = "SYNC") or (RSTTYPE = "sync")) then + rst_async_flag <= '0'; + elsif((RSTTYPE = "ASYNC") or (RSTTYPE = "async")) then + rst_async_flag <= '1'; + else + assert false + report "Attribute Syntax Error: The attribute RSTTYPE on DSP48A is incorrect. Legal values for this attribute are SYNC or ASYNC." + severity Failure; + end if; + +-------- CARRYINSEL --------- + + if((CARRYINSEL = "CARRYIN") or (CARRYINSEL = "carryin")) then + carryinsel_attr <= '0'; + elsif((CARRYINSEL = "OPMODE5") or (CARRYINSEL = "opmode5")) then + carryinsel_attr <= '1'; + else + assert false + report "Attribute Syntax Error: The attribute RSTTYPE on DSP48A is incorrect. Legal values for this attribute are SYNC or ASYNC." + severity Failure; + end if; + + wait; + + end process prcs_init; +--#################################################################### +--##### Input Register A with two levels of registers ### +--#################################################################### + + prcs_qa_2lvl:process(CLK_dly, GSR_dly, RSTA_dly) + begin + if(GSR_dly = '1') then + qa_o_reg1 <= ( others => '0'); + qa_o_reg2 <= ( others => '0'); + elsif (GSR_dly = '0') then + case rst_async_flag is + when '1' => + -----------// async reset + if(RSTA_dly = '1') then + qa_o_reg1 <= ( others => '0'); + qa_o_reg2 <= ( others => '0'); + elsif ((RSTA_dly = '0') and (CEA_dly = '1')) then + if(rising_edge(CLK_dly)) then + qa_o_reg2 <= qa_o_reg1; + qa_o_reg1 <= A_dly; + end if; + end if; + when '0' => + -----------// sync reset + if(rising_edge(CLK_dly)) then + if(RSTA_dly = '1') then + qa_o_reg1 <= ( others => '0'); + qa_o_reg2 <= ( others => '0'); + elsif ((RSTA_dly = '0') and (CEA_dly = '1')) then + qa_o_reg2 <= qa_o_reg1; + qa_o_reg1 <= A_dly; + end if; + end if; + when others => null; + end case; + end if; + end process prcs_qa_2lvl; +------------------------------------------------------------------ + prcs_qa_o_mux:process(A_dly, qa_o_reg1, qa_o_reg2) + begin + if((A0REG=0) and (A1REG=0)) then + qa_o_mux <= A_dly; + elsif(((A0REG=1) and (A1REG=0)) or ((A0REG=0) and (A1REG=1))) then + qa_o_mux <= qa_o_reg1; + elsif((A0REG=1) and (A1REG=1)) then + qa_o_mux <= qa_o_reg2; + end if; + end process prcs_qa_o_mux; + +--#################################################################### +--#### Input Register B with two levels of registers and two muxes ### +--#################################################################### + prcs_qb_2lvl:process(CLK_dly, GSR_dly, RSTB_dly) + begin + if(GSR_dly = '1') then + qb_o_reg1 <= ( others => '0'); + qb_o_reg2 <= ( others => '0'); + elsif (GSR_dly = '0') then + case rst_async_flag is + when '1' => + -----------// async reset + if(RSTB_dly = '1') then + qb_o_reg1 <= ( others => '0'); + qb_o_reg2 <= ( others => '0'); + elsif ((RSTB_dly = '0') and (CEB_dly = '1')) then + if(rising_edge(CLK_dly)) then + qb_o_reg2 <= mux_preadd; + qb_o_reg1 <= B_dly; + end if; + end if; + when '0' => + -----------// sync reset + if(rising_edge(CLK_dly)) then + if(RSTB_dly = '1') then + qb_o_reg1 <= ( others => '0'); + qb_o_reg2 <= ( others => '0'); + elsif ((RSTB_dly = '0') and (CEB_dly = '1')) then + qb_o_reg2 <= mux_preadd; + qb_o_reg1 <= B_dly; + end if; + end if; + when others => null; + end case; + end if; + end process prcs_qb_2lvl; + +------- PRE ADD -------------------------------------------------- + + prcs_qb_preadd:process(opmode_o_mux, B_dly, qd_o_mux, qb_o_reg1) + begin + if(((B0REG=0) and (B1REG=0)) or ((B0REG=0) and (B1REG=1))) then + qb_o_mux0 <= B_dly; + if(opmode_o_mux(6)='0') then + preadd <= (qd_o_mux + B_dly ); + elsif(opmode_o_mux(6)='1') then + preadd <= (qd_o_mux - B_dly ); + end if; + elsif(((B0REG=1) and (B1REG=1)) or ((B0REG=1) and (B1REG=0))) then + qb_o_mux0 <= qb_o_reg1; + if(opmode_o_mux(6)='0') then + preadd <= (qd_o_mux + qb_o_reg1); + elsif(opmode_o_mux(6)='1') then + preadd <= (qd_o_mux - qb_o_reg1); + end if; + end if; + end process prcs_qb_preadd; + +------------------------------------------------------------------ + prcs_preadd_sel:process(opmode_o_mux(4), preadd, qb_o_mux0) + begin + if(opmode_o_mux(4)='1') then + mux_preadd <= preadd; + elsif(opmode_o_mux(4)='0') then + mux_preadd <= qb_o_mux0; + end if; + end process prcs_preadd_sel; +------------------------------------------------------------------ + prcs_qb_o_mux:process(mux_preadd, qb_o_reg2) + begin + if(((B0REG=0) and (B1REG=0)) or ((B0REG=1) and (B1REG=0))) then + qb_o_mux <= mux_preadd; + elsif(((B0REG=1) and (B1REG=1)) or ((B0REG=0) and (B1REG=1))) then + qb_o_mux <= qb_o_reg2; + end if; + end process prcs_qb_o_mux; + +--#################################################################### +--##### Input Register C with 0, 1, level of registers ##### +--#################################################################### + + prcs_qc_1lvl:process(CLK_dly, GSR_dly, RSTC_dly) + + begin + if(GSR_dly = '1') then + qc_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + case rst_async_flag is + when '1' => + -----------// async reset + if(RSTC_dly = '1') then + qc_o_reg <= ( others => '0'); + elsif((RSTC_dly = '0') and (CEC_dly = '1'))then + if(rising_edge(CLK_dly)) then + qc_o_reg <= C_dly; + end if; + end if; + when '0' => + -----------// sync reset + if(rising_edge(CLK_dly)) then + if(RSTC_dly = '1') then + qc_o_reg <= ( others => '0'); + elsif ((RSTC_dly = '0') and (CEC_dly = '1')) then + qc_o_reg <= C_dly; + end if; + end if; + when others => null; + end case; + end if; + end process prcs_qc_1lvl; +------------------------------------------------------------------ + prcs_qc_o_mux:process(C_dly, qc_o_reg) + begin + case CREG is + when 0 => qc_o_mux <= C_dly; + when 1 => qc_o_mux <= qc_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for CREG on instace DSP48A are 0 or 1" + severity Failure; + end case; + end process prcs_qc_o_mux; + +--#################################################################### +--##### Input Register D with 0, 1, level of registers ##### +--#################################################################### + + prcs_qd_1lvl:process(CLK_dly, GSR_dly, RSTD_dly) + + begin + if(GSR_dly = '1') then + qd_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + case rst_async_flag is + when '1' => + -----------// async reset + if(RSTD_dly = '1') then + qd_o_reg <= ( others => '0'); + elsif((RSTD_dly = '0') and (CED_dly = '1'))then + if(rising_edge(CLK_dly)) then + qd_o_reg <= D_dly; + end if; + end if; + when '0' => + -----------// sync reset + if(rising_edge(CLK_dly)) then + if(RSTD_dly = '1') then + qd_o_reg <= ( others => '0'); + elsif ((RSTD_dly = '0') and (CED_dly = '1')) then + qd_o_reg <= D_dly; + end if; + end if; + when others => null; + end case; + end if; + end process prcs_qd_1lvl; +------------------------------------------------------------------ + prcs_qd_o_mux:process(D_dly, qd_o_reg) + begin + case DREG is + when 0 => qd_o_mux <= D_dly; + when 1 => qd_o_mux <= qd_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for DREG on instace DSP48A are 0 or 1" + severity Failure; + end case; + end process prcs_qd_o_mux; + +--#################################################################### +--##### Multiplier ##### +--#################################################################### + prcs_mult:process(qa_o_mux, qb_o_mux) + begin + mult_o_int <= qa_o_mux * qb_o_mux; + end process prcs_mult; +------------------------------------------------------------------ + prcs_mult_reg:process(CLK_dly, GSR_dly, RSTM_dly) + begin + if(GSR_dly = '1') then + mult_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + case rst_async_flag is + when '1' => + -----------// async reset + if(RSTM_dly = '1') then + mult_o_reg <= ( others => '0'); + elsif((RSTM_dly = '0') and (CEM_dly = '1'))then + if(rising_edge(CLK_dly)) then + mult_o_reg <= mult_o_int; + end if; + end if; + when '0' => + -----------// sync reset + if(rising_edge(CLK_dly)) then + if(RSTM_dly = '1') then + mult_o_reg <= ( others => '0'); + elsif ((RSTM_dly = '0') and (CEM_dly = '1')) then + mult_o_reg <= mult_o_int; + end if; + end if; + when others => null; + end case; + end if; + end process prcs_mult_reg; +------------------------------------------------------------------ + prcs_mult_mux:process(mult_o_reg, mult_o_int) + begin + case MREG is + when 0 => mult_o_mux <= mult_o_int; + when 1 => mult_o_mux <= mult_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for MREG on instance DSP48A are 0 or 1" + severity Failure; + end case; + end process prcs_mult_mux; + +--#################################################################### +--##### OpMode Register with 0, 1, level of registers ##### +--#################################################################### + + prcs_opmode_reg:process(CLK_dly, GSR_dly, RSTOPMODE_dly) + begin + if(GSR_dly = '1') then + opmode_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + case rst_async_flag is + when '1' => + -----------// async reset + if(RSTOPMODE_dly = '1') then + opmode_o_reg <= ( others => '0'); + elsif((RSTOPMODE_dly = '0') and (CEOPMODE_dly = '1'))then + if(rising_edge(CLK_dly)) then + opmode_o_reg <= OPMODE_dly; + end if; + end if; + when '0' => + -----------// sync reset + if(rising_edge(CLK_dly)) then + if(RSTOPMODE_dly = '1') then + opmode_o_reg <= ( others => '0'); + elsif ((RSTOPMODE_dly = '0') and (CEOPMODE_dly = '1')) then + opmode_o_reg <= OPMODE_dly; + end if; + end if; + when others => null; + end case; + end if; + end process prcs_opmode_reg; +------------------------------------------------------------------ + prcs_opmode_mux:process(opmode_o_reg, OPMODE_dly) + begin + case OPMODEREG is + when 0 => opmode_o_mux <= OPMODE_dly; + when 1 => opmode_o_mux <= opmode_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for OPMODEREG are 0 or 1" + severity Failure; + end case; + end process prcs_opmode_mux; +--#################################################################### +--##### MUX_XYZ ##### +--#################################################################### + prcs_mux_xz:process(opmode_o_mux, qp_o_mux, qa_o_mux, qb_o_mux, mult_o_mux, + qc_o_mux, qd_o_mux, PCIN_dly, output_x_sig) + begin + if(output_x_sig = '1') then + muxx_o_mux(MSB_P downto 0) <= ( others => 'X'); + muxy_o_mux(MSB_P downto 0) <= ( others => 'X'); + muxz_o_mux(MSB_P downto 0) <= ( others => 'X'); + elsif(output_x_sig = '0') then + --MUX_X ----- + case opmode_o_mux(1 downto 0) is + when "00" => muxx_o_mux <= ( others => '0'); + when "01" => muxx_o_mux((MAX_A + MAX_B - 1) downto 0) <= mult_o_mux; + if(mult_o_mux(MAX_A + MAX_B - 1) = '1') then + muxx_o_mux(MSB_P downto (MAX_A + MAX_B)) <= ( others => '1'); + elsif (mult_o_mux(MSB_A + MSB_B + 1) = '0') then + muxx_o_mux(MSB_P downto (MAX_A + MAX_B)) <= ( others => '0'); + end if; + + when "10" => muxx_o_mux <= qp_o_mux; + when "11" => muxx_o_mux(MSB_P downto 0) <= (qd_o_mux((MSB_P - (MAX_A + MAX_B)) downto 0) & qa_o_mux & qb_o_mux); + when others => null; + end case; + + --MUX_Z ----- + case opmode_o_mux(3 downto 2) is + when "00" => muxz_o_mux <= ( others => '0'); + when "01" => muxz_o_mux <= PCIN_dly; + when "10" => muxz_o_mux <= qp_o_mux; + when "11" => muxz_o_mux <= qc_o_mux; + when others => null; + end case; + end if; + end process prcs_mux_xz; + +--#################################################################### +--##### CarryIn 1 level of register ##### +--#################################################################### + + prcs_carryinsel_mux:process(opmode_o_mux(5), CARRYIN_dly) + begin + if((CARRYINSEL = "CARRYIN") or (CARRYINSEL = "carryin")) then + carryinsel_o_mux <= CARRYIN_dly; + elsif((CARRYINSEL = "OPMODE5") or (CARRYINSEL = "opmode5")) then + carryinsel_o_mux <= opmode_o_mux(5); + else + assert false + report "Attribute Syntax Error: The allowed values for CARRYINSEL on instance DSP48A are CARRYIN or OPMODES." + severity Failure; + end if; + end process prcs_carryinsel_mux; +------------------------------------------ + prcs_carryin_reg:process(CLK_dly, GSR_dly, RSTCARRYIN_dly) + begin + if(GSR_dly = '1') then + qcarryin_o_reg1 <= '0'; + elsif (GSR_dly = '0') then + case rst_async_flag is + when '1' => + -----------// async reset + if(RSTCARRYIN_dly = '1') then + qcarryin_o_reg1 <= '0'; + elsif((RSTCARRYIN_dly = '0') and (CECARRYIN_dly = '1'))then + if(rising_edge(CLK_dly)) then + qcarryin_o_reg1 <= carryinsel_o_mux; + end if; + end if; + when '0' => + -----------// sync reset + if(rising_edge(CLK_dly)) then + if(RSTCARRYIN_dly = '1') then + qcarryin_o_reg1 <= '0'; + elsif ((RSTCARRYIN_dly = '0') and (CECARRYIN_dly = '1')) then + qcarryin_o_reg1 <= carryinsel_o_mux; + end if; + end if; + when others => null; + end case; + end if; + end process prcs_carryin_reg; +------------------------------------------------------------------ + prcs_carryin_mux:process(qcarryin_o_reg1, carryinsel_o_mux) + begin + case CARRYINREG is + when 0 => carryin_o_mux <= carryinsel_o_mux; + when 1 => carryin_o_mux <= qcarryin_o_reg1; + when others => + assert false + report "Attribute Syntax Error: The allowed values for CARRYINREG on instance DSP48A are 0 or 1" + severity Failure; + end case; + end process prcs_carryin_mux; +------------------------------------------------------------------ +--#################################################################### +--##### Output register P with 1 level of register ##### +--#################################################################### + + prcs_qp_reg:process(CLK_dly, GSR_dly, RSTP_dly) + begin + if(GSR_dly = '1') then + qp_o_reg <= ( others => '0'); + elsif (GSR_dly = '0') then + case rst_async_flag is + when '1' => + -----------// async reset + if(RSTP_dly = '1') then + qp_o_reg <= ( others => '0'); + elsif((RSTP_dly = '0') and (CEP_dly = '1'))then + if(rising_edge(CLK_dly)) then + qp_o_reg <= accum_o; + end if; + end if; + when '0' => + -----------// sync reset + if(rising_edge(CLK_dly)) then + if(RSTP_dly = '1') then + qp_o_reg <= ( others => '0'); + elsif ((RSTP_dly = '0') and (CEP_dly = '1')) then + qp_o_reg <= accum_o; + end if; + end if; + when others => null; + end case; + end if; + end process prcs_qp_reg; +------------------------------------------------------------------ + prcs_qp_mux:process(accum_o, qp_o_reg) + begin + case PREG is + when 0 => qp_o_mux <= accum_o; + when 1 => qp_o_mux <= qp_o_reg; + when others => + assert false + report "Attribute Syntax Error: The allowed values for PREG on instace X_MDPS1 are 0 or 1" + severity Failure; + end case; + + end process prcs_qp_mux; +--#################################################################### +--##### ZERO_DELAY_OUTPUTS ##### +--#################################################################### + prcs_zero_delay_outputs:process(qb_o_mux, qp_o_mux) + begin + BCOUT_zd <= qb_o_mux; + P_zd <= qp_o_mux; + PCOUT_zd <= qp_o_mux; + end process prcs_zero_delay_outputs; + +--#################################################################### +--##### OPMODE DRC ##### +--#################################################################### + + prcs_opmode_drc:process(opmode_o_mux, carryinsel_attr, + muxx_o_mux, muxz_o_mux, carryin_o_mux) + variable Message : line; + variable invalid_opmode_flg : boolean := true; + variable opmode_valid_var : boolean := true; + variable opmode_carryinsel_var : std_logic_vector(8 downto 0) := (others => '0'); + variable accum_o_tmp : std_logic_vector(MAX_ACCUM downto 0) := (others => '0'); + begin + opmode_carryinsel_var := opmode_o_mux & carryinsel_attr; + case opmode_carryinsel_var is + when "000000000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000100000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001000000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001100000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010000000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010100000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011000000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011100000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100000000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100100000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101000000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101100000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110000000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110100000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111000000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111100000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000000001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000100001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001000001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001100001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010000001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010100001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011000001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011100001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100000001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100100001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101000001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101100001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110000001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110100001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111000001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111100001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000000100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000000101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000100100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000100101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001000100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001000101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001100100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001100101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010000100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010000101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010100100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010100101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011000100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011000101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011100100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011100101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100000100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100000101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100100100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100100101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101000100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101000101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101100100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101100101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110000100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110000101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110100100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110100101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111000100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111000101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111100100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111100101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000000110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000000111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001000110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001000111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010000110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010000111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011000110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011000111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100000110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100000111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101000110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101000111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110000110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110000111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111000110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111000111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000100110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000100111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001100110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001100111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010100110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010100111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011100110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011100111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100100110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100100111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101100110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101100111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110100110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110100111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111100110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111100111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000000010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000000011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001000010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001000011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010000010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010000011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011000010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011000011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100000010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100000011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101000010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101000011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110000010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110000011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111000010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111000011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000100010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000100011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001100010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001100011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100100010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100100011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101100010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101100011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010100010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010100011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011100010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011100011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110100010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110100011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111100010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111100011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000001000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000001001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000101000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000101001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001001000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001001001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001101000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001101001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010001000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010001001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010101000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010101001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011001000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011001001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011101000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011101001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100001000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100001001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100101000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100101001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101001000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101001001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101101000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101101001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110001000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110001001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110101000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110101001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111001000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111001001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111101000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111101001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000001100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000001101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000101100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000101101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001001100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001001101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001101100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001101101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010001100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010001101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010101100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010101101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011001100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011001101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011101100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011101101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100001100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100001101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100101100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100101101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101001100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101001101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101101100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101101101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110001100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110001101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110101100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110101101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111001100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111001101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111101100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111101101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000001110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000001111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001001110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001001111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010001110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010001111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011001110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011001111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100001110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100001111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101001110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101001111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110001110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110001111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111001110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111001111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000101110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000101111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001101110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001101111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010101110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010101111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011101110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011101111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100101110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100101111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101101110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101101111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110101110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110101111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111101110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111101111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000001010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000001011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001001010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001001011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010001010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010001011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011001010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011001011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100001010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100001011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101001010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101001011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110001010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110001011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111001010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111001011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000101010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000101011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001101010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001101011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100101010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100101011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101101010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101101011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010101010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010101011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011101010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011101011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110101010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110101011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111101010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111101011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000010000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000010001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000110000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000110001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001010000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001010001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001110000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001110001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010010000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010010001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010110000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010110001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011010000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011010001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011110000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011110001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100010000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100010001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100110000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100110001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101010000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101010001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101110000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101110001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110010000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110010001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110110000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110110001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111010000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111010001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111110000" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111110001" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000010100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000010101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000110100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000110101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001010100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001010101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001110100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001110101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010010100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010010101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010110100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010110101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011010100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011010101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011110100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011110101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100010100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100010101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100110100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100110101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101010100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101010101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101110100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101110101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110010100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110010101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110110100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110110101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111010100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111010101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111110100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111110101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000010110" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000010111" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001010110" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001010111" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010010110" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010010111" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011010110" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011010111" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100010110" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100010111" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101010110" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101010111" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110010110" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110010111" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111010110" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111010111" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000110110" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000110111" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001110110" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001110111" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010110110" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010110111" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011110110" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011110111" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100110110" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100110111" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101110110" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101110111" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110110110" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110110111" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111110110" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111110111" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000010010" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000010011" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001010010" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001010011" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010010010" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010010011" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011010010" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011010011" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100010010" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100010011" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101010010" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101010011" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110010010" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110010011" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111010010" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111010011" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000110010" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000110011" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001110010" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001110011" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100110010" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100110011" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101110010" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101110011" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010110010" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010110011" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011110010" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011110011" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110110010" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110110011" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111110010" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111110011" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000011000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000011001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000111000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000111001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001011000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001011001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001111000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001111001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010011000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010011001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010111000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010111001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011011000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011011001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011111000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011111001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100011000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100011001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100111000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100111001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101011000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101011001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101111000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101111001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110011000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110011001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110111000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110111001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111011000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111011001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111111000" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111111001" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000011100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000011101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000111100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000111101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001011100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001011101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001111100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "001111101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010011100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010011101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010111100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "010111101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011011100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011011101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011111100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "011111101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100011100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100011101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100111100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "100111101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101011100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101011101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101111100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "101111101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110011100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110011101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110111100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "110111101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111011100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111011101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111111100" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "111111101" => + if (PREG /= 1) then + accum_o <= (others => 'X'); + opmode_valid_var := false; + if(invalid_opmode_flg) then + invalid_opmode_preg_msg(slv_to_str(opmode_o_mux), CARRYINSEL); + end if; + invalid_opmode_flg := false; + else + invalid_opmode_flg := true; + opmode_valid_var := true; + output_x_sig <= '0'; + end if; + when "000011110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000011111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001011110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001011111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010011110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010011111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011011110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011011111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100011110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100011111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101011110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101011111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110011110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110011111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111011110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111011111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000011010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000011011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001011010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001011011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010011010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010011011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011011010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011011011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100011010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100011011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101011010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101011011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110011010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110011011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111011010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111011011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000111010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000111011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001111010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001111011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100111010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100111011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101111010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101111011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010111010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010111011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011111010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011111011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110111010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110111011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111111010" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111111011" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000111110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "000111111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001111110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "001111111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010111110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "010111111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011111110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "011111111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100111110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "100111111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101111110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "101111111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110111110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "110111111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111111110" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when "111111111" => + invalid_opmode_flg := true ; + opmode_valid_var := true ; + output_x_sig <= '0'; + when others => + if(invalid_opmode_flg = true) then + invalid_opmode_flg := false; + opmode_valid_var := false; + output_x_sig <= '1'; + accum_o <= (others => 'X'); + Write ( Message, string'("OPMODE Input Warning : The OPMODE ")); + Write ( Message, slv_to_str(opmode_o_mux)); + Write ( Message, string'(" with CARRYINSEL ")); + Write ( Message, CARRYINSEL); + Write ( Message, string'(" to DSP48A instance")); + Write ( Message, string'(" is invalid for that specific OPMODE.")); + assert false report Message.all severity Warning; + DEALLOCATE (Message); + end if; + end case; + + opmode_valid_flg <= opmode_valid_var; + + if(opmode_valid_var) then + if(opmode_o_mux(7) = '0') then + accum_o_tmp := ('0'& muxz_o_mux) + ('0'& muxx_o_mux) + carryin_o_mux; + elsif(opmode_o_mux(7) = '1') then + accum_o_tmp := ('0'& muxz_o_mux) - ('0'& muxx_o_mux) - carryin_o_mux; + end if; + + accum_o <= accum_o_tmp(MSB_ACCUM downto 0); + CARRYOUT_zd <= accum_o_tmp(MAX_ACCUM); + end if; + end process prcs_opmode_drc; + +--#################################################################### +--##### OUTPUT ##### +--#################################################################### + prcs_output:process(BCOUT_zd, CARRYOUT_zd, PCOUT_zd, P_zd) + begin + BCOUT <= BCOUT_zd after SYNC_PATH_DELAY; + CARRYOUT <= CARRYOUT_zd after SYNC_PATH_DELAY; + P <= P_zd after SYNC_PATH_DELAY; + PCOUT <= PCOUT_zd after SYNC_PATH_DELAY; + end process prcs_output; + + + +end DSP48A_V; + +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +-- /___/ /\ Filename : RAMB16BWER.vhd +-- \ \ / \ Timestamp : Thu Jan 26 16:47:05 PST 2006 +-- \___\/\___\ +-- +-- Revision: +-- 01/26/06 - Initial version. +-- 08/23/06 - fixed CR 422403. +-- 10/16/06 - fixed CR 426962 +-- 10/19/06 - fixed CR 427370 +-- 10/26/06 - fixed CR 427914 +-- 12/07/06 - fixed CR 430517 +-- End Revision + +----- CELL RAMB16BWER ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library STD; +use STD.TEXTIO.all; + + + +library unisim; +use unisim.vpkg.all; + +entity RAMB16BWER is + + generic ( + + DATA_WIDTH_A : integer := 0; + DATA_WIDTH_B : integer := 0; + + DOA_REG : integer := 0 ; + DOB_REG : integer := 0 ; + + INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + INIT_A : bit_vector := X"000000000"; + INIT_B : bit_vector := X"000000000"; + + INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + + RSTTYPE : string := "SYNC"; + + SIM_COLLISION_CHECK : string := "ALL"; + + SRVAL_A : bit_vector := X"000000000"; + SRVAL_B : bit_vector := X"000000000"; + + WRITE_MODE_A : string := "WRITE_FIRST"; + WRITE_MODE_B : string := "WRITE_FIRST" + ); + + port( + DOA : out std_logic_vector (31 downto 0); + DOB : out std_logic_vector (31 downto 0); + DOPA : out std_logic_vector (3 downto 0); + DOPB : out std_logic_vector (3 downto 0); + + ADDRA : in std_logic_vector (13 downto 0); + ADDRB : in std_logic_vector (13 downto 0); + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector (31 downto 0); + DIB : in std_logic_vector (31 downto 0); + DIPA : in std_logic_vector (3 downto 0); + DIPB : in std_logic_vector (3 downto 0); + ENA : in std_ulogic; + ENB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + WEA : in std_logic_vector (3 downto 0); + WEB : in std_logic_vector (3 downto 0) + ); + +end RAMB16BWER; + +architecture RAMB16BWER_V of RAMB16BWER is + + +-- Constants + + constant MAX_ADDR: integer := 13; + + constant MAX_DI: integer := 31; + constant MAX_DIP: integer := 3; + constant MAX_WE: integer := 3; + + constant SYNC_PATH_DELAY : time := 100 ps; + + TYPE CollisionFlagType IS RECORD + active_port : integer; + read_write : boolean; + write_read : boolean; + write_write : boolean; + we : std_logic_vector(MAX_WE downto 0); + END RECORD; + + TYPE DataWidthType IS RECORD + diaw : integer; + dipaw : integer; + doaw : integer; + dopaw : integer; + dibw : integer; + dipbw : integer; + dobw : integer; + dopbw : integer; + END RECORD; + + TYPE ClsnXbufType IS RECORD + DO1_clsn : std_logic_vector(31 downto 0); + DOP1_clsn : std_logic_vector(3 downto 0); + MEM1_clsn : std_logic_vector(31 downto 0); + MEMP1_clsn : std_logic_vector(3 downto 0); + + DO2_clsn : std_logic_vector(31 downto 0); + DOP2_clsn : std_logic_vector(3 downto 0); + MEM2_clsn : std_logic_vector(31 downto 0); + MEMP2_clsn : std_logic_vector(3 downto 0); + END RECORD; + + TYPE memory_collision_type is (Read_A_Write_B, + Write_A_Read_B, + Write_A_Write_B, + Read_B_Write_A, + Write_B_Read_A, + Write_B_Write_A); + + constant SETUP_ALL : time := 1000 ps; + constant SETUP_READ_FIRST : time := 3000 ps; + +-- Procedures and Functions + +------------------------------------------------ +-- procedure ClkCollisionCheck +------------------------------------------------ +-- +-- Checks whether the time duration of rising +-- clka and clkb violates required setup time +-- between these clocks. +-- + procedure ClkCollisionCheck( + variable violation : out integer; + constant CheckEnabled : in boolean := false; + variable CLK1_time : in time := 0 ns; + variable CLK2_time : in time := 0 ns; + constant SETUP_ALL : in time := 0 ns; + constant SETUP_READ_FIRST : in time := 0 ns + ) is + + begin + + violation := 0; + if(CheckEnabled) then + if((CLK1_time > 0 ns ) and (CLK2_time > 0 ns )) then + if((CLK1_time - CLK2_time) = 0 ns ) then + violation := 3; + elsif ((CLK1_time - CLK2_time) < SETUP_ALL) then + violation := 11; + elsif ((CLK1_time - CLK2_time) < SETUP_READ_FIRST) then + violation := 12; + end if; + end if; + end if; + end ClkCollisionCheck; + +------------------------------------------------ +-- function AddrOverlapCheck +------------------------------------------------ +-- + + function AddrOverlapCheck( + d1w : in integer := 0; + d2w : in integer := 0; + addr1 : in std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + addr2 : in std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + zero_addr1 : in std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + zero_addr2 : in std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + we_segment : in integer := 0 + ) return boolean is + variable collision, port1_overlap, port2_overlap : boolean := false; + variable addr1_zero_int, addr2_zero_int, wea_index, INDEX1, INDEX2 : integer := -1; + variable tmp_addr1_zero, tmp_addr2_zero : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + variable zero_out : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + variable tmp_we : std_logic_vector(1 downto 0) := (others => '0'); + + + + + begin + INDEX1 := SLV_TO_INT(addr1(4 downto 0)); + INDEX2 := SLV_TO_INT(addr2(4 downto 0)); + + if(D1W >= D2W) then + zero_out := zero_addr1; + elsif(D1W < D2W) then + zero_out := zero_addr2; + end if; + + tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_out); + tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_out); + + addr1_zero_int := SLV_TO_INT(tmp_addr1_zero); + addr2_zero_int := SLV_TO_INT(tmp_addr2_zero); + +-- if((addr1_zero_int = addr2_zero_int) and ((INDEX1 + D1W) > we_segment * 8 ) and ((INDEX2 + D2W) > we_segment * 8 )) then + if(addr1_zero_int = addr2_zero_int) then + + case D1W is + --------- + when 1|2|4|8 => + --------- + tmp_we(1 downto 0) := addr1( 4 downto 3); + wea_index := SLV_TO_INT(tmp_we); + if(wea_index = we_segment) then + port1_overlap := true; + end if; + + --------- + when 16 => + --------- + + tmp_we(1) := addr1(4); + tmp_we(0) := '0'; + wea_index := SLV_TO_INT(tmp_we); + if(wea_index = we_segment) then + port1_overlap := true; + end if; + + tmp_we(1) := addr1(4); + tmp_we(0) := '1'; + wea_index := SLV_TO_INT(tmp_we); + if(wea_index = we_segment) then + port1_overlap := true; + end if; + + --------- + when 32 => + --------- + + port1_overlap := true; + + --------- + when others => null; + --------- + end case; + + + + case D2W is + --------- + when 1|2|4|8 => + --------- + tmp_we(1 downto 0) := addr2( 4 downto 3); + wea_index := SLV_TO_INT(tmp_we); + if(wea_index = we_segment) then + port2_overlap := true; + end if; + + --------- + when 16 => + --------- + + tmp_we(1) := addr2(4); + tmp_we(0) := '0'; + wea_index := SLV_TO_INT(tmp_we); + if(wea_index = we_segment) then + port2_overlap := true; + end if; + + tmp_we(1) := addr2(4); + tmp_we(0) := '1'; + wea_index := SLV_TO_INT(tmp_we); + if(wea_index = we_segment) then + port2_overlap := true; + end if; + + --------- + when 32 => + --------- + + port2_overlap := true; + + --------- + when others => null; + --------- + end case; + + end if; + + collision := (port1_overlap and port2_overlap); + return collision; + end; +------------------------------------------------ +-- procedure QkAddrOverlapChk +------------------------------------------------ +-- + + procedure QkAddrOverlapChk( + variable addr_overlap : out boolean; + variable data_widths : in DataWidthType; + variable addra : in std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + variable addrb : in std_logic_vector(MAX_ADDR downto 0) := (others => 'X') + ) is + variable addra_int, addrb_int, max_width : integer := -1; + variable tmp_addra_zero, tmp_addrb_zero : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + variable zero_data_out : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + variable zero_parity_out : std_logic_vector((MAX_ADDR-3) downto 0) := (others => 'X'); + + begin + addr_overlap := false; + zero_data_out := (others => '1'); + zero_parity_out := (others => '1'); + + max_width := data_widths.diaw; + + if(data_widths.doaw > max_width) then + max_width := data_widths.doaw; + end if; + + if(data_widths.dibw > max_width) then + max_width := data_widths.dibw; + end if; + + if(data_widths.dobw > max_width) then + max_width := data_widths.dobw; + end if; + + + case max_width is + + ------- + when 32 => + ------- + zero_data_out(4 downto 0) := (others => '0'); + zero_parity_out(1 downto 0) := (others => '0'); + + ------- + when 16 => + ------- + zero_data_out(3 downto 0) := (others => '0'); + zero_parity_out(0 downto 0) := (others => '0'); + + ------- + when 8 => + ------- + zero_data_out(2 downto 0) := (others => '0'); + + ------- + when 4 => + ------- + zero_data_out(1 downto 0) := (others => '0'); + + ------- + when 2 => + ------- + zero_data_out(0 downto 0) := (others => '0'); + + ------- + when others => + ------- + null; + + + end case; + + tmp_addra_zero := (addra(MAX_ADDR downto 0) and zero_data_out); + tmp_addrb_zero := (addrb(MAX_ADDR downto 0) and zero_data_out); + + addra_int := SLV_TO_INT(tmp_addra_zero); + addrb_int := SLV_TO_INT(tmp_addrb_zero); + + if(addra_int = addrb_int) then + addr_overlap := true; + end if; + + end QkAddrOverlapChk; + +------------------------------------------------ +-- procedure SameDataChk +------------------------------------------------ +-- +-- Checks whether the data written is the same +-- as in the memory, or in the case of both ports +-- writing whether the inputs are the same. +-- If true, then there is no collision +-- + procedure SameDataChk( + variable same_data : out boolean; + variable same_datap : out boolean; + constant MEM : in std_logic_vector(18431 downto 0); + constant di1 : in std_logic_vector(31 downto 0); + constant di2 : in std_logic_vector(31 downto 0); + constant dip1 : in std_logic_vector(3 downto 0); + constant dip2 : in std_logic_vector(3 downto 0); + variable addr1 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable addr2 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable addrp1 : in std_logic_vector(10 downto 0) := (others => 'X'); + variable addrp2 : in std_logic_vector(10 downto 0) := (others => 'X'); + variable wr_mode_1 : in std_logic_vector(1 downto 0) := "00"; + variable wr_mode_2 : in std_logic_vector(1 downto 0) := "00"; + constant we_segment : in integer := -1; + variable we1 : in std_ulogic := 'X'; + variable we2 : in std_ulogic := 'X'; + variable D1W : in integer := -1; + variable D1PW : in integer := -1; + variable D2W : in integer := -1; + variable D2PW : in integer := -1 + ) is + variable REM1 : integer := -1; + variable REM2 : integer := -1; + variable XOUT_BITS : integer := -1; + variable XOUT_BITS_1 : integer := -1; + variable XOUT_PBITS_1 : integer := 0; + variable INDEX, INDEXP, DATA_INDEX : integer := -1; + variable ADDRESS, ADDRESS_P, ADDRESS32_1, ADDRESS32P_1, ADDRESS32_2, ADDRESS32P_2 : integer := -1; + variable SMALL_ADDRESS32, SMALL_ADDRESS32P : integer := -1; + variable SMALL_DW : integer := -1; + + + variable TableRow : std_logic_vector(1 downto 0) := (others => '0'); + + variable cmp_d1_buf : std_logic_vector(7 downto 0) := (others => '0'); + variable cmp_d1p_buf : std_logic_vector(0 downto 0) := (others => '0'); + variable cmp_d2_buf : std_logic_vector(7 downto 0) := (others => '0'); + variable cmp_d2p_buf : std_logic_vector(0 downto 0) := (others => '0'); + variable cmp_mem_buf : std_logic_vector(7 downto 0) := (others => '0'); + variable cmp_memp_buf : std_logic_vector(0 downto 0) := (others => '0'); + + variable cmp_d1_buf32 : std_logic_vector(31 downto 0) := (others => '0'); + variable cmp_d1p_buf4 : std_logic_vector(3 downto 0) := (others => '0'); + variable cmp_d2_buf32 : std_logic_vector(31 downto 0) := (others => '0'); + variable cmp_d2p_buf4 : std_logic_vector(3 downto 0) := (others => '0'); + + variable tmp_cmp_d1_buf : std_logic_vector(7 downto 0) := (others => '0'); + variable tmp_cmp_d1p_buf : std_logic_vector(0 downto 0) := (others => '0'); + variable tmp_cmp_d2_buf : std_logic_vector(7 downto 0) := (others => '0'); + variable tmp_cmp_d2p_buf : std_logic_vector(0 downto 0) := (others => '0'); + + variable memp_fp : std_logic_vector(3 downto 0) := (others => '0'); + + begin + +-- ################################################################## +----------------------------------------------------------------------- +------------ Port 1 Active Clock ------------------------------------- +----------------------------------------------------------------------- + + same_data := false; + same_datap := false; + + if((D1W >= D2W) and (D2W < 8)) then + INDEX := SLV_TO_INT(addr2(4 downto 0)); + elsif((D2W >= D1W) and (D1W < 8)) then + INDEX := SLV_TO_INT(addr1(4 downto 0)); + else + INDEX := we_segment * 8; + end if; + + + --- Data Bits --- + + REM1 := D1W REM 8; + REM2 := D2W REM 8; + + -- find the minimum data bits to overlap + if((REM1 = 0) and (REM2 = 0)) then + XOUT_BITS := 8 ; + elsif(REM1 = 0) then + XOUT_BITS := REM2; + elsif(REM2 = 0) then + XOUT_BITS := REM1; + elsif(REM1 > REM2) then + XOUT_BITS := REM2 ; + elsif (REM1 <= REM2) then + XOUT_BITS := REM1 ; + end if; + + XOUT_BITS_1 := XOUT_BITS - 1 ; + + + if(D1W <= D2W) then + SMALL_DW := D1W; + ADDRESS := SLV_TO_INT(addr1); + SMALL_ADDRESS32:= SLV_TO_INT(addr1(4 downto 0)); + elsif(D1W > D2W) then + SMALL_DW := D2W; + ADDRESS := SLV_TO_INT(addr2); + SMALL_ADDRESS32:= SLV_TO_INT(addr2(4 downto 0)); + end if; + + if(D1PW <= D2PW) then + ADDRESS_P := SLV_TO_INT(addrp1); + SMALL_ADDRESS32P:= SLV_TO_INT(addrp1(1 downto 0)); + elsif(D1PW > D2PW) then + ADDRESS_P := SLV_TO_INT(addrp2); + SMALL_ADDRESS32P:= SLV_TO_INT(addrp2(1 downto 0)); + end if; + + INDEXP := we_segment; + + TableRow := (we1 & we2); + + cmp_d1_buf := (others => '0'); + cmp_d1p_buf := (others => '0'); + cmp_d2_buf := (others => '0'); + cmp_d2p_buf := (others => '0'); + cmp_mem_buf := (others => '0'); + cmp_memp_buf := (others => '0'); + +--================================================================================================== + ADDRESS32_1 := SLV_TO_INT(addr1(4 downto 0)); + ADDRESS32P_1 := SLV_TO_INT(addrp1(1 downto 0)); + cmp_d1_buf32(((D1W - 1) + ADDRESS32_1) downto ADDRESS32_1) := di1((D1W - 1) downto 0); + cmp_d1p_buf4(((D1PW - 1) + ADDRESS32P_1) downto ADDRESS32P_1) := dip1((D1PW - 1) downto 0); + + ADDRESS32_2 := SLV_TO_INT(addr2(4 downto 0)); + ADDRESS32P_2 := SLV_TO_INT(addrp2(1 downto 0)); + cmp_d2_buf32(((D2W - 1) + ADDRESS32_2) downto ADDRESS32_2) := di2((D2W - 1) downto 0); + cmp_d2p_buf4(((D2PW - 1) + ADDRESS32P_2) downto ADDRESS32P_2) := dip2((D2PW - 1 ) downto 0); + + case SMALL_DW is + when 1|2|4 => + cmp_mem_buf(XOUT_BITS_1 downto 0) := MEM((XOUT_BITS_1 + ADDRESS ) downto (ADDRESS)); + + tmp_cmp_d1_buf(XOUT_BITS_1 downto 0) := cmp_d1_buf32((XOUT_BITS_1 + SMALL_ADDRESS32 ) downto SMALL_ADDRESS32); + tmp_cmp_d2_buf(XOUT_BITS_1 downto 0) := cmp_d2_buf32((XOUT_BITS_1 + SMALL_ADDRESS32 ) downto SMALL_ADDRESS32); + + when 8 => + cmp_mem_buf(XOUT_BITS_1 downto 0) := MEM((XOUT_BITS_1 + ADDRESS ) downto (ADDRESS)); + cmp_memp_buf(XOUT_PBITS_1 downto 0) := MEM((XOUT_PBITS_1 + 16384 + ADDRESS_P) downto (ADDRESS_P + 16384)); + + tmp_cmp_d1_buf(XOUT_BITS_1 downto 0) := cmp_d1_buf32((XOUT_BITS_1 + SMALL_ADDRESS32 ) downto SMALL_ADDRESS32); + tmp_cmp_d1p_buf(XOUT_PBITS_1 downto 0) := cmp_d1p_buf4((XOUT_PBITS_1 + SMALL_ADDRESS32P) downto SMALL_ADDRESS32P); + + tmp_cmp_d2_buf(XOUT_BITS_1 downto 0) := cmp_d2_buf32((XOUT_BITS_1 + SMALL_ADDRESS32 ) downto SMALL_ADDRESS32); + tmp_cmp_d2p_buf(XOUT_PBITS_1 downto 0) := cmp_d2p_buf4((XOUT_PBITS_1 + SMALL_ADDRESS32P) downto SMALL_ADDRESS32P); + + when 16 => + if((we_segment = 0) or (we_segment = 2)) then + DATA_INDEX := 0; + elsif((we_segment = 1) or (we_segment = 3))then + DATA_INDEX := 1; + end if; + + cmp_mem_buf(XOUT_BITS_1 downto 0) := MEM((XOUT_BITS_1 + ADDRESS + DATA_INDEX*8 ) downto (DATA_INDEX*8 + ADDRESS)); + cmp_memp_buf(XOUT_PBITS_1 downto 0) := MEM((XOUT_PBITS_1 + 16384 + DATA_INDEX + ADDRESS_P) downto (DATA_INDEX + ADDRESS_P + 16384)); + tmp_cmp_d1_buf(XOUT_BITS_1 downto 0) := cmp_d1_buf32((XOUT_BITS_1 + we_segment*8 ) downto we_segment*8); + tmp_cmp_d1p_buf(XOUT_PBITS_1 downto 0) := cmp_d1p_buf4((XOUT_PBITS_1 + we_segment*1) downto we_segment*1); + + tmp_cmp_d2_buf(XOUT_BITS_1 downto 0) := cmp_d2_buf32((XOUT_BITS_1 + we_segment*8 ) downto we_segment*8); + tmp_cmp_d2p_buf(XOUT_PBITS_1 downto 0) := cmp_d2p_buf4((XOUT_PBITS_1 + we_segment*1) downto we_segment*1); + + when 32 => + cmp_mem_buf(XOUT_BITS_1 downto 0) := MEM((XOUT_BITS_1 + INDEX + ADDRESS ) downto (INDEX + ADDRESS)); + cmp_memp_buf(XOUT_PBITS_1 downto 0) := MEM((XOUT_PBITS_1 + 16384 + INDEXP + ADDRESS_P) downto (INDEXP + ADDRESS_P + 16384)); + + tmp_cmp_d1_buf(XOUT_BITS_1 downto 0) := cmp_d1_buf32((XOUT_BITS_1 + we_segment*8 ) downto we_segment*8); + tmp_cmp_d1p_buf(XOUT_PBITS_1 downto 0) := cmp_d1p_buf4((XOUT_PBITS_1 + we_segment*1) downto we_segment*1); + + tmp_cmp_d2_buf(XOUT_BITS_1 downto 0) := cmp_d2_buf32((XOUT_BITS_1 + we_segment*8 ) downto we_segment*8); + tmp_cmp_d2p_buf(XOUT_PBITS_1 downto 0) := cmp_d2p_buf4((XOUT_PBITS_1 + we_segment*1) downto we_segment*1); + + when others => null; + + end case; + + case TableRow is +---=============================================================================== +--- wea&web = 11 +---=============================================================================== + ---- + when "11" => + ---- + + memp_fp := MEM(( 3 + 16384 + ADDRESS_P) downto (16384 + ADDRESS_P)); + + + if((tmp_cmp_d1_buf = tmp_cmp_d2_buf) and (tmp_cmp_d2_buf = cmp_mem_buf)) then + same_data := true; + end if; + + -- Parity + if((D1PW /= 0) and (D2PW /= 0)) then + if((tmp_cmp_d1p_buf = tmp_cmp_d2p_buf) and (tmp_cmp_d2p_buf = cmp_memp_buf)) then + same_datap := true; + end if; + end if; +---=============================================================================== +--- wea&web = 01 +---=============================================================================== + ---- + when "01" => + ---- + + if(tmp_cmp_d2_buf = cmp_mem_buf) then + same_data := true; + end if; + + -- Parity + if((D1PW /= 0) and (D2PW /= 0)) then + if(tmp_cmp_d2p_buf = cmp_memp_buf) then + same_datap := true; + end if; + end if; +---=============================================================================== +--- wea&web = 10 +---=============================================================================== + ---- + when "10" => + ---- + if(tmp_cmp_d1_buf = cmp_mem_buf) then + same_data := true; + end if; + + -- Parity + if((D1PW /= 0) and (D2PW /= 0)) then + if(tmp_cmp_d1p_buf = cmp_memp_buf) then + same_datap := true; + end if; + end if; +---=============================================================================== +--- others +---=============================================================================== + + --------- + when others => + --------- + null; + end case; + + end SameDataChk; + +------------------------------------------------ +-- procedure CollisionTableRest +------------------------------------------------ +-- +-- Checks whether the time duration of rising +-- clka and clkb violates required setup time +-- between these clocks. +-- + procedure CollisionTableRest( + variable clsn_bufs : out ClsnXbufType; + variable same_data_flg : out boolean; + variable same_datap_flg : out boolean; + constant MEM : in std_logic_vector(18431 downto 0); + constant di1 : in std_logic_vector(31 downto 0); + constant di2 : in std_logic_vector(31 downto 0); + constant dip1 : in std_logic_vector(3 downto 0); + constant dip2 : in std_logic_vector(3 downto 0); + variable addr1 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable addr2 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable addrp1 : in std_logic_vector(10 downto 0) := (others => 'X'); + variable addrp2 : in std_logic_vector(10 downto 0) := (others => 'X'); + variable wr_mode_1 : in std_logic_vector(1 downto 0) := "00"; + variable wr_mode_2 : in std_logic_vector(1 downto 0) := "00"; + constant we_segment : in integer := -1; + constant violation : in integer := -1; + variable we1 : in std_ulogic := 'X'; + variable we2 : in std_ulogic := 'X'; + variable D1W : in integer := -1; + variable D1PW : in integer := -1; + variable D2W : in integer := -1; + variable D2PW : in integer := -1 + ) is + variable REM1 : integer := -1; + variable REM2 : integer := -1; + variable XOUT_BITS : integer := -1; + variable XOUT_BITS_1 : integer := -1; + variable INDEX, INDEX_P : integer := -1; + + variable TableRow : std_logic_vector(5 downto 0) := (others => '0'); + variable we1we2 : std_logic_vector(1 downto 0) := (others => '0'); + + variable same_data : boolean := false; + variable same_datap : boolean := false; + variable SAME_DATA_CHECK_DISABLED : boolean := true; + + begin + +-- ################################################################## +----------------------------------------------------------------------- +------------ Port 1 Active Clock ------------------------------------- +----------------------------------------------------------------------- + + + if((D1W >= D2W) and (D2W < 8)) then + INDEX := SLV_TO_INT(addr2(4 downto 0)); + elsif((D2W >= D1W) and (D1W < 8)) then + INDEX := SLV_TO_INT(addr1(4 downto 0)); + else + INDEX := we_segment * 8; + end if; + + + --- Data Bits --- + + REM1 := D1W REM 8; + REM2 := D2W REM 8; + + -- find the minimum data bits to overlap + if((REM1 = 0) and (REM2 = 0)) then + XOUT_BITS := 8 ; + elsif(REM1 = 0) then + XOUT_BITS := REM2; + elsif(REM2 = 0) then + XOUT_BITS := REM1; + elsif(REM1 > REM2) then + XOUT_BITS := REM2 ; + elsif (REM1 <= REM2) then + XOUT_BITS := REM1 ; + end if; + + XOUT_BITS_1 := XOUT_BITS - 1 ; + + + + --- Parity Bits --- + + -- find the minimum parity bits to overlap + + if(D1PW >= D2PW) then + INDEX_P := SLV_TO_INT(addrp2(1 downto 0)); + else + INDEX_P := SLV_TO_INT(addrp1(1 downto 0)); + end if; +--=============================================================================== +-- Same Data Check for both Data and Parity +-- If Data/Parity_Data are the same in Ports A and B, and the contents of the +-- Memory/Parity_memory are the same as the Data, then here is no collision +--=============================================================================== + + + SameDataChk( + same_data => same_data, + same_datap => same_datap, + mem => mem, + di1 => di1, + di2 => di2, + dip1 => dip1, + dip2 => dip2, + addr1 => addr1, + addr2 => addr2, + addrp1 => addrp1, + addrp2 => addrp2, + wr_mode_1 => wr_mode_1, + wr_mode_2 => wr_mode_2, + we_segment => we_segment, + we1 => we1, + we2 => we2, + D1W => D1W, + D1PW => D1PW, + D2W => D2W, + D2PW => D2PW + ); + +---=============================================================================== +---=============================================================================== +-- DEBUG +if(SAME_DATA_CHECK_DISABLED) then + same_data := false; + same_datap := false; +end if; + + same_data_flg := same_data; + same_datap_flg := same_datap; + + TableRow := (wr_mode_1 & wr_mode_2 & we1 & we2); + case TableRow is +---=============================================================================== +--- wea&web = 11 +---=============================================================================== + ---- + when "000011" | "010011" => + ---- + if((violation = 3) or (violation = 11)) then + if(not same_data) then + -- port 1 + clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + -- port 2 + clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + end if; + if(not same_datap) then + -- parity port 1 + if((D1PW /= 0) and (D2PW /= 0)) then +-- clsn_bufs.DOP1_clsn((INDEX_P + (we_segment * 1)) downto (INDEX_P + (we_segment * 1))) := (others => 'X'); + clsn_bufs.DOP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + -- parity port 2 + if((D1PW /= 0) and (D2PW /= 0)) then +-- clsn_bufs.DOP2_clsn((INDEX_P + (we_segment * 1)) downto (INDEX_P + (we_segment * 1))) := (others => 'X'); + clsn_bufs.DOP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + + end if; + + ---- + when "001011" | "011011" => + ---- + if((violation = 3) or (violation = 11)) then + if(not same_data) then + -- port 1 + clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + -- port 2 + clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + end if; + if(not same_datap) then + -- parity port 1 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + end if; + ---- + when "000111" | "010111" => + ---- + if((violation = 3) or (violation = 11) or (violation = 12)) then + if(not same_data) then + -- port 1 + clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + -- port 2 + clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + end if; + if(not same_datap) then + -- parity port 1 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + -- parity port 2 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + end if; + + ---- + when "100011" => + ---- + if((violation = 3) or (violation = 11)) then + if(not same_data) then + -- port 1 + clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + -- port 2 + clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + end if; + + if(not same_datap) then + -- parity port 1 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + -- parity port 2 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + + end if; + + ---- + when "100111" => + ---- + if((violation = 3) or (violation = 11) or (violation = 12) ) then + if(not same_data) then + -- port 1 + clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + -- port 2 + clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + end if; + + if(not same_datap) then + -- parity port 1 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + -- parity port 2 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + + end if; + ---- + when "101011" => + ---- + if((violation = 3) or (violation = 11)) then + if(not same_data) then + -- port 1 + clsn_bufs.MEM1_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + -- port 2 + clsn_bufs.MEM2_clsn((INDEX + XOUT_BITS_1) downto INDEX ) := (others => 'X'); + end if; + if(not same_datap) then + if((D1PW /= 0) and (D2PW /= 0)) then + -- parity port 1 + clsn_bufs.MEMP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + -- parity port 2 + clsn_bufs.MEMP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + end if; + +---=============================================================================== +--- wea&web = 01 +---=============================================================================== + ---- + when "000001" | "010001" | "100001" => + ---- + if((violation = 3) or (violation = 11)) then + if(not same_data) then + -- port 1 + clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + end if; + if(not same_datap) then + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + end if; + ---- + when "000101" | "010101" | "100101" => + ---- + if((violation = 11) or (violation = 12)) then + if(not same_data) then + -- port 1 + clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + end if; + if(not same_datap) then + -- parity port 1 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + + end if; + ---- + when "001001" | "011001" | "101001" => + ---- + if((violation = 3) or (violation = 11)) then + if(not same_data) then + -- port 1 + clsn_bufs.DO1_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + end if; + if(not same_datap) then + -- parity port 1 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP1_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + end if; + +---=============================================================================== +--- wea&web = 10 +---=============================================================================== + + ---- + when "000010" | "000110" | "001010" => + ---- + if((violation = 3) or (violation = 11)) then + if(not same_data) then + -- port 1 + clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + end if; + if(not same_datap) then + -- parity port 1 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + end if; + ---- + when "100010" | "100110" | "101010" => + ---- + if((violation = 3) or (violation = 11)) then + if(not same_data) then + -- port 1 + clsn_bufs.DO2_clsn((INDEX + XOUT_BITS_1 ) downto INDEX) := (others => 'X'); + end if; + if(not same_datap) then + -- parity port 1 + if((D1PW /= 0) and (D2PW /= 0)) then + clsn_bufs.DOP2_clsn((we_segment * 1) downto (we_segment * 1)) := (others => 'X'); + end if; + end if; + + end if; + +---=============================================================================== +--- others +---=============================================================================== + + --------- + when others => + --------- + null; + end case; + + end CollisionTableRest; + +------------------------------------------------ +-- procedure PreProcessWe1We2 +------------------------------------------------ +-- +-- Checks whether the time duration of rising +-- clka and clkb violates required setup time +-- between these clocks. +-- + procedure PreProcessWe1We2( + variable clsn_bufs : out ClsnXbufType; + variable clsn_Type : out CollisionFlagType; + constant memory : in std_logic_vector(18431 downto 0); + constant di1 : in std_logic_vector(31 downto 0) := (others => 'X'); + constant di2 : in std_logic_vector(31 downto 0) := (others => 'X'); + constant dip1 : in std_logic_vector(3 downto 0) := (others => 'X'); + constant dip2 : in std_logic_vector(3 downto 0) := (others => 'X'); + variable addr1 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable addr2 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable we1 : in std_logic_vector(3 downto 0) := (others => 'X'); + variable we2 : in std_logic_vector(3 downto 0) := (others => 'X'); + variable zero_read_1 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable zero_readp_1 : in std_logic_vector(10 downto 0) := (others => 'X'); + variable zero_write_1 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable zero_writep_1 : in std_logic_vector(10 downto 0) := (others => 'X'); + variable zero_read_2 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable zero_readp_2 : in std_logic_vector(10 downto 0) := (others => 'X'); + variable zero_write_2 : in std_logic_vector(13 downto 0) := (others => 'X'); + variable zero_writep_2 : in std_logic_vector(10 downto 0) := (others => 'X'); + variable wr_mode_1 : in std_logic_vector(1 downto 0) := "00"; + variable wr_mode_2 : in std_logic_vector(1 downto 0) := "00"; + constant violation : in integer := -1; + variable DI1W : in integer := -1; + variable DIP1W : in integer := -1; + variable DI2W : in integer := -1; + variable DIP2W : in integer := -1; + variable DO1W : in integer := -1; + variable DOP1W : in integer := -1; + variable DO2W : in integer := -1; + variable DOP2W : in integer := -1 + ) is + + variable we1we2 : std_logic_vector(1 downto 0) := "XX"; + variable zero_addr1 : std_logic_vector(13 downto 0) := (others => 'X'); + variable zero_addr2 : std_logic_vector(13 downto 0) := (others => 'X'); + variable zero_parity_addr1 : std_logic_vector(10 downto 0) := (others => 'X'); + variable zero_parity_addr2 : std_logic_vector(10 downto 0) := (others => 'X'); + variable tmp_addr1_zero : std_logic_vector(13 downto 0) := (others => 'X'); + variable tmp_addr2_zero : std_logic_vector(13 downto 0) := (others => 'X'); + variable tmp_parity_addr1_zero : std_logic_vector(10 downto 0) := (others => 'X'); + variable tmp_parity_addr2_zero : std_logic_vector(10 downto 0) := (others => 'X'); + + + variable tmp_we1 : std_ulogic := 'X'; + variable tmp_we2 : std_ulogic := 'X'; + variable j : integer := 0; + + variable same_data_flg : boolean := false; + variable same_datap_flg : boolean := false; + + begin + + clsn_type.read_write := false; + clsn_type.write_read := false; + clsn_type.write_write := false; + + for i in 0 to 3 loop + we1we2 := we1(i)&we2(i); + clsn_type.we(i) := '0'; + case we1we2 is + --------- + when "00" => + --------- + null; + + --------- + when "01" => + --------- + same_data_flg := false; + same_datap_flg := false; + + zero_addr1 := zero_read_1; + zero_addr2 := zero_write_2; + + zero_parity_addr1 := zero_readp_1; + zero_parity_addr2 := zero_writep_2; + + tmp_we1 := '0'; + tmp_we2 := '1'; + + if(AddrOverlapCheck(DO1W, DI2W, addr1, addr2, zero_addr1, zero_addr2,i)) then + + tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1); + tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2); + + tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1; + tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2; + +-- FP fixed false message for DSP group 12/06/04 + + clsn_type.read_write := true; + clsn_type.we(i) := '1'; + + if((wr_mode_2 = "01")) then + clsn_type.read_write := false; + clsn_type.we(i) := '0'; + end if; + + + CollisionTableRest( + same_data_flg => same_data_flg, + same_datap_flg => same_datap_flg, + clsn_bufs => clsn_bufs, + mem => memory, + di1 => di1, + di2 => di2, + dip1 => dip1, + dip2 => dip2, + addr1 => tmp_addr1_zero, + addr2 => tmp_addr2_zero, + addrp1 => tmp_parity_addr1_zero, + addrp2 => tmp_parity_addr2_zero, + wr_mode_1 => wr_mode_1, + wr_mode_2 => wr_mode_2, + violation => violation, + we_segment => i, + we1 => tmp_we1, + we2 => tmp_we2, + D1W => DO1W, + D1PW => DOP1W, + D2W => DI2W, + D2PW => DIP2W + ); + end if; + --------- + when "10" => + --------- + same_data_flg := false; + same_datap_flg := false; + + zero_addr1 := zero_write_1; + zero_addr2 := zero_read_2; + + zero_parity_addr1 := zero_writep_1; + zero_parity_addr2 := zero_readp_2; + + tmp_we1 := '1'; + tmp_we2 := '0'; + + + if(AddrOverlapCheck(DI1W, DO2W, addr1, addr2, zero_addr1, zero_addr2,i)) then + + tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1); + tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2); + + tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1; + tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2; + + clsn_type.write_read := true; + clsn_type.we(i) := '1'; + +-- FP fixed false message for DSP group 12/06/04 +-- if((violation = 12) or (wr_mode_1 = "01")) then + if((wr_mode_1 = "01")) then + clsn_type.write_read := false; + clsn_type.we(i) := '0'; + end if; + + CollisionTableRest( + same_data_flg => same_data_flg, + same_datap_flg => same_datap_flg, + clsn_bufs => clsn_bufs, + mem => memory, + di1 => di1, + di2 => di2, + dip1 => dip1, + dip2 => dip2, + addr1 => tmp_addr1_zero, + addr2 => tmp_addr2_zero, + addrp1 => tmp_parity_addr1_zero, + addrp2 => tmp_parity_addr2_zero, + wr_mode_1 => wr_mode_1, + wr_mode_2 => wr_mode_2, + violation => violation, + we_segment => i, + we1 => tmp_we1, + we2 => tmp_we2, + D1W => DI1W, + D1PW => DIP1W, + D2W => DO2W, + D2PW => DOP2W + ); + end if; + --------- + when "11" => + --------- + same_data_flg := false; + same_datap_flg := false; + + zero_addr1 := zero_write_1; + zero_addr2 := zero_write_2; + + zero_parity_addr1 := zero_writep_1; + zero_parity_addr2 := zero_writep_2; + + tmp_we1 := '1'; + tmp_we2 := '1'; + + if(AddrOverlapCheck(DI1W, DI2W, addr1, addr2, zero_addr1, zero_addr2,i)) then + + tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1); + tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2); + + tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1; + tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2; + + if(violation = 12) then + if(wr_mode_2 = "01") then + clsn_type.write_write := true; + clsn_type.we(i) := '1'; + end if; + else + clsn_type.write_write := true; + clsn_type.we(i) := '1'; + end if; + + CollisionTableRest( + same_data_flg => same_data_flg, + same_datap_flg => same_datap_flg, + clsn_bufs => clsn_bufs, + mem => memory, + di1 => di1, + di2 => di2, + dip1 => dip1, + dip2 => dip2, + addr1 => tmp_addr1_zero, + addr2 => tmp_addr2_zero, + addrp1 => tmp_parity_addr1_zero, + addrp2 => tmp_parity_addr2_zero, + wr_mode_1 => wr_mode_1, + wr_mode_2 => wr_mode_2, + violation => violation, + we_segment => i, + we1 => tmp_we1, + we2 => tmp_we2, + D1W => DI1W, + D1PW => DIP1W, + D2W => DI2W, + D2PW => DIP2W + ); + end if; + + if((DI1W /= DO1W) or (DI2W /= DO2W)) then +--FP disabled the cross check call +-- tmp_we1 := '1'; +-- tmp_we2 := '0'; + tmp_we1 := '0'; + tmp_we2 := '0'; + + zero_addr1 := zero_write_1; + zero_addr2 := zero_read_2; + + zero_parity_addr1 := zero_writep_1; + zero_parity_addr2 := zero_readp_2; + + if(AddrOverlapCheck(DI1W, DO2W, addr1, addr2, zero_addr1, zero_addr2,i)) then + + tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1); + tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2); + + tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1; + tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2; + + CollisionTableRest( + same_data_flg => same_data_flg, + same_datap_flg => same_datap_flg, + clsn_bufs => clsn_bufs, + mem => memory, + di1 => di1, + di2 => di2, + dip1 => dip1, + dip2 => dip2, + addr1 => tmp_addr1_zero, + addr2 => tmp_addr2_zero, + addrp1 => tmp_parity_addr1_zero, + addrp2 => tmp_parity_addr2_zero, + wr_mode_1 => wr_mode_1, + wr_mode_2 => wr_mode_2, + violation => violation, + we_segment => i, + we1 => tmp_we1, + we2 => tmp_we2, + D1W => DI1W, + D1PW => DIP1W, + D2W => DO2W, + D2PW => DOP2W + ); + end if; + +--FP disabled the cross check call +-- tmp_we1 := '0'; +-- tmp_we2 := '1'; + tmp_we1 := '0'; + tmp_we2 := '0'; + + zero_addr1 := zero_read_1; + zero_addr2 := zero_write_2; + + zero_parity_addr1 := zero_readp_1; + zero_parity_addr2 := zero_writep_2; + + if(AddrOverlapCheck(DO1W, DI2W, addr1, addr2, zero_addr1, zero_addr2,i)) then + + tmp_addr1_zero := (addr1(MAX_ADDR downto 0) and zero_addr1); + tmp_addr2_zero := (addr2(MAX_ADDR downto 0) and zero_addr2); + + tmp_parity_addr1_zero := addr1(13 downto 3) and zero_parity_addr1; + tmp_parity_addr2_zero := addr2(13 downto 3) and zero_parity_addr2; + + CollisionTableRest( + same_data_flg => same_data_flg, + same_datap_flg => same_datap_flg, + clsn_bufs => clsn_bufs, + mem => memory, + di1 => di1, + di2 => di2, + dip1 => dip1, + dip2 => dip2, + addr1 => tmp_addr1_zero, + addr2 => tmp_addr2_zero, + addrp1 => tmp_parity_addr1_zero, + addrp2 => tmp_parity_addr2_zero, + wr_mode_1 => wr_mode_1, + wr_mode_2 => wr_mode_2, + violation => violation, + we_segment => i, + we1 => tmp_we1, + we2 => tmp_we2, + D1W => DO1W, + D1PW => DOP1W, + D2W => DI2W, + D2PW => DIP2W + ); + + end if; + end if; + + when others => + null; + + end case; + + end loop; + + end PreProcessWe1We2; +------------------------------------------------ +-- procedure Memory_Collision_Msg_ramb16 +------------------------------------------------ +-- This is almost the same procedure as the procedure for V2 ram collision +-- except that is is local to the model (since this is the only one that +-- calls this procedure + Procedure Memory_Collision_Msg_ramb16 ( + CONSTANT HeaderMsg : IN STRING := " Memory Collision Error on "; + CONSTANT EntityName : IN STRING := ""; + CONSTANT InstanceName : IN STRING := ""; + constant collision_type : in memory_collision_type; + constant address_1 : in std_logic_vector; + constant address_2 : in std_logic_vector; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := Error + + + ) IS + variable current_time : time := NOW; + variable string_length_1 : integer; + variable string_length_2 : integer; + + VARIABLE Message : LINE; + BEGIN + if ((address_1'length mod 4) = 0) then + string_length_1 := address_1'length/4; + elsif ((address_1'length mod 4) > 0) then + string_length_1 := address_1'length/4 + 1; + end if; + if ((address_2'length mod 4) = 0) then + string_length_2 := address_2'length/4; + elsif ((address_2'length mod 4) > 0) then + string_length_2 := address_2'length/4 + 1; + end if; +-- if ((collision_type = Read_A_Write_B) or (collision_type = Read_B_Write_A)) then + if ((collision_type = Read_A_Write_B) or (collision_type = Write_A_Read_B) or + (collision_type = Read_B_Write_A) or (collision_type = Write_B_Read_A)) then + Write ( Message, HeaderMsg); + Write ( Message, EntityName); + Write ( Message, STRING'(": ")); + Write ( Message, InstanceName); + Write ( Message, STRING'(" at simulation time ")); + Write ( Message, current_time); + Write ( Message, STRING'(".")); + Write ( Message, LF ); + Write ( Message, STRING'(" A read was performed on address ")); + Write ( Message, SLV_TO_HEX(address_1, string_length_1)); + Write ( Message, STRING'(" (hex) ")); +-- if (collision_type = Read_A_Write_B) then + if ((collision_type = Read_A_Write_B) or (collision_type = Write_B_Read_A))then + Write ( Message, STRING'("of port A while a write was requested to the same address on Port B ")); + Write ( Message, STRING'(" The write will be successful however the read value is unknown until the next CLKA cycle ")); +-- elsif(collision_type = Read_B_Write_A) then + elsif((collision_type = Read_B_Write_A) or (collision_type = Write_A_Read_B)) then + Write ( Message, STRING'("of port B while a write was requested to the same address on Port A ")); + Write ( Message, STRING'(" The write will be successful however the read value is unknown until the next CLKB cycle ")); + end if; + elsif ((collision_type = Write_A_Write_B) or (collision_type = Write_B_Write_A)) then + Write ( Message, HeaderMsg); + Write ( Message, EntityName); + Write ( Message, STRING'(": ")); + Write ( Message, InstanceName); + Write ( Message, STRING'(" at simulation time ")); + Write ( Message, current_time); + Write ( Message, STRING'(".")); + Write ( Message, LF ); + Write ( Message, STRING'(" A write was requested to the same address simultaneously at both Port A and Port B of the RAM.")); + Write ( Message, STRING'(" The contents written to the RAM at address location ")); + Write ( Message, SLV_TO_HEX(address_1, string_length_1)); + Write ( Message, STRING'(" (hex) ")); + Write ( Message, STRING'("of Port A and address location ")); + Write ( Message, SLV_TO_HEX(address_2, string_length_2)); + Write ( Message, STRING'(" (hex) ")); + Write ( Message, STRING'("of Port B are unknown. ")); + end if; + ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity; + + DEALLOCATE (Message); + END Memory_Collision_Msg_ramb16; + +------------------ END Procedures/Functions ------------------------------ + + signal ADDRA_ipd : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + signal CLKA_ipd : std_ulogic := 'X'; + signal DIA_ipd : std_logic_vector(MAX_DI downto 0) := (others => 'X'); + signal DIPA_ipd : std_logic_vector(MAX_DIP downto 0) := (others => 'X'); + signal ENA_ipd : std_ulogic := 'X'; + signal RSTA_ipd : std_ulogic := 'X'; + signal REGCEA_ipd : std_ulogic := 'X'; + signal WEA_ipd : std_logic_vector(MAX_WE downto 0) := (others => 'X'); + + signal ADDRB_ipd : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + signal CLKB_ipd : std_ulogic := 'X'; + signal DIB_ipd : std_logic_vector(MAX_DI downto 0) := (others => 'X'); + signal DIPB_ipd : std_logic_vector(MAX_DIP downto 0) := (others => 'X'); + signal ENB_ipd : std_ulogic := 'X'; + signal RSTB_ipd : std_ulogic := 'X'; + signal REGCEB_ipd : std_ulogic := 'X'; + signal WEB_ipd : std_logic_vector(MAX_WE downto 0) := (others => 'X'); + + signal GSR : std_ulogic := '0'; + signal GSR_ipd : std_ulogic := 'X'; + + signal GSR_dly : std_ulogic := 'X'; + + signal ADDRA_dly : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + signal CLKA_dly : std_ulogic := 'X'; + signal DIA_dly : std_logic_vector(MAX_DI downto 0) := (others => 'X'); + signal DIPA_dly : std_logic_vector(MAX_DIP downto 0) := (others => 'X'); + signal ENA_dly : std_ulogic := 'X'; + signal GSR_CLKA_dly : std_ulogic := 'X'; + signal RSTA_dly : std_ulogic := 'X'; + signal REGCEA_dly : std_ulogic := 'X'; + signal WEA_dly : std_logic_vector(MAX_WE downto 0) := (others => 'X'); + + signal ADDRB_dly : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + signal CLKB_dly : std_ulogic := 'X'; + signal DIB_dly : std_logic_vector(MAX_DI downto 0) := (others => 'X'); + signal DIPB_dly : std_logic_vector(MAX_DIP downto 0) := (others => 'X'); + signal ENB_dly : std_ulogic := 'X'; + signal GSR_CLKB_dly : std_ulogic := 'X'; + signal RSTB_dly : std_ulogic := 'X'; + signal REGCEB_dly : std_ulogic := 'X'; + signal WEB_dly : std_logic_vector(MAX_WE downto 0) := (others => 'X'); + + signal DOA_viol : std_logic_vector(MAX_DI downto 0); + signal DOPA_viol : std_logic_vector(3 downto 0); + signal DOB_viol : std_logic_vector(MAX_DI downto 0); + signal DOPB_viol : std_logic_vector(3 downto 0); + + signal DOA_regist : std_logic_vector(MAX_DI downto 0); + signal DOPA_regist : std_logic_vector(3 downto 0); + signal DOB_regist : std_logic_vector(MAX_DI downto 0); + signal DOPB_regist : std_logic_vector(3 downto 0); + + signal DOA_mux : std_logic_vector(MAX_DI downto 0); + signal DOPA_mux : std_logic_vector(3 downto 0); + signal DOB_mux : std_logic_vector(MAX_DI downto 0); + signal DOPB_mux : std_logic_vector(3 downto 0); + + + signal DIAW : integer; + signal DIAW_1 : integer; + signal DIBW : integer; + signal DIBW_1 : integer; + signal DIPAW : integer; + signal DIPAW_1 : integer; + signal DIPBW : integer; + signal DIPBW_1 : integer; + + signal DOAW : integer; + signal DOAW_1 : integer; + signal DOBW : integer; + signal DOBW_1 : integer; + signal DOPAW : integer; + signal DOPAW_1 : integer; + signal DOPBW : integer; + signal DOPBW_1 : integer; + + signal INI_A_sig : std_logic_vector (35 downto 0) := (others => 'X'); + signal INI_B_sig : std_logic_vector (35 downto 0) := (others => 'X'); + + signal SRVA_A_sig : std_logic_vector (35 downto 0) := (others => 'X'); + signal SRVA_B_sig : std_logic_vector (35 downto 0) := (others => 'X'); + + signal rst_async_flag : std_ulogic := '0'; + + signal INIT_DONE : boolean := false; + +begin + --------------------- + -- INPUT PATH DELAYs + -------------------- + + ADDRA_dly <= ADDRA after 0 ps; + ADDRB_dly <= ADDRB after 0 ps; + CLKA_dly <= CLKA after 0 ps; + CLKB_dly <= CLKB after 0 ps; + DIA_dly <= DIA after 0 ps; + DIB_dly <= DIB after 0 ps; + DIPA_dly <= DIPA after 0 ps; + DIPB_dly <= DIPB after 0 ps; + ENA_dly <= ENA after 0 ps; + ENB_dly <= ENB after 0 ps; + GSR_dly <= GSR after 0 ps; + RSTA_dly <= RSTA after 0 ps; + RSTB_dly <= RSTB after 0 ps; + REGCEA_dly <= REGCEA after 0 ps; + REGCEB_dly <= REGCEB after 0 ps; + WEA_dly <= WEA after 0 ps; + WEB_dly <= WEB after 0 ps; + GSR_CLKA_dly <= GSR after 0 ps; + GSR_CLKB_dly <= GSR after 0 ps; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + + prcs_initialize:process + variable INI_A : std_logic_vector (35 downto 0) := (others => 'X'); + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (35 downto 0) := (others => 'X'); + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + + variable SRVA_A : std_logic_vector (35 downto 0) := (others => 'X'); + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (35 downto 0) := (others => 'X'); + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + + variable DIAW_var : integer; + variable DIAW_1_var : integer; + variable DIBW_var : integer; + variable DIBW_1_var : integer; + variable DIPAW_var : integer; + variable DIPAW_1_var : integer; + variable DIPBW_var : integer; + variable DIPBW_1_var : integer; + + variable DOAW_var : integer; + variable DOAW_1_var : integer; + variable DOBW_var : integer; + variable DOBW_1_var : integer; + variable DOPAW_var : integer; + variable DOPAW_1_var : integer; + variable DOPBW_var : integer; + variable DOPBW_1_var : integer; + + begin + DIPAW_var := 0; + DIPAW_1_var := -1; + DIPBW_var := 0; + DIPBW_1_var := -1; + + DOPAW_var := 0; + DOPAW_1_var := -1; + DOPBW_var := 0; + DOPBW_1_var := -1; + + +-------------------------------------------------------------------- +-- Additional Checks Added Later +-------------------------------------------------------------------- + if((DATA_WIDTH_A = 0) and (DATA_WIDTH_B = 0 )) then + assert false + report "Attribute Syntax Error: Both DATA_WIDTH_A and DATA_WIDTH_B can not be 0." + severity Failure; + end if; + + case DATA_WIDTH_A is + + when 0 => + DOAW_var := 1; + DOAW_1_var := DOAW_var -1; + DIAW_var := 1; + DIAW_1_var := DIAW_var -1; + + when 1 => + DOAW_var := 1; + DOAW_1_var := DOAW_var -1; + DIAW_var := 1; + DIAW_1_var := DIAW_var -1; + + when 2 => + DOAW_var := 2; + DOAW_1_var := DOAW_var -1; + DIAW_var := 2; + DIAW_1_var := DIAW_var -1; + + when 4 => + DOAW_var := 4; + DOAW_1_var := DOAW_var -1; + DIAW_var := 4; + DIAW_1_var := DIAW_var -1; + + when 9 => + DOAW_var := 8; + DOAW_1_var := DOAW_var -1; + DOPAW_var := 1; + DOPAW_1_var := DOPAW_var -1; + DIAW_var := 8; + DIAW_1_var := DIAW_var -1; + DIPAW_var := 1; + DIPAW_1_var := DIPAW_var -1; + + when 18 => + DOAW_var := 16; + DOAW_1_var := DOAW_var -1; + DOPAW_var := 2; + DOPAW_1_var := DOPAW_var -1; + DIAW_var := 16; + DIAW_1_var := DIAW_var -1; + DIPAW_var := 2; + DIPAW_1_var := DIPAW_var -1; + + when 36 => + DOAW_var := 32; + DOAW_1_var := DOAW_var -1; + DOPAW_var := 4; + DOPAW_1_var := DOPAW_var -1; + DIAW_var := 32; + DIAW_1_var := DIAW_var -1; + DIPAW_var := 4; + DIPAW_1_var := DIPAW_var -1; + + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " DATA_WIDTH_A ", + EntityName => "/RAMB16BWER", + GenericValue => DATA_WIDTH_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", + TailMsg => "", + MsgSeverity => failure + ); + end case; + + + case DATA_WIDTH_B is + + when 0 => + DOBW_var := 1; + DOBW_1_var := DOBW_var -1; + DIBW_var := 1; + DIBW_1_var := DIBW_var -1; + + when 1 => + DOBW_var := 1; + DOBW_1_var := DOBW_var -1; + DIBW_var := 1; + DIBW_1_var := DIBW_var -1; + + when 2 => + DOBW_var := 2; + DOBW_1_var := DOBW_var -1; + DIBW_var := 2; + DIBW_1_var := DIBW_var -1; + + when 4 => + DOBW_var := 4; + DOBW_1_var := DOBW_var -1; + DIBW_var := 4; + DIBW_1_var := DIBW_var -1; + + when 9 => + DOBW_var := 8; + DOBW_1_var := DOBW_var -1; + DOPBW_var := 1; + DOPBW_1_var := DOPBW_var -1; + DIBW_var := 8; + DIBW_1_var := DIBW_var -1; + DIPBW_var := 1; + DIPBW_1_var := DIPBW_var -1; + + when 18 => + DOBW_var := 16; + DOBW_1_var := DOBW_var -1; + DOPBW_var := 2; + DOPBW_1_var := DOPBW_var -1; + DIBW_var := 16; + DIBW_1_var := DIBW_var -1; + DIPBW_var := 2; + DIPBW_1_var := DIPBW_var -1; + + when 36 => + DOBW_var := 32; + DOBW_1_var := DOBW_var -1; + DOPBW_var := 4; + DOPBW_1_var := DOPBW_var -1; + DIBW_var := 32; + DIBW_1_var := DIBW_var -1; + DIPBW_var := 4; + DIPBW_1_var := DIPBW_var -1; + + when others => + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " DATA_WIDTH_B ", + EntityName => "/RAMB16BWER", + GenericValue => DATA_WIDTH_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " 0, 1, 2, 4, 9, 18 or 36.", + TailMsg => "", + MsgSeverity => failure + ); + null; + + end case; + + + if (INIT_A'length > 36) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A ); + INI_A(35 downto 0) := INI_A_UNBOUND(35 downto 0); + elsif (INIT_A'length < 36) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A ); + elsif (INIT_A'length = 36) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A ); + end if; + + if (INIT_B'length > 36) then + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B ); + INI_B(35 downto 0) := INI_B_UNBOUND(35 downto 0); + elsif (INIT_B'length < 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B ); + elsif (INIT_B'length = 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B ); + end if; + + if (SRVAL_A'length > 36) then + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A ); + SRVA_A(35 downto 0) := SRVA_A_UNBOUND(35 downto 0); + elsif (SRVAL_A'length < 36) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A ); + elsif (SRVAL_A'length = 36) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A ); + end if; + + if (SRVAL_B'length > 36) then + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B ); + SRVA_B(35 downto 0) := SRVA_B_UNBOUND(35 downto 0); + elsif (SRVAL_B'length < 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B ); + elsif (SRVAL_B'length = 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B ); + end if; + + DIAW <= DIAW_var; + DIAW_1 <= DIAW_1_var; + DIBW <= DIBW_var; + DIBW_1 <= DIBW_1_var; + DIPAW <= DIPAW_var; + DIPAW_1 <= DIPAW_1_var; + DIPBW <= DIPBW_var; + DIPBW_1 <= DIPBW_1_var; + + DOAW <= DOAW_var; + DOAW_1 <= DOAW_1_var; + DOBW <= DOBW_var; + DOBW_1 <= DOBW_1_var; + DOPAW <= DOPAW_var; + DOPAW_1 <= DOPAW_1_var; + DOPBW <= DOPBW_var; + DOPBW_1 <= DOPBW_1_var; + + SRVA_A_sig <= SRVA_A; + SRVA_B_sig <= SRVA_B; + INI_A_sig <= INI_A; + INI_B_sig <= INI_B; + +-------- RSTTYPE ---------- + + if((RSTTYPE = "SYNC") or (RSTTYPE = "sync")) then + rst_async_flag <= '0'; + elsif((RSTTYPE = "ASYNC") or (RSTTYPE = "async")) then + rst_async_flag <= '1'; + else + assert false + report "Attribute Syntax Error: The attribute RSTTYPE on DSP48A is incorrect. Legal values for this attribute are SYNC or ASYNC." + severity Failure; + end if; +----------------------------- + + INIT_DONE <= true; + + wait; + end process prcs_initialize; +--------------------------------------------------------------------------------------- + VITALBehavior : process + + variable MEM : std_logic_vector(18431 downto 0) := To_StdLogicVector(INITP_07) & + To_StdLogicVector(INITP_06) & + To_StdLogicVector(INITP_05) & + To_StdLogicVector(INITP_04) & + To_StdLogicVector(INITP_03) & + To_StdLogicVector(INITP_02) & + To_StdLogicVector(INITP_01) & + To_StdLogicVector(INITP_00) & + + To_StdLogicVector(INIT_3F) & + To_StdLogicVector(INIT_3E) & + To_StdLogicVector(INIT_3D) & + To_StdLogicVector(INIT_3C) & + To_StdLogicVector(INIT_3B) & + To_StdLogicVector(INIT_3A) & + To_StdLogicVector(INIT_39) & + To_StdLogicVector(INIT_38) & + To_StdLogicVector(INIT_37) & + To_StdLogicVector(INIT_36) & + To_StdLogicVector(INIT_35) & + To_StdLogicVector(INIT_34) & + To_StdLogicVector(INIT_33) & + To_StdLogicVector(INIT_32) & + To_StdLogicVector(INIT_31) & + To_StdLogicVector(INIT_30) & + To_StdLogicVector(INIT_2F) & + To_StdLogicVector(INIT_2E) & + To_StdLogicVector(INIT_2D) & + To_StdLogicVector(INIT_2C) & + To_StdLogicVector(INIT_2B) & + To_StdLogicVector(INIT_2A) & + To_StdLogicVector(INIT_29) & + To_StdLogicVector(INIT_28) & + To_StdLogicVector(INIT_27) & + To_StdLogicVector(INIT_26) & + To_StdLogicVector(INIT_25) & + To_StdLogicVector(INIT_24) & + To_StdLogicVector(INIT_23) & + To_StdLogicVector(INIT_22) & + To_StdLogicVector(INIT_21) & + To_StdLogicVector(INIT_20) & + To_StdLogicVector(INIT_1F) & + To_StdLogicVector(INIT_1E) & + To_StdLogicVector(INIT_1D) & + To_StdLogicVector(INIT_1C) & + To_StdLogicVector(INIT_1B) & + To_StdLogicVector(INIT_1A) & + To_StdLogicVector(INIT_19) & + To_StdLogicVector(INIT_18) & + To_StdLogicVector(INIT_17) & + To_StdLogicVector(INIT_16) & + To_StdLogicVector(INIT_15) & + To_StdLogicVector(INIT_14) & + To_StdLogicVector(INIT_13) & + To_StdLogicVector(INIT_12) & + To_StdLogicVector(INIT_11) & + To_StdLogicVector(INIT_10) & + To_StdLogicVector(INIT_0F) & + To_StdLogicVector(INIT_0E) & + To_StdLogicVector(INIT_0D) & + To_StdLogicVector(INIT_0C) & + To_StdLogicVector(INIT_0B) & + To_StdLogicVector(INIT_0A) & + To_StdLogicVector(INIT_09) & + To_StdLogicVector(INIT_08) & + To_StdLogicVector(INIT_07) & + To_StdLogicVector(INIT_06) & + To_StdLogicVector(INIT_05) & + To_StdLogicVector(INIT_04) & + To_StdLogicVector(INIT_03) & + To_StdLogicVector(INIT_02) & + To_StdLogicVector(INIT_01) & + To_StdLogicVector(INIT_00) ; + + variable INI_A : std_logic_vector (35 downto 0) := (others => 'X'); + variable INI_A_UNBOUND : std_logic_vector (INIT_A'length-1 downto 0); + variable INI_B : std_logic_vector (35 downto 0) := (others => 'X'); + variable INI_B_UNBOUND : std_logic_vector (INIT_B'length-1 downto 0); + + variable DIAW : integer; + variable DIAW_1 : integer; + variable DIBW : integer; + variable DIBW_1 : integer; + variable DIPAW : integer; + variable DIPAW_1 : integer; + variable DIPBW : integer; + variable DIPBW_1 : integer; + + variable DOAW : integer; + variable DOAW_1 : integer; + variable DOBW : integer; + variable DOBW_1 : integer; + variable DOPAW : integer; + variable DOPAW_1 : integer; + variable DOPBW : integer; + variable DOPBW_1 : integer; + + variable ADDRA_dly_sampled : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + variable ADDRB_dly_sampled : std_logic_vector(MAX_ADDR downto 0) := (others => 'X'); + variable ADDRESS_A : integer; + variable ADDRESS_B : integer; + + variable ADDRESS_READ_A, ADDRESS_WRITE_A, ADDRESS_READ_B, ADDRESS_WRITE_B : integer; + variable ADDRESS_PARITY_READ_A, ADDRESS_PARITY_WRITE_A, ADDRESS_PARITY_READ_B, ADDRESS_PARITY_WRITE_B : integer; + + variable DOA_INDEX, DOPA_INDEX : integer := -1; + variable DOB_INDEX, DOPB_INDEX : integer := -1; + + variable DOA_OV_LSB : integer; + variable DOA_OV_MSB : integer; + variable DOA_zd : std_logic_vector(MAX_DI downto 0) := INI_A(MAX_DI downto 0); + variable DOA_zd_buf : std_logic_vector(MAX_DI downto 0) := INI_A(MAX_DI downto 0); + variable DOB_OV_LSB : integer; + variable DOB_OV_MSB : integer; + variable DOB_zd : std_logic_vector(MAX_DI downto 0) := INI_B(MAX_DI downto 0); + variable DOB_zd_buf : std_logic_vector(MAX_DI downto 0) := INI_B(MAX_DI downto 0); + variable DOPA_OV_LSB : integer; + variable DOPA_OV_MSB : integer; + variable DOPA_zd : std_logic_vector(3 downto 0) := INI_A(35 downto 32); + variable DOPA_zd_buf : std_logic_vector(3 downto 0) := INI_A(35 downto 32); + variable DOPB_OV_LSB : integer; + variable DOPB_OV_MSB : integer; + variable DOPB_zd : std_logic_vector(3 downto 0) := INI_B(35 downto 32); + variable DOPB_zd_buf : std_logic_vector(3 downto 0) := INI_B(35 downto 32); + variable ENA_dly_sampled : std_ulogic := 'X'; + variable ENB_dly_sampled : std_ulogic := 'X'; + variable FIRST_TIME : boolean := true; + variable HAS_OVERLAP : boolean := false; + variable HAS_OVERLAP_P : boolean := false; + variable OLPP_LSB : integer; + variable OLPP_MSB : integer; + variable OLP_LSB : integer; + variable OLP_MSB : integer; + variable SRVA_A : std_logic_vector (35 downto 0) := (others => 'X'); + variable SRVA_A_UNBOUND : std_logic_vector (SRVAL_A'length-1 downto 0); + variable SRVA_B : std_logic_vector (35 downto 0) := (others => 'X'); + variable SRVA_B_UNBOUND : std_logic_vector (SRVAL_B'length-1 downto 0); + variable RSTA_dly_sampled : std_ulogic := 'X'; + variable RSTB_dly_sampled : std_ulogic := 'X'; + variable VALID_ADDRA : boolean := true; + variable VALID_ADDRB : boolean := true; + variable ViolationA : std_ulogic := '0'; + variable ViolationB : std_ulogic := '0'; + variable ViolationCLKAB : std_ulogic := '0'; + variable ViolationCLKAB_S0 : boolean := false; + variable Violation_S1 : boolean := false; + variable Violation_S3 : boolean := false; + variable WEA_dly_sampled : std_logic_vector(MAX_WE downto 0) := (others => 'X'); + variable WEB_dly_sampled : std_logic_vector(MAX_WE downto 0) := (others => 'X'); + variable wr_mode_a : std_logic_vector(1 downto 0) := "00"; + variable wr_mode_b : std_logic_vector(1 downto 0) := "00"; + +--FP + variable wea_index : integer := -1; + variable web_index : integer := -1; + + variable tmp_we : std_logic_vector(1 downto 0) := (others => '1'); + variable xout_we_seg1 : std_logic_vector(1 downto 0) := (others => '0'); + variable xout_we_seg2 : std_logic_vector(1 downto 0) := (others => '0'); + + variable tmp_zero_write_a : std_logic_vector(MAX_ADDR downto 0) := (others => '1'); + variable tmp_zero_read_a : std_logic_vector(MAX_ADDR downto 0) := (others => '1'); + variable tmp_zero_parity_write_a : std_logic_vector((MAX_ADDR-3) downto 0) := (others => '0'); + variable tmp_zero_parity_read_a : std_logic_vector((MAX_ADDR-3) downto 0) := (others => '0'); + + variable tmp_zero_write_b : std_logic_vector(MAX_ADDR downto 0) := (others => '1'); + variable tmp_zero_read_b : std_logic_vector(MAX_ADDR downto 0) := (others => '1'); + variable tmp_zero_parity_write_b : std_logic_vector((MAX_ADDR-3) downto 0) := (others => '0'); + variable tmp_zero_parity_read_b : std_logic_vector((MAX_ADDR-3) downto 0) := (others => '0'); + + variable zero_write_a : std_logic_vector(MAX_ADDR downto 0) := (others => '1'); + variable zero_read_a : std_logic_vector(MAX_ADDR downto 0) := (others => '1'); + variable zero_parity_write_a : std_logic_vector((MAX_ADDR-3) downto 0) := (others => '1'); + variable zero_parity_read_a : std_logic_vector((MAX_ADDR-3) downto 0) := (others => '1'); + + variable zero_write_b : std_logic_vector(MAX_ADDR downto 0) := (others => '1'); + variable zero_read_b : std_logic_vector(MAX_ADDR downto 0) := (others => '1'); + variable zero_parity_write_b : std_logic_vector((MAX_ADDR-3) downto 0) := (others => '1'); + variable zero_parity_read_b : std_logic_vector((MAX_ADDR-3) downto 0) := (others => '1'); + + + variable addra_in_14 : std_ulogic := '0'; + variable addrb_in_14 : std_ulogic := '0'; + + variable SimCollisionCheck_var : integer := 3; + variable collision_clka_clkb : integer := 0; + variable addr_overlap : boolean := false; + + variable CLKA_time : time := 0 ps; + variable CLKB_time : time := 0 ps; + + variable DOA_clsn : std_logic_vector(31 downto 0) := (others => '0'); + variable DOPA_clsn : std_logic_vector(3 downto 0) := (others => '0'); + variable DOA_clsn_sav : std_logic_vector(31 downto 0) := (others => '0'); + variable DOPA_clsn_sav : std_logic_vector(3 downto 0) := (others => '0'); + variable DOA_clsn_zero : std_logic_vector(31 downto 0) := (others => '0'); + variable DOPA_clsn_zero : std_logic_vector(3 downto 0) := (others => '0'); + + variable DOB_clsn : std_logic_vector(31 downto 0) := (others => '0'); + variable DOPB_clsn : std_logic_vector(3 downto 0) := (others => '0'); + variable DOB_clsn_sav : std_logic_vector(31 downto 0) := (others => '0'); + variable DOPB_clsn_sav : std_logic_vector(3 downto 0) := (others => '0'); + variable DOB_clsn_zero : std_logic_vector(31 downto 0) := (others => '0'); + variable DOPB_clsn_zero : std_logic_vector(3 downto 0) := (others => '0'); + + variable DOA_clsn_slice : std_logic_vector(31 downto 0) := (others => '0'); + variable DOPA_clsn_slice : std_logic_vector(3 downto 0) := (others => '0'); + variable DOB_clsn_slice : std_logic_vector(31 downto 0) := (others => '0'); + variable DOPB_clsn_slice : std_logic_vector(3 downto 0) := (others => '0'); + + variable tmp_membuf : std_logic_vector(31 downto 0) := (others => '0'); + + variable DOA_clsn_read_index, DOPA_clsn_read_index : integer := -1; + variable DOB_clsn_read_index, DOPB_clsn_read_index : integer := -1; + + variable DOA_clsn_write_index, DOPA_clsn_write_index : integer := -1; + variable DOB_clsn_write_index, DOPB_clsn_write_index : integer := -1; + + variable clsn_type : CollisionFlagType; + variable data_widths : DataWidthType; + variable clsn_xbufs : ClsnXbufType; + + variable collision_msg : memory_collision_type; + + variable Write_A_Write_B : memory_collision_type := Write_A_Write_B; + variable Read_A_Write_B : memory_collision_type := Read_A_Write_B; + variable Write_A_Read_B : memory_collision_type := Write_A_Read_B; + variable Write_B_Write_A : memory_collision_type := Write_B_Write_A; + variable Read_B_Write_A : memory_collision_type := Read_B_Write_A; + variable Write_B_Read_A : memory_collision_type := Write_B_Read_A; + + variable msg_addr1 : std_logic_vector(MAX_ADDR downto 0) := (others => '0'); + variable msg_addr2 : std_logic_vector(MAX_ADDR downto 0) := (others => '0'); + + begin + + + if (FIRST_TIME) then + + DIPAW := 0; + DIPAW_1 := -1; + DIPBW := 0; + DIPBW_1 := -1; + + DOPAW := 0; + DOPAW_1 := -1; + DOPBW := 0; + DOPBW_1 := -1; + + case DATA_WIDTH_A is + + when 0 => + DOAW := 1; + DOAW_1 := DOAW -1; + DIAW := 1; + DIAW_1 := DIAW -1; + + when 1 => + zero_read_a(13 downto 0) := (others => '1'); + DOAW := 1; + DOAW_1 := DOAW -1; + zero_write_a(13 downto 0) := (others => '1'); + DIAW := 1; + DIAW_1 := DIAW -1; + + when 2 => + zero_read_a(0 downto 0) := (others => '0'); + DOAW := 2; + DOAW_1 := DOAW -1; + zero_write_a(0 downto 0) := (others => '0'); + DIAW := 2; + DIAW_1 := DIAW -1; + + when 4 => + zero_read_a(1 downto 0) := (others => '0'); + DOAW := 4; + DOAW_1 := DOAW -1; + zero_write_a(1 downto 0) := (others => '0'); + DIAW := 4; + DIAW_1 := DIAW -1; + + when 9 => + zero_read_a(2 downto 0) := (others => '0'); + DOAW := 8; + DOAW_1 := DOAW -1; + DOPAW := 1; + DOPAW_1 := DOPAW -1; + zero_write_a(2 downto 0) := (others => '0'); + DIAW := 8; + DIAW_1 := DIAW -1; + DIPAW := 1; + DIPAW_1 := DIPAW -1; + + when 18 => + zero_read_a(3 downto 0) := (others => '0'); + zero_parity_read_a(0 downto 0) := (others => '0'); + DOAW := 16; + DOAW_1 := DOAW -1; + DOPAW := 2; + DOPAW_1 := DOPAW -1; + zero_write_a(3 downto 0) := (others => '0'); + zero_parity_write_a(0 downto 0) := (others => '0'); + DIAW := 16; + DIAW_1 := DIAW -1; + DIPAW := 2; + DIPAW_1 := DIPAW -1; + + when 36 => + zero_read_a(4 downto 0) := (others => '0'); + zero_parity_read_a(1 downto 0) := (others => '0'); + DOAW := 32; + DOAW_1 := DOAW -1; + DOPAW := 4; + DOPAW_1 := DOPAW -1; + zero_write_a(4 downto 0) := (others => '0'); + zero_parity_write_a(1 downto 0) := (others => '0'); + DIAW := 32; + DIAW_1 := DIAW -1; + DIPAW := 4; + DIPAW_1 := DIPAW -1; + + when others => + null; + + end case; + + case DATA_WIDTH_B is + + when 0 => + DOBW := 1; + DOBW_1 := DOBW -1; + DIBW := 1; + DIBW_1 := DIBW -1; + + when 1 => + zero_read_b(13 downto 0) := (others => '1'); + DOBW := 1; + DOBW_1 := DOBW -1; + zero_write_b(13 downto 0) := (others => '1'); + DIBW := 1; + DIBW_1 := DIBW -1; + + when 2 => + zero_read_b(0 downto 0) := (others => '0'); + DOBW := 2; + DOBW_1 := DOBW -1; + zero_write_b(0 downto 0) := (others => '0'); + DIBW := 2; + DIBW_1 := DIBW -1; + + when 4 => + zero_read_b(1 downto 0) := (others => '0'); + DOBW := 4; + DOBW_1 := DOBW -1; + zero_write_b(1 downto 0) := (others => '0'); + DIBW := 4; + DIBW_1 := DIBW -1; + + when 9 => + zero_read_b(2 downto 0) := (others => '0'); + DOBW := 8; + DOBW_1 := DOBW -1; + DOPBW := 1; + DOPBW_1 := DOPBW -1; + zero_write_b(2 downto 0) := (others => '0'); + DIBW := 8; + DIBW_1 := DIBW -1; + DIPBW := 1; + DIPBW_1 := DIPBW -1; + + when 18 => + zero_read_b(3 downto 0) := (others => '0'); + zero_parity_read_b(0 downto 0) := (others => '0'); + DOBW := 16; + DOBW_1 := DOBW -1; + DOPBW := 2; + DOPBW_1 := DOPBW -1; + zero_write_b(3 downto 0) := (others => '0'); + zero_parity_write_b(0 downto 0) := (others => '0'); + DIBW := 16; + DIBW_1 := DIBW -1; + DIPBW := 2; + DIPBW_1 := DIPBW -1; + + when 36 => + zero_read_b(4 downto 0) := (others => '0'); + zero_parity_read_b(1 downto 0) := (others => '0'); + DOBW := 32; + DOBW_1 := DOBW -1; + DOPBW := 4; + DOPBW_1 := DOPBW -1; + zero_write_b(4 downto 0) := (others => '0'); + zero_parity_write_b(1 downto 0) := (others => '0'); + DIBW := 32; + DIBW_1 := DIBW -1; + DIPBW := 4; + DIPBW_1 := DIPBW -1; + + when others => + null; + + end case; + + if (INIT_A'length > 36) then + INI_A_UNBOUND(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A ); + INI_A(35 downto 0) := INI_A_UNBOUND(35 downto 0); + elsif (INIT_A'length < 36) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A ); + elsif (INIT_A'length = 36) then + INI_A(INIT_A'length-1 downto 0) := To_StdLogicVector(INIT_A ); + end if; + + if (INIT_B'length > 36) then + INI_B_UNBOUND(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B ); + INI_B(35 downto 0) := INI_B_UNBOUND(35 downto 0); + elsif (INIT_B'length < 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B ); + elsif (INIT_B'length = 36) then + INI_B(INIT_B'length-1 downto 0) := To_StdLogicVector(INIT_B ); + end if; + + if (SRVAL_A'length > 36) then + SRVA_A_UNBOUND(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A ); + SRVA_A(35 downto 0) := SRVA_A_UNBOUND(35 downto 0); + elsif (SRVAL_A'length < 36) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A ); + elsif (SRVAL_A'length = 36) then + SRVA_A(SRVAL_A'length-1 downto 0) := To_StdLogicVector(SRVAL_A ); + end if; + + if (SRVAL_B'length > 36) then + SRVA_B_UNBOUND(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B ); + SRVA_B(35 downto 0) := SRVA_B_UNBOUND(35 downto 0); + elsif (SRVAL_B'length < 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B ); + elsif (SRVAL_B'length = 36) then + SRVA_B(SRVAL_B'length-1 downto 0) := To_StdLogicVector(SRVAL_B ); + end if; + + if ((WRITE_MODE_A = "write_first") or (WRITE_MODE_A = "WRITE_FIRST")) then + wr_mode_a := "00"; + elsif ((WRITE_MODE_A = "read_first") or (WRITE_MODE_A = "READ_FIRST")) then + wr_mode_a := "01"; + elsif ((WRITE_MODE_A = "no_change") or (WRITE_MODE_A = "NO_CHANGE")) then + wr_mode_a := "10"; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " WRITE_MODE_A ", + EntityName => "/RAMB16BWER", + GenericValue => WRITE_MODE_A, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if ((WRITE_MODE_B = "write_first") or (WRITE_MODE_B = "WRITE_FIRST")) then + wr_mode_b := "00"; + elsif ((WRITE_MODE_B = "read_first") or (WRITE_MODE_B = "READ_FIRST")) then + wr_mode_b := "01"; + elsif ((WRITE_MODE_B = "no_change") or (WRITE_MODE_B = "NO_CHANGE")) then + wr_mode_b := "10"; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " WRITE_MODE_B ", + EntityName => "/RAMB16BWER", + GenericValue => WRITE_MODE_B, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " WRITE_FIRST, READ_FIRST or NO_CHANGE ", + TailMsg => "", + MsgSeverity => error + ); + end if; + + if((SIM_COLLISION_CHECK = "ALL") or (SIM_COLLISION_CHECK = "all")) then + SimCollisionCheck_var := 3; + elsif((SIM_COLLISION_CHECK = "NONE") or (SIM_COLLISION_CHECK = "none")) then + SimCollisionCheck_var := 0; + elsif((SIM_COLLISION_CHECK = "WARNING_ONLY") or (SIM_COLLISION_CHECK = "warning_only")) then + SimCollisionCheck_var := 1; + elsif((SIM_COLLISION_CHECK = "GENERATE_X_ONLY") or (SIM_COLLISION_CHECK = "generate_x_only")) then + SimCollisionCheck_var := 2; + else + GenericValueCheckMessage + ( HeaderMsg => " Attribute Syntax Error : ", + GenericName => " SIM_COLLISION_CHECK ", + EntityName => "/RAMB16BWER", + GenericValue => SIM_COLLISION_CHECK, + Unit => "", + ExpectedValueMsg => " The Legal values for this attribute are ", + ExpectedGenericValue => " ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY ", + TailMsg => "", + MsgSeverity => error + ); + end if; + + + wait until (GSR_CLKA_dly = '1' or GSR_CLKB_dly = '1' or ((CLKA_dly = '0' or CLKA_dly = '1') or (CLKB_dly = '0' or CLKB_dly = '1'))); +---################################################################################ + DOA_zd(DOAW_1 downto 0) := INI_A(DOAW_1 downto 0); + DOB_zd(DOBW_1 downto 0) := INI_B(DOBW_1 downto 0); + + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := INI_A((DOPAW_1 + DOAW) downto DOAW); + end if; + + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := INI_B((DOPBW_1 + DOBW) downto DOBW); + end if; + +----- Port A +-- DOA <= DOA_zd; +-- if(DOPAW_1 /= -1) then +-- DOPA <= DOPA_zd; +-- end if; + +----- Port B +-- DOB <= DOB_zd; +-- if(DOPBW_1 /= -1) then +-- DOPB <= DOPB_zd; +-- end if; + + data_widths.diaw := DIAW; + data_widths.dipaw := DIPAW; + data_widths.doaw := DOAW; + data_widths.dopaw := DOPAW; + + data_widths.dibw := DIBW; + data_widths.dipbw := DIPBW; + data_widths.dobw := DOBW; + data_widths.dopbw := DOPBW; + + FIRST_TIME := false; + end if; +---------------- END FIRST_TIME + +-- addra_in_14 := ADDRA_dly(14); + +-- if (CLKA_dly'event) then + if (rising_edge(CLKA_dly)) then + ENA_dly_sampled := ENA_dly; + RSTA_dly_sampled := RSTA_dly; + WEA_dly_sampled := WEA_dly; + ADDRA_dly_sampled := ADDRA_dly; + end if; + +------------------------------------------------------------- + +-- addrb_in_14 := ADDRB_dly(14); + +-- if (CLKB_dly'event) then + if (rising_edge(CLKB_dly)) then + ENB_dly_sampled := ENB_dly; + RSTB_dly_sampled := RSTB_dly; + WEB_dly_sampled := WEB_dly; + ADDRB_dly_sampled := ADDRB_dly; + end if; + + + +-------------------------------- A ---------------------------------------- + tmp_zero_write_a := (addra_dly_sampled(13 downto 0) and zero_write_a); + ADDRESS_WRITE_A := SLV_TO_INT(tmp_zero_write_a); + + tmp_zero_read_a := (addra_dly_sampled(13 downto 0) and zero_read_a); + ADDRESS_READ_A := SLV_TO_INT(tmp_zero_read_a); + + tmp_zero_parity_write_a(10 downto 0) := addra_dly_sampled( 13 downto 3) and zero_parity_write_a; + ADDRESS_PARITY_WRITE_A := SLV_TO_INT(tmp_zero_parity_write_a); + + tmp_zero_parity_read_a(10 downto 0) := addra_dly_sampled( 13 downto 3) and zero_parity_read_a; + ADDRESS_PARITY_READ_A := SLV_TO_INT(tmp_zero_parity_read_a); +-------------------------------- B ---------------------------------------- + tmp_zero_write_b := (addrb_dly_sampled(13 downto 0) and zero_write_b); + ADDRESS_WRITE_B := SLV_TO_INT(tmp_zero_write_b); + + tmp_zero_read_b := (addrb_dly_sampled(13 downto 0) and zero_read_b); + ADDRESS_READ_B := SLV_TO_INT(tmp_zero_read_b); + + tmp_zero_parity_write_b(10 downto 0) := addrb_dly_sampled( 13 downto 3) and zero_parity_write_b; + ADDRESS_PARITY_WRITE_B := SLV_TO_INT(tmp_zero_parity_write_b); + + tmp_zero_parity_read_b(10 downto 0) := addrb_dly_sampled( 13 downto 3) and zero_parity_read_b; + ADDRESS_PARITY_READ_B := SLV_TO_INT(tmp_zero_parity_read_b); + + +-- VALID_ADDRA := ADDR_IS_VALID(addra_dly_sampled); +-- if (VALID_ADDRA) then +-- end if; + +-- VALID_ADDRB := ADDR_IS_VALID(addrb_dly_sampled); +-- if (VALID_ADDRB) then +-- end if; + +-- DOA_INDEX / DOPA_INDEX + + if(DIAW <= DOAW) then + case DIAW is + when 1 => + case DOAW is + when 1 => DOA_INDEX := 0; + when 2 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(0 downto 0)); + when 4 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(1 downto 0)); + when 8 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(2 downto 0)); + when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(3 downto 0)); + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 0)); + when others => null; + end case; + + when 2 => + case DOAW is + when 2 => DOA_INDEX := 0; + when 4 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(1 downto 1)); + when 8 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(2 downto 1)); + when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(3 downto 1)); + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 1)); + when others => null; + end case; + + when 4 => + case DOAW is + when 4 => DOA_INDEX := 0; + when 8 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(2 downto 2)); + when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(3 downto 2)); + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 2)); + when others => null; + end case; + + when 8 => + case DOAW is + when 8 => DOA_INDEX := 0; + DOPA_INDEX := 0; + when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(3 downto 3)); + DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_write_a(0 downto 0)); + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 3)); + DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_write_a(1 downto 0)); + when others => null; + end case; + + when 16 => + case DOAW is + when 16 => DOA_INDEX := 0; + DOPA_INDEX := 0; + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_write_a(4 downto 4)); + DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_write_a(1 downto 1)); + when others => null; + end case; + + when 32 => + case DOAW is + when 32 => DOA_INDEX := 0; + DOPA_INDEX := 0; + when others => null; + end case; + + when others => null; + end case; + + elsif(DIAW > DOAW) then + case DOAW is + when 1 => + case DIAW is + when 2 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(0 downto 0)); + when 4 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(1 downto 0)); + when 8 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(2 downto 0)); + when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(3 downto 0)); + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 0)); + when others => null; + end case; + when 2 => + case DIAW is + when 4 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(1 downto 1)); + when 8 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(2 downto 1)); + when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(3 downto 1)); + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 1)); + when others => null; + end case; + + when 4 => + case DIAW is + when 8 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(2 downto 2)); + when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(3 downto 2)); + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 2)); + when others => null; + end case; + when 8 => + case DIAW is + when 16 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(3 downto 3)); + DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_read_a(0 downto 0)); + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 3)); + DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0)); + when others => null; + end case; + + when 16 => + case DIAW is + when 32 => DOA_INDEX := SLV_TO_INT(tmp_zero_read_a(4 downto 4)); + DOPA_INDEX := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 1)); + when others => null; + end case; + + when others => null; + end case; + end if; + +-- DOB_INDEX / DOPB_INDEX + + if(DIBW <= DOBW) then + case DIBW is + when 1 => + case DOBW is + when 1 => DOB_INDEX := 0; + when 2 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(0 downto 0)); + when 4 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(1 downto 0)); + when 8 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(2 downto 0)); + when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(3 downto 0)); + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 0)); + when others => null; + end case; + + when 2 => + case DOBW is + when 2 => DOB_INDEX := 0; + when 4 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(1 downto 1)); + when 8 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(2 downto 1)); + when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(3 downto 1)); + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 1)); + when others => null; + end case; + + when 4 => + case DOBW is + when 4 => DOB_INDEX := 0; + when 8 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(2 downto 2)); + when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(3 downto 2)); + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 2)); + when others => null; + end case; + + when 8 => + case DOBW is + when 8 => DOB_INDEX := 0; + DOPB_INDEX := 0; + when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(3 downto 3)); + DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_write_b(0 downto 0)); + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 3)); + DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_write_b(1 downto 0)); + when others => null; + end case; + + when 16 => + case DOBW is + when 16 => DOB_INDEX := 0; + DOPB_INDEX := 0; + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_write_b(4 downto 4)); + DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_write_b(1 downto 1)); + when others => null; + end case; + + when 32 => + case DOBW is + when 32 => DOB_INDEX := 0; + DOPB_INDEX := 0; + when others => null; + end case; + + when others => null; + end case; + + elsif(DIBW > DOBW) then + case DOBW is + when 1 => + case DIBW is + when 2 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(0 downto 0)); + when 4 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(1 downto 0)); + when 8 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(2 downto 0)); + when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(3 downto 0)); + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 0)); + when others => null; + end case; + when 2 => + case DIBW is + when 4 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(1 downto 1)); + when 8 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(2 downto 1)); + when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(3 downto 1)); + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 1)); + when others => null; + end case; + + when 4 => + case DIBW is + when 8 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(2 downto 2)); + when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(3 downto 2)); + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 2)); + when others => null; + end case; + when 8 => + case DIBW is + when 16 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(3 downto 3)); + DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_read_b(0 downto 0)); + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 3)); + DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0)); + when others => null; + end case; + + when 16 => + case DIBW is + when 32 => DOB_INDEX := SLV_TO_INT(tmp_zero_read_b(4 downto 4)); + DOPB_INDEX := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 1)); + when others => null; + end case; + + when others => null; + end case; + end if; + + + +----- ###################################################################################################### + + if(rising_edge(CLKA_dly)) then + CLKA_time := now; + end if; + + if(rising_edge(CLKB_dly)) then + CLKB_time := now; + end if; + + +----- ###################################################################################################### +------------------------------------------------------------------------ +------------ Port A ---------------------------------------------------- +------------------------------------------------------------------------ + if(GSR_CLKA_dly = '1') then + DOA_zd(DOAW_1 downto 0) := INI_A(DOAW_1 downto 0); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := INI_A((DOPAW_1 + DOAW) downto DOAW); + end if; + +-- CR 422403 + elsif((RSTA_dly = '1') and (rst_async_flag = '1') and (ena_dly_sampled = '1')) then + DOA_zd(DOAW_1 downto 0) := SRVA_A(DOAW_1 downto 0); + DOA_clsn_zero := (others => '0'); + DOA_clsn := (others => '0'); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := SRVA_A((DOPAW_1 + DOAW) downto DOAW); + DOPA_clsn_zero := (others => '0'); + DOPA_clsn := (others => '0'); + end if; + elsif(CLKA_dly'event AND CLKA_dly'last_value = '0') then + + if (ena_dly_sampled = '1') then + if (RSTA_dly_sampled = '1') then + DOA_zd(DOAW_1 downto 0) := SRVA_A(DOAW_1 downto 0); + DOA_clsn_zero := (others => '0'); + DOA_clsn := (others => '0'); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := SRVA_A((DOPAW_1 + DOAW) downto DOAW); + DOPA_clsn_zero := (others => '0'); + DOPA_clsn := (others => '0'); + end if; + else +----------------------- Start COLLISION A ------------------------------ + + if(SimCollisionCheck_var /= 0) then + DOA_clsn_sav := DOA_clsn; + DOPA_clsn_sav := DOPA_clsn; + + DOA_clsn := (others => '0'); + DOPA_clsn := (others => '0'); + clsn_xbufs.DO1_clsn := (others => '0'); + clsn_xbufs.DOP1_clsn := (others => '0'); + clsn_xbufs.MEM1_clsn := (others => '0'); + clsn_xbufs.MEMP1_clsn := (others => '0'); + + clsn_xbufs.DO2_clsn := (others => '0'); + clsn_xbufs.DOP2_clsn := (others => '0'); + clsn_xbufs.MEM2_clsn := (others => '0'); + clsn_xbufs.MEMP2_clsn := (others => '0'); + + clsn_type.active_port := 1; + addr_overlap := false; + clsn_type.read_write := false; + clsn_type.write_read := false; + clsn_type.write_write := false; + +-- CLKA_time := now; + + ClkCollisionCheck( + violation => collision_clka_clkb, + CheckEnabled => ((TO_X01(ena_dly_sampled) = '1') and (TO_X01(enb_dly_sampled) = '1')), + CLK1_time => CLKA_time, + CLK2_time => CLKB_time, + SETUP_All => SETUP_ALL, + SETUP_READ_FIRST => SETUP_READ_FIRST + ); + + if(collision_clka_clkb /= 0) then + QkAddrOverlapChk( + addr_overlap => addr_overlap, + data_widths => data_widths, + addra => addra_dly_sampled, + addrb => addrb_dly_sampled + ); + end if; + + if(addr_overlap) then + PreProcessWe1We2( + clsn_bufs => clsn_xbufs, + clsn_type => clsn_type, + memory => MEM, + di1 => dia_dly, + di2 => dib_dly, + dip1 => dipa_dly, + dip2 => dipb_dly, + addr1 => addra_dly_sampled, + addr2 => addrb_dly_sampled, + we1 => wea_dly_sampled, + we2 => web_dly_sampled, + zero_read_1 => zero_read_a, + zero_readp_1 => zero_parity_read_a, + zero_write_1 => zero_write_a, + zero_writep_1 => zero_parity_write_a, + zero_read_2 => zero_read_b, + zero_readp_2 => zero_parity_read_b, + zero_write_2 => zero_write_b, + zero_writep_2 => zero_parity_write_b, + wr_mode_1 => wr_mode_a, + wr_mode_2 => wr_mode_b, + violation => collision_clka_clkb, + DI1W => DIAW, + DIP1W => DIPAW, + DI2W => DIBW, + DIP2W => DIPBW, + DO1W => DOAW, + DOP1W => DOPAW, + DO2W => DOBW, + DOP2W => DOPBW + ); + end if; + + if(clsn_type.read_write or clsn_type.write_write or clsn_type.write_read) then + + if(clsn_type.write_write) then + collision_msg := Write_A_Write_B; + msg_addr1 := tmp_zero_write_a; + msg_addr2 := tmp_zero_write_b; + elsif(clsn_type.read_write) then + collision_msg := Read_A_Write_B; + msg_addr1 := tmp_zero_read_a; + msg_addr2 := tmp_zero_write_b; + elsif(clsn_type.write_read) then + collision_msg := Write_A_Read_B; +-- msg_addr1 := tmp_zero_write_a; +-- msg_addr2 := tmp_zero_read_b; + msg_addr1 := tmp_zero_read_b; + msg_addr2 := tmp_zero_write_a; + end if; + + if(SimCollisionCheck_var = 1) then + --- Message + Memory_Collision_Msg_ramb16 + ( collision_type => collision_msg, + EntityName => "RAMB16BWER", + InstanceName => RAMB16BWER'path_name, + address_1 => msg_addr1, + address_2 => msg_addr2 + ); + + DOA_clsn := (others => '0'); + DOPA_clsn := (others => '0'); + DOA_clsn_sav := DOA_clsn; + DOPA_clsn_sav := DOPA_clsn; + + elsif(SimCollisionCheck_var = 2) then + + DOA_clsn_read_index := SLV_TO_INT(tmp_zero_read_a(4 downto 0)); + DOB_clsn_read_index := SLV_TO_INT(tmp_zero_read_b(4 downto 0)); + DOA_clsn(DOAW_1 downto 0) := clsn_xbufs.DO1_clsn((DOA_clsn_read_index+DOAW_1) downto DOA_clsn_read_index); + DOB_clsn(DOBW_1 downto 0) := clsn_xbufs.DO2_clsn((DOB_clsn_read_index+DOBW_1) downto DOB_clsn_read_index); + if(DOPAW_1 /= -1) then + DOPA_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0)); + DOPA_clsn(DOPAW_1 downto 0) := clsn_xbufs.DOP1_clsn((DOPA_clsn_read_index+DOPAW_1) downto DOPA_clsn_read_index); + end if; + + if(DOPBW_1 /= -1) then + DOPB_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0)); + DOPB_clsn(DOPBW_1 downto 0) := clsn_xbufs.DOP2_clsn((DOPB_clsn_read_index+DOPBW_1) downto DOPB_clsn_read_index); + end if; + + if(wr_mode_a = "10") then + DOA_clsn(DOAW_1 downto 0) := DOA_clsn(DOAW_1 downto 0) xor DOA_clsn_sav(DOAW_1 downto 0); + if(DOPAW_1 /= -1) then + DOPA_clsn(DOPAW_1 downto 0) := DOPA_clsn(DOPAW_1 downto 0) xor DOPA_clsn_sav(DOPAW_1 downto 0); + end if; + end if; + + if(wr_mode_b = "10") then + DOB_clsn(DOBW_1 downto 0) := DOB_clsn(DOBW_1 downto 0) xor DOB_clsn_sav(DOBW_1 downto 0); + if(DOPBW_1 /= -1) then + DOPB_clsn(DOPBW_1 downto 0) := DOPB_clsn(DOPBW_1 downto 0) xor DOPB_clsn_sav(DOPBW_1 downto 0); + end if; + end if; + + elsif(SimCollisionCheck_var = 3) then + --- Message + Memory_Collision_Msg_ramb16 + ( collision_type => collision_msg, + EntityName => "RAMB16BWER", + InstanceName => RAMB16BWER'path_name, + address_1 => msg_addr1, + address_2 => msg_addr2 + ); + + DOA_clsn_read_index := SLV_TO_INT(tmp_zero_read_a(4 downto 0)); + DOB_clsn_read_index := SLV_TO_INT(tmp_zero_read_b(4 downto 0)); + DOA_clsn(DOAW_1 downto 0) := clsn_xbufs.DO1_clsn((DOA_clsn_read_index+DOAW_1) downto DOA_clsn_read_index); + DOB_clsn(DOBW_1 downto 0) := clsn_xbufs.DO2_clsn((DOB_clsn_read_index+DOBW_1) downto DOB_clsn_read_index); + if(DOPAW_1 /= -1) then + DOPA_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0)); + DOPA_clsn(DOPAW_1 downto 0) := clsn_xbufs.DOP1_clsn((DOPA_clsn_read_index+DOPAW_1) downto DOPA_clsn_read_index); + end if; + + if(DOPBW_1 /= -1) then + DOPB_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0)); + DOPB_clsn(DOPBW_1 downto 0) := clsn_xbufs.DOP2_clsn((DOPB_clsn_read_index+DOPBW_1) downto DOPB_clsn_read_index); + end if; + + if(wr_mode_a = "10") then + DOA_clsn(DOAW_1 downto 0) := DOA_clsn(DOAW_1 downto 0) xor DOA_clsn_sav(DOAW_1 downto 0); + if(DOPAW_1 /= -1) then + DOPA_clsn(DOPAW_1 downto 0) := DOPA_clsn(DOPAW_1 downto 0) xor DOPA_clsn_sav(DOPAW_1 downto 0); + end if; + end if; + + if(wr_mode_b = "10") then + DOB_clsn(DOBW_1 downto 0) := DOB_clsn(DOBW_1 downto 0) xor DOB_clsn_sav(DOBW_1 downto 0); + if(DOPBW_1 /= -1) then + DOPB_clsn(DOPBW_1 downto 0) := DOPB_clsn(DOPBW_1 downto 0) xor DOPB_clsn_sav(DOPBW_1 downto 0); + end if; + end if; + + + end if; + + end if; + + DOA_clsn_zero := DOA_clsn; + DOPA_clsn_zero := DOPA_clsn; + if(RSTB_dly_sampled = '0') then + DOB_clsn_zero := DOB_clsn; + DOPB_clsn_zero := DOPB_clsn; + end if; + + end if; + +---------------- END COLLISION A ------------------------------ + if (wr_mode_a = "00") then + + case DIAW is + --------- + when 1|2|4|8 => + --------- + tmp_we(1 downto 0) := addra_dly_sampled( 4 downto 3); + wea_index := SLV_TO_INT(tmp_we); + if(wea_dly_sampled(wea_index) = '1') then + if(DOAW > DIAW) then + DOA_zd_buf(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto ADDRESS_READ_A); + DOA_zd_buf(((DOA_INDEX *DIAW) + DIAW_1) downto (DOA_INDEX *DIAW)) := DIA_dly(DIAW_1 downto 0); + DOA_zd(DOAW_1 downto 0) := DOA_zd_buf(DOAW_1 downto 0); + + if(DOPAW_1 /= -1) then + DOPA_zd_buf(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A)); + DOPA_zd_buf(((DOPA_INDEX *DIPAW) + DIPAW_1) downto (DOPA_INDEX *DIPAW)) := DIPA_dly(DIPAW_1 downto 0); + DOPA_zd(DOPAW_1 downto 0) := DOPA_zd_buf(DOPAW_1 downto 0); + end if; + elsif(DOAW <= DIAW) then +--FP DOA_zd(DOAW_1 downto 0) := DIA_dly(DOAW_1 downto 0); + DOA_zd(DOAW_1 downto 0) := DIA_dly((((DOA_INDEX)*DOAW)+ DOAW_1) downto ((DOA_INDEX)*DOAW)); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := DIPA_dly(DOPAW_1 downto 0); + end if; + end if; + elsif(wea_dly_sampled(wea_index) = '0') then + DOA_zd(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto (ADDRESS_READ_A)); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A)); + end if; + end if; + + --------- + when 16 => + --------- + if(DOAW > DIAW) then + DOA_zd_buf(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto ADDRESS_READ_A); + DOPA_zd_buf(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A)); + +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + + xout_we_seg1(1) := addra_dly_sampled(4); + xout_we_seg1(0) := '0'; + xout_we_seg2(1) := addra_dly_sampled(4); + xout_we_seg2(0) := '1'; + + if(wea_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= wea_dly_sampled(SLV_TO_INT(xout_we_seg2))) then + DOA_zd_buf(DOAW_1 downto 0) := (others => 'X'); + DOPA_zd_buf(DOPAW_1 downto 0) := (others => 'X'); + else + tmp_we(1) := addra_dly_sampled(4); + tmp_we(0) := '0'; + wea_index := SLV_TO_INT(tmp_we); + if(wea_dly_sampled(wea_index) = '1') then + DOA_zd_buf(((DOA_INDEX *DIAW) + (DIAW/2 - 1)) downto (DOA_INDEX *DIAW)) := DIA_dly((DIAW/2 - 1) downto 0); + DOPA_zd_buf(((DOPA_INDEX *DIPAW) + (DIPAW/2 - 1)) downto (DOPA_INDEX *DIPAW)) := DIPA_dly((DIPAW/2 - 1) downto 0); + end if; + + tmp_we(1) := addra_dly_sampled(4); + tmp_we(0) := '1'; + wea_index := SLV_TO_INT(tmp_we); + if(wea_dly_sampled(wea_index) = '1') then + DOA_zd_buf(((DOA_INDEX *DIAW) + DIAW_1) downto ((DOA_INDEX *DIAW) + DIAW/2 )) := DIA_dly(DIAW_1 downto DIAW/2); + DOPA_zd_buf(((DOPA_INDEX *DIPAW) + DIPAW_1) downto ((DOPA_INDEX *DIPAW) + DIPAW/2 )) := DIPA_dly(DIPAW_1 downto DIPAW/2); + end if; + + end if; + + DOA_zd(DOAW_1 downto 0) := DOA_zd_buf(DOAW_1 downto 0); + DOPA_zd(DOPAW_1 downto 0) := DOPA_zd_buf(DOPAW_1 downto 0); + + end if; + +------------------- + if(DOAW <= DIAW) then + DOA_zd_buf(DIAW_1 downto 0) := MEM((ADDRESS_WRITE_A + DIAW_1) downto ADDRESS_WRITE_A); + if(DOPAW_1 /= -1) then + DOPA_zd_buf(DIPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A)); + end if; +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + + xout_we_seg1(1) := addra_dly_sampled(4); + xout_we_seg1(0) := '0'; + xout_we_seg2(1) := addra_dly_sampled(4); + xout_we_seg2(0) := '1'; + + tmp_we(1) := addra_dly_sampled(4); + tmp_we(0) := '0'; + wea_index := SLV_TO_INT(tmp_we); + if(wea_dly_sampled(wea_index) = '1') then + DOA_zd_buf((DIAW/2 - 1) downto 0) := DIA_dly((DIAW/2 -1 ) downto 0); + if(DOPAW_1 /= -1) then + DOPA_zd_buf((DIPAW/2 - 1) downto 0) := DIPA_dly((DIPAW/2 -1 ) downto 0); + end if; + elsif(wea_dly_sampled(wea_index) = '0') then + if(wea_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= wea_dly_sampled(SLV_TO_INT(xout_we_seg2))) then + DOA_zd_buf((DIAW/2 - 1) downto 0) := (others => 'X'); + if(DOPAW_1 /= -1) then + DOPA_zd_buf((DIPAW/2 - 1) downto 0) := (others => 'X'); + end if; + end if; + end if; + + tmp_we(1) := addra_dly_sampled(4); + tmp_we(0) := '1'; + wea_index := SLV_TO_INT(tmp_we); + if(wea_dly_sampled(wea_index) = '1') then + DOA_zd_buf(DIAW_1 downto DIAW/2 ) := DIA_dly(DIAW_1 downto DIAW/2); + if(DOPAW_1 /= -1) then + DOPA_zd_buf(DIPAW_1 downto DIPAW/2 ) := DIPA_dly(DIPAW_1 downto DIPAW/2); + end if; + elsif(wea_dly_sampled(wea_index) = '0') then + if(wea_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= wea_dly_sampled(SLV_TO_INT(xout_we_seg2))) then + DOA_zd_buf(DIAW_1 downto DIAW/2 ) := (others => 'X'); + if(DOPAW_1 /= -1) then + DOPA_zd_buf(DIPAW_1 downto DIPAW/2 ) := (others => 'X'); + end if; + end if; + end if; + +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + if((wea_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= wea_dly_sampled(SLV_TO_INT(xout_we_seg2))) and (DOAW /= DIAW)) then + DOA_zd_buf(DIAW_1 downto 0) := (others => 'X'); + DOPA_zd_buf(DIPAW_1 downto 0) := (others => 'X'); + end if; + + DOA_zd(DOAW_1 downto 0) := DOA_zd_buf(((DOA_INDEX * DOAW) + DOAW_1) downto (DOA_INDEX * DOAW)); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := DOPA_zd_buf(((DOPA_INDEX * DOPAW) + DOPAW_1) downto (DOPA_INDEX * DOPAW)); + end if; + + end if; + + --------- + when 32 => + --------- + + for i in 0 to 3 loop + if (wea_dly_sampled(i) = '1') then + DOA_zd_buf(((DIAW/4)*(i+1) - 1) downto (DIAW/4)*i) := DIA_dly(((DIAW/4)*(i+1) - 1) downto (DIAW/4)*i); + if(DOPAW_1 /= -1) then + DOPA_zd_buf(((DIPAW/4)*(i+1) - 1) downto (DIPAW/4)*i) := DIPA_dly(((DIPAW/4)*(i+1) - 1) downto (DIPAW/4)*i); + end if; + elsif (wea_dly_sampled(i) = '0') then +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + DOA_zd_buf(((DIAW/4)*(i+1) - 1) downto (DIAW/4)*i) := (others => 'X'); + if(DOPAW_1 /= -1) then + DOPA_zd_buf(((DIPAW/4)*(i+1) - 1) downto (DIPAW/4)*i) := (others => 'X'); + end if; + end if; + end loop; + +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + if((wea_dly_sampled(0) = '0') and (wea_dly_sampled(1) = '0') and (wea_dly_sampled(2) = '0') and (wea_dly_sampled(3) = '0')) then + DOA_zd_buf(DIAW_1 downto 0) := MEM((ADDRESS_WRITE_A + DIAW_1) downto ADDRESS_WRITE_A); + if(DOPAW_1 /= -1) then + DOPA_zd_buf(DIPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A)); + end if; + + elsif(not((wea_dly_sampled(0) = '1') and (wea_dly_sampled(1) = '1') and (wea_dly_sampled(2) = '1') and (wea_dly_sampled(3) = '1'))) then + if(DOAW /= DIAW) then + DOA_zd_buf(DIAW_1 downto 0) := (others => 'X'); + if(DOPAW_1 /= -1) then + DOPA_zd_buf(DIPAW_1 downto 0) := (others => 'X'); + end if; + end if; + end if; + + DOA_zd(DOAW_1 downto 0) := DOA_zd_buf(((DOA_INDEX * DOAW) + DOAW_1) downto (DOA_INDEX * DOAW)); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := DOPA_zd_buf(((DOPA_INDEX * DOPAW) + DOPAW_1) downto (DOPA_INDEX * DOPAW)); + end if; + + when others => + null; + end case; + + elsif(wr_mode_a = "01") then + DOA_zd(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto (ADDRESS_READ_A)); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A)); + end if; + elsif(wr_mode_a = "10") then + case DIAW is + when 1|2|4|8 => + tmp_we(1 downto 0) := addra_dly_sampled( 4 downto 3); + wea_index := SLV_TO_INT(tmp_we); + if (wea_dly_sampled(wea_index) = '0') then + DOA_zd(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto (ADDRESS_READ_A)); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A)); + end if; + end if; + ---------- + when 16|32 => + ---------- + if ((wea_dly_sampled(0) = '0') and (wea_dly_sampled(1) = '0') and (wea_dly_sampled(2) = '0') and (wea_dly_sampled(3) = '0'))then + DOA_zd(DOAW_1 downto 0) := MEM((ADDRESS_READ_A + DOAW_1) downto (ADDRESS_READ_A)); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_A + DOPAW_1) downto (16384 + ADDRESS_PARITY_READ_A)); + end if; + end if; + ---------- + when others => + ---------- + null; + end case; + end if; + end if; + end if; -- /* end ena_dly_sampled = '1' */ + end if; + +------------------------------------------------------------------------ +------------ Port B ---------------------------------------------------- +------------------------------------------------------------------------ + if(GSR_CLKB_dly = '1') then + DOB_zd(DOBW_1 downto 0) := INI_B(DOBW_1 downto 0); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := INI_B((DOPBW_1 + DOBW) downto DOBW); + end if; + +-- CR 422403 + elsif((RSTB_dly = '1') and (rst_async_flag = '1') and (enb_dly_sampled = '1')) then + DOB_zd(DOBW_1 downto 0) := SRVA_B(DOBW_1 downto 0); + DOB_clsn_zero := (others => '0'); + DOB_clsn := (others => '0'); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := SRVA_B((DOPBW_1 + DOBW) downto DOBW); + DOPB_clsn_zero := (others => '0'); + DOPB_clsn := (others => '0'); + end if; + elsif(CLKB_dly'event AND CLKB_dly'last_value = '0') then + if (enb_dly_sampled = '1') then + if (RSTB_dly_sampled = '1') then + DOB_zd(DOBW_1 downto 0) := SRVA_B(DOBW_1 downto 0); + DOB_clsn_zero := (others => '0'); + DOB_clsn := (others => '0'); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := SRVA_B((DOPBW_1 + DOBW) downto DOBW); + DOPB_clsn_zero := (others => '0'); + DOPB_clsn := (others => '0'); + end if; + else +----------------------- Start COLLISION B ------------------------------ + if(SimCollisionCheck_var /= 0) then + DOB_clsn_sav := DOB_clsn; + DOPB_clsn_sav := DOPB_clsn; + + DOB_clsn := (others => '0'); + DOPB_clsn := (others => '0'); + clsn_xbufs.DO1_clsn := (others => '0'); + clsn_xbufs.DOP1_clsn := (others => '0'); + clsn_xbufs.MEM1_clsn := (others => '0'); + clsn_xbufs.MEMP1_clsn := (others => '0'); + + clsn_xbufs.DO2_clsn := (others => '0'); + clsn_xbufs.DOP2_clsn := (others => '0'); + clsn_xbufs.MEM2_clsn := (others => '0'); + clsn_xbufs.MEMP2_clsn := (others => '0'); + + clsn_type.active_port := 2; + addr_overlap := false; + clsn_type.read_write := false; + clsn_type.write_read := false; + clsn_type.write_write := false; + +-- CLKB_time := now; + + ClkCollisionCheck( + violation => collision_clka_clkb, + CheckEnabled => ((TO_X01(ena_dly_sampled) = '1') and (TO_X01(enb_dly_sampled) = '1')), + CLK1_time => CLKB_time, + CLK2_time => CLKA_time, + SETUP_All => SETUP_ALL, + SETUP_READ_FIRST => SETUP_READ_FIRST + ); + + if(collision_clka_clkb /= 0) then + QkAddrOverlapChk( + addr_overlap => addr_overlap, + data_widths => data_widths, + addra => addra_dly_sampled, + addrb => addrb_dly_sampled + ); + end if; + + if(addr_overlap) then + PreProcessWe1We2( + clsn_bufs => clsn_xbufs, + clsn_type => clsn_type, + memory => MEM, + di1 => dib_dly, + di2 => dia_dly, + dip1 => dipb_dly, + dip2 => dipa_dly, + addr1 => addrb_dly_sampled, + addr2 => addra_dly_sampled, + we1 => web_dly_sampled, + we2 => wea_dly_sampled, + zero_read_1 => zero_read_b, + zero_readp_1 => zero_parity_read_b, + zero_write_1 => zero_write_b, + zero_writep_1 => zero_parity_write_b, + zero_read_2 => zero_read_a, + zero_readp_2 => zero_parity_read_a, + zero_write_2 => zero_write_a, + zero_writep_2 => zero_parity_write_a, + wr_mode_1 => wr_mode_b, + wr_mode_2 => wr_mode_a, + violation => collision_clka_clkb, + DI1W => DIBW, + DIP1W => DIPBW, + DI2W => DIAW, + DIP2W => DIPAW, + DO1W => DOBW, + DOP1W => DOPBW, + DO2W => DOAW, + DOP2W => DOPAW + ); + end if; + + if(clsn_type.read_write or clsn_type.write_write or clsn_type.write_read) then + + if(clsn_type.write_write) then + collision_msg := Write_B_Write_A; +-- msg_addr1 := tmp_zero_write_b; +-- msg_addr2 := tmp_zero_write_a; + msg_addr1 := tmp_zero_write_a; + msg_addr2 := tmp_zero_write_b; + elsif(clsn_type.read_write) then + collision_msg := Read_B_Write_A; + msg_addr1 := tmp_zero_read_b; + msg_addr2 := tmp_zero_write_a; + elsif(clsn_type.write_read) then + collision_msg := Write_B_Read_A; +-- msg_addr1 := tmp_zero_write_b; +-- msg_addr2 := tmp_zero_read_a; + msg_addr1 := tmp_zero_read_a; + msg_addr2 := tmp_zero_write_b; + end if; + + if(SimCollisionCheck_var = 1) then + --- Message + Memory_Collision_Msg_ramb16 + ( collision_type => collision_msg, + EntityName => "RAMB16BWER", + InstanceName => RAMB16BWER'path_name, + address_1 => msg_addr1, + address_2 => msg_addr2 + ); + + DOB_clsn := (others => '0'); + DOPB_clsn := (others => '0'); + DOB_clsn_sav := DOB_clsn; + DOPB_clsn_sav := DOPB_clsn; + + elsif(SimCollisionCheck_var = 2) then + + DOB_clsn_read_index := SLV_TO_INT(tmp_zero_read_b(4 downto 0)); + DOA_clsn_read_index := SLV_TO_INT(tmp_zero_read_a(4 downto 0)); + + DOB_clsn(DOBW_1 downto 0) := clsn_xbufs.DO1_clsn((DOB_clsn_read_index+DOBW_1) downto DOB_clsn_read_index); + DOA_clsn(DOAW_1 downto 0) := clsn_xbufs.DO2_clsn((DOA_clsn_read_index+DOAW_1) downto DOA_clsn_read_index); + + if(DOPBW_1 /= -1) then + DOPB_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0)); + DOPB_clsn(DOPBW_1 downto 0) := clsn_xbufs.DOP1_clsn((DOPB_clsn_read_index+DOPBW_1) downto DOPB_clsn_read_index); + end if; + + if(DOPAW_1 /= -1) then + DOPA_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0)); + DOPA_clsn(DOPAW_1 downto 0) := clsn_xbufs.DOP2_clsn((DOPA_clsn_read_index+DOPAW_1) downto DOPA_clsn_read_index); + end if; + + if(wr_mode_b = "10") then + DOB_clsn(DOBW_1 downto 0) := DOB_clsn(DOBW_1 downto 0) xor DOB_clsn_sav(DOBW_1 downto 0); + if(DOPBW_1 /= -1) then + DOPB_clsn(DOPBW_1 downto 0) := DOPB_clsn(DOPBW_1 downto 0) xor DOPB_clsn_sav(DOPBW_1 downto 0); + end if; + end if; + + if(wr_mode_a = "10") then + DOA_clsn(DOAW_1 downto 0) := DOA_clsn(DOAW_1 downto 0) xor DOA_clsn_sav(DOAW_1 downto 0); + if(DOPAW_1 /= -1) then + DOPA_clsn(DOPAW_1 downto 0) := DOPA_clsn(DOPAW_1 downto 0) xor DOPA_clsn_sav(DOPAW_1 downto 0); + end if; + end if; + + + elsif(SimCollisionCheck_var = 3) then + --- Message + Memory_Collision_Msg_ramb16 + ( collision_type => collision_msg, + EntityName => "RAMB16BWER", + InstanceName => RAMB16BWER'path_name, + address_1 => msg_addr1, + address_2 => msg_addr2 + ); + + + DOB_clsn_read_index := SLV_TO_INT(tmp_zero_read_b(4 downto 0)); + DOA_clsn_read_index := SLV_TO_INT(tmp_zero_read_a(4 downto 0)); + + DOB_clsn(DOBW_1 downto 0) := clsn_xbufs.DO1_clsn((DOB_clsn_read_index+DOBW_1) downto DOB_clsn_read_index); + DOA_clsn(DOAW_1 downto 0) := clsn_xbufs.DO2_clsn((DOA_clsn_read_index+DOAW_1) downto DOA_clsn_read_index); + + if(DOPBW_1 /= -1) then + DOPB_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_b(1 downto 0)); + DOPB_clsn(DOPBW_1 downto 0) := clsn_xbufs.DOP1_clsn((DOPB_clsn_read_index+DOPBW_1) downto DOPB_clsn_read_index); + end if; + + if(DOPAW_1 /= -1) then + DOPA_clsn_read_index := SLV_TO_INT(tmp_zero_parity_read_a(1 downto 0)); + DOPA_clsn(DOPAW_1 downto 0) := clsn_xbufs.DOP2_clsn((DOPA_clsn_read_index+DOPAW_1) downto DOPA_clsn_read_index); + end if; + + if(wr_mode_b = "10") then + DOB_clsn(DOBW_1 downto 0) := DOB_clsn(DOBW_1 downto 0) xor DOB_clsn_sav(DOBW_1 downto 0); + if(DOPBW_1 /= -1) then + DOPB_clsn(DOPBW_1 downto 0) := DOPB_clsn(DOPBW_1 downto 0) xor DOPB_clsn_sav(DOPBW_1 downto 0); + end if; + end if; + + if(wr_mode_a = "10") then + DOA_clsn(DOAW_1 downto 0) := DOA_clsn(DOAW_1 downto 0) xor DOA_clsn_sav(DOAW_1 downto 0); + if(DOPAW_1 /= -1) then + DOPA_clsn(DOPAW_1 downto 0) := DOPA_clsn(DOPAW_1 downto 0) xor DOPA_clsn_sav(DOPAW_1 downto 0); + end if; + end if; + + end if; + + end if; + + DOB_clsn_zero := DOB_clsn; + DOPB_clsn_zero := DOPB_clsn; + if(RSTA_dly_sampled = '0') then + DOA_clsn_zero := DOA_clsn; + DOPA_clsn_zero := DOPA_clsn; + end if; + + end if; + +---------------- END COLLISION B ------------------------------ + if (wr_mode_b = "00") then + + case DIBW is + --------- + when 1|2|4|8 => + --------- + tmp_we(1 downto 0) := addrb_dly_sampled( 4 downto 3); + web_index := SLV_TO_INT(tmp_we); + if(web_dly_sampled(web_index) = '1') then + if(DOBW > DIBW) then + DOB_zd_buf(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto ADDRESS_READ_B); + DOB_zd_buf(((DOB_INDEX *DIBW) + DIBW_1) downto (DOB_INDEX *DIBW)) := DIB_dly(DIBW_1 downto 0); + DOB_zd(DOBW_1 downto 0) := DOB_zd_buf(DOBW_1 downto 0); + + if(DOPBW_1 /= -1) then + DOPB_zd_buf(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B)); + DOPB_zd_buf(((DOPB_INDEX *DIPBW) + DIPBW_1) downto (DOPB_INDEX *DIPBW)) := DIPB_dly(DIPBW_1 downto 0); + DOPB_zd(DOPBW_1 downto 0) := DOPB_zd_buf(DOPBW_1 downto 0); + end if; + elsif(DOBW <= DIBW) then +--FP DOB_zd(DOBW_1 downto 0) := DIB_dly(DOBW_1 downto 0); + DOB_zd(DOBW_1 downto 0) := DIB_dly((((DOB_INDEX)*DOBW)+ DOBW_1) downto ((DOB_INDEX)*DOBW)); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := DIPB_dly(DOPBW_1 downto 0); + end if; + end if; + elsif(web_dly_sampled(web_index) = '0') then + DOB_zd(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto (ADDRESS_READ_B)); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B)); + end if; + end if; + + --------- + when 16 => + --------- + if(DOBW > DIBW) then + DOB_zd_buf(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto ADDRESS_READ_B); + DOPB_zd_buf(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B)); +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + + xout_we_seg1(1) := addrb_dly_sampled(4); + xout_we_seg1(0) := '0'; + xout_we_seg2(1) := addrb_dly_sampled(4); + xout_we_seg2(0) := '1'; + + if(web_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= web_dly_sampled(SLV_TO_INT(xout_we_seg2))) then + DOB_zd_buf(DOBW_1 downto 0) := (others => 'X'); + DOPB_zd_buf(DOPBW_1 downto 0) := (others => 'X'); + else + tmp_we(1) := addrb_dly_sampled(4); + tmp_we(0) := '0'; + web_index := SLV_TO_INT(tmp_we); + if(web_dly_sampled(web_index) = '1') then + DOB_zd_buf(((DOB_INDEX *DIBW) + (DIBW/2 - 1)) downto (DOB_INDEX *DIBW)) := DIB_dly((DIBW/2 - 1) downto 0); + DOPB_zd_buf(((DOPB_INDEX *DIPBW) + (DIPBW/2 - 1)) downto (DOPB_INDEX *DIPBW)) := DIPB_dly((DIPBW/2 - 1) downto 0); + end if; + + tmp_we(1) := addrb_dly_sampled(4); + tmp_we(0) := '1'; + web_index := SLV_TO_INT(tmp_we); + if(web_dly_sampled(web_index) = '1') then + DOB_zd_buf(((DOB_INDEX *DIBW) + DIBW_1) downto ((DOB_INDEX *DIBW) + DIBW/2 )) := DIB_dly(DIBW_1 downto DIBW/2); + DOPB_zd_buf(((DOPB_INDEX *DIPBW) + DIPBW_1) downto ((DOPB_INDEX *DIPBW) + DIPBW/2 )) := DIPB_dly(DIPBW_1 downto DIPBW/2); + end if; + + end if; + + DOB_zd(DOBW_1 downto 0) := DOB_zd_buf(DOBW_1 downto 0); + DOPB_zd(DOPBW_1 downto 0) := DOPB_zd_buf(DOPBW_1 downto 0); + + end if; + +------------------- + if(DOBW <= DIBW) then + DOB_zd_buf(DIBW_1 downto 0) := MEM((ADDRESS_WRITE_B + DIBW_1) downto ADDRESS_WRITE_B); + if(DOPBW_1 /= -1) then + DOPB_zd_buf(DIPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B)); + end if; +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + + xout_we_seg1(1) := addrb_dly_sampled(4); + xout_we_seg1(0) := '0'; + xout_we_seg2(1) := addrb_dly_sampled(4); + xout_we_seg2(0) := '1'; + + tmp_we(1) := addrb_dly_sampled(4); + tmp_we(0) := '0'; + web_index := SLV_TO_INT(tmp_we); + if(web_dly_sampled(web_index) = '1') then + DOB_zd_buf((DIBW/2 - 1) downto 0) := DIB_dly((DIBW/2 -1 ) downto 0); + if(DOPBW_1 /= -1) then + DOPB_zd_buf((DIPBW/2 - 1) downto 0) := DIPB_dly((DIPBW/2 -1 ) downto 0); + end if; + elsif(web_dly_sampled(web_index) = '0') then + if(web_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= web_dly_sampled(SLV_TO_INT(xout_we_seg2))) then + DOB_zd_buf((DIBW/2 - 1) downto 0) := (others => 'X'); + if(DOPBW_1 /= -1) then + DOPB_zd_buf((DIPBW/2 - 1) downto 0) := (others => 'X'); + end if; + end if; + end if; + + tmp_we(1) := addrb_dly_sampled(4); + tmp_we(0) := '1'; + web_index := SLV_TO_INT(tmp_we); + if(web_dly_sampled(web_index) = '1') then + DOB_zd_buf(DIBW_1 downto DIBW/2 ) := DIB_dly(DIBW_1 downto DIBW/2); + if(DOPBW_1 /= -1) then + DOPB_zd_buf(DIPBW_1 downto DIPBW/2 ) := DIPB_dly(DIPBW_1 downto DIPBW/2); + end if; + elsif(web_dly_sampled(web_index) = '0') then + if(web_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= web_dly_sampled(SLV_TO_INT(xout_we_seg2))) then + DOB_zd_buf(DIBW_1 downto DIBW/2 ) := (others => 'X'); + if(DOPBW_1 /= -1) then + DOPB_zd_buf(DIPBW_1 downto DIPBW/2 ) := (others => 'X'); + end if; + end if; + end if; + +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + if((web_dly_sampled(SLV_TO_INT(xout_we_seg1)) /= web_dly_sampled(SLV_TO_INT(xout_we_seg2))) and (DOBW /= DIBW)) then + DOB_zd_buf(DIBW_1 downto 0) := (others => 'X'); + DOPB_zd_buf(DIPBW_1 downto 0) := (others => 'X'); + end if; + + DOB_zd(DOBW_1 downto 0) := DOB_zd_buf(((DOB_INDEX * DOBW) + DOBW_1) downto (DOB_INDEX * DOBW)); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := DOPB_zd_buf(((DOPB_INDEX * DOPBW) + DOPBW_1) downto (DOPB_INDEX * DOPBW)); + end if; + + end if; + + --------- + when 32 => + --------- + for i in 0 to 3 loop + if (web_dly_sampled(i) = '1') then + DOB_zd_buf(((DIBW/4)*(i+1) - 1) downto (DIBW/4)*i) := DIB_dly(((DIBW/4)*(i+1) - 1) downto (DIBW/4)*i); + if(DOPBW_1 /= -1) then + DOPB_zd_buf(((DIPBW/4)*(i+1) - 1) downto (DIPBW/4)*i) := DIPB_dly(((DIPBW/4)*(i+1) - 1) downto (DIPBW/4)*i); + end if; + elsif (web_dly_sampled(i) = '0') then +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + DOB_zd_buf(((DIBW/4)*(i+1) - 1) downto (DIBW/4)*i) := (others => 'X'); + if(DOPBW_1 /= -1) then + DOPB_zd_buf(((DIPBW/4)*(i+1) - 1) downto (DIPBW/4)*i) := (others => 'X'); + end if; + end if; + end loop; +-- The following code was added to "X" the output in WRITE_FIRST_MODE when DO /= DI and the WE[--] segments are not all 0's or all 1's + if((web_dly_sampled(0) = '0') and (web_dly_sampled(1) = '0') and (web_dly_sampled(2) = '0') and (web_dly_sampled(3) = '0')) then + DOB_zd_buf(DIBW_1 downto 0) := MEM((ADDRESS_WRITE_B + DIBW_1) downto ADDRESS_WRITE_B); + if(DOPBW_1 /= -1) then + DOPB_zd_buf(DIPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B)); + end if; + elsif(not((web_dly_sampled(0) = '1') and (web_dly_sampled(1) = '1') and (web_dly_sampled(2) = '1') and (web_dly_sampled(3) = '1'))) then + if(DOBW /= DIBW) then + DOB_zd_buf(DIBW_1 downto 0) := (others => 'X'); + if(DOPBW_1 /= -1) then + DOPB_zd_buf(DIPBW_1 downto 0) := (others => 'X'); + end if; + end if; + end if; + + DOB_zd(DOBW_1 downto 0) := DOB_zd_buf(((DOB_INDEX * DOBW) + DOBW_1) downto (DOB_INDEX * DOBW)); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := DOPB_zd_buf(((DOPB_INDEX * DOPBW) + DOPBW_1) downto (DOPB_INDEX * DOPBW)); + end if; + + when others => + null; + end case; + + elsif(wr_mode_b = "01") then + DOB_zd(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto (ADDRESS_READ_B)); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B)); + end if; + elsif(wr_mode_b = "10") then + case DIBW is + when 1|2|4|8 => + tmp_we(1 downto 0) := addrb_dly_sampled( 4 downto 3); + web_index := SLV_TO_INT(tmp_we); + if (web_dly_sampled(web_index) = '0') then + DOB_zd(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto (ADDRESS_READ_B)); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B)); + end if; + end if; + ---------- + when 16|32 => + ---------- + if ((web_dly_sampled(0) = '0') and (web_dly_sampled(1) = '0') and (web_dly_sampled(2) = '0') and (web_dly_sampled(3) = '0'))then + DOB_zd(DOBW_1 downto 0) := MEM((ADDRESS_READ_B + DOBW_1) downto (ADDRESS_READ_B)); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_READ_B + DOPBW_1) downto (16384 + ADDRESS_PARITY_READ_B)); + end if; + end if; + ---------- + when others => + ---------- + null; + end case; + end if; + end if; + end if; -- /* end enb_dly_sampled = '1' */ + end if; + +------------------------------------------------------------------------ +------------ Port A -- Memory Update ---------------------------------- +------------------------------------------------------------------------ + + if((GSR_CLKA_dly = '0') and rising_edge(CLKA_dly)) then + if (ena_dly_sampled = '1') then + case DIAW is + -------------- + when 1|2|4|8 => + -------------- + tmp_we(1 downto 0) := addra_dly_sampled( 4 downto 3); + wea_index := SLV_TO_INT(tmp_we); + if (wea_dly_sampled(wea_index) = '1') then + if (VALID_ADDRA) then + MEM((ADDRESS_WRITE_A + DIAW_1) downto (ADDRESS_WRITE_A)) := DIA_dly(DIAW_1 downto 0); + if(DIPAW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A)) := DIPA_dly(DIPAW_1 downto 0); + end if; + else + DOA_zd(DOAW_1 downto 0) := (others => 'X'); + if(DOPAW_1 /= -1) then + DOPA_zd(DOPAW_1 downto 0) := (others => 'X'); + end if; + end if; -- /* VAILD ADDRA */ + end if; -- /* wea_dly_sampled = '1' */ + + --------- + when 16 => + --------- + tmp_we(1) := addra_dly_sampled(4); + tmp_we(0) := '0'; + wea_index := SLV_TO_INT(tmp_we); + if (wea_dly_sampled(wea_index) = '1') then + if (VALID_ADDRA) then + MEM((ADDRESS_WRITE_A + DIAW/2 -1) downto (ADDRESS_WRITE_A)) := DIA_dly((DIAW/2 - 1) downto 0); + if(DIPAW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW/2 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A)) := DIPA_dly((DIPAW/2 -1) downto 0); + end if; + end if; -- /* VAILD ADDRA */ + end if; -- /* wea_dly_sampled = '1' */ + + tmp_we(0) := '1'; + wea_index := SLV_TO_INT(tmp_we); + if (wea_dly_sampled(wea_index) = '1') then + if (VALID_ADDRA) then + MEM((ADDRESS_WRITE_A + DIAW_1) downto (ADDRESS_WRITE_A + DIAW/2)) := DIA_dly(DIAW_1 downto DIAW/2); + if(DIPAW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A + DIPAW/2)) := DIPA_dly(DIPAW_1 downto DIPAW/2); + end if; + end if; -- /* VAILD ADDRA */ + end if; -- /* wea_dly_sampled = '1' */ + + --------- + when 32 => + --------- + wea_index := 0; + if (wea_dly_sampled(wea_index) = '1') then + if (VALID_ADDRA) then + MEM((ADDRESS_WRITE_A + (DIAW/4)*1 -1) downto (ADDRESS_WRITE_A)) := DIA_dly((((DIAW/4)*1) - 1) downto 0); + if(DIPAW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*1 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A)) := DIPA_dly(((DIPAW/4)*1 -1) downto 0); + end if; + end if; -- /* VAILD ADDRA */ + end if; -- /* wea_dly_sampled = '1' */ + + wea_index := 1; + if (wea_dly_sampled(wea_index) = '1') then + if (VALID_ADDRA) then + MEM((ADDRESS_WRITE_A + (DIAW/4)*2 -1) downto (ADDRESS_WRITE_A + (DIAW/4)*1)) := DIA_dly((((DIAW/4)*2) - 1) downto (DIAW/4)*1); + if(DIPAW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*2 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*1)) := DIPA_dly(((DIPAW/4)*2 -1) downto ((DIPAW/4)*1)); + end if; + end if; -- /* VAILD ADDRA */ + end if; -- /* wea_dly_sampled = '1' */ + + wea_index := 2; + if (wea_dly_sampled(wea_index) = '1') then + if (VALID_ADDRA) then + MEM((ADDRESS_WRITE_A + (DIAW/4)*3 -1) downto (ADDRESS_WRITE_A + (DIAW/4)*2)) := DIA_dly((((DIAW/4)*3) - 1) downto (DIAW/4)*2); + if(DIPAW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*3 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*2)) := DIPA_dly(((DIPAW/4)*3 -1) downto ((DIPAW/4)*2)); + end if; + end if; -- /* VAILD ADDRA */ + end if; -- /* wea_dly_sampled = '1' */ + + wea_index := 3; + if (wea_dly_sampled(wea_index) = '1') then + if (VALID_ADDRA) then + MEM((ADDRESS_WRITE_A + (DIAW/4)*4 -1) downto (ADDRESS_WRITE_A + (DIAW/4)*3)) := DIA_dly((((DIAW/4)*4) - 1) downto (DIAW/4)*3); + if(DIPAW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*4 - 1) downto (16384 + ADDRESS_PARITY_WRITE_A + (DIPAW/4)*3)) := DIPA_dly(((DIPAW/4)*4 -1) downto ((DIPAW/4)*3)); + end if; + end if; -- /* VAILD ADDRA */ + end if; -- /* wea_dly_sampled = '1' */ + when others => + null; + end case; + +----------------------- Start COLLISION MEMORY UPDATE A ------------------------------ + + if(SimCollisionCheck_var /= 0) then + if(clsn_type.write_write) then + tmp_membuf := (others => '0'); + DOA_clsn_write_index := SLV_TO_INT(tmp_zero_write_a(4 downto 0)); + tmp_membuf(DIAW_1 downto 0) := MEM((ADDRESS_WRITE_A + DIAW_1) downto (ADDRESS_WRITE_A)); + MEM((ADDRESS_WRITE_A + DIAW_1) downto (ADDRESS_WRITE_A)) := tmp_membuf(DIAW_1 downto 0) xor clsn_xbufs.MEM1_clsn((DOA_clsn_write_index+DIAW_1) downto DOA_clsn_write_index); + + if((DIPAW_1 /= -1) and (DIPBW_1 /= -1)) then + tmp_membuf := (others => '0'); + DOPA_clsn_write_index := SLV_TO_INT(tmp_zero_parity_write_a(1 downto 0)); + tmp_membuf(DIPAW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A)); + MEM((16384 + ADDRESS_PARITY_WRITE_A + DIPAW_1) downto (16384 + ADDRESS_PARITY_WRITE_A)) := tmp_membuf(DIPAW_1 downto 0) xor clsn_xbufs.MEMP1_clsn((DOPA_clsn_write_index + DIPAW_1) downto DOPA_clsn_write_index); + end if; + end if; + end if; + +----------------------- END COLLISION MEMORY UPDATE A ------------------------------ + + end if; -- /* end ena_dly_sampled = '1' */ + end if; +------------------------------------------------------------------------ +------------ Port B -- Memory Update ---------------------------------- +------------------------------------------------------------------------ + + if((GSR_CLKB_dly = '0') and rising_edge(CLKB_dly)) then + if (enb_dly_sampled = '1') then + case DIBW is + -------------- + when 1|2|4|8 => + -------------- + tmp_we(1 downto 0) := addrb_dly_sampled( 4 downto 3); + web_index := SLV_TO_INT(tmp_we); + if (web_dly_sampled(web_index) = '1') then + if (VALID_ADDRB) then + MEM((ADDRESS_WRITE_B + DIBW_1) downto (ADDRESS_WRITE_B)) := DIB_dly(DIBW_1 downto 0); + if(DIPBW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B)) := DIPB_dly(DIPBW_1 downto 0); + end if; + else + DOB_zd(DOBW_1 downto 0) := (others => 'X'); + if(DOPBW_1 /= -1) then + DOPB_zd(DOPBW_1 downto 0) := (others => 'X'); + end if; + end if; -- /* VAILD ADDRB */ + end if; -- /* web_dly_sampled = '1' */ + + --------- + when 16 => + --------- + tmp_we(1) := addrb_dly_sampled(4); + tmp_we(0) := '0'; + web_index := SLV_TO_INT(tmp_we); + if (web_dly_sampled(web_index) = '1') then + if (VALID_ADDRB) then + MEM((ADDRESS_WRITE_B + DIBW/2 -1) downto (ADDRESS_WRITE_B)) := DIB_dly((DIBW/2 - 1) downto 0); + if(DIPBW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW/2 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B)) := DIPB_dly((DIPBW/2 -1) downto 0); + end if; + end if; -- /* VAILD ADDRB */ + end if; -- /* web_dly_sampled = '1' */ + + tmp_we(0) := '1'; + web_index := SLV_TO_INT(tmp_we); + if (web_dly_sampled(web_index) = '1') then + if (VALID_ADDRB) then + MEM((ADDRESS_WRITE_B + DIBW_1) downto (ADDRESS_WRITE_B + DIBW/2)) := DIB_dly(DIBW_1 downto DIBW/2); + if(DIPBW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B + DIPBW/2)) := DIPB_dly(DIPBW_1 downto DIPBW/2); + end if; + end if; -- /* VAILD ADDRB */ + end if; -- /* web_dly_sampled = '1' */ + + --------- + when 32 => + --------- + web_index := 0; + if (web_dly_sampled(web_index) = '1') then + if (VALID_ADDRB) then + MEM((ADDRESS_WRITE_B + (DIBW/4)*1 -1) downto (ADDRESS_WRITE_B)) := DIB_dly((((DIBW/4)*1) - 1) downto 0); + if(DIPBW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*1 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B)) := DIPB_dly(((DIPBW/4)*1 -1) downto 0); + end if; + end if; -- /* VAILD ADDRB */ + end if; -- /* web_dly_sampled = '1' */ + + web_index := 1; + if (web_dly_sampled(web_index) = '1') then + if (VALID_ADDRB) then + MEM((ADDRESS_WRITE_B + (DIBW/4)*2 -1) downto (ADDRESS_WRITE_B + (DIBW/4)*1)) := DIB_dly((((DIBW/4)*2) - 1) downto (DIBW/4)*1); + if(DIPBW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*2 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*1)) := DIPB_dly(((DIPBW/4)*2 -1) downto ((DIPBW/4)*1)); + end if; + end if; -- /* VAILD ADDRB */ + end if; -- /* web_dly_sampled = '1' */ + + web_index := 2; + if (web_dly_sampled(web_index) = '1') then + if (VALID_ADDRB) then + MEM((ADDRESS_WRITE_B + (DIBW/4)*3 -1) downto (ADDRESS_WRITE_B + (DIBW/4)*2)) := DIB_dly((((DIBW/4)*3) - 1) downto (DIBW/4)*2); + if(DIPBW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*3 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*2)) := DIPB_dly(((DIPBW/4)*3 -1) downto ((DIPBW/4)*2)); + end if; + end if; -- /* VAILD ADDRB */ + end if; -- /* web_dly_sampled = '1' */ + + web_index := 3; + if (web_dly_sampled(web_index) = '1') then + if (VALID_ADDRB) then + MEM((ADDRESS_WRITE_B + (DIBW/4)*4 -1) downto (ADDRESS_WRITE_B + (DIBW/4)*3)) := DIB_dly((((DIBW/4)*4) - 1) downto (DIBW/4)*3); + if(DIPBW_1 /= -1) then + MEM((16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*4 - 1) downto (16384 + ADDRESS_PARITY_WRITE_B + (DIPBW/4)*3)) := DIPB_dly(((DIPBW/4)*4 -1) downto ((DIPBW/4)*3)); + end if; + end if; -- /* VAILD ADDRB */ + end if; -- /* web_dly_sampled = '1' */ + when others => + null; + end case; + +----------------------- Start COLLISION MEMORY UPDATE B ------------------------------ + + if(SimCollisionCheck_var /= 0) then + if(clsn_type.write_write) then + tmp_membuf := (others => '0'); + DOB_clsn_write_index := SLV_TO_INT(tmp_zero_write_b(4 downto 0)); + tmp_membuf(DIBW_1 downto 0) := MEM((ADDRESS_WRITE_B + DIBW_1) downto (ADDRESS_WRITE_B)); + MEM((ADDRESS_WRITE_B + DIBW_1) downto (ADDRESS_WRITE_B)) := tmp_membuf(DIBW_1 downto 0) xor clsn_xbufs.MEM1_clsn((DOB_clsn_write_index+DIBW_1) downto DOB_clsn_write_index); + + if((DIPBW_1 /= -1) and (DIPAW_1 /= -1)) then + tmp_membuf := (others => '0'); + DOPB_clsn_write_index := SLV_TO_INT(tmp_zero_parity_write_b(1 downto 0)); + tmp_membuf(DIPBW_1 downto 0) := MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B)); + MEM((16384 + ADDRESS_PARITY_WRITE_B + DIPBW_1) downto (16384 + ADDRESS_PARITY_WRITE_B)) := tmp_membuf(DIPBW_1 downto 0) xor clsn_xbufs.MEMP1_clsn((DOPB_clsn_write_index + DIPBW_1) downto DOPB_clsn_write_index); + end if; + end if; + end if; + +----------------------- END COLLISION MEMORY UPDATE B ------------------------------ + + end if; -- /* end enb_dly_sampled = '1' */ + end if; +--======================================================================================= +----- Port A + + DOA_viol(0) <= ViolationA xor DOA_zd(0) xor DOA_clsn_zero(0); + DOA_viol(1) <= ViolationA xor DOA_zd(1) xor DOA_clsn_zero(1); + DOA_viol(2) <= ViolationA xor DOA_zd(2) xor DOA_clsn_zero(2); + DOA_viol(3) <= ViolationA xor DOA_zd(3) xor DOA_clsn_zero(3); + DOA_viol(4) <= ViolationA xor DOA_zd(4) xor DOA_clsn_zero(4); + DOA_viol(5) <= ViolationA xor DOA_zd(5) xor DOA_clsn_zero(5); + DOA_viol(6) <= ViolationA xor DOA_zd(6) xor DOA_clsn_zero(6); + DOA_viol(7) <= ViolationA xor DOA_zd(7) xor DOA_clsn_zero(7); + DOA_viol(8) <= ViolationA xor DOA_zd(8) xor DOA_clsn_zero(8); + DOA_viol(9) <= ViolationA xor DOA_zd(9) xor DOA_clsn_zero(9); + DOA_viol(10) <= ViolationA xor DOA_zd(10) xor DOA_clsn_zero(10); + DOA_viol(11) <= ViolationA xor DOA_zd(11) xor DOA_clsn_zero(11); + DOA_viol(12) <= ViolationA xor DOA_zd(12) xor DOA_clsn_zero(12); + DOA_viol(13) <= ViolationA xor DOA_zd(13) xor DOA_clsn_zero(13); + DOA_viol(14) <= ViolationA xor DOA_zd(14) xor DOA_clsn_zero(14); + DOA_viol(15) <= ViolationA xor DOA_zd(15) xor DOA_clsn_zero(15); + DOA_viol(16) <= ViolationA xor DOA_zd(16) xor DOA_clsn_zero(16); + DOA_viol(17) <= ViolationA xor DOA_zd(17) xor DOA_clsn_zero(17); + DOA_viol(18) <= ViolationA xor DOA_zd(18) xor DOA_clsn_zero(18); + DOA_viol(19) <= ViolationA xor DOA_zd(19) xor DOA_clsn_zero(19); + DOA_viol(20) <= ViolationA xor DOA_zd(20) xor DOA_clsn_zero(20); + DOA_viol(21) <= ViolationA xor DOA_zd(21) xor DOA_clsn_zero(21); + DOA_viol(22) <= ViolationA xor DOA_zd(22) xor DOA_clsn_zero(22); + DOA_viol(23) <= ViolationA xor DOA_zd(23) xor DOA_clsn_zero(23); + DOA_viol(24) <= ViolationA xor DOA_zd(24) xor DOA_clsn_zero(24); + DOA_viol(25) <= ViolationA xor DOA_zd(25) xor DOA_clsn_zero(25); + DOA_viol(26) <= ViolationA xor DOA_zd(26) xor DOA_clsn_zero(26); + DOA_viol(27) <= ViolationA xor DOA_zd(27) xor DOA_clsn_zero(27); + DOA_viol(28) <= ViolationA xor DOA_zd(28) xor DOA_clsn_zero(28); + DOA_viol(29) <= ViolationA xor DOA_zd(29) xor DOA_clsn_zero(29); + DOA_viol(30) <= ViolationA xor DOA_zd(30) xor DOA_clsn_zero(30); + DOA_viol(31) <= ViolationA xor DOA_zd(31) xor DOA_clsn_zero(31); + DOPA_viol(0) <= ViolationA xor DOPA_zd(0) xor DOPA_clsn_zero(0); + DOPA_viol(1) <= ViolationA xor DOPA_zd(1) xor DOPA_clsn_zero(1); + DOPA_viol(2) <= ViolationA xor DOPA_zd(2) xor DOPA_clsn_zero(2); + DOPA_viol(3) <= ViolationA xor DOPA_zd(3) xor DOPA_clsn_zero(3); + +----- Port B + + DOB_viol(0) <= ViolationB xor DOB_zd(0) xor DOB_clsn_zero(0); + DOB_viol(1) <= ViolationB xor DOB_zd(1) xor DOB_clsn_zero(1); + DOB_viol(2) <= ViolationB xor DOB_zd(2) xor DOB_clsn_zero(2); + DOB_viol(3) <= ViolationB xor DOB_zd(3) xor DOB_clsn_zero(3); + DOB_viol(4) <= ViolationB xor DOB_zd(4) xor DOB_clsn_zero(4); + DOB_viol(5) <= ViolationB xor DOB_zd(5) xor DOB_clsn_zero(5); + DOB_viol(6) <= ViolationB xor DOB_zd(6) xor DOB_clsn_zero(6); + DOB_viol(7) <= ViolationB xor DOB_zd(7) xor DOB_clsn_zero(7); + DOB_viol(8) <= ViolationB xor DOB_zd(8) xor DOB_clsn_zero(8); + DOB_viol(9) <= ViolationB xor DOB_zd(9) xor DOB_clsn_zero(9); + DOB_viol(10) <= ViolationB xor DOB_zd(10) xor DOB_clsn_zero(10); + DOB_viol(11) <= ViolationB xor DOB_zd(11) xor DOB_clsn_zero(11); + DOB_viol(12) <= ViolationB xor DOB_zd(12) xor DOB_clsn_zero(12); + DOB_viol(13) <= ViolationB xor DOB_zd(13) xor DOB_clsn_zero(13); + DOB_viol(14) <= ViolationB xor DOB_zd(14) xor DOB_clsn_zero(14); + DOB_viol(15) <= ViolationB xor DOB_zd(15) xor DOB_clsn_zero(15); + DOB_viol(16) <= ViolationB xor DOB_zd(16) xor DOB_clsn_zero(16); + DOB_viol(17) <= ViolationB xor DOB_zd(17) xor DOB_clsn_zero(17); + DOB_viol(18) <= ViolationB xor DOB_zd(18) xor DOB_clsn_zero(18); + DOB_viol(19) <= ViolationB xor DOB_zd(19) xor DOB_clsn_zero(19); + DOB_viol(20) <= ViolationB xor DOB_zd(20) xor DOB_clsn_zero(20); + DOB_viol(21) <= ViolationB xor DOB_zd(21) xor DOB_clsn_zero(21); + DOB_viol(22) <= ViolationB xor DOB_zd(22) xor DOB_clsn_zero(22); + DOB_viol(23) <= ViolationB xor DOB_zd(23) xor DOB_clsn_zero(23); + DOB_viol(24) <= ViolationB xor DOB_zd(24) xor DOB_clsn_zero(24); + DOB_viol(25) <= ViolationB xor DOB_zd(25) xor DOB_clsn_zero(25); + DOB_viol(26) <= ViolationB xor DOB_zd(26) xor DOB_clsn_zero(26); + DOB_viol(27) <= ViolationB xor DOB_zd(27) xor DOB_clsn_zero(27); + DOB_viol(28) <= ViolationB xor DOB_zd(28) xor DOB_clsn_zero(28); + DOB_viol(29) <= ViolationB xor DOB_zd(29) xor DOB_clsn_zero(29); + DOB_viol(30) <= ViolationB xor DOB_zd(30) xor DOB_clsn_zero(30); + DOB_viol(31) <= ViolationB xor DOB_zd(31) xor DOB_clsn_zero(31); + DOPB_viol(0) <= ViolationB xor DOPB_zd(0) xor DOPB_clsn_zero(0); + DOPB_viol(1) <= ViolationB xor DOPB_zd(1) xor DOPB_clsn_zero(1); + DOPB_viol(2) <= ViolationB xor DOPB_zd(2) xor DOPB_clsn_zero(2); + DOPB_viol(3) <= ViolationB xor DOPB_zd(3) xor DOPB_clsn_zero(3); + + wait on ADDRA_dly, ADDRB_dly, CLKA_dly, CLKB_dly, DIA_dly, DIB_dly, DIPA_dly, DIPB_dly, ENA_dly, ENB_dly, GSR_ipd, GSR_CLKA_dly, GSR_CLKB_dly, REGCEA_dly, REGCEB_dly, RSTA_dly, RSTB_dly, WEA_dly, WEB_dly; + end process VITALBehavior; + +---------------------------------------------------------------------------- +------------------- Output Registers -- Port A ----------------------------- +---------------------------------------------------------------------------- + + prcs_regA:process (INIT_DONE, CLKA_dly, GSR_CLKA_dly, RSTA_dly) + variable ssra_reg_var : std_ulogic := '0'; + variable FIRST_TIME : boolean := true; + begin + +-- CR 430517 - added 1 line though it may not be necessary + ssra_reg_var := '0'; + + if(FIRST_TIME and INIT_DONE) then + DOA_regist(DOAW_1 downto 0) <= INI_A_sig(DOAW_1 downto 0); + if(DOPAW_1 /= -1) then + DOPA_regist(DOPAW_1 downto 0) <= INI_A_sig((DOPAW_1 + DOAW) downto DOAW); + end if; + FIRST_TIME := false; + elsif(DOA_REG = 1) then + if(GSR_CLKA_dly = '1') then + DOA_regist(DOAW_1 downto 0) <= INI_A_sig(DOAW_1 downto 0); + if(DOPAW_1 /= -1) then + DOPA_regist(DOPAW_1 downto 0) <= INI_A_sig((DOPAW_1 + DOAW) downto DOAW); + end if; + ssra_reg_var := '0'; +-- CR 426962 +-- elsif((GSR_CLKA_dly = '0') and (ENA_dly = '1'))then + elsif (GSR_CLKA_dly = '0') then + if(ENA_dly = '1') then + ssra_reg_var := RSTA_dly; + end if; + case rst_async_flag is + when '1' => + -----------// async reset +-- CR 427370 fix + if((RSTA_dly = '1') and (ENA_dly = '1'))then + DOA_regist(DOAW_1 downto 0) <= SRVA_A_sig(DOAW_1 downto 0); + if(DOPAW_1 /= -1) then + DOPA_regist(DOPAW_1 downto 0) <= SRVA_A_sig((DOPAW_1 + DOAW) downto DOAW); + end if; +-- elsif ((RSTA_dly = '0') and (REGCEA_dly = '1')) then + elsif ((ssra_reg_var = '0') and (REGCEA_dly = '1')) then + if(rising_edge(CLKA_dly)) then + DOA_regist <= DOA_viol; + DOPA_regist <= DOPA_viol; + end if; + end if; + + when '0' => + if(rising_edge(CLKA_dly)) then +-- if(RSTA_dly = '1') then + if(ssra_reg_var = '1') then + DOA_regist(DOAW_1 downto 0) <= SRVA_A_sig(DOAW_1 downto 0); + if(DOPAW_1 /= -1) then + DOPA_regist(DOPAW_1 downto 0) <= SRVA_A_sig((DOPAW_1 + DOAW) downto DOAW); + end if; +-- elsif ((RSTA_dly = '0') and (REGCEA_dly = '1')) then + elsif ((ssra_reg_var = '0') and (REGCEA_dly = '1')) then + DOA_regist <= DOA_viol; + DOPA_regist <= DOPA_viol; + end if; + end if; + when others => null; + end case; + + end if; + end if; + end process prcs_regA; +----------------------------------------------------------------------------------- + prcs_PipeLineA:process (INIT_DONE, DOA_viol, DOPA_viol, DOA_regist, DOPA_regist) + variable FIRST_TIME : boolean := true; + begin + if(FIRST_TIME) then + if(INIT_DONE) then + DOA_mux(DOAW_1 downto 0) <= INI_A_sig(DOAW_1 downto 0); + if(DOPAW_1 /= -1) then + DOPA_mux(DOPAW_1 downto 0) <= INI_A_sig((DOPAW_1 + DOAW) downto DOAW); + end if; + FIRST_TIME := false; + end if; + else + case DOA_REG is + when 0 => + DOA_mux <= DOA_viol; + DOPA_mux <= DOPA_viol; + + when 1 => + DOA_mux <= DOA_regist; + DOPA_mux <= DOPA_regist; + when others => + assert false + report "Attribute Syntax Error : The allowed values for DOA_REG are 0 or 1" + severity Failure; + end case; + end if; + end process prcs_PipeLineA; + +---------------------------------------------------------------------------- +------------------- Output Registers -- Port B ----------------------------- +---------------------------------------------------------------------------- + + prcs_regB:process (INIT_DONE, CLKB_dly, GSR_CLKB_dly, RSTB_dly) + variable ssrb_reg_var : std_ulogic := '0'; + variable FIRST_TIME : boolean := true; + begin + +-- CR 430517 - added 1 line though it may not be necessary + ssrb_reg_var := '0'; + + if(FIRST_TIME and INIT_DONE) then + DOB_regist(DOBW_1 downto 0) <= INI_B_sig(DOBW_1 downto 0); + if(DOPBW_1 /= -1) then + DOPB_regist(DOPBW_1 downto 0) <= INI_B_sig((DOPBW_1 + DOBW) downto DOBW); + end if; + FIRST_TIME := false; + elsif(DOB_REG = 1) then + if(GSR_CLKB_dly = '1') then + DOB_regist(DOBW_1 downto 0) <= INI_B_sig(DOBW_1 downto 0); + if(DOPBW_1 /= -1) then + DOPB_regist(DOPBW_1 downto 0) <= INI_B_sig((DOPBW_1 + DOBW) downto DOBW); + end if; + ssrb_reg_var := '0'; +-- CR 426962 +-- elsif((GSR_CLKB_dly = '0') and (ENB_dly = '1'))then + elsif(GSR_CLKB_dly = '0') then + if(ENB_dly = '1') then + ssrb_reg_var := RSTB_dly; + end if; + case rst_async_flag is + when '1' => + -----------// async reset +-- CR 427370 fix + if((RSTB_dly = '1') and (ENB_dly = '1')) then + DOB_regist(DOBW_1 downto 0) <= SRVA_B_sig(DOBW_1 downto 0); + if(DOPBW_1 /= -1) then + DOPB_regist(DOPBW_1 downto 0) <= SRVA_B_sig((DOPBW_1 + DOBW) downto DOBW); + end if; +-- elsif ((RSTB_dly = '0') and (REGCEB_dly = '1')) then + elsif ((ssrb_reg_var = '0') and (REGCEB_dly = '1')) then + if(rising_edge(CLKB_dly)) then + DOB_regist <= DOB_viol; + DOPB_regist <= DOPB_viol; + end if; + end if; + + when '0' => + if(rising_edge(CLKB_dly)) then +-- if(RSTB_dly = '1') then + if(ssrb_reg_var = '1') then + DOB_regist(DOBW_1 downto 0) <= SRVA_B_sig(DOBW_1 downto 0); + if(DOPBW_1 /= -1) then + DOPB_regist(DOPBW_1 downto 0) <= SRVA_B_sig((DOPBW_1 + DOBW) downto DOBW); + end if; +-- elsif ((RSTB_dly = '0') and (REGCEB_dly = '1')) then + elsif ((ssrb_reg_var = '0') and (REGCEB_dly = '1')) then + DOB_regist <= DOB_viol; + DOPB_regist <= DOPB_viol; + end if; + end if; + when others => null; + end case; + + end if; + end if; + end process prcs_regB; + +---------------------------------------------------------------------------- + prcs_PipeLineB:process (INIT_DONE, DOB_viol, DOPB_viol, DOB_regist, DOPB_regist) + variable FIRST_TIME : boolean := true; + begin + if(FIRST_TIME) then + if(INIT_DONE) then + DOB_mux(DOBW_1 downto 0) <= INI_B_sig(DOBW_1 downto 0); + if(DOPBW_1 /= -1) then + DOPB_mux(DOPBW_1 downto 0) <= INI_B_sig((DOPBW_1 + DOBW) downto DOBW); + end if; + FIRST_TIME := false; + end if; + else + case DOB_REG is + when 0 => + DOB_mux <= DOB_viol; + DOPB_mux <= DOPB_viol; + + when 1 => + DOB_mux <= DOB_regist; + DOPB_mux <= DOPB_regist; + when others => + assert false + report "Attribute Syntax Error : The allowed values for DOB_REG are 0 or 1" + severity Failure; + end case; + end if; + end process prcs_PipeLineB; + +----- ############################################################################### + + prcs_output:process (DOA_mux, DOPA_mux, DOB_mux, DOPB_mux) + begin + DOA <= DOA_mux after SYNC_PATH_DELAY; + DOPA <= DOPA_mux after SYNC_PATH_DELAY; + DOB <= DOB_mux after SYNC_PATH_DELAY; + DOPB <= DOPB_mux after SYNC_PATH_DELAY; + end process prcs_output; + +end RAMB16BWER_V; + diff --git a/Common/sim/xilinx/libsrc/unisims/unisim_VPKG.vhd b/Common/sim/xilinx/libsrc/unisims/unisim_VPKG.vhd new file mode 100644 index 0000000..70032ac --- /dev/null +++ b/Common/sim/xilinx/libsrc/unisims/unisim_VPKG.vhd @@ -0,0 +1,1463 @@ +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisim_VPKG.vhd,v 1.16 2006/02/09 00:05:51 fphillip Exp $ +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler v3.4b +-- FILENAME : unisim_VPKG.vhd +-- FILE CONTENTS: VITAL Table, hex-to-std_logic_vector conversion function, +-- and adderess decoder function Package +-- DATE CREATED : Thu Sep 12 14:45:01 1996 +-- +-- LIBRARY : UNISIM (UNIfied SIMulation) +-- DATE ENTERED : Fri Jun 21 11:34:03 1996 +-- REVISION : 1.0.2 +-- TECHNOLOGY : FPGA +-- TIME SCALE : 1 NS +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : +-- HISTORY : 1. First created by runnning Synopsys LC V3.4b. DP, 09/12/96. +-- 2. Changed package name from VTABLES to VPKG. DP, 09/13/96. +-- 3. Added RAM_O_tab and RAMS_O_tab state tables. DP, 09/13/96. +-- 4. Added HEX_TO_SLV16, HEX_TO_SLV32, DECODE_ADDR4, and +-- DECODE_ADDR5 function, and XilinxIDENT procedure declarations. +-- DP, 09/13/96. +-- 5. Added package body with above functions and procedure. +-- DP, 09/13/96. +-- 6. Changed file name from XUP_VPKG.vhd to unisim_VPKG.vhd. +-- DP, 09/25/97. +-- 7. Added FD_Q_tab and FDE_Q_tab. DP, 09/25/97. +-- 8. Removed XilinxIDENT. DP, 09/26/97. +-- 9. Added VITAL state tables for Virtex flip flops and +-- latches. DP, 10/28/97. +-- 10. Added ADDR_IS_VALID and SLV_TO_STR functions and SET_MEM_TO_X, +-- ADDR_OVERLAP and COLLISION procedures for Virtex block +-- RAMs. DP, 10/28/97. +-- 11. Fixed bug in ADDR_OVERLAP procedure. DP, 04/04/98. +-- 12. Added SLV_TO_INT function. SG, 09/15/98 +-- 13. Added "IN" in SLV_TO_INT function decl.SG, 12/09/98. +-- 14. Fixed a bug in SLV_TO_STR function. SG, 01/06/99. +-- 15. Added type_std_logic_vector1,2,3,4 -- CR 225004 -- FP, 02/08/06 +---------------------------------------------------------------- +LIBRARY STD; +USE STD.TEXTIO.ALL; + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +-- synopsys translate_off + +library IEEE; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +-- synopsys translate_on + +package VPKG is + type OtherGenericsType is record + BooleanVal : BOOLEAN; + IntegerVal : INTEGER; + end record; + type memory_collision_type is (Read_A_Write_B, + Read_B_Write_A, + Write_A_Write_B); + + type std_logic_vector1 is array (natural range <>) of std_logic; + type std_logic_vector2 is array (natural range <>, natural range <>) of std_logic; + type std_logic_vector3 is array (natural range <>, natural range <>, natural range <>) of std_logic; + type std_logic_vector4 is array (natural range <>, natural range <>, natural range <>, natural range <>) of std_logic; + + + CONSTANT L : VitalTableSymbolType := '0'; + CONSTANT H : VitalTableSymbolType := '1'; + CONSTANT x : VitalTableSymbolType := '-'; + CONSTANT S : VitalTableSymbolType := 'S'; + CONSTANT R : VitalTableSymbolType := '/'; + CONSTANT U : VitalTableSymbolType := 'X'; + CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) + + CONSTANT FD_Q_tab : VitalStateTableType := ( + ( L, L, H, x, L ), + ( L, H, H, x, H ), + ( H, x, x, x, S ), + ( x, x, L, x, S )); + + CONSTANT FDC_Q_tab : VitalStateTableType := ( + ( L, L, H, x, x, L ), + ( L, H, H, L, x, H ), + ( H, x, x, L, x, S ), + ( x, x, L, L, x, S ), + ( x, x, x, H, x, L )); + + CONSTANT FDCE_Q_tab : VitalStateTableType := ( + ( L, L, L, x, H, x, x, L ), + ( L, L, x, L, H, x, x, L ), + ( L, H, H, x, H, L, x, H ), + ( L, H, x, L, H, L, x, H ), + ( L, x, L, H, H, x, x, L ), + ( L, x, H, H, H, L, x, H ), + ( H, x, x, x, x, L, x, S ), + ( x, x, x, x, L, L, x, S ), + ( x, x, x, x, x, H, x, L )); + + CONSTANT FDCP_Q_tab : VitalStateTableType := ( + ( L, L, L, H, x, x, L ), + ( L, H, x, H, L, x, H ), + ( H, x, L, x, L, x, S ), + ( x, x, L, L, L, x, S ), + ( x, x, H, x, L, x, H ), + ( x, x, x, x, H, x, L )); + + CONSTANT FDCPE_Q_tab : VitalStateTableType := ( + ( L, L, L, L, x, H, x, x, L ), + ( L, L, L, x, L, H, x, x, L ), + ( L, L, x, L, H, H, x, x, L ), + ( L, x, H, H, x, H, L, x, H ), + ( L, x, H, x, L, H, L, x, H ), + ( L, x, x, H, H, H, L, x, H ), + ( H, L, x, x, x, x, L, x, S ), + ( x, L, x, x, x, L, L, x, S ), + ( x, H, x, x, x, x, L, x, H ), + ( x, x, x, x, x, x, H, x, L )); + + CONSTANT FDE_Q_tab : VitalStateTableType := ( + ( L, L, L, x, H, x, L ), + ( L, L, x, L, H, x, L ), + ( L, H, H, x, H, x, H ), + ( L, H, x, L, H, x, H ), + ( L, x, L, H, H, x, L ), + ( L, x, H, H, H, x, H ), + ( H, x, x, x, x, x, S ), + ( x, x, x, x, L, x, S )); + + CONSTANT FDP_Q_tab : VitalStateTableType := ( + ( L, L, L, H, x, L ), + ( L, H, x, H, x, H ), + ( H, x, L, x, x, S ), + ( x, x, L, L, x, S ), + ( x, x, H, x, x, H )); + + CONSTANT FDPE_Q_tab : VitalStateTableType := ( + ( L, L, L, L, x, H, x, L ), + ( L, L, L, x, L, H, x, L ), + ( L, L, x, L, H, H, x, L ), + ( L, x, H, H, x, H, x, H ), + ( L, x, H, x, L, H, x, H ), + ( L, x, x, H, H, H, x, H ), + ( H, L, x, x, x, x, x, S ), + ( x, L, x, x, x, L, x, S ), + ( x, H, x, x, x, x, x, H )); + + CONSTANT FDR_Q_tab : VitalStateTableType := ( + ( L, L, x, H, x, L ), + ( L, H, L, H, x, H ), + ( L, x, H, H, x, L ), + ( H, x, x, x, x, S ), + ( x, x, x, L, x, S )); + + CONSTANT FDRE_Q_tab : VitalStateTableType := ( + ( L, L, L, x, x, H, x, L ), + ( L, L, x, L, x, H, x, L ), + ( L, H, H, x, L, H, x, H ), + ( L, H, x, L, L, H, x, H ), + ( L, x, L, H, x, H, x, L ), + ( L, x, H, H, L, H, x, H ), + ( L, x, x, x, H, H, x, L ), + ( H, x, x, x, x, x, x, S ), + ( x, x, x, x, x, L, x, S )); + + CONSTANT FDRS_Q_tab : VitalStateTableType := ( + ( L, L, L, x, H, x, L ), + ( L, H, x, L, H, x, H ), + ( L, x, H, L, H, x, H ), + ( L, x, x, H, H, x, L ), + ( H, x, x, x, x, x, S ), + ( x, x, x, x, L, x, S )); + + CONSTANT FDRSE_Q_tab : VitalStateTableType := ( + ( L, L, L, L, x, x, H, x, L ), + ( L, L, L, x, L, x, H, x, L ), + ( L, L, x, L, H, x, H, x, L ), + ( L, H, x, x, x, L, H, x, H ), + ( L, x, H, H, x, L, H, x, H ), + ( L, x, H, x, L, L, H, x, H ), + ( L, x, x, H, H, L, H, x, H ), + ( L, x, x, x, x, H, H, x, L ), + ( H, x, x, x, x, x, x, x, S ), + ( x, x, x, x, x, x, L, x, S )); + + CONSTANT FDS_Q_tab : VitalStateTableType := ( + ( L, L, L, H, x, L ), + ( L, H, x, H, x, H ), + ( L, x, H, H, x, H ), + ( H, x, x, x, x, S ), + ( x, x, x, L, x, S )); + + CONSTANT FDSE_Q_tab : VitalStateTableType := ( + ( L, L, L, L, x, H, x, L ), + ( L, L, L, x, L, H, x, L ), + ( L, L, x, L, H, H, x, L ), + ( L, H, x, x, x, H, x, H ), + ( L, x, H, H, x, H, x, H ), + ( L, x, H, x, L, H, x, H ), + ( L, x, x, H, H, H, x, H ), + ( H, x, x, x, x, x, x, S ), + ( x, x, x, x, x, L, x, S )); + + CONSTANT FDPC_Q_tab : VitalStateTableType := ( + ( L, L, L, H, x, x, L ), + ( L, H, x, x, L, x, S ), + ( L, x, x, L, L, x, S ), + ( L, x, x, x, H, x, L ), + ( H, x, x, x, x, x, H ), + ( x, L, H, H, L, x, H )); + + CONSTANT FTC_Q_tab : VitalStateTableType := ( + ( L, L, L, H, x, x, L ), + ( L, L, H, H, L, x, H ), + ( L, H, L, H, L, x, H ), + ( L, H, H, H, x, x, L ), + ( H, x, x, x, L, x, S ), + ( x, x, x, L, L, x, S ), + ( x, x, x, x, H, x, L )); + + CONSTANT FTP_Q_tab : VitalStateTableType := ( + ( L, L, L, L, H, x, L ), + ( L, L, H, H, H, x, L ), + ( L, x, L, H, H, x, H ), + ( L, x, H, L, H, x, H ), + ( H, L, x, x, x, x, S ), + ( x, L, x, x, L, x, S ), + ( x, H, x, x, x, x, H )); + + CONSTANT FTCP_Q_tab : VitalStateTableType := ( + ( L, L, L, L, H, x, x, L ), + ( L, L, H, H, H, x, x, L ), + ( L, x, L, H, H, L, x, H ), + ( L, x, H, L, H, L, x, H ), + ( H, L, x, x, x, L, x, S ), + ( x, L, x, x, L, L, x, S ), + ( x, H, x, x, x, L, x, H ), + ( x, x, x, x, x, H, x, L )); + + CONSTANT IFD_Q_tab : VitalStateTableType := ( + ( L, L, H, x, L ), + ( L, H, H, x, H ), + ( H, x, x, x, S ), + ( x, x, L, x, S )); + + CONSTANT IFDX_Q_tab : VitalStateTableType := ( + ( L, L, L, x, H, x, L ), + ( L, L, x, L, H, x, L ), + ( L, H, H, x, H, x, H ), + ( L, H, x, L, H, x, H ), + ( L, x, L, H, H, x, L ), + ( L, x, H, H, H, x, H ), + ( H, x, x, x, x, x, S ), + ( x, x, x, x, L, x, S )); + + CONSTANT ILD_Q_tab : VitalStateTableType := ( + ( L, H, x, L ), + ( H, H, x, H ), + ( x, L, x, S )); + + CONSTANT ILDI_1_Q_tab : VitalStateTableType := ( + ( L, L, x, L ), + ( L, H, x, H ), + ( H, x, x, S )); + + CONSTANT ILFFX_Q_tab : VitalStateTableType := ( + ( L, L, L, x, H, H, x, L ), + ( L, L, x, H, H, H, x, L ), + ( L, H, H, x, H, H, x, H ), + ( L, H, x, H, H, H, x, H ), + ( L, x, L, L, H, H, x, L ), + ( L, x, H, L, H, H, x, H ), + ( H, x, x, x, x, x, x, S ), + ( x, x, x, x, L, x, x, S ), + ( x, x, x, x, x, L, x, S )); + + CONSTANT ILFLX_Q_tab : VitalStateTableType := ( + ( L, L, x, H, H, x, L ), + ( L, x, H, H, H, x, L ), + ( H, H, x, H, H, x, H ), + ( H, x, H, H, H, x, H ), + ( x, L, L, H, H, x, L ), + ( x, H, L, H, H, x, H ), + ( x, x, x, L, x, x, S ), + ( x, x, x, x, L, x, S )); + + CONSTANT ILFLXI_1_Q_tab : VitalStateTableType := ( + ( L, L, L, x, H, x, L ), + ( L, L, x, H, H, x, L ), + ( L, H, H, x, H, x, H ), + ( L, H, x, H, H, x, H ), + ( L, x, L, L, H, x, L ), + ( L, x, H, L, H, x, H ), + ( H, x, x, x, x, x, S ), + ( x, x, x, x, L, x, S )); + + CONSTANT ILFFXI_F_Q_tab : VitalStateTableType := ( + ( L, L, L, x, H, H, x, L ), + ( L, L, x, H, H, H, x, L ), + ( L, H, H, x, H, H, x, H ), + ( L, H, x, H, H, H, x, H ), + ( L, x, L, L, H, H, x, L ), + ( L, x, H, L, H, H, x, H ), + ( H, x, x, x, x, x, x, S ), + ( x, x, x, x, L, x, x, S ), + ( x, x, x, x, x, L, x, S )); + + CONSTANT ILFFXI_F_INT_tab : VitalStateTableType := ( + ( L, L, x, L ), + ( L, H, x, H ), + ( H, x, x, S )); + + CONSTANT ILFLXI_1F_Q_tab : VitalStateTableType := ( + ( L, L, L, x, H, x, L ), + ( L, L, x, H, H, x, L ), + ( L, H, H, x, H, x, H ), + ( L, H, x, H, H, x, H ), + ( L, x, L, L, H, x, L ), + ( L, x, H, L, H, x, H ), + ( H, x, x, x, x, x, S ), + ( x, x, x, x, L, x, S )); + + CONSTANT ILFLX_F_Q_tab : VitalStateTableType := ( + ( L, L, x, H, H, x, L ), + ( L, x, H, H, H, x, L ), + ( H, H, x, H, H, x, H ), + ( H, x, H, H, H, x, H ), + ( x, L, L, H, H, x, L ), + ( x, H, L, H, H, x, H ), + ( x, x, x, L, x, x, S ), + ( x, x, x, x, L, x, S )); + + CONSTANT LDC_Q_tab : VitalStateTableType := ( + ( L, H, x, x, L ), + ( H, H, L, x, H ), + ( x, L, L, x, S ), + ( x, x, H, x, L )); + + CONSTANT LDCE_Q_tab : VitalStateTableType := ( + ( L, H, H, x, x, L ), + ( H, H, H, L, x, H ), + ( x, L, x, L, x, S ), + ( x, x, L, L, x, S ), + ( x, x, x, H, x, L )); + + CONSTANT LDCP_Q_tab : VitalStateTableType := ( + ( L, L, H, x, x, L ), + ( H, x, H, L, x, H ), + ( x, L, L, L, x, S ), + ( x, H, x, L, x, H ), + ( x, x, x, H, x, L )); + + CONSTANT LDCPE_Q_tab : VitalStateTableType := ( + ( L, L, H, H, x, x, L ), + ( H, x, H, H, L, x, H ), + ( x, L, L, x, L, x, S ), + ( x, L, x, L, L, x, S ), + ( x, H, x, x, L, x, H ), + ( x, x, x, x, H, x, L )); + + CONSTANT LDCP_1_Q_tab : VitalStateTableType := ( + ( L, L, L, x, x, L ), + ( L, H, x, L, x, H ), + ( H, x, L, L, x, S ), + ( x, x, H, L, x, H ), + ( x, x, x, H, x, L )); + + CONSTANT LDC_1_Q_tab : VitalStateTableType := ( + ( L, L, x, x, L ), + ( L, H, L, x, H ), + ( H, x, L, x, S ), + ( x, x, H, x, L )); + + CONSTANT LDE_Q_tab : VitalStateTableType := ( + ( L, H, H, x, L ), + ( H, H, H, x, H ), + ( x, L, x, x, S ), + ( x, x, L, x, S )); + + CONSTANT LDP_Q_tab : VitalStateTableType := ( + ( L, L, H, x, L ), + ( H, x, H, x, H ), + ( x, L, L, x, S ), + ( x, H, x, x, H )); + + CONSTANT LDPE_Q_tab : VitalStateTableType := ( + ( L, L, H, H, x, L ), + ( H, x, H, H, x, H ), + ( x, L, L, x, x, S ), + ( x, L, x, L, x, S ), + ( x, H, x, x, x, H )); + + CONSTANT LDP_1_Q_tab : VitalStateTableType := ( + ( L, L, L, x, L ), + ( L, H, x, x, H ), + ( H, x, L, x, S ), + ( x, x, H, x, H )); + + CONSTANT RAM_O_tab : VitalStateTableType := ( + ( L, H, x, L ), + ( H, H, x, H ), + ( x, L, x, S )); + + CONSTANT RAMS_O_tab : VitalStateTableType := ( + ( L, L, L, x, H, x, L ), + ( L, L, x, L, H, x, L ), + ( L, H, H, x, H, x, H ), + ( L, H, x, L, H, x, H ), + ( L, x, L, H, H, x, L ), + ( L, x, H, H, H, x, H ), + ( H, x, x, x, x, x, S ), + ( x, x, x, x, L, x, S )); + + CONSTANT RAMS_O_tab_1 : VitalStateTableType := ( + ( H, L, L, x, L, x, L ), + ( H, L, x, L, L, x, L ), + ( H, H, H, x, L, x, H ), + ( H, H, x, L, L, x, H ), + ( H, x, L, H, L, x, L ), + ( H, x, H, H, L, x, H ), + ( L, x, x, x, x, x, S ), + ( x, x, x, x, H, x, S )); + + + +------------------------------------------------------------------------------- +-- COOLRUNNER STUFF +------------------------------------------------------------------------------- + + CONSTANT FDD_Q_tab : VitalStateTableType := ( + ( L, L, H, x, L ), + ( L, H, H, x, H ), + ( H, L, L, x, L ), + ( H, H, L, x, H ), + ( H, x, x, x, S ), + ( x, x, L, x, S )); + + CONSTANT FDDC_Q_tab : VitalStateTableType := ( + ( L, L, H, x, x, L ), + ( L, H, H, L, x, H ), + ( H, L, L, x, x, L ), + ( H, H, L, L, x, H ), + ( H, x, x, L, x, S ), + ( x, x, L, L, x, S ), + ( x, x, x, H, x, L )); + + CONSTANT FDDCE_Q_tab : VitalStateTableType := ( +-- C_del Q_ D CE C_ipd CLR state Q + ( L, L, L, x, H, x, x, L ), + ( L, L, x, L, H, x, x, L ), + ( L, H, H, x, H, L, x, H ), + ( L, H, x, L, H, L, x, H ), + ( L, x, L, H, H, x, x, L ), + ( L, x, H, H, H, L, x, H ), +-- Duplicate of 2 lines above for falling edge + ( H, x, L, H, L, x, x, L ), + ( H, x, H, H, L, L, x, H ), + ( H, x, x, x, x, L, x, S ), + ( x, x, x, x, L, L, x, S ), + ( x, x, x, x, x, H, x, L )); + + CONSTANT FDDCP_Q_tab : VitalStateTableType := ( +-- C_d D PRE C_i CLR S Q + ( L, L, L, H, x, x, L ), + ( L, H, x, H, L, x, H ), +-- 2 lines below are duplicates from 2 above for falling edge + ( H, L, L, L, x, x, L ), + ( H, H, x, L, L, x, H ), + ( H, x, L, x, L, x, S ), + ( x, x, L, L, L, x, S ), + ( x, x, H, x, L, x, H ), + ( x, x, x, x, H, x, L )); + + CONSTANT FDDCPE_Q_tab : VitalStateTableType := ( +-- C_d PRE Qz D CE C_i CLR S Q + ( L, L, L, L, x, H, x, x, L ), + ( L, L, L, x, L, H, x, x, L ), + ( L, L, x, L, H, H, x, x, L ), + -- Line below is dup of line above for falling edge + ( H, L, x, L, H, L, x, x, L ), + ( L, x, H, H, x, H, L, x, H ), + ( L, x, H, x, L, H, L, x, H ), + ( L, x, x, H, H, H, L, x, H ), + -- Line below is dup of line above for falling edge + ( H, x, x, H, H, L, L, x, H ), + ( H, L, x, x, x, x, L, x, S ), + ( x, L, x, x, x, L, L, x, S ), + ( x, H, x, x, x, x, L, x, H ), + ( x, x, x, x, x, x, H, x, L )); + + + CONSTANT FDDP_Q_tab : VitalStateTableType := ( +-- C_d D PRE C_i State Q + ( L, L, L, H, x, L ), + ( L, H, x, H, x, H ), +-- Duplicate 2 lines above for falling edge + ( H, L, L, L, x, L ), + ( H, H, x, L, x, H ), + ( H, x, L, x, x, S ), + ( x, x, L, L, x, S ), + ( x, x, H, x, x, H )); + + CONSTANT FDDPE_Q_tab : VitalStateTableType := ( +-- C_d PRE Qz D CE C_i S Q + ( L, L, L, L, x, H, x, L ), + ( L, L, L, x, L, H, x, L ), + ( L, L, x, L, H, H, x, L ), +-- Line below is duplicate from above for falling edge + ( H, L, x, L, H, L, x, L ), + ( L, x, H, H, x, H, x, H ), + ( L, x, H, x, L, H, x, H ), + ( L, x, x, H, H, H, x, H ), +-- Line below is duplicate from above for falling edge + ( H, x, x, H, H, L, x, H ), + ( H, L, x, x, x, x, x, S ), + ( x, L, x, x, x, L, x, S ), + ( x, H, x, x, x, x, x, H )); + + + --------------------------------------------------------------------------- + -- Function HEX_TO_SLV16 converts a hexadecimal string to std_logic_vector + -- of size 15 downto 0. + --------------------------------------------------------------------------- + function HEX_TO_SLV16 ( + INIT : in string(4 downto 1) + ) return std_logic_vector; + + --------------------------------------------------------------------------- + -- Function HEX_TO_SLV32 converts a hexadecimal string to std_logic_vector + -- of size 31 downto 0. + --------------------------------------------------------------------------- + function HEX_TO_SLV32 ( + INIT : in string(8 downto 1) + ) return std_logic_vector; + + --------------------------------------------------------------------------- + -- Function DECODE_ADDR4 decodes a 4 bit address into an integer ranging + -- from 0 to 16. + --------------------------------------------------------------------------- + function DECODE_ADDR4 ( + ADDRESS : in std_logic_vector(3 downto 0) + ) return integer; + + --------------------------------------------------------------------------- + -- Function DECODE_ADDR5 decodes a 5 bit address into an integer ranging + -- from 0 to 32. + --------------------------------------------------------------------------- + function DECODE_ADDR5 ( + ADDRESS : in std_logic_vector(4 downto 0) + ) return integer; + + --------------------------------------------------------------------------- + -- Function SLV_TO_INT converts standard logic vector into an integer + --------------------------------------------------------------------------- + function SLV_TO_INT ( + SLV : in std_logic_vector + ) return integer; + + --------------------------------------------------------------------------- + -- Function ADDR_IS_VALID checks for the validity of the argument. A FALSE + -- is returned if any argument bit is other than a '0' or '1'. + --------------------------------------------------------------------------- + function ADDR_IS_VALID ( + SLV : in std_logic_vector + ) return boolean; + + --------------------------------------------------------------------------- + -- Function SLV_TO_STR returns a string version of the std_logic_vector + -- argument. + --------------------------------------------------------------------------- + function SLV_TO_STR ( + SLV : in std_logic_vector + ) return string; + + --------------------------------------------------------------------------- + -- Function SLV_TO_HEX returns a string version of the std_logic_vector + -- argument. + --------------------------------------------------------------------------- + function SLV_TO_HEX ( + SLV : in std_logic_vector; + string_length : in integer + ) return string; + + --------------------------------------------------------------------------- + -- Procedure SET_MEM_TO_X issues an "invalid address" warning and sets the + -- contents of the argument MEM to 'X'. + --------------------------------------------------------------------------- + procedure SET_MEM_TO_X ( + ADDRESS : in std_logic_vector; + MEM : inout std_logic_vector + ); + + --------------------------------------------------------------------------- + -- Procedure ADDR_OVERLAP determines if there is overlap between the data + -- addressed by ports A and B of a dual port RAM. If there is overlap, the + -- argument OVERLAP is set to TRUE, and the lower and upper indices of the + -- overlap bits in the array used to model the RAM, as well as in the RAM + -- A and B output ports are determined. + --------------------------------------------------------------------------- + procedure ADDR_OVERLAP ( + ADDRESS_A, ADDRESS_B, DAW, DBW : in integer; + OVERLAP : out boolean; + OVRLAP_LSB, OVRLAP_MSB, DOA_OV_LSB, + DOA_OV_MSB, DOB_OV_LSB, DOB_OV_MSB : out integer + ); + + --------------------------------------------------------------------------- + -- Procedure COLLISION issues either a "WRITE COLLISION detected" error or + -- a warning that an attempt was made to read some or all of the bits + -- addressed by one port of a dual port RAM while writing to some or all + -- of the bits from the other port. In case of write collision, some or all + -- of the bits addressed by the port at which the collision is detected are + -- set to 'X'. + --------------------------------------------------------------------------- + procedure COLLISION ( + ADDRESS : in std_logic_vector; + LSB, MSB : in integer; + MODE, PORT1, PORT2, InstancePath : in string; + MEM : inout std_logic_vector + ); + + PROCEDURE GenericValueCheckMessage ( + CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; + CONSTANT GenericName : IN STRING := ""; + CONSTANT EntityName : IN STRING := ""; + CONSTANT InstanceName : IN STRING := ""; + CONSTANT GenericValue : IN STRING := ""; + Constant Unit : IN STRING := ""; + Constant ExpectedValueMsg : IN STRING := ""; + Constant ExpectedGenericValue : IN STRING := ""; + CONSTANT TailMsg : IN STRING; + + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING + + ); + + PROCEDURE GenericValueCheckMessage ( + CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; + CONSTANT GenericName : IN STRING := ""; + CONSTANT EntityName : IN STRING := ""; + CONSTANT InstanceName : IN STRING := ""; + CONSTANT GenericValue : IN INTEGER; + Constant Unit : IN STRING := ""; + Constant ExpectedValueMsg : IN STRING := ""; + Constant ExpectedGenericValue : IN INTEGER; + CONSTANT TailMsg : IN STRING; + + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING + + ); + + PROCEDURE GenericValueCheckMessage ( + CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; + CONSTANT GenericName : IN STRING := ""; + CONSTANT EntityName : IN STRING := ""; + CONSTANT InstanceName : IN STRING := ""; + CONSTANT GenericValue : IN BOOLEAN; + Constant Unit : IN STRING := ""; + Constant ExpectedValueMsg : IN STRING := ""; + Constant ExpectedGenericValue : IN STRING := ""; + CONSTANT TailMsg : IN STRING; + + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING + + ); + + PROCEDURE GenericValueCheckMessage ( + CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; + CONSTANT GenericName : IN STRING := ""; + CONSTANT EntityName : IN STRING := ""; + CONSTANT InstanceName : IN STRING := ""; + CONSTANT GenericValue : IN INTEGER; + CONSTANT Unit : IN STRING := ""; + CONSTANT ExpectedValueMsg : IN STRING := ""; + CONSTANT ExpectedGenericValue : IN STRING := ""; + CONSTANT TailMsg : IN STRING; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING + ); + + PROCEDURE GenericValueCheckMessage ( + CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; + CONSTANT GenericName : IN STRING := ""; + CONSTANT EntityName : IN STRING := ""; + CONSTANT InstanceName : IN STRING := ""; + CONSTANT GenericValue : IN REAL; + CONSTANT Unit : IN STRING := ""; + CONSTANT ExpectedValueMsg : IN STRING := ""; + CONSTANT ExpectedGenericValue : IN STRING := ""; + CONSTANT TailMsg : IN STRING; + + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING + + ); + + PROCEDURE Memory_Collision_Msg ( + CONSTANT HeaderMsg : IN STRING := " Memory Collision Error on "; + CONSTANT EntityName : IN STRING := ""; + CONSTANT InstanceName : IN STRING := ""; + constant collision_type : in memory_collision_type; + constant address_a : in std_logic_vector; + constant address_b : in std_logic_vector; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := ERROR + + + ); + + + procedure detect_resolution ( + constant model_name : in string + ); + +end VPKG; + +----------------------------------------------------------------------------- + + + +package body VPKG is + + --------------------------------------------------------------------------- + -- Function SLV_TO_INT converts a std_logic_vector TO INTEGER + --------------------------------------------------------------------------- + function SLV_TO_INT(SLV: in std_logic_vector + ) return integer is + + variable int : integer; + begin + int := 0; + for i in SLV'high downto SLV'low loop + int := int * 2; + if SLV(i) = '1' then + int := int + 1; + end if; + end loop; + return int; + end; + + --------------------------------------------------------------------------- + -- Function HEX_TO_SLV16 converts a hexadecimal string to std_logic_vector + -- of size 15 downto 0. + --------------------------------------------------------------------------- + function HEX_TO_SLV16 ( + INIT : in string(4 downto 1) + ) return std_logic_vector is + + variable SLV_16 : std_logic_vector(15 downto 0); + + begin + for I in 0 to 3 loop + case INIT(I+1) is + when '0' => + SLV_16(I*4+3 downto I*4) := "0000"; + when '1' => + SLV_16(I*4+3 downto I*4) := "0001"; + when '2' => + SLV_16(I*4+3 downto I*4) := "0010"; + when '3' => + SLV_16(I*4+3 downto I*4) := "0011"; + when '4' => + SLV_16(I*4+3 downto I*4) := "0100"; + when '5' => + SLV_16(I*4+3 downto I*4) := "0101"; + when '6' => + SLV_16(I*4+3 downto I*4) := "0110"; + when '7' => + SLV_16(I*4+3 downto I*4) := "0111"; + when '8' => + SLV_16(I*4+3 downto I*4) := "1000"; + when '9' => + SLV_16(I*4+3 downto I*4) := "1001"; + when 'a' | 'A' => + SLV_16(I*4+3 downto I*4) := "1010"; + when 'b' | 'B' => + SLV_16(I*4+3 downto I*4) := "1011"; + when 'c' | 'C' => + SLV_16(I*4+3 downto I*4) := "1100"; + when 'd' | 'D' => + SLV_16(I*4+3 downto I*4) := "1101"; + when 'e' | 'E' => + SLV_16(I*4+3 downto I*4) := "1110"; + when 'f' | 'F' => + SLV_16(I*4+3 downto I*4) := "1111"; + when others => + assert false + report "WARNING: Unknown Hex digit in INIT: "&INIT(I+1) + severity warning; + SLV_16(I*4+3 downto I*4) := "XXXX"; + end case; + end loop; + return SLV_16; + end HEX_TO_SLV16; + + --------------------------------------------------------------------------- + -- Function HEX_TO_SLV32 converts a hexadecimal string to std_logic_vector + -- of size 31 downto 0. + --------------------------------------------------------------------------- + function HEX_TO_SLV32 ( + INIT : in string(8 downto 1) + ) return std_logic_vector is + + variable SLV_32 : std_logic_vector(31 downto 0); + + begin + for I in 0 to 7 loop + case INIT(I+1) is + when '0' => + SLV_32(I*4+3 downto I*4) := "0000"; + when '1' => + SLV_32(I*4+3 downto I*4) := "0001"; + when '2' => + SLV_32(I*4+3 downto I*4) := "0010"; + when '3' => + SLV_32(I*4+3 downto I*4) := "0011"; + when '4' => + SLV_32(I*4+3 downto I*4) := "0100"; + when '5' => + SLV_32(I*4+3 downto I*4) := "0101"; + when '6' => + SLV_32(I*4+3 downto I*4) := "0110"; + when '7' => + SLV_32(I*4+3 downto I*4) := "0111"; + when '8' => + SLV_32(I*4+3 downto I*4) := "1000"; + when '9' => + SLV_32(I*4+3 downto I*4) := "1001"; + when 'a' | 'A' => + SLV_32(I*4+3 downto I*4) := "1010"; + when 'b' | 'B' => + SLV_32(I*4+3 downto I*4) := "1011"; + when 'c' | 'C' => + SLV_32(I*4+3 downto I*4) := "1100"; + when 'd' | 'D' => + SLV_32(I*4+3 downto I*4) := "1101"; + when 'e' | 'E' => + SLV_32(I*4+3 downto I*4) := "1110"; + when 'f' | 'F' => + SLV_32(I*4+3 downto I*4) := "1111"; + when others => + assert false + report "WARNING: Unknown Hex digit in INIT: "&INIT(I+1) + severity warning; + SLV_32(I*4+3 downto I*4) := "XXXX"; + end case; + end loop; + return SLV_32; + end HEX_TO_SLV32; + + --------------------------------------------------------------------------- + -- Function DECODE_ADDR4 decodes a 4 bit address into an integer ranging + -- from 0 to 16. + --------------------------------------------------------------------------- + function DECODE_ADDR4 ( + ADDRESS : in std_logic_vector(3 downto 0) + ) return integer is + + variable I : integer; + + begin + case ADDRESS is + when "0000" => I := 0; + when "0001" => I := 1; + when "0010" => I := 2; + when "0011" => I := 3; + when "0100" => I := 4; + when "0101" => I := 5; + when "0110" => I := 6; + when "0111" => I := 7; + when "1000" => I := 8; + when "1001" => I := 9; + when "1010" => I := 10; + when "1011" => I := 11; + when "1100" => I := 12; + when "1101" => I := 13; + when "1110" => I := 14; + when "1111" => I := 15; + when others => I := 16; + end case; + return I; + end DECODE_ADDR4; + + --------------------------------------------------------------------------- + -- Function DECODE_ADDR5 decodes a 5 bit address into an integer ranging + -- from 0 to 32. + --------------------------------------------------------------------------- + function DECODE_ADDR5 ( + ADDRESS : in std_logic_vector(4 downto 0) + ) return integer is + + variable I : integer; + + begin + case ADDRESS is + when "00000" => I := 0; + when "00001" => I := 1; + when "00010" => I := 2; + when "00011" => I := 3; + when "00100" => I := 4; + when "00101" => I := 5; + when "00110" => I := 6; + when "00111" => I := 7; + when "01000" => I := 8; + when "01001" => I := 9; + when "01010" => I := 10; + when "01011" => I := 11; + when "01100" => I := 12; + when "01101" => I := 13; + when "01110" => I := 14; + when "01111" => I := 15; + when "10000" => I := 16; + when "10001" => I := 17; + when "10010" => I := 18; + when "10011" => I := 19; + when "10100" => I := 20; + when "10101" => I := 21; + when "10110" => I := 22; + when "10111" => I := 23; + when "11000" => I := 24; + when "11001" => I := 25; + when "11010" => I := 26; + when "11011" => I := 27; + when "11100" => I := 28; + when "11101" => I := 29; + when "11110" => I := 30; + when "11111" => I := 31; + when others => I := 32; + end case; + return I; + end DECODE_ADDR5; + + --------------------------------------------------------------------------- + -- Function ADDR_IS_VALID checks for the validity of the argument. A FALSE + -- is returned if any argument bit is other than a '0' or '1'. + --------------------------------------------------------------------------- + function ADDR_IS_VALID ( + SLV : in std_logic_vector + ) return boolean is + + variable IS_VALID : boolean := TRUE; + + begin + for I in SLV'high downto SLV'low loop + if (SLV(I) /= '0' AND SLV(I) /= '1') then + IS_VALID := FALSE; + end if; + end loop; + return IS_VALID; + end ADDR_IS_VALID; + + --------------------------------------------------------------------------- + -- Function SLV_TO_STR returns a string version of the std_logic_vector + -- argument. + --------------------------------------------------------------------------- + function SLV_TO_STR ( + SLV : in std_logic_vector + ) return string is + + variable j : integer := SLV'length; + variable STR : string (SLV'length downto 1); + + + begin + for I in SLV'high downto SLV'low loop + case SLV(I) is + when '0' => STR(J) := '0'; + when '1' => STR(J) := '1'; + when 'X' => STR(J) := 'X'; + when 'U' => STR(J) := 'U'; + when others => STR(J) := 'X'; + end case; + J := J - 1; + end loop; + return STR; + end SLV_TO_STR; + + --------------------------------------------------------------------------- + -- Function SLV_TO_HEX returns a hex string version of the std_logic_vector + -- argument. + --------------------------------------------------------------------------- + function SLV_TO_HEX ( + SLV : in std_logic_vector; + string_length : in integer + ) return string is + + variable i : integer := 1; + variable j : integer := 1; + variable STR : string(string_length downto 1); + variable nibble : std_logic_vector(3 downto 0) := "0000"; + variable full_nibble_count : integer := 0; + variable remaining_bits : integer := 0; + + + begin + full_nibble_count := SLV'length/4; + remaining_bits := SLV'length mod 4; + for i in 1 to full_nibble_count loop + nibble := SLV(((4*i) - 1) downto ((4*i) - 4)); + if (nibble = "0000") then + STR(j) := '0'; + elsif (nibble = "0001") then + STR(j) := '1'; + elsif (nibble = "0010") then + STR(j) := '2'; + elsif (nibble = "0011") then + STR(j) := '3'; + elsif (nibble = "0100") then + STR(j) := '4'; + elsif (nibble = "0101") then + STR(j) := '5'; + elsif (nibble = "0110") then + STR(j) := '6'; + elsif (nibble = "0111") then + STR(j) := '7'; + elsif (nibble = "1000") then + STR(j) := '8'; + elsif (nibble = "1001") then + STR(j) := '9'; + elsif (nibble = "1010") then + STR(j) := 'a'; + elsif (nibble = "1011") then + STR(j) := 'b'; + elsif (nibble = "1100") then + STR(j) := 'c'; + elsif (nibble = "1101") then + STR(j) := 'd'; + elsif (nibble = "1110") then + STR(j) := 'e'; + elsif (nibble = "1111") then + STR(j) := 'f'; + end if; + j := j + 1; + end loop; + + if (remaining_bits /= 0) then + nibble := "0000"; + nibble((remaining_bits -1) downto 0) := SLV((SLV'length -1) downto (SLV'length - remaining_bits)); + if (nibble = "0000") then + STR(j) := '0'; + elsif (nibble = "0001") then + STR(j) := '1'; + elsif (nibble = "0010") then + STR(j) := '2'; + elsif (nibble = "0011") then + STR(j) := '3'; + elsif (nibble = "0100") then + STR(j) := '4'; + elsif (nibble = "0101") then + STR(j) := '5'; + elsif (nibble = "0110") then + STR(j) := '6'; + elsif (nibble = "0111") then + STR(j) := '7'; + elsif (nibble = "1000") then + STR(j) := '8'; + elsif (nibble = "1001") then + STR(j) := '9'; + elsif (nibble = "1010") then + STR(j) := 'a'; + elsif (nibble = "1011") then + STR(j) := 'b'; + elsif (nibble = "1100") then + STR(j) := 'c'; + elsif (nibble = "1101") then + STR(j) := 'd'; + elsif (nibble = "1110") then + STR(j) := 'e'; + elsif (nibble = "1111") then + STR(j) := 'f'; + end if; + end if; + return STR; + end SLV_TO_HEX; + + + --------------------------------------------------------------------------- + -- Procedure SET_MEM_TO_X issues an "invalid address" warning and sets the + -- contents of the argument MEM to 'X'. + --------------------------------------------------------------------------- + procedure SET_MEM_TO_X (ADDRESS : in std_logic_vector; + MEM : inout std_logic_vector + ) is + + begin + assert false report + "Invalid ADDRESS: "& SLV_TO_STR(ADDRESS) & ". Memory contents will be set to 'X'." + severity warning; + for I in MEM'high downto MEM'low loop + MEM(I) := 'X'; + end loop; + end SET_MEM_TO_X; + + + --------------------------------------------------------------------------- + -- Procedure ADDR_OVERLAP determines if there is overlap between the data + -- addressed by ports A and B of a dual port RAM. If there is overlap, the + -- argument OVERLAP is set to TRUE, and the lower and upper indices of the + -- overlap bits in the array used to model the RAM, as well as in the RAM + -- A and B output ports are determined. + --------------------------------------------------------------------------- + procedure ADDR_OVERLAP ( + ADDRESS_A, ADDRESS_B, DAW, DBW : in integer; + OVERLAP : out boolean; + OVRLAP_LSB, OVRLAP_MSB, DOA_OV_LSB, + DOA_OV_MSB, DOB_OV_LSB, DOB_OV_MSB : out integer + ) is + + variable A_LSB, A_MSB, B_LSB, B_MSB : integer; + + begin + A_LSB := ADDRESS_A * DAW; + A_MSB := A_LSB + DAW - 1; + B_LSB := ADDRESS_B * DBW; + B_MSB := B_LSB + DBW - 1; + + if (A_MSB < B_LSB OR B_MSB < A_LSB) then + OVERLAP := FALSE; + else + OVERLAP := TRUE; + if (A_LSB >= B_LSB) then + OVRLAP_LSB := A_LSB; + DOA_OV_LSB := 0; + DOB_OV_LSB := A_LSB - B_LSB; + else + OVRLAP_LSB := B_LSB; + DOA_OV_LSB := B_LSB - A_LSB; + DOB_OV_LSB := 0; + end if; + if (A_MSB >= B_MSB) then + OVRLAP_MSB := B_MSB; + DOA_OV_MSB := DAW - (A_MSB - B_MSB) - 1; + DOB_OV_MSB := DBW - 1; + else + OVRLAP_MSB := A_MSB; + DOA_OV_MSB := DAW - 1; + DOB_OV_MSB := DBW - (B_MSB - A_MSB) - 1; + end if; + end if; + end ADDR_OVERLAP; + + --------------------------------------------------------------------------- + -- Procedure COLLISION issues either a "WRITE COLLISION detected" error or + -- a warning that an attempt was made to read some or all of the bits + -- addressed by one port of a dual port RAM while writing to some or all + -- of the bits from the other port. In case of write collision, some or all + -- of the bits addressed by the port at which the collision is detected are + -- set to 'X'. + --------------------------------------------------------------------------- + procedure COLLISION ( + ADDRESS : in std_logic_vector; + LSB, MSB : in integer; + MODE, PORT1, PORT2, InstancePath : in string; + MEM : inout std_logic_vector + ) is + + begin + if (MODE = "write") then + assert false report + "WRITE COLLISION detected at " & PORT1 & " in instance " & InstancePath & + ". Contents of address "& SLV_TO_STR(ADDRESS) & + " will be wholly or partially set to 'X'." + severity WARNING; + for I in MSB downto LSB loop + MEM(I) := 'X'; + end loop; + elsif (MODE = "read") then + assert false report + "Attempting to read some or all of contents of address "& SLV_TO_STR(ADDRESS) & + " from " & PORT2 & " while writing from " & PORT1 & + " in instance " & InstancePath + severity WARNING; + end if; + end COLLISION; + + PROCEDURE GenericValueCheckMessage ( + CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; + CONSTANT GenericName : IN STRING := ""; + CONSTANT EntityName : IN STRING := ""; + CONSTANT InstanceName : IN STRING := ""; + CONSTANT GenericValue : IN STRING := ""; + Constant Unit : IN STRING := ""; + Constant ExpectedValueMsg : IN STRING := ""; + Constant ExpectedGenericValue : IN STRING := ""; + CONSTANT TailMsg : IN STRING; + + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING + + ) IS + VARIABLE Message : LINE; + BEGIN + + Write ( Message, HeaderMsg ); + Write ( Message, STRING'(" The attribute ") ); + Write ( Message, GenericName ); + Write ( Message, STRING'(" on ") ); + Write ( Message, EntityName ); + Write ( Message, STRING'(" instance ") ); + Write ( Message, InstanceName ); + Write ( Message, STRING'(" is set to ") ); + Write ( Message, GenericValue ); + Write ( Message, Unit ); + Write ( Message, '.' & LF ); + Write ( Message, ExpectedValueMsg ); + Write ( Message, ExpectedGenericValue ); + Write ( Message, Unit ); + Write ( Message, TailMsg ); + + ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity; + + DEALLOCATE (Message); + END GenericValueCheckMessage; + + PROCEDURE GenericValueCheckMessage ( + CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; + CONSTANT GenericName : IN STRING := ""; + CONSTANT EntityName : IN STRING := ""; + CONSTANT InstanceName : IN STRING := ""; + CONSTANT GenericValue : IN INTEGER; + CONSTANT Unit : IN STRING := ""; + CONSTANT ExpectedValueMsg : IN STRING := ""; + CONSTANT ExpectedGenericValue : IN INTEGER; + CONSTANT TailMsg : IN STRING; + + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING + + ) IS + VARIABLE Message : LINE; + BEGIN + + Write ( Message, HeaderMsg ); + Write ( Message, STRING'(" The attribute ") ); + Write ( Message, GenericName ); + Write ( Message, STRING'(" on ") ); + Write ( Message, EntityName ); + Write ( Message, STRING'(" instance ") ); + Write ( Message, InstanceName ); + Write ( Message, STRING'(" is set to ") ); + Write ( Message, GenericValue ); + Write ( Message, Unit ); + Write ( Message, '.' & LF ); + Write ( Message, ExpectedValueMsg ); + Write ( Message, ExpectedGenericValue ); + Write ( Message, Unit ); + Write ( Message, TailMsg ); + + ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity; + + DEALLOCATE (Message); + END GenericValueCheckMessage; + + PROCEDURE GenericValueCheckMessage ( + CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; + CONSTANT GenericName : IN STRING := ""; + CONSTANT EntityName : IN STRING := ""; + CONSTANT InstanceName : IN STRING := ""; + CONSTANT GenericValue : IN BOOLEAN; + Constant Unit : IN STRING := ""; + CONSTANT ExpectedValueMsg : IN STRING := ""; + CONSTANT ExpectedGenericValue : IN STRING := ""; + CONSTANT TailMsg : IN STRING; + + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING + + ) IS + VARIABLE Message : LINE; + BEGIN + + Write ( Message, HeaderMsg ); + Write ( Message, STRING'(" The attribute ") ); + Write ( Message, GenericName ); + Write ( Message, STRING'(" on ") ); + Write ( Message, EntityName ); + Write ( Message, STRING'(" instance ") ); + Write ( Message, InstanceName ); + Write ( Message, STRING'(" is set to ") ); + Write ( Message, GenericValue ); + Write ( Message, Unit ); + Write ( Message, '.' & LF ); + Write ( Message, ExpectedValueMsg ); + Write ( Message, ExpectedGenericValue ); + Write ( Message, Unit ); + Write ( Message, TailMsg ); + + ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity; + + DEALLOCATE (Message); + END GenericValueCheckMessage; + + PROCEDURE GenericValueCheckMessage ( + CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; + CONSTANT GenericName : IN STRING := ""; + CONSTANT EntityName : IN STRING := ""; + CONSTANT InstanceName : IN STRING := ""; + CONSTANT GenericValue : IN INTEGER; + CONSTANT Unit : IN STRING := ""; + CONSTANT ExpectedValueMsg : IN STRING := ""; + CONSTANT ExpectedGenericValue : IN STRING := ""; + CONSTANT TailMsg : IN STRING; + + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING + + ) IS + VARIABLE Message : LINE; + BEGIN + + Write ( Message, HeaderMsg ); + Write ( Message, STRING'(" The attribute ") ); + Write ( Message, GenericName ); + Write ( Message, STRING'(" on ") ); + Write ( Message, EntityName ); + Write ( Message, STRING'(" instance ") ); + Write ( Message, InstanceName ); + Write ( Message, STRING'(" is set to ") ); + Write ( Message, GenericValue ); + Write ( Message, Unit ); + Write ( Message, '.' & LF ); + Write ( Message, ExpectedValueMsg ); + Write ( Message, ExpectedGenericValue ); + Write ( Message, Unit ); + Write ( Message, TailMsg ); + + ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity; + + DEALLOCATE (Message); + END GenericValueCheckMessage; + PROCEDURE GenericValueCheckMessage ( + CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error "; + CONSTANT GenericName : IN STRING := ""; + CONSTANT EntityName : IN STRING := ""; + CONSTANT InstanceName : IN STRING := ""; + CONSTANT GenericValue : IN REAL; + CONSTANT Unit : IN STRING := ""; + CONSTANT ExpectedValueMsg : IN STRING := ""; + CONSTANT ExpectedGenericValue : IN STRING := ""; + CONSTANT TailMsg : IN STRING; + + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING + + ) IS + VARIABLE Message : LINE; + BEGIN + + Write ( Message, HeaderMsg ); + Write ( Message, STRING'(" The attribute ") ); + Write ( Message, GenericName ); + Write ( Message, STRING'(" on ") ); + Write ( Message, EntityName ); + Write ( Message, STRING'(" instance ") ); + Write ( Message, InstanceName ); + Write ( Message, STRING'(" is set to ") ); + Write ( Message, GenericValue ); + Write ( Message, Unit ); + Write ( Message, '.' & LF ); + Write ( Message, ExpectedValueMsg ); + Write ( Message, ExpectedGenericValue ); + Write ( Message, Unit ); + Write ( Message, TailMsg ); + + ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity; + + DEALLOCATE (Message); + END GenericValueCheckMessage; + +-- + PROCEDURE Memory_Collision_Msg ( + CONSTANT HeaderMsg : IN STRING := " Memory Collision Error on "; + CONSTANT EntityName : IN STRING := ""; + CONSTANT InstanceName : IN STRING := ""; + constant collision_type : in memory_collision_type; + constant address_a : in std_logic_vector; + constant address_b : in std_logic_vector; + CONSTANT MsgSeverity : IN SEVERITY_LEVEL := ERROR + + + ) IS + variable current_time : time := NOW; + variable string_length_a : integer; + variable string_length_b : integer; + + VARIABLE Message : LINE; + BEGIN + if ((address_a'length mod 4) = 0) then + string_length_a := address_a'length/4; + elsif ((address_a'length mod 4) > 0) then + string_length_a := address_a'length/4 + 1; + end if; + if ((address_b'length mod 4) = 0) then + string_length_b := address_b'length/4; + elsif ((address_b'length mod 4) > 0) then + string_length_b := address_b'length/4 + 1; + end if; + if (collision_type = Read_A_Write_B) then + Write ( Message, HeaderMsg); + Write ( Message, EntityName); + Write ( Message, STRING'(": ")); + Write ( Message, InstanceName); + Write ( Message, STRING'(" at simulation time ")); + Write ( Message, current_time); + Write ( Message, STRING'(".")); + Write ( Message, LF ); + Write ( Message, STRING'(" A read was performed on address ")); + Write ( Message, SLV_TO_HEX(address_a, string_length_a)); + Write ( Message, STRING'(" (hex) ")); + Write ( Message, STRING'("of port A while a write was requested to the same address on Port B ")); + Write ( Message, STRING'(" The write will be successful however the read value is unknown until the next CLKA cycle ")); + + elsif (collision_type = Read_B_Write_A) then + Write ( Message, HeaderMsg); + Write ( Message, EntityName); + Write ( Message, STRING'(": ")); + Write ( Message, InstanceName); + Write ( Message, STRING'(" at simulation time ")); + Write ( Message, current_time); + Write ( Message, STRING'(".")); + Write ( Message, LF ); + Write ( Message, STRING'(" A read was performed on address ")); + Write ( Message, SLV_TO_HEX(address_b, string_length_b)); + Write ( Message, STRING'(" (hex) ")); + Write ( Message, STRING'("of port B while a write was requested to the same address on Port A ")); + Write ( Message, STRING'(" The write will be successful however the read value is unknown until the next CLKB cycle ")); + + elsif (collision_type = Write_A_Write_B) then + Write ( Message, HeaderMsg); + Write ( Message, EntityName); + Write ( Message, STRING'(": ")); + Write ( Message, InstanceName); + Write ( Message, STRING'(" at simulation time ")); + Write ( Message, current_time); + Write ( Message, STRING'(".")); + Write ( Message, LF ); + Write ( Message, STRING'(" A write was requested to the same address simultaneously at both Port A and Port B of the RAM.")); + Write ( Message, STRING'(" The contents written to the RAM at address location ")); + Write ( Message, SLV_TO_HEX(address_a, string_length_a)); + Write ( Message, STRING'(" (hex) ")); + Write ( Message, STRING'("of Port A and address location ")); + Write ( Message, SLV_TO_HEX(address_b, string_length_b)); + Write ( Message, STRING'(" (hex) ")); + Write ( Message, STRING'("of Port B are unknown. ")); + + end if; + ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity; + + DEALLOCATE (Message); + END Memory_Collision_Msg; + + procedure detect_resolution ( + constant model_name : in string + ) IS + + variable test_value : time; + variable Message : LINE; + BEGIN + test_value := 1 ps; + if (test_value = 0 ps) then + Write (Message, STRING'(" Simulator Resolution Error : ")); + Write (Message, STRING'(" Simulator resolution is set to a value greater than 1 ps. ")); + Write (Message, STRING'(" In order to simulate the ")); + Write (Message, model_name); + Write (Message, STRING'(", the simulator resolution must be set to 1ps or smaller ")); + ASSERT FALSE REPORT Message.ALL SEVERITY ERROR; + DEALLOCATE (Message); + end if; + END detect_resolution; + + +end VPKG; diff --git a/Common/sim/xilinx/libsrc/unisims/unisim_virtex5_SMODEL.vhd b/Common/sim/xilinx/libsrc/unisims/unisim_virtex5_SMODEL.vhd new file mode 100644 index 0000000..7080d6d --- /dev/null +++ b/Common/sim/xilinx/libsrc/unisims/unisim_virtex5_SMODEL.vhd @@ -0,0 +1,66348 @@ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2006 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Multi-Gigabit Transceiver +-- /___/ /\ Filename : gtp_dual.vhd +-- \ \ / \ Timestamp : Thu Dec 8 2005 +-- \___\/\___\ +-- +-- Revision: +-- 12/08/05 - Initial version. +-- 01/09/06 - Added architecture +-- 01/27/06 - Updated ONE_UI[10:0] to ONE_UI[31:0] +-- CR#22431 - Remove GSR pin +-- 02/23/06 - Updated Header +-- 03/29/06 - CR#226744 - Fixed output connectivity. +-- 03/29/06 - CR#225541 - Updated GTP_DUAL smartmodel version to 0.006 for following updates +-- - GTP_DUAL smartmodel not generating DO output on the DRP port properly +-- - Renamed some of the ports. +-- - Removed some of the attributes. +-- - Renamed some of the attributes. +-- 04/24/06 - CR#230306 - CLKIN => REFCLKOUT delay added +-- 04/27/06 - CR#230648 - REFCLKOUT removed from wait on +-- - CR#230642 - Spreadsheet updates for I.31 +-- 05/22/06 - CR#231412 - SIM_RECEIVER_DETECT_PASS0/1 attributes added +-- 05/23/06 - CR#231962 - Add buffers for connectivity +-- 10/26/06 - - replaced ZERO_DELAY with CLK_DELAY to be consistent with writers (PPC440 update) +-- - PBS_ERR_THRESHOLD_0 default value X"11111111" to X"00000001 +-- 05/23/07 - CR#439780 - Default attribute value change - PMA_CDR_SCAN0/1, PMA_RX_CFG_0/1, TX_DIFF_BOOST_0/1 +-- - PCS_COM_CFG is a user visible attribute +-- 05/23/07 - CR#440008 - Specify block timing update - RXCHBONDO0/1 synchronous to RXUSRCLK0, RXCHBONDI0/1 synchronous to RXUSRCLK1 +-- 02/21/08 - CR#467686 - Add SIM_MODE attribute with values LEGACY & FAST model +-- 06/24/08 - CR472608, CR472665 - Update SIM_MODE default to FAST +-- End Revision + +----- CELL GTP_DUAL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GTP_DUAL is +generic ( + AC_CAP_DIS_0 : boolean := TRUE; + AC_CAP_DIS_1 : boolean := TRUE; + ALIGN_COMMA_WORD_0 : integer := 1; + ALIGN_COMMA_WORD_1 : integer := 1; + CHAN_BOND_1_MAX_SKEW_0 : integer := 7; + CHAN_BOND_1_MAX_SKEW_1 : integer := 7; + CHAN_BOND_2_MAX_SKEW_0 : integer := 1; + CHAN_BOND_2_MAX_SKEW_1 : integer := 1; + CHAN_BOND_LEVEL_0 : integer := 0; + CHAN_BOND_LEVEL_1 : integer := 0; + CHAN_BOND_MODE_0 : string := "OFF"; + CHAN_BOND_MODE_1 : string := "OFF"; + CHAN_BOND_SEQ_1_1_0 : bit_vector := "0001001010"; + CHAN_BOND_SEQ_1_1_1 : bit_vector := "0001001010"; + CHAN_BOND_SEQ_1_2_0 : bit_vector := "0001001010"; + CHAN_BOND_SEQ_1_2_1 : bit_vector := "0001001010"; + CHAN_BOND_SEQ_1_3_0 : bit_vector := "0001001010"; + CHAN_BOND_SEQ_1_3_1 : bit_vector := "0001001010"; + CHAN_BOND_SEQ_1_4_0 : bit_vector := "0110111100"; + CHAN_BOND_SEQ_1_4_1 : bit_vector := "0110111100"; + CHAN_BOND_SEQ_1_ENABLE_0 : bit_vector := "1111"; + CHAN_BOND_SEQ_1_ENABLE_1 : bit_vector := "1111"; + CHAN_BOND_SEQ_2_1_0 : bit_vector := "0110111100"; + CHAN_BOND_SEQ_2_1_1 : bit_vector := "0110111100"; + CHAN_BOND_SEQ_2_2_0 : bit_vector := "0100111100"; + CHAN_BOND_SEQ_2_2_1 : bit_vector := "0100111100"; + CHAN_BOND_SEQ_2_3_0 : bit_vector := "0100111100"; + CHAN_BOND_SEQ_2_3_1 : bit_vector := "0100111100"; + CHAN_BOND_SEQ_2_4_0 : bit_vector := "0100111100"; + CHAN_BOND_SEQ_2_4_1 : bit_vector := "0100111100"; + CHAN_BOND_SEQ_2_ENABLE_0 : bit_vector := "1111"; + CHAN_BOND_SEQ_2_ENABLE_1 : bit_vector := "1111"; + CHAN_BOND_SEQ_2_USE_0 : boolean := TRUE; + CHAN_BOND_SEQ_2_USE_1 : boolean := TRUE; + CHAN_BOND_SEQ_LEN_0 : integer := 4; + CHAN_BOND_SEQ_LEN_1 : integer := 4; + CLK25_DIVIDER : integer := 4; + CLKINDC_B : boolean := TRUE; + CLK_CORRECT_USE_0 : boolean := TRUE; + CLK_CORRECT_USE_1 : boolean := TRUE; + CLK_COR_ADJ_LEN_0 : integer := 1; + CLK_COR_ADJ_LEN_1 : integer := 1; + CLK_COR_DET_LEN_0 : integer := 1; + CLK_COR_DET_LEN_1 : integer := 1; + CLK_COR_INSERT_IDLE_FLAG_0 : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG_1 : boolean := FALSE; + CLK_COR_KEEP_IDLE_0 : boolean := FALSE; + CLK_COR_KEEP_IDLE_1 : boolean := FALSE; + CLK_COR_MAX_LAT_0 : integer := 18; + CLK_COR_MAX_LAT_1 : integer := 18; + CLK_COR_MIN_LAT_0 : integer := 16; + CLK_COR_MIN_LAT_1 : integer := 16; + CLK_COR_PRECEDENCE_0 : boolean := TRUE; + CLK_COR_PRECEDENCE_1 : boolean := TRUE; + CLK_COR_REPEAT_WAIT_0 : integer := 5; + CLK_COR_REPEAT_WAIT_1 : integer := 5; + CLK_COR_SEQ_1_1_0 : bit_vector := "0100011100"; + CLK_COR_SEQ_1_1_1 : bit_vector := "0100011100"; + CLK_COR_SEQ_1_2_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_2_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_3_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_3_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_4_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_4_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_ENABLE_0 : bit_vector := "1111"; + CLK_COR_SEQ_1_ENABLE_1 : bit_vector := "1111"; + CLK_COR_SEQ_2_1_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_1_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_2_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_2_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_3_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_3_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_4_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_4_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_ENABLE_0 : bit_vector := "1111"; + CLK_COR_SEQ_2_ENABLE_1 : bit_vector := "1111"; + CLK_COR_SEQ_2_USE_0 : boolean := FALSE; + CLK_COR_SEQ_2_USE_1 : boolean := FALSE; + COMMA_10B_ENABLE_0 : bit_vector := "1111111111"; + COMMA_10B_ENABLE_1 : bit_vector := "1111111111"; + COMMA_DOUBLE_0 : boolean := FALSE; + COMMA_DOUBLE_1 : boolean := FALSE; + COM_BURST_VAL_0 : bit_vector := "1111"; + COM_BURST_VAL_1 : bit_vector := "1111"; + DEC_MCOMMA_DETECT_0 : boolean := TRUE; + DEC_MCOMMA_DETECT_1 : boolean := TRUE; + DEC_PCOMMA_DETECT_0 : boolean := TRUE; + DEC_PCOMMA_DETECT_1 : boolean := TRUE; + DEC_VALID_COMMA_ONLY_0 : boolean := TRUE; + DEC_VALID_COMMA_ONLY_1 : boolean := TRUE; + MCOMMA_10B_VALUE_0 : bit_vector := "1010000011"; + MCOMMA_10B_VALUE_1 : bit_vector := "1010000011"; + MCOMMA_DETECT_0 : boolean := TRUE; + MCOMMA_DETECT_1 : boolean := TRUE; + OOBDETECT_THRESHOLD_0 : bit_vector := "001"; + OOBDETECT_THRESHOLD_1 : bit_vector := "001"; + OOB_CLK_DIVIDER : integer := 4; + OVERSAMPLE_MODE : boolean := FALSE; + PCI_EXPRESS_MODE_0 : boolean := TRUE; + PCI_EXPRESS_MODE_1 : boolean := TRUE; + PCOMMA_10B_VALUE_0 : bit_vector := "0101111100"; + PCOMMA_10B_VALUE_1 : bit_vector := "0101111100"; + PCOMMA_DETECT_0 : boolean := TRUE; + PCOMMA_DETECT_1 : boolean := TRUE; + PCS_COM_CFG : bit_vector := X"1680a0e"; + PLL_DIVSEL_FB : integer := 5; + PLL_DIVSEL_REF : integer := 2; + PLL_RXDIVSEL_OUT_0 : integer := 1; + PLL_RXDIVSEL_OUT_1 : integer := 1; + PLL_SATA_0 : boolean := FALSE; + PLL_SATA_1 : boolean := FALSE; + PLL_TXDIVSEL_COMM_OUT : integer := 1; + PLL_TXDIVSEL_OUT_0 : integer := 1; + PLL_TXDIVSEL_OUT_1 : integer := 1; + PMA_CDR_SCAN_0 : bit_vector := X"6c07640"; + PMA_CDR_SCAN_1 : bit_vector := X"6c07640"; + PMA_RX_CFG_0 : bit_vector := X"09f0089"; + PMA_RX_CFG_1 : bit_vector := X"09f0089"; + PRBS_ERR_THRESHOLD_0 : bit_vector := X"00000001"; + PRBS_ERR_THRESHOLD_1 : bit_vector := X"00000001"; + RCV_TERM_GND_0 : boolean := TRUE; + RCV_TERM_GND_1 : boolean := TRUE; + RCV_TERM_MID_0 : boolean := FALSE; + RCV_TERM_MID_1 : boolean := FALSE; + RCV_TERM_VTTRX_0 : boolean := FALSE; + RCV_TERM_VTTRX_1 : boolean := FALSE; + RX_BUFFER_USE_0 : boolean := TRUE; + RX_BUFFER_USE_1 : boolean := TRUE; + RX_DECODE_SEQ_MATCH_0 : boolean := TRUE; + RX_DECODE_SEQ_MATCH_1 : boolean := TRUE; + RX_LOSS_OF_SYNC_FSM_0 : boolean := FALSE; + RX_LOSS_OF_SYNC_FSM_1 : boolean := FALSE; + RX_LOS_INVALID_INCR_0 : integer := 8; + RX_LOS_INVALID_INCR_1 : integer := 8; + RX_LOS_THRESHOLD_0 : integer := 128; + RX_LOS_THRESHOLD_1 : integer := 128; + RX_SLIDE_MODE_0 : string := "PCS"; + RX_SLIDE_MODE_1 : string := "PCS"; + RX_STATUS_FMT_0 : string := "PCIE"; + RX_STATUS_FMT_1 : string := "PCIE"; + RX_XCLK_SEL_0 : string := "RXREC"; + RX_XCLK_SEL_1 : string := "RXREC"; + SATA_BURST_VAL_0 : bit_vector := "100"; + SATA_BURST_VAL_1 : bit_vector := "100"; + SATA_IDLE_VAL_0 : bit_vector := "011"; + SATA_IDLE_VAL_1 : bit_vector := "011"; + SATA_MAX_BURST_0 : integer := 7; + SATA_MAX_BURST_1 : integer := 7; + SATA_MAX_INIT_0 : integer := 22; + SATA_MAX_INIT_1 : integer := 22; + SATA_MAX_WAKE_0 : integer := 7; + SATA_MAX_WAKE_1 : integer := 7; + SATA_MIN_BURST_0 : integer := 4; + SATA_MIN_BURST_1 : integer := 4; + SATA_MIN_INIT_0 : integer := 12; + SATA_MIN_INIT_1 : integer := 12; + SATA_MIN_WAKE_0 : integer := 4; + SATA_MIN_WAKE_1 : integer := 4; + SIM_GTPRESET_SPEEDUP : integer := 0; + SIM_MODE : string := "FAST"; + SIM_PLL_PERDIV2 : bit_vector := X"190"; + SIM_RECEIVER_DETECT_PASS0 : boolean := FALSE; + SIM_RECEIVER_DETECT_PASS1 : boolean := FALSE; + TERMINATION_CTRL : bit_vector := "10100"; + TERMINATION_IMP_0 : integer := 50; + TERMINATION_IMP_1 : integer := 50; + TERMINATION_OVRD : boolean := FALSE; + TRANS_TIME_FROM_P2_0 : bit_vector := X"003c"; + TRANS_TIME_FROM_P2_1 : bit_vector := X"003c"; + TRANS_TIME_NON_P2_0 : bit_vector := X"0019"; + TRANS_TIME_NON_P2_1 : bit_vector := X"0019"; + TRANS_TIME_TO_P2_0 : bit_vector := X"0064"; + TRANS_TIME_TO_P2_1 : bit_vector := X"0064"; + TXRX_INVERT_0 : bit_vector := "00000"; + TXRX_INVERT_1 : bit_vector := "00000"; + TX_BUFFER_USE_0 : boolean := TRUE; + TX_BUFFER_USE_1 : boolean := TRUE; + TX_DIFF_BOOST_0 : boolean := TRUE; + TX_DIFF_BOOST_1 : boolean := TRUE; + TX_SYNC_FILTERB : integer := 1; + TX_XCLK_SEL_0 : string := "TXUSR"; + TX_XCLK_SEL_1 : string := "TXUSR" + ); + +port ( + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + PHYSTATUS0 : out std_ulogic; + PHYSTATUS1 : out std_ulogic; + PLLLKDET : out std_ulogic; + REFCLKOUT : out std_ulogic; + RESETDONE0 : out std_ulogic; + RESETDONE1 : out std_ulogic; + RXBUFSTATUS0 : out std_logic_vector(2 downto 0); + RXBUFSTATUS1 : out std_logic_vector(2 downto 0); + RXBYTEISALIGNED0 : out std_ulogic; + RXBYTEISALIGNED1 : out std_ulogic; + RXBYTEREALIGN0 : out std_ulogic; + RXBYTEREALIGN1 : out std_ulogic; + RXCHANBONDSEQ0 : out std_ulogic; + RXCHANBONDSEQ1 : out std_ulogic; + RXCHANISALIGNED0 : out std_ulogic; + RXCHANISALIGNED1 : out std_ulogic; + RXCHANREALIGN0 : out std_ulogic; + RXCHANREALIGN1 : out std_ulogic; + RXCHARISCOMMA0 : out std_logic_vector(1 downto 0); + RXCHARISCOMMA1 : out std_logic_vector(1 downto 0); + RXCHARISK0 : out std_logic_vector(1 downto 0); + RXCHARISK1 : out std_logic_vector(1 downto 0); + RXCHBONDO0 : out std_logic_vector(2 downto 0); + RXCHBONDO1 : out std_logic_vector(2 downto 0); + RXCLKCORCNT0 : out std_logic_vector(2 downto 0); + RXCLKCORCNT1 : out std_logic_vector(2 downto 0); + RXCOMMADET0 : out std_ulogic; + RXCOMMADET1 : out std_ulogic; + RXDATA0 : out std_logic_vector(15 downto 0); + RXDATA1 : out std_logic_vector(15 downto 0); + RXDISPERR0 : out std_logic_vector(1 downto 0); + RXDISPERR1 : out std_logic_vector(1 downto 0); + RXELECIDLE0 : out std_ulogic; + RXELECIDLE1 : out std_ulogic; + RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); + RXNOTINTABLE0 : out std_logic_vector(1 downto 0); + RXNOTINTABLE1 : out std_logic_vector(1 downto 0); + RXOVERSAMPLEERR0 : out std_ulogic; + RXOVERSAMPLEERR1 : out std_ulogic; + RXPRBSERR0 : out std_ulogic; + RXPRBSERR1 : out std_ulogic; + RXRECCLK0 : out std_ulogic; + RXRECCLK1 : out std_ulogic; + RXRUNDISP0 : out std_logic_vector(1 downto 0); + RXRUNDISP1 : out std_logic_vector(1 downto 0); + RXSTATUS0 : out std_logic_vector(2 downto 0); + RXSTATUS1 : out std_logic_vector(2 downto 0); + RXVALID0 : out std_ulogic; + RXVALID1 : out std_ulogic; + TXBUFSTATUS0 : out std_logic_vector(1 downto 0); + TXBUFSTATUS1 : out std_logic_vector(1 downto 0); + TXKERR0 : out std_logic_vector(1 downto 0); + TXKERR1 : out std_logic_vector(1 downto 0); + TXN0 : out std_ulogic; + TXN1 : out std_ulogic; + TXOUTCLK0 : out std_ulogic; + TXOUTCLK1 : out std_ulogic; + TXP0 : out std_ulogic; + TXP1 : out std_ulogic; + TXRUNDISP0 : out std_logic_vector(1 downto 0); + TXRUNDISP1 : out std_logic_vector(1 downto 0); + + CLKIN : in std_ulogic; + DADDR : in std_logic_vector(6 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + GTPRESET : in std_ulogic; + GTPTEST : in std_logic_vector(3 downto 0); + INTDATAWIDTH : in std_ulogic; + LOOPBACK0 : in std_logic_vector(2 downto 0); + LOOPBACK1 : in std_logic_vector(2 downto 0); + PLLLKDETEN : in std_ulogic; + PLLPOWERDOWN : in std_ulogic; + PRBSCNTRESET0 : in std_ulogic; + PRBSCNTRESET1 : in std_ulogic; + REFCLKPWRDNB : in std_ulogic; + RXBUFRESET0 : in std_ulogic; + RXBUFRESET1 : in std_ulogic; + RXCDRRESET0 : in std_ulogic; + RXCDRRESET1 : in std_ulogic; + RXCHBONDI0 : in std_logic_vector(2 downto 0); + RXCHBONDI1 : in std_logic_vector(2 downto 0); + RXCOMMADETUSE0 : in std_ulogic; + RXCOMMADETUSE1 : in std_ulogic; + RXDATAWIDTH0 : in std_ulogic; + RXDATAWIDTH1 : in std_ulogic; + RXDEC8B10BUSE0 : in std_ulogic; + RXDEC8B10BUSE1 : in std_ulogic; + RXELECIDLERESET0 : in std_ulogic; + RXELECIDLERESET1 : in std_ulogic; + RXENCHANSYNC0 : in std_ulogic; + RXENCHANSYNC1 : in std_ulogic; + RXENELECIDLERESETB : in std_ulogic; + RXENEQB0 : in std_ulogic; + RXENEQB1 : in std_ulogic; + RXENMCOMMAALIGN0 : in std_ulogic; + RXENMCOMMAALIGN1 : in std_ulogic; + RXENPCOMMAALIGN0 : in std_ulogic; + RXENPCOMMAALIGN1 : in std_ulogic; + RXENPRBSTST0 : in std_logic_vector(1 downto 0); + RXENPRBSTST1 : in std_logic_vector(1 downto 0); + RXENSAMPLEALIGN0 : in std_ulogic; + RXENSAMPLEALIGN1 : in std_ulogic; + RXEQMIX0 : in std_logic_vector(1 downto 0); + RXEQMIX1 : in std_logic_vector(1 downto 0); + RXEQPOLE0 : in std_logic_vector(3 downto 0); + RXEQPOLE1 : in std_logic_vector(3 downto 0); + RXN0 : in std_ulogic; + RXN1 : in std_ulogic; + RXP0 : in std_ulogic; + RXP1 : in std_ulogic; + RXPMASETPHASE0 : in std_ulogic; + RXPMASETPHASE1 : in std_ulogic; + RXPOLARITY0 : in std_ulogic; + RXPOLARITY1 : in std_ulogic; + RXPOWERDOWN0 : in std_logic_vector(1 downto 0); + RXPOWERDOWN1 : in std_logic_vector(1 downto 0); + RXRESET0 : in std_ulogic; + RXRESET1 : in std_ulogic; + RXSLIDE0 : in std_ulogic; + RXSLIDE1 : in std_ulogic; + RXUSRCLK0 : in std_ulogic; + RXUSRCLK1 : in std_ulogic; + RXUSRCLK20 : in std_ulogic; + RXUSRCLK21 : in std_ulogic; + TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXBYPASS8B10B0 : in std_logic_vector(1 downto 0); + TXBYPASS8B10B1 : in std_logic_vector(1 downto 0); + TXCHARDISPMODE0 : in std_logic_vector(1 downto 0); + TXCHARDISPMODE1 : in std_logic_vector(1 downto 0); + TXCHARDISPVAL0 : in std_logic_vector(1 downto 0); + TXCHARDISPVAL1 : in std_logic_vector(1 downto 0); + TXCHARISK0 : in std_logic_vector(1 downto 0); + TXCHARISK1 : in std_logic_vector(1 downto 0); + TXCOMSTART0 : in std_ulogic; + TXCOMSTART1 : in std_ulogic; + TXCOMTYPE0 : in std_ulogic; + TXCOMTYPE1 : in std_ulogic; + TXDATA0 : in std_logic_vector(15 downto 0); + TXDATA1 : in std_logic_vector(15 downto 0); + TXDATAWIDTH0 : in std_ulogic; + TXDATAWIDTH1 : in std_ulogic; + TXDETECTRX0 : in std_ulogic; + TXDETECTRX1 : in std_ulogic; + TXDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXELECIDLE0 : in std_ulogic; + TXELECIDLE1 : in std_ulogic; + TXENC8B10BUSE0 : in std_ulogic; + TXENC8B10BUSE1 : in std_ulogic; + TXENPMAPHASEALIGN : in std_ulogic; + TXENPRBSTST0 : in std_logic_vector(1 downto 0); + TXENPRBSTST1 : in std_logic_vector(1 downto 0); + TXINHIBIT0 : in std_ulogic; + TXINHIBIT1 : in std_ulogic; + TXPMASETPHASE : in std_ulogic; + TXPOLARITY0 : in std_ulogic; + TXPOLARITY1 : in std_ulogic; + TXPOWERDOWN0 : in std_logic_vector(1 downto 0); + TXPOWERDOWN1 : in std_logic_vector(1 downto 0); + TXPREEMPHASIS0 : in std_logic_vector(2 downto 0); + TXPREEMPHASIS1 : in std_logic_vector(2 downto 0); + TXRESET0 : in std_ulogic; + TXRESET1 : in std_ulogic; + TXUSRCLK0 : in std_ulogic; + TXUSRCLK1 : in std_ulogic; + TXUSRCLK20 : in std_ulogic; + TXUSRCLK21 : in std_ulogic + ); +end GTP_DUAL; + +architecture GTP_DUAL_V of GTP_DUAL is + + component GTP_DUAL_SWIFT_BUS + port ( + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + PHYSTATUS0 : out std_ulogic; + PHYSTATUS1 : out std_ulogic; + PLLLKDET : out std_ulogic; + REFCLKOUT : out std_ulogic; + RESETDONE0 : out std_ulogic; + RESETDONE1 : out std_ulogic; + RXBUFSTATUS0 : out std_logic_vector(2 downto 0); + RXBUFSTATUS1 : out std_logic_vector(2 downto 0); + RXBYTEISALIGNED0 : out std_ulogic; + RXBYTEISALIGNED1 : out std_ulogic; + RXBYTEREALIGN0 : out std_ulogic; + RXBYTEREALIGN1 : out std_ulogic; + RXCHANBONDSEQ0 : out std_ulogic; + RXCHANBONDSEQ1 : out std_ulogic; + RXCHANISALIGNED0 : out std_ulogic; + RXCHANISALIGNED1 : out std_ulogic; + RXCHANREALIGN0 : out std_ulogic; + RXCHANREALIGN1 : out std_ulogic; + RXCHARISCOMMA0 : out std_logic_vector(1 downto 0); + RXCHARISCOMMA1 : out std_logic_vector(1 downto 0); + RXCHARISK0 : out std_logic_vector(1 downto 0); + RXCHARISK1 : out std_logic_vector(1 downto 0); + RXCHBONDO0 : out std_logic_vector(2 downto 0); + RXCHBONDO1 : out std_logic_vector(2 downto 0); + RXCLKCORCNT0 : out std_logic_vector(2 downto 0); + RXCLKCORCNT1 : out std_logic_vector(2 downto 0); + RXCOMMADET0 : out std_ulogic; + RXCOMMADET1 : out std_ulogic; + RXDATA0 : out std_logic_vector(15 downto 0); + RXDATA1 : out std_logic_vector(15 downto 0); + RXDISPERR0 : out std_logic_vector(1 downto 0); + RXDISPERR1 : out std_logic_vector(1 downto 0); + RXELECIDLE0 : out std_ulogic; + RXELECIDLE1 : out std_ulogic; + RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); + RXNOTINTABLE0 : out std_logic_vector(1 downto 0); + RXNOTINTABLE1 : out std_logic_vector(1 downto 0); + RXOVERSAMPLEERR0 : out std_ulogic; + RXOVERSAMPLEERR1 : out std_ulogic; + RXPRBSERR0 : out std_ulogic; + RXPRBSERR1 : out std_ulogic; + RXRECCLK0 : out std_ulogic; + RXRECCLK1 : out std_ulogic; + RXRUNDISP0 : out std_logic_vector(1 downto 0); + RXRUNDISP1 : out std_logic_vector(1 downto 0); + RXSTATUS0 : out std_logic_vector(2 downto 0); + RXSTATUS1 : out std_logic_vector(2 downto 0); + RXVALID0 : out std_ulogic; + RXVALID1 : out std_ulogic; + TXBUFSTATUS0 : out std_logic_vector(1 downto 0); + TXBUFSTATUS1 : out std_logic_vector(1 downto 0); + TXKERR0 : out std_logic_vector(1 downto 0); + TXKERR1 : out std_logic_vector(1 downto 0); + TXN0 : out std_ulogic; + TXN1 : out std_ulogic; + TXOUTCLK0 : out std_ulogic; + TXOUTCLK1 : out std_ulogic; + TXP0 : out std_ulogic; + TXP1 : out std_ulogic; + TXRUNDISP0 : out std_logic_vector(1 downto 0); + TXRUNDISP1 : out std_logic_vector(1 downto 0); + + CLKIN : in std_ulogic; + DADDR : in std_logic_vector(6 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + GSR : in std_ulogic; + GTPRESET : in std_ulogic; + GTPTEST : in std_logic_vector(3 downto 0); + INTDATAWIDTH : in std_ulogic; + LOOPBACK0 : in std_logic_vector(2 downto 0); + LOOPBACK1 : in std_logic_vector(2 downto 0); + PLLLKDETEN : in std_ulogic; + PLLPOWERDOWN : in std_ulogic; + PRBSCNTRESET0 : in std_ulogic; + PRBSCNTRESET1 : in std_ulogic; + REFCLKPWRDNB : in std_ulogic; + RXBUFRESET0 : in std_ulogic; + RXBUFRESET1 : in std_ulogic; + RXCDRRESET0 : in std_ulogic; + RXCDRRESET1 : in std_ulogic; + RXCHBONDI0 : in std_logic_vector(2 downto 0); + RXCHBONDI1 : in std_logic_vector(2 downto 0); + RXCOMMADETUSE0 : in std_ulogic; + RXCOMMADETUSE1 : in std_ulogic; + RXDATAWIDTH0 : in std_ulogic; + RXDATAWIDTH1 : in std_ulogic; + RXDEC8B10BUSE0 : in std_ulogic; + RXDEC8B10BUSE1 : in std_ulogic; + RXELECIDLERESET0 : in std_ulogic; + RXELECIDLERESET1 : in std_ulogic; + RXENCHANSYNC0 : in std_ulogic; + RXENCHANSYNC1 : in std_ulogic; + RXENELECIDLERESETB : in std_ulogic; + RXENEQB0 : in std_ulogic; + RXENEQB1 : in std_ulogic; + RXENMCOMMAALIGN0 : in std_ulogic; + RXENMCOMMAALIGN1 : in std_ulogic; + RXENPCOMMAALIGN0 : in std_ulogic; + RXENPCOMMAALIGN1 : in std_ulogic; + RXENPRBSTST0 : in std_logic_vector(1 downto 0); + RXENPRBSTST1 : in std_logic_vector(1 downto 0); + RXENSAMPLEALIGN0 : in std_ulogic; + RXENSAMPLEALIGN1 : in std_ulogic; + RXEQMIX0 : in std_logic_vector(1 downto 0); + RXEQMIX1 : in std_logic_vector(1 downto 0); + RXEQPOLE0 : in std_logic_vector(3 downto 0); + RXEQPOLE1 : in std_logic_vector(3 downto 0); + RXN0 : in std_ulogic; + RXN1 : in std_ulogic; + RXP0 : in std_ulogic; + RXP1 : in std_ulogic; + RXPMASETPHASE0 : in std_ulogic; + RXPMASETPHASE1 : in std_ulogic; + RXPOLARITY0 : in std_ulogic; + RXPOLARITY1 : in std_ulogic; + RXPOWERDOWN0 : in std_logic_vector(1 downto 0); + RXPOWERDOWN1 : in std_logic_vector(1 downto 0); + RXRESET0 : in std_ulogic; + RXRESET1 : in std_ulogic; + RXSLIDE0 : in std_ulogic; + RXSLIDE1 : in std_ulogic; + RXUSRCLK0 : in std_ulogic; + RXUSRCLK1 : in std_ulogic; + RXUSRCLK20 : in std_ulogic; + RXUSRCLK21 : in std_ulogic; + TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXBYPASS8B10B0 : in std_logic_vector(1 downto 0); + TXBYPASS8B10B1 : in std_logic_vector(1 downto 0); + TXCHARDISPMODE0 : in std_logic_vector(1 downto 0); + TXCHARDISPMODE1 : in std_logic_vector(1 downto 0); + TXCHARDISPVAL0 : in std_logic_vector(1 downto 0); + TXCHARDISPVAL1 : in std_logic_vector(1 downto 0); + TXCHARISK0 : in std_logic_vector(1 downto 0); + TXCHARISK1 : in std_logic_vector(1 downto 0); + TXCOMSTART0 : in std_ulogic; + TXCOMSTART1 : in std_ulogic; + TXCOMTYPE0 : in std_ulogic; + TXCOMTYPE1 : in std_ulogic; + TXDATA0 : in std_logic_vector(15 downto 0); + TXDATA1 : in std_logic_vector(15 downto 0); + TXDATAWIDTH0 : in std_ulogic; + TXDATAWIDTH1 : in std_ulogic; + TXDETECTRX0 : in std_ulogic; + TXDETECTRX1 : in std_ulogic; + TXDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXELECIDLE0 : in std_ulogic; + TXELECIDLE1 : in std_ulogic; + TXENC8B10BUSE0 : in std_ulogic; + TXENC8B10BUSE1 : in std_ulogic; + TXENPMAPHASEALIGN : in std_ulogic; + TXENPRBSTST0 : in std_logic_vector(1 downto 0); + TXENPRBSTST1 : in std_logic_vector(1 downto 0); + TXINHIBIT0 : in std_ulogic; + TXINHIBIT1 : in std_ulogic; + TXPMASETPHASE : in std_ulogic; + TXPOLARITY0 : in std_ulogic; + TXPOLARITY1 : in std_ulogic; + TXPOWERDOWN0 : in std_logic_vector(1 downto 0); + TXPOWERDOWN1 : in std_logic_vector(1 downto 0); + TXPREEMPHASIS0 : in std_logic_vector(2 downto 0); + TXPREEMPHASIS1 : in std_logic_vector(2 downto 0); + TXRESET0 : in std_ulogic; + TXRESET1 : in std_ulogic; + TXUSRCLK0 : in std_ulogic; + TXUSRCLK1 : in std_ulogic; + TXUSRCLK20 : in std_ulogic; + TXUSRCLK21 : in std_ulogic; + + AC_CAP_DIS_0 : in std_ulogic; + AC_CAP_DIS_1 : in std_ulogic; + ALIGN_COMMA_WORD_0 : in std_ulogic; + ALIGN_COMMA_WORD_1 : in std_ulogic; + CHAN_BOND_1_MAX_SKEW_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_1_MAX_SKEW_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_2_MAX_SKEW_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_2_MAX_SKEW_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_LEVEL_0 : in std_logic_vector(2 downto 0); + CHAN_BOND_LEVEL_1 : in std_logic_vector(2 downto 0); + CHAN_BOND_MODE_0 : in std_logic_vector(1 downto 0); + CHAN_BOND_MODE_1 : in std_logic_vector(1 downto 0); + CHAN_BOND_SEQ_1_1_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_1_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_2_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_2_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_3_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_3_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_4_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_4_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_1_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_1_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_2_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_2_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_3_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_3_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_4_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_4_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_USE_0 : in std_ulogic; + CHAN_BOND_SEQ_2_USE_1 : in std_ulogic; + CHAN_BOND_SEQ_LEN_0 : in std_logic_vector(1 downto 0); + CHAN_BOND_SEQ_LEN_1 : in std_logic_vector(1 downto 0); + CLK25_DIVIDER : in std_logic_vector(2 downto 0); + CLKINDC_B : in std_ulogic; + CLK_CORRECT_USE_0 : in std_ulogic; + CLK_CORRECT_USE_1 : in std_ulogic; + CLK_COR_ADJ_LEN_0 : in std_logic_vector(1 downto 0); + CLK_COR_ADJ_LEN_1 : in std_logic_vector(1 downto 0); + CLK_COR_DET_LEN_0 : in std_logic_vector(1 downto 0); + CLK_COR_DET_LEN_1 : in std_logic_vector(1 downto 0); + CLK_COR_INSERT_IDLE_FLAG_0 : in std_ulogic; + CLK_COR_INSERT_IDLE_FLAG_1 : in std_ulogic; + CLK_COR_KEEP_IDLE_0 : in std_ulogic; + CLK_COR_KEEP_IDLE_1 : in std_ulogic; + CLK_COR_MAX_LAT_0 : in std_logic_vector(5 downto 0); + CLK_COR_MAX_LAT_1 : in std_logic_vector(5 downto 0); + CLK_COR_MIN_LAT_0 : in std_logic_vector(5 downto 0); + CLK_COR_MIN_LAT_1 : in std_logic_vector(5 downto 0); + CLK_COR_PRECEDENCE_0 : in std_ulogic; + CLK_COR_PRECEDENCE_1 : in std_ulogic; + CLK_COR_REPEAT_WAIT_0 : in std_logic_vector(4 downto 0); + CLK_COR_REPEAT_WAIT_1 : in std_logic_vector(4 downto 0); + CLK_COR_SEQ_1_1_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_1_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_2_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_2_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_3_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_3_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_4_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_4_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_1_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_1_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_2_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_2_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_3_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_3_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_4_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_4_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_USE_0 : in std_ulogic; + CLK_COR_SEQ_2_USE_1 : in std_ulogic; + COMMA_10B_ENABLE_0 : in std_logic_vector(9 downto 0); + COMMA_10B_ENABLE_1 : in std_logic_vector(9 downto 0); + COMMA_DOUBLE_0 : in std_ulogic; + COMMA_DOUBLE_1 : in std_ulogic; + COM_BURST_VAL_0 : in std_logic_vector(3 downto 0); + COM_BURST_VAL_1 : in std_logic_vector(3 downto 0); + DEC_MCOMMA_DETECT_0 : in std_ulogic; + DEC_MCOMMA_DETECT_1 : in std_ulogic; + DEC_PCOMMA_DETECT_0 : in std_ulogic; + DEC_PCOMMA_DETECT_1 : in std_ulogic; + DEC_VALID_COMMA_ONLY_0 : in std_ulogic; + DEC_VALID_COMMA_ONLY_1 : in std_ulogic; + MCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); + MCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); + MCOMMA_DETECT_0 : in std_ulogic; + MCOMMA_DETECT_1 : in std_ulogic; + OOBDETECT_THRESHOLD_0 : in std_logic_vector(2 downto 0); + OOBDETECT_THRESHOLD_1 : in std_logic_vector(2 downto 0); + OOB_CLK_DIVIDER : in std_logic_vector(2 downto 0); + OVERSAMPLE_MODE : in std_ulogic; + PCI_EXPRESS_MODE_0 : in std_ulogic; + PCI_EXPRESS_MODE_1 : in std_ulogic; + PCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); + PCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); + PCOMMA_DETECT_0 : in std_ulogic; + PCOMMA_DETECT_1 : in std_ulogic; + PCS_COM_CFG : in std_logic_vector(27 downto 0); + PLL_DIVSEL_FB : in std_logic_vector(4 downto 0); + PLL_DIVSEL_REF : in std_logic_vector(5 downto 0); + PLL_RXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); + PLL_RXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); + PLL_SATA_0 : in std_ulogic; + PLL_SATA_1 : in std_ulogic; + PLL_TXDIVSEL_COMM_OUT : in std_logic_vector(1 downto 0); + PLL_TXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); + PLL_TXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); + PMA_CDR_SCAN_0 : in std_logic_vector(26 downto 0); + PMA_CDR_SCAN_1 : in std_logic_vector(26 downto 0); + PMA_RX_CFG_0 : in std_logic_vector(24 downto 0); + PMA_RX_CFG_1 : in std_logic_vector(24 downto 0); + PRBS_ERR_THRESHOLD_0 : in std_logic_vector(31 downto 0); + PRBS_ERR_THRESHOLD_1 : in std_logic_vector(31 downto 0); + RCV_TERM_GND_0 : in std_ulogic; + RCV_TERM_GND_1 : in std_ulogic; + RCV_TERM_MID_0 : in std_ulogic; + RCV_TERM_MID_1 : in std_ulogic; + RCV_TERM_VTTRX_0 : in std_ulogic; + RCV_TERM_VTTRX_1 : in std_ulogic; + RX_BUFFER_USE_0 : in std_ulogic; + RX_BUFFER_USE_1 : in std_ulogic; + RX_DECODE_SEQ_MATCH_0 : in std_ulogic; + RX_DECODE_SEQ_MATCH_1 : in std_ulogic; + RX_LOSS_OF_SYNC_FSM_0 : in std_ulogic; + RX_LOSS_OF_SYNC_FSM_1 : in std_ulogic; + RX_LOS_INVALID_INCR_0 : in std_logic_vector(2 downto 0); + RX_LOS_INVALID_INCR_1 : in std_logic_vector(2 downto 0); + RX_LOS_THRESHOLD_0 : in std_logic_vector(2 downto 0); + RX_LOS_THRESHOLD_1 : in std_logic_vector(2 downto 0); + RX_SLIDE_MODE_0 : in std_ulogic; + RX_SLIDE_MODE_1 : in std_ulogic; + RX_STATUS_FMT_0 : in std_ulogic; + RX_STATUS_FMT_1 : in std_ulogic; + RX_XCLK_SEL_0 : in std_ulogic; + RX_XCLK_SEL_1 : in std_ulogic; + SATA_BURST_VAL_0 : in std_logic_vector(2 downto 0); + SATA_BURST_VAL_1 : in std_logic_vector(2 downto 0); + SATA_IDLE_VAL_0 : in std_logic_vector(2 downto 0); + SATA_IDLE_VAL_1 : in std_logic_vector(2 downto 0); + SATA_MAX_BURST_0 : in std_logic_vector(5 downto 0); + SATA_MAX_BURST_1 : in std_logic_vector(5 downto 0); + SATA_MAX_INIT_0 : in std_logic_vector(5 downto 0); + SATA_MAX_INIT_1 : in std_logic_vector(5 downto 0); + SATA_MAX_WAKE_0 : in std_logic_vector(5 downto 0); + SATA_MAX_WAKE_1 : in std_logic_vector(5 downto 0); + SATA_MIN_BURST_0 : in std_logic_vector(5 downto 0); + SATA_MIN_BURST_1 : in std_logic_vector(5 downto 0); + SATA_MIN_INIT_0 : in std_logic_vector(5 downto 0); + SATA_MIN_INIT_1 : in std_logic_vector(5 downto 0); + SATA_MIN_WAKE_0 : in std_logic_vector(5 downto 0); + SATA_MIN_WAKE_1 : in std_logic_vector(5 downto 0); + SIM_GTPRESET_SPEEDUP : in std_ulogic; + SIM_PLL_PERDIV2 : in std_logic_vector(8 downto 0); + SIM_RECEIVER_DETECT_PASS0 : in std_ulogic; + SIM_RECEIVER_DETECT_PASS1 : in std_ulogic; + TERMINATION_CTRL : in std_logic_vector(4 downto 0); + TERMINATION_IMP_0 : in std_ulogic; + TERMINATION_IMP_1 : in std_ulogic; + TERMINATION_OVRD : in std_ulogic; + TRANS_TIME_FROM_P2_0 : in std_logic_vector(15 downto 0); + TRANS_TIME_FROM_P2_1 : in std_logic_vector(15 downto 0); + TRANS_TIME_NON_P2_0 : in std_logic_vector(15 downto 0); + TRANS_TIME_NON_P2_1 : in std_logic_vector(15 downto 0); + TRANS_TIME_TO_P2_0 : in std_logic_vector(15 downto 0); + TRANS_TIME_TO_P2_1 : in std_logic_vector(15 downto 0); + TXRX_INVERT_0 : in std_logic_vector(4 downto 0); + TXRX_INVERT_1 : in std_logic_vector(4 downto 0); + TX_BUFFER_USE_0 : in std_ulogic; + TX_BUFFER_USE_1 : in std_ulogic; + TX_DIFF_BOOST_0 : in std_ulogic; + TX_DIFF_BOOST_1 : in std_ulogic; + TX_SYNC_FILTERB : in std_ulogic; + TX_XCLK_SEL_0 : in std_ulogic; + TX_XCLK_SEL_1 : in std_ulogic + ); + end component; + + component GTP_DUAL_FAST_BUS + port ( + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + PHYSTATUS0 : out std_ulogic; + PHYSTATUS1 : out std_ulogic; + PLLLKDET : out std_ulogic; + REFCLKOUT : out std_ulogic; + RESETDONE0 : out std_ulogic; + RESETDONE1 : out std_ulogic; + RXBUFSTATUS0 : out std_logic_vector(2 downto 0); + RXBUFSTATUS1 : out std_logic_vector(2 downto 0); + RXBYTEISALIGNED0 : out std_ulogic; + RXBYTEISALIGNED1 : out std_ulogic; + RXBYTEREALIGN0 : out std_ulogic; + RXBYTEREALIGN1 : out std_ulogic; + RXCHANBONDSEQ0 : out std_ulogic; + RXCHANBONDSEQ1 : out std_ulogic; + RXCHANISALIGNED0 : out std_ulogic; + RXCHANISALIGNED1 : out std_ulogic; + RXCHANREALIGN0 : out std_ulogic; + RXCHANREALIGN1 : out std_ulogic; + RXCHARISCOMMA0 : out std_logic_vector(1 downto 0); + RXCHARISCOMMA1 : out std_logic_vector(1 downto 0); + RXCHARISK0 : out std_logic_vector(1 downto 0); + RXCHARISK1 : out std_logic_vector(1 downto 0); + RXCHBONDO0 : out std_logic_vector(2 downto 0); + RXCHBONDO1 : out std_logic_vector(2 downto 0); + RXCLKCORCNT0 : out std_logic_vector(2 downto 0); + RXCLKCORCNT1 : out std_logic_vector(2 downto 0); + RXCOMMADET0 : out std_ulogic; + RXCOMMADET1 : out std_ulogic; + RXDATA0 : out std_logic_vector(15 downto 0); + RXDATA1 : out std_logic_vector(15 downto 0); + RXDISPERR0 : out std_logic_vector(1 downto 0); + RXDISPERR1 : out std_logic_vector(1 downto 0); + RXELECIDLE0 : out std_ulogic; + RXELECIDLE1 : out std_ulogic; + RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); + RXNOTINTABLE0 : out std_logic_vector(1 downto 0); + RXNOTINTABLE1 : out std_logic_vector(1 downto 0); + RXOVERSAMPLEERR0 : out std_ulogic; + RXOVERSAMPLEERR1 : out std_ulogic; + RXPRBSERR0 : out std_ulogic; + RXPRBSERR1 : out std_ulogic; + RXRECCLK0 : out std_ulogic; + RXRECCLK1 : out std_ulogic; + RXRUNDISP0 : out std_logic_vector(1 downto 0); + RXRUNDISP1 : out std_logic_vector(1 downto 0); + RXSTATUS0 : out std_logic_vector(2 downto 0); + RXSTATUS1 : out std_logic_vector(2 downto 0); + RXVALID0 : out std_ulogic; + RXVALID1 : out std_ulogic; + TXBUFSTATUS0 : out std_logic_vector(1 downto 0); + TXBUFSTATUS1 : out std_logic_vector(1 downto 0); + TXKERR0 : out std_logic_vector(1 downto 0); + TXKERR1 : out std_logic_vector(1 downto 0); + TXN0 : out std_ulogic; + TXN1 : out std_ulogic; + TXOUTCLK0 : out std_ulogic; + TXOUTCLK1 : out std_ulogic; + TXP0 : out std_ulogic; + TXP1 : out std_ulogic; + TXRUNDISP0 : out std_logic_vector(1 downto 0); + TXRUNDISP1 : out std_logic_vector(1 downto 0); + + CLKIN : in std_ulogic; + DADDR : in std_logic_vector(6 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + GSR : in std_ulogic; + GTPRESET : in std_ulogic; + GTPTEST : in std_logic_vector(3 downto 0); + INTDATAWIDTH : in std_ulogic; + LOOPBACK0 : in std_logic_vector(2 downto 0); + LOOPBACK1 : in std_logic_vector(2 downto 0); + PLLLKDETEN : in std_ulogic; + PLLPOWERDOWN : in std_ulogic; + PRBSCNTRESET0 : in std_ulogic; + PRBSCNTRESET1 : in std_ulogic; + REFCLKPWRDNB : in std_ulogic; + RXBUFRESET0 : in std_ulogic; + RXBUFRESET1 : in std_ulogic; + RXCDRRESET0 : in std_ulogic; + RXCDRRESET1 : in std_ulogic; + RXCHBONDI0 : in std_logic_vector(2 downto 0); + RXCHBONDI1 : in std_logic_vector(2 downto 0); + RXCOMMADETUSE0 : in std_ulogic; + RXCOMMADETUSE1 : in std_ulogic; + RXDATAWIDTH0 : in std_ulogic; + RXDATAWIDTH1 : in std_ulogic; + RXDEC8B10BUSE0 : in std_ulogic; + RXDEC8B10BUSE1 : in std_ulogic; + RXELECIDLERESET0 : in std_ulogic; + RXELECIDLERESET1 : in std_ulogic; + RXENCHANSYNC0 : in std_ulogic; + RXENCHANSYNC1 : in std_ulogic; + RXENELECIDLERESETB : in std_ulogic; + RXENEQB0 : in std_ulogic; + RXENEQB1 : in std_ulogic; + RXENMCOMMAALIGN0 : in std_ulogic; + RXENMCOMMAALIGN1 : in std_ulogic; + RXENPCOMMAALIGN0 : in std_ulogic; + RXENPCOMMAALIGN1 : in std_ulogic; + RXENPRBSTST0 : in std_logic_vector(1 downto 0); + RXENPRBSTST1 : in std_logic_vector(1 downto 0); + RXENSAMPLEALIGN0 : in std_ulogic; + RXENSAMPLEALIGN1 : in std_ulogic; + RXEQMIX0 : in std_logic_vector(1 downto 0); + RXEQMIX1 : in std_logic_vector(1 downto 0); + RXEQPOLE0 : in std_logic_vector(3 downto 0); + RXEQPOLE1 : in std_logic_vector(3 downto 0); + RXN0 : in std_ulogic; + RXN1 : in std_ulogic; + RXP0 : in std_ulogic; + RXP1 : in std_ulogic; + RXPMASETPHASE0 : in std_ulogic; + RXPMASETPHASE1 : in std_ulogic; + RXPOLARITY0 : in std_ulogic; + RXPOLARITY1 : in std_ulogic; + RXPOWERDOWN0 : in std_logic_vector(1 downto 0); + RXPOWERDOWN1 : in std_logic_vector(1 downto 0); + RXRESET0 : in std_ulogic; + RXRESET1 : in std_ulogic; + RXSLIDE0 : in std_ulogic; + RXSLIDE1 : in std_ulogic; + RXUSRCLK0 : in std_ulogic; + RXUSRCLK1 : in std_ulogic; + RXUSRCLK20 : in std_ulogic; + RXUSRCLK21 : in std_ulogic; + TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXBYPASS8B10B0 : in std_logic_vector(1 downto 0); + TXBYPASS8B10B1 : in std_logic_vector(1 downto 0); + TXCHARDISPMODE0 : in std_logic_vector(1 downto 0); + TXCHARDISPMODE1 : in std_logic_vector(1 downto 0); + TXCHARDISPVAL0 : in std_logic_vector(1 downto 0); + TXCHARDISPVAL1 : in std_logic_vector(1 downto 0); + TXCHARISK0 : in std_logic_vector(1 downto 0); + TXCHARISK1 : in std_logic_vector(1 downto 0); + TXCOMSTART0 : in std_ulogic; + TXCOMSTART1 : in std_ulogic; + TXCOMTYPE0 : in std_ulogic; + TXCOMTYPE1 : in std_ulogic; + TXDATA0 : in std_logic_vector(15 downto 0); + TXDATA1 : in std_logic_vector(15 downto 0); + TXDATAWIDTH0 : in std_ulogic; + TXDATAWIDTH1 : in std_ulogic; + TXDETECTRX0 : in std_ulogic; + TXDETECTRX1 : in std_ulogic; + TXDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXELECIDLE0 : in std_ulogic; + TXELECIDLE1 : in std_ulogic; + TXENC8B10BUSE0 : in std_ulogic; + TXENC8B10BUSE1 : in std_ulogic; + TXENPMAPHASEALIGN : in std_ulogic; + TXENPRBSTST0 : in std_logic_vector(1 downto 0); + TXENPRBSTST1 : in std_logic_vector(1 downto 0); + TXINHIBIT0 : in std_ulogic; + TXINHIBIT1 : in std_ulogic; + TXPMASETPHASE : in std_ulogic; + TXPOLARITY0 : in std_ulogic; + TXPOLARITY1 : in std_ulogic; + TXPOWERDOWN0 : in std_logic_vector(1 downto 0); + TXPOWERDOWN1 : in std_logic_vector(1 downto 0); + TXPREEMPHASIS0 : in std_logic_vector(2 downto 0); + TXPREEMPHASIS1 : in std_logic_vector(2 downto 0); + TXRESET0 : in std_ulogic; + TXRESET1 : in std_ulogic; + TXUSRCLK0 : in std_ulogic; + TXUSRCLK1 : in std_ulogic; + TXUSRCLK20 : in std_ulogic; + TXUSRCLK21 : in std_ulogic; + + AC_CAP_DIS_0 : in std_ulogic; + AC_CAP_DIS_1 : in std_ulogic; + ALIGN_COMMA_WORD_0 : in std_ulogic; + ALIGN_COMMA_WORD_1 : in std_ulogic; + CHAN_BOND_1_MAX_SKEW_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_1_MAX_SKEW_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_2_MAX_SKEW_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_2_MAX_SKEW_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_LEVEL_0 : in std_logic_vector(2 downto 0); + CHAN_BOND_LEVEL_1 : in std_logic_vector(2 downto 0); + CHAN_BOND_MODE_0 : in std_logic_vector(1 downto 0); + CHAN_BOND_MODE_1 : in std_logic_vector(1 downto 0); + CHAN_BOND_SEQ_1_1_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_1_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_2_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_2_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_3_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_3_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_4_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_4_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_1_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_1_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_2_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_2_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_3_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_3_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_4_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_4_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_USE_0 : in std_ulogic; + CHAN_BOND_SEQ_2_USE_1 : in std_ulogic; + CHAN_BOND_SEQ_LEN_0 : in std_logic_vector(1 downto 0); + CHAN_BOND_SEQ_LEN_1 : in std_logic_vector(1 downto 0); + CLK25_DIVIDER : in std_logic_vector(2 downto 0); + CLKINDC_B : in std_ulogic; + CLK_CORRECT_USE_0 : in std_ulogic; + CLK_CORRECT_USE_1 : in std_ulogic; + CLK_COR_ADJ_LEN_0 : in std_logic_vector(1 downto 0); + CLK_COR_ADJ_LEN_1 : in std_logic_vector(1 downto 0); + CLK_COR_DET_LEN_0 : in std_logic_vector(1 downto 0); + CLK_COR_DET_LEN_1 : in std_logic_vector(1 downto 0); + CLK_COR_INSERT_IDLE_FLAG_0 : in std_ulogic; + CLK_COR_INSERT_IDLE_FLAG_1 : in std_ulogic; + CLK_COR_KEEP_IDLE_0 : in std_ulogic; + CLK_COR_KEEP_IDLE_1 : in std_ulogic; + CLK_COR_MAX_LAT_0 : in std_logic_vector(5 downto 0); + CLK_COR_MAX_LAT_1 : in std_logic_vector(5 downto 0); + CLK_COR_MIN_LAT_0 : in std_logic_vector(5 downto 0); + CLK_COR_MIN_LAT_1 : in std_logic_vector(5 downto 0); + CLK_COR_PRECEDENCE_0 : in std_ulogic; + CLK_COR_PRECEDENCE_1 : in std_ulogic; + CLK_COR_REPEAT_WAIT_0 : in std_logic_vector(4 downto 0); + CLK_COR_REPEAT_WAIT_1 : in std_logic_vector(4 downto 0); + CLK_COR_SEQ_1_1_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_1_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_2_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_2_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_3_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_3_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_4_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_4_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_1_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_1_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_2_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_2_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_3_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_3_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_4_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_4_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_USE_0 : in std_ulogic; + CLK_COR_SEQ_2_USE_1 : in std_ulogic; + COMMA_10B_ENABLE_0 : in std_logic_vector(9 downto 0); + COMMA_10B_ENABLE_1 : in std_logic_vector(9 downto 0); + COMMA_DOUBLE_0 : in std_ulogic; + COMMA_DOUBLE_1 : in std_ulogic; + COM_BURST_VAL_0 : in std_logic_vector(3 downto 0); + COM_BURST_VAL_1 : in std_logic_vector(3 downto 0); + DEC_MCOMMA_DETECT_0 : in std_ulogic; + DEC_MCOMMA_DETECT_1 : in std_ulogic; + DEC_PCOMMA_DETECT_0 : in std_ulogic; + DEC_PCOMMA_DETECT_1 : in std_ulogic; + DEC_VALID_COMMA_ONLY_0 : in std_ulogic; + DEC_VALID_COMMA_ONLY_1 : in std_ulogic; + MCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); + MCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); + MCOMMA_DETECT_0 : in std_ulogic; + MCOMMA_DETECT_1 : in std_ulogic; + OOBDETECT_THRESHOLD_0 : in std_logic_vector(2 downto 0); + OOBDETECT_THRESHOLD_1 : in std_logic_vector(2 downto 0); + OOB_CLK_DIVIDER : in std_logic_vector(2 downto 0); + OVERSAMPLE_MODE : in std_ulogic; + PCI_EXPRESS_MODE_0 : in std_ulogic; + PCI_EXPRESS_MODE_1 : in std_ulogic; + PCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); + PCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); + PCOMMA_DETECT_0 : in std_ulogic; + PCOMMA_DETECT_1 : in std_ulogic; + PCS_COM_CFG : in std_logic_vector(27 downto 0); + PLL_DIVSEL_FB : in std_logic_vector(4 downto 0); + PLL_DIVSEL_REF : in std_logic_vector(5 downto 0); + PLL_RXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); + PLL_RXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); + PLL_SATA_0 : in std_ulogic; + PLL_SATA_1 : in std_ulogic; + PLL_TXDIVSEL_COMM_OUT : in std_logic_vector(1 downto 0); + PLL_TXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); + PLL_TXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); + PMA_CDR_SCAN_0 : in std_logic_vector(26 downto 0); + PMA_CDR_SCAN_1 : in std_logic_vector(26 downto 0); + PMA_RX_CFG_0 : in std_logic_vector(24 downto 0); + PMA_RX_CFG_1 : in std_logic_vector(24 downto 0); + PRBS_ERR_THRESHOLD_0 : in std_logic_vector(31 downto 0); + PRBS_ERR_THRESHOLD_1 : in std_logic_vector(31 downto 0); + RCV_TERM_GND_0 : in std_ulogic; + RCV_TERM_GND_1 : in std_ulogic; + RCV_TERM_MID_0 : in std_ulogic; + RCV_TERM_MID_1 : in std_ulogic; + RCV_TERM_VTTRX_0 : in std_ulogic; + RCV_TERM_VTTRX_1 : in std_ulogic; + RX_BUFFER_USE_0 : in std_ulogic; + RX_BUFFER_USE_1 : in std_ulogic; + RX_DECODE_SEQ_MATCH_0 : in std_ulogic; + RX_DECODE_SEQ_MATCH_1 : in std_ulogic; + RX_LOSS_OF_SYNC_FSM_0 : in std_ulogic; + RX_LOSS_OF_SYNC_FSM_1 : in std_ulogic; + RX_LOS_INVALID_INCR_0 : in std_logic_vector(2 downto 0); + RX_LOS_INVALID_INCR_1 : in std_logic_vector(2 downto 0); + RX_LOS_THRESHOLD_0 : in std_logic_vector(2 downto 0); + RX_LOS_THRESHOLD_1 : in std_logic_vector(2 downto 0); + RX_SLIDE_MODE_0 : in std_ulogic; + RX_SLIDE_MODE_1 : in std_ulogic; + RX_STATUS_FMT_0 : in std_ulogic; + RX_STATUS_FMT_1 : in std_ulogic; + RX_XCLK_SEL_0 : in std_ulogic; + RX_XCLK_SEL_1 : in std_ulogic; + SATA_BURST_VAL_0 : in std_logic_vector(2 downto 0); + SATA_BURST_VAL_1 : in std_logic_vector(2 downto 0); + SATA_IDLE_VAL_0 : in std_logic_vector(2 downto 0); + SATA_IDLE_VAL_1 : in std_logic_vector(2 downto 0); + SATA_MAX_BURST_0 : in std_logic_vector(5 downto 0); + SATA_MAX_BURST_1 : in std_logic_vector(5 downto 0); + SATA_MAX_INIT_0 : in std_logic_vector(5 downto 0); + SATA_MAX_INIT_1 : in std_logic_vector(5 downto 0); + SATA_MAX_WAKE_0 : in std_logic_vector(5 downto 0); + SATA_MAX_WAKE_1 : in std_logic_vector(5 downto 0); + SATA_MIN_BURST_0 : in std_logic_vector(5 downto 0); + SATA_MIN_BURST_1 : in std_logic_vector(5 downto 0); + SATA_MIN_INIT_0 : in std_logic_vector(5 downto 0); + SATA_MIN_INIT_1 : in std_logic_vector(5 downto 0); + SATA_MIN_WAKE_0 : in std_logic_vector(5 downto 0); + SATA_MIN_WAKE_1 : in std_logic_vector(5 downto 0); + SIM_GTPRESET_SPEEDUP : in std_ulogic; + SIM_PLL_PERDIV2 : in std_logic_vector(8 downto 0); + SIM_RECEIVER_DETECT_PASS0 : in std_ulogic; + SIM_RECEIVER_DETECT_PASS1 : in std_ulogic; + TERMINATION_CTRL : in std_logic_vector(4 downto 0); + TERMINATION_IMP_0 : in std_ulogic; + TERMINATION_IMP_1 : in std_ulogic; + TERMINATION_OVRD : in std_ulogic; + TRANS_TIME_FROM_P2_0 : in std_logic_vector(15 downto 0); + TRANS_TIME_FROM_P2_1 : in std_logic_vector(15 downto 0); + TRANS_TIME_NON_P2_0 : in std_logic_vector(15 downto 0); + TRANS_TIME_NON_P2_1 : in std_logic_vector(15 downto 0); + TRANS_TIME_TO_P2_0 : in std_logic_vector(15 downto 0); + TRANS_TIME_TO_P2_1 : in std_logic_vector(15 downto 0); + TXRX_INVERT_0 : in std_logic_vector(4 downto 0); + TXRX_INVERT_1 : in std_logic_vector(4 downto 0); + TX_BUFFER_USE_0 : in std_ulogic; + TX_BUFFER_USE_1 : in std_ulogic; + TX_DIFF_BOOST_0 : in std_ulogic; + TX_DIFF_BOOST_1 : in std_ulogic; + TX_SYNC_FILTERB : in std_ulogic; + TX_XCLK_SEL_0 : in std_ulogic; + TX_XCLK_SEL_1 : in std_ulogic + ); + end component; + + constant IN_DELAY : time := 0 ps; + constant OUT_DELAY : time := 0 ps; + constant CLK_DELAY : time := 0 ps; + + constant PATH_DELAY : VitalDelayType01 := (100 ps, 100 ps); + + signal PLL_TXDIVSEL_OUT_0_BINARY : std_logic_vector(1 downto 0); + signal PLL_RXDIVSEL_OUT_0_BINARY : std_logic_vector(1 downto 0); + signal PLL_TXDIVSEL_OUT_1_BINARY : std_logic_vector(1 downto 0); + signal PLL_RXDIVSEL_OUT_1_BINARY : std_logic_vector(1 downto 0); + signal PLL_DIVSEL_FB_BINARY : std_logic_vector(4 downto 0); + signal PLL_DIVSEL_REF_BINARY : std_logic_vector(5 downto 0); + signal PLL_TXDIVSEL_COMM_OUT_BINARY : std_logic_vector(1 downto 0); + signal PLL_SATA_0_BINARY : std_ulogic; + signal PLL_SATA_1_BINARY : std_ulogic; + signal TX_DIFF_BOOST_0_BINARY : std_ulogic; + signal OOBDETECT_THRESHOLD_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(OOBDETECT_THRESHOLD_0); + signal TX_DIFF_BOOST_1_BINARY : std_ulogic; + signal OOBDETECT_THRESHOLD_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(OOBDETECT_THRESHOLD_1); + signal PMA_CDR_SCAN_0_BINARY : std_logic_vector(26 downto 0) := To_StdLogicVector(PMA_CDR_SCAN_0)(26 downto 0); + signal PMA_CDR_SCAN_1_BINARY : std_logic_vector(26 downto 0) := To_StdLogicVector(PMA_CDR_SCAN_1)(26 downto 0); + signal PMA_RX_CFG_0_BINARY : std_logic_vector(24 downto 0) := To_StdLogicVector(PMA_RX_CFG_0)(24 downto 0); + signal PMA_RX_CFG_1_BINARY : std_logic_vector(24 downto 0) := To_StdLogicVector(PMA_RX_CFG_1)(24 downto 0); + signal OOB_CLK_DIVIDER_BINARY : std_logic_vector(2 downto 0); + signal TX_SYNC_FILTERB_BINARY : std_ulogic; + signal AC_CAP_DIS_0_BINARY : std_ulogic; + signal AC_CAP_DIS_1_BINARY : std_ulogic; + signal RCV_TERM_GND_0_BINARY : std_ulogic; + signal RCV_TERM_GND_1_BINARY : std_ulogic; + signal RCV_TERM_MID_0_BINARY : std_ulogic; + signal RCV_TERM_MID_1_BINARY : std_ulogic; + signal TERMINATION_IMP_0_BINARY : std_ulogic; + signal TERMINATION_IMP_1_BINARY : std_ulogic; + signal TERMINATION_OVRD_BINARY : std_ulogic; + signal TERMINATION_CTRL_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TERMINATION_CTRL); + signal RCV_TERM_VTTRX_0_BINARY : std_ulogic; + signal RCV_TERM_VTTRX_1_BINARY : std_ulogic; + signal TXRX_INVERT_0_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TXRX_INVERT_0); + signal TXRX_INVERT_1_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TXRX_INVERT_1); + signal CLKINDC_B_BINARY : std_ulogic; + signal PCOMMA_DETECT_0_BINARY : std_ulogic; + signal MCOMMA_DETECT_0_BINARY : std_ulogic; + signal PCOMMA_10B_VALUE_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(PCOMMA_10B_VALUE_0); + signal MCOMMA_10B_VALUE_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(MCOMMA_10B_VALUE_0); + signal COMMA_10B_ENABLE_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(COMMA_10B_ENABLE_0); + signal COMMA_DOUBLE_0_BINARY : std_ulogic; + signal ALIGN_COMMA_WORD_0_BINARY : std_ulogic; + signal DEC_PCOMMA_DETECT_0_BINARY : std_ulogic; + signal DEC_MCOMMA_DETECT_0_BINARY : std_ulogic; + signal DEC_VALID_COMMA_ONLY_0_BINARY : std_ulogic; + signal PCOMMA_DETECT_1_BINARY : std_ulogic; + signal MCOMMA_DETECT_1_BINARY : std_ulogic; + signal PCOMMA_10B_VALUE_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(PCOMMA_10B_VALUE_1); + signal MCOMMA_10B_VALUE_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(MCOMMA_10B_VALUE_1); + signal COMMA_10B_ENABLE_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(COMMA_10B_ENABLE_1); + signal COMMA_DOUBLE_1_BINARY : std_ulogic; + signal ALIGN_COMMA_WORD_1_BINARY : std_ulogic; + signal DEC_PCOMMA_DETECT_1_BINARY : std_ulogic; + signal DEC_MCOMMA_DETECT_1_BINARY : std_ulogic; + signal DEC_VALID_COMMA_ONLY_1_BINARY : std_ulogic; + signal RX_LOSS_OF_SYNC_FSM_0_BINARY : std_ulogic; + signal RX_LOS_INVALID_INCR_0_BINARY : std_logic_vector(2 downto 0); + signal RX_LOS_THRESHOLD_0_BINARY : std_logic_vector(2 downto 0); + signal RX_LOSS_OF_SYNC_FSM_1_BINARY : std_ulogic; + signal RX_LOS_INVALID_INCR_1_BINARY : std_logic_vector(2 downto 0); + signal RX_LOS_THRESHOLD_1_BINARY : std_logic_vector(2 downto 0); + signal RX_BUFFER_USE_0_BINARY : std_ulogic; + signal RX_DECODE_SEQ_MATCH_0_BINARY : std_ulogic; + signal RX_BUFFER_USE_1_BINARY : std_ulogic; + signal RX_DECODE_SEQ_MATCH_1_BINARY : std_ulogic; + signal CLK_COR_MIN_LAT_0_BINARY : std_logic_vector(5 downto 0); + signal CLK_COR_MAX_LAT_0_BINARY : std_logic_vector(5 downto 0); + signal CLK_CORRECT_USE_0_BINARY : std_ulogic; + signal CLK_COR_PRECEDENCE_0_BINARY : std_ulogic; + signal CLK_COR_DET_LEN_0_BINARY : std_logic_vector(1 downto 0); + signal CLK_COR_ADJ_LEN_0_BINARY : std_logic_vector(1 downto 0); + signal CLK_COR_KEEP_IDLE_0_BINARY : std_ulogic; + signal CLK_COR_INSERT_IDLE_FLAG_0_BINARY : std_ulogic; + signal CLK_COR_REPEAT_WAIT_0_BINARY : std_logic_vector(4 downto 0); + signal CLK_COR_SEQ_2_USE_0_BINARY : std_ulogic; + signal CLK_COR_SEQ_1_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1_0); + signal CLK_COR_SEQ_1_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2_0); + signal CLK_COR_SEQ_1_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3_0); + signal CLK_COR_SEQ_1_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4_0); + signal CLK_COR_SEQ_2_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1_0); + signal CLK_COR_SEQ_2_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2_0); + signal CLK_COR_SEQ_2_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3_0); + signal CLK_COR_SEQ_2_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4_0); + signal CLK_COR_SEQ_1_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_ENABLE_0); + signal CLK_COR_SEQ_2_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_ENABLE_0); + signal CLK_COR_MIN_LAT_1_BINARY : std_logic_vector(5 downto 0); + signal CLK_COR_MAX_LAT_1_BINARY : std_logic_vector(5 downto 0); + signal CLK_CORRECT_USE_1_BINARY : std_ulogic; + signal CLK_COR_PRECEDENCE_1_BINARY : std_ulogic; + signal CLK_COR_DET_LEN_1_BINARY : std_logic_vector(1 downto 0); + signal CLK_COR_ADJ_LEN_1_BINARY : std_logic_vector(1 downto 0); + signal CLK_COR_KEEP_IDLE_1_BINARY : std_ulogic; + signal CLK_COR_INSERT_IDLE_FLAG_1_BINARY : std_ulogic; + signal CLK_COR_REPEAT_WAIT_1_BINARY : std_logic_vector(4 downto 0); + signal CLK_COR_SEQ_2_USE_1_BINARY : std_ulogic; + signal CLK_COR_SEQ_1_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1_1); + signal CLK_COR_SEQ_1_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2_1); + signal CLK_COR_SEQ_1_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3_1); + signal CLK_COR_SEQ_1_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4_1); + signal CLK_COR_SEQ_2_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1_1); + signal CLK_COR_SEQ_2_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2_1); + signal CLK_COR_SEQ_2_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3_1); + signal CLK_COR_SEQ_2_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4_1); + signal CLK_COR_SEQ_1_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_ENABLE_1); + signal CLK_COR_SEQ_2_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_ENABLE_1); + signal CHAN_BOND_MODE_0_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_LEVEL_0_BINARY : std_logic_vector(2 downto 0); + signal CHAN_BOND_SEQ_LEN_0_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_SEQ_2_USE_0_BINARY : std_ulogic; + signal CHAN_BOND_SEQ_1_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1_0); + signal CHAN_BOND_SEQ_1_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2_0); + signal CHAN_BOND_SEQ_1_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3_0); + signal CHAN_BOND_SEQ_1_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4_0); + signal CHAN_BOND_SEQ_2_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1_0); + signal CHAN_BOND_SEQ_2_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2_0); + signal CHAN_BOND_SEQ_2_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3_0); + signal CHAN_BOND_SEQ_2_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4_0); + signal CHAN_BOND_SEQ_1_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_ENABLE_0); + signal CHAN_BOND_SEQ_2_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_ENABLE_0); + signal CHAN_BOND_1_MAX_SKEW_0_BINARY : std_logic_vector(3 downto 0); + signal CHAN_BOND_2_MAX_SKEW_0_BINARY : std_logic_vector(3 downto 0); + signal CHAN_BOND_MODE_1_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_LEVEL_1_BINARY : std_logic_vector(2 downto 0); + signal CHAN_BOND_SEQ_LEN_1_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_SEQ_2_USE_1_BINARY : std_ulogic; + signal CHAN_BOND_SEQ_1_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1_1); + signal CHAN_BOND_SEQ_1_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2_1); + signal CHAN_BOND_SEQ_1_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3_1); + signal CHAN_BOND_SEQ_1_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4_1); + signal CHAN_BOND_SEQ_2_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1_1); + signal CHAN_BOND_SEQ_2_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2_1); + signal CHAN_BOND_SEQ_2_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3_1); + signal CHAN_BOND_SEQ_2_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4_1); + signal CHAN_BOND_SEQ_1_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_ENABLE_1); + signal CHAN_BOND_SEQ_2_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_ENABLE_1); + signal CHAN_BOND_1_MAX_SKEW_1_BINARY : std_logic_vector(3 downto 0); + signal CHAN_BOND_2_MAX_SKEW_1_BINARY : std_logic_vector(3 downto 0); + signal PCI_EXPRESS_MODE_0_BINARY : std_ulogic; + signal TRANS_TIME_FROM_P2_0_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TRANS_TIME_FROM_P2_0); + signal TRANS_TIME_NON_P2_0_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TRANS_TIME_NON_P2_0); + signal TRANS_TIME_TO_P2_0_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TRANS_TIME_TO_P2_0); + signal PCI_EXPRESS_MODE_1_BINARY : std_ulogic; + signal TRANS_TIME_FROM_P2_1_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TRANS_TIME_FROM_P2_1); + signal TRANS_TIME_NON_P2_1_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TRANS_TIME_NON_P2_1); + signal TRANS_TIME_TO_P2_1_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TRANS_TIME_TO_P2_1); + signal RX_STATUS_FMT_0_BINARY : std_ulogic; + signal TX_BUFFER_USE_0_BINARY : std_ulogic; + signal TX_XCLK_SEL_0_BINARY : std_ulogic; + signal RX_XCLK_SEL_0_BINARY : std_ulogic; + signal RX_STATUS_FMT_1_BINARY : std_ulogic; + signal TX_BUFFER_USE_1_BINARY : std_ulogic; + signal TX_XCLK_SEL_1_BINARY : std_ulogic; + signal RX_XCLK_SEL_1_BINARY : std_ulogic; + signal PRBS_ERR_THRESHOLD_0_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(PRBS_ERR_THRESHOLD_0); + signal RX_SLIDE_MODE_0_BINARY : std_ulogic; + signal PRBS_ERR_THRESHOLD_1_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(PRBS_ERR_THRESHOLD_1); + signal RX_SLIDE_MODE_1_BINARY : std_ulogic; + signal SATA_MIN_BURST_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_BURST_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_INIT_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_INIT_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_WAKE_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_WAKE_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_BURST_VAL_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_BURST_VAL_0); + signal SATA_IDLE_VAL_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_IDLE_VAL_0); + signal COM_BURST_VAL_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(COM_BURST_VAL_0); + signal SATA_MIN_BURST_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_BURST_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_INIT_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_INIT_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_WAKE_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_WAKE_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_BURST_VAL_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_BURST_VAL_1); + signal SATA_IDLE_VAL_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_IDLE_VAL_1); + signal COM_BURST_VAL_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(COM_BURST_VAL_1); + signal CLK25_DIVIDER_BINARY : std_logic_vector(2 downto 0); + signal PCS_COM_CFG_BINARY : std_logic_vector(27 downto 0) := To_StdLogicVector(PCS_COM_CFG); + signal OVERSAMPLE_MODE_BINARY : std_ulogic; + signal SIM_GTPRESET_SPEEDUP_BINARY : std_ulogic; + signal SIM_MODE_BINARY : std_ulogic; + signal SIM_PLL_PERDIV2_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(SIM_PLL_PERDIV2)(8 downto 0); + signal SIM_RECEIVER_DETECT_PASS0_BINARY : std_ulogic; + signal SIM_RECEIVER_DETECT_PASS1_BINARY : std_ulogic; + + signal REFCLKOUT_out : std_ulogic; + signal RXRECCLK0_out : std_ulogic; + signal TXOUTCLK0_out : std_ulogic; + signal RXRECCLK1_out : std_ulogic; + signal TXOUTCLK1_out : std_ulogic; + signal TXP0_out : std_ulogic; + signal TXN0_out : std_ulogic; + signal TXP1_out : std_ulogic; + signal TXN1_out : std_ulogic; + signal RXDATA0_out : std_logic_vector(15 downto 0); + signal RXNOTINTABLE0_out : std_logic_vector(1 downto 0); + signal RXDISPERR0_out : std_logic_vector(1 downto 0); + signal RXCHARISK0_out : std_logic_vector(1 downto 0); + signal RXRUNDISP0_out : std_logic_vector(1 downto 0); + signal RXCHARISCOMMA0_out : std_logic_vector(1 downto 0); + signal RXVALID0_out : std_ulogic; + signal RXDATA1_out : std_logic_vector(15 downto 0); + signal RXNOTINTABLE1_out : std_logic_vector(1 downto 0); + signal RXDISPERR1_out : std_logic_vector(1 downto 0); + signal RXCHARISK1_out : std_logic_vector(1 downto 0); + signal RXRUNDISP1_out : std_logic_vector(1 downto 0); + signal RXCHARISCOMMA1_out : std_logic_vector(1 downto 0); + signal RXVALID1_out : std_ulogic; + signal RESETDONE0_out : std_ulogic; + signal RESETDONE1_out : std_ulogic; + signal TXKERR0_out : std_logic_vector(1 downto 0); + signal TXRUNDISP0_out : std_logic_vector(1 downto 0); + signal TXBUFSTATUS0_out : std_logic_vector(1 downto 0); + signal TXKERR1_out : std_logic_vector(1 downto 0); + signal TXRUNDISP1_out : std_logic_vector(1 downto 0); + signal TXBUFSTATUS1_out : std_logic_vector(1 downto 0); + signal RXCOMMADET0_out : std_ulogic; + signal RXBYTEREALIGN0_out : std_ulogic; + signal RXBYTEISALIGNED0_out : std_ulogic; + signal RXLOSSOFSYNC0_out : std_logic_vector(1 downto 0); + signal RXCHBONDO0_out : std_logic_vector(2 downto 0); + signal RXCHANBONDSEQ0_out : std_ulogic; + signal RXCHANREALIGN0_out : std_ulogic; + signal RXCHANISALIGNED0_out : std_ulogic; + signal RXBUFSTATUS0_out : std_logic_vector(2 downto 0); + signal RXCOMMADET1_out : std_ulogic; + signal RXBYTEREALIGN1_out : std_ulogic; + signal RXBYTEISALIGNED1_out : std_ulogic; + signal RXLOSSOFSYNC1_out : std_logic_vector(1 downto 0); + signal RXCHBONDO1_out : std_logic_vector(2 downto 0); + signal RXCHANBONDSEQ1_out : std_ulogic; + signal RXCHANREALIGN1_out : std_ulogic; + signal RXCHANISALIGNED1_out : std_ulogic; + signal RXBUFSTATUS1_out : std_logic_vector(2 downto 0); + signal PHYSTATUS0_out : std_ulogic; + signal PHYSTATUS1_out : std_ulogic; + signal RXELECIDLE0_out : std_ulogic; + signal RXSTATUS0_out : std_logic_vector(2 downto 0); + signal RXCLKCORCNT0_out : std_logic_vector(2 downto 0); + signal RXELECIDLE1_out : std_ulogic; + signal RXSTATUS1_out : std_logic_vector(2 downto 0); + signal RXCLKCORCNT1_out : std_logic_vector(2 downto 0); + signal PLLLKDET_out : std_ulogic; + signal RXPRBSERR0_out : std_ulogic; + signal RXPRBSERR1_out : std_ulogic; + signal DO_out : std_logic_vector(15 downto 0); + signal DRDY_out : std_ulogic; + signal RXOVERSAMPLEERR0_out : std_ulogic; + signal RXOVERSAMPLEERR1_out : std_ulogic; + signal REFCLKOUT_outdelay : std_logic; + signal RXRECCLK0_outdelay : std_logic; + signal TXOUTCLK0_outdelay : std_logic; + signal RXRECCLK1_outdelay : std_logic; + signal TXOUTCLK1_outdelay : std_logic; + signal RXCLKCORCNT0_outdelay : std_logic_vector(2 downto 0); + signal RXCLKCORCNT1_outdelay : std_logic_vector(2 downto 0); + signal TXP0_outdelay : std_logic; + signal TXN0_outdelay : std_logic; + signal TXP1_outdelay : std_logic; + signal TXN1_outdelay : std_logic; + signal RXDATA0_outdelay : std_logic_vector(15 downto 0); + signal RXNOTINTABLE0_outdelay : std_logic_vector(1 downto 0); + signal RXDISPERR0_outdelay : std_logic_vector(1 downto 0); + signal RXCHARISK0_outdelay : std_logic_vector(1 downto 0); + signal RXRUNDISP0_outdelay : std_logic_vector(1 downto 0); + signal RXCHARISCOMMA0_outdelay : std_logic_vector(1 downto 0); + signal RXVALID0_outdelay : std_logic; + signal RXDATA1_outdelay : std_logic_vector(15 downto 0); + signal RXNOTINTABLE1_outdelay : std_logic_vector(1 downto 0); + signal RXDISPERR1_outdelay : std_logic_vector(1 downto 0); + signal RXCHARISK1_outdelay : std_logic_vector(1 downto 0); + signal RXRUNDISP1_outdelay : std_logic_vector(1 downto 0); + signal RXCHARISCOMMA1_outdelay : std_logic_vector(1 downto 0); + signal RXVALID1_outdelay : std_logic; + signal RESETDONE0_outdelay : std_logic; + signal RESETDONE1_outdelay : std_logic; + signal TXKERR0_outdelay : std_logic_vector(1 downto 0); + signal TXRUNDISP0_outdelay : std_logic_vector(1 downto 0); + signal TXBUFSTATUS0_outdelay : std_logic_vector(1 downto 0); + signal TXKERR1_outdelay : std_logic_vector(1 downto 0); + signal TXRUNDISP1_outdelay : std_logic_vector(1 downto 0); + signal TXBUFSTATUS1_outdelay : std_logic_vector(1 downto 0); + signal RXCOMMADET0_outdelay : std_logic; + signal RXBYTEREALIGN0_outdelay : std_logic; + signal RXBYTEISALIGNED0_outdelay : std_logic; + signal RXLOSSOFSYNC0_outdelay : std_logic_vector(1 downto 0); + signal RXCHBONDO0_outdelay : std_logic_vector(2 downto 0); + signal RXCHANBONDSEQ0_outdelay : std_logic; + signal RXCHANREALIGN0_outdelay : std_logic; + signal RXCHANISALIGNED0_outdelay : std_logic; + signal RXBUFSTATUS0_outdelay : std_logic_vector(2 downto 0); + signal RXCOMMADET1_outdelay : std_logic; + signal RXBYTEREALIGN1_outdelay : std_logic; + signal RXBYTEISALIGNED1_outdelay : std_logic; + signal RXLOSSOFSYNC1_outdelay : std_logic_vector(1 downto 0); + signal RXCHBONDO1_outdelay : std_logic_vector(2 downto 0); + signal RXCHANBONDSEQ1_outdelay : std_logic; + signal RXCHANREALIGN1_outdelay : std_logic; + signal RXCHANISALIGNED1_outdelay : std_logic; + signal RXBUFSTATUS1_outdelay : std_logic_vector(2 downto 0); + signal PHYSTATUS0_outdelay : std_logic; + signal PHYSTATUS1_outdelay : std_logic; + signal RXELECIDLE0_outdelay : std_logic; + signal RXSTATUS0_outdelay : std_logic_vector(2 downto 0); + signal RXELECIDLE1_outdelay : std_logic; + signal RXSTATUS1_outdelay : std_logic_vector(2 downto 0); + signal PLLLKDET_outdelay : std_logic; + signal RXPRBSERR0_outdelay : std_logic; + signal RXPRBSERR1_outdelay : std_logic; + signal DO_outdelay : std_logic_vector(15 downto 0); + signal DRDY_outdelay : std_logic; + signal RXOVERSAMPLEERR0_outdelay : std_logic; + signal RXOVERSAMPLEERR1_outdelay : std_logic; + + signal CLKIN_ipd : std_ulogic; + signal TXUSRCLK0_ipd : std_ulogic; + signal TXUSRCLK20_ipd : std_ulogic; + signal RXUSRCLK0_ipd : std_ulogic; + signal RXUSRCLK20_ipd : std_ulogic; + signal TXUSRCLK1_ipd : std_ulogic; + signal TXUSRCLK21_ipd : std_ulogic; + signal RXUSRCLK1_ipd : std_ulogic; + signal RXUSRCLK21_ipd : std_ulogic; + signal RXP0_ipd : std_ulogic; + signal RXN0_ipd : std_ulogic; + signal TXDATA0_ipd : std_logic_vector(15 downto 0); + signal TXBYPASS8B10B0_ipd : std_logic_vector(1 downto 0); + signal TXCHARISK0_ipd : std_logic_vector(1 downto 0); + signal TXCHARDISPMODE0_ipd : std_logic_vector(1 downto 0); + signal TXCHARDISPVAL0_ipd : std_logic_vector(1 downto 0); + signal RXP1_ipd : std_ulogic; + signal RXN1_ipd : std_ulogic; + signal TXDATA1_ipd : std_logic_vector(15 downto 0); + signal TXBYPASS8B10B1_ipd : std_logic_vector(1 downto 0); + signal TXCHARISK1_ipd : std_logic_vector(1 downto 0); + signal TXCHARDISPMODE1_ipd : std_logic_vector(1 downto 0); + signal TXCHARDISPVAL1_ipd : std_logic_vector(1 downto 0); + signal GTPRESET_ipd : std_ulogic; + signal RXCDRRESET0_ipd : std_ulogic; + signal TXRESET0_ipd : std_ulogic; + signal RXRESET0_ipd : std_ulogic; + signal RXBUFRESET0_ipd : std_ulogic; + signal RXCDRRESET1_ipd : std_ulogic; + signal TXRESET1_ipd : std_ulogic; + signal RXRESET1_ipd : std_ulogic; + signal RXBUFRESET1_ipd : std_ulogic; + signal TXPOWERDOWN0_ipd : std_logic_vector(1 downto 0); + signal RXPOWERDOWN0_ipd : std_logic_vector(1 downto 0); + signal TXPOWERDOWN1_ipd : std_logic_vector(1 downto 0); + signal RXPOWERDOWN1_ipd : std_logic_vector(1 downto 0); + signal PLLPOWERDOWN_ipd : std_ulogic; + signal REFCLKPWRDNB_ipd : std_ulogic; + signal LOOPBACK0_ipd : std_logic_vector(2 downto 0); + signal LOOPBACK1_ipd : std_logic_vector(2 downto 0); + signal TXDIFFCTRL0_ipd : std_logic_vector(2 downto 0); + signal TXBUFDIFFCTRL0_ipd : std_logic_vector(2 downto 0); + signal TXPREEMPHASIS0_ipd : std_logic_vector(2 downto 0); + signal TXDIFFCTRL1_ipd : std_logic_vector(2 downto 0); + signal TXBUFDIFFCTRL1_ipd : std_logic_vector(2 downto 0); + signal TXPREEMPHASIS1_ipd : std_logic_vector(2 downto 0); + signal RXENEQB0_ipd : std_ulogic; + signal RXEQMIX0_ipd : std_logic_vector(1 downto 0); + signal RXEQPOLE0_ipd : std_logic_vector(3 downto 0); + signal RXENEQB1_ipd : std_ulogic; + signal RXEQMIX1_ipd : std_logic_vector(1 downto 0); + signal RXEQPOLE1_ipd : std_logic_vector(3 downto 0); + signal INTDATAWIDTH_ipd : std_ulogic; + signal TXDATAWIDTH0_ipd : std_ulogic; + signal TXDATAWIDTH1_ipd : std_ulogic; + signal TXENPMAPHASEALIGN_ipd : std_ulogic; + signal TXPMASETPHASE_ipd : std_ulogic; + signal RXPMASETPHASE0_ipd : std_ulogic; + signal RXPMASETPHASE1_ipd : std_ulogic; + signal TXENC8B10BUSE0_ipd : std_ulogic; + signal TXPOLARITY0_ipd : std_ulogic; + signal TXINHIBIT0_ipd : std_ulogic; + signal TXENC8B10BUSE1_ipd : std_ulogic; + signal TXPOLARITY1_ipd : std_ulogic; + signal TXINHIBIT1_ipd : std_ulogic; + signal RXPOLARITY0_ipd : std_ulogic; + signal RXENPCOMMAALIGN0_ipd : std_ulogic; + signal RXENMCOMMAALIGN0_ipd : std_ulogic; + signal RXSLIDE0_ipd : std_ulogic; + signal RXCOMMADETUSE0_ipd : std_ulogic; + signal RXDEC8B10BUSE0_ipd : std_ulogic; + signal RXENCHANSYNC0_ipd : std_ulogic; + signal RXCHBONDI0_ipd : std_logic_vector(2 downto 0); + signal RXDATAWIDTH0_ipd : std_ulogic; + signal RXPOLARITY1_ipd : std_ulogic; + signal RXENPCOMMAALIGN1_ipd : std_ulogic; + signal RXENMCOMMAALIGN1_ipd : std_ulogic; + signal RXSLIDE1_ipd : std_ulogic; + signal RXCOMMADETUSE1_ipd : std_ulogic; + signal RXDEC8B10BUSE1_ipd : std_ulogic; + signal RXENCHANSYNC1_ipd : std_ulogic; + signal RXCHBONDI1_ipd : std_logic_vector(2 downto 0); + signal RXDATAWIDTH1_ipd : std_ulogic; + signal TXELECIDLE0_ipd : std_ulogic; + signal TXDETECTRX0_ipd : std_ulogic; + signal TXELECIDLE1_ipd : std_ulogic; + signal TXDETECTRX1_ipd : std_ulogic; + signal TXCOMSTART0_ipd : std_ulogic; + signal TXCOMTYPE0_ipd : std_ulogic; + signal TXCOMSTART1_ipd : std_ulogic; + signal TXCOMTYPE1_ipd : std_ulogic; + signal PLLLKDETEN_ipd : std_ulogic; + signal TXENPRBSTST0_ipd : std_logic_vector(1 downto 0); + signal RXENPRBSTST0_ipd : std_logic_vector(1 downto 0); + signal PRBSCNTRESET0_ipd : std_ulogic; + signal TXENPRBSTST1_ipd : std_logic_vector(1 downto 0); + signal RXENPRBSTST1_ipd : std_logic_vector(1 downto 0); + signal PRBSCNTRESET1_ipd : std_ulogic; + signal DCLK_ipd : std_ulogic; + signal DADDR_ipd : std_logic_vector(6 downto 0); + signal DI_ipd : std_logic_vector(15 downto 0); + signal DEN_ipd : std_ulogic; + signal DWE_ipd : std_ulogic; + signal RXENSAMPLEALIGN0_ipd : std_ulogic; + signal RXENSAMPLEALIGN1_ipd : std_ulogic; + signal RXELECIDLERESET0_ipd : std_ulogic; + signal RXELECIDLERESET1_ipd : std_ulogic; + signal RXENELECIDLERESETB_ipd : std_ulogic; + signal GTPTEST_ipd : std_logic_vector(3 downto 0); + + signal CLKIN_indelay : std_ulogic; + signal TXUSRCLK0_indelay : std_ulogic; + signal TXUSRCLK20_indelay : std_ulogic; + signal RXUSRCLK0_indelay : std_ulogic; + signal RXUSRCLK20_indelay : std_ulogic; + signal TXUSRCLK1_indelay : std_ulogic; + signal TXUSRCLK21_indelay : std_ulogic; + signal RXUSRCLK1_indelay : std_ulogic; + signal RXUSRCLK21_indelay : std_ulogic; + signal RXP0_indelay : std_ulogic; + signal RXN0_indelay : std_ulogic; + signal TXDATA0_indelay : std_logic_vector(15 downto 0); + signal TXBYPASS8B10B0_indelay : std_logic_vector(1 downto 0); + signal TXCHARISK0_indelay : std_logic_vector(1 downto 0); + signal TXCHARDISPMODE0_indelay : std_logic_vector(1 downto 0); + signal TXCHARDISPVAL0_indelay : std_logic_vector(1 downto 0); + signal RXP1_indelay : std_ulogic; + signal RXN1_indelay : std_ulogic; + signal TXDATA1_indelay : std_logic_vector(15 downto 0); + signal TXBYPASS8B10B1_indelay : std_logic_vector(1 downto 0); + signal TXCHARISK1_indelay : std_logic_vector(1 downto 0); + signal TXCHARDISPMODE1_indelay : std_logic_vector(1 downto 0); + signal TXCHARDISPVAL1_indelay : std_logic_vector(1 downto 0); + signal GTPRESET_indelay : std_ulogic; + signal RXCDRRESET0_indelay : std_ulogic; + signal TXRESET0_indelay : std_ulogic; + signal RXRESET0_indelay : std_ulogic; + signal RXBUFRESET0_indelay : std_ulogic; + signal RXCDRRESET1_indelay : std_ulogic; + signal TXRESET1_indelay : std_ulogic; + signal RXRESET1_indelay : std_ulogic; + signal RXBUFRESET1_indelay : std_ulogic; + signal TXPOWERDOWN0_indelay : std_logic_vector(1 downto 0); + signal RXPOWERDOWN0_indelay : std_logic_vector(1 downto 0); + signal TXPOWERDOWN1_indelay : std_logic_vector(1 downto 0); + signal RXPOWERDOWN1_indelay : std_logic_vector(1 downto 0); + signal PLLPOWERDOWN_indelay : std_ulogic; + signal REFCLKPWRDNB_indelay : std_ulogic; + signal LOOPBACK0_indelay : std_logic_vector(2 downto 0); + signal LOOPBACK1_indelay : std_logic_vector(2 downto 0); + signal TXDIFFCTRL0_indelay : std_logic_vector(2 downto 0); + signal TXBUFDIFFCTRL0_indelay : std_logic_vector(2 downto 0); + signal TXPREEMPHASIS0_indelay : std_logic_vector(2 downto 0); + signal TXDIFFCTRL1_indelay : std_logic_vector(2 downto 0); + signal TXBUFDIFFCTRL1_indelay : std_logic_vector(2 downto 0); + signal TXPREEMPHASIS1_indelay : std_logic_vector(2 downto 0); + signal RXENEQB0_indelay : std_ulogic; + signal RXEQMIX0_indelay : std_logic_vector(1 downto 0); + signal RXEQPOLE0_indelay : std_logic_vector(3 downto 0); + signal RXENEQB1_indelay : std_ulogic; + signal RXEQMIX1_indelay : std_logic_vector(1 downto 0); + signal RXEQPOLE1_indelay : std_logic_vector(3 downto 0); + signal INTDATAWIDTH_indelay : std_ulogic; + signal TXDATAWIDTH0_indelay : std_ulogic; + signal TXDATAWIDTH1_indelay : std_ulogic; + signal TXENPMAPHASEALIGN_indelay : std_ulogic; + signal TXPMASETPHASE_indelay : std_ulogic; + signal RXPMASETPHASE0_indelay : std_ulogic; + signal RXPMASETPHASE1_indelay : std_ulogic; + signal TXENC8B10BUSE0_indelay : std_ulogic; + signal TXPOLARITY0_indelay : std_ulogic; + signal TXINHIBIT0_indelay : std_ulogic; + signal TXENC8B10BUSE1_indelay : std_ulogic; + signal TXPOLARITY1_indelay : std_ulogic; + signal TXINHIBIT1_indelay : std_ulogic; + signal RXPOLARITY0_indelay : std_ulogic; + signal RXENPCOMMAALIGN0_indelay : std_ulogic; + signal RXENMCOMMAALIGN0_indelay : std_ulogic; + signal RXSLIDE0_indelay : std_ulogic; + signal RXCOMMADETUSE0_indelay : std_ulogic; + signal RXDEC8B10BUSE0_indelay : std_ulogic; + signal RXENCHANSYNC0_indelay : std_ulogic; + signal RXCHBONDI0_indelay : std_logic_vector(2 downto 0); + signal RXDATAWIDTH0_indelay : std_ulogic; + signal RXPOLARITY1_indelay : std_ulogic; + signal RXENPCOMMAALIGN1_indelay : std_ulogic; + signal RXENMCOMMAALIGN1_indelay : std_ulogic; + signal RXSLIDE1_indelay : std_ulogic; + signal RXCOMMADETUSE1_indelay : std_ulogic; + signal RXDEC8B10BUSE1_indelay : std_ulogic; + signal RXENCHANSYNC1_indelay : std_ulogic; + signal RXCHBONDI1_indelay : std_logic_vector(2 downto 0); + signal RXDATAWIDTH1_indelay : std_ulogic; + signal TXELECIDLE0_indelay : std_ulogic; + signal TXDETECTRX0_indelay : std_ulogic; + signal TXELECIDLE1_indelay : std_ulogic; + signal TXDETECTRX1_indelay : std_ulogic; + signal TXCOMSTART0_indelay : std_ulogic; + signal TXCOMTYPE0_indelay : std_ulogic; + signal TXCOMSTART1_indelay : std_ulogic; + signal TXCOMTYPE1_indelay : std_ulogic; + signal PLLLKDETEN_indelay : std_ulogic; + signal TXENPRBSTST0_indelay : std_logic_vector(1 downto 0); + signal RXENPRBSTST0_indelay : std_logic_vector(1 downto 0); + signal PRBSCNTRESET0_indelay : std_ulogic; + signal TXENPRBSTST1_indelay : std_logic_vector(1 downto 0); + signal RXENPRBSTST1_indelay : std_logic_vector(1 downto 0); + signal PRBSCNTRESET1_indelay : std_ulogic; + signal DCLK_indelay : std_ulogic; + signal DADDR_indelay : std_logic_vector(6 downto 0); + signal DI_indelay : std_logic_vector(15 downto 0); + signal DEN_indelay : std_ulogic; + signal DWE_indelay : std_ulogic; + signal RXENSAMPLEALIGN0_indelay : std_ulogic; + signal RXENSAMPLEALIGN1_indelay : std_ulogic; + signal RXELECIDLERESET0_indelay : std_ulogic; + signal RXELECIDLERESET1_indelay : std_ulogic; + signal RXENELECIDLERESETB_indelay : std_ulogic; + signal GTPTEST_indelay : std_logic_vector(3 downto 0); + +begin + + REFCLKOUT_out <= REFCLKOUT_outdelay after CLK_DELAY; + RXCLKCORCNT0_out <= RXCLKCORCNT0_outdelay after CLK_DELAY; + RXCLKCORCNT1_out <= RXCLKCORCNT1_outdelay after CLK_DELAY; + RXRECCLK0_out <= RXRECCLK0_outdelay after CLK_DELAY; + RXRECCLK1_out <= RXRECCLK1_outdelay after CLK_DELAY; + TXOUTCLK0_out <= TXOUTCLK0_outdelay after CLK_DELAY; + TXOUTCLK1_out <= TXOUTCLK1_outdelay after CLK_DELAY; + + DO_out <= DO_outdelay after OUT_DELAY; + DRDY_out <= DRDY_outdelay after OUT_DELAY; + PHYSTATUS0_out <= PHYSTATUS0_outdelay after OUT_DELAY; + PHYSTATUS1_out <= PHYSTATUS1_outdelay after OUT_DELAY; + PLLLKDET_out <= PLLLKDET_outdelay after OUT_DELAY; + RESETDONE0_out <= RESETDONE0_outdelay after OUT_DELAY; + RESETDONE1_out <= RESETDONE1_outdelay after OUT_DELAY; + RXBUFSTATUS0_out <= RXBUFSTATUS0_outdelay after OUT_DELAY; + RXBUFSTATUS1_out <= RXBUFSTATUS1_outdelay after OUT_DELAY; + RXBYTEISALIGNED0_out <= RXBYTEISALIGNED0_outdelay after OUT_DELAY; + RXBYTEISALIGNED1_out <= RXBYTEISALIGNED1_outdelay after OUT_DELAY; + RXBYTEREALIGN0_out <= RXBYTEREALIGN0_outdelay after OUT_DELAY; + RXBYTEREALIGN1_out <= RXBYTEREALIGN1_outdelay after OUT_DELAY; + RXCHANBONDSEQ0_out <= RXCHANBONDSEQ0_outdelay after OUT_DELAY; + RXCHANBONDSEQ1_out <= RXCHANBONDSEQ1_outdelay after OUT_DELAY; + RXCHANISALIGNED0_out <= RXCHANISALIGNED0_outdelay after OUT_DELAY; + RXCHANISALIGNED1_out <= RXCHANISALIGNED1_outdelay after OUT_DELAY; + RXCHANREALIGN0_out <= RXCHANREALIGN0_outdelay after OUT_DELAY; + RXCHANREALIGN1_out <= RXCHANREALIGN1_outdelay after OUT_DELAY; + RXCHARISCOMMA0_out <= RXCHARISCOMMA0_outdelay after OUT_DELAY; + RXCHARISCOMMA1_out <= RXCHARISCOMMA1_outdelay after OUT_DELAY; + RXCHARISK0_out <= RXCHARISK0_outdelay after OUT_DELAY; + RXCHARISK1_out <= RXCHARISK1_outdelay after OUT_DELAY; + RXCHBONDO0_out <= RXCHBONDO0_outdelay after OUT_DELAY; + RXCHBONDO1_out <= RXCHBONDO1_outdelay after OUT_DELAY; + RXCOMMADET0_out <= RXCOMMADET0_outdelay after OUT_DELAY; + RXCOMMADET1_out <= RXCOMMADET1_outdelay after OUT_DELAY; + RXDATA0_out <= RXDATA0_outdelay after OUT_DELAY; + RXDATA1_out <= RXDATA1_outdelay after OUT_DELAY; + RXDISPERR0_out <= RXDISPERR0_outdelay after OUT_DELAY; + RXDISPERR1_out <= RXDISPERR1_outdelay after OUT_DELAY; + RXELECIDLE0_out <= RXELECIDLE0_outdelay after OUT_DELAY; + RXELECIDLE1_out <= RXELECIDLE1_outdelay after OUT_DELAY; + RXLOSSOFSYNC0_out <= RXLOSSOFSYNC0_outdelay after OUT_DELAY; + RXLOSSOFSYNC1_out <= RXLOSSOFSYNC1_outdelay after OUT_DELAY; + RXNOTINTABLE0_out <= RXNOTINTABLE0_outdelay after OUT_DELAY; + RXNOTINTABLE1_out <= RXNOTINTABLE1_outdelay after OUT_DELAY; + RXOVERSAMPLEERR0_out <= RXOVERSAMPLEERR0_outdelay after OUT_DELAY; + RXOVERSAMPLEERR1_out <= RXOVERSAMPLEERR1_outdelay after OUT_DELAY; + RXPRBSERR0_out <= RXPRBSERR0_outdelay after OUT_DELAY; + RXPRBSERR1_out <= RXPRBSERR1_outdelay after OUT_DELAY; + RXRUNDISP0_out <= RXRUNDISP0_outdelay after OUT_DELAY; + RXRUNDISP1_out <= RXRUNDISP1_outdelay after OUT_DELAY; + RXSTATUS0_out <= RXSTATUS0_outdelay after OUT_DELAY; + RXSTATUS1_out <= RXSTATUS1_outdelay after OUT_DELAY; + RXVALID0_out <= RXVALID0_outdelay after OUT_DELAY; + RXVALID1_out <= RXVALID1_outdelay after OUT_DELAY; + TXBUFSTATUS0_out <= TXBUFSTATUS0_outdelay after OUT_DELAY; + TXBUFSTATUS1_out <= TXBUFSTATUS1_outdelay after OUT_DELAY; + TXKERR0_out <= TXKERR0_outdelay after OUT_DELAY; + TXKERR1_out <= TXKERR1_outdelay after OUT_DELAY; + TXN0_out <= TXN0_outdelay after OUT_DELAY; + TXN1_out <= TXN1_outdelay after OUT_DELAY; + TXP0_out <= TXP0_outdelay after OUT_DELAY; + TXP1_out <= TXP1_outdelay after OUT_DELAY; + TXRUNDISP0_out <= TXRUNDISP0_outdelay after OUT_DELAY; + TXRUNDISP1_out <= TXRUNDISP1_outdelay after OUT_DELAY; + + CLKIN_ipd <= CLKIN after CLK_DELAY; + DCLK_ipd <= DCLK after CLK_DELAY; + RXUSRCLK0_ipd <= RXUSRCLK0 after CLK_DELAY; + RXUSRCLK1_ipd <= RXUSRCLK1 after CLK_DELAY; + RXUSRCLK20_ipd <= RXUSRCLK20 after CLK_DELAY; + RXUSRCLK21_ipd <= RXUSRCLK21 after CLK_DELAY; + TXUSRCLK0_ipd <= TXUSRCLK0 after CLK_DELAY; + TXUSRCLK1_ipd <= TXUSRCLK1 after CLK_DELAY; + TXUSRCLK20_ipd <= TXUSRCLK20 after CLK_DELAY; + TXUSRCLK21_ipd <= TXUSRCLK21 after CLK_DELAY; + + DADDR_ipd <= DADDR after CLK_DELAY; + DEN_ipd <= DEN after CLK_DELAY; + DI_ipd <= DI after CLK_DELAY; + DWE_ipd <= DWE after CLK_DELAY; + GTPRESET_ipd <= GTPRESET after CLK_DELAY; + GTPTEST_ipd <= GTPTEST after CLK_DELAY; + INTDATAWIDTH_ipd <= INTDATAWIDTH after CLK_DELAY; + LOOPBACK0_ipd <= LOOPBACK0 after CLK_DELAY; + LOOPBACK1_ipd <= LOOPBACK1 after CLK_DELAY; + PLLLKDETEN_ipd <= PLLLKDETEN after CLK_DELAY; + PLLPOWERDOWN_ipd <= PLLPOWERDOWN after CLK_DELAY; + PRBSCNTRESET0_ipd <= PRBSCNTRESET0 after CLK_DELAY; + PRBSCNTRESET1_ipd <= PRBSCNTRESET1 after CLK_DELAY; + REFCLKPWRDNB_ipd <= REFCLKPWRDNB after CLK_DELAY; + RXBUFRESET0_ipd <= RXBUFRESET0 after CLK_DELAY; + RXBUFRESET1_ipd <= RXBUFRESET1 after CLK_DELAY; + RXCDRRESET0_ipd <= RXCDRRESET0 after CLK_DELAY; + RXCDRRESET1_ipd <= RXCDRRESET1 after CLK_DELAY; + RXCHBONDI0_ipd <= RXCHBONDI0 after CLK_DELAY; + RXCHBONDI1_ipd <= RXCHBONDI1 after CLK_DELAY; + RXCOMMADETUSE0_ipd <= RXCOMMADETUSE0 after CLK_DELAY; + RXCOMMADETUSE1_ipd <= RXCOMMADETUSE1 after CLK_DELAY; + RXDATAWIDTH0_ipd <= RXDATAWIDTH0 after CLK_DELAY; + RXDATAWIDTH1_ipd <= RXDATAWIDTH1 after CLK_DELAY; + RXDEC8B10BUSE0_ipd <= RXDEC8B10BUSE0 after CLK_DELAY; + RXDEC8B10BUSE1_ipd <= RXDEC8B10BUSE1 after CLK_DELAY; + RXELECIDLERESET0_ipd <= RXELECIDLERESET0 after CLK_DELAY; + RXELECIDLERESET1_ipd <= RXELECIDLERESET1 after CLK_DELAY; + RXENCHANSYNC0_ipd <= RXENCHANSYNC0 after CLK_DELAY; + RXENCHANSYNC1_ipd <= RXENCHANSYNC1 after CLK_DELAY; + RXENELECIDLERESETB_ipd <= RXENELECIDLERESETB after CLK_DELAY; + RXENEQB0_ipd <= RXENEQB0 after CLK_DELAY; + RXENEQB1_ipd <= RXENEQB1 after CLK_DELAY; + RXENMCOMMAALIGN0_ipd <= RXENMCOMMAALIGN0 after CLK_DELAY; + RXENMCOMMAALIGN1_ipd <= RXENMCOMMAALIGN1 after CLK_DELAY; + RXENPCOMMAALIGN0_ipd <= RXENPCOMMAALIGN0 after CLK_DELAY; + RXENPCOMMAALIGN1_ipd <= RXENPCOMMAALIGN1 after CLK_DELAY; + RXENPRBSTST0_ipd <= RXENPRBSTST0 after CLK_DELAY; + RXENPRBSTST1_ipd <= RXENPRBSTST1 after CLK_DELAY; + RXENSAMPLEALIGN0_ipd <= RXENSAMPLEALIGN0 after CLK_DELAY; + RXENSAMPLEALIGN1_ipd <= RXENSAMPLEALIGN1 after CLK_DELAY; + RXEQMIX0_ipd <= RXEQMIX0 after CLK_DELAY; + RXEQMIX1_ipd <= RXEQMIX1 after CLK_DELAY; + RXEQPOLE0_ipd <= RXEQPOLE0 after CLK_DELAY; + RXEQPOLE1_ipd <= RXEQPOLE1 after CLK_DELAY; + RXN0_ipd <= RXN0 after CLK_DELAY; + RXN1_ipd <= RXN1 after CLK_DELAY; + RXP0_ipd <= RXP0 after CLK_DELAY; + RXP1_ipd <= RXP1 after CLK_DELAY; + RXPMASETPHASE0_ipd <= RXPMASETPHASE0 after CLK_DELAY; + RXPMASETPHASE1_ipd <= RXPMASETPHASE1 after CLK_DELAY; + RXPOLARITY0_ipd <= RXPOLARITY0 after CLK_DELAY; + RXPOLARITY1_ipd <= RXPOLARITY1 after CLK_DELAY; + RXPOWERDOWN0_ipd <= RXPOWERDOWN0 after CLK_DELAY; + RXPOWERDOWN1_ipd <= RXPOWERDOWN1 after CLK_DELAY; + RXRESET0_ipd <= RXRESET0 after CLK_DELAY; + RXRESET1_ipd <= RXRESET1 after CLK_DELAY; + RXSLIDE0_ipd <= RXSLIDE0 after CLK_DELAY; + RXSLIDE1_ipd <= RXSLIDE1 after CLK_DELAY; + TXBUFDIFFCTRL0_ipd <= TXBUFDIFFCTRL0 after CLK_DELAY; + TXBUFDIFFCTRL1_ipd <= TXBUFDIFFCTRL1 after CLK_DELAY; + TXBYPASS8B10B0_ipd <= TXBYPASS8B10B0 after CLK_DELAY; + TXBYPASS8B10B1_ipd <= TXBYPASS8B10B1 after CLK_DELAY; + TXCHARDISPMODE0_ipd <= TXCHARDISPMODE0 after CLK_DELAY; + TXCHARDISPMODE1_ipd <= TXCHARDISPMODE1 after CLK_DELAY; + TXCHARDISPVAL0_ipd <= TXCHARDISPVAL0 after CLK_DELAY; + TXCHARDISPVAL1_ipd <= TXCHARDISPVAL1 after CLK_DELAY; + TXCHARISK0_ipd <= TXCHARISK0 after CLK_DELAY; + TXCHARISK1_ipd <= TXCHARISK1 after CLK_DELAY; + TXCOMSTART0_ipd <= TXCOMSTART0 after CLK_DELAY; + TXCOMSTART1_ipd <= TXCOMSTART1 after CLK_DELAY; + TXCOMTYPE0_ipd <= TXCOMTYPE0 after CLK_DELAY; + TXCOMTYPE1_ipd <= TXCOMTYPE1 after CLK_DELAY; + TXDATA0_ipd <= TXDATA0 after CLK_DELAY; + TXDATA1_ipd <= TXDATA1 after CLK_DELAY; + TXDATAWIDTH0_ipd <= TXDATAWIDTH0 after CLK_DELAY; + TXDATAWIDTH1_ipd <= TXDATAWIDTH1 after CLK_DELAY; + TXDETECTRX0_ipd <= TXDETECTRX0 after CLK_DELAY; + TXDETECTRX1_ipd <= TXDETECTRX1 after CLK_DELAY; + TXDIFFCTRL0_ipd <= TXDIFFCTRL0 after CLK_DELAY; + TXDIFFCTRL1_ipd <= TXDIFFCTRL1 after CLK_DELAY; + TXELECIDLE0_ipd <= TXELECIDLE0 after CLK_DELAY; + TXELECIDLE1_ipd <= TXELECIDLE1 after CLK_DELAY; + TXENC8B10BUSE0_ipd <= TXENC8B10BUSE0 after CLK_DELAY; + TXENC8B10BUSE1_ipd <= TXENC8B10BUSE1 after CLK_DELAY; + TXENPMAPHASEALIGN_ipd <= TXENPMAPHASEALIGN after CLK_DELAY; + TXENPRBSTST0_ipd <= TXENPRBSTST0 after CLK_DELAY; + TXENPRBSTST1_ipd <= TXENPRBSTST1 after CLK_DELAY; + TXINHIBIT0_ipd <= TXINHIBIT0 after CLK_DELAY; + TXINHIBIT1_ipd <= TXINHIBIT1 after CLK_DELAY; + TXPMASETPHASE_ipd <= TXPMASETPHASE after CLK_DELAY; + TXPOLARITY0_ipd <= TXPOLARITY0 after CLK_DELAY; + TXPOLARITY1_ipd <= TXPOLARITY1 after CLK_DELAY; + TXPOWERDOWN0_ipd <= TXPOWERDOWN0 after CLK_DELAY; + TXPOWERDOWN1_ipd <= TXPOWERDOWN1 after CLK_DELAY; + TXPREEMPHASIS0_ipd <= TXPREEMPHASIS0 after CLK_DELAY; + TXPREEMPHASIS1_ipd <= TXPREEMPHASIS1 after CLK_DELAY; + TXRESET0_ipd <= TXRESET0 after CLK_DELAY; + TXRESET1_ipd <= TXRESET1 after CLK_DELAY; + + CLKIN_indelay <= CLKIN_ipd after CLK_DELAY; + DCLK_indelay <= DCLK_ipd after CLK_DELAY; + RXUSRCLK0_indelay <= RXUSRCLK0_ipd after CLK_DELAY; + RXUSRCLK1_indelay <= RXUSRCLK1_ipd after CLK_DELAY; + RXUSRCLK20_indelay <= RXUSRCLK20_ipd after CLK_DELAY; + RXUSRCLK21_indelay <= RXUSRCLK21_ipd after CLK_DELAY; + TXUSRCLK0_indelay <= TXUSRCLK0_ipd after CLK_DELAY; + TXUSRCLK1_indelay <= TXUSRCLK1_ipd after CLK_DELAY; + TXUSRCLK20_indelay <= TXUSRCLK20_ipd after CLK_DELAY; + TXUSRCLK21_indelay <= TXUSRCLK21_ipd after CLK_DELAY; + + DADDR_indelay <= DADDR_ipd after IN_DELAY; + DEN_indelay <= DEN_ipd after IN_DELAY; + DI_indelay <= DI_ipd after IN_DELAY; + DWE_indelay <= DWE_ipd after IN_DELAY; + GTPRESET_indelay <= GTPRESET_ipd after IN_DELAY; + GTPTEST_indelay <= GTPTEST_ipd after IN_DELAY; + INTDATAWIDTH_indelay <= INTDATAWIDTH_ipd after IN_DELAY; + LOOPBACK0_indelay <= LOOPBACK0_ipd after IN_DELAY; + LOOPBACK1_indelay <= LOOPBACK1_ipd after IN_DELAY; + PLLLKDETEN_indelay <= PLLLKDETEN_ipd after IN_DELAY; + PLLPOWERDOWN_indelay <= PLLPOWERDOWN_ipd after IN_DELAY; + PRBSCNTRESET0_indelay <= PRBSCNTRESET0_ipd after IN_DELAY; + PRBSCNTRESET1_indelay <= PRBSCNTRESET1_ipd after IN_DELAY; + REFCLKPWRDNB_indelay <= REFCLKPWRDNB_ipd after IN_DELAY; + RXBUFRESET0_indelay <= RXBUFRESET0_ipd after IN_DELAY; + RXBUFRESET1_indelay <= RXBUFRESET1_ipd after IN_DELAY; + RXCDRRESET0_indelay <= RXCDRRESET0_ipd after IN_DELAY; + RXCDRRESET1_indelay <= RXCDRRESET1_ipd after IN_DELAY; + RXCHBONDI0_indelay <= RXCHBONDI0_ipd after IN_DELAY; + RXCHBONDI1_indelay <= RXCHBONDI1_ipd after IN_DELAY; + RXCOMMADETUSE0_indelay <= RXCOMMADETUSE0_ipd after IN_DELAY; + RXCOMMADETUSE1_indelay <= RXCOMMADETUSE1_ipd after IN_DELAY; + RXDATAWIDTH0_indelay <= RXDATAWIDTH0_ipd after IN_DELAY; + RXDATAWIDTH1_indelay <= RXDATAWIDTH1_ipd after IN_DELAY; + RXDEC8B10BUSE0_indelay <= RXDEC8B10BUSE0_ipd after IN_DELAY; + RXDEC8B10BUSE1_indelay <= RXDEC8B10BUSE1_ipd after IN_DELAY; + RXELECIDLERESET0_indelay <= RXELECIDLERESET0_ipd after IN_DELAY; + RXELECIDLERESET1_indelay <= RXELECIDLERESET1_ipd after IN_DELAY; + RXENCHANSYNC0_indelay <= RXENCHANSYNC0_ipd after IN_DELAY; + RXENCHANSYNC1_indelay <= RXENCHANSYNC1_ipd after IN_DELAY; + RXENELECIDLERESETB_indelay <= RXENELECIDLERESETB_ipd after IN_DELAY; + RXENEQB0_indelay <= RXENEQB0_ipd after IN_DELAY; + RXENEQB1_indelay <= RXENEQB1_ipd after IN_DELAY; + RXENMCOMMAALIGN0_indelay <= RXENMCOMMAALIGN0_ipd after IN_DELAY; + RXENMCOMMAALIGN1_indelay <= RXENMCOMMAALIGN1_ipd after IN_DELAY; + RXENPCOMMAALIGN0_indelay <= RXENPCOMMAALIGN0_ipd after IN_DELAY; + RXENPCOMMAALIGN1_indelay <= RXENPCOMMAALIGN1_ipd after IN_DELAY; + RXENPRBSTST0_indelay <= RXENPRBSTST0_ipd after IN_DELAY; + RXENPRBSTST1_indelay <= RXENPRBSTST1_ipd after IN_DELAY; + RXENSAMPLEALIGN0_indelay <= RXENSAMPLEALIGN0_ipd after IN_DELAY; + RXENSAMPLEALIGN1_indelay <= RXENSAMPLEALIGN1_ipd after IN_DELAY; + RXEQMIX0_indelay <= RXEQMIX0_ipd after IN_DELAY; + RXEQMIX1_indelay <= RXEQMIX1_ipd after IN_DELAY; + RXEQPOLE0_indelay <= RXEQPOLE0_ipd after IN_DELAY; + RXEQPOLE1_indelay <= RXEQPOLE1_ipd after IN_DELAY; + RXN0_indelay <= RXN0_ipd after IN_DELAY; + RXN1_indelay <= RXN1_ipd after IN_DELAY; + RXP0_indelay <= RXP0_ipd after IN_DELAY; + RXP1_indelay <= RXP1_ipd after IN_DELAY; + RXPMASETPHASE0_indelay <= RXPMASETPHASE0_ipd after IN_DELAY; + RXPMASETPHASE1_indelay <= RXPMASETPHASE1_ipd after IN_DELAY; + RXPOLARITY0_indelay <= RXPOLARITY0_ipd after IN_DELAY; + RXPOLARITY1_indelay <= RXPOLARITY1_ipd after IN_DELAY; + RXPOWERDOWN0_indelay <= RXPOWERDOWN0_ipd after IN_DELAY; + RXPOWERDOWN1_indelay <= RXPOWERDOWN1_ipd after IN_DELAY; + RXRESET0_indelay <= RXRESET0_ipd after IN_DELAY; + RXRESET1_indelay <= RXRESET1_ipd after IN_DELAY; + RXSLIDE0_indelay <= RXSLIDE0_ipd after IN_DELAY; + RXSLIDE1_indelay <= RXSLIDE1_ipd after IN_DELAY; + TXBUFDIFFCTRL0_indelay <= TXBUFDIFFCTRL0_ipd after IN_DELAY; + TXBUFDIFFCTRL1_indelay <= TXBUFDIFFCTRL1_ipd after IN_DELAY; + TXBYPASS8B10B0_indelay <= TXBYPASS8B10B0_ipd after IN_DELAY; + TXBYPASS8B10B1_indelay <= TXBYPASS8B10B1_ipd after IN_DELAY; + TXCHARDISPMODE0_indelay <= TXCHARDISPMODE0_ipd after IN_DELAY; + TXCHARDISPMODE1_indelay <= TXCHARDISPMODE1_ipd after IN_DELAY; + TXCHARDISPVAL0_indelay <= TXCHARDISPVAL0_ipd after IN_DELAY; + TXCHARDISPVAL1_indelay <= TXCHARDISPVAL1_ipd after IN_DELAY; + TXCHARISK0_indelay <= TXCHARISK0_ipd after IN_DELAY; + TXCHARISK1_indelay <= TXCHARISK1_ipd after IN_DELAY; + TXCOMSTART0_indelay <= TXCOMSTART0_ipd after IN_DELAY; + TXCOMSTART1_indelay <= TXCOMSTART1_ipd after IN_DELAY; + TXCOMTYPE0_indelay <= TXCOMTYPE0_ipd after IN_DELAY; + TXCOMTYPE1_indelay <= TXCOMTYPE1_ipd after IN_DELAY; + TXDATA0_indelay <= TXDATA0_ipd after IN_DELAY; + TXDATA1_indelay <= TXDATA1_ipd after IN_DELAY; + TXDATAWIDTH0_indelay <= TXDATAWIDTH0_ipd after IN_DELAY; + TXDATAWIDTH1_indelay <= TXDATAWIDTH1_ipd after IN_DELAY; + TXDETECTRX0_indelay <= TXDETECTRX0_ipd after IN_DELAY; + TXDETECTRX1_indelay <= TXDETECTRX1_ipd after IN_DELAY; + TXDIFFCTRL0_indelay <= TXDIFFCTRL0_ipd after IN_DELAY; + TXDIFFCTRL1_indelay <= TXDIFFCTRL1_ipd after IN_DELAY; + TXELECIDLE0_indelay <= TXELECIDLE0_ipd after IN_DELAY; + TXELECIDLE1_indelay <= TXELECIDLE1_ipd after IN_DELAY; + TXENC8B10BUSE0_indelay <= TXENC8B10BUSE0_ipd after IN_DELAY; + TXENC8B10BUSE1_indelay <= TXENC8B10BUSE1_ipd after IN_DELAY; + TXENPMAPHASEALIGN_indelay <= TXENPMAPHASEALIGN_ipd after IN_DELAY; + TXENPRBSTST0_indelay <= TXENPRBSTST0_ipd after IN_DELAY; + TXENPRBSTST1_indelay <= TXENPRBSTST1_ipd after IN_DELAY; + TXINHIBIT0_indelay <= TXINHIBIT0_ipd after IN_DELAY; + TXINHIBIT1_indelay <= TXINHIBIT1_ipd after IN_DELAY; + TXPMASETPHASE_indelay <= TXPMASETPHASE_ipd after IN_DELAY; + TXPOLARITY0_indelay <= TXPOLARITY0_ipd after IN_DELAY; + TXPOLARITY1_indelay <= TXPOLARITY1_ipd after IN_DELAY; + TXPOWERDOWN0_indelay <= TXPOWERDOWN0_ipd after IN_DELAY; + TXPOWERDOWN1_indelay <= TXPOWERDOWN1_ipd after IN_DELAY; + TXPREEMPHASIS0_indelay <= TXPREEMPHASIS0_ipd after IN_DELAY; + TXPREEMPHASIS1_indelay <= TXPREEMPHASIS1_ipd after IN_DELAY; + TXRESET0_indelay <= TXRESET0_ipd after IN_DELAY; + TXRESET1_indelay <= TXRESET1_ipd after IN_DELAY; + + legacy_model: if SIM_MODE = "LEGACY" generate + gtp_dual_swift_bw_1 : GTP_DUAL_SWIFT_BUS + port map ( + AC_CAP_DIS_0 => AC_CAP_DIS_0_BINARY, + AC_CAP_DIS_1 => AC_CAP_DIS_1_BINARY, + ALIGN_COMMA_WORD_0 => ALIGN_COMMA_WORD_0_BINARY, + ALIGN_COMMA_WORD_1 => ALIGN_COMMA_WORD_1_BINARY, + CHAN_BOND_1_MAX_SKEW_0 => CHAN_BOND_1_MAX_SKEW_0_BINARY, + CHAN_BOND_1_MAX_SKEW_1 => CHAN_BOND_1_MAX_SKEW_1_BINARY, + CHAN_BOND_2_MAX_SKEW_0 => CHAN_BOND_2_MAX_SKEW_0_BINARY, + CHAN_BOND_2_MAX_SKEW_1 => CHAN_BOND_2_MAX_SKEW_1_BINARY, + CHAN_BOND_LEVEL_0 => CHAN_BOND_LEVEL_0_BINARY, + CHAN_BOND_LEVEL_1 => CHAN_BOND_LEVEL_1_BINARY, + CHAN_BOND_MODE_0 => CHAN_BOND_MODE_0_BINARY, + CHAN_BOND_MODE_1 => CHAN_BOND_MODE_1_BINARY, + CHAN_BOND_SEQ_1_1_0 => CHAN_BOND_SEQ_1_1_0_BINARY, + CHAN_BOND_SEQ_1_1_1 => CHAN_BOND_SEQ_1_1_1_BINARY, + CHAN_BOND_SEQ_1_2_0 => CHAN_BOND_SEQ_1_2_0_BINARY, + CHAN_BOND_SEQ_1_2_1 => CHAN_BOND_SEQ_1_2_1_BINARY, + CHAN_BOND_SEQ_1_3_0 => CHAN_BOND_SEQ_1_3_0_BINARY, + CHAN_BOND_SEQ_1_3_1 => CHAN_BOND_SEQ_1_3_1_BINARY, + CHAN_BOND_SEQ_1_4_0 => CHAN_BOND_SEQ_1_4_0_BINARY, + CHAN_BOND_SEQ_1_4_1 => CHAN_BOND_SEQ_1_4_1_BINARY, + CHAN_BOND_SEQ_1_ENABLE_0 => CHAN_BOND_SEQ_1_ENABLE_0_BINARY, + CHAN_BOND_SEQ_1_ENABLE_1 => CHAN_BOND_SEQ_1_ENABLE_1_BINARY, + CHAN_BOND_SEQ_2_1_0 => CHAN_BOND_SEQ_2_1_0_BINARY, + CHAN_BOND_SEQ_2_1_1 => CHAN_BOND_SEQ_2_1_1_BINARY, + CHAN_BOND_SEQ_2_2_0 => CHAN_BOND_SEQ_2_2_0_BINARY, + CHAN_BOND_SEQ_2_2_1 => CHAN_BOND_SEQ_2_2_1_BINARY, + CHAN_BOND_SEQ_2_3_0 => CHAN_BOND_SEQ_2_3_0_BINARY, + CHAN_BOND_SEQ_2_3_1 => CHAN_BOND_SEQ_2_3_1_BINARY, + CHAN_BOND_SEQ_2_4_0 => CHAN_BOND_SEQ_2_4_0_BINARY, + CHAN_BOND_SEQ_2_4_1 => CHAN_BOND_SEQ_2_4_1_BINARY, + CHAN_BOND_SEQ_2_ENABLE_0 => CHAN_BOND_SEQ_2_ENABLE_0_BINARY, + CHAN_BOND_SEQ_2_ENABLE_1 => CHAN_BOND_SEQ_2_ENABLE_1_BINARY, + CHAN_BOND_SEQ_2_USE_0 => CHAN_BOND_SEQ_2_USE_0_BINARY, + CHAN_BOND_SEQ_2_USE_1 => CHAN_BOND_SEQ_2_USE_1_BINARY, + CHAN_BOND_SEQ_LEN_0 => CHAN_BOND_SEQ_LEN_0_BINARY, + CHAN_BOND_SEQ_LEN_1 => CHAN_BOND_SEQ_LEN_1_BINARY, + CLK25_DIVIDER => CLK25_DIVIDER_BINARY, + CLKINDC_B => CLKINDC_B_BINARY, + CLK_CORRECT_USE_0 => CLK_CORRECT_USE_0_BINARY, + CLK_CORRECT_USE_1 => CLK_CORRECT_USE_1_BINARY, + CLK_COR_ADJ_LEN_0 => CLK_COR_ADJ_LEN_0_BINARY, + CLK_COR_ADJ_LEN_1 => CLK_COR_ADJ_LEN_1_BINARY, + CLK_COR_DET_LEN_0 => CLK_COR_DET_LEN_0_BINARY, + CLK_COR_DET_LEN_1 => CLK_COR_DET_LEN_1_BINARY, + CLK_COR_INSERT_IDLE_FLAG_0 => CLK_COR_INSERT_IDLE_FLAG_0_BINARY, + CLK_COR_INSERT_IDLE_FLAG_1 => CLK_COR_INSERT_IDLE_FLAG_1_BINARY, + CLK_COR_KEEP_IDLE_0 => CLK_COR_KEEP_IDLE_0_BINARY, + CLK_COR_KEEP_IDLE_1 => CLK_COR_KEEP_IDLE_1_BINARY, + CLK_COR_MAX_LAT_0 => CLK_COR_MAX_LAT_0_BINARY, + CLK_COR_MAX_LAT_1 => CLK_COR_MAX_LAT_1_BINARY, + CLK_COR_MIN_LAT_0 => CLK_COR_MIN_LAT_0_BINARY, + CLK_COR_MIN_LAT_1 => CLK_COR_MIN_LAT_1_BINARY, + CLK_COR_PRECEDENCE_0 => CLK_COR_PRECEDENCE_0_BINARY, + CLK_COR_PRECEDENCE_1 => CLK_COR_PRECEDENCE_1_BINARY, + CLK_COR_REPEAT_WAIT_0 => CLK_COR_REPEAT_WAIT_0_BINARY, + CLK_COR_REPEAT_WAIT_1 => CLK_COR_REPEAT_WAIT_1_BINARY, + CLK_COR_SEQ_1_1_0 => CLK_COR_SEQ_1_1_0_BINARY, + CLK_COR_SEQ_1_1_1 => CLK_COR_SEQ_1_1_1_BINARY, + CLK_COR_SEQ_1_2_0 => CLK_COR_SEQ_1_2_0_BINARY, + CLK_COR_SEQ_1_2_1 => CLK_COR_SEQ_1_2_1_BINARY, + CLK_COR_SEQ_1_3_0 => CLK_COR_SEQ_1_3_0_BINARY, + CLK_COR_SEQ_1_3_1 => CLK_COR_SEQ_1_3_1_BINARY, + CLK_COR_SEQ_1_4_0 => CLK_COR_SEQ_1_4_0_BINARY, + CLK_COR_SEQ_1_4_1 => CLK_COR_SEQ_1_4_1_BINARY, + CLK_COR_SEQ_1_ENABLE_0 => CLK_COR_SEQ_1_ENABLE_0_BINARY, + CLK_COR_SEQ_1_ENABLE_1 => CLK_COR_SEQ_1_ENABLE_1_BINARY, + CLK_COR_SEQ_2_1_0 => CLK_COR_SEQ_2_1_0_BINARY, + CLK_COR_SEQ_2_1_1 => CLK_COR_SEQ_2_1_1_BINARY, + CLK_COR_SEQ_2_2_0 => CLK_COR_SEQ_2_2_0_BINARY, + CLK_COR_SEQ_2_2_1 => CLK_COR_SEQ_2_2_1_BINARY, + CLK_COR_SEQ_2_3_0 => CLK_COR_SEQ_2_3_0_BINARY, + CLK_COR_SEQ_2_3_1 => CLK_COR_SEQ_2_3_1_BINARY, + CLK_COR_SEQ_2_4_0 => CLK_COR_SEQ_2_4_0_BINARY, + CLK_COR_SEQ_2_4_1 => CLK_COR_SEQ_2_4_1_BINARY, + CLK_COR_SEQ_2_ENABLE_0 => CLK_COR_SEQ_2_ENABLE_0_BINARY, + CLK_COR_SEQ_2_ENABLE_1 => CLK_COR_SEQ_2_ENABLE_1_BINARY, + CLK_COR_SEQ_2_USE_0 => CLK_COR_SEQ_2_USE_0_BINARY, + CLK_COR_SEQ_2_USE_1 => CLK_COR_SEQ_2_USE_1_BINARY, + COMMA_10B_ENABLE_0 => COMMA_10B_ENABLE_0_BINARY, + COMMA_10B_ENABLE_1 => COMMA_10B_ENABLE_1_BINARY, + COMMA_DOUBLE_0 => COMMA_DOUBLE_0_BINARY, + COMMA_DOUBLE_1 => COMMA_DOUBLE_1_BINARY, + COM_BURST_VAL_0 => COM_BURST_VAL_0_BINARY, + COM_BURST_VAL_1 => COM_BURST_VAL_1_BINARY, + DEC_MCOMMA_DETECT_0 => DEC_MCOMMA_DETECT_0_BINARY, + DEC_MCOMMA_DETECT_1 => DEC_MCOMMA_DETECT_1_BINARY, + DEC_PCOMMA_DETECT_0 => DEC_PCOMMA_DETECT_0_BINARY, + DEC_PCOMMA_DETECT_1 => DEC_PCOMMA_DETECT_1_BINARY, + DEC_VALID_COMMA_ONLY_0 => DEC_VALID_COMMA_ONLY_0_BINARY, + DEC_VALID_COMMA_ONLY_1 => DEC_VALID_COMMA_ONLY_1_BINARY, + MCOMMA_10B_VALUE_0 => MCOMMA_10B_VALUE_0_BINARY, + MCOMMA_10B_VALUE_1 => MCOMMA_10B_VALUE_1_BINARY, + MCOMMA_DETECT_0 => MCOMMA_DETECT_0_BINARY, + MCOMMA_DETECT_1 => MCOMMA_DETECT_1_BINARY, + OOBDETECT_THRESHOLD_0 => OOBDETECT_THRESHOLD_0_BINARY, + OOBDETECT_THRESHOLD_1 => OOBDETECT_THRESHOLD_1_BINARY, + OOB_CLK_DIVIDER => OOB_CLK_DIVIDER_BINARY, + OVERSAMPLE_MODE => OVERSAMPLE_MODE_BINARY, + PCI_EXPRESS_MODE_0 => PCI_EXPRESS_MODE_0_BINARY, + PCI_EXPRESS_MODE_1 => PCI_EXPRESS_MODE_1_BINARY, + PCOMMA_10B_VALUE_0 => PCOMMA_10B_VALUE_0_BINARY, + PCOMMA_10B_VALUE_1 => PCOMMA_10B_VALUE_1_BINARY, + PCOMMA_DETECT_0 => PCOMMA_DETECT_0_BINARY, + PCOMMA_DETECT_1 => PCOMMA_DETECT_1_BINARY, + PCS_COM_CFG => PCS_COM_CFG_BINARY, + PLL_DIVSEL_FB => PLL_DIVSEL_FB_BINARY, + PLL_DIVSEL_REF => PLL_DIVSEL_REF_BINARY, + PLL_RXDIVSEL_OUT_0 => PLL_RXDIVSEL_OUT_0_BINARY, + PLL_RXDIVSEL_OUT_1 => PLL_RXDIVSEL_OUT_1_BINARY, + PLL_SATA_0 => PLL_SATA_0_BINARY, + PLL_SATA_1 => PLL_SATA_1_BINARY, + PLL_TXDIVSEL_COMM_OUT => PLL_TXDIVSEL_COMM_OUT_BINARY, + PLL_TXDIVSEL_OUT_0 => PLL_TXDIVSEL_OUT_0_BINARY, + PLL_TXDIVSEL_OUT_1 => PLL_TXDIVSEL_OUT_1_BINARY, + PMA_CDR_SCAN_0 => PMA_CDR_SCAN_0_BINARY, + PMA_CDR_SCAN_1 => PMA_CDR_SCAN_1_BINARY, + PMA_RX_CFG_0 => PMA_RX_CFG_0_BINARY, + PMA_RX_CFG_1 => PMA_RX_CFG_1_BINARY, + PRBS_ERR_THRESHOLD_0 => PRBS_ERR_THRESHOLD_0_BINARY, + PRBS_ERR_THRESHOLD_1 => PRBS_ERR_THRESHOLD_1_BINARY, + RCV_TERM_GND_0 => RCV_TERM_GND_0_BINARY, + RCV_TERM_GND_1 => RCV_TERM_GND_1_BINARY, + RCV_TERM_MID_0 => RCV_TERM_MID_0_BINARY, + RCV_TERM_MID_1 => RCV_TERM_MID_1_BINARY, + RCV_TERM_VTTRX_0 => RCV_TERM_VTTRX_0_BINARY, + RCV_TERM_VTTRX_1 => RCV_TERM_VTTRX_1_BINARY, + RX_BUFFER_USE_0 => RX_BUFFER_USE_0_BINARY, + RX_BUFFER_USE_1 => RX_BUFFER_USE_1_BINARY, + RX_DECODE_SEQ_MATCH_0 => RX_DECODE_SEQ_MATCH_0_BINARY, + RX_DECODE_SEQ_MATCH_1 => RX_DECODE_SEQ_MATCH_1_BINARY, + RX_LOSS_OF_SYNC_FSM_0 => RX_LOSS_OF_SYNC_FSM_0_BINARY, + RX_LOSS_OF_SYNC_FSM_1 => RX_LOSS_OF_SYNC_FSM_1_BINARY, + RX_LOS_INVALID_INCR_0 => RX_LOS_INVALID_INCR_0_BINARY, + RX_LOS_INVALID_INCR_1 => RX_LOS_INVALID_INCR_1_BINARY, + RX_LOS_THRESHOLD_0 => RX_LOS_THRESHOLD_0_BINARY, + RX_LOS_THRESHOLD_1 => RX_LOS_THRESHOLD_1_BINARY, + RX_SLIDE_MODE_0 => RX_SLIDE_MODE_0_BINARY, + RX_SLIDE_MODE_1 => RX_SLIDE_MODE_1_BINARY, + RX_STATUS_FMT_0 => RX_STATUS_FMT_0_BINARY, + RX_STATUS_FMT_1 => RX_STATUS_FMT_1_BINARY, + RX_XCLK_SEL_0 => RX_XCLK_SEL_0_BINARY, + RX_XCLK_SEL_1 => RX_XCLK_SEL_1_BINARY, + SATA_BURST_VAL_0 => SATA_BURST_VAL_0_BINARY, + SATA_BURST_VAL_1 => SATA_BURST_VAL_1_BINARY, + SATA_IDLE_VAL_0 => SATA_IDLE_VAL_0_BINARY, + SATA_IDLE_VAL_1 => SATA_IDLE_VAL_1_BINARY, + SATA_MAX_BURST_0 => SATA_MAX_BURST_0_BINARY, + SATA_MAX_BURST_1 => SATA_MAX_BURST_1_BINARY, + SATA_MAX_INIT_0 => SATA_MAX_INIT_0_BINARY, + SATA_MAX_INIT_1 => SATA_MAX_INIT_1_BINARY, + SATA_MAX_WAKE_0 => SATA_MAX_WAKE_0_BINARY, + SATA_MAX_WAKE_1 => SATA_MAX_WAKE_1_BINARY, + SATA_MIN_BURST_0 => SATA_MIN_BURST_0_BINARY, + SATA_MIN_BURST_1 => SATA_MIN_BURST_1_BINARY, + SATA_MIN_INIT_0 => SATA_MIN_INIT_0_BINARY, + SATA_MIN_INIT_1 => SATA_MIN_INIT_1_BINARY, + SATA_MIN_WAKE_0 => SATA_MIN_WAKE_0_BINARY, + SATA_MIN_WAKE_1 => SATA_MIN_WAKE_1_BINARY, + SIM_GTPRESET_SPEEDUP => SIM_GTPRESET_SPEEDUP_BINARY, + SIM_PLL_PERDIV2 => SIM_PLL_PERDIV2_BINARY, + SIM_RECEIVER_DETECT_PASS0 => SIM_RECEIVER_DETECT_PASS0_BINARY, + SIM_RECEIVER_DETECT_PASS1 => SIM_RECEIVER_DETECT_PASS1_BINARY, + TERMINATION_CTRL => TERMINATION_CTRL_BINARY, + TERMINATION_IMP_0 => TERMINATION_IMP_0_BINARY, + TERMINATION_IMP_1 => TERMINATION_IMP_1_BINARY, + TERMINATION_OVRD => TERMINATION_OVRD_BINARY, + TRANS_TIME_FROM_P2_0 => TRANS_TIME_FROM_P2_0_BINARY, + TRANS_TIME_FROM_P2_1 => TRANS_TIME_FROM_P2_1_BINARY, + TRANS_TIME_NON_P2_0 => TRANS_TIME_NON_P2_0_BINARY, + TRANS_TIME_NON_P2_1 => TRANS_TIME_NON_P2_1_BINARY, + TRANS_TIME_TO_P2_0 => TRANS_TIME_TO_P2_0_BINARY, + TRANS_TIME_TO_P2_1 => TRANS_TIME_TO_P2_1_BINARY, + TXRX_INVERT_0 => TXRX_INVERT_0_BINARY, + TXRX_INVERT_1 => TXRX_INVERT_1_BINARY, + TX_BUFFER_USE_0 => TX_BUFFER_USE_0_BINARY, + TX_BUFFER_USE_1 => TX_BUFFER_USE_1_BINARY, + TX_DIFF_BOOST_0 => TX_DIFF_BOOST_0_BINARY, + TX_DIFF_BOOST_1 => TX_DIFF_BOOST_1_BINARY, + TX_SYNC_FILTERB => TX_SYNC_FILTERB_BINARY, + TX_XCLK_SEL_0 => TX_XCLK_SEL_0_BINARY, + TX_XCLK_SEL_1 => TX_XCLK_SEL_1_BINARY, + DO => DO_outdelay, + DRDY => DRDY_outdelay, + PHYSTATUS0 => PHYSTATUS0_outdelay, + PHYSTATUS1 => PHYSTATUS1_outdelay, + PLLLKDET => PLLLKDET_outdelay, + REFCLKOUT => REFCLKOUT_outdelay, + RESETDONE0 => RESETDONE0_outdelay, + RESETDONE1 => RESETDONE1_outdelay, + RXBUFSTATUS0 => RXBUFSTATUS0_outdelay, + RXBUFSTATUS1 => RXBUFSTATUS1_outdelay, + RXBYTEISALIGNED0 => RXBYTEISALIGNED0_outdelay, + RXBYTEISALIGNED1 => RXBYTEISALIGNED1_outdelay, + RXBYTEREALIGN0 => RXBYTEREALIGN0_outdelay, + RXBYTEREALIGN1 => RXBYTEREALIGN1_outdelay, + RXCHANBONDSEQ0 => RXCHANBONDSEQ0_outdelay, + RXCHANBONDSEQ1 => RXCHANBONDSEQ1_outdelay, + RXCHANISALIGNED0 => RXCHANISALIGNED0_outdelay, + RXCHANISALIGNED1 => RXCHANISALIGNED1_outdelay, + RXCHANREALIGN0 => RXCHANREALIGN0_outdelay, + RXCHANREALIGN1 => RXCHANREALIGN1_outdelay, + RXCHARISCOMMA0 => RXCHARISCOMMA0_outdelay, + RXCHARISCOMMA1 => RXCHARISCOMMA1_outdelay, + RXCHARISK0 => RXCHARISK0_outdelay, + RXCHARISK1 => RXCHARISK1_outdelay, + RXCHBONDO0 => RXCHBONDO0_outdelay, + RXCHBONDO1 => RXCHBONDO1_outdelay, + RXCLKCORCNT0 => RXCLKCORCNT0_outdelay, + RXCLKCORCNT1 => RXCLKCORCNT1_outdelay, + RXCOMMADET0 => RXCOMMADET0_outdelay, + RXCOMMADET1 => RXCOMMADET1_outdelay, + RXDATA0 => RXDATA0_outdelay, + RXDATA1 => RXDATA1_outdelay, + RXDISPERR0 => RXDISPERR0_outdelay, + RXDISPERR1 => RXDISPERR1_outdelay, + RXELECIDLE0 => RXELECIDLE0_outdelay, + RXELECIDLE1 => RXELECIDLE1_outdelay, + RXLOSSOFSYNC0 => RXLOSSOFSYNC0_outdelay, + RXLOSSOFSYNC1 => RXLOSSOFSYNC1_outdelay, + RXNOTINTABLE0 => RXNOTINTABLE0_outdelay, + RXNOTINTABLE1 => RXNOTINTABLE1_outdelay, + RXOVERSAMPLEERR0 => RXOVERSAMPLEERR0_outdelay, + RXOVERSAMPLEERR1 => RXOVERSAMPLEERR1_outdelay, + RXPRBSERR0 => RXPRBSERR0_outdelay, + RXPRBSERR1 => RXPRBSERR1_outdelay, + RXRECCLK0 => RXRECCLK0_outdelay, + RXRECCLK1 => RXRECCLK1_outdelay, + RXRUNDISP0 => RXRUNDISP0_outdelay, + RXRUNDISP1 => RXRUNDISP1_outdelay, + RXSTATUS0 => RXSTATUS0_outdelay, + RXSTATUS1 => RXSTATUS1_outdelay, + RXVALID0 => RXVALID0_outdelay, + RXVALID1 => RXVALID1_outdelay, + TXBUFSTATUS0 => TXBUFSTATUS0_outdelay, + TXBUFSTATUS1 => TXBUFSTATUS1_outdelay, + TXKERR0 => TXKERR0_outdelay, + TXKERR1 => TXKERR1_outdelay, + TXN0 => TXN0_outdelay, + TXN1 => TXN1_outdelay, + TXOUTCLK0 => TXOUTCLK0_outdelay, + TXOUTCLK1 => TXOUTCLK1_outdelay, + TXP0 => TXP0_outdelay, + TXP1 => TXP1_outdelay, + TXRUNDISP0 => TXRUNDISP0_outdelay, + TXRUNDISP1 => TXRUNDISP1_outdelay, + CLKIN => CLKIN_indelay, + DADDR => DADDR_indelay, + DCLK => DCLK_indelay, + DEN => DEN_indelay, + DI => DI_indelay, + DWE => DWE_indelay, + GSR => GSR, + GTPRESET => GTPRESET_indelay, + GTPTEST => GTPTEST_indelay, + INTDATAWIDTH => INTDATAWIDTH_indelay, + LOOPBACK0 => LOOPBACK0_indelay, + LOOPBACK1 => LOOPBACK1_indelay, + PLLLKDETEN => PLLLKDETEN_indelay, + PLLPOWERDOWN => PLLPOWERDOWN_indelay, + PRBSCNTRESET0 => PRBSCNTRESET0_indelay, + PRBSCNTRESET1 => PRBSCNTRESET1_indelay, + REFCLKPWRDNB => REFCLKPWRDNB_indelay, + RXBUFRESET0 => RXBUFRESET0_indelay, + RXBUFRESET1 => RXBUFRESET1_indelay, + RXCDRRESET0 => RXCDRRESET0_indelay, + RXCDRRESET1 => RXCDRRESET1_indelay, + RXCHBONDI0 => RXCHBONDI0_indelay, + RXCHBONDI1 => RXCHBONDI1_indelay, + RXCOMMADETUSE0 => RXCOMMADETUSE0_indelay, + RXCOMMADETUSE1 => RXCOMMADETUSE1_indelay, + RXDATAWIDTH0 => RXDATAWIDTH0_indelay, + RXDATAWIDTH1 => RXDATAWIDTH1_indelay, + RXDEC8B10BUSE0 => RXDEC8B10BUSE0_indelay, + RXDEC8B10BUSE1 => RXDEC8B10BUSE1_indelay, + RXELECIDLERESET0 => RXELECIDLERESET0_indelay, + RXELECIDLERESET1 => RXELECIDLERESET1_indelay, + RXENCHANSYNC0 => RXENCHANSYNC0_indelay, + RXENCHANSYNC1 => RXENCHANSYNC1_indelay, + RXENELECIDLERESETB => RXENELECIDLERESETB_indelay, + RXENEQB0 => RXENEQB0_indelay, + RXENEQB1 => RXENEQB1_indelay, + RXENMCOMMAALIGN0 => RXENMCOMMAALIGN0_indelay, + RXENMCOMMAALIGN1 => RXENMCOMMAALIGN1_indelay, + RXENPCOMMAALIGN0 => RXENPCOMMAALIGN0_indelay, + RXENPCOMMAALIGN1 => RXENPCOMMAALIGN1_indelay, + RXENPRBSTST0 => RXENPRBSTST0_indelay, + RXENPRBSTST1 => RXENPRBSTST1_indelay, + RXENSAMPLEALIGN0 => RXENSAMPLEALIGN0_indelay, + RXENSAMPLEALIGN1 => RXENSAMPLEALIGN1_indelay, + RXEQMIX0 => RXEQMIX0_indelay, + RXEQMIX1 => RXEQMIX1_indelay, + RXEQPOLE0 => RXEQPOLE0_indelay, + RXEQPOLE1 => RXEQPOLE1_indelay, + RXN0 => RXN0_indelay, + RXN1 => RXN1_indelay, + RXP0 => RXP0_indelay, + RXP1 => RXP1_indelay, + RXPMASETPHASE0 => RXPMASETPHASE0_indelay, + RXPMASETPHASE1 => RXPMASETPHASE1_indelay, + RXPOLARITY0 => RXPOLARITY0_indelay, + RXPOLARITY1 => RXPOLARITY1_indelay, + RXPOWERDOWN0 => RXPOWERDOWN0_indelay, + RXPOWERDOWN1 => RXPOWERDOWN1_indelay, + RXRESET0 => RXRESET0_indelay, + RXRESET1 => RXRESET1_indelay, + RXSLIDE0 => RXSLIDE0_indelay, + RXSLIDE1 => RXSLIDE1_indelay, + RXUSRCLK0 => RXUSRCLK0_indelay, + RXUSRCLK1 => RXUSRCLK1_indelay, + RXUSRCLK20 => RXUSRCLK20_indelay, + RXUSRCLK21 => RXUSRCLK21_indelay, + TXBUFDIFFCTRL0 => TXBUFDIFFCTRL0_indelay, + TXBUFDIFFCTRL1 => TXBUFDIFFCTRL1_indelay, + TXBYPASS8B10B0 => TXBYPASS8B10B0_indelay, + TXBYPASS8B10B1 => TXBYPASS8B10B1_indelay, + TXCHARDISPMODE0 => TXCHARDISPMODE0_indelay, + TXCHARDISPMODE1 => TXCHARDISPMODE1_indelay, + TXCHARDISPVAL0 => TXCHARDISPVAL0_indelay, + TXCHARDISPVAL1 => TXCHARDISPVAL1_indelay, + TXCHARISK0 => TXCHARISK0_indelay, + TXCHARISK1 => TXCHARISK1_indelay, + TXCOMSTART0 => TXCOMSTART0_indelay, + TXCOMSTART1 => TXCOMSTART1_indelay, + TXCOMTYPE0 => TXCOMTYPE0_indelay, + TXCOMTYPE1 => TXCOMTYPE1_indelay, + TXDATA0 => TXDATA0_indelay, + TXDATA1 => TXDATA1_indelay, + TXDATAWIDTH0 => TXDATAWIDTH0_indelay, + TXDATAWIDTH1 => TXDATAWIDTH1_indelay, + TXDETECTRX0 => TXDETECTRX0_indelay, + TXDETECTRX1 => TXDETECTRX1_indelay, + TXDIFFCTRL0 => TXDIFFCTRL0_indelay, + TXDIFFCTRL1 => TXDIFFCTRL1_indelay, + TXELECIDLE0 => TXELECIDLE0_indelay, + TXELECIDLE1 => TXELECIDLE1_indelay, + TXENC8B10BUSE0 => TXENC8B10BUSE0_indelay, + TXENC8B10BUSE1 => TXENC8B10BUSE1_indelay, + TXENPMAPHASEALIGN => TXENPMAPHASEALIGN_indelay, + TXENPRBSTST0 => TXENPRBSTST0_indelay, + TXENPRBSTST1 => TXENPRBSTST1_indelay, + TXINHIBIT0 => TXINHIBIT0_indelay, + TXINHIBIT1 => TXINHIBIT1_indelay, + TXPMASETPHASE => TXPMASETPHASE_indelay, + TXPOLARITY0 => TXPOLARITY0_indelay, + TXPOLARITY1 => TXPOLARITY1_indelay, + TXPOWERDOWN0 => TXPOWERDOWN0_indelay, + TXPOWERDOWN1 => TXPOWERDOWN1_indelay, + TXPREEMPHASIS0 => TXPREEMPHASIS0_indelay, + TXPREEMPHASIS1 => TXPREEMPHASIS1_indelay, + TXRESET0 => TXRESET0_indelay, + TXRESET1 => TXRESET1_indelay, + TXUSRCLK0 => TXUSRCLK0_indelay, + TXUSRCLK1 => TXUSRCLK1_indelay, + TXUSRCLK20 => TXUSRCLK20_indelay, + TXUSRCLK21 => TXUSRCLK21_indelay + ); + end generate legacy_model; + + fast_model: if SIM_MODE = "FAST" generate + gtp_dual_fast_bw_1 : GTP_DUAL_FAST_BUS + port map ( + AC_CAP_DIS_0 => AC_CAP_DIS_0_BINARY, + AC_CAP_DIS_1 => AC_CAP_DIS_1_BINARY, + ALIGN_COMMA_WORD_0 => ALIGN_COMMA_WORD_0_BINARY, + ALIGN_COMMA_WORD_1 => ALIGN_COMMA_WORD_1_BINARY, + CHAN_BOND_1_MAX_SKEW_0 => CHAN_BOND_1_MAX_SKEW_0_BINARY, + CHAN_BOND_1_MAX_SKEW_1 => CHAN_BOND_1_MAX_SKEW_1_BINARY, + CHAN_BOND_2_MAX_SKEW_0 => CHAN_BOND_2_MAX_SKEW_0_BINARY, + CHAN_BOND_2_MAX_SKEW_1 => CHAN_BOND_2_MAX_SKEW_1_BINARY, + CHAN_BOND_LEVEL_0 => CHAN_BOND_LEVEL_0_BINARY, + CHAN_BOND_LEVEL_1 => CHAN_BOND_LEVEL_1_BINARY, + CHAN_BOND_MODE_0 => CHAN_BOND_MODE_0_BINARY, + CHAN_BOND_MODE_1 => CHAN_BOND_MODE_1_BINARY, + CHAN_BOND_SEQ_1_1_0 => CHAN_BOND_SEQ_1_1_0_BINARY, + CHAN_BOND_SEQ_1_1_1 => CHAN_BOND_SEQ_1_1_1_BINARY, + CHAN_BOND_SEQ_1_2_0 => CHAN_BOND_SEQ_1_2_0_BINARY, + CHAN_BOND_SEQ_1_2_1 => CHAN_BOND_SEQ_1_2_1_BINARY, + CHAN_BOND_SEQ_1_3_0 => CHAN_BOND_SEQ_1_3_0_BINARY, + CHAN_BOND_SEQ_1_3_1 => CHAN_BOND_SEQ_1_3_1_BINARY, + CHAN_BOND_SEQ_1_4_0 => CHAN_BOND_SEQ_1_4_0_BINARY, + CHAN_BOND_SEQ_1_4_1 => CHAN_BOND_SEQ_1_4_1_BINARY, + CHAN_BOND_SEQ_1_ENABLE_0 => CHAN_BOND_SEQ_1_ENABLE_0_BINARY, + CHAN_BOND_SEQ_1_ENABLE_1 => CHAN_BOND_SEQ_1_ENABLE_1_BINARY, + CHAN_BOND_SEQ_2_1_0 => CHAN_BOND_SEQ_2_1_0_BINARY, + CHAN_BOND_SEQ_2_1_1 => CHAN_BOND_SEQ_2_1_1_BINARY, + CHAN_BOND_SEQ_2_2_0 => CHAN_BOND_SEQ_2_2_0_BINARY, + CHAN_BOND_SEQ_2_2_1 => CHAN_BOND_SEQ_2_2_1_BINARY, + CHAN_BOND_SEQ_2_3_0 => CHAN_BOND_SEQ_2_3_0_BINARY, + CHAN_BOND_SEQ_2_3_1 => CHAN_BOND_SEQ_2_3_1_BINARY, + CHAN_BOND_SEQ_2_4_0 => CHAN_BOND_SEQ_2_4_0_BINARY, + CHAN_BOND_SEQ_2_4_1 => CHAN_BOND_SEQ_2_4_1_BINARY, + CHAN_BOND_SEQ_2_ENABLE_0 => CHAN_BOND_SEQ_2_ENABLE_0_BINARY, + CHAN_BOND_SEQ_2_ENABLE_1 => CHAN_BOND_SEQ_2_ENABLE_1_BINARY, + CHAN_BOND_SEQ_2_USE_0 => CHAN_BOND_SEQ_2_USE_0_BINARY, + CHAN_BOND_SEQ_2_USE_1 => CHAN_BOND_SEQ_2_USE_1_BINARY, + CHAN_BOND_SEQ_LEN_0 => CHAN_BOND_SEQ_LEN_0_BINARY, + CHAN_BOND_SEQ_LEN_1 => CHAN_BOND_SEQ_LEN_1_BINARY, + CLK25_DIVIDER => CLK25_DIVIDER_BINARY, + CLKINDC_B => CLKINDC_B_BINARY, + CLK_CORRECT_USE_0 => CLK_CORRECT_USE_0_BINARY, + CLK_CORRECT_USE_1 => CLK_CORRECT_USE_1_BINARY, + CLK_COR_ADJ_LEN_0 => CLK_COR_ADJ_LEN_0_BINARY, + CLK_COR_ADJ_LEN_1 => CLK_COR_ADJ_LEN_1_BINARY, + CLK_COR_DET_LEN_0 => CLK_COR_DET_LEN_0_BINARY, + CLK_COR_DET_LEN_1 => CLK_COR_DET_LEN_1_BINARY, + CLK_COR_INSERT_IDLE_FLAG_0 => CLK_COR_INSERT_IDLE_FLAG_0_BINARY, + CLK_COR_INSERT_IDLE_FLAG_1 => CLK_COR_INSERT_IDLE_FLAG_1_BINARY, + CLK_COR_KEEP_IDLE_0 => CLK_COR_KEEP_IDLE_0_BINARY, + CLK_COR_KEEP_IDLE_1 => CLK_COR_KEEP_IDLE_1_BINARY, + CLK_COR_MAX_LAT_0 => CLK_COR_MAX_LAT_0_BINARY, + CLK_COR_MAX_LAT_1 => CLK_COR_MAX_LAT_1_BINARY, + CLK_COR_MIN_LAT_0 => CLK_COR_MIN_LAT_0_BINARY, + CLK_COR_MIN_LAT_1 => CLK_COR_MIN_LAT_1_BINARY, + CLK_COR_PRECEDENCE_0 => CLK_COR_PRECEDENCE_0_BINARY, + CLK_COR_PRECEDENCE_1 => CLK_COR_PRECEDENCE_1_BINARY, + CLK_COR_REPEAT_WAIT_0 => CLK_COR_REPEAT_WAIT_0_BINARY, + CLK_COR_REPEAT_WAIT_1 => CLK_COR_REPEAT_WAIT_1_BINARY, + CLK_COR_SEQ_1_1_0 => CLK_COR_SEQ_1_1_0_BINARY, + CLK_COR_SEQ_1_1_1 => CLK_COR_SEQ_1_1_1_BINARY, + CLK_COR_SEQ_1_2_0 => CLK_COR_SEQ_1_2_0_BINARY, + CLK_COR_SEQ_1_2_1 => CLK_COR_SEQ_1_2_1_BINARY, + CLK_COR_SEQ_1_3_0 => CLK_COR_SEQ_1_3_0_BINARY, + CLK_COR_SEQ_1_3_1 => CLK_COR_SEQ_1_3_1_BINARY, + CLK_COR_SEQ_1_4_0 => CLK_COR_SEQ_1_4_0_BINARY, + CLK_COR_SEQ_1_4_1 => CLK_COR_SEQ_1_4_1_BINARY, + CLK_COR_SEQ_1_ENABLE_0 => CLK_COR_SEQ_1_ENABLE_0_BINARY, + CLK_COR_SEQ_1_ENABLE_1 => CLK_COR_SEQ_1_ENABLE_1_BINARY, + CLK_COR_SEQ_2_1_0 => CLK_COR_SEQ_2_1_0_BINARY, + CLK_COR_SEQ_2_1_1 => CLK_COR_SEQ_2_1_1_BINARY, + CLK_COR_SEQ_2_2_0 => CLK_COR_SEQ_2_2_0_BINARY, + CLK_COR_SEQ_2_2_1 => CLK_COR_SEQ_2_2_1_BINARY, + CLK_COR_SEQ_2_3_0 => CLK_COR_SEQ_2_3_0_BINARY, + CLK_COR_SEQ_2_3_1 => CLK_COR_SEQ_2_3_1_BINARY, + CLK_COR_SEQ_2_4_0 => CLK_COR_SEQ_2_4_0_BINARY, + CLK_COR_SEQ_2_4_1 => CLK_COR_SEQ_2_4_1_BINARY, + CLK_COR_SEQ_2_ENABLE_0 => CLK_COR_SEQ_2_ENABLE_0_BINARY, + CLK_COR_SEQ_2_ENABLE_1 => CLK_COR_SEQ_2_ENABLE_1_BINARY, + CLK_COR_SEQ_2_USE_0 => CLK_COR_SEQ_2_USE_0_BINARY, + CLK_COR_SEQ_2_USE_1 => CLK_COR_SEQ_2_USE_1_BINARY, + COMMA_10B_ENABLE_0 => COMMA_10B_ENABLE_0_BINARY, + COMMA_10B_ENABLE_1 => COMMA_10B_ENABLE_1_BINARY, + COMMA_DOUBLE_0 => COMMA_DOUBLE_0_BINARY, + COMMA_DOUBLE_1 => COMMA_DOUBLE_1_BINARY, + COM_BURST_VAL_0 => COM_BURST_VAL_0_BINARY, + COM_BURST_VAL_1 => COM_BURST_VAL_1_BINARY, + DEC_MCOMMA_DETECT_0 => DEC_MCOMMA_DETECT_0_BINARY, + DEC_MCOMMA_DETECT_1 => DEC_MCOMMA_DETECT_1_BINARY, + DEC_PCOMMA_DETECT_0 => DEC_PCOMMA_DETECT_0_BINARY, + DEC_PCOMMA_DETECT_1 => DEC_PCOMMA_DETECT_1_BINARY, + DEC_VALID_COMMA_ONLY_0 => DEC_VALID_COMMA_ONLY_0_BINARY, + DEC_VALID_COMMA_ONLY_1 => DEC_VALID_COMMA_ONLY_1_BINARY, + MCOMMA_10B_VALUE_0 => MCOMMA_10B_VALUE_0_BINARY, + MCOMMA_10B_VALUE_1 => MCOMMA_10B_VALUE_1_BINARY, + MCOMMA_DETECT_0 => MCOMMA_DETECT_0_BINARY, + MCOMMA_DETECT_1 => MCOMMA_DETECT_1_BINARY, + OOBDETECT_THRESHOLD_0 => OOBDETECT_THRESHOLD_0_BINARY, + OOBDETECT_THRESHOLD_1 => OOBDETECT_THRESHOLD_1_BINARY, + OOB_CLK_DIVIDER => OOB_CLK_DIVIDER_BINARY, + OVERSAMPLE_MODE => OVERSAMPLE_MODE_BINARY, + PCI_EXPRESS_MODE_0 => PCI_EXPRESS_MODE_0_BINARY, + PCI_EXPRESS_MODE_1 => PCI_EXPRESS_MODE_1_BINARY, + PCOMMA_10B_VALUE_0 => PCOMMA_10B_VALUE_0_BINARY, + PCOMMA_10B_VALUE_1 => PCOMMA_10B_VALUE_1_BINARY, + PCOMMA_DETECT_0 => PCOMMA_DETECT_0_BINARY, + PCOMMA_DETECT_1 => PCOMMA_DETECT_1_BINARY, + PCS_COM_CFG => PCS_COM_CFG_BINARY, + PLL_DIVSEL_FB => PLL_DIVSEL_FB_BINARY, + PLL_DIVSEL_REF => PLL_DIVSEL_REF_BINARY, + PLL_RXDIVSEL_OUT_0 => PLL_RXDIVSEL_OUT_0_BINARY, + PLL_RXDIVSEL_OUT_1 => PLL_RXDIVSEL_OUT_1_BINARY, + PLL_SATA_0 => PLL_SATA_0_BINARY, + PLL_SATA_1 => PLL_SATA_1_BINARY, + PLL_TXDIVSEL_COMM_OUT => PLL_TXDIVSEL_COMM_OUT_BINARY, + PLL_TXDIVSEL_OUT_0 => PLL_TXDIVSEL_OUT_0_BINARY, + PLL_TXDIVSEL_OUT_1 => PLL_TXDIVSEL_OUT_1_BINARY, + PMA_CDR_SCAN_0 => PMA_CDR_SCAN_0_BINARY, + PMA_CDR_SCAN_1 => PMA_CDR_SCAN_1_BINARY, + PMA_RX_CFG_0 => PMA_RX_CFG_0_BINARY, + PMA_RX_CFG_1 => PMA_RX_CFG_1_BINARY, + PRBS_ERR_THRESHOLD_0 => PRBS_ERR_THRESHOLD_0_BINARY, + PRBS_ERR_THRESHOLD_1 => PRBS_ERR_THRESHOLD_1_BINARY, + RCV_TERM_GND_0 => RCV_TERM_GND_0_BINARY, + RCV_TERM_GND_1 => RCV_TERM_GND_1_BINARY, + RCV_TERM_MID_0 => RCV_TERM_MID_0_BINARY, + RCV_TERM_MID_1 => RCV_TERM_MID_1_BINARY, + RCV_TERM_VTTRX_0 => RCV_TERM_VTTRX_0_BINARY, + RCV_TERM_VTTRX_1 => RCV_TERM_VTTRX_1_BINARY, + RX_BUFFER_USE_0 => RX_BUFFER_USE_0_BINARY, + RX_BUFFER_USE_1 => RX_BUFFER_USE_1_BINARY, + RX_DECODE_SEQ_MATCH_0 => RX_DECODE_SEQ_MATCH_0_BINARY, + RX_DECODE_SEQ_MATCH_1 => RX_DECODE_SEQ_MATCH_1_BINARY, + RX_LOSS_OF_SYNC_FSM_0 => RX_LOSS_OF_SYNC_FSM_0_BINARY, + RX_LOSS_OF_SYNC_FSM_1 => RX_LOSS_OF_SYNC_FSM_1_BINARY, + RX_LOS_INVALID_INCR_0 => RX_LOS_INVALID_INCR_0_BINARY, + RX_LOS_INVALID_INCR_1 => RX_LOS_INVALID_INCR_1_BINARY, + RX_LOS_THRESHOLD_0 => RX_LOS_THRESHOLD_0_BINARY, + RX_LOS_THRESHOLD_1 => RX_LOS_THRESHOLD_1_BINARY, + RX_SLIDE_MODE_0 => RX_SLIDE_MODE_0_BINARY, + RX_SLIDE_MODE_1 => RX_SLIDE_MODE_1_BINARY, + RX_STATUS_FMT_0 => RX_STATUS_FMT_0_BINARY, + RX_STATUS_FMT_1 => RX_STATUS_FMT_1_BINARY, + RX_XCLK_SEL_0 => RX_XCLK_SEL_0_BINARY, + RX_XCLK_SEL_1 => RX_XCLK_SEL_1_BINARY, + SATA_BURST_VAL_0 => SATA_BURST_VAL_0_BINARY, + SATA_BURST_VAL_1 => SATA_BURST_VAL_1_BINARY, + SATA_IDLE_VAL_0 => SATA_IDLE_VAL_0_BINARY, + SATA_IDLE_VAL_1 => SATA_IDLE_VAL_1_BINARY, + SATA_MAX_BURST_0 => SATA_MAX_BURST_0_BINARY, + SATA_MAX_BURST_1 => SATA_MAX_BURST_1_BINARY, + SATA_MAX_INIT_0 => SATA_MAX_INIT_0_BINARY, + SATA_MAX_INIT_1 => SATA_MAX_INIT_1_BINARY, + SATA_MAX_WAKE_0 => SATA_MAX_WAKE_0_BINARY, + SATA_MAX_WAKE_1 => SATA_MAX_WAKE_1_BINARY, + SATA_MIN_BURST_0 => SATA_MIN_BURST_0_BINARY, + SATA_MIN_BURST_1 => SATA_MIN_BURST_1_BINARY, + SATA_MIN_INIT_0 => SATA_MIN_INIT_0_BINARY, + SATA_MIN_INIT_1 => SATA_MIN_INIT_1_BINARY, + SATA_MIN_WAKE_0 => SATA_MIN_WAKE_0_BINARY, + SATA_MIN_WAKE_1 => SATA_MIN_WAKE_1_BINARY, + SIM_GTPRESET_SPEEDUP => SIM_GTPRESET_SPEEDUP_BINARY, + SIM_PLL_PERDIV2 => SIM_PLL_PERDIV2_BINARY, + SIM_RECEIVER_DETECT_PASS0 => SIM_RECEIVER_DETECT_PASS0_BINARY, + SIM_RECEIVER_DETECT_PASS1 => SIM_RECEIVER_DETECT_PASS1_BINARY, + TERMINATION_CTRL => TERMINATION_CTRL_BINARY, + TERMINATION_IMP_0 => TERMINATION_IMP_0_BINARY, + TERMINATION_IMP_1 => TERMINATION_IMP_1_BINARY, + TERMINATION_OVRD => TERMINATION_OVRD_BINARY, + TRANS_TIME_FROM_P2_0 => TRANS_TIME_FROM_P2_0_BINARY, + TRANS_TIME_FROM_P2_1 => TRANS_TIME_FROM_P2_1_BINARY, + TRANS_TIME_NON_P2_0 => TRANS_TIME_NON_P2_0_BINARY, + TRANS_TIME_NON_P2_1 => TRANS_TIME_NON_P2_1_BINARY, + TRANS_TIME_TO_P2_0 => TRANS_TIME_TO_P2_0_BINARY, + TRANS_TIME_TO_P2_1 => TRANS_TIME_TO_P2_1_BINARY, + TXRX_INVERT_0 => TXRX_INVERT_0_BINARY, + TXRX_INVERT_1 => TXRX_INVERT_1_BINARY, + TX_BUFFER_USE_0 => TX_BUFFER_USE_0_BINARY, + TX_BUFFER_USE_1 => TX_BUFFER_USE_1_BINARY, + TX_DIFF_BOOST_0 => TX_DIFF_BOOST_0_BINARY, + TX_DIFF_BOOST_1 => TX_DIFF_BOOST_1_BINARY, + TX_SYNC_FILTERB => TX_SYNC_FILTERB_BINARY, + TX_XCLK_SEL_0 => TX_XCLK_SEL_0_BINARY, + TX_XCLK_SEL_1 => TX_XCLK_SEL_1_BINARY, + DO => DO_outdelay, + DRDY => DRDY_outdelay, + PHYSTATUS0 => PHYSTATUS0_outdelay, + PHYSTATUS1 => PHYSTATUS1_outdelay, + PLLLKDET => PLLLKDET_outdelay, + REFCLKOUT => REFCLKOUT_outdelay, + RESETDONE0 => RESETDONE0_outdelay, + RESETDONE1 => RESETDONE1_outdelay, + RXBUFSTATUS0 => RXBUFSTATUS0_outdelay, + RXBUFSTATUS1 => RXBUFSTATUS1_outdelay, + RXBYTEISALIGNED0 => RXBYTEISALIGNED0_outdelay, + RXBYTEISALIGNED1 => RXBYTEISALIGNED1_outdelay, + RXBYTEREALIGN0 => RXBYTEREALIGN0_outdelay, + RXBYTEREALIGN1 => RXBYTEREALIGN1_outdelay, + RXCHANBONDSEQ0 => RXCHANBONDSEQ0_outdelay, + RXCHANBONDSEQ1 => RXCHANBONDSEQ1_outdelay, + RXCHANISALIGNED0 => RXCHANISALIGNED0_outdelay, + RXCHANISALIGNED1 => RXCHANISALIGNED1_outdelay, + RXCHANREALIGN0 => RXCHANREALIGN0_outdelay, + RXCHANREALIGN1 => RXCHANREALIGN1_outdelay, + RXCHARISCOMMA0 => RXCHARISCOMMA0_outdelay, + RXCHARISCOMMA1 => RXCHARISCOMMA1_outdelay, + RXCHARISK0 => RXCHARISK0_outdelay, + RXCHARISK1 => RXCHARISK1_outdelay, + RXCHBONDO0 => RXCHBONDO0_outdelay, + RXCHBONDO1 => RXCHBONDO1_outdelay, + RXCLKCORCNT0 => RXCLKCORCNT0_outdelay, + RXCLKCORCNT1 => RXCLKCORCNT1_outdelay, + RXCOMMADET0 => RXCOMMADET0_outdelay, + RXCOMMADET1 => RXCOMMADET1_outdelay, + RXDATA0 => RXDATA0_outdelay, + RXDATA1 => RXDATA1_outdelay, + RXDISPERR0 => RXDISPERR0_outdelay, + RXDISPERR1 => RXDISPERR1_outdelay, + RXELECIDLE0 => RXELECIDLE0_outdelay, + RXELECIDLE1 => RXELECIDLE1_outdelay, + RXLOSSOFSYNC0 => RXLOSSOFSYNC0_outdelay, + RXLOSSOFSYNC1 => RXLOSSOFSYNC1_outdelay, + RXNOTINTABLE0 => RXNOTINTABLE0_outdelay, + RXNOTINTABLE1 => RXNOTINTABLE1_outdelay, + RXOVERSAMPLEERR0 => RXOVERSAMPLEERR0_outdelay, + RXOVERSAMPLEERR1 => RXOVERSAMPLEERR1_outdelay, + RXPRBSERR0 => RXPRBSERR0_outdelay, + RXPRBSERR1 => RXPRBSERR1_outdelay, + RXRECCLK0 => RXRECCLK0_outdelay, + RXRECCLK1 => RXRECCLK1_outdelay, + RXRUNDISP0 => RXRUNDISP0_outdelay, + RXRUNDISP1 => RXRUNDISP1_outdelay, + RXSTATUS0 => RXSTATUS0_outdelay, + RXSTATUS1 => RXSTATUS1_outdelay, + RXVALID0 => RXVALID0_outdelay, + RXVALID1 => RXVALID1_outdelay, + TXBUFSTATUS0 => TXBUFSTATUS0_outdelay, + TXBUFSTATUS1 => TXBUFSTATUS1_outdelay, + TXKERR0 => TXKERR0_outdelay, + TXKERR1 => TXKERR1_outdelay, + TXN0 => TXN0_outdelay, + TXN1 => TXN1_outdelay, + TXOUTCLK0 => TXOUTCLK0_outdelay, + TXOUTCLK1 => TXOUTCLK1_outdelay, + TXP0 => TXP0_outdelay, + TXP1 => TXP1_outdelay, + TXRUNDISP0 => TXRUNDISP0_outdelay, + TXRUNDISP1 => TXRUNDISP1_outdelay, + CLKIN => CLKIN_indelay, + DADDR => DADDR_indelay, + DCLK => DCLK_indelay, + DEN => DEN_indelay, + DI => DI_indelay, + DWE => DWE_indelay, + GSR => GSR, + GTPRESET => GTPRESET_indelay, + GTPTEST => GTPTEST_indelay, + INTDATAWIDTH => INTDATAWIDTH_indelay, + LOOPBACK0 => LOOPBACK0_indelay, + LOOPBACK1 => LOOPBACK1_indelay, + PLLLKDETEN => PLLLKDETEN_indelay, + PLLPOWERDOWN => PLLPOWERDOWN_indelay, + PRBSCNTRESET0 => PRBSCNTRESET0_indelay, + PRBSCNTRESET1 => PRBSCNTRESET1_indelay, + REFCLKPWRDNB => REFCLKPWRDNB_indelay, + RXBUFRESET0 => RXBUFRESET0_indelay, + RXBUFRESET1 => RXBUFRESET1_indelay, + RXCDRRESET0 => RXCDRRESET0_indelay, + RXCDRRESET1 => RXCDRRESET1_indelay, + RXCHBONDI0 => RXCHBONDI0_indelay, + RXCHBONDI1 => RXCHBONDI1_indelay, + RXCOMMADETUSE0 => RXCOMMADETUSE0_indelay, + RXCOMMADETUSE1 => RXCOMMADETUSE1_indelay, + RXDATAWIDTH0 => RXDATAWIDTH0_indelay, + RXDATAWIDTH1 => RXDATAWIDTH1_indelay, + RXDEC8B10BUSE0 => RXDEC8B10BUSE0_indelay, + RXDEC8B10BUSE1 => RXDEC8B10BUSE1_indelay, + RXELECIDLERESET0 => RXELECIDLERESET0_indelay, + RXELECIDLERESET1 => RXELECIDLERESET1_indelay, + RXENCHANSYNC0 => RXENCHANSYNC0_indelay, + RXENCHANSYNC1 => RXENCHANSYNC1_indelay, + RXENELECIDLERESETB => RXENELECIDLERESETB_indelay, + RXENEQB0 => RXENEQB0_indelay, + RXENEQB1 => RXENEQB1_indelay, + RXENMCOMMAALIGN0 => RXENMCOMMAALIGN0_indelay, + RXENMCOMMAALIGN1 => RXENMCOMMAALIGN1_indelay, + RXENPCOMMAALIGN0 => RXENPCOMMAALIGN0_indelay, + RXENPCOMMAALIGN1 => RXENPCOMMAALIGN1_indelay, + RXENPRBSTST0 => RXENPRBSTST0_indelay, + RXENPRBSTST1 => RXENPRBSTST1_indelay, + RXENSAMPLEALIGN0 => RXENSAMPLEALIGN0_indelay, + RXENSAMPLEALIGN1 => RXENSAMPLEALIGN1_indelay, + RXEQMIX0 => RXEQMIX0_indelay, + RXEQMIX1 => RXEQMIX1_indelay, + RXEQPOLE0 => RXEQPOLE0_indelay, + RXEQPOLE1 => RXEQPOLE1_indelay, + RXN0 => RXN0_indelay, + RXN1 => RXN1_indelay, + RXP0 => RXP0_indelay, + RXP1 => RXP1_indelay, + RXPMASETPHASE0 => RXPMASETPHASE0_indelay, + RXPMASETPHASE1 => RXPMASETPHASE1_indelay, + RXPOLARITY0 => RXPOLARITY0_indelay, + RXPOLARITY1 => RXPOLARITY1_indelay, + RXPOWERDOWN0 => RXPOWERDOWN0_indelay, + RXPOWERDOWN1 => RXPOWERDOWN1_indelay, + RXRESET0 => RXRESET0_indelay, + RXRESET1 => RXRESET1_indelay, + RXSLIDE0 => RXSLIDE0_indelay, + RXSLIDE1 => RXSLIDE1_indelay, + RXUSRCLK0 => RXUSRCLK0_indelay, + RXUSRCLK1 => RXUSRCLK1_indelay, + RXUSRCLK20 => RXUSRCLK20_indelay, + RXUSRCLK21 => RXUSRCLK21_indelay, + TXBUFDIFFCTRL0 => TXBUFDIFFCTRL0_indelay, + TXBUFDIFFCTRL1 => TXBUFDIFFCTRL1_indelay, + TXBYPASS8B10B0 => TXBYPASS8B10B0_indelay, + TXBYPASS8B10B1 => TXBYPASS8B10B1_indelay, + TXCHARDISPMODE0 => TXCHARDISPMODE0_indelay, + TXCHARDISPMODE1 => TXCHARDISPMODE1_indelay, + TXCHARDISPVAL0 => TXCHARDISPVAL0_indelay, + TXCHARDISPVAL1 => TXCHARDISPVAL1_indelay, + TXCHARISK0 => TXCHARISK0_indelay, + TXCHARISK1 => TXCHARISK1_indelay, + TXCOMSTART0 => TXCOMSTART0_indelay, + TXCOMSTART1 => TXCOMSTART1_indelay, + TXCOMTYPE0 => TXCOMTYPE0_indelay, + TXCOMTYPE1 => TXCOMTYPE1_indelay, + TXDATA0 => TXDATA0_indelay, + TXDATA1 => TXDATA1_indelay, + TXDATAWIDTH0 => TXDATAWIDTH0_indelay, + TXDATAWIDTH1 => TXDATAWIDTH1_indelay, + TXDETECTRX0 => TXDETECTRX0_indelay, + TXDETECTRX1 => TXDETECTRX1_indelay, + TXDIFFCTRL0 => TXDIFFCTRL0_indelay, + TXDIFFCTRL1 => TXDIFFCTRL1_indelay, + TXELECIDLE0 => TXELECIDLE0_indelay, + TXELECIDLE1 => TXELECIDLE1_indelay, + TXENC8B10BUSE0 => TXENC8B10BUSE0_indelay, + TXENC8B10BUSE1 => TXENC8B10BUSE1_indelay, + TXENPMAPHASEALIGN => TXENPMAPHASEALIGN_indelay, + TXENPRBSTST0 => TXENPRBSTST0_indelay, + TXENPRBSTST1 => TXENPRBSTST1_indelay, + TXINHIBIT0 => TXINHIBIT0_indelay, + TXINHIBIT1 => TXINHIBIT1_indelay, + TXPMASETPHASE => TXPMASETPHASE_indelay, + TXPOLARITY0 => TXPOLARITY0_indelay, + TXPOLARITY1 => TXPOLARITY1_indelay, + TXPOWERDOWN0 => TXPOWERDOWN0_indelay, + TXPOWERDOWN1 => TXPOWERDOWN1_indelay, + TXPREEMPHASIS0 => TXPREEMPHASIS0_indelay, + TXPREEMPHASIS1 => TXPREEMPHASIS1_indelay, + TXRESET0 => TXRESET0_indelay, + TXRESET1 => TXRESET1_indelay, + TXUSRCLK0 => TXUSRCLK0_indelay, + TXUSRCLK1 => TXUSRCLK1_indelay, + TXUSRCLK20 => TXUSRCLK20_indelay, + TXUSRCLK21 => TXUSRCLK21_indelay + ); + end generate fast_model; + + INIPROC : process + begin + case PLL_TXDIVSEL_OUT_0 is + when 1 => PLL_TXDIVSEL_OUT_0_BINARY <= "00"; + when 2 => PLL_TXDIVSEL_OUT_0_BINARY <= "01"; + when 4 => PLL_TXDIVSEL_OUT_0_BINARY <= "10"; + when others => assert FALSE report "Error : PLL_TXDIVSEL_OUT_0 is not in 1, 2, 4." severity error; + end case; + case PLL_RXDIVSEL_OUT_0 is + when 1 => PLL_RXDIVSEL_OUT_0_BINARY <= "00"; + when 2 => PLL_RXDIVSEL_OUT_0_BINARY <= "01"; + when 4 => PLL_RXDIVSEL_OUT_0_BINARY <= "10"; + when others => assert FALSE report "Error : PLL_RXDIVSEL_OUT_0 is not in 1, 2, 4." severity error; + end case; + case PLL_TXDIVSEL_OUT_1 is + when 1 => PLL_TXDIVSEL_OUT_1_BINARY <= "00"; + when 2 => PLL_TXDIVSEL_OUT_1_BINARY <= "01"; + when 4 => PLL_TXDIVSEL_OUT_1_BINARY <= "10"; + when others => assert FALSE report "Error : PLL_TXDIVSEL_OUT_1 is not in 1, 2, 4." severity error; + end case; + case PLL_RXDIVSEL_OUT_1 is + when 1 => PLL_RXDIVSEL_OUT_1_BINARY <= "00"; + when 2 => PLL_RXDIVSEL_OUT_1_BINARY <= "01"; + when 4 => PLL_RXDIVSEL_OUT_1_BINARY <= "10"; + when others => assert FALSE report "Error : PLL_RXDIVSEL_OUT_1 is not in 1, 2, 4." severity error; + end case; + case PLL_DIVSEL_FB is + when 1 => PLL_DIVSEL_FB_BINARY <= "10000"; + when 2 => PLL_DIVSEL_FB_BINARY <= "00000"; + when 3 => PLL_DIVSEL_FB_BINARY <= "00001"; + when 4 => PLL_DIVSEL_FB_BINARY <= "00010"; + when 5 => PLL_DIVSEL_FB_BINARY <= "00011"; + when 8 => PLL_DIVSEL_FB_BINARY <= "00110"; + when 10 => PLL_DIVSEL_FB_BINARY <= "00111"; + when others => assert FALSE report "Error : PLL_DIVSEL_FB is not in 1, 2, 3, 4, 5, 8, 10." severity error; + end case; + case PLL_DIVSEL_REF is + when 1 => PLL_DIVSEL_REF_BINARY <= "010000"; + when 2 => PLL_DIVSEL_REF_BINARY <= "000000"; + when 3 => PLL_DIVSEL_REF_BINARY <= "000001"; + when 4 => PLL_DIVSEL_REF_BINARY <= "000010"; + when 5 => PLL_DIVSEL_REF_BINARY <= "000011"; + when 6 => PLL_DIVSEL_REF_BINARY <= "000101"; + when 8 => PLL_DIVSEL_REF_BINARY <= "000110"; + when 10 => PLL_DIVSEL_REF_BINARY <= "000111"; + when 12 => PLL_DIVSEL_REF_BINARY <= "001101"; + when 16 => PLL_DIVSEL_REF_BINARY <= "001110"; + when 20 => PLL_DIVSEL_REF_BINARY <= "001111"; + when others => assert FALSE report "Error : PLL_DIVSEL_REF is not in 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20." severity error; + end case; + case PLL_TXDIVSEL_COMM_OUT is + when 1 => PLL_TXDIVSEL_COMM_OUT_BINARY <= "00"; + when 2 => PLL_TXDIVSEL_COMM_OUT_BINARY <= "01"; + when 4 => PLL_TXDIVSEL_COMM_OUT_BINARY <= "10"; + when others => assert FALSE report "Error : PLL_TXDIVSEL_COMM_OUT is not in 1, 2, 4." severity error; + end case; + case PLL_SATA_0 is + when FALSE => PLL_SATA_0_BINARY <= '0'; + when TRUE => PLL_SATA_0_BINARY <= '1'; + when others => assert FALSE report "Error : PLL_SATA_0 is neither TRUE nor FALSE." severity error; + end case; + case PLL_SATA_1 is + when FALSE => PLL_SATA_1_BINARY <= '0'; + when TRUE => PLL_SATA_1_BINARY <= '1'; + when others => assert FALSE report "Error : PLL_SATA_1 is neither TRUE nor FALSE." severity error; + end case; + case TX_DIFF_BOOST_0 is + when FALSE => TX_DIFF_BOOST_0_BINARY <= '0'; + when TRUE => TX_DIFF_BOOST_0_BINARY <= '1'; + when others => assert FALSE report "Error : TX_DIFF_BOOST_0 is neither TRUE nor FALSE." severity error; + end case; + case TX_DIFF_BOOST_1 is + when FALSE => TX_DIFF_BOOST_1_BINARY <= '0'; + when TRUE => TX_DIFF_BOOST_1_BINARY <= '1'; + when others => assert FALSE report "Error : TX_DIFF_BOOST_1 is neither TRUE nor FALSE." severity error; + end case; + case OOB_CLK_DIVIDER is + when 1 => OOB_CLK_DIVIDER_BINARY <= "000"; + when 2 => OOB_CLK_DIVIDER_BINARY <= "001"; + when 4 => OOB_CLK_DIVIDER_BINARY <= "010"; + when 6 => OOB_CLK_DIVIDER_BINARY <= "011"; + when 8 => OOB_CLK_DIVIDER_BINARY <= "100"; + when 10 => OOB_CLK_DIVIDER_BINARY <= "101"; + when 12 => OOB_CLK_DIVIDER_BINARY <= "110"; + when 14 => OOB_CLK_DIVIDER_BINARY <= "111"; + when others => assert FALSE report "Error : OOB_CLK_DIVIDER is not in 1, 2, 4, 6, 8, 10, 12, 14." severity error; + end case; + case TX_SYNC_FILTERB is + when 0 => TX_SYNC_FILTERB_BINARY <= '0'; + when 1 => TX_SYNC_FILTERB_BINARY <= '1'; + when others => assert FALSE report "Error : TX_SYNC_FILTERB is not in 0, 1." severity error; + end case; + case AC_CAP_DIS_0 is + when FALSE => AC_CAP_DIS_0_BINARY <= '0'; + when TRUE => AC_CAP_DIS_0_BINARY <= '1'; + when others => assert FALSE report "Error : AC_CAP_DIS_0 is neither TRUE nor FALSE." severity error; + end case; + case AC_CAP_DIS_1 is + when FALSE => AC_CAP_DIS_1_BINARY <= '0'; + when TRUE => AC_CAP_DIS_1_BINARY <= '1'; + when others => assert FALSE report "Error : AC_CAP_DIS_1 is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_GND_0 is + when FALSE => RCV_TERM_GND_0_BINARY <= '0'; + when TRUE => RCV_TERM_GND_0_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_GND_0 is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_GND_1 is + when FALSE => RCV_TERM_GND_1_BINARY <= '0'; + when TRUE => RCV_TERM_GND_1_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_GND_1 is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_MID_0 is + when FALSE => RCV_TERM_MID_0_BINARY <= '0'; + when TRUE => RCV_TERM_MID_0_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_MID_0 is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_MID_1 is + when FALSE => RCV_TERM_MID_1_BINARY <= '0'; + when TRUE => RCV_TERM_MID_1_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_MID_1 is neither TRUE nor FALSE." severity error; + end case; + case TERMINATION_IMP_0 is + when 50 => TERMINATION_IMP_0_BINARY <= '0'; + when 75 => TERMINATION_IMP_0_BINARY <= '1'; + when others => assert FALSE report "Error : TERMINATION_IMP_0 is not in 50, 75." severity error; + end case; + case TERMINATION_IMP_1 is + when 50 => TERMINATION_IMP_1_BINARY <= '0'; + when 75 => TERMINATION_IMP_1_BINARY <= '1'; + when others => assert FALSE report "Error : TERMINATION_IMP_1 is not in 50, 75." severity error; + end case; + case TERMINATION_OVRD is + when FALSE => TERMINATION_OVRD_BINARY <= '0'; + when TRUE => TERMINATION_OVRD_BINARY <= '1'; + when others => assert FALSE report "Error : TERMINATION_OVRD is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_VTTRX_0 is + when FALSE => RCV_TERM_VTTRX_0_BINARY <= '0'; + when TRUE => RCV_TERM_VTTRX_0_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_VTTRX_0 is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_VTTRX_1 is + when FALSE => RCV_TERM_VTTRX_1_BINARY <= '0'; + when TRUE => RCV_TERM_VTTRX_1_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_VTTRX_1 is neither TRUE nor FALSE." severity error; + end case; + case CLKINDC_B is + when FALSE => CLKINDC_B_BINARY <= '0'; + when TRUE => CLKINDC_B_BINARY <= '1'; + when others => assert FALSE report "Error : CLKINDC_B is neither TRUE nor FALSE." severity error; + end case; + case PCOMMA_DETECT_0 is + when FALSE => PCOMMA_DETECT_0_BINARY <= '0'; + when TRUE => PCOMMA_DETECT_0_BINARY <= '1'; + when others => assert FALSE report "Error : PCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; + end case; + case MCOMMA_DETECT_0 is + when FALSE => MCOMMA_DETECT_0_BINARY <= '0'; + when TRUE => MCOMMA_DETECT_0_BINARY <= '1'; + when others => assert FALSE report "Error : MCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; + end case; + case COMMA_DOUBLE_0 is + when FALSE => COMMA_DOUBLE_0_BINARY <= '0'; + when TRUE => COMMA_DOUBLE_0_BINARY <= '1'; + when others => assert FALSE report "Error : COMMA_DOUBLE_0 is neither TRUE nor FALSE." severity error; + end case; + case ALIGN_COMMA_WORD_0 is + when 1 => ALIGN_COMMA_WORD_0_BINARY <= '0'; + when 2 => ALIGN_COMMA_WORD_0_BINARY <= '1'; + when others => assert FALSE report "Error : ALIGN_COMMA_WORD_0 is not in 1, 2." severity error; + end case; + case DEC_PCOMMA_DETECT_0 is + when FALSE => DEC_PCOMMA_DETECT_0_BINARY <= '0'; + when TRUE => DEC_PCOMMA_DETECT_0_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_PCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; + end case; + case DEC_MCOMMA_DETECT_0 is + when FALSE => DEC_MCOMMA_DETECT_0_BINARY <= '0'; + when TRUE => DEC_MCOMMA_DETECT_0_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_MCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; + end case; + case DEC_VALID_COMMA_ONLY_0 is + when FALSE => DEC_VALID_COMMA_ONLY_0_BINARY <= '0'; + when TRUE => DEC_VALID_COMMA_ONLY_0_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_VALID_COMMA_ONLY_0 is neither TRUE nor FALSE." severity error; + end case; + case PCOMMA_DETECT_1 is + when FALSE => PCOMMA_DETECT_1_BINARY <= '0'; + when TRUE => PCOMMA_DETECT_1_BINARY <= '1'; + when others => assert FALSE report "Error : PCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; + end case; + case MCOMMA_DETECT_1 is + when FALSE => MCOMMA_DETECT_1_BINARY <= '0'; + when TRUE => MCOMMA_DETECT_1_BINARY <= '1'; + when others => assert FALSE report "Error : MCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; + end case; + case COMMA_DOUBLE_1 is + when FALSE => COMMA_DOUBLE_1_BINARY <= '0'; + when TRUE => COMMA_DOUBLE_1_BINARY <= '1'; + when others => assert FALSE report "Error : COMMA_DOUBLE_1 is neither TRUE nor FALSE." severity error; + end case; + case ALIGN_COMMA_WORD_1 is + when 1 => ALIGN_COMMA_WORD_1_BINARY <= '0'; + when 2 => ALIGN_COMMA_WORD_1_BINARY <= '1'; + when others => assert FALSE report "Error : ALIGN_COMMA_WORD_1 is not in 1, 2." severity error; + end case; + case DEC_PCOMMA_DETECT_1 is + when FALSE => DEC_PCOMMA_DETECT_1_BINARY <= '0'; + when TRUE => DEC_PCOMMA_DETECT_1_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_PCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; + end case; + case DEC_MCOMMA_DETECT_1 is + when FALSE => DEC_MCOMMA_DETECT_1_BINARY <= '0'; + when TRUE => DEC_MCOMMA_DETECT_1_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_MCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; + end case; + case DEC_VALID_COMMA_ONLY_1 is + when FALSE => DEC_VALID_COMMA_ONLY_1_BINARY <= '0'; + when TRUE => DEC_VALID_COMMA_ONLY_1_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_VALID_COMMA_ONLY_1 is neither TRUE nor FALSE." severity error; + end case; + case RX_LOSS_OF_SYNC_FSM_0 is + when FALSE => RX_LOSS_OF_SYNC_FSM_0_BINARY <= '0'; + when TRUE => RX_LOSS_OF_SYNC_FSM_0_BINARY <= '1'; + when others => assert FALSE report "Error : RX_LOSS_OF_SYNC_FSM_0 is neither TRUE nor FALSE." severity error; + end case; + case RX_LOS_INVALID_INCR_0 is + when 1 => RX_LOS_INVALID_INCR_0_BINARY <= "000"; + when 2 => RX_LOS_INVALID_INCR_0_BINARY <= "001"; + when 4 => RX_LOS_INVALID_INCR_0_BINARY <= "010"; + when 8 => RX_LOS_INVALID_INCR_0_BINARY <= "011"; + when 16 => RX_LOS_INVALID_INCR_0_BINARY <= "100"; + when 32 => RX_LOS_INVALID_INCR_0_BINARY <= "101"; + when 64 => RX_LOS_INVALID_INCR_0_BINARY <= "110"; + when 128 => RX_LOS_INVALID_INCR_0_BINARY <= "111"; + when others => assert FALSE report "Error : RX_LOS_INVALID_INCR_0 is not in 1, 2, 4, 8, 16, 32, 64, 128." severity error; + end case; + case RX_LOS_THRESHOLD_0 is + when 4 => RX_LOS_THRESHOLD_0_BINARY <= "000"; + when 8 => RX_LOS_THRESHOLD_0_BINARY <= "001"; + when 16 => RX_LOS_THRESHOLD_0_BINARY <= "010"; + when 32 => RX_LOS_THRESHOLD_0_BINARY <= "011"; + when 64 => RX_LOS_THRESHOLD_0_BINARY <= "100"; + when 128 => RX_LOS_THRESHOLD_0_BINARY <= "101"; + when 256 => RX_LOS_THRESHOLD_0_BINARY <= "110"; + when 512 => RX_LOS_THRESHOLD_0_BINARY <= "111"; + when others => assert FALSE report "Error : RX_LOS_THRESHOLD_0 is not in 4, 8, 16, 32, 64, 128, 256, 512." severity error; + end case; + case RX_LOSS_OF_SYNC_FSM_1 is + when FALSE => RX_LOSS_OF_SYNC_FSM_1_BINARY <= '0'; + when TRUE => RX_LOSS_OF_SYNC_FSM_1_BINARY <= '1'; + when others => assert FALSE report "Error : RX_LOSS_OF_SYNC_FSM_1 is neither TRUE nor FALSE." severity error; + end case; + case RX_LOS_INVALID_INCR_1 is + when 1 => RX_LOS_INVALID_INCR_1_BINARY <= "000"; + when 2 => RX_LOS_INVALID_INCR_1_BINARY <= "001"; + when 4 => RX_LOS_INVALID_INCR_1_BINARY <= "010"; + when 8 => RX_LOS_INVALID_INCR_1_BINARY <= "011"; + when 16 => RX_LOS_INVALID_INCR_1_BINARY <= "100"; + when 32 => RX_LOS_INVALID_INCR_1_BINARY <= "101"; + when 64 => RX_LOS_INVALID_INCR_1_BINARY <= "110"; + when 128 => RX_LOS_INVALID_INCR_1_BINARY <= "111"; + when others => assert FALSE report "Error : RX_LOS_INVALID_INCR_1 is not in 1, 2, 4, 8, 16, 32, 64, 128." severity error; + end case; + case RX_LOS_THRESHOLD_1 is + when 4 => RX_LOS_THRESHOLD_1_BINARY <= "000"; + when 8 => RX_LOS_THRESHOLD_1_BINARY <= "001"; + when 16 => RX_LOS_THRESHOLD_1_BINARY <= "010"; + when 32 => RX_LOS_THRESHOLD_1_BINARY <= "011"; + when 64 => RX_LOS_THRESHOLD_1_BINARY <= "100"; + when 128 => RX_LOS_THRESHOLD_1_BINARY <= "101"; + when 256 => RX_LOS_THRESHOLD_1_BINARY <= "110"; + when 512 => RX_LOS_THRESHOLD_1_BINARY <= "111"; + when others => assert FALSE report "Error : RX_LOS_THRESHOLD_1 is not in 4, 8, 16, 32, 64, 128, 256, 512." severity error; + end case; + case RX_BUFFER_USE_0 is + when FALSE => RX_BUFFER_USE_0_BINARY <= '0'; + when TRUE => RX_BUFFER_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : RX_BUFFER_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case RX_DECODE_SEQ_MATCH_0 is + when FALSE => RX_DECODE_SEQ_MATCH_0_BINARY <= '0'; + when TRUE => RX_DECODE_SEQ_MATCH_0_BINARY <= '1'; + when others => assert FALSE report "Error : RX_DECODE_SEQ_MATCH_0 is neither TRUE nor FALSE." severity error; + end case; + case RX_BUFFER_USE_1 is + when FALSE => RX_BUFFER_USE_1_BINARY <= '0'; + when TRUE => RX_BUFFER_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : RX_BUFFER_USE_1 is neither TRUE nor FALSE." severity error; + end case; + case RX_DECODE_SEQ_MATCH_1 is + when FALSE => RX_DECODE_SEQ_MATCH_1_BINARY <= '0'; + when TRUE => RX_DECODE_SEQ_MATCH_1_BINARY <= '1'; + when others => assert FALSE report "Error : RX_DECODE_SEQ_MATCH_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_MIN_LAT_0 is + when 3 => CLK_COR_MIN_LAT_0_BINARY <= "000011"; + when 4 => CLK_COR_MIN_LAT_0_BINARY <= "000100"; + when 5 => CLK_COR_MIN_LAT_0_BINARY <= "000101"; + when 6 => CLK_COR_MIN_LAT_0_BINARY <= "000110"; + when 7 => CLK_COR_MIN_LAT_0_BINARY <= "000111"; + when 8 => CLK_COR_MIN_LAT_0_BINARY <= "001000"; + when 9 => CLK_COR_MIN_LAT_0_BINARY <= "001001"; + when 10 => CLK_COR_MIN_LAT_0_BINARY <= "001010"; + when 11 => CLK_COR_MIN_LAT_0_BINARY <= "001011"; + when 12 => CLK_COR_MIN_LAT_0_BINARY <= "001100"; + when 13 => CLK_COR_MIN_LAT_0_BINARY <= "001101"; + when 14 => CLK_COR_MIN_LAT_0_BINARY <= "001110"; + when 15 => CLK_COR_MIN_LAT_0_BINARY <= "001111"; + when 16 => CLK_COR_MIN_LAT_0_BINARY <= "010000"; + when 17 => CLK_COR_MIN_LAT_0_BINARY <= "010001"; + when 18 => CLK_COR_MIN_LAT_0_BINARY <= "010010"; + when 19 => CLK_COR_MIN_LAT_0_BINARY <= "010011"; + when 20 => CLK_COR_MIN_LAT_0_BINARY <= "010100"; + when 21 => CLK_COR_MIN_LAT_0_BINARY <= "010101"; + when 22 => CLK_COR_MIN_LAT_0_BINARY <= "010110"; + when 23 => CLK_COR_MIN_LAT_0_BINARY <= "010111"; + when 24 => CLK_COR_MIN_LAT_0_BINARY <= "011000"; + when 25 => CLK_COR_MIN_LAT_0_BINARY <= "011001"; + when 26 => CLK_COR_MIN_LAT_0_BINARY <= "011010"; + when 27 => CLK_COR_MIN_LAT_0_BINARY <= "011011"; + when 28 => CLK_COR_MIN_LAT_0_BINARY <= "011100"; + when 29 => CLK_COR_MIN_LAT_0_BINARY <= "011101"; + when 30 => CLK_COR_MIN_LAT_0_BINARY <= "011110"; + when 31 => CLK_COR_MIN_LAT_0_BINARY <= "011111"; + when 32 => CLK_COR_MIN_LAT_0_BINARY <= "100000"; + when 33 => CLK_COR_MIN_LAT_0_BINARY <= "100001"; + when 34 => CLK_COR_MIN_LAT_0_BINARY <= "100010"; + when 35 => CLK_COR_MIN_LAT_0_BINARY <= "100011"; + when 36 => CLK_COR_MIN_LAT_0_BINARY <= "100100"; + when 37 => CLK_COR_MIN_LAT_0_BINARY <= "100101"; + when 38 => CLK_COR_MIN_LAT_0_BINARY <= "100110"; + when 39 => CLK_COR_MIN_LAT_0_BINARY <= "100111"; + when 40 => CLK_COR_MIN_LAT_0_BINARY <= "101000"; + when 41 => CLK_COR_MIN_LAT_0_BINARY <= "101001"; + when 42 => CLK_COR_MIN_LAT_0_BINARY <= "101010"; + when 43 => CLK_COR_MIN_LAT_0_BINARY <= "101011"; + when 44 => CLK_COR_MIN_LAT_0_BINARY <= "101100"; + when 45 => CLK_COR_MIN_LAT_0_BINARY <= "101101"; + when 46 => CLK_COR_MIN_LAT_0_BINARY <= "101110"; + when 47 => CLK_COR_MIN_LAT_0_BINARY <= "101111"; + when 48 => CLK_COR_MIN_LAT_0_BINARY <= "110000"; + when others => assert FALSE report "Error : CLK_COR_MIN_LAT_0 is not in range 3...48." severity error; + end case; + case CLK_COR_MAX_LAT_0 is + when 3 => CLK_COR_MAX_LAT_0_BINARY <= "000011"; + when 4 => CLK_COR_MAX_LAT_0_BINARY <= "000100"; + when 5 => CLK_COR_MAX_LAT_0_BINARY <= "000101"; + when 6 => CLK_COR_MAX_LAT_0_BINARY <= "000110"; + when 7 => CLK_COR_MAX_LAT_0_BINARY <= "000111"; + when 8 => CLK_COR_MAX_LAT_0_BINARY <= "001000"; + when 9 => CLK_COR_MAX_LAT_0_BINARY <= "001001"; + when 10 => CLK_COR_MAX_LAT_0_BINARY <= "001010"; + when 11 => CLK_COR_MAX_LAT_0_BINARY <= "001011"; + when 12 => CLK_COR_MAX_LAT_0_BINARY <= "001100"; + when 13 => CLK_COR_MAX_LAT_0_BINARY <= "001101"; + when 14 => CLK_COR_MAX_LAT_0_BINARY <= "001110"; + when 15 => CLK_COR_MAX_LAT_0_BINARY <= "001111"; + when 16 => CLK_COR_MAX_LAT_0_BINARY <= "010000"; + when 17 => CLK_COR_MAX_LAT_0_BINARY <= "010001"; + when 18 => CLK_COR_MAX_LAT_0_BINARY <= "010010"; + when 19 => CLK_COR_MAX_LAT_0_BINARY <= "010011"; + when 20 => CLK_COR_MAX_LAT_0_BINARY <= "010100"; + when 21 => CLK_COR_MAX_LAT_0_BINARY <= "010101"; + when 22 => CLK_COR_MAX_LAT_0_BINARY <= "010110"; + when 23 => CLK_COR_MAX_LAT_0_BINARY <= "010111"; + when 24 => CLK_COR_MAX_LAT_0_BINARY <= "011000"; + when 25 => CLK_COR_MAX_LAT_0_BINARY <= "011001"; + when 26 => CLK_COR_MAX_LAT_0_BINARY <= "011010"; + when 27 => CLK_COR_MAX_LAT_0_BINARY <= "011011"; + when 28 => CLK_COR_MAX_LAT_0_BINARY <= "011100"; + when 29 => CLK_COR_MAX_LAT_0_BINARY <= "011101"; + when 30 => CLK_COR_MAX_LAT_0_BINARY <= "011110"; + when 31 => CLK_COR_MAX_LAT_0_BINARY <= "011111"; + when 32 => CLK_COR_MAX_LAT_0_BINARY <= "100000"; + when 33 => CLK_COR_MAX_LAT_0_BINARY <= "100001"; + when 34 => CLK_COR_MAX_LAT_0_BINARY <= "100010"; + when 35 => CLK_COR_MAX_LAT_0_BINARY <= "100011"; + when 36 => CLK_COR_MAX_LAT_0_BINARY <= "100100"; + when 37 => CLK_COR_MAX_LAT_0_BINARY <= "100101"; + when 38 => CLK_COR_MAX_LAT_0_BINARY <= "100110"; + when 39 => CLK_COR_MAX_LAT_0_BINARY <= "100111"; + when 40 => CLK_COR_MAX_LAT_0_BINARY <= "101000"; + when 41 => CLK_COR_MAX_LAT_0_BINARY <= "101001"; + when 42 => CLK_COR_MAX_LAT_0_BINARY <= "101010"; + when 43 => CLK_COR_MAX_LAT_0_BINARY <= "101011"; + when 44 => CLK_COR_MAX_LAT_0_BINARY <= "101100"; + when 45 => CLK_COR_MAX_LAT_0_BINARY <= "101101"; + when 46 => CLK_COR_MAX_LAT_0_BINARY <= "101110"; + when 47 => CLK_COR_MAX_LAT_0_BINARY <= "101111"; + when 48 => CLK_COR_MAX_LAT_0_BINARY <= "110000"; + when others => assert FALSE report "Error : CLK_COR_MAX_LAT_0 is not in range 3...48." severity error; + end case; + case CLK_CORRECT_USE_0 is + when FALSE => CLK_CORRECT_USE_0_BINARY <= '0'; + when TRUE => CLK_CORRECT_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_CORRECT_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_PRECEDENCE_0 is + when FALSE => CLK_COR_PRECEDENCE_0_BINARY <= '0'; + when TRUE => CLK_COR_PRECEDENCE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_PRECEDENCE_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_DET_LEN_0 is + when 1 => CLK_COR_DET_LEN_0_BINARY <= "00"; + when 2 => CLK_COR_DET_LEN_0_BINARY <= "01"; + when 3 => CLK_COR_DET_LEN_0_BINARY <= "10"; + when 4 => CLK_COR_DET_LEN_0_BINARY <= "11"; + when others => assert FALSE report "Error : CLK_COR_DET_LEN_0 is not in 1, 2, 3, 4." severity error; + end case; + case CLK_COR_ADJ_LEN_0 is + when 1 => CLK_COR_ADJ_LEN_0_BINARY <= "00"; + when 2 => CLK_COR_ADJ_LEN_0_BINARY <= "01"; + when 3 => CLK_COR_ADJ_LEN_0_BINARY <= "10"; + when 4 => CLK_COR_ADJ_LEN_0_BINARY <= "11"; + when others => assert FALSE report "Error : CLK_COR_ADJ_LEN_0 is not in 1, 2, 3, 4." severity error; + end case; + case CLK_COR_KEEP_IDLE_0 is + when FALSE => CLK_COR_KEEP_IDLE_0_BINARY <= '0'; + when TRUE => CLK_COR_KEEP_IDLE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_KEEP_IDLE_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_INSERT_IDLE_FLAG_0 is + when FALSE => CLK_COR_INSERT_IDLE_FLAG_0_BINARY <= '0'; + when TRUE => CLK_COR_INSERT_IDLE_FLAG_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_INSERT_IDLE_FLAG_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_REPEAT_WAIT_0 is + when 0 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00000"; + when 1 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00001"; + when 2 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00010"; + when 3 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00011"; + when 4 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00100"; + when 5 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00101"; + when 6 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00110"; + when 7 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00111"; + when 8 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01000"; + when 9 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01001"; + when 10 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01010"; + when 11 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01011"; + when 12 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01100"; + when 13 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01101"; + when 14 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01110"; + when 15 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01111"; + when 16 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10000"; + when 17 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10001"; + when 18 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10010"; + when 19 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10011"; + when 20 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10100"; + when 21 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10101"; + when 22 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10110"; + when 23 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10111"; + when 24 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11000"; + when 25 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11001"; + when 26 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11010"; + when 27 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11011"; + when 28 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11100"; + when 29 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11101"; + when 30 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11110"; + when 31 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11111"; + when others => assert FALSE report "Error : CLK_COR_REPEAT_WAIT_0 is not in range 0...31." severity error; + end case; + case CLK_COR_SEQ_2_USE_0 is + when FALSE => CLK_COR_SEQ_2_USE_0_BINARY <= '0'; + when TRUE => CLK_COR_SEQ_2_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_SEQ_2_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_MIN_LAT_1 is + when 3 => CLK_COR_MIN_LAT_1_BINARY <= "000011"; + when 4 => CLK_COR_MIN_LAT_1_BINARY <= "000100"; + when 5 => CLK_COR_MIN_LAT_1_BINARY <= "000101"; + when 6 => CLK_COR_MIN_LAT_1_BINARY <= "000110"; + when 7 => CLK_COR_MIN_LAT_1_BINARY <= "000111"; + when 8 => CLK_COR_MIN_LAT_1_BINARY <= "001000"; + when 9 => CLK_COR_MIN_LAT_1_BINARY <= "001001"; + when 10 => CLK_COR_MIN_LAT_1_BINARY <= "001010"; + when 11 => CLK_COR_MIN_LAT_1_BINARY <= "001011"; + when 12 => CLK_COR_MIN_LAT_1_BINARY <= "001100"; + when 13 => CLK_COR_MIN_LAT_1_BINARY <= "001101"; + when 14 => CLK_COR_MIN_LAT_1_BINARY <= "001110"; + when 15 => CLK_COR_MIN_LAT_1_BINARY <= "001111"; + when 16 => CLK_COR_MIN_LAT_1_BINARY <= "010000"; + when 17 => CLK_COR_MIN_LAT_1_BINARY <= "010001"; + when 18 => CLK_COR_MIN_LAT_1_BINARY <= "010010"; + when 19 => CLK_COR_MIN_LAT_1_BINARY <= "010011"; + when 20 => CLK_COR_MIN_LAT_1_BINARY <= "010100"; + when 21 => CLK_COR_MIN_LAT_1_BINARY <= "010101"; + when 22 => CLK_COR_MIN_LAT_1_BINARY <= "010110"; + when 23 => CLK_COR_MIN_LAT_1_BINARY <= "010111"; + when 24 => CLK_COR_MIN_LAT_1_BINARY <= "011000"; + when 25 => CLK_COR_MIN_LAT_1_BINARY <= "011001"; + when 26 => CLK_COR_MIN_LAT_1_BINARY <= "011010"; + when 27 => CLK_COR_MIN_LAT_1_BINARY <= "011011"; + when 28 => CLK_COR_MIN_LAT_1_BINARY <= "011100"; + when 29 => CLK_COR_MIN_LAT_1_BINARY <= "011101"; + when 30 => CLK_COR_MIN_LAT_1_BINARY <= "011110"; + when 31 => CLK_COR_MIN_LAT_1_BINARY <= "011111"; + when 32 => CLK_COR_MIN_LAT_1_BINARY <= "100000"; + when 33 => CLK_COR_MIN_LAT_1_BINARY <= "100001"; + when 34 => CLK_COR_MIN_LAT_1_BINARY <= "100010"; + when 35 => CLK_COR_MIN_LAT_1_BINARY <= "100011"; + when 36 => CLK_COR_MIN_LAT_1_BINARY <= "100100"; + when 37 => CLK_COR_MIN_LAT_1_BINARY <= "100101"; + when 38 => CLK_COR_MIN_LAT_1_BINARY <= "100110"; + when 39 => CLK_COR_MIN_LAT_1_BINARY <= "100111"; + when 40 => CLK_COR_MIN_LAT_1_BINARY <= "101000"; + when 41 => CLK_COR_MIN_LAT_1_BINARY <= "101001"; + when 42 => CLK_COR_MIN_LAT_1_BINARY <= "101010"; + when 43 => CLK_COR_MIN_LAT_1_BINARY <= "101011"; + when 44 => CLK_COR_MIN_LAT_1_BINARY <= "101100"; + when 45 => CLK_COR_MIN_LAT_1_BINARY <= "101101"; + when 46 => CLK_COR_MIN_LAT_1_BINARY <= "101110"; + when 47 => CLK_COR_MIN_LAT_1_BINARY <= "101111"; + when 48 => CLK_COR_MIN_LAT_1_BINARY <= "110000"; + when others => assert FALSE report "Error : CLK_COR_MIN_LAT_1 is not in range 3...48." severity error; + end case; + case CLK_COR_MAX_LAT_1 is + when 3 => CLK_COR_MAX_LAT_1_BINARY <= "000011"; + when 4 => CLK_COR_MAX_LAT_1_BINARY <= "000100"; + when 5 => CLK_COR_MAX_LAT_1_BINARY <= "000101"; + when 6 => CLK_COR_MAX_LAT_1_BINARY <= "000110"; + when 7 => CLK_COR_MAX_LAT_1_BINARY <= "000111"; + when 8 => CLK_COR_MAX_LAT_1_BINARY <= "001000"; + when 9 => CLK_COR_MAX_LAT_1_BINARY <= "001001"; + when 10 => CLK_COR_MAX_LAT_1_BINARY <= "001010"; + when 11 => CLK_COR_MAX_LAT_1_BINARY <= "001011"; + when 12 => CLK_COR_MAX_LAT_1_BINARY <= "001100"; + when 13 => CLK_COR_MAX_LAT_1_BINARY <= "001101"; + when 14 => CLK_COR_MAX_LAT_1_BINARY <= "001110"; + when 15 => CLK_COR_MAX_LAT_1_BINARY <= "001111"; + when 16 => CLK_COR_MAX_LAT_1_BINARY <= "010000"; + when 17 => CLK_COR_MAX_LAT_1_BINARY <= "010001"; + when 18 => CLK_COR_MAX_LAT_1_BINARY <= "010010"; + when 19 => CLK_COR_MAX_LAT_1_BINARY <= "010011"; + when 20 => CLK_COR_MAX_LAT_1_BINARY <= "010100"; + when 21 => CLK_COR_MAX_LAT_1_BINARY <= "010101"; + when 22 => CLK_COR_MAX_LAT_1_BINARY <= "010110"; + when 23 => CLK_COR_MAX_LAT_1_BINARY <= "010111"; + when 24 => CLK_COR_MAX_LAT_1_BINARY <= "011000"; + when 25 => CLK_COR_MAX_LAT_1_BINARY <= "011001"; + when 26 => CLK_COR_MAX_LAT_1_BINARY <= "011010"; + when 27 => CLK_COR_MAX_LAT_1_BINARY <= "011011"; + when 28 => CLK_COR_MAX_LAT_1_BINARY <= "011100"; + when 29 => CLK_COR_MAX_LAT_1_BINARY <= "011101"; + when 30 => CLK_COR_MAX_LAT_1_BINARY <= "011110"; + when 31 => CLK_COR_MAX_LAT_1_BINARY <= "011111"; + when 32 => CLK_COR_MAX_LAT_1_BINARY <= "100000"; + when 33 => CLK_COR_MAX_LAT_1_BINARY <= "100001"; + when 34 => CLK_COR_MAX_LAT_1_BINARY <= "100010"; + when 35 => CLK_COR_MAX_LAT_1_BINARY <= "100011"; + when 36 => CLK_COR_MAX_LAT_1_BINARY <= "100100"; + when 37 => CLK_COR_MAX_LAT_1_BINARY <= "100101"; + when 38 => CLK_COR_MAX_LAT_1_BINARY <= "100110"; + when 39 => CLK_COR_MAX_LAT_1_BINARY <= "100111"; + when 40 => CLK_COR_MAX_LAT_1_BINARY <= "101000"; + when 41 => CLK_COR_MAX_LAT_1_BINARY <= "101001"; + when 42 => CLK_COR_MAX_LAT_1_BINARY <= "101010"; + when 43 => CLK_COR_MAX_LAT_1_BINARY <= "101011"; + when 44 => CLK_COR_MAX_LAT_1_BINARY <= "101100"; + when 45 => CLK_COR_MAX_LAT_1_BINARY <= "101101"; + when 46 => CLK_COR_MAX_LAT_1_BINARY <= "101110"; + when 47 => CLK_COR_MAX_LAT_1_BINARY <= "101111"; + when 48 => CLK_COR_MAX_LAT_1_BINARY <= "110000"; + when others => assert FALSE report "Error : CLK_COR_MAX_LAT_1 is not in range 3...48." severity error; + end case; + case CLK_CORRECT_USE_1 is + when FALSE => CLK_CORRECT_USE_1_BINARY <= '0'; + when TRUE => CLK_CORRECT_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_CORRECT_USE_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_PRECEDENCE_1 is + when FALSE => CLK_COR_PRECEDENCE_1_BINARY <= '0'; + when TRUE => CLK_COR_PRECEDENCE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_PRECEDENCE_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_DET_LEN_1 is + when 1 => CLK_COR_DET_LEN_1_BINARY <= "00"; + when 2 => CLK_COR_DET_LEN_1_BINARY <= "01"; + when 3 => CLK_COR_DET_LEN_1_BINARY <= "10"; + when 4 => CLK_COR_DET_LEN_1_BINARY <= "11"; + when others => assert FALSE report "Error : CLK_COR_DET_LEN_1 is not in 1, 2, 3, 4." severity error; + end case; + case CLK_COR_ADJ_LEN_1 is + when 1 => CLK_COR_ADJ_LEN_1_BINARY <= "00"; + when 2 => CLK_COR_ADJ_LEN_1_BINARY <= "01"; + when 3 => CLK_COR_ADJ_LEN_1_BINARY <= "10"; + when 4 => CLK_COR_ADJ_LEN_1_BINARY <= "11"; + when others => assert FALSE report "Error : CLK_COR_ADJ_LEN_1 is not in 1, 2, 3, 4." severity error; + end case; + case CLK_COR_KEEP_IDLE_1 is + when FALSE => CLK_COR_KEEP_IDLE_1_BINARY <= '0'; + when TRUE => CLK_COR_KEEP_IDLE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_KEEP_IDLE_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_INSERT_IDLE_FLAG_1 is + when FALSE => CLK_COR_INSERT_IDLE_FLAG_1_BINARY <= '0'; + when TRUE => CLK_COR_INSERT_IDLE_FLAG_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_INSERT_IDLE_FLAG_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_REPEAT_WAIT_1 is + when 0 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00000"; + when 1 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00001"; + when 2 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00010"; + when 3 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00011"; + when 4 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00100"; + when 5 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00101"; + when 6 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00110"; + when 7 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00111"; + when 8 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01000"; + when 9 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01001"; + when 10 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01010"; + when 11 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01011"; + when 12 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01100"; + when 13 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01101"; + when 14 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01110"; + when 15 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01111"; + when 16 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10000"; + when 17 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10001"; + when 18 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10010"; + when 19 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10011"; + when 20 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10100"; + when 21 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10101"; + when 22 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10110"; + when 23 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10111"; + when 24 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11000"; + when 25 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11001"; + when 26 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11010"; + when 27 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11011"; + when 28 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11100"; + when 29 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11101"; + when 30 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11110"; + when 31 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11111"; + when others => assert FALSE report "Error : CLK_COR_REPEAT_WAIT_1 is not in range 0...31." severity error; + end case; + case CLK_COR_SEQ_2_USE_1 is + when FALSE => CLK_COR_SEQ_2_USE_1_BINARY <= '0'; + when TRUE => CLK_COR_SEQ_2_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_SEQ_2_USE_1 is neither TRUE nor FALSE." severity error; + end case; +-- case CHAN_BOND_MODE_0 is + if((CHAN_BOND_MODE_0 = "OFF") or (CHAN_BOND_MODE_0 = "off")) then + CHAN_BOND_MODE_0_BINARY <= "00"; + elsif((CHAN_BOND_MODE_0 = "MASTER") or (CHAN_BOND_MODE_0 = "master")) then + CHAN_BOND_MODE_0_BINARY <= "01"; + elsif((CHAN_BOND_MODE_0 = "SLAVE") or (CHAN_BOND_MODE_0 = "slave")) then + CHAN_BOND_MODE_0_BINARY <= "10"; + else + assert FALSE report "Error : CHAN_BOND_MODE_0 = is not OFF, MASTER, SLAVE." severity error; + end if; +-- end case; + case CHAN_BOND_LEVEL_0 is + when 0 => CHAN_BOND_LEVEL_0_BINARY <= "000"; + when 1 => CHAN_BOND_LEVEL_0_BINARY <= "001"; + when 2 => CHAN_BOND_LEVEL_0_BINARY <= "010"; + when 3 => CHAN_BOND_LEVEL_0_BINARY <= "011"; + when 4 => CHAN_BOND_LEVEL_0_BINARY <= "100"; + when 5 => CHAN_BOND_LEVEL_0_BINARY <= "101"; + when 6 => CHAN_BOND_LEVEL_0_BINARY <= "110"; + when 7 => CHAN_BOND_LEVEL_0_BINARY <= "111"; + when others => assert FALSE report "Error : CHAN_BOND_LEVEL_0 is not in range 0...7." severity error; + end case; + case CHAN_BOND_SEQ_LEN_0 is + when 1 => CHAN_BOND_SEQ_LEN_0_BINARY <= "00"; + when 2 => CHAN_BOND_SEQ_LEN_0_BINARY <= "01"; + when 3 => CHAN_BOND_SEQ_LEN_0_BINARY <= "10"; + when 4 => CHAN_BOND_SEQ_LEN_0_BINARY <= "11"; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_LEN_0 is not in 1, 2, 3, 4." severity error; + end case; + case CHAN_BOND_SEQ_2_USE_0 is + when FALSE => CHAN_BOND_SEQ_2_USE_0_BINARY <= '0'; + when TRUE => CHAN_BOND_SEQ_2_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_2_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case CHAN_BOND_1_MAX_SKEW_0 is + when 1 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0001"; + when 2 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0010"; + when 3 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0011"; + when 4 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0100"; + when 5 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0101"; + when 6 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0110"; + when 7 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0111"; + when 8 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1000"; + when 9 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1001"; + when 10 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1010"; + when 11 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1011"; + when 12 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1100"; + when 13 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1101"; + when 14 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1110"; + when others => assert FALSE report "Error : CHAN_BOND_1_MAX_SKEW_0 is not in range 1...14." severity error; + end case; + case CHAN_BOND_2_MAX_SKEW_0 is + when 1 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0001"; + when 2 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0010"; + when 3 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0011"; + when 4 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0100"; + when 5 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0101"; + when 6 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0110"; + when 7 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0111"; + when 8 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1000"; + when 9 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1001"; + when 10 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1010"; + when 11 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1011"; + when 12 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1100"; + when 13 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1101"; + when 14 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1110"; + when others => assert FALSE report "Error : CHAN_BOND_2_MAX_SKEW_0 is not in range 1...14." severity error; + end case; +-- case CHAN_BOND_MODE_1 is + if((CHAN_BOND_MODE_1 = "OFF") or (CHAN_BOND_MODE_1 = "off")) then + CHAN_BOND_MODE_1_BINARY <= "00"; + elsif((CHAN_BOND_MODE_1 = "MASTER") or (CHAN_BOND_MODE_1 = "master")) then + CHAN_BOND_MODE_1_BINARY <= "01"; + elsif((CHAN_BOND_MODE_1 = "SLAVE") or (CHAN_BOND_MODE_1 = "slave")) then + CHAN_BOND_MODE_1_BINARY <= "10"; + else + assert FALSE report "Error : CHAN_BOND_MODE_1 = is not OFF, MASTER, SLAVE." severity error; + end if; +-- end case; + case CHAN_BOND_LEVEL_1 is + when 0 => CHAN_BOND_LEVEL_1_BINARY <= "000"; + when 1 => CHAN_BOND_LEVEL_1_BINARY <= "001"; + when 2 => CHAN_BOND_LEVEL_1_BINARY <= "010"; + when 3 => CHAN_BOND_LEVEL_1_BINARY <= "011"; + when 4 => CHAN_BOND_LEVEL_1_BINARY <= "100"; + when 5 => CHAN_BOND_LEVEL_1_BINARY <= "101"; + when 6 => CHAN_BOND_LEVEL_1_BINARY <= "110"; + when 7 => CHAN_BOND_LEVEL_1_BINARY <= "111"; + when others => assert FALSE report "Error : CHAN_BOND_LEVEL_1 is not in range 0...7." severity error; + end case; + case CHAN_BOND_SEQ_LEN_1 is + when 1 => CHAN_BOND_SEQ_LEN_1_BINARY <= "00"; + when 2 => CHAN_BOND_SEQ_LEN_1_BINARY <= "01"; + when 3 => CHAN_BOND_SEQ_LEN_1_BINARY <= "10"; + when 4 => CHAN_BOND_SEQ_LEN_1_BINARY <= "11"; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_LEN_1 is not in 1, 2, 3, 4." severity error; + end case; + case CHAN_BOND_SEQ_2_USE_1 is + when FALSE => CHAN_BOND_SEQ_2_USE_1_BINARY <= '0'; + when TRUE => CHAN_BOND_SEQ_2_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_2_USE_1 is neither TRUE nor FALSE." severity error; + end case; + case CHAN_BOND_1_MAX_SKEW_1 is + when 1 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0001"; + when 2 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0010"; + when 3 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0011"; + when 4 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0100"; + when 5 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0101"; + when 6 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0110"; + when 7 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0111"; + when 8 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1000"; + when 9 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1001"; + when 10 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1010"; + when 11 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1011"; + when 12 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1100"; + when 13 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1101"; + when 14 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1110"; + when others => assert FALSE report "Error : CHAN_BOND_1_MAX_SKEW_1 is not in range 1...14." severity error; + end case; + case CHAN_BOND_2_MAX_SKEW_1 is + when 1 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0001"; + when 2 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0010"; + when 3 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0011"; + when 4 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0100"; + when 5 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0101"; + when 6 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0110"; + when 7 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0111"; + when 8 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1000"; + when 9 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1001"; + when 10 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1010"; + when 11 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1011"; + when 12 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1100"; + when 13 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1101"; + when 14 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1110"; + when others => assert FALSE report "Error : CHAN_BOND_2_MAX_SKEW_1 is not in range 1...14." severity error; + end case; + case PCI_EXPRESS_MODE_0 is + when FALSE => PCI_EXPRESS_MODE_0_BINARY <= '0'; + when TRUE => PCI_EXPRESS_MODE_0_BINARY <= '1'; + when others => assert FALSE report "Error : PCI_EXPRESS_MODE_0 is neither TRUE nor FALSE." severity error; + end case; + case PCI_EXPRESS_MODE_1 is + when FALSE => PCI_EXPRESS_MODE_1_BINARY <= '0'; + when TRUE => PCI_EXPRESS_MODE_1_BINARY <= '1'; + when others => assert FALSE report "Error : PCI_EXPRESS_MODE_1 is neither TRUE nor FALSE." severity error; + end case; +-- case RX_STATUS_FMT_0 is + if((RX_STATUS_FMT_0 = "PCIE") or (RX_STATUS_FMT_0 = "pcie")) then + RX_STATUS_FMT_0_BINARY <= '0'; + elsif((RX_STATUS_FMT_0 = "SATA") or (RX_STATUS_FMT_0 = "sata")) then + RX_STATUS_FMT_0_BINARY <= '1'; + else + assert FALSE report "Error : RX_STATUS_FMT_0 = is not PCIE, SATA." severity error; + end if; +-- end case; + case TX_BUFFER_USE_0 is + when FALSE => TX_BUFFER_USE_0_BINARY <= '0'; + when TRUE => TX_BUFFER_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : TX_BUFFER_USE_0 is neither TRUE nor FALSE." severity error; + end case; +-- case TX_XCLK_SEL_0 is + if((TX_XCLK_SEL_0 = "TXUSR") or (TX_XCLK_SEL_0 = "txusr")) then + TX_XCLK_SEL_0_BINARY <= '1'; + elsif((TX_XCLK_SEL_0 = "TXOUT") or (TX_XCLK_SEL_0 = "txout")) then + TX_XCLK_SEL_0_BINARY <= '0'; + else + assert FALSE report "Error : TX_XCLK_SEL_0 = is not TXUSR, TXOUT." severity error; + end if; +-- end case; +-- case RX_XCLK_SEL_0 is + if((RX_XCLK_SEL_0 = "RXREC") or (RX_XCLK_SEL_0 = "rxrec")) then + RX_XCLK_SEL_0_BINARY <= '0'; + elsif((RX_XCLK_SEL_0 = "RXUSR") or (RX_XCLK_SEL_0 = "rxusr")) then + RX_XCLK_SEL_0_BINARY <= '1'; + else + assert FALSE report "Error : RX_XCLK_SEL_0 = is not RXREC, RXUSR." severity error; + end if; +-- end case; +-- case RX_STATUS_FMT_1 is + if((RX_STATUS_FMT_1 = "PCIE") or (RX_STATUS_FMT_1 = "pcie")) then + RX_STATUS_FMT_1_BINARY <= '0'; + elsif((RX_STATUS_FMT_1 = "SATA") or (RX_STATUS_FMT_1 = "sata")) then + RX_STATUS_FMT_1_BINARY <= '1'; + else + assert FALSE report "Error : RX_STATUS_FMT_1 = is not PCIE, SATA." severity error; + end if; +-- end case; + case TX_BUFFER_USE_1 is + when FALSE => TX_BUFFER_USE_1_BINARY <= '0'; + when TRUE => TX_BUFFER_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : TX_BUFFER_USE_1 is neither TRUE nor FALSE." severity error; + end case; +-- case TX_XCLK_SEL_1 is + if((TX_XCLK_SEL_1 = "TXUSR") or (TX_XCLK_SEL_1 = "txusr")) then + TX_XCLK_SEL_1_BINARY <= '1'; + elsif((TX_XCLK_SEL_1 = "TXOUT") or (TX_XCLK_SEL_1 = "txout")) then + TX_XCLK_SEL_1_BINARY <= '0'; + else + assert FALSE report "Error : TX_XCLK_SEL_1 = is not TXUSR, TXOUT." severity error; + end if; +-- end case; +-- case RX_XCLK_SEL_1 is + if((RX_XCLK_SEL_1 = "RXREC") or (RX_XCLK_SEL_1 = "rxrec")) then + RX_XCLK_SEL_1_BINARY <= '0'; + elsif((RX_XCLK_SEL_1 = "RXUSR") or (RX_XCLK_SEL_1 = "rxusr")) then + RX_XCLK_SEL_1_BINARY <= '1'; + else + assert FALSE report "Error : RX_XCLK_SEL_1 = is not RXREC, RXUSR." severity error; + end if; +-- end case; +-- case RX_SLIDE_MODE_0 is + if((RX_SLIDE_MODE_0 = "PCS") or (RX_SLIDE_MODE_0 = "pcs")) then + RX_SLIDE_MODE_0_BINARY <= '0'; + elsif((RX_SLIDE_MODE_0 = "PMA") or (RX_SLIDE_MODE_0 = "pma")) then + RX_SLIDE_MODE_0_BINARY <= '1'; + else + assert FALSE report "Error : RX_SLIDE_MODE_0 = is not PCS, PMA." severity error; + end if; +-- end case; +-- case RX_SLIDE_MODE_1 is + if((RX_SLIDE_MODE_1 = "PCS") or (RX_SLIDE_MODE_1 = "pcs")) then + RX_SLIDE_MODE_1_BINARY <= '0'; + elsif((RX_SLIDE_MODE_1 = "PMA") or (RX_SLIDE_MODE_1 = "pma")) then + RX_SLIDE_MODE_1_BINARY <= '1'; + else + assert FALSE report "Error : RX_SLIDE_MODE_1 = is not PCS, PMA." severity error; + end if; +-- end case; + case SATA_MIN_BURST_0 is + when 1 => SATA_MIN_BURST_0_BINARY <= "000001"; + when 2 => SATA_MIN_BURST_0_BINARY <= "000010"; + when 3 => SATA_MIN_BURST_0_BINARY <= "000011"; + when 4 => SATA_MIN_BURST_0_BINARY <= "000100"; + when 5 => SATA_MIN_BURST_0_BINARY <= "000101"; + when 6 => SATA_MIN_BURST_0_BINARY <= "000110"; + when 7 => SATA_MIN_BURST_0_BINARY <= "000111"; + when 8 => SATA_MIN_BURST_0_BINARY <= "001000"; + when 9 => SATA_MIN_BURST_0_BINARY <= "001001"; + when 10 => SATA_MIN_BURST_0_BINARY <= "001010"; + when 11 => SATA_MIN_BURST_0_BINARY <= "001011"; + when 12 => SATA_MIN_BURST_0_BINARY <= "001100"; + when 13 => SATA_MIN_BURST_0_BINARY <= "001101"; + when 14 => SATA_MIN_BURST_0_BINARY <= "001110"; + when 15 => SATA_MIN_BURST_0_BINARY <= "001111"; + when 16 => SATA_MIN_BURST_0_BINARY <= "010000"; + when 17 => SATA_MIN_BURST_0_BINARY <= "010001"; + when 18 => SATA_MIN_BURST_0_BINARY <= "010010"; + when 19 => SATA_MIN_BURST_0_BINARY <= "010011"; + when 20 => SATA_MIN_BURST_0_BINARY <= "010100"; + when 21 => SATA_MIN_BURST_0_BINARY <= "010101"; + when 22 => SATA_MIN_BURST_0_BINARY <= "010110"; + when 23 => SATA_MIN_BURST_0_BINARY <= "010111"; + when 24 => SATA_MIN_BURST_0_BINARY <= "011000"; + when 25 => SATA_MIN_BURST_0_BINARY <= "011001"; + when 26 => SATA_MIN_BURST_0_BINARY <= "011010"; + when 27 => SATA_MIN_BURST_0_BINARY <= "011011"; + when 28 => SATA_MIN_BURST_0_BINARY <= "011100"; + when 29 => SATA_MIN_BURST_0_BINARY <= "011101"; + when 30 => SATA_MIN_BURST_0_BINARY <= "011110"; + when 31 => SATA_MIN_BURST_0_BINARY <= "011111"; + when 32 => SATA_MIN_BURST_0_BINARY <= "100000"; + when 33 => SATA_MIN_BURST_0_BINARY <= "100001"; + when 34 => SATA_MIN_BURST_0_BINARY <= "100010"; + when 35 => SATA_MIN_BURST_0_BINARY <= "100011"; + when 36 => SATA_MIN_BURST_0_BINARY <= "100100"; + when 37 => SATA_MIN_BURST_0_BINARY <= "100101"; + when 38 => SATA_MIN_BURST_0_BINARY <= "100110"; + when 39 => SATA_MIN_BURST_0_BINARY <= "100111"; + when 40 => SATA_MIN_BURST_0_BINARY <= "101000"; + when 41 => SATA_MIN_BURST_0_BINARY <= "101001"; + when 42 => SATA_MIN_BURST_0_BINARY <= "101010"; + when 43 => SATA_MIN_BURST_0_BINARY <= "101011"; + when 44 => SATA_MIN_BURST_0_BINARY <= "101100"; + when 45 => SATA_MIN_BURST_0_BINARY <= "101101"; + when 46 => SATA_MIN_BURST_0_BINARY <= "101110"; + when 47 => SATA_MIN_BURST_0_BINARY <= "101111"; + when 48 => SATA_MIN_BURST_0_BINARY <= "110000"; + when 49 => SATA_MIN_BURST_0_BINARY <= "110001"; + when 50 => SATA_MIN_BURST_0_BINARY <= "110010"; + when 51 => SATA_MIN_BURST_0_BINARY <= "110011"; + when 52 => SATA_MIN_BURST_0_BINARY <= "110100"; + when 53 => SATA_MIN_BURST_0_BINARY <= "110101"; + when 54 => SATA_MIN_BURST_0_BINARY <= "110110"; + when 55 => SATA_MIN_BURST_0_BINARY <= "110111"; + when 56 => SATA_MIN_BURST_0_BINARY <= "111000"; + when 57 => SATA_MIN_BURST_0_BINARY <= "111001"; + when 58 => SATA_MIN_BURST_0_BINARY <= "111010"; + when 59 => SATA_MIN_BURST_0_BINARY <= "111011"; + when 60 => SATA_MIN_BURST_0_BINARY <= "111100"; + when 61 => SATA_MIN_BURST_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_BURST_0 is not in range 1...61." severity error; + end case; + case SATA_MAX_BURST_0 is + when 1 => SATA_MAX_BURST_0_BINARY <= "000001"; + when 2 => SATA_MAX_BURST_0_BINARY <= "000010"; + when 3 => SATA_MAX_BURST_0_BINARY <= "000011"; + when 4 => SATA_MAX_BURST_0_BINARY <= "000100"; + when 5 => SATA_MAX_BURST_0_BINARY <= "000101"; + when 6 => SATA_MAX_BURST_0_BINARY <= "000110"; + when 7 => SATA_MAX_BURST_0_BINARY <= "000111"; + when 8 => SATA_MAX_BURST_0_BINARY <= "001000"; + when 9 => SATA_MAX_BURST_0_BINARY <= "001001"; + when 10 => SATA_MAX_BURST_0_BINARY <= "001010"; + when 11 => SATA_MAX_BURST_0_BINARY <= "001011"; + when 12 => SATA_MAX_BURST_0_BINARY <= "001100"; + when 13 => SATA_MAX_BURST_0_BINARY <= "001101"; + when 14 => SATA_MAX_BURST_0_BINARY <= "001110"; + when 15 => SATA_MAX_BURST_0_BINARY <= "001111"; + when 16 => SATA_MAX_BURST_0_BINARY <= "010000"; + when 17 => SATA_MAX_BURST_0_BINARY <= "010001"; + when 18 => SATA_MAX_BURST_0_BINARY <= "010010"; + when 19 => SATA_MAX_BURST_0_BINARY <= "010011"; + when 20 => SATA_MAX_BURST_0_BINARY <= "010100"; + when 21 => SATA_MAX_BURST_0_BINARY <= "010101"; + when 22 => SATA_MAX_BURST_0_BINARY <= "010110"; + when 23 => SATA_MAX_BURST_0_BINARY <= "010111"; + when 24 => SATA_MAX_BURST_0_BINARY <= "011000"; + when 25 => SATA_MAX_BURST_0_BINARY <= "011001"; + when 26 => SATA_MAX_BURST_0_BINARY <= "011010"; + when 27 => SATA_MAX_BURST_0_BINARY <= "011011"; + when 28 => SATA_MAX_BURST_0_BINARY <= "011100"; + when 29 => SATA_MAX_BURST_0_BINARY <= "011101"; + when 30 => SATA_MAX_BURST_0_BINARY <= "011110"; + when 31 => SATA_MAX_BURST_0_BINARY <= "011111"; + when 32 => SATA_MAX_BURST_0_BINARY <= "100000"; + when 33 => SATA_MAX_BURST_0_BINARY <= "100001"; + when 34 => SATA_MAX_BURST_0_BINARY <= "100010"; + when 35 => SATA_MAX_BURST_0_BINARY <= "100011"; + when 36 => SATA_MAX_BURST_0_BINARY <= "100100"; + when 37 => SATA_MAX_BURST_0_BINARY <= "100101"; + when 38 => SATA_MAX_BURST_0_BINARY <= "100110"; + when 39 => SATA_MAX_BURST_0_BINARY <= "100111"; + when 40 => SATA_MAX_BURST_0_BINARY <= "101000"; + when 41 => SATA_MAX_BURST_0_BINARY <= "101001"; + when 42 => SATA_MAX_BURST_0_BINARY <= "101010"; + when 43 => SATA_MAX_BURST_0_BINARY <= "101011"; + when 44 => SATA_MAX_BURST_0_BINARY <= "101100"; + when 45 => SATA_MAX_BURST_0_BINARY <= "101101"; + when 46 => SATA_MAX_BURST_0_BINARY <= "101110"; + when 47 => SATA_MAX_BURST_0_BINARY <= "101111"; + when 48 => SATA_MAX_BURST_0_BINARY <= "110000"; + when 49 => SATA_MAX_BURST_0_BINARY <= "110001"; + when 50 => SATA_MAX_BURST_0_BINARY <= "110010"; + when 51 => SATA_MAX_BURST_0_BINARY <= "110011"; + when 52 => SATA_MAX_BURST_0_BINARY <= "110100"; + when 53 => SATA_MAX_BURST_0_BINARY <= "110101"; + when 54 => SATA_MAX_BURST_0_BINARY <= "110110"; + when 55 => SATA_MAX_BURST_0_BINARY <= "110111"; + when 56 => SATA_MAX_BURST_0_BINARY <= "111000"; + when 57 => SATA_MAX_BURST_0_BINARY <= "111001"; + when 58 => SATA_MAX_BURST_0_BINARY <= "111010"; + when 59 => SATA_MAX_BURST_0_BINARY <= "111011"; + when 60 => SATA_MAX_BURST_0_BINARY <= "111100"; + when 61 => SATA_MAX_BURST_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_BURST_0 is not in range 1...61." severity error; + end case; + case SATA_MIN_INIT_0 is + when 1 => SATA_MIN_INIT_0_BINARY <= "000001"; + when 2 => SATA_MIN_INIT_0_BINARY <= "000010"; + when 3 => SATA_MIN_INIT_0_BINARY <= "000011"; + when 4 => SATA_MIN_INIT_0_BINARY <= "000100"; + when 5 => SATA_MIN_INIT_0_BINARY <= "000101"; + when 6 => SATA_MIN_INIT_0_BINARY <= "000110"; + when 7 => SATA_MIN_INIT_0_BINARY <= "000111"; + when 8 => SATA_MIN_INIT_0_BINARY <= "001000"; + when 9 => SATA_MIN_INIT_0_BINARY <= "001001"; + when 10 => SATA_MIN_INIT_0_BINARY <= "001010"; + when 11 => SATA_MIN_INIT_0_BINARY <= "001011"; + when 12 => SATA_MIN_INIT_0_BINARY <= "001100"; + when 13 => SATA_MIN_INIT_0_BINARY <= "001101"; + when 14 => SATA_MIN_INIT_0_BINARY <= "001110"; + when 15 => SATA_MIN_INIT_0_BINARY <= "001111"; + when 16 => SATA_MIN_INIT_0_BINARY <= "010000"; + when 17 => SATA_MIN_INIT_0_BINARY <= "010001"; + when 18 => SATA_MIN_INIT_0_BINARY <= "010010"; + when 19 => SATA_MIN_INIT_0_BINARY <= "010011"; + when 20 => SATA_MIN_INIT_0_BINARY <= "010100"; + when 21 => SATA_MIN_INIT_0_BINARY <= "010101"; + when 22 => SATA_MIN_INIT_0_BINARY <= "010110"; + when 23 => SATA_MIN_INIT_0_BINARY <= "010111"; + when 24 => SATA_MIN_INIT_0_BINARY <= "011000"; + when 25 => SATA_MIN_INIT_0_BINARY <= "011001"; + when 26 => SATA_MIN_INIT_0_BINARY <= "011010"; + when 27 => SATA_MIN_INIT_0_BINARY <= "011011"; + when 28 => SATA_MIN_INIT_0_BINARY <= "011100"; + when 29 => SATA_MIN_INIT_0_BINARY <= "011101"; + when 30 => SATA_MIN_INIT_0_BINARY <= "011110"; + when 31 => SATA_MIN_INIT_0_BINARY <= "011111"; + when 32 => SATA_MIN_INIT_0_BINARY <= "100000"; + when 33 => SATA_MIN_INIT_0_BINARY <= "100001"; + when 34 => SATA_MIN_INIT_0_BINARY <= "100010"; + when 35 => SATA_MIN_INIT_0_BINARY <= "100011"; + when 36 => SATA_MIN_INIT_0_BINARY <= "100100"; + when 37 => SATA_MIN_INIT_0_BINARY <= "100101"; + when 38 => SATA_MIN_INIT_0_BINARY <= "100110"; + when 39 => SATA_MIN_INIT_0_BINARY <= "100111"; + when 40 => SATA_MIN_INIT_0_BINARY <= "101000"; + when 41 => SATA_MIN_INIT_0_BINARY <= "101001"; + when 42 => SATA_MIN_INIT_0_BINARY <= "101010"; + when 43 => SATA_MIN_INIT_0_BINARY <= "101011"; + when 44 => SATA_MIN_INIT_0_BINARY <= "101100"; + when 45 => SATA_MIN_INIT_0_BINARY <= "101101"; + when 46 => SATA_MIN_INIT_0_BINARY <= "101110"; + when 47 => SATA_MIN_INIT_0_BINARY <= "101111"; + when 48 => SATA_MIN_INIT_0_BINARY <= "110000"; + when 49 => SATA_MIN_INIT_0_BINARY <= "110001"; + when 50 => SATA_MIN_INIT_0_BINARY <= "110010"; + when 51 => SATA_MIN_INIT_0_BINARY <= "110011"; + when 52 => SATA_MIN_INIT_0_BINARY <= "110100"; + when 53 => SATA_MIN_INIT_0_BINARY <= "110101"; + when 54 => SATA_MIN_INIT_0_BINARY <= "110110"; + when 55 => SATA_MIN_INIT_0_BINARY <= "110111"; + when 56 => SATA_MIN_INIT_0_BINARY <= "111000"; + when 57 => SATA_MIN_INIT_0_BINARY <= "111001"; + when 58 => SATA_MIN_INIT_0_BINARY <= "111010"; + when 59 => SATA_MIN_INIT_0_BINARY <= "111011"; + when 60 => SATA_MIN_INIT_0_BINARY <= "111100"; + when 61 => SATA_MIN_INIT_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_INIT_0 is not in range 1...61." severity error; + end case; + case SATA_MAX_INIT_0 is + when 1 => SATA_MAX_INIT_0_BINARY <= "000001"; + when 2 => SATA_MAX_INIT_0_BINARY <= "000010"; + when 3 => SATA_MAX_INIT_0_BINARY <= "000011"; + when 4 => SATA_MAX_INIT_0_BINARY <= "000100"; + when 5 => SATA_MAX_INIT_0_BINARY <= "000101"; + when 6 => SATA_MAX_INIT_0_BINARY <= "000110"; + when 7 => SATA_MAX_INIT_0_BINARY <= "000111"; + when 8 => SATA_MAX_INIT_0_BINARY <= "001000"; + when 9 => SATA_MAX_INIT_0_BINARY <= "001001"; + when 10 => SATA_MAX_INIT_0_BINARY <= "001010"; + when 11 => SATA_MAX_INIT_0_BINARY <= "001011"; + when 12 => SATA_MAX_INIT_0_BINARY <= "001100"; + when 13 => SATA_MAX_INIT_0_BINARY <= "001101"; + when 14 => SATA_MAX_INIT_0_BINARY <= "001110"; + when 15 => SATA_MAX_INIT_0_BINARY <= "001111"; + when 16 => SATA_MAX_INIT_0_BINARY <= "010000"; + when 17 => SATA_MAX_INIT_0_BINARY <= "010001"; + when 18 => SATA_MAX_INIT_0_BINARY <= "010010"; + when 19 => SATA_MAX_INIT_0_BINARY <= "010011"; + when 20 => SATA_MAX_INIT_0_BINARY <= "010100"; + when 21 => SATA_MAX_INIT_0_BINARY <= "010101"; + when 22 => SATA_MAX_INIT_0_BINARY <= "010110"; + when 23 => SATA_MAX_INIT_0_BINARY <= "010111"; + when 24 => SATA_MAX_INIT_0_BINARY <= "011000"; + when 25 => SATA_MAX_INIT_0_BINARY <= "011001"; + when 26 => SATA_MAX_INIT_0_BINARY <= "011010"; + when 27 => SATA_MAX_INIT_0_BINARY <= "011011"; + when 28 => SATA_MAX_INIT_0_BINARY <= "011100"; + when 29 => SATA_MAX_INIT_0_BINARY <= "011101"; + when 30 => SATA_MAX_INIT_0_BINARY <= "011110"; + when 31 => SATA_MAX_INIT_0_BINARY <= "011111"; + when 32 => SATA_MAX_INIT_0_BINARY <= "100000"; + when 33 => SATA_MAX_INIT_0_BINARY <= "100001"; + when 34 => SATA_MAX_INIT_0_BINARY <= "100010"; + when 35 => SATA_MAX_INIT_0_BINARY <= "100011"; + when 36 => SATA_MAX_INIT_0_BINARY <= "100100"; + when 37 => SATA_MAX_INIT_0_BINARY <= "100101"; + when 38 => SATA_MAX_INIT_0_BINARY <= "100110"; + when 39 => SATA_MAX_INIT_0_BINARY <= "100111"; + when 40 => SATA_MAX_INIT_0_BINARY <= "101000"; + when 41 => SATA_MAX_INIT_0_BINARY <= "101001"; + when 42 => SATA_MAX_INIT_0_BINARY <= "101010"; + when 43 => SATA_MAX_INIT_0_BINARY <= "101011"; + when 44 => SATA_MAX_INIT_0_BINARY <= "101100"; + when 45 => SATA_MAX_INIT_0_BINARY <= "101101"; + when 46 => SATA_MAX_INIT_0_BINARY <= "101110"; + when 47 => SATA_MAX_INIT_0_BINARY <= "101111"; + when 48 => SATA_MAX_INIT_0_BINARY <= "110000"; + when 49 => SATA_MAX_INIT_0_BINARY <= "110001"; + when 50 => SATA_MAX_INIT_0_BINARY <= "110010"; + when 51 => SATA_MAX_INIT_0_BINARY <= "110011"; + when 52 => SATA_MAX_INIT_0_BINARY <= "110100"; + when 53 => SATA_MAX_INIT_0_BINARY <= "110101"; + when 54 => SATA_MAX_INIT_0_BINARY <= "110110"; + when 55 => SATA_MAX_INIT_0_BINARY <= "110111"; + when 56 => SATA_MAX_INIT_0_BINARY <= "111000"; + when 57 => SATA_MAX_INIT_0_BINARY <= "111001"; + when 58 => SATA_MAX_INIT_0_BINARY <= "111010"; + when 59 => SATA_MAX_INIT_0_BINARY <= "111011"; + when 60 => SATA_MAX_INIT_0_BINARY <= "111100"; + when 61 => SATA_MAX_INIT_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_INIT_0 is not in range 1...61." severity error; + end case; + case SATA_MIN_WAKE_0 is + when 1 => SATA_MIN_WAKE_0_BINARY <= "000001"; + when 2 => SATA_MIN_WAKE_0_BINARY <= "000010"; + when 3 => SATA_MIN_WAKE_0_BINARY <= "000011"; + when 4 => SATA_MIN_WAKE_0_BINARY <= "000100"; + when 5 => SATA_MIN_WAKE_0_BINARY <= "000101"; + when 6 => SATA_MIN_WAKE_0_BINARY <= "000110"; + when 7 => SATA_MIN_WAKE_0_BINARY <= "000111"; + when 8 => SATA_MIN_WAKE_0_BINARY <= "001000"; + when 9 => SATA_MIN_WAKE_0_BINARY <= "001001"; + when 10 => SATA_MIN_WAKE_0_BINARY <= "001010"; + when 11 => SATA_MIN_WAKE_0_BINARY <= "001011"; + when 12 => SATA_MIN_WAKE_0_BINARY <= "001100"; + when 13 => SATA_MIN_WAKE_0_BINARY <= "001101"; + when 14 => SATA_MIN_WAKE_0_BINARY <= "001110"; + when 15 => SATA_MIN_WAKE_0_BINARY <= "001111"; + when 16 => SATA_MIN_WAKE_0_BINARY <= "010000"; + when 17 => SATA_MIN_WAKE_0_BINARY <= "010001"; + when 18 => SATA_MIN_WAKE_0_BINARY <= "010010"; + when 19 => SATA_MIN_WAKE_0_BINARY <= "010011"; + when 20 => SATA_MIN_WAKE_0_BINARY <= "010100"; + when 21 => SATA_MIN_WAKE_0_BINARY <= "010101"; + when 22 => SATA_MIN_WAKE_0_BINARY <= "010110"; + when 23 => SATA_MIN_WAKE_0_BINARY <= "010111"; + when 24 => SATA_MIN_WAKE_0_BINARY <= "011000"; + when 25 => SATA_MIN_WAKE_0_BINARY <= "011001"; + when 26 => SATA_MIN_WAKE_0_BINARY <= "011010"; + when 27 => SATA_MIN_WAKE_0_BINARY <= "011011"; + when 28 => SATA_MIN_WAKE_0_BINARY <= "011100"; + when 29 => SATA_MIN_WAKE_0_BINARY <= "011101"; + when 30 => SATA_MIN_WAKE_0_BINARY <= "011110"; + when 31 => SATA_MIN_WAKE_0_BINARY <= "011111"; + when 32 => SATA_MIN_WAKE_0_BINARY <= "100000"; + when 33 => SATA_MIN_WAKE_0_BINARY <= "100001"; + when 34 => SATA_MIN_WAKE_0_BINARY <= "100010"; + when 35 => SATA_MIN_WAKE_0_BINARY <= "100011"; + when 36 => SATA_MIN_WAKE_0_BINARY <= "100100"; + when 37 => SATA_MIN_WAKE_0_BINARY <= "100101"; + when 38 => SATA_MIN_WAKE_0_BINARY <= "100110"; + when 39 => SATA_MIN_WAKE_0_BINARY <= "100111"; + when 40 => SATA_MIN_WAKE_0_BINARY <= "101000"; + when 41 => SATA_MIN_WAKE_0_BINARY <= "101001"; + when 42 => SATA_MIN_WAKE_0_BINARY <= "101010"; + when 43 => SATA_MIN_WAKE_0_BINARY <= "101011"; + when 44 => SATA_MIN_WAKE_0_BINARY <= "101100"; + when 45 => SATA_MIN_WAKE_0_BINARY <= "101101"; + when 46 => SATA_MIN_WAKE_0_BINARY <= "101110"; + when 47 => SATA_MIN_WAKE_0_BINARY <= "101111"; + when 48 => SATA_MIN_WAKE_0_BINARY <= "110000"; + when 49 => SATA_MIN_WAKE_0_BINARY <= "110001"; + when 50 => SATA_MIN_WAKE_0_BINARY <= "110010"; + when 51 => SATA_MIN_WAKE_0_BINARY <= "110011"; + when 52 => SATA_MIN_WAKE_0_BINARY <= "110100"; + when 53 => SATA_MIN_WAKE_0_BINARY <= "110101"; + when 54 => SATA_MIN_WAKE_0_BINARY <= "110110"; + when 55 => SATA_MIN_WAKE_0_BINARY <= "110111"; + when 56 => SATA_MIN_WAKE_0_BINARY <= "111000"; + when 57 => SATA_MIN_WAKE_0_BINARY <= "111001"; + when 58 => SATA_MIN_WAKE_0_BINARY <= "111010"; + when 59 => SATA_MIN_WAKE_0_BINARY <= "111011"; + when 60 => SATA_MIN_WAKE_0_BINARY <= "111100"; + when 61 => SATA_MIN_WAKE_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_WAKE_0 is not in range 1...61." severity error; + end case; + case SATA_MAX_WAKE_0 is + when 1 => SATA_MAX_WAKE_0_BINARY <= "000001"; + when 2 => SATA_MAX_WAKE_0_BINARY <= "000010"; + when 3 => SATA_MAX_WAKE_0_BINARY <= "000011"; + when 4 => SATA_MAX_WAKE_0_BINARY <= "000100"; + when 5 => SATA_MAX_WAKE_0_BINARY <= "000101"; + when 6 => SATA_MAX_WAKE_0_BINARY <= "000110"; + when 7 => SATA_MAX_WAKE_0_BINARY <= "000111"; + when 8 => SATA_MAX_WAKE_0_BINARY <= "001000"; + when 9 => SATA_MAX_WAKE_0_BINARY <= "001001"; + when 10 => SATA_MAX_WAKE_0_BINARY <= "001010"; + when 11 => SATA_MAX_WAKE_0_BINARY <= "001011"; + when 12 => SATA_MAX_WAKE_0_BINARY <= "001100"; + when 13 => SATA_MAX_WAKE_0_BINARY <= "001101"; + when 14 => SATA_MAX_WAKE_0_BINARY <= "001110"; + when 15 => SATA_MAX_WAKE_0_BINARY <= "001111"; + when 16 => SATA_MAX_WAKE_0_BINARY <= "010000"; + when 17 => SATA_MAX_WAKE_0_BINARY <= "010001"; + when 18 => SATA_MAX_WAKE_0_BINARY <= "010010"; + when 19 => SATA_MAX_WAKE_0_BINARY <= "010011"; + when 20 => SATA_MAX_WAKE_0_BINARY <= "010100"; + when 21 => SATA_MAX_WAKE_0_BINARY <= "010101"; + when 22 => SATA_MAX_WAKE_0_BINARY <= "010110"; + when 23 => SATA_MAX_WAKE_0_BINARY <= "010111"; + when 24 => SATA_MAX_WAKE_0_BINARY <= "011000"; + when 25 => SATA_MAX_WAKE_0_BINARY <= "011001"; + when 26 => SATA_MAX_WAKE_0_BINARY <= "011010"; + when 27 => SATA_MAX_WAKE_0_BINARY <= "011011"; + when 28 => SATA_MAX_WAKE_0_BINARY <= "011100"; + when 29 => SATA_MAX_WAKE_0_BINARY <= "011101"; + when 30 => SATA_MAX_WAKE_0_BINARY <= "011110"; + when 31 => SATA_MAX_WAKE_0_BINARY <= "011111"; + when 32 => SATA_MAX_WAKE_0_BINARY <= "100000"; + when 33 => SATA_MAX_WAKE_0_BINARY <= "100001"; + when 34 => SATA_MAX_WAKE_0_BINARY <= "100010"; + when 35 => SATA_MAX_WAKE_0_BINARY <= "100011"; + when 36 => SATA_MAX_WAKE_0_BINARY <= "100100"; + when 37 => SATA_MAX_WAKE_0_BINARY <= "100101"; + when 38 => SATA_MAX_WAKE_0_BINARY <= "100110"; + when 39 => SATA_MAX_WAKE_0_BINARY <= "100111"; + when 40 => SATA_MAX_WAKE_0_BINARY <= "101000"; + when 41 => SATA_MAX_WAKE_0_BINARY <= "101001"; + when 42 => SATA_MAX_WAKE_0_BINARY <= "101010"; + when 43 => SATA_MAX_WAKE_0_BINARY <= "101011"; + when 44 => SATA_MAX_WAKE_0_BINARY <= "101100"; + when 45 => SATA_MAX_WAKE_0_BINARY <= "101101"; + when 46 => SATA_MAX_WAKE_0_BINARY <= "101110"; + when 47 => SATA_MAX_WAKE_0_BINARY <= "101111"; + when 48 => SATA_MAX_WAKE_0_BINARY <= "110000"; + when 49 => SATA_MAX_WAKE_0_BINARY <= "110001"; + when 50 => SATA_MAX_WAKE_0_BINARY <= "110010"; + when 51 => SATA_MAX_WAKE_0_BINARY <= "110011"; + when 52 => SATA_MAX_WAKE_0_BINARY <= "110100"; + when 53 => SATA_MAX_WAKE_0_BINARY <= "110101"; + when 54 => SATA_MAX_WAKE_0_BINARY <= "110110"; + when 55 => SATA_MAX_WAKE_0_BINARY <= "110111"; + when 56 => SATA_MAX_WAKE_0_BINARY <= "111000"; + when 57 => SATA_MAX_WAKE_0_BINARY <= "111001"; + when 58 => SATA_MAX_WAKE_0_BINARY <= "111010"; + when 59 => SATA_MAX_WAKE_0_BINARY <= "111011"; + when 60 => SATA_MAX_WAKE_0_BINARY <= "111100"; + when 61 => SATA_MAX_WAKE_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_WAKE_0 is not in range 1...61." severity error; + end case; + case SATA_MIN_BURST_1 is + when 1 => SATA_MIN_BURST_1_BINARY <= "000001"; + when 2 => SATA_MIN_BURST_1_BINARY <= "000010"; + when 3 => SATA_MIN_BURST_1_BINARY <= "000011"; + when 4 => SATA_MIN_BURST_1_BINARY <= "000100"; + when 5 => SATA_MIN_BURST_1_BINARY <= "000101"; + when 6 => SATA_MIN_BURST_1_BINARY <= "000110"; + when 7 => SATA_MIN_BURST_1_BINARY <= "000111"; + when 8 => SATA_MIN_BURST_1_BINARY <= "001000"; + when 9 => SATA_MIN_BURST_1_BINARY <= "001001"; + when 10 => SATA_MIN_BURST_1_BINARY <= "001010"; + when 11 => SATA_MIN_BURST_1_BINARY <= "001011"; + when 12 => SATA_MIN_BURST_1_BINARY <= "001100"; + when 13 => SATA_MIN_BURST_1_BINARY <= "001101"; + when 14 => SATA_MIN_BURST_1_BINARY <= "001110"; + when 15 => SATA_MIN_BURST_1_BINARY <= "001111"; + when 16 => SATA_MIN_BURST_1_BINARY <= "010000"; + when 17 => SATA_MIN_BURST_1_BINARY <= "010001"; + when 18 => SATA_MIN_BURST_1_BINARY <= "010010"; + when 19 => SATA_MIN_BURST_1_BINARY <= "010011"; + when 20 => SATA_MIN_BURST_1_BINARY <= "010100"; + when 21 => SATA_MIN_BURST_1_BINARY <= "010101"; + when 22 => SATA_MIN_BURST_1_BINARY <= "010110"; + when 23 => SATA_MIN_BURST_1_BINARY <= "010111"; + when 24 => SATA_MIN_BURST_1_BINARY <= "011000"; + when 25 => SATA_MIN_BURST_1_BINARY <= "011001"; + when 26 => SATA_MIN_BURST_1_BINARY <= "011010"; + when 27 => SATA_MIN_BURST_1_BINARY <= "011011"; + when 28 => SATA_MIN_BURST_1_BINARY <= "011100"; + when 29 => SATA_MIN_BURST_1_BINARY <= "011101"; + when 30 => SATA_MIN_BURST_1_BINARY <= "011110"; + when 31 => SATA_MIN_BURST_1_BINARY <= "011111"; + when 32 => SATA_MIN_BURST_1_BINARY <= "100000"; + when 33 => SATA_MIN_BURST_1_BINARY <= "100001"; + when 34 => SATA_MIN_BURST_1_BINARY <= "100010"; + when 35 => SATA_MIN_BURST_1_BINARY <= "100011"; + when 36 => SATA_MIN_BURST_1_BINARY <= "100100"; + when 37 => SATA_MIN_BURST_1_BINARY <= "100101"; + when 38 => SATA_MIN_BURST_1_BINARY <= "100110"; + when 39 => SATA_MIN_BURST_1_BINARY <= "100111"; + when 40 => SATA_MIN_BURST_1_BINARY <= "101000"; + when 41 => SATA_MIN_BURST_1_BINARY <= "101001"; + when 42 => SATA_MIN_BURST_1_BINARY <= "101010"; + when 43 => SATA_MIN_BURST_1_BINARY <= "101011"; + when 44 => SATA_MIN_BURST_1_BINARY <= "101100"; + when 45 => SATA_MIN_BURST_1_BINARY <= "101101"; + when 46 => SATA_MIN_BURST_1_BINARY <= "101110"; + when 47 => SATA_MIN_BURST_1_BINARY <= "101111"; + when 48 => SATA_MIN_BURST_1_BINARY <= "110000"; + when 49 => SATA_MIN_BURST_1_BINARY <= "110001"; + when 50 => SATA_MIN_BURST_1_BINARY <= "110010"; + when 51 => SATA_MIN_BURST_1_BINARY <= "110011"; + when 52 => SATA_MIN_BURST_1_BINARY <= "110100"; + when 53 => SATA_MIN_BURST_1_BINARY <= "110101"; + when 54 => SATA_MIN_BURST_1_BINARY <= "110110"; + when 55 => SATA_MIN_BURST_1_BINARY <= "110111"; + when 56 => SATA_MIN_BURST_1_BINARY <= "111000"; + when 57 => SATA_MIN_BURST_1_BINARY <= "111001"; + when 58 => SATA_MIN_BURST_1_BINARY <= "111010"; + when 59 => SATA_MIN_BURST_1_BINARY <= "111011"; + when 60 => SATA_MIN_BURST_1_BINARY <= "111100"; + when 61 => SATA_MIN_BURST_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_BURST_1 is not in range 1...61." severity error; + end case; + case SATA_MAX_BURST_1 is + when 1 => SATA_MAX_BURST_1_BINARY <= "000001"; + when 2 => SATA_MAX_BURST_1_BINARY <= "000010"; + when 3 => SATA_MAX_BURST_1_BINARY <= "000011"; + when 4 => SATA_MAX_BURST_1_BINARY <= "000100"; + when 5 => SATA_MAX_BURST_1_BINARY <= "000101"; + when 6 => SATA_MAX_BURST_1_BINARY <= "000110"; + when 7 => SATA_MAX_BURST_1_BINARY <= "000111"; + when 8 => SATA_MAX_BURST_1_BINARY <= "001000"; + when 9 => SATA_MAX_BURST_1_BINARY <= "001001"; + when 10 => SATA_MAX_BURST_1_BINARY <= "001010"; + when 11 => SATA_MAX_BURST_1_BINARY <= "001011"; + when 12 => SATA_MAX_BURST_1_BINARY <= "001100"; + when 13 => SATA_MAX_BURST_1_BINARY <= "001101"; + when 14 => SATA_MAX_BURST_1_BINARY <= "001110"; + when 15 => SATA_MAX_BURST_1_BINARY <= "001111"; + when 16 => SATA_MAX_BURST_1_BINARY <= "010000"; + when 17 => SATA_MAX_BURST_1_BINARY <= "010001"; + when 18 => SATA_MAX_BURST_1_BINARY <= "010010"; + when 19 => SATA_MAX_BURST_1_BINARY <= "010011"; + when 20 => SATA_MAX_BURST_1_BINARY <= "010100"; + when 21 => SATA_MAX_BURST_1_BINARY <= "010101"; + when 22 => SATA_MAX_BURST_1_BINARY <= "010110"; + when 23 => SATA_MAX_BURST_1_BINARY <= "010111"; + when 24 => SATA_MAX_BURST_1_BINARY <= "011000"; + when 25 => SATA_MAX_BURST_1_BINARY <= "011001"; + when 26 => SATA_MAX_BURST_1_BINARY <= "011010"; + when 27 => SATA_MAX_BURST_1_BINARY <= "011011"; + when 28 => SATA_MAX_BURST_1_BINARY <= "011100"; + when 29 => SATA_MAX_BURST_1_BINARY <= "011101"; + when 30 => SATA_MAX_BURST_1_BINARY <= "011110"; + when 31 => SATA_MAX_BURST_1_BINARY <= "011111"; + when 32 => SATA_MAX_BURST_1_BINARY <= "100000"; + when 33 => SATA_MAX_BURST_1_BINARY <= "100001"; + when 34 => SATA_MAX_BURST_1_BINARY <= "100010"; + when 35 => SATA_MAX_BURST_1_BINARY <= "100011"; + when 36 => SATA_MAX_BURST_1_BINARY <= "100100"; + when 37 => SATA_MAX_BURST_1_BINARY <= "100101"; + when 38 => SATA_MAX_BURST_1_BINARY <= "100110"; + when 39 => SATA_MAX_BURST_1_BINARY <= "100111"; + when 40 => SATA_MAX_BURST_1_BINARY <= "101000"; + when 41 => SATA_MAX_BURST_1_BINARY <= "101001"; + when 42 => SATA_MAX_BURST_1_BINARY <= "101010"; + when 43 => SATA_MAX_BURST_1_BINARY <= "101011"; + when 44 => SATA_MAX_BURST_1_BINARY <= "101100"; + when 45 => SATA_MAX_BURST_1_BINARY <= "101101"; + when 46 => SATA_MAX_BURST_1_BINARY <= "101110"; + when 47 => SATA_MAX_BURST_1_BINARY <= "101111"; + when 48 => SATA_MAX_BURST_1_BINARY <= "110000"; + when 49 => SATA_MAX_BURST_1_BINARY <= "110001"; + when 50 => SATA_MAX_BURST_1_BINARY <= "110010"; + when 51 => SATA_MAX_BURST_1_BINARY <= "110011"; + when 52 => SATA_MAX_BURST_1_BINARY <= "110100"; + when 53 => SATA_MAX_BURST_1_BINARY <= "110101"; + when 54 => SATA_MAX_BURST_1_BINARY <= "110110"; + when 55 => SATA_MAX_BURST_1_BINARY <= "110111"; + when 56 => SATA_MAX_BURST_1_BINARY <= "111000"; + when 57 => SATA_MAX_BURST_1_BINARY <= "111001"; + when 58 => SATA_MAX_BURST_1_BINARY <= "111010"; + when 59 => SATA_MAX_BURST_1_BINARY <= "111011"; + when 60 => SATA_MAX_BURST_1_BINARY <= "111100"; + when 61 => SATA_MAX_BURST_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_BURST_1 is not in range 1...61." severity error; + end case; + case SATA_MIN_INIT_1 is + when 1 => SATA_MIN_INIT_1_BINARY <= "000001"; + when 2 => SATA_MIN_INIT_1_BINARY <= "000010"; + when 3 => SATA_MIN_INIT_1_BINARY <= "000011"; + when 4 => SATA_MIN_INIT_1_BINARY <= "000100"; + when 5 => SATA_MIN_INIT_1_BINARY <= "000101"; + when 6 => SATA_MIN_INIT_1_BINARY <= "000110"; + when 7 => SATA_MIN_INIT_1_BINARY <= "000111"; + when 8 => SATA_MIN_INIT_1_BINARY <= "001000"; + when 9 => SATA_MIN_INIT_1_BINARY <= "001001"; + when 10 => SATA_MIN_INIT_1_BINARY <= "001010"; + when 11 => SATA_MIN_INIT_1_BINARY <= "001011"; + when 12 => SATA_MIN_INIT_1_BINARY <= "001100"; + when 13 => SATA_MIN_INIT_1_BINARY <= "001101"; + when 14 => SATA_MIN_INIT_1_BINARY <= "001110"; + when 15 => SATA_MIN_INIT_1_BINARY <= "001111"; + when 16 => SATA_MIN_INIT_1_BINARY <= "010000"; + when 17 => SATA_MIN_INIT_1_BINARY <= "010001"; + when 18 => SATA_MIN_INIT_1_BINARY <= "010010"; + when 19 => SATA_MIN_INIT_1_BINARY <= "010011"; + when 20 => SATA_MIN_INIT_1_BINARY <= "010100"; + when 21 => SATA_MIN_INIT_1_BINARY <= "010101"; + when 22 => SATA_MIN_INIT_1_BINARY <= "010110"; + when 23 => SATA_MIN_INIT_1_BINARY <= "010111"; + when 24 => SATA_MIN_INIT_1_BINARY <= "011000"; + when 25 => SATA_MIN_INIT_1_BINARY <= "011001"; + when 26 => SATA_MIN_INIT_1_BINARY <= "011010"; + when 27 => SATA_MIN_INIT_1_BINARY <= "011011"; + when 28 => SATA_MIN_INIT_1_BINARY <= "011100"; + when 29 => SATA_MIN_INIT_1_BINARY <= "011101"; + when 30 => SATA_MIN_INIT_1_BINARY <= "011110"; + when 31 => SATA_MIN_INIT_1_BINARY <= "011111"; + when 32 => SATA_MIN_INIT_1_BINARY <= "100000"; + when 33 => SATA_MIN_INIT_1_BINARY <= "100001"; + when 34 => SATA_MIN_INIT_1_BINARY <= "100010"; + when 35 => SATA_MIN_INIT_1_BINARY <= "100011"; + when 36 => SATA_MIN_INIT_1_BINARY <= "100100"; + when 37 => SATA_MIN_INIT_1_BINARY <= "100101"; + when 38 => SATA_MIN_INIT_1_BINARY <= "100110"; + when 39 => SATA_MIN_INIT_1_BINARY <= "100111"; + when 40 => SATA_MIN_INIT_1_BINARY <= "101000"; + when 41 => SATA_MIN_INIT_1_BINARY <= "101001"; + when 42 => SATA_MIN_INIT_1_BINARY <= "101010"; + when 43 => SATA_MIN_INIT_1_BINARY <= "101011"; + when 44 => SATA_MIN_INIT_1_BINARY <= "101100"; + when 45 => SATA_MIN_INIT_1_BINARY <= "101101"; + when 46 => SATA_MIN_INIT_1_BINARY <= "101110"; + when 47 => SATA_MIN_INIT_1_BINARY <= "101111"; + when 48 => SATA_MIN_INIT_1_BINARY <= "110000"; + when 49 => SATA_MIN_INIT_1_BINARY <= "110001"; + when 50 => SATA_MIN_INIT_1_BINARY <= "110010"; + when 51 => SATA_MIN_INIT_1_BINARY <= "110011"; + when 52 => SATA_MIN_INIT_1_BINARY <= "110100"; + when 53 => SATA_MIN_INIT_1_BINARY <= "110101"; + when 54 => SATA_MIN_INIT_1_BINARY <= "110110"; + when 55 => SATA_MIN_INIT_1_BINARY <= "110111"; + when 56 => SATA_MIN_INIT_1_BINARY <= "111000"; + when 57 => SATA_MIN_INIT_1_BINARY <= "111001"; + when 58 => SATA_MIN_INIT_1_BINARY <= "111010"; + when 59 => SATA_MIN_INIT_1_BINARY <= "111011"; + when 60 => SATA_MIN_INIT_1_BINARY <= "111100"; + when 61 => SATA_MIN_INIT_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_INIT_1 is not in range 1...61." severity error; + end case; + case SATA_MAX_INIT_1 is + when 1 => SATA_MAX_INIT_1_BINARY <= "000001"; + when 2 => SATA_MAX_INIT_1_BINARY <= "000010"; + when 3 => SATA_MAX_INIT_1_BINARY <= "000011"; + when 4 => SATA_MAX_INIT_1_BINARY <= "000100"; + when 5 => SATA_MAX_INIT_1_BINARY <= "000101"; + when 6 => SATA_MAX_INIT_1_BINARY <= "000110"; + when 7 => SATA_MAX_INIT_1_BINARY <= "000111"; + when 8 => SATA_MAX_INIT_1_BINARY <= "001000"; + when 9 => SATA_MAX_INIT_1_BINARY <= "001001"; + when 10 => SATA_MAX_INIT_1_BINARY <= "001010"; + when 11 => SATA_MAX_INIT_1_BINARY <= "001011"; + when 12 => SATA_MAX_INIT_1_BINARY <= "001100"; + when 13 => SATA_MAX_INIT_1_BINARY <= "001101"; + when 14 => SATA_MAX_INIT_1_BINARY <= "001110"; + when 15 => SATA_MAX_INIT_1_BINARY <= "001111"; + when 16 => SATA_MAX_INIT_1_BINARY <= "010000"; + when 17 => SATA_MAX_INIT_1_BINARY <= "010001"; + when 18 => SATA_MAX_INIT_1_BINARY <= "010010"; + when 19 => SATA_MAX_INIT_1_BINARY <= "010011"; + when 20 => SATA_MAX_INIT_1_BINARY <= "010100"; + when 21 => SATA_MAX_INIT_1_BINARY <= "010101"; + when 22 => SATA_MAX_INIT_1_BINARY <= "010110"; + when 23 => SATA_MAX_INIT_1_BINARY <= "010111"; + when 24 => SATA_MAX_INIT_1_BINARY <= "011000"; + when 25 => SATA_MAX_INIT_1_BINARY <= "011001"; + when 26 => SATA_MAX_INIT_1_BINARY <= "011010"; + when 27 => SATA_MAX_INIT_1_BINARY <= "011011"; + when 28 => SATA_MAX_INIT_1_BINARY <= "011100"; + when 29 => SATA_MAX_INIT_1_BINARY <= "011101"; + when 30 => SATA_MAX_INIT_1_BINARY <= "011110"; + when 31 => SATA_MAX_INIT_1_BINARY <= "011111"; + when 32 => SATA_MAX_INIT_1_BINARY <= "100000"; + when 33 => SATA_MAX_INIT_1_BINARY <= "100001"; + when 34 => SATA_MAX_INIT_1_BINARY <= "100010"; + when 35 => SATA_MAX_INIT_1_BINARY <= "100011"; + when 36 => SATA_MAX_INIT_1_BINARY <= "100100"; + when 37 => SATA_MAX_INIT_1_BINARY <= "100101"; + when 38 => SATA_MAX_INIT_1_BINARY <= "100110"; + when 39 => SATA_MAX_INIT_1_BINARY <= "100111"; + when 40 => SATA_MAX_INIT_1_BINARY <= "101000"; + when 41 => SATA_MAX_INIT_1_BINARY <= "101001"; + when 42 => SATA_MAX_INIT_1_BINARY <= "101010"; + when 43 => SATA_MAX_INIT_1_BINARY <= "101011"; + when 44 => SATA_MAX_INIT_1_BINARY <= "101100"; + when 45 => SATA_MAX_INIT_1_BINARY <= "101101"; + when 46 => SATA_MAX_INIT_1_BINARY <= "101110"; + when 47 => SATA_MAX_INIT_1_BINARY <= "101111"; + when 48 => SATA_MAX_INIT_1_BINARY <= "110000"; + when 49 => SATA_MAX_INIT_1_BINARY <= "110001"; + when 50 => SATA_MAX_INIT_1_BINARY <= "110010"; + when 51 => SATA_MAX_INIT_1_BINARY <= "110011"; + when 52 => SATA_MAX_INIT_1_BINARY <= "110100"; + when 53 => SATA_MAX_INIT_1_BINARY <= "110101"; + when 54 => SATA_MAX_INIT_1_BINARY <= "110110"; + when 55 => SATA_MAX_INIT_1_BINARY <= "110111"; + when 56 => SATA_MAX_INIT_1_BINARY <= "111000"; + when 57 => SATA_MAX_INIT_1_BINARY <= "111001"; + when 58 => SATA_MAX_INIT_1_BINARY <= "111010"; + when 59 => SATA_MAX_INIT_1_BINARY <= "111011"; + when 60 => SATA_MAX_INIT_1_BINARY <= "111100"; + when 61 => SATA_MAX_INIT_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_INIT_1 is not in range 1...61." severity error; + end case; + case SATA_MIN_WAKE_1 is + when 1 => SATA_MIN_WAKE_1_BINARY <= "000001"; + when 2 => SATA_MIN_WAKE_1_BINARY <= "000010"; + when 3 => SATA_MIN_WAKE_1_BINARY <= "000011"; + when 4 => SATA_MIN_WAKE_1_BINARY <= "000100"; + when 5 => SATA_MIN_WAKE_1_BINARY <= "000101"; + when 6 => SATA_MIN_WAKE_1_BINARY <= "000110"; + when 7 => SATA_MIN_WAKE_1_BINARY <= "000111"; + when 8 => SATA_MIN_WAKE_1_BINARY <= "001000"; + when 9 => SATA_MIN_WAKE_1_BINARY <= "001001"; + when 10 => SATA_MIN_WAKE_1_BINARY <= "001010"; + when 11 => SATA_MIN_WAKE_1_BINARY <= "001011"; + when 12 => SATA_MIN_WAKE_1_BINARY <= "001100"; + when 13 => SATA_MIN_WAKE_1_BINARY <= "001101"; + when 14 => SATA_MIN_WAKE_1_BINARY <= "001110"; + when 15 => SATA_MIN_WAKE_1_BINARY <= "001111"; + when 16 => SATA_MIN_WAKE_1_BINARY <= "010000"; + when 17 => SATA_MIN_WAKE_1_BINARY <= "010001"; + when 18 => SATA_MIN_WAKE_1_BINARY <= "010010"; + when 19 => SATA_MIN_WAKE_1_BINARY <= "010011"; + when 20 => SATA_MIN_WAKE_1_BINARY <= "010100"; + when 21 => SATA_MIN_WAKE_1_BINARY <= "010101"; + when 22 => SATA_MIN_WAKE_1_BINARY <= "010110"; + when 23 => SATA_MIN_WAKE_1_BINARY <= "010111"; + when 24 => SATA_MIN_WAKE_1_BINARY <= "011000"; + when 25 => SATA_MIN_WAKE_1_BINARY <= "011001"; + when 26 => SATA_MIN_WAKE_1_BINARY <= "011010"; + when 27 => SATA_MIN_WAKE_1_BINARY <= "011011"; + when 28 => SATA_MIN_WAKE_1_BINARY <= "011100"; + when 29 => SATA_MIN_WAKE_1_BINARY <= "011101"; + when 30 => SATA_MIN_WAKE_1_BINARY <= "011110"; + when 31 => SATA_MIN_WAKE_1_BINARY <= "011111"; + when 32 => SATA_MIN_WAKE_1_BINARY <= "100000"; + when 33 => SATA_MIN_WAKE_1_BINARY <= "100001"; + when 34 => SATA_MIN_WAKE_1_BINARY <= "100010"; + when 35 => SATA_MIN_WAKE_1_BINARY <= "100011"; + when 36 => SATA_MIN_WAKE_1_BINARY <= "100100"; + when 37 => SATA_MIN_WAKE_1_BINARY <= "100101"; + when 38 => SATA_MIN_WAKE_1_BINARY <= "100110"; + when 39 => SATA_MIN_WAKE_1_BINARY <= "100111"; + when 40 => SATA_MIN_WAKE_1_BINARY <= "101000"; + when 41 => SATA_MIN_WAKE_1_BINARY <= "101001"; + when 42 => SATA_MIN_WAKE_1_BINARY <= "101010"; + when 43 => SATA_MIN_WAKE_1_BINARY <= "101011"; + when 44 => SATA_MIN_WAKE_1_BINARY <= "101100"; + when 45 => SATA_MIN_WAKE_1_BINARY <= "101101"; + when 46 => SATA_MIN_WAKE_1_BINARY <= "101110"; + when 47 => SATA_MIN_WAKE_1_BINARY <= "101111"; + when 48 => SATA_MIN_WAKE_1_BINARY <= "110000"; + when 49 => SATA_MIN_WAKE_1_BINARY <= "110001"; + when 50 => SATA_MIN_WAKE_1_BINARY <= "110010"; + when 51 => SATA_MIN_WAKE_1_BINARY <= "110011"; + when 52 => SATA_MIN_WAKE_1_BINARY <= "110100"; + when 53 => SATA_MIN_WAKE_1_BINARY <= "110101"; + when 54 => SATA_MIN_WAKE_1_BINARY <= "110110"; + when 55 => SATA_MIN_WAKE_1_BINARY <= "110111"; + when 56 => SATA_MIN_WAKE_1_BINARY <= "111000"; + when 57 => SATA_MIN_WAKE_1_BINARY <= "111001"; + when 58 => SATA_MIN_WAKE_1_BINARY <= "111010"; + when 59 => SATA_MIN_WAKE_1_BINARY <= "111011"; + when 60 => SATA_MIN_WAKE_1_BINARY <= "111100"; + when 61 => SATA_MIN_WAKE_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_WAKE_1 is not in range 1...61." severity error; + end case; + case SATA_MAX_WAKE_1 is + when 1 => SATA_MAX_WAKE_1_BINARY <= "000001"; + when 2 => SATA_MAX_WAKE_1_BINARY <= "000010"; + when 3 => SATA_MAX_WAKE_1_BINARY <= "000011"; + when 4 => SATA_MAX_WAKE_1_BINARY <= "000100"; + when 5 => SATA_MAX_WAKE_1_BINARY <= "000101"; + when 6 => SATA_MAX_WAKE_1_BINARY <= "000110"; + when 7 => SATA_MAX_WAKE_1_BINARY <= "000111"; + when 8 => SATA_MAX_WAKE_1_BINARY <= "001000"; + when 9 => SATA_MAX_WAKE_1_BINARY <= "001001"; + when 10 => SATA_MAX_WAKE_1_BINARY <= "001010"; + when 11 => SATA_MAX_WAKE_1_BINARY <= "001011"; + when 12 => SATA_MAX_WAKE_1_BINARY <= "001100"; + when 13 => SATA_MAX_WAKE_1_BINARY <= "001101"; + when 14 => SATA_MAX_WAKE_1_BINARY <= "001110"; + when 15 => SATA_MAX_WAKE_1_BINARY <= "001111"; + when 16 => SATA_MAX_WAKE_1_BINARY <= "010000"; + when 17 => SATA_MAX_WAKE_1_BINARY <= "010001"; + when 18 => SATA_MAX_WAKE_1_BINARY <= "010010"; + when 19 => SATA_MAX_WAKE_1_BINARY <= "010011"; + when 20 => SATA_MAX_WAKE_1_BINARY <= "010100"; + when 21 => SATA_MAX_WAKE_1_BINARY <= "010101"; + when 22 => SATA_MAX_WAKE_1_BINARY <= "010110"; + when 23 => SATA_MAX_WAKE_1_BINARY <= "010111"; + when 24 => SATA_MAX_WAKE_1_BINARY <= "011000"; + when 25 => SATA_MAX_WAKE_1_BINARY <= "011001"; + when 26 => SATA_MAX_WAKE_1_BINARY <= "011010"; + when 27 => SATA_MAX_WAKE_1_BINARY <= "011011"; + when 28 => SATA_MAX_WAKE_1_BINARY <= "011100"; + when 29 => SATA_MAX_WAKE_1_BINARY <= "011101"; + when 30 => SATA_MAX_WAKE_1_BINARY <= "011110"; + when 31 => SATA_MAX_WAKE_1_BINARY <= "011111"; + when 32 => SATA_MAX_WAKE_1_BINARY <= "100000"; + when 33 => SATA_MAX_WAKE_1_BINARY <= "100001"; + when 34 => SATA_MAX_WAKE_1_BINARY <= "100010"; + when 35 => SATA_MAX_WAKE_1_BINARY <= "100011"; + when 36 => SATA_MAX_WAKE_1_BINARY <= "100100"; + when 37 => SATA_MAX_WAKE_1_BINARY <= "100101"; + when 38 => SATA_MAX_WAKE_1_BINARY <= "100110"; + when 39 => SATA_MAX_WAKE_1_BINARY <= "100111"; + when 40 => SATA_MAX_WAKE_1_BINARY <= "101000"; + when 41 => SATA_MAX_WAKE_1_BINARY <= "101001"; + when 42 => SATA_MAX_WAKE_1_BINARY <= "101010"; + when 43 => SATA_MAX_WAKE_1_BINARY <= "101011"; + when 44 => SATA_MAX_WAKE_1_BINARY <= "101100"; + when 45 => SATA_MAX_WAKE_1_BINARY <= "101101"; + when 46 => SATA_MAX_WAKE_1_BINARY <= "101110"; + when 47 => SATA_MAX_WAKE_1_BINARY <= "101111"; + when 48 => SATA_MAX_WAKE_1_BINARY <= "110000"; + when 49 => SATA_MAX_WAKE_1_BINARY <= "110001"; + when 50 => SATA_MAX_WAKE_1_BINARY <= "110010"; + when 51 => SATA_MAX_WAKE_1_BINARY <= "110011"; + when 52 => SATA_MAX_WAKE_1_BINARY <= "110100"; + when 53 => SATA_MAX_WAKE_1_BINARY <= "110101"; + when 54 => SATA_MAX_WAKE_1_BINARY <= "110110"; + when 55 => SATA_MAX_WAKE_1_BINARY <= "110111"; + when 56 => SATA_MAX_WAKE_1_BINARY <= "111000"; + when 57 => SATA_MAX_WAKE_1_BINARY <= "111001"; + when 58 => SATA_MAX_WAKE_1_BINARY <= "111010"; + when 59 => SATA_MAX_WAKE_1_BINARY <= "111011"; + when 60 => SATA_MAX_WAKE_1_BINARY <= "111100"; + when 61 => SATA_MAX_WAKE_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_WAKE_1 is not in range 1...61." severity error; + end case; + case CLK25_DIVIDER is + when 1 => CLK25_DIVIDER_BINARY <= "000"; + when 2 => CLK25_DIVIDER_BINARY <= "001"; + when 3 => CLK25_DIVIDER_BINARY <= "010"; + when 4 => CLK25_DIVIDER_BINARY <= "011"; + when 5 => CLK25_DIVIDER_BINARY <= "100"; + when 6 => CLK25_DIVIDER_BINARY <= "101"; + when 10 => CLK25_DIVIDER_BINARY <= "110"; + when 12 => CLK25_DIVIDER_BINARY <= "111"; + when others => assert FALSE report "Error : CLK25_DIVIDER is not in 1, 2, 3, 4, 5, 6, 10, 12." severity error; + end case; + case OVERSAMPLE_MODE is + when FALSE => OVERSAMPLE_MODE_BINARY <= '0'; + when TRUE => OVERSAMPLE_MODE_BINARY <= '1'; + when others => assert FALSE report "Error : OVERSAMPLE_MODE is neither TRUE nor FALSE." severity error; + end case; + case SIM_GTPRESET_SPEEDUP is + when 0 => SIM_GTPRESET_SPEEDUP_BINARY <= '0'; + when 1 => SIM_GTPRESET_SPEEDUP_BINARY <= '1'; + when others => assert FALSE report "Error : SIM_GTPRESET_SPEEDUP is not in 0, 1." severity error; + end case; +-- case SIM_MODE is + if((SIM_MODE = "LEGACY") or (SIM_MODE = "legacy")) then + SIM_MODE_BINARY <= '1'; + elsif((SIM_MODE = "FAST") or (SIM_MODE = "fast")) then + SIM_MODE_BINARY <= '0'; + else + assert FALSE report "Error : SIM_MODE = is not LEGACY, FAST." severity error; + end if; +-- end case; + case SIM_RECEIVER_DETECT_PASS0 is + when FALSE => SIM_RECEIVER_DETECT_PASS0_BINARY <= '0'; + when TRUE => SIM_RECEIVER_DETECT_PASS0_BINARY <= '1'; + when others => assert FALSE report "Error : SIM_RECEIVER_DETECT_PASS0 is neither TRUE nor FALSE." severity error; + end case; + case SIM_RECEIVER_DETECT_PASS1 is + when FALSE => SIM_RECEIVER_DETECT_PASS1_BINARY <= '0'; + when TRUE => SIM_RECEIVER_DETECT_PASS1_BINARY <= '1'; + when others => assert FALSE report "Error : SIM_RECEIVER_DETECT_PASS1 is neither TRUE nor FALSE." severity error; + end case; + wait; + end process INIPROC; + + TIMING : process + +-- Pin timing violations (clock input pins) + +-- Pin Timing Violations (all input pins) + +-- Output Pin glitch declaration + variable REFCLKOUT_GlitchData : VitalGlitchDataType; + variable RXRECCLK0_GlitchData : VitalGlitchDataType; + variable TXOUTCLK0_GlitchData : VitalGlitchDataType; + variable RXRECCLK1_GlitchData : VitalGlitchDataType; + variable TXOUTCLK1_GlitchData : VitalGlitchDataType; + variable TXP0_GlitchData : VitalGlitchDataType; + variable TXN0_GlitchData : VitalGlitchDataType; + variable TXP1_GlitchData : VitalGlitchDataType; + variable TXN1_GlitchData : VitalGlitchDataType; + variable RXDATA00_GlitchData : VitalGlitchDataType; + variable RXDATA01_GlitchData : VitalGlitchDataType; + variable RXDATA02_GlitchData : VitalGlitchDataType; + variable RXDATA03_GlitchData : VitalGlitchDataType; + variable RXDATA04_GlitchData : VitalGlitchDataType; + variable RXDATA05_GlitchData : VitalGlitchDataType; + variable RXDATA06_GlitchData : VitalGlitchDataType; + variable RXDATA07_GlitchData : VitalGlitchDataType; + variable RXDATA08_GlitchData : VitalGlitchDataType; + variable RXDATA09_GlitchData : VitalGlitchDataType; + variable RXDATA010_GlitchData : VitalGlitchDataType; + variable RXDATA011_GlitchData : VitalGlitchDataType; + variable RXDATA012_GlitchData : VitalGlitchDataType; + variable RXDATA013_GlitchData : VitalGlitchDataType; + variable RXDATA014_GlitchData : VitalGlitchDataType; + variable RXDATA015_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE00_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE01_GlitchData : VitalGlitchDataType; + variable RXDISPERR00_GlitchData : VitalGlitchDataType; + variable RXDISPERR01_GlitchData : VitalGlitchDataType; + variable RXCHARISK00_GlitchData : VitalGlitchDataType; + variable RXCHARISK01_GlitchData : VitalGlitchDataType; + variable RXRUNDISP00_GlitchData : VitalGlitchDataType; + variable RXRUNDISP01_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA00_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA01_GlitchData : VitalGlitchDataType; + variable RXVALID0_GlitchData : VitalGlitchDataType; + variable RXDATA10_GlitchData : VitalGlitchDataType; + variable RXDATA11_GlitchData : VitalGlitchDataType; + variable RXDATA12_GlitchData : VitalGlitchDataType; + variable RXDATA13_GlitchData : VitalGlitchDataType; + variable RXDATA14_GlitchData : VitalGlitchDataType; + variable RXDATA15_GlitchData : VitalGlitchDataType; + variable RXDATA16_GlitchData : VitalGlitchDataType; + variable RXDATA17_GlitchData : VitalGlitchDataType; + variable RXDATA18_GlitchData : VitalGlitchDataType; + variable RXDATA19_GlitchData : VitalGlitchDataType; + variable RXDATA110_GlitchData : VitalGlitchDataType; + variable RXDATA111_GlitchData : VitalGlitchDataType; + variable RXDATA112_GlitchData : VitalGlitchDataType; + variable RXDATA113_GlitchData : VitalGlitchDataType; + variable RXDATA114_GlitchData : VitalGlitchDataType; + variable RXDATA115_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE10_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE11_GlitchData : VitalGlitchDataType; + variable RXDISPERR10_GlitchData : VitalGlitchDataType; + variable RXDISPERR11_GlitchData : VitalGlitchDataType; + variable RXCHARISK10_GlitchData : VitalGlitchDataType; + variable RXCHARISK11_GlitchData : VitalGlitchDataType; + variable RXRUNDISP10_GlitchData : VitalGlitchDataType; + variable RXRUNDISP11_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA10_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA11_GlitchData : VitalGlitchDataType; + variable RXVALID1_GlitchData : VitalGlitchDataType; + variable RESETDONE0_GlitchData : VitalGlitchDataType; + variable RESETDONE1_GlitchData : VitalGlitchDataType; + variable TXKERR00_GlitchData : VitalGlitchDataType; + variable TXKERR01_GlitchData : VitalGlitchDataType; + variable TXRUNDISP00_GlitchData : VitalGlitchDataType; + variable TXRUNDISP01_GlitchData : VitalGlitchDataType; + variable TXBUFSTATUS00_GlitchData : VitalGlitchDataType; + variable TXBUFSTATUS01_GlitchData : VitalGlitchDataType; + variable TXKERR10_GlitchData : VitalGlitchDataType; + variable TXKERR11_GlitchData : VitalGlitchDataType; + variable TXRUNDISP10_GlitchData : VitalGlitchDataType; + variable TXRUNDISP11_GlitchData : VitalGlitchDataType; + variable TXBUFSTATUS10_GlitchData : VitalGlitchDataType; + variable TXBUFSTATUS11_GlitchData : VitalGlitchDataType; + variable RXCOMMADET0_GlitchData : VitalGlitchDataType; + variable RXBYTEREALIGN0_GlitchData : VitalGlitchDataType; + variable RXBYTEISALIGNED0_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC00_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC01_GlitchData : VitalGlitchDataType; + variable RXCHBONDO00_GlitchData : VitalGlitchDataType; + variable RXCHBONDO01_GlitchData : VitalGlitchDataType; + variable RXCHBONDO02_GlitchData : VitalGlitchDataType; + variable RXCHANBONDSEQ0_GlitchData : VitalGlitchDataType; + variable RXCHANREALIGN0_GlitchData : VitalGlitchDataType; + variable RXCHANISALIGNED0_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS00_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS01_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS02_GlitchData : VitalGlitchDataType; + variable RXCOMMADET1_GlitchData : VitalGlitchDataType; + variable RXBYTEREALIGN1_GlitchData : VitalGlitchDataType; + variable RXBYTEISALIGNED1_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC10_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC11_GlitchData : VitalGlitchDataType; + variable RXCHBONDO10_GlitchData : VitalGlitchDataType; + variable RXCHBONDO11_GlitchData : VitalGlitchDataType; + variable RXCHBONDO12_GlitchData : VitalGlitchDataType; + variable RXCHANBONDSEQ1_GlitchData : VitalGlitchDataType; + variable RXCHANREALIGN1_GlitchData : VitalGlitchDataType; + variable RXCHANISALIGNED1_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS10_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS11_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS12_GlitchData : VitalGlitchDataType; + variable PHYSTATUS0_GlitchData : VitalGlitchDataType; + variable PHYSTATUS1_GlitchData : VitalGlitchDataType; + variable RXELECIDLE0_GlitchData : VitalGlitchDataType; + variable RXSTATUS00_GlitchData : VitalGlitchDataType; + variable RXSTATUS01_GlitchData : VitalGlitchDataType; + variable RXSTATUS02_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT00_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT01_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT02_GlitchData : VitalGlitchDataType; + variable RXELECIDLE1_GlitchData : VitalGlitchDataType; + variable RXSTATUS10_GlitchData : VitalGlitchDataType; + variable RXSTATUS11_GlitchData : VitalGlitchDataType; + variable RXSTATUS12_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT10_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT11_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT12_GlitchData : VitalGlitchDataType; + variable PLLLKDET_GlitchData : VitalGlitchDataType; + variable RXPRBSERR0_GlitchData : VitalGlitchDataType; + variable RXPRBSERR1_GlitchData : VitalGlitchDataType; + variable DO0_GlitchData : VitalGlitchDataType; + variable DO1_GlitchData : VitalGlitchDataType; + variable DO2_GlitchData : VitalGlitchDataType; + variable DO3_GlitchData : VitalGlitchDataType; + variable DO4_GlitchData : VitalGlitchDataType; + variable DO5_GlitchData : VitalGlitchDataType; + variable DO6_GlitchData : VitalGlitchDataType; + variable DO7_GlitchData : VitalGlitchDataType; + variable DO8_GlitchData : VitalGlitchDataType; + variable DO9_GlitchData : VitalGlitchDataType; + variable DO10_GlitchData : VitalGlitchDataType; + variable DO11_GlitchData : VitalGlitchDataType; + variable DO12_GlitchData : VitalGlitchDataType; + variable DO13_GlitchData : VitalGlitchDataType; + variable DO14_GlitchData : VitalGlitchDataType; + variable DO15_GlitchData : VitalGlitchDataType; + variable DRDY_GlitchData : VitalGlitchDataType; + variable RXOVERSAMPLEERR0_GlitchData : VitalGlitchDataType; + variable RXOVERSAMPLEERR1_GlitchData : VitalGlitchDataType; +begin + +-- Output-to-Clock path delay + VitalPathDelay01 + ( + OutSignal => REFCLKOUT, + GlitchData => REFCLKOUT_GlitchData, + OutSignalName => "REFCLKOUT", + OutTemp => REFCLKOUT_OUT, + Paths => (0 => (CLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(0), + GlitchData => RXDATA00_GlitchData, + OutSignalName => "RXDATA0(0)", + OutTemp => RXDATA0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(1), + GlitchData => RXDATA01_GlitchData, + OutSignalName => "RXDATA0(1)", + OutTemp => RXDATA0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(2), + GlitchData => RXDATA02_GlitchData, + OutSignalName => "RXDATA0(2)", + OutTemp => RXDATA0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(3), + GlitchData => RXDATA03_GlitchData, + OutSignalName => "RXDATA0(3)", + OutTemp => RXDATA0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(4), + GlitchData => RXDATA04_GlitchData, + OutSignalName => "RXDATA0(4)", + OutTemp => RXDATA0_OUT(4), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(5), + GlitchData => RXDATA05_GlitchData, + OutSignalName => "RXDATA0(5)", + OutTemp => RXDATA0_OUT(5), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(6), + GlitchData => RXDATA06_GlitchData, + OutSignalName => "RXDATA0(6)", + OutTemp => RXDATA0_OUT(6), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(7), + GlitchData => RXDATA07_GlitchData, + OutSignalName => "RXDATA0(7)", + OutTemp => RXDATA0_OUT(7), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(8), + GlitchData => RXDATA08_GlitchData, + OutSignalName => "RXDATA0(8)", + OutTemp => RXDATA0_OUT(8), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(9), + GlitchData => RXDATA09_GlitchData, + OutSignalName => "RXDATA0(9)", + OutTemp => RXDATA0_OUT(9), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(10), + GlitchData => RXDATA010_GlitchData, + OutSignalName => "RXDATA0(10)", + OutTemp => RXDATA0_OUT(10), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(11), + GlitchData => RXDATA011_GlitchData, + OutSignalName => "RXDATA0(11)", + OutTemp => RXDATA0_OUT(11), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(12), + GlitchData => RXDATA012_GlitchData, + OutSignalName => "RXDATA0(12)", + OutTemp => RXDATA0_OUT(12), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(13), + GlitchData => RXDATA013_GlitchData, + OutSignalName => "RXDATA0(13)", + OutTemp => RXDATA0_OUT(13), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(14), + GlitchData => RXDATA014_GlitchData, + OutSignalName => "RXDATA0(14)", + OutTemp => RXDATA0_OUT(14), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(15), + GlitchData => RXDATA015_GlitchData, + OutSignalName => "RXDATA0(15)", + OutTemp => RXDATA0_OUT(15), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE0(0), + GlitchData => RXNOTINTABLE00_GlitchData, + OutSignalName => "RXNOTINTABLE0(0)", + OutTemp => RXNOTINTABLE0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE0(1), + GlitchData => RXNOTINTABLE01_GlitchData, + OutSignalName => "RXNOTINTABLE0(1)", + OutTemp => RXNOTINTABLE0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR0(0), + GlitchData => RXDISPERR00_GlitchData, + OutSignalName => "RXDISPERR0(0)", + OutTemp => RXDISPERR0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR0(1), + GlitchData => RXDISPERR01_GlitchData, + OutSignalName => "RXDISPERR0(1)", + OutTemp => RXDISPERR0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK0(0), + GlitchData => RXCHARISK00_GlitchData, + OutSignalName => "RXCHARISK0(0)", + OutTemp => RXCHARISK0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK0(1), + GlitchData => RXCHARISK01_GlitchData, + OutSignalName => "RXCHARISK0(1)", + OutTemp => RXCHARISK0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP0(0), + GlitchData => RXRUNDISP00_GlitchData, + OutSignalName => "RXRUNDISP0(0)", + OutTemp => RXRUNDISP0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP0(1), + GlitchData => RXRUNDISP01_GlitchData, + OutSignalName => "RXRUNDISP0(1)", + OutTemp => RXRUNDISP0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA0(0), + GlitchData => RXCHARISCOMMA00_GlitchData, + OutSignalName => "RXCHARISCOMMA0(0)", + OutTemp => RXCHARISCOMMA0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA0(1), + GlitchData => RXCHARISCOMMA01_GlitchData, + OutSignalName => "RXCHARISCOMMA0(1)", + OutTemp => RXCHARISCOMMA0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXVALID0, + GlitchData => RXVALID0_GlitchData, + OutSignalName => "RXVALID0", + OutTemp => RXVALID0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(0), + GlitchData => RXDATA10_GlitchData, + OutSignalName => "RXDATA1(0)", + OutTemp => RXDATA1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(1), + GlitchData => RXDATA11_GlitchData, + OutSignalName => "RXDATA1(1)", + OutTemp => RXDATA1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(2), + GlitchData => RXDATA12_GlitchData, + OutSignalName => "RXDATA1(2)", + OutTemp => RXDATA1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(3), + GlitchData => RXDATA13_GlitchData, + OutSignalName => "RXDATA1(3)", + OutTemp => RXDATA1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(4), + GlitchData => RXDATA14_GlitchData, + OutSignalName => "RXDATA1(4)", + OutTemp => RXDATA1_OUT(4), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(5), + GlitchData => RXDATA15_GlitchData, + OutSignalName => "RXDATA1(5)", + OutTemp => RXDATA1_OUT(5), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(6), + GlitchData => RXDATA16_GlitchData, + OutSignalName => "RXDATA1(6)", + OutTemp => RXDATA1_OUT(6), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(7), + GlitchData => RXDATA17_GlitchData, + OutSignalName => "RXDATA1(7)", + OutTemp => RXDATA1_OUT(7), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(8), + GlitchData => RXDATA18_GlitchData, + OutSignalName => "RXDATA1(8)", + OutTemp => RXDATA1_OUT(8), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(9), + GlitchData => RXDATA19_GlitchData, + OutSignalName => "RXDATA1(9)", + OutTemp => RXDATA1_OUT(9), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(10), + GlitchData => RXDATA110_GlitchData, + OutSignalName => "RXDATA1(10)", + OutTemp => RXDATA1_OUT(10), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(11), + GlitchData => RXDATA111_GlitchData, + OutSignalName => "RXDATA1(11)", + OutTemp => RXDATA1_OUT(11), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(12), + GlitchData => RXDATA112_GlitchData, + OutSignalName => "RXDATA1(12)", + OutTemp => RXDATA1_OUT(12), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(13), + GlitchData => RXDATA113_GlitchData, + OutSignalName => "RXDATA1(13)", + OutTemp => RXDATA1_OUT(13), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(14), + GlitchData => RXDATA114_GlitchData, + OutSignalName => "RXDATA1(14)", + OutTemp => RXDATA1_OUT(14), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(15), + GlitchData => RXDATA115_GlitchData, + OutSignalName => "RXDATA1(15)", + OutTemp => RXDATA1_OUT(15), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE1(0), + GlitchData => RXNOTINTABLE10_GlitchData, + OutSignalName => "RXNOTINTABLE1(0)", + OutTemp => RXNOTINTABLE1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE1(1), + GlitchData => RXNOTINTABLE11_GlitchData, + OutSignalName => "RXNOTINTABLE1(1)", + OutTemp => RXNOTINTABLE1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR1(0), + GlitchData => RXDISPERR10_GlitchData, + OutSignalName => "RXDISPERR1(0)", + OutTemp => RXDISPERR1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR1(1), + GlitchData => RXDISPERR11_GlitchData, + OutSignalName => "RXDISPERR1(1)", + OutTemp => RXDISPERR1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK1(0), + GlitchData => RXCHARISK10_GlitchData, + OutSignalName => "RXCHARISK1(0)", + OutTemp => RXCHARISK1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK1(1), + GlitchData => RXCHARISK11_GlitchData, + OutSignalName => "RXCHARISK1(1)", + OutTemp => RXCHARISK1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP1(0), + GlitchData => RXRUNDISP10_GlitchData, + OutSignalName => "RXRUNDISP1(0)", + OutTemp => RXRUNDISP1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP1(1), + GlitchData => RXRUNDISP11_GlitchData, + OutSignalName => "RXRUNDISP1(1)", + OutTemp => RXRUNDISP1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA1(0), + GlitchData => RXCHARISCOMMA10_GlitchData, + OutSignalName => "RXCHARISCOMMA1(0)", + OutTemp => RXCHARISCOMMA1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA1(1), + GlitchData => RXCHARISCOMMA11_GlitchData, + OutSignalName => "RXCHARISCOMMA1(1)", + OutTemp => RXCHARISCOMMA1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXVALID1, + GlitchData => RXVALID1_GlitchData, + OutSignalName => "RXVALID1", + OutTemp => RXVALID1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR0(0), + GlitchData => TXKERR00_GlitchData, + OutSignalName => "TXKERR0(0)", + OutTemp => TXKERR0_OUT(0), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR0(1), + GlitchData => TXKERR01_GlitchData, + OutSignalName => "TXKERR0(1)", + OutTemp => TXKERR0_OUT(1), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP0(0), + GlitchData => TXRUNDISP00_GlitchData, + OutSignalName => "TXRUNDISP0(0)", + OutTemp => TXRUNDISP0_OUT(0), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP0(1), + GlitchData => TXRUNDISP01_GlitchData, + OutSignalName => "TXRUNDISP0(1)", + OutTemp => TXRUNDISP0_OUT(1), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXBUFSTATUS0(0), + GlitchData => TXBUFSTATUS00_GlitchData, + OutSignalName => "TXBUFSTATUS0(0)", + OutTemp => TXBUFSTATUS0_OUT(0), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXBUFSTATUS0(1), + GlitchData => TXBUFSTATUS01_GlitchData, + OutSignalName => "TXBUFSTATUS0(1)", + OutTemp => TXBUFSTATUS0_OUT(1), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR1(0), + GlitchData => TXKERR10_GlitchData, + OutSignalName => "TXKERR1(0)", + OutTemp => TXKERR1_OUT(0), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR1(1), + GlitchData => TXKERR11_GlitchData, + OutSignalName => "TXKERR1(1)", + OutTemp => TXKERR1_OUT(1), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP1(0), + GlitchData => TXRUNDISP10_GlitchData, + OutSignalName => "TXRUNDISP1(0)", + OutTemp => TXRUNDISP1_OUT(0), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP1(1), + GlitchData => TXRUNDISP11_GlitchData, + OutSignalName => "TXRUNDISP1(1)", + OutTemp => TXRUNDISP1_OUT(1), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXBUFSTATUS1(0), + GlitchData => TXBUFSTATUS10_GlitchData, + OutSignalName => "TXBUFSTATUS1(0)", + OutTemp => TXBUFSTATUS1_OUT(0), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXBUFSTATUS1(1), + GlitchData => TXBUFSTATUS11_GlitchData, + OutSignalName => "TXBUFSTATUS1(1)", + OutTemp => TXBUFSTATUS1_OUT(1), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCOMMADET0, + GlitchData => RXCOMMADET0_GlitchData, + OutSignalName => "RXCOMMADET0", + OutTemp => RXCOMMADET0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBYTEREALIGN0, + GlitchData => RXBYTEREALIGN0_GlitchData, + OutSignalName => "RXBYTEREALIGN0", + OutTemp => RXBYTEREALIGN0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBYTEISALIGNED0, + GlitchData => RXBYTEISALIGNED0_GlitchData, + OutSignalName => "RXBYTEISALIGNED0", + OutTemp => RXBYTEISALIGNED0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC0(0), + GlitchData => RXLOSSOFSYNC00_GlitchData, + OutSignalName => "RXLOSSOFSYNC0(0)", + OutTemp => RXLOSSOFSYNC0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC0(1), + GlitchData => RXLOSSOFSYNC01_GlitchData, + OutSignalName => "RXLOSSOFSYNC0(1)", + OutTemp => RXLOSSOFSYNC0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO0(0), + GlitchData => RXCHBONDO00_GlitchData, + OutSignalName => "RXCHBONDO0(0)", + OutTemp => RXCHBONDO0_OUT(0), + Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO0(1), + GlitchData => RXCHBONDO01_GlitchData, + OutSignalName => "RXCHBONDO0(1)", + OutTemp => RXCHBONDO0_OUT(1), + Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO0(2), + GlitchData => RXCHBONDO02_GlitchData, + OutSignalName => "RXCHBONDO0(2)", + OutTemp => RXCHBONDO0_OUT(2), + Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANBONDSEQ0, + GlitchData => RXCHANBONDSEQ0_GlitchData, + OutSignalName => "RXCHANBONDSEQ0", + OutTemp => RXCHANBONDSEQ0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANREALIGN0, + GlitchData => RXCHANREALIGN0_GlitchData, + OutSignalName => "RXCHANREALIGN0", + OutTemp => RXCHANREALIGN0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANISALIGNED0, + GlitchData => RXCHANISALIGNED0_GlitchData, + OutSignalName => "RXCHANISALIGNED0", + OutTemp => RXCHANISALIGNED0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS0(0), + GlitchData => RXBUFSTATUS00_GlitchData, + OutSignalName => "RXBUFSTATUS0(0)", + OutTemp => RXBUFSTATUS0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS0(1), + GlitchData => RXBUFSTATUS01_GlitchData, + OutSignalName => "RXBUFSTATUS0(1)", + OutTemp => RXBUFSTATUS0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS0(2), + GlitchData => RXBUFSTATUS02_GlitchData, + OutSignalName => "RXBUFSTATUS0(2)", + OutTemp => RXBUFSTATUS0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCOMMADET1, + GlitchData => RXCOMMADET1_GlitchData, + OutSignalName => "RXCOMMADET1", + OutTemp => RXCOMMADET1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBYTEREALIGN1, + GlitchData => RXBYTEREALIGN1_GlitchData, + OutSignalName => "RXBYTEREALIGN1", + OutTemp => RXBYTEREALIGN1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBYTEISALIGNED1, + GlitchData => RXBYTEISALIGNED1_GlitchData, + OutSignalName => "RXBYTEISALIGNED1", + OutTemp => RXBYTEISALIGNED1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC1(0), + GlitchData => RXLOSSOFSYNC10_GlitchData, + OutSignalName => "RXLOSSOFSYNC1(0)", + OutTemp => RXLOSSOFSYNC1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC1(1), + GlitchData => RXLOSSOFSYNC11_GlitchData, + OutSignalName => "RXLOSSOFSYNC1(1)", + OutTemp => RXLOSSOFSYNC1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO1(0), + GlitchData => RXCHBONDO10_GlitchData, + OutSignalName => "RXCHBONDO1(0)", + OutTemp => RXCHBONDO1_OUT(0), + Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO1(1), + GlitchData => RXCHBONDO11_GlitchData, + OutSignalName => "RXCHBONDO1(1)", + OutTemp => RXCHBONDO1_OUT(1), + Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO1(2), + GlitchData => RXCHBONDO12_GlitchData, + OutSignalName => "RXCHBONDO1(2)", + OutTemp => RXCHBONDO1_OUT(2), + Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANBONDSEQ1, + GlitchData => RXCHANBONDSEQ1_GlitchData, + OutSignalName => "RXCHANBONDSEQ1", + OutTemp => RXCHANBONDSEQ1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANREALIGN1, + GlitchData => RXCHANREALIGN1_GlitchData, + OutSignalName => "RXCHANREALIGN1", + OutTemp => RXCHANREALIGN1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANISALIGNED1, + GlitchData => RXCHANISALIGNED1_GlitchData, + OutSignalName => "RXCHANISALIGNED1", + OutTemp => RXCHANISALIGNED1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS1(0), + GlitchData => RXBUFSTATUS10_GlitchData, + OutSignalName => "RXBUFSTATUS1(0)", + OutTemp => RXBUFSTATUS1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS1(1), + GlitchData => RXBUFSTATUS11_GlitchData, + OutSignalName => "RXBUFSTATUS1(1)", + OutTemp => RXBUFSTATUS1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS1(2), + GlitchData => RXBUFSTATUS12_GlitchData, + OutSignalName => "RXBUFSTATUS1(2)", + OutTemp => RXBUFSTATUS1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS0(0), + GlitchData => RXSTATUS00_GlitchData, + OutSignalName => "RXSTATUS0(0)", + OutTemp => RXSTATUS0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS0(1), + GlitchData => RXSTATUS01_GlitchData, + OutSignalName => "RXSTATUS0(1)", + OutTemp => RXSTATUS0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS0(2), + GlitchData => RXSTATUS02_GlitchData, + OutSignalName => "RXSTATUS0(2)", + OutTemp => RXSTATUS0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT0(0), + GlitchData => RXCLKCORCNT00_GlitchData, + OutSignalName => "RXCLKCORCNT0(0)", + OutTemp => RXCLKCORCNT0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT0(1), + GlitchData => RXCLKCORCNT01_GlitchData, + OutSignalName => "RXCLKCORCNT0(1)", + OutTemp => RXCLKCORCNT0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT0(2), + GlitchData => RXCLKCORCNT02_GlitchData, + OutSignalName => "RXCLKCORCNT0(2)", + OutTemp => RXCLKCORCNT0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS1(0), + GlitchData => RXSTATUS10_GlitchData, + OutSignalName => "RXSTATUS1(0)", + OutTemp => RXSTATUS1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS1(1), + GlitchData => RXSTATUS11_GlitchData, + OutSignalName => "RXSTATUS1(1)", + OutTemp => RXSTATUS1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS1(2), + GlitchData => RXSTATUS12_GlitchData, + OutSignalName => "RXSTATUS1(2)", + OutTemp => RXSTATUS1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT1(0), + GlitchData => RXCLKCORCNT10_GlitchData, + OutSignalName => "RXCLKCORCNT1(0)", + OutTemp => RXCLKCORCNT1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT1(1), + GlitchData => RXCLKCORCNT11_GlitchData, + OutSignalName => "RXCLKCORCNT1(1)", + OutTemp => RXCLKCORCNT1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT1(2), + GlitchData => RXCLKCORCNT12_GlitchData, + OutSignalName => "RXCLKCORCNT1(2)", + OutTemp => RXCLKCORCNT1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXPRBSERR0, + GlitchData => RXPRBSERR0_GlitchData, + OutSignalName => "RXPRBSERR0", + OutTemp => RXPRBSERR0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXPRBSERR1, + GlitchData => RXPRBSERR1_GlitchData, + OutSignalName => "RXPRBSERR1", + OutTemp => RXPRBSERR1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(0), + GlitchData => DO0_GlitchData, + OutSignalName => "DO(0)", + OutTemp => DO_OUT(0), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(1), + GlitchData => DO1_GlitchData, + OutSignalName => "DO(1)", + OutTemp => DO_OUT(1), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(2), + GlitchData => DO2_GlitchData, + OutSignalName => "DO(2)", + OutTemp => DO_OUT(2), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(3), + GlitchData => DO3_GlitchData, + OutSignalName => "DO(3)", + OutTemp => DO_OUT(3), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(4), + GlitchData => DO4_GlitchData, + OutSignalName => "DO(4)", + OutTemp => DO_OUT(4), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(5), + GlitchData => DO5_GlitchData, + OutSignalName => "DO(5)", + OutTemp => DO_OUT(5), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(6), + GlitchData => DO6_GlitchData, + OutSignalName => "DO(6)", + OutTemp => DO_OUT(6), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(7), + GlitchData => DO7_GlitchData, + OutSignalName => "DO(7)", + OutTemp => DO_OUT(7), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(8), + GlitchData => DO8_GlitchData, + OutSignalName => "DO(8)", + OutTemp => DO_OUT(8), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(9), + GlitchData => DO9_GlitchData, + OutSignalName => "DO(9)", + OutTemp => DO_OUT(9), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(10), + GlitchData => DO10_GlitchData, + OutSignalName => "DO(10)", + OutTemp => DO_OUT(10), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(11), + GlitchData => DO11_GlitchData, + OutSignalName => "DO(11)", + OutTemp => DO_OUT(11), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(12), + GlitchData => DO12_GlitchData, + OutSignalName => "DO(12)", + OutTemp => DO_OUT(12), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(13), + GlitchData => DO13_GlitchData, + OutSignalName => "DO(13)", + OutTemp => DO_OUT(13), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(14), + GlitchData => DO14_GlitchData, + OutSignalName => "DO(14)", + OutTemp => DO_OUT(14), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(15), + GlitchData => DO15_GlitchData, + OutSignalName => "DO(15)", + OutTemp => DO_OUT(15), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DRDY, + GlitchData => DRDY_GlitchData, + OutSignalName => "DRDY", + OutTemp => DRDY_OUT, + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXOVERSAMPLEERR0, + GlitchData => RXOVERSAMPLEERR0_GlitchData, + OutSignalName => "RXOVERSAMPLEERR0", + OutTemp => RXOVERSAMPLEERR0_OUT, + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXOVERSAMPLEERR1, + GlitchData => RXOVERSAMPLEERR1_GlitchData, + OutSignalName => "RXOVERSAMPLEERR1", + OutTemp => RXOVERSAMPLEERR1_OUT, + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + + +-- Wait signal (input/output pins) + wait on + DO_out, + DRDY_out, + REFCLKOUT_out, + RXBUFSTATUS0_out, + RXBUFSTATUS1_out, + RXBYTEISALIGNED0_out, + RXBYTEISALIGNED1_out, + RXBYTEREALIGN0_out, + RXBYTEREALIGN1_out, + RXCHANBONDSEQ0_out, + RXCHANBONDSEQ1_out, + RXCHANISALIGNED0_out, + RXCHANISALIGNED1_out, + RXCHANREALIGN0_out, + RXCHANREALIGN1_out, + RXCHARISCOMMA0_out, + RXCHARISCOMMA1_out, + RXCHARISK0_out, + RXCHARISK1_out, + RXCHBONDO0_out, + RXCHBONDO1_out, + RXCLKCORCNT0_out, + RXCLKCORCNT1_out, + RXCOMMADET0_out, + RXCOMMADET1_out, + RXDATA0_out, + RXDATA1_out, + RXDISPERR0_out, + RXDISPERR1_out, + RXLOSSOFSYNC0_out, + RXLOSSOFSYNC1_out, + RXNOTINTABLE0_out, + RXNOTINTABLE1_out, + RXOVERSAMPLEERR0_out, + RXOVERSAMPLEERR1_out, + RXPRBSERR0_out, + RXPRBSERR1_out, + RXRUNDISP0_out, + RXRUNDISP1_out, + RXSTATUS0_out, + RXSTATUS1_out, + RXVALID0_out, + RXVALID1_out, + TXBUFSTATUS0_out, + TXBUFSTATUS1_out, + TXKERR0_out, + TXKERR1_out, + TXRUNDISP0_out, + TXRUNDISP1_out, + + CLKIN_ipd, + DADDR_ipd, + DCLK_ipd, + DEN_ipd, + DI_ipd, + DWE_ipd, + GTPRESET_ipd, + GTPTEST_ipd, + INTDATAWIDTH_ipd, + LOOPBACK0_ipd, + LOOPBACK1_ipd, + PLLLKDETEN_ipd, + PLLPOWERDOWN_ipd, + PRBSCNTRESET0_ipd, + PRBSCNTRESET1_ipd, + REFCLKPWRDNB_ipd, + RXBUFRESET0_ipd, + RXBUFRESET1_ipd, + RXCDRRESET0_ipd, + RXCDRRESET1_ipd, + RXCHBONDI0_ipd, + RXCHBONDI1_ipd, + RXCOMMADETUSE0_ipd, + RXCOMMADETUSE1_ipd, + RXDATAWIDTH0_ipd, + RXDATAWIDTH1_ipd, + RXDEC8B10BUSE0_ipd, + RXDEC8B10BUSE1_ipd, + RXELECIDLERESET0_ipd, + RXELECIDLERESET1_ipd, + RXENCHANSYNC0_ipd, + RXENCHANSYNC1_ipd, + RXENELECIDLERESETB_ipd, + RXENEQB0_ipd, + RXENEQB1_ipd, + RXENMCOMMAALIGN0_ipd, + RXENMCOMMAALIGN1_ipd, + RXENPCOMMAALIGN0_ipd, + RXENPCOMMAALIGN1_ipd, + RXENPRBSTST0_ipd, + RXENPRBSTST1_ipd, + RXENSAMPLEALIGN0_ipd, + RXENSAMPLEALIGN1_ipd, + RXEQMIX0_ipd, + RXEQMIX1_ipd, + RXEQPOLE0_ipd, + RXEQPOLE1_ipd, + RXN0_ipd, + RXN1_ipd, + RXP0_ipd, + RXP1_ipd, + RXPMASETPHASE0_ipd, + RXPMASETPHASE1_ipd, + RXPOLARITY0_ipd, + RXPOLARITY1_ipd, + RXPOWERDOWN0_ipd, + RXPOWERDOWN1_ipd, + RXRESET0_ipd, + RXRESET1_ipd, + RXSLIDE0_ipd, + RXSLIDE1_ipd, + RXUSRCLK0_ipd, + RXUSRCLK1_ipd, + RXUSRCLK20_ipd, + RXUSRCLK21_ipd, + TXBUFDIFFCTRL0_ipd, + TXBUFDIFFCTRL1_ipd, + TXBYPASS8B10B0_ipd, + TXBYPASS8B10B1_ipd, + TXCHARDISPMODE0_ipd, + TXCHARDISPMODE1_ipd, + TXCHARDISPVAL0_ipd, + TXCHARDISPVAL1_ipd, + TXCHARISK0_ipd, + TXCHARISK1_ipd, + TXCOMSTART0_ipd, + TXCOMSTART1_ipd, + TXCOMTYPE0_ipd, + TXCOMTYPE1_ipd, + TXDATA0_ipd, + TXDATA1_ipd, + TXDATAWIDTH0_ipd, + TXDATAWIDTH1_ipd, + TXDETECTRX0_ipd, + TXDETECTRX1_ipd, + TXDIFFCTRL0_ipd, + TXDIFFCTRL1_ipd, + TXELECIDLE0_ipd, + TXELECIDLE1_ipd, + TXENC8B10BUSE0_ipd, + TXENC8B10BUSE1_ipd, + TXENPMAPHASEALIGN_ipd, + TXENPRBSTST0_ipd, + TXENPRBSTST1_ipd, + TXINHIBIT0_ipd, + TXINHIBIT1_ipd, + TXPMASETPHASE_ipd, + TXPOLARITY0_ipd, + TXPOLARITY1_ipd, + TXPOWERDOWN0_ipd, + TXPOWERDOWN1_ipd, + TXPREEMPHASIS0_ipd, + TXPREEMPHASIS1_ipd, + TXRESET0_ipd, + TXRESET1_ipd, + TXUSRCLK0_ipd, + TXUSRCLK1_ipd, + TXUSRCLK20_ipd, + TXUSRCLK21_ipd; + +end process TIMING; + + PHYSTATUS0 <= PHYSTATUS0_out; + PHYSTATUS1 <= PHYSTATUS1_out; + PLLLKDET <= PLLLKDET_out; + RESETDONE0 <= RESETDONE0_out; + RESETDONE1 <= RESETDONE1_out; + RXELECIDLE0 <= RXELECIDLE0_out; + RXELECIDLE1 <= RXELECIDLE1_out; + RXRECCLK0 <= RXRECCLK0_out; + RXRECCLK1 <= RXRECCLK1_out; + TXN0 <= TXN0_out; + TXN1 <= TXN1_out; + TXOUTCLK0 <= TXOUTCLK0_out; + TXOUTCLK1 <= TXOUTCLK1_out; + TXP0 <= TXP0_out; + TXP1 <= TXP1_out; + +end GTP_DUAL_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2006 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / PCI Express +-- /___/ /\ Filename : pcie_ep.vhd +-- \ \ / \ Timestamp : Thu Dec 8 2005 +-- \___\/\___\ +-- +-- Revision: +-- 08/14/06 - CR#421379 - Initial version. +-- 08/31/06 - BVT#1001 - Added PCIE_INTERNAL_1_1 component +-- 08/13/06 - CR#423912 - Added zero vectors (std_logic_vector) +-- 10/16/06 - CR#427095 - Modified generic map SWIFT instantiation to match spreadsheets +-- 12/05/06 - CR#420518 - Added input pin LLKRXDSTCONTREQN +-- 12/05/06 - CR#420518 - Added input pin LLKRXDSTCONTREQN +-- 03/13/07 - CR#435993 - Add LLKTXCONFIGREADYN +-- End Revision + +----- CELL PCIE_EP ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity PCIE_EP is +generic ( + ACTIVELANESIN : bit_vector := X"01"; + AERBASEPTR : bit_vector := X"110"; + AERCAPABILITYNEXTPTR : bit_vector := X"138"; + BAR0ADDRWIDTH : integer := 0; + BAR0EXIST : boolean := TRUE; + BAR0IOMEMN : integer := 0; + BAR0MASKWIDTH : bit_vector := X"14"; + BAR0PREFETCHABLE : boolean := TRUE; + BAR1ADDRWIDTH : integer := 0; + BAR1EXIST : boolean := FALSE; + BAR1IOMEMN : integer := 0; + BAR1MASKWIDTH : bit_vector := X"00"; + BAR1PREFETCHABLE : boolean := FALSE; + BAR2ADDRWIDTH : integer := 0; + BAR2EXIST : boolean := FALSE; + BAR2IOMEMN : integer := 0; + BAR2MASKWIDTH : bit_vector := X"00"; + BAR2PREFETCHABLE : boolean := FALSE; + BAR3ADDRWIDTH : integer := 0; + BAR3EXIST : boolean := FALSE; + BAR3IOMEMN : integer := 0; + BAR3MASKWIDTH : bit_vector := X"00"; + BAR3PREFETCHABLE : boolean := FALSE; + BAR4ADDRWIDTH : integer := 0; + BAR4EXIST : boolean := FALSE; + BAR4IOMEMN : integer := 0; + BAR4MASKWIDTH : bit_vector := X"00"; + BAR4PREFETCHABLE : boolean := FALSE; + BAR5EXIST : boolean := FALSE; + BAR5IOMEMN : integer := 0; + BAR5MASKWIDTH : bit_vector := X"00"; + BAR5PREFETCHABLE : boolean := FALSE; + CAPABILITIESPOINTER : bit_vector := X"40"; + CARDBUSCISPOINTER : bit_vector := X"00000000"; + CLASSCODE : bit_vector := X"058000"; + CLKDIVIDED : boolean := FALSE; + DEVICECAPABILITYENDPOINTL0SLATENCY : bit_vector := X"0"; + DEVICECAPABILITYENDPOINTL1LATENCY : bit_vector := X"0"; + DEVICEID : bit_vector := X"5050"; + DEVICESERIALNUMBER : bit_vector := X"E000000001000A35"; + DSNBASEPTR : bit_vector := X"148"; + DSNCAPABILITYNEXTPTR : bit_vector := X"154"; + INFINITECOMPLETIONS : boolean := TRUE; + INTERRUPTPIN : bit_vector := X"00"; + L0SEXITLATENCY : integer := 7; + L0SEXITLATENCYCOMCLK : integer := 7; + L1EXITLATENCY : integer := 7; + L1EXITLATENCYCOMCLK : integer := 7; + LINKCAPABILITYASPMSUPPORT : bit_vector := X"1"; + LINKCAPABILITYMAXLINKWIDTH : bit_vector := X"01"; + LINKSTATUSSLOTCLOCKCONFIG : boolean := FALSE; + LOWPRIORITYVCCOUNT : integer := 0; + MSIBASEPTR : bit_vector := X"048"; + MSICAPABILITYMULTIMSGCAP : bit_vector := X"0"; + MSICAPABILITYNEXTPTR : bit_vector := X"60"; + PBBASEPTR : bit_vector := X"138"; + PBCAPABILITYDW0BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW0DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW0PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW0PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW0POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW0TYPE : bit_vector := X"0"; + PBCAPABILITYDW1BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW1DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW1PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW1PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW1POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW1TYPE : bit_vector := X"0"; + PBCAPABILITYDW2BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW2DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW2PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW2PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW2POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW2TYPE : bit_vector := X"0"; + PBCAPABILITYDW3BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW3DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW3PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW3PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW3POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW3TYPE : bit_vector := X"0"; + PBCAPABILITYNEXTPTR : bit_vector := X"148"; + PBCAPABILITYSYSTEMALLOCATED : boolean := FALSE; + PCIECAPABILITYNEXTPTR : bit_vector := X"00"; + PMBASEPTR : bit_vector := X"040"; + PMCAPABILITYAUXCURRENT : bit_vector := X"0"; + PMCAPABILITYD1SUPPORT : boolean := FALSE; + PMCAPABILITYD2SUPPORT : boolean := FALSE; + PMCAPABILITYDSI : boolean := TRUE; + PMCAPABILITYNEXTPTR : bit_vector := X"60"; + PMCAPABILITYPMESUPPORT : bit_vector := X"00"; + PMDATA0 : bit_vector := X"00"; + PMDATA1 : bit_vector := X"00"; + PMDATA2 : bit_vector := X"00"; + PMDATA3 : bit_vector := X"00"; + PMDATA4 : bit_vector := X"00"; + PMDATA5 : bit_vector := X"00"; + PMDATA6 : bit_vector := X"00"; + PMDATA7 : bit_vector := X"00"; + PMDATASCALE0 : integer := 0; + PMDATASCALE1 : integer := 0; + PMDATASCALE2 : integer := 0; + PMDATASCALE3 : integer := 0; + PMDATASCALE4 : integer := 0; + PMDATASCALE5 : integer := 0; + PMDATASCALE6 : integer := 0; + PMDATASCALE7 : integer := 0; + PORTVCCAPABILITYEXTENDEDVCCOUNT : bit_vector := X"0"; + PORTVCCAPABILITYVCARBCAP : bit_vector := X"00"; + PORTVCCAPABILITYVCARBTABLEOFFSET : bit_vector := X"00"; + RESETMODE : boolean := FALSE; + RETRYRAMREADLATENCY : integer := 3; + RETRYRAMSIZE : bit_vector := X"009"; + RETRYRAMWRITELATENCY : integer := 1; + REVISIONID : bit_vector := X"00"; + SUBSYSTEMID : bit_vector := X"5050"; + SUBSYSTEMVENDORID : bit_vector := X"10EE"; + TLRAMREADLATENCY : integer := 3; + TLRAMWRITELATENCY : integer := 1; + TXTSNFTS : integer := 255; + TXTSNFTSCOMCLK : integer := 255; + VC0RXFIFOBASEC : bit_vector := X"0098"; + VC0RXFIFOBASENP : bit_vector := X"0080"; + VC0RXFIFOBASEP : bit_vector := X"0000"; + VC0RXFIFOLIMITC : bit_vector := X"0117"; + VC0RXFIFOLIMITNP : bit_vector := X"0097"; + VC0RXFIFOLIMITP : bit_vector := X"007f"; + VC0TOTALCREDITSCD : bit_vector := X"000"; + VC0TOTALCREDITSCH : bit_vector := X"00"; + VC0TOTALCREDITSNPH : bit_vector := X"08"; + VC0TOTALCREDITSPD : bit_vector := X"034"; + VC0TOTALCREDITSPH : bit_vector := X"08"; + VC0TXFIFOBASEC : bit_vector := X"0098"; + VC0TXFIFOBASENP : bit_vector := X"0080"; + VC0TXFIFOBASEP : bit_vector := X"0000"; + VC0TXFIFOLIMITC : bit_vector := X"0117"; + VC0TXFIFOLIMITNP : bit_vector := X"0097"; + VC0TXFIFOLIMITP : bit_vector := X"007f"; + VC1RXFIFOBASEC : bit_vector := X"0118"; + VC1RXFIFOBASENP : bit_vector := X"0118"; + VC1RXFIFOBASEP : bit_vector := X"0118"; + VC1RXFIFOLIMITC : bit_vector := X"0118"; + VC1RXFIFOLIMITNP : bit_vector := X"0118"; + VC1RXFIFOLIMITP : bit_vector := X"0118"; + VC1TOTALCREDITSCD : bit_vector := X"000"; + VC1TOTALCREDITSCH : bit_vector := X"00"; + VC1TOTALCREDITSNPH : bit_vector := X"00"; + VC1TOTALCREDITSPD : bit_vector := X"000"; + VC1TOTALCREDITSPH : bit_vector := X"00"; + VC1TXFIFOBASEC : bit_vector := X"0118"; + VC1TXFIFOBASENP : bit_vector := X"0118"; + VC1TXFIFOBASEP : bit_vector := X"0118"; + VC1TXFIFOLIMITC : bit_vector := X"0118"; + VC1TXFIFOLIMITNP : bit_vector := X"0118"; + VC1TXFIFOLIMITP : bit_vector := X"0118"; + VCBASEPTR : bit_vector := X"154"; + VCCAPABILITYNEXTPTR : bit_vector := X"000"; + VENDORID : bit_vector := X"10EE"; + XPBASEPTR : bit_vector := X"60"; + XPDEVICEPORTTYPE : bit_vector := X"0"; + XPMAXPAYLOAD : integer := 0 + ); + +port ( + BUSMASTERENABLE : out std_ulogic; + CRMDOHOTRESETN : out std_ulogic; + CRMPWRSOFTRESETN : out std_ulogic; + DLLTXPMDLLPOUTSTANDING : out std_ulogic; + INTERRUPTDISABLE : out std_ulogic; + IOSPACEENABLE : out std_ulogic; + L0CFGLOOPBACKACK : out std_ulogic; + L0COMPLETERID : out std_logic_vector(12 downto 0); + L0DLLERRORVECTOR : out std_logic_vector(6 downto 0); + L0DLLRXACKOUTSTANDING : out std_ulogic; + L0DLLTXNONFCOUTSTANDING : out std_ulogic; + L0DLLTXOUTSTANDING : out std_ulogic; + L0DLLVCSTATUS : out std_logic_vector(7 downto 0); + L0DLUPDOWN : out std_logic_vector(7 downto 0); + L0FIRSTCFGWRITEOCCURRED : out std_ulogic; + L0LTSSMSTATE : out std_logic_vector(3 downto 0); + L0MACENTEREDL0 : out std_ulogic; + L0MACLINKTRAINING : out std_ulogic; + L0MACLINKUP : out std_ulogic; + L0MACNEGOTIATEDLINKWIDTH : out std_logic_vector(3 downto 0); + L0MACNEWSTATEACK : out std_ulogic; + L0MACRXL0SSTATE : out std_ulogic; + L0MSIENABLE0 : out std_ulogic; + L0MULTIMSGEN0 : out std_logic_vector(2 downto 0); + L0PMEACK : out std_ulogic; + L0PMEEN : out std_ulogic; + L0PMEREQOUT : out std_ulogic; + L0PWRL1STATE : out std_ulogic; + L0PWRL23READYSTATE : out std_ulogic; + L0PWRSTATE0 : out std_logic_vector(1 downto 0); + L0PWRTURNOFFREQ : out std_ulogic; + L0PWRTXL0SSTATE : out std_ulogic; + L0RXDLLPM : out std_ulogic; + L0RXDLLPMTYPE : out std_logic_vector(2 downto 0); + L0RXMACLINKERROR : out std_logic_vector(1 downto 0); + L0STATSCFGOTHERRECEIVED : out std_ulogic; + L0STATSCFGOTHERTRANSMITTED : out std_ulogic; + L0STATSCFGRECEIVED : out std_ulogic; + L0STATSCFGTRANSMITTED : out std_ulogic; + L0STATSDLLPRECEIVED : out std_ulogic; + L0STATSDLLPTRANSMITTED : out std_ulogic; + L0STATSOSRECEIVED : out std_ulogic; + L0STATSOSTRANSMITTED : out std_ulogic; + L0STATSTLPRECEIVED : out std_ulogic; + L0STATSTLPTRANSMITTED : out std_ulogic; + L0UNLOCKRECEIVED : out std_ulogic; + LLKRXCHCOMPLETIONAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHNONPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXDATA : out std_logic_vector(63 downto 0); + LLKRXEOFN : out std_ulogic; + LLKRXEOPN : out std_ulogic; + LLKRXPREFERREDTYPE : out std_logic_vector(15 downto 0); + LLKRXSOFN : out std_ulogic; + LLKRXSOPN : out std_ulogic; + LLKRXSRCLASTREQN : out std_ulogic; + LLKRXSRCRDYN : out std_ulogic; + LLKRXVALIDN : out std_logic_vector(1 downto 0); + LLKTCSTATUS : out std_logic_vector(7 downto 0); + LLKTXCHANSPACE : out std_logic_vector(9 downto 0); + LLKTXCHCOMPLETIONREADYN : out std_logic_vector(7 downto 0); + LLKTXCHNONPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCHPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCONFIGREADYN : out std_ulogic; + LLKTXDSTRDYN : out std_ulogic; + MAXPAYLOADSIZE : out std_logic_vector(2 downto 0); + MAXREADREQUESTSIZE : out std_logic_vector(2 downto 0); + MEMSPACEENABLE : out std_ulogic; + MGMTPSO : out std_logic_vector(16 downto 0); + MGMTRDATA : out std_logic_vector(31 downto 0); + MGMTSTATSCREDIT : out std_logic_vector(11 downto 0); + MIMDLLBRADD : out std_logic_vector(11 downto 0); + MIMDLLBREN : out std_ulogic; + MIMDLLBWADD : out std_logic_vector(11 downto 0); + MIMDLLBWDATA : out std_logic_vector(63 downto 0); + MIMDLLBWEN : out std_ulogic; + MIMRXBRADD : out std_logic_vector(12 downto 0); + MIMRXBREN : out std_ulogic; + MIMRXBWADD : out std_logic_vector(12 downto 0); + MIMRXBWDATA : out std_logic_vector(63 downto 0); + MIMRXBWEN : out std_ulogic; + MIMTXBRADD : out std_logic_vector(12 downto 0); + MIMTXBREN : out std_ulogic; + MIMTXBWADD : out std_logic_vector(12 downto 0); + MIMTXBWDATA : out std_logic_vector(63 downto 0); + MIMTXBWEN : out std_ulogic; + PARITYERRORRESPONSE : out std_ulogic; + PIPEDESKEWLANESL0 : out std_ulogic; + PIPEDESKEWLANESL1 : out std_ulogic; + PIPEDESKEWLANESL2 : out std_ulogic; + PIPEDESKEWLANESL3 : out std_ulogic; + PIPEDESKEWLANESL4 : out std_ulogic; + PIPEDESKEWLANESL5 : out std_ulogic; + PIPEDESKEWLANESL6 : out std_ulogic; + PIPEDESKEWLANESL7 : out std_ulogic; + PIPEPOWERDOWNL0 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL1 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL2 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL3 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL4 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL5 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL6 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL7 : out std_logic_vector(1 downto 0); + PIPERESETL0 : out std_ulogic; + PIPERESETL1 : out std_ulogic; + PIPERESETL2 : out std_ulogic; + PIPERESETL3 : out std_ulogic; + PIPERESETL4 : out std_ulogic; + PIPERESETL5 : out std_ulogic; + PIPERESETL6 : out std_ulogic; + PIPERESETL7 : out std_ulogic; + PIPERXPOLARITYL0 : out std_ulogic; + PIPERXPOLARITYL1 : out std_ulogic; + PIPERXPOLARITYL2 : out std_ulogic; + PIPERXPOLARITYL3 : out std_ulogic; + PIPERXPOLARITYL4 : out std_ulogic; + PIPERXPOLARITYL5 : out std_ulogic; + PIPERXPOLARITYL6 : out std_ulogic; + PIPERXPOLARITYL7 : out std_ulogic; + PIPETXCOMPLIANCEL0 : out std_ulogic; + PIPETXCOMPLIANCEL1 : out std_ulogic; + PIPETXCOMPLIANCEL2 : out std_ulogic; + PIPETXCOMPLIANCEL3 : out std_ulogic; + PIPETXCOMPLIANCEL4 : out std_ulogic; + PIPETXCOMPLIANCEL5 : out std_ulogic; + PIPETXCOMPLIANCEL6 : out std_ulogic; + PIPETXCOMPLIANCEL7 : out std_ulogic; + PIPETXDATAKL0 : out std_ulogic; + PIPETXDATAKL1 : out std_ulogic; + PIPETXDATAKL2 : out std_ulogic; + PIPETXDATAKL3 : out std_ulogic; + PIPETXDATAKL4 : out std_ulogic; + PIPETXDATAKL5 : out std_ulogic; + PIPETXDATAKL6 : out std_ulogic; + PIPETXDATAKL7 : out std_ulogic; + PIPETXDATAL0 : out std_logic_vector(7 downto 0); + PIPETXDATAL1 : out std_logic_vector(7 downto 0); + PIPETXDATAL2 : out std_logic_vector(7 downto 0); + PIPETXDATAL3 : out std_logic_vector(7 downto 0); + PIPETXDATAL4 : out std_logic_vector(7 downto 0); + PIPETXDATAL5 : out std_logic_vector(7 downto 0); + PIPETXDATAL6 : out std_logic_vector(7 downto 0); + PIPETXDATAL7 : out std_logic_vector(7 downto 0); + PIPETXDETECTRXLOOPBACKL0 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL1 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL2 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL3 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL4 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL5 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL6 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL7 : out std_ulogic; + PIPETXELECIDLEL0 : out std_ulogic; + PIPETXELECIDLEL1 : out std_ulogic; + PIPETXELECIDLEL2 : out std_ulogic; + PIPETXELECIDLEL3 : out std_ulogic; + PIPETXELECIDLEL4 : out std_ulogic; + PIPETXELECIDLEL5 : out std_ulogic; + PIPETXELECIDLEL6 : out std_ulogic; + PIPETXELECIDLEL7 : out std_ulogic; + SERRENABLE : out std_ulogic; + URREPORTINGENABLE : out std_ulogic; + + AUXPOWER : in std_ulogic; + COMPLIANCEAVOID : in std_ulogic; + CRMCORECLK : in std_ulogic; + CRMCORECLKDLO : in std_ulogic; + CRMCORECLKRXO : in std_ulogic; + CRMCORECLKTXO : in std_ulogic; + CRMLINKRSTN : in std_ulogic; + CRMMACRSTN : in std_ulogic; + CRMMGMTRSTN : in std_ulogic; + CRMNVRSTN : in std_ulogic; + CRMURSTN : in std_ulogic; + CRMUSERCFGRSTN : in std_ulogic; + CRMUSERCLK : in std_ulogic; + CRMUSERCLKRXO : in std_ulogic; + CRMUSERCLKTXO : in std_ulogic; + L0CFGDISABLESCRAMBLE : in std_ulogic; + L0CFGLOOPBACKMASTER : in std_ulogic; + L0LEGACYINTFUNCT0 : in std_ulogic; + L0MSIREQUEST0 : in std_logic_vector(3 downto 0); + L0PACKETHEADERFROMUSER : in std_logic_vector(127 downto 0); + L0PMEREQIN : in std_ulogic; + L0SETCOMPLETERABORTERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTCORRERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTUNCORRERROR : in std_ulogic; + L0SETDETECTEDCORRERROR : in std_ulogic; + L0SETDETECTEDFATALERROR : in std_ulogic; + L0SETDETECTEDNONFATALERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONCORRERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTOTHERERROR : in std_ulogic; + L0SETUSERDETECTEDPARITYERROR : in std_ulogic; + L0SETUSERMASTERDATAPARITY : in std_ulogic; + L0SETUSERRECEIVEDMASTERABORT : in std_ulogic; + L0SETUSERRECEIVEDTARGETABORT : in std_ulogic; + L0SETUSERSIGNALLEDTARGETABORT : in std_ulogic; + L0SETUSERSYSTEMERROR : in std_ulogic; + L0TRANSACTIONSPENDING : in std_ulogic; + LLKRXCHFIFO : in std_logic_vector(1 downto 0); + LLKRXCHTC : in std_logic_vector(2 downto 0); + LLKRXDSTCONTREQN : in std_ulogic; + LLKRXDSTREQN : in std_ulogic; + LLKTXCHFIFO : in std_logic_vector(1 downto 0); + LLKTXCHTC : in std_logic_vector(2 downto 0); + LLKTXDATA : in std_logic_vector(63 downto 0); + LLKTXENABLEN : in std_logic_vector(1 downto 0); + LLKTXEOFN : in std_ulogic; + LLKTXEOPN : in std_ulogic; + LLKTXSOFN : in std_ulogic; + LLKTXSOPN : in std_ulogic; + LLKTXSRCDSCN : in std_ulogic; + LLKTXSRCRDYN : in std_ulogic; + MGMTADDR : in std_logic_vector(10 downto 0); + MGMTBWREN : in std_logic_vector(3 downto 0); + MGMTRDEN : in std_ulogic; + MGMTSTATSCREDITSEL : in std_logic_vector(6 downto 0); + MGMTWDATA : in std_logic_vector(31 downto 0); + MGMTWREN : in std_ulogic; + MIMDLLBRDATA : in std_logic_vector(63 downto 0); + MIMRXBRDATA : in std_logic_vector(63 downto 0); + MIMTXBRDATA : in std_logic_vector(63 downto 0); + PIPEPHYSTATUSL0 : in std_ulogic; + PIPEPHYSTATUSL1 : in std_ulogic; + PIPEPHYSTATUSL2 : in std_ulogic; + PIPEPHYSTATUSL3 : in std_ulogic; + PIPEPHYSTATUSL4 : in std_ulogic; + PIPEPHYSTATUSL5 : in std_ulogic; + PIPEPHYSTATUSL6 : in std_ulogic; + PIPEPHYSTATUSL7 : in std_ulogic; + PIPERXCHANISALIGNEDL0 : in std_ulogic; + PIPERXCHANISALIGNEDL1 : in std_ulogic; + PIPERXCHANISALIGNEDL2 : in std_ulogic; + PIPERXCHANISALIGNEDL3 : in std_ulogic; + PIPERXCHANISALIGNEDL4 : in std_ulogic; + PIPERXCHANISALIGNEDL5 : in std_ulogic; + PIPERXCHANISALIGNEDL6 : in std_ulogic; + PIPERXCHANISALIGNEDL7 : in std_ulogic; + PIPERXDATAKL0 : in std_ulogic; + PIPERXDATAKL1 : in std_ulogic; + PIPERXDATAKL2 : in std_ulogic; + PIPERXDATAKL3 : in std_ulogic; + PIPERXDATAKL4 : in std_ulogic; + PIPERXDATAKL5 : in std_ulogic; + PIPERXDATAKL6 : in std_ulogic; + PIPERXDATAKL7 : in std_ulogic; + PIPERXDATAL0 : in std_logic_vector(7 downto 0); + PIPERXDATAL1 : in std_logic_vector(7 downto 0); + PIPERXDATAL2 : in std_logic_vector(7 downto 0); + PIPERXDATAL3 : in std_logic_vector(7 downto 0); + PIPERXDATAL4 : in std_logic_vector(7 downto 0); + PIPERXDATAL5 : in std_logic_vector(7 downto 0); + PIPERXDATAL6 : in std_logic_vector(7 downto 0); + PIPERXDATAL7 : in std_logic_vector(7 downto 0); + PIPERXELECIDLEL0 : in std_ulogic; + PIPERXELECIDLEL1 : in std_ulogic; + PIPERXELECIDLEL2 : in std_ulogic; + PIPERXELECIDLEL3 : in std_ulogic; + PIPERXELECIDLEL4 : in std_ulogic; + PIPERXELECIDLEL5 : in std_ulogic; + PIPERXELECIDLEL6 : in std_ulogic; + PIPERXELECIDLEL7 : in std_ulogic; + PIPERXSTATUSL0 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL1 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL2 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL3 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL4 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL5 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL6 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL7 : in std_logic_vector(2 downto 0); + PIPERXVALIDL0 : in std_ulogic; + PIPERXVALIDL1 : in std_ulogic; + PIPERXVALIDL2 : in std_ulogic; + PIPERXVALIDL3 : in std_ulogic; + PIPERXVALIDL4 : in std_ulogic; + PIPERXVALIDL5 : in std_ulogic; + PIPERXVALIDL6 : in std_ulogic; + PIPERXVALIDL7 : in std_ulogic + ); +end PCIE_EP; + +architecture PCIE_EP_V of PCIE_EP is + + component PCIE_INTERNAL_1_1 + generic ( + ACTIVELANESIN : bit_vector := X"01"; + AERBASEPTR : bit_vector := X"110"; + AERCAPABILITYECRCCHECKCAPABLE : boolean := FALSE; + AERCAPABILITYECRCGENCAPABLE : boolean := FALSE; + AERCAPABILITYNEXTPTR : bit_vector := X"138"; + BAR0ADDRWIDTH : integer := 0; + BAR0EXIST : boolean := TRUE; + BAR0IOMEMN : integer := 0; + BAR0MASKWIDTH : bit_vector := X"14"; + BAR0PREFETCHABLE : boolean := TRUE; + BAR1ADDRWIDTH : integer := 0; + BAR1EXIST : boolean := FALSE; + BAR1IOMEMN : integer := 0; + BAR1MASKWIDTH : bit_vector := X"00"; + BAR1PREFETCHABLE : boolean := FALSE; + BAR2ADDRWIDTH : integer := 0; + BAR2EXIST : boolean := FALSE; + BAR2IOMEMN : integer := 0; + BAR2MASKWIDTH : bit_vector := X"00"; + BAR2PREFETCHABLE : boolean := FALSE; + BAR3ADDRWIDTH : integer := 0; + BAR3EXIST : boolean := FALSE; + BAR3IOMEMN : integer := 0; + BAR3MASKWIDTH : bit_vector := X"00"; + BAR3PREFETCHABLE : boolean := FALSE; + BAR4ADDRWIDTH : integer := 0; + BAR4EXIST : boolean := FALSE; + BAR4IOMEMN : integer := 0; + BAR4MASKWIDTH : bit_vector := X"00"; + BAR4PREFETCHABLE : boolean := FALSE; + BAR5EXIST : boolean := FALSE; + BAR5IOMEMN : integer := 0; + BAR5MASKWIDTH : bit_vector := X"00"; + BAR5PREFETCHABLE : boolean := FALSE; + CAPABILITIESPOINTER : bit_vector := X"40"; + CARDBUSCISPOINTER : bit_vector := X"00000000"; + CLASSCODE : bit_vector := X"058000"; + CLKDIVIDED : boolean := FALSE; + CONFIGROUTING : bit_vector := X"1"; + DEVICECAPABILITYENDPOINTL0SLATENCY : bit_vector := X"0"; + DEVICECAPABILITYENDPOINTL1LATENCY : bit_vector := X"0"; + DEVICEID : bit_vector := X"5050"; + DEVICESERIALNUMBER : bit_vector := X"E000000001000A35"; + DSNBASEPTR : bit_vector := X"148"; + DSNCAPABILITYNEXTPTR : bit_vector := X"154"; + DUALCOREENABLE : boolean := FALSE; + DUALCORESLAVE : boolean := FALSE; + DUALROLECFGCNTRLROOTEPN : integer := 0; + EXTCFGCAPPTR : bit_vector := X"00"; + EXTCFGXPCAPPTR : bit_vector := X"000"; + HEADERTYPE : bit_vector := X"00"; + INFINITECOMPLETIONS : boolean := TRUE; + INTERRUPTPIN : bit_vector := X"00"; + ISSWITCH : boolean := FALSE; + L0SEXITLATENCY : integer := 7; + L0SEXITLATENCYCOMCLK : integer := 7; + L1EXITLATENCY : integer := 7; + L1EXITLATENCYCOMCLK : integer := 7; + LINKCAPABILITYASPMSUPPORT : bit_vector := X"1"; + LINKCAPABILITYMAXLINKWIDTH : bit_vector := X"01"; + LINKSTATUSSLOTCLOCKCONFIG : boolean := FALSE; + LLKBYPASS : boolean := FALSE; + LOWPRIORITYVCCOUNT : integer := 0; + MSIBASEPTR : bit_vector := X"048"; + MSICAPABILITYMULTIMSGCAP : bit_vector := X"0"; + MSICAPABILITYNEXTPTR : bit_vector := X"60"; + PBBASEPTR : bit_vector := X"138"; + PBCAPABILITYDW0BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW0DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW0PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW0PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW0POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW0TYPE : bit_vector := X"0"; + PBCAPABILITYDW1BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW1DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW1PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW1PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW1POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW1TYPE : bit_vector := X"0"; + PBCAPABILITYDW2BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW2DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW2PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW2PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW2POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW2TYPE : bit_vector := X"0"; + PBCAPABILITYDW3BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW3DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW3PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW3PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW3POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW3TYPE : bit_vector := X"0"; + PBCAPABILITYNEXTPTR : bit_vector := X"148"; + PBCAPABILITYSYSTEMALLOCATED : boolean := FALSE; + PCIECAPABILITYINTMSGNUM : bit_vector := X"00"; + PCIECAPABILITYNEXTPTR : bit_vector := X"00"; + PCIECAPABILITYSLOTIMPL : boolean := FALSE; + PCIEREVISION : integer := 1; + PMBASEPTR : bit_vector := X"040"; + PMCAPABILITYAUXCURRENT : bit_vector := X"0"; + PMCAPABILITYD1SUPPORT : boolean := FALSE; + PMCAPABILITYD2SUPPORT : boolean := FALSE; + PMCAPABILITYDSI : boolean := TRUE; + PMCAPABILITYNEXTPTR : bit_vector := X"60"; + PMCAPABILITYPMESUPPORT : bit_vector := X"00"; + PMDATA0 : bit_vector := X"00"; + PMDATA1 : bit_vector := X"00"; + PMDATA2 : bit_vector := X"00"; + PMDATA3 : bit_vector := X"00"; + PMDATA4 : bit_vector := X"00"; + PMDATA5 : bit_vector := X"00"; + PMDATA6 : bit_vector := X"00"; + PMDATA7 : bit_vector := X"00"; + PMDATA8 : bit_vector := X"00"; + PMDATASCALE0 : integer := 0; + PMDATASCALE1 : integer := 0; + PMDATASCALE2 : integer := 0; + PMDATASCALE3 : integer := 0; + PMDATASCALE4 : integer := 0; + PMDATASCALE5 : integer := 0; + PMDATASCALE6 : integer := 0; + PMDATASCALE7 : integer := 0; + PMDATASCALE8 : integer := 0; + PMSTATUSCONTROLDATASCALE : bit_vector := X"0"; + PORTVCCAPABILITYEXTENDEDVCCOUNT : bit_vector := X"0"; + PORTVCCAPABILITYVCARBCAP : bit_vector := X"00"; + PORTVCCAPABILITYVCARBTABLEOFFSET : bit_vector := X"00"; + RAMSHARETXRX : boolean := FALSE; + RESETMODE : boolean := FALSE; + RETRYRAMREADLATENCY : integer := 3; + RETRYRAMSIZE : bit_vector := X"009"; + RETRYRAMWIDTH : integer := 0; + RETRYRAMWRITELATENCY : integer := 1; + RETRYREADADDRPIPE : boolean := FALSE; + RETRYREADDATAPIPE : boolean := FALSE; + RETRYWRITEPIPE : boolean := FALSE; + REVISIONID : bit_vector := X"00"; + RXREADADDRPIPE : boolean := FALSE; + RXREADDATAPIPE : boolean := FALSE; + RXWRITEPIPE : boolean := FALSE; + SELECTASMODE : boolean := FALSE; + SELECTDLLIF : boolean := FALSE; + SLOTCAPABILITYATTBUTTONPRESENT : boolean := FALSE; + SLOTCAPABILITYATTINDICATORPRESENT : boolean := FALSE; + SLOTCAPABILITYHOTPLUGCAPABLE : boolean := FALSE; + SLOTCAPABILITYHOTPLUGSURPRISE : boolean := FALSE; + SLOTCAPABILITYMSLSENSORPRESENT : boolean := FALSE; + SLOTCAPABILITYPHYSICALSLOTNUM : bit_vector := X"0000"; + SLOTCAPABILITYPOWERCONTROLLERPRESENT : boolean := FALSE; + SLOTCAPABILITYPOWERINDICATORPRESENT : boolean := FALSE; + SLOTCAPABILITYSLOTPOWERLIMITSCALE : bit_vector := X"0"; + SLOTCAPABILITYSLOTPOWERLIMITVALUE : bit_vector := X"00"; + SLOTIMPLEMENTED : boolean := FALSE; + SUBSYSTEMID : bit_vector := X"5050"; + SUBSYSTEMVENDORID : bit_vector := X"10EE"; + TLRAMREADLATENCY : integer := 3; + TLRAMWIDTH : integer := 0; + TLRAMWRITELATENCY : integer := 1; + TXREADADDRPIPE : boolean := FALSE; + TXREADDATAPIPE : boolean := FALSE; + TXTSNFTS : integer := 255; + TXTSNFTSCOMCLK : integer := 255; + TXWRITEPIPE : boolean := FALSE; + UPSTREAMFACING : boolean := TRUE; + VC0RXFIFOBASEC : bit_vector := X"0098"; + VC0RXFIFOBASENP : bit_vector := X"0080"; + VC0RXFIFOBASEP : bit_vector := X"0000"; + VC0RXFIFOLIMITC : bit_vector := X"0117"; + VC0RXFIFOLIMITNP : bit_vector := X"0097"; + VC0RXFIFOLIMITP : bit_vector := X"007f"; + VC0TOTALCREDITSCD : bit_vector := X"000"; + VC0TOTALCREDITSCH : bit_vector := X"00"; + VC0TOTALCREDITSNPH : bit_vector := X"08"; + VC0TOTALCREDITSPD : bit_vector := X"034"; + VC0TOTALCREDITSPH : bit_vector := X"08"; + VC0TXFIFOBASEC : bit_vector := X"0098"; + VC0TXFIFOBASENP : bit_vector := X"0080"; + VC0TXFIFOBASEP : bit_vector := X"0000"; + VC0TXFIFOLIMITC : bit_vector := X"0117"; + VC0TXFIFOLIMITNP : bit_vector := X"0097"; + VC0TXFIFOLIMITP : bit_vector := X"007f"; + VC1RXFIFOBASEC : bit_vector := X"0118"; + VC1RXFIFOBASENP : bit_vector := X"0118"; + VC1RXFIFOBASEP : bit_vector := X"0118"; + VC1RXFIFOLIMITC : bit_vector := X"0118"; + VC1RXFIFOLIMITNP : bit_vector := X"0118"; + VC1RXFIFOLIMITP : bit_vector := X"0118"; + VC1TOTALCREDITSCD : bit_vector := X"000"; + VC1TOTALCREDITSCH : bit_vector := X"00"; + VC1TOTALCREDITSNPH : bit_vector := X"00"; + VC1TOTALCREDITSPD : bit_vector := X"000"; + VC1TOTALCREDITSPH : bit_vector := X"00"; + VC1TXFIFOBASEC : bit_vector := X"0118"; + VC1TXFIFOBASENP : bit_vector := X"0118"; + VC1TXFIFOBASEP : bit_vector := X"0118"; + VC1TXFIFOLIMITC : bit_vector := X"0118"; + VC1TXFIFOLIMITNP : bit_vector := X"0118"; + VC1TXFIFOLIMITP : bit_vector := X"0118"; + VCBASEPTR : bit_vector := X"154"; + VCCAPABILITYNEXTPTR : bit_vector := X"000"; + VENDORID : bit_vector := X"10EE"; + XLINKSUPPORTED : boolean := FALSE; + XPBASEPTR : bit_vector := X"60"; + XPDEVICEPORTTYPE : bit_vector := X"0"; + XPMAXPAYLOAD : integer := 0; + XPRCBCONTROL : integer := 0 + + ); + port ( + BUSMASTERENABLE : out std_ulogic; + CRMDOHOTRESETN : out std_ulogic; + CRMPWRSOFTRESETN : out std_ulogic; + CRMRXHOTRESETN : out std_ulogic; + DLLTXPMDLLPOUTSTANDING : out std_ulogic; + INTERRUPTDISABLE : out std_ulogic; + IOSPACEENABLE : out std_ulogic; + L0ASAUTONOMOUSINITCOMPLETED : out std_ulogic; + L0ATTENTIONINDICATORCONTROL : out std_logic_vector(1 downto 0); + L0CFGLOOPBACKACK : out std_ulogic; + L0COMPLETERID : out std_logic_vector(12 downto 0); + L0CORRERRMSGRCVD : out std_ulogic; + L0DLLASRXSTATE : out std_logic_vector(1 downto 0); + L0DLLASTXSTATE : out std_ulogic; + L0DLLERRORVECTOR : out std_logic_vector(6 downto 0); + L0DLLRXACKOUTSTANDING : out std_ulogic; + L0DLLTXNONFCOUTSTANDING : out std_ulogic; + L0DLLTXOUTSTANDING : out std_ulogic; + L0DLLVCSTATUS : out std_logic_vector(7 downto 0); + L0DLUPDOWN : out std_logic_vector(7 downto 0); + L0ERRMSGREQID : out std_logic_vector(15 downto 0); + L0FATALERRMSGRCVD : out std_ulogic; + L0FIRSTCFGWRITEOCCURRED : out std_ulogic; + L0FWDCORRERROUT : out std_ulogic; + L0FWDFATALERROUT : out std_ulogic; + L0FWDNONFATALERROUT : out std_ulogic; + L0LTSSMSTATE : out std_logic_vector(3 downto 0); + L0MACENTEREDL0 : out std_ulogic; + L0MACLINKTRAINING : out std_ulogic; + L0MACLINKUP : out std_ulogic; + L0MACNEGOTIATEDLINKWIDTH : out std_logic_vector(3 downto 0); + L0MACNEWSTATEACK : out std_ulogic; + L0MACRXL0SSTATE : out std_ulogic; + L0MACUPSTREAMDOWNSTREAM : out std_ulogic; + L0MCFOUND : out std_logic_vector(2 downto 0); + L0MSIENABLE0 : out std_ulogic; + L0MULTIMSGEN0 : out std_logic_vector(2 downto 0); + L0NONFATALERRMSGRCVD : out std_ulogic; + L0PMEACK : out std_ulogic; + L0PMEEN : out std_ulogic; + L0PMEREQOUT : out std_ulogic; + L0POWERCONTROLLERCONTROL : out std_ulogic; + L0POWERINDICATORCONTROL : out std_logic_vector(1 downto 0); + L0PWRINHIBITTRANSFERS : out std_ulogic; + L0PWRL1STATE : out std_ulogic; + L0PWRL23READYDEVICE : out std_ulogic; + L0PWRL23READYSTATE : out std_ulogic; + L0PWRSTATE0 : out std_logic_vector(1 downto 0); + L0PWRTURNOFFREQ : out std_ulogic; + L0PWRTXL0SSTATE : out std_ulogic; + L0RECEIVEDASSERTINTALEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTBLEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTCLEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTDLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTALEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTBLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTCLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTDLEGACYINT : out std_ulogic; + L0RXBEACON : out std_ulogic; + L0RXDLLFCCMPLMCCRED : out std_logic_vector(23 downto 0); + L0RXDLLFCCMPLMCUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLFCNPOSTBYPCRED : out std_logic_vector(19 downto 0); + L0RXDLLFCNPOSTBYPUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLFCPOSTORDCRED : out std_logic_vector(23 downto 0); + L0RXDLLFCPOSTORDUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLPM : out std_ulogic; + L0RXDLLPMTYPE : out std_logic_vector(2 downto 0); + L0RXDLLSBFCDATA : out std_logic_vector(18 downto 0); + L0RXDLLSBFCUPDATE : out std_ulogic; + L0RXDLLTLPECRCOK : out std_ulogic; + L0RXDLLTLPEND : out std_logic_vector(1 downto 0); + L0RXMACLINKERROR : out std_logic_vector(1 downto 0); + L0STATSCFGOTHERRECEIVED : out std_ulogic; + L0STATSCFGOTHERTRANSMITTED : out std_ulogic; + L0STATSCFGRECEIVED : out std_ulogic; + L0STATSCFGTRANSMITTED : out std_ulogic; + L0STATSDLLPRECEIVED : out std_ulogic; + L0STATSDLLPTRANSMITTED : out std_ulogic; + L0STATSOSRECEIVED : out std_ulogic; + L0STATSOSTRANSMITTED : out std_ulogic; + L0STATSTLPRECEIVED : out std_ulogic; + L0STATSTLPTRANSMITTED : out std_ulogic; + L0TOGGLEELECTROMECHANICALINTERLOCK : out std_ulogic; + L0TRANSFORMEDVC : out std_logic_vector(2 downto 0); + L0TXDLLFCCMPLMCUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLFCNPOSTBYPUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLFCPOSTORDUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLPMUPDATED : out std_ulogic; + L0TXDLLSBFCUPDATED : out std_ulogic; + L0UCBYPFOUND : out std_logic_vector(3 downto 0); + L0UCORDFOUND : out std_logic_vector(3 downto 0); + L0UNLOCKRECEIVED : out std_ulogic; + LLKRX4DWHEADERN : out std_ulogic; + LLKRXCHCOMPLETIONAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHCOMPLETIONPARTIALN : out std_logic_vector(7 downto 0); + LLKRXCHCONFIGAVAILABLEN : out std_ulogic; + LLKRXCHCONFIGPARTIALN : out std_ulogic; + LLKRXCHNONPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHNONPOSTEDPARTIALN : out std_logic_vector(7 downto 0); + LLKRXCHPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHPOSTEDPARTIALN : out std_logic_vector(7 downto 0); + LLKRXDATA : out std_logic_vector(63 downto 0); + LLKRXECRCBADN : out std_ulogic; + LLKRXEOFN : out std_ulogic; + LLKRXEOPN : out std_ulogic; + LLKRXPREFERREDTYPE : out std_logic_vector(15 downto 0); + LLKRXSOFN : out std_ulogic; + LLKRXSOPN : out std_ulogic; + LLKRXSRCDSCN : out std_ulogic; + LLKRXSRCLASTREQN : out std_ulogic; + LLKRXSRCRDYN : out std_ulogic; + LLKRXVALIDN : out std_logic_vector(1 downto 0); + LLKTCSTATUS : out std_logic_vector(7 downto 0); + LLKTXCHANSPACE : out std_logic_vector(9 downto 0); + LLKTXCHCOMPLETIONREADYN : out std_logic_vector(7 downto 0); + LLKTXCHNONPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCHPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCONFIGREADYN : out std_ulogic; + LLKTXDSTRDYN : out std_ulogic; + MAXPAYLOADSIZE : out std_logic_vector(2 downto 0); + MAXREADREQUESTSIZE : out std_logic_vector(2 downto 0); + MEMSPACEENABLE : out std_ulogic; + MGMTPSO : out std_logic_vector(16 downto 0); + MGMTRDATA : out std_logic_vector(31 downto 0); + MGMTSTATSCREDIT : out std_logic_vector(11 downto 0); + MIMDLLBRADD : out std_logic_vector(11 downto 0); + MIMDLLBREN : out std_ulogic; + MIMDLLBWADD : out std_logic_vector(11 downto 0); + MIMDLLBWDATA : out std_logic_vector(63 downto 0); + MIMDLLBWEN : out std_ulogic; + MIMRXBRADD : out std_logic_vector(12 downto 0); + MIMRXBREN : out std_ulogic; + MIMRXBWADD : out std_logic_vector(12 downto 0); + MIMRXBWDATA : out std_logic_vector(63 downto 0); + MIMRXBWEN : out std_ulogic; + MIMTXBRADD : out std_logic_vector(12 downto 0); + MIMTXBREN : out std_ulogic; + MIMTXBWADD : out std_logic_vector(12 downto 0); + MIMTXBWDATA : out std_logic_vector(63 downto 0); + MIMTXBWEN : out std_ulogic; + PARITYERRORRESPONSE : out std_ulogic; + PIPEDESKEWLANESL0 : out std_ulogic; + PIPEDESKEWLANESL1 : out std_ulogic; + PIPEDESKEWLANESL2 : out std_ulogic; + PIPEDESKEWLANESL3 : out std_ulogic; + PIPEDESKEWLANESL4 : out std_ulogic; + PIPEDESKEWLANESL5 : out std_ulogic; + PIPEDESKEWLANESL6 : out std_ulogic; + PIPEDESKEWLANESL7 : out std_ulogic; + PIPEPOWERDOWNL0 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL1 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL2 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL3 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL4 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL5 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL6 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL7 : out std_logic_vector(1 downto 0); + PIPERESETL0 : out std_ulogic; + PIPERESETL1 : out std_ulogic; + PIPERESETL2 : out std_ulogic; + PIPERESETL3 : out std_ulogic; + PIPERESETL4 : out std_ulogic; + PIPERESETL5 : out std_ulogic; + PIPERESETL6 : out std_ulogic; + PIPERESETL7 : out std_ulogic; + PIPERXPOLARITYL0 : out std_ulogic; + PIPERXPOLARITYL1 : out std_ulogic; + PIPERXPOLARITYL2 : out std_ulogic; + PIPERXPOLARITYL3 : out std_ulogic; + PIPERXPOLARITYL4 : out std_ulogic; + PIPERXPOLARITYL5 : out std_ulogic; + PIPERXPOLARITYL6 : out std_ulogic; + PIPERXPOLARITYL7 : out std_ulogic; + PIPETXCOMPLIANCEL0 : out std_ulogic; + PIPETXCOMPLIANCEL1 : out std_ulogic; + PIPETXCOMPLIANCEL2 : out std_ulogic; + PIPETXCOMPLIANCEL3 : out std_ulogic; + PIPETXCOMPLIANCEL4 : out std_ulogic; + PIPETXCOMPLIANCEL5 : out std_ulogic; + PIPETXCOMPLIANCEL6 : out std_ulogic; + PIPETXCOMPLIANCEL7 : out std_ulogic; + PIPETXDATAKL0 : out std_ulogic; + PIPETXDATAKL1 : out std_ulogic; + PIPETXDATAKL2 : out std_ulogic; + PIPETXDATAKL3 : out std_ulogic; + PIPETXDATAKL4 : out std_ulogic; + PIPETXDATAKL5 : out std_ulogic; + PIPETXDATAKL6 : out std_ulogic; + PIPETXDATAKL7 : out std_ulogic; + PIPETXDATAL0 : out std_logic_vector(7 downto 0); + PIPETXDATAL1 : out std_logic_vector(7 downto 0); + PIPETXDATAL2 : out std_logic_vector(7 downto 0); + PIPETXDATAL3 : out std_logic_vector(7 downto 0); + PIPETXDATAL4 : out std_logic_vector(7 downto 0); + PIPETXDATAL5 : out std_logic_vector(7 downto 0); + PIPETXDATAL6 : out std_logic_vector(7 downto 0); + PIPETXDATAL7 : out std_logic_vector(7 downto 0); + PIPETXDETECTRXLOOPBACKL0 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL1 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL2 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL3 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL4 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL5 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL6 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL7 : out std_ulogic; + PIPETXELECIDLEL0 : out std_ulogic; + PIPETXELECIDLEL1 : out std_ulogic; + PIPETXELECIDLEL2 : out std_ulogic; + PIPETXELECIDLEL3 : out std_ulogic; + PIPETXELECIDLEL4 : out std_ulogic; + PIPETXELECIDLEL5 : out std_ulogic; + PIPETXELECIDLEL6 : out std_ulogic; + PIPETXELECIDLEL7 : out std_ulogic; + SERRENABLE : out std_ulogic; + URREPORTINGENABLE : out std_ulogic; + + AUXPOWER : in std_ulogic; + CFGNEGOTIATEDLINKWIDTH : in std_logic_vector(5 downto 0); + COMPLIANCEAVOID : in std_ulogic; + CRMCFGBRIDGEHOTRESET : in std_ulogic; + CRMCORECLK : in std_ulogic; + CRMCORECLKDLO : in std_ulogic; + CRMCORECLKRXO : in std_ulogic; + CRMCORECLKTXO : in std_ulogic; + CRMLINKRSTN : in std_ulogic; + CRMMACRSTN : in std_ulogic; + CRMMGMTRSTN : in std_ulogic; + CRMNVRSTN : in std_ulogic; + CRMTXHOTRESETN : in std_ulogic; + CRMURSTN : in std_ulogic; + CRMUSERCFGRSTN : in std_ulogic; + CRMUSERCLK : in std_ulogic; + CRMUSERCLKRXO : in std_ulogic; + CRMUSERCLKTXO : in std_ulogic; + CROSSLINKSEED : in std_ulogic; + L0ACKNAKTIMERADJUSTMENT : in std_logic_vector(11 downto 0); + L0ALLDOWNPORTSINL1 : in std_ulogic; + L0ALLDOWNRXPORTSINL0S : in std_ulogic; + L0ASE : in std_ulogic; + L0ASPORTCOUNT : in std_logic_vector(7 downto 0); + L0ASTURNPOOLBITSCONSUMED : in std_logic_vector(2 downto 0); + L0ATTENTIONBUTTONPRESSED : in std_ulogic; + L0CFGASSPANTREEOWNEDSTATE : in std_ulogic; + L0CFGASSTATECHANGECMD : in std_logic_vector(3 downto 0); + L0CFGDISABLESCRAMBLE : in std_ulogic; + L0CFGEXTENDEDSYNC : in std_ulogic; + L0CFGL0SENTRYENABLE : in std_ulogic; + L0CFGL0SENTRYSUP : in std_ulogic; + L0CFGL0SEXITLAT : in std_logic_vector(2 downto 0); + L0CFGLINKDISABLE : in std_ulogic; + L0CFGLOOPBACKMASTER : in std_ulogic; + L0CFGNEGOTIATEDMAXP : in std_logic_vector(2 downto 0); + L0CFGVCENABLE : in std_logic_vector(7 downto 0); + L0CFGVCID : in std_logic_vector(23 downto 0); + L0DLLHOLDLINKUP : in std_ulogic; + L0ELECTROMECHANICALINTERLOCKENGAGED : in std_ulogic; + L0FWDASSERTINTALEGACYINT : in std_ulogic; + L0FWDASSERTINTBLEGACYINT : in std_ulogic; + L0FWDASSERTINTCLEGACYINT : in std_ulogic; + L0FWDASSERTINTDLEGACYINT : in std_ulogic; + L0FWDCORRERRIN : in std_ulogic; + L0FWDDEASSERTINTALEGACYINT : in std_ulogic; + L0FWDDEASSERTINTBLEGACYINT : in std_ulogic; + L0FWDDEASSERTINTCLEGACYINT : in std_ulogic; + L0FWDDEASSERTINTDLEGACYINT : in std_ulogic; + L0FWDFATALERRIN : in std_ulogic; + L0FWDNONFATALERRIN : in std_ulogic; + L0LEGACYINTFUNCT0 : in std_ulogic; + L0MRLSENSORCLOSEDN : in std_ulogic; + L0MSIREQUEST0 : in std_logic_vector(3 downto 0); + L0PACKETHEADERFROMUSER : in std_logic_vector(127 downto 0); + L0PMEREQIN : in std_ulogic; + L0PORTNUMBER : in std_logic_vector(7 downto 0); + L0POWERFAULTDETECTED : in std_ulogic; + L0PRESENCEDETECTSLOTEMPTYN : in std_ulogic; + L0PWRNEWSTATEREQ : in std_ulogic; + L0PWRNEXTLINKSTATE : in std_logic_vector(1 downto 0); + L0REPLAYTIMERADJUSTMENT : in std_logic_vector(11 downto 0); + L0ROOTTURNOFFREQ : in std_ulogic; + L0RXTLTLPNONINITIALIZEDVC : in std_logic_vector(7 downto 0); + L0SENDUNLOCKMESSAGE : in std_ulogic; + L0SETCOMPLETERABORTERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTCORRERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTUNCORRERROR : in std_ulogic; + L0SETDETECTEDCORRERROR : in std_ulogic; + L0SETDETECTEDFATALERROR : in std_ulogic; + L0SETDETECTEDNONFATALERROR : in std_ulogic; + L0SETLINKDETECTEDPARITYERROR : in std_ulogic; + L0SETLINKMASTERDATAPARITY : in std_ulogic; + L0SETLINKRECEIVEDMASTERABORT : in std_ulogic; + L0SETLINKRECEIVEDTARGETABORT : in std_ulogic; + L0SETLINKSIGNALLEDTARGETABORT : in std_ulogic; + L0SETLINKSYSTEMERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONCORRERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTOTHERERROR : in std_ulogic; + L0SETUSERDETECTEDPARITYERROR : in std_ulogic; + L0SETUSERMASTERDATAPARITY : in std_ulogic; + L0SETUSERRECEIVEDMASTERABORT : in std_ulogic; + L0SETUSERRECEIVEDTARGETABORT : in std_ulogic; + L0SETUSERSIGNALLEDTARGETABORT : in std_ulogic; + L0SETUSERSYSTEMERROR : in std_ulogic; + L0TLASFCCREDSTARVATION : in std_ulogic; + L0TLLINKRETRAIN : in std_ulogic; + L0TRANSACTIONSPENDING : in std_ulogic; + L0TXBEACON : in std_ulogic; + L0TXCFGPM : in std_ulogic; + L0TXCFGPMTYPE : in std_logic_vector(2 downto 0); + L0TXTLFCCMPLMCCRED : in std_logic_vector(159 downto 0); + L0TXTLFCCMPLMCUPDATE : in std_logic_vector(15 downto 0); + L0TXTLFCNPOSTBYPCRED : in std_logic_vector(191 downto 0); + L0TXTLFCNPOSTBYPUPDATE : in std_logic_vector(15 downto 0); + L0TXTLFCPOSTORDCRED : in std_logic_vector(159 downto 0); + L0TXTLFCPOSTORDUPDATE : in std_logic_vector(15 downto 0); + L0TXTLSBFCDATA : in std_logic_vector(18 downto 0); + L0TXTLSBFCUPDATE : in std_ulogic; + L0TXTLTLPDATA : in std_logic_vector(63 downto 0); + L0TXTLTLPEDB : in std_ulogic; + L0TXTLTLPENABLE : in std_logic_vector(1 downto 0); + L0TXTLTLPEND : in std_logic_vector(1 downto 0); + L0TXTLTLPLATENCY : in std_logic_vector(3 downto 0); + L0TXTLTLPREQ : in std_ulogic; + L0TXTLTLPREQEND : in std_ulogic; + L0TXTLTLPWIDTH : in std_ulogic; + L0UPSTREAMRXPORTINL0S : in std_ulogic; + L0VC0PREVIEWEXPAND : in std_ulogic; + L0WAKEN : in std_ulogic; + LLKRXCHFIFO : in std_logic_vector(1 downto 0); + LLKRXCHTC : in std_logic_vector(2 downto 0); + LLKRXDSTCONTREQN : in std_ulogic; + LLKRXDSTREQN : in std_ulogic; + LLKTX4DWHEADERN : in std_ulogic; + LLKTXCHFIFO : in std_logic_vector(1 downto 0); + LLKTXCHTC : in std_logic_vector(2 downto 0); + LLKTXCOMPLETEN : in std_ulogic; + LLKTXCREATEECRCN : in std_ulogic; + LLKTXDATA : in std_logic_vector(63 downto 0); + LLKTXENABLEN : in std_logic_vector(1 downto 0); + LLKTXEOFN : in std_ulogic; + LLKTXEOPN : in std_ulogic; + LLKTXSOFN : in std_ulogic; + LLKTXSOPN : in std_ulogic; + LLKTXSRCDSCN : in std_ulogic; + LLKTXSRCRDYN : in std_ulogic; + MAINPOWER : in std_ulogic; + MGMTADDR : in std_logic_vector(10 downto 0); + MGMTBWREN : in std_logic_vector(3 downto 0); + MGMTRDEN : in std_ulogic; + MGMTSTATSCREDITSEL : in std_logic_vector(6 downto 0); + MGMTWDATA : in std_logic_vector(31 downto 0); + MGMTWREN : in std_ulogic; + MIMDLLBRDATA : in std_logic_vector(63 downto 0); + MIMRXBRDATA : in std_logic_vector(63 downto 0); + MIMTXBRDATA : in std_logic_vector(63 downto 0); + PIPEPHYSTATUSL0 : in std_ulogic; + PIPEPHYSTATUSL1 : in std_ulogic; + PIPEPHYSTATUSL2 : in std_ulogic; + PIPEPHYSTATUSL3 : in std_ulogic; + PIPEPHYSTATUSL4 : in std_ulogic; + PIPEPHYSTATUSL5 : in std_ulogic; + PIPEPHYSTATUSL6 : in std_ulogic; + PIPEPHYSTATUSL7 : in std_ulogic; + PIPERXCHANISALIGNEDL0 : in std_ulogic; + PIPERXCHANISALIGNEDL1 : in std_ulogic; + PIPERXCHANISALIGNEDL2 : in std_ulogic; + PIPERXCHANISALIGNEDL3 : in std_ulogic; + PIPERXCHANISALIGNEDL4 : in std_ulogic; + PIPERXCHANISALIGNEDL5 : in std_ulogic; + PIPERXCHANISALIGNEDL6 : in std_ulogic; + PIPERXCHANISALIGNEDL7 : in std_ulogic; + PIPERXDATAKL0 : in std_ulogic; + PIPERXDATAKL1 : in std_ulogic; + PIPERXDATAKL2 : in std_ulogic; + PIPERXDATAKL3 : in std_ulogic; + PIPERXDATAKL4 : in std_ulogic; + PIPERXDATAKL5 : in std_ulogic; + PIPERXDATAKL6 : in std_ulogic; + PIPERXDATAKL7 : in std_ulogic; + PIPERXDATAL0 : in std_logic_vector(7 downto 0); + PIPERXDATAL1 : in std_logic_vector(7 downto 0); + PIPERXDATAL2 : in std_logic_vector(7 downto 0); + PIPERXDATAL3 : in std_logic_vector(7 downto 0); + PIPERXDATAL4 : in std_logic_vector(7 downto 0); + PIPERXDATAL5 : in std_logic_vector(7 downto 0); + PIPERXDATAL6 : in std_logic_vector(7 downto 0); + PIPERXDATAL7 : in std_logic_vector(7 downto 0); + PIPERXELECIDLEL0 : in std_ulogic; + PIPERXELECIDLEL1 : in std_ulogic; + PIPERXELECIDLEL2 : in std_ulogic; + PIPERXELECIDLEL3 : in std_ulogic; + PIPERXELECIDLEL4 : in std_ulogic; + PIPERXELECIDLEL5 : in std_ulogic; + PIPERXELECIDLEL6 : in std_ulogic; + PIPERXELECIDLEL7 : in std_ulogic; + PIPERXSTATUSL0 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL1 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL2 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL3 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL4 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL5 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL6 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL7 : in std_logic_vector(2 downto 0); + PIPERXVALIDL0 : in std_ulogic; + PIPERXVALIDL1 : in std_ulogic; + PIPERXVALIDL2 : in std_ulogic; + PIPERXVALIDL3 : in std_ulogic; + PIPERXVALIDL4 : in std_ulogic; + PIPERXVALIDL5 : in std_ulogic; + PIPERXVALIDL6 : in std_ulogic; + PIPERXVALIDL7 : in std_ulogic + ); + end component; + +signal OPEN1 : std_logic; +signal OPEN8 : std_logic_vector(7 downto 0); +signal OPEN2 : std_logic_vector(1 downto 0); +signal OPEN16 : std_logic_vector(15 downto 0); +signal OPEN19 : std_logic_vector(18 downto 0); +signal OPEN20 : std_logic_vector(19 downto 0); +signal OPEN24 : std_logic_vector(23 downto 0); +signal OPEN4 : std_logic_vector(3 downto 0); +signal OPEN3 : std_logic_vector(2 downto 0); + +signal z1_0 : std_logic := '0'; +signal z1_1 : std_logic := '1'; +signal z2 : std_logic_vector(1 downto 0) := "00"; +signal z3 : std_logic_vector(2 downto 0) := "000"; +signal z4 : std_logic_vector(3 downto 0) := "0000"; +signal z6 : std_logic_vector(5 downto 0) := "000000"; +signal z8 : std_logic_vector(7 downto 0) := "00000000"; + +signal z12 : std_logic_vector(11 downto 0) := "000000000000"; +signal z16 : std_logic_vector(15 downto 0) := "0000000000000000"; +signal z19 : std_logic_vector(18 downto 0) := "0000000000000000000"; +signal z24 : std_logic_vector(23 downto 0) := "000000000000000000000000"; +signal z64 : std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; +signal z160 : std_logic_vector(159 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; +signal z192 : std_logic_vector(191 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + +begin +PCIE_INTERNAL_1_1_inst : PCIE_INTERNAL_1_1 + generic map ( + ACTIVELANESIN => ACTIVELANESIN, + AERBASEPTR => AERBASEPTR, + AERCAPABILITYECRCCHECKCAPABLE => FALSE, + AERCAPABILITYECRCGENCAPABLE => FALSE, + AERCAPABILITYNEXTPTR => AERCAPABILITYNEXTPTR, + BAR0ADDRWIDTH => BAR0ADDRWIDTH, + BAR0EXIST => BAR0EXIST, + BAR0IOMEMN => BAR0IOMEMN, + BAR0MASKWIDTH => BAR0MASKWIDTH, + BAR0PREFETCHABLE => BAR0PREFETCHABLE, + BAR1ADDRWIDTH => BAR1ADDRWIDTH, + BAR1EXIST => BAR1EXIST, + BAR1IOMEMN => BAR1IOMEMN, + BAR1MASKWIDTH => BAR1MASKWIDTH, + BAR1PREFETCHABLE => BAR1PREFETCHABLE, + BAR2ADDRWIDTH => BAR2ADDRWIDTH, + BAR2EXIST => BAR2EXIST, + BAR2IOMEMN => BAR2IOMEMN, + BAR2MASKWIDTH => BAR2MASKWIDTH, + BAR2PREFETCHABLE => BAR2PREFETCHABLE, + BAR3ADDRWIDTH => BAR3ADDRWIDTH, + BAR3EXIST => BAR3EXIST, + BAR3IOMEMN => BAR3IOMEMN, + BAR3MASKWIDTH => BAR3MASKWIDTH, + BAR3PREFETCHABLE => BAR3PREFETCHABLE, + BAR4ADDRWIDTH => BAR4ADDRWIDTH, + BAR4EXIST => BAR4EXIST, + BAR4IOMEMN => BAR4IOMEMN, + BAR4MASKWIDTH => BAR4MASKWIDTH, + BAR4PREFETCHABLE => BAR4PREFETCHABLE, + BAR5EXIST => BAR5EXIST, + BAR5IOMEMN => BAR5IOMEMN, + BAR5MASKWIDTH => BAR5MASKWIDTH, + BAR5PREFETCHABLE => BAR5PREFETCHABLE, + CAPABILITIESPOINTER => CAPABILITIESPOINTER, + CARDBUSCISPOINTER => CARDBUSCISPOINTER, + CLASSCODE => CLASSCODE, + CLKDIVIDED => CLKDIVIDED, + CONFIGROUTING => "001", + DEVICECAPABILITYENDPOINTL0SLATENCY => DEVICECAPABILITYENDPOINTL0SLATENCY, + DEVICECAPABILITYENDPOINTL1LATENCY => DEVICECAPABILITYENDPOINTL1LATENCY, + DEVICEID => DEVICEID, + DEVICESERIALNUMBER => DEVICESERIALNUMBER, + DSNBASEPTR => DSNBASEPTR, + DSNCAPABILITYNEXTPTR => DSNCAPABILITYNEXTPTR, + DUALCOREENABLE => FALSE, + DUALCORESLAVE => FALSE, + DUALROLECFGCNTRLROOTEPN => 0, + EXTCFGCAPPTR => X"00", + EXTCFGXPCAPPTR => X"000", + HEADERTYPE => X"00", + INFINITECOMPLETIONS => INFINITECOMPLETIONS, + INTERRUPTPIN => INTERRUPTPIN, + ISSWITCH => FALSE, + L0SEXITLATENCY => L0SEXITLATENCY, + L0SEXITLATENCYCOMCLK => L0SEXITLATENCYCOMCLK, + L1EXITLATENCY => L1EXITLATENCY, + L1EXITLATENCYCOMCLK => L1EXITLATENCYCOMCLK, + LINKCAPABILITYASPMSUPPORT => LINKCAPABILITYASPMSUPPORT, + LINKCAPABILITYMAXLINKWIDTH => LINKCAPABILITYMAXLINKWIDTH, + LINKSTATUSSLOTCLOCKCONFIG => LINKSTATUSSLOTCLOCKCONFIG, + LLKBYPASS => FALSE, + LOWPRIORITYVCCOUNT => LOWPRIORITYVCCOUNT, + MSIBASEPTR => MSIBASEPTR, + MSICAPABILITYMULTIMSGCAP => MSICAPABILITYMULTIMSGCAP, + MSICAPABILITYNEXTPTR => MSICAPABILITYNEXTPTR, + PBBASEPTR => PBBASEPTR, + PBCAPABILITYDW0BASEPOWER => PBCAPABILITYDW0BASEPOWER, + PBCAPABILITYDW0DATASCALE => PBCAPABILITYDW0DATASCALE, + PBCAPABILITYDW0PMSTATE => PBCAPABILITYDW0PMSTATE, + PBCAPABILITYDW0PMSUBSTATE => PBCAPABILITYDW0PMSUBSTATE, + PBCAPABILITYDW0POWERRAIL => PBCAPABILITYDW0POWERRAIL, + PBCAPABILITYDW0TYPE => PBCAPABILITYDW0TYPE, + PBCAPABILITYDW1BASEPOWER => PBCAPABILITYDW1BASEPOWER, + PBCAPABILITYDW1DATASCALE => PBCAPABILITYDW1DATASCALE, + PBCAPABILITYDW1PMSTATE => PBCAPABILITYDW1PMSTATE, + PBCAPABILITYDW1PMSUBSTATE => PBCAPABILITYDW1PMSUBSTATE, + PBCAPABILITYDW1POWERRAIL => PBCAPABILITYDW1POWERRAIL, + PBCAPABILITYDW1TYPE => PBCAPABILITYDW1TYPE, + PBCAPABILITYDW2BASEPOWER => PBCAPABILITYDW2BASEPOWER, + PBCAPABILITYDW2DATASCALE => PBCAPABILITYDW2DATASCALE, + PBCAPABILITYDW2PMSTATE => PBCAPABILITYDW2PMSTATE, + PBCAPABILITYDW2PMSUBSTATE => PBCAPABILITYDW2PMSUBSTATE, + PBCAPABILITYDW2POWERRAIL => PBCAPABILITYDW2POWERRAIL, + PBCAPABILITYDW2TYPE => PBCAPABILITYDW2TYPE, + PBCAPABILITYDW3BASEPOWER => PBCAPABILITYDW3BASEPOWER, + PBCAPABILITYDW3DATASCALE => PBCAPABILITYDW3DATASCALE, + PBCAPABILITYDW3PMSTATE => PBCAPABILITYDW3PMSTATE, + PBCAPABILITYDW3PMSUBSTATE => PBCAPABILITYDW3PMSUBSTATE, + PBCAPABILITYDW3POWERRAIL => PBCAPABILITYDW3POWERRAIL, + PBCAPABILITYDW3TYPE => PBCAPABILITYDW3TYPE, + PBCAPABILITYNEXTPTR => PBCAPABILITYNEXTPTR, + PBCAPABILITYSYSTEMALLOCATED => PBCAPABILITYSYSTEMALLOCATED, + PCIECAPABILITYINTMSGNUM => "00000", + PCIECAPABILITYNEXTPTR => PCIECAPABILITYNEXTPTR, + PCIECAPABILITYSLOTIMPL => FALSE, + PCIEREVISION => 1, + PMBASEPTR => PMBASEPTR, + PMCAPABILITYAUXCURRENT => PMCAPABILITYAUXCURRENT, + PMCAPABILITYD1SUPPORT => PMCAPABILITYD1SUPPORT, + PMCAPABILITYD2SUPPORT => PMCAPABILITYD2SUPPORT, + PMCAPABILITYDSI => PMCAPABILITYDSI, + PMCAPABILITYNEXTPTR => PMCAPABILITYNEXTPTR, + PMCAPABILITYPMESUPPORT => PMCAPABILITYPMESUPPORT, + PMDATA0 => PMDATA0, + PMDATA1 => PMDATA1, + PMDATA2 => PMDATA2, + PMDATA3 => PMDATA3, + PMDATA4 => PMDATA4, + PMDATA5 => PMDATA5, + PMDATA6 => PMDATA6, + PMDATA7 => PMDATA7, + PMDATA8 => X"00", + PMDATASCALE0 => PMDATASCALE0, + PMDATASCALE1 => PMDATASCALE1, + PMDATASCALE2 => PMDATASCALE2, + PMDATASCALE3 => PMDATASCALE3, + PMDATASCALE4 => PMDATASCALE4, + PMDATASCALE5 => PMDATASCALE5, + PMDATASCALE6 => PMDATASCALE6, + PMDATASCALE7 => PMDATASCALE7, + PMDATASCALE8 => 0, + PMSTATUSCONTROLDATASCALE => "00", + PORTVCCAPABILITYEXTENDEDVCCOUNT => PORTVCCAPABILITYEXTENDEDVCCOUNT, + PORTVCCAPABILITYVCARBCAP => PORTVCCAPABILITYVCARBCAP, + PORTVCCAPABILITYVCARBTABLEOFFSET => PORTVCCAPABILITYVCARBTABLEOFFSET, + RAMSHARETXRX => FALSE, + RESETMODE => RESETMODE, + RETRYRAMREADLATENCY => RETRYRAMREADLATENCY, + RETRYRAMSIZE => RETRYRAMSIZE, + RETRYRAMWIDTH => 0, + RETRYRAMWRITELATENCY => RETRYRAMWRITELATENCY, + RETRYREADADDRPIPE => FALSE, + RETRYREADDATAPIPE => FALSE, + RETRYWRITEPIPE => FALSE, + REVISIONID => REVISIONID, + RXREADADDRPIPE => FALSE, + RXREADDATAPIPE => FALSE, + RXWRITEPIPE => FALSE, + SELECTASMODE => FALSE, + SELECTDLLIF => FALSE, + SLOTCAPABILITYATTBUTTONPRESENT => FALSE, + SLOTCAPABILITYATTINDICATORPRESENT => FALSE, + SLOTCAPABILITYHOTPLUGCAPABLE => FALSE, + SLOTCAPABILITYHOTPLUGSURPRISE => FALSE, + SLOTCAPABILITYMSLSENSORPRESENT => FALSE, + SLOTCAPABILITYPHYSICALSLOTNUM => "0000000000000", + SLOTCAPABILITYPOWERCONTROLLERPRESENT => FALSE, + SLOTCAPABILITYPOWERINDICATORPRESENT => FALSE, + SLOTCAPABILITYSLOTPOWERLIMITSCALE => "00", + SLOTCAPABILITYSLOTPOWERLIMITVALUE => X"00", + SLOTIMPLEMENTED => FALSE, + SUBSYSTEMID => SUBSYSTEMID, + SUBSYSTEMVENDORID => SUBSYSTEMVENDORID, + TLRAMREADLATENCY => TLRAMREADLATENCY, + TLRAMWIDTH => 0, + TLRAMWRITELATENCY => TLRAMWRITELATENCY, + TXREADADDRPIPE => FALSE, + TXREADDATAPIPE => FALSE, + TXTSNFTS => TXTSNFTS, + TXTSNFTSCOMCLK => TXTSNFTSCOMCLK, + TXWRITEPIPE => FALSE, + UPSTREAMFACING => TRUE, + VC0RXFIFOBASEC => VC0RXFIFOBASEC, + VC0RXFIFOBASENP => VC0RXFIFOBASENP, + VC0RXFIFOBASEP => VC0RXFIFOBASEP, + VC0RXFIFOLIMITC => VC0RXFIFOLIMITC, + VC0RXFIFOLIMITNP => VC0RXFIFOLIMITNP, + VC0RXFIFOLIMITP => VC0RXFIFOLIMITP, + VC0TOTALCREDITSCD => VC0TOTALCREDITSCD, + VC0TOTALCREDITSCH => VC0TOTALCREDITSCH, + VC0TOTALCREDITSNPH => VC0TOTALCREDITSNPH, + VC0TOTALCREDITSPD => VC0TOTALCREDITSPD, + VC0TOTALCREDITSPH => VC0TOTALCREDITSPH, + VC0TXFIFOBASEC => VC0TXFIFOBASEC, + VC0TXFIFOBASENP => VC0TXFIFOBASENP, + VC0TXFIFOBASEP => VC0TXFIFOBASEP, + VC0TXFIFOLIMITC => VC0TXFIFOLIMITC, + VC0TXFIFOLIMITNP => VC0TXFIFOLIMITNP, + VC0TXFIFOLIMITP => VC0TXFIFOLIMITP, + VC1RXFIFOBASEC => VC1RXFIFOBASEC, + VC1RXFIFOBASENP => VC1RXFIFOBASENP, + VC1RXFIFOBASEP => VC1RXFIFOBASEP, + VC1RXFIFOLIMITC => VC1RXFIFOLIMITC, + VC1RXFIFOLIMITNP => VC1RXFIFOLIMITNP, + VC1RXFIFOLIMITP => VC1RXFIFOLIMITP, + VC1TOTALCREDITSCD => VC1TOTALCREDITSCD, + VC1TOTALCREDITSCH => VC1TOTALCREDITSCH, + VC1TOTALCREDITSNPH => VC1TOTALCREDITSNPH, + VC1TOTALCREDITSPD => VC1TOTALCREDITSPD, + VC1TOTALCREDITSPH => VC1TOTALCREDITSPH, + VC1TXFIFOBASEC => VC1TXFIFOBASEC, + VC1TXFIFOBASENP => VC1TXFIFOBASENP, + VC1TXFIFOBASEP => VC1TXFIFOBASEP, + VC1TXFIFOLIMITC => VC1TXFIFOLIMITC, + VC1TXFIFOLIMITNP => VC1TXFIFOLIMITNP, + VC1TXFIFOLIMITP => VC1TXFIFOLIMITP, + VCBASEPTR => VCBASEPTR, + VCCAPABILITYNEXTPTR => VCCAPABILITYNEXTPTR, + VENDORID => VENDORID, + XLINKSUPPORTED => FALSE, + XPBASEPTR => XPBASEPTR, + XPDEVICEPORTTYPE => XPDEVICEPORTTYPE, + XPMAXPAYLOAD => XPMAXPAYLOAD, + XPRCBCONTROL => 0 +) + +port map ( + AUXPOWER => AUXPOWER, + BUSMASTERENABLE => BUSMASTERENABLE, + CFGNEGOTIATEDLINKWIDTH => z6, + COMPLIANCEAVOID => COMPLIANCEAVOID, + CRMCFGBRIDGEHOTRESET => z1_0, + CRMCORECLK => CRMCORECLK, + CRMCORECLKDLO => CRMCORECLKDLO, + CRMCORECLKRXO => CRMCORECLKRXO, + CRMCORECLKTXO => CRMCORECLKTXO, + CRMDOHOTRESETN => CRMDOHOTRESETN, + CRMLINKRSTN => CRMLINKRSTN, + CRMMACRSTN => CRMMACRSTN, + CRMMGMTRSTN => CRMMGMTRSTN, + CRMNVRSTN => CRMNVRSTN, + CRMPWRSOFTRESETN => CRMPWRSOFTRESETN, + CRMRXHOTRESETN => OPEN1, + CRMTXHOTRESETN => z1_1, + CRMURSTN => CRMURSTN, + CRMUSERCFGRSTN => CRMUSERCFGRSTN, + CRMUSERCLK => CRMUSERCLK, + CRMUSERCLKRXO => CRMUSERCLKRXO, + CRMUSERCLKTXO => CRMUSERCLKTXO, + CROSSLINKSEED => z1_1, + DLLTXPMDLLPOUTSTANDING => DLLTXPMDLLPOUTSTANDING, + INTERRUPTDISABLE => INTERRUPTDISABLE, + IOSPACEENABLE => IOSPACEENABLE, + L0ACKNAKTIMERADJUSTMENT => z12, + L0ALLDOWNPORTSINL1 => z1_0, + L0ALLDOWNRXPORTSINL0S => z1_0, + L0ASAUTONOMOUSINITCOMPLETED => OPEN1, + L0ASE => z1_0, + L0ASPORTCOUNT => z8, + L0ASTURNPOOLBITSCONSUMED => z3, + L0ATTENTIONBUTTONPRESSED => z1_0, + L0ATTENTIONINDICATORCONTROL => OPEN2, + L0CFGASSPANTREEOWNEDSTATE => z1_0, + L0CFGASSTATECHANGECMD => z4, + L0CFGDISABLESCRAMBLE => L0CFGDISABLESCRAMBLE, + L0CFGEXTENDEDSYNC => z1_0, + L0CFGL0SENTRYENABLE => z1_0, + L0CFGL0SENTRYSUP => z1_0, + L0CFGL0SEXITLAT => z3, + L0CFGLINKDISABLE => z1_0, + L0CFGLOOPBACKACK => L0CFGLOOPBACKACK, + L0CFGLOOPBACKMASTER => L0CFGLOOPBACKMASTER, + L0CFGNEGOTIATEDMAXP => z3, + L0CFGVCENABLE => z8, + L0CFGVCID => z24, + L0COMPLETERID => L0COMPLETERID, + L0CORRERRMSGRCVD => OPEN1, + L0DLLASRXSTATE => OPEN2, + L0DLLASTXSTATE => OPEN1, + L0DLLERRORVECTOR => L0DLLERRORVECTOR, + L0DLLHOLDLINKUP => z1_0, + L0DLLRXACKOUTSTANDING => L0DLLRXACKOUTSTANDING, + L0DLLTXNONFCOUTSTANDING => L0DLLTXNONFCOUTSTANDING, + L0DLLTXOUTSTANDING => L0DLLTXOUTSTANDING, + L0DLLVCSTATUS => L0DLLVCSTATUS, + L0DLUPDOWN => L0DLUPDOWN, + L0ELECTROMECHANICALINTERLOCKENGAGED => z1_0, + L0ERRMSGREQID => OPEN16, + L0FATALERRMSGRCVD => OPEN1, + L0FIRSTCFGWRITEOCCURRED => L0FIRSTCFGWRITEOCCURRED, + L0FWDASSERTINTALEGACYINT => z1_0, + L0FWDASSERTINTBLEGACYINT => z1_0, + L0FWDASSERTINTCLEGACYINT => z1_0, + L0FWDASSERTINTDLEGACYINT => z1_0, + L0FWDCORRERRIN => z1_0, + L0FWDCORRERROUT => OPEN1, + L0FWDDEASSERTINTALEGACYINT => z1_0, + L0FWDDEASSERTINTBLEGACYINT => z1_0, + L0FWDDEASSERTINTCLEGACYINT => z1_0, + L0FWDDEASSERTINTDLEGACYINT => z1_0, + L0FWDFATALERRIN => z1_0, + L0FWDFATALERROUT => OPEN1, + L0FWDNONFATALERRIN => z1_0, + L0FWDNONFATALERROUT => OPEN1, + L0LEGACYINTFUNCT0 => L0LEGACYINTFUNCT0, + L0LTSSMSTATE => L0LTSSMSTATE, + L0MACENTEREDL0 => L0MACENTEREDL0, + L0MACLINKTRAINING => L0MACLINKTRAINING, + L0MACLINKUP => L0MACLINKUP, + L0MACNEGOTIATEDLINKWIDTH => L0MACNEGOTIATEDLINKWIDTH, + L0MACNEWSTATEACK => L0MACNEWSTATEACK, + L0MACRXL0SSTATE => L0MACRXL0SSTATE, + L0MACUPSTREAMDOWNSTREAM => OPEN1, + L0MCFOUND => OPEN3, + L0MRLSENSORCLOSEDN => z1_0, + L0MSIENABLE0 => L0MSIENABLE0, + L0MSIREQUEST0 => L0MSIREQUEST0, + L0MULTIMSGEN0 => L0MULTIMSGEN0, + L0NONFATALERRMSGRCVD => OPEN1, + L0PACKETHEADERFROMUSER => L0PACKETHEADERFROMUSER, + L0PMEACK => L0PMEACK, + L0PMEEN => L0PMEEN, + L0PMEREQIN => L0PMEREQIN, + L0PMEREQOUT => L0PMEREQOUT, + L0PORTNUMBER => z8, + L0POWERCONTROLLERCONTROL => OPEN1, + L0POWERFAULTDETECTED => z1_0, + L0POWERINDICATORCONTROL => OPEN2, + L0PRESENCEDETECTSLOTEMPTYN => z1_0, + L0PWRINHIBITTRANSFERS => OPEN1, + L0PWRL1STATE => L0PWRL1STATE, + L0PWRL23READYDEVICE => OPEN1, + L0PWRL23READYSTATE => L0PWRL23READYSTATE, + L0PWRNEWSTATEREQ => z1_0, + L0PWRNEXTLINKSTATE => z2, + L0PWRSTATE0 => L0PWRSTATE0, + L0PWRTURNOFFREQ => L0PWRTURNOFFREQ, + L0PWRTXL0SSTATE => L0PWRTXL0SSTATE, + L0RECEIVEDASSERTINTALEGACYINT => OPEN1, + L0RECEIVEDASSERTINTBLEGACYINT => OPEN1, + L0RECEIVEDASSERTINTCLEGACYINT => OPEN1, + L0RECEIVEDASSERTINTDLEGACYINT => OPEN1, + L0RECEIVEDDEASSERTINTALEGACYINT => OPEN1, + L0RECEIVEDDEASSERTINTBLEGACYINT => OPEN1, + L0RECEIVEDDEASSERTINTCLEGACYINT => OPEN1, + L0RECEIVEDDEASSERTINTDLEGACYINT => OPEN1, + L0REPLAYTIMERADJUSTMENT => z12, + L0ROOTTURNOFFREQ => z1_0, + L0RXBEACON => OPEN1, + L0RXDLLFCCMPLMCCRED => OPEN24, + L0RXDLLFCCMPLMCUPDATE => OPEN8, + L0RXDLLFCNPOSTBYPCRED => OPEN20, + L0RXDLLFCNPOSTBYPUPDATE => OPEN8, + L0RXDLLFCPOSTORDCRED => OPEN24, + L0RXDLLFCPOSTORDUPDATE => OPEN8, + L0RXDLLPM => L0RXDLLPM, + L0RXDLLPMTYPE => L0RXDLLPMTYPE, + L0RXDLLSBFCDATA => OPEN19, + L0RXDLLSBFCUPDATE => OPEN1, + L0RXDLLTLPECRCOK => OPEN1, + L0RXDLLTLPEND => OPEN2, + L0RXMACLINKERROR => L0RXMACLINKERROR, + L0RXTLTLPNONINITIALIZEDVC => z8, + L0SENDUNLOCKMESSAGE => z1_0, + L0SETCOMPLETERABORTERROR => L0SETCOMPLETERABORTERROR, + L0SETCOMPLETIONTIMEOUTCORRERROR => L0SETCOMPLETIONTIMEOUTCORRERROR, + L0SETCOMPLETIONTIMEOUTUNCORRERROR => L0SETCOMPLETIONTIMEOUTUNCORRERROR, + L0SETDETECTEDCORRERROR => L0SETDETECTEDCORRERROR, + L0SETDETECTEDFATALERROR => L0SETDETECTEDFATALERROR, + L0SETDETECTEDNONFATALERROR => L0SETDETECTEDNONFATALERROR, + L0SETLINKDETECTEDPARITYERROR => z1_0, + L0SETLINKMASTERDATAPARITY => z1_0, + L0SETLINKRECEIVEDMASTERABORT => z1_0, + L0SETLINKRECEIVEDTARGETABORT => z1_0, + L0SETLINKSIGNALLEDTARGETABORT => z1_0, + L0SETLINKSYSTEMERROR => z1_0, + L0SETUNEXPECTEDCOMPLETIONCORRERROR => L0SETUNEXPECTEDCOMPLETIONCORRERROR, + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR => L0SETUNEXPECTEDCOMPLETIONUNCORRERROR, + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR => L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR, + L0SETUNSUPPORTEDREQUESTOTHERERROR => L0SETUNSUPPORTEDREQUESTOTHERERROR, + L0SETUSERDETECTEDPARITYERROR => L0SETUSERDETECTEDPARITYERROR, + L0SETUSERMASTERDATAPARITY => L0SETUSERMASTERDATAPARITY, + L0SETUSERRECEIVEDMASTERABORT => L0SETUSERRECEIVEDMASTERABORT, + L0SETUSERRECEIVEDTARGETABORT => L0SETUSERRECEIVEDTARGETABORT, + L0SETUSERSIGNALLEDTARGETABORT => L0SETUSERSIGNALLEDTARGETABORT, + L0SETUSERSYSTEMERROR => L0SETUSERSYSTEMERROR, + L0STATSCFGOTHERRECEIVED => L0STATSCFGOTHERRECEIVED, + L0STATSCFGOTHERTRANSMITTED => L0STATSCFGOTHERTRANSMITTED, + L0STATSCFGRECEIVED => L0STATSCFGRECEIVED, + L0STATSCFGTRANSMITTED => L0STATSCFGTRANSMITTED, + L0STATSDLLPRECEIVED => L0STATSDLLPRECEIVED, + L0STATSDLLPTRANSMITTED => L0STATSDLLPTRANSMITTED, + L0STATSOSRECEIVED => L0STATSOSRECEIVED, + L0STATSOSTRANSMITTED => L0STATSOSTRANSMITTED, + L0STATSTLPRECEIVED => L0STATSTLPRECEIVED, + L0STATSTLPTRANSMITTED => L0STATSTLPTRANSMITTED, + L0TLASFCCREDSTARVATION => z1_0, + L0TLLINKRETRAIN => z1_0, + L0TOGGLEELECTROMECHANICALINTERLOCK => OPEN1, + L0TRANSACTIONSPENDING => L0TRANSACTIONSPENDING, + L0TRANSFORMEDVC => OPEN3, + L0TXBEACON => z1_0, + L0TXCFGPM => z1_0, + L0TXCFGPMTYPE => z3, + L0TXDLLFCCMPLMCUPDATED => OPEN8, + L0TXDLLFCNPOSTBYPUPDATED => OPEN8, + L0TXDLLFCPOSTORDUPDATED => OPEN8, + L0TXDLLPMUPDATED => OPEN1, + L0TXDLLSBFCUPDATED => OPEN1, + L0TXTLFCCMPLMCCRED => z160, + L0TXTLFCCMPLMCUPDATE => z16, + L0TXTLFCNPOSTBYPCRED => z192, + L0TXTLFCNPOSTBYPUPDATE => z16, + L0TXTLFCPOSTORDCRED => z160, + L0TXTLFCPOSTORDUPDATE => z16, + L0TXTLSBFCDATA => z19, + L0TXTLSBFCUPDATE => z1_0, + L0TXTLTLPDATA => z64, + L0TXTLTLPEDB => z1_0, + L0TXTLTLPENABLE => z2, + L0TXTLTLPEND => z2, + L0TXTLTLPLATENCY => z4, + L0TXTLTLPREQ => z1_0, + L0TXTLTLPREQEND => z1_0, + L0TXTLTLPWIDTH => z1_0, + L0UCBYPFOUND => OPEN4, + L0UCORDFOUND => OPEN4, + L0UNLOCKRECEIVED => L0UNLOCKRECEIVED, + L0UPSTREAMRXPORTINL0S => z1_0, + L0VC0PREVIEWEXPAND => z1_0, + L0WAKEN => z1_1, + LLKRX4DWHEADERN => OPEN1, + LLKRXCHCOMPLETIONAVAILABLEN => LLKRXCHCOMPLETIONAVAILABLEN, + LLKRXCHCOMPLETIONPARTIALN => OPEN8, + LLKRXCHCONFIGAVAILABLEN => OPEN1, + LLKRXCHCONFIGPARTIALN => OPEN1, + LLKRXCHFIFO => LLKRXCHFIFO, + LLKRXCHNONPOSTEDAVAILABLEN => LLKRXCHNONPOSTEDAVAILABLEN, + LLKRXCHNONPOSTEDPARTIALN => OPEN8, + LLKRXCHPOSTEDAVAILABLEN => LLKRXCHPOSTEDAVAILABLEN, + LLKRXCHPOSTEDPARTIALN => OPEN8, + LLKRXCHTC => LLKRXCHTC, + LLKRXDATA => LLKRXDATA, + LLKRXDSTCONTREQN => LLKRXDSTCONTREQN, + LLKRXDSTREQN => LLKRXDSTREQN, + LLKRXECRCBADN => OPEN1, + LLKRXEOFN => LLKRXEOFN, + LLKRXEOPN => LLKRXEOPN, + LLKRXPREFERREDTYPE => LLKRXPREFERREDTYPE, + LLKRXSOFN => LLKRXSOFN, + LLKRXSOPN => LLKRXSOPN, + LLKRXSRCDSCN => OPEN1, + LLKRXSRCLASTREQN => LLKRXSRCLASTREQN, + LLKRXSRCRDYN => LLKRXSRCRDYN, + LLKRXVALIDN => LLKRXVALIDN, + LLKTCSTATUS => LLKTCSTATUS, + LLKTX4DWHEADERN => z1_1, + LLKTXCHANSPACE => LLKTXCHANSPACE, + LLKTXCHCOMPLETIONREADYN => LLKTXCHCOMPLETIONREADYN, + LLKTXCHFIFO => LLKTXCHFIFO, + LLKTXCHNONPOSTEDREADYN => LLKTXCHNONPOSTEDREADYN, + LLKTXCHPOSTEDREADYN => LLKTXCHPOSTEDREADYN, + LLKTXCHTC => LLKTXCHTC, + LLKTXCOMPLETEN => z1_1, + LLKTXCONFIGREADYN => LLKTXCONFIGREADYN, + LLKTXCREATEECRCN => z1_1, + LLKTXDATA => LLKTXDATA, + LLKTXDSTRDYN => LLKTXDSTRDYN, + LLKTXENABLEN => LLKTXENABLEN, + LLKTXEOFN => LLKTXEOFN, + LLKTXEOPN => LLKTXEOPN, + LLKTXSOFN => LLKTXSOFN, + LLKTXSOPN => LLKTXSOPN, + LLKTXSRCDSCN => LLKTXSRCDSCN, + LLKTXSRCRDYN => LLKTXSRCRDYN, + MAINPOWER => z1_1, + MAXPAYLOADSIZE => MAXPAYLOADSIZE, + MAXREADREQUESTSIZE => MAXREADREQUESTSIZE, + MEMSPACEENABLE => MEMSPACEENABLE, + MGMTADDR => MGMTADDR, + MGMTBWREN => MGMTBWREN, + MGMTPSO => MGMTPSO, + MGMTRDATA => MGMTRDATA, + MGMTRDEN => MGMTRDEN, + MGMTSTATSCREDIT => MGMTSTATSCREDIT, + MGMTSTATSCREDITSEL => MGMTSTATSCREDITSEL, + MGMTWDATA => MGMTWDATA, + MGMTWREN => MGMTWREN, + MIMDLLBRADD => MIMDLLBRADD, + MIMDLLBRDATA => MIMDLLBRDATA, + MIMDLLBREN => MIMDLLBREN, + MIMDLLBWADD => MIMDLLBWADD, + MIMDLLBWDATA => MIMDLLBWDATA, + MIMDLLBWEN => MIMDLLBWEN, + MIMRXBRADD => MIMRXBRADD, + MIMRXBRDATA => MIMRXBRDATA, + MIMRXBREN => MIMRXBREN, + MIMRXBWADD => MIMRXBWADD, + MIMRXBWDATA => MIMRXBWDATA, + MIMRXBWEN => MIMRXBWEN, + MIMTXBRADD => MIMTXBRADD, + MIMTXBRDATA => MIMTXBRDATA, + MIMTXBREN => MIMTXBREN, + MIMTXBWADD => MIMTXBWADD, + MIMTXBWDATA => MIMTXBWDATA, + MIMTXBWEN => MIMTXBWEN, + PARITYERRORRESPONSE => PARITYERRORRESPONSE, + PIPEDESKEWLANESL0 => PIPEDESKEWLANESL0, + PIPEDESKEWLANESL1 => PIPEDESKEWLANESL1, + PIPEDESKEWLANESL2 => PIPEDESKEWLANESL2, + PIPEDESKEWLANESL3 => PIPEDESKEWLANESL3, + PIPEDESKEWLANESL4 => PIPEDESKEWLANESL4, + PIPEDESKEWLANESL5 => PIPEDESKEWLANESL5, + PIPEDESKEWLANESL6 => PIPEDESKEWLANESL6, + PIPEDESKEWLANESL7 => PIPEDESKEWLANESL7, + PIPEPHYSTATUSL0 => PIPEPHYSTATUSL0, + PIPEPHYSTATUSL1 => PIPEPHYSTATUSL1, + PIPEPHYSTATUSL2 => PIPEPHYSTATUSL2, + PIPEPHYSTATUSL3 => PIPEPHYSTATUSL3, + PIPEPHYSTATUSL4 => PIPEPHYSTATUSL4, + PIPEPHYSTATUSL5 => PIPEPHYSTATUSL5, + PIPEPHYSTATUSL6 => PIPEPHYSTATUSL6, + PIPEPHYSTATUSL7 => PIPEPHYSTATUSL7, + PIPEPOWERDOWNL0 => PIPEPOWERDOWNL0, + PIPEPOWERDOWNL1 => PIPEPOWERDOWNL1, + PIPEPOWERDOWNL2 => PIPEPOWERDOWNL2, + PIPEPOWERDOWNL3 => PIPEPOWERDOWNL3, + PIPEPOWERDOWNL4 => PIPEPOWERDOWNL4, + PIPEPOWERDOWNL5 => PIPEPOWERDOWNL5, + PIPEPOWERDOWNL6 => PIPEPOWERDOWNL6, + PIPEPOWERDOWNL7 => PIPEPOWERDOWNL7, + PIPERESETL0 => PIPERESETL0, + PIPERESETL1 => PIPERESETL1, + PIPERESETL2 => PIPERESETL2, + PIPERESETL3 => PIPERESETL3, + PIPERESETL4 => PIPERESETL4, + PIPERESETL5 => PIPERESETL5, + PIPERESETL6 => PIPERESETL6, + PIPERESETL7 => PIPERESETL7, + PIPERXCHANISALIGNEDL0 => PIPERXCHANISALIGNEDL0, + PIPERXCHANISALIGNEDL1 => PIPERXCHANISALIGNEDL1, + PIPERXCHANISALIGNEDL2 => PIPERXCHANISALIGNEDL2, + PIPERXCHANISALIGNEDL3 => PIPERXCHANISALIGNEDL3, + PIPERXCHANISALIGNEDL4 => PIPERXCHANISALIGNEDL4, + PIPERXCHANISALIGNEDL5 => PIPERXCHANISALIGNEDL5, + PIPERXCHANISALIGNEDL6 => PIPERXCHANISALIGNEDL6, + PIPERXCHANISALIGNEDL7 => PIPERXCHANISALIGNEDL7, + PIPERXDATAKL0 => PIPERXDATAKL0, + PIPERXDATAKL1 => PIPERXDATAKL1, + PIPERXDATAKL2 => PIPERXDATAKL2, + PIPERXDATAKL3 => PIPERXDATAKL3, + PIPERXDATAKL4 => PIPERXDATAKL4, + PIPERXDATAKL5 => PIPERXDATAKL5, + PIPERXDATAKL6 => PIPERXDATAKL6, + PIPERXDATAKL7 => PIPERXDATAKL7, + PIPERXDATAL0 => PIPERXDATAL0, + PIPERXDATAL1 => PIPERXDATAL1, + PIPERXDATAL2 => PIPERXDATAL2, + PIPERXDATAL3 => PIPERXDATAL3, + PIPERXDATAL4 => PIPERXDATAL4, + PIPERXDATAL5 => PIPERXDATAL5, + PIPERXDATAL6 => PIPERXDATAL6, + PIPERXDATAL7 => PIPERXDATAL7, + PIPERXELECIDLEL0 => PIPERXELECIDLEL0, + PIPERXELECIDLEL1 => PIPERXELECIDLEL1, + PIPERXELECIDLEL2 => PIPERXELECIDLEL2, + PIPERXELECIDLEL3 => PIPERXELECIDLEL3, + PIPERXELECIDLEL4 => PIPERXELECIDLEL4, + PIPERXELECIDLEL5 => PIPERXELECIDLEL5, + PIPERXELECIDLEL6 => PIPERXELECIDLEL6, + PIPERXELECIDLEL7 => PIPERXELECIDLEL7, + PIPERXPOLARITYL0 => PIPERXPOLARITYL0, + PIPERXPOLARITYL1 => PIPERXPOLARITYL1, + PIPERXPOLARITYL2 => PIPERXPOLARITYL2, + PIPERXPOLARITYL3 => PIPERXPOLARITYL3, + PIPERXPOLARITYL4 => PIPERXPOLARITYL4, + PIPERXPOLARITYL5 => PIPERXPOLARITYL5, + PIPERXPOLARITYL6 => PIPERXPOLARITYL6, + PIPERXPOLARITYL7 => PIPERXPOLARITYL7, + PIPERXSTATUSL0 => PIPERXSTATUSL0, + PIPERXSTATUSL1 => PIPERXSTATUSL1, + PIPERXSTATUSL2 => PIPERXSTATUSL2, + PIPERXSTATUSL3 => PIPERXSTATUSL3, + PIPERXSTATUSL4 => PIPERXSTATUSL4, + PIPERXSTATUSL5 => PIPERXSTATUSL5, + PIPERXSTATUSL6 => PIPERXSTATUSL6, + PIPERXSTATUSL7 => PIPERXSTATUSL7, + PIPERXVALIDL0 => PIPERXVALIDL0, + PIPERXVALIDL1 => PIPERXVALIDL1, + PIPERXVALIDL2 => PIPERXVALIDL2, + PIPERXVALIDL3 => PIPERXVALIDL3, + PIPERXVALIDL4 => PIPERXVALIDL4, + PIPERXVALIDL5 => PIPERXVALIDL5, + PIPERXVALIDL6 => PIPERXVALIDL6, + PIPERXVALIDL7 => PIPERXVALIDL7, + PIPETXCOMPLIANCEL0 => PIPETXCOMPLIANCEL0, + PIPETXCOMPLIANCEL1 => PIPETXCOMPLIANCEL1, + PIPETXCOMPLIANCEL2 => PIPETXCOMPLIANCEL2, + PIPETXCOMPLIANCEL3 => PIPETXCOMPLIANCEL3, + PIPETXCOMPLIANCEL4 => PIPETXCOMPLIANCEL4, + PIPETXCOMPLIANCEL5 => PIPETXCOMPLIANCEL5, + PIPETXCOMPLIANCEL6 => PIPETXCOMPLIANCEL6, + PIPETXCOMPLIANCEL7 => PIPETXCOMPLIANCEL7, + PIPETXDATAKL0 => PIPETXDATAKL0, + PIPETXDATAKL1 => PIPETXDATAKL1, + PIPETXDATAKL2 => PIPETXDATAKL2, + PIPETXDATAKL3 => PIPETXDATAKL3, + PIPETXDATAKL4 => PIPETXDATAKL4, + PIPETXDATAKL5 => PIPETXDATAKL5, + PIPETXDATAKL6 => PIPETXDATAKL6, + PIPETXDATAKL7 => PIPETXDATAKL7, + PIPETXDATAL0 => PIPETXDATAL0, + PIPETXDATAL1 => PIPETXDATAL1, + PIPETXDATAL2 => PIPETXDATAL2, + PIPETXDATAL3 => PIPETXDATAL3, + PIPETXDATAL4 => PIPETXDATAL4, + PIPETXDATAL5 => PIPETXDATAL5, + PIPETXDATAL6 => PIPETXDATAL6, + PIPETXDATAL7 => PIPETXDATAL7, + PIPETXDETECTRXLOOPBACKL0 => PIPETXDETECTRXLOOPBACKL0, + PIPETXDETECTRXLOOPBACKL1 => PIPETXDETECTRXLOOPBACKL1, + PIPETXDETECTRXLOOPBACKL2 => PIPETXDETECTRXLOOPBACKL2, + PIPETXDETECTRXLOOPBACKL3 => PIPETXDETECTRXLOOPBACKL3, + PIPETXDETECTRXLOOPBACKL4 => PIPETXDETECTRXLOOPBACKL4, + PIPETXDETECTRXLOOPBACKL5 => PIPETXDETECTRXLOOPBACKL5, + PIPETXDETECTRXLOOPBACKL6 => PIPETXDETECTRXLOOPBACKL6, + PIPETXDETECTRXLOOPBACKL7 => PIPETXDETECTRXLOOPBACKL7, + PIPETXELECIDLEL0 => PIPETXELECIDLEL0, + PIPETXELECIDLEL1 => PIPETXELECIDLEL1, + PIPETXELECIDLEL2 => PIPETXELECIDLEL2, + PIPETXELECIDLEL3 => PIPETXELECIDLEL3, + PIPETXELECIDLEL4 => PIPETXELECIDLEL4, + PIPETXELECIDLEL5 => PIPETXELECIDLEL5, + PIPETXELECIDLEL6 => PIPETXELECIDLEL6, + PIPETXELECIDLEL7 => PIPETXELECIDLEL7, + SERRENABLE => SERRENABLE, + URREPORTINGENABLE => URREPORTINGENABLE + +); + +end PCIE_EP_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2006 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / PCI Express +-- /___/ /\ Filename : pcie_internal_1_1.vhd +-- \ \ / \ Timestamp : Thu Dec 8 2005 +-- \___\/\___\ +-- +-- Revision: +-- 12/08/05 - Initial version. +-- 01/09/06 - Added architecture +-- 01/23/06 - Parameter MC updates CR#224562 +-- 01/27/06 - CR#224810 Remove GSR pins +-- 02/23/06 - Updated Header +-- 04/24/06 - CR#230393 - Updated timing according to the spreadsheets +-- 04/28/06 - CR#230712 - Spreadsheet update +-- 05/23/06 - CR#231962 - Add buffers for connectivity +-- 08/14/06 - CR#421379 - PCIE updated to PCIE_INTERNAL_1_1 +-- - spreadsheet updates on parameter default values +-- 10/26/06 - - replaced ZERO_DELAY with CLK_DELAY to be consistent with writers (PPC440 update) +-- End Revision + +----- CELL PCIE_INTERNAL_1_1 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity PCIE_INTERNAL_1_1 is +generic ( + ACTIVELANESIN : bit_vector := X"01"; + AERBASEPTR : bit_vector := X"110"; + AERCAPABILITYECRCCHECKCAPABLE : boolean := FALSE; + AERCAPABILITYECRCGENCAPABLE : boolean := FALSE; + AERCAPABILITYNEXTPTR : bit_vector := X"138"; + BAR0ADDRWIDTH : integer := 0; + BAR0EXIST : boolean := TRUE; + BAR0IOMEMN : integer := 0; + BAR0MASKWIDTH : bit_vector := X"14"; + BAR0PREFETCHABLE : boolean := TRUE; + BAR1ADDRWIDTH : integer := 0; + BAR1EXIST : boolean := FALSE; + BAR1IOMEMN : integer := 0; + BAR1MASKWIDTH : bit_vector := X"00"; + BAR1PREFETCHABLE : boolean := FALSE; + BAR2ADDRWIDTH : integer := 0; + BAR2EXIST : boolean := FALSE; + BAR2IOMEMN : integer := 0; + BAR2MASKWIDTH : bit_vector := X"00"; + BAR2PREFETCHABLE : boolean := FALSE; + BAR3ADDRWIDTH : integer := 0; + BAR3EXIST : boolean := FALSE; + BAR3IOMEMN : integer := 0; + BAR3MASKWIDTH : bit_vector := X"00"; + BAR3PREFETCHABLE : boolean := FALSE; + BAR4ADDRWIDTH : integer := 0; + BAR4EXIST : boolean := FALSE; + BAR4IOMEMN : integer := 0; + BAR4MASKWIDTH : bit_vector := X"00"; + BAR4PREFETCHABLE : boolean := FALSE; + BAR5EXIST : boolean := FALSE; + BAR5IOMEMN : integer := 0; + BAR5MASKWIDTH : bit_vector := X"00"; + BAR5PREFETCHABLE : boolean := FALSE; + CAPABILITIESPOINTER : bit_vector := X"40"; + CARDBUSCISPOINTER : bit_vector := X"00000000"; + CLASSCODE : bit_vector := X"058000"; + CLKDIVIDED : boolean := FALSE; + CONFIGROUTING : bit_vector := X"1"; + DEVICECAPABILITYENDPOINTL0SLATENCY : bit_vector := X"0"; + DEVICECAPABILITYENDPOINTL1LATENCY : bit_vector := X"0"; + DEVICEID : bit_vector := X"5050"; + DEVICESERIALNUMBER : bit_vector := X"E000000001000A35"; + DSNBASEPTR : bit_vector := X"148"; + DSNCAPABILITYNEXTPTR : bit_vector := X"154"; + DUALCOREENABLE : boolean := FALSE; + DUALCORESLAVE : boolean := FALSE; + DUALROLECFGCNTRLROOTEPN : integer := 0; + EXTCFGCAPPTR : bit_vector := X"00"; + EXTCFGXPCAPPTR : bit_vector := X"000"; + HEADERTYPE : bit_vector := X"00"; + INFINITECOMPLETIONS : boolean := TRUE; + INTERRUPTPIN : bit_vector := X"00"; + ISSWITCH : boolean := FALSE; + L0SEXITLATENCY : integer := 7; + L0SEXITLATENCYCOMCLK : integer := 7; + L1EXITLATENCY : integer := 7; + L1EXITLATENCYCOMCLK : integer := 7; + LINKCAPABILITYASPMSUPPORT : bit_vector := X"1"; + LINKCAPABILITYMAXLINKWIDTH : bit_vector := X"01"; + LINKSTATUSSLOTCLOCKCONFIG : boolean := FALSE; + LLKBYPASS : boolean := FALSE; + LOWPRIORITYVCCOUNT : integer := 0; + MSIBASEPTR : bit_vector := X"048"; + MSICAPABILITYMULTIMSGCAP : bit_vector := X"0"; + MSICAPABILITYNEXTPTR : bit_vector := X"60"; + PBBASEPTR : bit_vector := X"138"; + PBCAPABILITYDW0BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW0DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW0PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW0PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW0POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW0TYPE : bit_vector := X"0"; + PBCAPABILITYDW1BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW1DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW1PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW1PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW1POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW1TYPE : bit_vector := X"0"; + PBCAPABILITYDW2BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW2DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW2PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW2PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW2POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW2TYPE : bit_vector := X"0"; + PBCAPABILITYDW3BASEPOWER : bit_vector := X"00"; + PBCAPABILITYDW3DATASCALE : bit_vector := X"0"; + PBCAPABILITYDW3PMSTATE : bit_vector := X"0"; + PBCAPABILITYDW3PMSUBSTATE : bit_vector := X"0"; + PBCAPABILITYDW3POWERRAIL : bit_vector := X"0"; + PBCAPABILITYDW3TYPE : bit_vector := X"0"; + PBCAPABILITYNEXTPTR : bit_vector := X"148"; + PBCAPABILITYSYSTEMALLOCATED : boolean := FALSE; + PCIECAPABILITYINTMSGNUM : bit_vector := X"00"; + PCIECAPABILITYNEXTPTR : bit_vector := X"00"; + PCIECAPABILITYSLOTIMPL : boolean := FALSE; + PCIEREVISION : integer := 1; + PMBASEPTR : bit_vector := X"040"; + PMCAPABILITYAUXCURRENT : bit_vector := X"0"; + PMCAPABILITYD1SUPPORT : boolean := FALSE; + PMCAPABILITYD2SUPPORT : boolean := FALSE; + PMCAPABILITYDSI : boolean := TRUE; + PMCAPABILITYNEXTPTR : bit_vector := X"60"; + PMCAPABILITYPMESUPPORT : bit_vector := X"00"; + PMDATA0 : bit_vector := X"00"; + PMDATA1 : bit_vector := X"00"; + PMDATA2 : bit_vector := X"00"; + PMDATA3 : bit_vector := X"00"; + PMDATA4 : bit_vector := X"00"; + PMDATA5 : bit_vector := X"00"; + PMDATA6 : bit_vector := X"00"; + PMDATA7 : bit_vector := X"00"; + PMDATA8 : bit_vector := X"00"; + PMDATASCALE0 : integer := 0; + PMDATASCALE1 : integer := 0; + PMDATASCALE2 : integer := 0; + PMDATASCALE3 : integer := 0; + PMDATASCALE4 : integer := 0; + PMDATASCALE5 : integer := 0; + PMDATASCALE6 : integer := 0; + PMDATASCALE7 : integer := 0; + PMDATASCALE8 : integer := 0; + PMSTATUSCONTROLDATASCALE : bit_vector := X"0"; + PORTVCCAPABILITYEXTENDEDVCCOUNT : bit_vector := X"0"; + PORTVCCAPABILITYVCARBCAP : bit_vector := X"00"; + PORTVCCAPABILITYVCARBTABLEOFFSET : bit_vector := X"00"; + RAMSHARETXRX : boolean := FALSE; + RESETMODE : boolean := FALSE; + RETRYRAMREADLATENCY : integer := 3; + RETRYRAMSIZE : bit_vector := X"009"; + RETRYRAMWIDTH : integer := 0; + RETRYRAMWRITELATENCY : integer := 1; + RETRYREADADDRPIPE : boolean := FALSE; + RETRYREADDATAPIPE : boolean := FALSE; + RETRYWRITEPIPE : boolean := FALSE; + REVISIONID : bit_vector := X"00"; + RXREADADDRPIPE : boolean := FALSE; + RXREADDATAPIPE : boolean := FALSE; + RXWRITEPIPE : boolean := FALSE; + SELECTASMODE : boolean := FALSE; + SELECTDLLIF : boolean := FALSE; + SLOTCAPABILITYATTBUTTONPRESENT : boolean := FALSE; + SLOTCAPABILITYATTINDICATORPRESENT : boolean := FALSE; + SLOTCAPABILITYHOTPLUGCAPABLE : boolean := FALSE; + SLOTCAPABILITYHOTPLUGSURPRISE : boolean := FALSE; + SLOTCAPABILITYMSLSENSORPRESENT : boolean := FALSE; + SLOTCAPABILITYPHYSICALSLOTNUM : bit_vector := X"0000"; + SLOTCAPABILITYPOWERCONTROLLERPRESENT : boolean := FALSE; + SLOTCAPABILITYPOWERINDICATORPRESENT : boolean := FALSE; + SLOTCAPABILITYSLOTPOWERLIMITSCALE : bit_vector := X"0"; + SLOTCAPABILITYSLOTPOWERLIMITVALUE : bit_vector := X"00"; + SLOTIMPLEMENTED : boolean := FALSE; + SUBSYSTEMID : bit_vector := X"5050"; + SUBSYSTEMVENDORID : bit_vector := X"10EE"; + TLRAMREADLATENCY : integer := 3; + TLRAMWIDTH : integer := 0; + TLRAMWRITELATENCY : integer := 1; + TXREADADDRPIPE : boolean := FALSE; + TXREADDATAPIPE : boolean := FALSE; + TXTSNFTS : integer := 255; + TXTSNFTSCOMCLK : integer := 255; + TXWRITEPIPE : boolean := FALSE; + UPSTREAMFACING : boolean := TRUE; + VC0RXFIFOBASEC : bit_vector := X"0098"; + VC0RXFIFOBASENP : bit_vector := X"0080"; + VC0RXFIFOBASEP : bit_vector := X"0000"; + VC0RXFIFOLIMITC : bit_vector := X"0117"; + VC0RXFIFOLIMITNP : bit_vector := X"0097"; + VC0RXFIFOLIMITP : bit_vector := X"007f"; + VC0TOTALCREDITSCD : bit_vector := X"000"; + VC0TOTALCREDITSCH : bit_vector := X"00"; + VC0TOTALCREDITSNPH : bit_vector := X"08"; + VC0TOTALCREDITSPD : bit_vector := X"034"; + VC0TOTALCREDITSPH : bit_vector := X"08"; + VC0TXFIFOBASEC : bit_vector := X"0098"; + VC0TXFIFOBASENP : bit_vector := X"0080"; + VC0TXFIFOBASEP : bit_vector := X"0000"; + VC0TXFIFOLIMITC : bit_vector := X"0117"; + VC0TXFIFOLIMITNP : bit_vector := X"0097"; + VC0TXFIFOLIMITP : bit_vector := X"007f"; + VC1RXFIFOBASEC : bit_vector := X"0118"; + VC1RXFIFOBASENP : bit_vector := X"0118"; + VC1RXFIFOBASEP : bit_vector := X"0118"; + VC1RXFIFOLIMITC : bit_vector := X"0118"; + VC1RXFIFOLIMITNP : bit_vector := X"0118"; + VC1RXFIFOLIMITP : bit_vector := X"0118"; + VC1TOTALCREDITSCD : bit_vector := X"000"; + VC1TOTALCREDITSCH : bit_vector := X"00"; + VC1TOTALCREDITSNPH : bit_vector := X"00"; + VC1TOTALCREDITSPD : bit_vector := X"000"; + VC1TOTALCREDITSPH : bit_vector := X"00"; + VC1TXFIFOBASEC : bit_vector := X"0118"; + VC1TXFIFOBASENP : bit_vector := X"0118"; + VC1TXFIFOBASEP : bit_vector := X"0118"; + VC1TXFIFOLIMITC : bit_vector := X"0118"; + VC1TXFIFOLIMITNP : bit_vector := X"0118"; + VC1TXFIFOLIMITP : bit_vector := X"0118"; + VCBASEPTR : bit_vector := X"154"; + VCCAPABILITYNEXTPTR : bit_vector := X"000"; + VENDORID : bit_vector := X"10EE"; + XLINKSUPPORTED : boolean := FALSE; + XPBASEPTR : bit_vector := X"60"; + XPDEVICEPORTTYPE : bit_vector := X"0"; + XPMAXPAYLOAD : integer := 0; + XPRCBCONTROL : integer := 0 + + + + + ); + +port ( + BUSMASTERENABLE : out std_ulogic; + CRMDOHOTRESETN : out std_ulogic; + CRMPWRSOFTRESETN : out std_ulogic; + CRMRXHOTRESETN : out std_ulogic; + DLLTXPMDLLPOUTSTANDING : out std_ulogic; + INTERRUPTDISABLE : out std_ulogic; + IOSPACEENABLE : out std_ulogic; + L0ASAUTONOMOUSINITCOMPLETED : out std_ulogic; + L0ATTENTIONINDICATORCONTROL : out std_logic_vector(1 downto 0); + L0CFGLOOPBACKACK : out std_ulogic; + L0COMPLETERID : out std_logic_vector(12 downto 0); + L0CORRERRMSGRCVD : out std_ulogic; + L0DLLASRXSTATE : out std_logic_vector(1 downto 0); + L0DLLASTXSTATE : out std_ulogic; + L0DLLERRORVECTOR : out std_logic_vector(6 downto 0); + L0DLLRXACKOUTSTANDING : out std_ulogic; + L0DLLTXNONFCOUTSTANDING : out std_ulogic; + L0DLLTXOUTSTANDING : out std_ulogic; + L0DLLVCSTATUS : out std_logic_vector(7 downto 0); + L0DLUPDOWN : out std_logic_vector(7 downto 0); + L0ERRMSGREQID : out std_logic_vector(15 downto 0); + L0FATALERRMSGRCVD : out std_ulogic; + L0FIRSTCFGWRITEOCCURRED : out std_ulogic; + L0FWDCORRERROUT : out std_ulogic; + L0FWDFATALERROUT : out std_ulogic; + L0FWDNONFATALERROUT : out std_ulogic; + L0LTSSMSTATE : out std_logic_vector(3 downto 0); + L0MACENTEREDL0 : out std_ulogic; + L0MACLINKTRAINING : out std_ulogic; + L0MACLINKUP : out std_ulogic; + L0MACNEGOTIATEDLINKWIDTH : out std_logic_vector(3 downto 0); + L0MACNEWSTATEACK : out std_ulogic; + L0MACRXL0SSTATE : out std_ulogic; + L0MACUPSTREAMDOWNSTREAM : out std_ulogic; + L0MCFOUND : out std_logic_vector(2 downto 0); + L0MSIENABLE0 : out std_ulogic; + L0MULTIMSGEN0 : out std_logic_vector(2 downto 0); + L0NONFATALERRMSGRCVD : out std_ulogic; + L0PMEACK : out std_ulogic; + L0PMEEN : out std_ulogic; + L0PMEREQOUT : out std_ulogic; + L0POWERCONTROLLERCONTROL : out std_ulogic; + L0POWERINDICATORCONTROL : out std_logic_vector(1 downto 0); + L0PWRINHIBITTRANSFERS : out std_ulogic; + L0PWRL1STATE : out std_ulogic; + L0PWRL23READYDEVICE : out std_ulogic; + L0PWRL23READYSTATE : out std_ulogic; + L0PWRSTATE0 : out std_logic_vector(1 downto 0); + L0PWRTURNOFFREQ : out std_ulogic; + L0PWRTXL0SSTATE : out std_ulogic; + L0RECEIVEDASSERTINTALEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTBLEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTCLEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTDLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTALEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTBLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTCLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTDLEGACYINT : out std_ulogic; + L0RXBEACON : out std_ulogic; + L0RXDLLFCCMPLMCCRED : out std_logic_vector(23 downto 0); + L0RXDLLFCCMPLMCUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLFCNPOSTBYPCRED : out std_logic_vector(19 downto 0); + L0RXDLLFCNPOSTBYPUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLFCPOSTORDCRED : out std_logic_vector(23 downto 0); + L0RXDLLFCPOSTORDUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLPM : out std_ulogic; + L0RXDLLPMTYPE : out std_logic_vector(2 downto 0); + L0RXDLLSBFCDATA : out std_logic_vector(18 downto 0); + L0RXDLLSBFCUPDATE : out std_ulogic; + L0RXDLLTLPECRCOK : out std_ulogic; + L0RXDLLTLPEND : out std_logic_vector(1 downto 0); + L0RXMACLINKERROR : out std_logic_vector(1 downto 0); + L0STATSCFGOTHERRECEIVED : out std_ulogic; + L0STATSCFGOTHERTRANSMITTED : out std_ulogic; + L0STATSCFGRECEIVED : out std_ulogic; + L0STATSCFGTRANSMITTED : out std_ulogic; + L0STATSDLLPRECEIVED : out std_ulogic; + L0STATSDLLPTRANSMITTED : out std_ulogic; + L0STATSOSRECEIVED : out std_ulogic; + L0STATSOSTRANSMITTED : out std_ulogic; + L0STATSTLPRECEIVED : out std_ulogic; + L0STATSTLPTRANSMITTED : out std_ulogic; + L0TOGGLEELECTROMECHANICALINTERLOCK : out std_ulogic; + L0TRANSFORMEDVC : out std_logic_vector(2 downto 0); + L0TXDLLFCCMPLMCUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLFCNPOSTBYPUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLFCPOSTORDUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLPMUPDATED : out std_ulogic; + L0TXDLLSBFCUPDATED : out std_ulogic; + L0UCBYPFOUND : out std_logic_vector(3 downto 0); + L0UCORDFOUND : out std_logic_vector(3 downto 0); + L0UNLOCKRECEIVED : out std_ulogic; + LLKRX4DWHEADERN : out std_ulogic; + LLKRXCHCOMPLETIONAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHCOMPLETIONPARTIALN : out std_logic_vector(7 downto 0); + LLKRXCHCONFIGAVAILABLEN : out std_ulogic; + LLKRXCHCONFIGPARTIALN : out std_ulogic; + LLKRXCHNONPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHNONPOSTEDPARTIALN : out std_logic_vector(7 downto 0); + LLKRXCHPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHPOSTEDPARTIALN : out std_logic_vector(7 downto 0); + LLKRXDATA : out std_logic_vector(63 downto 0); + LLKRXECRCBADN : out std_ulogic; + LLKRXEOFN : out std_ulogic; + LLKRXEOPN : out std_ulogic; + LLKRXPREFERREDTYPE : out std_logic_vector(15 downto 0); + LLKRXSOFN : out std_ulogic; + LLKRXSOPN : out std_ulogic; + LLKRXSRCDSCN : out std_ulogic; + LLKRXSRCLASTREQN : out std_ulogic; + LLKRXSRCRDYN : out std_ulogic; + LLKRXVALIDN : out std_logic_vector(1 downto 0); + LLKTCSTATUS : out std_logic_vector(7 downto 0); + LLKTXCHANSPACE : out std_logic_vector(9 downto 0); + LLKTXCHCOMPLETIONREADYN : out std_logic_vector(7 downto 0); + LLKTXCHNONPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCHPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCONFIGREADYN : out std_ulogic; + LLKTXDSTRDYN : out std_ulogic; + MAXPAYLOADSIZE : out std_logic_vector(2 downto 0); + MAXREADREQUESTSIZE : out std_logic_vector(2 downto 0); + MEMSPACEENABLE : out std_ulogic; + MGMTPSO : out std_logic_vector(16 downto 0); + MGMTRDATA : out std_logic_vector(31 downto 0); + MGMTSTATSCREDIT : out std_logic_vector(11 downto 0); + MIMDLLBRADD : out std_logic_vector(11 downto 0); + MIMDLLBREN : out std_ulogic; + MIMDLLBWADD : out std_logic_vector(11 downto 0); + MIMDLLBWDATA : out std_logic_vector(63 downto 0); + MIMDLLBWEN : out std_ulogic; + MIMRXBRADD : out std_logic_vector(12 downto 0); + MIMRXBREN : out std_ulogic; + MIMRXBWADD : out std_logic_vector(12 downto 0); + MIMRXBWDATA : out std_logic_vector(63 downto 0); + MIMRXBWEN : out std_ulogic; + MIMTXBRADD : out std_logic_vector(12 downto 0); + MIMTXBREN : out std_ulogic; + MIMTXBWADD : out std_logic_vector(12 downto 0); + MIMTXBWDATA : out std_logic_vector(63 downto 0); + MIMTXBWEN : out std_ulogic; + PARITYERRORRESPONSE : out std_ulogic; + PIPEDESKEWLANESL0 : out std_ulogic; + PIPEDESKEWLANESL1 : out std_ulogic; + PIPEDESKEWLANESL2 : out std_ulogic; + PIPEDESKEWLANESL3 : out std_ulogic; + PIPEDESKEWLANESL4 : out std_ulogic; + PIPEDESKEWLANESL5 : out std_ulogic; + PIPEDESKEWLANESL6 : out std_ulogic; + PIPEDESKEWLANESL7 : out std_ulogic; + PIPEPOWERDOWNL0 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL1 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL2 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL3 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL4 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL5 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL6 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL7 : out std_logic_vector(1 downto 0); + PIPERESETL0 : out std_ulogic; + PIPERESETL1 : out std_ulogic; + PIPERESETL2 : out std_ulogic; + PIPERESETL3 : out std_ulogic; + PIPERESETL4 : out std_ulogic; + PIPERESETL5 : out std_ulogic; + PIPERESETL6 : out std_ulogic; + PIPERESETL7 : out std_ulogic; + PIPERXPOLARITYL0 : out std_ulogic; + PIPERXPOLARITYL1 : out std_ulogic; + PIPERXPOLARITYL2 : out std_ulogic; + PIPERXPOLARITYL3 : out std_ulogic; + PIPERXPOLARITYL4 : out std_ulogic; + PIPERXPOLARITYL5 : out std_ulogic; + PIPERXPOLARITYL6 : out std_ulogic; + PIPERXPOLARITYL7 : out std_ulogic; + PIPETXCOMPLIANCEL0 : out std_ulogic; + PIPETXCOMPLIANCEL1 : out std_ulogic; + PIPETXCOMPLIANCEL2 : out std_ulogic; + PIPETXCOMPLIANCEL3 : out std_ulogic; + PIPETXCOMPLIANCEL4 : out std_ulogic; + PIPETXCOMPLIANCEL5 : out std_ulogic; + PIPETXCOMPLIANCEL6 : out std_ulogic; + PIPETXCOMPLIANCEL7 : out std_ulogic; + PIPETXDATAKL0 : out std_ulogic; + PIPETXDATAKL1 : out std_ulogic; + PIPETXDATAKL2 : out std_ulogic; + PIPETXDATAKL3 : out std_ulogic; + PIPETXDATAKL4 : out std_ulogic; + PIPETXDATAKL5 : out std_ulogic; + PIPETXDATAKL6 : out std_ulogic; + PIPETXDATAKL7 : out std_ulogic; + PIPETXDATAL0 : out std_logic_vector(7 downto 0); + PIPETXDATAL1 : out std_logic_vector(7 downto 0); + PIPETXDATAL2 : out std_logic_vector(7 downto 0); + PIPETXDATAL3 : out std_logic_vector(7 downto 0); + PIPETXDATAL4 : out std_logic_vector(7 downto 0); + PIPETXDATAL5 : out std_logic_vector(7 downto 0); + PIPETXDATAL6 : out std_logic_vector(7 downto 0); + PIPETXDATAL7 : out std_logic_vector(7 downto 0); + PIPETXDETECTRXLOOPBACKL0 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL1 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL2 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL3 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL4 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL5 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL6 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL7 : out std_ulogic; + PIPETXELECIDLEL0 : out std_ulogic; + PIPETXELECIDLEL1 : out std_ulogic; + PIPETXELECIDLEL2 : out std_ulogic; + PIPETXELECIDLEL3 : out std_ulogic; + PIPETXELECIDLEL4 : out std_ulogic; + PIPETXELECIDLEL5 : out std_ulogic; + PIPETXELECIDLEL6 : out std_ulogic; + PIPETXELECIDLEL7 : out std_ulogic; + SERRENABLE : out std_ulogic; + URREPORTINGENABLE : out std_ulogic; + + AUXPOWER : in std_ulogic; + CFGNEGOTIATEDLINKWIDTH : in std_logic_vector(5 downto 0); + COMPLIANCEAVOID : in std_ulogic; + CRMCFGBRIDGEHOTRESET : in std_ulogic; + CRMCORECLK : in std_ulogic; + CRMCORECLKDLO : in std_ulogic; + CRMCORECLKRXO : in std_ulogic; + CRMCORECLKTXO : in std_ulogic; + CRMLINKRSTN : in std_ulogic; + CRMMACRSTN : in std_ulogic; + CRMMGMTRSTN : in std_ulogic; + CRMNVRSTN : in std_ulogic; + CRMTXHOTRESETN : in std_ulogic; + CRMURSTN : in std_ulogic; + CRMUSERCFGRSTN : in std_ulogic; + CRMUSERCLK : in std_ulogic; + CRMUSERCLKRXO : in std_ulogic; + CRMUSERCLKTXO : in std_ulogic; + CROSSLINKSEED : in std_ulogic; + L0ACKNAKTIMERADJUSTMENT : in std_logic_vector(11 downto 0); + L0ALLDOWNPORTSINL1 : in std_ulogic; + L0ALLDOWNRXPORTSINL0S : in std_ulogic; + L0ASE : in std_ulogic; + L0ASPORTCOUNT : in std_logic_vector(7 downto 0); + L0ASTURNPOOLBITSCONSUMED : in std_logic_vector(2 downto 0); + L0ATTENTIONBUTTONPRESSED : in std_ulogic; + L0CFGASSPANTREEOWNEDSTATE : in std_ulogic; + L0CFGASSTATECHANGECMD : in std_logic_vector(3 downto 0); + L0CFGDISABLESCRAMBLE : in std_ulogic; + L0CFGEXTENDEDSYNC : in std_ulogic; + L0CFGL0SENTRYENABLE : in std_ulogic; + L0CFGL0SENTRYSUP : in std_ulogic; + L0CFGL0SEXITLAT : in std_logic_vector(2 downto 0); + L0CFGLINKDISABLE : in std_ulogic; + L0CFGLOOPBACKMASTER : in std_ulogic; + L0CFGNEGOTIATEDMAXP : in std_logic_vector(2 downto 0); + L0CFGVCENABLE : in std_logic_vector(7 downto 0); + L0CFGVCID : in std_logic_vector(23 downto 0); + L0DLLHOLDLINKUP : in std_ulogic; + L0ELECTROMECHANICALINTERLOCKENGAGED : in std_ulogic; + L0FWDASSERTINTALEGACYINT : in std_ulogic; + L0FWDASSERTINTBLEGACYINT : in std_ulogic; + L0FWDASSERTINTCLEGACYINT : in std_ulogic; + L0FWDASSERTINTDLEGACYINT : in std_ulogic; + L0FWDCORRERRIN : in std_ulogic; + L0FWDDEASSERTINTALEGACYINT : in std_ulogic; + L0FWDDEASSERTINTBLEGACYINT : in std_ulogic; + L0FWDDEASSERTINTCLEGACYINT : in std_ulogic; + L0FWDDEASSERTINTDLEGACYINT : in std_ulogic; + L0FWDFATALERRIN : in std_ulogic; + L0FWDNONFATALERRIN : in std_ulogic; + L0LEGACYINTFUNCT0 : in std_ulogic; + L0MRLSENSORCLOSEDN : in std_ulogic; + L0MSIREQUEST0 : in std_logic_vector(3 downto 0); + L0PACKETHEADERFROMUSER : in std_logic_vector(127 downto 0); + L0PMEREQIN : in std_ulogic; + L0PORTNUMBER : in std_logic_vector(7 downto 0); + L0POWERFAULTDETECTED : in std_ulogic; + L0PRESENCEDETECTSLOTEMPTYN : in std_ulogic; + L0PWRNEWSTATEREQ : in std_ulogic; + L0PWRNEXTLINKSTATE : in std_logic_vector(1 downto 0); + L0REPLAYTIMERADJUSTMENT : in std_logic_vector(11 downto 0); + L0ROOTTURNOFFREQ : in std_ulogic; + L0RXTLTLPNONINITIALIZEDVC : in std_logic_vector(7 downto 0); + L0SENDUNLOCKMESSAGE : in std_ulogic; + L0SETCOMPLETERABORTERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTCORRERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTUNCORRERROR : in std_ulogic; + L0SETDETECTEDCORRERROR : in std_ulogic; + L0SETDETECTEDFATALERROR : in std_ulogic; + L0SETDETECTEDNONFATALERROR : in std_ulogic; + L0SETLINKDETECTEDPARITYERROR : in std_ulogic; + L0SETLINKMASTERDATAPARITY : in std_ulogic; + L0SETLINKRECEIVEDMASTERABORT : in std_ulogic; + L0SETLINKRECEIVEDTARGETABORT : in std_ulogic; + L0SETLINKSIGNALLEDTARGETABORT : in std_ulogic; + L0SETLINKSYSTEMERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONCORRERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTOTHERERROR : in std_ulogic; + L0SETUSERDETECTEDPARITYERROR : in std_ulogic; + L0SETUSERMASTERDATAPARITY : in std_ulogic; + L0SETUSERRECEIVEDMASTERABORT : in std_ulogic; + L0SETUSERRECEIVEDTARGETABORT : in std_ulogic; + L0SETUSERSIGNALLEDTARGETABORT : in std_ulogic; + L0SETUSERSYSTEMERROR : in std_ulogic; + L0TLASFCCREDSTARVATION : in std_ulogic; + L0TLLINKRETRAIN : in std_ulogic; + L0TRANSACTIONSPENDING : in std_ulogic; + L0TXBEACON : in std_ulogic; + L0TXCFGPM : in std_ulogic; + L0TXCFGPMTYPE : in std_logic_vector(2 downto 0); + L0TXTLFCCMPLMCCRED : in std_logic_vector(159 downto 0); + L0TXTLFCCMPLMCUPDATE : in std_logic_vector(15 downto 0); + L0TXTLFCNPOSTBYPCRED : in std_logic_vector(191 downto 0); + L0TXTLFCNPOSTBYPUPDATE : in std_logic_vector(15 downto 0); + L0TXTLFCPOSTORDCRED : in std_logic_vector(159 downto 0); + L0TXTLFCPOSTORDUPDATE : in std_logic_vector(15 downto 0); + L0TXTLSBFCDATA : in std_logic_vector(18 downto 0); + L0TXTLSBFCUPDATE : in std_ulogic; + L0TXTLTLPDATA : in std_logic_vector(63 downto 0); + L0TXTLTLPEDB : in std_ulogic; + L0TXTLTLPENABLE : in std_logic_vector(1 downto 0); + L0TXTLTLPEND : in std_logic_vector(1 downto 0); + L0TXTLTLPLATENCY : in std_logic_vector(3 downto 0); + L0TXTLTLPREQ : in std_ulogic; + L0TXTLTLPREQEND : in std_ulogic; + L0TXTLTLPWIDTH : in std_ulogic; + L0UPSTREAMRXPORTINL0S : in std_ulogic; + L0VC0PREVIEWEXPAND : in std_ulogic; + L0WAKEN : in std_ulogic; + LLKRXCHFIFO : in std_logic_vector(1 downto 0); + LLKRXCHTC : in std_logic_vector(2 downto 0); + LLKRXDSTCONTREQN : in std_ulogic; + LLKRXDSTREQN : in std_ulogic; + LLKTX4DWHEADERN : in std_ulogic; + LLKTXCHFIFO : in std_logic_vector(1 downto 0); + LLKTXCHTC : in std_logic_vector(2 downto 0); + LLKTXCOMPLETEN : in std_ulogic; + LLKTXCREATEECRCN : in std_ulogic; + LLKTXDATA : in std_logic_vector(63 downto 0); + LLKTXENABLEN : in std_logic_vector(1 downto 0); + LLKTXEOFN : in std_ulogic; + LLKTXEOPN : in std_ulogic; + LLKTXSOFN : in std_ulogic; + LLKTXSOPN : in std_ulogic; + LLKTXSRCDSCN : in std_ulogic; + LLKTXSRCRDYN : in std_ulogic; + MAINPOWER : in std_ulogic; + MGMTADDR : in std_logic_vector(10 downto 0); + MGMTBWREN : in std_logic_vector(3 downto 0); + MGMTRDEN : in std_ulogic; + MGMTSTATSCREDITSEL : in std_logic_vector(6 downto 0); + MGMTWDATA : in std_logic_vector(31 downto 0); + MGMTWREN : in std_ulogic; + MIMDLLBRDATA : in std_logic_vector(63 downto 0); + MIMRXBRDATA : in std_logic_vector(63 downto 0); + MIMTXBRDATA : in std_logic_vector(63 downto 0); + PIPEPHYSTATUSL0 : in std_ulogic; + PIPEPHYSTATUSL1 : in std_ulogic; + PIPEPHYSTATUSL2 : in std_ulogic; + PIPEPHYSTATUSL3 : in std_ulogic; + PIPEPHYSTATUSL4 : in std_ulogic; + PIPEPHYSTATUSL5 : in std_ulogic; + PIPEPHYSTATUSL6 : in std_ulogic; + PIPEPHYSTATUSL7 : in std_ulogic; + PIPERXCHANISALIGNEDL0 : in std_ulogic; + PIPERXCHANISALIGNEDL1 : in std_ulogic; + PIPERXCHANISALIGNEDL2 : in std_ulogic; + PIPERXCHANISALIGNEDL3 : in std_ulogic; + PIPERXCHANISALIGNEDL4 : in std_ulogic; + PIPERXCHANISALIGNEDL5 : in std_ulogic; + PIPERXCHANISALIGNEDL6 : in std_ulogic; + PIPERXCHANISALIGNEDL7 : in std_ulogic; + PIPERXDATAKL0 : in std_ulogic; + PIPERXDATAKL1 : in std_ulogic; + PIPERXDATAKL2 : in std_ulogic; + PIPERXDATAKL3 : in std_ulogic; + PIPERXDATAKL4 : in std_ulogic; + PIPERXDATAKL5 : in std_ulogic; + PIPERXDATAKL6 : in std_ulogic; + PIPERXDATAKL7 : in std_ulogic; + PIPERXDATAL0 : in std_logic_vector(7 downto 0); + PIPERXDATAL1 : in std_logic_vector(7 downto 0); + PIPERXDATAL2 : in std_logic_vector(7 downto 0); + PIPERXDATAL3 : in std_logic_vector(7 downto 0); + PIPERXDATAL4 : in std_logic_vector(7 downto 0); + PIPERXDATAL5 : in std_logic_vector(7 downto 0); + PIPERXDATAL6 : in std_logic_vector(7 downto 0); + PIPERXDATAL7 : in std_logic_vector(7 downto 0); + PIPERXELECIDLEL0 : in std_ulogic; + PIPERXELECIDLEL1 : in std_ulogic; + PIPERXELECIDLEL2 : in std_ulogic; + PIPERXELECIDLEL3 : in std_ulogic; + PIPERXELECIDLEL4 : in std_ulogic; + PIPERXELECIDLEL5 : in std_ulogic; + PIPERXELECIDLEL6 : in std_ulogic; + PIPERXELECIDLEL7 : in std_ulogic; + PIPERXSTATUSL0 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL1 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL2 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL3 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL4 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL5 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL6 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL7 : in std_logic_vector(2 downto 0); + PIPERXVALIDL0 : in std_ulogic; + PIPERXVALIDL1 : in std_ulogic; + PIPERXVALIDL2 : in std_ulogic; + PIPERXVALIDL3 : in std_ulogic; + PIPERXVALIDL4 : in std_ulogic; + PIPERXVALIDL5 : in std_ulogic; + PIPERXVALIDL6 : in std_ulogic; + PIPERXVALIDL7 : in std_ulogic + ); +end PCIE_INTERNAL_1_1; + +architecture PCIE_INTERNAL_1_1_V of PCIE_INTERNAL_1_1 is + + component PCIE_INTERNAL_1_1_SWIFT_BUS + port ( + BUSMASTERENABLE : out std_ulogic; + CRMDOHOTRESETN : out std_ulogic; + CRMPWRSOFTRESETN : out std_ulogic; + CRMRXHOTRESETN : out std_ulogic; + DLLTXPMDLLPOUTSTANDING : out std_ulogic; + INTERRUPTDISABLE : out std_ulogic; + IOSPACEENABLE : out std_ulogic; + L0ASAUTONOMOUSINITCOMPLETED : out std_ulogic; + L0ATTENTIONINDICATORCONTROL : out std_logic_vector(1 downto 0); + L0CFGLOOPBACKACK : out std_ulogic; + L0COMPLETERID : out std_logic_vector(12 downto 0); + L0CORRERRMSGRCVD : out std_ulogic; + L0DLLASRXSTATE : out std_logic_vector(1 downto 0); + L0DLLASTXSTATE : out std_ulogic; + L0DLLERRORVECTOR : out std_logic_vector(6 downto 0); + L0DLLRXACKOUTSTANDING : out std_ulogic; + L0DLLTXNONFCOUTSTANDING : out std_ulogic; + L0DLLTXOUTSTANDING : out std_ulogic; + L0DLLVCSTATUS : out std_logic_vector(7 downto 0); + L0DLUPDOWN : out std_logic_vector(7 downto 0); + L0ERRMSGREQID : out std_logic_vector(15 downto 0); + L0FATALERRMSGRCVD : out std_ulogic; + L0FIRSTCFGWRITEOCCURRED : out std_ulogic; + L0FWDCORRERROUT : out std_ulogic; + L0FWDFATALERROUT : out std_ulogic; + L0FWDNONFATALERROUT : out std_ulogic; + L0LTSSMSTATE : out std_logic_vector(3 downto 0); + L0MACENTEREDL0 : out std_ulogic; + L0MACLINKTRAINING : out std_ulogic; + L0MACLINKUP : out std_ulogic; + L0MACNEGOTIATEDLINKWIDTH : out std_logic_vector(3 downto 0); + L0MACNEWSTATEACK : out std_ulogic; + L0MACRXL0SSTATE : out std_ulogic; + L0MACUPSTREAMDOWNSTREAM : out std_ulogic; + L0MCFOUND : out std_logic_vector(2 downto 0); + L0MSIENABLE0 : out std_ulogic; + L0MULTIMSGEN0 : out std_logic_vector(2 downto 0); + L0NONFATALERRMSGRCVD : out std_ulogic; + L0PMEACK : out std_ulogic; + L0PMEEN : out std_ulogic; + L0PMEREQOUT : out std_ulogic; + L0POWERCONTROLLERCONTROL : out std_ulogic; + L0POWERINDICATORCONTROL : out std_logic_vector(1 downto 0); + L0PWRINHIBITTRANSFERS : out std_ulogic; + L0PWRL1STATE : out std_ulogic; + L0PWRL23READYDEVICE : out std_ulogic; + L0PWRL23READYSTATE : out std_ulogic; + L0PWRSTATE0 : out std_logic_vector(1 downto 0); + L0PWRTURNOFFREQ : out std_ulogic; + L0PWRTXL0SSTATE : out std_ulogic; + L0RECEIVEDASSERTINTALEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTBLEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTCLEGACYINT : out std_ulogic; + L0RECEIVEDASSERTINTDLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTALEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTBLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTCLEGACYINT : out std_ulogic; + L0RECEIVEDDEASSERTINTDLEGACYINT : out std_ulogic; + L0RXBEACON : out std_ulogic; + L0RXDLLFCCMPLMCCRED : out std_logic_vector(23 downto 0); + L0RXDLLFCCMPLMCUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLFCNPOSTBYPCRED : out std_logic_vector(19 downto 0); + L0RXDLLFCNPOSTBYPUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLFCPOSTORDCRED : out std_logic_vector(23 downto 0); + L0RXDLLFCPOSTORDUPDATE : out std_logic_vector(7 downto 0); + L0RXDLLPM : out std_ulogic; + L0RXDLLPMTYPE : out std_logic_vector(2 downto 0); + L0RXDLLSBFCDATA : out std_logic_vector(18 downto 0); + L0RXDLLSBFCUPDATE : out std_ulogic; + L0RXDLLTLPECRCOK : out std_ulogic; + L0RXDLLTLPEND : out std_logic_vector(1 downto 0); + L0RXMACLINKERROR : out std_logic_vector(1 downto 0); + L0STATSCFGOTHERRECEIVED : out std_ulogic; + L0STATSCFGOTHERTRANSMITTED : out std_ulogic; + L0STATSCFGRECEIVED : out std_ulogic; + L0STATSCFGTRANSMITTED : out std_ulogic; + L0STATSDLLPRECEIVED : out std_ulogic; + L0STATSDLLPTRANSMITTED : out std_ulogic; + L0STATSOSRECEIVED : out std_ulogic; + L0STATSOSTRANSMITTED : out std_ulogic; + L0STATSTLPRECEIVED : out std_ulogic; + L0STATSTLPTRANSMITTED : out std_ulogic; + L0TOGGLEELECTROMECHANICALINTERLOCK : out std_ulogic; + L0TRANSFORMEDVC : out std_logic_vector(2 downto 0); + L0TXDLLFCCMPLMCUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLFCNPOSTBYPUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLFCPOSTORDUPDATED : out std_logic_vector(7 downto 0); + L0TXDLLPMUPDATED : out std_ulogic; + L0TXDLLSBFCUPDATED : out std_ulogic; + L0UCBYPFOUND : out std_logic_vector(3 downto 0); + L0UCORDFOUND : out std_logic_vector(3 downto 0); + L0UNLOCKRECEIVED : out std_ulogic; + LLKRX4DWHEADERN : out std_ulogic; + LLKRXCHCOMPLETIONAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHCOMPLETIONPARTIALN : out std_logic_vector(7 downto 0); + LLKRXCHCONFIGAVAILABLEN : out std_ulogic; + LLKRXCHCONFIGPARTIALN : out std_ulogic; + LLKRXCHNONPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHNONPOSTEDPARTIALN : out std_logic_vector(7 downto 0); + LLKRXCHPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); + LLKRXCHPOSTEDPARTIALN : out std_logic_vector(7 downto 0); + LLKRXDATA : out std_logic_vector(63 downto 0); + LLKRXECRCBADN : out std_ulogic; + LLKRXEOFN : out std_ulogic; + LLKRXEOPN : out std_ulogic; + LLKRXPREFERREDTYPE : out std_logic_vector(15 downto 0); + LLKRXSOFN : out std_ulogic; + LLKRXSOPN : out std_ulogic; + LLKRXSRCDSCN : out std_ulogic; + LLKRXSRCLASTREQN : out std_ulogic; + LLKRXSRCRDYN : out std_ulogic; + LLKRXVALIDN : out std_logic_vector(1 downto 0); + LLKTCSTATUS : out std_logic_vector(7 downto 0); + LLKTXCHANSPACE : out std_logic_vector(9 downto 0); + LLKTXCHCOMPLETIONREADYN : out std_logic_vector(7 downto 0); + LLKTXCHNONPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCHPOSTEDREADYN : out std_logic_vector(7 downto 0); + LLKTXCONFIGREADYN : out std_ulogic; + LLKTXDSTRDYN : out std_ulogic; + MAXPAYLOADSIZE : out std_logic_vector(2 downto 0); + MAXREADREQUESTSIZE : out std_logic_vector(2 downto 0); + MEMSPACEENABLE : out std_ulogic; + MGMTPSO : out std_logic_vector(16 downto 0); + MGMTRDATA : out std_logic_vector(31 downto 0); + MGMTSTATSCREDIT : out std_logic_vector(11 downto 0); + MIMDLLBRADD : out std_logic_vector(11 downto 0); + MIMDLLBREN : out std_ulogic; + MIMDLLBWADD : out std_logic_vector(11 downto 0); + MIMDLLBWDATA : out std_logic_vector(63 downto 0); + MIMDLLBWEN : out std_ulogic; + MIMRXBRADD : out std_logic_vector(12 downto 0); + MIMRXBREN : out std_ulogic; + MIMRXBWADD : out std_logic_vector(12 downto 0); + MIMRXBWDATA : out std_logic_vector(63 downto 0); + MIMRXBWEN : out std_ulogic; + MIMTXBRADD : out std_logic_vector(12 downto 0); + MIMTXBREN : out std_ulogic; + MIMTXBWADD : out std_logic_vector(12 downto 0); + MIMTXBWDATA : out std_logic_vector(63 downto 0); + MIMTXBWEN : out std_ulogic; + PARITYERRORRESPONSE : out std_ulogic; + PIPEDESKEWLANESL0 : out std_ulogic; + PIPEDESKEWLANESL1 : out std_ulogic; + PIPEDESKEWLANESL2 : out std_ulogic; + PIPEDESKEWLANESL3 : out std_ulogic; + PIPEDESKEWLANESL4 : out std_ulogic; + PIPEDESKEWLANESL5 : out std_ulogic; + PIPEDESKEWLANESL6 : out std_ulogic; + PIPEDESKEWLANESL7 : out std_ulogic; + PIPEPOWERDOWNL0 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL1 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL2 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL3 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL4 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL5 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL6 : out std_logic_vector(1 downto 0); + PIPEPOWERDOWNL7 : out std_logic_vector(1 downto 0); + PIPERESETL0 : out std_ulogic; + PIPERESETL1 : out std_ulogic; + PIPERESETL2 : out std_ulogic; + PIPERESETL3 : out std_ulogic; + PIPERESETL4 : out std_ulogic; + PIPERESETL5 : out std_ulogic; + PIPERESETL6 : out std_ulogic; + PIPERESETL7 : out std_ulogic; + PIPERXPOLARITYL0 : out std_ulogic; + PIPERXPOLARITYL1 : out std_ulogic; + PIPERXPOLARITYL2 : out std_ulogic; + PIPERXPOLARITYL3 : out std_ulogic; + PIPERXPOLARITYL4 : out std_ulogic; + PIPERXPOLARITYL5 : out std_ulogic; + PIPERXPOLARITYL6 : out std_ulogic; + PIPERXPOLARITYL7 : out std_ulogic; + PIPETXCOMPLIANCEL0 : out std_ulogic; + PIPETXCOMPLIANCEL1 : out std_ulogic; + PIPETXCOMPLIANCEL2 : out std_ulogic; + PIPETXCOMPLIANCEL3 : out std_ulogic; + PIPETXCOMPLIANCEL4 : out std_ulogic; + PIPETXCOMPLIANCEL5 : out std_ulogic; + PIPETXCOMPLIANCEL6 : out std_ulogic; + PIPETXCOMPLIANCEL7 : out std_ulogic; + PIPETXDATAKL0 : out std_ulogic; + PIPETXDATAKL1 : out std_ulogic; + PIPETXDATAKL2 : out std_ulogic; + PIPETXDATAKL3 : out std_ulogic; + PIPETXDATAKL4 : out std_ulogic; + PIPETXDATAKL5 : out std_ulogic; + PIPETXDATAKL6 : out std_ulogic; + PIPETXDATAKL7 : out std_ulogic; + PIPETXDATAL0 : out std_logic_vector(7 downto 0); + PIPETXDATAL1 : out std_logic_vector(7 downto 0); + PIPETXDATAL2 : out std_logic_vector(7 downto 0); + PIPETXDATAL3 : out std_logic_vector(7 downto 0); + PIPETXDATAL4 : out std_logic_vector(7 downto 0); + PIPETXDATAL5 : out std_logic_vector(7 downto 0); + PIPETXDATAL6 : out std_logic_vector(7 downto 0); + PIPETXDATAL7 : out std_logic_vector(7 downto 0); + PIPETXDETECTRXLOOPBACKL0 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL1 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL2 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL3 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL4 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL5 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL6 : out std_ulogic; + PIPETXDETECTRXLOOPBACKL7 : out std_ulogic; + PIPETXELECIDLEL0 : out std_ulogic; + PIPETXELECIDLEL1 : out std_ulogic; + PIPETXELECIDLEL2 : out std_ulogic; + PIPETXELECIDLEL3 : out std_ulogic; + PIPETXELECIDLEL4 : out std_ulogic; + PIPETXELECIDLEL5 : out std_ulogic; + PIPETXELECIDLEL6 : out std_ulogic; + PIPETXELECIDLEL7 : out std_ulogic; + SERRENABLE : out std_ulogic; + URREPORTINGENABLE : out std_ulogic; + + AUXPOWER : in std_ulogic; + CFGNEGOTIATEDLINKWIDTH : in std_logic_vector(5 downto 0); + COMPLIANCEAVOID : in std_ulogic; + CRMCFGBRIDGEHOTRESET : in std_ulogic; + CRMCORECLK : in std_ulogic; + CRMCORECLKDLO : in std_ulogic; + CRMCORECLKRXO : in std_ulogic; + CRMCORECLKTXO : in std_ulogic; + CRMLINKRSTN : in std_ulogic; + CRMMACRSTN : in std_ulogic; + CRMMGMTRSTN : in std_ulogic; + CRMNVRSTN : in std_ulogic; + CRMTXHOTRESETN : in std_ulogic; + CRMURSTN : in std_ulogic; + CRMUSERCFGRSTN : in std_ulogic; + CRMUSERCLK : in std_ulogic; + CRMUSERCLKRXO : in std_ulogic; + CRMUSERCLKTXO : in std_ulogic; + CROSSLINKSEED : in std_ulogic; + GSR : in std_ulogic; + L0ACKNAKTIMERADJUSTMENT : in std_logic_vector(11 downto 0); + L0ALLDOWNPORTSINL1 : in std_ulogic; + L0ALLDOWNRXPORTSINL0S : in std_ulogic; + L0ASE : in std_ulogic; + L0ASPORTCOUNT : in std_logic_vector(7 downto 0); + L0ASTURNPOOLBITSCONSUMED : in std_logic_vector(2 downto 0); + L0ATTENTIONBUTTONPRESSED : in std_ulogic; + L0CFGASSPANTREEOWNEDSTATE : in std_ulogic; + L0CFGASSTATECHANGECMD : in std_logic_vector(3 downto 0); + L0CFGDISABLESCRAMBLE : in std_ulogic; + L0CFGEXTENDEDSYNC : in std_ulogic; + L0CFGL0SENTRYENABLE : in std_ulogic; + L0CFGL0SENTRYSUP : in std_ulogic; + L0CFGL0SEXITLAT : in std_logic_vector(2 downto 0); + L0CFGLINKDISABLE : in std_ulogic; + L0CFGLOOPBACKMASTER : in std_ulogic; + L0CFGNEGOTIATEDMAXP : in std_logic_vector(2 downto 0); + L0CFGVCENABLE : in std_logic_vector(7 downto 0); + L0CFGVCID : in std_logic_vector(23 downto 0); + L0DLLHOLDLINKUP : in std_ulogic; + L0ELECTROMECHANICALINTERLOCKENGAGED : in std_ulogic; + L0FWDASSERTINTALEGACYINT : in std_ulogic; + L0FWDASSERTINTBLEGACYINT : in std_ulogic; + L0FWDASSERTINTCLEGACYINT : in std_ulogic; + L0FWDASSERTINTDLEGACYINT : in std_ulogic; + L0FWDCORRERRIN : in std_ulogic; + L0FWDDEASSERTINTALEGACYINT : in std_ulogic; + L0FWDDEASSERTINTBLEGACYINT : in std_ulogic; + L0FWDDEASSERTINTCLEGACYINT : in std_ulogic; + L0FWDDEASSERTINTDLEGACYINT : in std_ulogic; + L0FWDFATALERRIN : in std_ulogic; + L0FWDNONFATALERRIN : in std_ulogic; + L0LEGACYINTFUNCT0 : in std_ulogic; + L0MRLSENSORCLOSEDN : in std_ulogic; + L0MSIREQUEST0 : in std_logic_vector(3 downto 0); + L0PACKETHEADERFROMUSER : in std_logic_vector(127 downto 0); + L0PMEREQIN : in std_ulogic; + L0PORTNUMBER : in std_logic_vector(7 downto 0); + L0POWERFAULTDETECTED : in std_ulogic; + L0PRESENCEDETECTSLOTEMPTYN : in std_ulogic; + L0PWRNEWSTATEREQ : in std_ulogic; + L0PWRNEXTLINKSTATE : in std_logic_vector(1 downto 0); + L0REPLAYTIMERADJUSTMENT : in std_logic_vector(11 downto 0); + L0ROOTTURNOFFREQ : in std_ulogic; + L0RXTLTLPNONINITIALIZEDVC : in std_logic_vector(7 downto 0); + L0SENDUNLOCKMESSAGE : in std_ulogic; + L0SETCOMPLETERABORTERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTCORRERROR : in std_ulogic; + L0SETCOMPLETIONTIMEOUTUNCORRERROR : in std_ulogic; + L0SETDETECTEDCORRERROR : in std_ulogic; + L0SETDETECTEDFATALERROR : in std_ulogic; + L0SETDETECTEDNONFATALERROR : in std_ulogic; + L0SETLINKDETECTEDPARITYERROR : in std_ulogic; + L0SETLINKMASTERDATAPARITY : in std_ulogic; + L0SETLINKRECEIVEDMASTERABORT : in std_ulogic; + L0SETLINKRECEIVEDTARGETABORT : in std_ulogic; + L0SETLINKSIGNALLEDTARGETABORT : in std_ulogic; + L0SETLINKSYSTEMERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONCORRERROR : in std_ulogic; + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR : in std_ulogic; + L0SETUNSUPPORTEDREQUESTOTHERERROR : in std_ulogic; + L0SETUSERDETECTEDPARITYERROR : in std_ulogic; + L0SETUSERMASTERDATAPARITY : in std_ulogic; + L0SETUSERRECEIVEDMASTERABORT : in std_ulogic; + L0SETUSERRECEIVEDTARGETABORT : in std_ulogic; + L0SETUSERSIGNALLEDTARGETABORT : in std_ulogic; + L0SETUSERSYSTEMERROR : in std_ulogic; + L0TLASFCCREDSTARVATION : in std_ulogic; + L0TLLINKRETRAIN : in std_ulogic; + L0TRANSACTIONSPENDING : in std_ulogic; + L0TXBEACON : in std_ulogic; + L0TXCFGPM : in std_ulogic; + L0TXCFGPMTYPE : in std_logic_vector(2 downto 0); + L0TXTLFCCMPLMCCRED : in std_logic_vector(159 downto 0); + L0TXTLFCCMPLMCUPDATE : in std_logic_vector(15 downto 0); + L0TXTLFCNPOSTBYPCRED : in std_logic_vector(191 downto 0); + L0TXTLFCNPOSTBYPUPDATE : in std_logic_vector(15 downto 0); + L0TXTLFCPOSTORDCRED : in std_logic_vector(159 downto 0); + L0TXTLFCPOSTORDUPDATE : in std_logic_vector(15 downto 0); + L0TXTLSBFCDATA : in std_logic_vector(18 downto 0); + L0TXTLSBFCUPDATE : in std_ulogic; + L0TXTLTLPDATA : in std_logic_vector(63 downto 0); + L0TXTLTLPEDB : in std_ulogic; + L0TXTLTLPENABLE : in std_logic_vector(1 downto 0); + L0TXTLTLPEND : in std_logic_vector(1 downto 0); + L0TXTLTLPLATENCY : in std_logic_vector(3 downto 0); + L0TXTLTLPREQ : in std_ulogic; + L0TXTLTLPREQEND : in std_ulogic; + L0TXTLTLPWIDTH : in std_ulogic; + L0UPSTREAMRXPORTINL0S : in std_ulogic; + L0VC0PREVIEWEXPAND : in std_ulogic; + L0WAKEN : in std_ulogic; + LLKRXCHFIFO : in std_logic_vector(1 downto 0); + LLKRXCHTC : in std_logic_vector(2 downto 0); + LLKRXDSTCONTREQN : in std_ulogic; + LLKRXDSTREQN : in std_ulogic; + LLKTX4DWHEADERN : in std_ulogic; + LLKTXCHFIFO : in std_logic_vector(1 downto 0); + LLKTXCHTC : in std_logic_vector(2 downto 0); + LLKTXCOMPLETEN : in std_ulogic; + LLKTXCREATEECRCN : in std_ulogic; + LLKTXDATA : in std_logic_vector(63 downto 0); + LLKTXENABLEN : in std_logic_vector(1 downto 0); + LLKTXEOFN : in std_ulogic; + LLKTXEOPN : in std_ulogic; + LLKTXSOFN : in std_ulogic; + LLKTXSOPN : in std_ulogic; + LLKTXSRCDSCN : in std_ulogic; + LLKTXSRCRDYN : in std_ulogic; + MAINPOWER : in std_ulogic; + MGMTADDR : in std_logic_vector(10 downto 0); + MGMTBWREN : in std_logic_vector(3 downto 0); + MGMTRDEN : in std_ulogic; + MGMTSTATSCREDITSEL : in std_logic_vector(6 downto 0); + MGMTWDATA : in std_logic_vector(31 downto 0); + MGMTWREN : in std_ulogic; + MIMDLLBRDATA : in std_logic_vector(63 downto 0); + MIMRXBRDATA : in std_logic_vector(63 downto 0); + MIMTXBRDATA : in std_logic_vector(63 downto 0); + PIPEPHYSTATUSL0 : in std_ulogic; + PIPEPHYSTATUSL1 : in std_ulogic; + PIPEPHYSTATUSL2 : in std_ulogic; + PIPEPHYSTATUSL3 : in std_ulogic; + PIPEPHYSTATUSL4 : in std_ulogic; + PIPEPHYSTATUSL5 : in std_ulogic; + PIPEPHYSTATUSL6 : in std_ulogic; + PIPEPHYSTATUSL7 : in std_ulogic; + PIPERXCHANISALIGNEDL0 : in std_ulogic; + PIPERXCHANISALIGNEDL1 : in std_ulogic; + PIPERXCHANISALIGNEDL2 : in std_ulogic; + PIPERXCHANISALIGNEDL3 : in std_ulogic; + PIPERXCHANISALIGNEDL4 : in std_ulogic; + PIPERXCHANISALIGNEDL5 : in std_ulogic; + PIPERXCHANISALIGNEDL6 : in std_ulogic; + PIPERXCHANISALIGNEDL7 : in std_ulogic; + PIPERXDATAKL0 : in std_ulogic; + PIPERXDATAKL1 : in std_ulogic; + PIPERXDATAKL2 : in std_ulogic; + PIPERXDATAKL3 : in std_ulogic; + PIPERXDATAKL4 : in std_ulogic; + PIPERXDATAKL5 : in std_ulogic; + PIPERXDATAKL6 : in std_ulogic; + PIPERXDATAKL7 : in std_ulogic; + PIPERXDATAL0 : in std_logic_vector(7 downto 0); + PIPERXDATAL1 : in std_logic_vector(7 downto 0); + PIPERXDATAL2 : in std_logic_vector(7 downto 0); + PIPERXDATAL3 : in std_logic_vector(7 downto 0); + PIPERXDATAL4 : in std_logic_vector(7 downto 0); + PIPERXDATAL5 : in std_logic_vector(7 downto 0); + PIPERXDATAL6 : in std_logic_vector(7 downto 0); + PIPERXDATAL7 : in std_logic_vector(7 downto 0); + PIPERXELECIDLEL0 : in std_ulogic; + PIPERXELECIDLEL1 : in std_ulogic; + PIPERXELECIDLEL2 : in std_ulogic; + PIPERXELECIDLEL3 : in std_ulogic; + PIPERXELECIDLEL4 : in std_ulogic; + PIPERXELECIDLEL5 : in std_ulogic; + PIPERXELECIDLEL6 : in std_ulogic; + PIPERXELECIDLEL7 : in std_ulogic; + PIPERXSTATUSL0 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL1 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL2 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL3 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL4 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL5 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL6 : in std_logic_vector(2 downto 0); + PIPERXSTATUSL7 : in std_logic_vector(2 downto 0); + PIPERXVALIDL0 : in std_ulogic; + PIPERXVALIDL1 : in std_ulogic; + PIPERXVALIDL2 : in std_ulogic; + PIPERXVALIDL3 : in std_ulogic; + PIPERXVALIDL4 : in std_ulogic; + PIPERXVALIDL5 : in std_ulogic; + PIPERXVALIDL6 : in std_ulogic; + PIPERXVALIDL7 : in std_ulogic; + + MCACTIVELANESIN : in std_logic_vector(7 downto 0); + MCAERBASEPTR : in std_logic_vector(11 downto 0); + MCAERCAPABILITYECRCCHECKCAPABLE : in std_ulogic; + MCAERCAPABILITYECRCGENCAPABLE : in std_ulogic; + MCAERCAPABILITYNEXTPTR : in std_logic_vector(11 downto 0); + MCBAR0ADDRWIDTH : in std_ulogic; + MCBAR0EXIST : in std_ulogic; + MCBAR0IOMEMN : in std_ulogic; + MCBAR0MASKWIDTH : in std_logic_vector(5 downto 0); + MCBAR0PREFETCHABLE : in std_ulogic; + MCBAR1ADDRWIDTH : in std_ulogic; + MCBAR1EXIST : in std_ulogic; + MCBAR1IOMEMN : in std_ulogic; + MCBAR1MASKWIDTH : in std_logic_vector(5 downto 0); + MCBAR1PREFETCHABLE : in std_ulogic; + MCBAR2ADDRWIDTH : in std_ulogic; + MCBAR2EXIST : in std_ulogic; + MCBAR2IOMEMN : in std_ulogic; + MCBAR2MASKWIDTH : in std_logic_vector(5 downto 0); + MCBAR2PREFETCHABLE : in std_ulogic; + MCBAR3ADDRWIDTH : in std_ulogic; + MCBAR3EXIST : in std_ulogic; + MCBAR3IOMEMN : in std_ulogic; + MCBAR3MASKWIDTH : in std_logic_vector(5 downto 0); + MCBAR3PREFETCHABLE : in std_ulogic; + MCBAR4ADDRWIDTH : in std_ulogic; + MCBAR4EXIST : in std_ulogic; + MCBAR4IOMEMN : in std_ulogic; + MCBAR4MASKWIDTH : in std_logic_vector(5 downto 0); + MCBAR4PREFETCHABLE : in std_ulogic; + MCBAR5ADDRWIDTH : in std_ulogic; + MCBAR5EXIST : in std_ulogic; + MCBAR5IOMEMN : in std_ulogic; + MCBAR5MASKWIDTH : in std_logic_vector(5 downto 0); + MCBAR5PREFETCHABLE : in std_ulogic; + MCCAPABILITIESPOINTER : in std_logic_vector(7 downto 0); + MCCARDBUSCISPOINTER : in std_logic_vector(31 downto 0); + MCCLASSCODE : in std_logic_vector(23 downto 0); +-- MCCLKDIVIDED : in std_ulogic; + MCCONFIGROUTING : in std_logic_vector(2 downto 0); + MCDEVICECAPABILITYENDPOINTL0SLATENCY : in std_logic_vector(2 downto 0); + MCDEVICECAPABILITYENDPOINTL1LATENCY : in std_logic_vector(2 downto 0); + MCDEVICEID : in std_logic_vector(15 downto 0); + MCDEVICESERIALNUMBER : in std_logic_vector(63 downto 0); + MCDSNBASEPTR : in std_logic_vector(11 downto 0); + MCDSNCAPABILITYNEXTPTR : in std_logic_vector(11 downto 0); + MCDUALCOREENABLE : in std_ulogic; + MCDUALCORESLAVE : in std_ulogic; + MCDUALROLECFGCNTRLROOTEPN : in std_ulogic; + MCEXTCFGCAPPTR : in std_logic_vector(7 downto 0); + MCEXTCFGXPCAPPTR : in std_logic_vector(11 downto 0); + MCHEADERTYPE : in std_logic_vector(7 downto 0); + MCINFINITECOMPLETIONS : in std_ulogic; + MCINTERRUPTPIN : in std_logic_vector(7 downto 0); + MCISSWITCH : in std_ulogic; + MCL0SEXITLATENCY : in std_logic_vector(2 downto 0); + MCL0SEXITLATENCYCOMCLK : in std_logic_vector(2 downto 0); + MCL1EXITLATENCY : in std_logic_vector(2 downto 0); + MCL1EXITLATENCYCOMCLK : in std_logic_vector(2 downto 0); + MCLINKCAPABILITYASPMSUPPORT : in std_logic_vector(1 downto 0); + MCLINKCAPABILITYMAXLINKWIDTH : in std_logic_vector(5 downto 0); + MCLINKSTATUSSLOTCLOCKCONFIG : in std_ulogic; + MCLLKBYPASS : in std_ulogic; + MCLOWPRIORITYVCCOUNT : in std_logic_vector(2 downto 0); + MCMSIBASEPTR : in std_logic_vector(11 downto 0); + MCMSICAPABILITYMULTIMSGCAP : in std_logic_vector(2 downto 0); + MCMSICAPABILITYNEXTPTR : in std_logic_vector(7 downto 0); + MCPBBASEPTR : in std_logic_vector(11 downto 0); + MCPBCAPABILITYDW0BASEPOWER : in std_logic_vector(7 downto 0); + MCPBCAPABILITYDW0DATASCALE : in std_logic_vector(1 downto 0); + MCPBCAPABILITYDW0PMSTATE : in std_logic_vector(1 downto 0); + MCPBCAPABILITYDW0PMSUBSTATE : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW0POWERRAIL : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW0TYPE : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW1BASEPOWER : in std_logic_vector(7 downto 0); + MCPBCAPABILITYDW1DATASCALE : in std_logic_vector(1 downto 0); + MCPBCAPABILITYDW1PMSTATE : in std_logic_vector(1 downto 0); + MCPBCAPABILITYDW1PMSUBSTATE : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW1POWERRAIL : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW1TYPE : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW2BASEPOWER : in std_logic_vector(7 downto 0); + MCPBCAPABILITYDW2DATASCALE : in std_logic_vector(1 downto 0); + MCPBCAPABILITYDW2PMSTATE : in std_logic_vector(1 downto 0); + MCPBCAPABILITYDW2PMSUBSTATE : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW2POWERRAIL : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW2TYPE : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW3BASEPOWER : in std_logic_vector(7 downto 0); + MCPBCAPABILITYDW3DATASCALE : in std_logic_vector(1 downto 0); + MCPBCAPABILITYDW3PMSTATE : in std_logic_vector(1 downto 0); + MCPBCAPABILITYDW3PMSUBSTATE : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW3POWERRAIL : in std_logic_vector(2 downto 0); + MCPBCAPABILITYDW3TYPE : in std_logic_vector(2 downto 0); + MCPBCAPABILITYNEXTPTR : in std_logic_vector(11 downto 0); + MCPBCAPABILITYSYSTEMALLOCATED : in std_ulogic; + MCPCIECAPABILITYINTMSGNUM : in std_logic_vector(4 downto 0); + MCPCIECAPABILITYNEXTPTR : in std_logic_vector(7 downto 0); + MCPCIECAPABILITYSLOTIMPL : in std_ulogic; + MCPCIEREVISION : in std_ulogic; + MCPMBASEPTR : in std_logic_vector(11 downto 0); + MCPMCAPABILITYAUXCURRENT : in std_logic_vector(2 downto 0); + MCPMCAPABILITYD1SUPPORT : in std_ulogic; + MCPMCAPABILITYD2SUPPORT : in std_ulogic; + MCPMCAPABILITYDSI : in std_ulogic; + MCPMCAPABILITYNEXTPTR : in std_logic_vector(7 downto 0); + MCPMCAPABILITYPMESUPPORT : in std_logic_vector(4 downto 0); + MCPMDATA0 : in std_logic_vector(7 downto 0); + MCPMDATA1 : in std_logic_vector(7 downto 0); + MCPMDATA2 : in std_logic_vector(7 downto 0); + MCPMDATA3 : in std_logic_vector(7 downto 0); + MCPMDATA4 : in std_logic_vector(7 downto 0); + MCPMDATA5 : in std_logic_vector(7 downto 0); + MCPMDATA6 : in std_logic_vector(7 downto 0); + MCPMDATA7 : in std_logic_vector(7 downto 0); + MCPMDATA8 : in std_logic_vector(7 downto 0); + MCPMDATASCALE0 : in std_logic_vector(1 downto 0); + MCPMDATASCALE1 : in std_logic_vector(1 downto 0); + MCPMDATASCALE2 : in std_logic_vector(1 downto 0); + MCPMDATASCALE3 : in std_logic_vector(1 downto 0); + MCPMDATASCALE4 : in std_logic_vector(1 downto 0); + MCPMDATASCALE5 : in std_logic_vector(1 downto 0); + MCPMDATASCALE6 : in std_logic_vector(1 downto 0); + MCPMDATASCALE7 : in std_logic_vector(1 downto 0); + MCPMDATASCALE8 : in std_logic_vector(1 downto 0); + MCPMSTATUSCONTROLDATASCALE : in std_logic_vector(1 downto 0); + MCPORTVCCAPABILITYEXTENDEDVCCOUNT : in std_logic_vector(2 downto 0); + MCPORTVCCAPABILITYVCARBCAP : in std_logic_vector(7 downto 0); + MCPORTVCCAPABILITYVCARBTABLEOFFSET : in std_logic_vector(7 downto 0); + MCRAMSHARETXRX : in std_ulogic; + MCRESETMODE : in std_ulogic; + MCRETRYRAMREADLATENCY : in std_logic_vector(2 downto 0); + MCRETRYRAMSIZE : in std_logic_vector(11 downto 0); + MCRETRYRAMWIDTH : in std_ulogic; + MCRETRYRAMWRITELATENCY : in std_logic_vector(2 downto 0); + MCRETRYREADADDRPIPE : in std_ulogic; + MCRETRYREADDATAPIPE : in std_ulogic; + MCRETRYWRITEPIPE : in std_ulogic; + MCREVISIONID : in std_logic_vector(7 downto 0); + MCRXREADADDRPIPE : in std_ulogic; + MCRXREADDATAPIPE : in std_ulogic; + MCRXWRITEPIPE : in std_ulogic; + MCSELECTASMODE : in std_ulogic; + MCSELECTDLLIF : in std_ulogic; + MCSLOTCAPABILITYATTBUTTONPRESENT : in std_ulogic; + MCSLOTCAPABILITYATTINDICATORPRESENT : in std_ulogic; + MCSLOTCAPABILITYHOTPLUGCAPABLE : in std_ulogic; + MCSLOTCAPABILITYHOTPLUGSURPRISE : in std_ulogic; + MCSLOTCAPABILITYMSLSENSORPRESENT : in std_ulogic; + MCSLOTCAPABILITYPHYSICALSLOTNUM : in std_logic_vector(12 downto 0); + MCSLOTCAPABILITYPOWERCONTROLLERPRESENT : in std_ulogic; + MCSLOTCAPABILITYPOWERINDICATORPRESENT : in std_ulogic; + MCSLOTCAPABILITYSLOTPOWERLIMITSCALE : in std_logic_vector(1 downto 0); + MCSLOTCAPABILITYSLOTPOWERLIMITVALUE : in std_logic_vector(7 downto 0); + MCSLOTIMPLEMENTED : in std_ulogic; + MCSUBSYSTEMID : in std_logic_vector(15 downto 0); + MCSUBSYSTEMVENDORID : in std_logic_vector(15 downto 0); + MCTLRAMREADLATENCY : in std_logic_vector(2 downto 0); + MCTLRAMWIDTH : in std_ulogic; + MCTLRAMWRITELATENCY : in std_logic_vector(2 downto 0); + MCTXREADADDRPIPE : in std_ulogic; + MCTXREADDATAPIPE : in std_ulogic; + MCTXTSNFTS : in std_logic_vector(7 downto 0); + MCTXTSNFTSCOMCLK : in std_logic_vector(7 downto 0); + MCTXWRITEPIPE : in std_ulogic; + MCUPSTREAMFACING : in std_ulogic; + MCVC0RXFIFOBASEC : in std_logic_vector(12 downto 0); + MCVC0RXFIFOBASENP : in std_logic_vector(12 downto 0); + MCVC0RXFIFOBASEP : in std_logic_vector(12 downto 0); + MCVC0RXFIFOLIMITC : in std_logic_vector(12 downto 0); + MCVC0RXFIFOLIMITNP : in std_logic_vector(12 downto 0); + MCVC0RXFIFOLIMITP : in std_logic_vector(12 downto 0); + MCVC0TOTALCREDITSCD : in std_logic_vector(10 downto 0); + MCVC0TOTALCREDITSCH : in std_logic_vector(6 downto 0); + MCVC0TOTALCREDITSNPH : in std_logic_vector(6 downto 0); + MCVC0TOTALCREDITSPD : in std_logic_vector(10 downto 0); + MCVC0TOTALCREDITSPH : in std_logic_vector(6 downto 0); + MCVC0TXFIFOBASEC : in std_logic_vector(12 downto 0); + MCVC0TXFIFOBASENP : in std_logic_vector(12 downto 0); + MCVC0TXFIFOBASEP : in std_logic_vector(12 downto 0); + MCVC0TXFIFOLIMITC : in std_logic_vector(12 downto 0); + MCVC0TXFIFOLIMITNP : in std_logic_vector(12 downto 0); + MCVC0TXFIFOLIMITP : in std_logic_vector(12 downto 0); + MCVC1RXFIFOBASEC : in std_logic_vector(12 downto 0); + MCVC1RXFIFOBASENP : in std_logic_vector(12 downto 0); + MCVC1RXFIFOBASEP : in std_logic_vector(12 downto 0); + MCVC1RXFIFOLIMITC : in std_logic_vector(12 downto 0); + MCVC1RXFIFOLIMITNP : in std_logic_vector(12 downto 0); + MCVC1RXFIFOLIMITP : in std_logic_vector(12 downto 0); + MCVC1TOTALCREDITSCD : in std_logic_vector(10 downto 0); + MCVC1TOTALCREDITSCH : in std_logic_vector(6 downto 0); + MCVC1TOTALCREDITSNPH : in std_logic_vector(6 downto 0); + MCVC1TOTALCREDITSPD : in std_logic_vector(10 downto 0); + MCVC1TOTALCREDITSPH : in std_logic_vector(6 downto 0); + MCVC1TXFIFOBASEC : in std_logic_vector(12 downto 0); + MCVC1TXFIFOBASENP : in std_logic_vector(12 downto 0); + MCVC1TXFIFOBASEP : in std_logic_vector(12 downto 0); + MCVC1TXFIFOLIMITC : in std_logic_vector(12 downto 0); + MCVC1TXFIFOLIMITNP : in std_logic_vector(12 downto 0); + MCVC1TXFIFOLIMITP : in std_logic_vector(12 downto 0); + MCVCBASEPTR : in std_logic_vector(11 downto 0); + MCVCCAPABILITYNEXTPTR : in std_logic_vector(11 downto 0); + MCVENDORID : in std_logic_vector(15 downto 0); + MCXLINKSUPPORTED : in std_ulogic; + MCXPBASEPTR : in std_logic_vector(7 downto 0); + MCXPDEVICEPORTTYPE : in std_logic_vector(3 downto 0); + MCXPMAXPAYLOAD : in std_logic_vector(2 downto 0); + MCXPRCBCONTROL : in std_ulogic + ); + end component; + + constant IN_DELAY : time := 0 ps; + constant OUT_DELAY : time := 0 ps; + constant CLK_DELAY : time := 0 ps; + + constant PATH_DELAY : VitalDelayType01 := (100 ps, 100 ps); + + + signal VC0TXFIFOBASEP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0TXFIFOBASEP)(12 downto 0); + signal VC0TXFIFOBASENP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0TXFIFOBASENP)(12 downto 0); + signal VC0TXFIFOBASEC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0TXFIFOBASEC)(12 downto 0); + signal VC0TXFIFOLIMITP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0TXFIFOLIMITP)(12 downto 0); + signal VC0TXFIFOLIMITNP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0TXFIFOLIMITNP)(12 downto 0); + signal VC0TXFIFOLIMITC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0TXFIFOLIMITC)(12 downto 0); + signal VC0TOTALCREDITSPH_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(VC0TOTALCREDITSPH)(6 downto 0); + signal VC0TOTALCREDITSNPH_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(VC0TOTALCREDITSNPH)(6 downto 0); + signal VC0TOTALCREDITSCH_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(VC0TOTALCREDITSCH)(6 downto 0); + signal VC0TOTALCREDITSPD_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(VC0TOTALCREDITSPD)(10 downto 0); + signal VC0TOTALCREDITSCD_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(VC0TOTALCREDITSCD)(10 downto 0); + signal VC0RXFIFOBASEP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0RXFIFOBASEP)(12 downto 0); + signal VC0RXFIFOBASENP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0RXFIFOBASENP)(12 downto 0); + signal VC0RXFIFOBASEC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0RXFIFOBASEC)(12 downto 0); + signal VC0RXFIFOLIMITP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0RXFIFOLIMITP)(12 downto 0); + signal VC0RXFIFOLIMITNP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0RXFIFOLIMITNP)(12 downto 0); + signal VC0RXFIFOLIMITC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0RXFIFOLIMITC)(12 downto 0); + signal VC1TXFIFOBASEP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1TXFIFOBASEP)(12 downto 0); + signal VC1TXFIFOBASENP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1TXFIFOBASENP)(12 downto 0); + signal VC1TXFIFOBASEC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1TXFIFOBASEC)(12 downto 0); + signal VC1TXFIFOLIMITP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1TXFIFOLIMITP)(12 downto 0); + signal VC1TXFIFOLIMITNP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1TXFIFOLIMITNP)(12 downto 0); + signal VC1TXFIFOLIMITC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1TXFIFOLIMITC)(12 downto 0); + signal VC1TOTALCREDITSPH_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(VC1TOTALCREDITSPH)(6 downto 0); + signal VC1TOTALCREDITSNPH_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(VC1TOTALCREDITSNPH)(6 downto 0); + signal VC1TOTALCREDITSCH_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(VC1TOTALCREDITSCH)(6 downto 0); + signal VC1TOTALCREDITSPD_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(VC1TOTALCREDITSPD)(10 downto 0); + signal VC1TOTALCREDITSCD_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(VC1TOTALCREDITSCD)(10 downto 0); + signal VC1RXFIFOBASEP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1RXFIFOBASEP)(12 downto 0); + signal VC1RXFIFOBASENP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1RXFIFOBASENP)(12 downto 0); + signal VC1RXFIFOBASEC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1RXFIFOBASEC)(12 downto 0); + signal VC1RXFIFOLIMITP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1RXFIFOLIMITP)(12 downto 0); + signal VC1RXFIFOLIMITNP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1RXFIFOLIMITNP)(12 downto 0); + signal VC1RXFIFOLIMITC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1RXFIFOLIMITC)(12 downto 0); + signal ACTIVELANESIN_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(ACTIVELANESIN); + signal TXTSNFTS_BINARY : std_logic_vector(7 downto 0); + signal TXTSNFTSCOMCLK_BINARY : std_logic_vector(7 downto 0); + signal RETRYRAMREADLATENCY_BINARY : std_logic_vector(2 downto 0); + signal RETRYRAMWRITELATENCY_BINARY : std_logic_vector(2 downto 0); + signal RETRYRAMWIDTH_BINARY : std_ulogic; + signal RETRYRAMSIZE_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(RETRYRAMSIZE); + signal RETRYWRITEPIPE_BINARY : std_ulogic; + signal RETRYREADADDRPIPE_BINARY : std_ulogic; + signal RETRYREADDATAPIPE_BINARY : std_ulogic; + signal XLINKSUPPORTED_BINARY : std_ulogic; + signal INFINITECOMPLETIONS_BINARY : std_ulogic; + signal TLRAMREADLATENCY_BINARY : std_logic_vector(2 downto 0); + signal TLRAMWRITELATENCY_BINARY : std_logic_vector(2 downto 0); + signal TLRAMWIDTH_BINARY : std_ulogic; + signal RAMSHARETXRX_BINARY : std_ulogic; + signal L0SEXITLATENCY_BINARY : std_logic_vector(2 downto 0); + signal L0SEXITLATENCYCOMCLK_BINARY : std_logic_vector(2 downto 0); + signal L1EXITLATENCY_BINARY : std_logic_vector(2 downto 0); + signal L1EXITLATENCYCOMCLK_BINARY : std_logic_vector(2 downto 0); + signal DUALCORESLAVE_BINARY : std_ulogic; + signal DUALCOREENABLE_BINARY : std_ulogic; + signal DUALROLECFGCNTRLROOTEPN_BINARY : std_ulogic; + signal RXREADADDRPIPE_BINARY : std_ulogic; + signal RXREADDATAPIPE_BINARY : std_ulogic; + signal TXWRITEPIPE_BINARY : std_ulogic; + signal TXREADADDRPIPE_BINARY : std_ulogic; + signal TXREADDATAPIPE_BINARY : std_ulogic; + signal RXWRITEPIPE_BINARY : std_ulogic; + signal LLKBYPASS_BINARY : std_ulogic; + signal PCIEREVISION_BINARY : std_ulogic; + signal SELECTDLLIF_BINARY : std_ulogic; + signal SELECTASMODE_BINARY : std_ulogic; + signal ISSWITCH_BINARY : std_ulogic; + signal UPSTREAMFACING_BINARY : std_ulogic; + signal SLOTIMPLEMENTED_BINARY : std_ulogic; + signal EXTCFGCAPPTR_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(EXTCFGCAPPTR); + signal EXTCFGXPCAPPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(EXTCFGXPCAPPTR); + signal BAR0EXIST_BINARY : std_ulogic; + signal BAR1EXIST_BINARY : std_ulogic; + signal BAR2EXIST_BINARY : std_ulogic; + signal BAR3EXIST_BINARY : std_ulogic; + signal BAR4EXIST_BINARY : std_ulogic; + signal BAR5EXIST_BINARY : std_ulogic; + signal BAR0ADDRWIDTH_BINARY : std_ulogic; + signal BAR1ADDRWIDTH_BINARY : std_ulogic; + signal BAR2ADDRWIDTH_BINARY : std_ulogic; + signal BAR3ADDRWIDTH_BINARY : std_ulogic; + signal BAR4ADDRWIDTH_BINARY : std_ulogic; + signal BAR5ADDRWIDTH_BINARY : std_ulogic := '0'; + signal BAR0PREFETCHABLE_BINARY : std_ulogic; + signal BAR1PREFETCHABLE_BINARY : std_ulogic; + signal BAR2PREFETCHABLE_BINARY : std_ulogic; + signal BAR3PREFETCHABLE_BINARY : std_ulogic; + signal BAR4PREFETCHABLE_BINARY : std_ulogic; + signal BAR5PREFETCHABLE_BINARY : std_ulogic; + signal BAR0IOMEMN_BINARY : std_ulogic; + signal BAR1IOMEMN_BINARY : std_ulogic; + signal BAR2IOMEMN_BINARY : std_ulogic; + signal BAR3IOMEMN_BINARY : std_ulogic; + signal BAR4IOMEMN_BINARY : std_ulogic; + signal BAR5IOMEMN_BINARY : std_ulogic; + signal BAR0MASKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(BAR0MASKWIDTH)(5 downto 0); + signal BAR1MASKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(BAR1MASKWIDTH)(5 downto 0); + signal BAR2MASKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(BAR2MASKWIDTH)(5 downto 0); + signal BAR3MASKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(BAR3MASKWIDTH)(5 downto 0); + signal BAR4MASKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(BAR4MASKWIDTH)(5 downto 0); + signal BAR5MASKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(BAR5MASKWIDTH)(5 downto 0); + signal CONFIGROUTING_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(CONFIGROUTING)(2 downto 0); + signal XPDEVICEPORTTYPE_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(XPDEVICEPORTTYPE); + signal HEADERTYPE_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(HEADERTYPE); + signal XPMAXPAYLOAD_BINARY : std_logic_vector(2 downto 0); + signal XPRCBCONTROL_BINARY : std_ulogic; + signal LOWPRIORITYVCCOUNT_BINARY : std_logic_vector(2 downto 0); + signal VENDORID_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(VENDORID); + signal DEVICEID_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(DEVICEID); + signal REVISIONID_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(REVISIONID); + signal CLASSCODE_BINARY : std_logic_vector(23 downto 0) := To_StdLogicVector(CLASSCODE); + signal CARDBUSCISPOINTER_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(CARDBUSCISPOINTER); + signal SUBSYSTEMVENDORID_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(SUBSYSTEMVENDORID); + signal SUBSYSTEMID_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(SUBSYSTEMID); + signal CAPABILITIESPOINTER_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(CAPABILITIESPOINTER); + signal INTERRUPTPIN_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(INTERRUPTPIN); + signal PMCAPABILITYNEXTPTR_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMCAPABILITYNEXTPTR); + signal PMCAPABILITYDSI_BINARY : std_ulogic; + signal PMCAPABILITYAUXCURRENT_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PMCAPABILITYAUXCURRENT)(2 downto 0); + signal PMCAPABILITYD1SUPPORT_BINARY : std_ulogic; + signal PMCAPABILITYD2SUPPORT_BINARY : std_ulogic; + signal PMCAPABILITYPMESUPPORT_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(PMCAPABILITYPMESUPPORT)(4 downto 0); + signal PMSTATUSCONTROLDATASCALE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PMSTATUSCONTROLDATASCALE)(1 downto 0); + signal PMDATA0_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA0); + signal PMDATA1_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA1); + signal PMDATA2_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA2); + signal PMDATA3_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA3); + signal PMDATA4_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA4); + signal PMDATA5_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA5); + signal PMDATA6_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA6); + signal PMDATA7_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA7); + signal PMDATA8_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA8); + signal PMDATASCALE0_BINARY : std_logic_vector(1 downto 0); + signal PMDATASCALE1_BINARY : std_logic_vector(1 downto 0); + signal PMDATASCALE2_BINARY : std_logic_vector(1 downto 0); + signal PMDATASCALE3_BINARY : std_logic_vector(1 downto 0); + signal PMDATASCALE4_BINARY : std_logic_vector(1 downto 0); + signal PMDATASCALE5_BINARY : std_logic_vector(1 downto 0); + signal PMDATASCALE6_BINARY : std_logic_vector(1 downto 0); + signal PMDATASCALE7_BINARY : std_logic_vector(1 downto 0); + signal PMDATASCALE8_BINARY : std_logic_vector(1 downto 0); + signal MSICAPABILITYNEXTPTR_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(MSICAPABILITYNEXTPTR); + signal MSICAPABILITYMULTIMSGCAP_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(MSICAPABILITYMULTIMSGCAP)(2 downto 0); + signal PCIECAPABILITYNEXTPTR_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PCIECAPABILITYNEXTPTR); + signal PCIECAPABILITYSLOTIMPL_BINARY : std_ulogic; + signal PCIECAPABILITYINTMSGNUM_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(PCIECAPABILITYINTMSGNUM)(4 downto 0); + signal DEVICECAPABILITYENDPOINTL0SLATENCY_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(DEVICECAPABILITYENDPOINTL0SLATENCY)(2 downto 0); + signal DEVICECAPABILITYENDPOINTL1LATENCY_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(DEVICECAPABILITYENDPOINTL1LATENCY)(2 downto 0); + signal LINKCAPABILITYMAXLINKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(LINKCAPABILITYMAXLINKWIDTH)(5 downto 0); + signal LINKCAPABILITYASPMSUPPORT_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(LINKCAPABILITYASPMSUPPORT)(1 downto 0); + signal LINKSTATUSSLOTCLOCKCONFIG_BINARY : std_ulogic; + signal SLOTCAPABILITYATTBUTTONPRESENT_BINARY : std_ulogic; + signal SLOTCAPABILITYPOWERCONTROLLERPRESENT_BINARY : std_ulogic; + signal SLOTCAPABILITYMSLSENSORPRESENT_BINARY : std_ulogic; + signal SLOTCAPABILITYATTINDICATORPRESENT_BINARY : std_ulogic; + signal SLOTCAPABILITYPOWERINDICATORPRESENT_BINARY : std_ulogic; + signal SLOTCAPABILITYHOTPLUGSURPRISE_BINARY : std_ulogic; + signal SLOTCAPABILITYHOTPLUGCAPABLE_BINARY : std_ulogic; + signal SLOTCAPABILITYSLOTPOWERLIMITVALUE_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(SLOTCAPABILITYSLOTPOWERLIMITVALUE); + signal SLOTCAPABILITYSLOTPOWERLIMITSCALE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(SLOTCAPABILITYSLOTPOWERLIMITSCALE)(1 downto 0); + signal SLOTCAPABILITYPHYSICALSLOTNUM_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(SLOTCAPABILITYPHYSICALSLOTNUM)(12 downto 0); + signal AERCAPABILITYNEXTPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(AERCAPABILITYNEXTPTR); + signal AERCAPABILITYECRCGENCAPABLE_BINARY : std_ulogic; + signal AERCAPABILITYECRCCHECKCAPABLE_BINARY : std_ulogic; + signal VCCAPABILITYNEXTPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(VCCAPABILITYNEXTPTR); + signal PORTVCCAPABILITYEXTENDEDVCCOUNT_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PORTVCCAPABILITYEXTENDEDVCCOUNT)(2 downto 0); + signal PORTVCCAPABILITYVCARBCAP_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PORTVCCAPABILITYVCARBCAP); + signal PORTVCCAPABILITYVCARBTABLEOFFSET_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PORTVCCAPABILITYVCARBTABLEOFFSET); + signal DSNCAPABILITYNEXTPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(DSNCAPABILITYNEXTPTR); + signal DEVICESERIALNUMBER_BINARY : std_logic_vector(63 downto 0) := To_StdLogicVector(DEVICESERIALNUMBER); + signal PBCAPABILITYNEXTPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(PBCAPABILITYNEXTPTR); + signal PBCAPABILITYDW0BASEPOWER_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PBCAPABILITYDW0BASEPOWER); + signal PBCAPABILITYDW0DATASCALE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW0DATASCALE)(1 downto 0); + signal PBCAPABILITYDW0PMSUBSTATE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW0PMSUBSTATE)(2 downto 0); + signal PBCAPABILITYDW0PMSTATE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW0PMSTATE)(1 downto 0); + signal PBCAPABILITYDW0TYPE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW0TYPE)(2 downto 0); + signal PBCAPABILITYDW0POWERRAIL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW0POWERRAIL)(2 downto 0); + signal PBCAPABILITYDW1BASEPOWER_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PBCAPABILITYDW1BASEPOWER); + signal PBCAPABILITYDW1DATASCALE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW1DATASCALE)(1 downto 0); + signal PBCAPABILITYDW1PMSUBSTATE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW1PMSUBSTATE)(2 downto 0); + signal PBCAPABILITYDW1PMSTATE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW1PMSTATE)(1 downto 0); + signal PBCAPABILITYDW1TYPE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW1TYPE)(2 downto 0); + signal PBCAPABILITYDW1POWERRAIL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW1POWERRAIL)(2 downto 0); + signal PBCAPABILITYDW2BASEPOWER_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PBCAPABILITYDW2BASEPOWER); + signal PBCAPABILITYDW2DATASCALE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW2DATASCALE)(1 downto 0); + signal PBCAPABILITYDW2PMSUBSTATE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW2PMSUBSTATE)(2 downto 0); + signal PBCAPABILITYDW2PMSTATE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW2PMSTATE)(1 downto 0); + signal PBCAPABILITYDW2TYPE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW2TYPE)(2 downto 0); + signal PBCAPABILITYDW2POWERRAIL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW2POWERRAIL)(2 downto 0); + signal PBCAPABILITYDW3BASEPOWER_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PBCAPABILITYDW3BASEPOWER); + signal PBCAPABILITYDW3DATASCALE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW3DATASCALE)(1 downto 0); + signal PBCAPABILITYDW3PMSUBSTATE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW3PMSUBSTATE)(2 downto 0); + signal PBCAPABILITYDW3PMSTATE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW3PMSTATE)(1 downto 0); + signal PBCAPABILITYDW3TYPE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW3TYPE)(2 downto 0); + signal PBCAPABILITYDW3POWERRAIL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW3POWERRAIL)(2 downto 0); + signal PBCAPABILITYSYSTEMALLOCATED_BINARY : std_ulogic; + signal RESETMODE_BINARY : std_ulogic; + signal AERBASEPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(AERBASEPTR); + signal DSNBASEPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(DSNBASEPTR); + signal MSIBASEPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(MSIBASEPTR); + signal PBBASEPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(PBBASEPTR); + signal PMBASEPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(PMBASEPTR); + signal VCBASEPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(VCBASEPTR); + signal XPBASEPTR_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(XPBASEPTR); + signal CLKDIVIDED_BINARY : std_ulogic; + + + signal PIPETXDATAL0_out : std_logic_vector(7 downto 0); + signal PIPETXDATAKL0_out : std_ulogic; + signal PIPETXELECIDLEL0_out : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL0_out : std_ulogic; + signal PIPETXCOMPLIANCEL0_out : std_ulogic; + signal PIPERXPOLARITYL0_out : std_ulogic; + signal PIPEPOWERDOWNL0_out : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL0_out : std_ulogic; + signal PIPERESETL0_out : std_ulogic; + signal PIPETXDATAL1_out : std_logic_vector(7 downto 0); + signal PIPETXDATAKL1_out : std_ulogic; + signal PIPETXELECIDLEL1_out : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL1_out : std_ulogic; + signal PIPETXCOMPLIANCEL1_out : std_ulogic; + signal PIPERXPOLARITYL1_out : std_ulogic; + signal PIPEPOWERDOWNL1_out : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL1_out : std_ulogic; + signal PIPERESETL1_out : std_ulogic; + signal PIPETXDATAL2_out : std_logic_vector(7 downto 0); + signal PIPETXDATAKL2_out : std_ulogic; + signal PIPETXELECIDLEL2_out : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL2_out : std_ulogic; + signal PIPETXCOMPLIANCEL2_out : std_ulogic; + signal PIPERXPOLARITYL2_out : std_ulogic; + signal PIPEPOWERDOWNL2_out : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL2_out : std_ulogic; + signal PIPERESETL2_out : std_ulogic; + signal PIPETXDATAL3_out : std_logic_vector(7 downto 0); + signal PIPETXDATAKL3_out : std_ulogic; + signal PIPETXELECIDLEL3_out : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL3_out : std_ulogic; + signal PIPETXCOMPLIANCEL3_out : std_ulogic; + signal PIPERXPOLARITYL3_out : std_ulogic; + signal PIPEPOWERDOWNL3_out : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL3_out : std_ulogic; + signal PIPERESETL3_out : std_ulogic; + signal PIPETXDATAL4_out : std_logic_vector(7 downto 0); + signal PIPETXDATAKL4_out : std_ulogic; + signal PIPETXELECIDLEL4_out : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL4_out : std_ulogic; + signal PIPETXCOMPLIANCEL4_out : std_ulogic; + signal PIPERXPOLARITYL4_out : std_ulogic; + signal PIPEPOWERDOWNL4_out : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL4_out : std_ulogic; + signal PIPERESETL4_out : std_ulogic; + signal PIPETXDATAL5_out : std_logic_vector(7 downto 0); + signal PIPETXDATAKL5_out : std_ulogic; + signal PIPETXELECIDLEL5_out : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL5_out : std_ulogic; + signal PIPETXCOMPLIANCEL5_out : std_ulogic; + signal PIPERXPOLARITYL5_out : std_ulogic; + signal PIPEPOWERDOWNL5_out : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL5_out : std_ulogic; + signal PIPERESETL5_out : std_ulogic; + signal PIPETXDATAL6_out : std_logic_vector(7 downto 0); + signal PIPETXDATAKL6_out : std_ulogic; + signal PIPETXELECIDLEL6_out : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL6_out : std_ulogic; + signal PIPETXCOMPLIANCEL6_out : std_ulogic; + signal PIPERXPOLARITYL6_out : std_ulogic; + signal PIPEPOWERDOWNL6_out : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL6_out : std_ulogic; + signal PIPERESETL6_out : std_ulogic; + signal PIPETXDATAL7_out : std_logic_vector(7 downto 0); + signal PIPETXDATAKL7_out : std_ulogic; + signal PIPETXELECIDLEL7_out : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL7_out : std_ulogic; + signal PIPETXCOMPLIANCEL7_out : std_ulogic; + signal PIPERXPOLARITYL7_out : std_ulogic; + signal PIPEPOWERDOWNL7_out : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL7_out : std_ulogic; + signal PIPERESETL7_out : std_ulogic; + signal MIMRXBWDATA_out : std_logic_vector(63 downto 0); + signal MIMRXBWADD_out : std_logic_vector(12 downto 0); + signal MIMRXBRADD_out : std_logic_vector(12 downto 0); + signal MIMRXBWEN_out : std_ulogic; + signal MIMRXBREN_out : std_ulogic; + signal MIMTXBWDATA_out : std_logic_vector(63 downto 0); + signal MIMTXBWADD_out : std_logic_vector(12 downto 0); + signal MIMTXBRADD_out : std_logic_vector(12 downto 0); + signal MIMTXBWEN_out : std_ulogic; + signal MIMTXBREN_out : std_ulogic; + signal MIMDLLBWDATA_out : std_logic_vector(63 downto 0); + signal MIMDLLBWADD_out : std_logic_vector(11 downto 0); + signal MIMDLLBRADD_out : std_logic_vector(11 downto 0); + signal MIMDLLBWEN_out : std_ulogic; + signal MIMDLLBREN_out : std_ulogic; + signal CRMRXHOTRESETN_out : std_ulogic; + signal CRMDOHOTRESETN_out : std_ulogic; + signal CRMPWRSOFTRESETN_out : std_ulogic; + signal LLKTCSTATUS_out : std_logic_vector(7 downto 0); + signal LLKTXDSTRDYN_out : std_ulogic; + signal LLKTXCHANSPACE_out : std_logic_vector(9 downto 0); + signal LLKTXCHPOSTEDREADYN_out : std_logic_vector(7 downto 0); + signal LLKTXCHNONPOSTEDREADYN_out : std_logic_vector(7 downto 0); + signal LLKTXCHCOMPLETIONREADYN_out : std_logic_vector(7 downto 0); + signal LLKTXCONFIGREADYN_out : std_ulogic; + signal LLKRXDATA_out : std_logic_vector(63 downto 0); + signal LLKRXSRCRDYN_out : std_ulogic; + signal LLKRXSRCLASTREQN_out : std_ulogic; + signal LLKRXSRCDSCN_out : std_ulogic; + signal LLKRXSOFN_out : std_ulogic; + signal LLKRXEOFN_out : std_ulogic; + signal LLKRXSOPN_out : std_ulogic; + signal LLKRXEOPN_out : std_ulogic; + signal LLKRXVALIDN_out : std_logic_vector(1 downto 0); + signal LLKRXPREFERREDTYPE_out : std_logic_vector(15 downto 0); + signal LLKRXCHPOSTEDAVAILABLEN_out : std_logic_vector(7 downto 0); + signal LLKRXCHNONPOSTEDAVAILABLEN_out : std_logic_vector(7 downto 0); + signal LLKRXCHCOMPLETIONAVAILABLEN_out : std_logic_vector(7 downto 0); + signal LLKRXCHCONFIGAVAILABLEN_out : std_ulogic; + signal LLKRXCHPOSTEDPARTIALN_out : std_logic_vector(7 downto 0); + signal LLKRXCHNONPOSTEDPARTIALN_out : std_logic_vector(7 downto 0); + signal LLKRXCHCOMPLETIONPARTIALN_out : std_logic_vector(7 downto 0); + signal LLKRXCHCONFIGPARTIALN_out : std_ulogic; + signal LLKRX4DWHEADERN_out : std_ulogic; + signal LLKRXECRCBADN_out : std_ulogic; + signal MGMTRDATA_out : std_logic_vector(31 downto 0); + signal MGMTPSO_out : std_logic_vector(16 downto 0); + signal MGMTSTATSCREDIT_out : std_logic_vector(11 downto 0); + signal L0RXDLLTLPECRCOK_out : std_ulogic; + signal DLLTXPMDLLPOUTSTANDING_out : std_ulogic; + signal L0FIRSTCFGWRITEOCCURRED_out : std_ulogic; + signal L0CFGLOOPBACKACK_out : std_ulogic; + signal L0MACUPSTREAMDOWNSTREAM_out : std_ulogic; + signal L0RXMACLINKERROR_out : std_logic_vector(1 downto 0); + signal L0MACLINKUP_out : std_ulogic; + signal L0MACNEGOTIATEDLINKWIDTH_out : std_logic_vector(3 downto 0); + signal L0MACLINKTRAINING_out : std_ulogic; + signal L0LTSSMSTATE_out : std_logic_vector(3 downto 0); + signal L0DLLVCSTATUS_out : std_logic_vector(7 downto 0); + signal L0DLUPDOWN_out : std_logic_vector(7 downto 0); + signal L0DLLERRORVECTOR_out : std_logic_vector(6 downto 0); + signal L0DLLASRXSTATE_out : std_logic_vector(1 downto 0); + signal L0DLLASTXSTATE_out : std_ulogic; + signal L0ASAUTONOMOUSINITCOMPLETED_out : std_ulogic; + signal L0COMPLETERID_out : std_logic_vector(12 downto 0); + signal L0UNLOCKRECEIVED_out : std_ulogic; + signal L0CORRERRMSGRCVD_out : std_ulogic; + signal L0FATALERRMSGRCVD_out : std_ulogic; + signal L0NONFATALERRMSGRCVD_out : std_ulogic; + signal L0ERRMSGREQID_out : std_logic_vector(15 downto 0); + signal L0FWDCORRERROUT_out : std_ulogic; + signal L0FWDFATALERROUT_out : std_ulogic; + signal L0FWDNONFATALERROUT_out : std_ulogic; + signal L0RECEIVEDASSERTINTALEGACYINT_out : std_ulogic; + signal L0RECEIVEDASSERTINTBLEGACYINT_out : std_ulogic; + signal L0RECEIVEDASSERTINTCLEGACYINT_out : std_ulogic; + signal L0RECEIVEDASSERTINTDLEGACYINT_out : std_ulogic; + signal L0RECEIVEDDEASSERTINTALEGACYINT_out : std_ulogic; + signal L0RECEIVEDDEASSERTINTBLEGACYINT_out : std_ulogic; + signal L0RECEIVEDDEASSERTINTCLEGACYINT_out : std_ulogic; + signal L0RECEIVEDDEASSERTINTDLEGACYINT_out : std_ulogic; + signal L0MSIENABLE0_out : std_ulogic; + signal L0MULTIMSGEN0_out : std_logic_vector(2 downto 0); + signal L0STATSDLLPRECEIVED_out : std_ulogic; + signal L0STATSDLLPTRANSMITTED_out : std_ulogic; + signal L0STATSOSRECEIVED_out : std_ulogic; + signal L0STATSOSTRANSMITTED_out : std_ulogic; + signal L0STATSTLPRECEIVED_out : std_ulogic; + signal L0STATSTLPTRANSMITTED_out : std_ulogic; + signal L0STATSCFGRECEIVED_out : std_ulogic; + signal L0STATSCFGTRANSMITTED_out : std_ulogic; + signal L0STATSCFGOTHERRECEIVED_out : std_ulogic; + signal L0STATSCFGOTHERTRANSMITTED_out : std_ulogic; + signal MAXPAYLOADSIZE_out : std_logic_vector(2 downto 0); + signal MAXREADREQUESTSIZE_out : std_logic_vector(2 downto 0); + signal IOSPACEENABLE_out : std_ulogic; + signal MEMSPACEENABLE_out : std_ulogic; + signal L0ATTENTIONINDICATORCONTROL_out : std_logic_vector(1 downto 0); + signal L0POWERINDICATORCONTROL_out : std_logic_vector(1 downto 0); + signal L0POWERCONTROLLERCONTROL_out : std_ulogic; + signal L0TOGGLEELECTROMECHANICALINTERLOCK_out : std_ulogic; + signal L0RXBEACON_out : std_ulogic; + signal L0PWRSTATE0_out : std_logic_vector(1 downto 0); + signal L0PMEACK_out : std_ulogic; + signal L0PMEREQOUT_out : std_ulogic; + signal L0PMEEN_out : std_ulogic; + signal L0PWRINHIBITTRANSFERS_out : std_ulogic; + signal L0PWRL1STATE_out : std_ulogic; + signal L0PWRL23READYDEVICE_out : std_ulogic; + signal L0PWRL23READYSTATE_out : std_ulogic; + signal L0PWRTXL0SSTATE_out : std_ulogic; + signal L0PWRTURNOFFREQ_out : std_ulogic; + signal L0RXDLLPM_out : std_ulogic; + signal L0RXDLLPMTYPE_out : std_logic_vector(2 downto 0); + signal L0TXDLLPMUPDATED_out : std_ulogic; + signal L0MACNEWSTATEACK_out : std_ulogic; + signal L0MACRXL0SSTATE_out : std_ulogic; + signal L0MACENTEREDL0_out : std_ulogic; + signal L0DLLRXACKOUTSTANDING_out : std_ulogic; + signal L0DLLTXOUTSTANDING_out : std_ulogic; + signal L0DLLTXNONFCOUTSTANDING_out : std_ulogic; + signal L0RXDLLTLPEND_out : std_logic_vector(1 downto 0); + signal L0TXDLLSBFCUPDATED_out : std_ulogic; + signal L0RXDLLSBFCDATA_out : std_logic_vector(18 downto 0); + signal L0RXDLLSBFCUPDATE_out : std_ulogic; + signal L0TXDLLFCNPOSTBYPUPDATED_out : std_logic_vector(7 downto 0); + signal L0TXDLLFCPOSTORDUPDATED_out : std_logic_vector(7 downto 0); + signal L0TXDLLFCCMPLMCUPDATED_out : std_logic_vector(7 downto 0); + signal L0RXDLLFCNPOSTBYPCRED_out : std_logic_vector(19 downto 0); + signal L0RXDLLFCNPOSTBYPUPDATE_out : std_logic_vector(7 downto 0); + signal L0RXDLLFCPOSTORDCRED_out : std_logic_vector(23 downto 0); + signal L0RXDLLFCPOSTORDUPDATE_out : std_logic_vector(7 downto 0); + signal L0RXDLLFCCMPLMCCRED_out : std_logic_vector(23 downto 0); + signal L0RXDLLFCCMPLMCUPDATE_out : std_logic_vector(7 downto 0); + signal L0UCBYPFOUND_out : std_logic_vector(3 downto 0); + signal L0UCORDFOUND_out : std_logic_vector(3 downto 0); + signal L0MCFOUND_out : std_logic_vector(2 downto 0); + signal L0TRANSFORMEDVC_out : std_logic_vector(2 downto 0); + signal BUSMASTERENABLE_out : std_ulogic; + signal PARITYERRORRESPONSE_out : std_ulogic; + signal SERRENABLE_out : std_ulogic; + signal INTERRUPTDISABLE_out : std_ulogic; + signal URREPORTINGENABLE_out : std_ulogic; + + + signal PIPETXDATAL0_outdelay : std_logic_vector(7 downto 0); + signal PIPETXDATAKL0_outdelay : std_ulogic; + signal PIPETXELECIDLEL0_outdelay : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL0_outdelay : std_ulogic; + signal PIPETXCOMPLIANCEL0_outdelay : std_ulogic; + signal PIPERXPOLARITYL0_outdelay : std_ulogic; + signal PIPEPOWERDOWNL0_outdelay : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL0_outdelay : std_ulogic; + signal PIPERESETL0_outdelay : std_ulogic; + signal PIPETXDATAL1_outdelay : std_logic_vector(7 downto 0); + signal PIPETXDATAKL1_outdelay : std_ulogic; + signal PIPETXELECIDLEL1_outdelay : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL1_outdelay : std_ulogic; + signal PIPETXCOMPLIANCEL1_outdelay : std_ulogic; + signal PIPERXPOLARITYL1_outdelay : std_ulogic; + signal PIPEPOWERDOWNL1_outdelay : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL1_outdelay : std_ulogic; + signal PIPERESETL1_outdelay : std_ulogic; + signal PIPETXDATAL2_outdelay : std_logic_vector(7 downto 0); + signal PIPETXDATAKL2_outdelay : std_ulogic; + signal PIPETXELECIDLEL2_outdelay : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL2_outdelay : std_ulogic; + signal PIPETXCOMPLIANCEL2_outdelay : std_ulogic; + signal PIPERXPOLARITYL2_outdelay : std_ulogic; + signal PIPEPOWERDOWNL2_outdelay : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL2_outdelay : std_ulogic; + signal PIPERESETL2_outdelay : std_ulogic; + signal PIPETXDATAL3_outdelay : std_logic_vector(7 downto 0); + signal PIPETXDATAKL3_outdelay : std_ulogic; + signal PIPETXELECIDLEL3_outdelay : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL3_outdelay : std_ulogic; + signal PIPETXCOMPLIANCEL3_outdelay : std_ulogic; + signal PIPERXPOLARITYL3_outdelay : std_ulogic; + signal PIPEPOWERDOWNL3_outdelay : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL3_outdelay : std_ulogic; + signal PIPERESETL3_outdelay : std_ulogic; + signal PIPETXDATAL4_outdelay : std_logic_vector(7 downto 0); + signal PIPETXDATAKL4_outdelay : std_ulogic; + signal PIPETXELECIDLEL4_outdelay : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL4_outdelay : std_ulogic; + signal PIPETXCOMPLIANCEL4_outdelay : std_ulogic; + signal PIPERXPOLARITYL4_outdelay : std_ulogic; + signal PIPEPOWERDOWNL4_outdelay : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL4_outdelay : std_ulogic; + signal PIPERESETL4_outdelay : std_ulogic; + signal PIPETXDATAL5_outdelay : std_logic_vector(7 downto 0); + signal PIPETXDATAKL5_outdelay : std_ulogic; + signal PIPETXELECIDLEL5_outdelay : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL5_outdelay : std_ulogic; + signal PIPETXCOMPLIANCEL5_outdelay : std_ulogic; + signal PIPERXPOLARITYL5_outdelay : std_ulogic; + signal PIPEPOWERDOWNL5_outdelay : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL5_outdelay : std_ulogic; + signal PIPERESETL5_outdelay : std_ulogic; + signal PIPETXDATAL6_outdelay : std_logic_vector(7 downto 0); + signal PIPETXDATAKL6_outdelay : std_ulogic; + signal PIPETXELECIDLEL6_outdelay : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL6_outdelay : std_ulogic; + signal PIPETXCOMPLIANCEL6_outdelay : std_ulogic; + signal PIPERXPOLARITYL6_outdelay : std_ulogic; + signal PIPEPOWERDOWNL6_outdelay : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL6_outdelay : std_ulogic; + signal PIPERESETL6_outdelay : std_ulogic; + signal PIPETXDATAL7_outdelay : std_logic_vector(7 downto 0); + signal PIPETXDATAKL7_outdelay : std_ulogic; + signal PIPETXELECIDLEL7_outdelay : std_ulogic; + signal PIPETXDETECTRXLOOPBACKL7_outdelay : std_ulogic; + signal PIPETXCOMPLIANCEL7_outdelay : std_ulogic; + signal PIPERXPOLARITYL7_outdelay : std_ulogic; + signal PIPEPOWERDOWNL7_outdelay : std_logic_vector(1 downto 0); + signal PIPEDESKEWLANESL7_outdelay : std_ulogic; + signal PIPERESETL7_outdelay : std_ulogic; + signal MIMRXBWDATA_outdelay : std_logic_vector(63 downto 0); + signal MIMRXBWADD_outdelay : std_logic_vector(12 downto 0); + signal MIMRXBRADD_outdelay : std_logic_vector(12 downto 0); + signal MIMRXBWEN_outdelay : std_ulogic; + signal MIMRXBREN_outdelay : std_ulogic; + signal MIMTXBWDATA_outdelay : std_logic_vector(63 downto 0); + signal MIMTXBWADD_outdelay : std_logic_vector(12 downto 0); + signal MIMTXBRADD_outdelay : std_logic_vector(12 downto 0); + signal MIMTXBWEN_outdelay : std_ulogic; + signal MIMTXBREN_outdelay : std_ulogic; + signal MIMDLLBWDATA_outdelay : std_logic_vector(63 downto 0); + signal MIMDLLBWADD_outdelay : std_logic_vector(11 downto 0); + signal MIMDLLBRADD_outdelay : std_logic_vector(11 downto 0); + signal MIMDLLBWEN_outdelay : std_ulogic; + signal MIMDLLBREN_outdelay : std_ulogic; + signal CRMRXHOTRESETN_outdelay : std_ulogic; + signal CRMDOHOTRESETN_outdelay : std_ulogic; + signal CRMPWRSOFTRESETN_outdelay : std_ulogic; + signal LLKTCSTATUS_outdelay : std_logic_vector(7 downto 0); + signal LLKTXDSTRDYN_outdelay : std_ulogic; + signal LLKTXCHANSPACE_outdelay : std_logic_vector(9 downto 0); + signal LLKTXCHPOSTEDREADYN_outdelay : std_logic_vector(7 downto 0); + signal LLKTXCHNONPOSTEDREADYN_outdelay : std_logic_vector(7 downto 0); + signal LLKTXCHCOMPLETIONREADYN_outdelay : std_logic_vector(7 downto 0); + signal LLKTXCONFIGREADYN_outdelay : std_ulogic; + signal LLKRXDATA_outdelay : std_logic_vector(63 downto 0); + signal LLKRXSRCRDYN_outdelay : std_ulogic; + signal LLKRXSRCLASTREQN_outdelay : std_ulogic; + signal LLKRXSRCDSCN_outdelay : std_ulogic; + signal LLKRXSOFN_outdelay : std_ulogic; + signal LLKRXEOFN_outdelay : std_ulogic; + signal LLKRXSOPN_outdelay : std_ulogic; + signal LLKRXEOPN_outdelay : std_ulogic; + signal LLKRXVALIDN_outdelay : std_logic_vector(1 downto 0); + signal LLKRXPREFERREDTYPE_outdelay : std_logic_vector(15 downto 0); + signal LLKRXCHPOSTEDAVAILABLEN_outdelay : std_logic_vector(7 downto 0); + signal LLKRXCHNONPOSTEDAVAILABLEN_outdelay : std_logic_vector(7 downto 0); + signal LLKRXCHCOMPLETIONAVAILABLEN_outdelay : std_logic_vector(7 downto 0); + signal LLKRXCHCONFIGAVAILABLEN_outdelay : std_ulogic; + signal LLKRXCHPOSTEDPARTIALN_outdelay : std_logic_vector(7 downto 0); + signal LLKRXCHNONPOSTEDPARTIALN_outdelay : std_logic_vector(7 downto 0); + signal LLKRXCHCOMPLETIONPARTIALN_outdelay : std_logic_vector(7 downto 0); + signal LLKRXCHCONFIGPARTIALN_outdelay : std_ulogic; + signal LLKRX4DWHEADERN_outdelay : std_ulogic; + signal LLKRXECRCBADN_outdelay : std_ulogic; + signal MGMTRDATA_outdelay : std_logic_vector(31 downto 0); + signal MGMTPSO_outdelay : std_logic_vector(16 downto 0); + signal MGMTSTATSCREDIT_outdelay : std_logic_vector(11 downto 0); + signal L0RXDLLTLPECRCOK_outdelay : std_ulogic; + signal DLLTXPMDLLPOUTSTANDING_outdelay : std_ulogic; + signal L0FIRSTCFGWRITEOCCURRED_outdelay : std_ulogic; + signal L0CFGLOOPBACKACK_outdelay : std_ulogic; + signal L0MACUPSTREAMDOWNSTREAM_outdelay : std_ulogic; + signal L0RXMACLINKERROR_outdelay : std_logic_vector(1 downto 0); + signal L0MACLINKUP_outdelay : std_ulogic; + signal L0MACNEGOTIATEDLINKWIDTH_outdelay : std_logic_vector(3 downto 0); + signal L0MACLINKTRAINING_outdelay : std_ulogic; + signal L0LTSSMSTATE_outdelay : std_logic_vector(3 downto 0); + signal L0DLLVCSTATUS_outdelay : std_logic_vector(7 downto 0); + signal L0DLUPDOWN_outdelay : std_logic_vector(7 downto 0); + signal L0DLLERRORVECTOR_outdelay : std_logic_vector(6 downto 0); + signal L0DLLASRXSTATE_outdelay : std_logic_vector(1 downto 0); + signal L0DLLASTXSTATE_outdelay : std_ulogic; + signal L0ASAUTONOMOUSINITCOMPLETED_outdelay : std_ulogic; + signal L0COMPLETERID_outdelay : std_logic_vector(12 downto 0); + signal L0UNLOCKRECEIVED_outdelay : std_ulogic; + signal L0CORRERRMSGRCVD_outdelay : std_ulogic; + signal L0FATALERRMSGRCVD_outdelay : std_ulogic; + signal L0NONFATALERRMSGRCVD_outdelay : std_ulogic; + signal L0ERRMSGREQID_outdelay : std_logic_vector(15 downto 0); + signal L0FWDCORRERROUT_outdelay : std_ulogic; + signal L0FWDFATALERROUT_outdelay : std_ulogic; + signal L0FWDNONFATALERROUT_outdelay : std_ulogic; + signal L0RECEIVEDASSERTINTALEGACYINT_outdelay : std_ulogic; + signal L0RECEIVEDASSERTINTBLEGACYINT_outdelay : std_ulogic; + signal L0RECEIVEDASSERTINTCLEGACYINT_outdelay : std_ulogic; + signal L0RECEIVEDASSERTINTDLEGACYINT_outdelay : std_ulogic; + signal L0RECEIVEDDEASSERTINTALEGACYINT_outdelay : std_ulogic; + signal L0RECEIVEDDEASSERTINTBLEGACYINT_outdelay : std_ulogic; + signal L0RECEIVEDDEASSERTINTCLEGACYINT_outdelay : std_ulogic; + signal L0RECEIVEDDEASSERTINTDLEGACYINT_outdelay : std_ulogic; + signal L0MSIENABLE0_outdelay : std_ulogic; + signal L0MULTIMSGEN0_outdelay : std_logic_vector(2 downto 0); + signal L0STATSDLLPRECEIVED_outdelay : std_ulogic; + signal L0STATSDLLPTRANSMITTED_outdelay : std_ulogic; + signal L0STATSOSRECEIVED_outdelay : std_ulogic; + signal L0STATSOSTRANSMITTED_outdelay : std_ulogic; + signal L0STATSTLPRECEIVED_outdelay : std_ulogic; + signal L0STATSTLPTRANSMITTED_outdelay : std_ulogic; + signal L0STATSCFGRECEIVED_outdelay : std_ulogic; + signal L0STATSCFGTRANSMITTED_outdelay : std_ulogic; + signal L0STATSCFGOTHERRECEIVED_outdelay : std_ulogic; + signal L0STATSCFGOTHERTRANSMITTED_outdelay : std_ulogic; + signal MAXPAYLOADSIZE_outdelay : std_logic_vector(2 downto 0); + signal MAXREADREQUESTSIZE_outdelay : std_logic_vector(2 downto 0); + signal IOSPACEENABLE_outdelay : std_ulogic; + signal MEMSPACEENABLE_outdelay : std_ulogic; + signal L0ATTENTIONINDICATORCONTROL_outdelay : std_logic_vector(1 downto 0); + signal L0POWERINDICATORCONTROL_outdelay : std_logic_vector(1 downto 0); + signal L0POWERCONTROLLERCONTROL_outdelay : std_ulogic; + signal L0TOGGLEELECTROMECHANICALINTERLOCK_outdelay : std_ulogic; + signal L0RXBEACON_outdelay : std_ulogic; + signal L0PWRSTATE0_outdelay : std_logic_vector(1 downto 0); + signal L0PMEACK_outdelay : std_ulogic; + signal L0PMEREQOUT_outdelay : std_ulogic; + signal L0PMEEN_outdelay : std_ulogic; + signal L0PWRINHIBITTRANSFERS_outdelay : std_ulogic; + signal L0PWRL1STATE_outdelay : std_ulogic; + signal L0PWRL23READYDEVICE_outdelay : std_ulogic; + signal L0PWRL23READYSTATE_outdelay : std_ulogic; + signal L0PWRTXL0SSTATE_outdelay : std_ulogic; + signal L0PWRTURNOFFREQ_outdelay : std_ulogic; + signal L0RXDLLPM_outdelay : std_ulogic; + signal L0RXDLLPMTYPE_outdelay : std_logic_vector(2 downto 0); + signal L0TXDLLPMUPDATED_outdelay : std_ulogic; + signal L0MACNEWSTATEACK_outdelay : std_ulogic; + signal L0MACRXL0SSTATE_outdelay : std_ulogic; + signal L0MACENTEREDL0_outdelay : std_ulogic; + signal L0DLLRXACKOUTSTANDING_outdelay : std_ulogic; + signal L0DLLTXOUTSTANDING_outdelay : std_ulogic; + signal L0DLLTXNONFCOUTSTANDING_outdelay : std_ulogic; + signal L0RXDLLTLPEND_outdelay : std_logic_vector(1 downto 0); + signal L0TXDLLSBFCUPDATED_outdelay : std_ulogic; + signal L0RXDLLSBFCDATA_outdelay : std_logic_vector(18 downto 0); + signal L0RXDLLSBFCUPDATE_outdelay : std_ulogic; + signal L0TXDLLFCNPOSTBYPUPDATED_outdelay : std_logic_vector(7 downto 0); + signal L0TXDLLFCPOSTORDUPDATED_outdelay : std_logic_vector(7 downto 0); + signal L0TXDLLFCCMPLMCUPDATED_outdelay : std_logic_vector(7 downto 0); + signal L0RXDLLFCNPOSTBYPCRED_outdelay : std_logic_vector(19 downto 0); + signal L0RXDLLFCNPOSTBYPUPDATE_outdelay : std_logic_vector(7 downto 0); + signal L0RXDLLFCPOSTORDCRED_outdelay : std_logic_vector(23 downto 0); + signal L0RXDLLFCPOSTORDUPDATE_outdelay : std_logic_vector(7 downto 0); + signal L0RXDLLFCCMPLMCCRED_outdelay : std_logic_vector(23 downto 0); + signal L0RXDLLFCCMPLMCUPDATE_outdelay : std_logic_vector(7 downto 0); + signal L0UCBYPFOUND_outdelay : std_logic_vector(3 downto 0); + signal L0UCORDFOUND_outdelay : std_logic_vector(3 downto 0); + signal L0MCFOUND_outdelay : std_logic_vector(2 downto 0); + signal L0TRANSFORMEDVC_outdelay : std_logic_vector(2 downto 0); + signal BUSMASTERENABLE_outdelay : std_ulogic; + signal PARITYERRORRESPONSE_outdelay : std_ulogic; + signal SERRENABLE_outdelay : std_ulogic; + signal INTERRUPTDISABLE_outdelay : std_ulogic; + signal URREPORTINGENABLE_outdelay : std_ulogic; + + signal PIPERXELECIDLEL0_ipd : std_ulogic; + signal PIPERXSTATUSL0_ipd : std_logic_vector(2 downto 0); + signal PIPERXDATAL0_ipd : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL0_ipd : std_ulogic; + signal PIPERXDATAKL0_ipd : std_ulogic; + signal PIPERXVALIDL0_ipd : std_ulogic; + signal PIPERXCHANISALIGNEDL0_ipd : std_ulogic; + signal PIPERXELECIDLEL1_ipd : std_ulogic; + signal PIPERXSTATUSL1_ipd : std_logic_vector(2 downto 0); + signal PIPERXDATAL1_ipd : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL1_ipd : std_ulogic; + signal PIPERXDATAKL1_ipd : std_ulogic; + signal PIPERXVALIDL1_ipd : std_ulogic; + signal PIPERXCHANISALIGNEDL1_ipd : std_ulogic; + signal PIPERXELECIDLEL2_ipd : std_ulogic; + signal PIPERXSTATUSL2_ipd : std_logic_vector(2 downto 0); + signal PIPERXDATAL2_ipd : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL2_ipd : std_ulogic; + signal PIPERXDATAKL2_ipd : std_ulogic; + signal PIPERXVALIDL2_ipd : std_ulogic; + signal PIPERXCHANISALIGNEDL2_ipd : std_ulogic; + signal PIPERXELECIDLEL3_ipd : std_ulogic; + signal PIPERXSTATUSL3_ipd : std_logic_vector(2 downto 0); + signal PIPERXDATAL3_ipd : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL3_ipd : std_ulogic; + signal PIPERXDATAKL3_ipd : std_ulogic; + signal PIPERXVALIDL3_ipd : std_ulogic; + signal PIPERXCHANISALIGNEDL3_ipd : std_ulogic; + signal PIPERXELECIDLEL4_ipd : std_ulogic; + signal PIPERXSTATUSL4_ipd : std_logic_vector(2 downto 0); + signal PIPERXDATAL4_ipd : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL4_ipd : std_ulogic; + signal PIPERXDATAKL4_ipd : std_ulogic; + signal PIPERXVALIDL4_ipd : std_ulogic; + signal PIPERXCHANISALIGNEDL4_ipd : std_ulogic; + signal PIPERXELECIDLEL5_ipd : std_ulogic; + signal PIPERXSTATUSL5_ipd : std_logic_vector(2 downto 0); + signal PIPERXDATAL5_ipd : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL5_ipd : std_ulogic; + signal PIPERXDATAKL5_ipd : std_ulogic; + signal PIPERXVALIDL5_ipd : std_ulogic; + signal PIPERXCHANISALIGNEDL5_ipd : std_ulogic; + signal PIPERXELECIDLEL6_ipd : std_ulogic; + signal PIPERXSTATUSL6_ipd : std_logic_vector(2 downto 0); + signal PIPERXDATAL6_ipd : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL6_ipd : std_ulogic; + signal PIPERXDATAKL6_ipd : std_ulogic; + signal PIPERXVALIDL6_ipd : std_ulogic; + signal PIPERXCHANISALIGNEDL6_ipd : std_ulogic; + signal PIPERXELECIDLEL7_ipd : std_ulogic; + signal PIPERXSTATUSL7_ipd : std_logic_vector(2 downto 0); + signal PIPERXDATAL7_ipd : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL7_ipd : std_ulogic; + signal PIPERXDATAKL7_ipd : std_ulogic; + signal PIPERXVALIDL7_ipd : std_ulogic; + signal PIPERXCHANISALIGNEDL7_ipd : std_ulogic; + signal MIMRXBRDATA_ipd : std_logic_vector(63 downto 0); + signal CRMCORECLKRXO_ipd : std_ulogic; + signal CRMUSERCLKRXO_ipd : std_ulogic; + signal MIMTXBRDATA_ipd : std_logic_vector(63 downto 0); + signal CRMCORECLKTXO_ipd : std_ulogic; + signal CRMUSERCLKTXO_ipd : std_ulogic; + signal MIMDLLBRDATA_ipd : std_logic_vector(63 downto 0); + signal CRMCORECLKDLO_ipd : std_ulogic; + signal CRMCORECLK_ipd : std_ulogic; + signal CRMUSERCLK_ipd : std_ulogic; + signal CRMURSTN_ipd : std_ulogic; + signal CRMNVRSTN_ipd : std_ulogic; + signal CRMMGMTRSTN_ipd : std_ulogic; + signal CRMUSERCFGRSTN_ipd : std_ulogic; + signal CRMMACRSTN_ipd : std_ulogic; + signal CRMLINKRSTN_ipd : std_ulogic; + signal CRMTXHOTRESETN_ipd : std_ulogic; + signal CRMCFGBRIDGEHOTRESET_ipd : std_ulogic; + signal LLKTXDATA_ipd : std_logic_vector(63 downto 0); + signal LLKTXSRCRDYN_ipd : std_ulogic; + signal LLKTXSRCDSCN_ipd : std_ulogic; + signal LLKTXCOMPLETEN_ipd : std_ulogic; + signal LLKTXSOFN_ipd : std_ulogic; + signal LLKTXEOFN_ipd : std_ulogic; + signal LLKTXSOPN_ipd : std_ulogic; + signal LLKTXEOPN_ipd : std_ulogic; + signal LLKTXENABLEN_ipd : std_logic_vector(1 downto 0); + signal LLKTXCHTC_ipd : std_logic_vector(2 downto 0); + signal LLKTXCHFIFO_ipd : std_logic_vector(1 downto 0); + signal LLKTXCREATEECRCN_ipd : std_ulogic; + signal LLKTX4DWHEADERN_ipd : std_ulogic; + signal LLKRXDSTREQN_ipd : std_ulogic; + signal LLKRXCHTC_ipd : std_logic_vector(2 downto 0); + signal LLKRXCHFIFO_ipd : std_logic_vector(1 downto 0); + signal LLKRXDSTCONTREQN_ipd : std_ulogic; + signal MGMTWDATA_ipd : std_logic_vector(31 downto 0); + signal MGMTBWREN_ipd : std_logic_vector(3 downto 0); + signal MGMTWREN_ipd : std_ulogic; + signal MGMTADDR_ipd : std_logic_vector(10 downto 0); + signal MGMTRDEN_ipd : std_ulogic; + signal MGMTSTATSCREDITSEL_ipd : std_logic_vector(6 downto 0); + signal MAINPOWER_ipd : std_ulogic; + signal AUXPOWER_ipd : std_ulogic; + signal L0TLLINKRETRAIN_ipd : std_ulogic; + signal CFGNEGOTIATEDLINKWIDTH_ipd : std_logic_vector(5 downto 0); + signal CROSSLINKSEED_ipd : std_ulogic; + signal COMPLIANCEAVOID_ipd : std_ulogic; + signal L0VC0PREVIEWEXPAND_ipd : std_ulogic; + signal L0CFGVCID_ipd : std_logic_vector(23 downto 0); + signal L0CFGLOOPBACKMASTER_ipd : std_ulogic; + signal L0REPLAYTIMERADJUSTMENT_ipd : std_logic_vector(11 downto 0); + signal L0ACKNAKTIMERADJUSTMENT_ipd : std_logic_vector(11 downto 0); + signal L0DLLHOLDLINKUP_ipd : std_ulogic; + signal L0CFGASSTATECHANGECMD_ipd : std_logic_vector(3 downto 0); + signal L0CFGASSPANTREEOWNEDSTATE_ipd : std_ulogic; + signal L0ASE_ipd : std_ulogic; + signal L0ASTURNPOOLBITSCONSUMED_ipd : std_logic_vector(2 downto 0); + signal L0ASPORTCOUNT_ipd : std_logic_vector(7 downto 0); + signal L0CFGVCENABLE_ipd : std_logic_vector(7 downto 0); + signal L0CFGNEGOTIATEDMAXP_ipd : std_logic_vector(2 downto 0); + signal L0CFGDISABLESCRAMBLE_ipd : std_ulogic; + signal L0CFGEXTENDEDSYNC_ipd : std_ulogic; + signal L0CFGLINKDISABLE_ipd : std_ulogic; + signal L0PORTNUMBER_ipd : std_logic_vector(7 downto 0); + signal L0SENDUNLOCKMESSAGE_ipd : std_ulogic; + signal L0ALLDOWNRXPORTSINL0S_ipd : std_ulogic; + signal L0UPSTREAMRXPORTINL0S_ipd : std_ulogic; + signal L0TRANSACTIONSPENDING_ipd : std_ulogic; + signal L0ALLDOWNPORTSINL1_ipd : std_ulogic; + signal L0FWDCORRERRIN_ipd : std_ulogic; + signal L0FWDFATALERRIN_ipd : std_ulogic; + signal L0FWDNONFATALERRIN_ipd : std_ulogic; + signal L0SETCOMPLETERABORTERROR_ipd : std_ulogic; + signal L0SETDETECTEDCORRERROR_ipd : std_ulogic; + signal L0SETDETECTEDFATALERROR_ipd : std_ulogic; + signal L0SETDETECTEDNONFATALERROR_ipd : std_ulogic; + signal L0SETLINKDETECTEDPARITYERROR_ipd : std_ulogic; + signal L0SETLINKMASTERDATAPARITY_ipd : std_ulogic; + signal L0SETLINKRECEIVEDMASTERABORT_ipd : std_ulogic; + signal L0SETLINKRECEIVEDTARGETABORT_ipd : std_ulogic; + signal L0SETLINKSYSTEMERROR_ipd : std_ulogic; + signal L0SETLINKSIGNALLEDTARGETABORT_ipd : std_ulogic; + signal L0SETUSERDETECTEDPARITYERROR_ipd : std_ulogic; + signal L0SETUSERMASTERDATAPARITY_ipd : std_ulogic; + signal L0SETUSERRECEIVEDMASTERABORT_ipd : std_ulogic; + signal L0SETUSERRECEIVEDTARGETABORT_ipd : std_ulogic; + signal L0SETUSERSYSTEMERROR_ipd : std_ulogic; + signal L0SETUSERSIGNALLEDTARGETABORT_ipd : std_ulogic; + signal L0SETCOMPLETIONTIMEOUTUNCORRERROR_ipd : std_ulogic; + signal L0SETCOMPLETIONTIMEOUTCORRERROR_ipd : std_ulogic; + signal L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_ipd : std_ulogic; + signal L0SETUNEXPECTEDCOMPLETIONCORRERROR_ipd : std_ulogic; + signal L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_ipd : std_ulogic; + signal L0SETUNSUPPORTEDREQUESTOTHERERROR_ipd : std_ulogic; + signal L0PACKETHEADERFROMUSER_ipd : std_logic_vector(127 downto 0); + signal L0LEGACYINTFUNCT0_ipd : std_ulogic; + signal L0FWDASSERTINTALEGACYINT_ipd : std_ulogic; + signal L0FWDASSERTINTBLEGACYINT_ipd : std_ulogic; + signal L0FWDASSERTINTCLEGACYINT_ipd : std_ulogic; + signal L0FWDASSERTINTDLEGACYINT_ipd : std_ulogic; + signal L0FWDDEASSERTINTALEGACYINT_ipd : std_ulogic; + signal L0FWDDEASSERTINTBLEGACYINT_ipd : std_ulogic; + signal L0FWDDEASSERTINTCLEGACYINT_ipd : std_ulogic; + signal L0FWDDEASSERTINTDLEGACYINT_ipd : std_ulogic; + signal L0MSIREQUEST0_ipd : std_logic_vector(3 downto 0); + signal L0ELECTROMECHANICALINTERLOCKENGAGED_ipd : std_ulogic; + signal L0MRLSENSORCLOSEDN_ipd : std_ulogic; + signal L0POWERFAULTDETECTED_ipd : std_ulogic; + signal L0PRESENCEDETECTSLOTEMPTYN_ipd : std_ulogic; + signal L0ATTENTIONBUTTONPRESSED_ipd : std_ulogic; + signal L0TXBEACON_ipd : std_ulogic; + signal L0WAKEN_ipd : std_ulogic; + signal L0PMEREQIN_ipd : std_ulogic; + signal L0ROOTTURNOFFREQ_ipd : std_ulogic; + signal L0TXCFGPM_ipd : std_ulogic; + signal L0TXCFGPMTYPE_ipd : std_logic_vector(2 downto 0); + signal L0PWRNEWSTATEREQ_ipd : std_ulogic; + signal L0PWRNEXTLINKSTATE_ipd : std_logic_vector(1 downto 0); + signal L0CFGL0SENTRYSUP_ipd : std_ulogic; + signal L0CFGL0SENTRYENABLE_ipd : std_ulogic; + signal L0CFGL0SEXITLAT_ipd : std_logic_vector(2 downto 0); + signal L0TXTLTLPDATA_ipd : std_logic_vector(63 downto 0); + signal L0TXTLTLPEND_ipd : std_logic_vector(1 downto 0); + signal L0TXTLTLPENABLE_ipd : std_logic_vector(1 downto 0); + signal L0TXTLTLPEDB_ipd : std_ulogic; + signal L0TXTLTLPREQ_ipd : std_ulogic; + signal L0TXTLTLPREQEND_ipd : std_ulogic; + signal L0TXTLTLPWIDTH_ipd : std_ulogic; + signal L0TXTLTLPLATENCY_ipd : std_logic_vector(3 downto 0); + signal L0TLASFCCREDSTARVATION_ipd : std_ulogic; + signal L0TXTLSBFCDATA_ipd : std_logic_vector(18 downto 0); + signal L0TXTLSBFCUPDATE_ipd : std_ulogic; + signal L0TXTLFCNPOSTBYPCRED_ipd : std_logic_vector(191 downto 0); + signal L0TXTLFCNPOSTBYPUPDATE_ipd : std_logic_vector(15 downto 0); + signal L0TXTLFCPOSTORDCRED_ipd : std_logic_vector(159 downto 0); + signal L0TXTLFCPOSTORDUPDATE_ipd : std_logic_vector(15 downto 0); + signal L0TXTLFCCMPLMCCRED_ipd : std_logic_vector(159 downto 0); + signal L0TXTLFCCMPLMCUPDATE_ipd : std_logic_vector(15 downto 0); + signal L0RXTLTLPNONINITIALIZEDVC_ipd : std_logic_vector(7 downto 0); + + + signal PIPERXELECIDLEL0_indelay : std_ulogic; + signal PIPERXSTATUSL0_indelay : std_logic_vector(2 downto 0); + signal PIPERXDATAL0_indelay : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL0_indelay : std_ulogic; + signal PIPERXDATAKL0_indelay : std_ulogic; + signal PIPERXVALIDL0_indelay : std_ulogic; + signal PIPERXCHANISALIGNEDL0_indelay : std_ulogic; + signal PIPERXELECIDLEL1_indelay : std_ulogic; + signal PIPERXSTATUSL1_indelay : std_logic_vector(2 downto 0); + signal PIPERXDATAL1_indelay : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL1_indelay : std_ulogic; + signal PIPERXDATAKL1_indelay : std_ulogic; + signal PIPERXVALIDL1_indelay : std_ulogic; + signal PIPERXCHANISALIGNEDL1_indelay : std_ulogic; + signal PIPERXELECIDLEL2_indelay : std_ulogic; + signal PIPERXSTATUSL2_indelay : std_logic_vector(2 downto 0); + signal PIPERXDATAL2_indelay : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL2_indelay : std_ulogic; + signal PIPERXDATAKL2_indelay : std_ulogic; + signal PIPERXVALIDL2_indelay : std_ulogic; + signal PIPERXCHANISALIGNEDL2_indelay : std_ulogic; + signal PIPERXELECIDLEL3_indelay : std_ulogic; + signal PIPERXSTATUSL3_indelay : std_logic_vector(2 downto 0); + signal PIPERXDATAL3_indelay : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL3_indelay : std_ulogic; + signal PIPERXDATAKL3_indelay : std_ulogic; + signal PIPERXVALIDL3_indelay : std_ulogic; + signal PIPERXCHANISALIGNEDL3_indelay : std_ulogic; + signal PIPERXELECIDLEL4_indelay : std_ulogic; + signal PIPERXSTATUSL4_indelay : std_logic_vector(2 downto 0); + signal PIPERXDATAL4_indelay : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL4_indelay : std_ulogic; + signal PIPERXDATAKL4_indelay : std_ulogic; + signal PIPERXVALIDL4_indelay : std_ulogic; + signal PIPERXCHANISALIGNEDL4_indelay : std_ulogic; + signal PIPERXELECIDLEL5_indelay : std_ulogic; + signal PIPERXSTATUSL5_indelay : std_logic_vector(2 downto 0); + signal PIPERXDATAL5_indelay : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL5_indelay : std_ulogic; + signal PIPERXDATAKL5_indelay : std_ulogic; + signal PIPERXVALIDL5_indelay : std_ulogic; + signal PIPERXCHANISALIGNEDL5_indelay : std_ulogic; + signal PIPERXELECIDLEL6_indelay : std_ulogic; + signal PIPERXSTATUSL6_indelay : std_logic_vector(2 downto 0); + signal PIPERXDATAL6_indelay : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL6_indelay : std_ulogic; + signal PIPERXDATAKL6_indelay : std_ulogic; + signal PIPERXVALIDL6_indelay : std_ulogic; + signal PIPERXCHANISALIGNEDL6_indelay : std_ulogic; + signal PIPERXELECIDLEL7_indelay : std_ulogic; + signal PIPERXSTATUSL7_indelay : std_logic_vector(2 downto 0); + signal PIPERXDATAL7_indelay : std_logic_vector(7 downto 0); + signal PIPEPHYSTATUSL7_indelay : std_ulogic; + signal PIPERXDATAKL7_indelay : std_ulogic; + signal PIPERXVALIDL7_indelay : std_ulogic; + signal PIPERXCHANISALIGNEDL7_indelay : std_ulogic; + signal MIMRXBRDATA_indelay : std_logic_vector(63 downto 0); + signal CRMCORECLKRXO_indelay : std_ulogic; + signal CRMUSERCLKRXO_indelay : std_ulogic; + signal MIMTXBRDATA_indelay : std_logic_vector(63 downto 0); + signal CRMCORECLKTXO_indelay : std_ulogic; + signal CRMUSERCLKTXO_indelay : std_ulogic; + signal MIMDLLBRDATA_indelay : std_logic_vector(63 downto 0); + signal CRMCORECLKDLO_indelay : std_ulogic; + signal CRMCORECLK_indelay : std_ulogic; + signal CRMUSERCLK_indelay : std_ulogic; + signal CRMURSTN_indelay : std_ulogic; + signal CRMNVRSTN_indelay : std_ulogic; + signal CRMMGMTRSTN_indelay : std_ulogic; + signal CRMUSERCFGRSTN_indelay : std_ulogic; + signal CRMMACRSTN_indelay : std_ulogic; + signal CRMLINKRSTN_indelay : std_ulogic; + signal CRMTXHOTRESETN_indelay : std_ulogic; + signal CRMCFGBRIDGEHOTRESET_indelay : std_ulogic; + signal LLKTXDATA_indelay : std_logic_vector(63 downto 0); + signal LLKTXSRCRDYN_indelay : std_ulogic; + signal LLKTXSRCDSCN_indelay : std_ulogic; + signal LLKTXCOMPLETEN_indelay : std_ulogic; + signal LLKTXSOFN_indelay : std_ulogic; + signal LLKTXEOFN_indelay : std_ulogic; + signal LLKTXSOPN_indelay : std_ulogic; + signal LLKTXEOPN_indelay : std_ulogic; + signal LLKTXENABLEN_indelay : std_logic_vector(1 downto 0); + signal LLKTXCHTC_indelay : std_logic_vector(2 downto 0); + signal LLKTXCHFIFO_indelay : std_logic_vector(1 downto 0); + signal LLKTXCREATEECRCN_indelay : std_ulogic; + signal LLKTX4DWHEADERN_indelay : std_ulogic; + signal LLKRXDSTREQN_indelay : std_ulogic; + signal LLKRXCHTC_indelay : std_logic_vector(2 downto 0); + signal LLKRXCHFIFO_indelay : std_logic_vector(1 downto 0); + signal LLKRXDSTCONTREQN_indelay : std_ulogic; + signal MGMTWDATA_indelay : std_logic_vector(31 downto 0); + signal MGMTBWREN_indelay : std_logic_vector(3 downto 0); + signal MGMTWREN_indelay : std_ulogic; + signal MGMTADDR_indelay : std_logic_vector(10 downto 0); + signal MGMTRDEN_indelay : std_ulogic; + signal MGMTSTATSCREDITSEL_indelay : std_logic_vector(6 downto 0); + signal MAINPOWER_indelay : std_ulogic; + signal AUXPOWER_indelay : std_ulogic; + signal L0TLLINKRETRAIN_indelay : std_ulogic; + signal CFGNEGOTIATEDLINKWIDTH_indelay : std_logic_vector(5 downto 0); + signal CROSSLINKSEED_indelay : std_ulogic; + signal COMPLIANCEAVOID_indelay : std_ulogic; + signal L0VC0PREVIEWEXPAND_indelay : std_ulogic; + signal L0CFGVCID_indelay : std_logic_vector(23 downto 0); + signal L0CFGLOOPBACKMASTER_indelay : std_ulogic; + signal L0REPLAYTIMERADJUSTMENT_indelay : std_logic_vector(11 downto 0); + signal L0ACKNAKTIMERADJUSTMENT_indelay : std_logic_vector(11 downto 0); + signal L0DLLHOLDLINKUP_indelay : std_ulogic; + signal L0CFGASSTATECHANGECMD_indelay : std_logic_vector(3 downto 0); + signal L0CFGASSPANTREEOWNEDSTATE_indelay : std_ulogic; + signal L0ASE_indelay : std_ulogic; + signal L0ASTURNPOOLBITSCONSUMED_indelay : std_logic_vector(2 downto 0); + signal L0ASPORTCOUNT_indelay : std_logic_vector(7 downto 0); + signal L0CFGVCENABLE_indelay : std_logic_vector(7 downto 0); + signal L0CFGNEGOTIATEDMAXP_indelay : std_logic_vector(2 downto 0); + signal L0CFGDISABLESCRAMBLE_indelay : std_ulogic; + signal L0CFGEXTENDEDSYNC_indelay : std_ulogic; + signal L0CFGLINKDISABLE_indelay : std_ulogic; + signal L0PORTNUMBER_indelay : std_logic_vector(7 downto 0); + signal L0SENDUNLOCKMESSAGE_indelay : std_ulogic; + signal L0ALLDOWNRXPORTSINL0S_indelay : std_ulogic; + signal L0UPSTREAMRXPORTINL0S_indelay : std_ulogic; + signal L0TRANSACTIONSPENDING_indelay : std_ulogic; + signal L0ALLDOWNPORTSINL1_indelay : std_ulogic; + signal L0FWDCORRERRIN_indelay : std_ulogic; + signal L0FWDFATALERRIN_indelay : std_ulogic; + signal L0FWDNONFATALERRIN_indelay : std_ulogic; + signal L0SETCOMPLETERABORTERROR_indelay : std_ulogic; + signal L0SETDETECTEDCORRERROR_indelay : std_ulogic; + signal L0SETDETECTEDFATALERROR_indelay : std_ulogic; + signal L0SETDETECTEDNONFATALERROR_indelay : std_ulogic; + signal L0SETLINKDETECTEDPARITYERROR_indelay : std_ulogic; + signal L0SETLINKMASTERDATAPARITY_indelay : std_ulogic; + signal L0SETLINKRECEIVEDMASTERABORT_indelay : std_ulogic; + signal L0SETLINKRECEIVEDTARGETABORT_indelay : std_ulogic; + signal L0SETLINKSYSTEMERROR_indelay : std_ulogic; + signal L0SETLINKSIGNALLEDTARGETABORT_indelay : std_ulogic; + signal L0SETUSERDETECTEDPARITYERROR_indelay : std_ulogic; + signal L0SETUSERMASTERDATAPARITY_indelay : std_ulogic; + signal L0SETUSERRECEIVEDMASTERABORT_indelay : std_ulogic; + signal L0SETUSERRECEIVEDTARGETABORT_indelay : std_ulogic; + signal L0SETUSERSYSTEMERROR_indelay : std_ulogic; + signal L0SETUSERSIGNALLEDTARGETABORT_indelay : std_ulogic; + signal L0SETCOMPLETIONTIMEOUTUNCORRERROR_indelay : std_ulogic; + signal L0SETCOMPLETIONTIMEOUTCORRERROR_indelay : std_ulogic; + signal L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_indelay : std_ulogic; + signal L0SETUNEXPECTEDCOMPLETIONCORRERROR_indelay : std_ulogic; + signal L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_indelay : std_ulogic; + signal L0SETUNSUPPORTEDREQUESTOTHERERROR_indelay : std_ulogic; + signal L0PACKETHEADERFROMUSER_indelay : std_logic_vector(127 downto 0); + signal L0LEGACYINTFUNCT0_indelay : std_ulogic; + signal L0FWDASSERTINTALEGACYINT_indelay : std_ulogic; + signal L0FWDASSERTINTBLEGACYINT_indelay : std_ulogic; + signal L0FWDASSERTINTCLEGACYINT_indelay : std_ulogic; + signal L0FWDASSERTINTDLEGACYINT_indelay : std_ulogic; + signal L0FWDDEASSERTINTALEGACYINT_indelay : std_ulogic; + signal L0FWDDEASSERTINTBLEGACYINT_indelay : std_ulogic; + signal L0FWDDEASSERTINTCLEGACYINT_indelay : std_ulogic; + signal L0FWDDEASSERTINTDLEGACYINT_indelay : std_ulogic; + signal L0MSIREQUEST0_indelay : std_logic_vector(3 downto 0); + signal L0ELECTROMECHANICALINTERLOCKENGAGED_indelay : std_ulogic; + signal L0MRLSENSORCLOSEDN_indelay : std_ulogic; + signal L0POWERFAULTDETECTED_indelay : std_ulogic; + signal L0PRESENCEDETECTSLOTEMPTYN_indelay : std_ulogic; + signal L0ATTENTIONBUTTONPRESSED_indelay : std_ulogic; + signal L0TXBEACON_indelay : std_ulogic; + signal L0WAKEN_indelay : std_ulogic; + signal L0PMEREQIN_indelay : std_ulogic; + signal L0ROOTTURNOFFREQ_indelay : std_ulogic; + signal L0TXCFGPM_indelay : std_ulogic; + signal L0TXCFGPMTYPE_indelay : std_logic_vector(2 downto 0); + signal L0PWRNEWSTATEREQ_indelay : std_ulogic; + signal L0PWRNEXTLINKSTATE_indelay : std_logic_vector(1 downto 0); + signal L0CFGL0SENTRYSUP_indelay : std_ulogic; + signal L0CFGL0SENTRYENABLE_indelay : std_ulogic; + signal L0CFGL0SEXITLAT_indelay : std_logic_vector(2 downto 0); + signal L0TXTLTLPDATA_indelay : std_logic_vector(63 downto 0); + signal L0TXTLTLPEND_indelay : std_logic_vector(1 downto 0); + signal L0TXTLTLPENABLE_indelay : std_logic_vector(1 downto 0); + signal L0TXTLTLPEDB_indelay : std_ulogic; + signal L0TXTLTLPREQ_indelay : std_ulogic; + signal L0TXTLTLPREQEND_indelay : std_ulogic; + signal L0TXTLTLPWIDTH_indelay : std_ulogic; + signal L0TXTLTLPLATENCY_indelay : std_logic_vector(3 downto 0); + signal L0TLASFCCREDSTARVATION_indelay : std_ulogic; + signal L0TXTLSBFCDATA_indelay : std_logic_vector(18 downto 0); + signal L0TXTLSBFCUPDATE_indelay : std_ulogic; + signal L0TXTLFCNPOSTBYPCRED_indelay : std_logic_vector(191 downto 0); + signal L0TXTLFCNPOSTBYPUPDATE_indelay : std_logic_vector(15 downto 0); + signal L0TXTLFCPOSTORDCRED_indelay : std_logic_vector(159 downto 0); + signal L0TXTLFCPOSTORDUPDATE_indelay : std_logic_vector(15 downto 0); + signal L0TXTLFCCMPLMCCRED_indelay : std_logic_vector(159 downto 0); + signal L0TXTLFCCMPLMCUPDATE_indelay : std_logic_vector(15 downto 0); + signal L0RXTLTLPNONINITIALIZEDVC_indelay : std_logic_vector(7 downto 0); + +begin + + + BUSMASTERENABLE_out <= BUSMASTERENABLE_outdelay after OUT_DELAY; + CRMDOHOTRESETN_out <= CRMDOHOTRESETN_outdelay after OUT_DELAY; + CRMPWRSOFTRESETN_out <= CRMPWRSOFTRESETN_outdelay after OUT_DELAY; + CRMRXHOTRESETN_out <= CRMRXHOTRESETN_outdelay after OUT_DELAY; + DLLTXPMDLLPOUTSTANDING_out <= DLLTXPMDLLPOUTSTANDING_outdelay after OUT_DELAY; + INTERRUPTDISABLE_out <= INTERRUPTDISABLE_outdelay after OUT_DELAY; + IOSPACEENABLE_out <= IOSPACEENABLE_outdelay after OUT_DELAY; + L0ASAUTONOMOUSINITCOMPLETED_out <= L0ASAUTONOMOUSINITCOMPLETED_outdelay after OUT_DELAY; + L0ATTENTIONINDICATORCONTROL_out <= L0ATTENTIONINDICATORCONTROL_outdelay after OUT_DELAY; + L0CFGLOOPBACKACK_out <= L0CFGLOOPBACKACK_outdelay after OUT_DELAY; + L0COMPLETERID_out <= L0COMPLETERID_outdelay after OUT_DELAY; + L0CORRERRMSGRCVD_out <= L0CORRERRMSGRCVD_outdelay after OUT_DELAY; + L0DLLASRXSTATE_out <= L0DLLASRXSTATE_outdelay after OUT_DELAY; + L0DLLASTXSTATE_out <= L0DLLASTXSTATE_outdelay after OUT_DELAY; + L0DLLERRORVECTOR_out <= L0DLLERRORVECTOR_outdelay after OUT_DELAY; + L0DLLRXACKOUTSTANDING_out <= L0DLLRXACKOUTSTANDING_outdelay after OUT_DELAY; + L0DLLTXNONFCOUTSTANDING_out <= L0DLLTXNONFCOUTSTANDING_outdelay after OUT_DELAY; + L0DLLTXOUTSTANDING_out <= L0DLLTXOUTSTANDING_outdelay after OUT_DELAY; + L0DLLVCSTATUS_out <= L0DLLVCSTATUS_outdelay after OUT_DELAY; + L0DLUPDOWN_out <= L0DLUPDOWN_outdelay after OUT_DELAY; + L0ERRMSGREQID_out <= L0ERRMSGREQID_outdelay after OUT_DELAY; + L0FATALERRMSGRCVD_out <= L0FATALERRMSGRCVD_outdelay after OUT_DELAY; + L0FIRSTCFGWRITEOCCURRED_out <= L0FIRSTCFGWRITEOCCURRED_outdelay after OUT_DELAY; + L0FWDCORRERROUT_out <= L0FWDCORRERROUT_outdelay after OUT_DELAY; + L0FWDFATALERROUT_out <= L0FWDFATALERROUT_outdelay after OUT_DELAY; + L0FWDNONFATALERROUT_out <= L0FWDNONFATALERROUT_outdelay after OUT_DELAY; + L0LTSSMSTATE_out <= L0LTSSMSTATE_outdelay after OUT_DELAY; + L0MACENTEREDL0_out <= L0MACENTEREDL0_outdelay after OUT_DELAY; + L0MACLINKTRAINING_out <= L0MACLINKTRAINING_outdelay after OUT_DELAY; + L0MACLINKUP_out <= L0MACLINKUP_outdelay after OUT_DELAY; + L0MACNEGOTIATEDLINKWIDTH_out <= L0MACNEGOTIATEDLINKWIDTH_outdelay after OUT_DELAY; + L0MACNEWSTATEACK_out <= L0MACNEWSTATEACK_outdelay after OUT_DELAY; + L0MACRXL0SSTATE_out <= L0MACRXL0SSTATE_outdelay after OUT_DELAY; + L0MACUPSTREAMDOWNSTREAM_out <= L0MACUPSTREAMDOWNSTREAM_outdelay after OUT_DELAY; + L0MCFOUND_out <= L0MCFOUND_outdelay after OUT_DELAY; + L0MSIENABLE0_out <= L0MSIENABLE0_outdelay after OUT_DELAY; + L0MULTIMSGEN0_out <= L0MULTIMSGEN0_outdelay after OUT_DELAY; + L0NONFATALERRMSGRCVD_out <= L0NONFATALERRMSGRCVD_outdelay after OUT_DELAY; + L0PMEACK_out <= L0PMEACK_outdelay after OUT_DELAY; + L0PMEEN_out <= L0PMEEN_outdelay after OUT_DELAY; + L0PMEREQOUT_out <= L0PMEREQOUT_outdelay after OUT_DELAY; + L0POWERCONTROLLERCONTROL_out <= L0POWERCONTROLLERCONTROL_outdelay after OUT_DELAY; + L0POWERINDICATORCONTROL_out <= L0POWERINDICATORCONTROL_outdelay after OUT_DELAY; + L0PWRINHIBITTRANSFERS_out <= L0PWRINHIBITTRANSFERS_outdelay after OUT_DELAY; + L0PWRL1STATE_out <= L0PWRL1STATE_outdelay after OUT_DELAY; + L0PWRL23READYDEVICE_out <= L0PWRL23READYDEVICE_outdelay after OUT_DELAY; + L0PWRL23READYSTATE_out <= L0PWRL23READYSTATE_outdelay after OUT_DELAY; + L0PWRSTATE0_out <= L0PWRSTATE0_outdelay after OUT_DELAY; + L0PWRTURNOFFREQ_out <= L0PWRTURNOFFREQ_outdelay after OUT_DELAY; + L0PWRTXL0SSTATE_out <= L0PWRTXL0SSTATE_outdelay after OUT_DELAY; + L0RECEIVEDASSERTINTALEGACYINT_out <= L0RECEIVEDASSERTINTALEGACYINT_outdelay after OUT_DELAY; + L0RECEIVEDASSERTINTBLEGACYINT_out <= L0RECEIVEDASSERTINTBLEGACYINT_outdelay after OUT_DELAY; + L0RECEIVEDASSERTINTCLEGACYINT_out <= L0RECEIVEDASSERTINTCLEGACYINT_outdelay after OUT_DELAY; + L0RECEIVEDASSERTINTDLEGACYINT_out <= L0RECEIVEDASSERTINTDLEGACYINT_outdelay after OUT_DELAY; + L0RECEIVEDDEASSERTINTALEGACYINT_out <= L0RECEIVEDDEASSERTINTALEGACYINT_outdelay after OUT_DELAY; + L0RECEIVEDDEASSERTINTBLEGACYINT_out <= L0RECEIVEDDEASSERTINTBLEGACYINT_outdelay after OUT_DELAY; + L0RECEIVEDDEASSERTINTCLEGACYINT_out <= L0RECEIVEDDEASSERTINTCLEGACYINT_outdelay after OUT_DELAY; + L0RECEIVEDDEASSERTINTDLEGACYINT_out <= L0RECEIVEDDEASSERTINTDLEGACYINT_outdelay after OUT_DELAY; + L0RXBEACON_out <= L0RXBEACON_outdelay after OUT_DELAY; + L0RXDLLFCCMPLMCCRED_out <= L0RXDLLFCCMPLMCCRED_outdelay after OUT_DELAY; + L0RXDLLFCCMPLMCUPDATE_out <= L0RXDLLFCCMPLMCUPDATE_outdelay after OUT_DELAY; + L0RXDLLFCNPOSTBYPCRED_out <= L0RXDLLFCNPOSTBYPCRED_outdelay after OUT_DELAY; + L0RXDLLFCNPOSTBYPUPDATE_out <= L0RXDLLFCNPOSTBYPUPDATE_outdelay after OUT_DELAY; + L0RXDLLFCPOSTORDCRED_out <= L0RXDLLFCPOSTORDCRED_outdelay after OUT_DELAY; + L0RXDLLFCPOSTORDUPDATE_out <= L0RXDLLFCPOSTORDUPDATE_outdelay after OUT_DELAY; + L0RXDLLPMTYPE_out <= L0RXDLLPMTYPE_outdelay after OUT_DELAY; + L0RXDLLPM_out <= L0RXDLLPM_outdelay after OUT_DELAY; + L0RXDLLSBFCDATA_out <= L0RXDLLSBFCDATA_outdelay after OUT_DELAY; + L0RXDLLSBFCUPDATE_out <= L0RXDLLSBFCUPDATE_outdelay after OUT_DELAY; + L0RXDLLTLPECRCOK_out <= L0RXDLLTLPECRCOK_outdelay after OUT_DELAY; + L0RXDLLTLPEND_out <= L0RXDLLTLPEND_outdelay after OUT_DELAY; + L0RXMACLINKERROR_out <= L0RXMACLINKERROR_outdelay after OUT_DELAY; + L0STATSCFGOTHERRECEIVED_out <= L0STATSCFGOTHERRECEIVED_outdelay after OUT_DELAY; + L0STATSCFGOTHERTRANSMITTED_out <= L0STATSCFGOTHERTRANSMITTED_outdelay after OUT_DELAY; + L0STATSCFGRECEIVED_out <= L0STATSCFGRECEIVED_outdelay after OUT_DELAY; + L0STATSCFGTRANSMITTED_out <= L0STATSCFGTRANSMITTED_outdelay after OUT_DELAY; + L0STATSDLLPRECEIVED_out <= L0STATSDLLPRECEIVED_outdelay after OUT_DELAY; + L0STATSDLLPTRANSMITTED_out <= L0STATSDLLPTRANSMITTED_outdelay after OUT_DELAY; + L0STATSOSRECEIVED_out <= L0STATSOSRECEIVED_outdelay after OUT_DELAY; + L0STATSOSTRANSMITTED_out <= L0STATSOSTRANSMITTED_outdelay after OUT_DELAY; + L0STATSTLPRECEIVED_out <= L0STATSTLPRECEIVED_outdelay after OUT_DELAY; + L0STATSTLPTRANSMITTED_out <= L0STATSTLPTRANSMITTED_outdelay after OUT_DELAY; + L0TOGGLEELECTROMECHANICALINTERLOCK_out <= L0TOGGLEELECTROMECHANICALINTERLOCK_outdelay after OUT_DELAY; + L0TRANSFORMEDVC_out <= L0TRANSFORMEDVC_outdelay after OUT_DELAY; + L0TXDLLFCCMPLMCUPDATED_out <= L0TXDLLFCCMPLMCUPDATED_outdelay after OUT_DELAY; + L0TXDLLFCNPOSTBYPUPDATED_out <= L0TXDLLFCNPOSTBYPUPDATED_outdelay after OUT_DELAY; + L0TXDLLFCPOSTORDUPDATED_out <= L0TXDLLFCPOSTORDUPDATED_outdelay after OUT_DELAY; + L0TXDLLPMUPDATED_out <= L0TXDLLPMUPDATED_outdelay after OUT_DELAY; + L0TXDLLSBFCUPDATED_out <= L0TXDLLSBFCUPDATED_outdelay after OUT_DELAY; + L0UCBYPFOUND_out <= L0UCBYPFOUND_outdelay after OUT_DELAY; + L0UCORDFOUND_out <= L0UCORDFOUND_outdelay after OUT_DELAY; + L0UNLOCKRECEIVED_out <= L0UNLOCKRECEIVED_outdelay after OUT_DELAY; + LLKRX4DWHEADERN_out <= LLKRX4DWHEADERN_outdelay after OUT_DELAY; + LLKRXCHCOMPLETIONAVAILABLEN_out <= LLKRXCHCOMPLETIONAVAILABLEN_outdelay after OUT_DELAY; + LLKRXCHCOMPLETIONPARTIALN_out <= LLKRXCHCOMPLETIONPARTIALN_outdelay after OUT_DELAY; + LLKRXCHCONFIGAVAILABLEN_out <= LLKRXCHCONFIGAVAILABLEN_outdelay after OUT_DELAY; + LLKRXCHCONFIGPARTIALN_out <= LLKRXCHCONFIGPARTIALN_outdelay after OUT_DELAY; + LLKRXCHNONPOSTEDAVAILABLEN_out <= LLKRXCHNONPOSTEDAVAILABLEN_outdelay after OUT_DELAY; + LLKRXCHNONPOSTEDPARTIALN_out <= LLKRXCHNONPOSTEDPARTIALN_outdelay after OUT_DELAY; + LLKRXCHPOSTEDAVAILABLEN_out <= LLKRXCHPOSTEDAVAILABLEN_outdelay after OUT_DELAY; + LLKRXCHPOSTEDPARTIALN_out <= LLKRXCHPOSTEDPARTIALN_outdelay after OUT_DELAY; + LLKRXDATA_out <= LLKRXDATA_outdelay after OUT_DELAY; + LLKRXECRCBADN_out <= LLKRXECRCBADN_outdelay after OUT_DELAY; + LLKRXEOFN_out <= LLKRXEOFN_outdelay after OUT_DELAY; + LLKRXEOPN_out <= LLKRXEOPN_outdelay after OUT_DELAY; + LLKRXPREFERREDTYPE_out <= LLKRXPREFERREDTYPE_outdelay after OUT_DELAY; + LLKRXSOFN_out <= LLKRXSOFN_outdelay after OUT_DELAY; + LLKRXSOPN_out <= LLKRXSOPN_outdelay after OUT_DELAY; + LLKRXSRCDSCN_out <= LLKRXSRCDSCN_outdelay after OUT_DELAY; + LLKRXSRCLASTREQN_out <= LLKRXSRCLASTREQN_outdelay after OUT_DELAY; + LLKRXSRCRDYN_out <= LLKRXSRCRDYN_outdelay after OUT_DELAY; + LLKRXVALIDN_out <= LLKRXVALIDN_outdelay after OUT_DELAY; + LLKTCSTATUS_out <= LLKTCSTATUS_outdelay after OUT_DELAY; + LLKTXCHANSPACE_out <= LLKTXCHANSPACE_outdelay after OUT_DELAY; + LLKTXCHCOMPLETIONREADYN_out <= LLKTXCHCOMPLETIONREADYN_outdelay after OUT_DELAY; + LLKTXCHNONPOSTEDREADYN_out <= LLKTXCHNONPOSTEDREADYN_outdelay after OUT_DELAY; + LLKTXCHPOSTEDREADYN_out <= LLKTXCHPOSTEDREADYN_outdelay after OUT_DELAY; + LLKTXCONFIGREADYN_out <= LLKTXCONFIGREADYN_outdelay after OUT_DELAY; + LLKTXDSTRDYN_out <= LLKTXDSTRDYN_outdelay after OUT_DELAY; + MAXPAYLOADSIZE_out <= MAXPAYLOADSIZE_outdelay after OUT_DELAY; + MAXREADREQUESTSIZE_out <= MAXREADREQUESTSIZE_outdelay after OUT_DELAY; + MEMSPACEENABLE_out <= MEMSPACEENABLE_outdelay after OUT_DELAY; + MGMTPSO_out <= MGMTPSO_outdelay after OUT_DELAY; + MGMTRDATA_out <= MGMTRDATA_outdelay after OUT_DELAY; + MGMTSTATSCREDIT_out <= MGMTSTATSCREDIT_outdelay after OUT_DELAY; + MIMDLLBRADD_out <= MIMDLLBRADD_outdelay after OUT_DELAY; + MIMDLLBREN_out <= MIMDLLBREN_outdelay after OUT_DELAY; + MIMDLLBWADD_out <= MIMDLLBWADD_outdelay after OUT_DELAY; + MIMDLLBWDATA_out <= MIMDLLBWDATA_outdelay after OUT_DELAY; + MIMDLLBWEN_out <= MIMDLLBWEN_outdelay after OUT_DELAY; + MIMRXBRADD_out <= MIMRXBRADD_outdelay after OUT_DELAY; + MIMRXBREN_out <= MIMRXBREN_outdelay after OUT_DELAY; + MIMRXBWADD_out <= MIMRXBWADD_outdelay after OUT_DELAY; + MIMRXBWDATA_out <= MIMRXBWDATA_outdelay after OUT_DELAY; + MIMRXBWEN_out <= MIMRXBWEN_outdelay after OUT_DELAY; + MIMTXBRADD_out <= MIMTXBRADD_outdelay after OUT_DELAY; + MIMTXBREN_out <= MIMTXBREN_outdelay after OUT_DELAY; + MIMTXBWADD_out <= MIMTXBWADD_outdelay after OUT_DELAY; + MIMTXBWDATA_out <= MIMTXBWDATA_outdelay after OUT_DELAY; + MIMTXBWEN_out <= MIMTXBWEN_outdelay after OUT_DELAY; + PARITYERRORRESPONSE_out <= PARITYERRORRESPONSE_outdelay after OUT_DELAY; + PIPEDESKEWLANESL0_out <= PIPEDESKEWLANESL0_outdelay after OUT_DELAY; + PIPEDESKEWLANESL1_out <= PIPEDESKEWLANESL1_outdelay after OUT_DELAY; + PIPEDESKEWLANESL2_out <= PIPEDESKEWLANESL2_outdelay after OUT_DELAY; + PIPEDESKEWLANESL3_out <= PIPEDESKEWLANESL3_outdelay after OUT_DELAY; + PIPEDESKEWLANESL4_out <= PIPEDESKEWLANESL4_outdelay after OUT_DELAY; + PIPEDESKEWLANESL5_out <= PIPEDESKEWLANESL5_outdelay after OUT_DELAY; + PIPEDESKEWLANESL6_out <= PIPEDESKEWLANESL6_outdelay after OUT_DELAY; + PIPEDESKEWLANESL7_out <= PIPEDESKEWLANESL7_outdelay after OUT_DELAY; + PIPEPOWERDOWNL0_out <= PIPEPOWERDOWNL0_outdelay after OUT_DELAY; + PIPEPOWERDOWNL1_out <= PIPEPOWERDOWNL1_outdelay after OUT_DELAY; + PIPEPOWERDOWNL2_out <= PIPEPOWERDOWNL2_outdelay after OUT_DELAY; + PIPEPOWERDOWNL3_out <= PIPEPOWERDOWNL3_outdelay after OUT_DELAY; + PIPEPOWERDOWNL4_out <= PIPEPOWERDOWNL4_outdelay after OUT_DELAY; + PIPEPOWERDOWNL5_out <= PIPEPOWERDOWNL5_outdelay after OUT_DELAY; + PIPEPOWERDOWNL6_out <= PIPEPOWERDOWNL6_outdelay after OUT_DELAY; + PIPEPOWERDOWNL7_out <= PIPEPOWERDOWNL7_outdelay after OUT_DELAY; + PIPERESETL0_out <= PIPERESETL0_outdelay after OUT_DELAY; + PIPERESETL1_out <= PIPERESETL1_outdelay after OUT_DELAY; + PIPERESETL2_out <= PIPERESETL2_outdelay after OUT_DELAY; + PIPERESETL3_out <= PIPERESETL3_outdelay after OUT_DELAY; + PIPERESETL4_out <= PIPERESETL4_outdelay after OUT_DELAY; + PIPERESETL5_out <= PIPERESETL5_outdelay after OUT_DELAY; + PIPERESETL6_out <= PIPERESETL6_outdelay after OUT_DELAY; + PIPERESETL7_out <= PIPERESETL7_outdelay after OUT_DELAY; + PIPERXPOLARITYL0_out <= PIPERXPOLARITYL0_outdelay after OUT_DELAY; + PIPERXPOLARITYL1_out <= PIPERXPOLARITYL1_outdelay after OUT_DELAY; + PIPERXPOLARITYL2_out <= PIPERXPOLARITYL2_outdelay after OUT_DELAY; + PIPERXPOLARITYL3_out <= PIPERXPOLARITYL3_outdelay after OUT_DELAY; + PIPERXPOLARITYL4_out <= PIPERXPOLARITYL4_outdelay after OUT_DELAY; + PIPERXPOLARITYL5_out <= PIPERXPOLARITYL5_outdelay after OUT_DELAY; + PIPERXPOLARITYL6_out <= PIPERXPOLARITYL6_outdelay after OUT_DELAY; + PIPERXPOLARITYL7_out <= PIPERXPOLARITYL7_outdelay after OUT_DELAY; + PIPETXCOMPLIANCEL0_out <= PIPETXCOMPLIANCEL0_outdelay after OUT_DELAY; + PIPETXCOMPLIANCEL1_out <= PIPETXCOMPLIANCEL1_outdelay after OUT_DELAY; + PIPETXCOMPLIANCEL2_out <= PIPETXCOMPLIANCEL2_outdelay after OUT_DELAY; + PIPETXCOMPLIANCEL3_out <= PIPETXCOMPLIANCEL3_outdelay after OUT_DELAY; + PIPETXCOMPLIANCEL4_out <= PIPETXCOMPLIANCEL4_outdelay after OUT_DELAY; + PIPETXCOMPLIANCEL5_out <= PIPETXCOMPLIANCEL5_outdelay after OUT_DELAY; + PIPETXCOMPLIANCEL6_out <= PIPETXCOMPLIANCEL6_outdelay after OUT_DELAY; + PIPETXCOMPLIANCEL7_out <= PIPETXCOMPLIANCEL7_outdelay after OUT_DELAY; + PIPETXDATAKL0_out <= PIPETXDATAKL0_outdelay after OUT_DELAY; + PIPETXDATAKL1_out <= PIPETXDATAKL1_outdelay after OUT_DELAY; + PIPETXDATAKL2_out <= PIPETXDATAKL2_outdelay after OUT_DELAY; + PIPETXDATAKL3_out <= PIPETXDATAKL3_outdelay after OUT_DELAY; + PIPETXDATAKL4_out <= PIPETXDATAKL4_outdelay after OUT_DELAY; + PIPETXDATAKL5_out <= PIPETXDATAKL5_outdelay after OUT_DELAY; + PIPETXDATAKL6_out <= PIPETXDATAKL6_outdelay after OUT_DELAY; + PIPETXDATAKL7_out <= PIPETXDATAKL7_outdelay after OUT_DELAY; + PIPETXDATAL0_out <= PIPETXDATAL0_outdelay after OUT_DELAY; + PIPETXDATAL1_out <= PIPETXDATAL1_outdelay after OUT_DELAY; + PIPETXDATAL2_out <= PIPETXDATAL2_outdelay after OUT_DELAY; + PIPETXDATAL3_out <= PIPETXDATAL3_outdelay after OUT_DELAY; + PIPETXDATAL4_out <= PIPETXDATAL4_outdelay after OUT_DELAY; + PIPETXDATAL5_out <= PIPETXDATAL5_outdelay after OUT_DELAY; + PIPETXDATAL6_out <= PIPETXDATAL6_outdelay after OUT_DELAY; + PIPETXDATAL7_out <= PIPETXDATAL7_outdelay after OUT_DELAY; + PIPETXDETECTRXLOOPBACKL0_out <= PIPETXDETECTRXLOOPBACKL0_outdelay after OUT_DELAY; + PIPETXDETECTRXLOOPBACKL1_out <= PIPETXDETECTRXLOOPBACKL1_outdelay after OUT_DELAY; + PIPETXDETECTRXLOOPBACKL2_out <= PIPETXDETECTRXLOOPBACKL2_outdelay after OUT_DELAY; + PIPETXDETECTRXLOOPBACKL3_out <= PIPETXDETECTRXLOOPBACKL3_outdelay after OUT_DELAY; + PIPETXDETECTRXLOOPBACKL4_out <= PIPETXDETECTRXLOOPBACKL4_outdelay after OUT_DELAY; + PIPETXDETECTRXLOOPBACKL5_out <= PIPETXDETECTRXLOOPBACKL5_outdelay after OUT_DELAY; + PIPETXDETECTRXLOOPBACKL6_out <= PIPETXDETECTRXLOOPBACKL6_outdelay after OUT_DELAY; + PIPETXDETECTRXLOOPBACKL7_out <= PIPETXDETECTRXLOOPBACKL7_outdelay after OUT_DELAY; + PIPETXELECIDLEL0_out <= PIPETXELECIDLEL0_outdelay after OUT_DELAY; + PIPETXELECIDLEL1_out <= PIPETXELECIDLEL1_outdelay after OUT_DELAY; + PIPETXELECIDLEL2_out <= PIPETXELECIDLEL2_outdelay after OUT_DELAY; + PIPETXELECIDLEL3_out <= PIPETXELECIDLEL3_outdelay after OUT_DELAY; + PIPETXELECIDLEL4_out <= PIPETXELECIDLEL4_outdelay after OUT_DELAY; + PIPETXELECIDLEL5_out <= PIPETXELECIDLEL5_outdelay after OUT_DELAY; + PIPETXELECIDLEL6_out <= PIPETXELECIDLEL6_outdelay after OUT_DELAY; + PIPETXELECIDLEL7_out <= PIPETXELECIDLEL7_outdelay after OUT_DELAY; + SERRENABLE_out <= SERRENABLE_outdelay after OUT_DELAY; + URREPORTINGENABLE_out <= URREPORTINGENABLE_outdelay after OUT_DELAY; + + CRMCORECLKDLO_ipd <= CRMCORECLKDLO after CLK_DELAY; + CRMCORECLKRXO_ipd <= CRMCORECLKRXO after CLK_DELAY; + CRMCORECLKTXO_ipd <= CRMCORECLKTXO after CLK_DELAY; + CRMCORECLK_ipd <= CRMCORECLK after CLK_DELAY; + CRMUSERCLKRXO_ipd <= CRMUSERCLKRXO after CLK_DELAY; + CRMUSERCLKTXO_ipd <= CRMUSERCLKTXO after CLK_DELAY; + CRMUSERCLK_ipd <= CRMUSERCLK after CLK_DELAY; + + AUXPOWER_ipd <= AUXPOWER after CLK_DELAY; + CFGNEGOTIATEDLINKWIDTH_ipd <= CFGNEGOTIATEDLINKWIDTH after CLK_DELAY; + COMPLIANCEAVOID_ipd <= COMPLIANCEAVOID after CLK_DELAY; + CRMCFGBRIDGEHOTRESET_ipd <= CRMCFGBRIDGEHOTRESET after CLK_DELAY; + CRMLINKRSTN_ipd <= CRMLINKRSTN after CLK_DELAY; + CRMMACRSTN_ipd <= CRMMACRSTN after CLK_DELAY; + CRMMGMTRSTN_ipd <= CRMMGMTRSTN after CLK_DELAY; + CRMNVRSTN_ipd <= CRMNVRSTN after CLK_DELAY; + CRMTXHOTRESETN_ipd <= CRMTXHOTRESETN after CLK_DELAY; + CRMURSTN_ipd <= CRMURSTN after CLK_DELAY; + CRMUSERCFGRSTN_ipd <= CRMUSERCFGRSTN after CLK_DELAY; + CROSSLINKSEED_ipd <= CROSSLINKSEED after CLK_DELAY; + L0ACKNAKTIMERADJUSTMENT_ipd <= L0ACKNAKTIMERADJUSTMENT after CLK_DELAY; + L0ALLDOWNPORTSINL1_ipd <= L0ALLDOWNPORTSINL1 after CLK_DELAY; + L0ALLDOWNRXPORTSINL0S_ipd <= L0ALLDOWNRXPORTSINL0S after CLK_DELAY; + L0ASE_ipd <= L0ASE after CLK_DELAY; + L0ASPORTCOUNT_ipd <= L0ASPORTCOUNT after CLK_DELAY; + L0ASTURNPOOLBITSCONSUMED_ipd <= L0ASTURNPOOLBITSCONSUMED after CLK_DELAY; + L0ATTENTIONBUTTONPRESSED_ipd <= L0ATTENTIONBUTTONPRESSED after CLK_DELAY; + L0CFGASSPANTREEOWNEDSTATE_ipd <= L0CFGASSPANTREEOWNEDSTATE after CLK_DELAY; + L0CFGASSTATECHANGECMD_ipd <= L0CFGASSTATECHANGECMD after CLK_DELAY; + L0CFGDISABLESCRAMBLE_ipd <= L0CFGDISABLESCRAMBLE after CLK_DELAY; + L0CFGEXTENDEDSYNC_ipd <= L0CFGEXTENDEDSYNC after CLK_DELAY; + L0CFGL0SENTRYENABLE_ipd <= L0CFGL0SENTRYENABLE after CLK_DELAY; + L0CFGL0SENTRYSUP_ipd <= L0CFGL0SENTRYSUP after CLK_DELAY; + L0CFGL0SEXITLAT_ipd <= L0CFGL0SEXITLAT after CLK_DELAY; + L0CFGLINKDISABLE_ipd <= L0CFGLINKDISABLE after CLK_DELAY; + L0CFGLOOPBACKMASTER_ipd <= L0CFGLOOPBACKMASTER after CLK_DELAY; + L0CFGNEGOTIATEDMAXP_ipd <= L0CFGNEGOTIATEDMAXP after CLK_DELAY; + L0CFGVCENABLE_ipd <= L0CFGVCENABLE after CLK_DELAY; + L0CFGVCID_ipd <= L0CFGVCID after CLK_DELAY; + L0DLLHOLDLINKUP_ipd <= L0DLLHOLDLINKUP after CLK_DELAY; + L0ELECTROMECHANICALINTERLOCKENGAGED_ipd <= L0ELECTROMECHANICALINTERLOCKENGAGED after CLK_DELAY; + L0FWDASSERTINTALEGACYINT_ipd <= L0FWDASSERTINTALEGACYINT after CLK_DELAY; + L0FWDASSERTINTBLEGACYINT_ipd <= L0FWDASSERTINTBLEGACYINT after CLK_DELAY; + L0FWDASSERTINTCLEGACYINT_ipd <= L0FWDASSERTINTCLEGACYINT after CLK_DELAY; + L0FWDASSERTINTDLEGACYINT_ipd <= L0FWDASSERTINTDLEGACYINT after CLK_DELAY; + L0FWDCORRERRIN_ipd <= L0FWDCORRERRIN after CLK_DELAY; + L0FWDDEASSERTINTALEGACYINT_ipd <= L0FWDDEASSERTINTALEGACYINT after CLK_DELAY; + L0FWDDEASSERTINTBLEGACYINT_ipd <= L0FWDDEASSERTINTBLEGACYINT after CLK_DELAY; + L0FWDDEASSERTINTCLEGACYINT_ipd <= L0FWDDEASSERTINTCLEGACYINT after CLK_DELAY; + L0FWDDEASSERTINTDLEGACYINT_ipd <= L0FWDDEASSERTINTDLEGACYINT after CLK_DELAY; + L0FWDFATALERRIN_ipd <= L0FWDFATALERRIN after CLK_DELAY; + L0FWDNONFATALERRIN_ipd <= L0FWDNONFATALERRIN after CLK_DELAY; + L0LEGACYINTFUNCT0_ipd <= L0LEGACYINTFUNCT0 after CLK_DELAY; + L0MRLSENSORCLOSEDN_ipd <= L0MRLSENSORCLOSEDN after CLK_DELAY; + L0MSIREQUEST0_ipd <= L0MSIREQUEST0 after CLK_DELAY; + L0PACKETHEADERFROMUSER_ipd <= L0PACKETHEADERFROMUSER after CLK_DELAY; + L0PMEREQIN_ipd <= L0PMEREQIN after CLK_DELAY; + L0PORTNUMBER_ipd <= L0PORTNUMBER after CLK_DELAY; + L0POWERFAULTDETECTED_ipd <= L0POWERFAULTDETECTED after CLK_DELAY; + L0PRESENCEDETECTSLOTEMPTYN_ipd <= L0PRESENCEDETECTSLOTEMPTYN after CLK_DELAY; + L0PWRNEWSTATEREQ_ipd <= L0PWRNEWSTATEREQ after CLK_DELAY; + L0PWRNEXTLINKSTATE_ipd <= L0PWRNEXTLINKSTATE after CLK_DELAY; + L0REPLAYTIMERADJUSTMENT_ipd <= L0REPLAYTIMERADJUSTMENT after CLK_DELAY; + L0ROOTTURNOFFREQ_ipd <= L0ROOTTURNOFFREQ after CLK_DELAY; + L0RXTLTLPNONINITIALIZEDVC_ipd <= L0RXTLTLPNONINITIALIZEDVC after CLK_DELAY; + L0SENDUNLOCKMESSAGE_ipd <= L0SENDUNLOCKMESSAGE after CLK_DELAY; + L0SETCOMPLETERABORTERROR_ipd <= L0SETCOMPLETERABORTERROR after CLK_DELAY; + L0SETCOMPLETIONTIMEOUTCORRERROR_ipd <= L0SETCOMPLETIONTIMEOUTCORRERROR after CLK_DELAY; + L0SETCOMPLETIONTIMEOUTUNCORRERROR_ipd <= L0SETCOMPLETIONTIMEOUTUNCORRERROR after CLK_DELAY; + L0SETDETECTEDCORRERROR_ipd <= L0SETDETECTEDCORRERROR after CLK_DELAY; + L0SETDETECTEDFATALERROR_ipd <= L0SETDETECTEDFATALERROR after CLK_DELAY; + L0SETDETECTEDNONFATALERROR_ipd <= L0SETDETECTEDNONFATALERROR after CLK_DELAY; + L0SETLINKDETECTEDPARITYERROR_ipd <= L0SETLINKDETECTEDPARITYERROR after CLK_DELAY; + L0SETLINKMASTERDATAPARITY_ipd <= L0SETLINKMASTERDATAPARITY after CLK_DELAY; + L0SETLINKRECEIVEDMASTERABORT_ipd <= L0SETLINKRECEIVEDMASTERABORT after CLK_DELAY; + L0SETLINKRECEIVEDTARGETABORT_ipd <= L0SETLINKRECEIVEDTARGETABORT after CLK_DELAY; + L0SETLINKSIGNALLEDTARGETABORT_ipd <= L0SETLINKSIGNALLEDTARGETABORT after CLK_DELAY; + L0SETLINKSYSTEMERROR_ipd <= L0SETLINKSYSTEMERROR after CLK_DELAY; + L0SETUNEXPECTEDCOMPLETIONCORRERROR_ipd <= L0SETUNEXPECTEDCOMPLETIONCORRERROR after CLK_DELAY; + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_ipd <= L0SETUNEXPECTEDCOMPLETIONUNCORRERROR after CLK_DELAY; + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_ipd <= L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR after CLK_DELAY; + L0SETUNSUPPORTEDREQUESTOTHERERROR_ipd <= L0SETUNSUPPORTEDREQUESTOTHERERROR after CLK_DELAY; + L0SETUSERDETECTEDPARITYERROR_ipd <= L0SETUSERDETECTEDPARITYERROR after CLK_DELAY; + L0SETUSERMASTERDATAPARITY_ipd <= L0SETUSERMASTERDATAPARITY after CLK_DELAY; + L0SETUSERRECEIVEDMASTERABORT_ipd <= L0SETUSERRECEIVEDMASTERABORT after CLK_DELAY; + L0SETUSERRECEIVEDTARGETABORT_ipd <= L0SETUSERRECEIVEDTARGETABORT after CLK_DELAY; + L0SETUSERSIGNALLEDTARGETABORT_ipd <= L0SETUSERSIGNALLEDTARGETABORT after CLK_DELAY; + L0SETUSERSYSTEMERROR_ipd <= L0SETUSERSYSTEMERROR after CLK_DELAY; + L0TLASFCCREDSTARVATION_ipd <= L0TLASFCCREDSTARVATION after CLK_DELAY; + L0TLLINKRETRAIN_ipd <= L0TLLINKRETRAIN after CLK_DELAY; + L0TRANSACTIONSPENDING_ipd <= L0TRANSACTIONSPENDING after CLK_DELAY; + L0TXBEACON_ipd <= L0TXBEACON after CLK_DELAY; + L0TXCFGPMTYPE_ipd <= L0TXCFGPMTYPE after CLK_DELAY; + L0TXCFGPM_ipd <= L0TXCFGPM after CLK_DELAY; + L0TXTLFCCMPLMCCRED_ipd <= L0TXTLFCCMPLMCCRED after CLK_DELAY; + L0TXTLFCCMPLMCUPDATE_ipd <= L0TXTLFCCMPLMCUPDATE after CLK_DELAY; + L0TXTLFCNPOSTBYPCRED_ipd <= L0TXTLFCNPOSTBYPCRED after CLK_DELAY; + L0TXTLFCNPOSTBYPUPDATE_ipd <= L0TXTLFCNPOSTBYPUPDATE after CLK_DELAY; + L0TXTLFCPOSTORDCRED_ipd <= L0TXTLFCPOSTORDCRED after CLK_DELAY; + L0TXTLFCPOSTORDUPDATE_ipd <= L0TXTLFCPOSTORDUPDATE after CLK_DELAY; + L0TXTLSBFCDATA_ipd <= L0TXTLSBFCDATA after CLK_DELAY; + L0TXTLSBFCUPDATE_ipd <= L0TXTLSBFCUPDATE after CLK_DELAY; + L0TXTLTLPDATA_ipd <= L0TXTLTLPDATA after CLK_DELAY; + L0TXTLTLPEDB_ipd <= L0TXTLTLPEDB after CLK_DELAY; + L0TXTLTLPENABLE_ipd <= L0TXTLTLPENABLE after CLK_DELAY; + L0TXTLTLPEND_ipd <= L0TXTLTLPEND after CLK_DELAY; + L0TXTLTLPLATENCY_ipd <= L0TXTLTLPLATENCY after CLK_DELAY; + L0TXTLTLPREQEND_ipd <= L0TXTLTLPREQEND after CLK_DELAY; + L0TXTLTLPREQ_ipd <= L0TXTLTLPREQ after CLK_DELAY; + L0TXTLTLPWIDTH_ipd <= L0TXTLTLPWIDTH after CLK_DELAY; + L0UPSTREAMRXPORTINL0S_ipd <= L0UPSTREAMRXPORTINL0S after CLK_DELAY; + L0VC0PREVIEWEXPAND_ipd <= L0VC0PREVIEWEXPAND after CLK_DELAY; + L0WAKEN_ipd <= L0WAKEN after CLK_DELAY; + LLKRXCHFIFO_ipd <= LLKRXCHFIFO after CLK_DELAY; + LLKRXCHTC_ipd <= LLKRXCHTC after CLK_DELAY; + LLKRXDSTCONTREQN_ipd <= LLKRXDSTCONTREQN after CLK_DELAY; + LLKRXDSTREQN_ipd <= LLKRXDSTREQN after CLK_DELAY; + LLKTX4DWHEADERN_ipd <= LLKTX4DWHEADERN after CLK_DELAY; + LLKTXCHFIFO_ipd <= LLKTXCHFIFO after CLK_DELAY; + LLKTXCHTC_ipd <= LLKTXCHTC after CLK_DELAY; + LLKTXCOMPLETEN_ipd <= LLKTXCOMPLETEN after CLK_DELAY; + LLKTXCREATEECRCN_ipd <= LLKTXCREATEECRCN after CLK_DELAY; + LLKTXDATA_ipd <= LLKTXDATA after CLK_DELAY; + LLKTXENABLEN_ipd <= LLKTXENABLEN after CLK_DELAY; + LLKTXEOFN_ipd <= LLKTXEOFN after CLK_DELAY; + LLKTXEOPN_ipd <= LLKTXEOPN after CLK_DELAY; + LLKTXSOFN_ipd <= LLKTXSOFN after CLK_DELAY; + LLKTXSOPN_ipd <= LLKTXSOPN after CLK_DELAY; + LLKTXSRCDSCN_ipd <= LLKTXSRCDSCN after CLK_DELAY; + LLKTXSRCRDYN_ipd <= LLKTXSRCRDYN after CLK_DELAY; + MAINPOWER_ipd <= MAINPOWER after CLK_DELAY; + MGMTADDR_ipd <= MGMTADDR after CLK_DELAY; + MGMTBWREN_ipd <= MGMTBWREN after CLK_DELAY; + MGMTRDEN_ipd <= MGMTRDEN after CLK_DELAY; + MGMTSTATSCREDITSEL_ipd <= MGMTSTATSCREDITSEL after CLK_DELAY; + MGMTWDATA_ipd <= MGMTWDATA after CLK_DELAY; + MGMTWREN_ipd <= MGMTWREN after CLK_DELAY; + MIMDLLBRDATA_ipd <= MIMDLLBRDATA after CLK_DELAY; + MIMRXBRDATA_ipd <= MIMRXBRDATA after CLK_DELAY; + MIMTXBRDATA_ipd <= MIMTXBRDATA after CLK_DELAY; + PIPEPHYSTATUSL0_ipd <= PIPEPHYSTATUSL0 after CLK_DELAY; + PIPEPHYSTATUSL1_ipd <= PIPEPHYSTATUSL1 after CLK_DELAY; + PIPEPHYSTATUSL2_ipd <= PIPEPHYSTATUSL2 after CLK_DELAY; + PIPEPHYSTATUSL3_ipd <= PIPEPHYSTATUSL3 after CLK_DELAY; + PIPEPHYSTATUSL4_ipd <= PIPEPHYSTATUSL4 after CLK_DELAY; + PIPEPHYSTATUSL5_ipd <= PIPEPHYSTATUSL5 after CLK_DELAY; + PIPEPHYSTATUSL6_ipd <= PIPEPHYSTATUSL6 after CLK_DELAY; + PIPEPHYSTATUSL7_ipd <= PIPEPHYSTATUSL7 after CLK_DELAY; + PIPERXCHANISALIGNEDL0_ipd <= PIPERXCHANISALIGNEDL0 after CLK_DELAY; + PIPERXCHANISALIGNEDL1_ipd <= PIPERXCHANISALIGNEDL1 after CLK_DELAY; + PIPERXCHANISALIGNEDL2_ipd <= PIPERXCHANISALIGNEDL2 after CLK_DELAY; + PIPERXCHANISALIGNEDL3_ipd <= PIPERXCHANISALIGNEDL3 after CLK_DELAY; + PIPERXCHANISALIGNEDL4_ipd <= PIPERXCHANISALIGNEDL4 after CLK_DELAY; + PIPERXCHANISALIGNEDL5_ipd <= PIPERXCHANISALIGNEDL5 after CLK_DELAY; + PIPERXCHANISALIGNEDL6_ipd <= PIPERXCHANISALIGNEDL6 after CLK_DELAY; + PIPERXCHANISALIGNEDL7_ipd <= PIPERXCHANISALIGNEDL7 after CLK_DELAY; + PIPERXDATAKL0_ipd <= PIPERXDATAKL0 after CLK_DELAY; + PIPERXDATAKL1_ipd <= PIPERXDATAKL1 after CLK_DELAY; + PIPERXDATAKL2_ipd <= PIPERXDATAKL2 after CLK_DELAY; + PIPERXDATAKL3_ipd <= PIPERXDATAKL3 after CLK_DELAY; + PIPERXDATAKL4_ipd <= PIPERXDATAKL4 after CLK_DELAY; + PIPERXDATAKL5_ipd <= PIPERXDATAKL5 after CLK_DELAY; + PIPERXDATAKL6_ipd <= PIPERXDATAKL6 after CLK_DELAY; + PIPERXDATAKL7_ipd <= PIPERXDATAKL7 after CLK_DELAY; + PIPERXDATAL0_ipd <= PIPERXDATAL0 after CLK_DELAY; + PIPERXDATAL1_ipd <= PIPERXDATAL1 after CLK_DELAY; + PIPERXDATAL2_ipd <= PIPERXDATAL2 after CLK_DELAY; + PIPERXDATAL3_ipd <= PIPERXDATAL3 after CLK_DELAY; + PIPERXDATAL4_ipd <= PIPERXDATAL4 after CLK_DELAY; + PIPERXDATAL5_ipd <= PIPERXDATAL5 after CLK_DELAY; + PIPERXDATAL6_ipd <= PIPERXDATAL6 after CLK_DELAY; + PIPERXDATAL7_ipd <= PIPERXDATAL7 after CLK_DELAY; + PIPERXELECIDLEL0_ipd <= PIPERXELECIDLEL0 after CLK_DELAY; + PIPERXELECIDLEL1_ipd <= PIPERXELECIDLEL1 after CLK_DELAY; + PIPERXELECIDLEL2_ipd <= PIPERXELECIDLEL2 after CLK_DELAY; + PIPERXELECIDLEL3_ipd <= PIPERXELECIDLEL3 after CLK_DELAY; + PIPERXELECIDLEL4_ipd <= PIPERXELECIDLEL4 after CLK_DELAY; + PIPERXELECIDLEL5_ipd <= PIPERXELECIDLEL5 after CLK_DELAY; + PIPERXELECIDLEL6_ipd <= PIPERXELECIDLEL6 after CLK_DELAY; + PIPERXELECIDLEL7_ipd <= PIPERXELECIDLEL7 after CLK_DELAY; + PIPERXSTATUSL0_ipd <= PIPERXSTATUSL0 after CLK_DELAY; + PIPERXSTATUSL1_ipd <= PIPERXSTATUSL1 after CLK_DELAY; + PIPERXSTATUSL2_ipd <= PIPERXSTATUSL2 after CLK_DELAY; + PIPERXSTATUSL3_ipd <= PIPERXSTATUSL3 after CLK_DELAY; + PIPERXSTATUSL4_ipd <= PIPERXSTATUSL4 after CLK_DELAY; + PIPERXSTATUSL5_ipd <= PIPERXSTATUSL5 after CLK_DELAY; + PIPERXSTATUSL6_ipd <= PIPERXSTATUSL6 after CLK_DELAY; + PIPERXSTATUSL7_ipd <= PIPERXSTATUSL7 after CLK_DELAY; + PIPERXVALIDL0_ipd <= PIPERXVALIDL0 after CLK_DELAY; + PIPERXVALIDL1_ipd <= PIPERXVALIDL1 after CLK_DELAY; + PIPERXVALIDL2_ipd <= PIPERXVALIDL2 after CLK_DELAY; + PIPERXVALIDL3_ipd <= PIPERXVALIDL3 after CLK_DELAY; + PIPERXVALIDL4_ipd <= PIPERXVALIDL4 after CLK_DELAY; + PIPERXVALIDL5_ipd <= PIPERXVALIDL5 after CLK_DELAY; + PIPERXVALIDL6_ipd <= PIPERXVALIDL6 after CLK_DELAY; + PIPERXVALIDL7_ipd <= PIPERXVALIDL7 after CLK_DELAY; + + CRMCORECLKDLO_indelay <= CRMCORECLKDLO_ipd after CLK_DELAY; + CRMCORECLKRXO_indelay <= CRMCORECLKRXO_ipd after CLK_DELAY; + CRMCORECLKTXO_indelay <= CRMCORECLKTXO_ipd after CLK_DELAY; + CRMCORECLK_indelay <= CRMCORECLK_ipd after CLK_DELAY; + CRMUSERCLKRXO_indelay <= CRMUSERCLKRXO_ipd after CLK_DELAY; + CRMUSERCLKTXO_indelay <= CRMUSERCLKTXO_ipd after CLK_DELAY; + CRMUSERCLK_indelay <= CRMUSERCLK_ipd after CLK_DELAY; + + AUXPOWER_indelay <= AUXPOWER_ipd after IN_DELAY; + CFGNEGOTIATEDLINKWIDTH_indelay <= CFGNEGOTIATEDLINKWIDTH_ipd after IN_DELAY; + COMPLIANCEAVOID_indelay <= COMPLIANCEAVOID_ipd after IN_DELAY; + CRMCFGBRIDGEHOTRESET_indelay <= CRMCFGBRIDGEHOTRESET_ipd after IN_DELAY; + CRMLINKRSTN_indelay <= CRMLINKRSTN_ipd after IN_DELAY; + CRMMACRSTN_indelay <= CRMMACRSTN_ipd after IN_DELAY; + CRMMGMTRSTN_indelay <= CRMMGMTRSTN_ipd after IN_DELAY; + CRMNVRSTN_indelay <= CRMNVRSTN_ipd after IN_DELAY; + CRMTXHOTRESETN_indelay <= CRMTXHOTRESETN_ipd after IN_DELAY; + CRMURSTN_indelay <= CRMURSTN_ipd after IN_DELAY; + CRMUSERCFGRSTN_indelay <= CRMUSERCFGRSTN_ipd after IN_DELAY; + CROSSLINKSEED_indelay <= CROSSLINKSEED_ipd after IN_DELAY; + L0ACKNAKTIMERADJUSTMENT_indelay <= L0ACKNAKTIMERADJUSTMENT_ipd after IN_DELAY; + L0ALLDOWNPORTSINL1_indelay <= L0ALLDOWNPORTSINL1_ipd after IN_DELAY; + L0ALLDOWNRXPORTSINL0S_indelay <= L0ALLDOWNRXPORTSINL0S_ipd after IN_DELAY; + L0ASE_indelay <= L0ASE_ipd after IN_DELAY; + L0ASPORTCOUNT_indelay <= L0ASPORTCOUNT_ipd after IN_DELAY; + L0ASTURNPOOLBITSCONSUMED_indelay <= L0ASTURNPOOLBITSCONSUMED_ipd after IN_DELAY; + L0ATTENTIONBUTTONPRESSED_indelay <= L0ATTENTIONBUTTONPRESSED_ipd after IN_DELAY; + L0CFGASSPANTREEOWNEDSTATE_indelay <= L0CFGASSPANTREEOWNEDSTATE_ipd after IN_DELAY; + L0CFGASSTATECHANGECMD_indelay <= L0CFGASSTATECHANGECMD_ipd after IN_DELAY; + L0CFGDISABLESCRAMBLE_indelay <= L0CFGDISABLESCRAMBLE_ipd after IN_DELAY; + L0CFGEXTENDEDSYNC_indelay <= L0CFGEXTENDEDSYNC_ipd after IN_DELAY; + L0CFGL0SENTRYENABLE_indelay <= L0CFGL0SENTRYENABLE_ipd after IN_DELAY; + L0CFGL0SENTRYSUP_indelay <= L0CFGL0SENTRYSUP_ipd after IN_DELAY; + L0CFGL0SEXITLAT_indelay <= L0CFGL0SEXITLAT_ipd after IN_DELAY; + L0CFGLINKDISABLE_indelay <= L0CFGLINKDISABLE_ipd after IN_DELAY; + L0CFGLOOPBACKMASTER_indelay <= L0CFGLOOPBACKMASTER_ipd after IN_DELAY; + L0CFGNEGOTIATEDMAXP_indelay <= L0CFGNEGOTIATEDMAXP_ipd after IN_DELAY; + L0CFGVCENABLE_indelay <= L0CFGVCENABLE_ipd after IN_DELAY; + L0CFGVCID_indelay <= L0CFGVCID_ipd after IN_DELAY; + L0DLLHOLDLINKUP_indelay <= L0DLLHOLDLINKUP_ipd after IN_DELAY; + L0ELECTROMECHANICALINTERLOCKENGAGED_indelay <= L0ELECTROMECHANICALINTERLOCKENGAGED_ipd after IN_DELAY; + L0FWDASSERTINTALEGACYINT_indelay <= L0FWDASSERTINTALEGACYINT_ipd after IN_DELAY; + L0FWDASSERTINTBLEGACYINT_indelay <= L0FWDASSERTINTBLEGACYINT_ipd after IN_DELAY; + L0FWDASSERTINTCLEGACYINT_indelay <= L0FWDASSERTINTCLEGACYINT_ipd after IN_DELAY; + L0FWDASSERTINTDLEGACYINT_indelay <= L0FWDASSERTINTDLEGACYINT_ipd after IN_DELAY; + L0FWDCORRERRIN_indelay <= L0FWDCORRERRIN_ipd after IN_DELAY; + L0FWDDEASSERTINTALEGACYINT_indelay <= L0FWDDEASSERTINTALEGACYINT_ipd after IN_DELAY; + L0FWDDEASSERTINTBLEGACYINT_indelay <= L0FWDDEASSERTINTBLEGACYINT_ipd after IN_DELAY; + L0FWDDEASSERTINTCLEGACYINT_indelay <= L0FWDDEASSERTINTCLEGACYINT_ipd after IN_DELAY; + L0FWDDEASSERTINTDLEGACYINT_indelay <= L0FWDDEASSERTINTDLEGACYINT_ipd after IN_DELAY; + L0FWDFATALERRIN_indelay <= L0FWDFATALERRIN_ipd after IN_DELAY; + L0FWDNONFATALERRIN_indelay <= L0FWDNONFATALERRIN_ipd after IN_DELAY; + L0LEGACYINTFUNCT0_indelay <= L0LEGACYINTFUNCT0_ipd after IN_DELAY; + L0MRLSENSORCLOSEDN_indelay <= L0MRLSENSORCLOSEDN_ipd after IN_DELAY; + L0MSIREQUEST0_indelay <= L0MSIREQUEST0_ipd after IN_DELAY; + L0PACKETHEADERFROMUSER_indelay <= L0PACKETHEADERFROMUSER_ipd after IN_DELAY; + L0PMEREQIN_indelay <= L0PMEREQIN_ipd after IN_DELAY; + L0PORTNUMBER_indelay <= L0PORTNUMBER_ipd after IN_DELAY; + L0POWERFAULTDETECTED_indelay <= L0POWERFAULTDETECTED_ipd after IN_DELAY; + L0PRESENCEDETECTSLOTEMPTYN_indelay <= L0PRESENCEDETECTSLOTEMPTYN_ipd after IN_DELAY; + L0PWRNEWSTATEREQ_indelay <= L0PWRNEWSTATEREQ_ipd after IN_DELAY; + L0PWRNEXTLINKSTATE_indelay <= L0PWRNEXTLINKSTATE_ipd after IN_DELAY; + L0REPLAYTIMERADJUSTMENT_indelay <= L0REPLAYTIMERADJUSTMENT_ipd after IN_DELAY; + L0ROOTTURNOFFREQ_indelay <= L0ROOTTURNOFFREQ_ipd after IN_DELAY; + L0RXTLTLPNONINITIALIZEDVC_indelay <= L0RXTLTLPNONINITIALIZEDVC_ipd after IN_DELAY; + L0SENDUNLOCKMESSAGE_indelay <= L0SENDUNLOCKMESSAGE_ipd after IN_DELAY; + L0SETCOMPLETERABORTERROR_indelay <= L0SETCOMPLETERABORTERROR_ipd after IN_DELAY; + L0SETCOMPLETIONTIMEOUTCORRERROR_indelay <= L0SETCOMPLETIONTIMEOUTCORRERROR_ipd after IN_DELAY; + L0SETCOMPLETIONTIMEOUTUNCORRERROR_indelay <= L0SETCOMPLETIONTIMEOUTUNCORRERROR_ipd after IN_DELAY; + L0SETDETECTEDCORRERROR_indelay <= L0SETDETECTEDCORRERROR_ipd after IN_DELAY; + L0SETDETECTEDFATALERROR_indelay <= L0SETDETECTEDFATALERROR_ipd after IN_DELAY; + L0SETDETECTEDNONFATALERROR_indelay <= L0SETDETECTEDNONFATALERROR_ipd after IN_DELAY; + L0SETLINKDETECTEDPARITYERROR_indelay <= L0SETLINKDETECTEDPARITYERROR_ipd after IN_DELAY; + L0SETLINKMASTERDATAPARITY_indelay <= L0SETLINKMASTERDATAPARITY_ipd after IN_DELAY; + L0SETLINKRECEIVEDMASTERABORT_indelay <= L0SETLINKRECEIVEDMASTERABORT_ipd after IN_DELAY; + L0SETLINKRECEIVEDTARGETABORT_indelay <= L0SETLINKRECEIVEDTARGETABORT_ipd after IN_DELAY; + L0SETLINKSIGNALLEDTARGETABORT_indelay <= L0SETLINKSIGNALLEDTARGETABORT_ipd after IN_DELAY; + L0SETLINKSYSTEMERROR_indelay <= L0SETLINKSYSTEMERROR_ipd after IN_DELAY; + L0SETUNEXPECTEDCOMPLETIONCORRERROR_indelay <= L0SETUNEXPECTEDCOMPLETIONCORRERROR_ipd after IN_DELAY; + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_indelay <= L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_ipd after IN_DELAY; + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_indelay <= L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_ipd after IN_DELAY; + L0SETUNSUPPORTEDREQUESTOTHERERROR_indelay <= L0SETUNSUPPORTEDREQUESTOTHERERROR_ipd after IN_DELAY; + L0SETUSERDETECTEDPARITYERROR_indelay <= L0SETUSERDETECTEDPARITYERROR_ipd after IN_DELAY; + L0SETUSERMASTERDATAPARITY_indelay <= L0SETUSERMASTERDATAPARITY_ipd after IN_DELAY; + L0SETUSERRECEIVEDMASTERABORT_indelay <= L0SETUSERRECEIVEDMASTERABORT_ipd after IN_DELAY; + L0SETUSERRECEIVEDTARGETABORT_indelay <= L0SETUSERRECEIVEDTARGETABORT_ipd after IN_DELAY; + L0SETUSERSIGNALLEDTARGETABORT_indelay <= L0SETUSERSIGNALLEDTARGETABORT_ipd after IN_DELAY; + L0SETUSERSYSTEMERROR_indelay <= L0SETUSERSYSTEMERROR_ipd after IN_DELAY; + L0TLASFCCREDSTARVATION_indelay <= L0TLASFCCREDSTARVATION_ipd after IN_DELAY; + L0TLLINKRETRAIN_indelay <= L0TLLINKRETRAIN_ipd after IN_DELAY; + L0TRANSACTIONSPENDING_indelay <= L0TRANSACTIONSPENDING_ipd after IN_DELAY; + L0TXBEACON_indelay <= L0TXBEACON_ipd after IN_DELAY; + L0TXCFGPMTYPE_indelay <= L0TXCFGPMTYPE_ipd after IN_DELAY; + L0TXCFGPM_indelay <= L0TXCFGPM_ipd after IN_DELAY; + L0TXTLFCCMPLMCCRED_indelay <= L0TXTLFCCMPLMCCRED_ipd after IN_DELAY; + L0TXTLFCCMPLMCUPDATE_indelay <= L0TXTLFCCMPLMCUPDATE_ipd after IN_DELAY; + L0TXTLFCNPOSTBYPCRED_indelay <= L0TXTLFCNPOSTBYPCRED_ipd after IN_DELAY; + L0TXTLFCNPOSTBYPUPDATE_indelay <= L0TXTLFCNPOSTBYPUPDATE_ipd after IN_DELAY; + L0TXTLFCPOSTORDCRED_indelay <= L0TXTLFCPOSTORDCRED_ipd after IN_DELAY; + L0TXTLFCPOSTORDUPDATE_indelay <= L0TXTLFCPOSTORDUPDATE_ipd after IN_DELAY; + L0TXTLSBFCDATA_indelay <= L0TXTLSBFCDATA_ipd after IN_DELAY; + L0TXTLSBFCUPDATE_indelay <= L0TXTLSBFCUPDATE_ipd after IN_DELAY; + L0TXTLTLPDATA_indelay <= L0TXTLTLPDATA_ipd after IN_DELAY; + L0TXTLTLPEDB_indelay <= L0TXTLTLPEDB_ipd after IN_DELAY; + L0TXTLTLPENABLE_indelay <= L0TXTLTLPENABLE_ipd after IN_DELAY; + L0TXTLTLPEND_indelay <= L0TXTLTLPEND_ipd after IN_DELAY; + L0TXTLTLPLATENCY_indelay <= L0TXTLTLPLATENCY_ipd after IN_DELAY; + L0TXTLTLPREQEND_indelay <= L0TXTLTLPREQEND_ipd after IN_DELAY; + L0TXTLTLPREQ_indelay <= L0TXTLTLPREQ_ipd after IN_DELAY; + L0TXTLTLPWIDTH_indelay <= L0TXTLTLPWIDTH_ipd after IN_DELAY; + L0UPSTREAMRXPORTINL0S_indelay <= L0UPSTREAMRXPORTINL0S_ipd after IN_DELAY; + L0VC0PREVIEWEXPAND_indelay <= L0VC0PREVIEWEXPAND_ipd after IN_DELAY; + L0WAKEN_indelay <= L0WAKEN_ipd after IN_DELAY; + LLKRXCHFIFO_indelay <= LLKRXCHFIFO_ipd after IN_DELAY; + LLKRXCHTC_indelay <= LLKRXCHTC_ipd after IN_DELAY; + LLKRXDSTCONTREQN_indelay <= LLKRXDSTCONTREQN_ipd after IN_DELAY; + LLKRXDSTREQN_indelay <= LLKRXDSTREQN_ipd after IN_DELAY; + LLKTX4DWHEADERN_indelay <= LLKTX4DWHEADERN_ipd after IN_DELAY; + LLKTXCHFIFO_indelay <= LLKTXCHFIFO_ipd after IN_DELAY; + LLKTXCHTC_indelay <= LLKTXCHTC_ipd after IN_DELAY; + LLKTXCOMPLETEN_indelay <= LLKTXCOMPLETEN_ipd after IN_DELAY; + LLKTXCREATEECRCN_indelay <= LLKTXCREATEECRCN_ipd after IN_DELAY; + LLKTXDATA_indelay <= LLKTXDATA_ipd after IN_DELAY; + LLKTXENABLEN_indelay <= LLKTXENABLEN_ipd after IN_DELAY; + LLKTXEOFN_indelay <= LLKTXEOFN_ipd after IN_DELAY; + LLKTXEOPN_indelay <= LLKTXEOPN_ipd after IN_DELAY; + LLKTXSOFN_indelay <= LLKTXSOFN_ipd after IN_DELAY; + LLKTXSOPN_indelay <= LLKTXSOPN_ipd after IN_DELAY; + LLKTXSRCDSCN_indelay <= LLKTXSRCDSCN_ipd after IN_DELAY; + LLKTXSRCRDYN_indelay <= LLKTXSRCRDYN_ipd after IN_DELAY; + MAINPOWER_indelay <= MAINPOWER_ipd after IN_DELAY; + MGMTADDR_indelay <= MGMTADDR_ipd after IN_DELAY; + MGMTBWREN_indelay <= MGMTBWREN_ipd after IN_DELAY; + MGMTRDEN_indelay <= MGMTRDEN_ipd after IN_DELAY; + MGMTSTATSCREDITSEL_indelay <= MGMTSTATSCREDITSEL_ipd after IN_DELAY; + MGMTWDATA_indelay <= MGMTWDATA_ipd after IN_DELAY; + MGMTWREN_indelay <= MGMTWREN_ipd after IN_DELAY; + MIMDLLBRDATA_indelay <= MIMDLLBRDATA_ipd after IN_DELAY; + MIMRXBRDATA_indelay <= MIMRXBRDATA_ipd after IN_DELAY; + MIMTXBRDATA_indelay <= MIMTXBRDATA_ipd after IN_DELAY; + PIPEPHYSTATUSL0_indelay <= PIPEPHYSTATUSL0_ipd after IN_DELAY; + PIPEPHYSTATUSL1_indelay <= PIPEPHYSTATUSL1_ipd after IN_DELAY; + PIPEPHYSTATUSL2_indelay <= PIPEPHYSTATUSL2_ipd after IN_DELAY; + PIPEPHYSTATUSL3_indelay <= PIPEPHYSTATUSL3_ipd after IN_DELAY; + PIPEPHYSTATUSL4_indelay <= PIPEPHYSTATUSL4_ipd after IN_DELAY; + PIPEPHYSTATUSL5_indelay <= PIPEPHYSTATUSL5_ipd after IN_DELAY; + PIPEPHYSTATUSL6_indelay <= PIPEPHYSTATUSL6_ipd after IN_DELAY; + PIPEPHYSTATUSL7_indelay <= PIPEPHYSTATUSL7_ipd after IN_DELAY; + PIPERXCHANISALIGNEDL0_indelay <= PIPERXCHANISALIGNEDL0_ipd after IN_DELAY; + PIPERXCHANISALIGNEDL1_indelay <= PIPERXCHANISALIGNEDL1_ipd after IN_DELAY; + PIPERXCHANISALIGNEDL2_indelay <= PIPERXCHANISALIGNEDL2_ipd after IN_DELAY; + PIPERXCHANISALIGNEDL3_indelay <= PIPERXCHANISALIGNEDL3_ipd after IN_DELAY; + PIPERXCHANISALIGNEDL4_indelay <= PIPERXCHANISALIGNEDL4_ipd after IN_DELAY; + PIPERXCHANISALIGNEDL5_indelay <= PIPERXCHANISALIGNEDL5_ipd after IN_DELAY; + PIPERXCHANISALIGNEDL6_indelay <= PIPERXCHANISALIGNEDL6_ipd after IN_DELAY; + PIPERXCHANISALIGNEDL7_indelay <= PIPERXCHANISALIGNEDL7_ipd after IN_DELAY; + PIPERXDATAKL0_indelay <= PIPERXDATAKL0_ipd after IN_DELAY; + PIPERXDATAKL1_indelay <= PIPERXDATAKL1_ipd after IN_DELAY; + PIPERXDATAKL2_indelay <= PIPERXDATAKL2_ipd after IN_DELAY; + PIPERXDATAKL3_indelay <= PIPERXDATAKL3_ipd after IN_DELAY; + PIPERXDATAKL4_indelay <= PIPERXDATAKL4_ipd after IN_DELAY; + PIPERXDATAKL5_indelay <= PIPERXDATAKL5_ipd after IN_DELAY; + PIPERXDATAKL6_indelay <= PIPERXDATAKL6_ipd after IN_DELAY; + PIPERXDATAKL7_indelay <= PIPERXDATAKL7_ipd after IN_DELAY; + PIPERXDATAL0_indelay <= PIPERXDATAL0_ipd after IN_DELAY; + PIPERXDATAL1_indelay <= PIPERXDATAL1_ipd after IN_DELAY; + PIPERXDATAL2_indelay <= PIPERXDATAL2_ipd after IN_DELAY; + PIPERXDATAL3_indelay <= PIPERXDATAL3_ipd after IN_DELAY; + PIPERXDATAL4_indelay <= PIPERXDATAL4_ipd after IN_DELAY; + PIPERXDATAL5_indelay <= PIPERXDATAL5_ipd after IN_DELAY; + PIPERXDATAL6_indelay <= PIPERXDATAL6_ipd after IN_DELAY; + PIPERXDATAL7_indelay <= PIPERXDATAL7_ipd after IN_DELAY; + PIPERXELECIDLEL0_indelay <= PIPERXELECIDLEL0_ipd after IN_DELAY; + PIPERXELECIDLEL1_indelay <= PIPERXELECIDLEL1_ipd after IN_DELAY; + PIPERXELECIDLEL2_indelay <= PIPERXELECIDLEL2_ipd after IN_DELAY; + PIPERXELECIDLEL3_indelay <= PIPERXELECIDLEL3_ipd after IN_DELAY; + PIPERXELECIDLEL4_indelay <= PIPERXELECIDLEL4_ipd after IN_DELAY; + PIPERXELECIDLEL5_indelay <= PIPERXELECIDLEL5_ipd after IN_DELAY; + PIPERXELECIDLEL6_indelay <= PIPERXELECIDLEL6_ipd after IN_DELAY; + PIPERXELECIDLEL7_indelay <= PIPERXELECIDLEL7_ipd after IN_DELAY; + PIPERXSTATUSL0_indelay <= PIPERXSTATUSL0_ipd after IN_DELAY; + PIPERXSTATUSL1_indelay <= PIPERXSTATUSL1_ipd after IN_DELAY; + PIPERXSTATUSL2_indelay <= PIPERXSTATUSL2_ipd after IN_DELAY; + PIPERXSTATUSL3_indelay <= PIPERXSTATUSL3_ipd after IN_DELAY; + PIPERXSTATUSL4_indelay <= PIPERXSTATUSL4_ipd after IN_DELAY; + PIPERXSTATUSL5_indelay <= PIPERXSTATUSL5_ipd after IN_DELAY; + PIPERXSTATUSL6_indelay <= PIPERXSTATUSL6_ipd after IN_DELAY; + PIPERXSTATUSL7_indelay <= PIPERXSTATUSL7_ipd after IN_DELAY; + PIPERXVALIDL0_indelay <= PIPERXVALIDL0_ipd after IN_DELAY; + PIPERXVALIDL1_indelay <= PIPERXVALIDL1_ipd after IN_DELAY; + PIPERXVALIDL2_indelay <= PIPERXVALIDL2_ipd after IN_DELAY; + PIPERXVALIDL3_indelay <= PIPERXVALIDL3_ipd after IN_DELAY; + PIPERXVALIDL4_indelay <= PIPERXVALIDL4_ipd after IN_DELAY; + PIPERXVALIDL5_indelay <= PIPERXVALIDL5_ipd after IN_DELAY; + PIPERXVALIDL6_indelay <= PIPERXVALIDL6_ipd after IN_DELAY; + PIPERXVALIDL7_indelay <= PIPERXVALIDL7_ipd after IN_DELAY; + + + pcie_internal_1_1_swift_bw_1 : PCIE_INTERNAL_1_1_SWIFT_BUS + port map ( + MCACTIVELANESIN => ACTIVELANESIN_BINARY, + MCAERBASEPTR => AERBASEPTR_BINARY, + MCAERCAPABILITYECRCCHECKCAPABLE => AERCAPABILITYECRCCHECKCAPABLE_BINARY, + MCAERCAPABILITYECRCGENCAPABLE => AERCAPABILITYECRCGENCAPABLE_BINARY, + MCAERCAPABILITYNEXTPTR => AERCAPABILITYNEXTPTR_BINARY, + MCBAR0ADDRWIDTH => BAR0ADDRWIDTH_BINARY, + MCBAR0EXIST => BAR0EXIST_BINARY, + MCBAR0IOMEMN => BAR0IOMEMN_BINARY, + MCBAR0MASKWIDTH => BAR0MASKWIDTH_BINARY, + MCBAR0PREFETCHABLE => BAR0PREFETCHABLE_BINARY, + MCBAR1ADDRWIDTH => BAR1ADDRWIDTH_BINARY, + MCBAR1EXIST => BAR1EXIST_BINARY, + MCBAR1IOMEMN => BAR1IOMEMN_BINARY, + MCBAR1MASKWIDTH => BAR1MASKWIDTH_BINARY, + MCBAR1PREFETCHABLE => BAR1PREFETCHABLE_BINARY, + MCBAR2ADDRWIDTH => BAR2ADDRWIDTH_BINARY, + MCBAR2EXIST => BAR2EXIST_BINARY, + MCBAR2IOMEMN => BAR2IOMEMN_BINARY, + MCBAR2MASKWIDTH => BAR2MASKWIDTH_BINARY, + MCBAR2PREFETCHABLE => BAR2PREFETCHABLE_BINARY, + MCBAR3ADDRWIDTH => BAR3ADDRWIDTH_BINARY, + MCBAR3EXIST => BAR3EXIST_BINARY, + MCBAR3IOMEMN => BAR3IOMEMN_BINARY, + MCBAR3MASKWIDTH => BAR3MASKWIDTH_BINARY, + MCBAR3PREFETCHABLE => BAR3PREFETCHABLE_BINARY, + MCBAR4ADDRWIDTH => BAR4ADDRWIDTH_BINARY, + MCBAR4EXIST => BAR4EXIST_BINARY, + MCBAR4IOMEMN => BAR4IOMEMN_BINARY, + MCBAR4MASKWIDTH => BAR4MASKWIDTH_BINARY, + MCBAR4PREFETCHABLE => BAR4PREFETCHABLE_BINARY, + MCBAR5ADDRWIDTH => BAR5ADDRWIDTH_BINARY, + MCBAR5EXIST => BAR5EXIST_BINARY, + MCBAR5IOMEMN => BAR5IOMEMN_BINARY, + MCBAR5MASKWIDTH => BAR5MASKWIDTH_BINARY, + MCBAR5PREFETCHABLE => BAR5PREFETCHABLE_BINARY, + MCCAPABILITIESPOINTER => CAPABILITIESPOINTER_BINARY, + MCCARDBUSCISPOINTER => CARDBUSCISPOINTER_BINARY, + MCCLASSCODE => CLASSCODE_BINARY, +-- MCCLKDIVIDED => CLKDIVIDED_BINARY, + MCCONFIGROUTING => CONFIGROUTING_BINARY, + MCDEVICECAPABILITYENDPOINTL0SLATENCY => DEVICECAPABILITYENDPOINTL0SLATENCY_BINARY, + MCDEVICECAPABILITYENDPOINTL1LATENCY => DEVICECAPABILITYENDPOINTL1LATENCY_BINARY, + MCDEVICEID => DEVICEID_BINARY, + MCDEVICESERIALNUMBER => DEVICESERIALNUMBER_BINARY, + MCDSNBASEPTR => DSNBASEPTR_BINARY, + MCDSNCAPABILITYNEXTPTR => DSNCAPABILITYNEXTPTR_BINARY, + MCDUALCOREENABLE => DUALCOREENABLE_BINARY, + MCDUALCORESLAVE => DUALCORESLAVE_BINARY, + MCDUALROLECFGCNTRLROOTEPN => DUALROLECFGCNTRLROOTEPN_BINARY, + MCEXTCFGCAPPTR => EXTCFGCAPPTR_BINARY, + MCEXTCFGXPCAPPTR => EXTCFGXPCAPPTR_BINARY, + MCHEADERTYPE => HEADERTYPE_BINARY, + MCINFINITECOMPLETIONS => INFINITECOMPLETIONS_BINARY, + MCINTERRUPTPIN => INTERRUPTPIN_BINARY, + MCISSWITCH => ISSWITCH_BINARY, + MCL0SEXITLATENCY => L0SEXITLATENCY_BINARY, + MCL0SEXITLATENCYCOMCLK => L0SEXITLATENCYCOMCLK_BINARY, + MCL1EXITLATENCY => L1EXITLATENCY_BINARY, + MCL1EXITLATENCYCOMCLK => L1EXITLATENCYCOMCLK_BINARY, + MCLINKCAPABILITYASPMSUPPORT => LINKCAPABILITYASPMSUPPORT_BINARY, + MCLINKCAPABILITYMAXLINKWIDTH => LINKCAPABILITYMAXLINKWIDTH_BINARY, + MCLINKSTATUSSLOTCLOCKCONFIG => LINKSTATUSSLOTCLOCKCONFIG_BINARY, + MCLLKBYPASS => LLKBYPASS_BINARY, + MCLOWPRIORITYVCCOUNT => LOWPRIORITYVCCOUNT_BINARY, + MCMSIBASEPTR => MSIBASEPTR_BINARY, + MCMSICAPABILITYMULTIMSGCAP => MSICAPABILITYMULTIMSGCAP_BINARY, + MCMSICAPABILITYNEXTPTR => MSICAPABILITYNEXTPTR_BINARY, + MCPBBASEPTR => PBBASEPTR_BINARY, + MCPBCAPABILITYDW0BASEPOWER => PBCAPABILITYDW0BASEPOWER_BINARY, + MCPBCAPABILITYDW0DATASCALE => PBCAPABILITYDW0DATASCALE_BINARY, + MCPBCAPABILITYDW0PMSTATE => PBCAPABILITYDW0PMSTATE_BINARY, + MCPBCAPABILITYDW0PMSUBSTATE => PBCAPABILITYDW0PMSUBSTATE_BINARY, + MCPBCAPABILITYDW0POWERRAIL => PBCAPABILITYDW0POWERRAIL_BINARY, + MCPBCAPABILITYDW0TYPE => PBCAPABILITYDW0TYPE_BINARY, + MCPBCAPABILITYDW1BASEPOWER => PBCAPABILITYDW1BASEPOWER_BINARY, + MCPBCAPABILITYDW1DATASCALE => PBCAPABILITYDW1DATASCALE_BINARY, + MCPBCAPABILITYDW1PMSTATE => PBCAPABILITYDW1PMSTATE_BINARY, + MCPBCAPABILITYDW1PMSUBSTATE => PBCAPABILITYDW1PMSUBSTATE_BINARY, + MCPBCAPABILITYDW1POWERRAIL => PBCAPABILITYDW1POWERRAIL_BINARY, + MCPBCAPABILITYDW1TYPE => PBCAPABILITYDW1TYPE_BINARY, + MCPBCAPABILITYDW2BASEPOWER => PBCAPABILITYDW2BASEPOWER_BINARY, + MCPBCAPABILITYDW2DATASCALE => PBCAPABILITYDW2DATASCALE_BINARY, + MCPBCAPABILITYDW2PMSTATE => PBCAPABILITYDW2PMSTATE_BINARY, + MCPBCAPABILITYDW2PMSUBSTATE => PBCAPABILITYDW2PMSUBSTATE_BINARY, + MCPBCAPABILITYDW2POWERRAIL => PBCAPABILITYDW2POWERRAIL_BINARY, + MCPBCAPABILITYDW2TYPE => PBCAPABILITYDW2TYPE_BINARY, + MCPBCAPABILITYDW3BASEPOWER => PBCAPABILITYDW3BASEPOWER_BINARY, + MCPBCAPABILITYDW3DATASCALE => PBCAPABILITYDW3DATASCALE_BINARY, + MCPBCAPABILITYDW3PMSTATE => PBCAPABILITYDW3PMSTATE_BINARY, + MCPBCAPABILITYDW3PMSUBSTATE => PBCAPABILITYDW3PMSUBSTATE_BINARY, + MCPBCAPABILITYDW3POWERRAIL => PBCAPABILITYDW3POWERRAIL_BINARY, + MCPBCAPABILITYDW3TYPE => PBCAPABILITYDW3TYPE_BINARY, + MCPBCAPABILITYNEXTPTR => PBCAPABILITYNEXTPTR_BINARY, + MCPBCAPABILITYSYSTEMALLOCATED => PBCAPABILITYSYSTEMALLOCATED_BINARY, + MCPCIECAPABILITYINTMSGNUM => PCIECAPABILITYINTMSGNUM_BINARY, + MCPCIECAPABILITYNEXTPTR => PCIECAPABILITYNEXTPTR_BINARY, + MCPCIECAPABILITYSLOTIMPL => PCIECAPABILITYSLOTIMPL_BINARY, + MCPCIEREVISION => PCIEREVISION_BINARY, + MCPMBASEPTR => PMBASEPTR_BINARY, + MCPMCAPABILITYAUXCURRENT => PMCAPABILITYAUXCURRENT_BINARY, + MCPMCAPABILITYD1SUPPORT => PMCAPABILITYD1SUPPORT_BINARY, + MCPMCAPABILITYD2SUPPORT => PMCAPABILITYD2SUPPORT_BINARY, + MCPMCAPABILITYDSI => PMCAPABILITYDSI_BINARY, + MCPMCAPABILITYNEXTPTR => PMCAPABILITYNEXTPTR_BINARY, + MCPMCAPABILITYPMESUPPORT => PMCAPABILITYPMESUPPORT_BINARY, + MCPMDATA0 => PMDATA0_BINARY, + MCPMDATA1 => PMDATA1_BINARY, + MCPMDATA2 => PMDATA2_BINARY, + MCPMDATA3 => PMDATA3_BINARY, + MCPMDATA4 => PMDATA4_BINARY, + MCPMDATA5 => PMDATA5_BINARY, + MCPMDATA6 => PMDATA6_BINARY, + MCPMDATA7 => PMDATA7_BINARY, + MCPMDATA8 => PMDATA8_BINARY, + MCPMDATASCALE0 => PMDATASCALE0_BINARY, + MCPMDATASCALE1 => PMDATASCALE1_BINARY, + MCPMDATASCALE2 => PMDATASCALE2_BINARY, + MCPMDATASCALE3 => PMDATASCALE3_BINARY, + MCPMDATASCALE4 => PMDATASCALE4_BINARY, + MCPMDATASCALE5 => PMDATASCALE5_BINARY, + MCPMDATASCALE6 => PMDATASCALE6_BINARY, + MCPMDATASCALE7 => PMDATASCALE7_BINARY, + MCPMDATASCALE8 => PMDATASCALE8_BINARY, + MCPMSTATUSCONTROLDATASCALE => PMSTATUSCONTROLDATASCALE_BINARY, + MCPORTVCCAPABILITYEXTENDEDVCCOUNT => PORTVCCAPABILITYEXTENDEDVCCOUNT_BINARY, + MCPORTVCCAPABILITYVCARBCAP => PORTVCCAPABILITYVCARBCAP_BINARY, + MCPORTVCCAPABILITYVCARBTABLEOFFSET => PORTVCCAPABILITYVCARBTABLEOFFSET_BINARY, + MCRAMSHARETXRX => RAMSHARETXRX_BINARY, + MCRESETMODE => RESETMODE_BINARY, + MCRETRYRAMREADLATENCY => RETRYRAMREADLATENCY_BINARY, + MCRETRYRAMSIZE => RETRYRAMSIZE_BINARY, + MCRETRYRAMWIDTH => RETRYRAMWIDTH_BINARY, + MCRETRYRAMWRITELATENCY => RETRYRAMWRITELATENCY_BINARY, + MCRETRYREADADDRPIPE => RETRYREADADDRPIPE_BINARY, + MCRETRYREADDATAPIPE => RETRYREADDATAPIPE_BINARY, + MCRETRYWRITEPIPE => RETRYWRITEPIPE_BINARY, + MCREVISIONID => REVISIONID_BINARY, + MCRXREADADDRPIPE => RXREADADDRPIPE_BINARY, + MCRXREADDATAPIPE => RXREADDATAPIPE_BINARY, + MCRXWRITEPIPE => RXWRITEPIPE_BINARY, + MCSELECTASMODE => SELECTASMODE_BINARY, + MCSELECTDLLIF => SELECTDLLIF_BINARY, + MCSLOTCAPABILITYATTBUTTONPRESENT => SLOTCAPABILITYATTBUTTONPRESENT_BINARY, + MCSLOTCAPABILITYATTINDICATORPRESENT => SLOTCAPABILITYATTINDICATORPRESENT_BINARY, + MCSLOTCAPABILITYHOTPLUGCAPABLE => SLOTCAPABILITYHOTPLUGCAPABLE_BINARY, + MCSLOTCAPABILITYHOTPLUGSURPRISE => SLOTCAPABILITYHOTPLUGSURPRISE_BINARY, + MCSLOTCAPABILITYMSLSENSORPRESENT => SLOTCAPABILITYMSLSENSORPRESENT_BINARY, + MCSLOTCAPABILITYPHYSICALSLOTNUM => SLOTCAPABILITYPHYSICALSLOTNUM_BINARY, + MCSLOTCAPABILITYPOWERCONTROLLERPRESENT => SLOTCAPABILITYPOWERCONTROLLERPRESENT_BINARY, + MCSLOTCAPABILITYPOWERINDICATORPRESENT => SLOTCAPABILITYPOWERINDICATORPRESENT_BINARY, + MCSLOTCAPABILITYSLOTPOWERLIMITSCALE => SLOTCAPABILITYSLOTPOWERLIMITSCALE_BINARY, + MCSLOTCAPABILITYSLOTPOWERLIMITVALUE => SLOTCAPABILITYSLOTPOWERLIMITVALUE_BINARY, + MCSLOTIMPLEMENTED => SLOTIMPLEMENTED_BINARY, + MCSUBSYSTEMID => SUBSYSTEMID_BINARY, + MCSUBSYSTEMVENDORID => SUBSYSTEMVENDORID_BINARY, + MCTLRAMREADLATENCY => TLRAMREADLATENCY_BINARY, + MCTLRAMWIDTH => TLRAMWIDTH_BINARY, + MCTLRAMWRITELATENCY => TLRAMWRITELATENCY_BINARY, + MCTXREADADDRPIPE => TXREADADDRPIPE_BINARY, + MCTXREADDATAPIPE => TXREADDATAPIPE_BINARY, + MCTXTSNFTS => TXTSNFTS_BINARY, + MCTXTSNFTSCOMCLK => TXTSNFTSCOMCLK_BINARY, + MCTXWRITEPIPE => TXWRITEPIPE_BINARY, + MCUPSTREAMFACING => UPSTREAMFACING_BINARY, + MCVC0RXFIFOBASEC => VC0RXFIFOBASEC_BINARY, + MCVC0RXFIFOBASENP => VC0RXFIFOBASENP_BINARY, + MCVC0RXFIFOBASEP => VC0RXFIFOBASEP_BINARY, + MCVC0RXFIFOLIMITC => VC0RXFIFOLIMITC_BINARY, + MCVC0RXFIFOLIMITNP => VC0RXFIFOLIMITNP_BINARY, + MCVC0RXFIFOLIMITP => VC0RXFIFOLIMITP_BINARY, + MCVC0TOTALCREDITSCD => VC0TOTALCREDITSCD_BINARY, + MCVC0TOTALCREDITSCH => VC0TOTALCREDITSCH_BINARY, + MCVC0TOTALCREDITSNPH => VC0TOTALCREDITSNPH_BINARY, + MCVC0TOTALCREDITSPD => VC0TOTALCREDITSPD_BINARY, + MCVC0TOTALCREDITSPH => VC0TOTALCREDITSPH_BINARY, + MCVC0TXFIFOBASEC => VC0TXFIFOBASEC_BINARY, + MCVC0TXFIFOBASENP => VC0TXFIFOBASENP_BINARY, + MCVC0TXFIFOBASEP => VC0TXFIFOBASEP_BINARY, + MCVC0TXFIFOLIMITC => VC0TXFIFOLIMITC_BINARY, + MCVC0TXFIFOLIMITNP => VC0TXFIFOLIMITNP_BINARY, + MCVC0TXFIFOLIMITP => VC0TXFIFOLIMITP_BINARY, + MCVC1RXFIFOBASEC => VC1RXFIFOBASEC_BINARY, + MCVC1RXFIFOBASENP => VC1RXFIFOBASENP_BINARY, + MCVC1RXFIFOBASEP => VC1RXFIFOBASEP_BINARY, + MCVC1RXFIFOLIMITC => VC1RXFIFOLIMITC_BINARY, + MCVC1RXFIFOLIMITNP => VC1RXFIFOLIMITNP_BINARY, + MCVC1RXFIFOLIMITP => VC1RXFIFOLIMITP_BINARY, + MCVC1TOTALCREDITSCD => VC1TOTALCREDITSCD_BINARY, + MCVC1TOTALCREDITSCH => VC1TOTALCREDITSCH_BINARY, + MCVC1TOTALCREDITSNPH => VC1TOTALCREDITSNPH_BINARY, + MCVC1TOTALCREDITSPD => VC1TOTALCREDITSPD_BINARY, + MCVC1TOTALCREDITSPH => VC1TOTALCREDITSPH_BINARY, + MCVC1TXFIFOBASEC => VC1TXFIFOBASEC_BINARY, + MCVC1TXFIFOBASENP => VC1TXFIFOBASENP_BINARY, + MCVC1TXFIFOBASEP => VC1TXFIFOBASEP_BINARY, + MCVC1TXFIFOLIMITC => VC1TXFIFOLIMITC_BINARY, + MCVC1TXFIFOLIMITNP => VC1TXFIFOLIMITNP_BINARY, + MCVC1TXFIFOLIMITP => VC1TXFIFOLIMITP_BINARY, + MCVCBASEPTR => VCBASEPTR_BINARY, + MCVCCAPABILITYNEXTPTR => VCCAPABILITYNEXTPTR_BINARY, + MCVENDORID => VENDORID_BINARY, + MCXLINKSUPPORTED => XLINKSUPPORTED_BINARY, + MCXPBASEPTR => XPBASEPTR_BINARY, + MCXPDEVICEPORTTYPE => XPDEVICEPORTTYPE_BINARY, + MCXPMAXPAYLOAD => XPMAXPAYLOAD_BINARY, + MCXPRCBCONTROL => XPRCBCONTROL_BINARY, + + BUSMASTERENABLE => BUSMASTERENABLE_outdelay, + CRMDOHOTRESETN => CRMDOHOTRESETN_outdelay, + CRMPWRSOFTRESETN => CRMPWRSOFTRESETN_outdelay, + CRMRXHOTRESETN => CRMRXHOTRESETN_outdelay, + DLLTXPMDLLPOUTSTANDING => DLLTXPMDLLPOUTSTANDING_outdelay, + INTERRUPTDISABLE => INTERRUPTDISABLE_outdelay, + IOSPACEENABLE => IOSPACEENABLE_outdelay, + L0ASAUTONOMOUSINITCOMPLETED => L0ASAUTONOMOUSINITCOMPLETED_outdelay, + L0ATTENTIONINDICATORCONTROL => L0ATTENTIONINDICATORCONTROL_outdelay, + L0CFGLOOPBACKACK => L0CFGLOOPBACKACK_outdelay, + L0COMPLETERID => L0COMPLETERID_outdelay, + L0CORRERRMSGRCVD => L0CORRERRMSGRCVD_outdelay, + L0DLLASRXSTATE => L0DLLASRXSTATE_outdelay, + L0DLLASTXSTATE => L0DLLASTXSTATE_outdelay, + L0DLLERRORVECTOR => L0DLLERRORVECTOR_outdelay, + L0DLLRXACKOUTSTANDING => L0DLLRXACKOUTSTANDING_outdelay, + L0DLLTXNONFCOUTSTANDING => L0DLLTXNONFCOUTSTANDING_outdelay, + L0DLLTXOUTSTANDING => L0DLLTXOUTSTANDING_outdelay, + L0DLLVCSTATUS => L0DLLVCSTATUS_outdelay, + L0DLUPDOWN => L0DLUPDOWN_outdelay, + L0ERRMSGREQID => L0ERRMSGREQID_outdelay, + L0FATALERRMSGRCVD => L0FATALERRMSGRCVD_outdelay, + L0FIRSTCFGWRITEOCCURRED => L0FIRSTCFGWRITEOCCURRED_outdelay, + L0FWDCORRERROUT => L0FWDCORRERROUT_outdelay, + L0FWDFATALERROUT => L0FWDFATALERROUT_outdelay, + L0FWDNONFATALERROUT => L0FWDNONFATALERROUT_outdelay, + L0LTSSMSTATE => L0LTSSMSTATE_outdelay, + L0MACENTEREDL0 => L0MACENTEREDL0_outdelay, + L0MACLINKTRAINING => L0MACLINKTRAINING_outdelay, + L0MACLINKUP => L0MACLINKUP_outdelay, + L0MACNEGOTIATEDLINKWIDTH => L0MACNEGOTIATEDLINKWIDTH_outdelay, + L0MACNEWSTATEACK => L0MACNEWSTATEACK_outdelay, + L0MACRXL0SSTATE => L0MACRXL0SSTATE_outdelay, + L0MACUPSTREAMDOWNSTREAM => L0MACUPSTREAMDOWNSTREAM_outdelay, + L0MCFOUND => L0MCFOUND_outdelay, + L0MSIENABLE0 => L0MSIENABLE0_outdelay, + L0MULTIMSGEN0 => L0MULTIMSGEN0_outdelay, + L0NONFATALERRMSGRCVD => L0NONFATALERRMSGRCVD_outdelay, + L0PMEACK => L0PMEACK_outdelay, + L0PMEEN => L0PMEEN_outdelay, + L0PMEREQOUT => L0PMEREQOUT_outdelay, + L0POWERCONTROLLERCONTROL => L0POWERCONTROLLERCONTROL_outdelay, + L0POWERINDICATORCONTROL => L0POWERINDICATORCONTROL_outdelay, + L0PWRINHIBITTRANSFERS => L0PWRINHIBITTRANSFERS_outdelay, + L0PWRL1STATE => L0PWRL1STATE_outdelay, + L0PWRL23READYDEVICE => L0PWRL23READYDEVICE_outdelay, + L0PWRL23READYSTATE => L0PWRL23READYSTATE_outdelay, + L0PWRSTATE0 => L0PWRSTATE0_outdelay, + L0PWRTURNOFFREQ => L0PWRTURNOFFREQ_outdelay, + L0PWRTXL0SSTATE => L0PWRTXL0SSTATE_outdelay, + L0RECEIVEDASSERTINTALEGACYINT => L0RECEIVEDASSERTINTALEGACYINT_outdelay, + L0RECEIVEDASSERTINTBLEGACYINT => L0RECEIVEDASSERTINTBLEGACYINT_outdelay, + L0RECEIVEDASSERTINTCLEGACYINT => L0RECEIVEDASSERTINTCLEGACYINT_outdelay, + L0RECEIVEDASSERTINTDLEGACYINT => L0RECEIVEDASSERTINTDLEGACYINT_outdelay, + L0RECEIVEDDEASSERTINTALEGACYINT => L0RECEIVEDDEASSERTINTALEGACYINT_outdelay, + L0RECEIVEDDEASSERTINTBLEGACYINT => L0RECEIVEDDEASSERTINTBLEGACYINT_outdelay, + L0RECEIVEDDEASSERTINTCLEGACYINT => L0RECEIVEDDEASSERTINTCLEGACYINT_outdelay, + L0RECEIVEDDEASSERTINTDLEGACYINT => L0RECEIVEDDEASSERTINTDLEGACYINT_outdelay, + L0RXBEACON => L0RXBEACON_outdelay, + L0RXDLLFCCMPLMCCRED => L0RXDLLFCCMPLMCCRED_outdelay, + L0RXDLLFCCMPLMCUPDATE => L0RXDLLFCCMPLMCUPDATE_outdelay, + L0RXDLLFCNPOSTBYPCRED => L0RXDLLFCNPOSTBYPCRED_outdelay, + L0RXDLLFCNPOSTBYPUPDATE => L0RXDLLFCNPOSTBYPUPDATE_outdelay, + L0RXDLLFCPOSTORDCRED => L0RXDLLFCPOSTORDCRED_outdelay, + L0RXDLLFCPOSTORDUPDATE => L0RXDLLFCPOSTORDUPDATE_outdelay, + L0RXDLLPM => L0RXDLLPM_outdelay, + L0RXDLLPMTYPE => L0RXDLLPMTYPE_outdelay, + L0RXDLLSBFCDATA => L0RXDLLSBFCDATA_outdelay, + L0RXDLLSBFCUPDATE => L0RXDLLSBFCUPDATE_outdelay, + L0RXDLLTLPECRCOK => L0RXDLLTLPECRCOK_outdelay, + L0RXDLLTLPEND => L0RXDLLTLPEND_outdelay, + L0RXMACLINKERROR => L0RXMACLINKERROR_outdelay, + L0STATSCFGOTHERRECEIVED => L0STATSCFGOTHERRECEIVED_outdelay, + L0STATSCFGOTHERTRANSMITTED => L0STATSCFGOTHERTRANSMITTED_outdelay, + L0STATSCFGRECEIVED => L0STATSCFGRECEIVED_outdelay, + L0STATSCFGTRANSMITTED => L0STATSCFGTRANSMITTED_outdelay, + L0STATSDLLPRECEIVED => L0STATSDLLPRECEIVED_outdelay, + L0STATSDLLPTRANSMITTED => L0STATSDLLPTRANSMITTED_outdelay, + L0STATSOSRECEIVED => L0STATSOSRECEIVED_outdelay, + L0STATSOSTRANSMITTED => L0STATSOSTRANSMITTED_outdelay, + L0STATSTLPRECEIVED => L0STATSTLPRECEIVED_outdelay, + L0STATSTLPTRANSMITTED => L0STATSTLPTRANSMITTED_outdelay, + L0TOGGLEELECTROMECHANICALINTERLOCK => L0TOGGLEELECTROMECHANICALINTERLOCK_outdelay, + L0TRANSFORMEDVC => L0TRANSFORMEDVC_outdelay, + L0TXDLLFCCMPLMCUPDATED => L0TXDLLFCCMPLMCUPDATED_outdelay, + L0TXDLLFCNPOSTBYPUPDATED => L0TXDLLFCNPOSTBYPUPDATED_outdelay, + L0TXDLLFCPOSTORDUPDATED => L0TXDLLFCPOSTORDUPDATED_outdelay, + L0TXDLLPMUPDATED => L0TXDLLPMUPDATED_outdelay, + L0TXDLLSBFCUPDATED => L0TXDLLSBFCUPDATED_outdelay, + L0UCBYPFOUND => L0UCBYPFOUND_outdelay, + L0UCORDFOUND => L0UCORDFOUND_outdelay, + L0UNLOCKRECEIVED => L0UNLOCKRECEIVED_outdelay, + LLKRX4DWHEADERN => LLKRX4DWHEADERN_outdelay, + LLKRXCHCOMPLETIONAVAILABLEN => LLKRXCHCOMPLETIONAVAILABLEN_outdelay, + LLKRXCHCOMPLETIONPARTIALN => LLKRXCHCOMPLETIONPARTIALN_outdelay, + LLKRXCHCONFIGAVAILABLEN => LLKRXCHCONFIGAVAILABLEN_outdelay, + LLKRXCHCONFIGPARTIALN => LLKRXCHCONFIGPARTIALN_outdelay, + LLKRXCHNONPOSTEDAVAILABLEN => LLKRXCHNONPOSTEDAVAILABLEN_outdelay, + LLKRXCHNONPOSTEDPARTIALN => LLKRXCHNONPOSTEDPARTIALN_outdelay, + LLKRXCHPOSTEDAVAILABLEN => LLKRXCHPOSTEDAVAILABLEN_outdelay, + LLKRXCHPOSTEDPARTIALN => LLKRXCHPOSTEDPARTIALN_outdelay, + LLKRXDATA => LLKRXDATA_outdelay, + LLKRXECRCBADN => LLKRXECRCBADN_outdelay, + LLKRXEOFN => LLKRXEOFN_outdelay, + LLKRXEOPN => LLKRXEOPN_outdelay, + LLKRXPREFERREDTYPE => LLKRXPREFERREDTYPE_outdelay, + LLKRXSOFN => LLKRXSOFN_outdelay, + LLKRXSOPN => LLKRXSOPN_outdelay, + LLKRXSRCDSCN => LLKRXSRCDSCN_outdelay, + LLKRXSRCLASTREQN => LLKRXSRCLASTREQN_outdelay, + LLKRXSRCRDYN => LLKRXSRCRDYN_outdelay, + LLKRXVALIDN => LLKRXVALIDN_outdelay, + LLKTCSTATUS => LLKTCSTATUS_outdelay, + LLKTXCHANSPACE => LLKTXCHANSPACE_outdelay, + LLKTXCHCOMPLETIONREADYN => LLKTXCHCOMPLETIONREADYN_outdelay, + LLKTXCHNONPOSTEDREADYN => LLKTXCHNONPOSTEDREADYN_outdelay, + LLKTXCHPOSTEDREADYN => LLKTXCHPOSTEDREADYN_outdelay, + LLKTXCONFIGREADYN => LLKTXCONFIGREADYN_outdelay, + LLKTXDSTRDYN => LLKTXDSTRDYN_outdelay, + MAXPAYLOADSIZE => MAXPAYLOADSIZE_outdelay, + MAXREADREQUESTSIZE => MAXREADREQUESTSIZE_outdelay, + MEMSPACEENABLE => MEMSPACEENABLE_outdelay, + MGMTPSO => MGMTPSO_outdelay, + MGMTRDATA => MGMTRDATA_outdelay, + MGMTSTATSCREDIT => MGMTSTATSCREDIT_outdelay, + MIMDLLBRADD => MIMDLLBRADD_outdelay, + MIMDLLBREN => MIMDLLBREN_outdelay, + MIMDLLBWADD => MIMDLLBWADD_outdelay, + MIMDLLBWDATA => MIMDLLBWDATA_outdelay, + MIMDLLBWEN => MIMDLLBWEN_outdelay, + MIMRXBRADD => MIMRXBRADD_outdelay, + MIMRXBREN => MIMRXBREN_outdelay, + MIMRXBWADD => MIMRXBWADD_outdelay, + MIMRXBWDATA => MIMRXBWDATA_outdelay, + MIMRXBWEN => MIMRXBWEN_outdelay, + MIMTXBRADD => MIMTXBRADD_outdelay, + MIMTXBREN => MIMTXBREN_outdelay, + MIMTXBWADD => MIMTXBWADD_outdelay, + MIMTXBWDATA => MIMTXBWDATA_outdelay, + MIMTXBWEN => MIMTXBWEN_outdelay, + PARITYERRORRESPONSE => PARITYERRORRESPONSE_outdelay, + PIPEDESKEWLANESL0 => PIPEDESKEWLANESL0_outdelay, + PIPEDESKEWLANESL1 => PIPEDESKEWLANESL1_outdelay, + PIPEDESKEWLANESL2 => PIPEDESKEWLANESL2_outdelay, + PIPEDESKEWLANESL3 => PIPEDESKEWLANESL3_outdelay, + PIPEDESKEWLANESL4 => PIPEDESKEWLANESL4_outdelay, + PIPEDESKEWLANESL5 => PIPEDESKEWLANESL5_outdelay, + PIPEDESKEWLANESL6 => PIPEDESKEWLANESL6_outdelay, + PIPEDESKEWLANESL7 => PIPEDESKEWLANESL7_outdelay, + PIPEPOWERDOWNL0 => PIPEPOWERDOWNL0_outdelay, + PIPEPOWERDOWNL1 => PIPEPOWERDOWNL1_outdelay, + PIPEPOWERDOWNL2 => PIPEPOWERDOWNL2_outdelay, + PIPEPOWERDOWNL3 => PIPEPOWERDOWNL3_outdelay, + PIPEPOWERDOWNL4 => PIPEPOWERDOWNL4_outdelay, + PIPEPOWERDOWNL5 => PIPEPOWERDOWNL5_outdelay, + PIPEPOWERDOWNL6 => PIPEPOWERDOWNL6_outdelay, + PIPEPOWERDOWNL7 => PIPEPOWERDOWNL7_outdelay, + PIPERESETL0 => PIPERESETL0_outdelay, + PIPERESETL1 => PIPERESETL1_outdelay, + PIPERESETL2 => PIPERESETL2_outdelay, + PIPERESETL3 => PIPERESETL3_outdelay, + PIPERESETL4 => PIPERESETL4_outdelay, + PIPERESETL5 => PIPERESETL5_outdelay, + PIPERESETL6 => PIPERESETL6_outdelay, + PIPERESETL7 => PIPERESETL7_outdelay, + PIPERXPOLARITYL0 => PIPERXPOLARITYL0_outdelay, + PIPERXPOLARITYL1 => PIPERXPOLARITYL1_outdelay, + PIPERXPOLARITYL2 => PIPERXPOLARITYL2_outdelay, + PIPERXPOLARITYL3 => PIPERXPOLARITYL3_outdelay, + PIPERXPOLARITYL4 => PIPERXPOLARITYL4_outdelay, + PIPERXPOLARITYL5 => PIPERXPOLARITYL5_outdelay, + PIPERXPOLARITYL6 => PIPERXPOLARITYL6_outdelay, + PIPERXPOLARITYL7 => PIPERXPOLARITYL7_outdelay, + PIPETXCOMPLIANCEL0 => PIPETXCOMPLIANCEL0_outdelay, + PIPETXCOMPLIANCEL1 => PIPETXCOMPLIANCEL1_outdelay, + PIPETXCOMPLIANCEL2 => PIPETXCOMPLIANCEL2_outdelay, + PIPETXCOMPLIANCEL3 => PIPETXCOMPLIANCEL3_outdelay, + PIPETXCOMPLIANCEL4 => PIPETXCOMPLIANCEL4_outdelay, + PIPETXCOMPLIANCEL5 => PIPETXCOMPLIANCEL5_outdelay, + PIPETXCOMPLIANCEL6 => PIPETXCOMPLIANCEL6_outdelay, + PIPETXCOMPLIANCEL7 => PIPETXCOMPLIANCEL7_outdelay, + PIPETXDATAKL0 => PIPETXDATAKL0_outdelay, + PIPETXDATAKL1 => PIPETXDATAKL1_outdelay, + PIPETXDATAKL2 => PIPETXDATAKL2_outdelay, + PIPETXDATAKL3 => PIPETXDATAKL3_outdelay, + PIPETXDATAKL4 => PIPETXDATAKL4_outdelay, + PIPETXDATAKL5 => PIPETXDATAKL5_outdelay, + PIPETXDATAKL6 => PIPETXDATAKL6_outdelay, + PIPETXDATAKL7 => PIPETXDATAKL7_outdelay, + PIPETXDATAL0 => PIPETXDATAL0_outdelay, + PIPETXDATAL1 => PIPETXDATAL1_outdelay, + PIPETXDATAL2 => PIPETXDATAL2_outdelay, + PIPETXDATAL3 => PIPETXDATAL3_outdelay, + PIPETXDATAL4 => PIPETXDATAL4_outdelay, + PIPETXDATAL5 => PIPETXDATAL5_outdelay, + PIPETXDATAL6 => PIPETXDATAL6_outdelay, + PIPETXDATAL7 => PIPETXDATAL7_outdelay, + PIPETXDETECTRXLOOPBACKL0 => PIPETXDETECTRXLOOPBACKL0_outdelay, + PIPETXDETECTRXLOOPBACKL1 => PIPETXDETECTRXLOOPBACKL1_outdelay, + PIPETXDETECTRXLOOPBACKL2 => PIPETXDETECTRXLOOPBACKL2_outdelay, + PIPETXDETECTRXLOOPBACKL3 => PIPETXDETECTRXLOOPBACKL3_outdelay, + PIPETXDETECTRXLOOPBACKL4 => PIPETXDETECTRXLOOPBACKL4_outdelay, + PIPETXDETECTRXLOOPBACKL5 => PIPETXDETECTRXLOOPBACKL5_outdelay, + PIPETXDETECTRXLOOPBACKL6 => PIPETXDETECTRXLOOPBACKL6_outdelay, + PIPETXDETECTRXLOOPBACKL7 => PIPETXDETECTRXLOOPBACKL7_outdelay, + PIPETXELECIDLEL0 => PIPETXELECIDLEL0_outdelay, + PIPETXELECIDLEL1 => PIPETXELECIDLEL1_outdelay, + PIPETXELECIDLEL2 => PIPETXELECIDLEL2_outdelay, + PIPETXELECIDLEL3 => PIPETXELECIDLEL3_outdelay, + PIPETXELECIDLEL4 => PIPETXELECIDLEL4_outdelay, + PIPETXELECIDLEL5 => PIPETXELECIDLEL5_outdelay, + PIPETXELECIDLEL6 => PIPETXELECIDLEL6_outdelay, + PIPETXELECIDLEL7 => PIPETXELECIDLEL7_outdelay, + SERRENABLE => SERRENABLE_outdelay, + URREPORTINGENABLE => URREPORTINGENABLE_outdelay, + + AUXPOWER => AUXPOWER_indelay, + CFGNEGOTIATEDLINKWIDTH => CFGNEGOTIATEDLINKWIDTH_indelay, + COMPLIANCEAVOID => COMPLIANCEAVOID_indelay, + CRMCFGBRIDGEHOTRESET => CRMCFGBRIDGEHOTRESET_indelay, + CRMCORECLK => CRMCORECLK_indelay, + CRMCORECLKDLO => CRMCORECLKDLO_indelay, + CRMCORECLKRXO => CRMCORECLKRXO_indelay, + CRMCORECLKTXO => CRMCORECLKTXO_indelay, + CRMLINKRSTN => CRMLINKRSTN_indelay, + CRMMACRSTN => CRMMACRSTN_indelay, + CRMMGMTRSTN => CRMMGMTRSTN_indelay, + CRMNVRSTN => CRMNVRSTN_indelay, + CRMTXHOTRESETN => CRMTXHOTRESETN_indelay, + CRMURSTN => CRMURSTN_indelay, + CRMUSERCFGRSTN => CRMUSERCFGRSTN_indelay, + CRMUSERCLK => CRMUSERCLK_indelay, + CRMUSERCLKRXO => CRMUSERCLKRXO_indelay, + CRMUSERCLKTXO => CRMUSERCLKTXO_indelay, + CROSSLINKSEED => CROSSLINKSEED_indelay, + GSR => GSR, + L0ACKNAKTIMERADJUSTMENT => L0ACKNAKTIMERADJUSTMENT_indelay, + L0ALLDOWNPORTSINL1 => L0ALLDOWNPORTSINL1_indelay, + L0ALLDOWNRXPORTSINL0S => L0ALLDOWNRXPORTSINL0S_indelay, + L0ASE => L0ASE_indelay, + L0ASPORTCOUNT => L0ASPORTCOUNT_indelay, + L0ASTURNPOOLBITSCONSUMED => L0ASTURNPOOLBITSCONSUMED_indelay, + L0ATTENTIONBUTTONPRESSED => L0ATTENTIONBUTTONPRESSED_indelay, + L0CFGASSPANTREEOWNEDSTATE => L0CFGASSPANTREEOWNEDSTATE_indelay, + L0CFGASSTATECHANGECMD => L0CFGASSTATECHANGECMD_indelay, + L0CFGDISABLESCRAMBLE => L0CFGDISABLESCRAMBLE_indelay, + L0CFGEXTENDEDSYNC => L0CFGEXTENDEDSYNC_indelay, + L0CFGL0SENTRYENABLE => L0CFGL0SENTRYENABLE_indelay, + L0CFGL0SENTRYSUP => L0CFGL0SENTRYSUP_indelay, + L0CFGL0SEXITLAT => L0CFGL0SEXITLAT_indelay, + L0CFGLINKDISABLE => L0CFGLINKDISABLE_indelay, + L0CFGLOOPBACKMASTER => L0CFGLOOPBACKMASTER_indelay, + L0CFGNEGOTIATEDMAXP => L0CFGNEGOTIATEDMAXP_indelay, + L0CFGVCENABLE => L0CFGVCENABLE_indelay, + L0CFGVCID => L0CFGVCID_indelay, + L0DLLHOLDLINKUP => L0DLLHOLDLINKUP_indelay, + L0ELECTROMECHANICALINTERLOCKENGAGED => L0ELECTROMECHANICALINTERLOCKENGAGED_indelay, + L0FWDASSERTINTALEGACYINT => L0FWDASSERTINTALEGACYINT_indelay, + L0FWDASSERTINTBLEGACYINT => L0FWDASSERTINTBLEGACYINT_indelay, + L0FWDASSERTINTCLEGACYINT => L0FWDASSERTINTCLEGACYINT_indelay, + L0FWDASSERTINTDLEGACYINT => L0FWDASSERTINTDLEGACYINT_indelay, + L0FWDCORRERRIN => L0FWDCORRERRIN_indelay, + L0FWDDEASSERTINTALEGACYINT => L0FWDDEASSERTINTALEGACYINT_indelay, + L0FWDDEASSERTINTBLEGACYINT => L0FWDDEASSERTINTBLEGACYINT_indelay, + L0FWDDEASSERTINTCLEGACYINT => L0FWDDEASSERTINTCLEGACYINT_indelay, + L0FWDDEASSERTINTDLEGACYINT => L0FWDDEASSERTINTDLEGACYINT_indelay, + L0FWDFATALERRIN => L0FWDFATALERRIN_indelay, + L0FWDNONFATALERRIN => L0FWDNONFATALERRIN_indelay, + L0LEGACYINTFUNCT0 => L0LEGACYINTFUNCT0_indelay, + L0MRLSENSORCLOSEDN => L0MRLSENSORCLOSEDN_indelay, + L0MSIREQUEST0 => L0MSIREQUEST0_indelay, + L0PACKETHEADERFROMUSER => L0PACKETHEADERFROMUSER_indelay, + L0PMEREQIN => L0PMEREQIN_indelay, + L0PORTNUMBER => L0PORTNUMBER_indelay, + L0POWERFAULTDETECTED => L0POWERFAULTDETECTED_indelay, + L0PRESENCEDETECTSLOTEMPTYN => L0PRESENCEDETECTSLOTEMPTYN_indelay, + L0PWRNEWSTATEREQ => L0PWRNEWSTATEREQ_indelay, + L0PWRNEXTLINKSTATE => L0PWRNEXTLINKSTATE_indelay, + L0REPLAYTIMERADJUSTMENT => L0REPLAYTIMERADJUSTMENT_indelay, + L0ROOTTURNOFFREQ => L0ROOTTURNOFFREQ_indelay, + L0RXTLTLPNONINITIALIZEDVC => L0RXTLTLPNONINITIALIZEDVC_indelay, + L0SENDUNLOCKMESSAGE => L0SENDUNLOCKMESSAGE_indelay, + L0SETCOMPLETERABORTERROR => L0SETCOMPLETERABORTERROR_indelay, + L0SETCOMPLETIONTIMEOUTCORRERROR => L0SETCOMPLETIONTIMEOUTCORRERROR_indelay, + L0SETCOMPLETIONTIMEOUTUNCORRERROR => L0SETCOMPLETIONTIMEOUTUNCORRERROR_indelay, + L0SETDETECTEDCORRERROR => L0SETDETECTEDCORRERROR_indelay, + L0SETDETECTEDFATALERROR => L0SETDETECTEDFATALERROR_indelay, + L0SETDETECTEDNONFATALERROR => L0SETDETECTEDNONFATALERROR_indelay, + L0SETLINKDETECTEDPARITYERROR => L0SETLINKDETECTEDPARITYERROR_indelay, + L0SETLINKMASTERDATAPARITY => L0SETLINKMASTERDATAPARITY_indelay, + L0SETLINKRECEIVEDMASTERABORT => L0SETLINKRECEIVEDMASTERABORT_indelay, + L0SETLINKRECEIVEDTARGETABORT => L0SETLINKRECEIVEDTARGETABORT_indelay, + L0SETLINKSIGNALLEDTARGETABORT => L0SETLINKSIGNALLEDTARGETABORT_indelay, + L0SETLINKSYSTEMERROR => L0SETLINKSYSTEMERROR_indelay, + L0SETUNEXPECTEDCOMPLETIONCORRERROR => L0SETUNEXPECTEDCOMPLETIONCORRERROR_indelay, + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR => L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_indelay, + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR => L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_indelay, + L0SETUNSUPPORTEDREQUESTOTHERERROR => L0SETUNSUPPORTEDREQUESTOTHERERROR_indelay, + L0SETUSERDETECTEDPARITYERROR => L0SETUSERDETECTEDPARITYERROR_indelay, + L0SETUSERMASTERDATAPARITY => L0SETUSERMASTERDATAPARITY_indelay, + L0SETUSERRECEIVEDMASTERABORT => L0SETUSERRECEIVEDMASTERABORT_indelay, + L0SETUSERRECEIVEDTARGETABORT => L0SETUSERRECEIVEDTARGETABORT_indelay, + L0SETUSERSIGNALLEDTARGETABORT => L0SETUSERSIGNALLEDTARGETABORT_indelay, + L0SETUSERSYSTEMERROR => L0SETUSERSYSTEMERROR_indelay, + L0TLASFCCREDSTARVATION => L0TLASFCCREDSTARVATION_indelay, + L0TLLINKRETRAIN => L0TLLINKRETRAIN_indelay, + L0TRANSACTIONSPENDING => L0TRANSACTIONSPENDING_indelay, + L0TXBEACON => L0TXBEACON_indelay, + L0TXCFGPM => L0TXCFGPM_indelay, + L0TXCFGPMTYPE => L0TXCFGPMTYPE_indelay, + L0TXTLFCCMPLMCCRED => L0TXTLFCCMPLMCCRED_indelay, + L0TXTLFCCMPLMCUPDATE => L0TXTLFCCMPLMCUPDATE_indelay, + L0TXTLFCNPOSTBYPCRED => L0TXTLFCNPOSTBYPCRED_indelay, + L0TXTLFCNPOSTBYPUPDATE => L0TXTLFCNPOSTBYPUPDATE_indelay, + L0TXTLFCPOSTORDCRED => L0TXTLFCPOSTORDCRED_indelay, + L0TXTLFCPOSTORDUPDATE => L0TXTLFCPOSTORDUPDATE_indelay, + L0TXTLSBFCDATA => L0TXTLSBFCDATA_indelay, + L0TXTLSBFCUPDATE => L0TXTLSBFCUPDATE_indelay, + L0TXTLTLPDATA => L0TXTLTLPDATA_indelay, + L0TXTLTLPEDB => L0TXTLTLPEDB_indelay, + L0TXTLTLPENABLE => L0TXTLTLPENABLE_indelay, + L0TXTLTLPEND => L0TXTLTLPEND_indelay, + L0TXTLTLPLATENCY => L0TXTLTLPLATENCY_indelay, + L0TXTLTLPREQ => L0TXTLTLPREQ_indelay, + L0TXTLTLPREQEND => L0TXTLTLPREQEND_indelay, + L0TXTLTLPWIDTH => L0TXTLTLPWIDTH_indelay, + L0UPSTREAMRXPORTINL0S => L0UPSTREAMRXPORTINL0S_indelay, + L0VC0PREVIEWEXPAND => L0VC0PREVIEWEXPAND_indelay, + L0WAKEN => L0WAKEN_indelay, + LLKRXCHFIFO => LLKRXCHFIFO_indelay, + LLKRXCHTC => LLKRXCHTC_indelay, + LLKRXDSTCONTREQN => LLKRXDSTCONTREQN_indelay, + LLKRXDSTREQN => LLKRXDSTREQN_indelay, + LLKTX4DWHEADERN => LLKTX4DWHEADERN_indelay, + LLKTXCHFIFO => LLKTXCHFIFO_indelay, + LLKTXCHTC => LLKTXCHTC_indelay, + LLKTXCOMPLETEN => LLKTXCOMPLETEN_indelay, + LLKTXCREATEECRCN => LLKTXCREATEECRCN_indelay, + LLKTXDATA => LLKTXDATA_indelay, + LLKTXENABLEN => LLKTXENABLEN_indelay, + LLKTXEOFN => LLKTXEOFN_indelay, + LLKTXEOPN => LLKTXEOPN_indelay, + LLKTXSOFN => LLKTXSOFN_indelay, + LLKTXSOPN => LLKTXSOPN_indelay, + LLKTXSRCDSCN => LLKTXSRCDSCN_indelay, + LLKTXSRCRDYN => LLKTXSRCRDYN_indelay, + MAINPOWER => MAINPOWER_indelay, + MGMTADDR => MGMTADDR_indelay, + MGMTBWREN => MGMTBWREN_indelay, + MGMTRDEN => MGMTRDEN_indelay, + MGMTSTATSCREDITSEL => MGMTSTATSCREDITSEL_indelay, + MGMTWDATA => MGMTWDATA_indelay, + MGMTWREN => MGMTWREN_indelay, + MIMDLLBRDATA => MIMDLLBRDATA_indelay, + MIMRXBRDATA => MIMRXBRDATA_indelay, + MIMTXBRDATA => MIMTXBRDATA_indelay, + PIPEPHYSTATUSL0 => PIPEPHYSTATUSL0_indelay, + PIPEPHYSTATUSL1 => PIPEPHYSTATUSL1_indelay, + PIPEPHYSTATUSL2 => PIPEPHYSTATUSL2_indelay, + PIPEPHYSTATUSL3 => PIPEPHYSTATUSL3_indelay, + PIPEPHYSTATUSL4 => PIPEPHYSTATUSL4_indelay, + PIPEPHYSTATUSL5 => PIPEPHYSTATUSL5_indelay, + PIPEPHYSTATUSL6 => PIPEPHYSTATUSL6_indelay, + PIPEPHYSTATUSL7 => PIPEPHYSTATUSL7_indelay, + PIPERXCHANISALIGNEDL0 => PIPERXCHANISALIGNEDL0_indelay, + PIPERXCHANISALIGNEDL1 => PIPERXCHANISALIGNEDL1_indelay, + PIPERXCHANISALIGNEDL2 => PIPERXCHANISALIGNEDL2_indelay, + PIPERXCHANISALIGNEDL3 => PIPERXCHANISALIGNEDL3_indelay, + PIPERXCHANISALIGNEDL4 => PIPERXCHANISALIGNEDL4_indelay, + PIPERXCHANISALIGNEDL5 => PIPERXCHANISALIGNEDL5_indelay, + PIPERXCHANISALIGNEDL6 => PIPERXCHANISALIGNEDL6_indelay, + PIPERXCHANISALIGNEDL7 => PIPERXCHANISALIGNEDL7_indelay, + PIPERXDATAKL0 => PIPERXDATAKL0_indelay, + PIPERXDATAKL1 => PIPERXDATAKL1_indelay, + PIPERXDATAKL2 => PIPERXDATAKL2_indelay, + PIPERXDATAKL3 => PIPERXDATAKL3_indelay, + PIPERXDATAKL4 => PIPERXDATAKL4_indelay, + PIPERXDATAKL5 => PIPERXDATAKL5_indelay, + PIPERXDATAKL6 => PIPERXDATAKL6_indelay, + PIPERXDATAKL7 => PIPERXDATAKL7_indelay, + PIPERXDATAL0 => PIPERXDATAL0_indelay, + PIPERXDATAL1 => PIPERXDATAL1_indelay, + PIPERXDATAL2 => PIPERXDATAL2_indelay, + PIPERXDATAL3 => PIPERXDATAL3_indelay, + PIPERXDATAL4 => PIPERXDATAL4_indelay, + PIPERXDATAL5 => PIPERXDATAL5_indelay, + PIPERXDATAL6 => PIPERXDATAL6_indelay, + PIPERXDATAL7 => PIPERXDATAL7_indelay, + PIPERXELECIDLEL0 => PIPERXELECIDLEL0_indelay, + PIPERXELECIDLEL1 => PIPERXELECIDLEL1_indelay, + PIPERXELECIDLEL2 => PIPERXELECIDLEL2_indelay, + PIPERXELECIDLEL3 => PIPERXELECIDLEL3_indelay, + PIPERXELECIDLEL4 => PIPERXELECIDLEL4_indelay, + PIPERXELECIDLEL5 => PIPERXELECIDLEL5_indelay, + PIPERXELECIDLEL6 => PIPERXELECIDLEL6_indelay, + PIPERXELECIDLEL7 => PIPERXELECIDLEL7_indelay, + PIPERXSTATUSL0 => PIPERXSTATUSL0_indelay, + PIPERXSTATUSL1 => PIPERXSTATUSL1_indelay, + PIPERXSTATUSL2 => PIPERXSTATUSL2_indelay, + PIPERXSTATUSL3 => PIPERXSTATUSL3_indelay, + PIPERXSTATUSL4 => PIPERXSTATUSL4_indelay, + PIPERXSTATUSL5 => PIPERXSTATUSL5_indelay, + PIPERXSTATUSL6 => PIPERXSTATUSL6_indelay, + PIPERXSTATUSL7 => PIPERXSTATUSL7_indelay, + PIPERXVALIDL0 => PIPERXVALIDL0_indelay, + PIPERXVALIDL1 => PIPERXVALIDL1_indelay, + PIPERXVALIDL2 => PIPERXVALIDL2_indelay, + PIPERXVALIDL3 => PIPERXVALIDL3_indelay, + PIPERXVALIDL4 => PIPERXVALIDL4_indelay, + PIPERXVALIDL5 => PIPERXVALIDL5_indelay, + PIPERXVALIDL6 => PIPERXVALIDL6_indelay, + PIPERXVALIDL7 => PIPERXVALIDL7_indelay + ); + + INIPROC : process + begin + case TXTSNFTS is + when 0 => TXTSNFTS_BINARY <= "00000000"; + when 1 => TXTSNFTS_BINARY <= "00000001"; + when 2 => TXTSNFTS_BINARY <= "00000010"; + when 3 => TXTSNFTS_BINARY <= "00000011"; + when 4 => TXTSNFTS_BINARY <= "00000100"; + when 5 => TXTSNFTS_BINARY <= "00000101"; + when 6 => TXTSNFTS_BINARY <= "00000110"; + when 7 => TXTSNFTS_BINARY <= "00000111"; + when 8 => TXTSNFTS_BINARY <= "00001000"; + when 9 => TXTSNFTS_BINARY <= "00001001"; + when 10 => TXTSNFTS_BINARY <= "00001010"; + when 11 => TXTSNFTS_BINARY <= "00001011"; + when 12 => TXTSNFTS_BINARY <= "00001100"; + when 13 => TXTSNFTS_BINARY <= "00001101"; + when 14 => TXTSNFTS_BINARY <= "00001110"; + when 15 => TXTSNFTS_BINARY <= "00001111"; + when 16 => TXTSNFTS_BINARY <= "00010000"; + when 17 => TXTSNFTS_BINARY <= "00010001"; + when 18 => TXTSNFTS_BINARY <= "00010010"; + when 19 => TXTSNFTS_BINARY <= "00010011"; + when 20 => TXTSNFTS_BINARY <= "00010100"; + when 21 => TXTSNFTS_BINARY <= "00010101"; + when 22 => TXTSNFTS_BINARY <= "00010110"; + when 23 => TXTSNFTS_BINARY <= "00010111"; + when 24 => TXTSNFTS_BINARY <= "00011000"; + when 25 => TXTSNFTS_BINARY <= "00011001"; + when 26 => TXTSNFTS_BINARY <= "00011010"; + when 27 => TXTSNFTS_BINARY <= "00011011"; + when 28 => TXTSNFTS_BINARY <= "00011100"; + when 29 => TXTSNFTS_BINARY <= "00011101"; + when 30 => TXTSNFTS_BINARY <= "00011110"; + when 31 => TXTSNFTS_BINARY <= "00011111"; + when 32 => TXTSNFTS_BINARY <= "00100000"; + when 33 => TXTSNFTS_BINARY <= "00100001"; + when 34 => TXTSNFTS_BINARY <= "00100010"; + when 35 => TXTSNFTS_BINARY <= "00100011"; + when 36 => TXTSNFTS_BINARY <= "00100100"; + when 37 => TXTSNFTS_BINARY <= "00100101"; + when 38 => TXTSNFTS_BINARY <= "00100110"; + when 39 => TXTSNFTS_BINARY <= "00100111"; + when 40 => TXTSNFTS_BINARY <= "00101000"; + when 41 => TXTSNFTS_BINARY <= "00101001"; + when 42 => TXTSNFTS_BINARY <= "00101010"; + when 43 => TXTSNFTS_BINARY <= "00101011"; + when 44 => TXTSNFTS_BINARY <= "00101100"; + when 45 => TXTSNFTS_BINARY <= "00101101"; + when 46 => TXTSNFTS_BINARY <= "00101110"; + when 47 => TXTSNFTS_BINARY <= "00101111"; + when 48 => TXTSNFTS_BINARY <= "00110000"; + when 49 => TXTSNFTS_BINARY <= "00110001"; + when 50 => TXTSNFTS_BINARY <= "00110010"; + when 51 => TXTSNFTS_BINARY <= "00110011"; + when 52 => TXTSNFTS_BINARY <= "00110100"; + when 53 => TXTSNFTS_BINARY <= "00110101"; + when 54 => TXTSNFTS_BINARY <= "00110110"; + when 55 => TXTSNFTS_BINARY <= "00110111"; + when 56 => TXTSNFTS_BINARY <= "00111000"; + when 57 => TXTSNFTS_BINARY <= "00111001"; + when 58 => TXTSNFTS_BINARY <= "00111010"; + when 59 => TXTSNFTS_BINARY <= "00111011"; + when 60 => TXTSNFTS_BINARY <= "00111100"; + when 61 => TXTSNFTS_BINARY <= "00111101"; + when 62 => TXTSNFTS_BINARY <= "00111110"; + when 63 => TXTSNFTS_BINARY <= "00111111"; + when 64 => TXTSNFTS_BINARY <= "01000000"; + when 65 => TXTSNFTS_BINARY <= "01000001"; + when 66 => TXTSNFTS_BINARY <= "01000010"; + when 67 => TXTSNFTS_BINARY <= "01000011"; + when 68 => TXTSNFTS_BINARY <= "01000100"; + when 69 => TXTSNFTS_BINARY <= "01000101"; + when 70 => TXTSNFTS_BINARY <= "01000110"; + when 71 => TXTSNFTS_BINARY <= "01000111"; + when 72 => TXTSNFTS_BINARY <= "01001000"; + when 73 => TXTSNFTS_BINARY <= "01001001"; + when 74 => TXTSNFTS_BINARY <= "01001010"; + when 75 => TXTSNFTS_BINARY <= "01001011"; + when 76 => TXTSNFTS_BINARY <= "01001100"; + when 77 => TXTSNFTS_BINARY <= "01001101"; + when 78 => TXTSNFTS_BINARY <= "01001110"; + when 79 => TXTSNFTS_BINARY <= "01001111"; + when 80 => TXTSNFTS_BINARY <= "01010000"; + when 81 => TXTSNFTS_BINARY <= "01010001"; + when 82 => TXTSNFTS_BINARY <= "01010010"; + when 83 => TXTSNFTS_BINARY <= "01010011"; + when 84 => TXTSNFTS_BINARY <= "01010100"; + when 85 => TXTSNFTS_BINARY <= "01010101"; + when 86 => TXTSNFTS_BINARY <= "01010110"; + when 87 => TXTSNFTS_BINARY <= "01010111"; + when 88 => TXTSNFTS_BINARY <= "01011000"; + when 89 => TXTSNFTS_BINARY <= "01011001"; + when 90 => TXTSNFTS_BINARY <= "01011010"; + when 91 => TXTSNFTS_BINARY <= "01011011"; + when 92 => TXTSNFTS_BINARY <= "01011100"; + when 93 => TXTSNFTS_BINARY <= "01011101"; + when 94 => TXTSNFTS_BINARY <= "01011110"; + when 95 => TXTSNFTS_BINARY <= "01011111"; + when 96 => TXTSNFTS_BINARY <= "01100000"; + when 97 => TXTSNFTS_BINARY <= "01100001"; + when 98 => TXTSNFTS_BINARY <= "01100010"; + when 99 => TXTSNFTS_BINARY <= "01100011"; + when 100 => TXTSNFTS_BINARY <= "01100100"; + when 101 => TXTSNFTS_BINARY <= "01100101"; + when 102 => TXTSNFTS_BINARY <= "01100110"; + when 103 => TXTSNFTS_BINARY <= "01100111"; + when 104 => TXTSNFTS_BINARY <= "01101000"; + when 105 => TXTSNFTS_BINARY <= "01101001"; + when 106 => TXTSNFTS_BINARY <= "01101010"; + when 107 => TXTSNFTS_BINARY <= "01101011"; + when 108 => TXTSNFTS_BINARY <= "01101100"; + when 109 => TXTSNFTS_BINARY <= "01101101"; + when 110 => TXTSNFTS_BINARY <= "01101110"; + when 111 => TXTSNFTS_BINARY <= "01101111"; + when 112 => TXTSNFTS_BINARY <= "01110000"; + when 113 => TXTSNFTS_BINARY <= "01110001"; + when 114 => TXTSNFTS_BINARY <= "01110010"; + when 115 => TXTSNFTS_BINARY <= "01110011"; + when 116 => TXTSNFTS_BINARY <= "01110100"; + when 117 => TXTSNFTS_BINARY <= "01110101"; + when 118 => TXTSNFTS_BINARY <= "01110110"; + when 119 => TXTSNFTS_BINARY <= "01110111"; + when 120 => TXTSNFTS_BINARY <= "01111000"; + when 121 => TXTSNFTS_BINARY <= "01111001"; + when 122 => TXTSNFTS_BINARY <= "01111010"; + when 123 => TXTSNFTS_BINARY <= "01111011"; + when 124 => TXTSNFTS_BINARY <= "01111100"; + when 125 => TXTSNFTS_BINARY <= "01111101"; + when 126 => TXTSNFTS_BINARY <= "01111110"; + when 127 => TXTSNFTS_BINARY <= "01111111"; + when 128 => TXTSNFTS_BINARY <= "10000000"; + when 129 => TXTSNFTS_BINARY <= "10000001"; + when 130 => TXTSNFTS_BINARY <= "10000010"; + when 131 => TXTSNFTS_BINARY <= "10000011"; + when 132 => TXTSNFTS_BINARY <= "10000100"; + when 133 => TXTSNFTS_BINARY <= "10000101"; + when 134 => TXTSNFTS_BINARY <= "10000110"; + when 135 => TXTSNFTS_BINARY <= "10000111"; + when 136 => TXTSNFTS_BINARY <= "10001000"; + when 137 => TXTSNFTS_BINARY <= "10001001"; + when 138 => TXTSNFTS_BINARY <= "10001010"; + when 139 => TXTSNFTS_BINARY <= "10001011"; + when 140 => TXTSNFTS_BINARY <= "10001100"; + when 141 => TXTSNFTS_BINARY <= "10001101"; + when 142 => TXTSNFTS_BINARY <= "10001110"; + when 143 => TXTSNFTS_BINARY <= "10001111"; + when 144 => TXTSNFTS_BINARY <= "10010000"; + when 145 => TXTSNFTS_BINARY <= "10010001"; + when 146 => TXTSNFTS_BINARY <= "10010010"; + when 147 => TXTSNFTS_BINARY <= "10010011"; + when 148 => TXTSNFTS_BINARY <= "10010100"; + when 149 => TXTSNFTS_BINARY <= "10010101"; + when 150 => TXTSNFTS_BINARY <= "10010110"; + when 151 => TXTSNFTS_BINARY <= "10010111"; + when 152 => TXTSNFTS_BINARY <= "10011000"; + when 153 => TXTSNFTS_BINARY <= "10011001"; + when 154 => TXTSNFTS_BINARY <= "10011010"; + when 155 => TXTSNFTS_BINARY <= "10011011"; + when 156 => TXTSNFTS_BINARY <= "10011100"; + when 157 => TXTSNFTS_BINARY <= "10011101"; + when 158 => TXTSNFTS_BINARY <= "10011110"; + when 159 => TXTSNFTS_BINARY <= "10011111"; + when 160 => TXTSNFTS_BINARY <= "10100000"; + when 161 => TXTSNFTS_BINARY <= "10100001"; + when 162 => TXTSNFTS_BINARY <= "10100010"; + when 163 => TXTSNFTS_BINARY <= "10100011"; + when 164 => TXTSNFTS_BINARY <= "10100100"; + when 165 => TXTSNFTS_BINARY <= "10100101"; + when 166 => TXTSNFTS_BINARY <= "10100110"; + when 167 => TXTSNFTS_BINARY <= "10100111"; + when 168 => TXTSNFTS_BINARY <= "10101000"; + when 169 => TXTSNFTS_BINARY <= "10101001"; + when 170 => TXTSNFTS_BINARY <= "10101010"; + when 171 => TXTSNFTS_BINARY <= "10101011"; + when 172 => TXTSNFTS_BINARY <= "10101100"; + when 173 => TXTSNFTS_BINARY <= "10101101"; + when 174 => TXTSNFTS_BINARY <= "10101110"; + when 175 => TXTSNFTS_BINARY <= "10101111"; + when 176 => TXTSNFTS_BINARY <= "10110000"; + when 177 => TXTSNFTS_BINARY <= "10110001"; + when 178 => TXTSNFTS_BINARY <= "10110010"; + when 179 => TXTSNFTS_BINARY <= "10110011"; + when 180 => TXTSNFTS_BINARY <= "10110100"; + when 181 => TXTSNFTS_BINARY <= "10110101"; + when 182 => TXTSNFTS_BINARY <= "10110110"; + when 183 => TXTSNFTS_BINARY <= "10110111"; + when 184 => TXTSNFTS_BINARY <= "10111000"; + when 185 => TXTSNFTS_BINARY <= "10111001"; + when 186 => TXTSNFTS_BINARY <= "10111010"; + when 187 => TXTSNFTS_BINARY <= "10111011"; + when 188 => TXTSNFTS_BINARY <= "10111100"; + when 189 => TXTSNFTS_BINARY <= "10111101"; + when 190 => TXTSNFTS_BINARY <= "10111110"; + when 191 => TXTSNFTS_BINARY <= "10111111"; + when 192 => TXTSNFTS_BINARY <= "11000000"; + when 193 => TXTSNFTS_BINARY <= "11000001"; + when 194 => TXTSNFTS_BINARY <= "11000010"; + when 195 => TXTSNFTS_BINARY <= "11000011"; + when 196 => TXTSNFTS_BINARY <= "11000100"; + when 197 => TXTSNFTS_BINARY <= "11000101"; + when 198 => TXTSNFTS_BINARY <= "11000110"; + when 199 => TXTSNFTS_BINARY <= "11000111"; + when 200 => TXTSNFTS_BINARY <= "11001000"; + when 201 => TXTSNFTS_BINARY <= "11001001"; + when 202 => TXTSNFTS_BINARY <= "11001010"; + when 203 => TXTSNFTS_BINARY <= "11001011"; + when 204 => TXTSNFTS_BINARY <= "11001100"; + when 205 => TXTSNFTS_BINARY <= "11001101"; + when 206 => TXTSNFTS_BINARY <= "11001110"; + when 207 => TXTSNFTS_BINARY <= "11001111"; + when 208 => TXTSNFTS_BINARY <= "11010000"; + when 209 => TXTSNFTS_BINARY <= "11010001"; + when 210 => TXTSNFTS_BINARY <= "11010010"; + when 211 => TXTSNFTS_BINARY <= "11010011"; + when 212 => TXTSNFTS_BINARY <= "11010100"; + when 213 => TXTSNFTS_BINARY <= "11010101"; + when 214 => TXTSNFTS_BINARY <= "11010110"; + when 215 => TXTSNFTS_BINARY <= "11010111"; + when 216 => TXTSNFTS_BINARY <= "11011000"; + when 217 => TXTSNFTS_BINARY <= "11011001"; + when 218 => TXTSNFTS_BINARY <= "11011010"; + when 219 => TXTSNFTS_BINARY <= "11011011"; + when 220 => TXTSNFTS_BINARY <= "11011100"; + when 221 => TXTSNFTS_BINARY <= "11011101"; + when 222 => TXTSNFTS_BINARY <= "11011110"; + when 223 => TXTSNFTS_BINARY <= "11011111"; + when 224 => TXTSNFTS_BINARY <= "11100000"; + when 225 => TXTSNFTS_BINARY <= "11100001"; + when 226 => TXTSNFTS_BINARY <= "11100010"; + when 227 => TXTSNFTS_BINARY <= "11100011"; + when 228 => TXTSNFTS_BINARY <= "11100100"; + when 229 => TXTSNFTS_BINARY <= "11100101"; + when 230 => TXTSNFTS_BINARY <= "11100110"; + when 231 => TXTSNFTS_BINARY <= "11100111"; + when 232 => TXTSNFTS_BINARY <= "11101000"; + when 233 => TXTSNFTS_BINARY <= "11101001"; + when 234 => TXTSNFTS_BINARY <= "11101010"; + when 235 => TXTSNFTS_BINARY <= "11101011"; + when 236 => TXTSNFTS_BINARY <= "11101100"; + when 237 => TXTSNFTS_BINARY <= "11101101"; + when 238 => TXTSNFTS_BINARY <= "11101110"; + when 239 => TXTSNFTS_BINARY <= "11101111"; + when 240 => TXTSNFTS_BINARY <= "11110000"; + when 241 => TXTSNFTS_BINARY <= "11110001"; + when 242 => TXTSNFTS_BINARY <= "11110010"; + when 243 => TXTSNFTS_BINARY <= "11110011"; + when 244 => TXTSNFTS_BINARY <= "11110100"; + when 245 => TXTSNFTS_BINARY <= "11110101"; + when 246 => TXTSNFTS_BINARY <= "11110110"; + when 247 => TXTSNFTS_BINARY <= "11110111"; + when 248 => TXTSNFTS_BINARY <= "11111000"; + when 249 => TXTSNFTS_BINARY <= "11111001"; + when 250 => TXTSNFTS_BINARY <= "11111010"; + when 251 => TXTSNFTS_BINARY <= "11111011"; + when 252 => TXTSNFTS_BINARY <= "11111100"; + when 253 => TXTSNFTS_BINARY <= "11111101"; + when 254 => TXTSNFTS_BINARY <= "11111110"; + when 255 => TXTSNFTS_BINARY <= "11111111"; + when others => assert FALSE report "Error : TXTSNFTS is not in range 0...255." severity error; + end case; + case TXTSNFTSCOMCLK is + when 0 => TXTSNFTSCOMCLK_BINARY <= "00000000"; + when 1 => TXTSNFTSCOMCLK_BINARY <= "00000001"; + when 2 => TXTSNFTSCOMCLK_BINARY <= "00000010"; + when 3 => TXTSNFTSCOMCLK_BINARY <= "00000011"; + when 4 => TXTSNFTSCOMCLK_BINARY <= "00000100"; + when 5 => TXTSNFTSCOMCLK_BINARY <= "00000101"; + when 6 => TXTSNFTSCOMCLK_BINARY <= "00000110"; + when 7 => TXTSNFTSCOMCLK_BINARY <= "00000111"; + when 8 => TXTSNFTSCOMCLK_BINARY <= "00001000"; + when 9 => TXTSNFTSCOMCLK_BINARY <= "00001001"; + when 10 => TXTSNFTSCOMCLK_BINARY <= "00001010"; + when 11 => TXTSNFTSCOMCLK_BINARY <= "00001011"; + when 12 => TXTSNFTSCOMCLK_BINARY <= "00001100"; + when 13 => TXTSNFTSCOMCLK_BINARY <= "00001101"; + when 14 => TXTSNFTSCOMCLK_BINARY <= "00001110"; + when 15 => TXTSNFTSCOMCLK_BINARY <= "00001111"; + when 16 => TXTSNFTSCOMCLK_BINARY <= "00010000"; + when 17 => TXTSNFTSCOMCLK_BINARY <= "00010001"; + when 18 => TXTSNFTSCOMCLK_BINARY <= "00010010"; + when 19 => TXTSNFTSCOMCLK_BINARY <= "00010011"; + when 20 => TXTSNFTSCOMCLK_BINARY <= "00010100"; + when 21 => TXTSNFTSCOMCLK_BINARY <= "00010101"; + when 22 => TXTSNFTSCOMCLK_BINARY <= "00010110"; + when 23 => TXTSNFTSCOMCLK_BINARY <= "00010111"; + when 24 => TXTSNFTSCOMCLK_BINARY <= "00011000"; + when 25 => TXTSNFTSCOMCLK_BINARY <= "00011001"; + when 26 => TXTSNFTSCOMCLK_BINARY <= "00011010"; + when 27 => TXTSNFTSCOMCLK_BINARY <= "00011011"; + when 28 => TXTSNFTSCOMCLK_BINARY <= "00011100"; + when 29 => TXTSNFTSCOMCLK_BINARY <= "00011101"; + when 30 => TXTSNFTSCOMCLK_BINARY <= "00011110"; + when 31 => TXTSNFTSCOMCLK_BINARY <= "00011111"; + when 32 => TXTSNFTSCOMCLK_BINARY <= "00100000"; + when 33 => TXTSNFTSCOMCLK_BINARY <= "00100001"; + when 34 => TXTSNFTSCOMCLK_BINARY <= "00100010"; + when 35 => TXTSNFTSCOMCLK_BINARY <= "00100011"; + when 36 => TXTSNFTSCOMCLK_BINARY <= "00100100"; + when 37 => TXTSNFTSCOMCLK_BINARY <= "00100101"; + when 38 => TXTSNFTSCOMCLK_BINARY <= "00100110"; + when 39 => TXTSNFTSCOMCLK_BINARY <= "00100111"; + when 40 => TXTSNFTSCOMCLK_BINARY <= "00101000"; + when 41 => TXTSNFTSCOMCLK_BINARY <= "00101001"; + when 42 => TXTSNFTSCOMCLK_BINARY <= "00101010"; + when 43 => TXTSNFTSCOMCLK_BINARY <= "00101011"; + when 44 => TXTSNFTSCOMCLK_BINARY <= "00101100"; + when 45 => TXTSNFTSCOMCLK_BINARY <= "00101101"; + when 46 => TXTSNFTSCOMCLK_BINARY <= "00101110"; + when 47 => TXTSNFTSCOMCLK_BINARY <= "00101111"; + when 48 => TXTSNFTSCOMCLK_BINARY <= "00110000"; + when 49 => TXTSNFTSCOMCLK_BINARY <= "00110001"; + when 50 => TXTSNFTSCOMCLK_BINARY <= "00110010"; + when 51 => TXTSNFTSCOMCLK_BINARY <= "00110011"; + when 52 => TXTSNFTSCOMCLK_BINARY <= "00110100"; + when 53 => TXTSNFTSCOMCLK_BINARY <= "00110101"; + when 54 => TXTSNFTSCOMCLK_BINARY <= "00110110"; + when 55 => TXTSNFTSCOMCLK_BINARY <= "00110111"; + when 56 => TXTSNFTSCOMCLK_BINARY <= "00111000"; + when 57 => TXTSNFTSCOMCLK_BINARY <= "00111001"; + when 58 => TXTSNFTSCOMCLK_BINARY <= "00111010"; + when 59 => TXTSNFTSCOMCLK_BINARY <= "00111011"; + when 60 => TXTSNFTSCOMCLK_BINARY <= "00111100"; + when 61 => TXTSNFTSCOMCLK_BINARY <= "00111101"; + when 62 => TXTSNFTSCOMCLK_BINARY <= "00111110"; + when 63 => TXTSNFTSCOMCLK_BINARY <= "00111111"; + when 64 => TXTSNFTSCOMCLK_BINARY <= "01000000"; + when 65 => TXTSNFTSCOMCLK_BINARY <= "01000001"; + when 66 => TXTSNFTSCOMCLK_BINARY <= "01000010"; + when 67 => TXTSNFTSCOMCLK_BINARY <= "01000011"; + when 68 => TXTSNFTSCOMCLK_BINARY <= "01000100"; + when 69 => TXTSNFTSCOMCLK_BINARY <= "01000101"; + when 70 => TXTSNFTSCOMCLK_BINARY <= "01000110"; + when 71 => TXTSNFTSCOMCLK_BINARY <= "01000111"; + when 72 => TXTSNFTSCOMCLK_BINARY <= "01001000"; + when 73 => TXTSNFTSCOMCLK_BINARY <= "01001001"; + when 74 => TXTSNFTSCOMCLK_BINARY <= "01001010"; + when 75 => TXTSNFTSCOMCLK_BINARY <= "01001011"; + when 76 => TXTSNFTSCOMCLK_BINARY <= "01001100"; + when 77 => TXTSNFTSCOMCLK_BINARY <= "01001101"; + when 78 => TXTSNFTSCOMCLK_BINARY <= "01001110"; + when 79 => TXTSNFTSCOMCLK_BINARY <= "01001111"; + when 80 => TXTSNFTSCOMCLK_BINARY <= "01010000"; + when 81 => TXTSNFTSCOMCLK_BINARY <= "01010001"; + when 82 => TXTSNFTSCOMCLK_BINARY <= "01010010"; + when 83 => TXTSNFTSCOMCLK_BINARY <= "01010011"; + when 84 => TXTSNFTSCOMCLK_BINARY <= "01010100"; + when 85 => TXTSNFTSCOMCLK_BINARY <= "01010101"; + when 86 => TXTSNFTSCOMCLK_BINARY <= "01010110"; + when 87 => TXTSNFTSCOMCLK_BINARY <= "01010111"; + when 88 => TXTSNFTSCOMCLK_BINARY <= "01011000"; + when 89 => TXTSNFTSCOMCLK_BINARY <= "01011001"; + when 90 => TXTSNFTSCOMCLK_BINARY <= "01011010"; + when 91 => TXTSNFTSCOMCLK_BINARY <= "01011011"; + when 92 => TXTSNFTSCOMCLK_BINARY <= "01011100"; + when 93 => TXTSNFTSCOMCLK_BINARY <= "01011101"; + when 94 => TXTSNFTSCOMCLK_BINARY <= "01011110"; + when 95 => TXTSNFTSCOMCLK_BINARY <= "01011111"; + when 96 => TXTSNFTSCOMCLK_BINARY <= "01100000"; + when 97 => TXTSNFTSCOMCLK_BINARY <= "01100001"; + when 98 => TXTSNFTSCOMCLK_BINARY <= "01100010"; + when 99 => TXTSNFTSCOMCLK_BINARY <= "01100011"; + when 100 => TXTSNFTSCOMCLK_BINARY <= "01100100"; + when 101 => TXTSNFTSCOMCLK_BINARY <= "01100101"; + when 102 => TXTSNFTSCOMCLK_BINARY <= "01100110"; + when 103 => TXTSNFTSCOMCLK_BINARY <= "01100111"; + when 104 => TXTSNFTSCOMCLK_BINARY <= "01101000"; + when 105 => TXTSNFTSCOMCLK_BINARY <= "01101001"; + when 106 => TXTSNFTSCOMCLK_BINARY <= "01101010"; + when 107 => TXTSNFTSCOMCLK_BINARY <= "01101011"; + when 108 => TXTSNFTSCOMCLK_BINARY <= "01101100"; + when 109 => TXTSNFTSCOMCLK_BINARY <= "01101101"; + when 110 => TXTSNFTSCOMCLK_BINARY <= "01101110"; + when 111 => TXTSNFTSCOMCLK_BINARY <= "01101111"; + when 112 => TXTSNFTSCOMCLK_BINARY <= "01110000"; + when 113 => TXTSNFTSCOMCLK_BINARY <= "01110001"; + when 114 => TXTSNFTSCOMCLK_BINARY <= "01110010"; + when 115 => TXTSNFTSCOMCLK_BINARY <= "01110011"; + when 116 => TXTSNFTSCOMCLK_BINARY <= "01110100"; + when 117 => TXTSNFTSCOMCLK_BINARY <= "01110101"; + when 118 => TXTSNFTSCOMCLK_BINARY <= "01110110"; + when 119 => TXTSNFTSCOMCLK_BINARY <= "01110111"; + when 120 => TXTSNFTSCOMCLK_BINARY <= "01111000"; + when 121 => TXTSNFTSCOMCLK_BINARY <= "01111001"; + when 122 => TXTSNFTSCOMCLK_BINARY <= "01111010"; + when 123 => TXTSNFTSCOMCLK_BINARY <= "01111011"; + when 124 => TXTSNFTSCOMCLK_BINARY <= "01111100"; + when 125 => TXTSNFTSCOMCLK_BINARY <= "01111101"; + when 126 => TXTSNFTSCOMCLK_BINARY <= "01111110"; + when 127 => TXTSNFTSCOMCLK_BINARY <= "01111111"; + when 128 => TXTSNFTSCOMCLK_BINARY <= "10000000"; + when 129 => TXTSNFTSCOMCLK_BINARY <= "10000001"; + when 130 => TXTSNFTSCOMCLK_BINARY <= "10000010"; + when 131 => TXTSNFTSCOMCLK_BINARY <= "10000011"; + when 132 => TXTSNFTSCOMCLK_BINARY <= "10000100"; + when 133 => TXTSNFTSCOMCLK_BINARY <= "10000101"; + when 134 => TXTSNFTSCOMCLK_BINARY <= "10000110"; + when 135 => TXTSNFTSCOMCLK_BINARY <= "10000111"; + when 136 => TXTSNFTSCOMCLK_BINARY <= "10001000"; + when 137 => TXTSNFTSCOMCLK_BINARY <= "10001001"; + when 138 => TXTSNFTSCOMCLK_BINARY <= "10001010"; + when 139 => TXTSNFTSCOMCLK_BINARY <= "10001011"; + when 140 => TXTSNFTSCOMCLK_BINARY <= "10001100"; + when 141 => TXTSNFTSCOMCLK_BINARY <= "10001101"; + when 142 => TXTSNFTSCOMCLK_BINARY <= "10001110"; + when 143 => TXTSNFTSCOMCLK_BINARY <= "10001111"; + when 144 => TXTSNFTSCOMCLK_BINARY <= "10010000"; + when 145 => TXTSNFTSCOMCLK_BINARY <= "10010001"; + when 146 => TXTSNFTSCOMCLK_BINARY <= "10010010"; + when 147 => TXTSNFTSCOMCLK_BINARY <= "10010011"; + when 148 => TXTSNFTSCOMCLK_BINARY <= "10010100"; + when 149 => TXTSNFTSCOMCLK_BINARY <= "10010101"; + when 150 => TXTSNFTSCOMCLK_BINARY <= "10010110"; + when 151 => TXTSNFTSCOMCLK_BINARY <= "10010111"; + when 152 => TXTSNFTSCOMCLK_BINARY <= "10011000"; + when 153 => TXTSNFTSCOMCLK_BINARY <= "10011001"; + when 154 => TXTSNFTSCOMCLK_BINARY <= "10011010"; + when 155 => TXTSNFTSCOMCLK_BINARY <= "10011011"; + when 156 => TXTSNFTSCOMCLK_BINARY <= "10011100"; + when 157 => TXTSNFTSCOMCLK_BINARY <= "10011101"; + when 158 => TXTSNFTSCOMCLK_BINARY <= "10011110"; + when 159 => TXTSNFTSCOMCLK_BINARY <= "10011111"; + when 160 => TXTSNFTSCOMCLK_BINARY <= "10100000"; + when 161 => TXTSNFTSCOMCLK_BINARY <= "10100001"; + when 162 => TXTSNFTSCOMCLK_BINARY <= "10100010"; + when 163 => TXTSNFTSCOMCLK_BINARY <= "10100011"; + when 164 => TXTSNFTSCOMCLK_BINARY <= "10100100"; + when 165 => TXTSNFTSCOMCLK_BINARY <= "10100101"; + when 166 => TXTSNFTSCOMCLK_BINARY <= "10100110"; + when 167 => TXTSNFTSCOMCLK_BINARY <= "10100111"; + when 168 => TXTSNFTSCOMCLK_BINARY <= "10101000"; + when 169 => TXTSNFTSCOMCLK_BINARY <= "10101001"; + when 170 => TXTSNFTSCOMCLK_BINARY <= "10101010"; + when 171 => TXTSNFTSCOMCLK_BINARY <= "10101011"; + when 172 => TXTSNFTSCOMCLK_BINARY <= "10101100"; + when 173 => TXTSNFTSCOMCLK_BINARY <= "10101101"; + when 174 => TXTSNFTSCOMCLK_BINARY <= "10101110"; + when 175 => TXTSNFTSCOMCLK_BINARY <= "10101111"; + when 176 => TXTSNFTSCOMCLK_BINARY <= "10110000"; + when 177 => TXTSNFTSCOMCLK_BINARY <= "10110001"; + when 178 => TXTSNFTSCOMCLK_BINARY <= "10110010"; + when 179 => TXTSNFTSCOMCLK_BINARY <= "10110011"; + when 180 => TXTSNFTSCOMCLK_BINARY <= "10110100"; + when 181 => TXTSNFTSCOMCLK_BINARY <= "10110101"; + when 182 => TXTSNFTSCOMCLK_BINARY <= "10110110"; + when 183 => TXTSNFTSCOMCLK_BINARY <= "10110111"; + when 184 => TXTSNFTSCOMCLK_BINARY <= "10111000"; + when 185 => TXTSNFTSCOMCLK_BINARY <= "10111001"; + when 186 => TXTSNFTSCOMCLK_BINARY <= "10111010"; + when 187 => TXTSNFTSCOMCLK_BINARY <= "10111011"; + when 188 => TXTSNFTSCOMCLK_BINARY <= "10111100"; + when 189 => TXTSNFTSCOMCLK_BINARY <= "10111101"; + when 190 => TXTSNFTSCOMCLK_BINARY <= "10111110"; + when 191 => TXTSNFTSCOMCLK_BINARY <= "10111111"; + when 192 => TXTSNFTSCOMCLK_BINARY <= "11000000"; + when 193 => TXTSNFTSCOMCLK_BINARY <= "11000001"; + when 194 => TXTSNFTSCOMCLK_BINARY <= "11000010"; + when 195 => TXTSNFTSCOMCLK_BINARY <= "11000011"; + when 196 => TXTSNFTSCOMCLK_BINARY <= "11000100"; + when 197 => TXTSNFTSCOMCLK_BINARY <= "11000101"; + when 198 => TXTSNFTSCOMCLK_BINARY <= "11000110"; + when 199 => TXTSNFTSCOMCLK_BINARY <= "11000111"; + when 200 => TXTSNFTSCOMCLK_BINARY <= "11001000"; + when 201 => TXTSNFTSCOMCLK_BINARY <= "11001001"; + when 202 => TXTSNFTSCOMCLK_BINARY <= "11001010"; + when 203 => TXTSNFTSCOMCLK_BINARY <= "11001011"; + when 204 => TXTSNFTSCOMCLK_BINARY <= "11001100"; + when 205 => TXTSNFTSCOMCLK_BINARY <= "11001101"; + when 206 => TXTSNFTSCOMCLK_BINARY <= "11001110"; + when 207 => TXTSNFTSCOMCLK_BINARY <= "11001111"; + when 208 => TXTSNFTSCOMCLK_BINARY <= "11010000"; + when 209 => TXTSNFTSCOMCLK_BINARY <= "11010001"; + when 210 => TXTSNFTSCOMCLK_BINARY <= "11010010"; + when 211 => TXTSNFTSCOMCLK_BINARY <= "11010011"; + when 212 => TXTSNFTSCOMCLK_BINARY <= "11010100"; + when 213 => TXTSNFTSCOMCLK_BINARY <= "11010101"; + when 214 => TXTSNFTSCOMCLK_BINARY <= "11010110"; + when 215 => TXTSNFTSCOMCLK_BINARY <= "11010111"; + when 216 => TXTSNFTSCOMCLK_BINARY <= "11011000"; + when 217 => TXTSNFTSCOMCLK_BINARY <= "11011001"; + when 218 => TXTSNFTSCOMCLK_BINARY <= "11011010"; + when 219 => TXTSNFTSCOMCLK_BINARY <= "11011011"; + when 220 => TXTSNFTSCOMCLK_BINARY <= "11011100"; + when 221 => TXTSNFTSCOMCLK_BINARY <= "11011101"; + when 222 => TXTSNFTSCOMCLK_BINARY <= "11011110"; + when 223 => TXTSNFTSCOMCLK_BINARY <= "11011111"; + when 224 => TXTSNFTSCOMCLK_BINARY <= "11100000"; + when 225 => TXTSNFTSCOMCLK_BINARY <= "11100001"; + when 226 => TXTSNFTSCOMCLK_BINARY <= "11100010"; + when 227 => TXTSNFTSCOMCLK_BINARY <= "11100011"; + when 228 => TXTSNFTSCOMCLK_BINARY <= "11100100"; + when 229 => TXTSNFTSCOMCLK_BINARY <= "11100101"; + when 230 => TXTSNFTSCOMCLK_BINARY <= "11100110"; + when 231 => TXTSNFTSCOMCLK_BINARY <= "11100111"; + when 232 => TXTSNFTSCOMCLK_BINARY <= "11101000"; + when 233 => TXTSNFTSCOMCLK_BINARY <= "11101001"; + when 234 => TXTSNFTSCOMCLK_BINARY <= "11101010"; + when 235 => TXTSNFTSCOMCLK_BINARY <= "11101011"; + when 236 => TXTSNFTSCOMCLK_BINARY <= "11101100"; + when 237 => TXTSNFTSCOMCLK_BINARY <= "11101101"; + when 238 => TXTSNFTSCOMCLK_BINARY <= "11101110"; + when 239 => TXTSNFTSCOMCLK_BINARY <= "11101111"; + when 240 => TXTSNFTSCOMCLK_BINARY <= "11110000"; + when 241 => TXTSNFTSCOMCLK_BINARY <= "11110001"; + when 242 => TXTSNFTSCOMCLK_BINARY <= "11110010"; + when 243 => TXTSNFTSCOMCLK_BINARY <= "11110011"; + when 244 => TXTSNFTSCOMCLK_BINARY <= "11110100"; + when 245 => TXTSNFTSCOMCLK_BINARY <= "11110101"; + when 246 => TXTSNFTSCOMCLK_BINARY <= "11110110"; + when 247 => TXTSNFTSCOMCLK_BINARY <= "11110111"; + when 248 => TXTSNFTSCOMCLK_BINARY <= "11111000"; + when 249 => TXTSNFTSCOMCLK_BINARY <= "11111001"; + when 250 => TXTSNFTSCOMCLK_BINARY <= "11111010"; + when 251 => TXTSNFTSCOMCLK_BINARY <= "11111011"; + when 252 => TXTSNFTSCOMCLK_BINARY <= "11111100"; + when 253 => TXTSNFTSCOMCLK_BINARY <= "11111101"; + when 254 => TXTSNFTSCOMCLK_BINARY <= "11111110"; + when 255 => TXTSNFTSCOMCLK_BINARY <= "11111111"; + when others => assert FALSE report "Error : TXTSNFTSCOMCLK is not in range 0...255." severity error; + end case; + case RETRYRAMREADLATENCY is + when 0 => RETRYRAMREADLATENCY_BINARY <= "000"; + when 1 => RETRYRAMREADLATENCY_BINARY <= "001"; + when 2 => RETRYRAMREADLATENCY_BINARY <= "010"; + when 3 => RETRYRAMREADLATENCY_BINARY <= "011"; + when 4 => RETRYRAMREADLATENCY_BINARY <= "100"; + when 5 => RETRYRAMREADLATENCY_BINARY <= "101"; + when 6 => RETRYRAMREADLATENCY_BINARY <= "110"; + when 7 => RETRYRAMREADLATENCY_BINARY <= "111"; + when others => assert FALSE report "Error : RETRYRAMREADLATENCY is not in range 0...7." severity error; + end case; + case RETRYRAMWRITELATENCY is + when 0 => RETRYRAMWRITELATENCY_BINARY <= "000"; + when 1 => RETRYRAMWRITELATENCY_BINARY <= "001"; + when 2 => RETRYRAMWRITELATENCY_BINARY <= "010"; + when 3 => RETRYRAMWRITELATENCY_BINARY <= "011"; + when 4 => RETRYRAMWRITELATENCY_BINARY <= "100"; + when 5 => RETRYRAMWRITELATENCY_BINARY <= "101"; + when 6 => RETRYRAMWRITELATENCY_BINARY <= "110"; + when 7 => RETRYRAMWRITELATENCY_BINARY <= "111"; + when others => assert FALSE report "Error : RETRYRAMWRITELATENCY is not in range 0...7." severity error; + end case; + case RETRYRAMWIDTH is + when 0 => RETRYRAMWIDTH_BINARY <= '0'; + when 1 => RETRYRAMWIDTH_BINARY <= '1'; + when others => assert FALSE report "Error : RETRYRAMWIDTH is not in range 0...1." severity error; + end case; + case RETRYWRITEPIPE is + when FALSE => RETRYWRITEPIPE_BINARY <= '0'; + when TRUE => RETRYWRITEPIPE_BINARY <= '1'; + when others => assert FALSE report "Error : RETRYWRITEPIPE is neither TRUE nor FALSE." severity error; + end case; + case RETRYREADADDRPIPE is + when FALSE => RETRYREADADDRPIPE_BINARY <= '0'; + when TRUE => RETRYREADADDRPIPE_BINARY <= '1'; + when others => assert FALSE report "Error : RETRYREADADDRPIPE is neither TRUE nor FALSE." severity error; + end case; + case RETRYREADDATAPIPE is + when FALSE => RETRYREADDATAPIPE_BINARY <= '0'; + when TRUE => RETRYREADDATAPIPE_BINARY <= '1'; + when others => assert FALSE report "Error : RETRYREADDATAPIPE is neither TRUE nor FALSE." severity error; + end case; + case XLINKSUPPORTED is + when FALSE => XLINKSUPPORTED_BINARY <= '0'; + when TRUE => XLINKSUPPORTED_BINARY <= '1'; + when others => assert FALSE report "Error : XLINKSUPPORTED is neither TRUE nor FALSE." severity error; + end case; + case INFINITECOMPLETIONS is + when FALSE => INFINITECOMPLETIONS_BINARY <= '0'; + when TRUE => INFINITECOMPLETIONS_BINARY <= '1'; + when others => assert FALSE report "Error : INFINITECOMPLETIONS is neither TRUE nor FALSE." severity error; + end case; + case TLRAMREADLATENCY is + when 0 => TLRAMREADLATENCY_BINARY <= "000"; + when 1 => TLRAMREADLATENCY_BINARY <= "001"; + when 2 => TLRAMREADLATENCY_BINARY <= "010"; + when 3 => TLRAMREADLATENCY_BINARY <= "011"; + when 4 => TLRAMREADLATENCY_BINARY <= "100"; + when 5 => TLRAMREADLATENCY_BINARY <= "101"; + when 6 => TLRAMREADLATENCY_BINARY <= "110"; + when 7 => TLRAMREADLATENCY_BINARY <= "111"; + when others => assert FALSE report "Error : TLRAMREADLATENCY is not in range 0...7." severity error; + end case; + case TLRAMWRITELATENCY is + when 0 => TLRAMWRITELATENCY_BINARY <= "000"; + when 1 => TLRAMWRITELATENCY_BINARY <= "001"; + when 2 => TLRAMWRITELATENCY_BINARY <= "010"; + when 3 => TLRAMWRITELATENCY_BINARY <= "011"; + when 4 => TLRAMWRITELATENCY_BINARY <= "100"; + when 5 => TLRAMWRITELATENCY_BINARY <= "101"; + when 6 => TLRAMWRITELATENCY_BINARY <= "110"; + when 7 => TLRAMWRITELATENCY_BINARY <= "111"; + when others => assert FALSE report "Error : TLRAMWRITELATENCY is not in range 0...7." severity error; + end case; + case TLRAMWIDTH is + when 0 => TLRAMWIDTH_BINARY <= '0'; + when 1 => TLRAMWIDTH_BINARY <= '1'; + when others => assert FALSE report "Error : TLRAMWIDTH is not in range 0...1." severity error; + end case; + case RAMSHARETXRX is + when FALSE => RAMSHARETXRX_BINARY <= '0'; + when TRUE => RAMSHARETXRX_BINARY <= '1'; + when others => assert FALSE report "Error : RAMSHARETXRX is neither TRUE nor FALSE." severity error; + end case; + case L0SEXITLATENCY is + when 0 => L0SEXITLATENCY_BINARY <= "000"; + when 1 => L0SEXITLATENCY_BINARY <= "001"; + when 2 => L0SEXITLATENCY_BINARY <= "010"; + when 3 => L0SEXITLATENCY_BINARY <= "011"; + when 4 => L0SEXITLATENCY_BINARY <= "100"; + when 5 => L0SEXITLATENCY_BINARY <= "101"; + when 6 => L0SEXITLATENCY_BINARY <= "110"; + when 7 => L0SEXITLATENCY_BINARY <= "111"; + when others => assert FALSE report "Error : L0SEXITLATENCY is not in range 0...7." severity error; + end case; + case L0SEXITLATENCYCOMCLK is + when 0 => L0SEXITLATENCYCOMCLK_BINARY <= "000"; + when 1 => L0SEXITLATENCYCOMCLK_BINARY <= "001"; + when 2 => L0SEXITLATENCYCOMCLK_BINARY <= "010"; + when 3 => L0SEXITLATENCYCOMCLK_BINARY <= "011"; + when 4 => L0SEXITLATENCYCOMCLK_BINARY <= "100"; + when 5 => L0SEXITLATENCYCOMCLK_BINARY <= "101"; + when 6 => L0SEXITLATENCYCOMCLK_BINARY <= "110"; + when 7 => L0SEXITLATENCYCOMCLK_BINARY <= "111"; + when others => assert FALSE report "Error : L0SEXITLATENCYCOMCLK is not in range 0...7." severity error; + end case; + case L1EXITLATENCY is + when 0 => L1EXITLATENCY_BINARY <= "000"; + when 1 => L1EXITLATENCY_BINARY <= "001"; + when 2 => L1EXITLATENCY_BINARY <= "010"; + when 3 => L1EXITLATENCY_BINARY <= "011"; + when 4 => L1EXITLATENCY_BINARY <= "100"; + when 5 => L1EXITLATENCY_BINARY <= "101"; + when 6 => L1EXITLATENCY_BINARY <= "110"; + when 7 => L1EXITLATENCY_BINARY <= "111"; + when others => assert FALSE report "Error : L1EXITLATENCY is not in range 0...7." severity error; + end case; + case L1EXITLATENCYCOMCLK is + when 0 => L1EXITLATENCYCOMCLK_BINARY <= "000"; + when 1 => L1EXITLATENCYCOMCLK_BINARY <= "001"; + when 2 => L1EXITLATENCYCOMCLK_BINARY <= "010"; + when 3 => L1EXITLATENCYCOMCLK_BINARY <= "011"; + when 4 => L1EXITLATENCYCOMCLK_BINARY <= "100"; + when 5 => L1EXITLATENCYCOMCLK_BINARY <= "101"; + when 6 => L1EXITLATENCYCOMCLK_BINARY <= "110"; + when 7 => L1EXITLATENCYCOMCLK_BINARY <= "111"; + when others => assert FALSE report "Error : L1EXITLATENCYCOMCLK is not in range 0...7." severity error; + end case; + case DUALCORESLAVE is + when FALSE => DUALCORESLAVE_BINARY <= '0'; + when TRUE => DUALCORESLAVE_BINARY <= '1'; + when others => assert FALSE report "Error : DUALCORESLAVE is neither TRUE nor FALSE." severity error; + end case; + case DUALCOREENABLE is + when FALSE => DUALCOREENABLE_BINARY <= '0'; + when TRUE => DUALCOREENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : DUALCOREENABLE is neither TRUE nor FALSE." severity error; + end case; + case DUALROLECFGCNTRLROOTEPN is + when 0 => DUALROLECFGCNTRLROOTEPN_BINARY <= '0'; + when 1 => DUALROLECFGCNTRLROOTEPN_BINARY <= '1'; + when others => assert FALSE report "Error : DUALROLECFGCNTRLROOTEPN is not in range 0...1." severity error; + end case; + case RXREADADDRPIPE is + when FALSE => RXREADADDRPIPE_BINARY <= '0'; + when TRUE => RXREADADDRPIPE_BINARY <= '1'; + when others => assert FALSE report "Error : RXREADADDRPIPE is neither TRUE nor FALSE." severity error; + end case; + case RXREADDATAPIPE is + when FALSE => RXREADDATAPIPE_BINARY <= '0'; + when TRUE => RXREADDATAPIPE_BINARY <= '1'; + when others => assert FALSE report "Error : RXREADDATAPIPE is neither TRUE nor FALSE." severity error; + end case; + case TXWRITEPIPE is + when FALSE => TXWRITEPIPE_BINARY <= '0'; + when TRUE => TXWRITEPIPE_BINARY <= '1'; + when others => assert FALSE report "Error : TXWRITEPIPE is neither TRUE nor FALSE." severity error; + end case; + case TXREADADDRPIPE is + when FALSE => TXREADADDRPIPE_BINARY <= '0'; + when TRUE => TXREADADDRPIPE_BINARY <= '1'; + when others => assert FALSE report "Error : TXREADADDRPIPE is neither TRUE nor FALSE." severity error; + end case; + case TXREADDATAPIPE is + when FALSE => TXREADDATAPIPE_BINARY <= '0'; + when TRUE => TXREADDATAPIPE_BINARY <= '1'; + when others => assert FALSE report "Error : TXREADDATAPIPE is neither TRUE nor FALSE." severity error; + end case; + case RXWRITEPIPE is + when FALSE => RXWRITEPIPE_BINARY <= '0'; + when TRUE => RXWRITEPIPE_BINARY <= '1'; + when others => assert FALSE report "Error : RXWRITEPIPE is neither TRUE nor FALSE." severity error; + end case; + case LLKBYPASS is + when FALSE => LLKBYPASS_BINARY <= '0'; + when TRUE => LLKBYPASS_BINARY <= '1'; + when others => assert FALSE report "Error : LLKBYPASS is neither TRUE nor FALSE." severity error; + end case; + case PCIEREVISION is + when 0 => PCIEREVISION_BINARY <= '0'; + when 1 => PCIEREVISION_BINARY <= '1'; + when others => assert FALSE report "Error : PCIEREVISION is not in range 0...1." severity error; + end case; + case SELECTDLLIF is + when FALSE => SELECTDLLIF_BINARY <= '0'; + when TRUE => SELECTDLLIF_BINARY <= '1'; + when others => assert FALSE report "Error : SELECTDLLIF is neither TRUE nor FALSE." severity error; + end case; + case SELECTASMODE is + when FALSE => SELECTASMODE_BINARY <= '0'; + when TRUE => SELECTASMODE_BINARY <= '1'; + when others => assert FALSE report "Error : SELECTASMODE is neither TRUE nor FALSE." severity error; + end case; + case ISSWITCH is + when FALSE => ISSWITCH_BINARY <= '0'; + when TRUE => ISSWITCH_BINARY <= '1'; + when others => assert FALSE report "Error : ISSWITCH is neither TRUE nor FALSE." severity error; + end case; + case UPSTREAMFACING is + when FALSE => UPSTREAMFACING_BINARY <= '0'; + when TRUE => UPSTREAMFACING_BINARY <= '1'; + when others => assert FALSE report "Error : UPSTREAMFACING is neither TRUE nor FALSE." severity error; + end case; + case SLOTIMPLEMENTED is + when FALSE => SLOTIMPLEMENTED_BINARY <= '0'; + when TRUE => SLOTIMPLEMENTED_BINARY <= '1'; + when others => assert FALSE report "Error : SLOTIMPLEMENTED is neither TRUE nor FALSE." severity error; + end case; + case BAR0EXIST is + when FALSE => BAR0EXIST_BINARY <= '0'; + when TRUE => BAR0EXIST_BINARY <= '1'; + when others => assert FALSE report "Error : BAR0EXIST is neither TRUE nor FALSE." severity error; + end case; + case BAR1EXIST is + when FALSE => BAR1EXIST_BINARY <= '0'; + when TRUE => BAR1EXIST_BINARY <= '1'; + when others => assert FALSE report "Error : BAR1EXIST is neither TRUE nor FALSE." severity error; + end case; + case BAR2EXIST is + when FALSE => BAR2EXIST_BINARY <= '0'; + when TRUE => BAR2EXIST_BINARY <= '1'; + when others => assert FALSE report "Error : BAR2EXIST is neither TRUE nor FALSE." severity error; + end case; + case BAR3EXIST is + when FALSE => BAR3EXIST_BINARY <= '0'; + when TRUE => BAR3EXIST_BINARY <= '1'; + when others => assert FALSE report "Error : BAR3EXIST is neither TRUE nor FALSE." severity error; + end case; + case BAR4EXIST is + when FALSE => BAR4EXIST_BINARY <= '0'; + when TRUE => BAR4EXIST_BINARY <= '1'; + when others => assert FALSE report "Error : BAR4EXIST is neither TRUE nor FALSE." severity error; + end case; + case BAR5EXIST is + when FALSE => BAR5EXIST_BINARY <= '0'; + when TRUE => BAR5EXIST_BINARY <= '1'; + when others => assert FALSE report "Error : BAR5EXIST is neither TRUE nor FALSE." severity error; + end case; + case BAR0ADDRWIDTH is + when 0 => BAR0ADDRWIDTH_BINARY <= '0'; + when 1 => BAR0ADDRWIDTH_BINARY <= '1'; + when others => assert FALSE report "Error : BAR0ADDRWIDTH is not in range 0...1." severity error; + end case; + case BAR1ADDRWIDTH is + when 0 => BAR1ADDRWIDTH_BINARY <= '0'; + when 1 => BAR1ADDRWIDTH_BINARY <= '1'; + when others => assert FALSE report "Error : BAR1ADDRWIDTH is not in range 0...1." severity error; + end case; + case BAR2ADDRWIDTH is + when 0 => BAR2ADDRWIDTH_BINARY <= '0'; + when 1 => BAR2ADDRWIDTH_BINARY <= '1'; + when others => assert FALSE report "Error : BAR2ADDRWIDTH is not in range 0...1." severity error; + end case; + case BAR3ADDRWIDTH is + when 0 => BAR3ADDRWIDTH_BINARY <= '0'; + when 1 => BAR3ADDRWIDTH_BINARY <= '1'; + when others => assert FALSE report "Error : BAR3ADDRWIDTH is not in range 0...1." severity error; + end case; + case BAR4ADDRWIDTH is + when 0 => BAR4ADDRWIDTH_BINARY <= '0'; + when 1 => BAR4ADDRWIDTH_BINARY <= '1'; + when others => assert FALSE report "Error : BAR4ADDRWIDTH is not in range 0...1." severity error; + end case; + case BAR0PREFETCHABLE is + when FALSE => BAR0PREFETCHABLE_BINARY <= '0'; + when TRUE => BAR0PREFETCHABLE_BINARY <= '1'; + when others => assert FALSE report "Error : BAR0PREFETCHABLE is neither TRUE nor FALSE." severity error; + end case; + case BAR1PREFETCHABLE is + when FALSE => BAR1PREFETCHABLE_BINARY <= '0'; + when TRUE => BAR1PREFETCHABLE_BINARY <= '1'; + when others => assert FALSE report "Error : BAR1PREFETCHABLE is neither TRUE nor FALSE." severity error; + end case; + case BAR2PREFETCHABLE is + when FALSE => BAR2PREFETCHABLE_BINARY <= '0'; + when TRUE => BAR2PREFETCHABLE_BINARY <= '1'; + when others => assert FALSE report "Error : BAR2PREFETCHABLE is neither TRUE nor FALSE." severity error; + end case; + case BAR3PREFETCHABLE is + when FALSE => BAR3PREFETCHABLE_BINARY <= '0'; + when TRUE => BAR3PREFETCHABLE_BINARY <= '1'; + when others => assert FALSE report "Error : BAR3PREFETCHABLE is neither TRUE nor FALSE." severity error; + end case; + case BAR4PREFETCHABLE is + when FALSE => BAR4PREFETCHABLE_BINARY <= '0'; + when TRUE => BAR4PREFETCHABLE_BINARY <= '1'; + when others => assert FALSE report "Error : BAR4PREFETCHABLE is neither TRUE nor FALSE." severity error; + end case; + case BAR5PREFETCHABLE is + when FALSE => BAR5PREFETCHABLE_BINARY <= '0'; + when TRUE => BAR5PREFETCHABLE_BINARY <= '1'; + when others => assert FALSE report "Error : BAR5PREFETCHABLE is neither TRUE nor FALSE." severity error; + end case; + case BAR0IOMEMN is + when 0 => BAR0IOMEMN_BINARY <= '0'; + when 1 => BAR0IOMEMN_BINARY <= '1'; + when others => assert FALSE report "Error : BAR0IOMEMN is not in range 0...1." severity error; + end case; + case BAR1IOMEMN is + when 0 => BAR1IOMEMN_BINARY <= '0'; + when 1 => BAR1IOMEMN_BINARY <= '1'; + when others => assert FALSE report "Error : BAR1IOMEMN is not in range 0...1." severity error; + end case; + case BAR2IOMEMN is + when 0 => BAR2IOMEMN_BINARY <= '0'; + when 1 => BAR2IOMEMN_BINARY <= '1'; + when others => assert FALSE report "Error : BAR2IOMEMN is not in range 0...1." severity error; + end case; + case BAR3IOMEMN is + when 0 => BAR3IOMEMN_BINARY <= '0'; + when 1 => BAR3IOMEMN_BINARY <= '1'; + when others => assert FALSE report "Error : BAR3IOMEMN is not in range 0...1." severity error; + end case; + case BAR4IOMEMN is + when 0 => BAR4IOMEMN_BINARY <= '0'; + when 1 => BAR4IOMEMN_BINARY <= '1'; + when others => assert FALSE report "Error : BAR4IOMEMN is not in range 0...1." severity error; + end case; + case BAR5IOMEMN is + when 0 => BAR5IOMEMN_BINARY <= '0'; + when 1 => BAR5IOMEMN_BINARY <= '1'; + when others => assert FALSE report "Error : BAR5IOMEMN is not in range 0...1." severity error; + end case; + case XPMAXPAYLOAD is + when 0 => XPMAXPAYLOAD_BINARY <= "000"; + when 1 => XPMAXPAYLOAD_BINARY <= "001"; + when 2 => XPMAXPAYLOAD_BINARY <= "010"; + when 3 => XPMAXPAYLOAD_BINARY <= "011"; + when 4 => XPMAXPAYLOAD_BINARY <= "100"; + when 5 => XPMAXPAYLOAD_BINARY <= "101"; + when 6 => XPMAXPAYLOAD_BINARY <= "110"; + when 7 => XPMAXPAYLOAD_BINARY <= "111"; + when others => assert FALSE report "Error : XPMAXPAYLOAD is not in range 0...7." severity error; + end case; + case XPRCBCONTROL is + when 0 => XPRCBCONTROL_BINARY <= '0'; + when 1 => XPRCBCONTROL_BINARY <= '1'; + when others => assert FALSE report "Error : XPRCBCONTROL is not in range 0...1." severity error; + end case; + case LOWPRIORITYVCCOUNT is + when 0 => LOWPRIORITYVCCOUNT_BINARY <= "000"; + when 1 => LOWPRIORITYVCCOUNT_BINARY <= "001"; + when 2 => LOWPRIORITYVCCOUNT_BINARY <= "010"; + when 3 => LOWPRIORITYVCCOUNT_BINARY <= "011"; + when 4 => LOWPRIORITYVCCOUNT_BINARY <= "100"; + when 5 => LOWPRIORITYVCCOUNT_BINARY <= "101"; + when 6 => LOWPRIORITYVCCOUNT_BINARY <= "110"; + when 7 => LOWPRIORITYVCCOUNT_BINARY <= "111"; + when others => assert FALSE report "Error : LOWPRIORITYVCCOUNT is not in range 0...7." severity error; + end case; + case PMCAPABILITYDSI is + when FALSE => PMCAPABILITYDSI_BINARY <= '0'; + when TRUE => PMCAPABILITYDSI_BINARY <= '1'; + when others => assert FALSE report "Error : PMCAPABILITYDSI is neither TRUE nor FALSE." severity error; + end case; + case PMCAPABILITYD1SUPPORT is + when FALSE => PMCAPABILITYD1SUPPORT_BINARY <= '0'; + when TRUE => PMCAPABILITYD1SUPPORT_BINARY <= '1'; + when others => assert FALSE report "Error : PMCAPABILITYD1SUPPORT is neither TRUE nor FALSE." severity error; + end case; + case PMCAPABILITYD2SUPPORT is + when FALSE => PMCAPABILITYD2SUPPORT_BINARY <= '0'; + when TRUE => PMCAPABILITYD2SUPPORT_BINARY <= '1'; + when others => assert FALSE report "Error : PMCAPABILITYD2SUPPORT is neither TRUE nor FALSE." severity error; + end case; + case PMDATASCALE0 is + when 0 => PMDATASCALE0_BINARY <= "00"; + when 1 => PMDATASCALE0_BINARY <= "01"; + when 2 => PMDATASCALE0_BINARY <= "10"; + when 3 => PMDATASCALE0_BINARY <= "11"; + when others => assert FALSE report "Error : PMDATASCALE0 is not in range 0...3." severity error; + end case; + case PMDATASCALE1 is + when 0 => PMDATASCALE1_BINARY <= "00"; + when 1 => PMDATASCALE1_BINARY <= "01"; + when 2 => PMDATASCALE1_BINARY <= "10"; + when 3 => PMDATASCALE1_BINARY <= "11"; + when others => assert FALSE report "Error : PMDATASCALE1 is not in range 0...3." severity error; + end case; + case PMDATASCALE2 is + when 0 => PMDATASCALE2_BINARY <= "00"; + when 1 => PMDATASCALE2_BINARY <= "01"; + when 2 => PMDATASCALE2_BINARY <= "10"; + when 3 => PMDATASCALE2_BINARY <= "11"; + when others => assert FALSE report "Error : PMDATASCALE2 is not in range 0...3." severity error; + end case; + case PMDATASCALE3 is + when 0 => PMDATASCALE3_BINARY <= "00"; + when 1 => PMDATASCALE3_BINARY <= "01"; + when 2 => PMDATASCALE3_BINARY <= "10"; + when 3 => PMDATASCALE3_BINARY <= "11"; + when others => assert FALSE report "Error : PMDATASCALE3 is not in range 0...3." severity error; + end case; + case PMDATASCALE4 is + when 0 => PMDATASCALE4_BINARY <= "00"; + when 1 => PMDATASCALE4_BINARY <= "01"; + when 2 => PMDATASCALE4_BINARY <= "10"; + when 3 => PMDATASCALE4_BINARY <= "11"; + when others => assert FALSE report "Error : PMDATASCALE4 is not in range 0...3." severity error; + end case; + case PMDATASCALE5 is + when 0 => PMDATASCALE5_BINARY <= "00"; + when 1 => PMDATASCALE5_BINARY <= "01"; + when 2 => PMDATASCALE5_BINARY <= "10"; + when 3 => PMDATASCALE5_BINARY <= "11"; + when others => assert FALSE report "Error : PMDATASCALE5 is not in range 0...3." severity error; + end case; + case PMDATASCALE6 is + when 0 => PMDATASCALE6_BINARY <= "00"; + when 1 => PMDATASCALE6_BINARY <= "01"; + when 2 => PMDATASCALE6_BINARY <= "10"; + when 3 => PMDATASCALE6_BINARY <= "11"; + when others => assert FALSE report "Error : PMDATASCALE6 is not in range 0...3." severity error; + end case; + case PMDATASCALE7 is + when 0 => PMDATASCALE7_BINARY <= "00"; + when 1 => PMDATASCALE7_BINARY <= "01"; + when 2 => PMDATASCALE7_BINARY <= "10"; + when 3 => PMDATASCALE7_BINARY <= "11"; + when others => assert FALSE report "Error : PMDATASCALE7 is not in range 0...3." severity error; + end case; + case PMDATASCALE8 is + when 0 => PMDATASCALE8_BINARY <= "00"; + when 1 => PMDATASCALE8_BINARY <= "01"; + when 2 => PMDATASCALE8_BINARY <= "10"; + when 3 => PMDATASCALE8_BINARY <= "11"; + when others => assert FALSE report "Error : PMDATASCALE8 is not in range 0...3." severity error; + end case; + case PCIECAPABILITYSLOTIMPL is + when FALSE => PCIECAPABILITYSLOTIMPL_BINARY <= '0'; + when TRUE => PCIECAPABILITYSLOTIMPL_BINARY <= '1'; + when others => assert FALSE report "Error : PCIECAPABILITYSLOTIMPL is neither TRUE nor FALSE." severity error; + end case; + case LINKSTATUSSLOTCLOCKCONFIG is + when FALSE => LINKSTATUSSLOTCLOCKCONFIG_BINARY <= '0'; + when TRUE => LINKSTATUSSLOTCLOCKCONFIG_BINARY <= '1'; + when others => assert FALSE report "Error : LINKSTATUSSLOTCLOCKCONFIG is neither TRUE nor FALSE." severity error; + end case; + case SLOTCAPABILITYATTBUTTONPRESENT is + when FALSE => SLOTCAPABILITYATTBUTTONPRESENT_BINARY <= '0'; + when TRUE => SLOTCAPABILITYATTBUTTONPRESENT_BINARY <= '1'; + when others => assert FALSE report "Error : SLOTCAPABILITYATTBUTTONPRESENT is neither TRUE nor FALSE." severity error; + end case; + case SLOTCAPABILITYPOWERCONTROLLERPRESENT is + when FALSE => SLOTCAPABILITYPOWERCONTROLLERPRESENT_BINARY <= '0'; + when TRUE => SLOTCAPABILITYPOWERCONTROLLERPRESENT_BINARY <= '1'; + when others => assert FALSE report "Error : SLOTCAPABILITYPOWERCONTROLLERPRESENT is neither TRUE nor FALSE." severity error; + end case; + case SLOTCAPABILITYMSLSENSORPRESENT is + when FALSE => SLOTCAPABILITYMSLSENSORPRESENT_BINARY <= '0'; + when TRUE => SLOTCAPABILITYMSLSENSORPRESENT_BINARY <= '1'; + when others => assert FALSE report "Error : SLOTCAPABILITYMSLSENSORPRESENT is neither TRUE nor FALSE." severity error; + end case; + case SLOTCAPABILITYATTINDICATORPRESENT is + when FALSE => SLOTCAPABILITYATTINDICATORPRESENT_BINARY <= '0'; + when TRUE => SLOTCAPABILITYATTINDICATORPRESENT_BINARY <= '1'; + when others => assert FALSE report "Error : SLOTCAPABILITYATTINDICATORPRESENT is neither TRUE nor FALSE." severity error; + end case; + case SLOTCAPABILITYPOWERINDICATORPRESENT is + when FALSE => SLOTCAPABILITYPOWERINDICATORPRESENT_BINARY <= '0'; + when TRUE => SLOTCAPABILITYPOWERINDICATORPRESENT_BINARY <= '1'; + when others => assert FALSE report "Error : SLOTCAPABILITYPOWERINDICATORPRESENT is neither TRUE nor FALSE." severity error; + end case; + case SLOTCAPABILITYHOTPLUGSURPRISE is + when FALSE => SLOTCAPABILITYHOTPLUGSURPRISE_BINARY <= '0'; + when TRUE => SLOTCAPABILITYHOTPLUGSURPRISE_BINARY <= '1'; + when others => assert FALSE report "Error : SLOTCAPABILITYHOTPLUGSURPRISE is neither TRUE nor FALSE." severity error; + end case; + case SLOTCAPABILITYHOTPLUGCAPABLE is + when FALSE => SLOTCAPABILITYHOTPLUGCAPABLE_BINARY <= '0'; + when TRUE => SLOTCAPABILITYHOTPLUGCAPABLE_BINARY <= '1'; + when others => assert FALSE report "Error : SLOTCAPABILITYHOTPLUGCAPABLE is neither TRUE nor FALSE." severity error; + end case; + case AERCAPABILITYECRCGENCAPABLE is + when FALSE => AERCAPABILITYECRCGENCAPABLE_BINARY <= '0'; + when TRUE => AERCAPABILITYECRCGENCAPABLE_BINARY <= '1'; + when others => assert FALSE report "Error : AERCAPABILITYECRCGENCAPABLE is neither TRUE nor FALSE." severity error; + end case; + case AERCAPABILITYECRCCHECKCAPABLE is + when FALSE => AERCAPABILITYECRCCHECKCAPABLE_BINARY <= '0'; + when TRUE => AERCAPABILITYECRCCHECKCAPABLE_BINARY <= '1'; + when others => assert FALSE report "Error : AERCAPABILITYECRCCHECKCAPABLE is neither TRUE nor FALSE." severity error; + end case; + case PBCAPABILITYSYSTEMALLOCATED is + when FALSE => PBCAPABILITYSYSTEMALLOCATED_BINARY <= '0'; + when TRUE => PBCAPABILITYSYSTEMALLOCATED_BINARY <= '1'; + when others => assert FALSE report "Error : PBCAPABILITYSYSTEMALLOCATED is neither TRUE nor FALSE." severity error; + end case; + case RESETMODE is + when FALSE => RESETMODE_BINARY <= '0'; + when TRUE => RESETMODE_BINARY <= '1'; + when others => assert FALSE report "Error : RESETMODE is neither TRUE nor FALSE." severity error; + end case; + case CLKDIVIDED is + when FALSE => CLKDIVIDED_BINARY <= '0'; + when TRUE => CLKDIVIDED_BINARY <= '1'; + when others => assert FALSE report "Error : CLKDIVIDED is neither TRUE nor FALSE." severity error; + end case; + wait; + end process INIPROC; + + TIMING : process + + + + variable PIPETXDATAL00_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL01_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL02_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL03_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL04_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL05_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL06_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL07_GlitchData : VitalGlitchDataType; + variable PIPETXDATAKL0_GlitchData : VitalGlitchDataType; + variable PIPETXELECIDLEL0_GlitchData : VitalGlitchDataType; + variable PIPETXDETECTRXLOOPBACKL0_GlitchData : VitalGlitchDataType; + variable PIPETXCOMPLIANCEL0_GlitchData : VitalGlitchDataType; + variable PIPERXPOLARITYL0_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL00_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL01_GlitchData : VitalGlitchDataType; + variable PIPEDESKEWLANESL0_GlitchData : VitalGlitchDataType; + variable PIPERESETL0_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL10_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL11_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL12_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL13_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL14_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL15_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL16_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL17_GlitchData : VitalGlitchDataType; + variable PIPETXDATAKL1_GlitchData : VitalGlitchDataType; + variable PIPETXELECIDLEL1_GlitchData : VitalGlitchDataType; + variable PIPETXDETECTRXLOOPBACKL1_GlitchData : VitalGlitchDataType; + variable PIPETXCOMPLIANCEL1_GlitchData : VitalGlitchDataType; + variable PIPERXPOLARITYL1_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL10_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL11_GlitchData : VitalGlitchDataType; + variable PIPEDESKEWLANESL1_GlitchData : VitalGlitchDataType; + variable PIPERESETL1_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL20_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL21_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL22_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL23_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL24_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL25_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL26_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL27_GlitchData : VitalGlitchDataType; + variable PIPETXDATAKL2_GlitchData : VitalGlitchDataType; + variable PIPETXELECIDLEL2_GlitchData : VitalGlitchDataType; + variable PIPETXDETECTRXLOOPBACKL2_GlitchData : VitalGlitchDataType; + variable PIPETXCOMPLIANCEL2_GlitchData : VitalGlitchDataType; + variable PIPERXPOLARITYL2_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL20_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL21_GlitchData : VitalGlitchDataType; + variable PIPEDESKEWLANESL2_GlitchData : VitalGlitchDataType; + variable PIPERESETL2_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL30_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL31_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL32_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL33_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL34_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL35_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL36_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL37_GlitchData : VitalGlitchDataType; + variable PIPETXDATAKL3_GlitchData : VitalGlitchDataType; + variable PIPETXELECIDLEL3_GlitchData : VitalGlitchDataType; + variable PIPETXDETECTRXLOOPBACKL3_GlitchData : VitalGlitchDataType; + variable PIPETXCOMPLIANCEL3_GlitchData : VitalGlitchDataType; + variable PIPERXPOLARITYL3_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL30_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL31_GlitchData : VitalGlitchDataType; + variable PIPEDESKEWLANESL3_GlitchData : VitalGlitchDataType; + variable PIPERESETL3_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL40_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL41_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL42_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL43_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL44_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL45_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL46_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL47_GlitchData : VitalGlitchDataType; + variable PIPETXDATAKL4_GlitchData : VitalGlitchDataType; + variable PIPETXELECIDLEL4_GlitchData : VitalGlitchDataType; + variable PIPETXDETECTRXLOOPBACKL4_GlitchData : VitalGlitchDataType; + variable PIPETXCOMPLIANCEL4_GlitchData : VitalGlitchDataType; + variable PIPERXPOLARITYL4_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL40_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL41_GlitchData : VitalGlitchDataType; + variable PIPEDESKEWLANESL4_GlitchData : VitalGlitchDataType; + variable PIPERESETL4_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL50_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL51_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL52_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL53_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL54_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL55_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL56_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL57_GlitchData : VitalGlitchDataType; + variable PIPETXDATAKL5_GlitchData : VitalGlitchDataType; + variable PIPETXELECIDLEL5_GlitchData : VitalGlitchDataType; + variable PIPETXDETECTRXLOOPBACKL5_GlitchData : VitalGlitchDataType; + variable PIPETXCOMPLIANCEL5_GlitchData : VitalGlitchDataType; + variable PIPERXPOLARITYL5_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL50_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL51_GlitchData : VitalGlitchDataType; + variable PIPEDESKEWLANESL5_GlitchData : VitalGlitchDataType; + variable PIPERESETL5_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL60_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL61_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL62_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL63_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL64_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL65_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL66_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL67_GlitchData : VitalGlitchDataType; + variable PIPETXDATAKL6_GlitchData : VitalGlitchDataType; + variable PIPETXELECIDLEL6_GlitchData : VitalGlitchDataType; + variable PIPETXDETECTRXLOOPBACKL6_GlitchData : VitalGlitchDataType; + variable PIPETXCOMPLIANCEL6_GlitchData : VitalGlitchDataType; + variable PIPERXPOLARITYL6_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL60_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL61_GlitchData : VitalGlitchDataType; + variable PIPEDESKEWLANESL6_GlitchData : VitalGlitchDataType; + variable PIPERESETL6_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL70_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL71_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL72_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL73_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL74_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL75_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL76_GlitchData : VitalGlitchDataType; + variable PIPETXDATAL77_GlitchData : VitalGlitchDataType; + variable PIPETXDATAKL7_GlitchData : VitalGlitchDataType; + variable PIPETXELECIDLEL7_GlitchData : VitalGlitchDataType; + variable PIPETXDETECTRXLOOPBACKL7_GlitchData : VitalGlitchDataType; + variable PIPETXCOMPLIANCEL7_GlitchData : VitalGlitchDataType; + variable PIPERXPOLARITYL7_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL70_GlitchData : VitalGlitchDataType; + variable PIPEPOWERDOWNL71_GlitchData : VitalGlitchDataType; + variable PIPEDESKEWLANESL7_GlitchData : VitalGlitchDataType; + variable PIPERESETL7_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA0_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA1_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA2_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA3_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA4_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA5_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA6_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA7_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA8_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA9_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA10_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA11_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA12_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA13_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA14_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA15_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA16_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA17_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA18_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA19_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA20_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA21_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA22_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA23_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA24_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA25_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA26_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA27_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA28_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA29_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA30_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA31_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA32_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA33_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA34_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA35_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA36_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA37_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA38_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA39_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA40_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA41_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA42_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA43_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA44_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA45_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA46_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA47_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA48_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA49_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA50_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA51_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA52_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA53_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA54_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA55_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA56_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA57_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA58_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA59_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA60_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA61_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA62_GlitchData : VitalGlitchDataType; + variable MIMRXBWDATA63_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD0_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD1_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD2_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD3_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD4_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD5_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD6_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD7_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD8_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD9_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD10_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD11_GlitchData : VitalGlitchDataType; + variable MIMRXBWADD12_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD0_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD1_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD2_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD3_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD4_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD5_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD6_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD7_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD8_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD9_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD10_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD11_GlitchData : VitalGlitchDataType; + variable MIMRXBRADD12_GlitchData : VitalGlitchDataType; + variable MIMRXBWEN_GlitchData : VitalGlitchDataType; + variable MIMRXBREN_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA0_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA1_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA2_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA3_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA4_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA5_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA6_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA7_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA8_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA9_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA10_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA11_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA12_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA13_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA14_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA15_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA16_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA17_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA18_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA19_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA20_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA21_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA22_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA23_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA24_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA25_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA26_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA27_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA28_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA29_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA30_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA31_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA32_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA33_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA34_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA35_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA36_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA37_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA38_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA39_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA40_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA41_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA42_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA43_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA44_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA45_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA46_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA47_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA48_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA49_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA50_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA51_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA52_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA53_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA54_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA55_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA56_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA57_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA58_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA59_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA60_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA61_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA62_GlitchData : VitalGlitchDataType; + variable MIMTXBWDATA63_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD0_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD1_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD2_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD3_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD4_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD5_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD6_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD7_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD8_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD9_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD10_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD11_GlitchData : VitalGlitchDataType; + variable MIMTXBWADD12_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD0_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD1_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD2_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD3_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD4_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD5_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD6_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD7_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD8_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD9_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD10_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD11_GlitchData : VitalGlitchDataType; + variable MIMTXBRADD12_GlitchData : VitalGlitchDataType; + variable MIMTXBWEN_GlitchData : VitalGlitchDataType; + variable MIMTXBREN_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA0_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA1_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA2_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA3_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA4_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA5_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA6_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA7_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA8_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA9_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA10_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA11_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA12_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA13_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA14_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA15_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA16_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA17_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA18_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA19_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA20_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA21_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA22_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA23_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA24_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA25_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA26_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA27_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA28_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA29_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA30_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA31_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA32_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA33_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA34_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA35_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA36_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA37_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA38_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA39_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA40_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA41_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA42_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA43_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA44_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA45_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA46_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA47_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA48_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA49_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA50_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA51_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA52_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA53_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA54_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA55_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA56_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA57_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA58_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA59_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA60_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA61_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA62_GlitchData : VitalGlitchDataType; + variable MIMDLLBWDATA63_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD0_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD1_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD2_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD3_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD4_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD5_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD6_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD7_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD8_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD9_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD10_GlitchData : VitalGlitchDataType; + variable MIMDLLBWADD11_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD0_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD1_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD2_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD3_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD4_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD5_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD6_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD7_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD8_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD9_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD10_GlitchData : VitalGlitchDataType; + variable MIMDLLBRADD11_GlitchData : VitalGlitchDataType; + variable MIMDLLBWEN_GlitchData : VitalGlitchDataType; + variable MIMDLLBREN_GlitchData : VitalGlitchDataType; + variable CRMRXHOTRESETN_GlitchData : VitalGlitchDataType; + variable CRMDOHOTRESETN_GlitchData : VitalGlitchDataType; + variable CRMPWRSOFTRESETN_GlitchData : VitalGlitchDataType; + variable LLKTCSTATUS0_GlitchData : VitalGlitchDataType; + variable LLKTCSTATUS1_GlitchData : VitalGlitchDataType; + variable LLKTCSTATUS2_GlitchData : VitalGlitchDataType; + variable LLKTCSTATUS3_GlitchData : VitalGlitchDataType; + variable LLKTCSTATUS4_GlitchData : VitalGlitchDataType; + variable LLKTCSTATUS5_GlitchData : VitalGlitchDataType; + variable LLKTCSTATUS6_GlitchData : VitalGlitchDataType; + variable LLKTCSTATUS7_GlitchData : VitalGlitchDataType; + variable LLKTXDSTRDYN_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE0_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE1_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE2_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE3_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE4_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE5_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE6_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE7_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE8_GlitchData : VitalGlitchDataType; + variable LLKTXCHANSPACE9_GlitchData : VitalGlitchDataType; + variable LLKTXCHPOSTEDREADYN0_GlitchData : VitalGlitchDataType; + variable LLKTXCHPOSTEDREADYN1_GlitchData : VitalGlitchDataType; + variable LLKTXCHPOSTEDREADYN2_GlitchData : VitalGlitchDataType; + variable LLKTXCHPOSTEDREADYN3_GlitchData : VitalGlitchDataType; + variable LLKTXCHPOSTEDREADYN4_GlitchData : VitalGlitchDataType; + variable LLKTXCHPOSTEDREADYN5_GlitchData : VitalGlitchDataType; + variable LLKTXCHPOSTEDREADYN6_GlitchData : VitalGlitchDataType; + variable LLKTXCHPOSTEDREADYN7_GlitchData : VitalGlitchDataType; + variable LLKTXCHNONPOSTEDREADYN0_GlitchData : VitalGlitchDataType; + variable LLKTXCHNONPOSTEDREADYN1_GlitchData : VitalGlitchDataType; + variable LLKTXCHNONPOSTEDREADYN2_GlitchData : VitalGlitchDataType; + variable LLKTXCHNONPOSTEDREADYN3_GlitchData : VitalGlitchDataType; + variable LLKTXCHNONPOSTEDREADYN4_GlitchData : VitalGlitchDataType; + variable LLKTXCHNONPOSTEDREADYN5_GlitchData : VitalGlitchDataType; + variable LLKTXCHNONPOSTEDREADYN6_GlitchData : VitalGlitchDataType; + variable LLKTXCHNONPOSTEDREADYN7_GlitchData : VitalGlitchDataType; + variable LLKTXCHCOMPLETIONREADYN0_GlitchData : VitalGlitchDataType; + variable LLKTXCHCOMPLETIONREADYN1_GlitchData : VitalGlitchDataType; + variable LLKTXCHCOMPLETIONREADYN2_GlitchData : VitalGlitchDataType; + variable LLKTXCHCOMPLETIONREADYN3_GlitchData : VitalGlitchDataType; + variable LLKTXCHCOMPLETIONREADYN4_GlitchData : VitalGlitchDataType; + variable LLKTXCHCOMPLETIONREADYN5_GlitchData : VitalGlitchDataType; + variable LLKTXCHCOMPLETIONREADYN6_GlitchData : VitalGlitchDataType; + variable LLKTXCHCOMPLETIONREADYN7_GlitchData : VitalGlitchDataType; + variable LLKTXCONFIGREADYN_GlitchData : VitalGlitchDataType; + variable LLKRXDATA0_GlitchData : VitalGlitchDataType; + variable LLKRXDATA1_GlitchData : VitalGlitchDataType; + variable LLKRXDATA2_GlitchData : VitalGlitchDataType; + variable LLKRXDATA3_GlitchData : VitalGlitchDataType; + variable LLKRXDATA4_GlitchData : VitalGlitchDataType; + variable LLKRXDATA5_GlitchData : VitalGlitchDataType; + variable LLKRXDATA6_GlitchData : VitalGlitchDataType; + variable LLKRXDATA7_GlitchData : VitalGlitchDataType; + variable LLKRXDATA8_GlitchData : VitalGlitchDataType; + variable LLKRXDATA9_GlitchData : VitalGlitchDataType; + variable LLKRXDATA10_GlitchData : VitalGlitchDataType; + variable LLKRXDATA11_GlitchData : VitalGlitchDataType; + variable LLKRXDATA12_GlitchData : VitalGlitchDataType; + variable LLKRXDATA13_GlitchData : VitalGlitchDataType; + variable LLKRXDATA14_GlitchData : VitalGlitchDataType; + variable LLKRXDATA15_GlitchData : VitalGlitchDataType; + variable LLKRXDATA16_GlitchData : VitalGlitchDataType; + variable LLKRXDATA17_GlitchData : VitalGlitchDataType; + variable LLKRXDATA18_GlitchData : VitalGlitchDataType; + variable LLKRXDATA19_GlitchData : VitalGlitchDataType; + variable LLKRXDATA20_GlitchData : VitalGlitchDataType; + variable LLKRXDATA21_GlitchData : VitalGlitchDataType; + variable LLKRXDATA22_GlitchData : VitalGlitchDataType; + variable LLKRXDATA23_GlitchData : VitalGlitchDataType; + variable LLKRXDATA24_GlitchData : VitalGlitchDataType; + variable LLKRXDATA25_GlitchData : VitalGlitchDataType; + variable LLKRXDATA26_GlitchData : VitalGlitchDataType; + variable LLKRXDATA27_GlitchData : VitalGlitchDataType; + variable LLKRXDATA28_GlitchData : VitalGlitchDataType; + variable LLKRXDATA29_GlitchData : VitalGlitchDataType; + variable LLKRXDATA30_GlitchData : VitalGlitchDataType; + variable LLKRXDATA31_GlitchData : VitalGlitchDataType; + variable LLKRXDATA32_GlitchData : VitalGlitchDataType; + variable LLKRXDATA33_GlitchData : VitalGlitchDataType; + variable LLKRXDATA34_GlitchData : VitalGlitchDataType; + variable LLKRXDATA35_GlitchData : VitalGlitchDataType; + variable LLKRXDATA36_GlitchData : VitalGlitchDataType; + variable LLKRXDATA37_GlitchData : VitalGlitchDataType; + variable LLKRXDATA38_GlitchData : VitalGlitchDataType; + variable LLKRXDATA39_GlitchData : VitalGlitchDataType; + variable LLKRXDATA40_GlitchData : VitalGlitchDataType; + variable LLKRXDATA41_GlitchData : VitalGlitchDataType; + variable LLKRXDATA42_GlitchData : VitalGlitchDataType; + variable LLKRXDATA43_GlitchData : VitalGlitchDataType; + variable LLKRXDATA44_GlitchData : VitalGlitchDataType; + variable LLKRXDATA45_GlitchData : VitalGlitchDataType; + variable LLKRXDATA46_GlitchData : VitalGlitchDataType; + variable LLKRXDATA47_GlitchData : VitalGlitchDataType; + variable LLKRXDATA48_GlitchData : VitalGlitchDataType; + variable LLKRXDATA49_GlitchData : VitalGlitchDataType; + variable LLKRXDATA50_GlitchData : VitalGlitchDataType; + variable LLKRXDATA51_GlitchData : VitalGlitchDataType; + variable LLKRXDATA52_GlitchData : VitalGlitchDataType; + variable LLKRXDATA53_GlitchData : VitalGlitchDataType; + variable LLKRXDATA54_GlitchData : VitalGlitchDataType; + variable LLKRXDATA55_GlitchData : VitalGlitchDataType; + variable LLKRXDATA56_GlitchData : VitalGlitchDataType; + variable LLKRXDATA57_GlitchData : VitalGlitchDataType; + variable LLKRXDATA58_GlitchData : VitalGlitchDataType; + variable LLKRXDATA59_GlitchData : VitalGlitchDataType; + variable LLKRXDATA60_GlitchData : VitalGlitchDataType; + variable LLKRXDATA61_GlitchData : VitalGlitchDataType; + variable LLKRXDATA62_GlitchData : VitalGlitchDataType; + variable LLKRXDATA63_GlitchData : VitalGlitchDataType; + variable LLKRXSRCRDYN_GlitchData : VitalGlitchDataType; + variable LLKRXSRCLASTREQN_GlitchData : VitalGlitchDataType; + variable LLKRXSRCDSCN_GlitchData : VitalGlitchDataType; + variable LLKRXSOFN_GlitchData : VitalGlitchDataType; + variable LLKRXEOFN_GlitchData : VitalGlitchDataType; + variable LLKRXSOPN_GlitchData : VitalGlitchDataType; + variable LLKRXEOPN_GlitchData : VitalGlitchDataType; + variable LLKRXVALIDN0_GlitchData : VitalGlitchDataType; + variable LLKRXVALIDN1_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE0_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE1_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE2_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE3_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE4_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE5_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE6_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE7_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE8_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE9_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE10_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE11_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE12_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE13_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE14_GlitchData : VitalGlitchDataType; + variable LLKRXPREFERREDTYPE15_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDAVAILABLEN0_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDAVAILABLEN1_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDAVAILABLEN2_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDAVAILABLEN3_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDAVAILABLEN4_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDAVAILABLEN5_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDAVAILABLEN6_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDAVAILABLEN7_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDAVAILABLEN0_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDAVAILABLEN1_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDAVAILABLEN2_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDAVAILABLEN3_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDAVAILABLEN4_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDAVAILABLEN5_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDAVAILABLEN6_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDAVAILABLEN7_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONAVAILABLEN0_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONAVAILABLEN1_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONAVAILABLEN2_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONAVAILABLEN3_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONAVAILABLEN4_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONAVAILABLEN5_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONAVAILABLEN6_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONAVAILABLEN7_GlitchData : VitalGlitchDataType; + variable LLKRXCHCONFIGAVAILABLEN_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDPARTIALN0_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDPARTIALN1_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDPARTIALN2_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDPARTIALN3_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDPARTIALN4_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDPARTIALN5_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDPARTIALN6_GlitchData : VitalGlitchDataType; + variable LLKRXCHPOSTEDPARTIALN7_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDPARTIALN0_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDPARTIALN1_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDPARTIALN2_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDPARTIALN3_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDPARTIALN4_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDPARTIALN5_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDPARTIALN6_GlitchData : VitalGlitchDataType; + variable LLKRXCHNONPOSTEDPARTIALN7_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONPARTIALN0_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONPARTIALN1_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONPARTIALN2_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONPARTIALN3_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONPARTIALN4_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONPARTIALN5_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONPARTIALN6_GlitchData : VitalGlitchDataType; + variable LLKRXCHCOMPLETIONPARTIALN7_GlitchData : VitalGlitchDataType; + variable LLKRXCHCONFIGPARTIALN_GlitchData : VitalGlitchDataType; + variable LLKRX4DWHEADERN_GlitchData : VitalGlitchDataType; + variable LLKRXECRCBADN_GlitchData : VitalGlitchDataType; + variable MGMTRDATA0_GlitchData : VitalGlitchDataType; + variable MGMTRDATA1_GlitchData : VitalGlitchDataType; + variable MGMTRDATA2_GlitchData : VitalGlitchDataType; + variable MGMTRDATA3_GlitchData : VitalGlitchDataType; + variable MGMTRDATA4_GlitchData : VitalGlitchDataType; + variable MGMTRDATA5_GlitchData : VitalGlitchDataType; + variable MGMTRDATA6_GlitchData : VitalGlitchDataType; + variable MGMTRDATA7_GlitchData : VitalGlitchDataType; + variable MGMTRDATA8_GlitchData : VitalGlitchDataType; + variable MGMTRDATA9_GlitchData : VitalGlitchDataType; + variable MGMTRDATA10_GlitchData : VitalGlitchDataType; + variable MGMTRDATA11_GlitchData : VitalGlitchDataType; + variable MGMTRDATA12_GlitchData : VitalGlitchDataType; + variable MGMTRDATA13_GlitchData : VitalGlitchDataType; + variable MGMTRDATA14_GlitchData : VitalGlitchDataType; + variable MGMTRDATA15_GlitchData : VitalGlitchDataType; + variable MGMTRDATA16_GlitchData : VitalGlitchDataType; + variable MGMTRDATA17_GlitchData : VitalGlitchDataType; + variable MGMTRDATA18_GlitchData : VitalGlitchDataType; + variable MGMTRDATA19_GlitchData : VitalGlitchDataType; + variable MGMTRDATA20_GlitchData : VitalGlitchDataType; + variable MGMTRDATA21_GlitchData : VitalGlitchDataType; + variable MGMTRDATA22_GlitchData : VitalGlitchDataType; + variable MGMTRDATA23_GlitchData : VitalGlitchDataType; + variable MGMTRDATA24_GlitchData : VitalGlitchDataType; + variable MGMTRDATA25_GlitchData : VitalGlitchDataType; + variable MGMTRDATA26_GlitchData : VitalGlitchDataType; + variable MGMTRDATA27_GlitchData : VitalGlitchDataType; + variable MGMTRDATA28_GlitchData : VitalGlitchDataType; + variable MGMTRDATA29_GlitchData : VitalGlitchDataType; + variable MGMTRDATA30_GlitchData : VitalGlitchDataType; + variable MGMTRDATA31_GlitchData : VitalGlitchDataType; + variable MGMTPSO0_GlitchData : VitalGlitchDataType; + variable MGMTPSO1_GlitchData : VitalGlitchDataType; + variable MGMTPSO2_GlitchData : VitalGlitchDataType; + variable MGMTPSO3_GlitchData : VitalGlitchDataType; + variable MGMTPSO4_GlitchData : VitalGlitchDataType; + variable MGMTPSO5_GlitchData : VitalGlitchDataType; + variable MGMTPSO6_GlitchData : VitalGlitchDataType; + variable MGMTPSO7_GlitchData : VitalGlitchDataType; + variable MGMTPSO8_GlitchData : VitalGlitchDataType; + variable MGMTPSO9_GlitchData : VitalGlitchDataType; + variable MGMTPSO10_GlitchData : VitalGlitchDataType; + variable MGMTPSO11_GlitchData : VitalGlitchDataType; + variable MGMTPSO12_GlitchData : VitalGlitchDataType; + variable MGMTPSO13_GlitchData : VitalGlitchDataType; + variable MGMTPSO14_GlitchData : VitalGlitchDataType; + variable MGMTPSO15_GlitchData : VitalGlitchDataType; + variable MGMTPSO16_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT0_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT1_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT2_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT3_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT4_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT5_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT6_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT7_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT8_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT9_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT10_GlitchData : VitalGlitchDataType; + variable MGMTSTATSCREDIT11_GlitchData : VitalGlitchDataType; + variable L0RXDLLTLPECRCOK_GlitchData : VitalGlitchDataType; + variable DLLTXPMDLLPOUTSTANDING_GlitchData : VitalGlitchDataType; + variable L0FIRSTCFGWRITEOCCURRED_GlitchData : VitalGlitchDataType; + variable L0CFGLOOPBACKACK_GlitchData : VitalGlitchDataType; + variable L0MACUPSTREAMDOWNSTREAM_GlitchData : VitalGlitchDataType; + variable L0RXMACLINKERROR0_GlitchData : VitalGlitchDataType; + variable L0RXMACLINKERROR1_GlitchData : VitalGlitchDataType; + variable L0MACLINKUP_GlitchData : VitalGlitchDataType; + variable L0MACNEGOTIATEDLINKWIDTH0_GlitchData : VitalGlitchDataType; + variable L0MACNEGOTIATEDLINKWIDTH1_GlitchData : VitalGlitchDataType; + variable L0MACNEGOTIATEDLINKWIDTH2_GlitchData : VitalGlitchDataType; + variable L0MACNEGOTIATEDLINKWIDTH3_GlitchData : VitalGlitchDataType; + variable L0MACLINKTRAINING_GlitchData : VitalGlitchDataType; + variable L0LTSSMSTATE0_GlitchData : VitalGlitchDataType; + variable L0LTSSMSTATE1_GlitchData : VitalGlitchDataType; + variable L0LTSSMSTATE2_GlitchData : VitalGlitchDataType; + variable L0LTSSMSTATE3_GlitchData : VitalGlitchDataType; + variable L0DLLVCSTATUS0_GlitchData : VitalGlitchDataType; + variable L0DLLVCSTATUS1_GlitchData : VitalGlitchDataType; + variable L0DLLVCSTATUS2_GlitchData : VitalGlitchDataType; + variable L0DLLVCSTATUS3_GlitchData : VitalGlitchDataType; + variable L0DLLVCSTATUS4_GlitchData : VitalGlitchDataType; + variable L0DLLVCSTATUS5_GlitchData : VitalGlitchDataType; + variable L0DLLVCSTATUS6_GlitchData : VitalGlitchDataType; + variable L0DLLVCSTATUS7_GlitchData : VitalGlitchDataType; + variable L0DLUPDOWN0_GlitchData : VitalGlitchDataType; + variable L0DLUPDOWN1_GlitchData : VitalGlitchDataType; + variable L0DLUPDOWN2_GlitchData : VitalGlitchDataType; + variable L0DLUPDOWN3_GlitchData : VitalGlitchDataType; + variable L0DLUPDOWN4_GlitchData : VitalGlitchDataType; + variable L0DLUPDOWN5_GlitchData : VitalGlitchDataType; + variable L0DLUPDOWN6_GlitchData : VitalGlitchDataType; + variable L0DLUPDOWN7_GlitchData : VitalGlitchDataType; + variable L0DLLERRORVECTOR0_GlitchData : VitalGlitchDataType; + variable L0DLLERRORVECTOR1_GlitchData : VitalGlitchDataType; + variable L0DLLERRORVECTOR2_GlitchData : VitalGlitchDataType; + variable L0DLLERRORVECTOR3_GlitchData : VitalGlitchDataType; + variable L0DLLERRORVECTOR4_GlitchData : VitalGlitchDataType; + variable L0DLLERRORVECTOR5_GlitchData : VitalGlitchDataType; + variable L0DLLERRORVECTOR6_GlitchData : VitalGlitchDataType; + variable L0DLLASRXSTATE0_GlitchData : VitalGlitchDataType; + variable L0DLLASRXSTATE1_GlitchData : VitalGlitchDataType; + variable L0DLLASTXSTATE_GlitchData : VitalGlitchDataType; + variable L0ASAUTONOMOUSINITCOMPLETED_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID0_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID1_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID2_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID3_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID4_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID5_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID6_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID7_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID8_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID9_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID10_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID11_GlitchData : VitalGlitchDataType; + variable L0COMPLETERID12_GlitchData : VitalGlitchDataType; + variable L0UNLOCKRECEIVED_GlitchData : VitalGlitchDataType; + variable L0CORRERRMSGRCVD_GlitchData : VitalGlitchDataType; + variable L0FATALERRMSGRCVD_GlitchData : VitalGlitchDataType; + variable L0NONFATALERRMSGRCVD_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID0_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID1_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID2_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID3_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID4_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID5_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID6_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID7_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID8_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID9_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID10_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID11_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID12_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID13_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID14_GlitchData : VitalGlitchDataType; + variable L0ERRMSGREQID15_GlitchData : VitalGlitchDataType; + variable L0FWDCORRERROUT_GlitchData : VitalGlitchDataType; + variable L0FWDFATALERROUT_GlitchData : VitalGlitchDataType; + variable L0FWDNONFATALERROUT_GlitchData : VitalGlitchDataType; + variable L0RECEIVEDASSERTINTALEGACYINT_GlitchData : VitalGlitchDataType; + variable L0RECEIVEDASSERTINTBLEGACYINT_GlitchData : VitalGlitchDataType; + variable L0RECEIVEDASSERTINTCLEGACYINT_GlitchData : VitalGlitchDataType; + variable L0RECEIVEDASSERTINTDLEGACYINT_GlitchData : VitalGlitchDataType; + variable L0RECEIVEDDEASSERTINTALEGACYINT_GlitchData : VitalGlitchDataType; + variable L0RECEIVEDDEASSERTINTBLEGACYINT_GlitchData : VitalGlitchDataType; + variable L0RECEIVEDDEASSERTINTCLEGACYINT_GlitchData : VitalGlitchDataType; + variable L0RECEIVEDDEASSERTINTDLEGACYINT_GlitchData : VitalGlitchDataType; + variable L0MSIENABLE0_GlitchData : VitalGlitchDataType; + variable L0MULTIMSGEN00_GlitchData : VitalGlitchDataType; + variable L0MULTIMSGEN01_GlitchData : VitalGlitchDataType; + variable L0MULTIMSGEN02_GlitchData : VitalGlitchDataType; + variable L0STATSDLLPRECEIVED_GlitchData : VitalGlitchDataType; + variable L0STATSDLLPTRANSMITTED_GlitchData : VitalGlitchDataType; + variable L0STATSOSRECEIVED_GlitchData : VitalGlitchDataType; + variable L0STATSOSTRANSMITTED_GlitchData : VitalGlitchDataType; + variable L0STATSTLPRECEIVED_GlitchData : VitalGlitchDataType; + variable L0STATSTLPTRANSMITTED_GlitchData : VitalGlitchDataType; + variable L0STATSCFGRECEIVED_GlitchData : VitalGlitchDataType; + variable L0STATSCFGTRANSMITTED_GlitchData : VitalGlitchDataType; + variable L0STATSCFGOTHERRECEIVED_GlitchData : VitalGlitchDataType; + variable L0STATSCFGOTHERTRANSMITTED_GlitchData : VitalGlitchDataType; + variable MAXPAYLOADSIZE0_GlitchData : VitalGlitchDataType; + variable MAXPAYLOADSIZE1_GlitchData : VitalGlitchDataType; + variable MAXPAYLOADSIZE2_GlitchData : VitalGlitchDataType; + variable MAXREADREQUESTSIZE0_GlitchData : VitalGlitchDataType; + variable MAXREADREQUESTSIZE1_GlitchData : VitalGlitchDataType; + variable MAXREADREQUESTSIZE2_GlitchData : VitalGlitchDataType; + variable IOSPACEENABLE_GlitchData : VitalGlitchDataType; + variable MEMSPACEENABLE_GlitchData : VitalGlitchDataType; + variable L0ATTENTIONINDICATORCONTROL0_GlitchData : VitalGlitchDataType; + variable L0ATTENTIONINDICATORCONTROL1_GlitchData : VitalGlitchDataType; + variable L0POWERINDICATORCONTROL0_GlitchData : VitalGlitchDataType; + variable L0POWERINDICATORCONTROL1_GlitchData : VitalGlitchDataType; + variable L0POWERCONTROLLERCONTROL_GlitchData : VitalGlitchDataType; + variable L0TOGGLEELECTROMECHANICALINTERLOCK_GlitchData : VitalGlitchDataType; + variable L0RXBEACON_GlitchData : VitalGlitchDataType; + variable L0PWRSTATE00_GlitchData : VitalGlitchDataType; + variable L0PWRSTATE01_GlitchData : VitalGlitchDataType; + variable L0PMEACK_GlitchData : VitalGlitchDataType; + variable L0PMEREQOUT_GlitchData : VitalGlitchDataType; + variable L0PMEEN_GlitchData : VitalGlitchDataType; + variable L0PWRINHIBITTRANSFERS_GlitchData : VitalGlitchDataType; + variable L0PWRL1STATE_GlitchData : VitalGlitchDataType; + variable L0PWRL23READYDEVICE_GlitchData : VitalGlitchDataType; + variable L0PWRL23READYSTATE_GlitchData : VitalGlitchDataType; + variable L0PWRTXL0SSTATE_GlitchData : VitalGlitchDataType; + variable L0PWRTURNOFFREQ_GlitchData : VitalGlitchDataType; + variable L0RXDLLPM_GlitchData : VitalGlitchDataType; + variable L0RXDLLPMTYPE0_GlitchData : VitalGlitchDataType; + variable L0RXDLLPMTYPE1_GlitchData : VitalGlitchDataType; + variable L0RXDLLPMTYPE2_GlitchData : VitalGlitchDataType; + variable L0TXDLLPMUPDATED_GlitchData : VitalGlitchDataType; + variable L0MACNEWSTATEACK_GlitchData : VitalGlitchDataType; + variable L0MACRXL0SSTATE_GlitchData : VitalGlitchDataType; + variable L0MACENTEREDL0_GlitchData : VitalGlitchDataType; + variable L0DLLRXACKOUTSTANDING_GlitchData : VitalGlitchDataType; + variable L0DLLTXOUTSTANDING_GlitchData : VitalGlitchDataType; + variable L0DLLTXNONFCOUTSTANDING_GlitchData : VitalGlitchDataType; + variable L0RXDLLTLPEND0_GlitchData : VitalGlitchDataType; + variable L0RXDLLTLPEND1_GlitchData : VitalGlitchDataType; + variable L0TXDLLSBFCUPDATED_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA0_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA1_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA2_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA3_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA4_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA5_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA6_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA7_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA8_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA9_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA10_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA11_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA12_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA13_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA14_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA15_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA16_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA17_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCDATA18_GlitchData : VitalGlitchDataType; + variable L0RXDLLSBFCUPDATE_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCNPOSTBYPUPDATED0_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCNPOSTBYPUPDATED1_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCNPOSTBYPUPDATED2_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCNPOSTBYPUPDATED3_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCNPOSTBYPUPDATED4_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCNPOSTBYPUPDATED5_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCNPOSTBYPUPDATED6_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCNPOSTBYPUPDATED7_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCPOSTORDUPDATED0_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCPOSTORDUPDATED1_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCPOSTORDUPDATED2_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCPOSTORDUPDATED3_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCPOSTORDUPDATED4_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCPOSTORDUPDATED5_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCPOSTORDUPDATED6_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCPOSTORDUPDATED7_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCCMPLMCUPDATED0_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCCMPLMCUPDATED1_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCCMPLMCUPDATED2_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCCMPLMCUPDATED3_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCCMPLMCUPDATED4_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCCMPLMCUPDATED5_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCCMPLMCUPDATED6_GlitchData : VitalGlitchDataType; + variable L0TXDLLFCCMPLMCUPDATED7_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED0_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED1_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED2_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED3_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED4_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED5_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED6_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED7_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED8_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED9_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED10_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED11_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED12_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED13_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED14_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED15_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED16_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED17_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED18_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPCRED19_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPUPDATE0_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPUPDATE1_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPUPDATE2_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPUPDATE3_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPUPDATE4_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPUPDATE5_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPUPDATE6_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCNPOSTBYPUPDATE7_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED0_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED1_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED2_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED3_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED4_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED5_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED6_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED7_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED8_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED9_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED10_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED11_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED12_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED13_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED14_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED15_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED16_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED17_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED18_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED19_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED20_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED21_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED22_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDCRED23_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDUPDATE0_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDUPDATE1_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDUPDATE2_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDUPDATE3_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDUPDATE4_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDUPDATE5_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDUPDATE6_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCPOSTORDUPDATE7_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED0_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED1_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED2_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED3_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED4_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED5_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED6_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED7_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED8_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED9_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED10_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED11_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED12_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED13_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED14_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED15_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED16_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED17_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED18_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED19_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED20_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED21_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED22_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCCRED23_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCUPDATE0_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCUPDATE1_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCUPDATE2_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCUPDATE3_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCUPDATE4_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCUPDATE5_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCUPDATE6_GlitchData : VitalGlitchDataType; + variable L0RXDLLFCCMPLMCUPDATE7_GlitchData : VitalGlitchDataType; + variable L0UCBYPFOUND0_GlitchData : VitalGlitchDataType; + variable L0UCBYPFOUND1_GlitchData : VitalGlitchDataType; + variable L0UCBYPFOUND2_GlitchData : VitalGlitchDataType; + variable L0UCBYPFOUND3_GlitchData : VitalGlitchDataType; + variable L0UCORDFOUND0_GlitchData : VitalGlitchDataType; + variable L0UCORDFOUND1_GlitchData : VitalGlitchDataType; + variable L0UCORDFOUND2_GlitchData : VitalGlitchDataType; + variable L0UCORDFOUND3_GlitchData : VitalGlitchDataType; + variable L0MCFOUND0_GlitchData : VitalGlitchDataType; + variable L0MCFOUND1_GlitchData : VitalGlitchDataType; + variable L0MCFOUND2_GlitchData : VitalGlitchDataType; + variable L0TRANSFORMEDVC0_GlitchData : VitalGlitchDataType; + variable L0TRANSFORMEDVC1_GlitchData : VitalGlitchDataType; + variable L0TRANSFORMEDVC2_GlitchData : VitalGlitchDataType; + variable BUSMASTERENABLE_GlitchData : VitalGlitchDataType; + variable PARITYERRORRESPONSE_GlitchData : VitalGlitchDataType; + variable SERRENABLE_GlitchData : VitalGlitchDataType; + variable INTERRUPTDISABLE_GlitchData : VitalGlitchDataType; + variable URREPORTINGENABLE_GlitchData : VitalGlitchDataType; +begin + + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL0(0), + GlitchData => PIPETXDATAL00_GlitchData, + OutSignalName => "PIPETXDATAL0(0)", + OutTemp => PIPETXDATAL0_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL0(1), + GlitchData => PIPETXDATAL01_GlitchData, + OutSignalName => "PIPETXDATAL0(1)", + OutTemp => PIPETXDATAL0_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL0(2), + GlitchData => PIPETXDATAL02_GlitchData, + OutSignalName => "PIPETXDATAL0(2)", + OutTemp => PIPETXDATAL0_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL0(3), + GlitchData => PIPETXDATAL03_GlitchData, + OutSignalName => "PIPETXDATAL0(3)", + OutTemp => PIPETXDATAL0_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL0(4), + GlitchData => PIPETXDATAL04_GlitchData, + OutSignalName => "PIPETXDATAL0(4)", + OutTemp => PIPETXDATAL0_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL0(5), + GlitchData => PIPETXDATAL05_GlitchData, + OutSignalName => "PIPETXDATAL0(5)", + OutTemp => PIPETXDATAL0_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL0(6), + GlitchData => PIPETXDATAL06_GlitchData, + OutSignalName => "PIPETXDATAL0(6)", + OutTemp => PIPETXDATAL0_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL0(7), + GlitchData => PIPETXDATAL07_GlitchData, + OutSignalName => "PIPETXDATAL0(7)", + OutTemp => PIPETXDATAL0_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAKL0, + GlitchData => PIPETXDATAKL0_GlitchData, + OutSignalName => "PIPETXDATAKL0", + OutTemp => PIPETXDATAKL0_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXELECIDLEL0, + GlitchData => PIPETXELECIDLEL0_GlitchData, + OutSignalName => "PIPETXELECIDLEL0", + OutTemp => PIPETXELECIDLEL0_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDETECTRXLOOPBACKL0, + GlitchData => PIPETXDETECTRXLOOPBACKL0_GlitchData, + OutSignalName => "PIPETXDETECTRXLOOPBACKL0", + OutTemp => PIPETXDETECTRXLOOPBACKL0_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXCOMPLIANCEL0, + GlitchData => PIPETXCOMPLIANCEL0_GlitchData, + OutSignalName => "PIPETXCOMPLIANCEL0", + OutTemp => PIPETXCOMPLIANCEL0_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERXPOLARITYL0, + GlitchData => PIPERXPOLARITYL0_GlitchData, + OutSignalName => "PIPERXPOLARITYL0", + OutTemp => PIPERXPOLARITYL0_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL0(0), + GlitchData => PIPEPOWERDOWNL00_GlitchData, + OutSignalName => "PIPEPOWERDOWNL0(0)", + OutTemp => PIPEPOWERDOWNL0_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL0(0), + GlitchData => PIPEPOWERDOWNL00_GlitchData, + OutSignalName => "PIPEPOWERDOWNL0(0)", + OutTemp => PIPEPOWERDOWNL0_OUT(0), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL0(1), + GlitchData => PIPEPOWERDOWNL01_GlitchData, + OutSignalName => "PIPEPOWERDOWNL0(1)", + OutTemp => PIPEPOWERDOWNL0_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL0(1), + GlitchData => PIPEPOWERDOWNL01_GlitchData, + OutSignalName => "PIPEPOWERDOWNL0(1)", + OutTemp => PIPEPOWERDOWNL0_OUT(1), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEDESKEWLANESL0, + GlitchData => PIPEDESKEWLANESL0_GlitchData, + OutSignalName => "PIPEDESKEWLANESL0", + OutTemp => PIPEDESKEWLANESL0_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERESETL0, + GlitchData => PIPERESETL0_GlitchData, + OutSignalName => "PIPERESETL0", + OutTemp => PIPERESETL0_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL1(0), + GlitchData => PIPETXDATAL10_GlitchData, + OutSignalName => "PIPETXDATAL1(0)", + OutTemp => PIPETXDATAL1_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL1(1), + GlitchData => PIPETXDATAL11_GlitchData, + OutSignalName => "PIPETXDATAL1(1)", + OutTemp => PIPETXDATAL1_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL1(2), + GlitchData => PIPETXDATAL12_GlitchData, + OutSignalName => "PIPETXDATAL1(2)", + OutTemp => PIPETXDATAL1_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL1(3), + GlitchData => PIPETXDATAL13_GlitchData, + OutSignalName => "PIPETXDATAL1(3)", + OutTemp => PIPETXDATAL1_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL1(4), + GlitchData => PIPETXDATAL14_GlitchData, + OutSignalName => "PIPETXDATAL1(4)", + OutTemp => PIPETXDATAL1_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL1(5), + GlitchData => PIPETXDATAL15_GlitchData, + OutSignalName => "PIPETXDATAL1(5)", + OutTemp => PIPETXDATAL1_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL1(6), + GlitchData => PIPETXDATAL16_GlitchData, + OutSignalName => "PIPETXDATAL1(6)", + OutTemp => PIPETXDATAL1_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL1(7), + GlitchData => PIPETXDATAL17_GlitchData, + OutSignalName => "PIPETXDATAL1(7)", + OutTemp => PIPETXDATAL1_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAKL1, + GlitchData => PIPETXDATAKL1_GlitchData, + OutSignalName => "PIPETXDATAKL1", + OutTemp => PIPETXDATAKL1_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXELECIDLEL1, + GlitchData => PIPETXELECIDLEL1_GlitchData, + OutSignalName => "PIPETXELECIDLEL1", + OutTemp => PIPETXELECIDLEL1_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDETECTRXLOOPBACKL1, + GlitchData => PIPETXDETECTRXLOOPBACKL1_GlitchData, + OutSignalName => "PIPETXDETECTRXLOOPBACKL1", + OutTemp => PIPETXDETECTRXLOOPBACKL1_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXCOMPLIANCEL1, + GlitchData => PIPETXCOMPLIANCEL1_GlitchData, + OutSignalName => "PIPETXCOMPLIANCEL1", + OutTemp => PIPETXCOMPLIANCEL1_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERXPOLARITYL1, + GlitchData => PIPERXPOLARITYL1_GlitchData, + OutSignalName => "PIPERXPOLARITYL1", + OutTemp => PIPERXPOLARITYL1_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL1(0), + GlitchData => PIPEPOWERDOWNL10_GlitchData, + OutSignalName => "PIPEPOWERDOWNL1(0)", + OutTemp => PIPEPOWERDOWNL1_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL1(0), + GlitchData => PIPEPOWERDOWNL10_GlitchData, + OutSignalName => "PIPEPOWERDOWNL1(0)", + OutTemp => PIPEPOWERDOWNL1_OUT(0), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL1(1), + GlitchData => PIPEPOWERDOWNL11_GlitchData, + OutSignalName => "PIPEPOWERDOWNL1(1)", + OutTemp => PIPEPOWERDOWNL1_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL1(1), + GlitchData => PIPEPOWERDOWNL11_GlitchData, + OutSignalName => "PIPEPOWERDOWNL1(1)", + OutTemp => PIPEPOWERDOWNL1_OUT(1), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEDESKEWLANESL1, + GlitchData => PIPEDESKEWLANESL1_GlitchData, + OutSignalName => "PIPEDESKEWLANESL1", + OutTemp => PIPEDESKEWLANESL1_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERESETL1, + GlitchData => PIPERESETL1_GlitchData, + OutSignalName => "PIPERESETL1", + OutTemp => PIPERESETL1_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL2(0), + GlitchData => PIPETXDATAL20_GlitchData, + OutSignalName => "PIPETXDATAL2(0)", + OutTemp => PIPETXDATAL2_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL2(1), + GlitchData => PIPETXDATAL21_GlitchData, + OutSignalName => "PIPETXDATAL2(1)", + OutTemp => PIPETXDATAL2_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL2(2), + GlitchData => PIPETXDATAL22_GlitchData, + OutSignalName => "PIPETXDATAL2(2)", + OutTemp => PIPETXDATAL2_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL2(3), + GlitchData => PIPETXDATAL23_GlitchData, + OutSignalName => "PIPETXDATAL2(3)", + OutTemp => PIPETXDATAL2_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL2(4), + GlitchData => PIPETXDATAL24_GlitchData, + OutSignalName => "PIPETXDATAL2(4)", + OutTemp => PIPETXDATAL2_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL2(5), + GlitchData => PIPETXDATAL25_GlitchData, + OutSignalName => "PIPETXDATAL2(5)", + OutTemp => PIPETXDATAL2_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL2(6), + GlitchData => PIPETXDATAL26_GlitchData, + OutSignalName => "PIPETXDATAL2(6)", + OutTemp => PIPETXDATAL2_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL2(7), + GlitchData => PIPETXDATAL27_GlitchData, + OutSignalName => "PIPETXDATAL2(7)", + OutTemp => PIPETXDATAL2_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAKL2, + GlitchData => PIPETXDATAKL2_GlitchData, + OutSignalName => "PIPETXDATAKL2", + OutTemp => PIPETXDATAKL2_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXELECIDLEL2, + GlitchData => PIPETXELECIDLEL2_GlitchData, + OutSignalName => "PIPETXELECIDLEL2", + OutTemp => PIPETXELECIDLEL2_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDETECTRXLOOPBACKL2, + GlitchData => PIPETXDETECTRXLOOPBACKL2_GlitchData, + OutSignalName => "PIPETXDETECTRXLOOPBACKL2", + OutTemp => PIPETXDETECTRXLOOPBACKL2_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXCOMPLIANCEL2, + GlitchData => PIPETXCOMPLIANCEL2_GlitchData, + OutSignalName => "PIPETXCOMPLIANCEL2", + OutTemp => PIPETXCOMPLIANCEL2_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERXPOLARITYL2, + GlitchData => PIPERXPOLARITYL2_GlitchData, + OutSignalName => "PIPERXPOLARITYL2", + OutTemp => PIPERXPOLARITYL2_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL2(0), + GlitchData => PIPEPOWERDOWNL20_GlitchData, + OutSignalName => "PIPEPOWERDOWNL2(0)", + OutTemp => PIPEPOWERDOWNL2_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL2(0), + GlitchData => PIPEPOWERDOWNL20_GlitchData, + OutSignalName => "PIPEPOWERDOWNL2(0)", + OutTemp => PIPEPOWERDOWNL2_OUT(0), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL2(1), + GlitchData => PIPEPOWERDOWNL21_GlitchData, + OutSignalName => "PIPEPOWERDOWNL2(1)", + OutTemp => PIPEPOWERDOWNL2_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL2(1), + GlitchData => PIPEPOWERDOWNL21_GlitchData, + OutSignalName => "PIPEPOWERDOWNL2(1)", + OutTemp => PIPEPOWERDOWNL2_OUT(1), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEDESKEWLANESL2, + GlitchData => PIPEDESKEWLANESL2_GlitchData, + OutSignalName => "PIPEDESKEWLANESL2", + OutTemp => PIPEDESKEWLANESL2_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERESETL2, + GlitchData => PIPERESETL2_GlitchData, + OutSignalName => "PIPERESETL2", + OutTemp => PIPERESETL2_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL3(0), + GlitchData => PIPETXDATAL30_GlitchData, + OutSignalName => "PIPETXDATAL3(0)", + OutTemp => PIPETXDATAL3_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL3(1), + GlitchData => PIPETXDATAL31_GlitchData, + OutSignalName => "PIPETXDATAL3(1)", + OutTemp => PIPETXDATAL3_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL3(2), + GlitchData => PIPETXDATAL32_GlitchData, + OutSignalName => "PIPETXDATAL3(2)", + OutTemp => PIPETXDATAL3_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL3(3), + GlitchData => PIPETXDATAL33_GlitchData, + OutSignalName => "PIPETXDATAL3(3)", + OutTemp => PIPETXDATAL3_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL3(4), + GlitchData => PIPETXDATAL34_GlitchData, + OutSignalName => "PIPETXDATAL3(4)", + OutTemp => PIPETXDATAL3_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL3(5), + GlitchData => PIPETXDATAL35_GlitchData, + OutSignalName => "PIPETXDATAL3(5)", + OutTemp => PIPETXDATAL3_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL3(6), + GlitchData => PIPETXDATAL36_GlitchData, + OutSignalName => "PIPETXDATAL3(6)", + OutTemp => PIPETXDATAL3_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL3(7), + GlitchData => PIPETXDATAL37_GlitchData, + OutSignalName => "PIPETXDATAL3(7)", + OutTemp => PIPETXDATAL3_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAKL3, + GlitchData => PIPETXDATAKL3_GlitchData, + OutSignalName => "PIPETXDATAKL3", + OutTemp => PIPETXDATAKL3_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXELECIDLEL3, + GlitchData => PIPETXELECIDLEL3_GlitchData, + OutSignalName => "PIPETXELECIDLEL3", + OutTemp => PIPETXELECIDLEL3_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDETECTRXLOOPBACKL3, + GlitchData => PIPETXDETECTRXLOOPBACKL3_GlitchData, + OutSignalName => "PIPETXDETECTRXLOOPBACKL3", + OutTemp => PIPETXDETECTRXLOOPBACKL3_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXCOMPLIANCEL3, + GlitchData => PIPETXCOMPLIANCEL3_GlitchData, + OutSignalName => "PIPETXCOMPLIANCEL3", + OutTemp => PIPETXCOMPLIANCEL3_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERXPOLARITYL3, + GlitchData => PIPERXPOLARITYL3_GlitchData, + OutSignalName => "PIPERXPOLARITYL3", + OutTemp => PIPERXPOLARITYL3_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL3(0), + GlitchData => PIPEPOWERDOWNL30_GlitchData, + OutSignalName => "PIPEPOWERDOWNL3(0)", + OutTemp => PIPEPOWERDOWNL3_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL3(0), + GlitchData => PIPEPOWERDOWNL30_GlitchData, + OutSignalName => "PIPEPOWERDOWNL3(0)", + OutTemp => PIPEPOWERDOWNL3_OUT(0), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL3(1), + GlitchData => PIPEPOWERDOWNL31_GlitchData, + OutSignalName => "PIPEPOWERDOWNL3(1)", + OutTemp => PIPEPOWERDOWNL3_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL3(1), + GlitchData => PIPEPOWERDOWNL31_GlitchData, + OutSignalName => "PIPEPOWERDOWNL3(1)", + OutTemp => PIPEPOWERDOWNL3_OUT(1), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEDESKEWLANESL3, + GlitchData => PIPEDESKEWLANESL3_GlitchData, + OutSignalName => "PIPEDESKEWLANESL3", + OutTemp => PIPEDESKEWLANESL3_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERESETL3, + GlitchData => PIPERESETL3_GlitchData, + OutSignalName => "PIPERESETL3", + OutTemp => PIPERESETL3_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL4(0), + GlitchData => PIPETXDATAL40_GlitchData, + OutSignalName => "PIPETXDATAL4(0)", + OutTemp => PIPETXDATAL4_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL4(1), + GlitchData => PIPETXDATAL41_GlitchData, + OutSignalName => "PIPETXDATAL4(1)", + OutTemp => PIPETXDATAL4_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL4(2), + GlitchData => PIPETXDATAL42_GlitchData, + OutSignalName => "PIPETXDATAL4(2)", + OutTemp => PIPETXDATAL4_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL4(3), + GlitchData => PIPETXDATAL43_GlitchData, + OutSignalName => "PIPETXDATAL4(3)", + OutTemp => PIPETXDATAL4_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL4(4), + GlitchData => PIPETXDATAL44_GlitchData, + OutSignalName => "PIPETXDATAL4(4)", + OutTemp => PIPETXDATAL4_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL4(5), + GlitchData => PIPETXDATAL45_GlitchData, + OutSignalName => "PIPETXDATAL4(5)", + OutTemp => PIPETXDATAL4_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL4(6), + GlitchData => PIPETXDATAL46_GlitchData, + OutSignalName => "PIPETXDATAL4(6)", + OutTemp => PIPETXDATAL4_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL4(7), + GlitchData => PIPETXDATAL47_GlitchData, + OutSignalName => "PIPETXDATAL4(7)", + OutTemp => PIPETXDATAL4_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAKL4, + GlitchData => PIPETXDATAKL4_GlitchData, + OutSignalName => "PIPETXDATAKL4", + OutTemp => PIPETXDATAKL4_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXELECIDLEL4, + GlitchData => PIPETXELECIDLEL4_GlitchData, + OutSignalName => "PIPETXELECIDLEL4", + OutTemp => PIPETXELECIDLEL4_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDETECTRXLOOPBACKL4, + GlitchData => PIPETXDETECTRXLOOPBACKL4_GlitchData, + OutSignalName => "PIPETXDETECTRXLOOPBACKL4", + OutTemp => PIPETXDETECTRXLOOPBACKL4_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXCOMPLIANCEL4, + GlitchData => PIPETXCOMPLIANCEL4_GlitchData, + OutSignalName => "PIPETXCOMPLIANCEL4", + OutTemp => PIPETXCOMPLIANCEL4_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERXPOLARITYL4, + GlitchData => PIPERXPOLARITYL4_GlitchData, + OutSignalName => "PIPERXPOLARITYL4", + OutTemp => PIPERXPOLARITYL4_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL4(0), + GlitchData => PIPEPOWERDOWNL40_GlitchData, + OutSignalName => "PIPEPOWERDOWNL4(0)", + OutTemp => PIPEPOWERDOWNL4_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL4(0), + GlitchData => PIPEPOWERDOWNL40_GlitchData, + OutSignalName => "PIPEPOWERDOWNL4(0)", + OutTemp => PIPEPOWERDOWNL4_OUT(0), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL4(1), + GlitchData => PIPEPOWERDOWNL41_GlitchData, + OutSignalName => "PIPEPOWERDOWNL4(1)", + OutTemp => PIPEPOWERDOWNL4_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL4(1), + GlitchData => PIPEPOWERDOWNL41_GlitchData, + OutSignalName => "PIPEPOWERDOWNL4(1)", + OutTemp => PIPEPOWERDOWNL4_OUT(1), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEDESKEWLANESL4, + GlitchData => PIPEDESKEWLANESL4_GlitchData, + OutSignalName => "PIPEDESKEWLANESL4", + OutTemp => PIPEDESKEWLANESL4_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERESETL4, + GlitchData => PIPERESETL4_GlitchData, + OutSignalName => "PIPERESETL4", + OutTemp => PIPERESETL4_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL5(0), + GlitchData => PIPETXDATAL50_GlitchData, + OutSignalName => "PIPETXDATAL5(0)", + OutTemp => PIPETXDATAL5_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL5(1), + GlitchData => PIPETXDATAL51_GlitchData, + OutSignalName => "PIPETXDATAL5(1)", + OutTemp => PIPETXDATAL5_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL5(2), + GlitchData => PIPETXDATAL52_GlitchData, + OutSignalName => "PIPETXDATAL5(2)", + OutTemp => PIPETXDATAL5_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL5(3), + GlitchData => PIPETXDATAL53_GlitchData, + OutSignalName => "PIPETXDATAL5(3)", + OutTemp => PIPETXDATAL5_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL5(4), + GlitchData => PIPETXDATAL54_GlitchData, + OutSignalName => "PIPETXDATAL5(4)", + OutTemp => PIPETXDATAL5_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL5(5), + GlitchData => PIPETXDATAL55_GlitchData, + OutSignalName => "PIPETXDATAL5(5)", + OutTemp => PIPETXDATAL5_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL5(6), + GlitchData => PIPETXDATAL56_GlitchData, + OutSignalName => "PIPETXDATAL5(6)", + OutTemp => PIPETXDATAL5_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL5(7), + GlitchData => PIPETXDATAL57_GlitchData, + OutSignalName => "PIPETXDATAL5(7)", + OutTemp => PIPETXDATAL5_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAKL5, + GlitchData => PIPETXDATAKL5_GlitchData, + OutSignalName => "PIPETXDATAKL5", + OutTemp => PIPETXDATAKL5_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXELECIDLEL5, + GlitchData => PIPETXELECIDLEL5_GlitchData, + OutSignalName => "PIPETXELECIDLEL5", + OutTemp => PIPETXELECIDLEL5_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDETECTRXLOOPBACKL5, + GlitchData => PIPETXDETECTRXLOOPBACKL5_GlitchData, + OutSignalName => "PIPETXDETECTRXLOOPBACKL5", + OutTemp => PIPETXDETECTRXLOOPBACKL5_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXCOMPLIANCEL5, + GlitchData => PIPETXCOMPLIANCEL5_GlitchData, + OutSignalName => "PIPETXCOMPLIANCEL5", + OutTemp => PIPETXCOMPLIANCEL5_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERXPOLARITYL5, + GlitchData => PIPERXPOLARITYL5_GlitchData, + OutSignalName => "PIPERXPOLARITYL5", + OutTemp => PIPERXPOLARITYL5_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL5(0), + GlitchData => PIPEPOWERDOWNL50_GlitchData, + OutSignalName => "PIPEPOWERDOWNL5(0)", + OutTemp => PIPEPOWERDOWNL5_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL5(0), + GlitchData => PIPEPOWERDOWNL50_GlitchData, + OutSignalName => "PIPEPOWERDOWNL5(0)", + OutTemp => PIPEPOWERDOWNL5_OUT(0), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL5(1), + GlitchData => PIPEPOWERDOWNL51_GlitchData, + OutSignalName => "PIPEPOWERDOWNL5(1)", + OutTemp => PIPEPOWERDOWNL5_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL5(1), + GlitchData => PIPEPOWERDOWNL51_GlitchData, + OutSignalName => "PIPEPOWERDOWNL5(1)", + OutTemp => PIPEPOWERDOWNL5_OUT(1), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEDESKEWLANESL5, + GlitchData => PIPEDESKEWLANESL5_GlitchData, + OutSignalName => "PIPEDESKEWLANESL5", + OutTemp => PIPEDESKEWLANESL5_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERESETL5, + GlitchData => PIPERESETL5_GlitchData, + OutSignalName => "PIPERESETL5", + OutTemp => PIPERESETL5_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL6(0), + GlitchData => PIPETXDATAL60_GlitchData, + OutSignalName => "PIPETXDATAL6(0)", + OutTemp => PIPETXDATAL6_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL6(1), + GlitchData => PIPETXDATAL61_GlitchData, + OutSignalName => "PIPETXDATAL6(1)", + OutTemp => PIPETXDATAL6_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL6(2), + GlitchData => PIPETXDATAL62_GlitchData, + OutSignalName => "PIPETXDATAL6(2)", + OutTemp => PIPETXDATAL6_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL6(3), + GlitchData => PIPETXDATAL63_GlitchData, + OutSignalName => "PIPETXDATAL6(3)", + OutTemp => PIPETXDATAL6_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL6(4), + GlitchData => PIPETXDATAL64_GlitchData, + OutSignalName => "PIPETXDATAL6(4)", + OutTemp => PIPETXDATAL6_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL6(5), + GlitchData => PIPETXDATAL65_GlitchData, + OutSignalName => "PIPETXDATAL6(5)", + OutTemp => PIPETXDATAL6_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL6(6), + GlitchData => PIPETXDATAL66_GlitchData, + OutSignalName => "PIPETXDATAL6(6)", + OutTemp => PIPETXDATAL6_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL6(7), + GlitchData => PIPETXDATAL67_GlitchData, + OutSignalName => "PIPETXDATAL6(7)", + OutTemp => PIPETXDATAL6_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAKL6, + GlitchData => PIPETXDATAKL6_GlitchData, + OutSignalName => "PIPETXDATAKL6", + OutTemp => PIPETXDATAKL6_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXELECIDLEL6, + GlitchData => PIPETXELECIDLEL6_GlitchData, + OutSignalName => "PIPETXELECIDLEL6", + OutTemp => PIPETXELECIDLEL6_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDETECTRXLOOPBACKL6, + GlitchData => PIPETXDETECTRXLOOPBACKL6_GlitchData, + OutSignalName => "PIPETXDETECTRXLOOPBACKL6", + OutTemp => PIPETXDETECTRXLOOPBACKL6_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXCOMPLIANCEL6, + GlitchData => PIPETXCOMPLIANCEL6_GlitchData, + OutSignalName => "PIPETXCOMPLIANCEL6", + OutTemp => PIPETXCOMPLIANCEL6_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERXPOLARITYL6, + GlitchData => PIPERXPOLARITYL6_GlitchData, + OutSignalName => "PIPERXPOLARITYL6", + OutTemp => PIPERXPOLARITYL6_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL6(0), + GlitchData => PIPEPOWERDOWNL60_GlitchData, + OutSignalName => "PIPEPOWERDOWNL6(0)", + OutTemp => PIPEPOWERDOWNL6_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL6(0), + GlitchData => PIPEPOWERDOWNL60_GlitchData, + OutSignalName => "PIPEPOWERDOWNL6(0)", + OutTemp => PIPEPOWERDOWNL6_OUT(0), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL6(1), + GlitchData => PIPEPOWERDOWNL61_GlitchData, + OutSignalName => "PIPEPOWERDOWNL6(1)", + OutTemp => PIPEPOWERDOWNL6_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL6(1), + GlitchData => PIPEPOWERDOWNL61_GlitchData, + OutSignalName => "PIPEPOWERDOWNL6(1)", + OutTemp => PIPEPOWERDOWNL6_OUT(1), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEDESKEWLANESL6, + GlitchData => PIPEDESKEWLANESL6_GlitchData, + OutSignalName => "PIPEDESKEWLANESL6", + OutTemp => PIPEDESKEWLANESL6_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERESETL6, + GlitchData => PIPERESETL6_GlitchData, + OutSignalName => "PIPERESETL6", + OutTemp => PIPERESETL6_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL7(0), + GlitchData => PIPETXDATAL70_GlitchData, + OutSignalName => "PIPETXDATAL7(0)", + OutTemp => PIPETXDATAL7_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL7(1), + GlitchData => PIPETXDATAL71_GlitchData, + OutSignalName => "PIPETXDATAL7(1)", + OutTemp => PIPETXDATAL7_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL7(2), + GlitchData => PIPETXDATAL72_GlitchData, + OutSignalName => "PIPETXDATAL7(2)", + OutTemp => PIPETXDATAL7_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL7(3), + GlitchData => PIPETXDATAL73_GlitchData, + OutSignalName => "PIPETXDATAL7(3)", + OutTemp => PIPETXDATAL7_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL7(4), + GlitchData => PIPETXDATAL74_GlitchData, + OutSignalName => "PIPETXDATAL7(4)", + OutTemp => PIPETXDATAL7_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL7(5), + GlitchData => PIPETXDATAL75_GlitchData, + OutSignalName => "PIPETXDATAL7(5)", + OutTemp => PIPETXDATAL7_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL7(6), + GlitchData => PIPETXDATAL76_GlitchData, + OutSignalName => "PIPETXDATAL7(6)", + OutTemp => PIPETXDATAL7_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAL7(7), + GlitchData => PIPETXDATAL77_GlitchData, + OutSignalName => "PIPETXDATAL7(7)", + OutTemp => PIPETXDATAL7_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDATAKL7, + GlitchData => PIPETXDATAKL7_GlitchData, + OutSignalName => "PIPETXDATAKL7", + OutTemp => PIPETXDATAKL7_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXELECIDLEL7, + GlitchData => PIPETXELECIDLEL7_GlitchData, + OutSignalName => "PIPETXELECIDLEL7", + OutTemp => PIPETXELECIDLEL7_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXDETECTRXLOOPBACKL7, + GlitchData => PIPETXDETECTRXLOOPBACKL7_GlitchData, + OutSignalName => "PIPETXDETECTRXLOOPBACKL7", + OutTemp => PIPETXDETECTRXLOOPBACKL7_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPETXCOMPLIANCEL7, + GlitchData => PIPETXCOMPLIANCEL7_GlitchData, + OutSignalName => "PIPETXCOMPLIANCEL7", + OutTemp => PIPETXCOMPLIANCEL7_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERXPOLARITYL7, + GlitchData => PIPERXPOLARITYL7_GlitchData, + OutSignalName => "PIPERXPOLARITYL7", + OutTemp => PIPERXPOLARITYL7_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL7(0), + GlitchData => PIPEPOWERDOWNL70_GlitchData, + OutSignalName => "PIPEPOWERDOWNL7(0)", + OutTemp => PIPEPOWERDOWNL7_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL7(0), + GlitchData => PIPEPOWERDOWNL70_GlitchData, + OutSignalName => "PIPEPOWERDOWNL7(0)", + OutTemp => PIPEPOWERDOWNL7_OUT(0), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL7(1), + GlitchData => PIPEPOWERDOWNL71_GlitchData, + OutSignalName => "PIPEPOWERDOWNL7(1)", + OutTemp => PIPEPOWERDOWNL7_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEPOWERDOWNL7(1), + GlitchData => PIPEPOWERDOWNL71_GlitchData, + OutSignalName => "PIPEPOWERDOWNL7(1)", + OutTemp => PIPEPOWERDOWNL7_OUT(1), + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPEDESKEWLANESL7, + GlitchData => PIPEDESKEWLANESL7_GlitchData, + OutSignalName => "PIPEDESKEWLANESL7", + OutTemp => PIPEDESKEWLANESL7_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PIPERESETL7, + GlitchData => PIPERESETL7_GlitchData, + OutSignalName => "PIPERESETL7", + OutTemp => PIPERESETL7_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(0), + GlitchData => MIMRXBWDATA0_GlitchData, + OutSignalName => "MIMRXBWDATA(0)", + OutTemp => MIMRXBWDATA_OUT(0), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(1), + GlitchData => MIMRXBWDATA1_GlitchData, + OutSignalName => "MIMRXBWDATA(1)", + OutTemp => MIMRXBWDATA_OUT(1), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(2), + GlitchData => MIMRXBWDATA2_GlitchData, + OutSignalName => "MIMRXBWDATA(2)", + OutTemp => MIMRXBWDATA_OUT(2), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(3), + GlitchData => MIMRXBWDATA3_GlitchData, + OutSignalName => "MIMRXBWDATA(3)", + OutTemp => MIMRXBWDATA_OUT(3), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(4), + GlitchData => MIMRXBWDATA4_GlitchData, + OutSignalName => "MIMRXBWDATA(4)", + OutTemp => MIMRXBWDATA_OUT(4), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(5), + GlitchData => MIMRXBWDATA5_GlitchData, + OutSignalName => "MIMRXBWDATA(5)", + OutTemp => MIMRXBWDATA_OUT(5), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(6), + GlitchData => MIMRXBWDATA6_GlitchData, + OutSignalName => "MIMRXBWDATA(6)", + OutTemp => MIMRXBWDATA_OUT(6), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(7), + GlitchData => MIMRXBWDATA7_GlitchData, + OutSignalName => "MIMRXBWDATA(7)", + OutTemp => MIMRXBWDATA_OUT(7), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(8), + GlitchData => MIMRXBWDATA8_GlitchData, + OutSignalName => "MIMRXBWDATA(8)", + OutTemp => MIMRXBWDATA_OUT(8), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(9), + GlitchData => MIMRXBWDATA9_GlitchData, + OutSignalName => "MIMRXBWDATA(9)", + OutTemp => MIMRXBWDATA_OUT(9), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(10), + GlitchData => MIMRXBWDATA10_GlitchData, + OutSignalName => "MIMRXBWDATA(10)", + OutTemp => MIMRXBWDATA_OUT(10), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(11), + GlitchData => MIMRXBWDATA11_GlitchData, + OutSignalName => "MIMRXBWDATA(11)", + OutTemp => MIMRXBWDATA_OUT(11), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(12), + GlitchData => MIMRXBWDATA12_GlitchData, + OutSignalName => "MIMRXBWDATA(12)", + OutTemp => MIMRXBWDATA_OUT(12), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(13), + GlitchData => MIMRXBWDATA13_GlitchData, + OutSignalName => "MIMRXBWDATA(13)", + OutTemp => MIMRXBWDATA_OUT(13), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(14), + GlitchData => MIMRXBWDATA14_GlitchData, + OutSignalName => "MIMRXBWDATA(14)", + OutTemp => MIMRXBWDATA_OUT(14), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(15), + GlitchData => MIMRXBWDATA15_GlitchData, + OutSignalName => "MIMRXBWDATA(15)", + OutTemp => MIMRXBWDATA_OUT(15), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(16), + GlitchData => MIMRXBWDATA16_GlitchData, + OutSignalName => "MIMRXBWDATA(16)", + OutTemp => MIMRXBWDATA_OUT(16), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(17), + GlitchData => MIMRXBWDATA17_GlitchData, + OutSignalName => "MIMRXBWDATA(17)", + OutTemp => MIMRXBWDATA_OUT(17), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(18), + GlitchData => MIMRXBWDATA18_GlitchData, + OutSignalName => "MIMRXBWDATA(18)", + OutTemp => MIMRXBWDATA_OUT(18), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(19), + GlitchData => MIMRXBWDATA19_GlitchData, + OutSignalName => "MIMRXBWDATA(19)", + OutTemp => MIMRXBWDATA_OUT(19), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(20), + GlitchData => MIMRXBWDATA20_GlitchData, + OutSignalName => "MIMRXBWDATA(20)", + OutTemp => MIMRXBWDATA_OUT(20), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(21), + GlitchData => MIMRXBWDATA21_GlitchData, + OutSignalName => "MIMRXBWDATA(21)", + OutTemp => MIMRXBWDATA_OUT(21), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(22), + GlitchData => MIMRXBWDATA22_GlitchData, + OutSignalName => "MIMRXBWDATA(22)", + OutTemp => MIMRXBWDATA_OUT(22), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(23), + GlitchData => MIMRXBWDATA23_GlitchData, + OutSignalName => "MIMRXBWDATA(23)", + OutTemp => MIMRXBWDATA_OUT(23), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(24), + GlitchData => MIMRXBWDATA24_GlitchData, + OutSignalName => "MIMRXBWDATA(24)", + OutTemp => MIMRXBWDATA_OUT(24), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(25), + GlitchData => MIMRXBWDATA25_GlitchData, + OutSignalName => "MIMRXBWDATA(25)", + OutTemp => MIMRXBWDATA_OUT(25), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(26), + GlitchData => MIMRXBWDATA26_GlitchData, + OutSignalName => "MIMRXBWDATA(26)", + OutTemp => MIMRXBWDATA_OUT(26), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(27), + GlitchData => MIMRXBWDATA27_GlitchData, + OutSignalName => "MIMRXBWDATA(27)", + OutTemp => MIMRXBWDATA_OUT(27), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(28), + GlitchData => MIMRXBWDATA28_GlitchData, + OutSignalName => "MIMRXBWDATA(28)", + OutTemp => MIMRXBWDATA_OUT(28), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(29), + GlitchData => MIMRXBWDATA29_GlitchData, + OutSignalName => "MIMRXBWDATA(29)", + OutTemp => MIMRXBWDATA_OUT(29), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(30), + GlitchData => MIMRXBWDATA30_GlitchData, + OutSignalName => "MIMRXBWDATA(30)", + OutTemp => MIMRXBWDATA_OUT(30), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(31), + GlitchData => MIMRXBWDATA31_GlitchData, + OutSignalName => "MIMRXBWDATA(31)", + OutTemp => MIMRXBWDATA_OUT(31), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(32), + GlitchData => MIMRXBWDATA32_GlitchData, + OutSignalName => "MIMRXBWDATA(32)", + OutTemp => MIMRXBWDATA_OUT(32), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(33), + GlitchData => MIMRXBWDATA33_GlitchData, + OutSignalName => "MIMRXBWDATA(33)", + OutTemp => MIMRXBWDATA_OUT(33), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(34), + GlitchData => MIMRXBWDATA34_GlitchData, + OutSignalName => "MIMRXBWDATA(34)", + OutTemp => MIMRXBWDATA_OUT(34), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(35), + GlitchData => MIMRXBWDATA35_GlitchData, + OutSignalName => "MIMRXBWDATA(35)", + OutTemp => MIMRXBWDATA_OUT(35), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(36), + GlitchData => MIMRXBWDATA36_GlitchData, + OutSignalName => "MIMRXBWDATA(36)", + OutTemp => MIMRXBWDATA_OUT(36), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(37), + GlitchData => MIMRXBWDATA37_GlitchData, + OutSignalName => "MIMRXBWDATA(37)", + OutTemp => MIMRXBWDATA_OUT(37), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(38), + GlitchData => MIMRXBWDATA38_GlitchData, + OutSignalName => "MIMRXBWDATA(38)", + OutTemp => MIMRXBWDATA_OUT(38), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(39), + GlitchData => MIMRXBWDATA39_GlitchData, + OutSignalName => "MIMRXBWDATA(39)", + OutTemp => MIMRXBWDATA_OUT(39), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(40), + GlitchData => MIMRXBWDATA40_GlitchData, + OutSignalName => "MIMRXBWDATA(40)", + OutTemp => MIMRXBWDATA_OUT(40), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(41), + GlitchData => MIMRXBWDATA41_GlitchData, + OutSignalName => "MIMRXBWDATA(41)", + OutTemp => MIMRXBWDATA_OUT(41), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(42), + GlitchData => MIMRXBWDATA42_GlitchData, + OutSignalName => "MIMRXBWDATA(42)", + OutTemp => MIMRXBWDATA_OUT(42), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(43), + GlitchData => MIMRXBWDATA43_GlitchData, + OutSignalName => "MIMRXBWDATA(43)", + OutTemp => MIMRXBWDATA_OUT(43), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(44), + GlitchData => MIMRXBWDATA44_GlitchData, + OutSignalName => "MIMRXBWDATA(44)", + OutTemp => MIMRXBWDATA_OUT(44), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(45), + GlitchData => MIMRXBWDATA45_GlitchData, + OutSignalName => "MIMRXBWDATA(45)", + OutTemp => MIMRXBWDATA_OUT(45), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(46), + GlitchData => MIMRXBWDATA46_GlitchData, + OutSignalName => "MIMRXBWDATA(46)", + OutTemp => MIMRXBWDATA_OUT(46), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(47), + GlitchData => MIMRXBWDATA47_GlitchData, + OutSignalName => "MIMRXBWDATA(47)", + OutTemp => MIMRXBWDATA_OUT(47), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(48), + GlitchData => MIMRXBWDATA48_GlitchData, + OutSignalName => "MIMRXBWDATA(48)", + OutTemp => MIMRXBWDATA_OUT(48), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(49), + GlitchData => MIMRXBWDATA49_GlitchData, + OutSignalName => "MIMRXBWDATA(49)", + OutTemp => MIMRXBWDATA_OUT(49), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(50), + GlitchData => MIMRXBWDATA50_GlitchData, + OutSignalName => "MIMRXBWDATA(50)", + OutTemp => MIMRXBWDATA_OUT(50), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(51), + GlitchData => MIMRXBWDATA51_GlitchData, + OutSignalName => "MIMRXBWDATA(51)", + OutTemp => MIMRXBWDATA_OUT(51), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(52), + GlitchData => MIMRXBWDATA52_GlitchData, + OutSignalName => "MIMRXBWDATA(52)", + OutTemp => MIMRXBWDATA_OUT(52), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(53), + GlitchData => MIMRXBWDATA53_GlitchData, + OutSignalName => "MIMRXBWDATA(53)", + OutTemp => MIMRXBWDATA_OUT(53), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(54), + GlitchData => MIMRXBWDATA54_GlitchData, + OutSignalName => "MIMRXBWDATA(54)", + OutTemp => MIMRXBWDATA_OUT(54), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(55), + GlitchData => MIMRXBWDATA55_GlitchData, + OutSignalName => "MIMRXBWDATA(55)", + OutTemp => MIMRXBWDATA_OUT(55), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(56), + GlitchData => MIMRXBWDATA56_GlitchData, + OutSignalName => "MIMRXBWDATA(56)", + OutTemp => MIMRXBWDATA_OUT(56), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(57), + GlitchData => MIMRXBWDATA57_GlitchData, + OutSignalName => "MIMRXBWDATA(57)", + OutTemp => MIMRXBWDATA_OUT(57), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(58), + GlitchData => MIMRXBWDATA58_GlitchData, + OutSignalName => "MIMRXBWDATA(58)", + OutTemp => MIMRXBWDATA_OUT(58), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(59), + GlitchData => MIMRXBWDATA59_GlitchData, + OutSignalName => "MIMRXBWDATA(59)", + OutTemp => MIMRXBWDATA_OUT(59), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(60), + GlitchData => MIMRXBWDATA60_GlitchData, + OutSignalName => "MIMRXBWDATA(60)", + OutTemp => MIMRXBWDATA_OUT(60), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(61), + GlitchData => MIMRXBWDATA61_GlitchData, + OutSignalName => "MIMRXBWDATA(61)", + OutTemp => MIMRXBWDATA_OUT(61), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(62), + GlitchData => MIMRXBWDATA62_GlitchData, + OutSignalName => "MIMRXBWDATA(62)", + OutTemp => MIMRXBWDATA_OUT(62), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWDATA(63), + GlitchData => MIMRXBWDATA63_GlitchData, + OutSignalName => "MIMRXBWDATA(63)", + OutTemp => MIMRXBWDATA_OUT(63), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(0), + GlitchData => MIMRXBWADD0_GlitchData, + OutSignalName => "MIMRXBWADD(0)", + OutTemp => MIMRXBWADD_OUT(0), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(1), + GlitchData => MIMRXBWADD1_GlitchData, + OutSignalName => "MIMRXBWADD(1)", + OutTemp => MIMRXBWADD_OUT(1), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(2), + GlitchData => MIMRXBWADD2_GlitchData, + OutSignalName => "MIMRXBWADD(2)", + OutTemp => MIMRXBWADD_OUT(2), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(3), + GlitchData => MIMRXBWADD3_GlitchData, + OutSignalName => "MIMRXBWADD(3)", + OutTemp => MIMRXBWADD_OUT(3), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(4), + GlitchData => MIMRXBWADD4_GlitchData, + OutSignalName => "MIMRXBWADD(4)", + OutTemp => MIMRXBWADD_OUT(4), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(5), + GlitchData => MIMRXBWADD5_GlitchData, + OutSignalName => "MIMRXBWADD(5)", + OutTemp => MIMRXBWADD_OUT(5), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(6), + GlitchData => MIMRXBWADD6_GlitchData, + OutSignalName => "MIMRXBWADD(6)", + OutTemp => MIMRXBWADD_OUT(6), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(7), + GlitchData => MIMRXBWADD7_GlitchData, + OutSignalName => "MIMRXBWADD(7)", + OutTemp => MIMRXBWADD_OUT(7), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(8), + GlitchData => MIMRXBWADD8_GlitchData, + OutSignalName => "MIMRXBWADD(8)", + OutTemp => MIMRXBWADD_OUT(8), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(9), + GlitchData => MIMRXBWADD9_GlitchData, + OutSignalName => "MIMRXBWADD(9)", + OutTemp => MIMRXBWADD_OUT(9), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(10), + GlitchData => MIMRXBWADD10_GlitchData, + OutSignalName => "MIMRXBWADD(10)", + OutTemp => MIMRXBWADD_OUT(10), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(11), + GlitchData => MIMRXBWADD11_GlitchData, + OutSignalName => "MIMRXBWADD(11)", + OutTemp => MIMRXBWADD_OUT(11), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWADD(12), + GlitchData => MIMRXBWADD12_GlitchData, + OutSignalName => "MIMRXBWADD(12)", + OutTemp => MIMRXBWADD_OUT(12), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(0), + GlitchData => MIMRXBRADD0_GlitchData, + OutSignalName => "MIMRXBRADD(0)", + OutTemp => MIMRXBRADD_OUT(0), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(0), + GlitchData => MIMRXBRADD0_GlitchData, + OutSignalName => "MIMRXBRADD(0)", + OutTemp => MIMRXBRADD_OUT(0), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(1), + GlitchData => MIMRXBRADD1_GlitchData, + OutSignalName => "MIMRXBRADD(1)", + OutTemp => MIMRXBRADD_OUT(1), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(1), + GlitchData => MIMRXBRADD1_GlitchData, + OutSignalName => "MIMRXBRADD(1)", + OutTemp => MIMRXBRADD_OUT(1), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(2), + GlitchData => MIMRXBRADD2_GlitchData, + OutSignalName => "MIMRXBRADD(2)", + OutTemp => MIMRXBRADD_OUT(2), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(2), + GlitchData => MIMRXBRADD2_GlitchData, + OutSignalName => "MIMRXBRADD(2)", + OutTemp => MIMRXBRADD_OUT(2), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(3), + GlitchData => MIMRXBRADD3_GlitchData, + OutSignalName => "MIMRXBRADD(3)", + OutTemp => MIMRXBRADD_OUT(3), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(3), + GlitchData => MIMRXBRADD3_GlitchData, + OutSignalName => "MIMRXBRADD(3)", + OutTemp => MIMRXBRADD_OUT(3), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(4), + GlitchData => MIMRXBRADD4_GlitchData, + OutSignalName => "MIMRXBRADD(4)", + OutTemp => MIMRXBRADD_OUT(4), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(4), + GlitchData => MIMRXBRADD4_GlitchData, + OutSignalName => "MIMRXBRADD(4)", + OutTemp => MIMRXBRADD_OUT(4), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(5), + GlitchData => MIMRXBRADD5_GlitchData, + OutSignalName => "MIMRXBRADD(5)", + OutTemp => MIMRXBRADD_OUT(5), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(5), + GlitchData => MIMRXBRADD5_GlitchData, + OutSignalName => "MIMRXBRADD(5)", + OutTemp => MIMRXBRADD_OUT(5), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(6), + GlitchData => MIMRXBRADD6_GlitchData, + OutSignalName => "MIMRXBRADD(6)", + OutTemp => MIMRXBRADD_OUT(6), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(6), + GlitchData => MIMRXBRADD6_GlitchData, + OutSignalName => "MIMRXBRADD(6)", + OutTemp => MIMRXBRADD_OUT(6), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(7), + GlitchData => MIMRXBRADD7_GlitchData, + OutSignalName => "MIMRXBRADD(7)", + OutTemp => MIMRXBRADD_OUT(7), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(7), + GlitchData => MIMRXBRADD7_GlitchData, + OutSignalName => "MIMRXBRADD(7)", + OutTemp => MIMRXBRADD_OUT(7), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(8), + GlitchData => MIMRXBRADD8_GlitchData, + OutSignalName => "MIMRXBRADD(8)", + OutTemp => MIMRXBRADD_OUT(8), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(8), + GlitchData => MIMRXBRADD8_GlitchData, + OutSignalName => "MIMRXBRADD(8)", + OutTemp => MIMRXBRADD_OUT(8), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(9), + GlitchData => MIMRXBRADD9_GlitchData, + OutSignalName => "MIMRXBRADD(9)", + OutTemp => MIMRXBRADD_OUT(9), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(9), + GlitchData => MIMRXBRADD9_GlitchData, + OutSignalName => "MIMRXBRADD(9)", + OutTemp => MIMRXBRADD_OUT(9), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(10), + GlitchData => MIMRXBRADD10_GlitchData, + OutSignalName => "MIMRXBRADD(10)", + OutTemp => MIMRXBRADD_OUT(10), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(10), + GlitchData => MIMRXBRADD10_GlitchData, + OutSignalName => "MIMRXBRADD(10)", + OutTemp => MIMRXBRADD_OUT(10), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(11), + GlitchData => MIMRXBRADD11_GlitchData, + OutSignalName => "MIMRXBRADD(11)", + OutTemp => MIMRXBRADD_OUT(11), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(11), + GlitchData => MIMRXBRADD11_GlitchData, + OutSignalName => "MIMRXBRADD(11)", + OutTemp => MIMRXBRADD_OUT(11), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(12), + GlitchData => MIMRXBRADD12_GlitchData, + OutSignalName => "MIMRXBRADD(12)", + OutTemp => MIMRXBRADD_OUT(12), + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBRADD(12), + GlitchData => MIMRXBRADD12_GlitchData, + OutSignalName => "MIMRXBRADD(12)", + OutTemp => MIMRXBRADD_OUT(12), + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBWEN, + GlitchData => MIMRXBWEN_GlitchData, + OutSignalName => "MIMRXBWEN", + OutTemp => MIMRXBWEN_OUT, + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBREN, + GlitchData => MIMRXBREN_GlitchData, + OutSignalName => "MIMRXBREN", + OutTemp => MIMRXBREN_OUT, + Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMRXBREN, + GlitchData => MIMRXBREN_GlitchData, + OutSignalName => "MIMRXBREN", + OutTemp => MIMRXBREN_OUT, + Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(0), + GlitchData => MIMTXBWDATA0_GlitchData, + OutSignalName => "MIMTXBWDATA(0)", + OutTemp => MIMTXBWDATA_OUT(0), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(0), + GlitchData => MIMTXBWDATA0_GlitchData, + OutSignalName => "MIMTXBWDATA(0)", + OutTemp => MIMTXBWDATA_OUT(0), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(1), + GlitchData => MIMTXBWDATA1_GlitchData, + OutSignalName => "MIMTXBWDATA(1)", + OutTemp => MIMTXBWDATA_OUT(1), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(1), + GlitchData => MIMTXBWDATA1_GlitchData, + OutSignalName => "MIMTXBWDATA(1)", + OutTemp => MIMTXBWDATA_OUT(1), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(2), + GlitchData => MIMTXBWDATA2_GlitchData, + OutSignalName => "MIMTXBWDATA(2)", + OutTemp => MIMTXBWDATA_OUT(2), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(2), + GlitchData => MIMTXBWDATA2_GlitchData, + OutSignalName => "MIMTXBWDATA(2)", + OutTemp => MIMTXBWDATA_OUT(2), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(3), + GlitchData => MIMTXBWDATA3_GlitchData, + OutSignalName => "MIMTXBWDATA(3)", + OutTemp => MIMTXBWDATA_OUT(3), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(3), + GlitchData => MIMTXBWDATA3_GlitchData, + OutSignalName => "MIMTXBWDATA(3)", + OutTemp => MIMTXBWDATA_OUT(3), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(4), + GlitchData => MIMTXBWDATA4_GlitchData, + OutSignalName => "MIMTXBWDATA(4)", + OutTemp => MIMTXBWDATA_OUT(4), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(4), + GlitchData => MIMTXBWDATA4_GlitchData, + OutSignalName => "MIMTXBWDATA(4)", + OutTemp => MIMTXBWDATA_OUT(4), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(5), + GlitchData => MIMTXBWDATA5_GlitchData, + OutSignalName => "MIMTXBWDATA(5)", + OutTemp => MIMTXBWDATA_OUT(5), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(5), + GlitchData => MIMTXBWDATA5_GlitchData, + OutSignalName => "MIMTXBWDATA(5)", + OutTemp => MIMTXBWDATA_OUT(5), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(6), + GlitchData => MIMTXBWDATA6_GlitchData, + OutSignalName => "MIMTXBWDATA(6)", + OutTemp => MIMTXBWDATA_OUT(6), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(6), + GlitchData => MIMTXBWDATA6_GlitchData, + OutSignalName => "MIMTXBWDATA(6)", + OutTemp => MIMTXBWDATA_OUT(6), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(7), + GlitchData => MIMTXBWDATA7_GlitchData, + OutSignalName => "MIMTXBWDATA(7)", + OutTemp => MIMTXBWDATA_OUT(7), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(7), + GlitchData => MIMTXBWDATA7_GlitchData, + OutSignalName => "MIMTXBWDATA(7)", + OutTemp => MIMTXBWDATA_OUT(7), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(8), + GlitchData => MIMTXBWDATA8_GlitchData, + OutSignalName => "MIMTXBWDATA(8)", + OutTemp => MIMTXBWDATA_OUT(8), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(8), + GlitchData => MIMTXBWDATA8_GlitchData, + OutSignalName => "MIMTXBWDATA(8)", + OutTemp => MIMTXBWDATA_OUT(8), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(9), + GlitchData => MIMTXBWDATA9_GlitchData, + OutSignalName => "MIMTXBWDATA(9)", + OutTemp => MIMTXBWDATA_OUT(9), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(9), + GlitchData => MIMTXBWDATA9_GlitchData, + OutSignalName => "MIMTXBWDATA(9)", + OutTemp => MIMTXBWDATA_OUT(9), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(10), + GlitchData => MIMTXBWDATA10_GlitchData, + OutSignalName => "MIMTXBWDATA(10)", + OutTemp => MIMTXBWDATA_OUT(10), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(10), + GlitchData => MIMTXBWDATA10_GlitchData, + OutSignalName => "MIMTXBWDATA(10)", + OutTemp => MIMTXBWDATA_OUT(10), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(11), + GlitchData => MIMTXBWDATA11_GlitchData, + OutSignalName => "MIMTXBWDATA(11)", + OutTemp => MIMTXBWDATA_OUT(11), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(11), + GlitchData => MIMTXBWDATA11_GlitchData, + OutSignalName => "MIMTXBWDATA(11)", + OutTemp => MIMTXBWDATA_OUT(11), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(12), + GlitchData => MIMTXBWDATA12_GlitchData, + OutSignalName => "MIMTXBWDATA(12)", + OutTemp => MIMTXBWDATA_OUT(12), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(12), + GlitchData => MIMTXBWDATA12_GlitchData, + OutSignalName => "MIMTXBWDATA(12)", + OutTemp => MIMTXBWDATA_OUT(12), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(13), + GlitchData => MIMTXBWDATA13_GlitchData, + OutSignalName => "MIMTXBWDATA(13)", + OutTemp => MIMTXBWDATA_OUT(13), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(13), + GlitchData => MIMTXBWDATA13_GlitchData, + OutSignalName => "MIMTXBWDATA(13)", + OutTemp => MIMTXBWDATA_OUT(13), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(14), + GlitchData => MIMTXBWDATA14_GlitchData, + OutSignalName => "MIMTXBWDATA(14)", + OutTemp => MIMTXBWDATA_OUT(14), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(14), + GlitchData => MIMTXBWDATA14_GlitchData, + OutSignalName => "MIMTXBWDATA(14)", + OutTemp => MIMTXBWDATA_OUT(14), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(15), + GlitchData => MIMTXBWDATA15_GlitchData, + OutSignalName => "MIMTXBWDATA(15)", + OutTemp => MIMTXBWDATA_OUT(15), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(15), + GlitchData => MIMTXBWDATA15_GlitchData, + OutSignalName => "MIMTXBWDATA(15)", + OutTemp => MIMTXBWDATA_OUT(15), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(16), + GlitchData => MIMTXBWDATA16_GlitchData, + OutSignalName => "MIMTXBWDATA(16)", + OutTemp => MIMTXBWDATA_OUT(16), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(16), + GlitchData => MIMTXBWDATA16_GlitchData, + OutSignalName => "MIMTXBWDATA(16)", + OutTemp => MIMTXBWDATA_OUT(16), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(17), + GlitchData => MIMTXBWDATA17_GlitchData, + OutSignalName => "MIMTXBWDATA(17)", + OutTemp => MIMTXBWDATA_OUT(17), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(17), + GlitchData => MIMTXBWDATA17_GlitchData, + OutSignalName => "MIMTXBWDATA(17)", + OutTemp => MIMTXBWDATA_OUT(17), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(18), + GlitchData => MIMTXBWDATA18_GlitchData, + OutSignalName => "MIMTXBWDATA(18)", + OutTemp => MIMTXBWDATA_OUT(18), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(18), + GlitchData => MIMTXBWDATA18_GlitchData, + OutSignalName => "MIMTXBWDATA(18)", + OutTemp => MIMTXBWDATA_OUT(18), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(19), + GlitchData => MIMTXBWDATA19_GlitchData, + OutSignalName => "MIMTXBWDATA(19)", + OutTemp => MIMTXBWDATA_OUT(19), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(19), + GlitchData => MIMTXBWDATA19_GlitchData, + OutSignalName => "MIMTXBWDATA(19)", + OutTemp => MIMTXBWDATA_OUT(19), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(20), + GlitchData => MIMTXBWDATA20_GlitchData, + OutSignalName => "MIMTXBWDATA(20)", + OutTemp => MIMTXBWDATA_OUT(20), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(20), + GlitchData => MIMTXBWDATA20_GlitchData, + OutSignalName => "MIMTXBWDATA(20)", + OutTemp => MIMTXBWDATA_OUT(20), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(21), + GlitchData => MIMTXBWDATA21_GlitchData, + OutSignalName => "MIMTXBWDATA(21)", + OutTemp => MIMTXBWDATA_OUT(21), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(21), + GlitchData => MIMTXBWDATA21_GlitchData, + OutSignalName => "MIMTXBWDATA(21)", + OutTemp => MIMTXBWDATA_OUT(21), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(22), + GlitchData => MIMTXBWDATA22_GlitchData, + OutSignalName => "MIMTXBWDATA(22)", + OutTemp => MIMTXBWDATA_OUT(22), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(22), + GlitchData => MIMTXBWDATA22_GlitchData, + OutSignalName => "MIMTXBWDATA(22)", + OutTemp => MIMTXBWDATA_OUT(22), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(23), + GlitchData => MIMTXBWDATA23_GlitchData, + OutSignalName => "MIMTXBWDATA(23)", + OutTemp => MIMTXBWDATA_OUT(23), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(23), + GlitchData => MIMTXBWDATA23_GlitchData, + OutSignalName => "MIMTXBWDATA(23)", + OutTemp => MIMTXBWDATA_OUT(23), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(24), + GlitchData => MIMTXBWDATA24_GlitchData, + OutSignalName => "MIMTXBWDATA(24)", + OutTemp => MIMTXBWDATA_OUT(24), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(24), + GlitchData => MIMTXBWDATA24_GlitchData, + OutSignalName => "MIMTXBWDATA(24)", + OutTemp => MIMTXBWDATA_OUT(24), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(25), + GlitchData => MIMTXBWDATA25_GlitchData, + OutSignalName => "MIMTXBWDATA(25)", + OutTemp => MIMTXBWDATA_OUT(25), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(25), + GlitchData => MIMTXBWDATA25_GlitchData, + OutSignalName => "MIMTXBWDATA(25)", + OutTemp => MIMTXBWDATA_OUT(25), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(26), + GlitchData => MIMTXBWDATA26_GlitchData, + OutSignalName => "MIMTXBWDATA(26)", + OutTemp => MIMTXBWDATA_OUT(26), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(26), + GlitchData => MIMTXBWDATA26_GlitchData, + OutSignalName => "MIMTXBWDATA(26)", + OutTemp => MIMTXBWDATA_OUT(26), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(27), + GlitchData => MIMTXBWDATA27_GlitchData, + OutSignalName => "MIMTXBWDATA(27)", + OutTemp => MIMTXBWDATA_OUT(27), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(27), + GlitchData => MIMTXBWDATA27_GlitchData, + OutSignalName => "MIMTXBWDATA(27)", + OutTemp => MIMTXBWDATA_OUT(27), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(28), + GlitchData => MIMTXBWDATA28_GlitchData, + OutSignalName => "MIMTXBWDATA(28)", + OutTemp => MIMTXBWDATA_OUT(28), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(28), + GlitchData => MIMTXBWDATA28_GlitchData, + OutSignalName => "MIMTXBWDATA(28)", + OutTemp => MIMTXBWDATA_OUT(28), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(29), + GlitchData => MIMTXBWDATA29_GlitchData, + OutSignalName => "MIMTXBWDATA(29)", + OutTemp => MIMTXBWDATA_OUT(29), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(29), + GlitchData => MIMTXBWDATA29_GlitchData, + OutSignalName => "MIMTXBWDATA(29)", + OutTemp => MIMTXBWDATA_OUT(29), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(30), + GlitchData => MIMTXBWDATA30_GlitchData, + OutSignalName => "MIMTXBWDATA(30)", + OutTemp => MIMTXBWDATA_OUT(30), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(30), + GlitchData => MIMTXBWDATA30_GlitchData, + OutSignalName => "MIMTXBWDATA(30)", + OutTemp => MIMTXBWDATA_OUT(30), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(31), + GlitchData => MIMTXBWDATA31_GlitchData, + OutSignalName => "MIMTXBWDATA(31)", + OutTemp => MIMTXBWDATA_OUT(31), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(31), + GlitchData => MIMTXBWDATA31_GlitchData, + OutSignalName => "MIMTXBWDATA(31)", + OutTemp => MIMTXBWDATA_OUT(31), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(32), + GlitchData => MIMTXBWDATA32_GlitchData, + OutSignalName => "MIMTXBWDATA(32)", + OutTemp => MIMTXBWDATA_OUT(32), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(32), + GlitchData => MIMTXBWDATA32_GlitchData, + OutSignalName => "MIMTXBWDATA(32)", + OutTemp => MIMTXBWDATA_OUT(32), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(33), + GlitchData => MIMTXBWDATA33_GlitchData, + OutSignalName => "MIMTXBWDATA(33)", + OutTemp => MIMTXBWDATA_OUT(33), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(33), + GlitchData => MIMTXBWDATA33_GlitchData, + OutSignalName => "MIMTXBWDATA(33)", + OutTemp => MIMTXBWDATA_OUT(33), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(34), + GlitchData => MIMTXBWDATA34_GlitchData, + OutSignalName => "MIMTXBWDATA(34)", + OutTemp => MIMTXBWDATA_OUT(34), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(34), + GlitchData => MIMTXBWDATA34_GlitchData, + OutSignalName => "MIMTXBWDATA(34)", + OutTemp => MIMTXBWDATA_OUT(34), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(35), + GlitchData => MIMTXBWDATA35_GlitchData, + OutSignalName => "MIMTXBWDATA(35)", + OutTemp => MIMTXBWDATA_OUT(35), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(35), + GlitchData => MIMTXBWDATA35_GlitchData, + OutSignalName => "MIMTXBWDATA(35)", + OutTemp => MIMTXBWDATA_OUT(35), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(36), + GlitchData => MIMTXBWDATA36_GlitchData, + OutSignalName => "MIMTXBWDATA(36)", + OutTemp => MIMTXBWDATA_OUT(36), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(36), + GlitchData => MIMTXBWDATA36_GlitchData, + OutSignalName => "MIMTXBWDATA(36)", + OutTemp => MIMTXBWDATA_OUT(36), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(37), + GlitchData => MIMTXBWDATA37_GlitchData, + OutSignalName => "MIMTXBWDATA(37)", + OutTemp => MIMTXBWDATA_OUT(37), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(37), + GlitchData => MIMTXBWDATA37_GlitchData, + OutSignalName => "MIMTXBWDATA(37)", + OutTemp => MIMTXBWDATA_OUT(37), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(38), + GlitchData => MIMTXBWDATA38_GlitchData, + OutSignalName => "MIMTXBWDATA(38)", + OutTemp => MIMTXBWDATA_OUT(38), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(38), + GlitchData => MIMTXBWDATA38_GlitchData, + OutSignalName => "MIMTXBWDATA(38)", + OutTemp => MIMTXBWDATA_OUT(38), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(39), + GlitchData => MIMTXBWDATA39_GlitchData, + OutSignalName => "MIMTXBWDATA(39)", + OutTemp => MIMTXBWDATA_OUT(39), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(39), + GlitchData => MIMTXBWDATA39_GlitchData, + OutSignalName => "MIMTXBWDATA(39)", + OutTemp => MIMTXBWDATA_OUT(39), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(40), + GlitchData => MIMTXBWDATA40_GlitchData, + OutSignalName => "MIMTXBWDATA(40)", + OutTemp => MIMTXBWDATA_OUT(40), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(40), + GlitchData => MIMTXBWDATA40_GlitchData, + OutSignalName => "MIMTXBWDATA(40)", + OutTemp => MIMTXBWDATA_OUT(40), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(41), + GlitchData => MIMTXBWDATA41_GlitchData, + OutSignalName => "MIMTXBWDATA(41)", + OutTemp => MIMTXBWDATA_OUT(41), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(41), + GlitchData => MIMTXBWDATA41_GlitchData, + OutSignalName => "MIMTXBWDATA(41)", + OutTemp => MIMTXBWDATA_OUT(41), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(42), + GlitchData => MIMTXBWDATA42_GlitchData, + OutSignalName => "MIMTXBWDATA(42)", + OutTemp => MIMTXBWDATA_OUT(42), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(42), + GlitchData => MIMTXBWDATA42_GlitchData, + OutSignalName => "MIMTXBWDATA(42)", + OutTemp => MIMTXBWDATA_OUT(42), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(43), + GlitchData => MIMTXBWDATA43_GlitchData, + OutSignalName => "MIMTXBWDATA(43)", + OutTemp => MIMTXBWDATA_OUT(43), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(43), + GlitchData => MIMTXBWDATA43_GlitchData, + OutSignalName => "MIMTXBWDATA(43)", + OutTemp => MIMTXBWDATA_OUT(43), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(44), + GlitchData => MIMTXBWDATA44_GlitchData, + OutSignalName => "MIMTXBWDATA(44)", + OutTemp => MIMTXBWDATA_OUT(44), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(44), + GlitchData => MIMTXBWDATA44_GlitchData, + OutSignalName => "MIMTXBWDATA(44)", + OutTemp => MIMTXBWDATA_OUT(44), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(45), + GlitchData => MIMTXBWDATA45_GlitchData, + OutSignalName => "MIMTXBWDATA(45)", + OutTemp => MIMTXBWDATA_OUT(45), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(45), + GlitchData => MIMTXBWDATA45_GlitchData, + OutSignalName => "MIMTXBWDATA(45)", + OutTemp => MIMTXBWDATA_OUT(45), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(46), + GlitchData => MIMTXBWDATA46_GlitchData, + OutSignalName => "MIMTXBWDATA(46)", + OutTemp => MIMTXBWDATA_OUT(46), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(46), + GlitchData => MIMTXBWDATA46_GlitchData, + OutSignalName => "MIMTXBWDATA(46)", + OutTemp => MIMTXBWDATA_OUT(46), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(47), + GlitchData => MIMTXBWDATA47_GlitchData, + OutSignalName => "MIMTXBWDATA(47)", + OutTemp => MIMTXBWDATA_OUT(47), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(47), + GlitchData => MIMTXBWDATA47_GlitchData, + OutSignalName => "MIMTXBWDATA(47)", + OutTemp => MIMTXBWDATA_OUT(47), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(48), + GlitchData => MIMTXBWDATA48_GlitchData, + OutSignalName => "MIMTXBWDATA(48)", + OutTemp => MIMTXBWDATA_OUT(48), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(48), + GlitchData => MIMTXBWDATA48_GlitchData, + OutSignalName => "MIMTXBWDATA(48)", + OutTemp => MIMTXBWDATA_OUT(48), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(49), + GlitchData => MIMTXBWDATA49_GlitchData, + OutSignalName => "MIMTXBWDATA(49)", + OutTemp => MIMTXBWDATA_OUT(49), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(49), + GlitchData => MIMTXBWDATA49_GlitchData, + OutSignalName => "MIMTXBWDATA(49)", + OutTemp => MIMTXBWDATA_OUT(49), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(50), + GlitchData => MIMTXBWDATA50_GlitchData, + OutSignalName => "MIMTXBWDATA(50)", + OutTemp => MIMTXBWDATA_OUT(50), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(50), + GlitchData => MIMTXBWDATA50_GlitchData, + OutSignalName => "MIMTXBWDATA(50)", + OutTemp => MIMTXBWDATA_OUT(50), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(51), + GlitchData => MIMTXBWDATA51_GlitchData, + OutSignalName => "MIMTXBWDATA(51)", + OutTemp => MIMTXBWDATA_OUT(51), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(51), + GlitchData => MIMTXBWDATA51_GlitchData, + OutSignalName => "MIMTXBWDATA(51)", + OutTemp => MIMTXBWDATA_OUT(51), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(52), + GlitchData => MIMTXBWDATA52_GlitchData, + OutSignalName => "MIMTXBWDATA(52)", + OutTemp => MIMTXBWDATA_OUT(52), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(52), + GlitchData => MIMTXBWDATA52_GlitchData, + OutSignalName => "MIMTXBWDATA(52)", + OutTemp => MIMTXBWDATA_OUT(52), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(53), + GlitchData => MIMTXBWDATA53_GlitchData, + OutSignalName => "MIMTXBWDATA(53)", + OutTemp => MIMTXBWDATA_OUT(53), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(53), + GlitchData => MIMTXBWDATA53_GlitchData, + OutSignalName => "MIMTXBWDATA(53)", + OutTemp => MIMTXBWDATA_OUT(53), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(54), + GlitchData => MIMTXBWDATA54_GlitchData, + OutSignalName => "MIMTXBWDATA(54)", + OutTemp => MIMTXBWDATA_OUT(54), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(54), + GlitchData => MIMTXBWDATA54_GlitchData, + OutSignalName => "MIMTXBWDATA(54)", + OutTemp => MIMTXBWDATA_OUT(54), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(55), + GlitchData => MIMTXBWDATA55_GlitchData, + OutSignalName => "MIMTXBWDATA(55)", + OutTemp => MIMTXBWDATA_OUT(55), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(55), + GlitchData => MIMTXBWDATA55_GlitchData, + OutSignalName => "MIMTXBWDATA(55)", + OutTemp => MIMTXBWDATA_OUT(55), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(56), + GlitchData => MIMTXBWDATA56_GlitchData, + OutSignalName => "MIMTXBWDATA(56)", + OutTemp => MIMTXBWDATA_OUT(56), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(56), + GlitchData => MIMTXBWDATA56_GlitchData, + OutSignalName => "MIMTXBWDATA(56)", + OutTemp => MIMTXBWDATA_OUT(56), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(57), + GlitchData => MIMTXBWDATA57_GlitchData, + OutSignalName => "MIMTXBWDATA(57)", + OutTemp => MIMTXBWDATA_OUT(57), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(57), + GlitchData => MIMTXBWDATA57_GlitchData, + OutSignalName => "MIMTXBWDATA(57)", + OutTemp => MIMTXBWDATA_OUT(57), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(58), + GlitchData => MIMTXBWDATA58_GlitchData, + OutSignalName => "MIMTXBWDATA(58)", + OutTemp => MIMTXBWDATA_OUT(58), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(58), + GlitchData => MIMTXBWDATA58_GlitchData, + OutSignalName => "MIMTXBWDATA(58)", + OutTemp => MIMTXBWDATA_OUT(58), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(59), + GlitchData => MIMTXBWDATA59_GlitchData, + OutSignalName => "MIMTXBWDATA(59)", + OutTemp => MIMTXBWDATA_OUT(59), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(59), + GlitchData => MIMTXBWDATA59_GlitchData, + OutSignalName => "MIMTXBWDATA(59)", + OutTemp => MIMTXBWDATA_OUT(59), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(60), + GlitchData => MIMTXBWDATA60_GlitchData, + OutSignalName => "MIMTXBWDATA(60)", + OutTemp => MIMTXBWDATA_OUT(60), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(60), + GlitchData => MIMTXBWDATA60_GlitchData, + OutSignalName => "MIMTXBWDATA(60)", + OutTemp => MIMTXBWDATA_OUT(60), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(61), + GlitchData => MIMTXBWDATA61_GlitchData, + OutSignalName => "MIMTXBWDATA(61)", + OutTemp => MIMTXBWDATA_OUT(61), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(61), + GlitchData => MIMTXBWDATA61_GlitchData, + OutSignalName => "MIMTXBWDATA(61)", + OutTemp => MIMTXBWDATA_OUT(61), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(62), + GlitchData => MIMTXBWDATA62_GlitchData, + OutSignalName => "MIMTXBWDATA(62)", + OutTemp => MIMTXBWDATA_OUT(62), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(62), + GlitchData => MIMTXBWDATA62_GlitchData, + OutSignalName => "MIMTXBWDATA(62)", + OutTemp => MIMTXBWDATA_OUT(62), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(63), + GlitchData => MIMTXBWDATA63_GlitchData, + OutSignalName => "MIMTXBWDATA(63)", + OutTemp => MIMTXBWDATA_OUT(63), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWDATA(63), + GlitchData => MIMTXBWDATA63_GlitchData, + OutSignalName => "MIMTXBWDATA(63)", + OutTemp => MIMTXBWDATA_OUT(63), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(0), + GlitchData => MIMTXBWADD0_GlitchData, + OutSignalName => "MIMTXBWADD(0)", + OutTemp => MIMTXBWADD_OUT(0), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(0), + GlitchData => MIMTXBWADD0_GlitchData, + OutSignalName => "MIMTXBWADD(0)", + OutTemp => MIMTXBWADD_OUT(0), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(1), + GlitchData => MIMTXBWADD1_GlitchData, + OutSignalName => "MIMTXBWADD(1)", + OutTemp => MIMTXBWADD_OUT(1), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(1), + GlitchData => MIMTXBWADD1_GlitchData, + OutSignalName => "MIMTXBWADD(1)", + OutTemp => MIMTXBWADD_OUT(1), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(2), + GlitchData => MIMTXBWADD2_GlitchData, + OutSignalName => "MIMTXBWADD(2)", + OutTemp => MIMTXBWADD_OUT(2), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(2), + GlitchData => MIMTXBWADD2_GlitchData, + OutSignalName => "MIMTXBWADD(2)", + OutTemp => MIMTXBWADD_OUT(2), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(3), + GlitchData => MIMTXBWADD3_GlitchData, + OutSignalName => "MIMTXBWADD(3)", + OutTemp => MIMTXBWADD_OUT(3), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(3), + GlitchData => MIMTXBWADD3_GlitchData, + OutSignalName => "MIMTXBWADD(3)", + OutTemp => MIMTXBWADD_OUT(3), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(4), + GlitchData => MIMTXBWADD4_GlitchData, + OutSignalName => "MIMTXBWADD(4)", + OutTemp => MIMTXBWADD_OUT(4), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(4), + GlitchData => MIMTXBWADD4_GlitchData, + OutSignalName => "MIMTXBWADD(4)", + OutTemp => MIMTXBWADD_OUT(4), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(5), + GlitchData => MIMTXBWADD5_GlitchData, + OutSignalName => "MIMTXBWADD(5)", + OutTemp => MIMTXBWADD_OUT(5), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(5), + GlitchData => MIMTXBWADD5_GlitchData, + OutSignalName => "MIMTXBWADD(5)", + OutTemp => MIMTXBWADD_OUT(5), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(6), + GlitchData => MIMTXBWADD6_GlitchData, + OutSignalName => "MIMTXBWADD(6)", + OutTemp => MIMTXBWADD_OUT(6), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(6), + GlitchData => MIMTXBWADD6_GlitchData, + OutSignalName => "MIMTXBWADD(6)", + OutTemp => MIMTXBWADD_OUT(6), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(7), + GlitchData => MIMTXBWADD7_GlitchData, + OutSignalName => "MIMTXBWADD(7)", + OutTemp => MIMTXBWADD_OUT(7), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(7), + GlitchData => MIMTXBWADD7_GlitchData, + OutSignalName => "MIMTXBWADD(7)", + OutTemp => MIMTXBWADD_OUT(7), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(8), + GlitchData => MIMTXBWADD8_GlitchData, + OutSignalName => "MIMTXBWADD(8)", + OutTemp => MIMTXBWADD_OUT(8), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(8), + GlitchData => MIMTXBWADD8_GlitchData, + OutSignalName => "MIMTXBWADD(8)", + OutTemp => MIMTXBWADD_OUT(8), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(9), + GlitchData => MIMTXBWADD9_GlitchData, + OutSignalName => "MIMTXBWADD(9)", + OutTemp => MIMTXBWADD_OUT(9), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(9), + GlitchData => MIMTXBWADD9_GlitchData, + OutSignalName => "MIMTXBWADD(9)", + OutTemp => MIMTXBWADD_OUT(9), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(10), + GlitchData => MIMTXBWADD10_GlitchData, + OutSignalName => "MIMTXBWADD(10)", + OutTemp => MIMTXBWADD_OUT(10), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(10), + GlitchData => MIMTXBWADD10_GlitchData, + OutSignalName => "MIMTXBWADD(10)", + OutTemp => MIMTXBWADD_OUT(10), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(11), + GlitchData => MIMTXBWADD11_GlitchData, + OutSignalName => "MIMTXBWADD(11)", + OutTemp => MIMTXBWADD_OUT(11), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(11), + GlitchData => MIMTXBWADD11_GlitchData, + OutSignalName => "MIMTXBWADD(11)", + OutTemp => MIMTXBWADD_OUT(11), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(12), + GlitchData => MIMTXBWADD12_GlitchData, + OutSignalName => "MIMTXBWADD(12)", + OutTemp => MIMTXBWADD_OUT(12), + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWADD(12), + GlitchData => MIMTXBWADD12_GlitchData, + OutSignalName => "MIMTXBWADD(12)", + OutTemp => MIMTXBWADD_OUT(12), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(0), + GlitchData => MIMTXBRADD0_GlitchData, + OutSignalName => "MIMTXBRADD(0)", + OutTemp => MIMTXBRADD_OUT(0), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(1), + GlitchData => MIMTXBRADD1_GlitchData, + OutSignalName => "MIMTXBRADD(1)", + OutTemp => MIMTXBRADD_OUT(1), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(2), + GlitchData => MIMTXBRADD2_GlitchData, + OutSignalName => "MIMTXBRADD(2)", + OutTemp => MIMTXBRADD_OUT(2), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(3), + GlitchData => MIMTXBRADD3_GlitchData, + OutSignalName => "MIMTXBRADD(3)", + OutTemp => MIMTXBRADD_OUT(3), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(4), + GlitchData => MIMTXBRADD4_GlitchData, + OutSignalName => "MIMTXBRADD(4)", + OutTemp => MIMTXBRADD_OUT(4), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(5), + GlitchData => MIMTXBRADD5_GlitchData, + OutSignalName => "MIMTXBRADD(5)", + OutTemp => MIMTXBRADD_OUT(5), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(6), + GlitchData => MIMTXBRADD6_GlitchData, + OutSignalName => "MIMTXBRADD(6)", + OutTemp => MIMTXBRADD_OUT(6), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(7), + GlitchData => MIMTXBRADD7_GlitchData, + OutSignalName => "MIMTXBRADD(7)", + OutTemp => MIMTXBRADD_OUT(7), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(8), + GlitchData => MIMTXBRADD8_GlitchData, + OutSignalName => "MIMTXBRADD(8)", + OutTemp => MIMTXBRADD_OUT(8), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(9), + GlitchData => MIMTXBRADD9_GlitchData, + OutSignalName => "MIMTXBRADD(9)", + OutTemp => MIMTXBRADD_OUT(9), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(10), + GlitchData => MIMTXBRADD10_GlitchData, + OutSignalName => "MIMTXBRADD(10)", + OutTemp => MIMTXBRADD_OUT(10), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(11), + GlitchData => MIMTXBRADD11_GlitchData, + OutSignalName => "MIMTXBRADD(11)", + OutTemp => MIMTXBRADD_OUT(11), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBRADD(12), + GlitchData => MIMTXBRADD12_GlitchData, + OutSignalName => "MIMTXBRADD(12)", + OutTemp => MIMTXBRADD_OUT(12), + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWEN, + GlitchData => MIMTXBWEN_GlitchData, + OutSignalName => "MIMTXBWEN", + OutTemp => MIMTXBWEN_OUT, + Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBWEN, + GlitchData => MIMTXBWEN_GlitchData, + OutSignalName => "MIMTXBWEN", + OutTemp => MIMTXBWEN_OUT, + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMTXBREN, + GlitchData => MIMTXBREN_GlitchData, + OutSignalName => "MIMTXBREN", + OutTemp => MIMTXBREN_OUT, + Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(0), + GlitchData => MIMDLLBWDATA0_GlitchData, + OutSignalName => "MIMDLLBWDATA(0)", + OutTemp => MIMDLLBWDATA_OUT(0), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(1), + GlitchData => MIMDLLBWDATA1_GlitchData, + OutSignalName => "MIMDLLBWDATA(1)", + OutTemp => MIMDLLBWDATA_OUT(1), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(2), + GlitchData => MIMDLLBWDATA2_GlitchData, + OutSignalName => "MIMDLLBWDATA(2)", + OutTemp => MIMDLLBWDATA_OUT(2), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(3), + GlitchData => MIMDLLBWDATA3_GlitchData, + OutSignalName => "MIMDLLBWDATA(3)", + OutTemp => MIMDLLBWDATA_OUT(3), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(4), + GlitchData => MIMDLLBWDATA4_GlitchData, + OutSignalName => "MIMDLLBWDATA(4)", + OutTemp => MIMDLLBWDATA_OUT(4), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(5), + GlitchData => MIMDLLBWDATA5_GlitchData, + OutSignalName => "MIMDLLBWDATA(5)", + OutTemp => MIMDLLBWDATA_OUT(5), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(6), + GlitchData => MIMDLLBWDATA6_GlitchData, + OutSignalName => "MIMDLLBWDATA(6)", + OutTemp => MIMDLLBWDATA_OUT(6), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(7), + GlitchData => MIMDLLBWDATA7_GlitchData, + OutSignalName => "MIMDLLBWDATA(7)", + OutTemp => MIMDLLBWDATA_OUT(7), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(8), + GlitchData => MIMDLLBWDATA8_GlitchData, + OutSignalName => "MIMDLLBWDATA(8)", + OutTemp => MIMDLLBWDATA_OUT(8), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(9), + GlitchData => MIMDLLBWDATA9_GlitchData, + OutSignalName => "MIMDLLBWDATA(9)", + OutTemp => MIMDLLBWDATA_OUT(9), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(10), + GlitchData => MIMDLLBWDATA10_GlitchData, + OutSignalName => "MIMDLLBWDATA(10)", + OutTemp => MIMDLLBWDATA_OUT(10), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(11), + GlitchData => MIMDLLBWDATA11_GlitchData, + OutSignalName => "MIMDLLBWDATA(11)", + OutTemp => MIMDLLBWDATA_OUT(11), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(12), + GlitchData => MIMDLLBWDATA12_GlitchData, + OutSignalName => "MIMDLLBWDATA(12)", + OutTemp => MIMDLLBWDATA_OUT(12), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(13), + GlitchData => MIMDLLBWDATA13_GlitchData, + OutSignalName => "MIMDLLBWDATA(13)", + OutTemp => MIMDLLBWDATA_OUT(13), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(14), + GlitchData => MIMDLLBWDATA14_GlitchData, + OutSignalName => "MIMDLLBWDATA(14)", + OutTemp => MIMDLLBWDATA_OUT(14), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(15), + GlitchData => MIMDLLBWDATA15_GlitchData, + OutSignalName => "MIMDLLBWDATA(15)", + OutTemp => MIMDLLBWDATA_OUT(15), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(16), + GlitchData => MIMDLLBWDATA16_GlitchData, + OutSignalName => "MIMDLLBWDATA(16)", + OutTemp => MIMDLLBWDATA_OUT(16), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(17), + GlitchData => MIMDLLBWDATA17_GlitchData, + OutSignalName => "MIMDLLBWDATA(17)", + OutTemp => MIMDLLBWDATA_OUT(17), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(18), + GlitchData => MIMDLLBWDATA18_GlitchData, + OutSignalName => "MIMDLLBWDATA(18)", + OutTemp => MIMDLLBWDATA_OUT(18), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(19), + GlitchData => MIMDLLBWDATA19_GlitchData, + OutSignalName => "MIMDLLBWDATA(19)", + OutTemp => MIMDLLBWDATA_OUT(19), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(20), + GlitchData => MIMDLLBWDATA20_GlitchData, + OutSignalName => "MIMDLLBWDATA(20)", + OutTemp => MIMDLLBWDATA_OUT(20), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(21), + GlitchData => MIMDLLBWDATA21_GlitchData, + OutSignalName => "MIMDLLBWDATA(21)", + OutTemp => MIMDLLBWDATA_OUT(21), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(22), + GlitchData => MIMDLLBWDATA22_GlitchData, + OutSignalName => "MIMDLLBWDATA(22)", + OutTemp => MIMDLLBWDATA_OUT(22), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(23), + GlitchData => MIMDLLBWDATA23_GlitchData, + OutSignalName => "MIMDLLBWDATA(23)", + OutTemp => MIMDLLBWDATA_OUT(23), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(24), + GlitchData => MIMDLLBWDATA24_GlitchData, + OutSignalName => "MIMDLLBWDATA(24)", + OutTemp => MIMDLLBWDATA_OUT(24), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(25), + GlitchData => MIMDLLBWDATA25_GlitchData, + OutSignalName => "MIMDLLBWDATA(25)", + OutTemp => MIMDLLBWDATA_OUT(25), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(26), + GlitchData => MIMDLLBWDATA26_GlitchData, + OutSignalName => "MIMDLLBWDATA(26)", + OutTemp => MIMDLLBWDATA_OUT(26), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(27), + GlitchData => MIMDLLBWDATA27_GlitchData, + OutSignalName => "MIMDLLBWDATA(27)", + OutTemp => MIMDLLBWDATA_OUT(27), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(28), + GlitchData => MIMDLLBWDATA28_GlitchData, + OutSignalName => "MIMDLLBWDATA(28)", + OutTemp => MIMDLLBWDATA_OUT(28), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(29), + GlitchData => MIMDLLBWDATA29_GlitchData, + OutSignalName => "MIMDLLBWDATA(29)", + OutTemp => MIMDLLBWDATA_OUT(29), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(30), + GlitchData => MIMDLLBWDATA30_GlitchData, + OutSignalName => "MIMDLLBWDATA(30)", + OutTemp => MIMDLLBWDATA_OUT(30), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(31), + GlitchData => MIMDLLBWDATA31_GlitchData, + OutSignalName => "MIMDLLBWDATA(31)", + OutTemp => MIMDLLBWDATA_OUT(31), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(32), + GlitchData => MIMDLLBWDATA32_GlitchData, + OutSignalName => "MIMDLLBWDATA(32)", + OutTemp => MIMDLLBWDATA_OUT(32), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(33), + GlitchData => MIMDLLBWDATA33_GlitchData, + OutSignalName => "MIMDLLBWDATA(33)", + OutTemp => MIMDLLBWDATA_OUT(33), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(34), + GlitchData => MIMDLLBWDATA34_GlitchData, + OutSignalName => "MIMDLLBWDATA(34)", + OutTemp => MIMDLLBWDATA_OUT(34), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(35), + GlitchData => MIMDLLBWDATA35_GlitchData, + OutSignalName => "MIMDLLBWDATA(35)", + OutTemp => MIMDLLBWDATA_OUT(35), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(36), + GlitchData => MIMDLLBWDATA36_GlitchData, + OutSignalName => "MIMDLLBWDATA(36)", + OutTemp => MIMDLLBWDATA_OUT(36), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(37), + GlitchData => MIMDLLBWDATA37_GlitchData, + OutSignalName => "MIMDLLBWDATA(37)", + OutTemp => MIMDLLBWDATA_OUT(37), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(38), + GlitchData => MIMDLLBWDATA38_GlitchData, + OutSignalName => "MIMDLLBWDATA(38)", + OutTemp => MIMDLLBWDATA_OUT(38), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(39), + GlitchData => MIMDLLBWDATA39_GlitchData, + OutSignalName => "MIMDLLBWDATA(39)", + OutTemp => MIMDLLBWDATA_OUT(39), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(40), + GlitchData => MIMDLLBWDATA40_GlitchData, + OutSignalName => "MIMDLLBWDATA(40)", + OutTemp => MIMDLLBWDATA_OUT(40), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(41), + GlitchData => MIMDLLBWDATA41_GlitchData, + OutSignalName => "MIMDLLBWDATA(41)", + OutTemp => MIMDLLBWDATA_OUT(41), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(42), + GlitchData => MIMDLLBWDATA42_GlitchData, + OutSignalName => "MIMDLLBWDATA(42)", + OutTemp => MIMDLLBWDATA_OUT(42), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(43), + GlitchData => MIMDLLBWDATA43_GlitchData, + OutSignalName => "MIMDLLBWDATA(43)", + OutTemp => MIMDLLBWDATA_OUT(43), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(44), + GlitchData => MIMDLLBWDATA44_GlitchData, + OutSignalName => "MIMDLLBWDATA(44)", + OutTemp => MIMDLLBWDATA_OUT(44), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(45), + GlitchData => MIMDLLBWDATA45_GlitchData, + OutSignalName => "MIMDLLBWDATA(45)", + OutTemp => MIMDLLBWDATA_OUT(45), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(46), + GlitchData => MIMDLLBWDATA46_GlitchData, + OutSignalName => "MIMDLLBWDATA(46)", + OutTemp => MIMDLLBWDATA_OUT(46), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(47), + GlitchData => MIMDLLBWDATA47_GlitchData, + OutSignalName => "MIMDLLBWDATA(47)", + OutTemp => MIMDLLBWDATA_OUT(47), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(48), + GlitchData => MIMDLLBWDATA48_GlitchData, + OutSignalName => "MIMDLLBWDATA(48)", + OutTemp => MIMDLLBWDATA_OUT(48), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(49), + GlitchData => MIMDLLBWDATA49_GlitchData, + OutSignalName => "MIMDLLBWDATA(49)", + OutTemp => MIMDLLBWDATA_OUT(49), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(50), + GlitchData => MIMDLLBWDATA50_GlitchData, + OutSignalName => "MIMDLLBWDATA(50)", + OutTemp => MIMDLLBWDATA_OUT(50), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(51), + GlitchData => MIMDLLBWDATA51_GlitchData, + OutSignalName => "MIMDLLBWDATA(51)", + OutTemp => MIMDLLBWDATA_OUT(51), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(52), + GlitchData => MIMDLLBWDATA52_GlitchData, + OutSignalName => "MIMDLLBWDATA(52)", + OutTemp => MIMDLLBWDATA_OUT(52), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(53), + GlitchData => MIMDLLBWDATA53_GlitchData, + OutSignalName => "MIMDLLBWDATA(53)", + OutTemp => MIMDLLBWDATA_OUT(53), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(54), + GlitchData => MIMDLLBWDATA54_GlitchData, + OutSignalName => "MIMDLLBWDATA(54)", + OutTemp => MIMDLLBWDATA_OUT(54), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(55), + GlitchData => MIMDLLBWDATA55_GlitchData, + OutSignalName => "MIMDLLBWDATA(55)", + OutTemp => MIMDLLBWDATA_OUT(55), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(56), + GlitchData => MIMDLLBWDATA56_GlitchData, + OutSignalName => "MIMDLLBWDATA(56)", + OutTemp => MIMDLLBWDATA_OUT(56), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(57), + GlitchData => MIMDLLBWDATA57_GlitchData, + OutSignalName => "MIMDLLBWDATA(57)", + OutTemp => MIMDLLBWDATA_OUT(57), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(58), + GlitchData => MIMDLLBWDATA58_GlitchData, + OutSignalName => "MIMDLLBWDATA(58)", + OutTemp => MIMDLLBWDATA_OUT(58), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(59), + GlitchData => MIMDLLBWDATA59_GlitchData, + OutSignalName => "MIMDLLBWDATA(59)", + OutTemp => MIMDLLBWDATA_OUT(59), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(60), + GlitchData => MIMDLLBWDATA60_GlitchData, + OutSignalName => "MIMDLLBWDATA(60)", + OutTemp => MIMDLLBWDATA_OUT(60), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(61), + GlitchData => MIMDLLBWDATA61_GlitchData, + OutSignalName => "MIMDLLBWDATA(61)", + OutTemp => MIMDLLBWDATA_OUT(61), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(62), + GlitchData => MIMDLLBWDATA62_GlitchData, + OutSignalName => "MIMDLLBWDATA(62)", + OutTemp => MIMDLLBWDATA_OUT(62), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWDATA(63), + GlitchData => MIMDLLBWDATA63_GlitchData, + OutSignalName => "MIMDLLBWDATA(63)", + OutTemp => MIMDLLBWDATA_OUT(63), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(0), + GlitchData => MIMDLLBWADD0_GlitchData, + OutSignalName => "MIMDLLBWADD(0)", + OutTemp => MIMDLLBWADD_OUT(0), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(1), + GlitchData => MIMDLLBWADD1_GlitchData, + OutSignalName => "MIMDLLBWADD(1)", + OutTemp => MIMDLLBWADD_OUT(1), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(2), + GlitchData => MIMDLLBWADD2_GlitchData, + OutSignalName => "MIMDLLBWADD(2)", + OutTemp => MIMDLLBWADD_OUT(2), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(3), + GlitchData => MIMDLLBWADD3_GlitchData, + OutSignalName => "MIMDLLBWADD(3)", + OutTemp => MIMDLLBWADD_OUT(3), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(4), + GlitchData => MIMDLLBWADD4_GlitchData, + OutSignalName => "MIMDLLBWADD(4)", + OutTemp => MIMDLLBWADD_OUT(4), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(5), + GlitchData => MIMDLLBWADD5_GlitchData, + OutSignalName => "MIMDLLBWADD(5)", + OutTemp => MIMDLLBWADD_OUT(5), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(6), + GlitchData => MIMDLLBWADD6_GlitchData, + OutSignalName => "MIMDLLBWADD(6)", + OutTemp => MIMDLLBWADD_OUT(6), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(7), + GlitchData => MIMDLLBWADD7_GlitchData, + OutSignalName => "MIMDLLBWADD(7)", + OutTemp => MIMDLLBWADD_OUT(7), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(8), + GlitchData => MIMDLLBWADD8_GlitchData, + OutSignalName => "MIMDLLBWADD(8)", + OutTemp => MIMDLLBWADD_OUT(8), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(9), + GlitchData => MIMDLLBWADD9_GlitchData, + OutSignalName => "MIMDLLBWADD(9)", + OutTemp => MIMDLLBWADD_OUT(9), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(10), + GlitchData => MIMDLLBWADD10_GlitchData, + OutSignalName => "MIMDLLBWADD(10)", + OutTemp => MIMDLLBWADD_OUT(10), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWADD(11), + GlitchData => MIMDLLBWADD11_GlitchData, + OutSignalName => "MIMDLLBWADD(11)", + OutTemp => MIMDLLBWADD_OUT(11), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(0), + GlitchData => MIMDLLBRADD0_GlitchData, + OutSignalName => "MIMDLLBRADD(0)", + OutTemp => MIMDLLBRADD_OUT(0), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(1), + GlitchData => MIMDLLBRADD1_GlitchData, + OutSignalName => "MIMDLLBRADD(1)", + OutTemp => MIMDLLBRADD_OUT(1), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(2), + GlitchData => MIMDLLBRADD2_GlitchData, + OutSignalName => "MIMDLLBRADD(2)", + OutTemp => MIMDLLBRADD_OUT(2), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(3), + GlitchData => MIMDLLBRADD3_GlitchData, + OutSignalName => "MIMDLLBRADD(3)", + OutTemp => MIMDLLBRADD_OUT(3), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(4), + GlitchData => MIMDLLBRADD4_GlitchData, + OutSignalName => "MIMDLLBRADD(4)", + OutTemp => MIMDLLBRADD_OUT(4), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(5), + GlitchData => MIMDLLBRADD5_GlitchData, + OutSignalName => "MIMDLLBRADD(5)", + OutTemp => MIMDLLBRADD_OUT(5), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(6), + GlitchData => MIMDLLBRADD6_GlitchData, + OutSignalName => "MIMDLLBRADD(6)", + OutTemp => MIMDLLBRADD_OUT(6), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(7), + GlitchData => MIMDLLBRADD7_GlitchData, + OutSignalName => "MIMDLLBRADD(7)", + OutTemp => MIMDLLBRADD_OUT(7), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(8), + GlitchData => MIMDLLBRADD8_GlitchData, + OutSignalName => "MIMDLLBRADD(8)", + OutTemp => MIMDLLBRADD_OUT(8), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(9), + GlitchData => MIMDLLBRADD9_GlitchData, + OutSignalName => "MIMDLLBRADD(9)", + OutTemp => MIMDLLBRADD_OUT(9), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(10), + GlitchData => MIMDLLBRADD10_GlitchData, + OutSignalName => "MIMDLLBRADD(10)", + OutTemp => MIMDLLBRADD_OUT(10), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBRADD(11), + GlitchData => MIMDLLBRADD11_GlitchData, + OutSignalName => "MIMDLLBRADD(11)", + OutTemp => MIMDLLBRADD_OUT(11), + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBWEN, + GlitchData => MIMDLLBWEN_GlitchData, + OutSignalName => "MIMDLLBWEN", + OutTemp => MIMDLLBWEN_OUT, + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMDLLBREN, + GlitchData => MIMDLLBREN_GlitchData, + OutSignalName => "MIMDLLBREN", + OutTemp => MIMDLLBREN_OUT, + Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CRMRXHOTRESETN, + GlitchData => CRMRXHOTRESETN_GlitchData, + OutSignalName => "CRMRXHOTRESETN", + OutTemp => CRMRXHOTRESETN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CRMDOHOTRESETN, + GlitchData => CRMDOHOTRESETN_GlitchData, + OutSignalName => "CRMDOHOTRESETN", + OutTemp => CRMDOHOTRESETN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => CRMPWRSOFTRESETN, + GlitchData => CRMPWRSOFTRESETN_GlitchData, + OutSignalName => "CRMPWRSOFTRESETN", + OutTemp => CRMPWRSOFTRESETN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(0), + GlitchData => LLKTCSTATUS0_GlitchData, + OutSignalName => "LLKTCSTATUS(0)", + OutTemp => LLKTCSTATUS_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(0), + GlitchData => LLKTCSTATUS0_GlitchData, + OutSignalName => "LLKTCSTATUS(0)", + OutTemp => LLKTCSTATUS_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(1), + GlitchData => LLKTCSTATUS1_GlitchData, + OutSignalName => "LLKTCSTATUS(1)", + OutTemp => LLKTCSTATUS_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(1), + GlitchData => LLKTCSTATUS1_GlitchData, + OutSignalName => "LLKTCSTATUS(1)", + OutTemp => LLKTCSTATUS_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(2), + GlitchData => LLKTCSTATUS2_GlitchData, + OutSignalName => "LLKTCSTATUS(2)", + OutTemp => LLKTCSTATUS_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(2), + GlitchData => LLKTCSTATUS2_GlitchData, + OutSignalName => "LLKTCSTATUS(2)", + OutTemp => LLKTCSTATUS_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(3), + GlitchData => LLKTCSTATUS3_GlitchData, + OutSignalName => "LLKTCSTATUS(3)", + OutTemp => LLKTCSTATUS_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(3), + GlitchData => LLKTCSTATUS3_GlitchData, + OutSignalName => "LLKTCSTATUS(3)", + OutTemp => LLKTCSTATUS_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(4), + GlitchData => LLKTCSTATUS4_GlitchData, + OutSignalName => "LLKTCSTATUS(4)", + OutTemp => LLKTCSTATUS_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(4), + GlitchData => LLKTCSTATUS4_GlitchData, + OutSignalName => "LLKTCSTATUS(4)", + OutTemp => LLKTCSTATUS_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(5), + GlitchData => LLKTCSTATUS5_GlitchData, + OutSignalName => "LLKTCSTATUS(5)", + OutTemp => LLKTCSTATUS_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(5), + GlitchData => LLKTCSTATUS5_GlitchData, + OutSignalName => "LLKTCSTATUS(5)", + OutTemp => LLKTCSTATUS_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(6), + GlitchData => LLKTCSTATUS6_GlitchData, + OutSignalName => "LLKTCSTATUS(6)", + OutTemp => LLKTCSTATUS_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(6), + GlitchData => LLKTCSTATUS6_GlitchData, + OutSignalName => "LLKTCSTATUS(6)", + OutTemp => LLKTCSTATUS_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(7), + GlitchData => LLKTCSTATUS7_GlitchData, + OutSignalName => "LLKTCSTATUS(7)", + OutTemp => LLKTCSTATUS_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTCSTATUS(7), + GlitchData => LLKTCSTATUS7_GlitchData, + OutSignalName => "LLKTCSTATUS(7)", + OutTemp => LLKTCSTATUS_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXDSTRDYN, + GlitchData => LLKTXDSTRDYN_GlitchData, + OutSignalName => "LLKTXDSTRDYN", + OutTemp => LLKTXDSTRDYN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXDSTRDYN, + GlitchData => LLKTXDSTRDYN_GlitchData, + OutSignalName => "LLKTXDSTRDYN", + OutTemp => LLKTXDSTRDYN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(0), + GlitchData => LLKTXCHANSPACE0_GlitchData, + OutSignalName => "LLKTXCHANSPACE(0)", + OutTemp => LLKTXCHANSPACE_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(0), + GlitchData => LLKTXCHANSPACE0_GlitchData, + OutSignalName => "LLKTXCHANSPACE(0)", + OutTemp => LLKTXCHANSPACE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(1), + GlitchData => LLKTXCHANSPACE1_GlitchData, + OutSignalName => "LLKTXCHANSPACE(1)", + OutTemp => LLKTXCHANSPACE_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(1), + GlitchData => LLKTXCHANSPACE1_GlitchData, + OutSignalName => "LLKTXCHANSPACE(1)", + OutTemp => LLKTXCHANSPACE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(2), + GlitchData => LLKTXCHANSPACE2_GlitchData, + OutSignalName => "LLKTXCHANSPACE(2)", + OutTemp => LLKTXCHANSPACE_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(2), + GlitchData => LLKTXCHANSPACE2_GlitchData, + OutSignalName => "LLKTXCHANSPACE(2)", + OutTemp => LLKTXCHANSPACE_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(3), + GlitchData => LLKTXCHANSPACE3_GlitchData, + OutSignalName => "LLKTXCHANSPACE(3)", + OutTemp => LLKTXCHANSPACE_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(3), + GlitchData => LLKTXCHANSPACE3_GlitchData, + OutSignalName => "LLKTXCHANSPACE(3)", + OutTemp => LLKTXCHANSPACE_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(4), + GlitchData => LLKTXCHANSPACE4_GlitchData, + OutSignalName => "LLKTXCHANSPACE(4)", + OutTemp => LLKTXCHANSPACE_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(4), + GlitchData => LLKTXCHANSPACE4_GlitchData, + OutSignalName => "LLKTXCHANSPACE(4)", + OutTemp => LLKTXCHANSPACE_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(5), + GlitchData => LLKTXCHANSPACE5_GlitchData, + OutSignalName => "LLKTXCHANSPACE(5)", + OutTemp => LLKTXCHANSPACE_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(5), + GlitchData => LLKTXCHANSPACE5_GlitchData, + OutSignalName => "LLKTXCHANSPACE(5)", + OutTemp => LLKTXCHANSPACE_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(6), + GlitchData => LLKTXCHANSPACE6_GlitchData, + OutSignalName => "LLKTXCHANSPACE(6)", + OutTemp => LLKTXCHANSPACE_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(6), + GlitchData => LLKTXCHANSPACE6_GlitchData, + OutSignalName => "LLKTXCHANSPACE(6)", + OutTemp => LLKTXCHANSPACE_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(7), + GlitchData => LLKTXCHANSPACE7_GlitchData, + OutSignalName => "LLKTXCHANSPACE(7)", + OutTemp => LLKTXCHANSPACE_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(7), + GlitchData => LLKTXCHANSPACE7_GlitchData, + OutSignalName => "LLKTXCHANSPACE(7)", + OutTemp => LLKTXCHANSPACE_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(8), + GlitchData => LLKTXCHANSPACE8_GlitchData, + OutSignalName => "LLKTXCHANSPACE(8)", + OutTemp => LLKTXCHANSPACE_OUT(8), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(8), + GlitchData => LLKTXCHANSPACE8_GlitchData, + OutSignalName => "LLKTXCHANSPACE(8)", + OutTemp => LLKTXCHANSPACE_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(9), + GlitchData => LLKTXCHANSPACE9_GlitchData, + OutSignalName => "LLKTXCHANSPACE(9)", + OutTemp => LLKTXCHANSPACE_OUT(9), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHANSPACE(9), + GlitchData => LLKTXCHANSPACE9_GlitchData, + OutSignalName => "LLKTXCHANSPACE(9)", + OutTemp => LLKTXCHANSPACE_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(0), + GlitchData => LLKTXCHPOSTEDREADYN0_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(0)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(0), + GlitchData => LLKTXCHPOSTEDREADYN0_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(0)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(1), + GlitchData => LLKTXCHPOSTEDREADYN1_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(1)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(1), + GlitchData => LLKTXCHPOSTEDREADYN1_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(1)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(2), + GlitchData => LLKTXCHPOSTEDREADYN2_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(2)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(2), + GlitchData => LLKTXCHPOSTEDREADYN2_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(2)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(3), + GlitchData => LLKTXCHPOSTEDREADYN3_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(3)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(3), + GlitchData => LLKTXCHPOSTEDREADYN3_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(3)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(4), + GlitchData => LLKTXCHPOSTEDREADYN4_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(4)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(4), + GlitchData => LLKTXCHPOSTEDREADYN4_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(4)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(5), + GlitchData => LLKTXCHPOSTEDREADYN5_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(5)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(5), + GlitchData => LLKTXCHPOSTEDREADYN5_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(5)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(6), + GlitchData => LLKTXCHPOSTEDREADYN6_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(6)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(6), + GlitchData => LLKTXCHPOSTEDREADYN6_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(6)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(7), + GlitchData => LLKTXCHPOSTEDREADYN7_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(7)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHPOSTEDREADYN(7), + GlitchData => LLKTXCHPOSTEDREADYN7_GlitchData, + OutSignalName => "LLKTXCHPOSTEDREADYN(7)", + OutTemp => LLKTXCHPOSTEDREADYN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(0), + GlitchData => LLKTXCHNONPOSTEDREADYN0_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(0)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(0), + GlitchData => LLKTXCHNONPOSTEDREADYN0_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(0)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(1), + GlitchData => LLKTXCHNONPOSTEDREADYN1_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(1)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(1), + GlitchData => LLKTXCHNONPOSTEDREADYN1_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(1)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(2), + GlitchData => LLKTXCHNONPOSTEDREADYN2_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(2)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(2), + GlitchData => LLKTXCHNONPOSTEDREADYN2_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(2)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(3), + GlitchData => LLKTXCHNONPOSTEDREADYN3_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(3)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(3), + GlitchData => LLKTXCHNONPOSTEDREADYN3_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(3)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(4), + GlitchData => LLKTXCHNONPOSTEDREADYN4_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(4)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(4), + GlitchData => LLKTXCHNONPOSTEDREADYN4_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(4)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(5), + GlitchData => LLKTXCHNONPOSTEDREADYN5_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(5)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(5), + GlitchData => LLKTXCHNONPOSTEDREADYN5_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(5)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(6), + GlitchData => LLKTXCHNONPOSTEDREADYN6_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(6)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(6), + GlitchData => LLKTXCHNONPOSTEDREADYN6_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(6)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(7), + GlitchData => LLKTXCHNONPOSTEDREADYN7_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(7)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHNONPOSTEDREADYN(7), + GlitchData => LLKTXCHNONPOSTEDREADYN7_GlitchData, + OutSignalName => "LLKTXCHNONPOSTEDREADYN(7)", + OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(0), + GlitchData => LLKTXCHCOMPLETIONREADYN0_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(0)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(0), + GlitchData => LLKTXCHCOMPLETIONREADYN0_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(0)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(1), + GlitchData => LLKTXCHCOMPLETIONREADYN1_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(1)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(1), + GlitchData => LLKTXCHCOMPLETIONREADYN1_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(1)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(2), + GlitchData => LLKTXCHCOMPLETIONREADYN2_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(2)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(2), + GlitchData => LLKTXCHCOMPLETIONREADYN2_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(2)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(3), + GlitchData => LLKTXCHCOMPLETIONREADYN3_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(3)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(3), + GlitchData => LLKTXCHCOMPLETIONREADYN3_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(3)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(4), + GlitchData => LLKTXCHCOMPLETIONREADYN4_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(4)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(4), + GlitchData => LLKTXCHCOMPLETIONREADYN4_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(4)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(5), + GlitchData => LLKTXCHCOMPLETIONREADYN5_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(5)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(5), + GlitchData => LLKTXCHCOMPLETIONREADYN5_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(5)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(6), + GlitchData => LLKTXCHCOMPLETIONREADYN6_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(6)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(6), + GlitchData => LLKTXCHCOMPLETIONREADYN6_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(6)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(7), + GlitchData => LLKTXCHCOMPLETIONREADYN7_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(7)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCHCOMPLETIONREADYN(7), + GlitchData => LLKTXCHCOMPLETIONREADYN7_GlitchData, + OutSignalName => "LLKTXCHCOMPLETIONREADYN(7)", + OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCONFIGREADYN, + GlitchData => LLKTXCONFIGREADYN_GlitchData, + OutSignalName => "LLKTXCONFIGREADYN", + OutTemp => LLKTXCONFIGREADYN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKTXCONFIGREADYN, + GlitchData => LLKTXCONFIGREADYN_GlitchData, + OutSignalName => "LLKTXCONFIGREADYN", + OutTemp => LLKTXCONFIGREADYN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(0), + GlitchData => LLKRXDATA0_GlitchData, + OutSignalName => "LLKRXDATA(0)", + OutTemp => LLKRXDATA_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(0), + GlitchData => LLKRXDATA0_GlitchData, + OutSignalName => "LLKRXDATA(0)", + OutTemp => LLKRXDATA_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(1), + GlitchData => LLKRXDATA1_GlitchData, + OutSignalName => "LLKRXDATA(1)", + OutTemp => LLKRXDATA_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(1), + GlitchData => LLKRXDATA1_GlitchData, + OutSignalName => "LLKRXDATA(1)", + OutTemp => LLKRXDATA_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(2), + GlitchData => LLKRXDATA2_GlitchData, + OutSignalName => "LLKRXDATA(2)", + OutTemp => LLKRXDATA_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(2), + GlitchData => LLKRXDATA2_GlitchData, + OutSignalName => "LLKRXDATA(2)", + OutTemp => LLKRXDATA_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(3), + GlitchData => LLKRXDATA3_GlitchData, + OutSignalName => "LLKRXDATA(3)", + OutTemp => LLKRXDATA_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(3), + GlitchData => LLKRXDATA3_GlitchData, + OutSignalName => "LLKRXDATA(3)", + OutTemp => LLKRXDATA_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(4), + GlitchData => LLKRXDATA4_GlitchData, + OutSignalName => "LLKRXDATA(4)", + OutTemp => LLKRXDATA_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(4), + GlitchData => LLKRXDATA4_GlitchData, + OutSignalName => "LLKRXDATA(4)", + OutTemp => LLKRXDATA_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(5), + GlitchData => LLKRXDATA5_GlitchData, + OutSignalName => "LLKRXDATA(5)", + OutTemp => LLKRXDATA_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(5), + GlitchData => LLKRXDATA5_GlitchData, + OutSignalName => "LLKRXDATA(5)", + OutTemp => LLKRXDATA_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(6), + GlitchData => LLKRXDATA6_GlitchData, + OutSignalName => "LLKRXDATA(6)", + OutTemp => LLKRXDATA_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(6), + GlitchData => LLKRXDATA6_GlitchData, + OutSignalName => "LLKRXDATA(6)", + OutTemp => LLKRXDATA_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(7), + GlitchData => LLKRXDATA7_GlitchData, + OutSignalName => "LLKRXDATA(7)", + OutTemp => LLKRXDATA_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(7), + GlitchData => LLKRXDATA7_GlitchData, + OutSignalName => "LLKRXDATA(7)", + OutTemp => LLKRXDATA_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(8), + GlitchData => LLKRXDATA8_GlitchData, + OutSignalName => "LLKRXDATA(8)", + OutTemp => LLKRXDATA_OUT(8), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(8), + GlitchData => LLKRXDATA8_GlitchData, + OutSignalName => "LLKRXDATA(8)", + OutTemp => LLKRXDATA_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(9), + GlitchData => LLKRXDATA9_GlitchData, + OutSignalName => "LLKRXDATA(9)", + OutTemp => LLKRXDATA_OUT(9), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(9), + GlitchData => LLKRXDATA9_GlitchData, + OutSignalName => "LLKRXDATA(9)", + OutTemp => LLKRXDATA_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(10), + GlitchData => LLKRXDATA10_GlitchData, + OutSignalName => "LLKRXDATA(10)", + OutTemp => LLKRXDATA_OUT(10), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(10), + GlitchData => LLKRXDATA10_GlitchData, + OutSignalName => "LLKRXDATA(10)", + OutTemp => LLKRXDATA_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(11), + GlitchData => LLKRXDATA11_GlitchData, + OutSignalName => "LLKRXDATA(11)", + OutTemp => LLKRXDATA_OUT(11), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(11), + GlitchData => LLKRXDATA11_GlitchData, + OutSignalName => "LLKRXDATA(11)", + OutTemp => LLKRXDATA_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(12), + GlitchData => LLKRXDATA12_GlitchData, + OutSignalName => "LLKRXDATA(12)", + OutTemp => LLKRXDATA_OUT(12), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(12), + GlitchData => LLKRXDATA12_GlitchData, + OutSignalName => "LLKRXDATA(12)", + OutTemp => LLKRXDATA_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(13), + GlitchData => LLKRXDATA13_GlitchData, + OutSignalName => "LLKRXDATA(13)", + OutTemp => LLKRXDATA_OUT(13), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(13), + GlitchData => LLKRXDATA13_GlitchData, + OutSignalName => "LLKRXDATA(13)", + OutTemp => LLKRXDATA_OUT(13), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(14), + GlitchData => LLKRXDATA14_GlitchData, + OutSignalName => "LLKRXDATA(14)", + OutTemp => LLKRXDATA_OUT(14), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(14), + GlitchData => LLKRXDATA14_GlitchData, + OutSignalName => "LLKRXDATA(14)", + OutTemp => LLKRXDATA_OUT(14), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(15), + GlitchData => LLKRXDATA15_GlitchData, + OutSignalName => "LLKRXDATA(15)", + OutTemp => LLKRXDATA_OUT(15), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(15), + GlitchData => LLKRXDATA15_GlitchData, + OutSignalName => "LLKRXDATA(15)", + OutTemp => LLKRXDATA_OUT(15), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(16), + GlitchData => LLKRXDATA16_GlitchData, + OutSignalName => "LLKRXDATA(16)", + OutTemp => LLKRXDATA_OUT(16), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(16), + GlitchData => LLKRXDATA16_GlitchData, + OutSignalName => "LLKRXDATA(16)", + OutTemp => LLKRXDATA_OUT(16), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(17), + GlitchData => LLKRXDATA17_GlitchData, + OutSignalName => "LLKRXDATA(17)", + OutTemp => LLKRXDATA_OUT(17), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(17), + GlitchData => LLKRXDATA17_GlitchData, + OutSignalName => "LLKRXDATA(17)", + OutTemp => LLKRXDATA_OUT(17), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(18), + GlitchData => LLKRXDATA18_GlitchData, + OutSignalName => "LLKRXDATA(18)", + OutTemp => LLKRXDATA_OUT(18), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(18), + GlitchData => LLKRXDATA18_GlitchData, + OutSignalName => "LLKRXDATA(18)", + OutTemp => LLKRXDATA_OUT(18), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(19), + GlitchData => LLKRXDATA19_GlitchData, + OutSignalName => "LLKRXDATA(19)", + OutTemp => LLKRXDATA_OUT(19), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(19), + GlitchData => LLKRXDATA19_GlitchData, + OutSignalName => "LLKRXDATA(19)", + OutTemp => LLKRXDATA_OUT(19), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(20), + GlitchData => LLKRXDATA20_GlitchData, + OutSignalName => "LLKRXDATA(20)", + OutTemp => LLKRXDATA_OUT(20), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(20), + GlitchData => LLKRXDATA20_GlitchData, + OutSignalName => "LLKRXDATA(20)", + OutTemp => LLKRXDATA_OUT(20), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(21), + GlitchData => LLKRXDATA21_GlitchData, + OutSignalName => "LLKRXDATA(21)", + OutTemp => LLKRXDATA_OUT(21), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(21), + GlitchData => LLKRXDATA21_GlitchData, + OutSignalName => "LLKRXDATA(21)", + OutTemp => LLKRXDATA_OUT(21), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(22), + GlitchData => LLKRXDATA22_GlitchData, + OutSignalName => "LLKRXDATA(22)", + OutTemp => LLKRXDATA_OUT(22), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(22), + GlitchData => LLKRXDATA22_GlitchData, + OutSignalName => "LLKRXDATA(22)", + OutTemp => LLKRXDATA_OUT(22), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(23), + GlitchData => LLKRXDATA23_GlitchData, + OutSignalName => "LLKRXDATA(23)", + OutTemp => LLKRXDATA_OUT(23), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(23), + GlitchData => LLKRXDATA23_GlitchData, + OutSignalName => "LLKRXDATA(23)", + OutTemp => LLKRXDATA_OUT(23), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(24), + GlitchData => LLKRXDATA24_GlitchData, + OutSignalName => "LLKRXDATA(24)", + OutTemp => LLKRXDATA_OUT(24), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(24), + GlitchData => LLKRXDATA24_GlitchData, + OutSignalName => "LLKRXDATA(24)", + OutTemp => LLKRXDATA_OUT(24), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(25), + GlitchData => LLKRXDATA25_GlitchData, + OutSignalName => "LLKRXDATA(25)", + OutTemp => LLKRXDATA_OUT(25), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(25), + GlitchData => LLKRXDATA25_GlitchData, + OutSignalName => "LLKRXDATA(25)", + OutTemp => LLKRXDATA_OUT(25), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(26), + GlitchData => LLKRXDATA26_GlitchData, + OutSignalName => "LLKRXDATA(26)", + OutTemp => LLKRXDATA_OUT(26), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(26), + GlitchData => LLKRXDATA26_GlitchData, + OutSignalName => "LLKRXDATA(26)", + OutTemp => LLKRXDATA_OUT(26), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(27), + GlitchData => LLKRXDATA27_GlitchData, + OutSignalName => "LLKRXDATA(27)", + OutTemp => LLKRXDATA_OUT(27), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(27), + GlitchData => LLKRXDATA27_GlitchData, + OutSignalName => "LLKRXDATA(27)", + OutTemp => LLKRXDATA_OUT(27), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(28), + GlitchData => LLKRXDATA28_GlitchData, + OutSignalName => "LLKRXDATA(28)", + OutTemp => LLKRXDATA_OUT(28), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(28), + GlitchData => LLKRXDATA28_GlitchData, + OutSignalName => "LLKRXDATA(28)", + OutTemp => LLKRXDATA_OUT(28), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(29), + GlitchData => LLKRXDATA29_GlitchData, + OutSignalName => "LLKRXDATA(29)", + OutTemp => LLKRXDATA_OUT(29), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(29), + GlitchData => LLKRXDATA29_GlitchData, + OutSignalName => "LLKRXDATA(29)", + OutTemp => LLKRXDATA_OUT(29), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(30), + GlitchData => LLKRXDATA30_GlitchData, + OutSignalName => "LLKRXDATA(30)", + OutTemp => LLKRXDATA_OUT(30), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(30), + GlitchData => LLKRXDATA30_GlitchData, + OutSignalName => "LLKRXDATA(30)", + OutTemp => LLKRXDATA_OUT(30), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(31), + GlitchData => LLKRXDATA31_GlitchData, + OutSignalName => "LLKRXDATA(31)", + OutTemp => LLKRXDATA_OUT(31), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(31), + GlitchData => LLKRXDATA31_GlitchData, + OutSignalName => "LLKRXDATA(31)", + OutTemp => LLKRXDATA_OUT(31), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(32), + GlitchData => LLKRXDATA32_GlitchData, + OutSignalName => "LLKRXDATA(32)", + OutTemp => LLKRXDATA_OUT(32), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(32), + GlitchData => LLKRXDATA32_GlitchData, + OutSignalName => "LLKRXDATA(32)", + OutTemp => LLKRXDATA_OUT(32), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(33), + GlitchData => LLKRXDATA33_GlitchData, + OutSignalName => "LLKRXDATA(33)", + OutTemp => LLKRXDATA_OUT(33), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(33), + GlitchData => LLKRXDATA33_GlitchData, + OutSignalName => "LLKRXDATA(33)", + OutTemp => LLKRXDATA_OUT(33), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(34), + GlitchData => LLKRXDATA34_GlitchData, + OutSignalName => "LLKRXDATA(34)", + OutTemp => LLKRXDATA_OUT(34), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(34), + GlitchData => LLKRXDATA34_GlitchData, + OutSignalName => "LLKRXDATA(34)", + OutTemp => LLKRXDATA_OUT(34), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(35), + GlitchData => LLKRXDATA35_GlitchData, + OutSignalName => "LLKRXDATA(35)", + OutTemp => LLKRXDATA_OUT(35), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(35), + GlitchData => LLKRXDATA35_GlitchData, + OutSignalName => "LLKRXDATA(35)", + OutTemp => LLKRXDATA_OUT(35), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(36), + GlitchData => LLKRXDATA36_GlitchData, + OutSignalName => "LLKRXDATA(36)", + OutTemp => LLKRXDATA_OUT(36), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(36), + GlitchData => LLKRXDATA36_GlitchData, + OutSignalName => "LLKRXDATA(36)", + OutTemp => LLKRXDATA_OUT(36), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(37), + GlitchData => LLKRXDATA37_GlitchData, + OutSignalName => "LLKRXDATA(37)", + OutTemp => LLKRXDATA_OUT(37), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(37), + GlitchData => LLKRXDATA37_GlitchData, + OutSignalName => "LLKRXDATA(37)", + OutTemp => LLKRXDATA_OUT(37), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(38), + GlitchData => LLKRXDATA38_GlitchData, + OutSignalName => "LLKRXDATA(38)", + OutTemp => LLKRXDATA_OUT(38), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(38), + GlitchData => LLKRXDATA38_GlitchData, + OutSignalName => "LLKRXDATA(38)", + OutTemp => LLKRXDATA_OUT(38), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(39), + GlitchData => LLKRXDATA39_GlitchData, + OutSignalName => "LLKRXDATA(39)", + OutTemp => LLKRXDATA_OUT(39), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(39), + GlitchData => LLKRXDATA39_GlitchData, + OutSignalName => "LLKRXDATA(39)", + OutTemp => LLKRXDATA_OUT(39), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(40), + GlitchData => LLKRXDATA40_GlitchData, + OutSignalName => "LLKRXDATA(40)", + OutTemp => LLKRXDATA_OUT(40), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(40), + GlitchData => LLKRXDATA40_GlitchData, + OutSignalName => "LLKRXDATA(40)", + OutTemp => LLKRXDATA_OUT(40), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(41), + GlitchData => LLKRXDATA41_GlitchData, + OutSignalName => "LLKRXDATA(41)", + OutTemp => LLKRXDATA_OUT(41), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(41), + GlitchData => LLKRXDATA41_GlitchData, + OutSignalName => "LLKRXDATA(41)", + OutTemp => LLKRXDATA_OUT(41), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(42), + GlitchData => LLKRXDATA42_GlitchData, + OutSignalName => "LLKRXDATA(42)", + OutTemp => LLKRXDATA_OUT(42), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(42), + GlitchData => LLKRXDATA42_GlitchData, + OutSignalName => "LLKRXDATA(42)", + OutTemp => LLKRXDATA_OUT(42), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(43), + GlitchData => LLKRXDATA43_GlitchData, + OutSignalName => "LLKRXDATA(43)", + OutTemp => LLKRXDATA_OUT(43), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(43), + GlitchData => LLKRXDATA43_GlitchData, + OutSignalName => "LLKRXDATA(43)", + OutTemp => LLKRXDATA_OUT(43), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(44), + GlitchData => LLKRXDATA44_GlitchData, + OutSignalName => "LLKRXDATA(44)", + OutTemp => LLKRXDATA_OUT(44), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(44), + GlitchData => LLKRXDATA44_GlitchData, + OutSignalName => "LLKRXDATA(44)", + OutTemp => LLKRXDATA_OUT(44), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(45), + GlitchData => LLKRXDATA45_GlitchData, + OutSignalName => "LLKRXDATA(45)", + OutTemp => LLKRXDATA_OUT(45), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(45), + GlitchData => LLKRXDATA45_GlitchData, + OutSignalName => "LLKRXDATA(45)", + OutTemp => LLKRXDATA_OUT(45), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(46), + GlitchData => LLKRXDATA46_GlitchData, + OutSignalName => "LLKRXDATA(46)", + OutTemp => LLKRXDATA_OUT(46), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(46), + GlitchData => LLKRXDATA46_GlitchData, + OutSignalName => "LLKRXDATA(46)", + OutTemp => LLKRXDATA_OUT(46), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(47), + GlitchData => LLKRXDATA47_GlitchData, + OutSignalName => "LLKRXDATA(47)", + OutTemp => LLKRXDATA_OUT(47), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(47), + GlitchData => LLKRXDATA47_GlitchData, + OutSignalName => "LLKRXDATA(47)", + OutTemp => LLKRXDATA_OUT(47), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(48), + GlitchData => LLKRXDATA48_GlitchData, + OutSignalName => "LLKRXDATA(48)", + OutTemp => LLKRXDATA_OUT(48), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(48), + GlitchData => LLKRXDATA48_GlitchData, + OutSignalName => "LLKRXDATA(48)", + OutTemp => LLKRXDATA_OUT(48), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(49), + GlitchData => LLKRXDATA49_GlitchData, + OutSignalName => "LLKRXDATA(49)", + OutTemp => LLKRXDATA_OUT(49), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(49), + GlitchData => LLKRXDATA49_GlitchData, + OutSignalName => "LLKRXDATA(49)", + OutTemp => LLKRXDATA_OUT(49), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(50), + GlitchData => LLKRXDATA50_GlitchData, + OutSignalName => "LLKRXDATA(50)", + OutTemp => LLKRXDATA_OUT(50), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(50), + GlitchData => LLKRXDATA50_GlitchData, + OutSignalName => "LLKRXDATA(50)", + OutTemp => LLKRXDATA_OUT(50), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(51), + GlitchData => LLKRXDATA51_GlitchData, + OutSignalName => "LLKRXDATA(51)", + OutTemp => LLKRXDATA_OUT(51), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(51), + GlitchData => LLKRXDATA51_GlitchData, + OutSignalName => "LLKRXDATA(51)", + OutTemp => LLKRXDATA_OUT(51), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(52), + GlitchData => LLKRXDATA52_GlitchData, + OutSignalName => "LLKRXDATA(52)", + OutTemp => LLKRXDATA_OUT(52), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(52), + GlitchData => LLKRXDATA52_GlitchData, + OutSignalName => "LLKRXDATA(52)", + OutTemp => LLKRXDATA_OUT(52), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(53), + GlitchData => LLKRXDATA53_GlitchData, + OutSignalName => "LLKRXDATA(53)", + OutTemp => LLKRXDATA_OUT(53), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(53), + GlitchData => LLKRXDATA53_GlitchData, + OutSignalName => "LLKRXDATA(53)", + OutTemp => LLKRXDATA_OUT(53), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(54), + GlitchData => LLKRXDATA54_GlitchData, + OutSignalName => "LLKRXDATA(54)", + OutTemp => LLKRXDATA_OUT(54), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(54), + GlitchData => LLKRXDATA54_GlitchData, + OutSignalName => "LLKRXDATA(54)", + OutTemp => LLKRXDATA_OUT(54), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(55), + GlitchData => LLKRXDATA55_GlitchData, + OutSignalName => "LLKRXDATA(55)", + OutTemp => LLKRXDATA_OUT(55), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(55), + GlitchData => LLKRXDATA55_GlitchData, + OutSignalName => "LLKRXDATA(55)", + OutTemp => LLKRXDATA_OUT(55), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(56), + GlitchData => LLKRXDATA56_GlitchData, + OutSignalName => "LLKRXDATA(56)", + OutTemp => LLKRXDATA_OUT(56), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(56), + GlitchData => LLKRXDATA56_GlitchData, + OutSignalName => "LLKRXDATA(56)", + OutTemp => LLKRXDATA_OUT(56), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(57), + GlitchData => LLKRXDATA57_GlitchData, + OutSignalName => "LLKRXDATA(57)", + OutTemp => LLKRXDATA_OUT(57), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(57), + GlitchData => LLKRXDATA57_GlitchData, + OutSignalName => "LLKRXDATA(57)", + OutTemp => LLKRXDATA_OUT(57), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(58), + GlitchData => LLKRXDATA58_GlitchData, + OutSignalName => "LLKRXDATA(58)", + OutTemp => LLKRXDATA_OUT(58), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(58), + GlitchData => LLKRXDATA58_GlitchData, + OutSignalName => "LLKRXDATA(58)", + OutTemp => LLKRXDATA_OUT(58), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(59), + GlitchData => LLKRXDATA59_GlitchData, + OutSignalName => "LLKRXDATA(59)", + OutTemp => LLKRXDATA_OUT(59), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(59), + GlitchData => LLKRXDATA59_GlitchData, + OutSignalName => "LLKRXDATA(59)", + OutTemp => LLKRXDATA_OUT(59), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(60), + GlitchData => LLKRXDATA60_GlitchData, + OutSignalName => "LLKRXDATA(60)", + OutTemp => LLKRXDATA_OUT(60), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(60), + GlitchData => LLKRXDATA60_GlitchData, + OutSignalName => "LLKRXDATA(60)", + OutTemp => LLKRXDATA_OUT(60), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(61), + GlitchData => LLKRXDATA61_GlitchData, + OutSignalName => "LLKRXDATA(61)", + OutTemp => LLKRXDATA_OUT(61), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(61), + GlitchData => LLKRXDATA61_GlitchData, + OutSignalName => "LLKRXDATA(61)", + OutTemp => LLKRXDATA_OUT(61), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(62), + GlitchData => LLKRXDATA62_GlitchData, + OutSignalName => "LLKRXDATA(62)", + OutTemp => LLKRXDATA_OUT(62), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(62), + GlitchData => LLKRXDATA62_GlitchData, + OutSignalName => "LLKRXDATA(62)", + OutTemp => LLKRXDATA_OUT(62), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(63), + GlitchData => LLKRXDATA63_GlitchData, + OutSignalName => "LLKRXDATA(63)", + OutTemp => LLKRXDATA_OUT(63), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXDATA(63), + GlitchData => LLKRXDATA63_GlitchData, + OutSignalName => "LLKRXDATA(63)", + OutTemp => LLKRXDATA_OUT(63), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSRCRDYN, + GlitchData => LLKRXSRCRDYN_GlitchData, + OutSignalName => "LLKRXSRCRDYN", + OutTemp => LLKRXSRCRDYN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSRCRDYN, + GlitchData => LLKRXSRCRDYN_GlitchData, + OutSignalName => "LLKRXSRCRDYN", + OutTemp => LLKRXSRCRDYN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSRCLASTREQN, + GlitchData => LLKRXSRCLASTREQN_GlitchData, + OutSignalName => "LLKRXSRCLASTREQN", + OutTemp => LLKRXSRCLASTREQN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSRCLASTREQN, + GlitchData => LLKRXSRCLASTREQN_GlitchData, + OutSignalName => "LLKRXSRCLASTREQN", + OutTemp => LLKRXSRCLASTREQN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSRCDSCN, + GlitchData => LLKRXSRCDSCN_GlitchData, + OutSignalName => "LLKRXSRCDSCN", + OutTemp => LLKRXSRCDSCN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSRCDSCN, + GlitchData => LLKRXSRCDSCN_GlitchData, + OutSignalName => "LLKRXSRCDSCN", + OutTemp => LLKRXSRCDSCN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSOFN, + GlitchData => LLKRXSOFN_GlitchData, + OutSignalName => "LLKRXSOFN", + OutTemp => LLKRXSOFN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSOFN, + GlitchData => LLKRXSOFN_GlitchData, + OutSignalName => "LLKRXSOFN", + OutTemp => LLKRXSOFN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXEOFN, + GlitchData => LLKRXEOFN_GlitchData, + OutSignalName => "LLKRXEOFN", + OutTemp => LLKRXEOFN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXEOFN, + GlitchData => LLKRXEOFN_GlitchData, + OutSignalName => "LLKRXEOFN", + OutTemp => LLKRXEOFN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSOPN, + GlitchData => LLKRXSOPN_GlitchData, + OutSignalName => "LLKRXSOPN", + OutTemp => LLKRXSOPN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXSOPN, + GlitchData => LLKRXSOPN_GlitchData, + OutSignalName => "LLKRXSOPN", + OutTemp => LLKRXSOPN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXEOPN, + GlitchData => LLKRXEOPN_GlitchData, + OutSignalName => "LLKRXEOPN", + OutTemp => LLKRXEOPN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXEOPN, + GlitchData => LLKRXEOPN_GlitchData, + OutSignalName => "LLKRXEOPN", + OutTemp => LLKRXEOPN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXVALIDN(0), + GlitchData => LLKRXVALIDN0_GlitchData, + OutSignalName => "LLKRXVALIDN(0)", + OutTemp => LLKRXVALIDN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXVALIDN(0), + GlitchData => LLKRXVALIDN0_GlitchData, + OutSignalName => "LLKRXVALIDN(0)", + OutTemp => LLKRXVALIDN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXVALIDN(1), + GlitchData => LLKRXVALIDN1_GlitchData, + OutSignalName => "LLKRXVALIDN(1)", + OutTemp => LLKRXVALIDN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXVALIDN(1), + GlitchData => LLKRXVALIDN1_GlitchData, + OutSignalName => "LLKRXVALIDN(1)", + OutTemp => LLKRXVALIDN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(0), + GlitchData => LLKRXPREFERREDTYPE0_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(0)", + OutTemp => LLKRXPREFERREDTYPE_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(0), + GlitchData => LLKRXPREFERREDTYPE0_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(0)", + OutTemp => LLKRXPREFERREDTYPE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(1), + GlitchData => LLKRXPREFERREDTYPE1_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(1)", + OutTemp => LLKRXPREFERREDTYPE_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(1), + GlitchData => LLKRXPREFERREDTYPE1_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(1)", + OutTemp => LLKRXPREFERREDTYPE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(2), + GlitchData => LLKRXPREFERREDTYPE2_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(2)", + OutTemp => LLKRXPREFERREDTYPE_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(2), + GlitchData => LLKRXPREFERREDTYPE2_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(2)", + OutTemp => LLKRXPREFERREDTYPE_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(3), + GlitchData => LLKRXPREFERREDTYPE3_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(3)", + OutTemp => LLKRXPREFERREDTYPE_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(3), + GlitchData => LLKRXPREFERREDTYPE3_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(3)", + OutTemp => LLKRXPREFERREDTYPE_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(4), + GlitchData => LLKRXPREFERREDTYPE4_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(4)", + OutTemp => LLKRXPREFERREDTYPE_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(4), + GlitchData => LLKRXPREFERREDTYPE4_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(4)", + OutTemp => LLKRXPREFERREDTYPE_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(5), + GlitchData => LLKRXPREFERREDTYPE5_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(5)", + OutTemp => LLKRXPREFERREDTYPE_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(5), + GlitchData => LLKRXPREFERREDTYPE5_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(5)", + OutTemp => LLKRXPREFERREDTYPE_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(6), + GlitchData => LLKRXPREFERREDTYPE6_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(6)", + OutTemp => LLKRXPREFERREDTYPE_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(6), + GlitchData => LLKRXPREFERREDTYPE6_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(6)", + OutTemp => LLKRXPREFERREDTYPE_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(7), + GlitchData => LLKRXPREFERREDTYPE7_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(7)", + OutTemp => LLKRXPREFERREDTYPE_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(7), + GlitchData => LLKRXPREFERREDTYPE7_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(7)", + OutTemp => LLKRXPREFERREDTYPE_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(8), + GlitchData => LLKRXPREFERREDTYPE8_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(8)", + OutTemp => LLKRXPREFERREDTYPE_OUT(8), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(8), + GlitchData => LLKRXPREFERREDTYPE8_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(8)", + OutTemp => LLKRXPREFERREDTYPE_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(9), + GlitchData => LLKRXPREFERREDTYPE9_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(9)", + OutTemp => LLKRXPREFERREDTYPE_OUT(9), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(9), + GlitchData => LLKRXPREFERREDTYPE9_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(9)", + OutTemp => LLKRXPREFERREDTYPE_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(10), + GlitchData => LLKRXPREFERREDTYPE10_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(10)", + OutTemp => LLKRXPREFERREDTYPE_OUT(10), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(10), + GlitchData => LLKRXPREFERREDTYPE10_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(10)", + OutTemp => LLKRXPREFERREDTYPE_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(11), + GlitchData => LLKRXPREFERREDTYPE11_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(11)", + OutTemp => LLKRXPREFERREDTYPE_OUT(11), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(11), + GlitchData => LLKRXPREFERREDTYPE11_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(11)", + OutTemp => LLKRXPREFERREDTYPE_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(12), + GlitchData => LLKRXPREFERREDTYPE12_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(12)", + OutTemp => LLKRXPREFERREDTYPE_OUT(12), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(12), + GlitchData => LLKRXPREFERREDTYPE12_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(12)", + OutTemp => LLKRXPREFERREDTYPE_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(13), + GlitchData => LLKRXPREFERREDTYPE13_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(13)", + OutTemp => LLKRXPREFERREDTYPE_OUT(13), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(13), + GlitchData => LLKRXPREFERREDTYPE13_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(13)", + OutTemp => LLKRXPREFERREDTYPE_OUT(13), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(14), + GlitchData => LLKRXPREFERREDTYPE14_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(14)", + OutTemp => LLKRXPREFERREDTYPE_OUT(14), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(14), + GlitchData => LLKRXPREFERREDTYPE14_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(14)", + OutTemp => LLKRXPREFERREDTYPE_OUT(14), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(15), + GlitchData => LLKRXPREFERREDTYPE15_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(15)", + OutTemp => LLKRXPREFERREDTYPE_OUT(15), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXPREFERREDTYPE(15), + GlitchData => LLKRXPREFERREDTYPE15_GlitchData, + OutSignalName => "LLKRXPREFERREDTYPE(15)", + OutTemp => LLKRXPREFERREDTYPE_OUT(15), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(0), + GlitchData => LLKRXCHPOSTEDAVAILABLEN0_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(0)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(0), + GlitchData => LLKRXCHPOSTEDAVAILABLEN0_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(0)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(1), + GlitchData => LLKRXCHPOSTEDAVAILABLEN1_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(1)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(1), + GlitchData => LLKRXCHPOSTEDAVAILABLEN1_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(1)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(2), + GlitchData => LLKRXCHPOSTEDAVAILABLEN2_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(2)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(2), + GlitchData => LLKRXCHPOSTEDAVAILABLEN2_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(2)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(3), + GlitchData => LLKRXCHPOSTEDAVAILABLEN3_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(3)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(3), + GlitchData => LLKRXCHPOSTEDAVAILABLEN3_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(3)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(4), + GlitchData => LLKRXCHPOSTEDAVAILABLEN4_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(4)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(4), + GlitchData => LLKRXCHPOSTEDAVAILABLEN4_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(4)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(5), + GlitchData => LLKRXCHPOSTEDAVAILABLEN5_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(5)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(5), + GlitchData => LLKRXCHPOSTEDAVAILABLEN5_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(5)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(6), + GlitchData => LLKRXCHPOSTEDAVAILABLEN6_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(6)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(6), + GlitchData => LLKRXCHPOSTEDAVAILABLEN6_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(6)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(7), + GlitchData => LLKRXCHPOSTEDAVAILABLEN7_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(7)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDAVAILABLEN(7), + GlitchData => LLKRXCHPOSTEDAVAILABLEN7_GlitchData, + OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(7)", + OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(0), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN0_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(0)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(0), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN0_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(0)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(1), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN1_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(1)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(1), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN1_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(1)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(2), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN2_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(2)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(2), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN2_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(2)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(3), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN3_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(3)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(3), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN3_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(3)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(4), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN4_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(4)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(4), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN4_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(4)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(5), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN5_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(5)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(5), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN5_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(5)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(6), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN6_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(6)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(6), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN6_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(6)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(7), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN7_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(7)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(7), + GlitchData => LLKRXCHNONPOSTEDAVAILABLEN7_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(7)", + OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(0), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN0_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(0)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(0), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN0_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(0)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(1), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN1_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(1)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(1), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN1_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(1)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(2), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN2_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(2)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(2), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN2_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(2)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(3), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN3_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(3)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(3), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN3_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(3)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(4), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN4_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(4)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(4), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN4_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(4)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(5), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN5_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(5)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(5), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN5_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(5)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(6), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN6_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(6)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(6), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN6_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(6)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(7), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN7_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(7)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(7), + GlitchData => LLKRXCHCOMPLETIONAVAILABLEN7_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(7)", + OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCONFIGAVAILABLEN, + GlitchData => LLKRXCHCONFIGAVAILABLEN_GlitchData, + OutSignalName => "LLKRXCHCONFIGAVAILABLEN", + OutTemp => LLKRXCHCONFIGAVAILABLEN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCONFIGAVAILABLEN, + GlitchData => LLKRXCHCONFIGAVAILABLEN_GlitchData, + OutSignalName => "LLKRXCHCONFIGAVAILABLEN", + OutTemp => LLKRXCHCONFIGAVAILABLEN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(0), + GlitchData => LLKRXCHPOSTEDPARTIALN0_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(0)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(0), + GlitchData => LLKRXCHPOSTEDPARTIALN0_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(0)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(1), + GlitchData => LLKRXCHPOSTEDPARTIALN1_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(1)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(1), + GlitchData => LLKRXCHPOSTEDPARTIALN1_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(1)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(2), + GlitchData => LLKRXCHPOSTEDPARTIALN2_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(2)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(2), + GlitchData => LLKRXCHPOSTEDPARTIALN2_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(2)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(3), + GlitchData => LLKRXCHPOSTEDPARTIALN3_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(3)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(3), + GlitchData => LLKRXCHPOSTEDPARTIALN3_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(3)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(4), + GlitchData => LLKRXCHPOSTEDPARTIALN4_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(4)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(4), + GlitchData => LLKRXCHPOSTEDPARTIALN4_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(4)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(5), + GlitchData => LLKRXCHPOSTEDPARTIALN5_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(5)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(5), + GlitchData => LLKRXCHPOSTEDPARTIALN5_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(5)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(6), + GlitchData => LLKRXCHPOSTEDPARTIALN6_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(6)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(6), + GlitchData => LLKRXCHPOSTEDPARTIALN6_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(6)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(7), + GlitchData => LLKRXCHPOSTEDPARTIALN7_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(7)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHPOSTEDPARTIALN(7), + GlitchData => LLKRXCHPOSTEDPARTIALN7_GlitchData, + OutSignalName => "LLKRXCHPOSTEDPARTIALN(7)", + OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(0), + GlitchData => LLKRXCHNONPOSTEDPARTIALN0_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(0)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(0), + GlitchData => LLKRXCHNONPOSTEDPARTIALN0_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(0)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(1), + GlitchData => LLKRXCHNONPOSTEDPARTIALN1_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(1)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(1), + GlitchData => LLKRXCHNONPOSTEDPARTIALN1_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(1)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(2), + GlitchData => LLKRXCHNONPOSTEDPARTIALN2_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(2)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(2), + GlitchData => LLKRXCHNONPOSTEDPARTIALN2_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(2)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(3), + GlitchData => LLKRXCHNONPOSTEDPARTIALN3_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(3)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(3), + GlitchData => LLKRXCHNONPOSTEDPARTIALN3_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(3)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(4), + GlitchData => LLKRXCHNONPOSTEDPARTIALN4_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(4)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(4), + GlitchData => LLKRXCHNONPOSTEDPARTIALN4_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(4)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(5), + GlitchData => LLKRXCHNONPOSTEDPARTIALN5_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(5)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(5), + GlitchData => LLKRXCHNONPOSTEDPARTIALN5_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(5)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(6), + GlitchData => LLKRXCHNONPOSTEDPARTIALN6_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(6)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(6), + GlitchData => LLKRXCHNONPOSTEDPARTIALN6_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(6)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(7), + GlitchData => LLKRXCHNONPOSTEDPARTIALN7_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(7)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHNONPOSTEDPARTIALN(7), + GlitchData => LLKRXCHNONPOSTEDPARTIALN7_GlitchData, + OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(7)", + OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(0), + GlitchData => LLKRXCHCOMPLETIONPARTIALN0_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(0)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(0), + GlitchData => LLKRXCHCOMPLETIONPARTIALN0_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(0)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(1), + GlitchData => LLKRXCHCOMPLETIONPARTIALN1_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(1)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(1), + GlitchData => LLKRXCHCOMPLETIONPARTIALN1_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(1)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(2), + GlitchData => LLKRXCHCOMPLETIONPARTIALN2_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(2)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(2), + GlitchData => LLKRXCHCOMPLETIONPARTIALN2_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(2)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(3), + GlitchData => LLKRXCHCOMPLETIONPARTIALN3_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(3)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(3), + GlitchData => LLKRXCHCOMPLETIONPARTIALN3_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(3)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(4), + GlitchData => LLKRXCHCOMPLETIONPARTIALN4_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(4)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(4), + GlitchData => LLKRXCHCOMPLETIONPARTIALN4_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(4)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(5), + GlitchData => LLKRXCHCOMPLETIONPARTIALN5_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(5)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(5), + GlitchData => LLKRXCHCOMPLETIONPARTIALN5_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(5)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(6), + GlitchData => LLKRXCHCOMPLETIONPARTIALN6_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(6)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(6), + GlitchData => LLKRXCHCOMPLETIONPARTIALN6_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(6)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(7), + GlitchData => LLKRXCHCOMPLETIONPARTIALN7_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(7)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCOMPLETIONPARTIALN(7), + GlitchData => LLKRXCHCOMPLETIONPARTIALN7_GlitchData, + OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(7)", + OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCONFIGPARTIALN, + GlitchData => LLKRXCHCONFIGPARTIALN_GlitchData, + OutSignalName => "LLKRXCHCONFIGPARTIALN", + OutTemp => LLKRXCHCONFIGPARTIALN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXCHCONFIGPARTIALN, + GlitchData => LLKRXCHCONFIGPARTIALN_GlitchData, + OutSignalName => "LLKRXCHCONFIGPARTIALN", + OutTemp => LLKRXCHCONFIGPARTIALN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRX4DWHEADERN, + GlitchData => LLKRX4DWHEADERN_GlitchData, + OutSignalName => "LLKRX4DWHEADERN", + OutTemp => LLKRX4DWHEADERN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRX4DWHEADERN, + GlitchData => LLKRX4DWHEADERN_GlitchData, + OutSignalName => "LLKRX4DWHEADERN", + OutTemp => LLKRX4DWHEADERN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXECRCBADN, + GlitchData => LLKRXECRCBADN_GlitchData, + OutSignalName => "LLKRXECRCBADN", + OutTemp => LLKRXECRCBADN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => LLKRXECRCBADN, + GlitchData => LLKRXECRCBADN_GlitchData, + OutSignalName => "LLKRXECRCBADN", + OutTemp => LLKRXECRCBADN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(0), + GlitchData => MGMTRDATA0_GlitchData, + OutSignalName => "MGMTRDATA(0)", + OutTemp => MGMTRDATA_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(0), + GlitchData => MGMTRDATA0_GlitchData, + OutSignalName => "MGMTRDATA(0)", + OutTemp => MGMTRDATA_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(1), + GlitchData => MGMTRDATA1_GlitchData, + OutSignalName => "MGMTRDATA(1)", + OutTemp => MGMTRDATA_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(1), + GlitchData => MGMTRDATA1_GlitchData, + OutSignalName => "MGMTRDATA(1)", + OutTemp => MGMTRDATA_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(2), + GlitchData => MGMTRDATA2_GlitchData, + OutSignalName => "MGMTRDATA(2)", + OutTemp => MGMTRDATA_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(2), + GlitchData => MGMTRDATA2_GlitchData, + OutSignalName => "MGMTRDATA(2)", + OutTemp => MGMTRDATA_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(3), + GlitchData => MGMTRDATA3_GlitchData, + OutSignalName => "MGMTRDATA(3)", + OutTemp => MGMTRDATA_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(3), + GlitchData => MGMTRDATA3_GlitchData, + OutSignalName => "MGMTRDATA(3)", + OutTemp => MGMTRDATA_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(4), + GlitchData => MGMTRDATA4_GlitchData, + OutSignalName => "MGMTRDATA(4)", + OutTemp => MGMTRDATA_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(4), + GlitchData => MGMTRDATA4_GlitchData, + OutSignalName => "MGMTRDATA(4)", + OutTemp => MGMTRDATA_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(5), + GlitchData => MGMTRDATA5_GlitchData, + OutSignalName => "MGMTRDATA(5)", + OutTemp => MGMTRDATA_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(5), + GlitchData => MGMTRDATA5_GlitchData, + OutSignalName => "MGMTRDATA(5)", + OutTemp => MGMTRDATA_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(6), + GlitchData => MGMTRDATA6_GlitchData, + OutSignalName => "MGMTRDATA(6)", + OutTemp => MGMTRDATA_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(6), + GlitchData => MGMTRDATA6_GlitchData, + OutSignalName => "MGMTRDATA(6)", + OutTemp => MGMTRDATA_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(7), + GlitchData => MGMTRDATA7_GlitchData, + OutSignalName => "MGMTRDATA(7)", + OutTemp => MGMTRDATA_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(7), + GlitchData => MGMTRDATA7_GlitchData, + OutSignalName => "MGMTRDATA(7)", + OutTemp => MGMTRDATA_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(8), + GlitchData => MGMTRDATA8_GlitchData, + OutSignalName => "MGMTRDATA(8)", + OutTemp => MGMTRDATA_OUT(8), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(8), + GlitchData => MGMTRDATA8_GlitchData, + OutSignalName => "MGMTRDATA(8)", + OutTemp => MGMTRDATA_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(9), + GlitchData => MGMTRDATA9_GlitchData, + OutSignalName => "MGMTRDATA(9)", + OutTemp => MGMTRDATA_OUT(9), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(9), + GlitchData => MGMTRDATA9_GlitchData, + OutSignalName => "MGMTRDATA(9)", + OutTemp => MGMTRDATA_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(10), + GlitchData => MGMTRDATA10_GlitchData, + OutSignalName => "MGMTRDATA(10)", + OutTemp => MGMTRDATA_OUT(10), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(10), + GlitchData => MGMTRDATA10_GlitchData, + OutSignalName => "MGMTRDATA(10)", + OutTemp => MGMTRDATA_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(11), + GlitchData => MGMTRDATA11_GlitchData, + OutSignalName => "MGMTRDATA(11)", + OutTemp => MGMTRDATA_OUT(11), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(11), + GlitchData => MGMTRDATA11_GlitchData, + OutSignalName => "MGMTRDATA(11)", + OutTemp => MGMTRDATA_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(12), + GlitchData => MGMTRDATA12_GlitchData, + OutSignalName => "MGMTRDATA(12)", + OutTemp => MGMTRDATA_OUT(12), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(12), + GlitchData => MGMTRDATA12_GlitchData, + OutSignalName => "MGMTRDATA(12)", + OutTemp => MGMTRDATA_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(13), + GlitchData => MGMTRDATA13_GlitchData, + OutSignalName => "MGMTRDATA(13)", + OutTemp => MGMTRDATA_OUT(13), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(13), + GlitchData => MGMTRDATA13_GlitchData, + OutSignalName => "MGMTRDATA(13)", + OutTemp => MGMTRDATA_OUT(13), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(14), + GlitchData => MGMTRDATA14_GlitchData, + OutSignalName => "MGMTRDATA(14)", + OutTemp => MGMTRDATA_OUT(14), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(14), + GlitchData => MGMTRDATA14_GlitchData, + OutSignalName => "MGMTRDATA(14)", + OutTemp => MGMTRDATA_OUT(14), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(15), + GlitchData => MGMTRDATA15_GlitchData, + OutSignalName => "MGMTRDATA(15)", + OutTemp => MGMTRDATA_OUT(15), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(15), + GlitchData => MGMTRDATA15_GlitchData, + OutSignalName => "MGMTRDATA(15)", + OutTemp => MGMTRDATA_OUT(15), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(16), + GlitchData => MGMTRDATA16_GlitchData, + OutSignalName => "MGMTRDATA(16)", + OutTemp => MGMTRDATA_OUT(16), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(16), + GlitchData => MGMTRDATA16_GlitchData, + OutSignalName => "MGMTRDATA(16)", + OutTemp => MGMTRDATA_OUT(16), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(17), + GlitchData => MGMTRDATA17_GlitchData, + OutSignalName => "MGMTRDATA(17)", + OutTemp => MGMTRDATA_OUT(17), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(17), + GlitchData => MGMTRDATA17_GlitchData, + OutSignalName => "MGMTRDATA(17)", + OutTemp => MGMTRDATA_OUT(17), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(18), + GlitchData => MGMTRDATA18_GlitchData, + OutSignalName => "MGMTRDATA(18)", + OutTemp => MGMTRDATA_OUT(18), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(18), + GlitchData => MGMTRDATA18_GlitchData, + OutSignalName => "MGMTRDATA(18)", + OutTemp => MGMTRDATA_OUT(18), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(19), + GlitchData => MGMTRDATA19_GlitchData, + OutSignalName => "MGMTRDATA(19)", + OutTemp => MGMTRDATA_OUT(19), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(19), + GlitchData => MGMTRDATA19_GlitchData, + OutSignalName => "MGMTRDATA(19)", + OutTemp => MGMTRDATA_OUT(19), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(20), + GlitchData => MGMTRDATA20_GlitchData, + OutSignalName => "MGMTRDATA(20)", + OutTemp => MGMTRDATA_OUT(20), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(20), + GlitchData => MGMTRDATA20_GlitchData, + OutSignalName => "MGMTRDATA(20)", + OutTemp => MGMTRDATA_OUT(20), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(21), + GlitchData => MGMTRDATA21_GlitchData, + OutSignalName => "MGMTRDATA(21)", + OutTemp => MGMTRDATA_OUT(21), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(21), + GlitchData => MGMTRDATA21_GlitchData, + OutSignalName => "MGMTRDATA(21)", + OutTemp => MGMTRDATA_OUT(21), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(22), + GlitchData => MGMTRDATA22_GlitchData, + OutSignalName => "MGMTRDATA(22)", + OutTemp => MGMTRDATA_OUT(22), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(22), + GlitchData => MGMTRDATA22_GlitchData, + OutSignalName => "MGMTRDATA(22)", + OutTemp => MGMTRDATA_OUT(22), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(23), + GlitchData => MGMTRDATA23_GlitchData, + OutSignalName => "MGMTRDATA(23)", + OutTemp => MGMTRDATA_OUT(23), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(23), + GlitchData => MGMTRDATA23_GlitchData, + OutSignalName => "MGMTRDATA(23)", + OutTemp => MGMTRDATA_OUT(23), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(24), + GlitchData => MGMTRDATA24_GlitchData, + OutSignalName => "MGMTRDATA(24)", + OutTemp => MGMTRDATA_OUT(24), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(24), + GlitchData => MGMTRDATA24_GlitchData, + OutSignalName => "MGMTRDATA(24)", + OutTemp => MGMTRDATA_OUT(24), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(25), + GlitchData => MGMTRDATA25_GlitchData, + OutSignalName => "MGMTRDATA(25)", + OutTemp => MGMTRDATA_OUT(25), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(25), + GlitchData => MGMTRDATA25_GlitchData, + OutSignalName => "MGMTRDATA(25)", + OutTemp => MGMTRDATA_OUT(25), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(26), + GlitchData => MGMTRDATA26_GlitchData, + OutSignalName => "MGMTRDATA(26)", + OutTemp => MGMTRDATA_OUT(26), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(26), + GlitchData => MGMTRDATA26_GlitchData, + OutSignalName => "MGMTRDATA(26)", + OutTemp => MGMTRDATA_OUT(26), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(27), + GlitchData => MGMTRDATA27_GlitchData, + OutSignalName => "MGMTRDATA(27)", + OutTemp => MGMTRDATA_OUT(27), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(27), + GlitchData => MGMTRDATA27_GlitchData, + OutSignalName => "MGMTRDATA(27)", + OutTemp => MGMTRDATA_OUT(27), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(28), + GlitchData => MGMTRDATA28_GlitchData, + OutSignalName => "MGMTRDATA(28)", + OutTemp => MGMTRDATA_OUT(28), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(28), + GlitchData => MGMTRDATA28_GlitchData, + OutSignalName => "MGMTRDATA(28)", + OutTemp => MGMTRDATA_OUT(28), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(29), + GlitchData => MGMTRDATA29_GlitchData, + OutSignalName => "MGMTRDATA(29)", + OutTemp => MGMTRDATA_OUT(29), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(29), + GlitchData => MGMTRDATA29_GlitchData, + OutSignalName => "MGMTRDATA(29)", + OutTemp => MGMTRDATA_OUT(29), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(30), + GlitchData => MGMTRDATA30_GlitchData, + OutSignalName => "MGMTRDATA(30)", + OutTemp => MGMTRDATA_OUT(30), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(30), + GlitchData => MGMTRDATA30_GlitchData, + OutSignalName => "MGMTRDATA(30)", + OutTemp => MGMTRDATA_OUT(30), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(31), + GlitchData => MGMTRDATA31_GlitchData, + OutSignalName => "MGMTRDATA(31)", + OutTemp => MGMTRDATA_OUT(31), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTRDATA(31), + GlitchData => MGMTRDATA31_GlitchData, + OutSignalName => "MGMTRDATA(31)", + OutTemp => MGMTRDATA_OUT(31), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(0), + GlitchData => MGMTPSO0_GlitchData, + OutSignalName => "MGMTPSO(0)", + OutTemp => MGMTPSO_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(0), + GlitchData => MGMTPSO0_GlitchData, + OutSignalName => "MGMTPSO(0)", + OutTemp => MGMTPSO_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(1), + GlitchData => MGMTPSO1_GlitchData, + OutSignalName => "MGMTPSO(1)", + OutTemp => MGMTPSO_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(1), + GlitchData => MGMTPSO1_GlitchData, + OutSignalName => "MGMTPSO(1)", + OutTemp => MGMTPSO_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(2), + GlitchData => MGMTPSO2_GlitchData, + OutSignalName => "MGMTPSO(2)", + OutTemp => MGMTPSO_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(2), + GlitchData => MGMTPSO2_GlitchData, + OutSignalName => "MGMTPSO(2)", + OutTemp => MGMTPSO_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(3), + GlitchData => MGMTPSO3_GlitchData, + OutSignalName => "MGMTPSO(3)", + OutTemp => MGMTPSO_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(3), + GlitchData => MGMTPSO3_GlitchData, + OutSignalName => "MGMTPSO(3)", + OutTemp => MGMTPSO_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(4), + GlitchData => MGMTPSO4_GlitchData, + OutSignalName => "MGMTPSO(4)", + OutTemp => MGMTPSO_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(4), + GlitchData => MGMTPSO4_GlitchData, + OutSignalName => "MGMTPSO(4)", + OutTemp => MGMTPSO_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(5), + GlitchData => MGMTPSO5_GlitchData, + OutSignalName => "MGMTPSO(5)", + OutTemp => MGMTPSO_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(5), + GlitchData => MGMTPSO5_GlitchData, + OutSignalName => "MGMTPSO(5)", + OutTemp => MGMTPSO_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(6), + GlitchData => MGMTPSO6_GlitchData, + OutSignalName => "MGMTPSO(6)", + OutTemp => MGMTPSO_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(6), + GlitchData => MGMTPSO6_GlitchData, + OutSignalName => "MGMTPSO(6)", + OutTemp => MGMTPSO_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(7), + GlitchData => MGMTPSO7_GlitchData, + OutSignalName => "MGMTPSO(7)", + OutTemp => MGMTPSO_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(7), + GlitchData => MGMTPSO7_GlitchData, + OutSignalName => "MGMTPSO(7)", + OutTemp => MGMTPSO_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(8), + GlitchData => MGMTPSO8_GlitchData, + OutSignalName => "MGMTPSO(8)", + OutTemp => MGMTPSO_OUT(8), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(8), + GlitchData => MGMTPSO8_GlitchData, + OutSignalName => "MGMTPSO(8)", + OutTemp => MGMTPSO_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(9), + GlitchData => MGMTPSO9_GlitchData, + OutSignalName => "MGMTPSO(9)", + OutTemp => MGMTPSO_OUT(9), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(9), + GlitchData => MGMTPSO9_GlitchData, + OutSignalName => "MGMTPSO(9)", + OutTemp => MGMTPSO_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(10), + GlitchData => MGMTPSO10_GlitchData, + OutSignalName => "MGMTPSO(10)", + OutTemp => MGMTPSO_OUT(10), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(10), + GlitchData => MGMTPSO10_GlitchData, + OutSignalName => "MGMTPSO(10)", + OutTemp => MGMTPSO_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(11), + GlitchData => MGMTPSO11_GlitchData, + OutSignalName => "MGMTPSO(11)", + OutTemp => MGMTPSO_OUT(11), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(11), + GlitchData => MGMTPSO11_GlitchData, + OutSignalName => "MGMTPSO(11)", + OutTemp => MGMTPSO_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(12), + GlitchData => MGMTPSO12_GlitchData, + OutSignalName => "MGMTPSO(12)", + OutTemp => MGMTPSO_OUT(12), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(12), + GlitchData => MGMTPSO12_GlitchData, + OutSignalName => "MGMTPSO(12)", + OutTemp => MGMTPSO_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(13), + GlitchData => MGMTPSO13_GlitchData, + OutSignalName => "MGMTPSO(13)", + OutTemp => MGMTPSO_OUT(13), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(13), + GlitchData => MGMTPSO13_GlitchData, + OutSignalName => "MGMTPSO(13)", + OutTemp => MGMTPSO_OUT(13), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(14), + GlitchData => MGMTPSO14_GlitchData, + OutSignalName => "MGMTPSO(14)", + OutTemp => MGMTPSO_OUT(14), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(14), + GlitchData => MGMTPSO14_GlitchData, + OutSignalName => "MGMTPSO(14)", + OutTemp => MGMTPSO_OUT(14), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(15), + GlitchData => MGMTPSO15_GlitchData, + OutSignalName => "MGMTPSO(15)", + OutTemp => MGMTPSO_OUT(15), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(15), + GlitchData => MGMTPSO15_GlitchData, + OutSignalName => "MGMTPSO(15)", + OutTemp => MGMTPSO_OUT(15), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(16), + GlitchData => MGMTPSO16_GlitchData, + OutSignalName => "MGMTPSO(16)", + OutTemp => MGMTPSO_OUT(16), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTPSO(16), + GlitchData => MGMTPSO16_GlitchData, + OutSignalName => "MGMTPSO(16)", + OutTemp => MGMTPSO_OUT(16), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(0), + GlitchData => MGMTSTATSCREDIT0_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(0)", + OutTemp => MGMTSTATSCREDIT_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(0), + GlitchData => MGMTSTATSCREDIT0_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(0)", + OutTemp => MGMTSTATSCREDIT_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(1), + GlitchData => MGMTSTATSCREDIT1_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(1)", + OutTemp => MGMTSTATSCREDIT_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(1), + GlitchData => MGMTSTATSCREDIT1_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(1)", + OutTemp => MGMTSTATSCREDIT_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(2), + GlitchData => MGMTSTATSCREDIT2_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(2)", + OutTemp => MGMTSTATSCREDIT_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(2), + GlitchData => MGMTSTATSCREDIT2_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(2)", + OutTemp => MGMTSTATSCREDIT_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(3), + GlitchData => MGMTSTATSCREDIT3_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(3)", + OutTemp => MGMTSTATSCREDIT_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(3), + GlitchData => MGMTSTATSCREDIT3_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(3)", + OutTemp => MGMTSTATSCREDIT_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(4), + GlitchData => MGMTSTATSCREDIT4_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(4)", + OutTemp => MGMTSTATSCREDIT_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(4), + GlitchData => MGMTSTATSCREDIT4_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(4)", + OutTemp => MGMTSTATSCREDIT_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(5), + GlitchData => MGMTSTATSCREDIT5_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(5)", + OutTemp => MGMTSTATSCREDIT_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(5), + GlitchData => MGMTSTATSCREDIT5_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(5)", + OutTemp => MGMTSTATSCREDIT_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(6), + GlitchData => MGMTSTATSCREDIT6_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(6)", + OutTemp => MGMTSTATSCREDIT_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(6), + GlitchData => MGMTSTATSCREDIT6_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(6)", + OutTemp => MGMTSTATSCREDIT_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(7), + GlitchData => MGMTSTATSCREDIT7_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(7)", + OutTemp => MGMTSTATSCREDIT_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(7), + GlitchData => MGMTSTATSCREDIT7_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(7)", + OutTemp => MGMTSTATSCREDIT_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(8), + GlitchData => MGMTSTATSCREDIT8_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(8)", + OutTemp => MGMTSTATSCREDIT_OUT(8), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(8), + GlitchData => MGMTSTATSCREDIT8_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(8)", + OutTemp => MGMTSTATSCREDIT_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(9), + GlitchData => MGMTSTATSCREDIT9_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(9)", + OutTemp => MGMTSTATSCREDIT_OUT(9), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(9), + GlitchData => MGMTSTATSCREDIT9_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(9)", + OutTemp => MGMTSTATSCREDIT_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(10), + GlitchData => MGMTSTATSCREDIT10_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(10)", + OutTemp => MGMTSTATSCREDIT_OUT(10), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(10), + GlitchData => MGMTSTATSCREDIT10_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(10)", + OutTemp => MGMTSTATSCREDIT_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(11), + GlitchData => MGMTSTATSCREDIT11_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(11)", + OutTemp => MGMTSTATSCREDIT_OUT(11), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MGMTSTATSCREDIT(11), + GlitchData => MGMTSTATSCREDIT11_GlitchData, + OutSignalName => "MGMTSTATSCREDIT(11)", + OutTemp => MGMTSTATSCREDIT_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLTLPECRCOK, + GlitchData => L0RXDLLTLPECRCOK_GlitchData, + OutSignalName => "L0RXDLLTLPECRCOK", + OutTemp => L0RXDLLTLPECRCOK_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DLLTXPMDLLPOUTSTANDING, + GlitchData => DLLTXPMDLLPOUTSTANDING_GlitchData, + OutSignalName => "DLLTXPMDLLPOUTSTANDING", + OutTemp => DLLTXPMDLLPOUTSTANDING_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FIRSTCFGWRITEOCCURRED, + GlitchData => L0FIRSTCFGWRITEOCCURRED_GlitchData, + OutSignalName => "L0FIRSTCFGWRITEOCCURRED", + OutTemp => L0FIRSTCFGWRITEOCCURRED_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FIRSTCFGWRITEOCCURRED, + GlitchData => L0FIRSTCFGWRITEOCCURRED_GlitchData, + OutSignalName => "L0FIRSTCFGWRITEOCCURRED", + OutTemp => L0FIRSTCFGWRITEOCCURRED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0CFGLOOPBACKACK, + GlitchData => L0CFGLOOPBACKACK_GlitchData, + OutSignalName => "L0CFGLOOPBACKACK", + OutTemp => L0CFGLOOPBACKACK_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACUPSTREAMDOWNSTREAM, + GlitchData => L0MACUPSTREAMDOWNSTREAM_GlitchData, + OutSignalName => "L0MACUPSTREAMDOWNSTREAM", + OutTemp => L0MACUPSTREAMDOWNSTREAM_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXMACLINKERROR(0), + GlitchData => L0RXMACLINKERROR0_GlitchData, + OutSignalName => "L0RXMACLINKERROR(0)", + OutTemp => L0RXMACLINKERROR_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXMACLINKERROR(1), + GlitchData => L0RXMACLINKERROR1_GlitchData, + OutSignalName => "L0RXMACLINKERROR(1)", + OutTemp => L0RXMACLINKERROR_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACLINKUP, + GlitchData => L0MACLINKUP_GlitchData, + OutSignalName => "L0MACLINKUP", + OutTemp => L0MACLINKUP_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACNEGOTIATEDLINKWIDTH(0), + GlitchData => L0MACNEGOTIATEDLINKWIDTH0_GlitchData, + OutSignalName => "L0MACNEGOTIATEDLINKWIDTH(0)", + OutTemp => L0MACNEGOTIATEDLINKWIDTH_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACNEGOTIATEDLINKWIDTH(1), + GlitchData => L0MACNEGOTIATEDLINKWIDTH1_GlitchData, + OutSignalName => "L0MACNEGOTIATEDLINKWIDTH(1)", + OutTemp => L0MACNEGOTIATEDLINKWIDTH_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACNEGOTIATEDLINKWIDTH(2), + GlitchData => L0MACNEGOTIATEDLINKWIDTH2_GlitchData, + OutSignalName => "L0MACNEGOTIATEDLINKWIDTH(2)", + OutTemp => L0MACNEGOTIATEDLINKWIDTH_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACNEGOTIATEDLINKWIDTH(3), + GlitchData => L0MACNEGOTIATEDLINKWIDTH3_GlitchData, + OutSignalName => "L0MACNEGOTIATEDLINKWIDTH(3)", + OutTemp => L0MACNEGOTIATEDLINKWIDTH_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACLINKTRAINING, + GlitchData => L0MACLINKTRAINING_GlitchData, + OutSignalName => "L0MACLINKTRAINING", + OutTemp => L0MACLINKTRAINING_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0LTSSMSTATE(0), + GlitchData => L0LTSSMSTATE0_GlitchData, + OutSignalName => "L0LTSSMSTATE(0)", + OutTemp => L0LTSSMSTATE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0LTSSMSTATE(1), + GlitchData => L0LTSSMSTATE1_GlitchData, + OutSignalName => "L0LTSSMSTATE(1)", + OutTemp => L0LTSSMSTATE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0LTSSMSTATE(2), + GlitchData => L0LTSSMSTATE2_GlitchData, + OutSignalName => "L0LTSSMSTATE(2)", + OutTemp => L0LTSSMSTATE_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0LTSSMSTATE(3), + GlitchData => L0LTSSMSTATE3_GlitchData, + OutSignalName => "L0LTSSMSTATE(3)", + OutTemp => L0LTSSMSTATE_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLVCSTATUS(0), + GlitchData => L0DLLVCSTATUS0_GlitchData, + OutSignalName => "L0DLLVCSTATUS(0)", + OutTemp => L0DLLVCSTATUS_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLVCSTATUS(1), + GlitchData => L0DLLVCSTATUS1_GlitchData, + OutSignalName => "L0DLLVCSTATUS(1)", + OutTemp => L0DLLVCSTATUS_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLVCSTATUS(2), + GlitchData => L0DLLVCSTATUS2_GlitchData, + OutSignalName => "L0DLLVCSTATUS(2)", + OutTemp => L0DLLVCSTATUS_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLVCSTATUS(3), + GlitchData => L0DLLVCSTATUS3_GlitchData, + OutSignalName => "L0DLLVCSTATUS(3)", + OutTemp => L0DLLVCSTATUS_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLVCSTATUS(4), + GlitchData => L0DLLVCSTATUS4_GlitchData, + OutSignalName => "L0DLLVCSTATUS(4)", + OutTemp => L0DLLVCSTATUS_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLVCSTATUS(5), + GlitchData => L0DLLVCSTATUS5_GlitchData, + OutSignalName => "L0DLLVCSTATUS(5)", + OutTemp => L0DLLVCSTATUS_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLVCSTATUS(6), + GlitchData => L0DLLVCSTATUS6_GlitchData, + OutSignalName => "L0DLLVCSTATUS(6)", + OutTemp => L0DLLVCSTATUS_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLVCSTATUS(7), + GlitchData => L0DLLVCSTATUS7_GlitchData, + OutSignalName => "L0DLLVCSTATUS(7)", + OutTemp => L0DLLVCSTATUS_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLUPDOWN(0), + GlitchData => L0DLUPDOWN0_GlitchData, + OutSignalName => "L0DLUPDOWN(0)", + OutTemp => L0DLUPDOWN_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLUPDOWN(1), + GlitchData => L0DLUPDOWN1_GlitchData, + OutSignalName => "L0DLUPDOWN(1)", + OutTemp => L0DLUPDOWN_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLUPDOWN(2), + GlitchData => L0DLUPDOWN2_GlitchData, + OutSignalName => "L0DLUPDOWN(2)", + OutTemp => L0DLUPDOWN_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLUPDOWN(3), + GlitchData => L0DLUPDOWN3_GlitchData, + OutSignalName => "L0DLUPDOWN(3)", + OutTemp => L0DLUPDOWN_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLUPDOWN(4), + GlitchData => L0DLUPDOWN4_GlitchData, + OutSignalName => "L0DLUPDOWN(4)", + OutTemp => L0DLUPDOWN_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLUPDOWN(5), + GlitchData => L0DLUPDOWN5_GlitchData, + OutSignalName => "L0DLUPDOWN(5)", + OutTemp => L0DLUPDOWN_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLUPDOWN(6), + GlitchData => L0DLUPDOWN6_GlitchData, + OutSignalName => "L0DLUPDOWN(6)", + OutTemp => L0DLUPDOWN_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLUPDOWN(7), + GlitchData => L0DLUPDOWN7_GlitchData, + OutSignalName => "L0DLUPDOWN(7)", + OutTemp => L0DLUPDOWN_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLERRORVECTOR(0), + GlitchData => L0DLLERRORVECTOR0_GlitchData, + OutSignalName => "L0DLLERRORVECTOR(0)", + OutTemp => L0DLLERRORVECTOR_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLERRORVECTOR(1), + GlitchData => L0DLLERRORVECTOR1_GlitchData, + OutSignalName => "L0DLLERRORVECTOR(1)", + OutTemp => L0DLLERRORVECTOR_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLERRORVECTOR(2), + GlitchData => L0DLLERRORVECTOR2_GlitchData, + OutSignalName => "L0DLLERRORVECTOR(2)", + OutTemp => L0DLLERRORVECTOR_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLERRORVECTOR(3), + GlitchData => L0DLLERRORVECTOR3_GlitchData, + OutSignalName => "L0DLLERRORVECTOR(3)", + OutTemp => L0DLLERRORVECTOR_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLERRORVECTOR(4), + GlitchData => L0DLLERRORVECTOR4_GlitchData, + OutSignalName => "L0DLLERRORVECTOR(4)", + OutTemp => L0DLLERRORVECTOR_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLERRORVECTOR(5), + GlitchData => L0DLLERRORVECTOR5_GlitchData, + OutSignalName => "L0DLLERRORVECTOR(5)", + OutTemp => L0DLLERRORVECTOR_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLERRORVECTOR(6), + GlitchData => L0DLLERRORVECTOR6_GlitchData, + OutSignalName => "L0DLLERRORVECTOR(6)", + OutTemp => L0DLLERRORVECTOR_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLASRXSTATE(0), + GlitchData => L0DLLASRXSTATE0_GlitchData, + OutSignalName => "L0DLLASRXSTATE(0)", + OutTemp => L0DLLASRXSTATE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLASRXSTATE(1), + GlitchData => L0DLLASRXSTATE1_GlitchData, + OutSignalName => "L0DLLASRXSTATE(1)", + OutTemp => L0DLLASRXSTATE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLASTXSTATE, + GlitchData => L0DLLASTXSTATE_GlitchData, + OutSignalName => "L0DLLASTXSTATE", + OutTemp => L0DLLASTXSTATE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ASAUTONOMOUSINITCOMPLETED, + GlitchData => L0ASAUTONOMOUSINITCOMPLETED_GlitchData, + OutSignalName => "L0ASAUTONOMOUSINITCOMPLETED", + OutTemp => L0ASAUTONOMOUSINITCOMPLETED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(0), + GlitchData => L0COMPLETERID0_GlitchData, + OutSignalName => "L0COMPLETERID(0)", + OutTemp => L0COMPLETERID_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(0), + GlitchData => L0COMPLETERID0_GlitchData, + OutSignalName => "L0COMPLETERID(0)", + OutTemp => L0COMPLETERID_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(1), + GlitchData => L0COMPLETERID1_GlitchData, + OutSignalName => "L0COMPLETERID(1)", + OutTemp => L0COMPLETERID_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(1), + GlitchData => L0COMPLETERID1_GlitchData, + OutSignalName => "L0COMPLETERID(1)", + OutTemp => L0COMPLETERID_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(2), + GlitchData => L0COMPLETERID2_GlitchData, + OutSignalName => "L0COMPLETERID(2)", + OutTemp => L0COMPLETERID_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(2), + GlitchData => L0COMPLETERID2_GlitchData, + OutSignalName => "L0COMPLETERID(2)", + OutTemp => L0COMPLETERID_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(3), + GlitchData => L0COMPLETERID3_GlitchData, + OutSignalName => "L0COMPLETERID(3)", + OutTemp => L0COMPLETERID_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(3), + GlitchData => L0COMPLETERID3_GlitchData, + OutSignalName => "L0COMPLETERID(3)", + OutTemp => L0COMPLETERID_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(4), + GlitchData => L0COMPLETERID4_GlitchData, + OutSignalName => "L0COMPLETERID(4)", + OutTemp => L0COMPLETERID_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(4), + GlitchData => L0COMPLETERID4_GlitchData, + OutSignalName => "L0COMPLETERID(4)", + OutTemp => L0COMPLETERID_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(5), + GlitchData => L0COMPLETERID5_GlitchData, + OutSignalName => "L0COMPLETERID(5)", + OutTemp => L0COMPLETERID_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(5), + GlitchData => L0COMPLETERID5_GlitchData, + OutSignalName => "L0COMPLETERID(5)", + OutTemp => L0COMPLETERID_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(6), + GlitchData => L0COMPLETERID6_GlitchData, + OutSignalName => "L0COMPLETERID(6)", + OutTemp => L0COMPLETERID_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(6), + GlitchData => L0COMPLETERID6_GlitchData, + OutSignalName => "L0COMPLETERID(6)", + OutTemp => L0COMPLETERID_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(7), + GlitchData => L0COMPLETERID7_GlitchData, + OutSignalName => "L0COMPLETERID(7)", + OutTemp => L0COMPLETERID_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(7), + GlitchData => L0COMPLETERID7_GlitchData, + OutSignalName => "L0COMPLETERID(7)", + OutTemp => L0COMPLETERID_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(8), + GlitchData => L0COMPLETERID8_GlitchData, + OutSignalName => "L0COMPLETERID(8)", + OutTemp => L0COMPLETERID_OUT(8), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(8), + GlitchData => L0COMPLETERID8_GlitchData, + OutSignalName => "L0COMPLETERID(8)", + OutTemp => L0COMPLETERID_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(9), + GlitchData => L0COMPLETERID9_GlitchData, + OutSignalName => "L0COMPLETERID(9)", + OutTemp => L0COMPLETERID_OUT(9), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(9), + GlitchData => L0COMPLETERID9_GlitchData, + OutSignalName => "L0COMPLETERID(9)", + OutTemp => L0COMPLETERID_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(10), + GlitchData => L0COMPLETERID10_GlitchData, + OutSignalName => "L0COMPLETERID(10)", + OutTemp => L0COMPLETERID_OUT(10), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(10), + GlitchData => L0COMPLETERID10_GlitchData, + OutSignalName => "L0COMPLETERID(10)", + OutTemp => L0COMPLETERID_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(11), + GlitchData => L0COMPLETERID11_GlitchData, + OutSignalName => "L0COMPLETERID(11)", + OutTemp => L0COMPLETERID_OUT(11), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(11), + GlitchData => L0COMPLETERID11_GlitchData, + OutSignalName => "L0COMPLETERID(11)", + OutTemp => L0COMPLETERID_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(12), + GlitchData => L0COMPLETERID12_GlitchData, + OutSignalName => "L0COMPLETERID(12)", + OutTemp => L0COMPLETERID_OUT(12), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0COMPLETERID(12), + GlitchData => L0COMPLETERID12_GlitchData, + OutSignalName => "L0COMPLETERID(12)", + OutTemp => L0COMPLETERID_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UNLOCKRECEIVED, + GlitchData => L0UNLOCKRECEIVED_GlitchData, + OutSignalName => "L0UNLOCKRECEIVED", + OutTemp => L0UNLOCKRECEIVED_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UNLOCKRECEIVED, + GlitchData => L0UNLOCKRECEIVED_GlitchData, + OutSignalName => "L0UNLOCKRECEIVED", + OutTemp => L0UNLOCKRECEIVED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0CORRERRMSGRCVD, + GlitchData => L0CORRERRMSGRCVD_GlitchData, + OutSignalName => "L0CORRERRMSGRCVD", + OutTemp => L0CORRERRMSGRCVD_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0CORRERRMSGRCVD, + GlitchData => L0CORRERRMSGRCVD_GlitchData, + OutSignalName => "L0CORRERRMSGRCVD", + OutTemp => L0CORRERRMSGRCVD_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FATALERRMSGRCVD, + GlitchData => L0FATALERRMSGRCVD_GlitchData, + OutSignalName => "L0FATALERRMSGRCVD", + OutTemp => L0FATALERRMSGRCVD_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FATALERRMSGRCVD, + GlitchData => L0FATALERRMSGRCVD_GlitchData, + OutSignalName => "L0FATALERRMSGRCVD", + OutTemp => L0FATALERRMSGRCVD_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0NONFATALERRMSGRCVD, + GlitchData => L0NONFATALERRMSGRCVD_GlitchData, + OutSignalName => "L0NONFATALERRMSGRCVD", + OutTemp => L0NONFATALERRMSGRCVD_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0NONFATALERRMSGRCVD, + GlitchData => L0NONFATALERRMSGRCVD_GlitchData, + OutSignalName => "L0NONFATALERRMSGRCVD", + OutTemp => L0NONFATALERRMSGRCVD_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(0), + GlitchData => L0ERRMSGREQID0_GlitchData, + OutSignalName => "L0ERRMSGREQID(0)", + OutTemp => L0ERRMSGREQID_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(0), + GlitchData => L0ERRMSGREQID0_GlitchData, + OutSignalName => "L0ERRMSGREQID(0)", + OutTemp => L0ERRMSGREQID_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(1), + GlitchData => L0ERRMSGREQID1_GlitchData, + OutSignalName => "L0ERRMSGREQID(1)", + OutTemp => L0ERRMSGREQID_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(1), + GlitchData => L0ERRMSGREQID1_GlitchData, + OutSignalName => "L0ERRMSGREQID(1)", + OutTemp => L0ERRMSGREQID_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(2), + GlitchData => L0ERRMSGREQID2_GlitchData, + OutSignalName => "L0ERRMSGREQID(2)", + OutTemp => L0ERRMSGREQID_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(2), + GlitchData => L0ERRMSGREQID2_GlitchData, + OutSignalName => "L0ERRMSGREQID(2)", + OutTemp => L0ERRMSGREQID_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(3), + GlitchData => L0ERRMSGREQID3_GlitchData, + OutSignalName => "L0ERRMSGREQID(3)", + OutTemp => L0ERRMSGREQID_OUT(3), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(3), + GlitchData => L0ERRMSGREQID3_GlitchData, + OutSignalName => "L0ERRMSGREQID(3)", + OutTemp => L0ERRMSGREQID_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(4), + GlitchData => L0ERRMSGREQID4_GlitchData, + OutSignalName => "L0ERRMSGREQID(4)", + OutTemp => L0ERRMSGREQID_OUT(4), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(4), + GlitchData => L0ERRMSGREQID4_GlitchData, + OutSignalName => "L0ERRMSGREQID(4)", + OutTemp => L0ERRMSGREQID_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(5), + GlitchData => L0ERRMSGREQID5_GlitchData, + OutSignalName => "L0ERRMSGREQID(5)", + OutTemp => L0ERRMSGREQID_OUT(5), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(5), + GlitchData => L0ERRMSGREQID5_GlitchData, + OutSignalName => "L0ERRMSGREQID(5)", + OutTemp => L0ERRMSGREQID_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(6), + GlitchData => L0ERRMSGREQID6_GlitchData, + OutSignalName => "L0ERRMSGREQID(6)", + OutTemp => L0ERRMSGREQID_OUT(6), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(6), + GlitchData => L0ERRMSGREQID6_GlitchData, + OutSignalName => "L0ERRMSGREQID(6)", + OutTemp => L0ERRMSGREQID_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(7), + GlitchData => L0ERRMSGREQID7_GlitchData, + OutSignalName => "L0ERRMSGREQID(7)", + OutTemp => L0ERRMSGREQID_OUT(7), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(7), + GlitchData => L0ERRMSGREQID7_GlitchData, + OutSignalName => "L0ERRMSGREQID(7)", + OutTemp => L0ERRMSGREQID_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(8), + GlitchData => L0ERRMSGREQID8_GlitchData, + OutSignalName => "L0ERRMSGREQID(8)", + OutTemp => L0ERRMSGREQID_OUT(8), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(8), + GlitchData => L0ERRMSGREQID8_GlitchData, + OutSignalName => "L0ERRMSGREQID(8)", + OutTemp => L0ERRMSGREQID_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(9), + GlitchData => L0ERRMSGREQID9_GlitchData, + OutSignalName => "L0ERRMSGREQID(9)", + OutTemp => L0ERRMSGREQID_OUT(9), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(9), + GlitchData => L0ERRMSGREQID9_GlitchData, + OutSignalName => "L0ERRMSGREQID(9)", + OutTemp => L0ERRMSGREQID_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(10), + GlitchData => L0ERRMSGREQID10_GlitchData, + OutSignalName => "L0ERRMSGREQID(10)", + OutTemp => L0ERRMSGREQID_OUT(10), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(10), + GlitchData => L0ERRMSGREQID10_GlitchData, + OutSignalName => "L0ERRMSGREQID(10)", + OutTemp => L0ERRMSGREQID_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(11), + GlitchData => L0ERRMSGREQID11_GlitchData, + OutSignalName => "L0ERRMSGREQID(11)", + OutTemp => L0ERRMSGREQID_OUT(11), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(11), + GlitchData => L0ERRMSGREQID11_GlitchData, + OutSignalName => "L0ERRMSGREQID(11)", + OutTemp => L0ERRMSGREQID_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(12), + GlitchData => L0ERRMSGREQID12_GlitchData, + OutSignalName => "L0ERRMSGREQID(12)", + OutTemp => L0ERRMSGREQID_OUT(12), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(12), + GlitchData => L0ERRMSGREQID12_GlitchData, + OutSignalName => "L0ERRMSGREQID(12)", + OutTemp => L0ERRMSGREQID_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(13), + GlitchData => L0ERRMSGREQID13_GlitchData, + OutSignalName => "L0ERRMSGREQID(13)", + OutTemp => L0ERRMSGREQID_OUT(13), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(13), + GlitchData => L0ERRMSGREQID13_GlitchData, + OutSignalName => "L0ERRMSGREQID(13)", + OutTemp => L0ERRMSGREQID_OUT(13), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(14), + GlitchData => L0ERRMSGREQID14_GlitchData, + OutSignalName => "L0ERRMSGREQID(14)", + OutTemp => L0ERRMSGREQID_OUT(14), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(14), + GlitchData => L0ERRMSGREQID14_GlitchData, + OutSignalName => "L0ERRMSGREQID(14)", + OutTemp => L0ERRMSGREQID_OUT(14), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(15), + GlitchData => L0ERRMSGREQID15_GlitchData, + OutSignalName => "L0ERRMSGREQID(15)", + OutTemp => L0ERRMSGREQID_OUT(15), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ERRMSGREQID(15), + GlitchData => L0ERRMSGREQID15_GlitchData, + OutSignalName => "L0ERRMSGREQID(15)", + OutTemp => L0ERRMSGREQID_OUT(15), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FWDCORRERROUT, + GlitchData => L0FWDCORRERROUT_GlitchData, + OutSignalName => "L0FWDCORRERROUT", + OutTemp => L0FWDCORRERROUT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FWDCORRERROUT, + GlitchData => L0FWDCORRERROUT_GlitchData, + OutSignalName => "L0FWDCORRERROUT", + OutTemp => L0FWDCORRERROUT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FWDFATALERROUT, + GlitchData => L0FWDFATALERROUT_GlitchData, + OutSignalName => "L0FWDFATALERROUT", + OutTemp => L0FWDFATALERROUT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FWDFATALERROUT, + GlitchData => L0FWDFATALERROUT_GlitchData, + OutSignalName => "L0FWDFATALERROUT", + OutTemp => L0FWDFATALERROUT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FWDNONFATALERROUT, + GlitchData => L0FWDNONFATALERROUT_GlitchData, + OutSignalName => "L0FWDNONFATALERROUT", + OutTemp => L0FWDNONFATALERROUT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0FWDNONFATALERROUT, + GlitchData => L0FWDNONFATALERROUT_GlitchData, + OutSignalName => "L0FWDNONFATALERROUT", + OutTemp => L0FWDNONFATALERROUT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDASSERTINTALEGACYINT, + GlitchData => L0RECEIVEDASSERTINTALEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDASSERTINTALEGACYINT", + OutTemp => L0RECEIVEDASSERTINTALEGACYINT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDASSERTINTALEGACYINT, + GlitchData => L0RECEIVEDASSERTINTALEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDASSERTINTALEGACYINT", + OutTemp => L0RECEIVEDASSERTINTALEGACYINT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDASSERTINTBLEGACYINT, + GlitchData => L0RECEIVEDASSERTINTBLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDASSERTINTBLEGACYINT", + OutTemp => L0RECEIVEDASSERTINTBLEGACYINT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDASSERTINTBLEGACYINT, + GlitchData => L0RECEIVEDASSERTINTBLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDASSERTINTBLEGACYINT", + OutTemp => L0RECEIVEDASSERTINTBLEGACYINT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDASSERTINTCLEGACYINT, + GlitchData => L0RECEIVEDASSERTINTCLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDASSERTINTCLEGACYINT", + OutTemp => L0RECEIVEDASSERTINTCLEGACYINT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDASSERTINTCLEGACYINT, + GlitchData => L0RECEIVEDASSERTINTCLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDASSERTINTCLEGACYINT", + OutTemp => L0RECEIVEDASSERTINTCLEGACYINT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDASSERTINTDLEGACYINT, + GlitchData => L0RECEIVEDASSERTINTDLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDASSERTINTDLEGACYINT", + OutTemp => L0RECEIVEDASSERTINTDLEGACYINT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDASSERTINTDLEGACYINT, + GlitchData => L0RECEIVEDASSERTINTDLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDASSERTINTDLEGACYINT", + OutTemp => L0RECEIVEDASSERTINTDLEGACYINT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDDEASSERTINTALEGACYINT, + GlitchData => L0RECEIVEDDEASSERTINTALEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDDEASSERTINTALEGACYINT", + OutTemp => L0RECEIVEDDEASSERTINTALEGACYINT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDDEASSERTINTALEGACYINT, + GlitchData => L0RECEIVEDDEASSERTINTALEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDDEASSERTINTALEGACYINT", + OutTemp => L0RECEIVEDDEASSERTINTALEGACYINT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDDEASSERTINTBLEGACYINT, + GlitchData => L0RECEIVEDDEASSERTINTBLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDDEASSERTINTBLEGACYINT", + OutTemp => L0RECEIVEDDEASSERTINTBLEGACYINT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDDEASSERTINTBLEGACYINT, + GlitchData => L0RECEIVEDDEASSERTINTBLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDDEASSERTINTBLEGACYINT", + OutTemp => L0RECEIVEDDEASSERTINTBLEGACYINT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDDEASSERTINTCLEGACYINT, + GlitchData => L0RECEIVEDDEASSERTINTCLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDDEASSERTINTCLEGACYINT", + OutTemp => L0RECEIVEDDEASSERTINTCLEGACYINT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDDEASSERTINTCLEGACYINT, + GlitchData => L0RECEIVEDDEASSERTINTCLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDDEASSERTINTCLEGACYINT", + OutTemp => L0RECEIVEDDEASSERTINTCLEGACYINT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDDEASSERTINTDLEGACYINT, + GlitchData => L0RECEIVEDDEASSERTINTDLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDDEASSERTINTDLEGACYINT", + OutTemp => L0RECEIVEDDEASSERTINTDLEGACYINT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RECEIVEDDEASSERTINTDLEGACYINT, + GlitchData => L0RECEIVEDDEASSERTINTDLEGACYINT_GlitchData, + OutSignalName => "L0RECEIVEDDEASSERTINTDLEGACYINT", + OutTemp => L0RECEIVEDDEASSERTINTDLEGACYINT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MSIENABLE0, + GlitchData => L0MSIENABLE0_GlitchData, + OutSignalName => "L0MSIENABLE0", + OutTemp => L0MSIENABLE0_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MSIENABLE0, + GlitchData => L0MSIENABLE0_GlitchData, + OutSignalName => "L0MSIENABLE0", + OutTemp => L0MSIENABLE0_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MULTIMSGEN0(0), + GlitchData => L0MULTIMSGEN00_GlitchData, + OutSignalName => "L0MULTIMSGEN0(0)", + OutTemp => L0MULTIMSGEN0_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MULTIMSGEN0(0), + GlitchData => L0MULTIMSGEN00_GlitchData, + OutSignalName => "L0MULTIMSGEN0(0)", + OutTemp => L0MULTIMSGEN0_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MULTIMSGEN0(1), + GlitchData => L0MULTIMSGEN01_GlitchData, + OutSignalName => "L0MULTIMSGEN0(1)", + OutTemp => L0MULTIMSGEN0_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MULTIMSGEN0(1), + GlitchData => L0MULTIMSGEN01_GlitchData, + OutSignalName => "L0MULTIMSGEN0(1)", + OutTemp => L0MULTIMSGEN0_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MULTIMSGEN0(2), + GlitchData => L0MULTIMSGEN02_GlitchData, + OutSignalName => "L0MULTIMSGEN0(2)", + OutTemp => L0MULTIMSGEN0_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MULTIMSGEN0(2), + GlitchData => L0MULTIMSGEN02_GlitchData, + OutSignalName => "L0MULTIMSGEN0(2)", + OutTemp => L0MULTIMSGEN0_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSDLLPRECEIVED, + GlitchData => L0STATSDLLPRECEIVED_GlitchData, + OutSignalName => "L0STATSDLLPRECEIVED", + OutTemp => L0STATSDLLPRECEIVED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSDLLPTRANSMITTED, + GlitchData => L0STATSDLLPTRANSMITTED_GlitchData, + OutSignalName => "L0STATSDLLPTRANSMITTED", + OutTemp => L0STATSDLLPTRANSMITTED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSOSRECEIVED, + GlitchData => L0STATSOSRECEIVED_GlitchData, + OutSignalName => "L0STATSOSRECEIVED", + OutTemp => L0STATSOSRECEIVED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSOSTRANSMITTED, + GlitchData => L0STATSOSTRANSMITTED_GlitchData, + OutSignalName => "L0STATSOSTRANSMITTED", + OutTemp => L0STATSOSTRANSMITTED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSTLPRECEIVED, + GlitchData => L0STATSTLPRECEIVED_GlitchData, + OutSignalName => "L0STATSTLPRECEIVED", + OutTemp => L0STATSTLPRECEIVED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSTLPTRANSMITTED, + GlitchData => L0STATSTLPTRANSMITTED_GlitchData, + OutSignalName => "L0STATSTLPTRANSMITTED", + OutTemp => L0STATSTLPTRANSMITTED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSCFGRECEIVED, + GlitchData => L0STATSCFGRECEIVED_GlitchData, + OutSignalName => "L0STATSCFGRECEIVED", + OutTemp => L0STATSCFGRECEIVED_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSCFGRECEIVED, + GlitchData => L0STATSCFGRECEIVED_GlitchData, + OutSignalName => "L0STATSCFGRECEIVED", + OutTemp => L0STATSCFGRECEIVED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSCFGTRANSMITTED, + GlitchData => L0STATSCFGTRANSMITTED_GlitchData, + OutSignalName => "L0STATSCFGTRANSMITTED", + OutTemp => L0STATSCFGTRANSMITTED_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSCFGTRANSMITTED, + GlitchData => L0STATSCFGTRANSMITTED_GlitchData, + OutSignalName => "L0STATSCFGTRANSMITTED", + OutTemp => L0STATSCFGTRANSMITTED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSCFGOTHERRECEIVED, + GlitchData => L0STATSCFGOTHERRECEIVED_GlitchData, + OutSignalName => "L0STATSCFGOTHERRECEIVED", + OutTemp => L0STATSCFGOTHERRECEIVED_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSCFGOTHERRECEIVED, + GlitchData => L0STATSCFGOTHERRECEIVED_GlitchData, + OutSignalName => "L0STATSCFGOTHERRECEIVED", + OutTemp => L0STATSCFGOTHERRECEIVED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSCFGOTHERTRANSMITTED, + GlitchData => L0STATSCFGOTHERTRANSMITTED_GlitchData, + OutSignalName => "L0STATSCFGOTHERTRANSMITTED", + OutTemp => L0STATSCFGOTHERTRANSMITTED_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0STATSCFGOTHERTRANSMITTED, + GlitchData => L0STATSCFGOTHERTRANSMITTED_GlitchData, + OutSignalName => "L0STATSCFGOTHERTRANSMITTED", + OutTemp => L0STATSCFGOTHERTRANSMITTED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXPAYLOADSIZE(0), + GlitchData => MAXPAYLOADSIZE0_GlitchData, + OutSignalName => "MAXPAYLOADSIZE(0)", + OutTemp => MAXPAYLOADSIZE_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXPAYLOADSIZE(0), + GlitchData => MAXPAYLOADSIZE0_GlitchData, + OutSignalName => "MAXPAYLOADSIZE(0)", + OutTemp => MAXPAYLOADSIZE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXPAYLOADSIZE(1), + GlitchData => MAXPAYLOADSIZE1_GlitchData, + OutSignalName => "MAXPAYLOADSIZE(1)", + OutTemp => MAXPAYLOADSIZE_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXPAYLOADSIZE(1), + GlitchData => MAXPAYLOADSIZE1_GlitchData, + OutSignalName => "MAXPAYLOADSIZE(1)", + OutTemp => MAXPAYLOADSIZE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXPAYLOADSIZE(2), + GlitchData => MAXPAYLOADSIZE2_GlitchData, + OutSignalName => "MAXPAYLOADSIZE(2)", + OutTemp => MAXPAYLOADSIZE_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXPAYLOADSIZE(2), + GlitchData => MAXPAYLOADSIZE2_GlitchData, + OutSignalName => "MAXPAYLOADSIZE(2)", + OutTemp => MAXPAYLOADSIZE_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXREADREQUESTSIZE(0), + GlitchData => MAXREADREQUESTSIZE0_GlitchData, + OutSignalName => "MAXREADREQUESTSIZE(0)", + OutTemp => MAXREADREQUESTSIZE_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXREADREQUESTSIZE(0), + GlitchData => MAXREADREQUESTSIZE0_GlitchData, + OutSignalName => "MAXREADREQUESTSIZE(0)", + OutTemp => MAXREADREQUESTSIZE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXREADREQUESTSIZE(1), + GlitchData => MAXREADREQUESTSIZE1_GlitchData, + OutSignalName => "MAXREADREQUESTSIZE(1)", + OutTemp => MAXREADREQUESTSIZE_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXREADREQUESTSIZE(1), + GlitchData => MAXREADREQUESTSIZE1_GlitchData, + OutSignalName => "MAXREADREQUESTSIZE(1)", + OutTemp => MAXREADREQUESTSIZE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXREADREQUESTSIZE(2), + GlitchData => MAXREADREQUESTSIZE2_GlitchData, + OutSignalName => "MAXREADREQUESTSIZE(2)", + OutTemp => MAXREADREQUESTSIZE_OUT(2), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MAXREADREQUESTSIZE(2), + GlitchData => MAXREADREQUESTSIZE2_GlitchData, + OutSignalName => "MAXREADREQUESTSIZE(2)", + OutTemp => MAXREADREQUESTSIZE_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => IOSPACEENABLE, + GlitchData => IOSPACEENABLE_GlitchData, + OutSignalName => "IOSPACEENABLE", + OutTemp => IOSPACEENABLE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => IOSPACEENABLE, + GlitchData => IOSPACEENABLE_GlitchData, + OutSignalName => "IOSPACEENABLE", + OutTemp => IOSPACEENABLE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MEMSPACEENABLE, + GlitchData => MEMSPACEENABLE_GlitchData, + OutSignalName => "MEMSPACEENABLE", + OutTemp => MEMSPACEENABLE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MEMSPACEENABLE, + GlitchData => MEMSPACEENABLE_GlitchData, + OutSignalName => "MEMSPACEENABLE", + OutTemp => MEMSPACEENABLE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ATTENTIONINDICATORCONTROL(0), + GlitchData => L0ATTENTIONINDICATORCONTROL0_GlitchData, + OutSignalName => "L0ATTENTIONINDICATORCONTROL(0)", + OutTemp => L0ATTENTIONINDICATORCONTROL_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ATTENTIONINDICATORCONTROL(0), + GlitchData => L0ATTENTIONINDICATORCONTROL0_GlitchData, + OutSignalName => "L0ATTENTIONINDICATORCONTROL(0)", + OutTemp => L0ATTENTIONINDICATORCONTROL_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ATTENTIONINDICATORCONTROL(1), + GlitchData => L0ATTENTIONINDICATORCONTROL1_GlitchData, + OutSignalName => "L0ATTENTIONINDICATORCONTROL(1)", + OutTemp => L0ATTENTIONINDICATORCONTROL_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0ATTENTIONINDICATORCONTROL(1), + GlitchData => L0ATTENTIONINDICATORCONTROL1_GlitchData, + OutSignalName => "L0ATTENTIONINDICATORCONTROL(1)", + OutTemp => L0ATTENTIONINDICATORCONTROL_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0POWERINDICATORCONTROL(0), + GlitchData => L0POWERINDICATORCONTROL0_GlitchData, + OutSignalName => "L0POWERINDICATORCONTROL(0)", + OutTemp => L0POWERINDICATORCONTROL_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0POWERINDICATORCONTROL(0), + GlitchData => L0POWERINDICATORCONTROL0_GlitchData, + OutSignalName => "L0POWERINDICATORCONTROL(0)", + OutTemp => L0POWERINDICATORCONTROL_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0POWERINDICATORCONTROL(1), + GlitchData => L0POWERINDICATORCONTROL1_GlitchData, + OutSignalName => "L0POWERINDICATORCONTROL(1)", + OutTemp => L0POWERINDICATORCONTROL_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0POWERINDICATORCONTROL(1), + GlitchData => L0POWERINDICATORCONTROL1_GlitchData, + OutSignalName => "L0POWERINDICATORCONTROL(1)", + OutTemp => L0POWERINDICATORCONTROL_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0POWERCONTROLLERCONTROL, + GlitchData => L0POWERCONTROLLERCONTROL_GlitchData, + OutSignalName => "L0POWERCONTROLLERCONTROL", + OutTemp => L0POWERCONTROLLERCONTROL_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0POWERCONTROLLERCONTROL, + GlitchData => L0POWERCONTROLLERCONTROL_GlitchData, + OutSignalName => "L0POWERCONTROLLERCONTROL", + OutTemp => L0POWERCONTROLLERCONTROL_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TOGGLEELECTROMECHANICALINTERLOCK, + GlitchData => L0TOGGLEELECTROMECHANICALINTERLOCK_GlitchData, + OutSignalName => "L0TOGGLEELECTROMECHANICALINTERLOCK", + OutTemp => L0TOGGLEELECTROMECHANICALINTERLOCK_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TOGGLEELECTROMECHANICALINTERLOCK, + GlitchData => L0TOGGLEELECTROMECHANICALINTERLOCK_GlitchData, + OutSignalName => "L0TOGGLEELECTROMECHANICALINTERLOCK", + OutTemp => L0TOGGLEELECTROMECHANICALINTERLOCK_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXBEACON, + GlitchData => L0RXBEACON_GlitchData, + OutSignalName => "L0RXBEACON", + OutTemp => L0RXBEACON_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXBEACON, + GlitchData => L0RXBEACON_GlitchData, + OutSignalName => "L0RXBEACON", + OutTemp => L0RXBEACON_OUT, + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXBEACON, + GlitchData => L0RXBEACON_GlitchData, + OutSignalName => "L0RXBEACON", + OutTemp => L0RXBEACON_OUT, + Paths => (0 => (L0WAKEN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRSTATE0(0), + GlitchData => L0PWRSTATE00_GlitchData, + OutSignalName => "L0PWRSTATE0(0)", + OutTemp => L0PWRSTATE0_OUT(0), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRSTATE0(0), + GlitchData => L0PWRSTATE00_GlitchData, + OutSignalName => "L0PWRSTATE0(0)", + OutTemp => L0PWRSTATE0_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRSTATE0(1), + GlitchData => L0PWRSTATE01_GlitchData, + OutSignalName => "L0PWRSTATE0(1)", + OutTemp => L0PWRSTATE0_OUT(1), + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRSTATE0(1), + GlitchData => L0PWRSTATE01_GlitchData, + OutSignalName => "L0PWRSTATE0(1)", + OutTemp => L0PWRSTATE0_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PMEACK, + GlitchData => L0PMEACK_GlitchData, + OutSignalName => "L0PMEACK", + OutTemp => L0PMEACK_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PMEACK, + GlitchData => L0PMEACK_GlitchData, + OutSignalName => "L0PMEACK", + OutTemp => L0PMEACK_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PMEREQOUT, + GlitchData => L0PMEREQOUT_GlitchData, + OutSignalName => "L0PMEREQOUT", + OutTemp => L0PMEREQOUT_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PMEREQOUT, + GlitchData => L0PMEREQOUT_GlitchData, + OutSignalName => "L0PMEREQOUT", + OutTemp => L0PMEREQOUT_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PMEREQOUT, + GlitchData => L0PMEREQOUT_GlitchData, + OutSignalName => "L0PMEREQOUT", + OutTemp => L0PMEREQOUT_OUT, + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PMEEN, + GlitchData => L0PMEEN_GlitchData, + OutSignalName => "L0PMEEN", + OutTemp => L0PMEEN_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PMEEN, + GlitchData => L0PMEEN_GlitchData, + OutSignalName => "L0PMEEN", + OutTemp => L0PMEEN_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PMEEN, + GlitchData => L0PMEEN_GlitchData, + OutSignalName => "L0PMEEN", + OutTemp => L0PMEEN_OUT, + Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRINHIBITTRANSFERS, + GlitchData => L0PWRINHIBITTRANSFERS_GlitchData, + OutSignalName => "L0PWRINHIBITTRANSFERS", + OutTemp => L0PWRINHIBITTRANSFERS_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRL1STATE, + GlitchData => L0PWRL1STATE_GlitchData, + OutSignalName => "L0PWRL1STATE", + OutTemp => L0PWRL1STATE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRL1STATE, + GlitchData => L0PWRL1STATE_GlitchData, + OutSignalName => "L0PWRL1STATE", + OutTemp => L0PWRL1STATE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRL23READYDEVICE, + GlitchData => L0PWRL23READYDEVICE_GlitchData, + OutSignalName => "L0PWRL23READYDEVICE", + OutTemp => L0PWRL23READYDEVICE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRL23READYDEVICE, + GlitchData => L0PWRL23READYDEVICE_GlitchData, + OutSignalName => "L0PWRL23READYDEVICE", + OutTemp => L0PWRL23READYDEVICE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRL23READYSTATE, + GlitchData => L0PWRL23READYSTATE_GlitchData, + OutSignalName => "L0PWRL23READYSTATE", + OutTemp => L0PWRL23READYSTATE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRL23READYSTATE, + GlitchData => L0PWRL23READYSTATE_GlitchData, + OutSignalName => "L0PWRL23READYSTATE", + OutTemp => L0PWRL23READYSTATE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRTXL0SSTATE, + GlitchData => L0PWRTXL0SSTATE_GlitchData, + OutSignalName => "L0PWRTXL0SSTATE", + OutTemp => L0PWRTXL0SSTATE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRTXL0SSTATE, + GlitchData => L0PWRTXL0SSTATE_GlitchData, + OutSignalName => "L0PWRTXL0SSTATE", + OutTemp => L0PWRTXL0SSTATE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRTURNOFFREQ, + GlitchData => L0PWRTURNOFFREQ_GlitchData, + OutSignalName => "L0PWRTURNOFFREQ", + OutTemp => L0PWRTURNOFFREQ_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0PWRTURNOFFREQ, + GlitchData => L0PWRTURNOFFREQ_GlitchData, + OutSignalName => "L0PWRTURNOFFREQ", + OutTemp => L0PWRTURNOFFREQ_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLPM, + GlitchData => L0RXDLLPM_GlitchData, + OutSignalName => "L0RXDLLPM", + OutTemp => L0RXDLLPM_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLPMTYPE(0), + GlitchData => L0RXDLLPMTYPE0_GlitchData, + OutSignalName => "L0RXDLLPMTYPE(0)", + OutTemp => L0RXDLLPMTYPE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLPMTYPE(1), + GlitchData => L0RXDLLPMTYPE1_GlitchData, + OutSignalName => "L0RXDLLPMTYPE(1)", + OutTemp => L0RXDLLPMTYPE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLPMTYPE(2), + GlitchData => L0RXDLLPMTYPE2_GlitchData, + OutSignalName => "L0RXDLLPMTYPE(2)", + OutTemp => L0RXDLLPMTYPE_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLPMUPDATED, + GlitchData => L0TXDLLPMUPDATED_GlitchData, + OutSignalName => "L0TXDLLPMUPDATED", + OutTemp => L0TXDLLPMUPDATED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACNEWSTATEACK, + GlitchData => L0MACNEWSTATEACK_GlitchData, + OutSignalName => "L0MACNEWSTATEACK", + OutTemp => L0MACNEWSTATEACK_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACRXL0SSTATE, + GlitchData => L0MACRXL0SSTATE_GlitchData, + OutSignalName => "L0MACRXL0SSTATE", + OutTemp => L0MACRXL0SSTATE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MACENTEREDL0, + GlitchData => L0MACENTEREDL0_GlitchData, + OutSignalName => "L0MACENTEREDL0", + OutTemp => L0MACENTEREDL0_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLRXACKOUTSTANDING, + GlitchData => L0DLLRXACKOUTSTANDING_GlitchData, + OutSignalName => "L0DLLRXACKOUTSTANDING", + OutTemp => L0DLLRXACKOUTSTANDING_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLTXOUTSTANDING, + GlitchData => L0DLLTXOUTSTANDING_GlitchData, + OutSignalName => "L0DLLTXOUTSTANDING", + OutTemp => L0DLLTXOUTSTANDING_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0DLLTXNONFCOUTSTANDING, + GlitchData => L0DLLTXNONFCOUTSTANDING_GlitchData, + OutSignalName => "L0DLLTXNONFCOUTSTANDING", + OutTemp => L0DLLTXNONFCOUTSTANDING_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLTLPEND(0), + GlitchData => L0RXDLLTLPEND0_GlitchData, + OutSignalName => "L0RXDLLTLPEND(0)", + OutTemp => L0RXDLLTLPEND_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLTLPEND(1), + GlitchData => L0RXDLLTLPEND1_GlitchData, + OutSignalName => "L0RXDLLTLPEND(1)", + OutTemp => L0RXDLLTLPEND_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLSBFCUPDATED, + GlitchData => L0TXDLLSBFCUPDATED_GlitchData, + OutSignalName => "L0TXDLLSBFCUPDATED", + OutTemp => L0TXDLLSBFCUPDATED_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(0), + GlitchData => L0RXDLLSBFCDATA0_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(0)", + OutTemp => L0RXDLLSBFCDATA_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(1), + GlitchData => L0RXDLLSBFCDATA1_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(1)", + OutTemp => L0RXDLLSBFCDATA_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(2), + GlitchData => L0RXDLLSBFCDATA2_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(2)", + OutTemp => L0RXDLLSBFCDATA_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(3), + GlitchData => L0RXDLLSBFCDATA3_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(3)", + OutTemp => L0RXDLLSBFCDATA_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(4), + GlitchData => L0RXDLLSBFCDATA4_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(4)", + OutTemp => L0RXDLLSBFCDATA_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(5), + GlitchData => L0RXDLLSBFCDATA5_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(5)", + OutTemp => L0RXDLLSBFCDATA_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(6), + GlitchData => L0RXDLLSBFCDATA6_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(6)", + OutTemp => L0RXDLLSBFCDATA_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(7), + GlitchData => L0RXDLLSBFCDATA7_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(7)", + OutTemp => L0RXDLLSBFCDATA_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(8), + GlitchData => L0RXDLLSBFCDATA8_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(8)", + OutTemp => L0RXDLLSBFCDATA_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(9), + GlitchData => L0RXDLLSBFCDATA9_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(9)", + OutTemp => L0RXDLLSBFCDATA_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(10), + GlitchData => L0RXDLLSBFCDATA10_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(10)", + OutTemp => L0RXDLLSBFCDATA_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(11), + GlitchData => L0RXDLLSBFCDATA11_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(11)", + OutTemp => L0RXDLLSBFCDATA_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(12), + GlitchData => L0RXDLLSBFCDATA12_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(12)", + OutTemp => L0RXDLLSBFCDATA_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(13), + GlitchData => L0RXDLLSBFCDATA13_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(13)", + OutTemp => L0RXDLLSBFCDATA_OUT(13), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(14), + GlitchData => L0RXDLLSBFCDATA14_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(14)", + OutTemp => L0RXDLLSBFCDATA_OUT(14), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(15), + GlitchData => L0RXDLLSBFCDATA15_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(15)", + OutTemp => L0RXDLLSBFCDATA_OUT(15), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(16), + GlitchData => L0RXDLLSBFCDATA16_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(16)", + OutTemp => L0RXDLLSBFCDATA_OUT(16), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(17), + GlitchData => L0RXDLLSBFCDATA17_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(17)", + OutTemp => L0RXDLLSBFCDATA_OUT(17), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCDATA(18), + GlitchData => L0RXDLLSBFCDATA18_GlitchData, + OutSignalName => "L0RXDLLSBFCDATA(18)", + OutTemp => L0RXDLLSBFCDATA_OUT(18), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLSBFCUPDATE, + GlitchData => L0RXDLLSBFCUPDATE_GlitchData, + OutSignalName => "L0RXDLLSBFCUPDATE", + OutTemp => L0RXDLLSBFCUPDATE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCNPOSTBYPUPDATED(0), + GlitchData => L0TXDLLFCNPOSTBYPUPDATED0_GlitchData, + OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(0)", + OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCNPOSTBYPUPDATED(1), + GlitchData => L0TXDLLFCNPOSTBYPUPDATED1_GlitchData, + OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(1)", + OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCNPOSTBYPUPDATED(2), + GlitchData => L0TXDLLFCNPOSTBYPUPDATED2_GlitchData, + OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(2)", + OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCNPOSTBYPUPDATED(3), + GlitchData => L0TXDLLFCNPOSTBYPUPDATED3_GlitchData, + OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(3)", + OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCNPOSTBYPUPDATED(4), + GlitchData => L0TXDLLFCNPOSTBYPUPDATED4_GlitchData, + OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(4)", + OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCNPOSTBYPUPDATED(5), + GlitchData => L0TXDLLFCNPOSTBYPUPDATED5_GlitchData, + OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(5)", + OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCNPOSTBYPUPDATED(6), + GlitchData => L0TXDLLFCNPOSTBYPUPDATED6_GlitchData, + OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(6)", + OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCNPOSTBYPUPDATED(7), + GlitchData => L0TXDLLFCNPOSTBYPUPDATED7_GlitchData, + OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(7)", + OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCPOSTORDUPDATED(0), + GlitchData => L0TXDLLFCPOSTORDUPDATED0_GlitchData, + OutSignalName => "L0TXDLLFCPOSTORDUPDATED(0)", + OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCPOSTORDUPDATED(1), + GlitchData => L0TXDLLFCPOSTORDUPDATED1_GlitchData, + OutSignalName => "L0TXDLLFCPOSTORDUPDATED(1)", + OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCPOSTORDUPDATED(2), + GlitchData => L0TXDLLFCPOSTORDUPDATED2_GlitchData, + OutSignalName => "L0TXDLLFCPOSTORDUPDATED(2)", + OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCPOSTORDUPDATED(3), + GlitchData => L0TXDLLFCPOSTORDUPDATED3_GlitchData, + OutSignalName => "L0TXDLLFCPOSTORDUPDATED(3)", + OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCPOSTORDUPDATED(4), + GlitchData => L0TXDLLFCPOSTORDUPDATED4_GlitchData, + OutSignalName => "L0TXDLLFCPOSTORDUPDATED(4)", + OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCPOSTORDUPDATED(5), + GlitchData => L0TXDLLFCPOSTORDUPDATED5_GlitchData, + OutSignalName => "L0TXDLLFCPOSTORDUPDATED(5)", + OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCPOSTORDUPDATED(6), + GlitchData => L0TXDLLFCPOSTORDUPDATED6_GlitchData, + OutSignalName => "L0TXDLLFCPOSTORDUPDATED(6)", + OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCPOSTORDUPDATED(7), + GlitchData => L0TXDLLFCPOSTORDUPDATED7_GlitchData, + OutSignalName => "L0TXDLLFCPOSTORDUPDATED(7)", + OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCCMPLMCUPDATED(0), + GlitchData => L0TXDLLFCCMPLMCUPDATED0_GlitchData, + OutSignalName => "L0TXDLLFCCMPLMCUPDATED(0)", + OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCCMPLMCUPDATED(1), + GlitchData => L0TXDLLFCCMPLMCUPDATED1_GlitchData, + OutSignalName => "L0TXDLLFCCMPLMCUPDATED(1)", + OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCCMPLMCUPDATED(2), + GlitchData => L0TXDLLFCCMPLMCUPDATED2_GlitchData, + OutSignalName => "L0TXDLLFCCMPLMCUPDATED(2)", + OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCCMPLMCUPDATED(3), + GlitchData => L0TXDLLFCCMPLMCUPDATED3_GlitchData, + OutSignalName => "L0TXDLLFCCMPLMCUPDATED(3)", + OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCCMPLMCUPDATED(4), + GlitchData => L0TXDLLFCCMPLMCUPDATED4_GlitchData, + OutSignalName => "L0TXDLLFCCMPLMCUPDATED(4)", + OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCCMPLMCUPDATED(5), + GlitchData => L0TXDLLFCCMPLMCUPDATED5_GlitchData, + OutSignalName => "L0TXDLLFCCMPLMCUPDATED(5)", + OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCCMPLMCUPDATED(6), + GlitchData => L0TXDLLFCCMPLMCUPDATED6_GlitchData, + OutSignalName => "L0TXDLLFCCMPLMCUPDATED(6)", + OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TXDLLFCCMPLMCUPDATED(7), + GlitchData => L0TXDLLFCCMPLMCUPDATED7_GlitchData, + OutSignalName => "L0TXDLLFCCMPLMCUPDATED(7)", + OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(0), + GlitchData => L0RXDLLFCNPOSTBYPCRED0_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(0)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(1), + GlitchData => L0RXDLLFCNPOSTBYPCRED1_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(1)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(2), + GlitchData => L0RXDLLFCNPOSTBYPCRED2_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(2)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(3), + GlitchData => L0RXDLLFCNPOSTBYPCRED3_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(3)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(4), + GlitchData => L0RXDLLFCNPOSTBYPCRED4_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(4)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(5), + GlitchData => L0RXDLLFCNPOSTBYPCRED5_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(5)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(6), + GlitchData => L0RXDLLFCNPOSTBYPCRED6_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(6)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(7), + GlitchData => L0RXDLLFCNPOSTBYPCRED7_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(7)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(8), + GlitchData => L0RXDLLFCNPOSTBYPCRED8_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(8)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(9), + GlitchData => L0RXDLLFCNPOSTBYPCRED9_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(9)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(10), + GlitchData => L0RXDLLFCNPOSTBYPCRED10_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(10)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(11), + GlitchData => L0RXDLLFCNPOSTBYPCRED11_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(11)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(12), + GlitchData => L0RXDLLFCNPOSTBYPCRED12_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(12)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(13), + GlitchData => L0RXDLLFCNPOSTBYPCRED13_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(13)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(13), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(14), + GlitchData => L0RXDLLFCNPOSTBYPCRED14_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(14)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(14), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(15), + GlitchData => L0RXDLLFCNPOSTBYPCRED15_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(15)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(15), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(16), + GlitchData => L0RXDLLFCNPOSTBYPCRED16_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(16)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(16), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(17), + GlitchData => L0RXDLLFCNPOSTBYPCRED17_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(17)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(17), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(18), + GlitchData => L0RXDLLFCNPOSTBYPCRED18_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(18)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(18), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPCRED(19), + GlitchData => L0RXDLLFCNPOSTBYPCRED19_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPCRED(19)", + OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(19), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPUPDATE(0), + GlitchData => L0RXDLLFCNPOSTBYPUPDATE0_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(0)", + OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPUPDATE(1), + GlitchData => L0RXDLLFCNPOSTBYPUPDATE1_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(1)", + OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPUPDATE(2), + GlitchData => L0RXDLLFCNPOSTBYPUPDATE2_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(2)", + OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPUPDATE(3), + GlitchData => L0RXDLLFCNPOSTBYPUPDATE3_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(3)", + OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPUPDATE(4), + GlitchData => L0RXDLLFCNPOSTBYPUPDATE4_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(4)", + OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPUPDATE(5), + GlitchData => L0RXDLLFCNPOSTBYPUPDATE5_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(5)", + OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPUPDATE(6), + GlitchData => L0RXDLLFCNPOSTBYPUPDATE6_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(6)", + OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCNPOSTBYPUPDATE(7), + GlitchData => L0RXDLLFCNPOSTBYPUPDATE7_GlitchData, + OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(7)", + OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(0), + GlitchData => L0RXDLLFCPOSTORDCRED0_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(0)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(1), + GlitchData => L0RXDLLFCPOSTORDCRED1_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(1)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(2), + GlitchData => L0RXDLLFCPOSTORDCRED2_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(2)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(3), + GlitchData => L0RXDLLFCPOSTORDCRED3_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(3)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(4), + GlitchData => L0RXDLLFCPOSTORDCRED4_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(4)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(5), + GlitchData => L0RXDLLFCPOSTORDCRED5_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(5)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(6), + GlitchData => L0RXDLLFCPOSTORDCRED6_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(6)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(7), + GlitchData => L0RXDLLFCPOSTORDCRED7_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(7)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(8), + GlitchData => L0RXDLLFCPOSTORDCRED8_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(8)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(9), + GlitchData => L0RXDLLFCPOSTORDCRED9_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(9)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(10), + GlitchData => L0RXDLLFCPOSTORDCRED10_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(10)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(11), + GlitchData => L0RXDLLFCPOSTORDCRED11_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(11)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(12), + GlitchData => L0RXDLLFCPOSTORDCRED12_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(12)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(13), + GlitchData => L0RXDLLFCPOSTORDCRED13_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(13)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(13), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(14), + GlitchData => L0RXDLLFCPOSTORDCRED14_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(14)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(14), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(15), + GlitchData => L0RXDLLFCPOSTORDCRED15_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(15)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(15), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(16), + GlitchData => L0RXDLLFCPOSTORDCRED16_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(16)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(16), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(17), + GlitchData => L0RXDLLFCPOSTORDCRED17_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(17)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(17), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(18), + GlitchData => L0RXDLLFCPOSTORDCRED18_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(18)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(18), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(19), + GlitchData => L0RXDLLFCPOSTORDCRED19_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(19)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(19), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(20), + GlitchData => L0RXDLLFCPOSTORDCRED20_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(20)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(20), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(21), + GlitchData => L0RXDLLFCPOSTORDCRED21_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(21)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(21), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(22), + GlitchData => L0RXDLLFCPOSTORDCRED22_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(22)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(22), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDCRED(23), + GlitchData => L0RXDLLFCPOSTORDCRED23_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDCRED(23)", + OutTemp => L0RXDLLFCPOSTORDCRED_OUT(23), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDUPDATE(0), + GlitchData => L0RXDLLFCPOSTORDUPDATE0_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDUPDATE(0)", + OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDUPDATE(1), + GlitchData => L0RXDLLFCPOSTORDUPDATE1_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDUPDATE(1)", + OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDUPDATE(2), + GlitchData => L0RXDLLFCPOSTORDUPDATE2_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDUPDATE(2)", + OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDUPDATE(3), + GlitchData => L0RXDLLFCPOSTORDUPDATE3_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDUPDATE(3)", + OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDUPDATE(4), + GlitchData => L0RXDLLFCPOSTORDUPDATE4_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDUPDATE(4)", + OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDUPDATE(5), + GlitchData => L0RXDLLFCPOSTORDUPDATE5_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDUPDATE(5)", + OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDUPDATE(6), + GlitchData => L0RXDLLFCPOSTORDUPDATE6_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDUPDATE(6)", + OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCPOSTORDUPDATE(7), + GlitchData => L0RXDLLFCPOSTORDUPDATE7_GlitchData, + OutSignalName => "L0RXDLLFCPOSTORDUPDATE(7)", + OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(0), + GlitchData => L0RXDLLFCCMPLMCCRED0_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(0)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(1), + GlitchData => L0RXDLLFCCMPLMCCRED1_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(1)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(2), + GlitchData => L0RXDLLFCCMPLMCCRED2_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(2)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(3), + GlitchData => L0RXDLLFCCMPLMCCRED3_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(3)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(4), + GlitchData => L0RXDLLFCCMPLMCCRED4_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(4)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(5), + GlitchData => L0RXDLLFCCMPLMCCRED5_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(5)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(6), + GlitchData => L0RXDLLFCCMPLMCCRED6_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(6)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(7), + GlitchData => L0RXDLLFCCMPLMCCRED7_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(7)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(8), + GlitchData => L0RXDLLFCCMPLMCCRED8_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(8)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(8), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(9), + GlitchData => L0RXDLLFCCMPLMCCRED9_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(9)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(9), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(10), + GlitchData => L0RXDLLFCCMPLMCCRED10_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(10)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(10), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(11), + GlitchData => L0RXDLLFCCMPLMCCRED11_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(11)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(11), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(12), + GlitchData => L0RXDLLFCCMPLMCCRED12_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(12)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(12), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(13), + GlitchData => L0RXDLLFCCMPLMCCRED13_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(13)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(13), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(14), + GlitchData => L0RXDLLFCCMPLMCCRED14_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(14)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(14), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(15), + GlitchData => L0RXDLLFCCMPLMCCRED15_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(15)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(15), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(16), + GlitchData => L0RXDLLFCCMPLMCCRED16_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(16)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(16), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(17), + GlitchData => L0RXDLLFCCMPLMCCRED17_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(17)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(17), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(18), + GlitchData => L0RXDLLFCCMPLMCCRED18_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(18)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(18), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(19), + GlitchData => L0RXDLLFCCMPLMCCRED19_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(19)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(19), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(20), + GlitchData => L0RXDLLFCCMPLMCCRED20_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(20)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(20), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(21), + GlitchData => L0RXDLLFCCMPLMCCRED21_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(21)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(21), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(22), + GlitchData => L0RXDLLFCCMPLMCCRED22_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(22)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(22), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCCRED(23), + GlitchData => L0RXDLLFCCMPLMCCRED23_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCCRED(23)", + OutTemp => L0RXDLLFCCMPLMCCRED_OUT(23), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCUPDATE(0), + GlitchData => L0RXDLLFCCMPLMCUPDATE0_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCUPDATE(0)", + OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCUPDATE(1), + GlitchData => L0RXDLLFCCMPLMCUPDATE1_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCUPDATE(1)", + OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCUPDATE(2), + GlitchData => L0RXDLLFCCMPLMCUPDATE2_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCUPDATE(2)", + OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCUPDATE(3), + GlitchData => L0RXDLLFCCMPLMCUPDATE3_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCUPDATE(3)", + OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCUPDATE(4), + GlitchData => L0RXDLLFCCMPLMCUPDATE4_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCUPDATE(4)", + OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(4), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCUPDATE(5), + GlitchData => L0RXDLLFCCMPLMCUPDATE5_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCUPDATE(5)", + OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(5), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCUPDATE(6), + GlitchData => L0RXDLLFCCMPLMCUPDATE6_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCUPDATE(6)", + OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(6), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0RXDLLFCCMPLMCUPDATE(7), + GlitchData => L0RXDLLFCCMPLMCUPDATE7_GlitchData, + OutSignalName => "L0RXDLLFCCMPLMCUPDATE(7)", + OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(7), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UCBYPFOUND(0), + GlitchData => L0UCBYPFOUND0_GlitchData, + OutSignalName => "L0UCBYPFOUND(0)", + OutTemp => L0UCBYPFOUND_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UCBYPFOUND(1), + GlitchData => L0UCBYPFOUND1_GlitchData, + OutSignalName => "L0UCBYPFOUND(1)", + OutTemp => L0UCBYPFOUND_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UCBYPFOUND(2), + GlitchData => L0UCBYPFOUND2_GlitchData, + OutSignalName => "L0UCBYPFOUND(2)", + OutTemp => L0UCBYPFOUND_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UCBYPFOUND(3), + GlitchData => L0UCBYPFOUND3_GlitchData, + OutSignalName => "L0UCBYPFOUND(3)", + OutTemp => L0UCBYPFOUND_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UCORDFOUND(0), + GlitchData => L0UCORDFOUND0_GlitchData, + OutSignalName => "L0UCORDFOUND(0)", + OutTemp => L0UCORDFOUND_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UCORDFOUND(1), + GlitchData => L0UCORDFOUND1_GlitchData, + OutSignalName => "L0UCORDFOUND(1)", + OutTemp => L0UCORDFOUND_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UCORDFOUND(2), + GlitchData => L0UCORDFOUND2_GlitchData, + OutSignalName => "L0UCORDFOUND(2)", + OutTemp => L0UCORDFOUND_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0UCORDFOUND(3), + GlitchData => L0UCORDFOUND3_GlitchData, + OutSignalName => "L0UCORDFOUND(3)", + OutTemp => L0UCORDFOUND_OUT(3), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MCFOUND(0), + GlitchData => L0MCFOUND0_GlitchData, + OutSignalName => "L0MCFOUND(0)", + OutTemp => L0MCFOUND_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MCFOUND(1), + GlitchData => L0MCFOUND1_GlitchData, + OutSignalName => "L0MCFOUND(1)", + OutTemp => L0MCFOUND_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0MCFOUND(2), + GlitchData => L0MCFOUND2_GlitchData, + OutSignalName => "L0MCFOUND(2)", + OutTemp => L0MCFOUND_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TRANSFORMEDVC(0), + GlitchData => L0TRANSFORMEDVC0_GlitchData, + OutSignalName => "L0TRANSFORMEDVC(0)", + OutTemp => L0TRANSFORMEDVC_OUT(0), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TRANSFORMEDVC(1), + GlitchData => L0TRANSFORMEDVC1_GlitchData, + OutSignalName => "L0TRANSFORMEDVC(1)", + OutTemp => L0TRANSFORMEDVC_OUT(1), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => L0TRANSFORMEDVC(2), + GlitchData => L0TRANSFORMEDVC2_GlitchData, + OutSignalName => "L0TRANSFORMEDVC(2)", + OutTemp => L0TRANSFORMEDVC_OUT(2), + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => BUSMASTERENABLE, + GlitchData => BUSMASTERENABLE_GlitchData, + OutSignalName => "BUSMASTERENABLE", + OutTemp => BUSMASTERENABLE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => BUSMASTERENABLE, + GlitchData => BUSMASTERENABLE_GlitchData, + OutSignalName => "BUSMASTERENABLE", + OutTemp => BUSMASTERENABLE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PARITYERRORRESPONSE, + GlitchData => PARITYERRORRESPONSE_GlitchData, + OutSignalName => "PARITYERRORRESPONSE", + OutTemp => PARITYERRORRESPONSE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PARITYERRORRESPONSE, + GlitchData => PARITYERRORRESPONSE_GlitchData, + OutSignalName => "PARITYERRORRESPONSE", + OutTemp => PARITYERRORRESPONSE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => SERRENABLE, + GlitchData => SERRENABLE_GlitchData, + OutSignalName => "SERRENABLE", + OutTemp => SERRENABLE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => SERRENABLE, + GlitchData => SERRENABLE_GlitchData, + OutSignalName => "SERRENABLE", + OutTemp => SERRENABLE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => INTERRUPTDISABLE, + GlitchData => INTERRUPTDISABLE_GlitchData, + OutSignalName => "INTERRUPTDISABLE", + OutTemp => INTERRUPTDISABLE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => INTERRUPTDISABLE, + GlitchData => INTERRUPTDISABLE_GlitchData, + OutSignalName => "INTERRUPTDISABLE", + OutTemp => INTERRUPTDISABLE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => URREPORTINGENABLE, + GlitchData => URREPORTINGENABLE_GlitchData, + OutSignalName => "URREPORTINGENABLE", + OutTemp => URREPORTINGENABLE_OUT, + Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => URREPORTINGENABLE, + GlitchData => URREPORTINGENABLE_GlitchData, + OutSignalName => "URREPORTINGENABLE", + OutTemp => URREPORTINGENABLE_OUT, + Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + + wait on + BUSMASTERENABLE_out, + CRMDOHOTRESETN_out, + CRMPWRSOFTRESETN_out, + CRMRXHOTRESETN_out, + DLLTXPMDLLPOUTSTANDING_out, + INTERRUPTDISABLE_out, + IOSPACEENABLE_out, + L0ASAUTONOMOUSINITCOMPLETED_out, + L0ATTENTIONINDICATORCONTROL_out, + L0CFGLOOPBACKACK_out, + L0COMPLETERID_out, + L0CORRERRMSGRCVD_out, + L0DLLASRXSTATE_out, + L0DLLASTXSTATE_out, + L0DLLERRORVECTOR_out, + L0DLLRXACKOUTSTANDING_out, + L0DLLTXNONFCOUTSTANDING_out, + L0DLLTXOUTSTANDING_out, + L0DLLVCSTATUS_out, + L0DLUPDOWN_out, + L0ERRMSGREQID_out, + L0FATALERRMSGRCVD_out, + L0FIRSTCFGWRITEOCCURRED_out, + L0FWDCORRERROUT_out, + L0FWDFATALERROUT_out, + L0FWDNONFATALERROUT_out, + L0LTSSMSTATE_out, + L0MACENTEREDL0_out, + L0MACLINKTRAINING_out, + L0MACLINKUP_out, + L0MACNEGOTIATEDLINKWIDTH_out, + L0MACNEWSTATEACK_out, + L0MACRXL0SSTATE_out, + L0MACUPSTREAMDOWNSTREAM_out, + L0MCFOUND_out, + L0MSIENABLE0_out, + L0MULTIMSGEN0_out, + L0NONFATALERRMSGRCVD_out, + L0PMEACK_out, + L0PMEEN_out, + L0PMEREQOUT_out, + L0POWERCONTROLLERCONTROL_out, + L0POWERINDICATORCONTROL_out, + L0PWRINHIBITTRANSFERS_out, + L0PWRL1STATE_out, + L0PWRL23READYDEVICE_out, + L0PWRL23READYSTATE_out, + L0PWRSTATE0_out, + L0PWRTURNOFFREQ_out, + L0PWRTXL0SSTATE_out, + L0RECEIVEDASSERTINTALEGACYINT_out, + L0RECEIVEDASSERTINTBLEGACYINT_out, + L0RECEIVEDASSERTINTCLEGACYINT_out, + L0RECEIVEDASSERTINTDLEGACYINT_out, + L0RECEIVEDDEASSERTINTALEGACYINT_out, + L0RECEIVEDDEASSERTINTBLEGACYINT_out, + L0RECEIVEDDEASSERTINTCLEGACYINT_out, + L0RECEIVEDDEASSERTINTDLEGACYINT_out, + L0RXBEACON_out, + L0RXDLLFCCMPLMCCRED_out, + L0RXDLLFCCMPLMCUPDATE_out, + L0RXDLLFCNPOSTBYPCRED_out, + L0RXDLLFCNPOSTBYPUPDATE_out, + L0RXDLLFCPOSTORDCRED_out, + L0RXDLLFCPOSTORDUPDATE_out, + L0RXDLLPMTYPE_out, + L0RXDLLPM_out, + L0RXDLLSBFCDATA_out, + L0RXDLLSBFCUPDATE_out, + L0RXDLLTLPECRCOK_out, + L0RXDLLTLPEND_out, + L0RXMACLINKERROR_out, + L0STATSCFGOTHERRECEIVED_out, + L0STATSCFGOTHERTRANSMITTED_out, + L0STATSCFGRECEIVED_out, + L0STATSCFGTRANSMITTED_out, + L0STATSDLLPRECEIVED_out, + L0STATSDLLPTRANSMITTED_out, + L0STATSOSRECEIVED_out, + L0STATSOSTRANSMITTED_out, + L0STATSTLPRECEIVED_out, + L0STATSTLPTRANSMITTED_out, + L0TOGGLEELECTROMECHANICALINTERLOCK_out, + L0TRANSFORMEDVC_out, + L0TXDLLFCCMPLMCUPDATED_out, + L0TXDLLFCNPOSTBYPUPDATED_out, + L0TXDLLFCPOSTORDUPDATED_out, + L0TXDLLPMUPDATED_out, + L0TXDLLSBFCUPDATED_out, + L0UCBYPFOUND_out, + L0UCORDFOUND_out, + L0UNLOCKRECEIVED_out, + LLKRX4DWHEADERN_out, + LLKRXCHCOMPLETIONAVAILABLEN_out, + LLKRXCHCOMPLETIONPARTIALN_out, + LLKRXCHCONFIGAVAILABLEN_out, + LLKRXCHCONFIGPARTIALN_out, + LLKRXCHNONPOSTEDAVAILABLEN_out, + LLKRXCHNONPOSTEDPARTIALN_out, + LLKRXCHPOSTEDAVAILABLEN_out, + LLKRXCHPOSTEDPARTIALN_out, + LLKRXDATA_out, + LLKRXECRCBADN_out, + LLKRXEOFN_out, + LLKRXEOPN_out, + LLKRXPREFERREDTYPE_out, + LLKRXSOFN_out, + LLKRXSOPN_out, + LLKRXSRCDSCN_out, + LLKRXSRCLASTREQN_out, + LLKRXSRCRDYN_out, + LLKRXVALIDN_out, + LLKTCSTATUS_out, + LLKTXCHANSPACE_out, + LLKTXCHCOMPLETIONREADYN_out, + LLKTXCHNONPOSTEDREADYN_out, + LLKTXCHPOSTEDREADYN_out, + LLKTXCONFIGREADYN_out, + LLKTXDSTRDYN_out, + MAXPAYLOADSIZE_out, + MAXREADREQUESTSIZE_out, + MEMSPACEENABLE_out, + MGMTPSO_out, + MGMTRDATA_out, + MGMTSTATSCREDIT_out, + MIMDLLBRADD_out, + MIMDLLBREN_out, + MIMDLLBWADD_out, + MIMDLLBWDATA_out, + MIMDLLBWEN_out, + MIMRXBRADD_out, + MIMRXBREN_out, + MIMRXBWADD_out, + MIMRXBWDATA_out, + MIMRXBWEN_out, + MIMTXBRADD_out, + MIMTXBREN_out, + MIMTXBWADD_out, + MIMTXBWDATA_out, + MIMTXBWEN_out, + PARITYERRORRESPONSE_out, + PIPEDESKEWLANESL0_out, + PIPEDESKEWLANESL1_out, + PIPEDESKEWLANESL2_out, + PIPEDESKEWLANESL3_out, + PIPEDESKEWLANESL4_out, + PIPEDESKEWLANESL5_out, + PIPEDESKEWLANESL6_out, + PIPEDESKEWLANESL7_out, + PIPEPOWERDOWNL0_out, + PIPEPOWERDOWNL1_out, + PIPEPOWERDOWNL2_out, + PIPEPOWERDOWNL3_out, + PIPEPOWERDOWNL4_out, + PIPEPOWERDOWNL5_out, + PIPEPOWERDOWNL6_out, + PIPEPOWERDOWNL7_out, + PIPERESETL0_out, + PIPERESETL1_out, + PIPERESETL2_out, + PIPERESETL3_out, + PIPERESETL4_out, + PIPERESETL5_out, + PIPERESETL6_out, + PIPERESETL7_out, + PIPERXPOLARITYL0_out, + PIPERXPOLARITYL1_out, + PIPERXPOLARITYL2_out, + PIPERXPOLARITYL3_out, + PIPERXPOLARITYL4_out, + PIPERXPOLARITYL5_out, + PIPERXPOLARITYL6_out, + PIPERXPOLARITYL7_out, + PIPETXCOMPLIANCEL0_out, + PIPETXCOMPLIANCEL1_out, + PIPETXCOMPLIANCEL2_out, + PIPETXCOMPLIANCEL3_out, + PIPETXCOMPLIANCEL4_out, + PIPETXCOMPLIANCEL5_out, + PIPETXCOMPLIANCEL6_out, + PIPETXCOMPLIANCEL7_out, + PIPETXDATAKL0_out, + PIPETXDATAKL1_out, + PIPETXDATAKL2_out, + PIPETXDATAKL3_out, + PIPETXDATAKL4_out, + PIPETXDATAKL5_out, + PIPETXDATAKL6_out, + PIPETXDATAKL7_out, + PIPETXDATAL0_out, + PIPETXDATAL1_out, + PIPETXDATAL2_out, + PIPETXDATAL3_out, + PIPETXDATAL4_out, + PIPETXDATAL5_out, + PIPETXDATAL6_out, + PIPETXDATAL7_out, + PIPETXDETECTRXLOOPBACKL0_out, + PIPETXDETECTRXLOOPBACKL1_out, + PIPETXDETECTRXLOOPBACKL2_out, + PIPETXDETECTRXLOOPBACKL3_out, + PIPETXDETECTRXLOOPBACKL4_out, + PIPETXDETECTRXLOOPBACKL5_out, + PIPETXDETECTRXLOOPBACKL6_out, + PIPETXDETECTRXLOOPBACKL7_out, + PIPETXELECIDLEL0_out, + PIPETXELECIDLEL1_out, + PIPETXELECIDLEL2_out, + PIPETXELECIDLEL3_out, + PIPETXELECIDLEL4_out, + PIPETXELECIDLEL5_out, + PIPETXELECIDLEL6_out, + PIPETXELECIDLEL7_out, + SERRENABLE_out, + URREPORTINGENABLE_out, + + AUXPOWER_ipd, + CFGNEGOTIATEDLINKWIDTH_ipd, + COMPLIANCEAVOID_ipd, + CRMCFGBRIDGEHOTRESET_ipd, + CRMCORECLKDLO_ipd, + CRMCORECLKRXO_ipd, + CRMCORECLKTXO_ipd, + CRMCORECLK_ipd, + CRMLINKRSTN_ipd, + CRMMACRSTN_ipd, + CRMMGMTRSTN_ipd, + CRMNVRSTN_ipd, + CRMTXHOTRESETN_ipd, + CRMURSTN_ipd, + CRMUSERCFGRSTN_ipd, + CRMUSERCLKRXO_ipd, + CRMUSERCLKTXO_ipd, + CRMUSERCLK_ipd, + CROSSLINKSEED_ipd, + L0ACKNAKTIMERADJUSTMENT_ipd, + L0ALLDOWNPORTSINL1_ipd, + L0ALLDOWNRXPORTSINL0S_ipd, + L0ASE_ipd, + L0ASPORTCOUNT_ipd, + L0ASTURNPOOLBITSCONSUMED_ipd, + L0ATTENTIONBUTTONPRESSED_ipd, + L0CFGASSPANTREEOWNEDSTATE_ipd, + L0CFGASSTATECHANGECMD_ipd, + L0CFGDISABLESCRAMBLE_ipd, + L0CFGEXTENDEDSYNC_ipd, + L0CFGL0SENTRYENABLE_ipd, + L0CFGL0SENTRYSUP_ipd, + L0CFGL0SEXITLAT_ipd, + L0CFGLINKDISABLE_ipd, + L0CFGLOOPBACKMASTER_ipd, + L0CFGNEGOTIATEDMAXP_ipd, + L0CFGVCENABLE_ipd, + L0CFGVCID_ipd, + L0DLLHOLDLINKUP_ipd, + L0ELECTROMECHANICALINTERLOCKENGAGED_ipd, + L0FWDASSERTINTALEGACYINT_ipd, + L0FWDASSERTINTBLEGACYINT_ipd, + L0FWDASSERTINTCLEGACYINT_ipd, + L0FWDASSERTINTDLEGACYINT_ipd, + L0FWDCORRERRIN_ipd, + L0FWDDEASSERTINTALEGACYINT_ipd, + L0FWDDEASSERTINTBLEGACYINT_ipd, + L0FWDDEASSERTINTCLEGACYINT_ipd, + L0FWDDEASSERTINTDLEGACYINT_ipd, + L0FWDFATALERRIN_ipd, + L0FWDNONFATALERRIN_ipd, + L0LEGACYINTFUNCT0_ipd, + L0MRLSENSORCLOSEDN_ipd, + L0MSIREQUEST0_ipd, + L0PACKETHEADERFROMUSER_ipd, + L0PMEREQIN_ipd, + L0PORTNUMBER_ipd, + L0POWERFAULTDETECTED_ipd, + L0PRESENCEDETECTSLOTEMPTYN_ipd, + L0PWRNEWSTATEREQ_ipd, + L0PWRNEXTLINKSTATE_ipd, + L0REPLAYTIMERADJUSTMENT_ipd, + L0ROOTTURNOFFREQ_ipd, + L0RXTLTLPNONINITIALIZEDVC_ipd, + L0SENDUNLOCKMESSAGE_ipd, + L0SETCOMPLETERABORTERROR_ipd, + L0SETCOMPLETIONTIMEOUTCORRERROR_ipd, + L0SETCOMPLETIONTIMEOUTUNCORRERROR_ipd, + L0SETDETECTEDCORRERROR_ipd, + L0SETDETECTEDFATALERROR_ipd, + L0SETDETECTEDNONFATALERROR_ipd, + L0SETLINKDETECTEDPARITYERROR_ipd, + L0SETLINKMASTERDATAPARITY_ipd, + L0SETLINKRECEIVEDMASTERABORT_ipd, + L0SETLINKRECEIVEDTARGETABORT_ipd, + L0SETLINKSIGNALLEDTARGETABORT_ipd, + L0SETLINKSYSTEMERROR_ipd, + L0SETUNEXPECTEDCOMPLETIONCORRERROR_ipd, + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_ipd, + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_ipd, + L0SETUNSUPPORTEDREQUESTOTHERERROR_ipd, + L0SETUSERDETECTEDPARITYERROR_ipd, + L0SETUSERMASTERDATAPARITY_ipd, + L0SETUSERRECEIVEDMASTERABORT_ipd, + L0SETUSERRECEIVEDTARGETABORT_ipd, + L0SETUSERSIGNALLEDTARGETABORT_ipd, + L0SETUSERSYSTEMERROR_ipd, + L0TLASFCCREDSTARVATION_ipd, + L0TLLINKRETRAIN_ipd, + L0TRANSACTIONSPENDING_ipd, + L0TXBEACON_ipd, + L0TXCFGPMTYPE_ipd, + L0TXCFGPM_ipd, + L0TXTLFCCMPLMCCRED_ipd, + L0TXTLFCCMPLMCUPDATE_ipd, + L0TXTLFCNPOSTBYPCRED_ipd, + L0TXTLFCNPOSTBYPUPDATE_ipd, + L0TXTLFCPOSTORDCRED_ipd, + L0TXTLFCPOSTORDUPDATE_ipd, + L0TXTLSBFCDATA_ipd, + L0TXTLSBFCUPDATE_ipd, + L0TXTLTLPDATA_ipd, + L0TXTLTLPEDB_ipd, + L0TXTLTLPENABLE_ipd, + L0TXTLTLPEND_ipd, + L0TXTLTLPLATENCY_ipd, + L0TXTLTLPREQEND_ipd, + L0TXTLTLPREQ_ipd, + L0TXTLTLPWIDTH_ipd, + L0UPSTREAMRXPORTINL0S_ipd, + L0VC0PREVIEWEXPAND_ipd, + L0WAKEN_ipd, + LLKRXCHFIFO_ipd, + LLKRXCHTC_ipd, + LLKRXDSTCONTREQN_ipd, + LLKRXDSTREQN_ipd, + LLKTX4DWHEADERN_ipd, + LLKTXCHFIFO_ipd, + LLKTXCHTC_ipd, + LLKTXCOMPLETEN_ipd, + LLKTXCREATEECRCN_ipd, + LLKTXDATA_ipd, + LLKTXENABLEN_ipd, + LLKTXEOFN_ipd, + LLKTXEOPN_ipd, + LLKTXSOFN_ipd, + LLKTXSOPN_ipd, + LLKTXSRCDSCN_ipd, + LLKTXSRCRDYN_ipd, + MAINPOWER_ipd, + MGMTADDR_ipd, + MGMTBWREN_ipd, + MGMTRDEN_ipd, + MGMTSTATSCREDITSEL_ipd, + MGMTWDATA_ipd, + MGMTWREN_ipd, + MIMDLLBRDATA_ipd, + MIMRXBRDATA_ipd, + MIMTXBRDATA_ipd, + PIPEPHYSTATUSL0_ipd, + PIPEPHYSTATUSL1_ipd, + PIPEPHYSTATUSL2_ipd, + PIPEPHYSTATUSL3_ipd, + PIPEPHYSTATUSL4_ipd, + PIPEPHYSTATUSL5_ipd, + PIPEPHYSTATUSL6_ipd, + PIPEPHYSTATUSL7_ipd, + PIPERXCHANISALIGNEDL0_ipd, + PIPERXCHANISALIGNEDL1_ipd, + PIPERXCHANISALIGNEDL2_ipd, + PIPERXCHANISALIGNEDL3_ipd, + PIPERXCHANISALIGNEDL4_ipd, + PIPERXCHANISALIGNEDL5_ipd, + PIPERXCHANISALIGNEDL6_ipd, + PIPERXCHANISALIGNEDL7_ipd, + PIPERXDATAKL0_ipd, + PIPERXDATAKL1_ipd, + PIPERXDATAKL2_ipd, + PIPERXDATAKL3_ipd, + PIPERXDATAKL4_ipd, + PIPERXDATAKL5_ipd, + PIPERXDATAKL6_ipd, + PIPERXDATAKL7_ipd, + PIPERXDATAL0_ipd, + PIPERXDATAL1_ipd, + PIPERXDATAL2_ipd, + PIPERXDATAL3_ipd, + PIPERXDATAL4_ipd, + PIPERXDATAL5_ipd, + PIPERXDATAL6_ipd, + PIPERXDATAL7_ipd, + PIPERXELECIDLEL0_ipd, + PIPERXELECIDLEL1_ipd, + PIPERXELECIDLEL2_ipd, + PIPERXELECIDLEL3_ipd, + PIPERXELECIDLEL4_ipd, + PIPERXELECIDLEL5_ipd, + PIPERXELECIDLEL6_ipd, + PIPERXELECIDLEL7_ipd, + PIPERXSTATUSL0_ipd, + PIPERXSTATUSL1_ipd, + PIPERXSTATUSL2_ipd, + PIPERXSTATUSL3_ipd, + PIPERXSTATUSL4_ipd, + PIPERXSTATUSL5_ipd, + PIPERXSTATUSL6_ipd, + PIPERXSTATUSL7_ipd, + PIPERXVALIDL0_ipd, + PIPERXVALIDL1_ipd, + PIPERXVALIDL2_ipd, + PIPERXVALIDL3_ipd, + PIPERXVALIDL4_ipd, + PIPERXVALIDL5_ipd, + PIPERXVALIDL6_ipd, + PIPERXVALIDL7_ipd; + + end process TIMING; + + +end PCIE_INTERNAL_1_1_V; +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2006 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / Tri-Mode Ethernet MAC +-- /___/ /\ Filename : temac.vhd +-- \ \ / \ Timestamp : Thu Dec 8 2005 +-- \___\/\___\ +-- +-- Revision: +-- 12/08/05 - Initial version. +-- 01/09/06 - Added architecture +-- 02/06/06 - pinTime updates +-- 02/23/06 - Updated Header +-- 03/10/06 - CR#226740. Changed generic type of some of the generics from +-- string to boolean +-- 03/27/06 - Updated TEMAC smartmodel to version number 00.002 for following changes +-- CR#224695 - +-- 1. TEMAC smartmodel 16 bit client interface problem. +-- 2. Compiled smartmodel with `delay_mode_zero directive +-- CR#226083 - +-- 1. Loopback attributes don't work in Verilog TEMAC smartmodel. +-- CR#224695 - +-- 1 . Added 50 ps input delay to all inputs(except clocks) going into temac swift model +-- 04/11/06 - CR#228762 - Added some missing path delays to timing block. +-- 04/27/06 - CR#230105 - Fixed connectivity for CLK +-- 05/23/06 - CR#231962 - Add buffers for connectivity +-- 09/15/06 - CR#423162 - Timing updates +-- 10/26/06 - - replaced ZERO_DELAY with CLK_DELAY to be consistent with writers (PPC440 update) +-- 06/08/07 - CR#440717 - Add constant EMAC0MIITXCLK_DELAY & EMAC1MIITXCLK_DELAY +-- 08/28/07 - CR#447575 - Path Delay updates due to pinDev/pinTime updates +-- End Revision + + +----- CELL TEMAC ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity TEMAC is +generic ( + EMAC0_1000BASEX_ENABLE : boolean := FALSE; + EMAC0_ADDRFILTER_ENABLE : boolean := FALSE; + EMAC0_BYTEPHY : boolean := FALSE; + EMAC0_CONFIGVEC_79 : boolean := FALSE; + EMAC0_DCRBASEADDR : bit_vector := X"00"; + EMAC0_GTLOOPBACK : boolean := FALSE; + EMAC0_HOST_ENABLE : boolean := FALSE; + EMAC0_LINKTIMERVAL : bit_vector := X"000"; + EMAC0_LTCHECK_DISABLE : boolean := FALSE; + EMAC0_MDIO_ENABLE : boolean := FALSE; + EMAC0_PAUSEADDR : bit_vector := X"000000000000"; + EMAC0_PHYINITAUTONEG_ENABLE : boolean := FALSE; + EMAC0_PHYISOLATE : boolean := FALSE; + EMAC0_PHYLOOPBACKMSB : boolean := FALSE; + EMAC0_PHYPOWERDOWN : boolean := FALSE; + EMAC0_PHYRESET : boolean := FALSE; + EMAC0_RGMII_ENABLE : boolean := FALSE; + EMAC0_RX16BITCLIENT_ENABLE : boolean := FALSE; + EMAC0_RXFLOWCTRL_ENABLE : boolean := FALSE; + EMAC0_RXHALFDUPLEX : boolean := FALSE; + EMAC0_RXINBANDFCS_ENABLE : boolean := FALSE; + EMAC0_RXJUMBOFRAME_ENABLE : boolean := FALSE; + EMAC0_RXRESET : boolean := FALSE; + EMAC0_RXVLAN_ENABLE : boolean := FALSE; + EMAC0_RX_ENABLE : boolean := FALSE; + EMAC0_SGMII_ENABLE : boolean := FALSE; + EMAC0_SPEED_LSB : boolean := FALSE; + EMAC0_SPEED_MSB : boolean := FALSE; + EMAC0_TX16BITCLIENT_ENABLE : boolean := FALSE; + EMAC0_TXFLOWCTRL_ENABLE : boolean := FALSE; + EMAC0_TXHALFDUPLEX : boolean := FALSE; + EMAC0_TXIFGADJUST_ENABLE : boolean := FALSE; + EMAC0_TXINBANDFCS_ENABLE : boolean := FALSE; + EMAC0_TXJUMBOFRAME_ENABLE : boolean := FALSE; + EMAC0_TXRESET : boolean := FALSE; + EMAC0_TXVLAN_ENABLE : boolean := FALSE; + EMAC0_TX_ENABLE : boolean := FALSE; + EMAC0_UNICASTADDR : bit_vector := X"000000000000"; + EMAC0_UNIDIRECTION_ENABLE : boolean := FALSE; + EMAC0_USECLKEN : boolean := FALSE; + EMAC1_1000BASEX_ENABLE : boolean := FALSE; + EMAC1_ADDRFILTER_ENABLE : boolean := FALSE; + EMAC1_BYTEPHY : boolean := FALSE; + EMAC1_CONFIGVEC_79 : boolean := FALSE; + EMAC1_DCRBASEADDR : bit_vector := X"00"; + EMAC1_GTLOOPBACK : boolean := FALSE; + EMAC1_HOST_ENABLE : boolean := FALSE; + EMAC1_LINKTIMERVAL : bit_vector := X"000"; + EMAC1_LTCHECK_DISABLE : boolean := FALSE; + EMAC1_MDIO_ENABLE : boolean := FALSE; + EMAC1_PAUSEADDR : bit_vector := X"000000000000"; + EMAC1_PHYINITAUTONEG_ENABLE : boolean := FALSE; + EMAC1_PHYISOLATE : boolean := FALSE; + EMAC1_PHYLOOPBACKMSB : boolean := FALSE; + EMAC1_PHYPOWERDOWN : boolean := FALSE; + EMAC1_PHYRESET : boolean := FALSE; + EMAC1_RGMII_ENABLE : boolean := FALSE; + EMAC1_RX16BITCLIENT_ENABLE : boolean := FALSE; + EMAC1_RXFLOWCTRL_ENABLE : boolean := FALSE; + EMAC1_RXHALFDUPLEX : boolean := FALSE; + EMAC1_RXINBANDFCS_ENABLE : boolean := FALSE; + EMAC1_RXJUMBOFRAME_ENABLE : boolean := FALSE; + EMAC1_RXRESET : boolean := FALSE; + EMAC1_RXVLAN_ENABLE : boolean := FALSE; + EMAC1_RX_ENABLE : boolean := FALSE; + EMAC1_SGMII_ENABLE : boolean := FALSE; + EMAC1_SPEED_LSB : boolean := FALSE; + EMAC1_SPEED_MSB : boolean := FALSE; + EMAC1_TX16BITCLIENT_ENABLE : boolean := FALSE; + EMAC1_TXFLOWCTRL_ENABLE : boolean := FALSE; + EMAC1_TXHALFDUPLEX : boolean := FALSE; + EMAC1_TXIFGADJUST_ENABLE : boolean := FALSE; + EMAC1_TXINBANDFCS_ENABLE : boolean := FALSE; + EMAC1_TXJUMBOFRAME_ENABLE : boolean := FALSE; + EMAC1_TXRESET : boolean := FALSE; + EMAC1_TXVLAN_ENABLE : boolean := FALSE; + EMAC1_TX_ENABLE : boolean := FALSE; + EMAC1_UNICASTADDR : bit_vector := X"000000000000"; + EMAC1_UNIDIRECTION_ENABLE : boolean := FALSE; + EMAC1_USECLKEN : boolean := FALSE + ); + +port ( + DCRHOSTDONEIR : out std_ulogic; + EMAC0CLIENTANINTERRUPT : out std_ulogic; + EMAC0CLIENTRXBADFRAME : out std_ulogic; + EMAC0CLIENTRXCLIENTCLKOUT : out std_ulogic; + EMAC0CLIENTRXD : out std_logic_vector(15 downto 0); + EMAC0CLIENTRXDVLD : out std_ulogic; + EMAC0CLIENTRXDVLDMSW : out std_ulogic; + EMAC0CLIENTRXFRAMEDROP : out std_ulogic; + EMAC0CLIENTRXGOODFRAME : out std_ulogic; + EMAC0CLIENTRXSTATS : out std_logic_vector(6 downto 0); + EMAC0CLIENTRXSTATSBYTEVLD : out std_ulogic; + EMAC0CLIENTRXSTATSVLD : out std_ulogic; + EMAC0CLIENTTXACK : out std_ulogic; + EMAC0CLIENTTXCLIENTCLKOUT : out std_ulogic; + EMAC0CLIENTTXCOLLISION : out std_ulogic; + EMAC0CLIENTTXRETRANSMIT : out std_ulogic; + EMAC0CLIENTTXSTATS : out std_ulogic; + EMAC0CLIENTTXSTATSBYTEVLD : out std_ulogic; + EMAC0CLIENTTXSTATSVLD : out std_ulogic; + EMAC0PHYENCOMMAALIGN : out std_ulogic; + EMAC0PHYLOOPBACKMSB : out std_ulogic; + EMAC0PHYMCLKOUT : out std_ulogic; + EMAC0PHYMDOUT : out std_ulogic; + EMAC0PHYMDTRI : out std_ulogic; + EMAC0PHYMGTRXRESET : out std_ulogic; + EMAC0PHYMGTTXRESET : out std_ulogic; + EMAC0PHYPOWERDOWN : out std_ulogic; + EMAC0PHYSYNCACQSTATUS : out std_ulogic; + EMAC0PHYTXCHARDISPMODE : out std_ulogic; + EMAC0PHYTXCHARDISPVAL : out std_ulogic; + EMAC0PHYTXCHARISK : out std_ulogic; + EMAC0PHYTXCLK : out std_ulogic; + EMAC0PHYTXD : out std_logic_vector(7 downto 0); + EMAC0PHYTXEN : out std_ulogic; + EMAC0PHYTXER : out std_ulogic; + EMAC0PHYTXGMIIMIICLKOUT : out std_ulogic; + EMAC0SPEEDIS10100 : out std_ulogic; + EMAC1CLIENTANINTERRUPT : out std_ulogic; + EMAC1CLIENTRXBADFRAME : out std_ulogic; + EMAC1CLIENTRXCLIENTCLKOUT : out std_ulogic; + EMAC1CLIENTRXD : out std_logic_vector(15 downto 0); + EMAC1CLIENTRXDVLD : out std_ulogic; + EMAC1CLIENTRXDVLDMSW : out std_ulogic; + EMAC1CLIENTRXFRAMEDROP : out std_ulogic; + EMAC1CLIENTRXGOODFRAME : out std_ulogic; + EMAC1CLIENTRXSTATS : out std_logic_vector(6 downto 0); + EMAC1CLIENTRXSTATSBYTEVLD : out std_ulogic; + EMAC1CLIENTRXSTATSVLD : out std_ulogic; + EMAC1CLIENTTXACK : out std_ulogic; + EMAC1CLIENTTXCLIENTCLKOUT : out std_ulogic; + EMAC1CLIENTTXCOLLISION : out std_ulogic; + EMAC1CLIENTTXRETRANSMIT : out std_ulogic; + EMAC1CLIENTTXSTATS : out std_ulogic; + EMAC1CLIENTTXSTATSBYTEVLD : out std_ulogic; + EMAC1CLIENTTXSTATSVLD : out std_ulogic; + EMAC1PHYENCOMMAALIGN : out std_ulogic; + EMAC1PHYLOOPBACKMSB : out std_ulogic; + EMAC1PHYMCLKOUT : out std_ulogic; + EMAC1PHYMDOUT : out std_ulogic; + EMAC1PHYMDTRI : out std_ulogic; + EMAC1PHYMGTRXRESET : out std_ulogic; + EMAC1PHYMGTTXRESET : out std_ulogic; + EMAC1PHYPOWERDOWN : out std_ulogic; + EMAC1PHYSYNCACQSTATUS : out std_ulogic; + EMAC1PHYTXCHARDISPMODE : out std_ulogic; + EMAC1PHYTXCHARDISPVAL : out std_ulogic; + EMAC1PHYTXCHARISK : out std_ulogic; + EMAC1PHYTXCLK : out std_ulogic; + EMAC1PHYTXD : out std_logic_vector(7 downto 0); + EMAC1PHYTXEN : out std_ulogic; + EMAC1PHYTXER : out std_ulogic; + EMAC1PHYTXGMIIMIICLKOUT : out std_ulogic; + EMAC1SPEEDIS10100 : out std_ulogic; + EMACDCRACK : out std_ulogic; + EMACDCRDBUS : out std_logic_vector(0 to 31); + HOSTMIIMRDY : out std_ulogic; + HOSTRDDATA : out std_logic_vector(31 downto 0); + + CLIENTEMAC0DCMLOCKED : in std_ulogic; + CLIENTEMAC0PAUSEREQ : in std_ulogic; + CLIENTEMAC0PAUSEVAL : in std_logic_vector(15 downto 0); + CLIENTEMAC0RXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC0TXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC0TXD : in std_logic_vector(15 downto 0); + CLIENTEMAC0TXDVLD : in std_ulogic; + CLIENTEMAC0TXDVLDMSW : in std_ulogic; + CLIENTEMAC0TXFIRSTBYTE : in std_ulogic; + CLIENTEMAC0TXIFGDELAY : in std_logic_vector(7 downto 0); + CLIENTEMAC0TXUNDERRUN : in std_ulogic; + CLIENTEMAC1DCMLOCKED : in std_ulogic; + CLIENTEMAC1PAUSEREQ : in std_ulogic; + CLIENTEMAC1PAUSEVAL : in std_logic_vector(15 downto 0); + CLIENTEMAC1RXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC1TXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC1TXD : in std_logic_vector(15 downto 0); + CLIENTEMAC1TXDVLD : in std_ulogic; + CLIENTEMAC1TXDVLDMSW : in std_ulogic; + CLIENTEMAC1TXFIRSTBYTE : in std_ulogic; + CLIENTEMAC1TXIFGDELAY : in std_logic_vector(7 downto 0); + CLIENTEMAC1TXUNDERRUN : in std_ulogic; + DCREMACABUS : in std_logic_vector(0 to 9); + DCREMACCLK : in std_ulogic; + DCREMACDBUS : in std_logic_vector(0 to 31); + DCREMACENABLE : in std_ulogic; + DCREMACREAD : in std_ulogic; + DCREMACWRITE : in std_ulogic; + HOSTADDR : in std_logic_vector(9 downto 0); + HOSTCLK : in std_ulogic; + HOSTEMAC1SEL : in std_ulogic; + HOSTMIIMSEL : in std_ulogic; + HOSTOPCODE : in std_logic_vector(1 downto 0); + HOSTREQ : in std_ulogic; + HOSTWRDATA : in std_logic_vector(31 downto 0); + PHYEMAC0COL : in std_ulogic; + PHYEMAC0CRS : in std_ulogic; + PHYEMAC0GTXCLK : in std_ulogic; + PHYEMAC0MCLKIN : in std_ulogic; + PHYEMAC0MDIN : in std_ulogic; + PHYEMAC0MIITXCLK : in std_ulogic; + PHYEMAC0PHYAD : in std_logic_vector(4 downto 0); + PHYEMAC0RXBUFERR : in std_ulogic; + PHYEMAC0RXBUFSTATUS : in std_logic_vector(1 downto 0); + PHYEMAC0RXCHARISCOMMA : in std_ulogic; + PHYEMAC0RXCHARISK : in std_ulogic; + PHYEMAC0RXCHECKINGCRC : in std_ulogic; + PHYEMAC0RXCLK : in std_ulogic; + PHYEMAC0RXCLKCORCNT : in std_logic_vector(2 downto 0); + PHYEMAC0RXCOMMADET : in std_ulogic; + PHYEMAC0RXD : in std_logic_vector(7 downto 0); + PHYEMAC0RXDISPERR : in std_ulogic; + PHYEMAC0RXDV : in std_ulogic; + PHYEMAC0RXER : in std_ulogic; + PHYEMAC0RXLOSSOFSYNC : in std_logic_vector(1 downto 0); + PHYEMAC0RXNOTINTABLE : in std_ulogic; + PHYEMAC0RXRUNDISP : in std_ulogic; + PHYEMAC0SIGNALDET : in std_ulogic; + PHYEMAC0TXBUFERR : in std_ulogic; + PHYEMAC0TXGMIIMIICLKIN : in std_ulogic; + PHYEMAC1COL : in std_ulogic; + PHYEMAC1CRS : in std_ulogic; + PHYEMAC1GTXCLK : in std_ulogic; + PHYEMAC1MCLKIN : in std_ulogic; + PHYEMAC1MDIN : in std_ulogic; + PHYEMAC1MIITXCLK : in std_ulogic; + PHYEMAC1PHYAD : in std_logic_vector(4 downto 0); + PHYEMAC1RXBUFERR : in std_ulogic; + PHYEMAC1RXBUFSTATUS : in std_logic_vector(1 downto 0); + PHYEMAC1RXCHARISCOMMA : in std_ulogic; + PHYEMAC1RXCHARISK : in std_ulogic; + PHYEMAC1RXCHECKINGCRC : in std_ulogic; + PHYEMAC1RXCLK : in std_ulogic; + PHYEMAC1RXCLKCORCNT : in std_logic_vector(2 downto 0); + PHYEMAC1RXCOMMADET : in std_ulogic; + PHYEMAC1RXD : in std_logic_vector(7 downto 0); + PHYEMAC1RXDISPERR : in std_ulogic; + PHYEMAC1RXDV : in std_ulogic; + PHYEMAC1RXER : in std_ulogic; + PHYEMAC1RXLOSSOFSYNC : in std_logic_vector(1 downto 0); + PHYEMAC1RXNOTINTABLE : in std_ulogic; + PHYEMAC1RXRUNDISP : in std_ulogic; + PHYEMAC1SIGNALDET : in std_ulogic; + PHYEMAC1TXBUFERR : in std_ulogic; + PHYEMAC1TXGMIIMIICLKIN : in std_ulogic; + RESET : in std_ulogic + ); +end TEMAC; + +architecture TEMAC_V of TEMAC is + + + + component TEMAC_SWIFT_BUS + port ( + DCRHOSTDONEIR : out std_ulogic; + EMAC0CLIENTANINTERRUPT : out std_ulogic; + EMAC0CLIENTRXBADFRAME : out std_ulogic; + EMAC0CLIENTRXCLIENTCLKOUT : out std_ulogic; + EMAC0CLIENTRXD : out std_logic_vector(15 downto 0); + EMAC0CLIENTRXDVLD : out std_ulogic; + EMAC0CLIENTRXDVLDMSW : out std_ulogic; + EMAC0CLIENTRXFRAMEDROP : out std_ulogic; + EMAC0CLIENTRXGOODFRAME : out std_ulogic; + EMAC0CLIENTRXSTATS : out std_logic_vector(6 downto 0); + EMAC0CLIENTRXSTATSBYTEVLD : out std_ulogic; + EMAC0CLIENTRXSTATSVLD : out std_ulogic; + EMAC0CLIENTTXACK : out std_ulogic; + EMAC0CLIENTTXCLIENTCLKOUT : out std_ulogic; + EMAC0CLIENTTXCOLLISION : out std_ulogic; + EMAC0CLIENTTXRETRANSMIT : out std_ulogic; + EMAC0CLIENTTXSTATS : out std_ulogic; + EMAC0CLIENTTXSTATSBYTEVLD : out std_ulogic; + EMAC0CLIENTTXSTATSVLD : out std_ulogic; + EMAC0PHYENCOMMAALIGN : out std_ulogic; + EMAC0PHYLOOPBACKMSB : out std_ulogic; + EMAC0PHYMCLKOUT : out std_ulogic; + EMAC0PHYMDOUT : out std_ulogic; + EMAC0PHYMDTRI : out std_ulogic; + EMAC0PHYMGTRXRESET : out std_ulogic; + EMAC0PHYMGTTXRESET : out std_ulogic; + EMAC0PHYPOWERDOWN : out std_ulogic; + EMAC0PHYSYNCACQSTATUS : out std_ulogic; + EMAC0PHYTXCHARDISPMODE : out std_ulogic; + EMAC0PHYTXCHARDISPVAL : out std_ulogic; + EMAC0PHYTXCHARISK : out std_ulogic; + EMAC0PHYTXCLK : out std_ulogic; + EMAC0PHYTXD : out std_logic_vector(7 downto 0); + EMAC0PHYTXEN : out std_ulogic; + EMAC0PHYTXER : out std_ulogic; + EMAC0PHYTXGMIIMIICLKOUT : out std_ulogic; + EMAC0SPEEDIS10100 : out std_ulogic; + EMAC1CLIENTANINTERRUPT : out std_ulogic; + EMAC1CLIENTRXBADFRAME : out std_ulogic; + EMAC1CLIENTRXCLIENTCLKOUT : out std_ulogic; + EMAC1CLIENTRXD : out std_logic_vector(15 downto 0); + EMAC1CLIENTRXDVLD : out std_ulogic; + EMAC1CLIENTRXDVLDMSW : out std_ulogic; + EMAC1CLIENTRXFRAMEDROP : out std_ulogic; + EMAC1CLIENTRXGOODFRAME : out std_ulogic; + EMAC1CLIENTRXSTATS : out std_logic_vector(6 downto 0); + EMAC1CLIENTRXSTATSBYTEVLD : out std_ulogic; + EMAC1CLIENTRXSTATSVLD : out std_ulogic; + EMAC1CLIENTTXACK : out std_ulogic; + EMAC1CLIENTTXCLIENTCLKOUT : out std_ulogic; + EMAC1CLIENTTXCOLLISION : out std_ulogic; + EMAC1CLIENTTXRETRANSMIT : out std_ulogic; + EMAC1CLIENTTXSTATS : out std_ulogic; + EMAC1CLIENTTXSTATSBYTEVLD : out std_ulogic; + EMAC1CLIENTTXSTATSVLD : out std_ulogic; + EMAC1PHYENCOMMAALIGN : out std_ulogic; + EMAC1PHYLOOPBACKMSB : out std_ulogic; + EMAC1PHYMCLKOUT : out std_ulogic; + EMAC1PHYMDOUT : out std_ulogic; + EMAC1PHYMDTRI : out std_ulogic; + EMAC1PHYMGTRXRESET : out std_ulogic; + EMAC1PHYMGTTXRESET : out std_ulogic; + EMAC1PHYPOWERDOWN : out std_ulogic; + EMAC1PHYSYNCACQSTATUS : out std_ulogic; + EMAC1PHYTXCHARDISPMODE : out std_ulogic; + EMAC1PHYTXCHARDISPVAL : out std_ulogic; + EMAC1PHYTXCHARISK : out std_ulogic; + EMAC1PHYTXCLK : out std_ulogic; + EMAC1PHYTXD : out std_logic_vector(7 downto 0); + EMAC1PHYTXEN : out std_ulogic; + EMAC1PHYTXER : out std_ulogic; + EMAC1PHYTXGMIIMIICLKOUT : out std_ulogic; + EMAC1SPEEDIS10100 : out std_ulogic; + EMACDCRACK : out std_ulogic; + EMACDCRDBUS : out std_logic_vector(0 to 31); + HOSTMIIMRDY : out std_ulogic; + HOSTRDDATA : out std_logic_vector(31 downto 0); + + CLIENTEMAC0DCMLOCKED : in std_ulogic; + CLIENTEMAC0PAUSEREQ : in std_ulogic; + CLIENTEMAC0PAUSEVAL : in std_logic_vector(15 downto 0); + CLIENTEMAC0RXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC0TXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC0TXD : in std_logic_vector(15 downto 0); + CLIENTEMAC0TXDVLD : in std_ulogic; + CLIENTEMAC0TXDVLDMSW : in std_ulogic; + CLIENTEMAC0TXFIRSTBYTE : in std_ulogic; + CLIENTEMAC0TXIFGDELAY : in std_logic_vector(7 downto 0); + CLIENTEMAC0TXUNDERRUN : in std_ulogic; + CLIENTEMAC1DCMLOCKED : in std_ulogic; + CLIENTEMAC1PAUSEREQ : in std_ulogic; + CLIENTEMAC1PAUSEVAL : in std_logic_vector(15 downto 0); + CLIENTEMAC1RXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC1TXCLIENTCLKIN : in std_ulogic; + CLIENTEMAC1TXD : in std_logic_vector(15 downto 0); + CLIENTEMAC1TXDVLD : in std_ulogic; + CLIENTEMAC1TXDVLDMSW : in std_ulogic; + CLIENTEMAC1TXFIRSTBYTE : in std_ulogic; + CLIENTEMAC1TXIFGDELAY : in std_logic_vector(7 downto 0); + CLIENTEMAC1TXUNDERRUN : in std_ulogic; + DCREMACABUS : in std_logic_vector(0 to 9); + DCREMACCLK : in std_ulogic; + DCREMACDBUS : in std_logic_vector(0 to 31); + DCREMACENABLE : in std_ulogic; + DCREMACREAD : in std_ulogic; + DCREMACWRITE : in std_ulogic; + HOSTADDR : in std_logic_vector(9 downto 0); + HOSTCLK : in std_ulogic; + HOSTEMAC1SEL : in std_ulogic; + HOSTMIIMSEL : in std_ulogic; + HOSTOPCODE : in std_logic_vector(1 downto 0); + HOSTREQ : in std_ulogic; + HOSTWRDATA : in std_logic_vector(31 downto 0); + PHYEMAC0COL : in std_ulogic; + PHYEMAC0CRS : in std_ulogic; + PHYEMAC0GTXCLK : in std_ulogic; + PHYEMAC0MCLKIN : in std_ulogic; + PHYEMAC0MDIN : in std_ulogic; + PHYEMAC0MIITXCLK : in std_ulogic; + PHYEMAC0PHYAD : in std_logic_vector(4 downto 0); + PHYEMAC0RXBUFERR : in std_ulogic; + PHYEMAC0RXBUFSTATUS : in std_logic_vector(1 downto 0); + PHYEMAC0RXCHARISCOMMA : in std_ulogic; + PHYEMAC0RXCHARISK : in std_ulogic; + PHYEMAC0RXCHECKINGCRC : in std_ulogic; + PHYEMAC0RXCLK : in std_ulogic; + PHYEMAC0RXCLKCORCNT : in std_logic_vector(2 downto 0); + PHYEMAC0RXCOMMADET : in std_ulogic; + PHYEMAC0RXD : in std_logic_vector(7 downto 0); + PHYEMAC0RXDISPERR : in std_ulogic; + PHYEMAC0RXDV : in std_ulogic; + PHYEMAC0RXER : in std_ulogic; + PHYEMAC0RXLOSSOFSYNC : in std_logic_vector(1 downto 0); + PHYEMAC0RXNOTINTABLE : in std_ulogic; + PHYEMAC0RXRUNDISP : in std_ulogic; + PHYEMAC0SIGNALDET : in std_ulogic; + PHYEMAC0TXBUFERR : in std_ulogic; + PHYEMAC0TXGMIIMIICLKIN : in std_ulogic; + PHYEMAC1COL : in std_ulogic; + PHYEMAC1CRS : in std_ulogic; + PHYEMAC1GTXCLK : in std_ulogic; + PHYEMAC1MCLKIN : in std_ulogic; + PHYEMAC1MDIN : in std_ulogic; + PHYEMAC1MIITXCLK : in std_ulogic; + PHYEMAC1PHYAD : in std_logic_vector(4 downto 0); + PHYEMAC1RXBUFERR : in std_ulogic; + PHYEMAC1RXBUFSTATUS : in std_logic_vector(1 downto 0); + PHYEMAC1RXCHARISCOMMA : in std_ulogic; + PHYEMAC1RXCHARISK : in std_ulogic; + PHYEMAC1RXCHECKINGCRC : in std_ulogic; + PHYEMAC1RXCLK : in std_ulogic; + PHYEMAC1RXCLKCORCNT : in std_logic_vector(2 downto 0); + PHYEMAC1RXCOMMADET : in std_ulogic; + PHYEMAC1RXD : in std_logic_vector(7 downto 0); + PHYEMAC1RXDISPERR : in std_ulogic; + PHYEMAC1RXDV : in std_ulogic; + PHYEMAC1RXER : in std_ulogic; + PHYEMAC1RXLOSSOFSYNC : in std_logic_vector(1 downto 0); + PHYEMAC1RXNOTINTABLE : in std_ulogic; + PHYEMAC1RXRUNDISP : in std_ulogic; + PHYEMAC1SIGNALDET : in std_ulogic; + PHYEMAC1TXBUFERR : in std_ulogic; + PHYEMAC1TXGMIIMIICLKIN : in std_ulogic; + RESET : in std_ulogic; + + EMAC0_1000BASEX_ENABLE : in std_ulogic; + EMAC0_ADDRFILTER_ENABLE : in std_ulogic; + EMAC0_BYTEPHY : in std_ulogic; + EMAC0_CONFIGVEC_79 : in std_ulogic; + EMAC0_DCRBASEADDR : in std_logic_vector(0 to 7); + EMAC0_GTLOOPBACK : in std_ulogic; + EMAC0_HOST_ENABLE : in std_ulogic; + EMAC0_LINKTIMERVAL : in std_logic_vector(8 downto 0); + EMAC0_LTCHECK_DISABLE : in std_ulogic; + EMAC0_MDIO_ENABLE : in std_ulogic; + EMAC0_PAUSEADDR : in std_logic_vector(47 downto 0); + EMAC0_PHYINITAUTONEG_ENABLE : in std_ulogic; + EMAC0_PHYISOLATE : in std_ulogic; + EMAC0_PHYLOOPBACKMSB : in std_ulogic; + EMAC0_PHYPOWERDOWN : in std_ulogic; + EMAC0_PHYRESET : in std_ulogic; + EMAC0_RGMII_ENABLE : in std_ulogic; + EMAC0_RX16BITCLIENT_ENABLE : in std_ulogic; + EMAC0_RXFLOWCTRL_ENABLE : in std_ulogic; + EMAC0_RXHALFDUPLEX : in std_ulogic; + EMAC0_RXINBANDFCS_ENABLE : in std_ulogic; + EMAC0_RXJUMBOFRAME_ENABLE : in std_ulogic; + EMAC0_RXRESET : in std_ulogic; + EMAC0_RXVLAN_ENABLE : in std_ulogic; + EMAC0_RX_ENABLE : in std_ulogic; + EMAC0_SGMII_ENABLE : in std_ulogic; + EMAC0_SPEED_LSB : in std_ulogic; + EMAC0_SPEED_MSB : in std_ulogic; + EMAC0_TX16BITCLIENT_ENABLE : in std_ulogic; + EMAC0_TXFLOWCTRL_ENABLE : in std_ulogic; + EMAC0_TXHALFDUPLEX : in std_ulogic; + EMAC0_TXIFGADJUST_ENABLE : in std_ulogic; + EMAC0_TXINBANDFCS_ENABLE : in std_ulogic; + EMAC0_TXJUMBOFRAME_ENABLE : in std_ulogic; + EMAC0_TXRESET : in std_ulogic; + EMAC0_TXVLAN_ENABLE : in std_ulogic; + EMAC0_TX_ENABLE : in std_ulogic; + EMAC0_UNICASTADDR : in std_logic_vector(47 downto 0); + EMAC0_UNIDIRECTION_ENABLE : in std_ulogic; + EMAC0_USECLKEN : in std_ulogic; + EMAC1_1000BASEX_ENABLE : in std_ulogic; + EMAC1_ADDRFILTER_ENABLE : in std_ulogic; + EMAC1_BYTEPHY : in std_ulogic; + EMAC1_CONFIGVEC_79 : in std_ulogic; + EMAC1_DCRBASEADDR : in std_logic_vector(0 to 7); + EMAC1_GTLOOPBACK : in std_ulogic; + EMAC1_HOST_ENABLE : in std_ulogic; + EMAC1_LINKTIMERVAL : in std_logic_vector(8 downto 0); + EMAC1_LTCHECK_DISABLE : in std_ulogic; + EMAC1_MDIO_ENABLE : in std_ulogic; + EMAC1_PAUSEADDR : in std_logic_vector(47 downto 0); + EMAC1_PHYINITAUTONEG_ENABLE : in std_ulogic; + EMAC1_PHYISOLATE : in std_ulogic; + EMAC1_PHYLOOPBACKMSB : in std_ulogic; + EMAC1_PHYPOWERDOWN : in std_ulogic; + EMAC1_PHYRESET : in std_ulogic; + EMAC1_RGMII_ENABLE : in std_ulogic; + EMAC1_RX16BITCLIENT_ENABLE : in std_ulogic; + EMAC1_RXFLOWCTRL_ENABLE : in std_ulogic; + EMAC1_RXHALFDUPLEX : in std_ulogic; + EMAC1_RXINBANDFCS_ENABLE : in std_ulogic; + EMAC1_RXJUMBOFRAME_ENABLE : in std_ulogic; + EMAC1_RXRESET : in std_ulogic; + EMAC1_RXVLAN_ENABLE : in std_ulogic; + EMAC1_RX_ENABLE : in std_ulogic; + EMAC1_SGMII_ENABLE : in std_ulogic; + EMAC1_SPEED_LSB : in std_ulogic; + EMAC1_SPEED_MSB : in std_ulogic; + EMAC1_TX16BITCLIENT_ENABLE : in std_ulogic; + EMAC1_TXFLOWCTRL_ENABLE : in std_ulogic; + EMAC1_TXHALFDUPLEX : in std_ulogic; + EMAC1_TXIFGADJUST_ENABLE : in std_ulogic; + EMAC1_TXINBANDFCS_ENABLE : in std_ulogic; + EMAC1_TXJUMBOFRAME_ENABLE : in std_ulogic; + EMAC1_TXRESET : in std_ulogic; + EMAC1_TXVLAN_ENABLE : in std_ulogic; + EMAC1_TX_ENABLE : in std_ulogic; + EMAC1_UNICASTADDR : in std_logic_vector(47 downto 0); + EMAC1_UNIDIRECTION_ENABLE : in std_ulogic; + EMAC1_USECLKEN : in std_ulogic + ); + end component; + + + function GetValue_EMAC0 ( + EMAC0_TX16BITCLIENT_ENABLE : in boolean + ) return time is + variable delay_time : time; + begin + case EMAC0_TX16BITCLIENT_ENABLE is + when TRUE => delay_time := 25 ps; + when FALSE => delay_time := 0 ps; + end case; + return delay_time; + end; + + function GetValue_EMAC1 ( + EMAC1_TX16BITCLIENT_ENABLE : in boolean + ) return time is + variable delay_time : time; + begin + case EMAC1_TX16BITCLIENT_ENABLE is + when TRUE => delay_time := 25 ps; + when FALSE => delay_time := 0 ps; + end case; + return delay_time; + end; + constant IN_DELAY : time := 50 ps; + constant OUT_DELAY : time := 0 ps; + constant CLK_DELAY : time := 0 ps; + constant EMAC0MIITXCLK_DELAY : time := GetValue_EMAC0(EMAC0_TX16BITCLIENT_ENABLE); + constant EMAC1MIITXCLK_DELAY : time := GetValue_EMAC1(EMAC1_TX16BITCLIENT_ENABLE); + + constant PATH_DELAY : VitalDelayType01 := (100 ps, 100 ps); + + signal EMAC0_PAUSEADDR_BINARY : std_logic_vector(47 downto 0) := To_StdLogicVector(EMAC0_PAUSEADDR); + signal EMAC0_RXHALFDUPLEX_BINARY : std_ulogic; + signal EMAC0_RXVLAN_ENABLE_BINARY : std_ulogic; + signal EMAC0_RX_ENABLE_BINARY : std_ulogic; + signal EMAC0_RXINBANDFCS_ENABLE_BINARY : std_ulogic; + signal EMAC0_RXJUMBOFRAME_ENABLE_BINARY : std_ulogic; + signal EMAC0_RXRESET_BINARY : std_ulogic; + signal EMAC0_TXIFGADJUST_ENABLE_BINARY : std_ulogic; + signal EMAC0_TXHALFDUPLEX_BINARY : std_ulogic; + signal EMAC0_TXVLAN_ENABLE_BINARY : std_ulogic; + signal EMAC0_TX_ENABLE_BINARY : std_ulogic; + signal EMAC0_TXINBANDFCS_ENABLE_BINARY : std_ulogic; + signal EMAC0_TXJUMBOFRAME_ENABLE_BINARY : std_ulogic; + signal EMAC0_TXRESET_BINARY : std_ulogic; + signal EMAC0_TXFLOWCTRL_ENABLE_BINARY : std_ulogic; + signal EMAC0_RXFLOWCTRL_ENABLE_BINARY : std_ulogic; + signal EMAC0_LTCHECK_DISABLE_BINARY : std_ulogic; + signal EMAC0_ADDRFILTER_ENABLE_BINARY : std_ulogic; + signal EMAC0_RX16BITCLIENT_ENABLE_BINARY : std_ulogic; + signal EMAC0_TX16BITCLIENT_ENABLE_BINARY : std_ulogic; + signal EMAC0_HOST_ENABLE_BINARY : std_ulogic; + signal EMAC0_1000BASEX_ENABLE_BINARY : std_ulogic; + signal EMAC0_SGMII_ENABLE_BINARY : std_ulogic; + signal EMAC0_RGMII_ENABLE_BINARY : std_ulogic; + signal EMAC0_SPEED_LSB_BINARY : std_ulogic; + signal EMAC0_SPEED_MSB_BINARY : std_ulogic; + signal EMAC0_MDIO_ENABLE_BINARY : std_ulogic; + signal EMAC0_PHYLOOPBACKMSB_BINARY : std_ulogic; + signal EMAC0_PHYPOWERDOWN_BINARY : std_ulogic; + signal EMAC0_PHYISOLATE_BINARY : std_ulogic; + signal EMAC0_PHYINITAUTONEG_ENABLE_BINARY : std_ulogic; + signal EMAC0_PHYRESET_BINARY : std_ulogic; + signal EMAC0_CONFIGVEC_79_BINARY : std_ulogic; + signal EMAC0_UNIDIRECTION_ENABLE_BINARY : std_ulogic; + signal EMAC0_GTLOOPBACK_BINARY : std_ulogic; + signal EMAC0_UNICASTADDR_BINARY : std_logic_vector(47 downto 0) := To_StdLogicVector(EMAC0_UNICASTADDR); + signal EMAC0_LINKTIMERVAL_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(EMAC0_LINKTIMERVAL)(8 downto 0); + signal EMAC0_BYTEPHY_BINARY : std_ulogic; + signal EMAC0_USECLKEN_BINARY : std_ulogic; + signal EMAC0_DCRBASEADDR_BINARY : std_logic_vector(0 to 7) := To_StdLogicVector(EMAC0_DCRBASEADDR); + signal EMAC1_PAUSEADDR_BINARY : std_logic_vector(47 downto 0) := To_StdLogicVector(EMAC1_PAUSEADDR); + signal EMAC1_RXHALFDUPLEX_BINARY : std_ulogic; + signal EMAC1_RXVLAN_ENABLE_BINARY : std_ulogic; + signal EMAC1_RX_ENABLE_BINARY : std_ulogic; + signal EMAC1_RXINBANDFCS_ENABLE_BINARY : std_ulogic; + signal EMAC1_RXJUMBOFRAME_ENABLE_BINARY : std_ulogic; + signal EMAC1_RXRESET_BINARY : std_ulogic; + signal EMAC1_TXIFGADJUST_ENABLE_BINARY : std_ulogic; + signal EMAC1_TXHALFDUPLEX_BINARY : std_ulogic; + signal EMAC1_TXVLAN_ENABLE_BINARY : std_ulogic; + signal EMAC1_TX_ENABLE_BINARY : std_ulogic; + signal EMAC1_TXINBANDFCS_ENABLE_BINARY : std_ulogic; + signal EMAC1_TXJUMBOFRAME_ENABLE_BINARY : std_ulogic; + signal EMAC1_TXRESET_BINARY : std_ulogic; + signal EMAC1_TXFLOWCTRL_ENABLE_BINARY : std_ulogic; + signal EMAC1_RXFLOWCTRL_ENABLE_BINARY : std_ulogic; + signal EMAC1_LTCHECK_DISABLE_BINARY : std_ulogic; + signal EMAC1_ADDRFILTER_ENABLE_BINARY : std_ulogic; + signal EMAC1_RX16BITCLIENT_ENABLE_BINARY : std_ulogic; + signal EMAC1_TX16BITCLIENT_ENABLE_BINARY : std_ulogic; + signal EMAC1_HOST_ENABLE_BINARY : std_ulogic; + signal EMAC1_1000BASEX_ENABLE_BINARY : std_ulogic; + signal EMAC1_SGMII_ENABLE_BINARY : std_ulogic; + signal EMAC1_RGMII_ENABLE_BINARY : std_ulogic; + signal EMAC1_SPEED_LSB_BINARY : std_ulogic; + signal EMAC1_SPEED_MSB_BINARY : std_ulogic; + signal EMAC1_MDIO_ENABLE_BINARY : std_ulogic; + signal EMAC1_PHYLOOPBACKMSB_BINARY : std_ulogic; + signal EMAC1_PHYPOWERDOWN_BINARY : std_ulogic; + signal EMAC1_PHYISOLATE_BINARY : std_ulogic; + signal EMAC1_PHYINITAUTONEG_ENABLE_BINARY : std_ulogic; + signal EMAC1_PHYRESET_BINARY : std_ulogic; + signal EMAC1_CONFIGVEC_79_BINARY : std_ulogic; + signal EMAC1_UNIDIRECTION_ENABLE_BINARY : std_ulogic; + signal EMAC1_GTLOOPBACK_BINARY : std_ulogic; + signal EMAC1_UNICASTADDR_BINARY : std_logic_vector(47 downto 0) := To_StdLogicVector(EMAC1_UNICASTADDR); + signal EMAC1_LINKTIMERVAL_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(EMAC1_LINKTIMERVAL)(8 downto 0); + signal EMAC1_BYTEPHY_BINARY : std_ulogic; + signal EMAC1_USECLKEN_BINARY : std_ulogic; + signal EMAC1_DCRBASEADDR_BINARY : std_logic_vector(0 to 7) := To_StdLogicVector(EMAC1_DCRBASEADDR); + + signal DCRHOSTDONEIR_out : std_ulogic; + signal EMAC0CLIENTANINTERRUPT_out : std_ulogic; + signal EMAC0CLIENTRXBADFRAME_out : std_ulogic; + signal EMAC0CLIENTRXCLIENTCLKOUT_out : std_ulogic; + signal EMAC0CLIENTRXD_out : std_logic_vector(15 downto 0); + signal EMAC0CLIENTRXDVLD_out : std_ulogic; + signal EMAC0CLIENTRXDVLDMSW_out : std_ulogic; + signal EMAC0CLIENTRXFRAMEDROP_out : std_ulogic; + signal EMAC0CLIENTRXGOODFRAME_out : std_ulogic; + signal EMAC0CLIENTRXSTATS_out : std_logic_vector(6 downto 0); + signal EMAC0CLIENTRXSTATSBYTEVLD_out : std_ulogic; + signal EMAC0CLIENTRXSTATSVLD_out : std_ulogic; + signal EMAC0CLIENTTXACK_out : std_ulogic; + signal EMAC0CLIENTTXCLIENTCLKOUT_out : std_ulogic; + signal EMAC0CLIENTTXCOLLISION_out : std_ulogic; + signal EMAC0PHYTXGMIIMIICLKOUT_out : std_ulogic; + signal EMAC0CLIENTTXRETRANSMIT_out : std_ulogic; + signal EMAC0CLIENTTXSTATS_out : std_ulogic; + signal EMAC0CLIENTTXSTATSBYTEVLD_out : std_ulogic; + signal EMAC0CLIENTTXSTATSVLD_out : std_ulogic; + signal EMAC0PHYENCOMMAALIGN_out : std_ulogic; + signal EMAC0PHYLOOPBACKMSB_out : std_ulogic; + signal EMAC0PHYMCLKOUT_out : std_ulogic; + signal EMAC0PHYMDOUT_out : std_ulogic; + signal EMAC0PHYMDTRI_out : std_ulogic; + signal EMAC0PHYMGTRXRESET_out : std_ulogic; + signal EMAC0PHYMGTTXRESET_out : std_ulogic; + signal EMAC0PHYPOWERDOWN_out : std_ulogic; + signal EMAC0PHYSYNCACQSTATUS_out : std_ulogic; + signal EMAC0PHYTXCHARDISPMODE_out : std_ulogic; + signal EMAC0PHYTXCHARDISPVAL_out : std_ulogic; + signal EMAC0PHYTXCHARISK_out : std_ulogic; + signal EMAC0PHYTXCLK_out : std_ulogic; + signal EMAC0PHYTXD_out : std_logic_vector(7 downto 0); + signal EMAC0PHYTXEN_out : std_ulogic; + signal EMAC0PHYTXER_out : std_ulogic; + signal EMAC0SPEEDIS10100_out : std_ulogic; + signal EMAC1CLIENTANINTERRUPT_out : std_ulogic; + signal EMAC1CLIENTRXBADFRAME_out : std_ulogic; + signal EMAC1CLIENTRXCLIENTCLKOUT_out : std_ulogic; + signal EMAC1CLIENTRXD_out : std_logic_vector(15 downto 0); + signal EMAC1CLIENTRXDVLD_out : std_ulogic; + signal EMAC1CLIENTRXDVLDMSW_out : std_ulogic; + signal EMAC1CLIENTRXFRAMEDROP_out : std_ulogic; + signal EMAC1CLIENTRXGOODFRAME_out : std_ulogic; + signal EMAC1CLIENTRXSTATS_out : std_logic_vector(6 downto 0); + signal EMAC1CLIENTRXSTATSBYTEVLD_out : std_ulogic; + signal EMAC1CLIENTRXSTATSVLD_out : std_ulogic; + signal EMAC1CLIENTTXACK_out : std_ulogic; + signal EMAC1CLIENTTXCLIENTCLKOUT_out : std_ulogic; + signal EMAC1CLIENTTXCOLLISION_out : std_ulogic; + signal EMAC1PHYTXGMIIMIICLKOUT_out : std_ulogic; + signal EMAC1CLIENTTXRETRANSMIT_out : std_ulogic; + signal EMAC1CLIENTTXSTATS_out : std_ulogic; + signal EMAC1CLIENTTXSTATSBYTEVLD_out : std_ulogic; + signal EMAC1CLIENTTXSTATSVLD_out : std_ulogic; + signal EMAC1PHYENCOMMAALIGN_out : std_ulogic; + signal EMAC1PHYLOOPBACKMSB_out : std_ulogic; + signal EMAC1PHYMCLKOUT_out : std_ulogic; + signal EMAC1PHYMDOUT_out : std_ulogic; + signal EMAC1PHYMDTRI_out : std_ulogic; + signal EMAC1PHYMGTRXRESET_out : std_ulogic; + signal EMAC1PHYMGTTXRESET_out : std_ulogic; + signal EMAC1PHYPOWERDOWN_out : std_ulogic; + signal EMAC1PHYSYNCACQSTATUS_out : std_ulogic; + signal EMAC1PHYTXCHARDISPMODE_out : std_ulogic; + signal EMAC1PHYTXCHARDISPVAL_out : std_ulogic; + signal EMAC1PHYTXCHARISK_out : std_ulogic; + signal EMAC1PHYTXCLK_out : std_ulogic; + signal EMAC1PHYTXD_out : std_logic_vector(7 downto 0); + signal EMAC1PHYTXEN_out : std_ulogic; + signal EMAC1PHYTXER_out : std_ulogic; + signal EMAC1SPEEDIS10100_out : std_ulogic; + signal EMACDCRACK_out : std_ulogic; + signal EMACDCRDBUS_out : std_logic_vector(0 to 31); + signal HOSTMIIMRDY_out : std_ulogic; + signal HOSTRDDATA_out : std_logic_vector(31 downto 0); + + signal EMAC0CLIENTRXCLIENTCLKOUT_outdelay : std_ulogic; + signal EMAC0CLIENTTXCLIENTCLKOUT_outdelay : std_ulogic; + signal EMAC0PHYTXGMIIMIICLKOUT_outdelay : std_ulogic; + signal EMAC0PHYMCLKOUT_outdelay : std_ulogic; + signal EMAC0PHYTXCLK_outdelay : std_ulogic; + signal EMAC1CLIENTRXCLIENTCLKOUT_outdelay : std_ulogic; + signal EMAC1CLIENTTXCLIENTCLKOUT_outdelay : std_ulogic; + signal EMAC1PHYTXGMIIMIICLKOUT_outdelay : std_ulogic; + signal EMAC1PHYMCLKOUT_outdelay : std_ulogic; + signal EMAC1PHYTXCLK_outdelay : std_ulogic; + + signal DCRHOSTDONEIR_outdelay : std_ulogic; + signal EMAC0CLIENTANINTERRUPT_outdelay : std_ulogic; + signal EMAC0CLIENTRXBADFRAME_outdelay : std_ulogic; + signal EMAC0CLIENTRXD_outdelay : std_logic_vector(15 downto 0); + signal EMAC0CLIENTRXDVLD_outdelay : std_ulogic; + signal EMAC0CLIENTRXDVLDMSW_outdelay : std_ulogic; + signal EMAC0CLIENTRXFRAMEDROP_outdelay : std_ulogic; + signal EMAC0CLIENTRXGOODFRAME_outdelay : std_ulogic; + signal EMAC0CLIENTRXSTATS_outdelay : std_logic_vector(6 downto 0); + signal EMAC0CLIENTRXSTATSBYTEVLD_outdelay : std_ulogic; + signal EMAC0CLIENTRXSTATSVLD_outdelay : std_ulogic; + signal EMAC0CLIENTTXACK_outdelay : std_ulogic; + signal EMAC0CLIENTTXCOLLISION_outdelay : std_ulogic; + signal EMAC0CLIENTTXRETRANSMIT_outdelay : std_ulogic; + signal EMAC0CLIENTTXSTATS_outdelay : std_ulogic; + signal EMAC0CLIENTTXSTATSBYTEVLD_outdelay : std_ulogic; + signal EMAC0CLIENTTXSTATSVLD_outdelay : std_ulogic; + signal EMAC0PHYENCOMMAALIGN_outdelay : std_ulogic; + signal EMAC0PHYLOOPBACKMSB_outdelay : std_ulogic; + signal EMAC0PHYMDOUT_outdelay : std_ulogic; + signal EMAC0PHYMDTRI_outdelay : std_ulogic; + signal EMAC0PHYMGTRXRESET_outdelay : std_ulogic; + signal EMAC0PHYMGTTXRESET_outdelay : std_ulogic; + signal EMAC0PHYPOWERDOWN_outdelay : std_ulogic; + signal EMAC0PHYSYNCACQSTATUS_outdelay : std_ulogic; + signal EMAC0PHYTXCHARDISPMODE_outdelay : std_ulogic; + signal EMAC0PHYTXCHARDISPVAL_outdelay : std_ulogic; + signal EMAC0PHYTXCHARISK_outdelay : std_ulogic; + signal EMAC0PHYTXD_outdelay : std_logic_vector(7 downto 0); + signal EMAC0PHYTXEN_outdelay : std_ulogic; + signal EMAC0PHYTXER_outdelay : std_ulogic; + signal EMAC0SPEEDIS10100_outdelay : std_ulogic; + signal EMAC1CLIENTANINTERRUPT_outdelay : std_ulogic; + signal EMAC1CLIENTRXBADFRAME_outdelay : std_ulogic; + signal EMAC1CLIENTRXD_outdelay : std_logic_vector(15 downto 0); + signal EMAC1CLIENTRXDVLD_outdelay : std_ulogic; + signal EMAC1CLIENTRXDVLDMSW_outdelay : std_ulogic; + signal EMAC1CLIENTRXFRAMEDROP_outdelay : std_ulogic; + signal EMAC1CLIENTRXGOODFRAME_outdelay : std_ulogic; + signal EMAC1CLIENTRXSTATS_outdelay : std_logic_vector(6 downto 0); + signal EMAC1CLIENTRXSTATSBYTEVLD_outdelay : std_ulogic; + signal EMAC1CLIENTRXSTATSVLD_outdelay : std_ulogic; + signal EMAC1CLIENTTXACK_outdelay : std_ulogic; + signal EMAC1CLIENTTXCOLLISION_outdelay : std_ulogic; + signal EMAC1CLIENTTXRETRANSMIT_outdelay : std_ulogic; + signal EMAC1CLIENTTXSTATS_outdelay : std_ulogic; + signal EMAC1CLIENTTXSTATSBYTEVLD_outdelay : std_ulogic; + signal EMAC1CLIENTTXSTATSVLD_outdelay : std_ulogic; + signal EMAC1PHYENCOMMAALIGN_outdelay : std_ulogic; + signal EMAC1PHYLOOPBACKMSB_outdelay : std_ulogic; + signal EMAC1PHYMDOUT_outdelay : std_ulogic; + signal EMAC1PHYMDTRI_outdelay : std_ulogic; + signal EMAC1PHYMGTRXRESET_outdelay : std_ulogic; + signal EMAC1PHYMGTTXRESET_outdelay : std_ulogic; + signal EMAC1PHYPOWERDOWN_outdelay : std_ulogic; + signal EMAC1PHYSYNCACQSTATUS_outdelay : std_ulogic; + signal EMAC1PHYTXCHARDISPMODE_outdelay : std_ulogic; + signal EMAC1PHYTXCHARDISPVAL_outdelay : std_ulogic; + signal EMAC1PHYTXCHARISK_outdelay : std_ulogic; + signal EMAC1PHYTXD_outdelay : std_logic_vector(7 downto 0); + signal EMAC1PHYTXEN_outdelay : std_ulogic; + signal EMAC1PHYTXER_outdelay : std_ulogic; + signal EMAC1SPEEDIS10100_outdelay : std_ulogic; + signal EMACDCRACK_outdelay : std_ulogic; + signal EMACDCRDBUS_outdelay : std_logic_vector(0 to 31); + signal HOSTMIIMRDY_outdelay : std_ulogic; + signal HOSTRDDATA_outdelay : std_logic_vector(31 downto 0); + + signal CLIENTEMAC0DCMLOCKED_ipd : std_ulogic; + signal CLIENTEMAC0PAUSEREQ_ipd : std_ulogic; + signal CLIENTEMAC0PAUSEVAL_ipd : std_logic_vector(15 downto 0); + signal CLIENTEMAC0RXCLIENTCLKIN_ipd : std_ulogic; + signal CLIENTEMAC0TXCLIENTCLKIN_ipd : std_ulogic; + signal CLIENTEMAC0TXD_ipd : std_logic_vector(15 downto 0); + signal CLIENTEMAC0TXDVLD_ipd : std_ulogic; + signal CLIENTEMAC0TXDVLDMSW_ipd : std_ulogic; + signal CLIENTEMAC0TXFIRSTBYTE_ipd : std_ulogic; + signal PHYEMAC0TXGMIIMIICLKIN_ipd : std_ulogic; + signal CLIENTEMAC0TXIFGDELAY_ipd : std_logic_vector(7 downto 0); + signal CLIENTEMAC0TXUNDERRUN_ipd : std_ulogic; + signal CLIENTEMAC1DCMLOCKED_ipd : std_ulogic; + signal CLIENTEMAC1PAUSEREQ_ipd : std_ulogic; + signal CLIENTEMAC1PAUSEVAL_ipd : std_logic_vector(15 downto 0); + signal CLIENTEMAC1RXCLIENTCLKIN_ipd : std_ulogic; + signal CLIENTEMAC1TXCLIENTCLKIN_ipd : std_ulogic; + signal CLIENTEMAC1TXD_ipd : std_logic_vector(15 downto 0); + signal CLIENTEMAC1TXDVLD_ipd : std_ulogic; + signal CLIENTEMAC1TXDVLDMSW_ipd : std_ulogic; + signal CLIENTEMAC1TXFIRSTBYTE_ipd : std_ulogic; + signal PHYEMAC1TXGMIIMIICLKIN_ipd : std_ulogic; + signal CLIENTEMAC1TXIFGDELAY_ipd : std_logic_vector(7 downto 0); + signal CLIENTEMAC1TXUNDERRUN_ipd : std_ulogic; + signal DCREMACABUS_ipd : std_logic_vector(0 to 9); + signal DCREMACCLK_ipd : std_ulogic; + signal DCREMACDBUS_ipd : std_logic_vector(0 to 31); + signal DCREMACENABLE_ipd : std_ulogic; + signal DCREMACREAD_ipd : std_ulogic; + signal DCREMACWRITE_ipd : std_ulogic; + signal HOSTADDR_ipd : std_logic_vector(9 downto 0); + signal HOSTCLK_ipd : std_ulogic; + signal HOSTEMAC1SEL_ipd : std_ulogic; + signal HOSTMIIMSEL_ipd : std_ulogic; + signal HOSTOPCODE_ipd : std_logic_vector(1 downto 0); + signal HOSTREQ_ipd : std_ulogic; + signal HOSTWRDATA_ipd : std_logic_vector(31 downto 0); + signal PHYEMAC0COL_ipd : std_ulogic; + signal PHYEMAC0CRS_ipd : std_ulogic; + signal PHYEMAC0GTXCLK_ipd : std_ulogic; + signal PHYEMAC0MCLKIN_ipd : std_ulogic; + signal PHYEMAC0MDIN_ipd : std_ulogic; + signal PHYEMAC0MIITXCLK_ipd : std_ulogic; + signal PHYEMAC0PHYAD_ipd : std_logic_vector(4 downto 0); + signal PHYEMAC0RXBUFERR_ipd : std_ulogic; + signal PHYEMAC0RXBUFSTATUS_ipd : std_logic_vector(1 downto 0); + signal PHYEMAC0RXCHARISCOMMA_ipd : std_ulogic; + signal PHYEMAC0RXCHARISK_ipd : std_ulogic; + signal PHYEMAC0RXCHECKINGCRC_ipd : std_ulogic; + signal PHYEMAC0RXCLK_ipd : std_ulogic; + signal PHYEMAC0RXCLKCORCNT_ipd : std_logic_vector(2 downto 0); + signal PHYEMAC0RXCOMMADET_ipd : std_ulogic; + signal PHYEMAC0RXD_ipd : std_logic_vector(7 downto 0); + signal PHYEMAC0RXDISPERR_ipd : std_ulogic; + signal PHYEMAC0RXDV_ipd : std_ulogic; + signal PHYEMAC0RXER_ipd : std_ulogic; + signal PHYEMAC0RXLOSSOFSYNC_ipd : std_logic_vector(1 downto 0); + signal PHYEMAC0RXNOTINTABLE_ipd : std_ulogic; + signal PHYEMAC0RXRUNDISP_ipd : std_ulogic; + signal PHYEMAC0SIGNALDET_ipd : std_ulogic; + signal PHYEMAC0TXBUFERR_ipd : std_ulogic; + signal PHYEMAC1COL_ipd : std_ulogic; + signal PHYEMAC1CRS_ipd : std_ulogic; + signal PHYEMAC1GTXCLK_ipd : std_ulogic; + signal PHYEMAC1MCLKIN_ipd : std_ulogic; + signal PHYEMAC1MDIN_ipd : std_ulogic; + signal PHYEMAC1MIITXCLK_ipd : std_ulogic; + signal PHYEMAC1PHYAD_ipd : std_logic_vector(4 downto 0); + signal PHYEMAC1RXBUFERR_ipd : std_ulogic; + signal PHYEMAC1RXBUFSTATUS_ipd : std_logic_vector(1 downto 0); + signal PHYEMAC1RXCHARISCOMMA_ipd : std_ulogic; + signal PHYEMAC1RXCHARISK_ipd : std_ulogic; + signal PHYEMAC1RXCHECKINGCRC_ipd : std_ulogic; + signal PHYEMAC1RXCLK_ipd : std_ulogic; + signal PHYEMAC1RXCLKCORCNT_ipd : std_logic_vector(2 downto 0); + signal PHYEMAC1RXCOMMADET_ipd : std_ulogic; + signal PHYEMAC1RXD_ipd : std_logic_vector(7 downto 0); + signal PHYEMAC1RXDISPERR_ipd : std_ulogic; + signal PHYEMAC1RXDV_ipd : std_ulogic; + signal PHYEMAC1RXER_ipd : std_ulogic; + signal PHYEMAC1RXLOSSOFSYNC_ipd : std_logic_vector(1 downto 0); + signal PHYEMAC1RXNOTINTABLE_ipd : std_ulogic; + signal PHYEMAC1RXRUNDISP_ipd : std_ulogic; + signal PHYEMAC1SIGNALDET_ipd : std_ulogic; + signal PHYEMAC1TXBUFERR_ipd : std_ulogic; + signal RESET_ipd : std_ulogic; + + signal CLIENTEMAC0DCMLOCKED_indelay : std_ulogic; + signal CLIENTEMAC0PAUSEREQ_indelay : std_ulogic; + signal CLIENTEMAC0PAUSEVAL_indelay : std_logic_vector(15 downto 0); + signal CLIENTEMAC0RXCLIENTCLKIN_indelay : std_ulogic; + signal CLIENTEMAC0TXCLIENTCLKIN_indelay : std_ulogic; + signal CLIENTEMAC0TXD_indelay : std_logic_vector(15 downto 0); + signal CLIENTEMAC0TXDVLD_indelay : std_ulogic; + signal CLIENTEMAC0TXDVLDMSW_indelay : std_ulogic; + signal CLIENTEMAC0TXFIRSTBYTE_indelay : std_ulogic; + signal PHYEMAC0TXGMIIMIICLKIN_indelay : std_ulogic; + signal CLIENTEMAC0TXIFGDELAY_indelay : std_logic_vector(7 downto 0); + signal CLIENTEMAC0TXUNDERRUN_indelay : std_ulogic; + signal CLIENTEMAC1DCMLOCKED_indelay : std_ulogic; + signal CLIENTEMAC1PAUSEREQ_indelay : std_ulogic; + signal CLIENTEMAC1PAUSEVAL_indelay : std_logic_vector(15 downto 0); + signal CLIENTEMAC1RXCLIENTCLKIN_indelay : std_ulogic; + signal CLIENTEMAC1TXCLIENTCLKIN_indelay : std_ulogic; + signal CLIENTEMAC1TXD_indelay : std_logic_vector(15 downto 0); + signal CLIENTEMAC1TXDVLD_indelay : std_ulogic; + signal CLIENTEMAC1TXDVLDMSW_indelay : std_ulogic; + signal CLIENTEMAC1TXFIRSTBYTE_indelay : std_ulogic; + signal PHYEMAC1TXGMIIMIICLKIN_indelay : std_ulogic; + signal CLIENTEMAC1TXIFGDELAY_indelay : std_logic_vector(7 downto 0); + signal CLIENTEMAC1TXUNDERRUN_indelay : std_ulogic; + signal DCREMACABUS_indelay : std_logic_vector(0 to 9); + signal DCREMACCLK_indelay : std_ulogic; + signal DCREMACDBUS_indelay : std_logic_vector(0 to 31); + signal DCREMACENABLE_indelay : std_ulogic; + signal DCREMACREAD_indelay : std_ulogic; + signal DCREMACWRITE_indelay : std_ulogic; + signal HOSTADDR_indelay : std_logic_vector(9 downto 0); + signal HOSTCLK_indelay : std_ulogic; + signal HOSTEMAC1SEL_indelay : std_ulogic; + signal HOSTMIIMSEL_indelay : std_ulogic; + signal HOSTOPCODE_indelay : std_logic_vector(1 downto 0); + signal HOSTREQ_indelay : std_ulogic; + signal HOSTWRDATA_indelay : std_logic_vector(31 downto 0); + signal PHYEMAC0COL_indelay : std_ulogic; + signal PHYEMAC0CRS_indelay : std_ulogic; + signal PHYEMAC0GTXCLK_indelay : std_ulogic; + signal PHYEMAC0MCLKIN_indelay : std_ulogic; + signal PHYEMAC0MDIN_indelay : std_ulogic; + signal PHYEMAC0MIITXCLK_indelay : std_ulogic; + signal PHYEMAC0PHYAD_indelay : std_logic_vector(4 downto 0); + signal PHYEMAC0RXBUFERR_indelay : std_ulogic; + signal PHYEMAC0RXBUFSTATUS_indelay : std_logic_vector(1 downto 0); + signal PHYEMAC0RXCHARISCOMMA_indelay : std_ulogic; + signal PHYEMAC0RXCHARISK_indelay : std_ulogic; + signal PHYEMAC0RXCHECKINGCRC_indelay : std_ulogic; + signal PHYEMAC0RXCLK_indelay : std_ulogic; + signal PHYEMAC0RXCLKCORCNT_indelay : std_logic_vector(2 downto 0); + signal PHYEMAC0RXCOMMADET_indelay : std_ulogic; + signal PHYEMAC0RXD_indelay : std_logic_vector(7 downto 0); + signal PHYEMAC0RXDISPERR_indelay : std_ulogic; + signal PHYEMAC0RXDV_indelay : std_ulogic; + signal PHYEMAC0RXER_indelay : std_ulogic; + signal PHYEMAC0RXLOSSOFSYNC_indelay : std_logic_vector(1 downto 0); + signal PHYEMAC0RXNOTINTABLE_indelay : std_ulogic; + signal PHYEMAC0RXRUNDISP_indelay : std_ulogic; + signal PHYEMAC0SIGNALDET_indelay : std_ulogic; + signal PHYEMAC0TXBUFERR_indelay : std_ulogic; + signal PHYEMAC1COL_indelay : std_ulogic; + signal PHYEMAC1CRS_indelay : std_ulogic; + signal PHYEMAC1GTXCLK_indelay : std_ulogic; + signal PHYEMAC1MCLKIN_indelay : std_ulogic; + signal PHYEMAC1MDIN_indelay : std_ulogic; + signal PHYEMAC1MIITXCLK_indelay : std_ulogic; + signal PHYEMAC1PHYAD_indelay : std_logic_vector(4 downto 0); + signal PHYEMAC1RXBUFERR_indelay : std_ulogic; + signal PHYEMAC1RXBUFSTATUS_indelay : std_logic_vector(1 downto 0); + signal PHYEMAC1RXCHARISCOMMA_indelay : std_ulogic; + signal PHYEMAC1RXCHARISK_indelay : std_ulogic; + signal PHYEMAC1RXCHECKINGCRC_indelay : std_ulogic; + signal PHYEMAC1RXCLK_indelay : std_ulogic; + signal PHYEMAC1RXCLKCORCNT_indelay : std_logic_vector(2 downto 0); + signal PHYEMAC1RXCOMMADET_indelay : std_ulogic; + signal PHYEMAC1RXD_indelay : std_logic_vector(7 downto 0); + signal PHYEMAC1RXDISPERR_indelay : std_ulogic; + signal PHYEMAC1RXDV_indelay : std_ulogic; + signal PHYEMAC1RXER_indelay : std_ulogic; + signal PHYEMAC1RXLOSSOFSYNC_indelay : std_logic_vector(1 downto 0); + signal PHYEMAC1RXNOTINTABLE_indelay : std_ulogic; + signal PHYEMAC1RXRUNDISP_indelay : std_ulogic; + signal PHYEMAC1SIGNALDET_indelay : std_ulogic; + signal PHYEMAC1TXBUFERR_indelay : std_ulogic; + signal RESET_indelay : std_ulogic; + + begin + + EMAC0CLIENTRXCLIENTCLKOUT_out <= EMAC0CLIENTRXCLIENTCLKOUT_outdelay after CLK_DELAY; + EMAC0CLIENTTXCLIENTCLKOUT_out <= EMAC0CLIENTTXCLIENTCLKOUT_outdelay after CLK_DELAY; + EMAC0PHYMCLKOUT_out <= EMAC0PHYMCLKOUT_outdelay after CLK_DELAY; + EMAC0PHYTXCLK_out <= EMAC0PHYTXCLK_outdelay after CLK_DELAY; + EMAC0PHYTXGMIIMIICLKOUT_out <= EMAC0PHYTXGMIIMIICLKOUT_outdelay after CLK_DELAY; + EMAC1CLIENTRXCLIENTCLKOUT_out <= EMAC1CLIENTRXCLIENTCLKOUT_outdelay after CLK_DELAY; + EMAC1CLIENTTXCLIENTCLKOUT_out <= EMAC1CLIENTTXCLIENTCLKOUT_outdelay after CLK_DELAY; + EMAC1PHYMCLKOUT_out <= EMAC1PHYMCLKOUT_outdelay after CLK_DELAY; + EMAC1PHYTXCLK_out <= EMAC1PHYTXCLK_outdelay after CLK_DELAY; + EMAC1PHYTXGMIIMIICLKOUT_out <= EMAC1PHYTXGMIIMIICLKOUT_outdelay after CLK_DELAY; + + DCRHOSTDONEIR_out <= DCRHOSTDONEIR_outdelay after OUT_DELAY; + EMAC0CLIENTANINTERRUPT_out <= EMAC0CLIENTANINTERRUPT_outdelay after OUT_DELAY; + EMAC0CLIENTRXBADFRAME_out <= EMAC0CLIENTRXBADFRAME_outdelay after OUT_DELAY; + EMAC0CLIENTRXDVLDMSW_out <= EMAC0CLIENTRXDVLDMSW_outdelay after OUT_DELAY; + EMAC0CLIENTRXDVLD_out <= EMAC0CLIENTRXDVLD_outdelay after OUT_DELAY; + EMAC0CLIENTRXD_out <= EMAC0CLIENTRXD_outdelay after OUT_DELAY; + EMAC0CLIENTRXFRAMEDROP_out <= EMAC0CLIENTRXFRAMEDROP_outdelay after OUT_DELAY; + EMAC0CLIENTRXGOODFRAME_out <= EMAC0CLIENTRXGOODFRAME_outdelay after OUT_DELAY; + EMAC0CLIENTRXSTATSBYTEVLD_out <= EMAC0CLIENTRXSTATSBYTEVLD_outdelay after OUT_DELAY; + EMAC0CLIENTRXSTATSVLD_out <= EMAC0CLIENTRXSTATSVLD_outdelay after OUT_DELAY; + EMAC0CLIENTRXSTATS_out <= EMAC0CLIENTRXSTATS_outdelay after OUT_DELAY; + EMAC0CLIENTTXACK_out <= EMAC0CLIENTTXACK_outdelay after OUT_DELAY; + EMAC0CLIENTTXCOLLISION_out <= EMAC0CLIENTTXCOLLISION_outdelay after OUT_DELAY; + EMAC0CLIENTTXRETRANSMIT_out <= EMAC0CLIENTTXRETRANSMIT_outdelay after OUT_DELAY; + EMAC0CLIENTTXSTATSBYTEVLD_out <= EMAC0CLIENTTXSTATSBYTEVLD_outdelay after OUT_DELAY; + EMAC0CLIENTTXSTATSVLD_out <= EMAC0CLIENTTXSTATSVLD_outdelay after OUT_DELAY; + EMAC0CLIENTTXSTATS_out <= EMAC0CLIENTTXSTATS_outdelay after OUT_DELAY; + EMAC0PHYENCOMMAALIGN_out <= EMAC0PHYENCOMMAALIGN_outdelay after OUT_DELAY; + EMAC0PHYLOOPBACKMSB_out <= EMAC0PHYLOOPBACKMSB_outdelay after OUT_DELAY; + EMAC0PHYMDOUT_out <= EMAC0PHYMDOUT_outdelay after OUT_DELAY; + EMAC0PHYMDTRI_out <= EMAC0PHYMDTRI_outdelay after OUT_DELAY; + EMAC0PHYMGTRXRESET_out <= EMAC0PHYMGTRXRESET_outdelay after OUT_DELAY; + EMAC0PHYMGTTXRESET_out <= EMAC0PHYMGTTXRESET_outdelay after OUT_DELAY; + EMAC0PHYPOWERDOWN_out <= EMAC0PHYPOWERDOWN_outdelay after OUT_DELAY; + EMAC0PHYSYNCACQSTATUS_out <= EMAC0PHYSYNCACQSTATUS_outdelay after OUT_DELAY; + EMAC0PHYTXCHARDISPMODE_out <= EMAC0PHYTXCHARDISPMODE_outdelay after OUT_DELAY; + EMAC0PHYTXCHARDISPVAL_out <= EMAC0PHYTXCHARDISPVAL_outdelay after OUT_DELAY; + EMAC0PHYTXCHARISK_out <= EMAC0PHYTXCHARISK_outdelay after OUT_DELAY; + EMAC0PHYTXD_out <= EMAC0PHYTXD_outdelay after OUT_DELAY; + EMAC0PHYTXEN_out <= EMAC0PHYTXEN_outdelay after OUT_DELAY; + EMAC0PHYTXER_out <= EMAC0PHYTXER_outdelay after OUT_DELAY; + EMAC0SPEEDIS10100_out <= EMAC0SPEEDIS10100_outdelay after OUT_DELAY; + EMAC1CLIENTANINTERRUPT_out <= EMAC1CLIENTANINTERRUPT_outdelay after OUT_DELAY; + EMAC1CLIENTRXBADFRAME_out <= EMAC1CLIENTRXBADFRAME_outdelay after OUT_DELAY; + EMAC1CLIENTRXDVLDMSW_out <= EMAC1CLIENTRXDVLDMSW_outdelay after OUT_DELAY; + EMAC1CLIENTRXDVLD_out <= EMAC1CLIENTRXDVLD_outdelay after OUT_DELAY; + EMAC1CLIENTRXD_out <= EMAC1CLIENTRXD_outdelay after OUT_DELAY; + EMAC1CLIENTRXFRAMEDROP_out <= EMAC1CLIENTRXFRAMEDROP_outdelay after OUT_DELAY; + EMAC1CLIENTRXGOODFRAME_out <= EMAC1CLIENTRXGOODFRAME_outdelay after OUT_DELAY; + EMAC1CLIENTRXSTATSBYTEVLD_out <= EMAC1CLIENTRXSTATSBYTEVLD_outdelay after OUT_DELAY; + EMAC1CLIENTRXSTATSVLD_out <= EMAC1CLIENTRXSTATSVLD_outdelay after OUT_DELAY; + EMAC1CLIENTRXSTATS_out <= EMAC1CLIENTRXSTATS_outdelay after OUT_DELAY; + EMAC1CLIENTTXACK_out <= EMAC1CLIENTTXACK_outdelay after OUT_DELAY; + EMAC1CLIENTTXCOLLISION_out <= EMAC1CLIENTTXCOLLISION_outdelay after OUT_DELAY; + EMAC1CLIENTTXRETRANSMIT_out <= EMAC1CLIENTTXRETRANSMIT_outdelay after OUT_DELAY; + EMAC1CLIENTTXSTATSBYTEVLD_out <= EMAC1CLIENTTXSTATSBYTEVLD_outdelay after OUT_DELAY; + EMAC1CLIENTTXSTATSVLD_out <= EMAC1CLIENTTXSTATSVLD_outdelay after OUT_DELAY; + EMAC1CLIENTTXSTATS_out <= EMAC1CLIENTTXSTATS_outdelay after OUT_DELAY; + EMAC1PHYENCOMMAALIGN_out <= EMAC1PHYENCOMMAALIGN_outdelay after OUT_DELAY; + EMAC1PHYLOOPBACKMSB_out <= EMAC1PHYLOOPBACKMSB_outdelay after OUT_DELAY; + EMAC1PHYMDOUT_out <= EMAC1PHYMDOUT_outdelay after OUT_DELAY; + EMAC1PHYMDTRI_out <= EMAC1PHYMDTRI_outdelay after OUT_DELAY; + EMAC1PHYMGTRXRESET_out <= EMAC1PHYMGTRXRESET_outdelay after OUT_DELAY; + EMAC1PHYMGTTXRESET_out <= EMAC1PHYMGTTXRESET_outdelay after OUT_DELAY; + EMAC1PHYPOWERDOWN_out <= EMAC1PHYPOWERDOWN_outdelay after OUT_DELAY; + EMAC1PHYSYNCACQSTATUS_out <= EMAC1PHYSYNCACQSTATUS_outdelay after OUT_DELAY; + EMAC1PHYTXCHARDISPMODE_out <= EMAC1PHYTXCHARDISPMODE_outdelay after OUT_DELAY; + EMAC1PHYTXCHARDISPVAL_out <= EMAC1PHYTXCHARDISPVAL_outdelay after OUT_DELAY; + EMAC1PHYTXCHARISK_out <= EMAC1PHYTXCHARISK_outdelay after OUT_DELAY; + EMAC1PHYTXD_out <= EMAC1PHYTXD_outdelay after OUT_DELAY; + EMAC1PHYTXEN_out <= EMAC1PHYTXEN_outdelay after OUT_DELAY; + EMAC1PHYTXER_out <= EMAC1PHYTXER_outdelay after OUT_DELAY; + EMAC1SPEEDIS10100_out <= EMAC1SPEEDIS10100_outdelay after OUT_DELAY; + EMACDCRACK_out <= EMACDCRACK_outdelay after OUT_DELAY; + EMACDCRDBUS_out <= EMACDCRDBUS_outdelay after OUT_DELAY; + HOSTMIIMRDY_out <= HOSTMIIMRDY_outdelay after OUT_DELAY; + HOSTRDDATA_out <= HOSTRDDATA_outdelay after OUT_DELAY; + + CLIENTEMAC0RXCLIENTCLKIN_ipd <= CLIENTEMAC0RXCLIENTCLKIN after CLK_DELAY; + CLIENTEMAC0TXCLIENTCLKIN_ipd <= CLIENTEMAC0TXCLIENTCLKIN after CLK_DELAY; + CLIENTEMAC1RXCLIENTCLKIN_ipd <= CLIENTEMAC1RXCLIENTCLKIN after CLK_DELAY; + CLIENTEMAC1TXCLIENTCLKIN_ipd <= CLIENTEMAC1TXCLIENTCLKIN after CLK_DELAY; + DCREMACCLK_ipd <= DCREMACCLK after CLK_DELAY; + HOSTCLK_ipd <= HOSTCLK after CLK_DELAY; + PHYEMAC0GTXCLK_ipd <= PHYEMAC0GTXCLK after CLK_DELAY; + PHYEMAC0MCLKIN_ipd <= PHYEMAC0MCLKIN after CLK_DELAY; + PHYEMAC0MIITXCLK_ipd <= PHYEMAC0MIITXCLK after EMAC0MIITXCLK_DELAY; + PHYEMAC0RXCLK_ipd <= PHYEMAC0RXCLK after CLK_DELAY; + PHYEMAC0TXGMIIMIICLKIN_ipd <= PHYEMAC0TXGMIIMIICLKIN after CLK_DELAY; + PHYEMAC1GTXCLK_ipd <= PHYEMAC1GTXCLK after CLK_DELAY; + PHYEMAC1MCLKIN_ipd <= PHYEMAC1MCLKIN after CLK_DELAY; + PHYEMAC1MIITXCLK_ipd <= PHYEMAC1MIITXCLK after EMAC1MIITXCLK_DELAY; + PHYEMAC1RXCLK_ipd <= PHYEMAC1RXCLK after CLK_DELAY; + PHYEMAC1TXGMIIMIICLKIN_ipd <= PHYEMAC1TXGMIIMIICLKIN after CLK_DELAY; + + CLIENTEMAC0DCMLOCKED_ipd <= CLIENTEMAC0DCMLOCKED after CLK_DELAY; + CLIENTEMAC0PAUSEREQ_ipd <= CLIENTEMAC0PAUSEREQ after CLK_DELAY; + CLIENTEMAC0PAUSEVAL_ipd <= CLIENTEMAC0PAUSEVAL after CLK_DELAY; + CLIENTEMAC0TXDVLDMSW_ipd <= CLIENTEMAC0TXDVLDMSW after CLK_DELAY; + CLIENTEMAC0TXDVLD_ipd <= CLIENTEMAC0TXDVLD after CLK_DELAY; + CLIENTEMAC0TXD_ipd <= CLIENTEMAC0TXD after CLK_DELAY; + CLIENTEMAC0TXFIRSTBYTE_ipd <= CLIENTEMAC0TXFIRSTBYTE after CLK_DELAY; + CLIENTEMAC0TXIFGDELAY_ipd <= CLIENTEMAC0TXIFGDELAY after CLK_DELAY; + CLIENTEMAC0TXUNDERRUN_ipd <= CLIENTEMAC0TXUNDERRUN after CLK_DELAY; + CLIENTEMAC1DCMLOCKED_ipd <= CLIENTEMAC1DCMLOCKED after CLK_DELAY; + CLIENTEMAC1PAUSEREQ_ipd <= CLIENTEMAC1PAUSEREQ after CLK_DELAY; + CLIENTEMAC1PAUSEVAL_ipd <= CLIENTEMAC1PAUSEVAL after CLK_DELAY; + CLIENTEMAC1TXDVLDMSW_ipd <= CLIENTEMAC1TXDVLDMSW after CLK_DELAY; + CLIENTEMAC1TXDVLD_ipd <= CLIENTEMAC1TXDVLD after CLK_DELAY; + CLIENTEMAC1TXD_ipd <= CLIENTEMAC1TXD after CLK_DELAY; + CLIENTEMAC1TXFIRSTBYTE_ipd <= CLIENTEMAC1TXFIRSTBYTE after CLK_DELAY; + CLIENTEMAC1TXIFGDELAY_ipd <= CLIENTEMAC1TXIFGDELAY after CLK_DELAY; + CLIENTEMAC1TXUNDERRUN_ipd <= CLIENTEMAC1TXUNDERRUN after CLK_DELAY; + DCREMACABUS_ipd <= DCREMACABUS after CLK_DELAY; + DCREMACDBUS_ipd <= DCREMACDBUS after CLK_DELAY; + DCREMACENABLE_ipd <= DCREMACENABLE after CLK_DELAY; + DCREMACREAD_ipd <= DCREMACREAD after CLK_DELAY; + DCREMACWRITE_ipd <= DCREMACWRITE after CLK_DELAY; + HOSTADDR_ipd <= HOSTADDR after CLK_DELAY; + HOSTEMAC1SEL_ipd <= HOSTEMAC1SEL after CLK_DELAY; + HOSTMIIMSEL_ipd <= HOSTMIIMSEL after CLK_DELAY; + HOSTOPCODE_ipd <= HOSTOPCODE after CLK_DELAY; + HOSTREQ_ipd <= HOSTREQ after CLK_DELAY; + HOSTWRDATA_ipd <= HOSTWRDATA after CLK_DELAY; + PHYEMAC0COL_ipd <= PHYEMAC0COL after CLK_DELAY; + PHYEMAC0CRS_ipd <= PHYEMAC0CRS after CLK_DELAY; + PHYEMAC0MDIN_ipd <= PHYEMAC0MDIN after CLK_DELAY; + PHYEMAC0PHYAD_ipd <= PHYEMAC0PHYAD after CLK_DELAY; + PHYEMAC0RXBUFERR_ipd <= PHYEMAC0RXBUFERR after CLK_DELAY; + PHYEMAC0RXBUFSTATUS_ipd <= PHYEMAC0RXBUFSTATUS after CLK_DELAY; + PHYEMAC0RXCHARISCOMMA_ipd <= PHYEMAC0RXCHARISCOMMA after CLK_DELAY; + PHYEMAC0RXCHARISK_ipd <= PHYEMAC0RXCHARISK after CLK_DELAY; + PHYEMAC0RXCHECKINGCRC_ipd <= PHYEMAC0RXCHECKINGCRC after CLK_DELAY; + PHYEMAC0RXCLKCORCNT_ipd <= PHYEMAC0RXCLKCORCNT after CLK_DELAY; + PHYEMAC0RXCOMMADET_ipd <= PHYEMAC0RXCOMMADET after CLK_DELAY; + PHYEMAC0RXDISPERR_ipd <= PHYEMAC0RXDISPERR after CLK_DELAY; + PHYEMAC0RXDV_ipd <= PHYEMAC0RXDV after CLK_DELAY; + PHYEMAC0RXD_ipd <= PHYEMAC0RXD after CLK_DELAY; + PHYEMAC0RXER_ipd <= PHYEMAC0RXER after CLK_DELAY; + PHYEMAC0RXLOSSOFSYNC_ipd <= PHYEMAC0RXLOSSOFSYNC after CLK_DELAY; + PHYEMAC0RXNOTINTABLE_ipd <= PHYEMAC0RXNOTINTABLE after CLK_DELAY; + PHYEMAC0RXRUNDISP_ipd <= PHYEMAC0RXRUNDISP after CLK_DELAY; + PHYEMAC0SIGNALDET_ipd <= PHYEMAC0SIGNALDET after CLK_DELAY; + PHYEMAC0TXBUFERR_ipd <= PHYEMAC0TXBUFERR after CLK_DELAY; + PHYEMAC1COL_ipd <= PHYEMAC1COL after CLK_DELAY; + PHYEMAC1CRS_ipd <= PHYEMAC1CRS after CLK_DELAY; + PHYEMAC1MDIN_ipd <= PHYEMAC1MDIN after CLK_DELAY; + PHYEMAC1PHYAD_ipd <= PHYEMAC1PHYAD after CLK_DELAY; + PHYEMAC1RXBUFERR_ipd <= PHYEMAC1RXBUFERR after CLK_DELAY; + PHYEMAC1RXBUFSTATUS_ipd <= PHYEMAC1RXBUFSTATUS after CLK_DELAY; + PHYEMAC1RXCHARISCOMMA_ipd <= PHYEMAC1RXCHARISCOMMA after CLK_DELAY; + PHYEMAC1RXCHARISK_ipd <= PHYEMAC1RXCHARISK after CLK_DELAY; + PHYEMAC1RXCHECKINGCRC_ipd <= PHYEMAC1RXCHECKINGCRC after CLK_DELAY; + PHYEMAC1RXCLKCORCNT_ipd <= PHYEMAC1RXCLKCORCNT after CLK_DELAY; + PHYEMAC1RXCOMMADET_ipd <= PHYEMAC1RXCOMMADET after CLK_DELAY; + PHYEMAC1RXDISPERR_ipd <= PHYEMAC1RXDISPERR after CLK_DELAY; + PHYEMAC1RXDV_ipd <= PHYEMAC1RXDV after CLK_DELAY; + PHYEMAC1RXD_ipd <= PHYEMAC1RXD after CLK_DELAY; + PHYEMAC1RXER_ipd <= PHYEMAC1RXER after CLK_DELAY; + PHYEMAC1RXLOSSOFSYNC_ipd <= PHYEMAC1RXLOSSOFSYNC after CLK_DELAY; + PHYEMAC1RXNOTINTABLE_ipd <= PHYEMAC1RXNOTINTABLE after CLK_DELAY; + PHYEMAC1RXRUNDISP_ipd <= PHYEMAC1RXRUNDISP after CLK_DELAY; + PHYEMAC1SIGNALDET_ipd <= PHYEMAC1SIGNALDET after CLK_DELAY; + PHYEMAC1TXBUFERR_ipd <= PHYEMAC1TXBUFERR after CLK_DELAY; + RESET_ipd <= RESET after CLK_DELAY; + + CLIENTEMAC0RXCLIENTCLKIN_indelay <= CLIENTEMAC0RXCLIENTCLKIN_ipd after CLK_DELAY; + CLIENTEMAC0TXCLIENTCLKIN_indelay <= CLIENTEMAC0TXCLIENTCLKIN_ipd after CLK_DELAY; + CLIENTEMAC1RXCLIENTCLKIN_indelay <= CLIENTEMAC1RXCLIENTCLKIN_ipd after CLK_DELAY; + CLIENTEMAC1TXCLIENTCLKIN_indelay <= CLIENTEMAC1TXCLIENTCLKIN_ipd after CLK_DELAY; + DCREMACCLK_indelay <= DCREMACCLK_ipd after CLK_DELAY; + HOSTCLK_indelay <= HOSTCLK_ipd after CLK_DELAY; + PHYEMAC0GTXCLK_indelay <= PHYEMAC0GTXCLK_ipd after CLK_DELAY; + PHYEMAC0MCLKIN_indelay <= PHYEMAC0MCLKIN_ipd after CLK_DELAY; + PHYEMAC0MIITXCLK_indelay <= PHYEMAC0MIITXCLK_ipd after EMAC0MIITXCLK_DELAY; + PHYEMAC0RXCLK_indelay <= PHYEMAC0RXCLK_ipd after CLK_DELAY; + PHYEMAC0TXGMIIMIICLKIN_indelay <= PHYEMAC0TXGMIIMIICLKIN_ipd after CLK_DELAY; + PHYEMAC1GTXCLK_indelay <= PHYEMAC1GTXCLK_ipd after CLK_DELAY; + PHYEMAC1MCLKIN_indelay <= PHYEMAC1MCLKIN_ipd after CLK_DELAY; + PHYEMAC1MIITXCLK_indelay <= PHYEMAC1MIITXCLK_ipd after EMAC1MIITXCLK_DELAY; + PHYEMAC1RXCLK_indelay <= PHYEMAC1RXCLK_ipd after CLK_DELAY; + PHYEMAC1TXGMIIMIICLKIN_indelay <= PHYEMAC1TXGMIIMIICLKIN_ipd after CLK_DELAY; + + CLIENTEMAC0DCMLOCKED_indelay <= CLIENTEMAC0DCMLOCKED_ipd after IN_DELAY; + CLIENTEMAC0PAUSEREQ_indelay <= CLIENTEMAC0PAUSEREQ_ipd after IN_DELAY; + CLIENTEMAC0PAUSEVAL_indelay <= CLIENTEMAC0PAUSEVAL_ipd after IN_DELAY; + CLIENTEMAC0TXDVLDMSW_indelay <= CLIENTEMAC0TXDVLDMSW_ipd after IN_DELAY; + CLIENTEMAC0TXDVLD_indelay <= CLIENTEMAC0TXDVLD_ipd after IN_DELAY; + CLIENTEMAC0TXD_indelay <= CLIENTEMAC0TXD_ipd after IN_DELAY; + CLIENTEMAC0TXFIRSTBYTE_indelay <= CLIENTEMAC0TXFIRSTBYTE_ipd after IN_DELAY; + CLIENTEMAC0TXIFGDELAY_indelay <= CLIENTEMAC0TXIFGDELAY_ipd after IN_DELAY; + CLIENTEMAC0TXUNDERRUN_indelay <= CLIENTEMAC0TXUNDERRUN_ipd after IN_DELAY; + CLIENTEMAC1DCMLOCKED_indelay <= CLIENTEMAC1DCMLOCKED_ipd after IN_DELAY; + CLIENTEMAC1PAUSEREQ_indelay <= CLIENTEMAC1PAUSEREQ_ipd after IN_DELAY; + CLIENTEMAC1PAUSEVAL_indelay <= CLIENTEMAC1PAUSEVAL_ipd after IN_DELAY; + CLIENTEMAC1TXDVLDMSW_indelay <= CLIENTEMAC1TXDVLDMSW_ipd after IN_DELAY; + CLIENTEMAC1TXDVLD_indelay <= CLIENTEMAC1TXDVLD_ipd after IN_DELAY; + CLIENTEMAC1TXD_indelay <= CLIENTEMAC1TXD_ipd after IN_DELAY; + CLIENTEMAC1TXFIRSTBYTE_indelay <= CLIENTEMAC1TXFIRSTBYTE_ipd after IN_DELAY; + CLIENTEMAC1TXIFGDELAY_indelay <= CLIENTEMAC1TXIFGDELAY_ipd after IN_DELAY; + CLIENTEMAC1TXUNDERRUN_indelay <= CLIENTEMAC1TXUNDERRUN_ipd after IN_DELAY; + DCREMACABUS_indelay <= DCREMACABUS_ipd after IN_DELAY; + DCREMACDBUS_indelay <= DCREMACDBUS_ipd after IN_DELAY; + DCREMACENABLE_indelay <= DCREMACENABLE_ipd after IN_DELAY; + DCREMACREAD_indelay <= DCREMACREAD_ipd after IN_DELAY; + DCREMACWRITE_indelay <= DCREMACWRITE_ipd after IN_DELAY; + HOSTADDR_indelay <= HOSTADDR_ipd after IN_DELAY; + HOSTEMAC1SEL_indelay <= HOSTEMAC1SEL_ipd after IN_DELAY; + HOSTMIIMSEL_indelay <= HOSTMIIMSEL_ipd after IN_DELAY; + HOSTOPCODE_indelay <= HOSTOPCODE_ipd after IN_DELAY; + HOSTREQ_indelay <= HOSTREQ_ipd after IN_DELAY; + HOSTWRDATA_indelay <= HOSTWRDATA_ipd after IN_DELAY; + PHYEMAC0COL_indelay <= PHYEMAC0COL_ipd after IN_DELAY; + PHYEMAC0CRS_indelay <= PHYEMAC0CRS_ipd after IN_DELAY; + PHYEMAC0MDIN_indelay <= PHYEMAC0MDIN_ipd after IN_DELAY; + PHYEMAC0PHYAD_indelay <= PHYEMAC0PHYAD_ipd after IN_DELAY; + PHYEMAC0RXBUFERR_indelay <= PHYEMAC0RXBUFERR_ipd after IN_DELAY; + PHYEMAC0RXBUFSTATUS_indelay <= PHYEMAC0RXBUFSTATUS_ipd after IN_DELAY; + PHYEMAC0RXCHARISCOMMA_indelay <= PHYEMAC0RXCHARISCOMMA_ipd after IN_DELAY; + PHYEMAC0RXCHARISK_indelay <= PHYEMAC0RXCHARISK_ipd after IN_DELAY; + PHYEMAC0RXCHECKINGCRC_indelay <= PHYEMAC0RXCHECKINGCRC_ipd after IN_DELAY; + PHYEMAC0RXCLKCORCNT_indelay <= PHYEMAC0RXCLKCORCNT_ipd after IN_DELAY; + PHYEMAC0RXCOMMADET_indelay <= PHYEMAC0RXCOMMADET_ipd after IN_DELAY; + PHYEMAC0RXDISPERR_indelay <= PHYEMAC0RXDISPERR_ipd after IN_DELAY; + PHYEMAC0RXDV_indelay <= PHYEMAC0RXDV_ipd after IN_DELAY; + PHYEMAC0RXD_indelay <= PHYEMAC0RXD_ipd after IN_DELAY; + PHYEMAC0RXER_indelay <= PHYEMAC0RXER_ipd after IN_DELAY; + PHYEMAC0RXLOSSOFSYNC_indelay <= PHYEMAC0RXLOSSOFSYNC_ipd after IN_DELAY; + PHYEMAC0RXNOTINTABLE_indelay <= PHYEMAC0RXNOTINTABLE_ipd after IN_DELAY; + PHYEMAC0RXRUNDISP_indelay <= PHYEMAC0RXRUNDISP_ipd after IN_DELAY; + PHYEMAC0SIGNALDET_indelay <= PHYEMAC0SIGNALDET_ipd after IN_DELAY; + PHYEMAC0TXBUFERR_indelay <= PHYEMAC0TXBUFERR_ipd after IN_DELAY; + PHYEMAC1COL_indelay <= PHYEMAC1COL_ipd after IN_DELAY; + PHYEMAC1CRS_indelay <= PHYEMAC1CRS_ipd after IN_DELAY; + PHYEMAC1MDIN_indelay <= PHYEMAC1MDIN_ipd after IN_DELAY; + PHYEMAC1PHYAD_indelay <= PHYEMAC1PHYAD_ipd after IN_DELAY; + PHYEMAC1RXBUFERR_indelay <= PHYEMAC1RXBUFERR_ipd after IN_DELAY; + PHYEMAC1RXBUFSTATUS_indelay <= PHYEMAC1RXBUFSTATUS_ipd after IN_DELAY; + PHYEMAC1RXCHARISCOMMA_indelay <= PHYEMAC1RXCHARISCOMMA_ipd after IN_DELAY; + PHYEMAC1RXCHARISK_indelay <= PHYEMAC1RXCHARISK_ipd after IN_DELAY; + PHYEMAC1RXCHECKINGCRC_indelay <= PHYEMAC1RXCHECKINGCRC_ipd after IN_DELAY; + PHYEMAC1RXCLKCORCNT_indelay <= PHYEMAC1RXCLKCORCNT_ipd after IN_DELAY; + PHYEMAC1RXCOMMADET_indelay <= PHYEMAC1RXCOMMADET_ipd after IN_DELAY; + PHYEMAC1RXDISPERR_indelay <= PHYEMAC1RXDISPERR_ipd after IN_DELAY; + PHYEMAC1RXDV_indelay <= PHYEMAC1RXDV_ipd after IN_DELAY; + PHYEMAC1RXD_indelay <= PHYEMAC1RXD_ipd after IN_DELAY; + PHYEMAC1RXER_indelay <= PHYEMAC1RXER_ipd after IN_DELAY; + PHYEMAC1RXLOSSOFSYNC_indelay <= PHYEMAC1RXLOSSOFSYNC_ipd after IN_DELAY; + PHYEMAC1RXNOTINTABLE_indelay <= PHYEMAC1RXNOTINTABLE_ipd after IN_DELAY; + PHYEMAC1RXRUNDISP_indelay <= PHYEMAC1RXRUNDISP_ipd after IN_DELAY; + PHYEMAC1SIGNALDET_indelay <= PHYEMAC1SIGNALDET_ipd after IN_DELAY; + PHYEMAC1TXBUFERR_indelay <= PHYEMAC1TXBUFERR_ipd after IN_DELAY; + RESET_indelay <= RESET_ipd after IN_DELAY; + + temac_swift_bw_1 : TEMAC_SWIFT_BUS + port map ( + EMAC0_1000BASEX_ENABLE => EMAC0_1000BASEX_ENABLE_BINARY, + EMAC0_ADDRFILTER_ENABLE => EMAC0_ADDRFILTER_ENABLE_BINARY, + EMAC0_BYTEPHY => EMAC0_BYTEPHY_BINARY, + EMAC0_CONFIGVEC_79 => EMAC0_CONFIGVEC_79_BINARY, + EMAC0_DCRBASEADDR => EMAC0_DCRBASEADDR_BINARY, + EMAC0_GTLOOPBACK => EMAC0_GTLOOPBACK_BINARY, + EMAC0_HOST_ENABLE => EMAC0_HOST_ENABLE_BINARY, + EMAC0_LINKTIMERVAL => EMAC0_LINKTIMERVAL_BINARY, + EMAC0_LTCHECK_DISABLE => EMAC0_LTCHECK_DISABLE_BINARY, + EMAC0_MDIO_ENABLE => EMAC0_MDIO_ENABLE_BINARY, + EMAC0_PAUSEADDR => EMAC0_PAUSEADDR_BINARY, + EMAC0_PHYINITAUTONEG_ENABLE => EMAC0_PHYINITAUTONEG_ENABLE_BINARY, + EMAC0_PHYISOLATE => EMAC0_PHYISOLATE_BINARY, + EMAC0_PHYLOOPBACKMSB => EMAC0_PHYLOOPBACKMSB_BINARY, + EMAC0_PHYPOWERDOWN => EMAC0_PHYPOWERDOWN_BINARY, + EMAC0_PHYRESET => EMAC0_PHYRESET_BINARY, + EMAC0_RGMII_ENABLE => EMAC0_RGMII_ENABLE_BINARY, + EMAC0_RX16BITCLIENT_ENABLE => EMAC0_RX16BITCLIENT_ENABLE_BINARY, + EMAC0_RXFLOWCTRL_ENABLE => EMAC0_RXFLOWCTRL_ENABLE_BINARY, + EMAC0_RXHALFDUPLEX => EMAC0_RXHALFDUPLEX_BINARY, + EMAC0_RXINBANDFCS_ENABLE => EMAC0_RXINBANDFCS_ENABLE_BINARY, + EMAC0_RXJUMBOFRAME_ENABLE => EMAC0_RXJUMBOFRAME_ENABLE_BINARY, + EMAC0_RXRESET => EMAC0_RXRESET_BINARY, + EMAC0_RXVLAN_ENABLE => EMAC0_RXVLAN_ENABLE_BINARY, + EMAC0_RX_ENABLE => EMAC0_RX_ENABLE_BINARY, + EMAC0_SGMII_ENABLE => EMAC0_SGMII_ENABLE_BINARY, + EMAC0_SPEED_LSB => EMAC0_SPEED_LSB_BINARY, + EMAC0_SPEED_MSB => EMAC0_SPEED_MSB_BINARY, + EMAC0_TX16BITCLIENT_ENABLE => EMAC0_TX16BITCLIENT_ENABLE_BINARY, + EMAC0_TXFLOWCTRL_ENABLE => EMAC0_TXFLOWCTRL_ENABLE_BINARY, + EMAC0_TXHALFDUPLEX => EMAC0_TXHALFDUPLEX_BINARY, + EMAC0_TXIFGADJUST_ENABLE => EMAC0_TXIFGADJUST_ENABLE_BINARY, + EMAC0_TXINBANDFCS_ENABLE => EMAC0_TXINBANDFCS_ENABLE_BINARY, + EMAC0_TXJUMBOFRAME_ENABLE => EMAC0_TXJUMBOFRAME_ENABLE_BINARY, + EMAC0_TXRESET => EMAC0_TXRESET_BINARY, + EMAC0_TXVLAN_ENABLE => EMAC0_TXVLAN_ENABLE_BINARY, + EMAC0_TX_ENABLE => EMAC0_TX_ENABLE_BINARY, + EMAC0_UNICASTADDR => EMAC0_UNICASTADDR_BINARY, + EMAC0_UNIDIRECTION_ENABLE => EMAC0_UNIDIRECTION_ENABLE_BINARY, + EMAC0_USECLKEN => EMAC0_USECLKEN_BINARY, + EMAC1_1000BASEX_ENABLE => EMAC1_1000BASEX_ENABLE_BINARY, + EMAC1_ADDRFILTER_ENABLE => EMAC1_ADDRFILTER_ENABLE_BINARY, + EMAC1_BYTEPHY => EMAC1_BYTEPHY_BINARY, + EMAC1_CONFIGVEC_79 => EMAC1_CONFIGVEC_79_BINARY, + EMAC1_DCRBASEADDR => EMAC1_DCRBASEADDR_BINARY, + EMAC1_GTLOOPBACK => EMAC1_GTLOOPBACK_BINARY, + EMAC1_HOST_ENABLE => EMAC1_HOST_ENABLE_BINARY, + EMAC1_LINKTIMERVAL => EMAC1_LINKTIMERVAL_BINARY, + EMAC1_LTCHECK_DISABLE => EMAC1_LTCHECK_DISABLE_BINARY, + EMAC1_MDIO_ENABLE => EMAC1_MDIO_ENABLE_BINARY, + EMAC1_PAUSEADDR => EMAC1_PAUSEADDR_BINARY, + EMAC1_PHYINITAUTONEG_ENABLE => EMAC1_PHYINITAUTONEG_ENABLE_BINARY, + EMAC1_PHYISOLATE => EMAC1_PHYISOLATE_BINARY, + EMAC1_PHYLOOPBACKMSB => EMAC1_PHYLOOPBACKMSB_BINARY, + EMAC1_PHYPOWERDOWN => EMAC1_PHYPOWERDOWN_BINARY, + EMAC1_PHYRESET => EMAC1_PHYRESET_BINARY, + EMAC1_RGMII_ENABLE => EMAC1_RGMII_ENABLE_BINARY, + EMAC1_RX16BITCLIENT_ENABLE => EMAC1_RX16BITCLIENT_ENABLE_BINARY, + EMAC1_RXFLOWCTRL_ENABLE => EMAC1_RXFLOWCTRL_ENABLE_BINARY, + EMAC1_RXHALFDUPLEX => EMAC1_RXHALFDUPLEX_BINARY, + EMAC1_RXINBANDFCS_ENABLE => EMAC1_RXINBANDFCS_ENABLE_BINARY, + EMAC1_RXJUMBOFRAME_ENABLE => EMAC1_RXJUMBOFRAME_ENABLE_BINARY, + EMAC1_RXRESET => EMAC1_RXRESET_BINARY, + EMAC1_RXVLAN_ENABLE => EMAC1_RXVLAN_ENABLE_BINARY, + EMAC1_RX_ENABLE => EMAC1_RX_ENABLE_BINARY, + EMAC1_SGMII_ENABLE => EMAC1_SGMII_ENABLE_BINARY, + EMAC1_SPEED_LSB => EMAC1_SPEED_LSB_BINARY, + EMAC1_SPEED_MSB => EMAC1_SPEED_MSB_BINARY, + EMAC1_TX16BITCLIENT_ENABLE => EMAC1_TX16BITCLIENT_ENABLE_BINARY, + EMAC1_TXFLOWCTRL_ENABLE => EMAC1_TXFLOWCTRL_ENABLE_BINARY, + EMAC1_TXHALFDUPLEX => EMAC1_TXHALFDUPLEX_BINARY, + EMAC1_TXIFGADJUST_ENABLE => EMAC1_TXIFGADJUST_ENABLE_BINARY, + EMAC1_TXINBANDFCS_ENABLE => EMAC1_TXINBANDFCS_ENABLE_BINARY, + EMAC1_TXJUMBOFRAME_ENABLE => EMAC1_TXJUMBOFRAME_ENABLE_BINARY, + EMAC1_TXRESET => EMAC1_TXRESET_BINARY, + EMAC1_TXVLAN_ENABLE => EMAC1_TXVLAN_ENABLE_BINARY, + EMAC1_TX_ENABLE => EMAC1_TX_ENABLE_BINARY, + EMAC1_UNICASTADDR => EMAC1_UNICASTADDR_BINARY, + EMAC1_UNIDIRECTION_ENABLE => EMAC1_UNIDIRECTION_ENABLE_BINARY, + EMAC1_USECLKEN => EMAC1_USECLKEN_BINARY, + + DCRHOSTDONEIR => DCRHOSTDONEIR_outdelay, + EMAC0CLIENTANINTERRUPT => EMAC0CLIENTANINTERRUPT_outdelay, + EMAC0CLIENTRXBADFRAME => EMAC0CLIENTRXBADFRAME_outdelay, + EMAC0CLIENTRXCLIENTCLKOUT => EMAC0CLIENTRXCLIENTCLKOUT_outdelay, + EMAC0CLIENTRXD => EMAC0CLIENTRXD_outdelay, + EMAC0CLIENTRXDVLD => EMAC0CLIENTRXDVLD_outdelay, + EMAC0CLIENTRXDVLDMSW => EMAC0CLIENTRXDVLDMSW_outdelay, + EMAC0CLIENTRXFRAMEDROP => EMAC0CLIENTRXFRAMEDROP_outdelay, + EMAC0CLIENTRXGOODFRAME => EMAC0CLIENTRXGOODFRAME_outdelay, + EMAC0CLIENTRXSTATS => EMAC0CLIENTRXSTATS_outdelay, + EMAC0CLIENTRXSTATSBYTEVLD => EMAC0CLIENTRXSTATSBYTEVLD_outdelay, + EMAC0CLIENTRXSTATSVLD => EMAC0CLIENTRXSTATSVLD_outdelay, + EMAC0CLIENTTXACK => EMAC0CLIENTTXACK_outdelay, + EMAC0CLIENTTXCLIENTCLKOUT => EMAC0CLIENTTXCLIENTCLKOUT_outdelay, + EMAC0CLIENTTXCOLLISION => EMAC0CLIENTTXCOLLISION_outdelay, + EMAC0CLIENTTXRETRANSMIT => EMAC0CLIENTTXRETRANSMIT_outdelay, + EMAC0CLIENTTXSTATS => EMAC0CLIENTTXSTATS_outdelay, + EMAC0CLIENTTXSTATSBYTEVLD => EMAC0CLIENTTXSTATSBYTEVLD_outdelay, + EMAC0CLIENTTXSTATSVLD => EMAC0CLIENTTXSTATSVLD_outdelay, + EMAC0PHYENCOMMAALIGN => EMAC0PHYENCOMMAALIGN_outdelay, + EMAC0PHYLOOPBACKMSB => EMAC0PHYLOOPBACKMSB_outdelay, + EMAC0PHYMCLKOUT => EMAC0PHYMCLKOUT_outdelay, + EMAC0PHYMDOUT => EMAC0PHYMDOUT_outdelay, + EMAC0PHYMDTRI => EMAC0PHYMDTRI_outdelay, + EMAC0PHYMGTRXRESET => EMAC0PHYMGTRXRESET_outdelay, + EMAC0PHYMGTTXRESET => EMAC0PHYMGTTXRESET_outdelay, + EMAC0PHYPOWERDOWN => EMAC0PHYPOWERDOWN_outdelay, + EMAC0PHYSYNCACQSTATUS => EMAC0PHYSYNCACQSTATUS_outdelay, + EMAC0PHYTXCHARDISPMODE => EMAC0PHYTXCHARDISPMODE_outdelay, + EMAC0PHYTXCHARDISPVAL => EMAC0PHYTXCHARDISPVAL_outdelay, + EMAC0PHYTXCHARISK => EMAC0PHYTXCHARISK_outdelay, + EMAC0PHYTXCLK => EMAC0PHYTXCLK_outdelay, + EMAC0PHYTXD => EMAC0PHYTXD_outdelay, + EMAC0PHYTXEN => EMAC0PHYTXEN_outdelay, + EMAC0PHYTXER => EMAC0PHYTXER_outdelay, + EMAC0PHYTXGMIIMIICLKOUT => EMAC0PHYTXGMIIMIICLKOUT_outdelay, + EMAC0SPEEDIS10100 => EMAC0SPEEDIS10100_outdelay, + EMAC1CLIENTANINTERRUPT => EMAC1CLIENTANINTERRUPT_outdelay, + EMAC1CLIENTRXBADFRAME => EMAC1CLIENTRXBADFRAME_outdelay, + EMAC1CLIENTRXCLIENTCLKOUT => EMAC1CLIENTRXCLIENTCLKOUT_outdelay, + EMAC1CLIENTRXD => EMAC1CLIENTRXD_outdelay, + EMAC1CLIENTRXDVLD => EMAC1CLIENTRXDVLD_outdelay, + EMAC1CLIENTRXDVLDMSW => EMAC1CLIENTRXDVLDMSW_outdelay, + EMAC1CLIENTRXFRAMEDROP => EMAC1CLIENTRXFRAMEDROP_outdelay, + EMAC1CLIENTRXGOODFRAME => EMAC1CLIENTRXGOODFRAME_outdelay, + EMAC1CLIENTRXSTATS => EMAC1CLIENTRXSTATS_outdelay, + EMAC1CLIENTRXSTATSBYTEVLD => EMAC1CLIENTRXSTATSBYTEVLD_outdelay, + EMAC1CLIENTRXSTATSVLD => EMAC1CLIENTRXSTATSVLD_outdelay, + EMAC1CLIENTTXACK => EMAC1CLIENTTXACK_outdelay, + EMAC1CLIENTTXCLIENTCLKOUT => EMAC1CLIENTTXCLIENTCLKOUT_outdelay, + EMAC1CLIENTTXCOLLISION => EMAC1CLIENTTXCOLLISION_outdelay, + EMAC1CLIENTTXRETRANSMIT => EMAC1CLIENTTXRETRANSMIT_outdelay, + EMAC1CLIENTTXSTATS => EMAC1CLIENTTXSTATS_outdelay, + EMAC1CLIENTTXSTATSBYTEVLD => EMAC1CLIENTTXSTATSBYTEVLD_outdelay, + EMAC1CLIENTTXSTATSVLD => EMAC1CLIENTTXSTATSVLD_outdelay, + EMAC1PHYENCOMMAALIGN => EMAC1PHYENCOMMAALIGN_outdelay, + EMAC1PHYLOOPBACKMSB => EMAC1PHYLOOPBACKMSB_outdelay, + EMAC1PHYMCLKOUT => EMAC1PHYMCLKOUT_outdelay, + EMAC1PHYMDOUT => EMAC1PHYMDOUT_outdelay, + EMAC1PHYMDTRI => EMAC1PHYMDTRI_outdelay, + EMAC1PHYMGTRXRESET => EMAC1PHYMGTRXRESET_outdelay, + EMAC1PHYMGTTXRESET => EMAC1PHYMGTTXRESET_outdelay, + EMAC1PHYPOWERDOWN => EMAC1PHYPOWERDOWN_outdelay, + EMAC1PHYSYNCACQSTATUS => EMAC1PHYSYNCACQSTATUS_outdelay, + EMAC1PHYTXCHARDISPMODE => EMAC1PHYTXCHARDISPMODE_outdelay, + EMAC1PHYTXCHARDISPVAL => EMAC1PHYTXCHARDISPVAL_outdelay, + EMAC1PHYTXCHARISK => EMAC1PHYTXCHARISK_outdelay, + EMAC1PHYTXCLK => EMAC1PHYTXCLK_outdelay, + EMAC1PHYTXD => EMAC1PHYTXD_outdelay, + EMAC1PHYTXEN => EMAC1PHYTXEN_outdelay, + EMAC1PHYTXER => EMAC1PHYTXER_outdelay, + EMAC1PHYTXGMIIMIICLKOUT => EMAC1PHYTXGMIIMIICLKOUT_outdelay, + EMAC1SPEEDIS10100 => EMAC1SPEEDIS10100_outdelay, + EMACDCRACK => EMACDCRACK_outdelay, + EMACDCRDBUS => EMACDCRDBUS_outdelay, + HOSTMIIMRDY => HOSTMIIMRDY_outdelay, + HOSTRDDATA => HOSTRDDATA_outdelay, + + CLIENTEMAC0DCMLOCKED => CLIENTEMAC0DCMLOCKED_indelay, + CLIENTEMAC0PAUSEREQ => CLIENTEMAC0PAUSEREQ_indelay, + CLIENTEMAC0PAUSEVAL => CLIENTEMAC0PAUSEVAL_indelay, + CLIENTEMAC0RXCLIENTCLKIN => CLIENTEMAC0RXCLIENTCLKIN_indelay, + CLIENTEMAC0TXCLIENTCLKIN => CLIENTEMAC0TXCLIENTCLKIN_indelay, + CLIENTEMAC0TXD => CLIENTEMAC0TXD_indelay, + CLIENTEMAC0TXDVLD => CLIENTEMAC0TXDVLD_indelay, + CLIENTEMAC0TXDVLDMSW => CLIENTEMAC0TXDVLDMSW_indelay, + CLIENTEMAC0TXFIRSTBYTE => CLIENTEMAC0TXFIRSTBYTE_indelay, + CLIENTEMAC0TXIFGDELAY => CLIENTEMAC0TXIFGDELAY_indelay, + CLIENTEMAC0TXUNDERRUN => CLIENTEMAC0TXUNDERRUN_indelay, + CLIENTEMAC1DCMLOCKED => CLIENTEMAC1DCMLOCKED_indelay, + CLIENTEMAC1PAUSEREQ => CLIENTEMAC1PAUSEREQ_indelay, + CLIENTEMAC1PAUSEVAL => CLIENTEMAC1PAUSEVAL_indelay, + CLIENTEMAC1RXCLIENTCLKIN => CLIENTEMAC1RXCLIENTCLKIN_indelay, + CLIENTEMAC1TXCLIENTCLKIN => CLIENTEMAC1TXCLIENTCLKIN_indelay, + CLIENTEMAC1TXD => CLIENTEMAC1TXD_indelay, + CLIENTEMAC1TXDVLD => CLIENTEMAC1TXDVLD_indelay, + CLIENTEMAC1TXDVLDMSW => CLIENTEMAC1TXDVLDMSW_indelay, + CLIENTEMAC1TXFIRSTBYTE => CLIENTEMAC1TXFIRSTBYTE_indelay, + CLIENTEMAC1TXIFGDELAY => CLIENTEMAC1TXIFGDELAY_indelay, + CLIENTEMAC1TXUNDERRUN => CLIENTEMAC1TXUNDERRUN_indelay, + DCREMACABUS => DCREMACABUS_indelay, + DCREMACCLK => DCREMACCLK_indelay, + DCREMACDBUS => DCREMACDBUS_indelay, + DCREMACENABLE => DCREMACENABLE_indelay, + DCREMACREAD => DCREMACREAD_indelay, + DCREMACWRITE => DCREMACWRITE_indelay, + HOSTADDR => HOSTADDR_indelay, + HOSTCLK => HOSTCLK_indelay, + HOSTEMAC1SEL => HOSTEMAC1SEL_indelay, + HOSTMIIMSEL => HOSTMIIMSEL_indelay, + HOSTOPCODE => HOSTOPCODE_indelay, + HOSTREQ => HOSTREQ_indelay, + HOSTWRDATA => HOSTWRDATA_indelay, + PHYEMAC0COL => PHYEMAC0COL_indelay, + PHYEMAC0CRS => PHYEMAC0CRS_indelay, + PHYEMAC0GTXCLK => PHYEMAC0GTXCLK_indelay, + PHYEMAC0MCLKIN => PHYEMAC0MCLKIN_indelay, + PHYEMAC0MDIN => PHYEMAC0MDIN_indelay, + PHYEMAC0MIITXCLK => PHYEMAC0MIITXCLK_indelay, + PHYEMAC0PHYAD => PHYEMAC0PHYAD_indelay, + PHYEMAC0RXBUFERR => PHYEMAC0RXBUFERR_indelay, + PHYEMAC0RXBUFSTATUS => PHYEMAC0RXBUFSTATUS_indelay, + PHYEMAC0RXCHARISCOMMA => PHYEMAC0RXCHARISCOMMA_indelay, + PHYEMAC0RXCHARISK => PHYEMAC0RXCHARISK_indelay, + PHYEMAC0RXCHECKINGCRC => PHYEMAC0RXCHECKINGCRC_indelay, + PHYEMAC0RXCLK => PHYEMAC0RXCLK_indelay, + PHYEMAC0RXCLKCORCNT => PHYEMAC0RXCLKCORCNT_indelay, + PHYEMAC0RXCOMMADET => PHYEMAC0RXCOMMADET_indelay, + PHYEMAC0RXD => PHYEMAC0RXD_indelay, + PHYEMAC0RXDISPERR => PHYEMAC0RXDISPERR_indelay, + PHYEMAC0RXDV => PHYEMAC0RXDV_indelay, + PHYEMAC0RXER => PHYEMAC0RXER_indelay, + PHYEMAC0RXLOSSOFSYNC => PHYEMAC0RXLOSSOFSYNC_indelay, + PHYEMAC0RXNOTINTABLE => PHYEMAC0RXNOTINTABLE_indelay, + PHYEMAC0RXRUNDISP => PHYEMAC0RXRUNDISP_indelay, + PHYEMAC0SIGNALDET => PHYEMAC0SIGNALDET_indelay, + PHYEMAC0TXBUFERR => PHYEMAC0TXBUFERR_indelay, + PHYEMAC0TXGMIIMIICLKIN => PHYEMAC0TXGMIIMIICLKIN_indelay, + PHYEMAC1COL => PHYEMAC1COL_indelay, + PHYEMAC1CRS => PHYEMAC1CRS_indelay, + PHYEMAC1GTXCLK => PHYEMAC1GTXCLK_indelay, + PHYEMAC1MCLKIN => PHYEMAC1MCLKIN_indelay, + PHYEMAC1MDIN => PHYEMAC1MDIN_indelay, + PHYEMAC1MIITXCLK => PHYEMAC1MIITXCLK_indelay, + PHYEMAC1PHYAD => PHYEMAC1PHYAD_indelay, + PHYEMAC1RXBUFERR => PHYEMAC1RXBUFERR_indelay, + PHYEMAC1RXBUFSTATUS => PHYEMAC1RXBUFSTATUS_indelay, + PHYEMAC1RXCHARISCOMMA => PHYEMAC1RXCHARISCOMMA_indelay, + PHYEMAC1RXCHARISK => PHYEMAC1RXCHARISK_indelay, + PHYEMAC1RXCHECKINGCRC => PHYEMAC1RXCHECKINGCRC_indelay, + PHYEMAC1RXCLK => PHYEMAC1RXCLK_indelay, + PHYEMAC1RXCLKCORCNT => PHYEMAC1RXCLKCORCNT_indelay, + PHYEMAC1RXCOMMADET => PHYEMAC1RXCOMMADET_indelay, + PHYEMAC1RXD => PHYEMAC1RXD_indelay, + PHYEMAC1RXDISPERR => PHYEMAC1RXDISPERR_indelay, + PHYEMAC1RXDV => PHYEMAC1RXDV_indelay, + PHYEMAC1RXER => PHYEMAC1RXER_indelay, + PHYEMAC1RXLOSSOFSYNC => PHYEMAC1RXLOSSOFSYNC_indelay, + PHYEMAC1RXNOTINTABLE => PHYEMAC1RXNOTINTABLE_indelay, + PHYEMAC1RXRUNDISP => PHYEMAC1RXRUNDISP_indelay, + PHYEMAC1SIGNALDET => PHYEMAC1SIGNALDET_indelay, + PHYEMAC1TXBUFERR => PHYEMAC1TXBUFERR_indelay, + PHYEMAC1TXGMIIMIICLKIN => PHYEMAC1TXGMIIMIICLKIN_indelay, + RESET => RESET_indelay + ); + + INIPROC : process + begin + case EMAC0_RXHALFDUPLEX is + when FALSE => EMAC0_RXHALFDUPLEX_BINARY <= '0'; + when TRUE => EMAC0_RXHALFDUPLEX_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_RXHALFDUPLEX is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_RXVLAN_ENABLE is + when FALSE => EMAC0_RXVLAN_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_RXVLAN_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_RXVLAN_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_RX_ENABLE is + when FALSE => EMAC0_RX_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_RX_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_RX_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_RXINBANDFCS_ENABLE is + when FALSE => EMAC0_RXINBANDFCS_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_RXINBANDFCS_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_RXINBANDFCS_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_RXJUMBOFRAME_ENABLE is + when FALSE => EMAC0_RXJUMBOFRAME_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_RXJUMBOFRAME_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_RXJUMBOFRAME_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_RXRESET is + when FALSE => EMAC0_RXRESET_BINARY <= '0'; + when TRUE => EMAC0_RXRESET_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_RXRESET is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_TXIFGADJUST_ENABLE is + when FALSE => EMAC0_TXIFGADJUST_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_TXIFGADJUST_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_TXIFGADJUST_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_TXHALFDUPLEX is + when FALSE => EMAC0_TXHALFDUPLEX_BINARY <= '0'; + when TRUE => EMAC0_TXHALFDUPLEX_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_TXHALFDUPLEX is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_TXVLAN_ENABLE is + when FALSE => EMAC0_TXVLAN_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_TXVLAN_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_TXVLAN_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_TX_ENABLE is + when FALSE => EMAC0_TX_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_TX_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_TX_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_TXINBANDFCS_ENABLE is + when FALSE => EMAC0_TXINBANDFCS_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_TXINBANDFCS_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_TXINBANDFCS_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_TXJUMBOFRAME_ENABLE is + when FALSE => EMAC0_TXJUMBOFRAME_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_TXJUMBOFRAME_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_TXJUMBOFRAME_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_TXRESET is + when FALSE => EMAC0_TXRESET_BINARY <= '0'; + when TRUE => EMAC0_TXRESET_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_TXRESET is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_TXFLOWCTRL_ENABLE is + when FALSE => EMAC0_TXFLOWCTRL_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_TXFLOWCTRL_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_TXFLOWCTRL_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_RXFLOWCTRL_ENABLE is + when FALSE => EMAC0_RXFLOWCTRL_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_RXFLOWCTRL_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_RXFLOWCTRL_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_LTCHECK_DISABLE is + when FALSE => EMAC0_LTCHECK_DISABLE_BINARY <= '0'; + when TRUE => EMAC0_LTCHECK_DISABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_LTCHECK_DISABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_ADDRFILTER_ENABLE is + when FALSE => EMAC0_ADDRFILTER_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_ADDRFILTER_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_ADDRFILTER_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_RX16BITCLIENT_ENABLE is + when FALSE => EMAC0_RX16BITCLIENT_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_RX16BITCLIENT_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_RX16BITCLIENT_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_TX16BITCLIENT_ENABLE is + when FALSE => EMAC0_TX16BITCLIENT_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_TX16BITCLIENT_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_TX16BITCLIENT_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_HOST_ENABLE is + when FALSE => EMAC0_HOST_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_HOST_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_HOST_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_1000BASEX_ENABLE is + when FALSE => EMAC0_1000BASEX_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_1000BASEX_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_1000BASEX_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_SGMII_ENABLE is + when FALSE => EMAC0_SGMII_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_SGMII_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_SGMII_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_RGMII_ENABLE is + when FALSE => EMAC0_RGMII_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_RGMII_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_RGMII_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_SPEED_LSB is + when FALSE => EMAC0_SPEED_LSB_BINARY <= '0'; + when TRUE => EMAC0_SPEED_LSB_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_SPEED_LSB is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_SPEED_MSB is + when FALSE => EMAC0_SPEED_MSB_BINARY <= '0'; + when TRUE => EMAC0_SPEED_MSB_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_SPEED_MSB is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_MDIO_ENABLE is + when FALSE => EMAC0_MDIO_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_MDIO_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_MDIO_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_PHYLOOPBACKMSB is + when FALSE => EMAC0_PHYLOOPBACKMSB_BINARY <= '0'; + when TRUE => EMAC0_PHYLOOPBACKMSB_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_PHYLOOPBACKMSB is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_PHYPOWERDOWN is + when FALSE => EMAC0_PHYPOWERDOWN_BINARY <= '0'; + when TRUE => EMAC0_PHYPOWERDOWN_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_PHYPOWERDOWN is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_PHYISOLATE is + when FALSE => EMAC0_PHYISOLATE_BINARY <= '0'; + when TRUE => EMAC0_PHYISOLATE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_PHYISOLATE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_PHYINITAUTONEG_ENABLE is + when FALSE => EMAC0_PHYINITAUTONEG_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_PHYINITAUTONEG_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_PHYINITAUTONEG_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_PHYRESET is + when FALSE => EMAC0_PHYRESET_BINARY <= '0'; + when TRUE => EMAC0_PHYRESET_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_PHYRESET is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_CONFIGVEC_79 is + when FALSE => EMAC0_CONFIGVEC_79_BINARY <= '0'; + when TRUE => EMAC0_CONFIGVEC_79_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_CONFIGVEC_79 is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_UNIDIRECTION_ENABLE is + when FALSE => EMAC0_UNIDIRECTION_ENABLE_BINARY <= '0'; + when TRUE => EMAC0_UNIDIRECTION_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_UNIDIRECTION_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_GTLOOPBACK is + when FALSE => EMAC0_GTLOOPBACK_BINARY <= '0'; + when TRUE => EMAC0_GTLOOPBACK_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_GTLOOPBACK is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_BYTEPHY is + when FALSE => EMAC0_BYTEPHY_BINARY <= '0'; + when TRUE => EMAC0_BYTEPHY_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_BYTEPHY is neither TRUE nor FALSE." severity error; + end case; + case EMAC0_USECLKEN is + when FALSE => EMAC0_USECLKEN_BINARY <= '0'; + when TRUE => EMAC0_USECLKEN_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC0_USECLKEN is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_RXHALFDUPLEX is + when FALSE => EMAC1_RXHALFDUPLEX_BINARY <= '0'; + when TRUE => EMAC1_RXHALFDUPLEX_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_RXHALFDUPLEX is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_RXVLAN_ENABLE is + when FALSE => EMAC1_RXVLAN_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_RXVLAN_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_RXVLAN_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_RX_ENABLE is + when FALSE => EMAC1_RX_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_RX_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_RX_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_RXINBANDFCS_ENABLE is + when FALSE => EMAC1_RXINBANDFCS_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_RXINBANDFCS_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_RXINBANDFCS_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_RXJUMBOFRAME_ENABLE is + when FALSE => EMAC1_RXJUMBOFRAME_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_RXJUMBOFRAME_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_RXJUMBOFRAME_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_RXRESET is + when FALSE => EMAC1_RXRESET_BINARY <= '0'; + when TRUE => EMAC1_RXRESET_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_RXRESET is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_TXIFGADJUST_ENABLE is + when FALSE => EMAC1_TXIFGADJUST_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_TXIFGADJUST_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_TXIFGADJUST_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_TXHALFDUPLEX is + when FALSE => EMAC1_TXHALFDUPLEX_BINARY <= '0'; + when TRUE => EMAC1_TXHALFDUPLEX_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_TXHALFDUPLEX is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_TXVLAN_ENABLE is + when FALSE => EMAC1_TXVLAN_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_TXVLAN_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_TXVLAN_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_TX_ENABLE is + when FALSE => EMAC1_TX_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_TX_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_TX_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_TXINBANDFCS_ENABLE is + when FALSE => EMAC1_TXINBANDFCS_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_TXINBANDFCS_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_TXINBANDFCS_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_TXJUMBOFRAME_ENABLE is + when FALSE => EMAC1_TXJUMBOFRAME_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_TXJUMBOFRAME_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_TXJUMBOFRAME_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_TXRESET is + when FALSE => EMAC1_TXRESET_BINARY <= '0'; + when TRUE => EMAC1_TXRESET_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_TXRESET is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_TXFLOWCTRL_ENABLE is + when FALSE => EMAC1_TXFLOWCTRL_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_TXFLOWCTRL_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_TXFLOWCTRL_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_RXFLOWCTRL_ENABLE is + when FALSE => EMAC1_RXFLOWCTRL_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_RXFLOWCTRL_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_RXFLOWCTRL_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_LTCHECK_DISABLE is + when FALSE => EMAC1_LTCHECK_DISABLE_BINARY <= '0'; + when TRUE => EMAC1_LTCHECK_DISABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_LTCHECK_DISABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_ADDRFILTER_ENABLE is + when FALSE => EMAC1_ADDRFILTER_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_ADDRFILTER_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_ADDRFILTER_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_RX16BITCLIENT_ENABLE is + when FALSE => EMAC1_RX16BITCLIENT_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_RX16BITCLIENT_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_RX16BITCLIENT_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_TX16BITCLIENT_ENABLE is + when FALSE => EMAC1_TX16BITCLIENT_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_TX16BITCLIENT_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_TX16BITCLIENT_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_HOST_ENABLE is + when FALSE => EMAC1_HOST_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_HOST_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_HOST_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_1000BASEX_ENABLE is + when FALSE => EMAC1_1000BASEX_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_1000BASEX_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_1000BASEX_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_SGMII_ENABLE is + when FALSE => EMAC1_SGMII_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_SGMII_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_SGMII_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_RGMII_ENABLE is + when FALSE => EMAC1_RGMII_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_RGMII_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_RGMII_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_SPEED_LSB is + when FALSE => EMAC1_SPEED_LSB_BINARY <= '0'; + when TRUE => EMAC1_SPEED_LSB_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_SPEED_LSB is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_SPEED_MSB is + when FALSE => EMAC1_SPEED_MSB_BINARY <= '0'; + when TRUE => EMAC1_SPEED_MSB_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_SPEED_MSB is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_MDIO_ENABLE is + when FALSE => EMAC1_MDIO_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_MDIO_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_MDIO_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_PHYLOOPBACKMSB is + when FALSE => EMAC1_PHYLOOPBACKMSB_BINARY <= '0'; + when TRUE => EMAC1_PHYLOOPBACKMSB_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_PHYLOOPBACKMSB is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_PHYPOWERDOWN is + when FALSE => EMAC1_PHYPOWERDOWN_BINARY <= '0'; + when TRUE => EMAC1_PHYPOWERDOWN_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_PHYPOWERDOWN is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_PHYISOLATE is + when FALSE => EMAC1_PHYISOLATE_BINARY <= '0'; + when TRUE => EMAC1_PHYISOLATE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_PHYISOLATE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_PHYINITAUTONEG_ENABLE is + when FALSE => EMAC1_PHYINITAUTONEG_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_PHYINITAUTONEG_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_PHYINITAUTONEG_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_PHYRESET is + when FALSE => EMAC1_PHYRESET_BINARY <= '0'; + when TRUE => EMAC1_PHYRESET_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_PHYRESET is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_CONFIGVEC_79 is + when FALSE => EMAC1_CONFIGVEC_79_BINARY <= '0'; + when TRUE => EMAC1_CONFIGVEC_79_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_CONFIGVEC_79 is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_UNIDIRECTION_ENABLE is + when FALSE => EMAC1_UNIDIRECTION_ENABLE_BINARY <= '0'; + when TRUE => EMAC1_UNIDIRECTION_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_UNIDIRECTION_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_GTLOOPBACK is + when FALSE => EMAC1_GTLOOPBACK_BINARY <= '0'; + when TRUE => EMAC1_GTLOOPBACK_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_GTLOOPBACK is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_BYTEPHY is + when FALSE => EMAC1_BYTEPHY_BINARY <= '0'; + when TRUE => EMAC1_BYTEPHY_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_BYTEPHY is neither TRUE nor FALSE." severity error; + end case; + case EMAC1_USECLKEN is + when FALSE => EMAC1_USECLKEN_BINARY <= '0'; + when TRUE => EMAC1_USECLKEN_BINARY <= '1'; + when others => assert FALSE report "Error : EMAC1_USECLKEN is neither TRUE nor FALSE." severity error; + end case; + wait; + end process INIPROC; + + TIMING : process + + variable DCRHOSTDONEIR_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTANINTERRUPT_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXBADFRAME_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD0_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD1_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD2_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD3_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD4_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD5_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD6_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD7_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD8_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD9_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD10_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD11_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD12_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD13_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD14_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXD15_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXDVLD_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXDVLDMSW_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXFRAMEDROP_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXGOODFRAME_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS0_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS1_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS2_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS3_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS4_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS5_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATS6_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTRXSTATSVLD_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXACK_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXCOLLISION_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXGMIIMIICLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXRETRANSMIT_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXSTATS_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; + variable EMAC0CLIENTTXSTATSVLD_GlitchData : VitalGlitchDataType; + variable EMAC0PHYENCOMMAALIGN_GlitchData : VitalGlitchDataType; + variable EMAC0PHYLOOPBACKMSB_GlitchData : VitalGlitchDataType; + variable EMAC0PHYMCLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC0PHYMDOUT_GlitchData : VitalGlitchDataType; + variable EMAC0PHYMDTRI_GlitchData : VitalGlitchDataType; + variable EMAC0PHYMGTRXRESET_GlitchData : VitalGlitchDataType; + variable EMAC0PHYMGTTXRESET_GlitchData : VitalGlitchDataType; + variable EMAC0PHYPOWERDOWN_GlitchData : VitalGlitchDataType; + variable EMAC0PHYSYNCACQSTATUS_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXCHARDISPMODE_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXCHARDISPVAL_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXCHARISK_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXCLK_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD0_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD1_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD2_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD3_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD4_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD5_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD6_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXD7_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXEN_GlitchData : VitalGlitchDataType; + variable EMAC0PHYTXER_GlitchData : VitalGlitchDataType; + variable EMAC0SPEEDIS10100_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTANINTERRUPT_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXBADFRAME_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD0_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD1_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD2_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD3_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD4_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD5_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD6_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD7_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD8_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD9_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD10_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD11_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD12_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD13_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD14_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXD15_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXDVLD_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXDVLDMSW_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXFRAMEDROP_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXGOODFRAME_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS0_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS1_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS2_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS3_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS4_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS5_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATS6_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTRXSTATSVLD_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXACK_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXCOLLISION_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXGMIIMIICLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXRETRANSMIT_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXSTATS_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; + variable EMAC1CLIENTTXSTATSVLD_GlitchData : VitalGlitchDataType; + variable EMAC1PHYENCOMMAALIGN_GlitchData : VitalGlitchDataType; + variable EMAC1PHYLOOPBACKMSB_GlitchData : VitalGlitchDataType; + variable EMAC1PHYMCLKOUT_GlitchData : VitalGlitchDataType; + variable EMAC1PHYMDOUT_GlitchData : VitalGlitchDataType; + variable EMAC1PHYMDTRI_GlitchData : VitalGlitchDataType; + variable EMAC1PHYMGTRXRESET_GlitchData : VitalGlitchDataType; + variable EMAC1PHYMGTTXRESET_GlitchData : VitalGlitchDataType; + variable EMAC1PHYPOWERDOWN_GlitchData : VitalGlitchDataType; + variable EMAC1PHYSYNCACQSTATUS_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXCHARDISPMODE_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXCHARDISPVAL_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXCHARISK_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXCLK_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD0_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD1_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD2_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD3_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD4_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD5_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD6_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXD7_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXEN_GlitchData : VitalGlitchDataType; + variable EMAC1PHYTXER_GlitchData : VitalGlitchDataType; + variable EMAC1SPEEDIS10100_GlitchData : VitalGlitchDataType; + variable EMACDCRACK_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS0_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS1_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS2_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS3_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS4_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS5_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS6_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS7_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS8_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS9_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS10_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS11_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS12_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS13_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS14_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS15_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS16_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS17_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS18_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS19_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS20_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS21_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS22_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS23_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS24_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS25_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS26_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS27_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS28_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS29_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS30_GlitchData : VitalGlitchDataType; + variable EMACDCRDBUS31_GlitchData : VitalGlitchDataType; + variable HOSTMIIMRDY_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA0_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA1_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA2_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA3_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA4_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA5_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA6_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA7_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA8_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA9_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA10_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA11_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA12_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA13_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA14_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA15_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA16_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA17_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA18_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA19_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA20_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA21_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA22_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA23_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA24_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA25_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA26_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA27_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA28_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA29_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA30_GlitchData : VitalGlitchDataType; + variable HOSTRDDATA31_GlitchData : VitalGlitchDataType; +begin + + VitalPathDelay01 + ( + OutSignal => DCRHOSTDONEIR, + GlitchData => DCRHOSTDONEIR_GlitchData, + OutSignalName => "DCRHOSTDONEIR", + OutTemp => DCRHOSTDONEIR_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTANINTERRUPT, + GlitchData => EMAC0CLIENTANINTERRUPT_GlitchData, + OutSignalName => "EMAC0CLIENTANINTERRUPT", + OutTemp => EMAC0CLIENTANINTERRUPT_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXBADFRAME, + GlitchData => EMAC0CLIENTRXBADFRAME_GlitchData, + OutSignalName => "EMAC0CLIENTRXBADFRAME", + OutTemp => EMAC0CLIENTRXBADFRAME_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXBADFRAME, + GlitchData => EMAC0CLIENTRXBADFRAME_GlitchData, + OutSignalName => "EMAC0CLIENTRXBADFRAME", + OutTemp => EMAC0CLIENTRXBADFRAME_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXBADFRAME, + GlitchData => EMAC0CLIENTRXBADFRAME_GlitchData, + OutSignalName => "EMAC0CLIENTRXBADFRAME", + OutTemp => EMAC0CLIENTRXBADFRAME_OUT, + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXCLIENTCLKOUT, + GlitchData => EMAC0CLIENTRXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC0CLIENTRXCLIENTCLKOUT", + OutTemp => EMAC0CLIENTRXCLIENTCLKOUT_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXCLIENTCLKOUT, + GlitchData => EMAC0CLIENTRXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC0CLIENTRXCLIENTCLKOUT", + OutTemp => EMAC0CLIENTRXCLIENTCLKOUT_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXCLIENTCLKOUT, + GlitchData => EMAC0CLIENTRXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC0CLIENTRXCLIENTCLKOUT", + OutTemp => EMAC0CLIENTRXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXCLIENTCLKOUT, + GlitchData => EMAC0CLIENTRXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC0CLIENTRXCLIENTCLKOUT", + OutTemp => EMAC0CLIENTRXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(0), + GlitchData => EMAC0CLIENTRXD0_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(0)", + OutTemp => EMAC0CLIENTRXD_OUT(0), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(0), + GlitchData => EMAC0CLIENTRXD0_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(0)", + OutTemp => EMAC0CLIENTRXD_OUT(0), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(0), + GlitchData => EMAC0CLIENTRXD0_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(0)", + OutTemp => EMAC0CLIENTRXD_OUT(0), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(1), + GlitchData => EMAC0CLIENTRXD1_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(1)", + OutTemp => EMAC0CLIENTRXD_OUT(1), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(1), + GlitchData => EMAC0CLIENTRXD1_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(1)", + OutTemp => EMAC0CLIENTRXD_OUT(1), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(1), + GlitchData => EMAC0CLIENTRXD1_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(1)", + OutTemp => EMAC0CLIENTRXD_OUT(1), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(2), + GlitchData => EMAC0CLIENTRXD2_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(2)", + OutTemp => EMAC0CLIENTRXD_OUT(2), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(2), + GlitchData => EMAC0CLIENTRXD2_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(2)", + OutTemp => EMAC0CLIENTRXD_OUT(2), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(2), + GlitchData => EMAC0CLIENTRXD2_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(2)", + OutTemp => EMAC0CLIENTRXD_OUT(2), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(3), + GlitchData => EMAC0CLIENTRXD3_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(3)", + OutTemp => EMAC0CLIENTRXD_OUT(3), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(3), + GlitchData => EMAC0CLIENTRXD3_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(3)", + OutTemp => EMAC0CLIENTRXD_OUT(3), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(3), + GlitchData => EMAC0CLIENTRXD3_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(3)", + OutTemp => EMAC0CLIENTRXD_OUT(3), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(4), + GlitchData => EMAC0CLIENTRXD4_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(4)", + OutTemp => EMAC0CLIENTRXD_OUT(4), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(4), + GlitchData => EMAC0CLIENTRXD4_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(4)", + OutTemp => EMAC0CLIENTRXD_OUT(4), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(4), + GlitchData => EMAC0CLIENTRXD4_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(4)", + OutTemp => EMAC0CLIENTRXD_OUT(4), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(5), + GlitchData => EMAC0CLIENTRXD5_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(5)", + OutTemp => EMAC0CLIENTRXD_OUT(5), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(5), + GlitchData => EMAC0CLIENTRXD5_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(5)", + OutTemp => EMAC0CLIENTRXD_OUT(5), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(5), + GlitchData => EMAC0CLIENTRXD5_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(5)", + OutTemp => EMAC0CLIENTRXD_OUT(5), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(6), + GlitchData => EMAC0CLIENTRXD6_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(6)", + OutTemp => EMAC0CLIENTRXD_OUT(6), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(6), + GlitchData => EMAC0CLIENTRXD6_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(6)", + OutTemp => EMAC0CLIENTRXD_OUT(6), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(6), + GlitchData => EMAC0CLIENTRXD6_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(6)", + OutTemp => EMAC0CLIENTRXD_OUT(6), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(7), + GlitchData => EMAC0CLIENTRXD7_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(7)", + OutTemp => EMAC0CLIENTRXD_OUT(7), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(7), + GlitchData => EMAC0CLIENTRXD7_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(7)", + OutTemp => EMAC0CLIENTRXD_OUT(7), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(7), + GlitchData => EMAC0CLIENTRXD7_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(7)", + OutTemp => EMAC0CLIENTRXD_OUT(7), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(8), + GlitchData => EMAC0CLIENTRXD8_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(8)", + OutTemp => EMAC0CLIENTRXD_OUT(8), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(8), + GlitchData => EMAC0CLIENTRXD8_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(8)", + OutTemp => EMAC0CLIENTRXD_OUT(8), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(8), + GlitchData => EMAC0CLIENTRXD8_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(8)", + OutTemp => EMAC0CLIENTRXD_OUT(8), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(9), + GlitchData => EMAC0CLIENTRXD9_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(9)", + OutTemp => EMAC0CLIENTRXD_OUT(9), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(9), + GlitchData => EMAC0CLIENTRXD9_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(9)", + OutTemp => EMAC0CLIENTRXD_OUT(9), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(9), + GlitchData => EMAC0CLIENTRXD9_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(9)", + OutTemp => EMAC0CLIENTRXD_OUT(9), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(10), + GlitchData => EMAC0CLIENTRXD10_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(10)", + OutTemp => EMAC0CLIENTRXD_OUT(10), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(10), + GlitchData => EMAC0CLIENTRXD10_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(10)", + OutTemp => EMAC0CLIENTRXD_OUT(10), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(10), + GlitchData => EMAC0CLIENTRXD10_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(10)", + OutTemp => EMAC0CLIENTRXD_OUT(10), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(11), + GlitchData => EMAC0CLIENTRXD11_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(11)", + OutTemp => EMAC0CLIENTRXD_OUT(11), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(11), + GlitchData => EMAC0CLIENTRXD11_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(11)", + OutTemp => EMAC0CLIENTRXD_OUT(11), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(11), + GlitchData => EMAC0CLIENTRXD11_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(11)", + OutTemp => EMAC0CLIENTRXD_OUT(11), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(12), + GlitchData => EMAC0CLIENTRXD12_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(12)", + OutTemp => EMAC0CLIENTRXD_OUT(12), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(12), + GlitchData => EMAC0CLIENTRXD12_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(12)", + OutTemp => EMAC0CLIENTRXD_OUT(12), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(12), + GlitchData => EMAC0CLIENTRXD12_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(12)", + OutTemp => EMAC0CLIENTRXD_OUT(12), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(13), + GlitchData => EMAC0CLIENTRXD13_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(13)", + OutTemp => EMAC0CLIENTRXD_OUT(13), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(13), + GlitchData => EMAC0CLIENTRXD13_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(13)", + OutTemp => EMAC0CLIENTRXD_OUT(13), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(13), + GlitchData => EMAC0CLIENTRXD13_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(13)", + OutTemp => EMAC0CLIENTRXD_OUT(13), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(14), + GlitchData => EMAC0CLIENTRXD14_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(14)", + OutTemp => EMAC0CLIENTRXD_OUT(14), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(14), + GlitchData => EMAC0CLIENTRXD14_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(14)", + OutTemp => EMAC0CLIENTRXD_OUT(14), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(14), + GlitchData => EMAC0CLIENTRXD14_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(14)", + OutTemp => EMAC0CLIENTRXD_OUT(14), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(15), + GlitchData => EMAC0CLIENTRXD15_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(15)", + OutTemp => EMAC0CLIENTRXD_OUT(15), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(15), + GlitchData => EMAC0CLIENTRXD15_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(15)", + OutTemp => EMAC0CLIENTRXD_OUT(15), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXD(15), + GlitchData => EMAC0CLIENTRXD15_GlitchData, + OutSignalName => "EMAC0CLIENTRXD(15)", + OutTemp => EMAC0CLIENTRXD_OUT(15), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXDVLD, + GlitchData => EMAC0CLIENTRXDVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXDVLD", + OutTemp => EMAC0CLIENTRXDVLD_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXDVLD, + GlitchData => EMAC0CLIENTRXDVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXDVLD", + OutTemp => EMAC0CLIENTRXDVLD_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXDVLD, + GlitchData => EMAC0CLIENTRXDVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXDVLD", + OutTemp => EMAC0CLIENTRXDVLD_OUT, + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXDVLDMSW, + GlitchData => EMAC0CLIENTRXDVLDMSW_GlitchData, + OutSignalName => "EMAC0CLIENTRXDVLDMSW", + OutTemp => EMAC0CLIENTRXDVLDMSW_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXDVLDMSW, + GlitchData => EMAC0CLIENTRXDVLDMSW_GlitchData, + OutSignalName => "EMAC0CLIENTRXDVLDMSW", + OutTemp => EMAC0CLIENTRXDVLDMSW_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXDVLDMSW, + GlitchData => EMAC0CLIENTRXDVLDMSW_GlitchData, + OutSignalName => "EMAC0CLIENTRXDVLDMSW", + OutTemp => EMAC0CLIENTRXDVLDMSW_OUT, + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXFRAMEDROP, + GlitchData => EMAC0CLIENTRXFRAMEDROP_GlitchData, + OutSignalName => "EMAC0CLIENTRXFRAMEDROP", + OutTemp => EMAC0CLIENTRXFRAMEDROP_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXFRAMEDROP, + GlitchData => EMAC0CLIENTRXFRAMEDROP_GlitchData, + OutSignalName => "EMAC0CLIENTRXFRAMEDROP", + OutTemp => EMAC0CLIENTRXFRAMEDROP_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXFRAMEDROP, + GlitchData => EMAC0CLIENTRXFRAMEDROP_GlitchData, + OutSignalName => "EMAC0CLIENTRXFRAMEDROP", + OutTemp => EMAC0CLIENTRXFRAMEDROP_OUT, + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXGOODFRAME, + GlitchData => EMAC0CLIENTRXGOODFRAME_GlitchData, + OutSignalName => "EMAC0CLIENTRXGOODFRAME", + OutTemp => EMAC0CLIENTRXGOODFRAME_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXGOODFRAME, + GlitchData => EMAC0CLIENTRXGOODFRAME_GlitchData, + OutSignalName => "EMAC0CLIENTRXGOODFRAME", + OutTemp => EMAC0CLIENTRXGOODFRAME_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXGOODFRAME, + GlitchData => EMAC0CLIENTRXGOODFRAME_GlitchData, + OutSignalName => "EMAC0CLIENTRXGOODFRAME", + OutTemp => EMAC0CLIENTRXGOODFRAME_OUT, + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(0), + GlitchData => EMAC0CLIENTRXSTATS0_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(0)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(0), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(0), + GlitchData => EMAC0CLIENTRXSTATS0_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(0)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(0), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(0), + GlitchData => EMAC0CLIENTRXSTATS0_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(0)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(0), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(1), + GlitchData => EMAC0CLIENTRXSTATS1_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(1)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(1), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(1), + GlitchData => EMAC0CLIENTRXSTATS1_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(1)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(1), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(1), + GlitchData => EMAC0CLIENTRXSTATS1_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(1)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(1), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(2), + GlitchData => EMAC0CLIENTRXSTATS2_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(2)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(2), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(2), + GlitchData => EMAC0CLIENTRXSTATS2_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(2)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(2), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(2), + GlitchData => EMAC0CLIENTRXSTATS2_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(2)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(2), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(3), + GlitchData => EMAC0CLIENTRXSTATS3_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(3)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(3), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(3), + GlitchData => EMAC0CLIENTRXSTATS3_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(3)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(3), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(3), + GlitchData => EMAC0CLIENTRXSTATS3_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(3)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(3), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(4), + GlitchData => EMAC0CLIENTRXSTATS4_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(4)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(4), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(4), + GlitchData => EMAC0CLIENTRXSTATS4_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(4)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(4), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(4), + GlitchData => EMAC0CLIENTRXSTATS4_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(4)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(4), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(5), + GlitchData => EMAC0CLIENTRXSTATS5_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(5)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(5), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(5), + GlitchData => EMAC0CLIENTRXSTATS5_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(5)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(5), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(5), + GlitchData => EMAC0CLIENTRXSTATS5_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(5)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(5), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(6), + GlitchData => EMAC0CLIENTRXSTATS6_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(6)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(6), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(6), + GlitchData => EMAC0CLIENTRXSTATS6_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(6)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(6), + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATS(6), + GlitchData => EMAC0CLIENTRXSTATS6_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATS(6)", + OutTemp => EMAC0CLIENTRXSTATS_OUT(6), + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATSBYTEVLD, + GlitchData => EMAC0CLIENTRXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATSBYTEVLD", + OutTemp => EMAC0CLIENTRXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATSBYTEVLD, + GlitchData => EMAC0CLIENTRXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATSBYTEVLD", + OutTemp => EMAC0CLIENTRXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATSBYTEVLD, + GlitchData => EMAC0CLIENTRXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATSBYTEVLD", + OutTemp => EMAC0CLIENTRXSTATSBYTEVLD_OUT, + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATSVLD, + GlitchData => EMAC0CLIENTRXSTATSVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATSVLD", + OutTemp => EMAC0CLIENTRXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATSVLD, + GlitchData => EMAC0CLIENTRXSTATSVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATSVLD", + OutTemp => EMAC0CLIENTRXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTRXSTATSVLD, + GlitchData => EMAC0CLIENTRXSTATSVLD_GlitchData, + OutSignalName => "EMAC0CLIENTRXSTATSVLD", + OutTemp => EMAC0CLIENTRXSTATSVLD_OUT, + Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXACK, + GlitchData => EMAC0CLIENTTXACK_GlitchData, + OutSignalName => "EMAC0CLIENTTXACK", + OutTemp => EMAC0CLIENTTXACK_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXACK, + GlitchData => EMAC0CLIENTTXACK_GlitchData, + OutSignalName => "EMAC0CLIENTTXACK", + OutTemp => EMAC0CLIENTTXACK_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXACK, + GlitchData => EMAC0CLIENTTXACK_GlitchData, + OutSignalName => "EMAC0CLIENTTXACK", + OutTemp => EMAC0CLIENTTXACK_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXCLIENTCLKOUT, + GlitchData => EMAC0CLIENTTXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC0CLIENTTXCLIENTCLKOUT", + OutTemp => EMAC0CLIENTTXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXCLIENTCLKOUT, + GlitchData => EMAC0CLIENTTXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC0CLIENTTXCLIENTCLKOUT", + OutTemp => EMAC0CLIENTTXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC0MIITXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXCLIENTCLKOUT, + GlitchData => EMAC0CLIENTTXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC0CLIENTTXCLIENTCLKOUT", + OutTemp => EMAC0CLIENTTXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXCOLLISION, + GlitchData => EMAC0CLIENTTXCOLLISION_GlitchData, + OutSignalName => "EMAC0CLIENTTXCOLLISION", + OutTemp => EMAC0CLIENTTXCOLLISION_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXCOLLISION, + GlitchData => EMAC0CLIENTTXCOLLISION_GlitchData, + OutSignalName => "EMAC0CLIENTTXCOLLISION", + OutTemp => EMAC0CLIENTTXCOLLISION_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXCOLLISION, + GlitchData => EMAC0CLIENTTXCOLLISION_GlitchData, + OutSignalName => "EMAC0CLIENTTXCOLLISION", + OutTemp => EMAC0CLIENTTXCOLLISION_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXGMIIMIICLKOUT, + GlitchData => EMAC0PHYTXGMIIMIICLKOUT_GlitchData, + OutSignalName => "EMAC0PHYTXGMIIMIICLKOUT", + OutTemp => EMAC0PHYTXGMIIMIICLKOUT_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXGMIIMIICLKOUT, + GlitchData => EMAC0PHYTXGMIIMIICLKOUT_GlitchData, + OutSignalName => "EMAC0PHYTXGMIIMIICLKOUT", + OutTemp => EMAC0PHYTXGMIIMIICLKOUT_OUT, + Paths => (0 => (PHYEMAC0MIITXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXRETRANSMIT, + GlitchData => EMAC0CLIENTTXRETRANSMIT_GlitchData, + OutSignalName => "EMAC0CLIENTTXRETRANSMIT", + OutTemp => EMAC0CLIENTTXRETRANSMIT_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXRETRANSMIT, + GlitchData => EMAC0CLIENTTXRETRANSMIT_GlitchData, + OutSignalName => "EMAC0CLIENTTXRETRANSMIT", + OutTemp => EMAC0CLIENTTXRETRANSMIT_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXRETRANSMIT, + GlitchData => EMAC0CLIENTTXRETRANSMIT_GlitchData, + OutSignalName => "EMAC0CLIENTTXRETRANSMIT", + OutTemp => EMAC0CLIENTTXRETRANSMIT_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATS, + GlitchData => EMAC0CLIENTTXSTATS_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATS", + OutTemp => EMAC0CLIENTTXSTATS_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATS, + GlitchData => EMAC0CLIENTTXSTATS_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATS", + OutTemp => EMAC0CLIENTTXSTATS_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATS, + GlitchData => EMAC0CLIENTTXSTATS_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATS", + OutTemp => EMAC0CLIENTTXSTATS_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATSBYTEVLD, + GlitchData => EMAC0CLIENTTXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATSBYTEVLD", + OutTemp => EMAC0CLIENTTXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATSBYTEVLD, + GlitchData => EMAC0CLIENTTXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATSBYTEVLD", + OutTemp => EMAC0CLIENTTXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATSBYTEVLD, + GlitchData => EMAC0CLIENTTXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATSBYTEVLD", + OutTemp => EMAC0CLIENTTXSTATSBYTEVLD_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATSVLD, + GlitchData => EMAC0CLIENTTXSTATSVLD_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATSVLD", + OutTemp => EMAC0CLIENTTXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATSVLD, + GlitchData => EMAC0CLIENTTXSTATSVLD_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATSVLD", + OutTemp => EMAC0CLIENTTXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0CLIENTTXSTATSVLD, + GlitchData => EMAC0CLIENTTXSTATSVLD_GlitchData, + OutSignalName => "EMAC0CLIENTTXSTATSVLD", + OutTemp => EMAC0CLIENTTXSTATSVLD_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYENCOMMAALIGN, + GlitchData => EMAC0PHYENCOMMAALIGN_GlitchData, + OutSignalName => "EMAC0PHYENCOMMAALIGN", + OutTemp => EMAC0PHYENCOMMAALIGN_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYLOOPBACKMSB, + GlitchData => EMAC0PHYLOOPBACKMSB_GlitchData, + OutSignalName => "EMAC0PHYLOOPBACKMSB", + OutTemp => EMAC0PHYLOOPBACKMSB_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMCLKOUT, + GlitchData => EMAC0PHYMCLKOUT_GlitchData, + OutSignalName => "EMAC0PHYMCLKOUT", + OutTemp => EMAC0PHYMCLKOUT_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMCLKOUT, + GlitchData => EMAC0PHYMCLKOUT_GlitchData, + OutSignalName => "EMAC0PHYMCLKOUT", + OutTemp => EMAC0PHYMCLKOUT_OUT, + Paths => (0 => (PHYEMAC0MCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMDOUT, + GlitchData => EMAC0PHYMDOUT_GlitchData, + OutSignalName => "EMAC0PHYMDOUT", + OutTemp => EMAC0PHYMDOUT_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMDOUT, + GlitchData => EMAC0PHYMDOUT_GlitchData, + OutSignalName => "EMAC0PHYMDOUT", + OutTemp => EMAC0PHYMDOUT_OUT, + Paths => (0 => (PHYEMAC0MCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMDTRI, + GlitchData => EMAC0PHYMDTRI_GlitchData, + OutSignalName => "EMAC0PHYMDTRI", + OutTemp => EMAC0PHYMDTRI_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMDTRI, + GlitchData => EMAC0PHYMDTRI_GlitchData, + OutSignalName => "EMAC0PHYMDTRI", + OutTemp => EMAC0PHYMDTRI_OUT, + Paths => (0 => (PHYEMAC0MCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMGTRXRESET, + GlitchData => EMAC0PHYMGTRXRESET_GlitchData, + OutSignalName => "EMAC0PHYMGTRXRESET", + OutTemp => EMAC0PHYMGTRXRESET_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYMGTTXRESET, + GlitchData => EMAC0PHYMGTTXRESET_GlitchData, + OutSignalName => "EMAC0PHYMGTTXRESET", + OutTemp => EMAC0PHYMGTTXRESET_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYPOWERDOWN, + GlitchData => EMAC0PHYPOWERDOWN_GlitchData, + OutSignalName => "EMAC0PHYPOWERDOWN", + OutTemp => EMAC0PHYPOWERDOWN_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYSYNCACQSTATUS, + GlitchData => EMAC0PHYSYNCACQSTATUS_GlitchData, + OutSignalName => "EMAC0PHYSYNCACQSTATUS", + OutTemp => EMAC0PHYSYNCACQSTATUS_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYSYNCACQSTATUS, + GlitchData => EMAC0PHYSYNCACQSTATUS_GlitchData, + OutSignalName => "EMAC0PHYSYNCACQSTATUS", + OutTemp => EMAC0PHYSYNCACQSTATUS_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYSYNCACQSTATUS, + GlitchData => EMAC0PHYSYNCACQSTATUS_GlitchData, + OutSignalName => "EMAC0PHYSYNCACQSTATUS", + OutTemp => EMAC0PHYSYNCACQSTATUS_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARDISPMODE, + GlitchData => EMAC0PHYTXCHARDISPMODE_GlitchData, + OutSignalName => "EMAC0PHYTXCHARDISPMODE", + OutTemp => EMAC0PHYTXCHARDISPMODE_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARDISPMODE, + GlitchData => EMAC0PHYTXCHARDISPMODE_GlitchData, + OutSignalName => "EMAC0PHYTXCHARDISPMODE", + OutTemp => EMAC0PHYTXCHARDISPMODE_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARDISPMODE, + GlitchData => EMAC0PHYTXCHARDISPMODE_GlitchData, + OutSignalName => "EMAC0PHYTXCHARDISPMODE", + OutTemp => EMAC0PHYTXCHARDISPMODE_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARDISPVAL, + GlitchData => EMAC0PHYTXCHARDISPVAL_GlitchData, + OutSignalName => "EMAC0PHYTXCHARDISPVAL", + OutTemp => EMAC0PHYTXCHARDISPVAL_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARDISPVAL, + GlitchData => EMAC0PHYTXCHARDISPVAL_GlitchData, + OutSignalName => "EMAC0PHYTXCHARDISPVAL", + OutTemp => EMAC0PHYTXCHARDISPVAL_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARDISPVAL, + GlitchData => EMAC0PHYTXCHARDISPVAL_GlitchData, + OutSignalName => "EMAC0PHYTXCHARDISPVAL", + OutTemp => EMAC0PHYTXCHARDISPVAL_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARISK, + GlitchData => EMAC0PHYTXCHARISK_GlitchData, + OutSignalName => "EMAC0PHYTXCHARISK", + OutTemp => EMAC0PHYTXCHARISK_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARISK, + GlitchData => EMAC0PHYTXCHARISK_GlitchData, + OutSignalName => "EMAC0PHYTXCHARISK", + OutTemp => EMAC0PHYTXCHARISK_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCHARISK, + GlitchData => EMAC0PHYTXCHARISK_GlitchData, + OutSignalName => "EMAC0PHYTXCHARISK", + OutTemp => EMAC0PHYTXCHARISK_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCLK, + GlitchData => EMAC0PHYTXCLK_GlitchData, + OutSignalName => "EMAC0PHYTXCLK", + OutTemp => EMAC0PHYTXCLK_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCLK, + GlitchData => EMAC0PHYTXCLK_GlitchData, + OutSignalName => "EMAC0PHYTXCLK", + OutTemp => EMAC0PHYTXCLK_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXCLK, + GlitchData => EMAC0PHYTXCLK_GlitchData, + OutSignalName => "EMAC0PHYTXCLK", + OutTemp => EMAC0PHYTXCLK_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(0), + GlitchData => EMAC0PHYTXD0_GlitchData, + OutSignalName => "EMAC0PHYTXD(0)", + OutTemp => EMAC0PHYTXD_OUT(0), + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(0), + GlitchData => EMAC0PHYTXD0_GlitchData, + OutSignalName => "EMAC0PHYTXD(0)", + OutTemp => EMAC0PHYTXD_OUT(0), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(0), + GlitchData => EMAC0PHYTXD0_GlitchData, + OutSignalName => "EMAC0PHYTXD(0)", + OutTemp => EMAC0PHYTXD_OUT(0), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(1), + GlitchData => EMAC0PHYTXD1_GlitchData, + OutSignalName => "EMAC0PHYTXD(1)", + OutTemp => EMAC0PHYTXD_OUT(1), + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(1), + GlitchData => EMAC0PHYTXD1_GlitchData, + OutSignalName => "EMAC0PHYTXD(1)", + OutTemp => EMAC0PHYTXD_OUT(1), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(1), + GlitchData => EMAC0PHYTXD1_GlitchData, + OutSignalName => "EMAC0PHYTXD(1)", + OutTemp => EMAC0PHYTXD_OUT(1), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(2), + GlitchData => EMAC0PHYTXD2_GlitchData, + OutSignalName => "EMAC0PHYTXD(2)", + OutTemp => EMAC0PHYTXD_OUT(2), + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(2), + GlitchData => EMAC0PHYTXD2_GlitchData, + OutSignalName => "EMAC0PHYTXD(2)", + OutTemp => EMAC0PHYTXD_OUT(2), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(2), + GlitchData => EMAC0PHYTXD2_GlitchData, + OutSignalName => "EMAC0PHYTXD(2)", + OutTemp => EMAC0PHYTXD_OUT(2), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(3), + GlitchData => EMAC0PHYTXD3_GlitchData, + OutSignalName => "EMAC0PHYTXD(3)", + OutTemp => EMAC0PHYTXD_OUT(3), + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(3), + GlitchData => EMAC0PHYTXD3_GlitchData, + OutSignalName => "EMAC0PHYTXD(3)", + OutTemp => EMAC0PHYTXD_OUT(3), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(3), + GlitchData => EMAC0PHYTXD3_GlitchData, + OutSignalName => "EMAC0PHYTXD(3)", + OutTemp => EMAC0PHYTXD_OUT(3), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(4), + GlitchData => EMAC0PHYTXD4_GlitchData, + OutSignalName => "EMAC0PHYTXD(4)", + OutTemp => EMAC0PHYTXD_OUT(4), + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(4), + GlitchData => EMAC0PHYTXD4_GlitchData, + OutSignalName => "EMAC0PHYTXD(4)", + OutTemp => EMAC0PHYTXD_OUT(4), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(4), + GlitchData => EMAC0PHYTXD4_GlitchData, + OutSignalName => "EMAC0PHYTXD(4)", + OutTemp => EMAC0PHYTXD_OUT(4), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(4), + GlitchData => EMAC0PHYTXD4_GlitchData, + OutSignalName => "EMAC0PHYTXD(4)", + OutTemp => EMAC0PHYTXD_OUT(4), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(5), + GlitchData => EMAC0PHYTXD5_GlitchData, + OutSignalName => "EMAC0PHYTXD(5)", + OutTemp => EMAC0PHYTXD_OUT(5), + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(5), + GlitchData => EMAC0PHYTXD5_GlitchData, + OutSignalName => "EMAC0PHYTXD(5)", + OutTemp => EMAC0PHYTXD_OUT(5), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(5), + GlitchData => EMAC0PHYTXD5_GlitchData, + OutSignalName => "EMAC0PHYTXD(5)", + OutTemp => EMAC0PHYTXD_OUT(5), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(5), + GlitchData => EMAC0PHYTXD5_GlitchData, + OutSignalName => "EMAC0PHYTXD(5)", + OutTemp => EMAC0PHYTXD_OUT(5), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(6), + GlitchData => EMAC0PHYTXD6_GlitchData, + OutSignalName => "EMAC0PHYTXD(6)", + OutTemp => EMAC0PHYTXD_OUT(6), + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(6), + GlitchData => EMAC0PHYTXD6_GlitchData, + OutSignalName => "EMAC0PHYTXD(6)", + OutTemp => EMAC0PHYTXD_OUT(6), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(6), + GlitchData => EMAC0PHYTXD6_GlitchData, + OutSignalName => "EMAC0PHYTXD(6)", + OutTemp => EMAC0PHYTXD_OUT(6), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(6), + GlitchData => EMAC0PHYTXD6_GlitchData, + OutSignalName => "EMAC0PHYTXD(6)", + OutTemp => EMAC0PHYTXD_OUT(6), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(7), + GlitchData => EMAC0PHYTXD7_GlitchData, + OutSignalName => "EMAC0PHYTXD(7)", + OutTemp => EMAC0PHYTXD_OUT(7), + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(7), + GlitchData => EMAC0PHYTXD7_GlitchData, + OutSignalName => "EMAC0PHYTXD(7)", + OutTemp => EMAC0PHYTXD_OUT(7), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(7), + GlitchData => EMAC0PHYTXD7_GlitchData, + OutSignalName => "EMAC0PHYTXD(7)", + OutTemp => EMAC0PHYTXD_OUT(7), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXD(7), + GlitchData => EMAC0PHYTXD7_GlitchData, + OutSignalName => "EMAC0PHYTXD(7)", + OutTemp => EMAC0PHYTXD_OUT(7), + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXEN, + GlitchData => EMAC0PHYTXEN_GlitchData, + OutSignalName => "EMAC0PHYTXEN", + OutTemp => EMAC0PHYTXEN_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXEN, + GlitchData => EMAC0PHYTXEN_GlitchData, + OutSignalName => "EMAC0PHYTXEN", + OutTemp => EMAC0PHYTXEN_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXEN, + GlitchData => EMAC0PHYTXEN_GlitchData, + OutSignalName => "EMAC0PHYTXEN", + OutTemp => EMAC0PHYTXEN_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXER, + GlitchData => EMAC0PHYTXER_GlitchData, + OutSignalName => "EMAC0PHYTXER", + OutTemp => EMAC0PHYTXER_OUT, + Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXER, + GlitchData => EMAC0PHYTXER_GlitchData, + OutSignalName => "EMAC0PHYTXER", + OutTemp => EMAC0PHYTXER_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXER, + GlitchData => EMAC0PHYTXER_GlitchData, + OutSignalName => "EMAC0PHYTXER", + OutTemp => EMAC0PHYTXER_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0PHYTXER, + GlitchData => EMAC0PHYTXER_GlitchData, + OutSignalName => "EMAC0PHYTXER", + OutTemp => EMAC0PHYTXER_OUT, + Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC0SPEEDIS10100, + GlitchData => EMAC0SPEEDIS10100_GlitchData, + OutSignalName => "EMAC0SPEEDIS10100", + OutTemp => EMAC0SPEEDIS10100_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTANINTERRUPT, + GlitchData => EMAC1CLIENTANINTERRUPT_GlitchData, + OutSignalName => "EMAC1CLIENTANINTERRUPT", + OutTemp => EMAC1CLIENTANINTERRUPT_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXBADFRAME, + GlitchData => EMAC1CLIENTRXBADFRAME_GlitchData, + OutSignalName => "EMAC1CLIENTRXBADFRAME", + OutTemp => EMAC1CLIENTRXBADFRAME_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXBADFRAME, + GlitchData => EMAC1CLIENTRXBADFRAME_GlitchData, + OutSignalName => "EMAC1CLIENTRXBADFRAME", + OutTemp => EMAC1CLIENTRXBADFRAME_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXBADFRAME, + GlitchData => EMAC1CLIENTRXBADFRAME_GlitchData, + OutSignalName => "EMAC1CLIENTRXBADFRAME", + OutTemp => EMAC1CLIENTRXBADFRAME_OUT, + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXCLIENTCLKOUT, + GlitchData => EMAC1CLIENTRXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC1CLIENTRXCLIENTCLKOUT", + OutTemp => EMAC1CLIENTRXCLIENTCLKOUT_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXCLIENTCLKOUT, + GlitchData => EMAC1CLIENTRXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC1CLIENTRXCLIENTCLKOUT", + OutTemp => EMAC1CLIENTRXCLIENTCLKOUT_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXCLIENTCLKOUT, + GlitchData => EMAC1CLIENTRXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC1CLIENTRXCLIENTCLKOUT", + OutTemp => EMAC1CLIENTRXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXCLIENTCLKOUT, + GlitchData => EMAC1CLIENTRXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC1CLIENTRXCLIENTCLKOUT", + OutTemp => EMAC1CLIENTRXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(0), + GlitchData => EMAC1CLIENTRXD0_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(0)", + OutTemp => EMAC1CLIENTRXD_OUT(0), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(0), + GlitchData => EMAC1CLIENTRXD0_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(0)", + OutTemp => EMAC1CLIENTRXD_OUT(0), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(0), + GlitchData => EMAC1CLIENTRXD0_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(0)", + OutTemp => EMAC1CLIENTRXD_OUT(0), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(1), + GlitchData => EMAC1CLIENTRXD1_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(1)", + OutTemp => EMAC1CLIENTRXD_OUT(1), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(1), + GlitchData => EMAC1CLIENTRXD1_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(1)", + OutTemp => EMAC1CLIENTRXD_OUT(1), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(1), + GlitchData => EMAC1CLIENTRXD1_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(1)", + OutTemp => EMAC1CLIENTRXD_OUT(1), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(2), + GlitchData => EMAC1CLIENTRXD2_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(2)", + OutTemp => EMAC1CLIENTRXD_OUT(2), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(2), + GlitchData => EMAC1CLIENTRXD2_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(2)", + OutTemp => EMAC1CLIENTRXD_OUT(2), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(2), + GlitchData => EMAC1CLIENTRXD2_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(2)", + OutTemp => EMAC1CLIENTRXD_OUT(2), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(3), + GlitchData => EMAC1CLIENTRXD3_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(3)", + OutTemp => EMAC1CLIENTRXD_OUT(3), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(3), + GlitchData => EMAC1CLIENTRXD3_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(3)", + OutTemp => EMAC1CLIENTRXD_OUT(3), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(3), + GlitchData => EMAC1CLIENTRXD3_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(3)", + OutTemp => EMAC1CLIENTRXD_OUT(3), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(4), + GlitchData => EMAC1CLIENTRXD4_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(4)", + OutTemp => EMAC1CLIENTRXD_OUT(4), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(4), + GlitchData => EMAC1CLIENTRXD4_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(4)", + OutTemp => EMAC1CLIENTRXD_OUT(4), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(4), + GlitchData => EMAC1CLIENTRXD4_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(4)", + OutTemp => EMAC1CLIENTRXD_OUT(4), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(5), + GlitchData => EMAC1CLIENTRXD5_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(5)", + OutTemp => EMAC1CLIENTRXD_OUT(5), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(5), + GlitchData => EMAC1CLIENTRXD5_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(5)", + OutTemp => EMAC1CLIENTRXD_OUT(5), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(5), + GlitchData => EMAC1CLIENTRXD5_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(5)", + OutTemp => EMAC1CLIENTRXD_OUT(5), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(6), + GlitchData => EMAC1CLIENTRXD6_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(6)", + OutTemp => EMAC1CLIENTRXD_OUT(6), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(6), + GlitchData => EMAC1CLIENTRXD6_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(6)", + OutTemp => EMAC1CLIENTRXD_OUT(6), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(6), + GlitchData => EMAC1CLIENTRXD6_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(6)", + OutTemp => EMAC1CLIENTRXD_OUT(6), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(7), + GlitchData => EMAC1CLIENTRXD7_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(7)", + OutTemp => EMAC1CLIENTRXD_OUT(7), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(7), + GlitchData => EMAC1CLIENTRXD7_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(7)", + OutTemp => EMAC1CLIENTRXD_OUT(7), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(7), + GlitchData => EMAC1CLIENTRXD7_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(7)", + OutTemp => EMAC1CLIENTRXD_OUT(7), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(8), + GlitchData => EMAC1CLIENTRXD8_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(8)", + OutTemp => EMAC1CLIENTRXD_OUT(8), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(8), + GlitchData => EMAC1CLIENTRXD8_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(8)", + OutTemp => EMAC1CLIENTRXD_OUT(8), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(8), + GlitchData => EMAC1CLIENTRXD8_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(8)", + OutTemp => EMAC1CLIENTRXD_OUT(8), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(9), + GlitchData => EMAC1CLIENTRXD9_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(9)", + OutTemp => EMAC1CLIENTRXD_OUT(9), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(9), + GlitchData => EMAC1CLIENTRXD9_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(9)", + OutTemp => EMAC1CLIENTRXD_OUT(9), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(9), + GlitchData => EMAC1CLIENTRXD9_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(9)", + OutTemp => EMAC1CLIENTRXD_OUT(9), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(10), + GlitchData => EMAC1CLIENTRXD10_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(10)", + OutTemp => EMAC1CLIENTRXD_OUT(10), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(10), + GlitchData => EMAC1CLIENTRXD10_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(10)", + OutTemp => EMAC1CLIENTRXD_OUT(10), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(10), + GlitchData => EMAC1CLIENTRXD10_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(10)", + OutTemp => EMAC1CLIENTRXD_OUT(10), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(11), + GlitchData => EMAC1CLIENTRXD11_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(11)", + OutTemp => EMAC1CLIENTRXD_OUT(11), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(11), + GlitchData => EMAC1CLIENTRXD11_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(11)", + OutTemp => EMAC1CLIENTRXD_OUT(11), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(11), + GlitchData => EMAC1CLIENTRXD11_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(11)", + OutTemp => EMAC1CLIENTRXD_OUT(11), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(12), + GlitchData => EMAC1CLIENTRXD12_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(12)", + OutTemp => EMAC1CLIENTRXD_OUT(12), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(12), + GlitchData => EMAC1CLIENTRXD12_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(12)", + OutTemp => EMAC1CLIENTRXD_OUT(12), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(12), + GlitchData => EMAC1CLIENTRXD12_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(12)", + OutTemp => EMAC1CLIENTRXD_OUT(12), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(13), + GlitchData => EMAC1CLIENTRXD13_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(13)", + OutTemp => EMAC1CLIENTRXD_OUT(13), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(13), + GlitchData => EMAC1CLIENTRXD13_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(13)", + OutTemp => EMAC1CLIENTRXD_OUT(13), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(13), + GlitchData => EMAC1CLIENTRXD13_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(13)", + OutTemp => EMAC1CLIENTRXD_OUT(13), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(14), + GlitchData => EMAC1CLIENTRXD14_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(14)", + OutTemp => EMAC1CLIENTRXD_OUT(14), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(14), + GlitchData => EMAC1CLIENTRXD14_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(14)", + OutTemp => EMAC1CLIENTRXD_OUT(14), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(14), + GlitchData => EMAC1CLIENTRXD14_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(14)", + OutTemp => EMAC1CLIENTRXD_OUT(14), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(15), + GlitchData => EMAC1CLIENTRXD15_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(15)", + OutTemp => EMAC1CLIENTRXD_OUT(15), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(15), + GlitchData => EMAC1CLIENTRXD15_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(15)", + OutTemp => EMAC1CLIENTRXD_OUT(15), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXD(15), + GlitchData => EMAC1CLIENTRXD15_GlitchData, + OutSignalName => "EMAC1CLIENTRXD(15)", + OutTemp => EMAC1CLIENTRXD_OUT(15), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXDVLD, + GlitchData => EMAC1CLIENTRXDVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXDVLD", + OutTemp => EMAC1CLIENTRXDVLD_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXDVLD, + GlitchData => EMAC1CLIENTRXDVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXDVLD", + OutTemp => EMAC1CLIENTRXDVLD_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXDVLD, + GlitchData => EMAC1CLIENTRXDVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXDVLD", + OutTemp => EMAC1CLIENTRXDVLD_OUT, + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXDVLDMSW, + GlitchData => EMAC1CLIENTRXDVLDMSW_GlitchData, + OutSignalName => "EMAC1CLIENTRXDVLDMSW", + OutTemp => EMAC1CLIENTRXDVLDMSW_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXDVLDMSW, + GlitchData => EMAC1CLIENTRXDVLDMSW_GlitchData, + OutSignalName => "EMAC1CLIENTRXDVLDMSW", + OutTemp => EMAC1CLIENTRXDVLDMSW_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXDVLDMSW, + GlitchData => EMAC1CLIENTRXDVLDMSW_GlitchData, + OutSignalName => "EMAC1CLIENTRXDVLDMSW", + OutTemp => EMAC1CLIENTRXDVLDMSW_OUT, + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXFRAMEDROP, + GlitchData => EMAC1CLIENTRXFRAMEDROP_GlitchData, + OutSignalName => "EMAC1CLIENTRXFRAMEDROP", + OutTemp => EMAC1CLIENTRXFRAMEDROP_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXFRAMEDROP, + GlitchData => EMAC1CLIENTRXFRAMEDROP_GlitchData, + OutSignalName => "EMAC1CLIENTRXFRAMEDROP", + OutTemp => EMAC1CLIENTRXFRAMEDROP_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXFRAMEDROP, + GlitchData => EMAC1CLIENTRXFRAMEDROP_GlitchData, + OutSignalName => "EMAC1CLIENTRXFRAMEDROP", + OutTemp => EMAC1CLIENTRXFRAMEDROP_OUT, + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXGOODFRAME, + GlitchData => EMAC1CLIENTRXGOODFRAME_GlitchData, + OutSignalName => "EMAC1CLIENTRXGOODFRAME", + OutTemp => EMAC1CLIENTRXGOODFRAME_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXGOODFRAME, + GlitchData => EMAC1CLIENTRXGOODFRAME_GlitchData, + OutSignalName => "EMAC1CLIENTRXGOODFRAME", + OutTemp => EMAC1CLIENTRXGOODFRAME_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXGOODFRAME, + GlitchData => EMAC1CLIENTRXGOODFRAME_GlitchData, + OutSignalName => "EMAC1CLIENTRXGOODFRAME", + OutTemp => EMAC1CLIENTRXGOODFRAME_OUT, + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(0), + GlitchData => EMAC1CLIENTRXSTATS0_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(0)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(0), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(0), + GlitchData => EMAC1CLIENTRXSTATS0_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(0)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(0), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(0), + GlitchData => EMAC1CLIENTRXSTATS0_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(0)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(0), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(1), + GlitchData => EMAC1CLIENTRXSTATS1_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(1)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(1), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(1), + GlitchData => EMAC1CLIENTRXSTATS1_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(1)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(1), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(1), + GlitchData => EMAC1CLIENTRXSTATS1_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(1)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(1), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(2), + GlitchData => EMAC1CLIENTRXSTATS2_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(2)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(2), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(2), + GlitchData => EMAC1CLIENTRXSTATS2_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(2)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(2), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(2), + GlitchData => EMAC1CLIENTRXSTATS2_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(2)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(2), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(3), + GlitchData => EMAC1CLIENTRXSTATS3_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(3)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(3), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(3), + GlitchData => EMAC1CLIENTRXSTATS3_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(3)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(3), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(3), + GlitchData => EMAC1CLIENTRXSTATS3_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(3)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(3), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(4), + GlitchData => EMAC1CLIENTRXSTATS4_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(4)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(4), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(4), + GlitchData => EMAC1CLIENTRXSTATS4_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(4)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(4), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(4), + GlitchData => EMAC1CLIENTRXSTATS4_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(4)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(4), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(5), + GlitchData => EMAC1CLIENTRXSTATS5_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(5)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(5), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(5), + GlitchData => EMAC1CLIENTRXSTATS5_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(5)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(5), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(5), + GlitchData => EMAC1CLIENTRXSTATS5_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(5)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(5), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(6), + GlitchData => EMAC1CLIENTRXSTATS6_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(6)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(6), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(6), + GlitchData => EMAC1CLIENTRXSTATS6_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(6)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(6), + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATS(6), + GlitchData => EMAC1CLIENTRXSTATS6_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATS(6)", + OutTemp => EMAC1CLIENTRXSTATS_OUT(6), + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATSBYTEVLD, + GlitchData => EMAC1CLIENTRXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATSBYTEVLD", + OutTemp => EMAC1CLIENTRXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATSBYTEVLD, + GlitchData => EMAC1CLIENTRXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATSBYTEVLD", + OutTemp => EMAC1CLIENTRXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATSBYTEVLD, + GlitchData => EMAC1CLIENTRXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATSBYTEVLD", + OutTemp => EMAC1CLIENTRXSTATSBYTEVLD_OUT, + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATSVLD, + GlitchData => EMAC1CLIENTRXSTATSVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATSVLD", + OutTemp => EMAC1CLIENTRXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATSVLD, + GlitchData => EMAC1CLIENTRXSTATSVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATSVLD", + OutTemp => EMAC1CLIENTRXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTRXSTATSVLD, + GlitchData => EMAC1CLIENTRXSTATSVLD_GlitchData, + OutSignalName => "EMAC1CLIENTRXSTATSVLD", + OutTemp => EMAC1CLIENTRXSTATSVLD_OUT, + Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXACK, + GlitchData => EMAC1CLIENTTXACK_GlitchData, + OutSignalName => "EMAC1CLIENTTXACK", + OutTemp => EMAC1CLIENTTXACK_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXACK, + GlitchData => EMAC1CLIENTTXACK_GlitchData, + OutSignalName => "EMAC1CLIENTTXACK", + OutTemp => EMAC1CLIENTTXACK_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXACK, + GlitchData => EMAC1CLIENTTXACK_GlitchData, + OutSignalName => "EMAC1CLIENTTXACK", + OutTemp => EMAC1CLIENTTXACK_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXCLIENTCLKOUT, + GlitchData => EMAC1CLIENTTXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC1CLIENTTXCLIENTCLKOUT", + OutTemp => EMAC1CLIENTTXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXCLIENTCLKOUT, + GlitchData => EMAC1CLIENTTXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC1CLIENTTXCLIENTCLKOUT", + OutTemp => EMAC1CLIENTTXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC1MIITXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXCLIENTCLKOUT, + GlitchData => EMAC1CLIENTTXCLIENTCLKOUT_GlitchData, + OutSignalName => "EMAC1CLIENTTXCLIENTCLKOUT", + OutTemp => EMAC1CLIENTTXCLIENTCLKOUT_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXCOLLISION, + GlitchData => EMAC1CLIENTTXCOLLISION_GlitchData, + OutSignalName => "EMAC1CLIENTTXCOLLISION", + OutTemp => EMAC1CLIENTTXCOLLISION_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXCOLLISION, + GlitchData => EMAC1CLIENTTXCOLLISION_GlitchData, + OutSignalName => "EMAC1CLIENTTXCOLLISION", + OutTemp => EMAC1CLIENTTXCOLLISION_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXCOLLISION, + GlitchData => EMAC1CLIENTTXCOLLISION_GlitchData, + OutSignalName => "EMAC1CLIENTTXCOLLISION", + OutTemp => EMAC1CLIENTTXCOLLISION_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXGMIIMIICLKOUT, + GlitchData => EMAC1PHYTXGMIIMIICLKOUT_GlitchData, + OutSignalName => "EMAC1PHYTXGMIIMIICLKOUT", + OutTemp => EMAC1PHYTXGMIIMIICLKOUT_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXGMIIMIICLKOUT, + GlitchData => EMAC1PHYTXGMIIMIICLKOUT_GlitchData, + OutSignalName => "EMAC1PHYTXGMIIMIICLKOUT", + OutTemp => EMAC1PHYTXGMIIMIICLKOUT_OUT, + Paths => (0 => (PHYEMAC1MIITXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXRETRANSMIT, + GlitchData => EMAC1CLIENTTXRETRANSMIT_GlitchData, + OutSignalName => "EMAC1CLIENTTXRETRANSMIT", + OutTemp => EMAC1CLIENTTXRETRANSMIT_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXRETRANSMIT, + GlitchData => EMAC1CLIENTTXRETRANSMIT_GlitchData, + OutSignalName => "EMAC1CLIENTTXRETRANSMIT", + OutTemp => EMAC1CLIENTTXRETRANSMIT_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXRETRANSMIT, + GlitchData => EMAC1CLIENTTXRETRANSMIT_GlitchData, + OutSignalName => "EMAC1CLIENTTXRETRANSMIT", + OutTemp => EMAC1CLIENTTXRETRANSMIT_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATS, + GlitchData => EMAC1CLIENTTXSTATS_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATS", + OutTemp => EMAC1CLIENTTXSTATS_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATS, + GlitchData => EMAC1CLIENTTXSTATS_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATS", + OutTemp => EMAC1CLIENTTXSTATS_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATS, + GlitchData => EMAC1CLIENTTXSTATS_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATS", + OutTemp => EMAC1CLIENTTXSTATS_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATSBYTEVLD, + GlitchData => EMAC1CLIENTTXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATSBYTEVLD", + OutTemp => EMAC1CLIENTTXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATSBYTEVLD, + GlitchData => EMAC1CLIENTTXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATSBYTEVLD", + OutTemp => EMAC1CLIENTTXSTATSBYTEVLD_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATSBYTEVLD, + GlitchData => EMAC1CLIENTTXSTATSBYTEVLD_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATSBYTEVLD", + OutTemp => EMAC1CLIENTTXSTATSBYTEVLD_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATSVLD, + GlitchData => EMAC1CLIENTTXSTATSVLD_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATSVLD", + OutTemp => EMAC1CLIENTTXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATSVLD, + GlitchData => EMAC1CLIENTTXSTATSVLD_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATSVLD", + OutTemp => EMAC1CLIENTTXSTATSVLD_OUT, + Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1CLIENTTXSTATSVLD, + GlitchData => EMAC1CLIENTTXSTATSVLD_GlitchData, + OutSignalName => "EMAC1CLIENTTXSTATSVLD", + OutTemp => EMAC1CLIENTTXSTATSVLD_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYENCOMMAALIGN, + GlitchData => EMAC1PHYENCOMMAALIGN_GlitchData, + OutSignalName => "EMAC1PHYENCOMMAALIGN", + OutTemp => EMAC1PHYENCOMMAALIGN_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYLOOPBACKMSB, + GlitchData => EMAC1PHYLOOPBACKMSB_GlitchData, + OutSignalName => "EMAC1PHYLOOPBACKMSB", + OutTemp => EMAC1PHYLOOPBACKMSB_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMCLKOUT, + GlitchData => EMAC1PHYMCLKOUT_GlitchData, + OutSignalName => "EMAC1PHYMCLKOUT", + OutTemp => EMAC1PHYMCLKOUT_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMCLKOUT, + GlitchData => EMAC1PHYMCLKOUT_GlitchData, + OutSignalName => "EMAC1PHYMCLKOUT", + OutTemp => EMAC1PHYMCLKOUT_OUT, + Paths => (0 => (PHYEMAC1MCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMDOUT, + GlitchData => EMAC1PHYMDOUT_GlitchData, + OutSignalName => "EMAC1PHYMDOUT", + OutTemp => EMAC1PHYMDOUT_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMDOUT, + GlitchData => EMAC1PHYMDOUT_GlitchData, + OutSignalName => "EMAC1PHYMDOUT", + OutTemp => EMAC1PHYMDOUT_OUT, + Paths => (0 => (PHYEMAC1MCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMDTRI, + GlitchData => EMAC1PHYMDTRI_GlitchData, + OutSignalName => "EMAC1PHYMDTRI", + OutTemp => EMAC1PHYMDTRI_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMDTRI, + GlitchData => EMAC1PHYMDTRI_GlitchData, + OutSignalName => "EMAC1PHYMDTRI", + OutTemp => EMAC1PHYMDTRI_OUT, + Paths => (0 => (PHYEMAC1MCLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMGTRXRESET, + GlitchData => EMAC1PHYMGTRXRESET_GlitchData, + OutSignalName => "EMAC1PHYMGTRXRESET", + OutTemp => EMAC1PHYMGTRXRESET_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYMGTTXRESET, + GlitchData => EMAC1PHYMGTTXRESET_GlitchData, + OutSignalName => "EMAC1PHYMGTTXRESET", + OutTemp => EMAC1PHYMGTTXRESET_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYPOWERDOWN, + GlitchData => EMAC1PHYPOWERDOWN_GlitchData, + OutSignalName => "EMAC1PHYPOWERDOWN", + OutTemp => EMAC1PHYPOWERDOWN_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYSYNCACQSTATUS, + GlitchData => EMAC1PHYSYNCACQSTATUS_GlitchData, + OutSignalName => "EMAC1PHYSYNCACQSTATUS", + OutTemp => EMAC1PHYSYNCACQSTATUS_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYSYNCACQSTATUS, + GlitchData => EMAC1PHYSYNCACQSTATUS_GlitchData, + OutSignalName => "EMAC1PHYSYNCACQSTATUS", + OutTemp => EMAC1PHYSYNCACQSTATUS_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYSYNCACQSTATUS, + GlitchData => EMAC1PHYSYNCACQSTATUS_GlitchData, + OutSignalName => "EMAC1PHYSYNCACQSTATUS", + OutTemp => EMAC1PHYSYNCACQSTATUS_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARDISPMODE, + GlitchData => EMAC1PHYTXCHARDISPMODE_GlitchData, + OutSignalName => "EMAC1PHYTXCHARDISPMODE", + OutTemp => EMAC1PHYTXCHARDISPMODE_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARDISPMODE, + GlitchData => EMAC1PHYTXCHARDISPMODE_GlitchData, + OutSignalName => "EMAC1PHYTXCHARDISPMODE", + OutTemp => EMAC1PHYTXCHARDISPMODE_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARDISPMODE, + GlitchData => EMAC1PHYTXCHARDISPMODE_GlitchData, + OutSignalName => "EMAC1PHYTXCHARDISPMODE", + OutTemp => EMAC1PHYTXCHARDISPMODE_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARDISPVAL, + GlitchData => EMAC1PHYTXCHARDISPVAL_GlitchData, + OutSignalName => "EMAC1PHYTXCHARDISPVAL", + OutTemp => EMAC1PHYTXCHARDISPVAL_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARDISPVAL, + GlitchData => EMAC1PHYTXCHARDISPVAL_GlitchData, + OutSignalName => "EMAC1PHYTXCHARDISPVAL", + OutTemp => EMAC1PHYTXCHARDISPVAL_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARDISPVAL, + GlitchData => EMAC1PHYTXCHARDISPVAL_GlitchData, + OutSignalName => "EMAC1PHYTXCHARDISPVAL", + OutTemp => EMAC1PHYTXCHARDISPVAL_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARISK, + GlitchData => EMAC1PHYTXCHARISK_GlitchData, + OutSignalName => "EMAC1PHYTXCHARISK", + OutTemp => EMAC1PHYTXCHARISK_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARISK, + GlitchData => EMAC1PHYTXCHARISK_GlitchData, + OutSignalName => "EMAC1PHYTXCHARISK", + OutTemp => EMAC1PHYTXCHARISK_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCHARISK, + GlitchData => EMAC1PHYTXCHARISK_GlitchData, + OutSignalName => "EMAC1PHYTXCHARISK", + OutTemp => EMAC1PHYTXCHARISK_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCLK, + GlitchData => EMAC1PHYTXCLK_GlitchData, + OutSignalName => "EMAC1PHYTXCLK", + OutTemp => EMAC1PHYTXCLK_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCLK, + GlitchData => EMAC1PHYTXCLK_GlitchData, + OutSignalName => "EMAC1PHYTXCLK", + OutTemp => EMAC1PHYTXCLK_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXCLK, + GlitchData => EMAC1PHYTXCLK_GlitchData, + OutSignalName => "EMAC1PHYTXCLK", + OutTemp => EMAC1PHYTXCLK_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(0), + GlitchData => EMAC1PHYTXD0_GlitchData, + OutSignalName => "EMAC1PHYTXD(0)", + OutTemp => EMAC1PHYTXD_OUT(0), + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(0), + GlitchData => EMAC1PHYTXD0_GlitchData, + OutSignalName => "EMAC1PHYTXD(0)", + OutTemp => EMAC1PHYTXD_OUT(0), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(0), + GlitchData => EMAC1PHYTXD0_GlitchData, + OutSignalName => "EMAC1PHYTXD(0)", + OutTemp => EMAC1PHYTXD_OUT(0), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(1), + GlitchData => EMAC1PHYTXD1_GlitchData, + OutSignalName => "EMAC1PHYTXD(1)", + OutTemp => EMAC1PHYTXD_OUT(1), + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(1), + GlitchData => EMAC1PHYTXD1_GlitchData, + OutSignalName => "EMAC1PHYTXD(1)", + OutTemp => EMAC1PHYTXD_OUT(1), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(1), + GlitchData => EMAC1PHYTXD1_GlitchData, + OutSignalName => "EMAC1PHYTXD(1)", + OutTemp => EMAC1PHYTXD_OUT(1), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(2), + GlitchData => EMAC1PHYTXD2_GlitchData, + OutSignalName => "EMAC1PHYTXD(2)", + OutTemp => EMAC1PHYTXD_OUT(2), + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(2), + GlitchData => EMAC1PHYTXD2_GlitchData, + OutSignalName => "EMAC1PHYTXD(2)", + OutTemp => EMAC1PHYTXD_OUT(2), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(2), + GlitchData => EMAC1PHYTXD2_GlitchData, + OutSignalName => "EMAC1PHYTXD(2)", + OutTemp => EMAC1PHYTXD_OUT(2), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(3), + GlitchData => EMAC1PHYTXD3_GlitchData, + OutSignalName => "EMAC1PHYTXD(3)", + OutTemp => EMAC1PHYTXD_OUT(3), + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(3), + GlitchData => EMAC1PHYTXD3_GlitchData, + OutSignalName => "EMAC1PHYTXD(3)", + OutTemp => EMAC1PHYTXD_OUT(3), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(3), + GlitchData => EMAC1PHYTXD3_GlitchData, + OutSignalName => "EMAC1PHYTXD(3)", + OutTemp => EMAC1PHYTXD_OUT(3), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(4), + GlitchData => EMAC1PHYTXD4_GlitchData, + OutSignalName => "EMAC1PHYTXD(4)", + OutTemp => EMAC1PHYTXD_OUT(4), + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(4), + GlitchData => EMAC1PHYTXD4_GlitchData, + OutSignalName => "EMAC1PHYTXD(4)", + OutTemp => EMAC1PHYTXD_OUT(4), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(4), + GlitchData => EMAC1PHYTXD4_GlitchData, + OutSignalName => "EMAC1PHYTXD(4)", + OutTemp => EMAC1PHYTXD_OUT(4), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(4), + GlitchData => EMAC1PHYTXD4_GlitchData, + OutSignalName => "EMAC1PHYTXD(4)", + OutTemp => EMAC1PHYTXD_OUT(4), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(5), + GlitchData => EMAC1PHYTXD5_GlitchData, + OutSignalName => "EMAC1PHYTXD(5)", + OutTemp => EMAC1PHYTXD_OUT(5), + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(5), + GlitchData => EMAC1PHYTXD5_GlitchData, + OutSignalName => "EMAC1PHYTXD(5)", + OutTemp => EMAC1PHYTXD_OUT(5), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(5), + GlitchData => EMAC1PHYTXD5_GlitchData, + OutSignalName => "EMAC1PHYTXD(5)", + OutTemp => EMAC1PHYTXD_OUT(5), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(5), + GlitchData => EMAC1PHYTXD5_GlitchData, + OutSignalName => "EMAC1PHYTXD(5)", + OutTemp => EMAC1PHYTXD_OUT(5), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(6), + GlitchData => EMAC1PHYTXD6_GlitchData, + OutSignalName => "EMAC1PHYTXD(6)", + OutTemp => EMAC1PHYTXD_OUT(6), + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(6), + GlitchData => EMAC1PHYTXD6_GlitchData, + OutSignalName => "EMAC1PHYTXD(6)", + OutTemp => EMAC1PHYTXD_OUT(6), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(6), + GlitchData => EMAC1PHYTXD6_GlitchData, + OutSignalName => "EMAC1PHYTXD(6)", + OutTemp => EMAC1PHYTXD_OUT(6), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(6), + GlitchData => EMAC1PHYTXD6_GlitchData, + OutSignalName => "EMAC1PHYTXD(6)", + OutTemp => EMAC1PHYTXD_OUT(6), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(7), + GlitchData => EMAC1PHYTXD7_GlitchData, + OutSignalName => "EMAC1PHYTXD(7)", + OutTemp => EMAC1PHYTXD_OUT(7), + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(7), + GlitchData => EMAC1PHYTXD7_GlitchData, + OutSignalName => "EMAC1PHYTXD(7)", + OutTemp => EMAC1PHYTXD_OUT(7), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(7), + GlitchData => EMAC1PHYTXD7_GlitchData, + OutSignalName => "EMAC1PHYTXD(7)", + OutTemp => EMAC1PHYTXD_OUT(7), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXD(7), + GlitchData => EMAC1PHYTXD7_GlitchData, + OutSignalName => "EMAC1PHYTXD(7)", + OutTemp => EMAC1PHYTXD_OUT(7), + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXEN, + GlitchData => EMAC1PHYTXEN_GlitchData, + OutSignalName => "EMAC1PHYTXEN", + OutTemp => EMAC1PHYTXEN_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXEN, + GlitchData => EMAC1PHYTXEN_GlitchData, + OutSignalName => "EMAC1PHYTXEN", + OutTemp => EMAC1PHYTXEN_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXEN, + GlitchData => EMAC1PHYTXEN_GlitchData, + OutSignalName => "EMAC1PHYTXEN", + OutTemp => EMAC1PHYTXEN_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXER, + GlitchData => EMAC1PHYTXER_GlitchData, + OutSignalName => "EMAC1PHYTXER", + OutTemp => EMAC1PHYTXER_OUT, + Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXER, + GlitchData => EMAC1PHYTXER_GlitchData, + OutSignalName => "EMAC1PHYTXER", + OutTemp => EMAC1PHYTXER_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXER, + GlitchData => EMAC1PHYTXER_GlitchData, + OutSignalName => "EMAC1PHYTXER", + OutTemp => EMAC1PHYTXER_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1PHYTXER, + GlitchData => EMAC1PHYTXER_GlitchData, + OutSignalName => "EMAC1PHYTXER", + OutTemp => EMAC1PHYTXER_OUT, + Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMAC1SPEEDIS10100, + GlitchData => EMAC1SPEEDIS10100_GlitchData, + OutSignalName => "EMAC1SPEEDIS10100", + OutTemp => EMAC1SPEEDIS10100_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRACK, + GlitchData => EMACDCRACK_GlitchData, + OutSignalName => "EMACDCRACK", + OutTemp => EMACDCRACK_OUT, + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(0), + GlitchData => EMACDCRDBUS0_GlitchData, + OutSignalName => "EMACDCRDBUS(0)", + OutTemp => EMACDCRDBUS_OUT(0), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(1), + GlitchData => EMACDCRDBUS1_GlitchData, + OutSignalName => "EMACDCRDBUS(1)", + OutTemp => EMACDCRDBUS_OUT(1), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(2), + GlitchData => EMACDCRDBUS2_GlitchData, + OutSignalName => "EMACDCRDBUS(2)", + OutTemp => EMACDCRDBUS_OUT(2), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(3), + GlitchData => EMACDCRDBUS3_GlitchData, + OutSignalName => "EMACDCRDBUS(3)", + OutTemp => EMACDCRDBUS_OUT(3), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(4), + GlitchData => EMACDCRDBUS4_GlitchData, + OutSignalName => "EMACDCRDBUS(4)", + OutTemp => EMACDCRDBUS_OUT(4), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(5), + GlitchData => EMACDCRDBUS5_GlitchData, + OutSignalName => "EMACDCRDBUS(5)", + OutTemp => EMACDCRDBUS_OUT(5), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(6), + GlitchData => EMACDCRDBUS6_GlitchData, + OutSignalName => "EMACDCRDBUS(6)", + OutTemp => EMACDCRDBUS_OUT(6), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(7), + GlitchData => EMACDCRDBUS7_GlitchData, + OutSignalName => "EMACDCRDBUS(7)", + OutTemp => EMACDCRDBUS_OUT(7), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(8), + GlitchData => EMACDCRDBUS8_GlitchData, + OutSignalName => "EMACDCRDBUS(8)", + OutTemp => EMACDCRDBUS_OUT(8), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(9), + GlitchData => EMACDCRDBUS9_GlitchData, + OutSignalName => "EMACDCRDBUS(9)", + OutTemp => EMACDCRDBUS_OUT(9), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(10), + GlitchData => EMACDCRDBUS10_GlitchData, + OutSignalName => "EMACDCRDBUS(10)", + OutTemp => EMACDCRDBUS_OUT(10), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(11), + GlitchData => EMACDCRDBUS11_GlitchData, + OutSignalName => "EMACDCRDBUS(11)", + OutTemp => EMACDCRDBUS_OUT(11), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(12), + GlitchData => EMACDCRDBUS12_GlitchData, + OutSignalName => "EMACDCRDBUS(12)", + OutTemp => EMACDCRDBUS_OUT(12), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(13), + GlitchData => EMACDCRDBUS13_GlitchData, + OutSignalName => "EMACDCRDBUS(13)", + OutTemp => EMACDCRDBUS_OUT(13), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(14), + GlitchData => EMACDCRDBUS14_GlitchData, + OutSignalName => "EMACDCRDBUS(14)", + OutTemp => EMACDCRDBUS_OUT(14), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(15), + GlitchData => EMACDCRDBUS15_GlitchData, + OutSignalName => "EMACDCRDBUS(15)", + OutTemp => EMACDCRDBUS_OUT(15), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(16), + GlitchData => EMACDCRDBUS16_GlitchData, + OutSignalName => "EMACDCRDBUS(16)", + OutTemp => EMACDCRDBUS_OUT(16), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(17), + GlitchData => EMACDCRDBUS17_GlitchData, + OutSignalName => "EMACDCRDBUS(17)", + OutTemp => EMACDCRDBUS_OUT(17), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(18), + GlitchData => EMACDCRDBUS18_GlitchData, + OutSignalName => "EMACDCRDBUS(18)", + OutTemp => EMACDCRDBUS_OUT(18), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(19), + GlitchData => EMACDCRDBUS19_GlitchData, + OutSignalName => "EMACDCRDBUS(19)", + OutTemp => EMACDCRDBUS_OUT(19), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(20), + GlitchData => EMACDCRDBUS20_GlitchData, + OutSignalName => "EMACDCRDBUS(20)", + OutTemp => EMACDCRDBUS_OUT(20), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(21), + GlitchData => EMACDCRDBUS21_GlitchData, + OutSignalName => "EMACDCRDBUS(21)", + OutTemp => EMACDCRDBUS_OUT(21), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(22), + GlitchData => EMACDCRDBUS22_GlitchData, + OutSignalName => "EMACDCRDBUS(22)", + OutTemp => EMACDCRDBUS_OUT(22), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(23), + GlitchData => EMACDCRDBUS23_GlitchData, + OutSignalName => "EMACDCRDBUS(23)", + OutTemp => EMACDCRDBUS_OUT(23), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(24), + GlitchData => EMACDCRDBUS24_GlitchData, + OutSignalName => "EMACDCRDBUS(24)", + OutTemp => EMACDCRDBUS_OUT(24), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(25), + GlitchData => EMACDCRDBUS25_GlitchData, + OutSignalName => "EMACDCRDBUS(25)", + OutTemp => EMACDCRDBUS_OUT(25), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(26), + GlitchData => EMACDCRDBUS26_GlitchData, + OutSignalName => "EMACDCRDBUS(26)", + OutTemp => EMACDCRDBUS_OUT(26), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(27), + GlitchData => EMACDCRDBUS27_GlitchData, + OutSignalName => "EMACDCRDBUS(27)", + OutTemp => EMACDCRDBUS_OUT(27), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(28), + GlitchData => EMACDCRDBUS28_GlitchData, + OutSignalName => "EMACDCRDBUS(28)", + OutTemp => EMACDCRDBUS_OUT(28), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(29), + GlitchData => EMACDCRDBUS29_GlitchData, + OutSignalName => "EMACDCRDBUS(29)", + OutTemp => EMACDCRDBUS_OUT(29), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(30), + GlitchData => EMACDCRDBUS30_GlitchData, + OutSignalName => "EMACDCRDBUS(30)", + OutTemp => EMACDCRDBUS_OUT(30), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => EMACDCRDBUS(31), + GlitchData => EMACDCRDBUS31_GlitchData, + OutSignalName => "EMACDCRDBUS(31)", + OutTemp => EMACDCRDBUS_OUT(31), + Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTMIIMRDY, + GlitchData => HOSTMIIMRDY_GlitchData, + OutSignalName => "HOSTMIIMRDY", + OutTemp => HOSTMIIMRDY_OUT, + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(0), + GlitchData => HOSTRDDATA0_GlitchData, + OutSignalName => "HOSTRDDATA(0)", + OutTemp => HOSTRDDATA_OUT(0), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(1), + GlitchData => HOSTRDDATA1_GlitchData, + OutSignalName => "HOSTRDDATA(1)", + OutTemp => HOSTRDDATA_OUT(1), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(2), + GlitchData => HOSTRDDATA2_GlitchData, + OutSignalName => "HOSTRDDATA(2)", + OutTemp => HOSTRDDATA_OUT(2), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(3), + GlitchData => HOSTRDDATA3_GlitchData, + OutSignalName => "HOSTRDDATA(3)", + OutTemp => HOSTRDDATA_OUT(3), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(4), + GlitchData => HOSTRDDATA4_GlitchData, + OutSignalName => "HOSTRDDATA(4)", + OutTemp => HOSTRDDATA_OUT(4), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(5), + GlitchData => HOSTRDDATA5_GlitchData, + OutSignalName => "HOSTRDDATA(5)", + OutTemp => HOSTRDDATA_OUT(5), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(6), + GlitchData => HOSTRDDATA6_GlitchData, + OutSignalName => "HOSTRDDATA(6)", + OutTemp => HOSTRDDATA_OUT(6), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(7), + GlitchData => HOSTRDDATA7_GlitchData, + OutSignalName => "HOSTRDDATA(7)", + OutTemp => HOSTRDDATA_OUT(7), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(8), + GlitchData => HOSTRDDATA8_GlitchData, + OutSignalName => "HOSTRDDATA(8)", + OutTemp => HOSTRDDATA_OUT(8), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(9), + GlitchData => HOSTRDDATA9_GlitchData, + OutSignalName => "HOSTRDDATA(9)", + OutTemp => HOSTRDDATA_OUT(9), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(10), + GlitchData => HOSTRDDATA10_GlitchData, + OutSignalName => "HOSTRDDATA(10)", + OutTemp => HOSTRDDATA_OUT(10), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(11), + GlitchData => HOSTRDDATA11_GlitchData, + OutSignalName => "HOSTRDDATA(11)", + OutTemp => HOSTRDDATA_OUT(11), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(12), + GlitchData => HOSTRDDATA12_GlitchData, + OutSignalName => "HOSTRDDATA(12)", + OutTemp => HOSTRDDATA_OUT(12), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(13), + GlitchData => HOSTRDDATA13_GlitchData, + OutSignalName => "HOSTRDDATA(13)", + OutTemp => HOSTRDDATA_OUT(13), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(14), + GlitchData => HOSTRDDATA14_GlitchData, + OutSignalName => "HOSTRDDATA(14)", + OutTemp => HOSTRDDATA_OUT(14), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(15), + GlitchData => HOSTRDDATA15_GlitchData, + OutSignalName => "HOSTRDDATA(15)", + OutTemp => HOSTRDDATA_OUT(15), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(16), + GlitchData => HOSTRDDATA16_GlitchData, + OutSignalName => "HOSTRDDATA(16)", + OutTemp => HOSTRDDATA_OUT(16), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(17), + GlitchData => HOSTRDDATA17_GlitchData, + OutSignalName => "HOSTRDDATA(17)", + OutTemp => HOSTRDDATA_OUT(17), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(18), + GlitchData => HOSTRDDATA18_GlitchData, + OutSignalName => "HOSTRDDATA(18)", + OutTemp => HOSTRDDATA_OUT(18), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(19), + GlitchData => HOSTRDDATA19_GlitchData, + OutSignalName => "HOSTRDDATA(19)", + OutTemp => HOSTRDDATA_OUT(19), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(20), + GlitchData => HOSTRDDATA20_GlitchData, + OutSignalName => "HOSTRDDATA(20)", + OutTemp => HOSTRDDATA_OUT(20), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(21), + GlitchData => HOSTRDDATA21_GlitchData, + OutSignalName => "HOSTRDDATA(21)", + OutTemp => HOSTRDDATA_OUT(21), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(22), + GlitchData => HOSTRDDATA22_GlitchData, + OutSignalName => "HOSTRDDATA(22)", + OutTemp => HOSTRDDATA_OUT(22), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(23), + GlitchData => HOSTRDDATA23_GlitchData, + OutSignalName => "HOSTRDDATA(23)", + OutTemp => HOSTRDDATA_OUT(23), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(24), + GlitchData => HOSTRDDATA24_GlitchData, + OutSignalName => "HOSTRDDATA(24)", + OutTemp => HOSTRDDATA_OUT(24), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(25), + GlitchData => HOSTRDDATA25_GlitchData, + OutSignalName => "HOSTRDDATA(25)", + OutTemp => HOSTRDDATA_OUT(25), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(26), + GlitchData => HOSTRDDATA26_GlitchData, + OutSignalName => "HOSTRDDATA(26)", + OutTemp => HOSTRDDATA_OUT(26), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(27), + GlitchData => HOSTRDDATA27_GlitchData, + OutSignalName => "HOSTRDDATA(27)", + OutTemp => HOSTRDDATA_OUT(27), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(28), + GlitchData => HOSTRDDATA28_GlitchData, + OutSignalName => "HOSTRDDATA(28)", + OutTemp => HOSTRDDATA_OUT(28), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(29), + GlitchData => HOSTRDDATA29_GlitchData, + OutSignalName => "HOSTRDDATA(29)", + OutTemp => HOSTRDDATA_OUT(29), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(30), + GlitchData => HOSTRDDATA30_GlitchData, + OutSignalName => "HOSTRDDATA(30)", + OutTemp => HOSTRDDATA_OUT(30), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => HOSTRDDATA(31), + GlitchData => HOSTRDDATA31_GlitchData, + OutSignalName => "HOSTRDDATA(31)", + OutTemp => HOSTRDDATA_OUT(31), + Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + + + wait on + DCRHOSTDONEIR_out, + EMAC0CLIENTANINTERRUPT_out, + EMAC0CLIENTRXBADFRAME_out, + EMAC0CLIENTRXCLIENTCLKOUT_out, + EMAC0CLIENTRXDVLDMSW_out, + EMAC0CLIENTRXDVLD_out, + EMAC0CLIENTRXD_out, + EMAC0CLIENTRXFRAMEDROP_out, + EMAC0CLIENTRXGOODFRAME_out, + EMAC0CLIENTRXSTATSBYTEVLD_out, + EMAC0CLIENTRXSTATSVLD_out, + EMAC0CLIENTRXSTATS_out, + EMAC0CLIENTTXACK_out, + EMAC0CLIENTTXCLIENTCLKOUT_out, + EMAC0CLIENTTXCOLLISION_out, + EMAC0CLIENTTXRETRANSMIT_out, + EMAC0CLIENTTXSTATSBYTEVLD_out, + EMAC0CLIENTTXSTATSVLD_out, + EMAC0CLIENTTXSTATS_out, + EMAC0PHYENCOMMAALIGN_out, + EMAC0PHYLOOPBACKMSB_out, + EMAC0PHYMCLKOUT_out, + EMAC0PHYMDOUT_out, + EMAC0PHYMDTRI_out, + EMAC0PHYMGTRXRESET_out, + EMAC0PHYMGTTXRESET_out, + EMAC0PHYPOWERDOWN_out, + EMAC0PHYSYNCACQSTATUS_out, + EMAC0PHYTXCHARDISPMODE_out, + EMAC0PHYTXCHARDISPVAL_out, + EMAC0PHYTXCHARISK_out, + EMAC0PHYTXCLK_out, + EMAC0PHYTXD_out, + EMAC0PHYTXEN_out, + EMAC0PHYTXER_out, + EMAC0PHYTXGMIIMIICLKOUT_out, + EMAC0SPEEDIS10100_out, + EMAC1CLIENTANINTERRUPT_out, + EMAC1CLIENTRXBADFRAME_out, + EMAC1CLIENTRXCLIENTCLKOUT_out, + EMAC1CLIENTRXDVLDMSW_out, + EMAC1CLIENTRXDVLD_out, + EMAC1CLIENTRXD_out, + EMAC1CLIENTRXFRAMEDROP_out, + EMAC1CLIENTRXGOODFRAME_out, + EMAC1CLIENTRXSTATSBYTEVLD_out, + EMAC1CLIENTRXSTATSVLD_out, + EMAC1CLIENTRXSTATS_out, + EMAC1CLIENTTXACK_out, + EMAC1CLIENTTXCLIENTCLKOUT_out, + EMAC1CLIENTTXCOLLISION_out, + EMAC1CLIENTTXRETRANSMIT_out, + EMAC1CLIENTTXSTATSBYTEVLD_out, + EMAC1CLIENTTXSTATSVLD_out, + EMAC1CLIENTTXSTATS_out, + EMAC1PHYENCOMMAALIGN_out, + EMAC1PHYLOOPBACKMSB_out, + EMAC1PHYMCLKOUT_out, + EMAC1PHYMDOUT_out, + EMAC1PHYMDTRI_out, + EMAC1PHYMGTRXRESET_out, + EMAC1PHYMGTTXRESET_out, + EMAC1PHYPOWERDOWN_out, + EMAC1PHYSYNCACQSTATUS_out, + EMAC1PHYTXCHARDISPMODE_out, + EMAC1PHYTXCHARDISPVAL_out, + EMAC1PHYTXCHARISK_out, + EMAC1PHYTXCLK_out, + EMAC1PHYTXD_out, + EMAC1PHYTXEN_out, + EMAC1PHYTXER_out, + EMAC1PHYTXGMIIMIICLKOUT_out, + EMAC1SPEEDIS10100_out, + EMACDCRACK_out, + EMACDCRDBUS_out, + HOSTMIIMRDY_out, + HOSTRDDATA_out, + + CLIENTEMAC0DCMLOCKED_ipd, + CLIENTEMAC0PAUSEREQ_ipd, + CLIENTEMAC0PAUSEVAL_ipd, + CLIENTEMAC0RXCLIENTCLKIN_ipd, + CLIENTEMAC0TXCLIENTCLKIN_ipd, + CLIENTEMAC0TXDVLDMSW_ipd, + CLIENTEMAC0TXDVLD_ipd, + CLIENTEMAC0TXD_ipd, + CLIENTEMAC0TXFIRSTBYTE_ipd, + CLIENTEMAC0TXIFGDELAY_ipd, + CLIENTEMAC0TXUNDERRUN_ipd, + CLIENTEMAC1DCMLOCKED_ipd, + CLIENTEMAC1PAUSEREQ_ipd, + CLIENTEMAC1PAUSEVAL_ipd, + CLIENTEMAC1RXCLIENTCLKIN_ipd, + CLIENTEMAC1TXCLIENTCLKIN_ipd, + CLIENTEMAC1TXDVLDMSW_ipd, + CLIENTEMAC1TXDVLD_ipd, + CLIENTEMAC1TXD_ipd, + CLIENTEMAC1TXFIRSTBYTE_ipd, + CLIENTEMAC1TXIFGDELAY_ipd, + CLIENTEMAC1TXUNDERRUN_ipd, + DCREMACABUS_ipd, + DCREMACCLK_ipd, + DCREMACDBUS_ipd, + DCREMACENABLE_ipd, + DCREMACREAD_ipd, + DCREMACWRITE_ipd, + HOSTADDR_ipd, + HOSTCLK_ipd, + HOSTEMAC1SEL_ipd, + HOSTMIIMSEL_ipd, + HOSTOPCODE_ipd, + HOSTREQ_ipd, + HOSTWRDATA_ipd, + PHYEMAC0COL_ipd, + PHYEMAC0CRS_ipd, + PHYEMAC0GTXCLK_ipd, + PHYEMAC0MCLKIN_ipd, + PHYEMAC0MDIN_ipd, + PHYEMAC0MIITXCLK_ipd, + PHYEMAC0PHYAD_ipd, + PHYEMAC0RXBUFERR_ipd, + PHYEMAC0RXBUFSTATUS_ipd, + PHYEMAC0RXCHARISCOMMA_ipd, + PHYEMAC0RXCHARISK_ipd, + PHYEMAC0RXCHECKINGCRC_ipd, + PHYEMAC0RXCLKCORCNT_ipd, + PHYEMAC0RXCLK_ipd, + PHYEMAC0RXCOMMADET_ipd, + PHYEMAC0RXDISPERR_ipd, + PHYEMAC0RXDV_ipd, + PHYEMAC0RXD_ipd, + PHYEMAC0RXER_ipd, + PHYEMAC0RXLOSSOFSYNC_ipd, + PHYEMAC0RXNOTINTABLE_ipd, + PHYEMAC0RXRUNDISP_ipd, + PHYEMAC0SIGNALDET_ipd, + PHYEMAC0TXBUFERR_ipd, + PHYEMAC0TXGMIIMIICLKIN_ipd, + PHYEMAC1COL_ipd, + PHYEMAC1CRS_ipd, + PHYEMAC1GTXCLK_ipd, + PHYEMAC1MCLKIN_ipd, + PHYEMAC1MDIN_ipd, + PHYEMAC1MIITXCLK_ipd, + PHYEMAC1PHYAD_ipd, + PHYEMAC1RXBUFERR_ipd, + PHYEMAC1RXBUFSTATUS_ipd, + PHYEMAC1RXCHARISCOMMA_ipd, + PHYEMAC1RXCHARISK_ipd, + PHYEMAC1RXCHECKINGCRC_ipd, + PHYEMAC1RXCLKCORCNT_ipd, + PHYEMAC1RXCLK_ipd, + PHYEMAC1RXCOMMADET_ipd, + PHYEMAC1RXDISPERR_ipd, + PHYEMAC1RXDV_ipd, + PHYEMAC1RXD_ipd, + PHYEMAC1RXER_ipd, + PHYEMAC1RXLOSSOFSYNC_ipd, + PHYEMAC1RXNOTINTABLE_ipd, + PHYEMAC1RXRUNDISP_ipd, + PHYEMAC1SIGNALDET_ipd, + PHYEMAC1TXBUFERR_ipd, + PHYEMAC1TXGMIIMIICLKIN_ipd, + RESET_ipd; + + end process TIMING; +end TEMAC_V; +------------------------------------------------------- +-- Copyright (c) 1995/2006 Xilinx Inc. +-- All Right Reserved. +------------------------------------------------------- +-- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : +-- / / +-- /___/ /\ Filename : GTX_DUAL.vhd +-- \ \ / \ Timestamp : Tue Jan 9 10:05:31 2007 +-- \__ \/\__ \ +-- +-- 09/12/06 - CR#423671 - Initial version. +-- 12/05/06 - CR#426138 - J.31 spreadsheet update +-- 01/23/07 - CR#430426 - J.32 pinTime added +-- 02/20/07 - CR#434096 - Parameter default value update PLL_RXDIVSEL_OUT_0/1 +-- 06/18/07 - CR#441601 - BT1445 - Test attributes made visible +-- 06/18/07 - CR#441576 - BT1488 - Add STEPPING attribute +-- 10/05/07 - CR#451343 - BT1514 - Add ES1 (ES1 mapped to 0) as STEPPING value +-- 11/05/07 - CR#452590 - BT1514 - Remove STEPPING attribute from unisim/simprim wrapper +-- 02/05/08 - CR#459742 - Attribute default changes +-- 03/14/08 - CR#468285 - Updated timing checks +-- 03/17/08 - CR#467692 - Add SIM_MODE attribute with values LEGACY & FAST model +-- 04/24/08 - CR#472011 - OOBDETECT_THRESHOLD_0/1 default from 001 to 110, range changes from 000-111 to 110-111 +-- 05/13/08 - CR#472931 - OOBDETECT_THRESHOLD_0/1 case statement updates +-- 06/24/08 - CR472608, CR472665 - Update SIM_MODE default to FAST +------------------------------------------------------- + +----- CELL GTX_DUAL ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; + + +library unisim; +use unisim.VCOMPONENTS.all; + +entity GTX_DUAL is +generic ( + AC_CAP_DIS_0 : boolean := TRUE; + AC_CAP_DIS_1 : boolean := TRUE; + ALIGN_COMMA_WORD_0 : integer := 1; + ALIGN_COMMA_WORD_1 : integer := 1; + CB2_INH_CC_PERIOD_0 : integer := 8; + CB2_INH_CC_PERIOD_1 : integer := 8; + CDR_PH_ADJ_TIME : bit_vector := "01010"; + CHAN_BOND_1_MAX_SKEW_0 : integer := 7; + CHAN_BOND_1_MAX_SKEW_1 : integer := 7; + CHAN_BOND_2_MAX_SKEW_0 : integer := 7; + CHAN_BOND_2_MAX_SKEW_1 : integer := 7; + CHAN_BOND_KEEP_ALIGN_0 : boolean := FALSE; + CHAN_BOND_KEEP_ALIGN_1 : boolean := FALSE; + CHAN_BOND_LEVEL_0 : integer := 0; + CHAN_BOND_LEVEL_1 : integer := 0; + CHAN_BOND_MODE_0 : string := "OFF"; + CHAN_BOND_MODE_1 : string := "OFF"; + CHAN_BOND_SEQ_1_1_0 : bit_vector := "0101111100"; + CHAN_BOND_SEQ_1_1_1 : bit_vector := "0101111100"; + CHAN_BOND_SEQ_1_2_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_2_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_3_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_3_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_4_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_4_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_1_ENABLE_0 : bit_vector := "0001"; + CHAN_BOND_SEQ_1_ENABLE_1 : bit_vector := "0001"; + CHAN_BOND_SEQ_2_1_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_1_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_2_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_2_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_3_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_3_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_4_0 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_4_1 : bit_vector := "0000000000"; + CHAN_BOND_SEQ_2_ENABLE_0 : bit_vector := "0000"; + CHAN_BOND_SEQ_2_ENABLE_1 : bit_vector := "0000"; + CHAN_BOND_SEQ_2_USE_0 : boolean := FALSE; + CHAN_BOND_SEQ_2_USE_1 : boolean := FALSE; + CHAN_BOND_SEQ_LEN_0 : integer := 1; + CHAN_BOND_SEQ_LEN_1 : integer := 1; + CLK25_DIVIDER : integer := 10; + CLKINDC_B : boolean := TRUE; + CLKRCV_TRST : boolean := TRUE; + CLK_CORRECT_USE_0 : boolean := TRUE; + CLK_CORRECT_USE_1 : boolean := TRUE; + CLK_COR_ADJ_LEN_0 : integer := 1; + CLK_COR_ADJ_LEN_1 : integer := 1; + CLK_COR_DET_LEN_0 : integer := 1; + CLK_COR_DET_LEN_1 : integer := 1; + CLK_COR_INSERT_IDLE_FLAG_0 : boolean := FALSE; + CLK_COR_INSERT_IDLE_FLAG_1 : boolean := FALSE; + CLK_COR_KEEP_IDLE_0 : boolean := FALSE; + CLK_COR_KEEP_IDLE_1 : boolean := FALSE; + CLK_COR_MAX_LAT_0 : integer := 20; + CLK_COR_MAX_LAT_1 : integer := 20; + CLK_COR_MIN_LAT_0 : integer := 18; + CLK_COR_MIN_LAT_1 : integer := 18; + CLK_COR_PRECEDENCE_0 : boolean := TRUE; + CLK_COR_PRECEDENCE_1 : boolean := TRUE; + CLK_COR_REPEAT_WAIT_0 : integer := 0; + CLK_COR_REPEAT_WAIT_1 : integer := 0; + CLK_COR_SEQ_1_1_0 : bit_vector := "0100011100"; + CLK_COR_SEQ_1_1_1 : bit_vector := "0100011100"; + CLK_COR_SEQ_1_2_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_2_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_3_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_3_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_4_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_4_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_1_ENABLE_0 : bit_vector := "0001"; + CLK_COR_SEQ_1_ENABLE_1 : bit_vector := "0001"; + CLK_COR_SEQ_2_1_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_1_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_2_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_2_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_3_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_3_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_4_0 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_4_1 : bit_vector := "0000000000"; + CLK_COR_SEQ_2_ENABLE_0 : bit_vector := "0000"; + CLK_COR_SEQ_2_ENABLE_1 : bit_vector := "0000"; + CLK_COR_SEQ_2_USE_0 : boolean := FALSE; + CLK_COR_SEQ_2_USE_1 : boolean := FALSE; + CM_TRIM_0 : bit_vector := "10"; + CM_TRIM_1 : bit_vector := "10"; + COMMA_10B_ENABLE_0 : bit_vector := "0001111111"; + COMMA_10B_ENABLE_1 : bit_vector := "0001111111"; + COMMA_DOUBLE_0 : boolean := FALSE; + COMMA_DOUBLE_1 : boolean := FALSE; + COM_BURST_VAL_0 : bit_vector := "1111"; + COM_BURST_VAL_1 : bit_vector := "1111"; + DEC_MCOMMA_DETECT_0 : boolean := TRUE; + DEC_MCOMMA_DETECT_1 : boolean := TRUE; + DEC_PCOMMA_DETECT_0 : boolean := TRUE; + DEC_PCOMMA_DETECT_1 : boolean := TRUE; + DEC_VALID_COMMA_ONLY_0 : boolean := TRUE; + DEC_VALID_COMMA_ONLY_1 : boolean := TRUE; + DFE_CAL_TIME : bit_vector := "00110"; + DFE_CFG_0 : bit_vector := "1101111011"; + DFE_CFG_1 : bit_vector := "1101111011"; + GEARBOX_ENDEC_0 : bit_vector := "000"; + GEARBOX_ENDEC_1 : bit_vector := "000"; + MCOMMA_10B_VALUE_0 : bit_vector := "1010000011"; + MCOMMA_10B_VALUE_1 : bit_vector := "1010000011"; + MCOMMA_DETECT_0 : boolean := TRUE; + MCOMMA_DETECT_1 : boolean := TRUE; + OOBDETECT_THRESHOLD_0 : bit_vector := "110"; + OOBDETECT_THRESHOLD_1 : bit_vector := "110"; + OOB_CLK_DIVIDER : integer := 6; + OVERSAMPLE_MODE : boolean := FALSE; + PCI_EXPRESS_MODE_0 : boolean := FALSE; + PCI_EXPRESS_MODE_1 : boolean := FALSE; + PCOMMA_10B_VALUE_0 : bit_vector := "0101111100"; + PCOMMA_10B_VALUE_1 : bit_vector := "0101111100"; + PCOMMA_DETECT_0 : boolean := TRUE; + PCOMMA_DETECT_1 : boolean := TRUE; + PLL_COM_CFG : bit_vector := X"21680a"; + PLL_CP_CFG : bit_vector := X"00"; + PLL_DIVSEL_FB : integer := 2; + PLL_DIVSEL_REF : integer := 1; + PLL_FB_DCCEN : boolean := FALSE; + PLL_LKDET_CFG : bit_vector := "101"; + PLL_RXDIVSEL_OUT_0 : integer := 1; + PLL_RXDIVSEL_OUT_1 : integer := 1; + PLL_SATA_0 : boolean := FALSE; + PLL_SATA_1 : boolean := FALSE; + PLL_TDCC_CFG : bit_vector := "000"; + PLL_TXDIVSEL_OUT_0 : integer := 1; + PLL_TXDIVSEL_OUT_1 : integer := 1; + PMA_CDR_SCAN_0 : bit_vector := X"6404035"; + PMA_CDR_SCAN_1 : bit_vector := X"6404035"; + PMA_COM_CFG : bit_vector := X"000000000000000000"; + PMA_RXSYNC_CFG_0 : bit_vector := X"00"; + PMA_RXSYNC_CFG_1 : bit_vector := X"00"; + PMA_RX_CFG_0 : bit_vector := X"0f44089"; + PMA_RX_CFG_1 : bit_vector := X"0f44089"; + PMA_TX_CFG_0 : bit_vector := X"80082"; + PMA_TX_CFG_1 : bit_vector := X"80082"; + PRBS_ERR_THRESHOLD_0 : bit_vector := X"00000001"; + PRBS_ERR_THRESHOLD_1 : bit_vector := X"00000001"; + RCV_TERM_GND_0 : boolean := FALSE; + RCV_TERM_GND_1 : boolean := FALSE; + RCV_TERM_VTTRX_0 : boolean := FALSE; + RCV_TERM_VTTRX_1 : boolean := FALSE; + RXGEARBOX_USE_0 : boolean := FALSE; + RXGEARBOX_USE_1 : boolean := FALSE; + RX_BUFFER_USE_0 : boolean := TRUE; + RX_BUFFER_USE_1 : boolean := TRUE; + RX_DECODE_SEQ_MATCH_0 : boolean := TRUE; + RX_DECODE_SEQ_MATCH_1 : boolean := TRUE; + RX_EN_IDLE_HOLD_CDR : boolean := FALSE; + RX_EN_IDLE_HOLD_DFE_0 : boolean := TRUE; + RX_EN_IDLE_HOLD_DFE_1 : boolean := TRUE; + RX_EN_IDLE_RESET_BUF_0 : boolean := TRUE; + RX_EN_IDLE_RESET_BUF_1 : boolean := TRUE; + RX_EN_IDLE_RESET_FR : boolean := TRUE; + RX_EN_IDLE_RESET_PH : boolean := TRUE; + RX_IDLE_HI_CNT_0 : bit_vector := "1000"; + RX_IDLE_HI_CNT_1 : bit_vector := "1000"; + RX_IDLE_LO_CNT_0 : bit_vector := "0000"; + RX_IDLE_LO_CNT_1 : bit_vector := "0000"; + RX_LOSS_OF_SYNC_FSM_0 : boolean := FALSE; + RX_LOSS_OF_SYNC_FSM_1 : boolean := FALSE; + RX_LOS_INVALID_INCR_0 : integer := 1; + RX_LOS_INVALID_INCR_1 : integer := 1; + RX_LOS_THRESHOLD_0 : integer := 4; + RX_LOS_THRESHOLD_1 : integer := 4; + RX_SLIDE_MODE_0 : string := "PCS"; + RX_SLIDE_MODE_1 : string := "PCS"; + RX_STATUS_FMT_0 : string := "PCIE"; + RX_STATUS_FMT_1 : string := "PCIE"; + RX_XCLK_SEL_0 : string := "RXREC"; + RX_XCLK_SEL_1 : string := "RXREC"; + SATA_BURST_VAL_0 : bit_vector := "100"; + SATA_BURST_VAL_1 : bit_vector := "100"; + SATA_IDLE_VAL_0 : bit_vector := "100"; + SATA_IDLE_VAL_1 : bit_vector := "100"; + SATA_MAX_BURST_0 : integer := 7; + SATA_MAX_BURST_1 : integer := 7; + SATA_MAX_INIT_0 : integer := 22; + SATA_MAX_INIT_1 : integer := 22; + SATA_MAX_WAKE_0 : integer := 7; + SATA_MAX_WAKE_1 : integer := 7; + SATA_MIN_BURST_0 : integer := 4; + SATA_MIN_BURST_1 : integer := 4; + SATA_MIN_INIT_0 : integer := 12; + SATA_MIN_INIT_1 : integer := 12; + SATA_MIN_WAKE_0 : integer := 4; + SATA_MIN_WAKE_1 : integer := 4; + SIM_GTXRESET_SPEEDUP : integer := 1; + SIM_MODE : string := "FAST"; + SIM_PLL_PERDIV2 : bit_vector := X"140"; + SIM_RECEIVER_DETECT_PASS_0 : boolean := TRUE; + SIM_RECEIVER_DETECT_PASS_1 : boolean := TRUE; + TERMINATION_CTRL : bit_vector := "10100"; + TERMINATION_IMP_0 : integer := 50; + TERMINATION_IMP_1 : integer := 50; + TERMINATION_OVRD : boolean := FALSE; + TRANS_TIME_FROM_P2_0 : bit_vector := X"03c"; + TRANS_TIME_FROM_P2_1 : bit_vector := X"03c"; + TRANS_TIME_NON_P2_0 : bit_vector := X"19"; + TRANS_TIME_NON_P2_1 : bit_vector := X"19"; + TRANS_TIME_TO_P2_0 : bit_vector := X"064"; + TRANS_TIME_TO_P2_1 : bit_vector := X"064"; + TXGEARBOX_USE_0 : boolean := FALSE; + TXGEARBOX_USE_1 : boolean := FALSE; + TXRX_INVERT_0 : bit_vector := "011"; + TXRX_INVERT_1 : bit_vector := "011"; + TX_BUFFER_USE_0 : boolean := TRUE; + TX_BUFFER_USE_1 : boolean := TRUE; + TX_DETECT_RX_CFG_0 : bit_vector := X"1832"; + TX_DETECT_RX_CFG_1 : bit_vector := X"1832"; + TX_IDLE_DELAY_0 : bit_vector := "010"; + TX_IDLE_DELAY_1 : bit_vector := "010"; + TX_XCLK_SEL_0 : string := "TXOUT"; + TX_XCLK_SEL_1 : string := "TXOUT" + + + + ); + +port ( + DFECLKDLYADJMONITOR0 : out std_logic_vector(5 downto 0); + DFECLKDLYADJMONITOR1 : out std_logic_vector(5 downto 0); + DFEEYEDACMONITOR0 : out std_logic_vector(4 downto 0); + DFEEYEDACMONITOR1 : out std_logic_vector(4 downto 0); + DFESENSCAL0 : out std_logic_vector(2 downto 0); + DFESENSCAL1 : out std_logic_vector(2 downto 0); + DFETAP1MONITOR0 : out std_logic_vector(4 downto 0); + DFETAP1MONITOR1 : out std_logic_vector(4 downto 0); + DFETAP2MONITOR0 : out std_logic_vector(4 downto 0); + DFETAP2MONITOR1 : out std_logic_vector(4 downto 0); + DFETAP3MONITOR0 : out std_logic_vector(3 downto 0); + DFETAP3MONITOR1 : out std_logic_vector(3 downto 0); + DFETAP4MONITOR0 : out std_logic_vector(3 downto 0); + DFETAP4MONITOR1 : out std_logic_vector(3 downto 0); + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + PHYSTATUS0 : out std_ulogic; + PHYSTATUS1 : out std_ulogic; + PLLLKDET : out std_ulogic; + REFCLKOUT : out std_ulogic; + RESETDONE0 : out std_ulogic; + RESETDONE1 : out std_ulogic; + RXBUFSTATUS0 : out std_logic_vector(2 downto 0); + RXBUFSTATUS1 : out std_logic_vector(2 downto 0); + RXBYTEISALIGNED0 : out std_ulogic; + RXBYTEISALIGNED1 : out std_ulogic; + RXBYTEREALIGN0 : out std_ulogic; + RXBYTEREALIGN1 : out std_ulogic; + RXCHANBONDSEQ0 : out std_ulogic; + RXCHANBONDSEQ1 : out std_ulogic; + RXCHANISALIGNED0 : out std_ulogic; + RXCHANISALIGNED1 : out std_ulogic; + RXCHANREALIGN0 : out std_ulogic; + RXCHANREALIGN1 : out std_ulogic; + RXCHARISCOMMA0 : out std_logic_vector(3 downto 0); + RXCHARISCOMMA1 : out std_logic_vector(3 downto 0); + RXCHARISK0 : out std_logic_vector(3 downto 0); + RXCHARISK1 : out std_logic_vector(3 downto 0); + RXCHBONDO0 : out std_logic_vector(3 downto 0); + RXCHBONDO1 : out std_logic_vector(3 downto 0); + RXCLKCORCNT0 : out std_logic_vector(2 downto 0); + RXCLKCORCNT1 : out std_logic_vector(2 downto 0); + RXCOMMADET0 : out std_ulogic; + RXCOMMADET1 : out std_ulogic; + RXDATA0 : out std_logic_vector(31 downto 0); + RXDATA1 : out std_logic_vector(31 downto 0); + RXDATAVALID0 : out std_ulogic; + RXDATAVALID1 : out std_ulogic; + RXDISPERR0 : out std_logic_vector(3 downto 0); + RXDISPERR1 : out std_logic_vector(3 downto 0); + RXELECIDLE0 : out std_ulogic; + RXELECIDLE1 : out std_ulogic; + RXHEADER0 : out std_logic_vector(2 downto 0); + RXHEADER1 : out std_logic_vector(2 downto 0); + RXHEADERVALID0 : out std_ulogic; + RXHEADERVALID1 : out std_ulogic; + RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); + RXNOTINTABLE0 : out std_logic_vector(3 downto 0); + RXNOTINTABLE1 : out std_logic_vector(3 downto 0); + RXOVERSAMPLEERR0 : out std_ulogic; + RXOVERSAMPLEERR1 : out std_ulogic; + RXPRBSERR0 : out std_ulogic; + RXPRBSERR1 : out std_ulogic; + RXRECCLK0 : out std_ulogic; + RXRECCLK1 : out std_ulogic; + RXRUNDISP0 : out std_logic_vector(3 downto 0); + RXRUNDISP1 : out std_logic_vector(3 downto 0); + RXSTARTOFSEQ0 : out std_ulogic; + RXSTARTOFSEQ1 : out std_ulogic; + RXSTATUS0 : out std_logic_vector(2 downto 0); + RXSTATUS1 : out std_logic_vector(2 downto 0); + RXVALID0 : out std_ulogic; + RXVALID1 : out std_ulogic; + TXBUFSTATUS0 : out std_logic_vector(1 downto 0); + TXBUFSTATUS1 : out std_logic_vector(1 downto 0); + TXGEARBOXREADY0 : out std_ulogic; + TXGEARBOXREADY1 : out std_ulogic; + TXKERR0 : out std_logic_vector(3 downto 0); + TXKERR1 : out std_logic_vector(3 downto 0); + TXN0 : out std_ulogic; + TXN1 : out std_ulogic; + TXOUTCLK0 : out std_ulogic; + TXOUTCLK1 : out std_ulogic; + TXP0 : out std_ulogic; + TXP1 : out std_ulogic; + TXRUNDISP0 : out std_logic_vector(3 downto 0); + TXRUNDISP1 : out std_logic_vector(3 downto 0); + + CLKIN : in std_ulogic; + DADDR : in std_logic_vector(6 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DFECLKDLYADJ0 : in std_logic_vector(5 downto 0); + DFECLKDLYADJ1 : in std_logic_vector(5 downto 0); + DFETAP10 : in std_logic_vector(4 downto 0); + DFETAP11 : in std_logic_vector(4 downto 0); + DFETAP20 : in std_logic_vector(4 downto 0); + DFETAP21 : in std_logic_vector(4 downto 0); + DFETAP30 : in std_logic_vector(3 downto 0); + DFETAP31 : in std_logic_vector(3 downto 0); + DFETAP40 : in std_logic_vector(3 downto 0); + DFETAP41 : in std_logic_vector(3 downto 0); + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + GTXRESET : in std_ulogic; + GTXTEST : in std_logic_vector(13 downto 0); + INTDATAWIDTH : in std_ulogic; + LOOPBACK0 : in std_logic_vector(2 downto 0); + LOOPBACK1 : in std_logic_vector(2 downto 0); + PLLLKDETEN : in std_ulogic; + PLLPOWERDOWN : in std_ulogic; + PRBSCNTRESET0 : in std_ulogic; + PRBSCNTRESET1 : in std_ulogic; + REFCLKPWRDNB : in std_ulogic; + RXBUFRESET0 : in std_ulogic; + RXBUFRESET1 : in std_ulogic; + RXCDRRESET0 : in std_ulogic; + RXCDRRESET1 : in std_ulogic; + RXCHBONDI0 : in std_logic_vector(3 downto 0); + RXCHBONDI1 : in std_logic_vector(3 downto 0); + RXCOMMADETUSE0 : in std_ulogic; + RXCOMMADETUSE1 : in std_ulogic; + RXDATAWIDTH0 : in std_logic_vector(1 downto 0); + RXDATAWIDTH1 : in std_logic_vector(1 downto 0); + RXDEC8B10BUSE0 : in std_ulogic; + RXDEC8B10BUSE1 : in std_ulogic; + RXENCHANSYNC0 : in std_ulogic; + RXENCHANSYNC1 : in std_ulogic; + RXENEQB0 : in std_ulogic; + RXENEQB1 : in std_ulogic; + RXENMCOMMAALIGN0 : in std_ulogic; + RXENMCOMMAALIGN1 : in std_ulogic; + RXENPCOMMAALIGN0 : in std_ulogic; + RXENPCOMMAALIGN1 : in std_ulogic; + RXENPMAPHASEALIGN0 : in std_ulogic; + RXENPMAPHASEALIGN1 : in std_ulogic; + RXENPRBSTST0 : in std_logic_vector(1 downto 0); + RXENPRBSTST1 : in std_logic_vector(1 downto 0); + RXENSAMPLEALIGN0 : in std_ulogic; + RXENSAMPLEALIGN1 : in std_ulogic; + RXEQMIX0 : in std_logic_vector(1 downto 0); + RXEQMIX1 : in std_logic_vector(1 downto 0); + RXEQPOLE0 : in std_logic_vector(3 downto 0); + RXEQPOLE1 : in std_logic_vector(3 downto 0); + RXGEARBOXSLIP0 : in std_ulogic; + RXGEARBOXSLIP1 : in std_ulogic; + RXN0 : in std_ulogic; + RXN1 : in std_ulogic; + RXP0 : in std_ulogic; + RXP1 : in std_ulogic; + RXPMASETPHASE0 : in std_ulogic; + RXPMASETPHASE1 : in std_ulogic; + RXPOLARITY0 : in std_ulogic; + RXPOLARITY1 : in std_ulogic; + RXPOWERDOWN0 : in std_logic_vector(1 downto 0); + RXPOWERDOWN1 : in std_logic_vector(1 downto 0); + RXRESET0 : in std_ulogic; + RXRESET1 : in std_ulogic; + RXSLIDE0 : in std_ulogic; + RXSLIDE1 : in std_ulogic; + RXUSRCLK0 : in std_ulogic; + RXUSRCLK1 : in std_ulogic; + RXUSRCLK20 : in std_ulogic; + RXUSRCLK21 : in std_ulogic; + TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXBYPASS8B10B0 : in std_logic_vector(3 downto 0); + TXBYPASS8B10B1 : in std_logic_vector(3 downto 0); + TXCHARDISPMODE0 : in std_logic_vector(3 downto 0); + TXCHARDISPMODE1 : in std_logic_vector(3 downto 0); + TXCHARDISPVAL0 : in std_logic_vector(3 downto 0); + TXCHARDISPVAL1 : in std_logic_vector(3 downto 0); + TXCHARISK0 : in std_logic_vector(3 downto 0); + TXCHARISK1 : in std_logic_vector(3 downto 0); + TXCOMSTART0 : in std_ulogic; + TXCOMSTART1 : in std_ulogic; + TXCOMTYPE0 : in std_ulogic; + TXCOMTYPE1 : in std_ulogic; + TXDATA0 : in std_logic_vector(31 downto 0); + TXDATA1 : in std_logic_vector(31 downto 0); + TXDATAWIDTH0 : in std_logic_vector(1 downto 0); + TXDATAWIDTH1 : in std_logic_vector(1 downto 0); + TXDETECTRX0 : in std_ulogic; + TXDETECTRX1 : in std_ulogic; + TXDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXELECIDLE0 : in std_ulogic; + TXELECIDLE1 : in std_ulogic; + TXENC8B10BUSE0 : in std_ulogic; + TXENC8B10BUSE1 : in std_ulogic; + TXENPMAPHASEALIGN0 : in std_ulogic; + TXENPMAPHASEALIGN1 : in std_ulogic; + TXENPRBSTST0 : in std_logic_vector(1 downto 0); + TXENPRBSTST1 : in std_logic_vector(1 downto 0); + TXHEADER0 : in std_logic_vector(2 downto 0); + TXHEADER1 : in std_logic_vector(2 downto 0); + TXINHIBIT0 : in std_ulogic; + TXINHIBIT1 : in std_ulogic; + TXPMASETPHASE0 : in std_ulogic; + TXPMASETPHASE1 : in std_ulogic; + TXPOLARITY0 : in std_ulogic; + TXPOLARITY1 : in std_ulogic; + TXPOWERDOWN0 : in std_logic_vector(1 downto 0); + TXPOWERDOWN1 : in std_logic_vector(1 downto 0); + TXPREEMPHASIS0 : in std_logic_vector(3 downto 0); + TXPREEMPHASIS1 : in std_logic_vector(3 downto 0); + TXRESET0 : in std_ulogic; + TXRESET1 : in std_ulogic; + TXSEQUENCE0 : in std_logic_vector(6 downto 0); + TXSEQUENCE1 : in std_logic_vector(6 downto 0); + TXSTARTSEQ0 : in std_ulogic; + TXSTARTSEQ1 : in std_ulogic; + TXUSRCLK0 : in std_ulogic; + TXUSRCLK1 : in std_ulogic; + TXUSRCLK20 : in std_ulogic; + TXUSRCLK21 : in std_ulogic + ); +end GTX_DUAL; + +architecture GTX_DUAL_V of GTX_DUAL is + + component GTX_DUAL_SWIFT_BUS + port ( + DFECLKDLYADJMONITOR0 : out std_logic_vector(5 downto 0); + DFECLKDLYADJMONITOR1 : out std_logic_vector(5 downto 0); + DFEEYEDACMONITOR0 : out std_logic_vector(4 downto 0); + DFEEYEDACMONITOR1 : out std_logic_vector(4 downto 0); + DFESENSCAL0 : out std_logic_vector(2 downto 0); + DFESENSCAL1 : out std_logic_vector(2 downto 0); + DFETAP1MONITOR0 : out std_logic_vector(4 downto 0); + DFETAP1MONITOR1 : out std_logic_vector(4 downto 0); + DFETAP2MONITOR0 : out std_logic_vector(4 downto 0); + DFETAP2MONITOR1 : out std_logic_vector(4 downto 0); + DFETAP3MONITOR0 : out std_logic_vector(3 downto 0); + DFETAP3MONITOR1 : out std_logic_vector(3 downto 0); + DFETAP4MONITOR0 : out std_logic_vector(3 downto 0); + DFETAP4MONITOR1 : out std_logic_vector(3 downto 0); + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + PHYSTATUS0 : out std_ulogic; + PHYSTATUS1 : out std_ulogic; + PLLLKDET : out std_ulogic; + REFCLKOUT : out std_ulogic; + RESETDONE0 : out std_ulogic; + RESETDONE1 : out std_ulogic; + RXBUFSTATUS0 : out std_logic_vector(2 downto 0); + RXBUFSTATUS1 : out std_logic_vector(2 downto 0); + RXBYTEISALIGNED0 : out std_ulogic; + RXBYTEISALIGNED1 : out std_ulogic; + RXBYTEREALIGN0 : out std_ulogic; + RXBYTEREALIGN1 : out std_ulogic; + RXCHANBONDSEQ0 : out std_ulogic; + RXCHANBONDSEQ1 : out std_ulogic; + RXCHANISALIGNED0 : out std_ulogic; + RXCHANISALIGNED1 : out std_ulogic; + RXCHANREALIGN0 : out std_ulogic; + RXCHANREALIGN1 : out std_ulogic; + RXCHARISCOMMA0 : out std_logic_vector(3 downto 0); + RXCHARISCOMMA1 : out std_logic_vector(3 downto 0); + RXCHARISK0 : out std_logic_vector(3 downto 0); + RXCHARISK1 : out std_logic_vector(3 downto 0); + RXCHBONDO0 : out std_logic_vector(3 downto 0); + RXCHBONDO1 : out std_logic_vector(3 downto 0); + RXCLKCORCNT0 : out std_logic_vector(2 downto 0); + RXCLKCORCNT1 : out std_logic_vector(2 downto 0); + RXCOMMADET0 : out std_ulogic; + RXCOMMADET1 : out std_ulogic; + RXDATA0 : out std_logic_vector(31 downto 0); + RXDATA1 : out std_logic_vector(31 downto 0); + RXDATAVALID0 : out std_ulogic; + RXDATAVALID1 : out std_ulogic; + RXDISPERR0 : out std_logic_vector(3 downto 0); + RXDISPERR1 : out std_logic_vector(3 downto 0); + RXELECIDLE0 : out std_ulogic; + RXELECIDLE1 : out std_ulogic; + RXHEADER0 : out std_logic_vector(2 downto 0); + RXHEADER1 : out std_logic_vector(2 downto 0); + RXHEADERVALID0 : out std_ulogic; + RXHEADERVALID1 : out std_ulogic; + RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); + RXNOTINTABLE0 : out std_logic_vector(3 downto 0); + RXNOTINTABLE1 : out std_logic_vector(3 downto 0); + RXOVERSAMPLEERR0 : out std_ulogic; + RXOVERSAMPLEERR1 : out std_ulogic; + RXPRBSERR0 : out std_ulogic; + RXPRBSERR1 : out std_ulogic; + RXRECCLK0 : out std_ulogic; + RXRECCLK1 : out std_ulogic; + RXRUNDISP0 : out std_logic_vector(3 downto 0); + RXRUNDISP1 : out std_logic_vector(3 downto 0); + RXSTARTOFSEQ0 : out std_ulogic; + RXSTARTOFSEQ1 : out std_ulogic; + RXSTATUS0 : out std_logic_vector(2 downto 0); + RXSTATUS1 : out std_logic_vector(2 downto 0); + RXVALID0 : out std_ulogic; + RXVALID1 : out std_ulogic; + TXBUFSTATUS0 : out std_logic_vector(1 downto 0); + TXBUFSTATUS1 : out std_logic_vector(1 downto 0); + TXGEARBOXREADY0 : out std_ulogic; + TXGEARBOXREADY1 : out std_ulogic; + TXKERR0 : out std_logic_vector(3 downto 0); + TXKERR1 : out std_logic_vector(3 downto 0); + TXN0 : out std_ulogic; + TXN1 : out std_ulogic; + TXOUTCLK0 : out std_ulogic; + TXOUTCLK1 : out std_ulogic; + TXP0 : out std_ulogic; + TXP1 : out std_ulogic; + TXRUNDISP0 : out std_logic_vector(3 downto 0); + TXRUNDISP1 : out std_logic_vector(3 downto 0); + + CLKIN : in std_ulogic; + DADDR : in std_logic_vector(6 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DFECLKDLYADJ0 : in std_logic_vector(5 downto 0); + DFECLKDLYADJ1 : in std_logic_vector(5 downto 0); + DFETAP10 : in std_logic_vector(4 downto 0); + DFETAP11 : in std_logic_vector(4 downto 0); + DFETAP20 : in std_logic_vector(4 downto 0); + DFETAP21 : in std_logic_vector(4 downto 0); + DFETAP30 : in std_logic_vector(3 downto 0); + DFETAP31 : in std_logic_vector(3 downto 0); + DFETAP40 : in std_logic_vector(3 downto 0); + DFETAP41 : in std_logic_vector(3 downto 0); + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + GSR : in std_ulogic; + GTXRESET : in std_ulogic; + GTXTEST : in std_logic_vector(13 downto 0); + INTDATAWIDTH : in std_ulogic; + LOOPBACK0 : in std_logic_vector(2 downto 0); + LOOPBACK1 : in std_logic_vector(2 downto 0); + PLLLKDETEN : in std_ulogic; + PLLPOWERDOWN : in std_ulogic; + PRBSCNTRESET0 : in std_ulogic; + PRBSCNTRESET1 : in std_ulogic; + REFCLKPWRDNB : in std_ulogic; + RXBUFRESET0 : in std_ulogic; + RXBUFRESET1 : in std_ulogic; + RXCDRRESET0 : in std_ulogic; + RXCDRRESET1 : in std_ulogic; + RXCHBONDI0 : in std_logic_vector(3 downto 0); + RXCHBONDI1 : in std_logic_vector(3 downto 0); + RXCOMMADETUSE0 : in std_ulogic; + RXCOMMADETUSE1 : in std_ulogic; + RXDATAWIDTH0 : in std_logic_vector(1 downto 0); + RXDATAWIDTH1 : in std_logic_vector(1 downto 0); + RXDEC8B10BUSE0 : in std_ulogic; + RXDEC8B10BUSE1 : in std_ulogic; + RXENCHANSYNC0 : in std_ulogic; + RXENCHANSYNC1 : in std_ulogic; + RXENEQB0 : in std_ulogic; + RXENEQB1 : in std_ulogic; + RXENMCOMMAALIGN0 : in std_ulogic; + RXENMCOMMAALIGN1 : in std_ulogic; + RXENPCOMMAALIGN0 : in std_ulogic; + RXENPCOMMAALIGN1 : in std_ulogic; + RXENPMAPHASEALIGN0 : in std_ulogic; + RXENPMAPHASEALIGN1 : in std_ulogic; + RXENPRBSTST0 : in std_logic_vector(1 downto 0); + RXENPRBSTST1 : in std_logic_vector(1 downto 0); + RXENSAMPLEALIGN0 : in std_ulogic; + RXENSAMPLEALIGN1 : in std_ulogic; + RXEQMIX0 : in std_logic_vector(1 downto 0); + RXEQMIX1 : in std_logic_vector(1 downto 0); + RXEQPOLE0 : in std_logic_vector(3 downto 0); + RXEQPOLE1 : in std_logic_vector(3 downto 0); + RXGEARBOXSLIP0 : in std_ulogic; + RXGEARBOXSLIP1 : in std_ulogic; + RXN0 : in std_ulogic; + RXN1 : in std_ulogic; + RXP0 : in std_ulogic; + RXP1 : in std_ulogic; + RXPMASETPHASE0 : in std_ulogic; + RXPMASETPHASE1 : in std_ulogic; + RXPOLARITY0 : in std_ulogic; + RXPOLARITY1 : in std_ulogic; + RXPOWERDOWN0 : in std_logic_vector(1 downto 0); + RXPOWERDOWN1 : in std_logic_vector(1 downto 0); + RXRESET0 : in std_ulogic; + RXRESET1 : in std_ulogic; + RXSLIDE0 : in std_ulogic; + RXSLIDE1 : in std_ulogic; + RXUSRCLK0 : in std_ulogic; + RXUSRCLK1 : in std_ulogic; + RXUSRCLK20 : in std_ulogic; + RXUSRCLK21 : in std_ulogic; + TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXBYPASS8B10B0 : in std_logic_vector(3 downto 0); + TXBYPASS8B10B1 : in std_logic_vector(3 downto 0); + TXCHARDISPMODE0 : in std_logic_vector(3 downto 0); + TXCHARDISPMODE1 : in std_logic_vector(3 downto 0); + TXCHARDISPVAL0 : in std_logic_vector(3 downto 0); + TXCHARDISPVAL1 : in std_logic_vector(3 downto 0); + TXCHARISK0 : in std_logic_vector(3 downto 0); + TXCHARISK1 : in std_logic_vector(3 downto 0); + TXCOMSTART0 : in std_ulogic; + TXCOMSTART1 : in std_ulogic; + TXCOMTYPE0 : in std_ulogic; + TXCOMTYPE1 : in std_ulogic; + TXDATA0 : in std_logic_vector(31 downto 0); + TXDATA1 : in std_logic_vector(31 downto 0); + TXDATAWIDTH0 : in std_logic_vector(1 downto 0); + TXDATAWIDTH1 : in std_logic_vector(1 downto 0); + TXDETECTRX0 : in std_ulogic; + TXDETECTRX1 : in std_ulogic; + TXDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXELECIDLE0 : in std_ulogic; + TXELECIDLE1 : in std_ulogic; + TXENC8B10BUSE0 : in std_ulogic; + TXENC8B10BUSE1 : in std_ulogic; + TXENPMAPHASEALIGN0 : in std_ulogic; + TXENPMAPHASEALIGN1 : in std_ulogic; + TXENPRBSTST0 : in std_logic_vector(1 downto 0); + TXENPRBSTST1 : in std_logic_vector(1 downto 0); + TXHEADER0 : in std_logic_vector(2 downto 0); + TXHEADER1 : in std_logic_vector(2 downto 0); + TXINHIBIT0 : in std_ulogic; + TXINHIBIT1 : in std_ulogic; + TXPMASETPHASE0 : in std_ulogic; + TXPMASETPHASE1 : in std_ulogic; + TXPOLARITY0 : in std_ulogic; + TXPOLARITY1 : in std_ulogic; + TXPOWERDOWN0 : in std_logic_vector(1 downto 0); + TXPOWERDOWN1 : in std_logic_vector(1 downto 0); + TXPREEMPHASIS0 : in std_logic_vector(3 downto 0); + TXPREEMPHASIS1 : in std_logic_vector(3 downto 0); + TXRESET0 : in std_ulogic; + TXRESET1 : in std_ulogic; + TXSEQUENCE0 : in std_logic_vector(6 downto 0); + TXSEQUENCE1 : in std_logic_vector(6 downto 0); + TXSTARTSEQ0 : in std_ulogic; + TXSTARTSEQ1 : in std_ulogic; + TXUSRCLK0 : in std_ulogic; + TXUSRCLK1 : in std_ulogic; + TXUSRCLK20 : in std_ulogic; + TXUSRCLK21 : in std_ulogic; + + STEPPING : in std_ulogic; + AC_CAP_DIS_0 : in std_ulogic; + AC_CAP_DIS_1 : in std_ulogic; + ALIGN_COMMA_WORD_0 : in std_ulogic; + ALIGN_COMMA_WORD_1 : in std_ulogic; + CB2_INH_CC_PERIOD_0 : in std_logic_vector(3 downto 0); + CB2_INH_CC_PERIOD_1 : in std_logic_vector(3 downto 0); + CDR_PH_ADJ_TIME : in std_logic_vector(4 downto 0); + CHAN_BOND_1_MAX_SKEW_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_1_MAX_SKEW_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_2_MAX_SKEW_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_2_MAX_SKEW_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_KEEP_ALIGN_0 : in std_ulogic; + CHAN_BOND_KEEP_ALIGN_1 : in std_ulogic; + CHAN_BOND_LEVEL_0 : in std_logic_vector(2 downto 0); + CHAN_BOND_LEVEL_1 : in std_logic_vector(2 downto 0); + CHAN_BOND_MODE_0 : in std_logic_vector(1 downto 0); + CHAN_BOND_MODE_1 : in std_logic_vector(1 downto 0); + CHAN_BOND_SEQ_1_1_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_1_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_2_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_2_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_3_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_3_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_4_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_4_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_1_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_1_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_2_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_2_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_3_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_3_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_4_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_4_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_USE_0 : in std_ulogic; + CHAN_BOND_SEQ_2_USE_1 : in std_ulogic; + CHAN_BOND_SEQ_LEN_0 : in std_logic_vector(1 downto 0); + CHAN_BOND_SEQ_LEN_1 : in std_logic_vector(1 downto 0); + CLK25_DIVIDER : in std_logic_vector(2 downto 0); + CLKINDC_B : in std_ulogic; + CLKRCV_TRST : in std_ulogic; + CLK_CORRECT_USE_0 : in std_ulogic; + CLK_CORRECT_USE_1 : in std_ulogic; + CLK_COR_ADJ_LEN_0 : in std_logic_vector(1 downto 0); + CLK_COR_ADJ_LEN_1 : in std_logic_vector(1 downto 0); + CLK_COR_DET_LEN_0 : in std_logic_vector(1 downto 0); + CLK_COR_DET_LEN_1 : in std_logic_vector(1 downto 0); + CLK_COR_INSERT_IDLE_FLAG_0 : in std_ulogic; + CLK_COR_INSERT_IDLE_FLAG_1 : in std_ulogic; + CLK_COR_KEEP_IDLE_0 : in std_ulogic; + CLK_COR_KEEP_IDLE_1 : in std_ulogic; + CLK_COR_MAX_LAT_0 : in std_logic_vector(5 downto 0); + CLK_COR_MAX_LAT_1 : in std_logic_vector(5 downto 0); + CLK_COR_MIN_LAT_0 : in std_logic_vector(5 downto 0); + CLK_COR_MIN_LAT_1 : in std_logic_vector(5 downto 0); + CLK_COR_PRECEDENCE_0 : in std_ulogic; + CLK_COR_PRECEDENCE_1 : in std_ulogic; + CLK_COR_REPEAT_WAIT_0 : in std_logic_vector(4 downto 0); + CLK_COR_REPEAT_WAIT_1 : in std_logic_vector(4 downto 0); + CLK_COR_SEQ_1_1_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_1_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_2_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_2_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_3_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_3_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_4_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_4_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_1_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_1_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_2_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_2_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_3_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_3_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_4_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_4_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_USE_0 : in std_ulogic; + CLK_COR_SEQ_2_USE_1 : in std_ulogic; + CM_TRIM_0 : in std_logic_vector(1 downto 0); + CM_TRIM_1 : in std_logic_vector(1 downto 0); + COMMA_10B_ENABLE_0 : in std_logic_vector(9 downto 0); + COMMA_10B_ENABLE_1 : in std_logic_vector(9 downto 0); + COMMA_DOUBLE_0 : in std_ulogic; + COMMA_DOUBLE_1 : in std_ulogic; + COM_BURST_VAL_0 : in std_logic_vector(3 downto 0); + COM_BURST_VAL_1 : in std_logic_vector(3 downto 0); + DEC_MCOMMA_DETECT_0 : in std_ulogic; + DEC_MCOMMA_DETECT_1 : in std_ulogic; + DEC_PCOMMA_DETECT_0 : in std_ulogic; + DEC_PCOMMA_DETECT_1 : in std_ulogic; + DEC_VALID_COMMA_ONLY_0 : in std_ulogic; + DEC_VALID_COMMA_ONLY_1 : in std_ulogic; + DFE_CAL_TIME : in std_logic_vector(4 downto 0); + DFE_CFG_0 : in std_logic_vector(9 downto 0); + DFE_CFG_1 : in std_logic_vector(9 downto 0); + GEARBOX_ENDEC_0 : in std_logic_vector(2 downto 0); + GEARBOX_ENDEC_1 : in std_logic_vector(2 downto 0); + MCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); + MCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); + MCOMMA_DETECT_0 : in std_ulogic; + MCOMMA_DETECT_1 : in std_ulogic; + OOBDETECT_THRESHOLD_0 : in std_logic_vector(2 downto 0); + OOBDETECT_THRESHOLD_1 : in std_logic_vector(2 downto 0); + OOB_CLK_DIVIDER : in std_logic_vector(2 downto 0); + OVERSAMPLE_MODE : in std_ulogic; + PCI_EXPRESS_MODE_0 : in std_ulogic; + PCI_EXPRESS_MODE_1 : in std_ulogic; + PCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); + PCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); + PCOMMA_DETECT_0 : in std_ulogic; + PCOMMA_DETECT_1 : in std_ulogic; + PLL_COM_CFG : in std_logic_vector(23 downto 0); + PLL_CP_CFG : in std_logic_vector(7 downto 0); + PLL_DIVSEL_FB : in std_logic_vector(4 downto 0); + PLL_DIVSEL_REF : in std_logic_vector(5 downto 0); + PLL_FB_DCCEN : in std_ulogic; + PLL_LKDET_CFG : in std_logic_vector(2 downto 0); + PLL_RXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); + PLL_RXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); + PLL_SATA_0 : in std_ulogic; + PLL_SATA_1 : in std_ulogic; + PLL_TDCC_CFG : in std_logic_vector(2 downto 0); + PLL_TXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); + PLL_TXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); + PMA_CDR_SCAN_0 : in std_logic_vector(26 downto 0); + PMA_CDR_SCAN_1 : in std_logic_vector(26 downto 0); + PMA_COM_CFG : in std_logic_vector(68 downto 0); + PMA_RXSYNC_CFG_0 : in std_logic_vector(6 downto 0); + PMA_RXSYNC_CFG_1 : in std_logic_vector(6 downto 0); + PMA_RX_CFG_0 : in std_logic_vector(24 downto 0); + PMA_RX_CFG_1 : in std_logic_vector(24 downto 0); + PMA_TX_CFG_0 : in std_logic_vector(19 downto 0); + PMA_TX_CFG_1 : in std_logic_vector(19 downto 0); + PRBS_ERR_THRESHOLD_0 : in std_logic_vector(31 downto 0); + PRBS_ERR_THRESHOLD_1 : in std_logic_vector(31 downto 0); + RCV_TERM_GND_0 : in std_ulogic; + RCV_TERM_GND_1 : in std_ulogic; + RCV_TERM_VTTRX_0 : in std_ulogic; + RCV_TERM_VTTRX_1 : in std_ulogic; + RXGEARBOX_USE_0 : in std_ulogic; + RXGEARBOX_USE_1 : in std_ulogic; + RX_BUFFER_USE_0 : in std_ulogic; + RX_BUFFER_USE_1 : in std_ulogic; + RX_DECODE_SEQ_MATCH_0 : in std_ulogic; + RX_DECODE_SEQ_MATCH_1 : in std_ulogic; + RX_EN_IDLE_HOLD_CDR : in std_ulogic; + RX_EN_IDLE_HOLD_DFE_0 : in std_ulogic; + RX_EN_IDLE_HOLD_DFE_1 : in std_ulogic; + RX_EN_IDLE_RESET_BUF_0 : in std_ulogic; + RX_EN_IDLE_RESET_BUF_1 : in std_ulogic; + RX_EN_IDLE_RESET_FR : in std_ulogic; + RX_EN_IDLE_RESET_PH : in std_ulogic; + RX_IDLE_HI_CNT_0 : in std_logic_vector(3 downto 0); + RX_IDLE_HI_CNT_1 : in std_logic_vector(3 downto 0); + RX_IDLE_LO_CNT_0 : in std_logic_vector(3 downto 0); + RX_IDLE_LO_CNT_1 : in std_logic_vector(3 downto 0); + RX_LOSS_OF_SYNC_FSM_0 : in std_ulogic; + RX_LOSS_OF_SYNC_FSM_1 : in std_ulogic; + RX_LOS_INVALID_INCR_0 : in std_logic_vector(2 downto 0); + RX_LOS_INVALID_INCR_1 : in std_logic_vector(2 downto 0); + RX_LOS_THRESHOLD_0 : in std_logic_vector(2 downto 0); + RX_LOS_THRESHOLD_1 : in std_logic_vector(2 downto 0); + RX_SLIDE_MODE_0 : in std_ulogic; + RX_SLIDE_MODE_1 : in std_ulogic; + RX_STATUS_FMT_0 : in std_ulogic; + RX_STATUS_FMT_1 : in std_ulogic; + RX_XCLK_SEL_0 : in std_ulogic; + RX_XCLK_SEL_1 : in std_ulogic; + SATA_BURST_VAL_0 : in std_logic_vector(2 downto 0); + SATA_BURST_VAL_1 : in std_logic_vector(2 downto 0); + SATA_IDLE_VAL_0 : in std_logic_vector(2 downto 0); + SATA_IDLE_VAL_1 : in std_logic_vector(2 downto 0); + SATA_MAX_BURST_0 : in std_logic_vector(5 downto 0); + SATA_MAX_BURST_1 : in std_logic_vector(5 downto 0); + SATA_MAX_INIT_0 : in std_logic_vector(5 downto 0); + SATA_MAX_INIT_1 : in std_logic_vector(5 downto 0); + SATA_MAX_WAKE_0 : in std_logic_vector(5 downto 0); + SATA_MAX_WAKE_1 : in std_logic_vector(5 downto 0); + SATA_MIN_BURST_0 : in std_logic_vector(5 downto 0); + SATA_MIN_BURST_1 : in std_logic_vector(5 downto 0); + SATA_MIN_INIT_0 : in std_logic_vector(5 downto 0); + SATA_MIN_INIT_1 : in std_logic_vector(5 downto 0); + SATA_MIN_WAKE_0 : in std_logic_vector(5 downto 0); + SATA_MIN_WAKE_1 : in std_logic_vector(5 downto 0); + SIM_GTXRESET_SPEEDUP : in std_ulogic; + SIM_PLL_PERDIV2 : in std_logic_vector(8 downto 0); + SIM_RECEIVER_DETECT_PASS_0 : in std_ulogic; + SIM_RECEIVER_DETECT_PASS_1 : in std_ulogic; + TERMINATION_CTRL : in std_logic_vector(4 downto 0); + TERMINATION_IMP_0 : in std_ulogic; + TERMINATION_IMP_1 : in std_ulogic; + TERMINATION_OVRD : in std_ulogic; + TRANS_TIME_FROM_P2_0 : in std_logic_vector(11 downto 0); + TRANS_TIME_FROM_P2_1 : in std_logic_vector(11 downto 0); + TRANS_TIME_NON_P2_0 : in std_logic_vector(7 downto 0); + TRANS_TIME_NON_P2_1 : in std_logic_vector(7 downto 0); + TRANS_TIME_TO_P2_0 : in std_logic_vector(9 downto 0); + TRANS_TIME_TO_P2_1 : in std_logic_vector(9 downto 0); + TXGEARBOX_USE_0 : in std_ulogic; + TXGEARBOX_USE_1 : in std_ulogic; + TXRX_INVERT_0 : in std_logic_vector(2 downto 0); + TXRX_INVERT_1 : in std_logic_vector(2 downto 0); + TX_BUFFER_USE_0 : in std_ulogic; + TX_BUFFER_USE_1 : in std_ulogic; + TX_DETECT_RX_CFG_0 : in std_logic_vector(13 downto 0); + TX_DETECT_RX_CFG_1 : in std_logic_vector(13 downto 0); + TX_IDLE_DELAY_0 : in std_logic_vector(2 downto 0); + TX_IDLE_DELAY_1 : in std_logic_vector(2 downto 0); + TX_XCLK_SEL_0 : in std_ulogic; + TX_XCLK_SEL_1 : in std_ulogic + ); + end component; + + component GTX_DUAL_FAST_BUS + port ( + DFECLKDLYADJMONITOR0 : out std_logic_vector(5 downto 0); + DFECLKDLYADJMONITOR1 : out std_logic_vector(5 downto 0); + DFEEYEDACMONITOR0 : out std_logic_vector(4 downto 0); + DFEEYEDACMONITOR1 : out std_logic_vector(4 downto 0); + DFESENSCAL0 : out std_logic_vector(2 downto 0); + DFESENSCAL1 : out std_logic_vector(2 downto 0); + DFETAP1MONITOR0 : out std_logic_vector(4 downto 0); + DFETAP1MONITOR1 : out std_logic_vector(4 downto 0); + DFETAP2MONITOR0 : out std_logic_vector(4 downto 0); + DFETAP2MONITOR1 : out std_logic_vector(4 downto 0); + DFETAP3MONITOR0 : out std_logic_vector(3 downto 0); + DFETAP3MONITOR1 : out std_logic_vector(3 downto 0); + DFETAP4MONITOR0 : out std_logic_vector(3 downto 0); + DFETAP4MONITOR1 : out std_logic_vector(3 downto 0); + DO : out std_logic_vector(15 downto 0); + DRDY : out std_ulogic; + PHYSTATUS0 : out std_ulogic; + PHYSTATUS1 : out std_ulogic; + PLLLKDET : out std_ulogic; + REFCLKOUT : out std_ulogic; + RESETDONE0 : out std_ulogic; + RESETDONE1 : out std_ulogic; + RXBUFSTATUS0 : out std_logic_vector(2 downto 0); + RXBUFSTATUS1 : out std_logic_vector(2 downto 0); + RXBYTEISALIGNED0 : out std_ulogic; + RXBYTEISALIGNED1 : out std_ulogic; + RXBYTEREALIGN0 : out std_ulogic; + RXBYTEREALIGN1 : out std_ulogic; + RXCHANBONDSEQ0 : out std_ulogic; + RXCHANBONDSEQ1 : out std_ulogic; + RXCHANISALIGNED0 : out std_ulogic; + RXCHANISALIGNED1 : out std_ulogic; + RXCHANREALIGN0 : out std_ulogic; + RXCHANREALIGN1 : out std_ulogic; + RXCHARISCOMMA0 : out std_logic_vector(3 downto 0); + RXCHARISCOMMA1 : out std_logic_vector(3 downto 0); + RXCHARISK0 : out std_logic_vector(3 downto 0); + RXCHARISK1 : out std_logic_vector(3 downto 0); + RXCHBONDO0 : out std_logic_vector(3 downto 0); + RXCHBONDO1 : out std_logic_vector(3 downto 0); + RXCLKCORCNT0 : out std_logic_vector(2 downto 0); + RXCLKCORCNT1 : out std_logic_vector(2 downto 0); + RXCOMMADET0 : out std_ulogic; + RXCOMMADET1 : out std_ulogic; + RXDATA0 : out std_logic_vector(31 downto 0); + RXDATA1 : out std_logic_vector(31 downto 0); + RXDATAVALID0 : out std_ulogic; + RXDATAVALID1 : out std_ulogic; + RXDISPERR0 : out std_logic_vector(3 downto 0); + RXDISPERR1 : out std_logic_vector(3 downto 0); + RXELECIDLE0 : out std_ulogic; + RXELECIDLE1 : out std_ulogic; + RXHEADER0 : out std_logic_vector(2 downto 0); + RXHEADER1 : out std_logic_vector(2 downto 0); + RXHEADERVALID0 : out std_ulogic; + RXHEADERVALID1 : out std_ulogic; + RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); + RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); + RXNOTINTABLE0 : out std_logic_vector(3 downto 0); + RXNOTINTABLE1 : out std_logic_vector(3 downto 0); + RXOVERSAMPLEERR0 : out std_ulogic; + RXOVERSAMPLEERR1 : out std_ulogic; + RXPRBSERR0 : out std_ulogic; + RXPRBSERR1 : out std_ulogic; + RXRECCLK0 : out std_ulogic; + RXRECCLK1 : out std_ulogic; + RXRUNDISP0 : out std_logic_vector(3 downto 0); + RXRUNDISP1 : out std_logic_vector(3 downto 0); + RXSTARTOFSEQ0 : out std_ulogic; + RXSTARTOFSEQ1 : out std_ulogic; + RXSTATUS0 : out std_logic_vector(2 downto 0); + RXSTATUS1 : out std_logic_vector(2 downto 0); + RXVALID0 : out std_ulogic; + RXVALID1 : out std_ulogic; + TXBUFSTATUS0 : out std_logic_vector(1 downto 0); + TXBUFSTATUS1 : out std_logic_vector(1 downto 0); + TXGEARBOXREADY0 : out std_ulogic; + TXGEARBOXREADY1 : out std_ulogic; + TXKERR0 : out std_logic_vector(3 downto 0); + TXKERR1 : out std_logic_vector(3 downto 0); + TXN0 : out std_ulogic; + TXN1 : out std_ulogic; + TXOUTCLK0 : out std_ulogic; + TXOUTCLK1 : out std_ulogic; + TXP0 : out std_ulogic; + TXP1 : out std_ulogic; + TXRUNDISP0 : out std_logic_vector(3 downto 0); + TXRUNDISP1 : out std_logic_vector(3 downto 0); + + CLKIN : in std_ulogic; + DADDR : in std_logic_vector(6 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DFECLKDLYADJ0 : in std_logic_vector(5 downto 0); + DFECLKDLYADJ1 : in std_logic_vector(5 downto 0); + DFETAP10 : in std_logic_vector(4 downto 0); + DFETAP11 : in std_logic_vector(4 downto 0); + DFETAP20 : in std_logic_vector(4 downto 0); + DFETAP21 : in std_logic_vector(4 downto 0); + DFETAP30 : in std_logic_vector(3 downto 0); + DFETAP31 : in std_logic_vector(3 downto 0); + DFETAP40 : in std_logic_vector(3 downto 0); + DFETAP41 : in std_logic_vector(3 downto 0); + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + GSR : in std_ulogic; + GTXRESET : in std_ulogic; + GTXTEST : in std_logic_vector(13 downto 0); + INTDATAWIDTH : in std_ulogic; + LOOPBACK0 : in std_logic_vector(2 downto 0); + LOOPBACK1 : in std_logic_vector(2 downto 0); + PLLLKDETEN : in std_ulogic; + PLLPOWERDOWN : in std_ulogic; + PRBSCNTRESET0 : in std_ulogic; + PRBSCNTRESET1 : in std_ulogic; + REFCLKPWRDNB : in std_ulogic; + RXBUFRESET0 : in std_ulogic; + RXBUFRESET1 : in std_ulogic; + RXCDRRESET0 : in std_ulogic; + RXCDRRESET1 : in std_ulogic; + RXCHBONDI0 : in std_logic_vector(3 downto 0); + RXCHBONDI1 : in std_logic_vector(3 downto 0); + RXCOMMADETUSE0 : in std_ulogic; + RXCOMMADETUSE1 : in std_ulogic; + RXDATAWIDTH0 : in std_logic_vector(1 downto 0); + RXDATAWIDTH1 : in std_logic_vector(1 downto 0); + RXDEC8B10BUSE0 : in std_ulogic; + RXDEC8B10BUSE1 : in std_ulogic; + RXENCHANSYNC0 : in std_ulogic; + RXENCHANSYNC1 : in std_ulogic; + RXENEQB0 : in std_ulogic; + RXENEQB1 : in std_ulogic; + RXENMCOMMAALIGN0 : in std_ulogic; + RXENMCOMMAALIGN1 : in std_ulogic; + RXENPCOMMAALIGN0 : in std_ulogic; + RXENPCOMMAALIGN1 : in std_ulogic; + RXENPMAPHASEALIGN0 : in std_ulogic; + RXENPMAPHASEALIGN1 : in std_ulogic; + RXENPRBSTST0 : in std_logic_vector(1 downto 0); + RXENPRBSTST1 : in std_logic_vector(1 downto 0); + RXENSAMPLEALIGN0 : in std_ulogic; + RXENSAMPLEALIGN1 : in std_ulogic; + RXEQMIX0 : in std_logic_vector(1 downto 0); + RXEQMIX1 : in std_logic_vector(1 downto 0); + RXEQPOLE0 : in std_logic_vector(3 downto 0); + RXEQPOLE1 : in std_logic_vector(3 downto 0); + RXGEARBOXSLIP0 : in std_ulogic; + RXGEARBOXSLIP1 : in std_ulogic; + RXN0 : in std_ulogic; + RXN1 : in std_ulogic; + RXP0 : in std_ulogic; + RXP1 : in std_ulogic; + RXPMASETPHASE0 : in std_ulogic; + RXPMASETPHASE1 : in std_ulogic; + RXPOLARITY0 : in std_ulogic; + RXPOLARITY1 : in std_ulogic; + RXPOWERDOWN0 : in std_logic_vector(1 downto 0); + RXPOWERDOWN1 : in std_logic_vector(1 downto 0); + RXRESET0 : in std_ulogic; + RXRESET1 : in std_ulogic; + RXSLIDE0 : in std_ulogic; + RXSLIDE1 : in std_ulogic; + RXUSRCLK0 : in std_ulogic; + RXUSRCLK1 : in std_ulogic; + RXUSRCLK20 : in std_ulogic; + RXUSRCLK21 : in std_ulogic; + TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXBYPASS8B10B0 : in std_logic_vector(3 downto 0); + TXBYPASS8B10B1 : in std_logic_vector(3 downto 0); + TXCHARDISPMODE0 : in std_logic_vector(3 downto 0); + TXCHARDISPMODE1 : in std_logic_vector(3 downto 0); + TXCHARDISPVAL0 : in std_logic_vector(3 downto 0); + TXCHARDISPVAL1 : in std_logic_vector(3 downto 0); + TXCHARISK0 : in std_logic_vector(3 downto 0); + TXCHARISK1 : in std_logic_vector(3 downto 0); + TXCOMSTART0 : in std_ulogic; + TXCOMSTART1 : in std_ulogic; + TXCOMTYPE0 : in std_ulogic; + TXCOMTYPE1 : in std_ulogic; + TXDATA0 : in std_logic_vector(31 downto 0); + TXDATA1 : in std_logic_vector(31 downto 0); + TXDATAWIDTH0 : in std_logic_vector(1 downto 0); + TXDATAWIDTH1 : in std_logic_vector(1 downto 0); + TXDETECTRX0 : in std_ulogic; + TXDETECTRX1 : in std_ulogic; + TXDIFFCTRL0 : in std_logic_vector(2 downto 0); + TXDIFFCTRL1 : in std_logic_vector(2 downto 0); + TXELECIDLE0 : in std_ulogic; + TXELECIDLE1 : in std_ulogic; + TXENC8B10BUSE0 : in std_ulogic; + TXENC8B10BUSE1 : in std_ulogic; + TXENPMAPHASEALIGN0 : in std_ulogic; + TXENPMAPHASEALIGN1 : in std_ulogic; + TXENPRBSTST0 : in std_logic_vector(1 downto 0); + TXENPRBSTST1 : in std_logic_vector(1 downto 0); + TXHEADER0 : in std_logic_vector(2 downto 0); + TXHEADER1 : in std_logic_vector(2 downto 0); + TXINHIBIT0 : in std_ulogic; + TXINHIBIT1 : in std_ulogic; + TXPMASETPHASE0 : in std_ulogic; + TXPMASETPHASE1 : in std_ulogic; + TXPOLARITY0 : in std_ulogic; + TXPOLARITY1 : in std_ulogic; + TXPOWERDOWN0 : in std_logic_vector(1 downto 0); + TXPOWERDOWN1 : in std_logic_vector(1 downto 0); + TXPREEMPHASIS0 : in std_logic_vector(3 downto 0); + TXPREEMPHASIS1 : in std_logic_vector(3 downto 0); + TXRESET0 : in std_ulogic; + TXRESET1 : in std_ulogic; + TXSEQUENCE0 : in std_logic_vector(6 downto 0); + TXSEQUENCE1 : in std_logic_vector(6 downto 0); + TXSTARTSEQ0 : in std_ulogic; + TXSTARTSEQ1 : in std_ulogic; + TXUSRCLK0 : in std_ulogic; + TXUSRCLK1 : in std_ulogic; + TXUSRCLK20 : in std_ulogic; + TXUSRCLK21 : in std_ulogic; + + STEPPING : in std_ulogic; + AC_CAP_DIS_0 : in std_ulogic; + AC_CAP_DIS_1 : in std_ulogic; + ALIGN_COMMA_WORD_0 : in std_ulogic; + ALIGN_COMMA_WORD_1 : in std_ulogic; + CB2_INH_CC_PERIOD_0 : in std_logic_vector(3 downto 0); + CB2_INH_CC_PERIOD_1 : in std_logic_vector(3 downto 0); + CDR_PH_ADJ_TIME : in std_logic_vector(4 downto 0); + CHAN_BOND_1_MAX_SKEW_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_1_MAX_SKEW_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_2_MAX_SKEW_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_2_MAX_SKEW_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_KEEP_ALIGN_0 : in std_ulogic; + CHAN_BOND_KEEP_ALIGN_1 : in std_ulogic; + CHAN_BOND_LEVEL_0 : in std_logic_vector(2 downto 0); + CHAN_BOND_LEVEL_1 : in std_logic_vector(2 downto 0); + CHAN_BOND_MODE_0 : in std_logic_vector(1 downto 0); + CHAN_BOND_MODE_1 : in std_logic_vector(1 downto 0); + CHAN_BOND_SEQ_1_1_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_1_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_2_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_2_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_3_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_3_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_4_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_4_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_1_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_1_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_2_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_2_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_3_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_3_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_4_0 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_4_1 : in std_logic_vector(9 downto 0); + CHAN_BOND_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); + CHAN_BOND_SEQ_2_USE_0 : in std_ulogic; + CHAN_BOND_SEQ_2_USE_1 : in std_ulogic; + CHAN_BOND_SEQ_LEN_0 : in std_logic_vector(1 downto 0); + CHAN_BOND_SEQ_LEN_1 : in std_logic_vector(1 downto 0); + CLK25_DIVIDER : in std_logic_vector(2 downto 0); + CLKINDC_B : in std_ulogic; + CLKRCV_TRST : in std_ulogic; + CLK_CORRECT_USE_0 : in std_ulogic; + CLK_CORRECT_USE_1 : in std_ulogic; + CLK_COR_ADJ_LEN_0 : in std_logic_vector(1 downto 0); + CLK_COR_ADJ_LEN_1 : in std_logic_vector(1 downto 0); + CLK_COR_DET_LEN_0 : in std_logic_vector(1 downto 0); + CLK_COR_DET_LEN_1 : in std_logic_vector(1 downto 0); + CLK_COR_INSERT_IDLE_FLAG_0 : in std_ulogic; + CLK_COR_INSERT_IDLE_FLAG_1 : in std_ulogic; + CLK_COR_KEEP_IDLE_0 : in std_ulogic; + CLK_COR_KEEP_IDLE_1 : in std_ulogic; + CLK_COR_MAX_LAT_0 : in std_logic_vector(5 downto 0); + CLK_COR_MAX_LAT_1 : in std_logic_vector(5 downto 0); + CLK_COR_MIN_LAT_0 : in std_logic_vector(5 downto 0); + CLK_COR_MIN_LAT_1 : in std_logic_vector(5 downto 0); + CLK_COR_PRECEDENCE_0 : in std_ulogic; + CLK_COR_PRECEDENCE_1 : in std_ulogic; + CLK_COR_REPEAT_WAIT_0 : in std_logic_vector(4 downto 0); + CLK_COR_REPEAT_WAIT_1 : in std_logic_vector(4 downto 0); + CLK_COR_SEQ_1_1_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_1_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_2_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_2_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_3_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_3_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_4_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_4_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_1_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_1_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_2_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_2_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_3_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_3_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_4_0 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_4_1 : in std_logic_vector(9 downto 0); + CLK_COR_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); + CLK_COR_SEQ_2_USE_0 : in std_ulogic; + CLK_COR_SEQ_2_USE_1 : in std_ulogic; + CM_TRIM_0 : in std_logic_vector(1 downto 0); + CM_TRIM_1 : in std_logic_vector(1 downto 0); + COMMA_10B_ENABLE_0 : in std_logic_vector(9 downto 0); + COMMA_10B_ENABLE_1 : in std_logic_vector(9 downto 0); + COMMA_DOUBLE_0 : in std_ulogic; + COMMA_DOUBLE_1 : in std_ulogic; + COM_BURST_VAL_0 : in std_logic_vector(3 downto 0); + COM_BURST_VAL_1 : in std_logic_vector(3 downto 0); + DEC_MCOMMA_DETECT_0 : in std_ulogic; + DEC_MCOMMA_DETECT_1 : in std_ulogic; + DEC_PCOMMA_DETECT_0 : in std_ulogic; + DEC_PCOMMA_DETECT_1 : in std_ulogic; + DEC_VALID_COMMA_ONLY_0 : in std_ulogic; + DEC_VALID_COMMA_ONLY_1 : in std_ulogic; + DFE_CAL_TIME : in std_logic_vector(4 downto 0); + DFE_CFG_0 : in std_logic_vector(9 downto 0); + DFE_CFG_1 : in std_logic_vector(9 downto 0); + GEARBOX_ENDEC_0 : in std_logic_vector(2 downto 0); + GEARBOX_ENDEC_1 : in std_logic_vector(2 downto 0); + MCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); + MCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); + MCOMMA_DETECT_0 : in std_ulogic; + MCOMMA_DETECT_1 : in std_ulogic; + OOBDETECT_THRESHOLD_0 : in std_logic_vector(2 downto 0); + OOBDETECT_THRESHOLD_1 : in std_logic_vector(2 downto 0); + OOB_CLK_DIVIDER : in std_logic_vector(2 downto 0); + OVERSAMPLE_MODE : in std_ulogic; + PCI_EXPRESS_MODE_0 : in std_ulogic; + PCI_EXPRESS_MODE_1 : in std_ulogic; + PCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); + PCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); + PCOMMA_DETECT_0 : in std_ulogic; + PCOMMA_DETECT_1 : in std_ulogic; + PLL_COM_CFG : in std_logic_vector(23 downto 0); + PLL_CP_CFG : in std_logic_vector(7 downto 0); + PLL_DIVSEL_FB : in std_logic_vector(4 downto 0); + PLL_DIVSEL_REF : in std_logic_vector(5 downto 0); + PLL_FB_DCCEN : in std_ulogic; + PLL_LKDET_CFG : in std_logic_vector(2 downto 0); + PLL_RXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); + PLL_RXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); + PLL_SATA_0 : in std_ulogic; + PLL_SATA_1 : in std_ulogic; + PLL_TDCC_CFG : in std_logic_vector(2 downto 0); + PLL_TXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); + PLL_TXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); + PMA_CDR_SCAN_0 : in std_logic_vector(26 downto 0); + PMA_CDR_SCAN_1 : in std_logic_vector(26 downto 0); + PMA_COM_CFG : in std_logic_vector(68 downto 0); + PMA_RXSYNC_CFG_0 : in std_logic_vector(6 downto 0); + PMA_RXSYNC_CFG_1 : in std_logic_vector(6 downto 0); + PMA_RX_CFG_0 : in std_logic_vector(24 downto 0); + PMA_RX_CFG_1 : in std_logic_vector(24 downto 0); + PMA_TX_CFG_0 : in std_logic_vector(19 downto 0); + PMA_TX_CFG_1 : in std_logic_vector(19 downto 0); + PRBS_ERR_THRESHOLD_0 : in std_logic_vector(31 downto 0); + PRBS_ERR_THRESHOLD_1 : in std_logic_vector(31 downto 0); + RCV_TERM_GND_0 : in std_ulogic; + RCV_TERM_GND_1 : in std_ulogic; + RCV_TERM_VTTRX_0 : in std_ulogic; + RCV_TERM_VTTRX_1 : in std_ulogic; + RXGEARBOX_USE_0 : in std_ulogic; + RXGEARBOX_USE_1 : in std_ulogic; + RX_BUFFER_USE_0 : in std_ulogic; + RX_BUFFER_USE_1 : in std_ulogic; + RX_DECODE_SEQ_MATCH_0 : in std_ulogic; + RX_DECODE_SEQ_MATCH_1 : in std_ulogic; + RX_EN_IDLE_HOLD_CDR : in std_ulogic; + RX_EN_IDLE_HOLD_DFE_0 : in std_ulogic; + RX_EN_IDLE_HOLD_DFE_1 : in std_ulogic; + RX_EN_IDLE_RESET_BUF_0 : in std_ulogic; + RX_EN_IDLE_RESET_BUF_1 : in std_ulogic; + RX_EN_IDLE_RESET_FR : in std_ulogic; + RX_EN_IDLE_RESET_PH : in std_ulogic; + RX_IDLE_HI_CNT_0 : in std_logic_vector(3 downto 0); + RX_IDLE_HI_CNT_1 : in std_logic_vector(3 downto 0); + RX_IDLE_LO_CNT_0 : in std_logic_vector(3 downto 0); + RX_IDLE_LO_CNT_1 : in std_logic_vector(3 downto 0); + RX_LOSS_OF_SYNC_FSM_0 : in std_ulogic; + RX_LOSS_OF_SYNC_FSM_1 : in std_ulogic; + RX_LOS_INVALID_INCR_0 : in std_logic_vector(2 downto 0); + RX_LOS_INVALID_INCR_1 : in std_logic_vector(2 downto 0); + RX_LOS_THRESHOLD_0 : in std_logic_vector(2 downto 0); + RX_LOS_THRESHOLD_1 : in std_logic_vector(2 downto 0); + RX_SLIDE_MODE_0 : in std_ulogic; + RX_SLIDE_MODE_1 : in std_ulogic; + RX_STATUS_FMT_0 : in std_ulogic; + RX_STATUS_FMT_1 : in std_ulogic; + RX_XCLK_SEL_0 : in std_ulogic; + RX_XCLK_SEL_1 : in std_ulogic; + SATA_BURST_VAL_0 : in std_logic_vector(2 downto 0); + SATA_BURST_VAL_1 : in std_logic_vector(2 downto 0); + SATA_IDLE_VAL_0 : in std_logic_vector(2 downto 0); + SATA_IDLE_VAL_1 : in std_logic_vector(2 downto 0); + SATA_MAX_BURST_0 : in std_logic_vector(5 downto 0); + SATA_MAX_BURST_1 : in std_logic_vector(5 downto 0); + SATA_MAX_INIT_0 : in std_logic_vector(5 downto 0); + SATA_MAX_INIT_1 : in std_logic_vector(5 downto 0); + SATA_MAX_WAKE_0 : in std_logic_vector(5 downto 0); + SATA_MAX_WAKE_1 : in std_logic_vector(5 downto 0); + SATA_MIN_BURST_0 : in std_logic_vector(5 downto 0); + SATA_MIN_BURST_1 : in std_logic_vector(5 downto 0); + SATA_MIN_INIT_0 : in std_logic_vector(5 downto 0); + SATA_MIN_INIT_1 : in std_logic_vector(5 downto 0); + SATA_MIN_WAKE_0 : in std_logic_vector(5 downto 0); + SATA_MIN_WAKE_1 : in std_logic_vector(5 downto 0); + SIM_GTXRESET_SPEEDUP : in std_ulogic; + SIM_PLL_PERDIV2 : in std_logic_vector(8 downto 0); + SIM_RECEIVER_DETECT_PASS_0 : in std_ulogic; + SIM_RECEIVER_DETECT_PASS_1 : in std_ulogic; + TERMINATION_CTRL : in std_logic_vector(4 downto 0); + TERMINATION_IMP_0 : in std_ulogic; + TERMINATION_IMP_1 : in std_ulogic; + TERMINATION_OVRD : in std_ulogic; + TRANS_TIME_FROM_P2_0 : in std_logic_vector(11 downto 0); + TRANS_TIME_FROM_P2_1 : in std_logic_vector(11 downto 0); + TRANS_TIME_NON_P2_0 : in std_logic_vector(7 downto 0); + TRANS_TIME_NON_P2_1 : in std_logic_vector(7 downto 0); + TRANS_TIME_TO_P2_0 : in std_logic_vector(9 downto 0); + TRANS_TIME_TO_P2_1 : in std_logic_vector(9 downto 0); + TXGEARBOX_USE_0 : in std_ulogic; + TXGEARBOX_USE_1 : in std_ulogic; + TXRX_INVERT_0 : in std_logic_vector(2 downto 0); + TXRX_INVERT_1 : in std_logic_vector(2 downto 0); + TX_BUFFER_USE_0 : in std_ulogic; + TX_BUFFER_USE_1 : in std_ulogic; + TX_DETECT_RX_CFG_0 : in std_logic_vector(13 downto 0); + TX_DETECT_RX_CFG_1 : in std_logic_vector(13 downto 0); + TX_IDLE_DELAY_0 : in std_logic_vector(2 downto 0); + TX_IDLE_DELAY_1 : in std_logic_vector(2 downto 0); + TX_XCLK_SEL_0 : in std_ulogic; + TX_XCLK_SEL_1 : in std_ulogic + ); + end component; + + + constant IN_DELAY : time := 0 ps; + constant OUT_DELAY : time := 0 ps; + constant CLK_DELAY : time := 0 ps; + + constant PATH_DELAY : VitalDelayType01 := (100 ps, 100 ps); + + + signal PLL_TXDIVSEL_OUT_0_BINARY : std_logic_vector(1 downto 0); + signal PLL_RXDIVSEL_OUT_0_BINARY : std_logic_vector(1 downto 0); + signal PLL_TXDIVSEL_OUT_1_BINARY : std_logic_vector(1 downto 0); + signal PLL_RXDIVSEL_OUT_1_BINARY : std_logic_vector(1 downto 0); + signal PLL_DIVSEL_FB_BINARY : std_logic_vector(4 downto 0); + signal PLL_DIVSEL_REF_BINARY : std_logic_vector(5 downto 0); + signal PLL_SATA_0_BINARY : std_ulogic; + signal PLL_SATA_1_BINARY : std_ulogic; + signal OOBDETECT_THRESHOLD_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(OOBDETECT_THRESHOLD_0)(2 downto 0); + signal OOBDETECT_THRESHOLD_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(OOBDETECT_THRESHOLD_1)(2 downto 0); + signal PMA_CDR_SCAN_0_BINARY : std_logic_vector(26 downto 0) := To_StdLogicVector(PMA_CDR_SCAN_0)(26 downto 0); + signal PMA_CDR_SCAN_1_BINARY : std_logic_vector(26 downto 0) := To_StdLogicVector(PMA_CDR_SCAN_1)(26 downto 0); + signal PMA_RX_CFG_0_BINARY : std_logic_vector(24 downto 0) := To_StdLogicVector(PMA_RX_CFG_0)(24 downto 0); + signal PMA_RX_CFG_1_BINARY : std_logic_vector(24 downto 0) := To_StdLogicVector(PMA_RX_CFG_1)(24 downto 0); + signal PLL_TDCC_CFG_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PLL_TDCC_CFG); + signal PMA_COM_CFG_BINARY : std_logic_vector(68 downto 0) := To_StdLogicVector(PMA_COM_CFG)(68 downto 0); + signal PMA_RXSYNC_CFG_0_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(PMA_RXSYNC_CFG_0)(6 downto 0); + signal PMA_RXSYNC_CFG_1_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(PMA_RXSYNC_CFG_1)(6 downto 0); + signal OOB_CLK_DIVIDER_BINARY : std_logic_vector(2 downto 0); + signal STEPPING_BINARY : std_ulogic := '0'; + signal AC_CAP_DIS_0_BINARY : std_ulogic; + signal AC_CAP_DIS_1_BINARY : std_ulogic; + signal RCV_TERM_GND_0_BINARY : std_ulogic; + signal RCV_TERM_GND_1_BINARY : std_ulogic; + signal TERMINATION_IMP_0_BINARY : std_ulogic; + signal TERMINATION_IMP_1_BINARY : std_ulogic; + signal TERMINATION_OVRD_BINARY : std_ulogic; + signal TERMINATION_CTRL_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TERMINATION_CTRL)(4 downto 0); + signal RCV_TERM_VTTRX_0_BINARY : std_ulogic; + signal RCV_TERM_VTTRX_1_BINARY : std_ulogic; + signal PLL_LKDET_CFG_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PLL_LKDET_CFG); + signal TXRX_INVERT_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TXRX_INVERT_0)(2 downto 0); + signal TXRX_INVERT_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TXRX_INVERT_1)(2 downto 0); + signal CLKINDC_B_BINARY : std_ulogic; + signal PCOMMA_DETECT_0_BINARY : std_ulogic; + signal MCOMMA_DETECT_0_BINARY : std_ulogic; + signal PCOMMA_10B_VALUE_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(PCOMMA_10B_VALUE_0)(9 downto 0); + signal MCOMMA_10B_VALUE_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(MCOMMA_10B_VALUE_0)(9 downto 0); + signal COMMA_10B_ENABLE_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(COMMA_10B_ENABLE_0)(9 downto 0); + signal COMMA_DOUBLE_0_BINARY : std_ulogic; + signal ALIGN_COMMA_WORD_0_BINARY : std_ulogic; + signal DEC_PCOMMA_DETECT_0_BINARY : std_ulogic; + signal DEC_MCOMMA_DETECT_0_BINARY : std_ulogic; + signal DEC_VALID_COMMA_ONLY_0_BINARY : std_ulogic; + signal PCOMMA_DETECT_1_BINARY : std_ulogic; + signal MCOMMA_DETECT_1_BINARY : std_ulogic; + signal PCOMMA_10B_VALUE_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(PCOMMA_10B_VALUE_1)(9 downto 0); + signal MCOMMA_10B_VALUE_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(MCOMMA_10B_VALUE_1)(9 downto 0); + signal COMMA_10B_ENABLE_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(COMMA_10B_ENABLE_1)(9 downto 0); + signal COMMA_DOUBLE_1_BINARY : std_ulogic; + signal ALIGN_COMMA_WORD_1_BINARY : std_ulogic; + signal DEC_PCOMMA_DETECT_1_BINARY : std_ulogic; + signal DEC_MCOMMA_DETECT_1_BINARY : std_ulogic; + signal DEC_VALID_COMMA_ONLY_1_BINARY : std_ulogic; + signal RX_LOSS_OF_SYNC_FSM_0_BINARY : std_ulogic; + signal RX_LOS_INVALID_INCR_0_BINARY : std_logic_vector(2 downto 0); + signal RX_LOS_THRESHOLD_0_BINARY : std_logic_vector(2 downto 0); + signal RX_LOSS_OF_SYNC_FSM_1_BINARY : std_ulogic; + signal RX_LOS_INVALID_INCR_1_BINARY : std_logic_vector(2 downto 0); + signal RX_LOS_THRESHOLD_1_BINARY : std_logic_vector(2 downto 0); + signal RX_BUFFER_USE_0_BINARY : std_ulogic; + signal RX_DECODE_SEQ_MATCH_0_BINARY : std_ulogic; + signal RX_BUFFER_USE_1_BINARY : std_ulogic; + signal RX_DECODE_SEQ_MATCH_1_BINARY : std_ulogic; + signal CLK_COR_MIN_LAT_0_BINARY : std_logic_vector(5 downto 0); + signal CLK_COR_MAX_LAT_0_BINARY : std_logic_vector(5 downto 0); + signal CLK_CORRECT_USE_0_BINARY : std_ulogic; + signal CLK_COR_PRECEDENCE_0_BINARY : std_ulogic; + signal CLK_COR_DET_LEN_0_BINARY : std_logic_vector(1 downto 0); + signal CLK_COR_ADJ_LEN_0_BINARY : std_logic_vector(1 downto 0); + signal CLK_COR_KEEP_IDLE_0_BINARY : std_ulogic; + signal CLK_COR_INSERT_IDLE_FLAG_0_BINARY : std_ulogic; + signal CLK_COR_REPEAT_WAIT_0_BINARY : std_logic_vector(4 downto 0); + signal CLK_COR_SEQ_2_USE_0_BINARY : std_ulogic; + signal CLK_COR_SEQ_1_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1_0)(9 downto 0); + signal CLK_COR_SEQ_1_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2_0)(9 downto 0); + signal CLK_COR_SEQ_1_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3_0)(9 downto 0); + signal CLK_COR_SEQ_1_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4_0)(9 downto 0); + signal CLK_COR_SEQ_2_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1_0)(9 downto 0); + signal CLK_COR_SEQ_2_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2_0)(9 downto 0); + signal CLK_COR_SEQ_2_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3_0)(9 downto 0); + signal CLK_COR_SEQ_2_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4_0)(9 downto 0); + signal CLK_COR_SEQ_1_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_ENABLE_0)(3 downto 0); + signal CLK_COR_SEQ_2_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_ENABLE_0)(3 downto 0); + signal CLK_COR_MIN_LAT_1_BINARY : std_logic_vector(5 downto 0); + signal CLK_COR_MAX_LAT_1_BINARY : std_logic_vector(5 downto 0); + signal CLK_CORRECT_USE_1_BINARY : std_ulogic; + signal CLK_COR_PRECEDENCE_1_BINARY : std_ulogic; + signal CLK_COR_DET_LEN_1_BINARY : std_logic_vector(1 downto 0); + signal CLK_COR_ADJ_LEN_1_BINARY : std_logic_vector(1 downto 0); + signal CLK_COR_KEEP_IDLE_1_BINARY : std_ulogic; + signal CLK_COR_INSERT_IDLE_FLAG_1_BINARY : std_ulogic; + signal CLK_COR_REPEAT_WAIT_1_BINARY : std_logic_vector(4 downto 0); + signal CLK_COR_SEQ_2_USE_1_BINARY : std_ulogic; + signal CLK_COR_SEQ_1_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1_1)(9 downto 0); + signal CLK_COR_SEQ_1_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2_1)(9 downto 0); + signal CLK_COR_SEQ_1_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3_1)(9 downto 0); + signal CLK_COR_SEQ_1_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4_1)(9 downto 0); + signal CLK_COR_SEQ_2_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1_1)(9 downto 0); + signal CLK_COR_SEQ_2_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2_1)(9 downto 0); + signal CLK_COR_SEQ_2_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3_1)(9 downto 0); + signal CLK_COR_SEQ_2_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4_1)(9 downto 0); + signal CLK_COR_SEQ_1_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_ENABLE_1)(3 downto 0); + signal CLK_COR_SEQ_2_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_ENABLE_1)(3 downto 0); + signal CHAN_BOND_MODE_0_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_LEVEL_0_BINARY : std_logic_vector(2 downto 0); + signal CHAN_BOND_SEQ_LEN_0_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_SEQ_2_USE_0_BINARY : std_ulogic; + signal CHAN_BOND_SEQ_1_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1_0)(9 downto 0); + signal CHAN_BOND_SEQ_1_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2_0)(9 downto 0); + signal CHAN_BOND_SEQ_1_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3_0)(9 downto 0); + signal CHAN_BOND_SEQ_1_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4_0)(9 downto 0); + signal CHAN_BOND_SEQ_2_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1_0)(9 downto 0); + signal CHAN_BOND_SEQ_2_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2_0)(9 downto 0); + signal CHAN_BOND_SEQ_2_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3_0)(9 downto 0); + signal CHAN_BOND_SEQ_2_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4_0)(9 downto 0); + signal CHAN_BOND_SEQ_1_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_ENABLE_0)(3 downto 0); + signal CHAN_BOND_SEQ_2_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_ENABLE_0)(3 downto 0); + signal CHAN_BOND_1_MAX_SKEW_0_BINARY : std_logic_vector(3 downto 0); + signal CHAN_BOND_2_MAX_SKEW_0_BINARY : std_logic_vector(3 downto 0); + signal CHAN_BOND_KEEP_ALIGN_0_BINARY : std_ulogic; + signal CB2_INH_CC_PERIOD_0_BINARY : std_logic_vector(3 downto 0); + signal CHAN_BOND_MODE_1_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_LEVEL_1_BINARY : std_logic_vector(2 downto 0); + signal CHAN_BOND_SEQ_LEN_1_BINARY : std_logic_vector(1 downto 0); + signal CHAN_BOND_SEQ_2_USE_1_BINARY : std_ulogic; + signal CHAN_BOND_SEQ_1_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1_1)(9 downto 0); + signal CHAN_BOND_SEQ_1_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2_1)(9 downto 0); + signal CHAN_BOND_SEQ_1_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3_1)(9 downto 0); + signal CHAN_BOND_SEQ_1_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4_1)(9 downto 0); + signal CHAN_BOND_SEQ_2_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1_1)(9 downto 0); + signal CHAN_BOND_SEQ_2_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2_1)(9 downto 0); + signal CHAN_BOND_SEQ_2_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3_1)(9 downto 0); + signal CHAN_BOND_SEQ_2_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4_1)(9 downto 0); + signal CHAN_BOND_SEQ_1_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_ENABLE_1)(3 downto 0); + signal CHAN_BOND_SEQ_2_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_ENABLE_1)(3 downto 0); + signal CHAN_BOND_1_MAX_SKEW_1_BINARY : std_logic_vector(3 downto 0); + signal CHAN_BOND_2_MAX_SKEW_1_BINARY : std_logic_vector(3 downto 0); + signal CHAN_BOND_KEEP_ALIGN_1_BINARY : std_ulogic; + signal CB2_INH_CC_PERIOD_1_BINARY : std_logic_vector(3 downto 0); + signal PCI_EXPRESS_MODE_0_BINARY : std_ulogic; + signal TRANS_TIME_FROM_P2_0_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(TRANS_TIME_FROM_P2_0)(11 downto 0); + signal TRANS_TIME_NON_P2_0_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(TRANS_TIME_NON_P2_0)(7 downto 0); + signal TRANS_TIME_TO_P2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(TRANS_TIME_TO_P2_0)(9 downto 0); + signal PCI_EXPRESS_MODE_1_BINARY : std_ulogic; + signal TRANS_TIME_FROM_P2_1_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(TRANS_TIME_FROM_P2_1)(11 downto 0); + signal TRANS_TIME_NON_P2_1_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(TRANS_TIME_NON_P2_1)(7 downto 0); + signal TRANS_TIME_TO_P2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(TRANS_TIME_TO_P2_1)(9 downto 0); + signal RX_STATUS_FMT_0_BINARY : std_ulogic; + signal TX_BUFFER_USE_0_BINARY : std_ulogic; + signal TX_XCLK_SEL_0_BINARY : std_ulogic; + signal RX_XCLK_SEL_0_BINARY : std_ulogic; + signal RX_STATUS_FMT_1_BINARY : std_ulogic; + signal TX_BUFFER_USE_1_BINARY : std_ulogic; + signal TX_XCLK_SEL_1_BINARY : std_ulogic; + signal RX_XCLK_SEL_1_BINARY : std_ulogic; + signal PRBS_ERR_THRESHOLD_0_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(PRBS_ERR_THRESHOLD_0)(31 downto 0); + signal RX_SLIDE_MODE_0_BINARY : std_ulogic; + signal PRBS_ERR_THRESHOLD_1_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(PRBS_ERR_THRESHOLD_1)(31 downto 0); + signal RX_SLIDE_MODE_1_BINARY : std_ulogic; + signal SATA_MIN_BURST_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_BURST_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_INIT_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_INIT_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_WAKE_0_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_WAKE_0_BINARY : std_logic_vector(5 downto 0); + signal TX_DETECT_RX_CFG_0_BINARY : std_logic_vector(13 downto 0) := To_StdLogicVector(TX_DETECT_RX_CFG_0)(13 downto 0); + signal SATA_BURST_VAL_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_BURST_VAL_0)(2 downto 0); + signal SATA_IDLE_VAL_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_IDLE_VAL_0)(2 downto 0); + signal COM_BURST_VAL_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(COM_BURST_VAL_0)(3 downto 0); + signal SATA_MIN_BURST_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_BURST_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_INIT_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_INIT_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MIN_WAKE_1_BINARY : std_logic_vector(5 downto 0); + signal SATA_MAX_WAKE_1_BINARY : std_logic_vector(5 downto 0); + signal TX_DETECT_RX_CFG_1_BINARY : std_logic_vector(13 downto 0) := To_StdLogicVector(TX_DETECT_RX_CFG_1)(13 downto 0); + signal SATA_BURST_VAL_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_BURST_VAL_1)(2 downto 0); + signal SATA_IDLE_VAL_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_IDLE_VAL_1)(2 downto 0); + signal COM_BURST_VAL_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(COM_BURST_VAL_1)(3 downto 0); + signal CLK25_DIVIDER_BINARY : std_logic_vector(2 downto 0); + signal PLL_COM_CFG_BINARY : std_logic_vector(23 downto 0) := To_StdLogicVector(PLL_COM_CFG); + signal PLL_CP_CFG_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PLL_CP_CFG); + signal OVERSAMPLE_MODE_BINARY : std_ulogic; + signal TXGEARBOX_USE_0_BINARY : std_ulogic; + signal RXGEARBOX_USE_0_BINARY : std_ulogic; + signal GEARBOX_ENDEC_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(GEARBOX_ENDEC_0)(2 downto 0); + signal TXGEARBOX_USE_1_BINARY : std_ulogic; + signal RXGEARBOX_USE_1_BINARY : std_ulogic; + signal GEARBOX_ENDEC_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(GEARBOX_ENDEC_1)(2 downto 0); + signal DFE_CFG_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(DFE_CFG_0)(9 downto 0); + signal DFE_CFG_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(DFE_CFG_1)(9 downto 0); + signal PMA_TX_CFG_0_BINARY : std_logic_vector(19 downto 0) := To_StdLogicVector(PMA_TX_CFG_0)(19 downto 0); + signal CM_TRIM_0_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(CM_TRIM_0)(1 downto 0); + signal PMA_TX_CFG_1_BINARY : std_logic_vector(19 downto 0) := To_StdLogicVector(PMA_TX_CFG_1)(19 downto 0); + signal CM_TRIM_1_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(CM_TRIM_1)(1 downto 0); + signal PLL_FB_DCCEN_BINARY : std_ulogic; + signal CLKRCV_TRST_BINARY : std_ulogic; + signal TX_IDLE_DELAY_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TX_IDLE_DELAY_0)(2 downto 0); + signal RX_EN_IDLE_HOLD_DFE_0_BINARY : std_ulogic; + signal RX_EN_IDLE_RESET_BUF_0_BINARY : std_ulogic; + signal RX_IDLE_HI_CNT_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RX_IDLE_HI_CNT_0)(3 downto 0); + signal RX_IDLE_LO_CNT_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RX_IDLE_LO_CNT_0)(3 downto 0); + signal TX_IDLE_DELAY_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TX_IDLE_DELAY_1)(2 downto 0); + signal RX_EN_IDLE_HOLD_DFE_1_BINARY : std_ulogic; + signal RX_EN_IDLE_RESET_BUF_1_BINARY : std_ulogic; + signal RX_IDLE_HI_CNT_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RX_IDLE_HI_CNT_1)(3 downto 0); + signal RX_IDLE_LO_CNT_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RX_IDLE_LO_CNT_1)(3 downto 0); + signal RX_EN_IDLE_HOLD_CDR_BINARY : std_ulogic; + signal RX_EN_IDLE_RESET_PH_BINARY : std_ulogic; + signal RX_EN_IDLE_RESET_FR_BINARY : std_ulogic; + signal DFE_CAL_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(DFE_CAL_TIME)(4 downto 0); + signal CDR_PH_ADJ_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(CDR_PH_ADJ_TIME)(4 downto 0); + signal SIM_GTXRESET_SPEEDUP_BINARY : std_ulogic; + signal SIM_MODE_BINARY : std_ulogic; + signal SIM_PLL_PERDIV2_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(SIM_PLL_PERDIV2)(8 downto 0); + signal SIM_RECEIVER_DETECT_PASS_0_BINARY : std_ulogic; + signal SIM_RECEIVER_DETECT_PASS_1_BINARY : std_ulogic; + + + signal REFCLKOUT_out : std_ulogic; + signal RXRECCLK0_out : std_ulogic; + signal TXOUTCLK0_out : std_ulogic; + signal RXRECCLK1_out : std_ulogic; + signal TXOUTCLK1_out : std_ulogic; + signal TXP0_out : std_ulogic; + signal TXN0_out : std_ulogic; + signal TXP1_out : std_ulogic; + signal TXN1_out : std_ulogic; + signal RXDATA0_out : std_logic_vector(31 downto 0); + signal RXNOTINTABLE0_out : std_logic_vector(3 downto 0); + signal RXDISPERR0_out : std_logic_vector(3 downto 0); + signal RXCHARISK0_out : std_logic_vector(3 downto 0); + signal RXRUNDISP0_out : std_logic_vector(3 downto 0); + signal RXCHARISCOMMA0_out : std_logic_vector(3 downto 0); + signal RXVALID0_out : std_ulogic; + signal RXDATA1_out : std_logic_vector(31 downto 0); + signal RXNOTINTABLE1_out : std_logic_vector(3 downto 0); + signal RXDISPERR1_out : std_logic_vector(3 downto 0); + signal RXCHARISK1_out : std_logic_vector(3 downto 0); + signal RXRUNDISP1_out : std_logic_vector(3 downto 0); + signal RXCHARISCOMMA1_out : std_logic_vector(3 downto 0); + signal RXVALID1_out : std_ulogic; + signal RESETDONE0_out : std_ulogic; + signal RESETDONE1_out : std_ulogic; + signal TXKERR0_out : std_logic_vector(3 downto 0); + signal TXRUNDISP0_out : std_logic_vector(3 downto 0); + signal TXBUFSTATUS0_out : std_logic_vector(1 downto 0); + signal TXKERR1_out : std_logic_vector(3 downto 0); + signal TXRUNDISP1_out : std_logic_vector(3 downto 0); + signal TXBUFSTATUS1_out : std_logic_vector(1 downto 0); + signal RXCOMMADET0_out : std_ulogic; + signal RXBYTEREALIGN0_out : std_ulogic; + signal RXBYTEISALIGNED0_out : std_ulogic; + signal RXLOSSOFSYNC0_out : std_logic_vector(1 downto 0); + signal RXCHBONDO0_out : std_logic_vector(3 downto 0); + signal RXCHANBONDSEQ0_out : std_ulogic; + signal RXCHANREALIGN0_out : std_ulogic; + signal RXCHANISALIGNED0_out : std_ulogic; + signal RXBUFSTATUS0_out : std_logic_vector(2 downto 0); + signal RXCOMMADET1_out : std_ulogic; + signal RXBYTEREALIGN1_out : std_ulogic; + signal RXBYTEISALIGNED1_out : std_ulogic; + signal RXLOSSOFSYNC1_out : std_logic_vector(1 downto 0); + signal RXCHBONDO1_out : std_logic_vector(3 downto 0); + signal RXCHANBONDSEQ1_out : std_ulogic; + signal RXCHANREALIGN1_out : std_ulogic; + signal RXCHANISALIGNED1_out : std_ulogic; + signal RXBUFSTATUS1_out : std_logic_vector(2 downto 0); + signal PHYSTATUS0_out : std_ulogic; + signal PHYSTATUS1_out : std_ulogic; + signal RXELECIDLE0_out : std_ulogic; + signal RXSTATUS0_out : std_logic_vector(2 downto 0); + signal RXCLKCORCNT0_out : std_logic_vector(2 downto 0); + signal RXELECIDLE1_out : std_ulogic; + signal RXSTATUS1_out : std_logic_vector(2 downto 0); + signal RXCLKCORCNT1_out : std_logic_vector(2 downto 0); + signal PLLLKDET_out : std_ulogic; + signal RXPRBSERR0_out : std_ulogic; + signal RXPRBSERR1_out : std_ulogic; + signal DO_out : std_logic_vector(15 downto 0); + signal DRDY_out : std_ulogic; + signal RXOVERSAMPLEERR0_out : std_ulogic; + signal RXOVERSAMPLEERR1_out : std_ulogic; + signal TXGEARBOXREADY0_out : std_ulogic; + signal RXHEADER0_out : std_logic_vector(2 downto 0); + signal RXHEADERVALID0_out : std_ulogic; + signal RXDATAVALID0_out : std_ulogic; + signal RXSTARTOFSEQ0_out : std_ulogic; + signal TXGEARBOXREADY1_out : std_ulogic; + signal RXHEADER1_out : std_logic_vector(2 downto 0); + signal RXHEADERVALID1_out : std_ulogic; + signal RXDATAVALID1_out : std_ulogic; + signal RXSTARTOFSEQ1_out : std_ulogic; + signal DFECLKDLYADJMONITOR0_out : std_logic_vector(5 downto 0); + signal DFEEYEDACMONITOR0_out : std_logic_vector(4 downto 0); + signal DFETAP1MONITOR0_out : std_logic_vector(4 downto 0); + signal DFETAP2MONITOR0_out : std_logic_vector(4 downto 0); + signal DFETAP3MONITOR0_out : std_logic_vector(3 downto 0); + signal DFETAP4MONITOR0_out : std_logic_vector(3 downto 0); + signal DFECLKDLYADJMONITOR1_out : std_logic_vector(5 downto 0); + signal DFEEYEDACMONITOR1_out : std_logic_vector(4 downto 0); + signal DFETAP1MONITOR1_out : std_logic_vector(4 downto 0); + signal DFETAP2MONITOR1_out : std_logic_vector(4 downto 0); + signal DFETAP3MONITOR1_out : std_logic_vector(3 downto 0); + signal DFETAP4MONITOR1_out : std_logic_vector(3 downto 0); + signal DFESENSCAL0_out : std_logic_vector(2 downto 0); + signal DFESENSCAL1_out : std_logic_vector(2 downto 0); + + signal REFCLKOUT_outdelay : std_logic; + signal RXRECCLK0_outdelay : std_logic; + signal TXOUTCLK0_outdelay : std_logic; + signal RXRECCLK1_outdelay : std_logic; + signal TXOUTCLK1_outdelay : std_logic; + signal RXCLKCORCNT0_outdelay : std_logic_vector(2 downto 0); + signal RXCLKCORCNT1_outdelay : std_logic_vector(2 downto 0); + signal DFECLKDLYADJMONITOR0_outdelay : std_logic_vector(5 downto 0); + signal DFECLKDLYADJMONITOR1_outdelay : std_logic_vector(5 downto 0); + + signal TXP0_outdelay : std_logic; + signal TXN0_outdelay : std_logic; + signal TXP1_outdelay : std_logic; + signal TXN1_outdelay : std_logic; + signal RXDATA0_outdelay : std_logic_vector(31 downto 0); + signal RXNOTINTABLE0_outdelay : std_logic_vector(3 downto 0); + signal RXDISPERR0_outdelay : std_logic_vector(3 downto 0); + signal RXCHARISK0_outdelay : std_logic_vector(3 downto 0); + signal RXRUNDISP0_outdelay : std_logic_vector(3 downto 0); + signal RXCHARISCOMMA0_outdelay : std_logic_vector(3 downto 0); + signal RXVALID0_outdelay : std_logic; + signal RXDATA1_outdelay : std_logic_vector(31 downto 0); + signal RXNOTINTABLE1_outdelay : std_logic_vector(3 downto 0); + signal RXDISPERR1_outdelay : std_logic_vector(3 downto 0); + signal RXCHARISK1_outdelay : std_logic_vector(3 downto 0); + signal RXRUNDISP1_outdelay : std_logic_vector(3 downto 0); + signal RXCHARISCOMMA1_outdelay : std_logic_vector(3 downto 0); + signal RXVALID1_outdelay : std_logic; + signal RESETDONE0_outdelay : std_logic; + signal RESETDONE1_outdelay : std_logic; + signal TXKERR0_outdelay : std_logic_vector(3 downto 0); + signal TXRUNDISP0_outdelay : std_logic_vector(3 downto 0); + signal TXBUFSTATUS0_outdelay : std_logic_vector(1 downto 0); + signal TXKERR1_outdelay : std_logic_vector(3 downto 0); + signal TXRUNDISP1_outdelay : std_logic_vector(3 downto 0); + signal TXBUFSTATUS1_outdelay : std_logic_vector(1 downto 0); + signal RXCOMMADET0_outdelay : std_logic; + signal RXBYTEREALIGN0_outdelay : std_logic; + signal RXBYTEISALIGNED0_outdelay : std_logic; + signal RXLOSSOFSYNC0_outdelay : std_logic_vector(1 downto 0); + signal RXCHBONDO0_outdelay : std_logic_vector(3 downto 0); + signal RXCHANBONDSEQ0_outdelay : std_logic; + signal RXCHANREALIGN0_outdelay : std_logic; + signal RXCHANISALIGNED0_outdelay : std_logic; + signal RXBUFSTATUS0_outdelay : std_logic_vector(2 downto 0); + signal RXCOMMADET1_outdelay : std_logic; + signal RXBYTEREALIGN1_outdelay : std_logic; + signal RXBYTEISALIGNED1_outdelay : std_logic; + signal RXLOSSOFSYNC1_outdelay : std_logic_vector(1 downto 0); + signal RXCHBONDO1_outdelay : std_logic_vector(3 downto 0); + signal RXCHANBONDSEQ1_outdelay : std_logic; + signal RXCHANREALIGN1_outdelay : std_logic; + signal RXCHANISALIGNED1_outdelay : std_logic; + signal RXBUFSTATUS1_outdelay : std_logic_vector(2 downto 0); + signal PHYSTATUS0_outdelay : std_logic; + signal PHYSTATUS1_outdelay : std_logic; + signal RXELECIDLE0_outdelay : std_logic; + signal RXSTATUS0_outdelay : std_logic_vector(2 downto 0); + signal RXELECIDLE1_outdelay : std_logic; + signal RXSTATUS1_outdelay : std_logic_vector(2 downto 0); + signal PLLLKDET_outdelay : std_logic; + signal RXPRBSERR0_outdelay : std_logic; + signal RXPRBSERR1_outdelay : std_logic; + signal DO_outdelay : std_logic_vector(15 downto 0); + signal DRDY_outdelay : std_logic; + signal RXOVERSAMPLEERR0_outdelay : std_logic; + signal RXOVERSAMPLEERR1_outdelay : std_logic; + signal TXGEARBOXREADY0_outdelay : std_logic; + signal RXHEADER0_outdelay : std_logic_vector(2 downto 0); + signal RXHEADERVALID0_outdelay : std_logic; + signal RXDATAVALID0_outdelay : std_logic; + signal RXSTARTOFSEQ0_outdelay : std_logic; + signal TXGEARBOXREADY1_outdelay : std_logic; + signal RXHEADER1_outdelay : std_logic_vector(2 downto 0); + signal RXHEADERVALID1_outdelay : std_logic; + signal RXDATAVALID1_outdelay : std_logic; + signal RXSTARTOFSEQ1_outdelay : std_logic; + signal DFEEYEDACMONITOR0_outdelay : std_logic_vector(4 downto 0); + signal DFETAP1MONITOR0_outdelay : std_logic_vector(4 downto 0); + signal DFETAP2MONITOR0_outdelay : std_logic_vector(4 downto 0); + signal DFETAP3MONITOR0_outdelay : std_logic_vector(3 downto 0); + signal DFETAP4MONITOR0_outdelay : std_logic_vector(3 downto 0); + signal DFEEYEDACMONITOR1_outdelay : std_logic_vector(4 downto 0); + signal DFETAP1MONITOR1_outdelay : std_logic_vector(4 downto 0); + signal DFETAP2MONITOR1_outdelay : std_logic_vector(4 downto 0); + signal DFETAP3MONITOR1_outdelay : std_logic_vector(3 downto 0); + signal DFETAP4MONITOR1_outdelay : std_logic_vector(3 downto 0); + signal DFESENSCAL0_outdelay : std_logic_vector(2 downto 0); + signal DFESENSCAL1_outdelay : std_logic_vector(2 downto 0); + + signal CLKIN_ipd : std_ulogic; + signal TXUSRCLK0_ipd : std_ulogic; + signal TXUSRCLK20_ipd : std_ulogic; + signal RXUSRCLK0_ipd : std_ulogic; + signal RXUSRCLK20_ipd : std_ulogic; + signal TXUSRCLK1_ipd : std_ulogic; + signal TXUSRCLK21_ipd : std_ulogic; + signal RXUSRCLK1_ipd : std_ulogic; + signal RXUSRCLK21_ipd : std_ulogic; + signal RXP0_ipd : std_ulogic; + signal RXN0_ipd : std_ulogic; + signal TXDATA0_ipd : std_logic_vector(31 downto 0); + signal TXBYPASS8B10B0_ipd : std_logic_vector(3 downto 0); + signal TXCHARISK0_ipd : std_logic_vector(3 downto 0); + signal TXCHARDISPMODE0_ipd : std_logic_vector(3 downto 0); + signal TXCHARDISPVAL0_ipd : std_logic_vector(3 downto 0); + signal RXP1_ipd : std_ulogic; + signal RXN1_ipd : std_ulogic; + signal TXDATA1_ipd : std_logic_vector(31 downto 0); + signal TXBYPASS8B10B1_ipd : std_logic_vector(3 downto 0); + signal TXCHARISK1_ipd : std_logic_vector(3 downto 0); + signal TXCHARDISPMODE1_ipd : std_logic_vector(3 downto 0); + signal TXCHARDISPVAL1_ipd : std_logic_vector(3 downto 0); + signal GTXRESET_ipd : std_ulogic; + signal RXCDRRESET0_ipd : std_ulogic; + signal TXRESET0_ipd : std_ulogic; + signal RXRESET0_ipd : std_ulogic; + signal RXBUFRESET0_ipd : std_ulogic; + signal RXCDRRESET1_ipd : std_ulogic; + signal TXRESET1_ipd : std_ulogic; + signal RXRESET1_ipd : std_ulogic; + signal RXBUFRESET1_ipd : std_ulogic; + signal TXPOWERDOWN0_ipd : std_logic_vector(1 downto 0); + signal RXPOWERDOWN0_ipd : std_logic_vector(1 downto 0); + signal TXPOWERDOWN1_ipd : std_logic_vector(1 downto 0); + signal RXPOWERDOWN1_ipd : std_logic_vector(1 downto 0); + signal PLLPOWERDOWN_ipd : std_ulogic; + signal REFCLKPWRDNB_ipd : std_ulogic; + signal LOOPBACK0_ipd : std_logic_vector(2 downto 0); + signal LOOPBACK1_ipd : std_logic_vector(2 downto 0); + signal TXDIFFCTRL0_ipd : std_logic_vector(2 downto 0); + signal TXBUFDIFFCTRL0_ipd : std_logic_vector(2 downto 0); + signal TXPREEMPHASIS0_ipd : std_logic_vector(3 downto 0); + signal TXDIFFCTRL1_ipd : std_logic_vector(2 downto 0); + signal TXBUFDIFFCTRL1_ipd : std_logic_vector(2 downto 0); + signal TXPREEMPHASIS1_ipd : std_logic_vector(3 downto 0); + signal RXENEQB0_ipd : std_ulogic; + signal RXEQMIX0_ipd : std_logic_vector(1 downto 0); + signal RXEQPOLE0_ipd : std_logic_vector(3 downto 0); + signal RXENEQB1_ipd : std_ulogic; + signal RXEQMIX1_ipd : std_logic_vector(1 downto 0); + signal RXEQPOLE1_ipd : std_logic_vector(3 downto 0); + signal INTDATAWIDTH_ipd : std_ulogic; + signal TXDATAWIDTH0_ipd : std_logic_vector(1 downto 0); + signal TXDATAWIDTH1_ipd : std_logic_vector(1 downto 0); + signal TXENPMAPHASEALIGN0_ipd : std_ulogic; + signal TXPMASETPHASE0_ipd : std_ulogic; + signal RXENPMAPHASEALIGN0_ipd : std_ulogic; + signal RXPMASETPHASE0_ipd : std_ulogic; + signal TXENPMAPHASEALIGN1_ipd : std_ulogic; + signal TXPMASETPHASE1_ipd : std_ulogic; + signal RXENPMAPHASEALIGN1_ipd : std_ulogic; + signal RXPMASETPHASE1_ipd : std_ulogic; + signal TXENC8B10BUSE0_ipd : std_ulogic; + signal TXPOLARITY0_ipd : std_ulogic; + signal TXINHIBIT0_ipd : std_ulogic; + signal TXENC8B10BUSE1_ipd : std_ulogic; + signal TXPOLARITY1_ipd : std_ulogic; + signal TXINHIBIT1_ipd : std_ulogic; + signal RXPOLARITY0_ipd : std_ulogic; + signal RXENPCOMMAALIGN0_ipd : std_ulogic; + signal RXENMCOMMAALIGN0_ipd : std_ulogic; + signal RXSLIDE0_ipd : std_ulogic; + signal RXCOMMADETUSE0_ipd : std_ulogic; + signal RXDEC8B10BUSE0_ipd : std_ulogic; + signal RXENCHANSYNC0_ipd : std_ulogic; + signal RXCHBONDI0_ipd : std_logic_vector(3 downto 0); + signal RXDATAWIDTH0_ipd : std_logic_vector(1 downto 0); + signal RXPOLARITY1_ipd : std_ulogic; + signal RXENPCOMMAALIGN1_ipd : std_ulogic; + signal RXENMCOMMAALIGN1_ipd : std_ulogic; + signal RXSLIDE1_ipd : std_ulogic; + signal RXCOMMADETUSE1_ipd : std_ulogic; + signal RXDEC8B10BUSE1_ipd : std_ulogic; + signal RXENCHANSYNC1_ipd : std_ulogic; + signal RXCHBONDI1_ipd : std_logic_vector(3 downto 0); + signal RXDATAWIDTH1_ipd : std_logic_vector(1 downto 0); + signal TXELECIDLE0_ipd : std_ulogic; + signal TXDETECTRX0_ipd : std_ulogic; + signal TXELECIDLE1_ipd : std_ulogic; + signal TXDETECTRX1_ipd : std_ulogic; + signal TXCOMSTART0_ipd : std_ulogic; + signal TXCOMTYPE0_ipd : std_ulogic; + signal TXCOMSTART1_ipd : std_ulogic; + signal TXCOMTYPE1_ipd : std_ulogic; + signal PLLLKDETEN_ipd : std_ulogic; + signal TXENPRBSTST0_ipd : std_logic_vector(1 downto 0); + signal RXENPRBSTST0_ipd : std_logic_vector(1 downto 0); + signal PRBSCNTRESET0_ipd : std_ulogic; + signal TXENPRBSTST1_ipd : std_logic_vector(1 downto 0); + signal RXENPRBSTST1_ipd : std_logic_vector(1 downto 0); + signal PRBSCNTRESET1_ipd : std_ulogic; + signal DCLK_ipd : std_ulogic; + signal DADDR_ipd : std_logic_vector(6 downto 0); + signal DI_ipd : std_logic_vector(15 downto 0); + signal DEN_ipd : std_ulogic; + signal DWE_ipd : std_ulogic; + signal RXENSAMPLEALIGN0_ipd : std_ulogic; + signal RXENSAMPLEALIGN1_ipd : std_ulogic; + signal GTXTEST_ipd : std_logic_vector(13 downto 0); + signal TXHEADER0_ipd : std_logic_vector(2 downto 0); + signal TXSEQUENCE0_ipd : std_logic_vector(6 downto 0); + signal TXSTARTSEQ0_ipd : std_ulogic; + signal RXGEARBOXSLIP0_ipd : std_ulogic; + signal TXHEADER1_ipd : std_logic_vector(2 downto 0); + signal TXSEQUENCE1_ipd : std_logic_vector(6 downto 0); + signal TXSTARTSEQ1_ipd : std_ulogic; + signal RXGEARBOXSLIP1_ipd : std_ulogic; + signal DFECLKDLYADJ0_ipd : std_logic_vector(5 downto 0); + signal DFETAP10_ipd : std_logic_vector(4 downto 0); + signal DFETAP20_ipd : std_logic_vector(4 downto 0); + signal DFETAP30_ipd : std_logic_vector(3 downto 0); + signal DFETAP40_ipd : std_logic_vector(3 downto 0); + signal DFECLKDLYADJ1_ipd : std_logic_vector(5 downto 0); + signal DFETAP11_ipd : std_logic_vector(4 downto 0); + signal DFETAP21_ipd : std_logic_vector(4 downto 0); + signal DFETAP31_ipd : std_logic_vector(3 downto 0); + signal DFETAP41_ipd : std_logic_vector(3 downto 0); + + + signal CLKIN_indelay : std_ulogic; + signal TXUSRCLK0_indelay : std_ulogic; + signal TXUSRCLK20_indelay : std_ulogic; + signal RXUSRCLK0_indelay : std_ulogic; + signal RXUSRCLK20_indelay : std_ulogic; + signal TXUSRCLK1_indelay : std_ulogic; + signal TXUSRCLK21_indelay : std_ulogic; + signal RXUSRCLK1_indelay : std_ulogic; + signal RXUSRCLK21_indelay : std_ulogic; + signal RXP0_indelay : std_ulogic; + signal RXN0_indelay : std_ulogic; + signal TXDATA0_indelay : std_logic_vector(31 downto 0); + signal TXBYPASS8B10B0_indelay : std_logic_vector(3 downto 0); + signal TXCHARISK0_indelay : std_logic_vector(3 downto 0); + signal TXCHARDISPMODE0_indelay : std_logic_vector(3 downto 0); + signal TXCHARDISPVAL0_indelay : std_logic_vector(3 downto 0); + signal RXP1_indelay : std_ulogic; + signal RXN1_indelay : std_ulogic; + signal TXDATA1_indelay : std_logic_vector(31 downto 0); + signal TXBYPASS8B10B1_indelay : std_logic_vector(3 downto 0); + signal TXCHARISK1_indelay : std_logic_vector(3 downto 0); + signal TXCHARDISPMODE1_indelay : std_logic_vector(3 downto 0); + signal TXCHARDISPVAL1_indelay : std_logic_vector(3 downto 0); + signal GTXRESET_indelay : std_ulogic; + signal RXCDRRESET0_indelay : std_ulogic; + signal TXRESET0_indelay : std_ulogic; + signal RXRESET0_indelay : std_ulogic; + signal RXBUFRESET0_indelay : std_ulogic; + signal RXCDRRESET1_indelay : std_ulogic; + signal TXRESET1_indelay : std_ulogic; + signal RXRESET1_indelay : std_ulogic; + signal RXBUFRESET1_indelay : std_ulogic; + signal TXPOWERDOWN0_indelay : std_logic_vector(1 downto 0); + signal RXPOWERDOWN0_indelay : std_logic_vector(1 downto 0); + signal TXPOWERDOWN1_indelay : std_logic_vector(1 downto 0); + signal RXPOWERDOWN1_indelay : std_logic_vector(1 downto 0); + signal PLLPOWERDOWN_indelay : std_ulogic; + signal REFCLKPWRDNB_indelay : std_ulogic; + signal LOOPBACK0_indelay : std_logic_vector(2 downto 0); + signal LOOPBACK1_indelay : std_logic_vector(2 downto 0); + signal TXDIFFCTRL0_indelay : std_logic_vector(2 downto 0); + signal TXBUFDIFFCTRL0_indelay : std_logic_vector(2 downto 0); + signal TXPREEMPHASIS0_indelay : std_logic_vector(3 downto 0); + signal TXDIFFCTRL1_indelay : std_logic_vector(2 downto 0); + signal TXBUFDIFFCTRL1_indelay : std_logic_vector(2 downto 0); + signal TXPREEMPHASIS1_indelay : std_logic_vector(3 downto 0); + signal RXENEQB0_indelay : std_ulogic; + signal RXEQMIX0_indelay : std_logic_vector(1 downto 0); + signal RXEQPOLE0_indelay : std_logic_vector(3 downto 0); + signal RXENEQB1_indelay : std_ulogic; + signal RXEQMIX1_indelay : std_logic_vector(1 downto 0); + signal RXEQPOLE1_indelay : std_logic_vector(3 downto 0); + signal INTDATAWIDTH_indelay : std_ulogic; + signal TXDATAWIDTH0_indelay : std_logic_vector(1 downto 0); + signal TXDATAWIDTH1_indelay : std_logic_vector(1 downto 0); + signal TXENPMAPHASEALIGN0_indelay : std_ulogic; + signal TXPMASETPHASE0_indelay : std_ulogic; + signal RXENPMAPHASEALIGN0_indelay : std_ulogic; + signal RXPMASETPHASE0_indelay : std_ulogic; + signal TXENPMAPHASEALIGN1_indelay : std_ulogic; + signal TXPMASETPHASE1_indelay : std_ulogic; + signal RXENPMAPHASEALIGN1_indelay : std_ulogic; + signal RXPMASETPHASE1_indelay : std_ulogic; + signal TXENC8B10BUSE0_indelay : std_ulogic; + signal TXPOLARITY0_indelay : std_ulogic; + signal TXINHIBIT0_indelay : std_ulogic; + signal TXENC8B10BUSE1_indelay : std_ulogic; + signal TXPOLARITY1_indelay : std_ulogic; + signal TXINHIBIT1_indelay : std_ulogic; + signal RXPOLARITY0_indelay : std_ulogic; + signal RXENPCOMMAALIGN0_indelay : std_ulogic; + signal RXENMCOMMAALIGN0_indelay : std_ulogic; + signal RXSLIDE0_indelay : std_ulogic; + signal RXCOMMADETUSE0_indelay : std_ulogic; + signal RXDEC8B10BUSE0_indelay : std_ulogic; + signal RXENCHANSYNC0_indelay : std_ulogic; + signal RXCHBONDI0_indelay : std_logic_vector(3 downto 0); + signal RXDATAWIDTH0_indelay : std_logic_vector(1 downto 0); + signal RXPOLARITY1_indelay : std_ulogic; + signal RXENPCOMMAALIGN1_indelay : std_ulogic; + signal RXENMCOMMAALIGN1_indelay : std_ulogic; + signal RXSLIDE1_indelay : std_ulogic; + signal RXCOMMADETUSE1_indelay : std_ulogic; + signal RXDEC8B10BUSE1_indelay : std_ulogic; + signal RXENCHANSYNC1_indelay : std_ulogic; + signal RXCHBONDI1_indelay : std_logic_vector(3 downto 0); + signal RXDATAWIDTH1_indelay : std_logic_vector(1 downto 0); + signal TXELECIDLE0_indelay : std_ulogic; + signal TXDETECTRX0_indelay : std_ulogic; + signal TXELECIDLE1_indelay : std_ulogic; + signal TXDETECTRX1_indelay : std_ulogic; + signal TXCOMSTART0_indelay : std_ulogic; + signal TXCOMTYPE0_indelay : std_ulogic; + signal TXCOMSTART1_indelay : std_ulogic; + signal TXCOMTYPE1_indelay : std_ulogic; + signal PLLLKDETEN_indelay : std_ulogic; + signal TXENPRBSTST0_indelay : std_logic_vector(1 downto 0); + signal RXENPRBSTST0_indelay : std_logic_vector(1 downto 0); + signal PRBSCNTRESET0_indelay : std_ulogic; + signal TXENPRBSTST1_indelay : std_logic_vector(1 downto 0); + signal RXENPRBSTST1_indelay : std_logic_vector(1 downto 0); + signal PRBSCNTRESET1_indelay : std_ulogic; + signal DCLK_indelay : std_ulogic; + signal DADDR_indelay : std_logic_vector(6 downto 0); + signal DI_indelay : std_logic_vector(15 downto 0); + signal DEN_indelay : std_ulogic; + signal DWE_indelay : std_ulogic; + signal RXENSAMPLEALIGN0_indelay : std_ulogic; + signal RXENSAMPLEALIGN1_indelay : std_ulogic; + signal GTXTEST_indelay : std_logic_vector(13 downto 0); + signal TXHEADER0_indelay : std_logic_vector(2 downto 0); + signal TXSEQUENCE0_indelay : std_logic_vector(6 downto 0); + signal TXSTARTSEQ0_indelay : std_ulogic; + signal RXGEARBOXSLIP0_indelay : std_ulogic; + signal TXHEADER1_indelay : std_logic_vector(2 downto 0); + signal TXSEQUENCE1_indelay : std_logic_vector(6 downto 0); + signal TXSTARTSEQ1_indelay : std_ulogic; + signal RXGEARBOXSLIP1_indelay : std_ulogic; + signal DFECLKDLYADJ0_indelay : std_logic_vector(5 downto 0); + signal DFETAP10_indelay : std_logic_vector(4 downto 0); + signal DFETAP20_indelay : std_logic_vector(4 downto 0); + signal DFETAP30_indelay : std_logic_vector(3 downto 0); + signal DFETAP40_indelay : std_logic_vector(3 downto 0); + signal DFECLKDLYADJ1_indelay : std_logic_vector(5 downto 0); + signal DFETAP11_indelay : std_logic_vector(4 downto 0); + signal DFETAP21_indelay : std_logic_vector(4 downto 0); + signal DFETAP31_indelay : std_logic_vector(3 downto 0); + signal DFETAP41_indelay : std_logic_vector(3 downto 0); + +begin + + DFECLKDLYADJMONITOR0_out <= DFECLKDLYADJMONITOR0_outdelay after CLK_DELAY; + DFECLKDLYADJMONITOR1_out <= DFECLKDLYADJMONITOR1_outdelay after CLK_DELAY; + REFCLKOUT_out <= REFCLKOUT_outdelay after CLK_DELAY; + RXCLKCORCNT0_out <= RXCLKCORCNT0_outdelay after CLK_DELAY; + RXCLKCORCNT1_out <= RXCLKCORCNT1_outdelay after CLK_DELAY; + RXRECCLK0_out <= RXRECCLK0_outdelay after CLK_DELAY; + RXRECCLK1_out <= RXRECCLK1_outdelay after CLK_DELAY; + TXOUTCLK0_out <= TXOUTCLK0_outdelay after CLK_DELAY; + TXOUTCLK1_out <= TXOUTCLK1_outdelay after CLK_DELAY; + + DFEEYEDACMONITOR0_out <= DFEEYEDACMONITOR0_outdelay after OUT_DELAY; + DFEEYEDACMONITOR1_out <= DFEEYEDACMONITOR1_outdelay after OUT_DELAY; + DFESENSCAL0_out <= DFESENSCAL0_outdelay after OUT_DELAY; + DFESENSCAL1_out <= DFESENSCAL1_outdelay after OUT_DELAY; + DFETAP1MONITOR0_out <= DFETAP1MONITOR0_outdelay after OUT_DELAY; + DFETAP1MONITOR1_out <= DFETAP1MONITOR1_outdelay after OUT_DELAY; + DFETAP2MONITOR0_out <= DFETAP2MONITOR0_outdelay after OUT_DELAY; + DFETAP2MONITOR1_out <= DFETAP2MONITOR1_outdelay after OUT_DELAY; + DFETAP3MONITOR0_out <= DFETAP3MONITOR0_outdelay after OUT_DELAY; + DFETAP3MONITOR1_out <= DFETAP3MONITOR1_outdelay after OUT_DELAY; + DFETAP4MONITOR0_out <= DFETAP4MONITOR0_outdelay after OUT_DELAY; + DFETAP4MONITOR1_out <= DFETAP4MONITOR1_outdelay after OUT_DELAY; + DO_out <= DO_outdelay after OUT_DELAY; + DRDY_out <= DRDY_outdelay after OUT_DELAY; + PHYSTATUS0_out <= PHYSTATUS0_outdelay after OUT_DELAY; + PHYSTATUS1_out <= PHYSTATUS1_outdelay after OUT_DELAY; + PLLLKDET_out <= PLLLKDET_outdelay after OUT_DELAY; + RESETDONE0_out <= RESETDONE0_outdelay after OUT_DELAY; + RESETDONE1_out <= RESETDONE1_outdelay after OUT_DELAY; + RXBUFSTATUS0_out <= RXBUFSTATUS0_outdelay after OUT_DELAY; + RXBUFSTATUS1_out <= RXBUFSTATUS1_outdelay after OUT_DELAY; + RXBYTEISALIGNED0_out <= RXBYTEISALIGNED0_outdelay after OUT_DELAY; + RXBYTEISALIGNED1_out <= RXBYTEISALIGNED1_outdelay after OUT_DELAY; + RXBYTEREALIGN0_out <= RXBYTEREALIGN0_outdelay after OUT_DELAY; + RXBYTEREALIGN1_out <= RXBYTEREALIGN1_outdelay after OUT_DELAY; + RXCHANBONDSEQ0_out <= RXCHANBONDSEQ0_outdelay after OUT_DELAY; + RXCHANBONDSEQ1_out <= RXCHANBONDSEQ1_outdelay after OUT_DELAY; + RXCHANISALIGNED0_out <= RXCHANISALIGNED0_outdelay after OUT_DELAY; + RXCHANISALIGNED1_out <= RXCHANISALIGNED1_outdelay after OUT_DELAY; + RXCHANREALIGN0_out <= RXCHANREALIGN0_outdelay after OUT_DELAY; + RXCHANREALIGN1_out <= RXCHANREALIGN1_outdelay after OUT_DELAY; + RXCHARISCOMMA0_out <= RXCHARISCOMMA0_outdelay after OUT_DELAY; + RXCHARISCOMMA1_out <= RXCHARISCOMMA1_outdelay after OUT_DELAY; + RXCHARISK0_out <= RXCHARISK0_outdelay after OUT_DELAY; + RXCHARISK1_out <= RXCHARISK1_outdelay after OUT_DELAY; + RXCHBONDO0_out <= RXCHBONDO0_outdelay after OUT_DELAY; + RXCHBONDO1_out <= RXCHBONDO1_outdelay after OUT_DELAY; + RXCOMMADET0_out <= RXCOMMADET0_outdelay after OUT_DELAY; + RXCOMMADET1_out <= RXCOMMADET1_outdelay after OUT_DELAY; + RXDATA0_out <= RXDATA0_outdelay after OUT_DELAY; + RXDATA1_out <= RXDATA1_outdelay after OUT_DELAY; + RXDATAVALID0_out <= RXDATAVALID0_outdelay after OUT_DELAY; + RXDATAVALID1_out <= RXDATAVALID1_outdelay after OUT_DELAY; + RXDISPERR0_out <= RXDISPERR0_outdelay after OUT_DELAY; + RXDISPERR1_out <= RXDISPERR1_outdelay after OUT_DELAY; + RXELECIDLE0_out <= RXELECIDLE0_outdelay after OUT_DELAY; + RXELECIDLE1_out <= RXELECIDLE1_outdelay after OUT_DELAY; + RXHEADER0_out <= RXHEADER0_outdelay after OUT_DELAY; + RXHEADER1_out <= RXHEADER1_outdelay after OUT_DELAY; + RXHEADERVALID0_out <= RXHEADERVALID0_outdelay after OUT_DELAY; + RXHEADERVALID1_out <= RXHEADERVALID1_outdelay after OUT_DELAY; + RXLOSSOFSYNC0_out <= RXLOSSOFSYNC0_outdelay after OUT_DELAY; + RXLOSSOFSYNC1_out <= RXLOSSOFSYNC1_outdelay after OUT_DELAY; + RXNOTINTABLE0_out <= RXNOTINTABLE0_outdelay after OUT_DELAY; + RXNOTINTABLE1_out <= RXNOTINTABLE1_outdelay after OUT_DELAY; + RXOVERSAMPLEERR0_out <= RXOVERSAMPLEERR0_outdelay after OUT_DELAY; + RXOVERSAMPLEERR1_out <= RXOVERSAMPLEERR1_outdelay after OUT_DELAY; + RXPRBSERR0_out <= RXPRBSERR0_outdelay after OUT_DELAY; + RXPRBSERR1_out <= RXPRBSERR1_outdelay after OUT_DELAY; + RXRUNDISP0_out <= RXRUNDISP0_outdelay after OUT_DELAY; + RXRUNDISP1_out <= RXRUNDISP1_outdelay after OUT_DELAY; + RXSTARTOFSEQ0_out <= RXSTARTOFSEQ0_outdelay after OUT_DELAY; + RXSTARTOFSEQ1_out <= RXSTARTOFSEQ1_outdelay after OUT_DELAY; + RXSTATUS0_out <= RXSTATUS0_outdelay after OUT_DELAY; + RXSTATUS1_out <= RXSTATUS1_outdelay after OUT_DELAY; + RXVALID0_out <= RXVALID0_outdelay after OUT_DELAY; + RXVALID1_out <= RXVALID1_outdelay after OUT_DELAY; + TXBUFSTATUS0_out <= TXBUFSTATUS0_outdelay after OUT_DELAY; + TXBUFSTATUS1_out <= TXBUFSTATUS1_outdelay after OUT_DELAY; + TXGEARBOXREADY0_out <= TXGEARBOXREADY0_outdelay after OUT_DELAY; + TXGEARBOXREADY1_out <= TXGEARBOXREADY1_outdelay after OUT_DELAY; + TXKERR0_out <= TXKERR0_outdelay after OUT_DELAY; + TXKERR1_out <= TXKERR1_outdelay after OUT_DELAY; + TXN0_out <= TXN0_outdelay after OUT_DELAY; + TXN1_out <= TXN1_outdelay after OUT_DELAY; + TXP0_out <= TXP0_outdelay after OUT_DELAY; + TXP1_out <= TXP1_outdelay after OUT_DELAY; + TXRUNDISP0_out <= TXRUNDISP0_outdelay after OUT_DELAY; + TXRUNDISP1_out <= TXRUNDISP1_outdelay after OUT_DELAY; + + DCLK_ipd <= DCLK after CLK_DELAY; + RXUSRCLK0_ipd <= RXUSRCLK0 after CLK_DELAY; + RXUSRCLK1_ipd <= RXUSRCLK1 after CLK_DELAY; + RXUSRCLK20_ipd <= RXUSRCLK20 after CLK_DELAY; + RXUSRCLK21_ipd <= RXUSRCLK21 after CLK_DELAY; + TXUSRCLK0_ipd <= TXUSRCLK0 after CLK_DELAY; + TXUSRCLK1_ipd <= TXUSRCLK1 after CLK_DELAY; + TXUSRCLK20_ipd <= TXUSRCLK20 after CLK_DELAY; + TXUSRCLK21_ipd <= TXUSRCLK21 after CLK_DELAY; + + CLKIN_ipd <= CLKIN after CLK_DELAY; + DADDR_ipd <= DADDR after CLK_DELAY; + DEN_ipd <= DEN after CLK_DELAY; + DFECLKDLYADJ0_ipd <= DFECLKDLYADJ0 after CLK_DELAY; + DFECLKDLYADJ1_ipd <= DFECLKDLYADJ1 after CLK_DELAY; + DFETAP10_ipd <= DFETAP10 after CLK_DELAY; + DFETAP11_ipd <= DFETAP11 after CLK_DELAY; + DFETAP20_ipd <= DFETAP20 after CLK_DELAY; + DFETAP21_ipd <= DFETAP21 after CLK_DELAY; + DFETAP30_ipd <= DFETAP30 after CLK_DELAY; + DFETAP31_ipd <= DFETAP31 after CLK_DELAY; + DFETAP40_ipd <= DFETAP40 after CLK_DELAY; + DFETAP41_ipd <= DFETAP41 after CLK_DELAY; + DI_ipd <= DI after CLK_DELAY; + DWE_ipd <= DWE after CLK_DELAY; + GTXRESET_ipd <= GTXRESET after CLK_DELAY; + GTXTEST_ipd <= GTXTEST after CLK_DELAY; + INTDATAWIDTH_ipd <= INTDATAWIDTH after CLK_DELAY; + LOOPBACK0_ipd <= LOOPBACK0 after CLK_DELAY; + LOOPBACK1_ipd <= LOOPBACK1 after CLK_DELAY; + PLLLKDETEN_ipd <= PLLLKDETEN after CLK_DELAY; + PLLPOWERDOWN_ipd <= PLLPOWERDOWN after CLK_DELAY; + PRBSCNTRESET0_ipd <= PRBSCNTRESET0 after CLK_DELAY; + PRBSCNTRESET1_ipd <= PRBSCNTRESET1 after CLK_DELAY; + REFCLKPWRDNB_ipd <= REFCLKPWRDNB after CLK_DELAY; + RXBUFRESET0_ipd <= RXBUFRESET0 after CLK_DELAY; + RXBUFRESET1_ipd <= RXBUFRESET1 after CLK_DELAY; + RXCDRRESET0_ipd <= RXCDRRESET0 after CLK_DELAY; + RXCDRRESET1_ipd <= RXCDRRESET1 after CLK_DELAY; + RXCHBONDI0_ipd <= RXCHBONDI0 after CLK_DELAY; + RXCHBONDI1_ipd <= RXCHBONDI1 after CLK_DELAY; + RXCOMMADETUSE0_ipd <= RXCOMMADETUSE0 after CLK_DELAY; + RXCOMMADETUSE1_ipd <= RXCOMMADETUSE1 after CLK_DELAY; + RXDATAWIDTH0_ipd <= RXDATAWIDTH0 after CLK_DELAY; + RXDATAWIDTH1_ipd <= RXDATAWIDTH1 after CLK_DELAY; + RXDEC8B10BUSE0_ipd <= RXDEC8B10BUSE0 after CLK_DELAY; + RXDEC8B10BUSE1_ipd <= RXDEC8B10BUSE1 after CLK_DELAY; + RXENCHANSYNC0_ipd <= RXENCHANSYNC0 after CLK_DELAY; + RXENCHANSYNC1_ipd <= RXENCHANSYNC1 after CLK_DELAY; + RXENEQB0_ipd <= RXENEQB0 after CLK_DELAY; + RXENEQB1_ipd <= RXENEQB1 after CLK_DELAY; + RXENMCOMMAALIGN0_ipd <= RXENMCOMMAALIGN0 after CLK_DELAY; + RXENMCOMMAALIGN1_ipd <= RXENMCOMMAALIGN1 after CLK_DELAY; + RXENPCOMMAALIGN0_ipd <= RXENPCOMMAALIGN0 after CLK_DELAY; + RXENPCOMMAALIGN1_ipd <= RXENPCOMMAALIGN1 after CLK_DELAY; + RXENPMAPHASEALIGN0_ipd <= RXENPMAPHASEALIGN0 after CLK_DELAY; + RXENPMAPHASEALIGN1_ipd <= RXENPMAPHASEALIGN1 after CLK_DELAY; + RXENPRBSTST0_ipd <= RXENPRBSTST0 after CLK_DELAY; + RXENPRBSTST1_ipd <= RXENPRBSTST1 after CLK_DELAY; + RXENSAMPLEALIGN0_ipd <= RXENSAMPLEALIGN0 after CLK_DELAY; + RXENSAMPLEALIGN1_ipd <= RXENSAMPLEALIGN1 after CLK_DELAY; + RXEQMIX0_ipd <= RXEQMIX0 after CLK_DELAY; + RXEQMIX1_ipd <= RXEQMIX1 after CLK_DELAY; + RXEQPOLE0_ipd <= RXEQPOLE0 after CLK_DELAY; + RXEQPOLE1_ipd <= RXEQPOLE1 after CLK_DELAY; + RXGEARBOXSLIP0_ipd <= RXGEARBOXSLIP0 after CLK_DELAY; + RXGEARBOXSLIP1_ipd <= RXGEARBOXSLIP1 after CLK_DELAY; + RXN0_ipd <= RXN0 after CLK_DELAY; + RXN1_ipd <= RXN1 after CLK_DELAY; + RXP0_ipd <= RXP0 after CLK_DELAY; + RXP1_ipd <= RXP1 after CLK_DELAY; + RXPMASETPHASE0_ipd <= RXPMASETPHASE0 after CLK_DELAY; + RXPMASETPHASE1_ipd <= RXPMASETPHASE1 after CLK_DELAY; + RXPOLARITY0_ipd <= RXPOLARITY0 after CLK_DELAY; + RXPOLARITY1_ipd <= RXPOLARITY1 after CLK_DELAY; + RXPOWERDOWN0_ipd <= RXPOWERDOWN0 after CLK_DELAY; + RXPOWERDOWN1_ipd <= RXPOWERDOWN1 after CLK_DELAY; + RXRESET0_ipd <= RXRESET0 after CLK_DELAY; + RXRESET1_ipd <= RXRESET1 after CLK_DELAY; + RXSLIDE0_ipd <= RXSLIDE0 after CLK_DELAY; + RXSLIDE1_ipd <= RXSLIDE1 after CLK_DELAY; + TXBUFDIFFCTRL0_ipd <= TXBUFDIFFCTRL0 after CLK_DELAY; + TXBUFDIFFCTRL1_ipd <= TXBUFDIFFCTRL1 after CLK_DELAY; + TXBYPASS8B10B0_ipd <= TXBYPASS8B10B0 after CLK_DELAY; + TXBYPASS8B10B1_ipd <= TXBYPASS8B10B1 after CLK_DELAY; + TXCHARDISPMODE0_ipd <= TXCHARDISPMODE0 after CLK_DELAY; + TXCHARDISPMODE1_ipd <= TXCHARDISPMODE1 after CLK_DELAY; + TXCHARDISPVAL0_ipd <= TXCHARDISPVAL0 after CLK_DELAY; + TXCHARDISPVAL1_ipd <= TXCHARDISPVAL1 after CLK_DELAY; + TXCHARISK0_ipd <= TXCHARISK0 after CLK_DELAY; + TXCHARISK1_ipd <= TXCHARISK1 after CLK_DELAY; + TXCOMSTART0_ipd <= TXCOMSTART0 after CLK_DELAY; + TXCOMSTART1_ipd <= TXCOMSTART1 after CLK_DELAY; + TXCOMTYPE0_ipd <= TXCOMTYPE0 after CLK_DELAY; + TXCOMTYPE1_ipd <= TXCOMTYPE1 after CLK_DELAY; + TXDATA0_ipd <= TXDATA0 after CLK_DELAY; + TXDATA1_ipd <= TXDATA1 after CLK_DELAY; + TXDATAWIDTH0_ipd <= TXDATAWIDTH0 after CLK_DELAY; + TXDATAWIDTH1_ipd <= TXDATAWIDTH1 after CLK_DELAY; + TXDETECTRX0_ipd <= TXDETECTRX0 after CLK_DELAY; + TXDETECTRX1_ipd <= TXDETECTRX1 after CLK_DELAY; + TXDIFFCTRL0_ipd <= TXDIFFCTRL0 after CLK_DELAY; + TXDIFFCTRL1_ipd <= TXDIFFCTRL1 after CLK_DELAY; + TXELECIDLE0_ipd <= TXELECIDLE0 after CLK_DELAY; + TXELECIDLE1_ipd <= TXELECIDLE1 after CLK_DELAY; + TXENC8B10BUSE0_ipd <= TXENC8B10BUSE0 after CLK_DELAY; + TXENC8B10BUSE1_ipd <= TXENC8B10BUSE1 after CLK_DELAY; + TXENPMAPHASEALIGN0_ipd <= TXENPMAPHASEALIGN0 after CLK_DELAY; + TXENPMAPHASEALIGN1_ipd <= TXENPMAPHASEALIGN1 after CLK_DELAY; + TXENPRBSTST0_ipd <= TXENPRBSTST0 after CLK_DELAY; + TXENPRBSTST1_ipd <= TXENPRBSTST1 after CLK_DELAY; + TXHEADER0_ipd <= TXHEADER0 after CLK_DELAY; + TXHEADER1_ipd <= TXHEADER1 after CLK_DELAY; + TXINHIBIT0_ipd <= TXINHIBIT0 after CLK_DELAY; + TXINHIBIT1_ipd <= TXINHIBIT1 after CLK_DELAY; + TXPMASETPHASE0_ipd <= TXPMASETPHASE0 after CLK_DELAY; + TXPMASETPHASE1_ipd <= TXPMASETPHASE1 after CLK_DELAY; + TXPOLARITY0_ipd <= TXPOLARITY0 after CLK_DELAY; + TXPOLARITY1_ipd <= TXPOLARITY1 after CLK_DELAY; + TXPOWERDOWN0_ipd <= TXPOWERDOWN0 after CLK_DELAY; + TXPOWERDOWN1_ipd <= TXPOWERDOWN1 after CLK_DELAY; + TXPREEMPHASIS0_ipd <= TXPREEMPHASIS0 after CLK_DELAY; + TXPREEMPHASIS1_ipd <= TXPREEMPHASIS1 after CLK_DELAY; + TXRESET0_ipd <= TXRESET0 after CLK_DELAY; + TXRESET1_ipd <= TXRESET1 after CLK_DELAY; + TXSEQUENCE0_ipd <= TXSEQUENCE0 after CLK_DELAY; + TXSEQUENCE1_ipd <= TXSEQUENCE1 after CLK_DELAY; + TXSTARTSEQ0_ipd <= TXSTARTSEQ0 after CLK_DELAY; + TXSTARTSEQ1_ipd <= TXSTARTSEQ1 after CLK_DELAY; + + DCLK_indelay <= DCLK_ipd after CLK_DELAY; + RXUSRCLK0_indelay <= RXUSRCLK0_ipd after CLK_DELAY; + RXUSRCLK1_indelay <= RXUSRCLK1_ipd after CLK_DELAY; + RXUSRCLK20_indelay <= RXUSRCLK20_ipd after CLK_DELAY; + RXUSRCLK21_indelay <= RXUSRCLK21_ipd after CLK_DELAY; + TXUSRCLK0_indelay <= TXUSRCLK0_ipd after CLK_DELAY; + TXUSRCLK1_indelay <= TXUSRCLK1_ipd after CLK_DELAY; + TXUSRCLK20_indelay <= TXUSRCLK20_ipd after CLK_DELAY; + TXUSRCLK21_indelay <= TXUSRCLK21_ipd after CLK_DELAY; + + CLKIN_indelay <= CLKIN_ipd after IN_DELAY; + DADDR_indelay <= DADDR_ipd after IN_DELAY; + DEN_indelay <= DEN_ipd after IN_DELAY; + DFECLKDLYADJ0_indelay <= DFECLKDLYADJ0_ipd after IN_DELAY; + DFECLKDLYADJ1_indelay <= DFECLKDLYADJ1_ipd after IN_DELAY; + DFETAP10_indelay <= DFETAP10_ipd after IN_DELAY; + DFETAP11_indelay <= DFETAP11_ipd after IN_DELAY; + DFETAP20_indelay <= DFETAP20_ipd after IN_DELAY; + DFETAP21_indelay <= DFETAP21_ipd after IN_DELAY; + DFETAP30_indelay <= DFETAP30_ipd after IN_DELAY; + DFETAP31_indelay <= DFETAP31_ipd after IN_DELAY; + DFETAP40_indelay <= DFETAP40_ipd after IN_DELAY; + DFETAP41_indelay <= DFETAP41_ipd after IN_DELAY; + DI_indelay <= DI_ipd after IN_DELAY; + DWE_indelay <= DWE_ipd after IN_DELAY; + GTXRESET_indelay <= GTXRESET_ipd after IN_DELAY; + GTXTEST_indelay <= GTXTEST_ipd after IN_DELAY; + INTDATAWIDTH_indelay <= INTDATAWIDTH_ipd after IN_DELAY; + LOOPBACK0_indelay <= LOOPBACK0_ipd after IN_DELAY; + LOOPBACK1_indelay <= LOOPBACK1_ipd after IN_DELAY; + PLLLKDETEN_indelay <= PLLLKDETEN_ipd after IN_DELAY; + PLLPOWERDOWN_indelay <= PLLPOWERDOWN_ipd after IN_DELAY; + PRBSCNTRESET0_indelay <= PRBSCNTRESET0_ipd after IN_DELAY; + PRBSCNTRESET1_indelay <= PRBSCNTRESET1_ipd after IN_DELAY; + REFCLKPWRDNB_indelay <= REFCLKPWRDNB_ipd after IN_DELAY; + RXBUFRESET0_indelay <= RXBUFRESET0_ipd after IN_DELAY; + RXBUFRESET1_indelay <= RXBUFRESET1_ipd after IN_DELAY; + RXCDRRESET0_indelay <= RXCDRRESET0_ipd after IN_DELAY; + RXCDRRESET1_indelay <= RXCDRRESET1_ipd after IN_DELAY; + RXCHBONDI0_indelay <= RXCHBONDI0_ipd after IN_DELAY; + RXCHBONDI1_indelay <= RXCHBONDI1_ipd after IN_DELAY; + RXCOMMADETUSE0_indelay <= RXCOMMADETUSE0_ipd after IN_DELAY; + RXCOMMADETUSE1_indelay <= RXCOMMADETUSE1_ipd after IN_DELAY; + RXDATAWIDTH0_indelay <= RXDATAWIDTH0_ipd after IN_DELAY; + RXDATAWIDTH1_indelay <= RXDATAWIDTH1_ipd after IN_DELAY; + RXDEC8B10BUSE0_indelay <= RXDEC8B10BUSE0_ipd after IN_DELAY; + RXDEC8B10BUSE1_indelay <= RXDEC8B10BUSE1_ipd after IN_DELAY; + RXENCHANSYNC0_indelay <= RXENCHANSYNC0_ipd after IN_DELAY; + RXENCHANSYNC1_indelay <= RXENCHANSYNC1_ipd after IN_DELAY; + RXENEQB0_indelay <= RXENEQB0_ipd after IN_DELAY; + RXENEQB1_indelay <= RXENEQB1_ipd after IN_DELAY; + RXENMCOMMAALIGN0_indelay <= RXENMCOMMAALIGN0_ipd after IN_DELAY; + RXENMCOMMAALIGN1_indelay <= RXENMCOMMAALIGN1_ipd after IN_DELAY; + RXENPCOMMAALIGN0_indelay <= RXENPCOMMAALIGN0_ipd after IN_DELAY; + RXENPCOMMAALIGN1_indelay <= RXENPCOMMAALIGN1_ipd after IN_DELAY; + RXENPMAPHASEALIGN0_indelay <= RXENPMAPHASEALIGN0_ipd after IN_DELAY; + RXENPMAPHASEALIGN1_indelay <= RXENPMAPHASEALIGN1_ipd after IN_DELAY; + RXENPRBSTST0_indelay <= RXENPRBSTST0_ipd after IN_DELAY; + RXENPRBSTST1_indelay <= RXENPRBSTST1_ipd after IN_DELAY; + RXENSAMPLEALIGN0_indelay <= RXENSAMPLEALIGN0_ipd after IN_DELAY; + RXENSAMPLEALIGN1_indelay <= RXENSAMPLEALIGN1_ipd after IN_DELAY; + RXEQMIX0_indelay <= RXEQMIX0_ipd after IN_DELAY; + RXEQMIX1_indelay <= RXEQMIX1_ipd after IN_DELAY; + RXEQPOLE0_indelay <= RXEQPOLE0_ipd after IN_DELAY; + RXEQPOLE1_indelay <= RXEQPOLE1_ipd after IN_DELAY; + RXGEARBOXSLIP0_indelay <= RXGEARBOXSLIP0_ipd after IN_DELAY; + RXGEARBOXSLIP1_indelay <= RXGEARBOXSLIP1_ipd after IN_DELAY; + RXN0_indelay <= RXN0_ipd after IN_DELAY; + RXN1_indelay <= RXN1_ipd after IN_DELAY; + RXP0_indelay <= RXP0_ipd after IN_DELAY; + RXP1_indelay <= RXP1_ipd after IN_DELAY; + RXPMASETPHASE0_indelay <= RXPMASETPHASE0_ipd after IN_DELAY; + RXPMASETPHASE1_indelay <= RXPMASETPHASE1_ipd after IN_DELAY; + RXPOLARITY0_indelay <= RXPOLARITY0_ipd after IN_DELAY; + RXPOLARITY1_indelay <= RXPOLARITY1_ipd after IN_DELAY; + RXPOWERDOWN0_indelay <= RXPOWERDOWN0_ipd after IN_DELAY; + RXPOWERDOWN1_indelay <= RXPOWERDOWN1_ipd after IN_DELAY; + RXRESET0_indelay <= RXRESET0_ipd after IN_DELAY; + RXRESET1_indelay <= RXRESET1_ipd after IN_DELAY; + RXSLIDE0_indelay <= RXSLIDE0_ipd after IN_DELAY; + RXSLIDE1_indelay <= RXSLIDE1_ipd after IN_DELAY; + TXBUFDIFFCTRL0_indelay <= TXBUFDIFFCTRL0_ipd after IN_DELAY; + TXBUFDIFFCTRL1_indelay <= TXBUFDIFFCTRL1_ipd after IN_DELAY; + TXBYPASS8B10B0_indelay <= TXBYPASS8B10B0_ipd after IN_DELAY; + TXBYPASS8B10B1_indelay <= TXBYPASS8B10B1_ipd after IN_DELAY; + TXCHARDISPMODE0_indelay <= TXCHARDISPMODE0_ipd after IN_DELAY; + TXCHARDISPMODE1_indelay <= TXCHARDISPMODE1_ipd after IN_DELAY; + TXCHARDISPVAL0_indelay <= TXCHARDISPVAL0_ipd after IN_DELAY; + TXCHARDISPVAL1_indelay <= TXCHARDISPVAL1_ipd after IN_DELAY; + TXCHARISK0_indelay <= TXCHARISK0_ipd after IN_DELAY; + TXCHARISK1_indelay <= TXCHARISK1_ipd after IN_DELAY; + TXCOMSTART0_indelay <= TXCOMSTART0_ipd after IN_DELAY; + TXCOMSTART1_indelay <= TXCOMSTART1_ipd after IN_DELAY; + TXCOMTYPE0_indelay <= TXCOMTYPE0_ipd after IN_DELAY; + TXCOMTYPE1_indelay <= TXCOMTYPE1_ipd after IN_DELAY; + TXDATA0_indelay <= TXDATA0_ipd after IN_DELAY; + TXDATA1_indelay <= TXDATA1_ipd after IN_DELAY; + TXDATAWIDTH0_indelay <= TXDATAWIDTH0_ipd after IN_DELAY; + TXDATAWIDTH1_indelay <= TXDATAWIDTH1_ipd after IN_DELAY; + TXDETECTRX0_indelay <= TXDETECTRX0_ipd after IN_DELAY; + TXDETECTRX1_indelay <= TXDETECTRX1_ipd after IN_DELAY; + TXDIFFCTRL0_indelay <= TXDIFFCTRL0_ipd after IN_DELAY; + TXDIFFCTRL1_indelay <= TXDIFFCTRL1_ipd after IN_DELAY; + TXELECIDLE0_indelay <= TXELECIDLE0_ipd after IN_DELAY; + TXELECIDLE1_indelay <= TXELECIDLE1_ipd after IN_DELAY; + TXENC8B10BUSE0_indelay <= TXENC8B10BUSE0_ipd after IN_DELAY; + TXENC8B10BUSE1_indelay <= TXENC8B10BUSE1_ipd after IN_DELAY; + TXENPMAPHASEALIGN0_indelay <= TXENPMAPHASEALIGN0_ipd after IN_DELAY; + TXENPMAPHASEALIGN1_indelay <= TXENPMAPHASEALIGN1_ipd after IN_DELAY; + TXENPRBSTST0_indelay <= TXENPRBSTST0_ipd after IN_DELAY; + TXENPRBSTST1_indelay <= TXENPRBSTST1_ipd after IN_DELAY; + TXHEADER0_indelay <= TXHEADER0_ipd after IN_DELAY; + TXHEADER1_indelay <= TXHEADER1_ipd after IN_DELAY; + TXINHIBIT0_indelay <= TXINHIBIT0_ipd after IN_DELAY; + TXINHIBIT1_indelay <= TXINHIBIT1_ipd after IN_DELAY; + TXPMASETPHASE0_indelay <= TXPMASETPHASE0_ipd after IN_DELAY; + TXPMASETPHASE1_indelay <= TXPMASETPHASE1_ipd after IN_DELAY; + TXPOLARITY0_indelay <= TXPOLARITY0_ipd after IN_DELAY; + TXPOLARITY1_indelay <= TXPOLARITY1_ipd after IN_DELAY; + TXPOWERDOWN0_indelay <= TXPOWERDOWN0_ipd after IN_DELAY; + TXPOWERDOWN1_indelay <= TXPOWERDOWN1_ipd after IN_DELAY; + TXPREEMPHASIS0_indelay <= TXPREEMPHASIS0_ipd after IN_DELAY; + TXPREEMPHASIS1_indelay <= TXPREEMPHASIS1_ipd after IN_DELAY; + TXRESET0_indelay <= TXRESET0_ipd after IN_DELAY; + TXRESET1_indelay <= TXRESET1_ipd after IN_DELAY; + TXSEQUENCE0_indelay <= TXSEQUENCE0_ipd after IN_DELAY; + TXSEQUENCE1_indelay <= TXSEQUENCE1_ipd after IN_DELAY; + TXSTARTSEQ0_indelay <= TXSTARTSEQ0_ipd after IN_DELAY; + TXSTARTSEQ1_indelay <= TXSTARTSEQ1_ipd after IN_DELAY; + + + legacy_model: if SIM_MODE = "LEGACY" generate + gtx_dual_swift_bw_1 : GTX_DUAL_SWIFT_BUS + port map ( + STEPPING => STEPPING_BINARY, + AC_CAP_DIS_0 => AC_CAP_DIS_0_BINARY, + AC_CAP_DIS_1 => AC_CAP_DIS_1_BINARY, + ALIGN_COMMA_WORD_0 => ALIGN_COMMA_WORD_0_BINARY, + ALIGN_COMMA_WORD_1 => ALIGN_COMMA_WORD_1_BINARY, + CB2_INH_CC_PERIOD_0 => CB2_INH_CC_PERIOD_0_BINARY, + CB2_INH_CC_PERIOD_1 => CB2_INH_CC_PERIOD_1_BINARY, + CDR_PH_ADJ_TIME => CDR_PH_ADJ_TIME_BINARY, + CHAN_BOND_1_MAX_SKEW_0 => CHAN_BOND_1_MAX_SKEW_0_BINARY, + CHAN_BOND_1_MAX_SKEW_1 => CHAN_BOND_1_MAX_SKEW_1_BINARY, + CHAN_BOND_2_MAX_SKEW_0 => CHAN_BOND_2_MAX_SKEW_0_BINARY, + CHAN_BOND_2_MAX_SKEW_1 => CHAN_BOND_2_MAX_SKEW_1_BINARY, + CHAN_BOND_KEEP_ALIGN_0 => CHAN_BOND_KEEP_ALIGN_0_BINARY, + CHAN_BOND_KEEP_ALIGN_1 => CHAN_BOND_KEEP_ALIGN_1_BINARY, + CHAN_BOND_LEVEL_0 => CHAN_BOND_LEVEL_0_BINARY, + CHAN_BOND_LEVEL_1 => CHAN_BOND_LEVEL_1_BINARY, + CHAN_BOND_MODE_0 => CHAN_BOND_MODE_0_BINARY, + CHAN_BOND_MODE_1 => CHAN_BOND_MODE_1_BINARY, + CHAN_BOND_SEQ_1_1_0 => CHAN_BOND_SEQ_1_1_0_BINARY, + CHAN_BOND_SEQ_1_1_1 => CHAN_BOND_SEQ_1_1_1_BINARY, + CHAN_BOND_SEQ_1_2_0 => CHAN_BOND_SEQ_1_2_0_BINARY, + CHAN_BOND_SEQ_1_2_1 => CHAN_BOND_SEQ_1_2_1_BINARY, + CHAN_BOND_SEQ_1_3_0 => CHAN_BOND_SEQ_1_3_0_BINARY, + CHAN_BOND_SEQ_1_3_1 => CHAN_BOND_SEQ_1_3_1_BINARY, + CHAN_BOND_SEQ_1_4_0 => CHAN_BOND_SEQ_1_4_0_BINARY, + CHAN_BOND_SEQ_1_4_1 => CHAN_BOND_SEQ_1_4_1_BINARY, + CHAN_BOND_SEQ_1_ENABLE_0 => CHAN_BOND_SEQ_1_ENABLE_0_BINARY, + CHAN_BOND_SEQ_1_ENABLE_1 => CHAN_BOND_SEQ_1_ENABLE_1_BINARY, + CHAN_BOND_SEQ_2_1_0 => CHAN_BOND_SEQ_2_1_0_BINARY, + CHAN_BOND_SEQ_2_1_1 => CHAN_BOND_SEQ_2_1_1_BINARY, + CHAN_BOND_SEQ_2_2_0 => CHAN_BOND_SEQ_2_2_0_BINARY, + CHAN_BOND_SEQ_2_2_1 => CHAN_BOND_SEQ_2_2_1_BINARY, + CHAN_BOND_SEQ_2_3_0 => CHAN_BOND_SEQ_2_3_0_BINARY, + CHAN_BOND_SEQ_2_3_1 => CHAN_BOND_SEQ_2_3_1_BINARY, + CHAN_BOND_SEQ_2_4_0 => CHAN_BOND_SEQ_2_4_0_BINARY, + CHAN_BOND_SEQ_2_4_1 => CHAN_BOND_SEQ_2_4_1_BINARY, + CHAN_BOND_SEQ_2_ENABLE_0 => CHAN_BOND_SEQ_2_ENABLE_0_BINARY, + CHAN_BOND_SEQ_2_ENABLE_1 => CHAN_BOND_SEQ_2_ENABLE_1_BINARY, + CHAN_BOND_SEQ_2_USE_0 => CHAN_BOND_SEQ_2_USE_0_BINARY, + CHAN_BOND_SEQ_2_USE_1 => CHAN_BOND_SEQ_2_USE_1_BINARY, + CHAN_BOND_SEQ_LEN_0 => CHAN_BOND_SEQ_LEN_0_BINARY, + CHAN_BOND_SEQ_LEN_1 => CHAN_BOND_SEQ_LEN_1_BINARY, + CLK25_DIVIDER => CLK25_DIVIDER_BINARY, + CLKINDC_B => CLKINDC_B_BINARY, + CLKRCV_TRST => CLKRCV_TRST_BINARY, + CLK_CORRECT_USE_0 => CLK_CORRECT_USE_0_BINARY, + CLK_CORRECT_USE_1 => CLK_CORRECT_USE_1_BINARY, + CLK_COR_ADJ_LEN_0 => CLK_COR_ADJ_LEN_0_BINARY, + CLK_COR_ADJ_LEN_1 => CLK_COR_ADJ_LEN_1_BINARY, + CLK_COR_DET_LEN_0 => CLK_COR_DET_LEN_0_BINARY, + CLK_COR_DET_LEN_1 => CLK_COR_DET_LEN_1_BINARY, + CLK_COR_INSERT_IDLE_FLAG_0 => CLK_COR_INSERT_IDLE_FLAG_0_BINARY, + CLK_COR_INSERT_IDLE_FLAG_1 => CLK_COR_INSERT_IDLE_FLAG_1_BINARY, + CLK_COR_KEEP_IDLE_0 => CLK_COR_KEEP_IDLE_0_BINARY, + CLK_COR_KEEP_IDLE_1 => CLK_COR_KEEP_IDLE_1_BINARY, + CLK_COR_MAX_LAT_0 => CLK_COR_MAX_LAT_0_BINARY, + CLK_COR_MAX_LAT_1 => CLK_COR_MAX_LAT_1_BINARY, + CLK_COR_MIN_LAT_0 => CLK_COR_MIN_LAT_0_BINARY, + CLK_COR_MIN_LAT_1 => CLK_COR_MIN_LAT_1_BINARY, + CLK_COR_PRECEDENCE_0 => CLK_COR_PRECEDENCE_0_BINARY, + CLK_COR_PRECEDENCE_1 => CLK_COR_PRECEDENCE_1_BINARY, + CLK_COR_REPEAT_WAIT_0 => CLK_COR_REPEAT_WAIT_0_BINARY, + CLK_COR_REPEAT_WAIT_1 => CLK_COR_REPEAT_WAIT_1_BINARY, + CLK_COR_SEQ_1_1_0 => CLK_COR_SEQ_1_1_0_BINARY, + CLK_COR_SEQ_1_1_1 => CLK_COR_SEQ_1_1_1_BINARY, + CLK_COR_SEQ_1_2_0 => CLK_COR_SEQ_1_2_0_BINARY, + CLK_COR_SEQ_1_2_1 => CLK_COR_SEQ_1_2_1_BINARY, + CLK_COR_SEQ_1_3_0 => CLK_COR_SEQ_1_3_0_BINARY, + CLK_COR_SEQ_1_3_1 => CLK_COR_SEQ_1_3_1_BINARY, + CLK_COR_SEQ_1_4_0 => CLK_COR_SEQ_1_4_0_BINARY, + CLK_COR_SEQ_1_4_1 => CLK_COR_SEQ_1_4_1_BINARY, + CLK_COR_SEQ_1_ENABLE_0 => CLK_COR_SEQ_1_ENABLE_0_BINARY, + CLK_COR_SEQ_1_ENABLE_1 => CLK_COR_SEQ_1_ENABLE_1_BINARY, + CLK_COR_SEQ_2_1_0 => CLK_COR_SEQ_2_1_0_BINARY, + CLK_COR_SEQ_2_1_1 => CLK_COR_SEQ_2_1_1_BINARY, + CLK_COR_SEQ_2_2_0 => CLK_COR_SEQ_2_2_0_BINARY, + CLK_COR_SEQ_2_2_1 => CLK_COR_SEQ_2_2_1_BINARY, + CLK_COR_SEQ_2_3_0 => CLK_COR_SEQ_2_3_0_BINARY, + CLK_COR_SEQ_2_3_1 => CLK_COR_SEQ_2_3_1_BINARY, + CLK_COR_SEQ_2_4_0 => CLK_COR_SEQ_2_4_0_BINARY, + CLK_COR_SEQ_2_4_1 => CLK_COR_SEQ_2_4_1_BINARY, + CLK_COR_SEQ_2_ENABLE_0 => CLK_COR_SEQ_2_ENABLE_0_BINARY, + CLK_COR_SEQ_2_ENABLE_1 => CLK_COR_SEQ_2_ENABLE_1_BINARY, + CLK_COR_SEQ_2_USE_0 => CLK_COR_SEQ_2_USE_0_BINARY, + CLK_COR_SEQ_2_USE_1 => CLK_COR_SEQ_2_USE_1_BINARY, + CM_TRIM_0 => CM_TRIM_0_BINARY, + CM_TRIM_1 => CM_TRIM_1_BINARY, + COMMA_10B_ENABLE_0 => COMMA_10B_ENABLE_0_BINARY, + COMMA_10B_ENABLE_1 => COMMA_10B_ENABLE_1_BINARY, + COMMA_DOUBLE_0 => COMMA_DOUBLE_0_BINARY, + COMMA_DOUBLE_1 => COMMA_DOUBLE_1_BINARY, + COM_BURST_VAL_0 => COM_BURST_VAL_0_BINARY, + COM_BURST_VAL_1 => COM_BURST_VAL_1_BINARY, + DEC_MCOMMA_DETECT_0 => DEC_MCOMMA_DETECT_0_BINARY, + DEC_MCOMMA_DETECT_1 => DEC_MCOMMA_DETECT_1_BINARY, + DEC_PCOMMA_DETECT_0 => DEC_PCOMMA_DETECT_0_BINARY, + DEC_PCOMMA_DETECT_1 => DEC_PCOMMA_DETECT_1_BINARY, + DEC_VALID_COMMA_ONLY_0 => DEC_VALID_COMMA_ONLY_0_BINARY, + DEC_VALID_COMMA_ONLY_1 => DEC_VALID_COMMA_ONLY_1_BINARY, + DFE_CAL_TIME => DFE_CAL_TIME_BINARY, + DFE_CFG_0 => DFE_CFG_0_BINARY, + DFE_CFG_1 => DFE_CFG_1_BINARY, + GEARBOX_ENDEC_0 => GEARBOX_ENDEC_0_BINARY, + GEARBOX_ENDEC_1 => GEARBOX_ENDEC_1_BINARY, + MCOMMA_10B_VALUE_0 => MCOMMA_10B_VALUE_0_BINARY, + MCOMMA_10B_VALUE_1 => MCOMMA_10B_VALUE_1_BINARY, + MCOMMA_DETECT_0 => MCOMMA_DETECT_0_BINARY, + MCOMMA_DETECT_1 => MCOMMA_DETECT_1_BINARY, + OOBDETECT_THRESHOLD_0 => OOBDETECT_THRESHOLD_0_BINARY, + OOBDETECT_THRESHOLD_1 => OOBDETECT_THRESHOLD_1_BINARY, + OOB_CLK_DIVIDER => OOB_CLK_DIVIDER_BINARY, + OVERSAMPLE_MODE => OVERSAMPLE_MODE_BINARY, + PCI_EXPRESS_MODE_0 => PCI_EXPRESS_MODE_0_BINARY, + PCI_EXPRESS_MODE_1 => PCI_EXPRESS_MODE_1_BINARY, + PCOMMA_10B_VALUE_0 => PCOMMA_10B_VALUE_0_BINARY, + PCOMMA_10B_VALUE_1 => PCOMMA_10B_VALUE_1_BINARY, + PCOMMA_DETECT_0 => PCOMMA_DETECT_0_BINARY, + PCOMMA_DETECT_1 => PCOMMA_DETECT_1_BINARY, + PLL_COM_CFG => PLL_COM_CFG_BINARY, + PLL_CP_CFG => PLL_CP_CFG_BINARY, + PLL_DIVSEL_FB => PLL_DIVSEL_FB_BINARY, + PLL_DIVSEL_REF => PLL_DIVSEL_REF_BINARY, + PLL_FB_DCCEN => PLL_FB_DCCEN_BINARY, + PLL_LKDET_CFG => PLL_LKDET_CFG_BINARY, + PLL_RXDIVSEL_OUT_0 => PLL_RXDIVSEL_OUT_0_BINARY, + PLL_RXDIVSEL_OUT_1 => PLL_RXDIVSEL_OUT_1_BINARY, + PLL_SATA_0 => PLL_SATA_0_BINARY, + PLL_SATA_1 => PLL_SATA_1_BINARY, + PLL_TDCC_CFG => PLL_TDCC_CFG_BINARY, + PLL_TXDIVSEL_OUT_0 => PLL_TXDIVSEL_OUT_0_BINARY, + PLL_TXDIVSEL_OUT_1 => PLL_TXDIVSEL_OUT_1_BINARY, + PMA_CDR_SCAN_0 => PMA_CDR_SCAN_0_BINARY, + PMA_CDR_SCAN_1 => PMA_CDR_SCAN_1_BINARY, + PMA_COM_CFG => PMA_COM_CFG_BINARY, + PMA_RXSYNC_CFG_0 => PMA_RXSYNC_CFG_0_BINARY, + PMA_RXSYNC_CFG_1 => PMA_RXSYNC_CFG_1_BINARY, + PMA_RX_CFG_0 => PMA_RX_CFG_0_BINARY, + PMA_RX_CFG_1 => PMA_RX_CFG_1_BINARY, + PMA_TX_CFG_0 => PMA_TX_CFG_0_BINARY, + PMA_TX_CFG_1 => PMA_TX_CFG_1_BINARY, + PRBS_ERR_THRESHOLD_0 => PRBS_ERR_THRESHOLD_0_BINARY, + PRBS_ERR_THRESHOLD_1 => PRBS_ERR_THRESHOLD_1_BINARY, + RCV_TERM_GND_0 => RCV_TERM_GND_0_BINARY, + RCV_TERM_GND_1 => RCV_TERM_GND_1_BINARY, + RCV_TERM_VTTRX_0 => RCV_TERM_VTTRX_0_BINARY, + RCV_TERM_VTTRX_1 => RCV_TERM_VTTRX_1_BINARY, + RXGEARBOX_USE_0 => RXGEARBOX_USE_0_BINARY, + RXGEARBOX_USE_1 => RXGEARBOX_USE_1_BINARY, + RX_BUFFER_USE_0 => RX_BUFFER_USE_0_BINARY, + RX_BUFFER_USE_1 => RX_BUFFER_USE_1_BINARY, + RX_DECODE_SEQ_MATCH_0 => RX_DECODE_SEQ_MATCH_0_BINARY, + RX_DECODE_SEQ_MATCH_1 => RX_DECODE_SEQ_MATCH_1_BINARY, + RX_EN_IDLE_HOLD_CDR => RX_EN_IDLE_HOLD_CDR_BINARY, + RX_EN_IDLE_HOLD_DFE_0 => RX_EN_IDLE_HOLD_DFE_0_BINARY, + RX_EN_IDLE_HOLD_DFE_1 => RX_EN_IDLE_HOLD_DFE_1_BINARY, + RX_EN_IDLE_RESET_BUF_0 => RX_EN_IDLE_RESET_BUF_0_BINARY, + RX_EN_IDLE_RESET_BUF_1 => RX_EN_IDLE_RESET_BUF_1_BINARY, + RX_EN_IDLE_RESET_FR => RX_EN_IDLE_RESET_FR_BINARY, + RX_EN_IDLE_RESET_PH => RX_EN_IDLE_RESET_PH_BINARY, + RX_IDLE_HI_CNT_0 => RX_IDLE_HI_CNT_0_BINARY, + RX_IDLE_HI_CNT_1 => RX_IDLE_HI_CNT_1_BINARY, + RX_IDLE_LO_CNT_0 => RX_IDLE_LO_CNT_0_BINARY, + RX_IDLE_LO_CNT_1 => RX_IDLE_LO_CNT_1_BINARY, + RX_LOSS_OF_SYNC_FSM_0 => RX_LOSS_OF_SYNC_FSM_0_BINARY, + RX_LOSS_OF_SYNC_FSM_1 => RX_LOSS_OF_SYNC_FSM_1_BINARY, + RX_LOS_INVALID_INCR_0 => RX_LOS_INVALID_INCR_0_BINARY, + RX_LOS_INVALID_INCR_1 => RX_LOS_INVALID_INCR_1_BINARY, + RX_LOS_THRESHOLD_0 => RX_LOS_THRESHOLD_0_BINARY, + RX_LOS_THRESHOLD_1 => RX_LOS_THRESHOLD_1_BINARY, + RX_SLIDE_MODE_0 => RX_SLIDE_MODE_0_BINARY, + RX_SLIDE_MODE_1 => RX_SLIDE_MODE_1_BINARY, + RX_STATUS_FMT_0 => RX_STATUS_FMT_0_BINARY, + RX_STATUS_FMT_1 => RX_STATUS_FMT_1_BINARY, + RX_XCLK_SEL_0 => RX_XCLK_SEL_0_BINARY, + RX_XCLK_SEL_1 => RX_XCLK_SEL_1_BINARY, + SATA_BURST_VAL_0 => SATA_BURST_VAL_0_BINARY, + SATA_BURST_VAL_1 => SATA_BURST_VAL_1_BINARY, + SATA_IDLE_VAL_0 => SATA_IDLE_VAL_0_BINARY, + SATA_IDLE_VAL_1 => SATA_IDLE_VAL_1_BINARY, + SATA_MAX_BURST_0 => SATA_MAX_BURST_0_BINARY, + SATA_MAX_BURST_1 => SATA_MAX_BURST_1_BINARY, + SATA_MAX_INIT_0 => SATA_MAX_INIT_0_BINARY, + SATA_MAX_INIT_1 => SATA_MAX_INIT_1_BINARY, + SATA_MAX_WAKE_0 => SATA_MAX_WAKE_0_BINARY, + SATA_MAX_WAKE_1 => SATA_MAX_WAKE_1_BINARY, + SATA_MIN_BURST_0 => SATA_MIN_BURST_0_BINARY, + SATA_MIN_BURST_1 => SATA_MIN_BURST_1_BINARY, + SATA_MIN_INIT_0 => SATA_MIN_INIT_0_BINARY, + SATA_MIN_INIT_1 => SATA_MIN_INIT_1_BINARY, + SATA_MIN_WAKE_0 => SATA_MIN_WAKE_0_BINARY, + SATA_MIN_WAKE_1 => SATA_MIN_WAKE_1_BINARY, + SIM_GTXRESET_SPEEDUP => SIM_GTXRESET_SPEEDUP_BINARY, + SIM_PLL_PERDIV2 => SIM_PLL_PERDIV2_BINARY, + SIM_RECEIVER_DETECT_PASS_0 => SIM_RECEIVER_DETECT_PASS_0_BINARY, + SIM_RECEIVER_DETECT_PASS_1 => SIM_RECEIVER_DETECT_PASS_1_BINARY, + TERMINATION_CTRL => TERMINATION_CTRL_BINARY, + TERMINATION_IMP_0 => TERMINATION_IMP_0_BINARY, + TERMINATION_IMP_1 => TERMINATION_IMP_1_BINARY, + TERMINATION_OVRD => TERMINATION_OVRD_BINARY, + TRANS_TIME_FROM_P2_0 => TRANS_TIME_FROM_P2_0_BINARY, + TRANS_TIME_FROM_P2_1 => TRANS_TIME_FROM_P2_1_BINARY, + TRANS_TIME_NON_P2_0 => TRANS_TIME_NON_P2_0_BINARY, + TRANS_TIME_NON_P2_1 => TRANS_TIME_NON_P2_1_BINARY, + TRANS_TIME_TO_P2_0 => TRANS_TIME_TO_P2_0_BINARY, + TRANS_TIME_TO_P2_1 => TRANS_TIME_TO_P2_1_BINARY, + TXGEARBOX_USE_0 => TXGEARBOX_USE_0_BINARY, + TXGEARBOX_USE_1 => TXGEARBOX_USE_1_BINARY, + TXRX_INVERT_0 => TXRX_INVERT_0_BINARY, + TXRX_INVERT_1 => TXRX_INVERT_1_BINARY, + TX_BUFFER_USE_0 => TX_BUFFER_USE_0_BINARY, + TX_BUFFER_USE_1 => TX_BUFFER_USE_1_BINARY, + TX_DETECT_RX_CFG_0 => TX_DETECT_RX_CFG_0_BINARY, + TX_DETECT_RX_CFG_1 => TX_DETECT_RX_CFG_1_BINARY, + TX_IDLE_DELAY_0 => TX_IDLE_DELAY_0_BINARY, + TX_IDLE_DELAY_1 => TX_IDLE_DELAY_1_BINARY, + TX_XCLK_SEL_0 => TX_XCLK_SEL_0_BINARY, + TX_XCLK_SEL_1 => TX_XCLK_SEL_1_BINARY, + + DFECLKDLYADJMONITOR0 => DFECLKDLYADJMONITOR0_outdelay, + DFECLKDLYADJMONITOR1 => DFECLKDLYADJMONITOR1_outdelay, + DFEEYEDACMONITOR0 => DFEEYEDACMONITOR0_outdelay, + DFEEYEDACMONITOR1 => DFEEYEDACMONITOR1_outdelay, + DFESENSCAL0 => DFESENSCAL0_outdelay, + DFESENSCAL1 => DFESENSCAL1_outdelay, + DFETAP1MONITOR0 => DFETAP1MONITOR0_outdelay, + DFETAP1MONITOR1 => DFETAP1MONITOR1_outdelay, + DFETAP2MONITOR0 => DFETAP2MONITOR0_outdelay, + DFETAP2MONITOR1 => DFETAP2MONITOR1_outdelay, + DFETAP3MONITOR0 => DFETAP3MONITOR0_outdelay, + DFETAP3MONITOR1 => DFETAP3MONITOR1_outdelay, + DFETAP4MONITOR0 => DFETAP4MONITOR0_outdelay, + DFETAP4MONITOR1 => DFETAP4MONITOR1_outdelay, + DO => DO_outdelay, + DRDY => DRDY_outdelay, + PHYSTATUS0 => PHYSTATUS0_outdelay, + PHYSTATUS1 => PHYSTATUS1_outdelay, + PLLLKDET => PLLLKDET_outdelay, + REFCLKOUT => REFCLKOUT_outdelay, + RESETDONE0 => RESETDONE0_outdelay, + RESETDONE1 => RESETDONE1_outdelay, + RXBUFSTATUS0 => RXBUFSTATUS0_outdelay, + RXBUFSTATUS1 => RXBUFSTATUS1_outdelay, + RXBYTEISALIGNED0 => RXBYTEISALIGNED0_outdelay, + RXBYTEISALIGNED1 => RXBYTEISALIGNED1_outdelay, + RXBYTEREALIGN0 => RXBYTEREALIGN0_outdelay, + RXBYTEREALIGN1 => RXBYTEREALIGN1_outdelay, + RXCHANBONDSEQ0 => RXCHANBONDSEQ0_outdelay, + RXCHANBONDSEQ1 => RXCHANBONDSEQ1_outdelay, + RXCHANISALIGNED0 => RXCHANISALIGNED0_outdelay, + RXCHANISALIGNED1 => RXCHANISALIGNED1_outdelay, + RXCHANREALIGN0 => RXCHANREALIGN0_outdelay, + RXCHANREALIGN1 => RXCHANREALIGN1_outdelay, + RXCHARISCOMMA0 => RXCHARISCOMMA0_outdelay, + RXCHARISCOMMA1 => RXCHARISCOMMA1_outdelay, + RXCHARISK0 => RXCHARISK0_outdelay, + RXCHARISK1 => RXCHARISK1_outdelay, + RXCHBONDO0 => RXCHBONDO0_outdelay, + RXCHBONDO1 => RXCHBONDO1_outdelay, + RXCLKCORCNT0 => RXCLKCORCNT0_outdelay, + RXCLKCORCNT1 => RXCLKCORCNT1_outdelay, + RXCOMMADET0 => RXCOMMADET0_outdelay, + RXCOMMADET1 => RXCOMMADET1_outdelay, + RXDATA0 => RXDATA0_outdelay, + RXDATA1 => RXDATA1_outdelay, + RXDATAVALID0 => RXDATAVALID0_outdelay, + RXDATAVALID1 => RXDATAVALID1_outdelay, + RXDISPERR0 => RXDISPERR0_outdelay, + RXDISPERR1 => RXDISPERR1_outdelay, + RXELECIDLE0 => RXELECIDLE0_outdelay, + RXELECIDLE1 => RXELECIDLE1_outdelay, + RXHEADER0 => RXHEADER0_outdelay, + RXHEADER1 => RXHEADER1_outdelay, + RXHEADERVALID0 => RXHEADERVALID0_outdelay, + RXHEADERVALID1 => RXHEADERVALID1_outdelay, + RXLOSSOFSYNC0 => RXLOSSOFSYNC0_outdelay, + RXLOSSOFSYNC1 => RXLOSSOFSYNC1_outdelay, + RXNOTINTABLE0 => RXNOTINTABLE0_outdelay, + RXNOTINTABLE1 => RXNOTINTABLE1_outdelay, + RXOVERSAMPLEERR0 => RXOVERSAMPLEERR0_outdelay, + RXOVERSAMPLEERR1 => RXOVERSAMPLEERR1_outdelay, + RXPRBSERR0 => RXPRBSERR0_outdelay, + RXPRBSERR1 => RXPRBSERR1_outdelay, + RXRECCLK0 => RXRECCLK0_outdelay, + RXRECCLK1 => RXRECCLK1_outdelay, + RXRUNDISP0 => RXRUNDISP0_outdelay, + RXRUNDISP1 => RXRUNDISP1_outdelay, + RXSTARTOFSEQ0 => RXSTARTOFSEQ0_outdelay, + RXSTARTOFSEQ1 => RXSTARTOFSEQ1_outdelay, + RXSTATUS0 => RXSTATUS0_outdelay, + RXSTATUS1 => RXSTATUS1_outdelay, + RXVALID0 => RXVALID0_outdelay, + RXVALID1 => RXVALID1_outdelay, + TXBUFSTATUS0 => TXBUFSTATUS0_outdelay, + TXBUFSTATUS1 => TXBUFSTATUS1_outdelay, + TXGEARBOXREADY0 => TXGEARBOXREADY0_outdelay, + TXGEARBOXREADY1 => TXGEARBOXREADY1_outdelay, + TXKERR0 => TXKERR0_outdelay, + TXKERR1 => TXKERR1_outdelay, + TXN0 => TXN0_outdelay, + TXN1 => TXN1_outdelay, + TXOUTCLK0 => TXOUTCLK0_outdelay, + TXOUTCLK1 => TXOUTCLK1_outdelay, + TXP0 => TXP0_outdelay, + TXP1 => TXP1_outdelay, + TXRUNDISP0 => TXRUNDISP0_outdelay, + TXRUNDISP1 => TXRUNDISP1_outdelay, + + CLKIN => CLKIN_indelay, + DADDR => DADDR_indelay, + DCLK => DCLK_indelay, + DEN => DEN_indelay, + DFECLKDLYADJ0 => DFECLKDLYADJ0_indelay, + DFECLKDLYADJ1 => DFECLKDLYADJ1_indelay, + DFETAP10 => DFETAP10_indelay, + DFETAP11 => DFETAP11_indelay, + DFETAP20 => DFETAP20_indelay, + DFETAP21 => DFETAP21_indelay, + DFETAP30 => DFETAP30_indelay, + DFETAP31 => DFETAP31_indelay, + DFETAP40 => DFETAP40_indelay, + DFETAP41 => DFETAP41_indelay, + DI => DI_indelay, + DWE => DWE_indelay, + GSR => GSR, + GTXRESET => GTXRESET_indelay, + GTXTEST => GTXTEST_indelay, + INTDATAWIDTH => INTDATAWIDTH_indelay, + LOOPBACK0 => LOOPBACK0_indelay, + LOOPBACK1 => LOOPBACK1_indelay, + PLLLKDETEN => PLLLKDETEN_indelay, + PLLPOWERDOWN => PLLPOWERDOWN_indelay, + PRBSCNTRESET0 => PRBSCNTRESET0_indelay, + PRBSCNTRESET1 => PRBSCNTRESET1_indelay, + REFCLKPWRDNB => REFCLKPWRDNB_indelay, + RXBUFRESET0 => RXBUFRESET0_indelay, + RXBUFRESET1 => RXBUFRESET1_indelay, + RXCDRRESET0 => RXCDRRESET0_indelay, + RXCDRRESET1 => RXCDRRESET1_indelay, + RXCHBONDI0 => RXCHBONDI0_indelay, + RXCHBONDI1 => RXCHBONDI1_indelay, + RXCOMMADETUSE0 => RXCOMMADETUSE0_indelay, + RXCOMMADETUSE1 => RXCOMMADETUSE1_indelay, + RXDATAWIDTH0 => RXDATAWIDTH0_indelay, + RXDATAWIDTH1 => RXDATAWIDTH1_indelay, + RXDEC8B10BUSE0 => RXDEC8B10BUSE0_indelay, + RXDEC8B10BUSE1 => RXDEC8B10BUSE1_indelay, + RXENCHANSYNC0 => RXENCHANSYNC0_indelay, + RXENCHANSYNC1 => RXENCHANSYNC1_indelay, + RXENEQB0 => RXENEQB0_indelay, + RXENEQB1 => RXENEQB1_indelay, + RXENMCOMMAALIGN0 => RXENMCOMMAALIGN0_indelay, + RXENMCOMMAALIGN1 => RXENMCOMMAALIGN1_indelay, + RXENPCOMMAALIGN0 => RXENPCOMMAALIGN0_indelay, + RXENPCOMMAALIGN1 => RXENPCOMMAALIGN1_indelay, + RXENPMAPHASEALIGN0 => RXENPMAPHASEALIGN0_indelay, + RXENPMAPHASEALIGN1 => RXENPMAPHASEALIGN1_indelay, + RXENPRBSTST0 => RXENPRBSTST0_indelay, + RXENPRBSTST1 => RXENPRBSTST1_indelay, + RXENSAMPLEALIGN0 => RXENSAMPLEALIGN0_indelay, + RXENSAMPLEALIGN1 => RXENSAMPLEALIGN1_indelay, + RXEQMIX0 => RXEQMIX0_indelay, + RXEQMIX1 => RXEQMIX1_indelay, + RXEQPOLE0 => RXEQPOLE0_indelay, + RXEQPOLE1 => RXEQPOLE1_indelay, + RXGEARBOXSLIP0 => RXGEARBOXSLIP0_indelay, + RXGEARBOXSLIP1 => RXGEARBOXSLIP1_indelay, + RXN0 => RXN0_indelay, + RXN1 => RXN1_indelay, + RXP0 => RXP0_indelay, + RXP1 => RXP1_indelay, + RXPMASETPHASE0 => RXPMASETPHASE0_indelay, + RXPMASETPHASE1 => RXPMASETPHASE1_indelay, + RXPOLARITY0 => RXPOLARITY0_indelay, + RXPOLARITY1 => RXPOLARITY1_indelay, + RXPOWERDOWN0 => RXPOWERDOWN0_indelay, + RXPOWERDOWN1 => RXPOWERDOWN1_indelay, + RXRESET0 => RXRESET0_indelay, + RXRESET1 => RXRESET1_indelay, + RXSLIDE0 => RXSLIDE0_indelay, + RXSLIDE1 => RXSLIDE1_indelay, + RXUSRCLK0 => RXUSRCLK0_indelay, + RXUSRCLK1 => RXUSRCLK1_indelay, + RXUSRCLK20 => RXUSRCLK20_indelay, + RXUSRCLK21 => RXUSRCLK21_indelay, + TXBUFDIFFCTRL0 => TXBUFDIFFCTRL0_indelay, + TXBUFDIFFCTRL1 => TXBUFDIFFCTRL1_indelay, + TXBYPASS8B10B0 => TXBYPASS8B10B0_indelay, + TXBYPASS8B10B1 => TXBYPASS8B10B1_indelay, + TXCHARDISPMODE0 => TXCHARDISPMODE0_indelay, + TXCHARDISPMODE1 => TXCHARDISPMODE1_indelay, + TXCHARDISPVAL0 => TXCHARDISPVAL0_indelay, + TXCHARDISPVAL1 => TXCHARDISPVAL1_indelay, + TXCHARISK0 => TXCHARISK0_indelay, + TXCHARISK1 => TXCHARISK1_indelay, + TXCOMSTART0 => TXCOMSTART0_indelay, + TXCOMSTART1 => TXCOMSTART1_indelay, + TXCOMTYPE0 => TXCOMTYPE0_indelay, + TXCOMTYPE1 => TXCOMTYPE1_indelay, + TXDATA0 => TXDATA0_indelay, + TXDATA1 => TXDATA1_indelay, + TXDATAWIDTH0 => TXDATAWIDTH0_indelay, + TXDATAWIDTH1 => TXDATAWIDTH1_indelay, + TXDETECTRX0 => TXDETECTRX0_indelay, + TXDETECTRX1 => TXDETECTRX1_indelay, + TXDIFFCTRL0 => TXDIFFCTRL0_indelay, + TXDIFFCTRL1 => TXDIFFCTRL1_indelay, + TXELECIDLE0 => TXELECIDLE0_indelay, + TXELECIDLE1 => TXELECIDLE1_indelay, + TXENC8B10BUSE0 => TXENC8B10BUSE0_indelay, + TXENC8B10BUSE1 => TXENC8B10BUSE1_indelay, + TXENPMAPHASEALIGN0 => TXENPMAPHASEALIGN0_indelay, + TXENPMAPHASEALIGN1 => TXENPMAPHASEALIGN1_indelay, + TXENPRBSTST0 => TXENPRBSTST0_indelay, + TXENPRBSTST1 => TXENPRBSTST1_indelay, + TXHEADER0 => TXHEADER0_indelay, + TXHEADER1 => TXHEADER1_indelay, + TXINHIBIT0 => TXINHIBIT0_indelay, + TXINHIBIT1 => TXINHIBIT1_indelay, + TXPMASETPHASE0 => TXPMASETPHASE0_indelay, + TXPMASETPHASE1 => TXPMASETPHASE1_indelay, + TXPOLARITY0 => TXPOLARITY0_indelay, + TXPOLARITY1 => TXPOLARITY1_indelay, + TXPOWERDOWN0 => TXPOWERDOWN0_indelay, + TXPOWERDOWN1 => TXPOWERDOWN1_indelay, + TXPREEMPHASIS0 => TXPREEMPHASIS0_indelay, + TXPREEMPHASIS1 => TXPREEMPHASIS1_indelay, + TXRESET0 => TXRESET0_indelay, + TXRESET1 => TXRESET1_indelay, + TXSEQUENCE0 => TXSEQUENCE0_indelay, + TXSEQUENCE1 => TXSEQUENCE1_indelay, + TXSTARTSEQ0 => TXSTARTSEQ0_indelay, + TXSTARTSEQ1 => TXSTARTSEQ1_indelay, + TXUSRCLK0 => TXUSRCLK0_indelay, + TXUSRCLK1 => TXUSRCLK1_indelay, + TXUSRCLK20 => TXUSRCLK20_indelay, + TXUSRCLK21 => TXUSRCLK21_indelay + ); + end generate legacy_model; + + fast_model: if SIM_MODE = "FAST" generate + gtx_dual_fast_bw_1 : GTX_DUAL_FAST_BUS + port map ( + STEPPING => STEPPING_BINARY, + AC_CAP_DIS_0 => AC_CAP_DIS_0_BINARY, + AC_CAP_DIS_1 => AC_CAP_DIS_1_BINARY, + ALIGN_COMMA_WORD_0 => ALIGN_COMMA_WORD_0_BINARY, + ALIGN_COMMA_WORD_1 => ALIGN_COMMA_WORD_1_BINARY, + CB2_INH_CC_PERIOD_0 => CB2_INH_CC_PERIOD_0_BINARY, + CB2_INH_CC_PERIOD_1 => CB2_INH_CC_PERIOD_1_BINARY, + CDR_PH_ADJ_TIME => CDR_PH_ADJ_TIME_BINARY, + CHAN_BOND_1_MAX_SKEW_0 => CHAN_BOND_1_MAX_SKEW_0_BINARY, + CHAN_BOND_1_MAX_SKEW_1 => CHAN_BOND_1_MAX_SKEW_1_BINARY, + CHAN_BOND_2_MAX_SKEW_0 => CHAN_BOND_2_MAX_SKEW_0_BINARY, + CHAN_BOND_2_MAX_SKEW_1 => CHAN_BOND_2_MAX_SKEW_1_BINARY, + CHAN_BOND_KEEP_ALIGN_0 => CHAN_BOND_KEEP_ALIGN_0_BINARY, + CHAN_BOND_KEEP_ALIGN_1 => CHAN_BOND_KEEP_ALIGN_1_BINARY, + CHAN_BOND_LEVEL_0 => CHAN_BOND_LEVEL_0_BINARY, + CHAN_BOND_LEVEL_1 => CHAN_BOND_LEVEL_1_BINARY, + CHAN_BOND_MODE_0 => CHAN_BOND_MODE_0_BINARY, + CHAN_BOND_MODE_1 => CHAN_BOND_MODE_1_BINARY, + CHAN_BOND_SEQ_1_1_0 => CHAN_BOND_SEQ_1_1_0_BINARY, + CHAN_BOND_SEQ_1_1_1 => CHAN_BOND_SEQ_1_1_1_BINARY, + CHAN_BOND_SEQ_1_2_0 => CHAN_BOND_SEQ_1_2_0_BINARY, + CHAN_BOND_SEQ_1_2_1 => CHAN_BOND_SEQ_1_2_1_BINARY, + CHAN_BOND_SEQ_1_3_0 => CHAN_BOND_SEQ_1_3_0_BINARY, + CHAN_BOND_SEQ_1_3_1 => CHAN_BOND_SEQ_1_3_1_BINARY, + CHAN_BOND_SEQ_1_4_0 => CHAN_BOND_SEQ_1_4_0_BINARY, + CHAN_BOND_SEQ_1_4_1 => CHAN_BOND_SEQ_1_4_1_BINARY, + CHAN_BOND_SEQ_1_ENABLE_0 => CHAN_BOND_SEQ_1_ENABLE_0_BINARY, + CHAN_BOND_SEQ_1_ENABLE_1 => CHAN_BOND_SEQ_1_ENABLE_1_BINARY, + CHAN_BOND_SEQ_2_1_0 => CHAN_BOND_SEQ_2_1_0_BINARY, + CHAN_BOND_SEQ_2_1_1 => CHAN_BOND_SEQ_2_1_1_BINARY, + CHAN_BOND_SEQ_2_2_0 => CHAN_BOND_SEQ_2_2_0_BINARY, + CHAN_BOND_SEQ_2_2_1 => CHAN_BOND_SEQ_2_2_1_BINARY, + CHAN_BOND_SEQ_2_3_0 => CHAN_BOND_SEQ_2_3_0_BINARY, + CHAN_BOND_SEQ_2_3_1 => CHAN_BOND_SEQ_2_3_1_BINARY, + CHAN_BOND_SEQ_2_4_0 => CHAN_BOND_SEQ_2_4_0_BINARY, + CHAN_BOND_SEQ_2_4_1 => CHAN_BOND_SEQ_2_4_1_BINARY, + CHAN_BOND_SEQ_2_ENABLE_0 => CHAN_BOND_SEQ_2_ENABLE_0_BINARY, + CHAN_BOND_SEQ_2_ENABLE_1 => CHAN_BOND_SEQ_2_ENABLE_1_BINARY, + CHAN_BOND_SEQ_2_USE_0 => CHAN_BOND_SEQ_2_USE_0_BINARY, + CHAN_BOND_SEQ_2_USE_1 => CHAN_BOND_SEQ_2_USE_1_BINARY, + CHAN_BOND_SEQ_LEN_0 => CHAN_BOND_SEQ_LEN_0_BINARY, + CHAN_BOND_SEQ_LEN_1 => CHAN_BOND_SEQ_LEN_1_BINARY, + CLK25_DIVIDER => CLK25_DIVIDER_BINARY, + CLKINDC_B => CLKINDC_B_BINARY, + CLKRCV_TRST => CLKRCV_TRST_BINARY, + CLK_CORRECT_USE_0 => CLK_CORRECT_USE_0_BINARY, + CLK_CORRECT_USE_1 => CLK_CORRECT_USE_1_BINARY, + CLK_COR_ADJ_LEN_0 => CLK_COR_ADJ_LEN_0_BINARY, + CLK_COR_ADJ_LEN_1 => CLK_COR_ADJ_LEN_1_BINARY, + CLK_COR_DET_LEN_0 => CLK_COR_DET_LEN_0_BINARY, + CLK_COR_DET_LEN_1 => CLK_COR_DET_LEN_1_BINARY, + CLK_COR_INSERT_IDLE_FLAG_0 => CLK_COR_INSERT_IDLE_FLAG_0_BINARY, + CLK_COR_INSERT_IDLE_FLAG_1 => CLK_COR_INSERT_IDLE_FLAG_1_BINARY, + CLK_COR_KEEP_IDLE_0 => CLK_COR_KEEP_IDLE_0_BINARY, + CLK_COR_KEEP_IDLE_1 => CLK_COR_KEEP_IDLE_1_BINARY, + CLK_COR_MAX_LAT_0 => CLK_COR_MAX_LAT_0_BINARY, + CLK_COR_MAX_LAT_1 => CLK_COR_MAX_LAT_1_BINARY, + CLK_COR_MIN_LAT_0 => CLK_COR_MIN_LAT_0_BINARY, + CLK_COR_MIN_LAT_1 => CLK_COR_MIN_LAT_1_BINARY, + CLK_COR_PRECEDENCE_0 => CLK_COR_PRECEDENCE_0_BINARY, + CLK_COR_PRECEDENCE_1 => CLK_COR_PRECEDENCE_1_BINARY, + CLK_COR_REPEAT_WAIT_0 => CLK_COR_REPEAT_WAIT_0_BINARY, + CLK_COR_REPEAT_WAIT_1 => CLK_COR_REPEAT_WAIT_1_BINARY, + CLK_COR_SEQ_1_1_0 => CLK_COR_SEQ_1_1_0_BINARY, + CLK_COR_SEQ_1_1_1 => CLK_COR_SEQ_1_1_1_BINARY, + CLK_COR_SEQ_1_2_0 => CLK_COR_SEQ_1_2_0_BINARY, + CLK_COR_SEQ_1_2_1 => CLK_COR_SEQ_1_2_1_BINARY, + CLK_COR_SEQ_1_3_0 => CLK_COR_SEQ_1_3_0_BINARY, + CLK_COR_SEQ_1_3_1 => CLK_COR_SEQ_1_3_1_BINARY, + CLK_COR_SEQ_1_4_0 => CLK_COR_SEQ_1_4_0_BINARY, + CLK_COR_SEQ_1_4_1 => CLK_COR_SEQ_1_4_1_BINARY, + CLK_COR_SEQ_1_ENABLE_0 => CLK_COR_SEQ_1_ENABLE_0_BINARY, + CLK_COR_SEQ_1_ENABLE_1 => CLK_COR_SEQ_1_ENABLE_1_BINARY, + CLK_COR_SEQ_2_1_0 => CLK_COR_SEQ_2_1_0_BINARY, + CLK_COR_SEQ_2_1_1 => CLK_COR_SEQ_2_1_1_BINARY, + CLK_COR_SEQ_2_2_0 => CLK_COR_SEQ_2_2_0_BINARY, + CLK_COR_SEQ_2_2_1 => CLK_COR_SEQ_2_2_1_BINARY, + CLK_COR_SEQ_2_3_0 => CLK_COR_SEQ_2_3_0_BINARY, + CLK_COR_SEQ_2_3_1 => CLK_COR_SEQ_2_3_1_BINARY, + CLK_COR_SEQ_2_4_0 => CLK_COR_SEQ_2_4_0_BINARY, + CLK_COR_SEQ_2_4_1 => CLK_COR_SEQ_2_4_1_BINARY, + CLK_COR_SEQ_2_ENABLE_0 => CLK_COR_SEQ_2_ENABLE_0_BINARY, + CLK_COR_SEQ_2_ENABLE_1 => CLK_COR_SEQ_2_ENABLE_1_BINARY, + CLK_COR_SEQ_2_USE_0 => CLK_COR_SEQ_2_USE_0_BINARY, + CLK_COR_SEQ_2_USE_1 => CLK_COR_SEQ_2_USE_1_BINARY, + CM_TRIM_0 => CM_TRIM_0_BINARY, + CM_TRIM_1 => CM_TRIM_1_BINARY, + COMMA_10B_ENABLE_0 => COMMA_10B_ENABLE_0_BINARY, + COMMA_10B_ENABLE_1 => COMMA_10B_ENABLE_1_BINARY, + COMMA_DOUBLE_0 => COMMA_DOUBLE_0_BINARY, + COMMA_DOUBLE_1 => COMMA_DOUBLE_1_BINARY, + COM_BURST_VAL_0 => COM_BURST_VAL_0_BINARY, + COM_BURST_VAL_1 => COM_BURST_VAL_1_BINARY, + DEC_MCOMMA_DETECT_0 => DEC_MCOMMA_DETECT_0_BINARY, + DEC_MCOMMA_DETECT_1 => DEC_MCOMMA_DETECT_1_BINARY, + DEC_PCOMMA_DETECT_0 => DEC_PCOMMA_DETECT_0_BINARY, + DEC_PCOMMA_DETECT_1 => DEC_PCOMMA_DETECT_1_BINARY, + DEC_VALID_COMMA_ONLY_0 => DEC_VALID_COMMA_ONLY_0_BINARY, + DEC_VALID_COMMA_ONLY_1 => DEC_VALID_COMMA_ONLY_1_BINARY, + DFE_CAL_TIME => DFE_CAL_TIME_BINARY, + DFE_CFG_0 => DFE_CFG_0_BINARY, + DFE_CFG_1 => DFE_CFG_1_BINARY, + GEARBOX_ENDEC_0 => GEARBOX_ENDEC_0_BINARY, + GEARBOX_ENDEC_1 => GEARBOX_ENDEC_1_BINARY, + MCOMMA_10B_VALUE_0 => MCOMMA_10B_VALUE_0_BINARY, + MCOMMA_10B_VALUE_1 => MCOMMA_10B_VALUE_1_BINARY, + MCOMMA_DETECT_0 => MCOMMA_DETECT_0_BINARY, + MCOMMA_DETECT_1 => MCOMMA_DETECT_1_BINARY, + OOBDETECT_THRESHOLD_0 => OOBDETECT_THRESHOLD_0_BINARY, + OOBDETECT_THRESHOLD_1 => OOBDETECT_THRESHOLD_1_BINARY, + OOB_CLK_DIVIDER => OOB_CLK_DIVIDER_BINARY, + OVERSAMPLE_MODE => OVERSAMPLE_MODE_BINARY, + PCI_EXPRESS_MODE_0 => PCI_EXPRESS_MODE_0_BINARY, + PCI_EXPRESS_MODE_1 => PCI_EXPRESS_MODE_1_BINARY, + PCOMMA_10B_VALUE_0 => PCOMMA_10B_VALUE_0_BINARY, + PCOMMA_10B_VALUE_1 => PCOMMA_10B_VALUE_1_BINARY, + PCOMMA_DETECT_0 => PCOMMA_DETECT_0_BINARY, + PCOMMA_DETECT_1 => PCOMMA_DETECT_1_BINARY, + PLL_COM_CFG => PLL_COM_CFG_BINARY, + PLL_CP_CFG => PLL_CP_CFG_BINARY, + PLL_DIVSEL_FB => PLL_DIVSEL_FB_BINARY, + PLL_DIVSEL_REF => PLL_DIVSEL_REF_BINARY, + PLL_FB_DCCEN => PLL_FB_DCCEN_BINARY, + PLL_LKDET_CFG => PLL_LKDET_CFG_BINARY, + PLL_RXDIVSEL_OUT_0 => PLL_RXDIVSEL_OUT_0_BINARY, + PLL_RXDIVSEL_OUT_1 => PLL_RXDIVSEL_OUT_1_BINARY, + PLL_SATA_0 => PLL_SATA_0_BINARY, + PLL_SATA_1 => PLL_SATA_1_BINARY, + PLL_TDCC_CFG => PLL_TDCC_CFG_BINARY, + PLL_TXDIVSEL_OUT_0 => PLL_TXDIVSEL_OUT_0_BINARY, + PLL_TXDIVSEL_OUT_1 => PLL_TXDIVSEL_OUT_1_BINARY, + PMA_CDR_SCAN_0 => PMA_CDR_SCAN_0_BINARY, + PMA_CDR_SCAN_1 => PMA_CDR_SCAN_1_BINARY, + PMA_COM_CFG => PMA_COM_CFG_BINARY, + PMA_RXSYNC_CFG_0 => PMA_RXSYNC_CFG_0_BINARY, + PMA_RXSYNC_CFG_1 => PMA_RXSYNC_CFG_1_BINARY, + PMA_RX_CFG_0 => PMA_RX_CFG_0_BINARY, + PMA_RX_CFG_1 => PMA_RX_CFG_1_BINARY, + PMA_TX_CFG_0 => PMA_TX_CFG_0_BINARY, + PMA_TX_CFG_1 => PMA_TX_CFG_1_BINARY, + PRBS_ERR_THRESHOLD_0 => PRBS_ERR_THRESHOLD_0_BINARY, + PRBS_ERR_THRESHOLD_1 => PRBS_ERR_THRESHOLD_1_BINARY, + RCV_TERM_GND_0 => RCV_TERM_GND_0_BINARY, + RCV_TERM_GND_1 => RCV_TERM_GND_1_BINARY, + RCV_TERM_VTTRX_0 => RCV_TERM_VTTRX_0_BINARY, + RCV_TERM_VTTRX_1 => RCV_TERM_VTTRX_1_BINARY, + RXGEARBOX_USE_0 => RXGEARBOX_USE_0_BINARY, + RXGEARBOX_USE_1 => RXGEARBOX_USE_1_BINARY, + RX_BUFFER_USE_0 => RX_BUFFER_USE_0_BINARY, + RX_BUFFER_USE_1 => RX_BUFFER_USE_1_BINARY, + RX_DECODE_SEQ_MATCH_0 => RX_DECODE_SEQ_MATCH_0_BINARY, + RX_DECODE_SEQ_MATCH_1 => RX_DECODE_SEQ_MATCH_1_BINARY, + RX_EN_IDLE_HOLD_CDR => RX_EN_IDLE_HOLD_CDR_BINARY, + RX_EN_IDLE_HOLD_DFE_0 => RX_EN_IDLE_HOLD_DFE_0_BINARY, + RX_EN_IDLE_HOLD_DFE_1 => RX_EN_IDLE_HOLD_DFE_1_BINARY, + RX_EN_IDLE_RESET_BUF_0 => RX_EN_IDLE_RESET_BUF_0_BINARY, + RX_EN_IDLE_RESET_BUF_1 => RX_EN_IDLE_RESET_BUF_1_BINARY, + RX_EN_IDLE_RESET_FR => RX_EN_IDLE_RESET_FR_BINARY, + RX_EN_IDLE_RESET_PH => RX_EN_IDLE_RESET_PH_BINARY, + RX_IDLE_HI_CNT_0 => RX_IDLE_HI_CNT_0_BINARY, + RX_IDLE_HI_CNT_1 => RX_IDLE_HI_CNT_1_BINARY, + RX_IDLE_LO_CNT_0 => RX_IDLE_LO_CNT_0_BINARY, + RX_IDLE_LO_CNT_1 => RX_IDLE_LO_CNT_1_BINARY, + RX_LOSS_OF_SYNC_FSM_0 => RX_LOSS_OF_SYNC_FSM_0_BINARY, + RX_LOSS_OF_SYNC_FSM_1 => RX_LOSS_OF_SYNC_FSM_1_BINARY, + RX_LOS_INVALID_INCR_0 => RX_LOS_INVALID_INCR_0_BINARY, + RX_LOS_INVALID_INCR_1 => RX_LOS_INVALID_INCR_1_BINARY, + RX_LOS_THRESHOLD_0 => RX_LOS_THRESHOLD_0_BINARY, + RX_LOS_THRESHOLD_1 => RX_LOS_THRESHOLD_1_BINARY, + RX_SLIDE_MODE_0 => RX_SLIDE_MODE_0_BINARY, + RX_SLIDE_MODE_1 => RX_SLIDE_MODE_1_BINARY, + RX_STATUS_FMT_0 => RX_STATUS_FMT_0_BINARY, + RX_STATUS_FMT_1 => RX_STATUS_FMT_1_BINARY, + RX_XCLK_SEL_0 => RX_XCLK_SEL_0_BINARY, + RX_XCLK_SEL_1 => RX_XCLK_SEL_1_BINARY, + SATA_BURST_VAL_0 => SATA_BURST_VAL_0_BINARY, + SATA_BURST_VAL_1 => SATA_BURST_VAL_1_BINARY, + SATA_IDLE_VAL_0 => SATA_IDLE_VAL_0_BINARY, + SATA_IDLE_VAL_1 => SATA_IDLE_VAL_1_BINARY, + SATA_MAX_BURST_0 => SATA_MAX_BURST_0_BINARY, + SATA_MAX_BURST_1 => SATA_MAX_BURST_1_BINARY, + SATA_MAX_INIT_0 => SATA_MAX_INIT_0_BINARY, + SATA_MAX_INIT_1 => SATA_MAX_INIT_1_BINARY, + SATA_MAX_WAKE_0 => SATA_MAX_WAKE_0_BINARY, + SATA_MAX_WAKE_1 => SATA_MAX_WAKE_1_BINARY, + SATA_MIN_BURST_0 => SATA_MIN_BURST_0_BINARY, + SATA_MIN_BURST_1 => SATA_MIN_BURST_1_BINARY, + SATA_MIN_INIT_0 => SATA_MIN_INIT_0_BINARY, + SATA_MIN_INIT_1 => SATA_MIN_INIT_1_BINARY, + SATA_MIN_WAKE_0 => SATA_MIN_WAKE_0_BINARY, + SATA_MIN_WAKE_1 => SATA_MIN_WAKE_1_BINARY, + SIM_GTXRESET_SPEEDUP => SIM_GTXRESET_SPEEDUP_BINARY, + SIM_PLL_PERDIV2 => SIM_PLL_PERDIV2_BINARY, + SIM_RECEIVER_DETECT_PASS_0 => SIM_RECEIVER_DETECT_PASS_0_BINARY, + SIM_RECEIVER_DETECT_PASS_1 => SIM_RECEIVER_DETECT_PASS_1_BINARY, + TERMINATION_CTRL => TERMINATION_CTRL_BINARY, + TERMINATION_IMP_0 => TERMINATION_IMP_0_BINARY, + TERMINATION_IMP_1 => TERMINATION_IMP_1_BINARY, + TERMINATION_OVRD => TERMINATION_OVRD_BINARY, + TRANS_TIME_FROM_P2_0 => TRANS_TIME_FROM_P2_0_BINARY, + TRANS_TIME_FROM_P2_1 => TRANS_TIME_FROM_P2_1_BINARY, + TRANS_TIME_NON_P2_0 => TRANS_TIME_NON_P2_0_BINARY, + TRANS_TIME_NON_P2_1 => TRANS_TIME_NON_P2_1_BINARY, + TRANS_TIME_TO_P2_0 => TRANS_TIME_TO_P2_0_BINARY, + TRANS_TIME_TO_P2_1 => TRANS_TIME_TO_P2_1_BINARY, + TXGEARBOX_USE_0 => TXGEARBOX_USE_0_BINARY, + TXGEARBOX_USE_1 => TXGEARBOX_USE_1_BINARY, + TXRX_INVERT_0 => TXRX_INVERT_0_BINARY, + TXRX_INVERT_1 => TXRX_INVERT_1_BINARY, + TX_BUFFER_USE_0 => TX_BUFFER_USE_0_BINARY, + TX_BUFFER_USE_1 => TX_BUFFER_USE_1_BINARY, + TX_DETECT_RX_CFG_0 => TX_DETECT_RX_CFG_0_BINARY, + TX_DETECT_RX_CFG_1 => TX_DETECT_RX_CFG_1_BINARY, + TX_IDLE_DELAY_0 => TX_IDLE_DELAY_0_BINARY, + TX_IDLE_DELAY_1 => TX_IDLE_DELAY_1_BINARY, + TX_XCLK_SEL_0 => TX_XCLK_SEL_0_BINARY, + TX_XCLK_SEL_1 => TX_XCLK_SEL_1_BINARY, + + DFECLKDLYADJMONITOR0 => DFECLKDLYADJMONITOR0_outdelay, + DFECLKDLYADJMONITOR1 => DFECLKDLYADJMONITOR1_outdelay, + DFEEYEDACMONITOR0 => DFEEYEDACMONITOR0_outdelay, + DFEEYEDACMONITOR1 => DFEEYEDACMONITOR1_outdelay, + DFESENSCAL0 => DFESENSCAL0_outdelay, + DFESENSCAL1 => DFESENSCAL1_outdelay, + DFETAP1MONITOR0 => DFETAP1MONITOR0_outdelay, + DFETAP1MONITOR1 => DFETAP1MONITOR1_outdelay, + DFETAP2MONITOR0 => DFETAP2MONITOR0_outdelay, + DFETAP2MONITOR1 => DFETAP2MONITOR1_outdelay, + DFETAP3MONITOR0 => DFETAP3MONITOR0_outdelay, + DFETAP3MONITOR1 => DFETAP3MONITOR1_outdelay, + DFETAP4MONITOR0 => DFETAP4MONITOR0_outdelay, + DFETAP4MONITOR1 => DFETAP4MONITOR1_outdelay, + DO => DO_outdelay, + DRDY => DRDY_outdelay, + PHYSTATUS0 => PHYSTATUS0_outdelay, + PHYSTATUS1 => PHYSTATUS1_outdelay, + PLLLKDET => PLLLKDET_outdelay, + REFCLKOUT => REFCLKOUT_outdelay, + RESETDONE0 => RESETDONE0_outdelay, + RESETDONE1 => RESETDONE1_outdelay, + RXBUFSTATUS0 => RXBUFSTATUS0_outdelay, + RXBUFSTATUS1 => RXBUFSTATUS1_outdelay, + RXBYTEISALIGNED0 => RXBYTEISALIGNED0_outdelay, + RXBYTEISALIGNED1 => RXBYTEISALIGNED1_outdelay, + RXBYTEREALIGN0 => RXBYTEREALIGN0_outdelay, + RXBYTEREALIGN1 => RXBYTEREALIGN1_outdelay, + RXCHANBONDSEQ0 => RXCHANBONDSEQ0_outdelay, + RXCHANBONDSEQ1 => RXCHANBONDSEQ1_outdelay, + RXCHANISALIGNED0 => RXCHANISALIGNED0_outdelay, + RXCHANISALIGNED1 => RXCHANISALIGNED1_outdelay, + RXCHANREALIGN0 => RXCHANREALIGN0_outdelay, + RXCHANREALIGN1 => RXCHANREALIGN1_outdelay, + RXCHARISCOMMA0 => RXCHARISCOMMA0_outdelay, + RXCHARISCOMMA1 => RXCHARISCOMMA1_outdelay, + RXCHARISK0 => RXCHARISK0_outdelay, + RXCHARISK1 => RXCHARISK1_outdelay, + RXCHBONDO0 => RXCHBONDO0_outdelay, + RXCHBONDO1 => RXCHBONDO1_outdelay, + RXCLKCORCNT0 => RXCLKCORCNT0_outdelay, + RXCLKCORCNT1 => RXCLKCORCNT1_outdelay, + RXCOMMADET0 => RXCOMMADET0_outdelay, + RXCOMMADET1 => RXCOMMADET1_outdelay, + RXDATA0 => RXDATA0_outdelay, + RXDATA1 => RXDATA1_outdelay, + RXDATAVALID0 => RXDATAVALID0_outdelay, + RXDATAVALID1 => RXDATAVALID1_outdelay, + RXDISPERR0 => RXDISPERR0_outdelay, + RXDISPERR1 => RXDISPERR1_outdelay, + RXELECIDLE0 => RXELECIDLE0_outdelay, + RXELECIDLE1 => RXELECIDLE1_outdelay, + RXHEADER0 => RXHEADER0_outdelay, + RXHEADER1 => RXHEADER1_outdelay, + RXHEADERVALID0 => RXHEADERVALID0_outdelay, + RXHEADERVALID1 => RXHEADERVALID1_outdelay, + RXLOSSOFSYNC0 => RXLOSSOFSYNC0_outdelay, + RXLOSSOFSYNC1 => RXLOSSOFSYNC1_outdelay, + RXNOTINTABLE0 => RXNOTINTABLE0_outdelay, + RXNOTINTABLE1 => RXNOTINTABLE1_outdelay, + RXOVERSAMPLEERR0 => RXOVERSAMPLEERR0_outdelay, + RXOVERSAMPLEERR1 => RXOVERSAMPLEERR1_outdelay, + RXPRBSERR0 => RXPRBSERR0_outdelay, + RXPRBSERR1 => RXPRBSERR1_outdelay, + RXRECCLK0 => RXRECCLK0_outdelay, + RXRECCLK1 => RXRECCLK1_outdelay, + RXRUNDISP0 => RXRUNDISP0_outdelay, + RXRUNDISP1 => RXRUNDISP1_outdelay, + RXSTARTOFSEQ0 => RXSTARTOFSEQ0_outdelay, + RXSTARTOFSEQ1 => RXSTARTOFSEQ1_outdelay, + RXSTATUS0 => RXSTATUS0_outdelay, + RXSTATUS1 => RXSTATUS1_outdelay, + RXVALID0 => RXVALID0_outdelay, + RXVALID1 => RXVALID1_outdelay, + TXBUFSTATUS0 => TXBUFSTATUS0_outdelay, + TXBUFSTATUS1 => TXBUFSTATUS1_outdelay, + TXGEARBOXREADY0 => TXGEARBOXREADY0_outdelay, + TXGEARBOXREADY1 => TXGEARBOXREADY1_outdelay, + TXKERR0 => TXKERR0_outdelay, + TXKERR1 => TXKERR1_outdelay, + TXN0 => TXN0_outdelay, + TXN1 => TXN1_outdelay, + TXOUTCLK0 => TXOUTCLK0_outdelay, + TXOUTCLK1 => TXOUTCLK1_outdelay, + TXP0 => TXP0_outdelay, + TXP1 => TXP1_outdelay, + TXRUNDISP0 => TXRUNDISP0_outdelay, + TXRUNDISP1 => TXRUNDISP1_outdelay, + + CLKIN => CLKIN_indelay, + DADDR => DADDR_indelay, + DCLK => DCLK_indelay, + DEN => DEN_indelay, + DFECLKDLYADJ0 => DFECLKDLYADJ0_indelay, + DFECLKDLYADJ1 => DFECLKDLYADJ1_indelay, + DFETAP10 => DFETAP10_indelay, + DFETAP11 => DFETAP11_indelay, + DFETAP20 => DFETAP20_indelay, + DFETAP21 => DFETAP21_indelay, + DFETAP30 => DFETAP30_indelay, + DFETAP31 => DFETAP31_indelay, + DFETAP40 => DFETAP40_indelay, + DFETAP41 => DFETAP41_indelay, + DI => DI_indelay, + DWE => DWE_indelay, + GSR => GSR, + GTXRESET => GTXRESET_indelay, + GTXTEST => GTXTEST_indelay, + INTDATAWIDTH => INTDATAWIDTH_indelay, + LOOPBACK0 => LOOPBACK0_indelay, + LOOPBACK1 => LOOPBACK1_indelay, + PLLLKDETEN => PLLLKDETEN_indelay, + PLLPOWERDOWN => PLLPOWERDOWN_indelay, + PRBSCNTRESET0 => PRBSCNTRESET0_indelay, + PRBSCNTRESET1 => PRBSCNTRESET1_indelay, + REFCLKPWRDNB => REFCLKPWRDNB_indelay, + RXBUFRESET0 => RXBUFRESET0_indelay, + RXBUFRESET1 => RXBUFRESET1_indelay, + RXCDRRESET0 => RXCDRRESET0_indelay, + RXCDRRESET1 => RXCDRRESET1_indelay, + RXCHBONDI0 => RXCHBONDI0_indelay, + RXCHBONDI1 => RXCHBONDI1_indelay, + RXCOMMADETUSE0 => RXCOMMADETUSE0_indelay, + RXCOMMADETUSE1 => RXCOMMADETUSE1_indelay, + RXDATAWIDTH0 => RXDATAWIDTH0_indelay, + RXDATAWIDTH1 => RXDATAWIDTH1_indelay, + RXDEC8B10BUSE0 => RXDEC8B10BUSE0_indelay, + RXDEC8B10BUSE1 => RXDEC8B10BUSE1_indelay, + RXENCHANSYNC0 => RXENCHANSYNC0_indelay, + RXENCHANSYNC1 => RXENCHANSYNC1_indelay, + RXENEQB0 => RXENEQB0_indelay, + RXENEQB1 => RXENEQB1_indelay, + RXENMCOMMAALIGN0 => RXENMCOMMAALIGN0_indelay, + RXENMCOMMAALIGN1 => RXENMCOMMAALIGN1_indelay, + RXENPCOMMAALIGN0 => RXENPCOMMAALIGN0_indelay, + RXENPCOMMAALIGN1 => RXENPCOMMAALIGN1_indelay, + RXENPMAPHASEALIGN0 => RXENPMAPHASEALIGN0_indelay, + RXENPMAPHASEALIGN1 => RXENPMAPHASEALIGN1_indelay, + RXENPRBSTST0 => RXENPRBSTST0_indelay, + RXENPRBSTST1 => RXENPRBSTST1_indelay, + RXENSAMPLEALIGN0 => RXENSAMPLEALIGN0_indelay, + RXENSAMPLEALIGN1 => RXENSAMPLEALIGN1_indelay, + RXEQMIX0 => RXEQMIX0_indelay, + RXEQMIX1 => RXEQMIX1_indelay, + RXEQPOLE0 => RXEQPOLE0_indelay, + RXEQPOLE1 => RXEQPOLE1_indelay, + RXGEARBOXSLIP0 => RXGEARBOXSLIP0_indelay, + RXGEARBOXSLIP1 => RXGEARBOXSLIP1_indelay, + RXN0 => RXN0_indelay, + RXN1 => RXN1_indelay, + RXP0 => RXP0_indelay, + RXP1 => RXP1_indelay, + RXPMASETPHASE0 => RXPMASETPHASE0_indelay, + RXPMASETPHASE1 => RXPMASETPHASE1_indelay, + RXPOLARITY0 => RXPOLARITY0_indelay, + RXPOLARITY1 => RXPOLARITY1_indelay, + RXPOWERDOWN0 => RXPOWERDOWN0_indelay, + RXPOWERDOWN1 => RXPOWERDOWN1_indelay, + RXRESET0 => RXRESET0_indelay, + RXRESET1 => RXRESET1_indelay, + RXSLIDE0 => RXSLIDE0_indelay, + RXSLIDE1 => RXSLIDE1_indelay, + RXUSRCLK0 => RXUSRCLK0_indelay, + RXUSRCLK1 => RXUSRCLK1_indelay, + RXUSRCLK20 => RXUSRCLK20_indelay, + RXUSRCLK21 => RXUSRCLK21_indelay, + TXBUFDIFFCTRL0 => TXBUFDIFFCTRL0_indelay, + TXBUFDIFFCTRL1 => TXBUFDIFFCTRL1_indelay, + TXBYPASS8B10B0 => TXBYPASS8B10B0_indelay, + TXBYPASS8B10B1 => TXBYPASS8B10B1_indelay, + TXCHARDISPMODE0 => TXCHARDISPMODE0_indelay, + TXCHARDISPMODE1 => TXCHARDISPMODE1_indelay, + TXCHARDISPVAL0 => TXCHARDISPVAL0_indelay, + TXCHARDISPVAL1 => TXCHARDISPVAL1_indelay, + TXCHARISK0 => TXCHARISK0_indelay, + TXCHARISK1 => TXCHARISK1_indelay, + TXCOMSTART0 => TXCOMSTART0_indelay, + TXCOMSTART1 => TXCOMSTART1_indelay, + TXCOMTYPE0 => TXCOMTYPE0_indelay, + TXCOMTYPE1 => TXCOMTYPE1_indelay, + TXDATA0 => TXDATA0_indelay, + TXDATA1 => TXDATA1_indelay, + TXDATAWIDTH0 => TXDATAWIDTH0_indelay, + TXDATAWIDTH1 => TXDATAWIDTH1_indelay, + TXDETECTRX0 => TXDETECTRX0_indelay, + TXDETECTRX1 => TXDETECTRX1_indelay, + TXDIFFCTRL0 => TXDIFFCTRL0_indelay, + TXDIFFCTRL1 => TXDIFFCTRL1_indelay, + TXELECIDLE0 => TXELECIDLE0_indelay, + TXELECIDLE1 => TXELECIDLE1_indelay, + TXENC8B10BUSE0 => TXENC8B10BUSE0_indelay, + TXENC8B10BUSE1 => TXENC8B10BUSE1_indelay, + TXENPMAPHASEALIGN0 => TXENPMAPHASEALIGN0_indelay, + TXENPMAPHASEALIGN1 => TXENPMAPHASEALIGN1_indelay, + TXENPRBSTST0 => TXENPRBSTST0_indelay, + TXENPRBSTST1 => TXENPRBSTST1_indelay, + TXHEADER0 => TXHEADER0_indelay, + TXHEADER1 => TXHEADER1_indelay, + TXINHIBIT0 => TXINHIBIT0_indelay, + TXINHIBIT1 => TXINHIBIT1_indelay, + TXPMASETPHASE0 => TXPMASETPHASE0_indelay, + TXPMASETPHASE1 => TXPMASETPHASE1_indelay, + TXPOLARITY0 => TXPOLARITY0_indelay, + TXPOLARITY1 => TXPOLARITY1_indelay, + TXPOWERDOWN0 => TXPOWERDOWN0_indelay, + TXPOWERDOWN1 => TXPOWERDOWN1_indelay, + TXPREEMPHASIS0 => TXPREEMPHASIS0_indelay, + TXPREEMPHASIS1 => TXPREEMPHASIS1_indelay, + TXRESET0 => TXRESET0_indelay, + TXRESET1 => TXRESET1_indelay, + TXSEQUENCE0 => TXSEQUENCE0_indelay, + TXSEQUENCE1 => TXSEQUENCE1_indelay, + TXSTARTSEQ0 => TXSTARTSEQ0_indelay, + TXSTARTSEQ1 => TXSTARTSEQ1_indelay, + TXUSRCLK0 => TXUSRCLK0_indelay, + TXUSRCLK1 => TXUSRCLK1_indelay, + TXUSRCLK20 => TXUSRCLK20_indelay, + TXUSRCLK21 => TXUSRCLK21_indelay + ); + end generate fast_model; + + INIPROC : process + begin + case PLL_TXDIVSEL_OUT_0 is + when 1 => PLL_TXDIVSEL_OUT_0_BINARY <= "00"; + when 2 => PLL_TXDIVSEL_OUT_0_BINARY <= "01"; + when 4 => PLL_TXDIVSEL_OUT_0_BINARY <= "10"; + when others => assert FALSE report "Error : PLL_TXDIVSEL_OUT_0 is not in 1, 2, 4." severity error; + end case; + case PLL_RXDIVSEL_OUT_0 is + when 1 => PLL_RXDIVSEL_OUT_0_BINARY <= "00"; + when 2 => PLL_RXDIVSEL_OUT_0_BINARY <= "01"; + when 4 => PLL_RXDIVSEL_OUT_0_BINARY <= "10"; + when others => assert FALSE report "Error : PLL_RXDIVSEL_OUT_0 is not in 1, 2, 4." severity error; + end case; + case PLL_TXDIVSEL_OUT_1 is + when 1 => PLL_TXDIVSEL_OUT_1_BINARY <= "00"; + when 2 => PLL_TXDIVSEL_OUT_1_BINARY <= "01"; + when 4 => PLL_TXDIVSEL_OUT_1_BINARY <= "10"; + when others => assert FALSE report "Error : PLL_TXDIVSEL_OUT_1 is not in 1, 2, 4." severity error; + end case; + case PLL_RXDIVSEL_OUT_1 is + when 1 => PLL_RXDIVSEL_OUT_1_BINARY <= "00"; + when 2 => PLL_RXDIVSEL_OUT_1_BINARY <= "01"; + when 4 => PLL_RXDIVSEL_OUT_1_BINARY <= "10"; + when others => assert FALSE report "Error : PLL_RXDIVSEL_OUT_1 is not in 1, 2, 4." severity error; + end case; + case PLL_DIVSEL_FB is + when 1 => PLL_DIVSEL_FB_BINARY <= "10000"; + when 2 => PLL_DIVSEL_FB_BINARY <= "00000"; + when 3 => PLL_DIVSEL_FB_BINARY <= "00001"; + when 4 => PLL_DIVSEL_FB_BINARY <= "00010"; + when 5 => PLL_DIVSEL_FB_BINARY <= "00011"; + when 8 => PLL_DIVSEL_FB_BINARY <= "00110"; + when 10 => PLL_DIVSEL_FB_BINARY <= "00111"; + when others => assert FALSE report "Error : PLL_DIVSEL_FB is not in 1, 2, 3, 4, 5, 8, 10." severity error; + end case; + case PLL_DIVSEL_REF is + when 1 => PLL_DIVSEL_REF_BINARY <= "010000"; + when 2 => PLL_DIVSEL_REF_BINARY <= "000000"; + when 3 => PLL_DIVSEL_REF_BINARY <= "000001"; + when 4 => PLL_DIVSEL_REF_BINARY <= "000010"; + when 5 => PLL_DIVSEL_REF_BINARY <= "000011"; + when 6 => PLL_DIVSEL_REF_BINARY <= "000101"; + when 8 => PLL_DIVSEL_REF_BINARY <= "000110"; + when 10 => PLL_DIVSEL_REF_BINARY <= "000111"; + when 12 => PLL_DIVSEL_REF_BINARY <= "001101"; + when 16 => PLL_DIVSEL_REF_BINARY <= "001110"; + when 20 => PLL_DIVSEL_REF_BINARY <= "001111"; + when others => assert FALSE report "Error : PLL_DIVSEL_REF is not in 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20." severity error; + end case; + case PLL_SATA_0 is + when FALSE => PLL_SATA_0_BINARY <= '0'; + when TRUE => PLL_SATA_0_BINARY <= '1'; + when others => assert FALSE report "Error : PLL_SATA_0 is neither TRUE nor FALSE." severity error; + end case; + case PLL_SATA_1 is + when FALSE => PLL_SATA_1_BINARY <= '0'; + when TRUE => PLL_SATA_1_BINARY <= '1'; + when others => assert FALSE report "Error : PLL_SATA_1 is neither TRUE nor FALSE." severity error; + end case; + case OOB_CLK_DIVIDER is + when 1 => OOB_CLK_DIVIDER_BINARY <= "000"; + when 2 => OOB_CLK_DIVIDER_BINARY <= "001"; + when 4 => OOB_CLK_DIVIDER_BINARY <= "010"; + when 6 => OOB_CLK_DIVIDER_BINARY <= "011"; + when 8 => OOB_CLK_DIVIDER_BINARY <= "100"; + when 10 => OOB_CLK_DIVIDER_BINARY <= "101"; + when 12 => OOB_CLK_DIVIDER_BINARY <= "110"; + when 14 => OOB_CLK_DIVIDER_BINARY <= "111"; + when others => assert FALSE report "Error : OOB_CLK_DIVIDER is not in 1, 2, 4, 6, 8, 10, 12, 14." severity error; + end case; + + if (OOBDETECT_THRESHOLD_0 = "110") then + OOBDETECT_THRESHOLD_0_BINARY <= "110"; + elsif (OOBDETECT_THRESHOLD_0 = "111") then + OOBDETECT_THRESHOLD_0_BINARY <= "111"; + else + assert FALSE report "Warning : OOBDETECT_THRESHOLD_0 is not in 110, 111." severity warning; + end if; + + if (OOBDETECT_THRESHOLD_1 = "110") then + OOBDETECT_THRESHOLD_1_BINARY <= "110"; + elsif (OOBDETECT_THRESHOLD_1 = "111") then + OOBDETECT_THRESHOLD_1_BINARY <= "111"; + else + assert FALSE report "Warning : OOBDETECT_THRESHOLD_1 is not in 110, 111." severity warning; + end if; + + case AC_CAP_DIS_0 is + when FALSE => AC_CAP_DIS_0_BINARY <= '0'; + when TRUE => AC_CAP_DIS_0_BINARY <= '1'; + when others => assert FALSE report "Error : AC_CAP_DIS_0 is neither TRUE nor FALSE." severity error; + end case; + case AC_CAP_DIS_1 is + when FALSE => AC_CAP_DIS_1_BINARY <= '0'; + when TRUE => AC_CAP_DIS_1_BINARY <= '1'; + when others => assert FALSE report "Error : AC_CAP_DIS_1 is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_GND_0 is + when FALSE => RCV_TERM_GND_0_BINARY <= '0'; + when TRUE => RCV_TERM_GND_0_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_GND_0 is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_GND_1 is + when FALSE => RCV_TERM_GND_1_BINARY <= '0'; + when TRUE => RCV_TERM_GND_1_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_GND_1 is neither TRUE nor FALSE." severity error; + end case; + case TERMINATION_IMP_0 is + when 50 => TERMINATION_IMP_0_BINARY <= '0'; + when 75 => TERMINATION_IMP_0_BINARY <= '1'; + when others => assert FALSE report "Error : TERMINATION_IMP_0 is not in 50, 75." severity error; + end case; + case TERMINATION_IMP_1 is + when 50 => TERMINATION_IMP_1_BINARY <= '0'; + when 75 => TERMINATION_IMP_1_BINARY <= '1'; + when others => assert FALSE report "Error : TERMINATION_IMP_1 is not in 50, 75." severity error; + end case; + case TERMINATION_OVRD is + when FALSE => TERMINATION_OVRD_BINARY <= '0'; + when TRUE => TERMINATION_OVRD_BINARY <= '1'; + when others => assert FALSE report "Error : TERMINATION_OVRD is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_VTTRX_0 is + when FALSE => RCV_TERM_VTTRX_0_BINARY <= '0'; + when TRUE => RCV_TERM_VTTRX_0_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_VTTRX_0 is neither TRUE nor FALSE." severity error; + end case; + case RCV_TERM_VTTRX_1 is + when FALSE => RCV_TERM_VTTRX_1_BINARY <= '0'; + when TRUE => RCV_TERM_VTTRX_1_BINARY <= '1'; + when others => assert FALSE report "Error : RCV_TERM_VTTRX_1 is neither TRUE nor FALSE." severity error; + end case; + case CLKINDC_B is + when FALSE => CLKINDC_B_BINARY <= '0'; + when TRUE => CLKINDC_B_BINARY <= '1'; + when others => assert FALSE report "Error : CLKINDC_B is neither TRUE nor FALSE." severity error; + end case; + case PCOMMA_DETECT_0 is + when FALSE => PCOMMA_DETECT_0_BINARY <= '0'; + when TRUE => PCOMMA_DETECT_0_BINARY <= '1'; + when others => assert FALSE report "Error : PCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; + end case; + case MCOMMA_DETECT_0 is + when FALSE => MCOMMA_DETECT_0_BINARY <= '0'; + when TRUE => MCOMMA_DETECT_0_BINARY <= '1'; + when others => assert FALSE report "Error : MCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; + end case; + case COMMA_DOUBLE_0 is + when FALSE => COMMA_DOUBLE_0_BINARY <= '0'; + when TRUE => COMMA_DOUBLE_0_BINARY <= '1'; + when others => assert FALSE report "Error : COMMA_DOUBLE_0 is neither TRUE nor FALSE." severity error; + end case; + case ALIGN_COMMA_WORD_0 is + when 1 => ALIGN_COMMA_WORD_0_BINARY <= '0'; + when 2 => ALIGN_COMMA_WORD_0_BINARY <= '1'; + when others => assert FALSE report "Error : ALIGN_COMMA_WORD_0 is not in 1, 2." severity error; + end case; + case DEC_PCOMMA_DETECT_0 is + when FALSE => DEC_PCOMMA_DETECT_0_BINARY <= '0'; + when TRUE => DEC_PCOMMA_DETECT_0_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_PCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; + end case; + case DEC_MCOMMA_DETECT_0 is + when FALSE => DEC_MCOMMA_DETECT_0_BINARY <= '0'; + when TRUE => DEC_MCOMMA_DETECT_0_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_MCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; + end case; + case DEC_VALID_COMMA_ONLY_0 is + when FALSE => DEC_VALID_COMMA_ONLY_0_BINARY <= '0'; + when TRUE => DEC_VALID_COMMA_ONLY_0_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_VALID_COMMA_ONLY_0 is neither TRUE nor FALSE." severity error; + end case; + case PCOMMA_DETECT_1 is + when FALSE => PCOMMA_DETECT_1_BINARY <= '0'; + when TRUE => PCOMMA_DETECT_1_BINARY <= '1'; + when others => assert FALSE report "Error : PCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; + end case; + case MCOMMA_DETECT_1 is + when FALSE => MCOMMA_DETECT_1_BINARY <= '0'; + when TRUE => MCOMMA_DETECT_1_BINARY <= '1'; + when others => assert FALSE report "Error : MCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; + end case; + case COMMA_DOUBLE_1 is + when FALSE => COMMA_DOUBLE_1_BINARY <= '0'; + when TRUE => COMMA_DOUBLE_1_BINARY <= '1'; + when others => assert FALSE report "Error : COMMA_DOUBLE_1 is neither TRUE nor FALSE." severity error; + end case; + case ALIGN_COMMA_WORD_1 is + when 1 => ALIGN_COMMA_WORD_1_BINARY <= '0'; + when 2 => ALIGN_COMMA_WORD_1_BINARY <= '1'; + when others => assert FALSE report "Error : ALIGN_COMMA_WORD_1 is not in 1, 2." severity error; + end case; + case DEC_PCOMMA_DETECT_1 is + when FALSE => DEC_PCOMMA_DETECT_1_BINARY <= '0'; + when TRUE => DEC_PCOMMA_DETECT_1_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_PCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; + end case; + case DEC_MCOMMA_DETECT_1 is + when FALSE => DEC_MCOMMA_DETECT_1_BINARY <= '0'; + when TRUE => DEC_MCOMMA_DETECT_1_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_MCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; + end case; + case DEC_VALID_COMMA_ONLY_1 is + when FALSE => DEC_VALID_COMMA_ONLY_1_BINARY <= '0'; + when TRUE => DEC_VALID_COMMA_ONLY_1_BINARY <= '1'; + when others => assert FALSE report "Error : DEC_VALID_COMMA_ONLY_1 is neither TRUE nor FALSE." severity error; + end case; + case RX_LOSS_OF_SYNC_FSM_0 is + when FALSE => RX_LOSS_OF_SYNC_FSM_0_BINARY <= '0'; + when TRUE => RX_LOSS_OF_SYNC_FSM_0_BINARY <= '1'; + when others => assert FALSE report "Error : RX_LOSS_OF_SYNC_FSM_0 is neither TRUE nor FALSE." severity error; + end case; + case RX_LOS_INVALID_INCR_0 is + when 1 => RX_LOS_INVALID_INCR_0_BINARY <= "000"; + when 2 => RX_LOS_INVALID_INCR_0_BINARY <= "001"; + when 4 => RX_LOS_INVALID_INCR_0_BINARY <= "010"; + when 8 => RX_LOS_INVALID_INCR_0_BINARY <= "011"; + when 16 => RX_LOS_INVALID_INCR_0_BINARY <= "100"; + when 32 => RX_LOS_INVALID_INCR_0_BINARY <= "101"; + when 64 => RX_LOS_INVALID_INCR_0_BINARY <= "110"; + when 128 => RX_LOS_INVALID_INCR_0_BINARY <= "111"; + when others => assert FALSE report "Error : RX_LOS_INVALID_INCR_0 is not in 1, 2, 4, 8, 16, 32, 64, 128." severity error; + end case; + case RX_LOS_THRESHOLD_0 is + when 4 => RX_LOS_THRESHOLD_0_BINARY <= "000"; + when 8 => RX_LOS_THRESHOLD_0_BINARY <= "001"; + when 16 => RX_LOS_THRESHOLD_0_BINARY <= "010"; + when 32 => RX_LOS_THRESHOLD_0_BINARY <= "011"; + when 64 => RX_LOS_THRESHOLD_0_BINARY <= "100"; + when 128 => RX_LOS_THRESHOLD_0_BINARY <= "101"; + when 256 => RX_LOS_THRESHOLD_0_BINARY <= "110"; + when 512 => RX_LOS_THRESHOLD_0_BINARY <= "111"; + when others => assert FALSE report "Error : RX_LOS_THRESHOLD_0 is not in 4, 8, 16, 32, 64, 128, 256, 512." severity error; + end case; + case RX_LOSS_OF_SYNC_FSM_1 is + when FALSE => RX_LOSS_OF_SYNC_FSM_1_BINARY <= '0'; + when TRUE => RX_LOSS_OF_SYNC_FSM_1_BINARY <= '1'; + when others => assert FALSE report "Error : RX_LOSS_OF_SYNC_FSM_1 is neither TRUE nor FALSE." severity error; + end case; + case RX_LOS_INVALID_INCR_1 is + when 1 => RX_LOS_INVALID_INCR_1_BINARY <= "000"; + when 2 => RX_LOS_INVALID_INCR_1_BINARY <= "001"; + when 4 => RX_LOS_INVALID_INCR_1_BINARY <= "010"; + when 8 => RX_LOS_INVALID_INCR_1_BINARY <= "011"; + when 16 => RX_LOS_INVALID_INCR_1_BINARY <= "100"; + when 32 => RX_LOS_INVALID_INCR_1_BINARY <= "101"; + when 64 => RX_LOS_INVALID_INCR_1_BINARY <= "110"; + when 128 => RX_LOS_INVALID_INCR_1_BINARY <= "111"; + when others => assert FALSE report "Error : RX_LOS_INVALID_INCR_1 is not in 1, 2, 4, 8, 16, 32, 64, 128." severity error; + end case; + case RX_LOS_THRESHOLD_1 is + when 4 => RX_LOS_THRESHOLD_1_BINARY <= "000"; + when 8 => RX_LOS_THRESHOLD_1_BINARY <= "001"; + when 16 => RX_LOS_THRESHOLD_1_BINARY <= "010"; + when 32 => RX_LOS_THRESHOLD_1_BINARY <= "011"; + when 64 => RX_LOS_THRESHOLD_1_BINARY <= "100"; + when 128 => RX_LOS_THRESHOLD_1_BINARY <= "101"; + when 256 => RX_LOS_THRESHOLD_1_BINARY <= "110"; + when 512 => RX_LOS_THRESHOLD_1_BINARY <= "111"; + when others => assert FALSE report "Error : RX_LOS_THRESHOLD_1 is not in 4, 8, 16, 32, 64, 128, 256, 512." severity error; + end case; + case RX_BUFFER_USE_0 is + when FALSE => RX_BUFFER_USE_0_BINARY <= '0'; + when TRUE => RX_BUFFER_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : RX_BUFFER_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case RX_DECODE_SEQ_MATCH_0 is + when FALSE => RX_DECODE_SEQ_MATCH_0_BINARY <= '0'; + when TRUE => RX_DECODE_SEQ_MATCH_0_BINARY <= '1'; + when others => assert FALSE report "Error : RX_DECODE_SEQ_MATCH_0 is neither TRUE nor FALSE." severity error; + end case; + case RX_BUFFER_USE_1 is + when FALSE => RX_BUFFER_USE_1_BINARY <= '0'; + when TRUE => RX_BUFFER_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : RX_BUFFER_USE_1 is neither TRUE nor FALSE." severity error; + end case; + case RX_DECODE_SEQ_MATCH_1 is + when FALSE => RX_DECODE_SEQ_MATCH_1_BINARY <= '0'; + when TRUE => RX_DECODE_SEQ_MATCH_1_BINARY <= '1'; + when others => assert FALSE report "Error : RX_DECODE_SEQ_MATCH_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_MIN_LAT_0 is + when 3 => CLK_COR_MIN_LAT_0_BINARY <= "000011"; + when 4 => CLK_COR_MIN_LAT_0_BINARY <= "000100"; + when 5 => CLK_COR_MIN_LAT_0_BINARY <= "000101"; + when 6 => CLK_COR_MIN_LAT_0_BINARY <= "000110"; + when 7 => CLK_COR_MIN_LAT_0_BINARY <= "000111"; + when 8 => CLK_COR_MIN_LAT_0_BINARY <= "001000"; + when 9 => CLK_COR_MIN_LAT_0_BINARY <= "001001"; + when 10 => CLK_COR_MIN_LAT_0_BINARY <= "001010"; + when 11 => CLK_COR_MIN_LAT_0_BINARY <= "001011"; + when 12 => CLK_COR_MIN_LAT_0_BINARY <= "001100"; + when 13 => CLK_COR_MIN_LAT_0_BINARY <= "001101"; + when 14 => CLK_COR_MIN_LAT_0_BINARY <= "001110"; + when 15 => CLK_COR_MIN_LAT_0_BINARY <= "001111"; + when 16 => CLK_COR_MIN_LAT_0_BINARY <= "010000"; + when 17 => CLK_COR_MIN_LAT_0_BINARY <= "010001"; + when 18 => CLK_COR_MIN_LAT_0_BINARY <= "010010"; + when 19 => CLK_COR_MIN_LAT_0_BINARY <= "010011"; + when 20 => CLK_COR_MIN_LAT_0_BINARY <= "010100"; + when 21 => CLK_COR_MIN_LAT_0_BINARY <= "010101"; + when 22 => CLK_COR_MIN_LAT_0_BINARY <= "010110"; + when 23 => CLK_COR_MIN_LAT_0_BINARY <= "010111"; + when 24 => CLK_COR_MIN_LAT_0_BINARY <= "011000"; + when 25 => CLK_COR_MIN_LAT_0_BINARY <= "011001"; + when 26 => CLK_COR_MIN_LAT_0_BINARY <= "011010"; + when 27 => CLK_COR_MIN_LAT_0_BINARY <= "011011"; + when 28 => CLK_COR_MIN_LAT_0_BINARY <= "011100"; + when 29 => CLK_COR_MIN_LAT_0_BINARY <= "011101"; + when 30 => CLK_COR_MIN_LAT_0_BINARY <= "011110"; + when 31 => CLK_COR_MIN_LAT_0_BINARY <= "011111"; + when 32 => CLK_COR_MIN_LAT_0_BINARY <= "100000"; + when 33 => CLK_COR_MIN_LAT_0_BINARY <= "100001"; + when 34 => CLK_COR_MIN_LAT_0_BINARY <= "100010"; + when 35 => CLK_COR_MIN_LAT_0_BINARY <= "100011"; + when 36 => CLK_COR_MIN_LAT_0_BINARY <= "100100"; + when 37 => CLK_COR_MIN_LAT_0_BINARY <= "100101"; + when 38 => CLK_COR_MIN_LAT_0_BINARY <= "100110"; + when 39 => CLK_COR_MIN_LAT_0_BINARY <= "100111"; + when 40 => CLK_COR_MIN_LAT_0_BINARY <= "101000"; + when 41 => CLK_COR_MIN_LAT_0_BINARY <= "101001"; + when 42 => CLK_COR_MIN_LAT_0_BINARY <= "101010"; + when 43 => CLK_COR_MIN_LAT_0_BINARY <= "101011"; + when 44 => CLK_COR_MIN_LAT_0_BINARY <= "101100"; + when 45 => CLK_COR_MIN_LAT_0_BINARY <= "101101"; + when 46 => CLK_COR_MIN_LAT_0_BINARY <= "101110"; + when 47 => CLK_COR_MIN_LAT_0_BINARY <= "101111"; + when 48 => CLK_COR_MIN_LAT_0_BINARY <= "110000"; + when others => assert FALSE report "Error : CLK_COR_MIN_LAT_0 is not in range 3...48." severity error; + end case; + case CLK_COR_MAX_LAT_0 is + when 3 => CLK_COR_MAX_LAT_0_BINARY <= "000011"; + when 4 => CLK_COR_MAX_LAT_0_BINARY <= "000100"; + when 5 => CLK_COR_MAX_LAT_0_BINARY <= "000101"; + when 6 => CLK_COR_MAX_LAT_0_BINARY <= "000110"; + when 7 => CLK_COR_MAX_LAT_0_BINARY <= "000111"; + when 8 => CLK_COR_MAX_LAT_0_BINARY <= "001000"; + when 9 => CLK_COR_MAX_LAT_0_BINARY <= "001001"; + when 10 => CLK_COR_MAX_LAT_0_BINARY <= "001010"; + when 11 => CLK_COR_MAX_LAT_0_BINARY <= "001011"; + when 12 => CLK_COR_MAX_LAT_0_BINARY <= "001100"; + when 13 => CLK_COR_MAX_LAT_0_BINARY <= "001101"; + when 14 => CLK_COR_MAX_LAT_0_BINARY <= "001110"; + when 15 => CLK_COR_MAX_LAT_0_BINARY <= "001111"; + when 16 => CLK_COR_MAX_LAT_0_BINARY <= "010000"; + when 17 => CLK_COR_MAX_LAT_0_BINARY <= "010001"; + when 18 => CLK_COR_MAX_LAT_0_BINARY <= "010010"; + when 19 => CLK_COR_MAX_LAT_0_BINARY <= "010011"; + when 20 => CLK_COR_MAX_LAT_0_BINARY <= "010100"; + when 21 => CLK_COR_MAX_LAT_0_BINARY <= "010101"; + when 22 => CLK_COR_MAX_LAT_0_BINARY <= "010110"; + when 23 => CLK_COR_MAX_LAT_0_BINARY <= "010111"; + when 24 => CLK_COR_MAX_LAT_0_BINARY <= "011000"; + when 25 => CLK_COR_MAX_LAT_0_BINARY <= "011001"; + when 26 => CLK_COR_MAX_LAT_0_BINARY <= "011010"; + when 27 => CLK_COR_MAX_LAT_0_BINARY <= "011011"; + when 28 => CLK_COR_MAX_LAT_0_BINARY <= "011100"; + when 29 => CLK_COR_MAX_LAT_0_BINARY <= "011101"; + when 30 => CLK_COR_MAX_LAT_0_BINARY <= "011110"; + when 31 => CLK_COR_MAX_LAT_0_BINARY <= "011111"; + when 32 => CLK_COR_MAX_LAT_0_BINARY <= "100000"; + when 33 => CLK_COR_MAX_LAT_0_BINARY <= "100001"; + when 34 => CLK_COR_MAX_LAT_0_BINARY <= "100010"; + when 35 => CLK_COR_MAX_LAT_0_BINARY <= "100011"; + when 36 => CLK_COR_MAX_LAT_0_BINARY <= "100100"; + when 37 => CLK_COR_MAX_LAT_0_BINARY <= "100101"; + when 38 => CLK_COR_MAX_LAT_0_BINARY <= "100110"; + when 39 => CLK_COR_MAX_LAT_0_BINARY <= "100111"; + when 40 => CLK_COR_MAX_LAT_0_BINARY <= "101000"; + when 41 => CLK_COR_MAX_LAT_0_BINARY <= "101001"; + when 42 => CLK_COR_MAX_LAT_0_BINARY <= "101010"; + when 43 => CLK_COR_MAX_LAT_0_BINARY <= "101011"; + when 44 => CLK_COR_MAX_LAT_0_BINARY <= "101100"; + when 45 => CLK_COR_MAX_LAT_0_BINARY <= "101101"; + when 46 => CLK_COR_MAX_LAT_0_BINARY <= "101110"; + when 47 => CLK_COR_MAX_LAT_0_BINARY <= "101111"; + when 48 => CLK_COR_MAX_LAT_0_BINARY <= "110000"; + when others => assert FALSE report "Error : CLK_COR_MAX_LAT_0 is not in range 3...48." severity error; + end case; + case CLK_CORRECT_USE_0 is + when FALSE => CLK_CORRECT_USE_0_BINARY <= '0'; + when TRUE => CLK_CORRECT_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_CORRECT_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_PRECEDENCE_0 is + when FALSE => CLK_COR_PRECEDENCE_0_BINARY <= '0'; + when TRUE => CLK_COR_PRECEDENCE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_PRECEDENCE_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_DET_LEN_0 is + when 1 => CLK_COR_DET_LEN_0_BINARY <= "00"; + when 2 => CLK_COR_DET_LEN_0_BINARY <= "01"; + when 3 => CLK_COR_DET_LEN_0_BINARY <= "10"; + when 4 => CLK_COR_DET_LEN_0_BINARY <= "11"; + when others => assert FALSE report "Error : CLK_COR_DET_LEN_0 is not in 1, 2, 3, 4." severity error; + end case; + case CLK_COR_ADJ_LEN_0 is + when 1 => CLK_COR_ADJ_LEN_0_BINARY <= "00"; + when 2 => CLK_COR_ADJ_LEN_0_BINARY <= "01"; + when 3 => CLK_COR_ADJ_LEN_0_BINARY <= "10"; + when 4 => CLK_COR_ADJ_LEN_0_BINARY <= "11"; + when others => assert FALSE report "Error : CLK_COR_ADJ_LEN_0 is not in 1, 2, 3, 4." severity error; + end case; + case CLK_COR_KEEP_IDLE_0 is + when FALSE => CLK_COR_KEEP_IDLE_0_BINARY <= '0'; + when TRUE => CLK_COR_KEEP_IDLE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_KEEP_IDLE_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_INSERT_IDLE_FLAG_0 is + when FALSE => CLK_COR_INSERT_IDLE_FLAG_0_BINARY <= '0'; + when TRUE => CLK_COR_INSERT_IDLE_FLAG_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_INSERT_IDLE_FLAG_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_REPEAT_WAIT_0 is + when 0 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00000"; + when 1 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00001"; + when 2 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00010"; + when 3 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00011"; + when 4 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00100"; + when 5 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00101"; + when 6 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00110"; + when 7 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00111"; + when 8 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01000"; + when 9 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01001"; + when 10 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01010"; + when 11 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01011"; + when 12 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01100"; + when 13 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01101"; + when 14 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01110"; + when 15 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01111"; + when 16 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10000"; + when 17 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10001"; + when 18 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10010"; + when 19 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10011"; + when 20 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10100"; + when 21 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10101"; + when 22 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10110"; + when 23 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10111"; + when 24 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11000"; + when 25 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11001"; + when 26 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11010"; + when 27 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11011"; + when 28 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11100"; + when 29 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11101"; + when 30 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11110"; + when 31 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11111"; + when others => assert FALSE report "Error : CLK_COR_REPEAT_WAIT_0 is not in range 0...31." severity error; + end case; + case CLK_COR_SEQ_2_USE_0 is + when FALSE => CLK_COR_SEQ_2_USE_0_BINARY <= '0'; + when TRUE => CLK_COR_SEQ_2_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_SEQ_2_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_MIN_LAT_1 is + when 3 => CLK_COR_MIN_LAT_1_BINARY <= "000011"; + when 4 => CLK_COR_MIN_LAT_1_BINARY <= "000100"; + when 5 => CLK_COR_MIN_LAT_1_BINARY <= "000101"; + when 6 => CLK_COR_MIN_LAT_1_BINARY <= "000110"; + when 7 => CLK_COR_MIN_LAT_1_BINARY <= "000111"; + when 8 => CLK_COR_MIN_LAT_1_BINARY <= "001000"; + when 9 => CLK_COR_MIN_LAT_1_BINARY <= "001001"; + when 10 => CLK_COR_MIN_LAT_1_BINARY <= "001010"; + when 11 => CLK_COR_MIN_LAT_1_BINARY <= "001011"; + when 12 => CLK_COR_MIN_LAT_1_BINARY <= "001100"; + when 13 => CLK_COR_MIN_LAT_1_BINARY <= "001101"; + when 14 => CLK_COR_MIN_LAT_1_BINARY <= "001110"; + when 15 => CLK_COR_MIN_LAT_1_BINARY <= "001111"; + when 16 => CLK_COR_MIN_LAT_1_BINARY <= "010000"; + when 17 => CLK_COR_MIN_LAT_1_BINARY <= "010001"; + when 18 => CLK_COR_MIN_LAT_1_BINARY <= "010010"; + when 19 => CLK_COR_MIN_LAT_1_BINARY <= "010011"; + when 20 => CLK_COR_MIN_LAT_1_BINARY <= "010100"; + when 21 => CLK_COR_MIN_LAT_1_BINARY <= "010101"; + when 22 => CLK_COR_MIN_LAT_1_BINARY <= "010110"; + when 23 => CLK_COR_MIN_LAT_1_BINARY <= "010111"; + when 24 => CLK_COR_MIN_LAT_1_BINARY <= "011000"; + when 25 => CLK_COR_MIN_LAT_1_BINARY <= "011001"; + when 26 => CLK_COR_MIN_LAT_1_BINARY <= "011010"; + when 27 => CLK_COR_MIN_LAT_1_BINARY <= "011011"; + when 28 => CLK_COR_MIN_LAT_1_BINARY <= "011100"; + when 29 => CLK_COR_MIN_LAT_1_BINARY <= "011101"; + when 30 => CLK_COR_MIN_LAT_1_BINARY <= "011110"; + when 31 => CLK_COR_MIN_LAT_1_BINARY <= "011111"; + when 32 => CLK_COR_MIN_LAT_1_BINARY <= "100000"; + when 33 => CLK_COR_MIN_LAT_1_BINARY <= "100001"; + when 34 => CLK_COR_MIN_LAT_1_BINARY <= "100010"; + when 35 => CLK_COR_MIN_LAT_1_BINARY <= "100011"; + when 36 => CLK_COR_MIN_LAT_1_BINARY <= "100100"; + when 37 => CLK_COR_MIN_LAT_1_BINARY <= "100101"; + when 38 => CLK_COR_MIN_LAT_1_BINARY <= "100110"; + when 39 => CLK_COR_MIN_LAT_1_BINARY <= "100111"; + when 40 => CLK_COR_MIN_LAT_1_BINARY <= "101000"; + when 41 => CLK_COR_MIN_LAT_1_BINARY <= "101001"; + when 42 => CLK_COR_MIN_LAT_1_BINARY <= "101010"; + when 43 => CLK_COR_MIN_LAT_1_BINARY <= "101011"; + when 44 => CLK_COR_MIN_LAT_1_BINARY <= "101100"; + when 45 => CLK_COR_MIN_LAT_1_BINARY <= "101101"; + when 46 => CLK_COR_MIN_LAT_1_BINARY <= "101110"; + when 47 => CLK_COR_MIN_LAT_1_BINARY <= "101111"; + when 48 => CLK_COR_MIN_LAT_1_BINARY <= "110000"; + when others => assert FALSE report "Error : CLK_COR_MIN_LAT_1 is not in range 3...48." severity error; + end case; + case CLK_COR_MAX_LAT_1 is + when 3 => CLK_COR_MAX_LAT_1_BINARY <= "000011"; + when 4 => CLK_COR_MAX_LAT_1_BINARY <= "000100"; + when 5 => CLK_COR_MAX_LAT_1_BINARY <= "000101"; + when 6 => CLK_COR_MAX_LAT_1_BINARY <= "000110"; + when 7 => CLK_COR_MAX_LAT_1_BINARY <= "000111"; + when 8 => CLK_COR_MAX_LAT_1_BINARY <= "001000"; + when 9 => CLK_COR_MAX_LAT_1_BINARY <= "001001"; + when 10 => CLK_COR_MAX_LAT_1_BINARY <= "001010"; + when 11 => CLK_COR_MAX_LAT_1_BINARY <= "001011"; + when 12 => CLK_COR_MAX_LAT_1_BINARY <= "001100"; + when 13 => CLK_COR_MAX_LAT_1_BINARY <= "001101"; + when 14 => CLK_COR_MAX_LAT_1_BINARY <= "001110"; + when 15 => CLK_COR_MAX_LAT_1_BINARY <= "001111"; + when 16 => CLK_COR_MAX_LAT_1_BINARY <= "010000"; + when 17 => CLK_COR_MAX_LAT_1_BINARY <= "010001"; + when 18 => CLK_COR_MAX_LAT_1_BINARY <= "010010"; + when 19 => CLK_COR_MAX_LAT_1_BINARY <= "010011"; + when 20 => CLK_COR_MAX_LAT_1_BINARY <= "010100"; + when 21 => CLK_COR_MAX_LAT_1_BINARY <= "010101"; + when 22 => CLK_COR_MAX_LAT_1_BINARY <= "010110"; + when 23 => CLK_COR_MAX_LAT_1_BINARY <= "010111"; + when 24 => CLK_COR_MAX_LAT_1_BINARY <= "011000"; + when 25 => CLK_COR_MAX_LAT_1_BINARY <= "011001"; + when 26 => CLK_COR_MAX_LAT_1_BINARY <= "011010"; + when 27 => CLK_COR_MAX_LAT_1_BINARY <= "011011"; + when 28 => CLK_COR_MAX_LAT_1_BINARY <= "011100"; + when 29 => CLK_COR_MAX_LAT_1_BINARY <= "011101"; + when 30 => CLK_COR_MAX_LAT_1_BINARY <= "011110"; + when 31 => CLK_COR_MAX_LAT_1_BINARY <= "011111"; + when 32 => CLK_COR_MAX_LAT_1_BINARY <= "100000"; + when 33 => CLK_COR_MAX_LAT_1_BINARY <= "100001"; + when 34 => CLK_COR_MAX_LAT_1_BINARY <= "100010"; + when 35 => CLK_COR_MAX_LAT_1_BINARY <= "100011"; + when 36 => CLK_COR_MAX_LAT_1_BINARY <= "100100"; + when 37 => CLK_COR_MAX_LAT_1_BINARY <= "100101"; + when 38 => CLK_COR_MAX_LAT_1_BINARY <= "100110"; + when 39 => CLK_COR_MAX_LAT_1_BINARY <= "100111"; + when 40 => CLK_COR_MAX_LAT_1_BINARY <= "101000"; + when 41 => CLK_COR_MAX_LAT_1_BINARY <= "101001"; + when 42 => CLK_COR_MAX_LAT_1_BINARY <= "101010"; + when 43 => CLK_COR_MAX_LAT_1_BINARY <= "101011"; + when 44 => CLK_COR_MAX_LAT_1_BINARY <= "101100"; + when 45 => CLK_COR_MAX_LAT_1_BINARY <= "101101"; + when 46 => CLK_COR_MAX_LAT_1_BINARY <= "101110"; + when 47 => CLK_COR_MAX_LAT_1_BINARY <= "101111"; + when 48 => CLK_COR_MAX_LAT_1_BINARY <= "110000"; + when others => assert FALSE report "Error : CLK_COR_MAX_LAT_1 is not in range 3...48." severity error; + end case; + case CLK_CORRECT_USE_1 is + when FALSE => CLK_CORRECT_USE_1_BINARY <= '0'; + when TRUE => CLK_CORRECT_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_CORRECT_USE_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_PRECEDENCE_1 is + when FALSE => CLK_COR_PRECEDENCE_1_BINARY <= '0'; + when TRUE => CLK_COR_PRECEDENCE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_PRECEDENCE_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_DET_LEN_1 is + when 1 => CLK_COR_DET_LEN_1_BINARY <= "00"; + when 2 => CLK_COR_DET_LEN_1_BINARY <= "01"; + when 3 => CLK_COR_DET_LEN_1_BINARY <= "10"; + when 4 => CLK_COR_DET_LEN_1_BINARY <= "11"; + when others => assert FALSE report "Error : CLK_COR_DET_LEN_1 is not in 1, 2, 3, 4." severity error; + end case; + case CLK_COR_ADJ_LEN_1 is + when 1 => CLK_COR_ADJ_LEN_1_BINARY <= "00"; + when 2 => CLK_COR_ADJ_LEN_1_BINARY <= "01"; + when 3 => CLK_COR_ADJ_LEN_1_BINARY <= "10"; + when 4 => CLK_COR_ADJ_LEN_1_BINARY <= "11"; + when others => assert FALSE report "Error : CLK_COR_ADJ_LEN_1 is not in 1, 2, 3, 4." severity error; + end case; + case CLK_COR_KEEP_IDLE_1 is + when FALSE => CLK_COR_KEEP_IDLE_1_BINARY <= '0'; + when TRUE => CLK_COR_KEEP_IDLE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_KEEP_IDLE_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_INSERT_IDLE_FLAG_1 is + when FALSE => CLK_COR_INSERT_IDLE_FLAG_1_BINARY <= '0'; + when TRUE => CLK_COR_INSERT_IDLE_FLAG_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_INSERT_IDLE_FLAG_1 is neither TRUE nor FALSE." severity error; + end case; + case CLK_COR_REPEAT_WAIT_1 is + when 0 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00000"; + when 1 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00001"; + when 2 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00010"; + when 3 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00011"; + when 4 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00100"; + when 5 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00101"; + when 6 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00110"; + when 7 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00111"; + when 8 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01000"; + when 9 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01001"; + when 10 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01010"; + when 11 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01011"; + when 12 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01100"; + when 13 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01101"; + when 14 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01110"; + when 15 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01111"; + when 16 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10000"; + when 17 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10001"; + when 18 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10010"; + when 19 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10011"; + when 20 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10100"; + when 21 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10101"; + when 22 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10110"; + when 23 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10111"; + when 24 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11000"; + when 25 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11001"; + when 26 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11010"; + when 27 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11011"; + when 28 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11100"; + when 29 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11101"; + when 30 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11110"; + when 31 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11111"; + when others => assert FALSE report "Error : CLK_COR_REPEAT_WAIT_1 is not in range 0...31." severity error; + end case; + case CLK_COR_SEQ_2_USE_1 is + when FALSE => CLK_COR_SEQ_2_USE_1_BINARY <= '0'; + when TRUE => CLK_COR_SEQ_2_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CLK_COR_SEQ_2_USE_1 is neither TRUE nor FALSE." severity error; + end case; +-- case CHAN_BOND_MODE_0 is + if((CHAN_BOND_MODE_0 = "OFF") or (CHAN_BOND_MODE_0 = "off")) then + CHAN_BOND_MODE_0_BINARY <= "00"; + elsif((CHAN_BOND_MODE_0 = "MASTER") or (CHAN_BOND_MODE_0 = "master")) then + CHAN_BOND_MODE_0_BINARY <= "01"; + elsif((CHAN_BOND_MODE_0 = "SLAVE") or (CHAN_BOND_MODE_0 = "slave")) then + CHAN_BOND_MODE_0_BINARY <= "10"; + else + assert FALSE report "Error : CHAN_BOND_MODE_0 = is not OFF, MASTER, SLAVE." severity error; + end if; +-- end case; + case CHAN_BOND_LEVEL_0 is + when 0 => CHAN_BOND_LEVEL_0_BINARY <= "000"; + when 1 => CHAN_BOND_LEVEL_0_BINARY <= "001"; + when 2 => CHAN_BOND_LEVEL_0_BINARY <= "010"; + when 3 => CHAN_BOND_LEVEL_0_BINARY <= "011"; + when 4 => CHAN_BOND_LEVEL_0_BINARY <= "100"; + when 5 => CHAN_BOND_LEVEL_0_BINARY <= "101"; + when 6 => CHAN_BOND_LEVEL_0_BINARY <= "110"; + when 7 => CHAN_BOND_LEVEL_0_BINARY <= "111"; + when others => assert FALSE report "Error : CHAN_BOND_LEVEL_0 is not in range 0...7." severity error; + end case; + case CHAN_BOND_SEQ_LEN_0 is + when 1 => CHAN_BOND_SEQ_LEN_0_BINARY <= "00"; + when 2 => CHAN_BOND_SEQ_LEN_0_BINARY <= "01"; + when 3 => CHAN_BOND_SEQ_LEN_0_BINARY <= "10"; + when 4 => CHAN_BOND_SEQ_LEN_0_BINARY <= "11"; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_LEN_0 is not in 1, 2, 3, 4." severity error; + end case; + case CHAN_BOND_SEQ_2_USE_0 is + when FALSE => CHAN_BOND_SEQ_2_USE_0_BINARY <= '0'; + when TRUE => CHAN_BOND_SEQ_2_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_2_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case CHAN_BOND_1_MAX_SKEW_0 is + when 1 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0001"; + when 2 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0010"; + when 3 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0011"; + when 4 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0100"; + when 5 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0101"; + when 6 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0110"; + when 7 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0111"; + when 8 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1000"; + when 9 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1001"; + when 10 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1010"; + when 11 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1011"; + when 12 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1100"; + when 13 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1101"; + when 14 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1110"; + when others => assert FALSE report "Error : CHAN_BOND_1_MAX_SKEW_0 is not in range 1...14." severity error; + end case; + case CHAN_BOND_2_MAX_SKEW_0 is + when 1 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0001"; + when 2 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0010"; + when 3 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0011"; + when 4 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0100"; + when 5 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0101"; + when 6 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0110"; + when 7 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0111"; + when 8 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1000"; + when 9 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1001"; + when 10 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1010"; + when 11 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1011"; + when 12 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1100"; + when 13 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1101"; + when 14 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1110"; + when others => assert FALSE report "Error : CHAN_BOND_2_MAX_SKEW_0 is not in range 1...14." severity error; + end case; + case CHAN_BOND_KEEP_ALIGN_0 is + when FALSE => CHAN_BOND_KEEP_ALIGN_0_BINARY <= '0'; + when TRUE => CHAN_BOND_KEEP_ALIGN_0_BINARY <= '1'; + when others => assert FALSE report "Error : CHAN_BOND_KEEP_ALIGN_0 is neither TRUE nor FALSE." severity error; + end case; + case CB2_INH_CC_PERIOD_0 is + when 0 => CB2_INH_CC_PERIOD_0_BINARY <= "0000"; + when 1 => CB2_INH_CC_PERIOD_0_BINARY <= "0001"; + when 2 => CB2_INH_CC_PERIOD_0_BINARY <= "0010"; + when 3 => CB2_INH_CC_PERIOD_0_BINARY <= "0011"; + when 4 => CB2_INH_CC_PERIOD_0_BINARY <= "0100"; + when 5 => CB2_INH_CC_PERIOD_0_BINARY <= "0101"; + when 6 => CB2_INH_CC_PERIOD_0_BINARY <= "0110"; + when 7 => CB2_INH_CC_PERIOD_0_BINARY <= "0111"; + when 8 => CB2_INH_CC_PERIOD_0_BINARY <= "1000"; + when 9 => CB2_INH_CC_PERIOD_0_BINARY <= "1001"; + when 10 => CB2_INH_CC_PERIOD_0_BINARY <= "1010"; + when 11 => CB2_INH_CC_PERIOD_0_BINARY <= "1011"; + when 12 => CB2_INH_CC_PERIOD_0_BINARY <= "1100"; + when 13 => CB2_INH_CC_PERIOD_0_BINARY <= "1101"; + when 14 => CB2_INH_CC_PERIOD_0_BINARY <= "1110"; + when 15 => CB2_INH_CC_PERIOD_0_BINARY <= "1111"; + when others => assert FALSE report "Error : CB2_INH_CC_PERIOD_0 is not in range 0...15." severity error; + end case; +-- case CHAN_BOND_MODE_1 is + if((CHAN_BOND_MODE_1 = "OFF") or (CHAN_BOND_MODE_1 = "off")) then + CHAN_BOND_MODE_1_BINARY <= "00"; + elsif((CHAN_BOND_MODE_1 = "MASTER") or (CHAN_BOND_MODE_1 = "master")) then + CHAN_BOND_MODE_1_BINARY <= "01"; + elsif((CHAN_BOND_MODE_1 = "SLAVE") or (CHAN_BOND_MODE_1 = "slave")) then + CHAN_BOND_MODE_1_BINARY <= "10"; + else + assert FALSE report "Error : CHAN_BOND_MODE_1 = is not OFF, MASTER, SLAVE." severity error; + end if; +-- end case; + case CHAN_BOND_LEVEL_1 is + when 0 => CHAN_BOND_LEVEL_1_BINARY <= "000"; + when 1 => CHAN_BOND_LEVEL_1_BINARY <= "001"; + when 2 => CHAN_BOND_LEVEL_1_BINARY <= "010"; + when 3 => CHAN_BOND_LEVEL_1_BINARY <= "011"; + when 4 => CHAN_BOND_LEVEL_1_BINARY <= "100"; + when 5 => CHAN_BOND_LEVEL_1_BINARY <= "101"; + when 6 => CHAN_BOND_LEVEL_1_BINARY <= "110"; + when 7 => CHAN_BOND_LEVEL_1_BINARY <= "111"; + when others => assert FALSE report "Error : CHAN_BOND_LEVEL_1 is not in range 0...7." severity error; + end case; + case CHAN_BOND_SEQ_LEN_1 is + when 1 => CHAN_BOND_SEQ_LEN_1_BINARY <= "00"; + when 2 => CHAN_BOND_SEQ_LEN_1_BINARY <= "01"; + when 3 => CHAN_BOND_SEQ_LEN_1_BINARY <= "10"; + when 4 => CHAN_BOND_SEQ_LEN_1_BINARY <= "11"; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_LEN_1 is not in 1, 2, 3, 4." severity error; + end case; + case CHAN_BOND_SEQ_2_USE_1 is + when FALSE => CHAN_BOND_SEQ_2_USE_1_BINARY <= '0'; + when TRUE => CHAN_BOND_SEQ_2_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : CHAN_BOND_SEQ_2_USE_1 is neither TRUE nor FALSE." severity error; + end case; + case CHAN_BOND_1_MAX_SKEW_1 is + when 1 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0001"; + when 2 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0010"; + when 3 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0011"; + when 4 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0100"; + when 5 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0101"; + when 6 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0110"; + when 7 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0111"; + when 8 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1000"; + when 9 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1001"; + when 10 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1010"; + when 11 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1011"; + when 12 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1100"; + when 13 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1101"; + when 14 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1110"; + when others => assert FALSE report "Error : CHAN_BOND_1_MAX_SKEW_1 is not in range 1...14." severity error; + end case; + case CHAN_BOND_2_MAX_SKEW_1 is + when 1 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0001"; + when 2 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0010"; + when 3 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0011"; + when 4 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0100"; + when 5 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0101"; + when 6 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0110"; + when 7 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0111"; + when 8 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1000"; + when 9 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1001"; + when 10 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1010"; + when 11 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1011"; + when 12 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1100"; + when 13 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1101"; + when 14 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1110"; + when others => assert FALSE report "Error : CHAN_BOND_2_MAX_SKEW_1 is not in range 1...14." severity error; + end case; + case CHAN_BOND_KEEP_ALIGN_1 is + when FALSE => CHAN_BOND_KEEP_ALIGN_1_BINARY <= '0'; + when TRUE => CHAN_BOND_KEEP_ALIGN_1_BINARY <= '1'; + when others => assert FALSE report "Error : CHAN_BOND_KEEP_ALIGN_1 is neither TRUE nor FALSE." severity error; + end case; + case CB2_INH_CC_PERIOD_1 is + when 0 => CB2_INH_CC_PERIOD_1_BINARY <= "0000"; + when 1 => CB2_INH_CC_PERIOD_1_BINARY <= "0001"; + when 2 => CB2_INH_CC_PERIOD_1_BINARY <= "0010"; + when 3 => CB2_INH_CC_PERIOD_1_BINARY <= "0011"; + when 4 => CB2_INH_CC_PERIOD_1_BINARY <= "0100"; + when 5 => CB2_INH_CC_PERIOD_1_BINARY <= "0101"; + when 6 => CB2_INH_CC_PERIOD_1_BINARY <= "0110"; + when 7 => CB2_INH_CC_PERIOD_1_BINARY <= "0111"; + when 8 => CB2_INH_CC_PERIOD_1_BINARY <= "1000"; + when 9 => CB2_INH_CC_PERIOD_1_BINARY <= "1001"; + when 10 => CB2_INH_CC_PERIOD_1_BINARY <= "1010"; + when 11 => CB2_INH_CC_PERIOD_1_BINARY <= "1011"; + when 12 => CB2_INH_CC_PERIOD_1_BINARY <= "1100"; + when 13 => CB2_INH_CC_PERIOD_1_BINARY <= "1101"; + when 14 => CB2_INH_CC_PERIOD_1_BINARY <= "1110"; + when 15 => CB2_INH_CC_PERIOD_1_BINARY <= "1111"; + when others => assert FALSE report "Error : CB2_INH_CC_PERIOD_1 is not in range 0...15." severity error; + end case; + case PCI_EXPRESS_MODE_0 is + when FALSE => PCI_EXPRESS_MODE_0_BINARY <= '0'; + when TRUE => PCI_EXPRESS_MODE_0_BINARY <= '1'; + when others => assert FALSE report "Error : PCI_EXPRESS_MODE_0 is neither TRUE nor FALSE." severity error; + end case; + case PCI_EXPRESS_MODE_1 is + when FALSE => PCI_EXPRESS_MODE_1_BINARY <= '0'; + when TRUE => PCI_EXPRESS_MODE_1_BINARY <= '1'; + when others => assert FALSE report "Error : PCI_EXPRESS_MODE_1 is neither TRUE nor FALSE." severity error; + end case; +-- case RX_STATUS_FMT_0 is + if((RX_STATUS_FMT_0 = "PCIE") or (RX_STATUS_FMT_0 = "pcie")) then + RX_STATUS_FMT_0_BINARY <= '0'; + elsif((RX_STATUS_FMT_0 = "SATA") or (RX_STATUS_FMT_0 = "sata")) then + RX_STATUS_FMT_0_BINARY <= '1'; + else + assert FALSE report "Error : RX_STATUS_FMT_0 = is not PCIE, SATA." severity error; + end if; +-- end case; + case TX_BUFFER_USE_0 is + when FALSE => TX_BUFFER_USE_0_BINARY <= '0'; + when TRUE => TX_BUFFER_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : TX_BUFFER_USE_0 is neither TRUE nor FALSE." severity error; + end case; +-- case TX_XCLK_SEL_0 is + if((TX_XCLK_SEL_0 = "TXUSR") or (TX_XCLK_SEL_0 = "txusr")) then + TX_XCLK_SEL_0_BINARY <= '1'; + elsif((TX_XCLK_SEL_0 = "TXOUT") or (TX_XCLK_SEL_0 = "txout")) then + TX_XCLK_SEL_0_BINARY <= '0'; + else + assert FALSE report "Error : TX_XCLK_SEL_0 = is not TXUSR, TXOUT." severity error; + end if; +-- end case; +-- case RX_XCLK_SEL_0 is + if((RX_XCLK_SEL_0 = "RXREC") or (RX_XCLK_SEL_0 = "rxrec")) then + RX_XCLK_SEL_0_BINARY <= '0'; + elsif((RX_XCLK_SEL_0 = "RXUSR") or (RX_XCLK_SEL_0 = "rxusr")) then + RX_XCLK_SEL_0_BINARY <= '1'; + else + assert FALSE report "Error : RX_XCLK_SEL_0 = is not RXREC, RXUSR." severity error; + end if; +-- end case; +-- case RX_STATUS_FMT_1 is + if((RX_STATUS_FMT_1 = "PCIE") or (RX_STATUS_FMT_1 = "pcie")) then + RX_STATUS_FMT_1_BINARY <= '0'; + elsif((RX_STATUS_FMT_1 = "SATA") or (RX_STATUS_FMT_1 = "sata")) then + RX_STATUS_FMT_1_BINARY <= '1'; + else + assert FALSE report "Error : RX_STATUS_FMT_1 = is not PCIE, SATA." severity error; + end if; +-- end case; + case TX_BUFFER_USE_1 is + when FALSE => TX_BUFFER_USE_1_BINARY <= '0'; + when TRUE => TX_BUFFER_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : TX_BUFFER_USE_1 is neither TRUE nor FALSE." severity error; + end case; +-- case TX_XCLK_SEL_1 is + if((TX_XCLK_SEL_1 = "TXUSR") or (TX_XCLK_SEL_1 = "txusr")) then + TX_XCLK_SEL_1_BINARY <= '1'; + elsif((TX_XCLK_SEL_1 = "TXOUT") or (TX_XCLK_SEL_1 = "txout")) then + TX_XCLK_SEL_1_BINARY <= '0'; + else + assert FALSE report "Error : TX_XCLK_SEL_1 = is not TXUSR, TXOUT." severity error; + end if; +-- end case; +-- case RX_XCLK_SEL_1 is + if((RX_XCLK_SEL_1 = "RXREC") or (RX_XCLK_SEL_1 = "rxrec")) then + RX_XCLK_SEL_1_BINARY <= '0'; + elsif((RX_XCLK_SEL_1 = "RXUSR") or (RX_XCLK_SEL_1 = "rxusr")) then + RX_XCLK_SEL_1_BINARY <= '1'; + else + assert FALSE report "Error : RX_XCLK_SEL_1 = is not RXREC, RXUSR." severity error; + end if; +-- end case; +-- case RX_SLIDE_MODE_0 is + if((RX_SLIDE_MODE_0 = "PCS") or (RX_SLIDE_MODE_0 = "pcs")) then + RX_SLIDE_MODE_0_BINARY <= '0'; + elsif((RX_SLIDE_MODE_0 = "PMA") or (RX_SLIDE_MODE_0 = "pma")) then + RX_SLIDE_MODE_0_BINARY <= '1'; + else + assert FALSE report "Error : RX_SLIDE_MODE_0 = is not PCS, PMA." severity error; + end if; +-- end case; +-- case RX_SLIDE_MODE_1 is + if((RX_SLIDE_MODE_1 = "PCS") or (RX_SLIDE_MODE_1 = "pcs")) then + RX_SLIDE_MODE_1_BINARY <= '0'; + elsif((RX_SLIDE_MODE_1 = "PMA") or (RX_SLIDE_MODE_1 = "pma")) then + RX_SLIDE_MODE_1_BINARY <= '1'; + else + assert FALSE report "Error : RX_SLIDE_MODE_1 = is not PCS, PMA." severity error; + end if; +-- end case; + case SATA_MIN_BURST_0 is + when 1 => SATA_MIN_BURST_0_BINARY <= "000001"; + when 2 => SATA_MIN_BURST_0_BINARY <= "000010"; + when 3 => SATA_MIN_BURST_0_BINARY <= "000011"; + when 4 => SATA_MIN_BURST_0_BINARY <= "000100"; + when 5 => SATA_MIN_BURST_0_BINARY <= "000101"; + when 6 => SATA_MIN_BURST_0_BINARY <= "000110"; + when 7 => SATA_MIN_BURST_0_BINARY <= "000111"; + when 8 => SATA_MIN_BURST_0_BINARY <= "001000"; + when 9 => SATA_MIN_BURST_0_BINARY <= "001001"; + when 10 => SATA_MIN_BURST_0_BINARY <= "001010"; + when 11 => SATA_MIN_BURST_0_BINARY <= "001011"; + when 12 => SATA_MIN_BURST_0_BINARY <= "001100"; + when 13 => SATA_MIN_BURST_0_BINARY <= "001101"; + when 14 => SATA_MIN_BURST_0_BINARY <= "001110"; + when 15 => SATA_MIN_BURST_0_BINARY <= "001111"; + when 16 => SATA_MIN_BURST_0_BINARY <= "010000"; + when 17 => SATA_MIN_BURST_0_BINARY <= "010001"; + when 18 => SATA_MIN_BURST_0_BINARY <= "010010"; + when 19 => SATA_MIN_BURST_0_BINARY <= "010011"; + when 20 => SATA_MIN_BURST_0_BINARY <= "010100"; + when 21 => SATA_MIN_BURST_0_BINARY <= "010101"; + when 22 => SATA_MIN_BURST_0_BINARY <= "010110"; + when 23 => SATA_MIN_BURST_0_BINARY <= "010111"; + when 24 => SATA_MIN_BURST_0_BINARY <= "011000"; + when 25 => SATA_MIN_BURST_0_BINARY <= "011001"; + when 26 => SATA_MIN_BURST_0_BINARY <= "011010"; + when 27 => SATA_MIN_BURST_0_BINARY <= "011011"; + when 28 => SATA_MIN_BURST_0_BINARY <= "011100"; + when 29 => SATA_MIN_BURST_0_BINARY <= "011101"; + when 30 => SATA_MIN_BURST_0_BINARY <= "011110"; + when 31 => SATA_MIN_BURST_0_BINARY <= "011111"; + when 32 => SATA_MIN_BURST_0_BINARY <= "100000"; + when 33 => SATA_MIN_BURST_0_BINARY <= "100001"; + when 34 => SATA_MIN_BURST_0_BINARY <= "100010"; + when 35 => SATA_MIN_BURST_0_BINARY <= "100011"; + when 36 => SATA_MIN_BURST_0_BINARY <= "100100"; + when 37 => SATA_MIN_BURST_0_BINARY <= "100101"; + when 38 => SATA_MIN_BURST_0_BINARY <= "100110"; + when 39 => SATA_MIN_BURST_0_BINARY <= "100111"; + when 40 => SATA_MIN_BURST_0_BINARY <= "101000"; + when 41 => SATA_MIN_BURST_0_BINARY <= "101001"; + when 42 => SATA_MIN_BURST_0_BINARY <= "101010"; + when 43 => SATA_MIN_BURST_0_BINARY <= "101011"; + when 44 => SATA_MIN_BURST_0_BINARY <= "101100"; + when 45 => SATA_MIN_BURST_0_BINARY <= "101101"; + when 46 => SATA_MIN_BURST_0_BINARY <= "101110"; + when 47 => SATA_MIN_BURST_0_BINARY <= "101111"; + when 48 => SATA_MIN_BURST_0_BINARY <= "110000"; + when 49 => SATA_MIN_BURST_0_BINARY <= "110001"; + when 50 => SATA_MIN_BURST_0_BINARY <= "110010"; + when 51 => SATA_MIN_BURST_0_BINARY <= "110011"; + when 52 => SATA_MIN_BURST_0_BINARY <= "110100"; + when 53 => SATA_MIN_BURST_0_BINARY <= "110101"; + when 54 => SATA_MIN_BURST_0_BINARY <= "110110"; + when 55 => SATA_MIN_BURST_0_BINARY <= "110111"; + when 56 => SATA_MIN_BURST_0_BINARY <= "111000"; + when 57 => SATA_MIN_BURST_0_BINARY <= "111001"; + when 58 => SATA_MIN_BURST_0_BINARY <= "111010"; + when 59 => SATA_MIN_BURST_0_BINARY <= "111011"; + when 60 => SATA_MIN_BURST_0_BINARY <= "111100"; + when 61 => SATA_MIN_BURST_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_BURST_0 is not in range 1...61." severity error; + end case; + case SATA_MAX_BURST_0 is + when 1 => SATA_MAX_BURST_0_BINARY <= "000001"; + when 2 => SATA_MAX_BURST_0_BINARY <= "000010"; + when 3 => SATA_MAX_BURST_0_BINARY <= "000011"; + when 4 => SATA_MAX_BURST_0_BINARY <= "000100"; + when 5 => SATA_MAX_BURST_0_BINARY <= "000101"; + when 6 => SATA_MAX_BURST_0_BINARY <= "000110"; + when 7 => SATA_MAX_BURST_0_BINARY <= "000111"; + when 8 => SATA_MAX_BURST_0_BINARY <= "001000"; + when 9 => SATA_MAX_BURST_0_BINARY <= "001001"; + when 10 => SATA_MAX_BURST_0_BINARY <= "001010"; + when 11 => SATA_MAX_BURST_0_BINARY <= "001011"; + when 12 => SATA_MAX_BURST_0_BINARY <= "001100"; + when 13 => SATA_MAX_BURST_0_BINARY <= "001101"; + when 14 => SATA_MAX_BURST_0_BINARY <= "001110"; + when 15 => SATA_MAX_BURST_0_BINARY <= "001111"; + when 16 => SATA_MAX_BURST_0_BINARY <= "010000"; + when 17 => SATA_MAX_BURST_0_BINARY <= "010001"; + when 18 => SATA_MAX_BURST_0_BINARY <= "010010"; + when 19 => SATA_MAX_BURST_0_BINARY <= "010011"; + when 20 => SATA_MAX_BURST_0_BINARY <= "010100"; + when 21 => SATA_MAX_BURST_0_BINARY <= "010101"; + when 22 => SATA_MAX_BURST_0_BINARY <= "010110"; + when 23 => SATA_MAX_BURST_0_BINARY <= "010111"; + when 24 => SATA_MAX_BURST_0_BINARY <= "011000"; + when 25 => SATA_MAX_BURST_0_BINARY <= "011001"; + when 26 => SATA_MAX_BURST_0_BINARY <= "011010"; + when 27 => SATA_MAX_BURST_0_BINARY <= "011011"; + when 28 => SATA_MAX_BURST_0_BINARY <= "011100"; + when 29 => SATA_MAX_BURST_0_BINARY <= "011101"; + when 30 => SATA_MAX_BURST_0_BINARY <= "011110"; + when 31 => SATA_MAX_BURST_0_BINARY <= "011111"; + when 32 => SATA_MAX_BURST_0_BINARY <= "100000"; + when 33 => SATA_MAX_BURST_0_BINARY <= "100001"; + when 34 => SATA_MAX_BURST_0_BINARY <= "100010"; + when 35 => SATA_MAX_BURST_0_BINARY <= "100011"; + when 36 => SATA_MAX_BURST_0_BINARY <= "100100"; + when 37 => SATA_MAX_BURST_0_BINARY <= "100101"; + when 38 => SATA_MAX_BURST_0_BINARY <= "100110"; + when 39 => SATA_MAX_BURST_0_BINARY <= "100111"; + when 40 => SATA_MAX_BURST_0_BINARY <= "101000"; + when 41 => SATA_MAX_BURST_0_BINARY <= "101001"; + when 42 => SATA_MAX_BURST_0_BINARY <= "101010"; + when 43 => SATA_MAX_BURST_0_BINARY <= "101011"; + when 44 => SATA_MAX_BURST_0_BINARY <= "101100"; + when 45 => SATA_MAX_BURST_0_BINARY <= "101101"; + when 46 => SATA_MAX_BURST_0_BINARY <= "101110"; + when 47 => SATA_MAX_BURST_0_BINARY <= "101111"; + when 48 => SATA_MAX_BURST_0_BINARY <= "110000"; + when 49 => SATA_MAX_BURST_0_BINARY <= "110001"; + when 50 => SATA_MAX_BURST_0_BINARY <= "110010"; + when 51 => SATA_MAX_BURST_0_BINARY <= "110011"; + when 52 => SATA_MAX_BURST_0_BINARY <= "110100"; + when 53 => SATA_MAX_BURST_0_BINARY <= "110101"; + when 54 => SATA_MAX_BURST_0_BINARY <= "110110"; + when 55 => SATA_MAX_BURST_0_BINARY <= "110111"; + when 56 => SATA_MAX_BURST_0_BINARY <= "111000"; + when 57 => SATA_MAX_BURST_0_BINARY <= "111001"; + when 58 => SATA_MAX_BURST_0_BINARY <= "111010"; + when 59 => SATA_MAX_BURST_0_BINARY <= "111011"; + when 60 => SATA_MAX_BURST_0_BINARY <= "111100"; + when 61 => SATA_MAX_BURST_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_BURST_0 is not in range 1...61." severity error; + end case; + case SATA_MIN_INIT_0 is + when 1 => SATA_MIN_INIT_0_BINARY <= "000001"; + when 2 => SATA_MIN_INIT_0_BINARY <= "000010"; + when 3 => SATA_MIN_INIT_0_BINARY <= "000011"; + when 4 => SATA_MIN_INIT_0_BINARY <= "000100"; + when 5 => SATA_MIN_INIT_0_BINARY <= "000101"; + when 6 => SATA_MIN_INIT_0_BINARY <= "000110"; + when 7 => SATA_MIN_INIT_0_BINARY <= "000111"; + when 8 => SATA_MIN_INIT_0_BINARY <= "001000"; + when 9 => SATA_MIN_INIT_0_BINARY <= "001001"; + when 10 => SATA_MIN_INIT_0_BINARY <= "001010"; + when 11 => SATA_MIN_INIT_0_BINARY <= "001011"; + when 12 => SATA_MIN_INIT_0_BINARY <= "001100"; + when 13 => SATA_MIN_INIT_0_BINARY <= "001101"; + when 14 => SATA_MIN_INIT_0_BINARY <= "001110"; + when 15 => SATA_MIN_INIT_0_BINARY <= "001111"; + when 16 => SATA_MIN_INIT_0_BINARY <= "010000"; + when 17 => SATA_MIN_INIT_0_BINARY <= "010001"; + when 18 => SATA_MIN_INIT_0_BINARY <= "010010"; + when 19 => SATA_MIN_INIT_0_BINARY <= "010011"; + when 20 => SATA_MIN_INIT_0_BINARY <= "010100"; + when 21 => SATA_MIN_INIT_0_BINARY <= "010101"; + when 22 => SATA_MIN_INIT_0_BINARY <= "010110"; + when 23 => SATA_MIN_INIT_0_BINARY <= "010111"; + when 24 => SATA_MIN_INIT_0_BINARY <= "011000"; + when 25 => SATA_MIN_INIT_0_BINARY <= "011001"; + when 26 => SATA_MIN_INIT_0_BINARY <= "011010"; + when 27 => SATA_MIN_INIT_0_BINARY <= "011011"; + when 28 => SATA_MIN_INIT_0_BINARY <= "011100"; + when 29 => SATA_MIN_INIT_0_BINARY <= "011101"; + when 30 => SATA_MIN_INIT_0_BINARY <= "011110"; + when 31 => SATA_MIN_INIT_0_BINARY <= "011111"; + when 32 => SATA_MIN_INIT_0_BINARY <= "100000"; + when 33 => SATA_MIN_INIT_0_BINARY <= "100001"; + when 34 => SATA_MIN_INIT_0_BINARY <= "100010"; + when 35 => SATA_MIN_INIT_0_BINARY <= "100011"; + when 36 => SATA_MIN_INIT_0_BINARY <= "100100"; + when 37 => SATA_MIN_INIT_0_BINARY <= "100101"; + when 38 => SATA_MIN_INIT_0_BINARY <= "100110"; + when 39 => SATA_MIN_INIT_0_BINARY <= "100111"; + when 40 => SATA_MIN_INIT_0_BINARY <= "101000"; + when 41 => SATA_MIN_INIT_0_BINARY <= "101001"; + when 42 => SATA_MIN_INIT_0_BINARY <= "101010"; + when 43 => SATA_MIN_INIT_0_BINARY <= "101011"; + when 44 => SATA_MIN_INIT_0_BINARY <= "101100"; + when 45 => SATA_MIN_INIT_0_BINARY <= "101101"; + when 46 => SATA_MIN_INIT_0_BINARY <= "101110"; + when 47 => SATA_MIN_INIT_0_BINARY <= "101111"; + when 48 => SATA_MIN_INIT_0_BINARY <= "110000"; + when 49 => SATA_MIN_INIT_0_BINARY <= "110001"; + when 50 => SATA_MIN_INIT_0_BINARY <= "110010"; + when 51 => SATA_MIN_INIT_0_BINARY <= "110011"; + when 52 => SATA_MIN_INIT_0_BINARY <= "110100"; + when 53 => SATA_MIN_INIT_0_BINARY <= "110101"; + when 54 => SATA_MIN_INIT_0_BINARY <= "110110"; + when 55 => SATA_MIN_INIT_0_BINARY <= "110111"; + when 56 => SATA_MIN_INIT_0_BINARY <= "111000"; + when 57 => SATA_MIN_INIT_0_BINARY <= "111001"; + when 58 => SATA_MIN_INIT_0_BINARY <= "111010"; + when 59 => SATA_MIN_INIT_0_BINARY <= "111011"; + when 60 => SATA_MIN_INIT_0_BINARY <= "111100"; + when 61 => SATA_MIN_INIT_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_INIT_0 is not in range 1...61." severity error; + end case; + case SATA_MAX_INIT_0 is + when 1 => SATA_MAX_INIT_0_BINARY <= "000001"; + when 2 => SATA_MAX_INIT_0_BINARY <= "000010"; + when 3 => SATA_MAX_INIT_0_BINARY <= "000011"; + when 4 => SATA_MAX_INIT_0_BINARY <= "000100"; + when 5 => SATA_MAX_INIT_0_BINARY <= "000101"; + when 6 => SATA_MAX_INIT_0_BINARY <= "000110"; + when 7 => SATA_MAX_INIT_0_BINARY <= "000111"; + when 8 => SATA_MAX_INIT_0_BINARY <= "001000"; + when 9 => SATA_MAX_INIT_0_BINARY <= "001001"; + when 10 => SATA_MAX_INIT_0_BINARY <= "001010"; + when 11 => SATA_MAX_INIT_0_BINARY <= "001011"; + when 12 => SATA_MAX_INIT_0_BINARY <= "001100"; + when 13 => SATA_MAX_INIT_0_BINARY <= "001101"; + when 14 => SATA_MAX_INIT_0_BINARY <= "001110"; + when 15 => SATA_MAX_INIT_0_BINARY <= "001111"; + when 16 => SATA_MAX_INIT_0_BINARY <= "010000"; + when 17 => SATA_MAX_INIT_0_BINARY <= "010001"; + when 18 => SATA_MAX_INIT_0_BINARY <= "010010"; + when 19 => SATA_MAX_INIT_0_BINARY <= "010011"; + when 20 => SATA_MAX_INIT_0_BINARY <= "010100"; + when 21 => SATA_MAX_INIT_0_BINARY <= "010101"; + when 22 => SATA_MAX_INIT_0_BINARY <= "010110"; + when 23 => SATA_MAX_INIT_0_BINARY <= "010111"; + when 24 => SATA_MAX_INIT_0_BINARY <= "011000"; + when 25 => SATA_MAX_INIT_0_BINARY <= "011001"; + when 26 => SATA_MAX_INIT_0_BINARY <= "011010"; + when 27 => SATA_MAX_INIT_0_BINARY <= "011011"; + when 28 => SATA_MAX_INIT_0_BINARY <= "011100"; + when 29 => SATA_MAX_INIT_0_BINARY <= "011101"; + when 30 => SATA_MAX_INIT_0_BINARY <= "011110"; + when 31 => SATA_MAX_INIT_0_BINARY <= "011111"; + when 32 => SATA_MAX_INIT_0_BINARY <= "100000"; + when 33 => SATA_MAX_INIT_0_BINARY <= "100001"; + when 34 => SATA_MAX_INIT_0_BINARY <= "100010"; + when 35 => SATA_MAX_INIT_0_BINARY <= "100011"; + when 36 => SATA_MAX_INIT_0_BINARY <= "100100"; + when 37 => SATA_MAX_INIT_0_BINARY <= "100101"; + when 38 => SATA_MAX_INIT_0_BINARY <= "100110"; + when 39 => SATA_MAX_INIT_0_BINARY <= "100111"; + when 40 => SATA_MAX_INIT_0_BINARY <= "101000"; + when 41 => SATA_MAX_INIT_0_BINARY <= "101001"; + when 42 => SATA_MAX_INIT_0_BINARY <= "101010"; + when 43 => SATA_MAX_INIT_0_BINARY <= "101011"; + when 44 => SATA_MAX_INIT_0_BINARY <= "101100"; + when 45 => SATA_MAX_INIT_0_BINARY <= "101101"; + when 46 => SATA_MAX_INIT_0_BINARY <= "101110"; + when 47 => SATA_MAX_INIT_0_BINARY <= "101111"; + when 48 => SATA_MAX_INIT_0_BINARY <= "110000"; + when 49 => SATA_MAX_INIT_0_BINARY <= "110001"; + when 50 => SATA_MAX_INIT_0_BINARY <= "110010"; + when 51 => SATA_MAX_INIT_0_BINARY <= "110011"; + when 52 => SATA_MAX_INIT_0_BINARY <= "110100"; + when 53 => SATA_MAX_INIT_0_BINARY <= "110101"; + when 54 => SATA_MAX_INIT_0_BINARY <= "110110"; + when 55 => SATA_MAX_INIT_0_BINARY <= "110111"; + when 56 => SATA_MAX_INIT_0_BINARY <= "111000"; + when 57 => SATA_MAX_INIT_0_BINARY <= "111001"; + when 58 => SATA_MAX_INIT_0_BINARY <= "111010"; + when 59 => SATA_MAX_INIT_0_BINARY <= "111011"; + when 60 => SATA_MAX_INIT_0_BINARY <= "111100"; + when 61 => SATA_MAX_INIT_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_INIT_0 is not in range 1...61." severity error; + end case; + case SATA_MIN_WAKE_0 is + when 1 => SATA_MIN_WAKE_0_BINARY <= "000001"; + when 2 => SATA_MIN_WAKE_0_BINARY <= "000010"; + when 3 => SATA_MIN_WAKE_0_BINARY <= "000011"; + when 4 => SATA_MIN_WAKE_0_BINARY <= "000100"; + when 5 => SATA_MIN_WAKE_0_BINARY <= "000101"; + when 6 => SATA_MIN_WAKE_0_BINARY <= "000110"; + when 7 => SATA_MIN_WAKE_0_BINARY <= "000111"; + when 8 => SATA_MIN_WAKE_0_BINARY <= "001000"; + when 9 => SATA_MIN_WAKE_0_BINARY <= "001001"; + when 10 => SATA_MIN_WAKE_0_BINARY <= "001010"; + when 11 => SATA_MIN_WAKE_0_BINARY <= "001011"; + when 12 => SATA_MIN_WAKE_0_BINARY <= "001100"; + when 13 => SATA_MIN_WAKE_0_BINARY <= "001101"; + when 14 => SATA_MIN_WAKE_0_BINARY <= "001110"; + when 15 => SATA_MIN_WAKE_0_BINARY <= "001111"; + when 16 => SATA_MIN_WAKE_0_BINARY <= "010000"; + when 17 => SATA_MIN_WAKE_0_BINARY <= "010001"; + when 18 => SATA_MIN_WAKE_0_BINARY <= "010010"; + when 19 => SATA_MIN_WAKE_0_BINARY <= "010011"; + when 20 => SATA_MIN_WAKE_0_BINARY <= "010100"; + when 21 => SATA_MIN_WAKE_0_BINARY <= "010101"; + when 22 => SATA_MIN_WAKE_0_BINARY <= "010110"; + when 23 => SATA_MIN_WAKE_0_BINARY <= "010111"; + when 24 => SATA_MIN_WAKE_0_BINARY <= "011000"; + when 25 => SATA_MIN_WAKE_0_BINARY <= "011001"; + when 26 => SATA_MIN_WAKE_0_BINARY <= "011010"; + when 27 => SATA_MIN_WAKE_0_BINARY <= "011011"; + when 28 => SATA_MIN_WAKE_0_BINARY <= "011100"; + when 29 => SATA_MIN_WAKE_0_BINARY <= "011101"; + when 30 => SATA_MIN_WAKE_0_BINARY <= "011110"; + when 31 => SATA_MIN_WAKE_0_BINARY <= "011111"; + when 32 => SATA_MIN_WAKE_0_BINARY <= "100000"; + when 33 => SATA_MIN_WAKE_0_BINARY <= "100001"; + when 34 => SATA_MIN_WAKE_0_BINARY <= "100010"; + when 35 => SATA_MIN_WAKE_0_BINARY <= "100011"; + when 36 => SATA_MIN_WAKE_0_BINARY <= "100100"; + when 37 => SATA_MIN_WAKE_0_BINARY <= "100101"; + when 38 => SATA_MIN_WAKE_0_BINARY <= "100110"; + when 39 => SATA_MIN_WAKE_0_BINARY <= "100111"; + when 40 => SATA_MIN_WAKE_0_BINARY <= "101000"; + when 41 => SATA_MIN_WAKE_0_BINARY <= "101001"; + when 42 => SATA_MIN_WAKE_0_BINARY <= "101010"; + when 43 => SATA_MIN_WAKE_0_BINARY <= "101011"; + when 44 => SATA_MIN_WAKE_0_BINARY <= "101100"; + when 45 => SATA_MIN_WAKE_0_BINARY <= "101101"; + when 46 => SATA_MIN_WAKE_0_BINARY <= "101110"; + when 47 => SATA_MIN_WAKE_0_BINARY <= "101111"; + when 48 => SATA_MIN_WAKE_0_BINARY <= "110000"; + when 49 => SATA_MIN_WAKE_0_BINARY <= "110001"; + when 50 => SATA_MIN_WAKE_0_BINARY <= "110010"; + when 51 => SATA_MIN_WAKE_0_BINARY <= "110011"; + when 52 => SATA_MIN_WAKE_0_BINARY <= "110100"; + when 53 => SATA_MIN_WAKE_0_BINARY <= "110101"; + when 54 => SATA_MIN_WAKE_0_BINARY <= "110110"; + when 55 => SATA_MIN_WAKE_0_BINARY <= "110111"; + when 56 => SATA_MIN_WAKE_0_BINARY <= "111000"; + when 57 => SATA_MIN_WAKE_0_BINARY <= "111001"; + when 58 => SATA_MIN_WAKE_0_BINARY <= "111010"; + when 59 => SATA_MIN_WAKE_0_BINARY <= "111011"; + when 60 => SATA_MIN_WAKE_0_BINARY <= "111100"; + when 61 => SATA_MIN_WAKE_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_WAKE_0 is not in range 1...61." severity error; + end case; + case SATA_MAX_WAKE_0 is + when 1 => SATA_MAX_WAKE_0_BINARY <= "000001"; + when 2 => SATA_MAX_WAKE_0_BINARY <= "000010"; + when 3 => SATA_MAX_WAKE_0_BINARY <= "000011"; + when 4 => SATA_MAX_WAKE_0_BINARY <= "000100"; + when 5 => SATA_MAX_WAKE_0_BINARY <= "000101"; + when 6 => SATA_MAX_WAKE_0_BINARY <= "000110"; + when 7 => SATA_MAX_WAKE_0_BINARY <= "000111"; + when 8 => SATA_MAX_WAKE_0_BINARY <= "001000"; + when 9 => SATA_MAX_WAKE_0_BINARY <= "001001"; + when 10 => SATA_MAX_WAKE_0_BINARY <= "001010"; + when 11 => SATA_MAX_WAKE_0_BINARY <= "001011"; + when 12 => SATA_MAX_WAKE_0_BINARY <= "001100"; + when 13 => SATA_MAX_WAKE_0_BINARY <= "001101"; + when 14 => SATA_MAX_WAKE_0_BINARY <= "001110"; + when 15 => SATA_MAX_WAKE_0_BINARY <= "001111"; + when 16 => SATA_MAX_WAKE_0_BINARY <= "010000"; + when 17 => SATA_MAX_WAKE_0_BINARY <= "010001"; + when 18 => SATA_MAX_WAKE_0_BINARY <= "010010"; + when 19 => SATA_MAX_WAKE_0_BINARY <= "010011"; + when 20 => SATA_MAX_WAKE_0_BINARY <= "010100"; + when 21 => SATA_MAX_WAKE_0_BINARY <= "010101"; + when 22 => SATA_MAX_WAKE_0_BINARY <= "010110"; + when 23 => SATA_MAX_WAKE_0_BINARY <= "010111"; + when 24 => SATA_MAX_WAKE_0_BINARY <= "011000"; + when 25 => SATA_MAX_WAKE_0_BINARY <= "011001"; + when 26 => SATA_MAX_WAKE_0_BINARY <= "011010"; + when 27 => SATA_MAX_WAKE_0_BINARY <= "011011"; + when 28 => SATA_MAX_WAKE_0_BINARY <= "011100"; + when 29 => SATA_MAX_WAKE_0_BINARY <= "011101"; + when 30 => SATA_MAX_WAKE_0_BINARY <= "011110"; + when 31 => SATA_MAX_WAKE_0_BINARY <= "011111"; + when 32 => SATA_MAX_WAKE_0_BINARY <= "100000"; + when 33 => SATA_MAX_WAKE_0_BINARY <= "100001"; + when 34 => SATA_MAX_WAKE_0_BINARY <= "100010"; + when 35 => SATA_MAX_WAKE_0_BINARY <= "100011"; + when 36 => SATA_MAX_WAKE_0_BINARY <= "100100"; + when 37 => SATA_MAX_WAKE_0_BINARY <= "100101"; + when 38 => SATA_MAX_WAKE_0_BINARY <= "100110"; + when 39 => SATA_MAX_WAKE_0_BINARY <= "100111"; + when 40 => SATA_MAX_WAKE_0_BINARY <= "101000"; + when 41 => SATA_MAX_WAKE_0_BINARY <= "101001"; + when 42 => SATA_MAX_WAKE_0_BINARY <= "101010"; + when 43 => SATA_MAX_WAKE_0_BINARY <= "101011"; + when 44 => SATA_MAX_WAKE_0_BINARY <= "101100"; + when 45 => SATA_MAX_WAKE_0_BINARY <= "101101"; + when 46 => SATA_MAX_WAKE_0_BINARY <= "101110"; + when 47 => SATA_MAX_WAKE_0_BINARY <= "101111"; + when 48 => SATA_MAX_WAKE_0_BINARY <= "110000"; + when 49 => SATA_MAX_WAKE_0_BINARY <= "110001"; + when 50 => SATA_MAX_WAKE_0_BINARY <= "110010"; + when 51 => SATA_MAX_WAKE_0_BINARY <= "110011"; + when 52 => SATA_MAX_WAKE_0_BINARY <= "110100"; + when 53 => SATA_MAX_WAKE_0_BINARY <= "110101"; + when 54 => SATA_MAX_WAKE_0_BINARY <= "110110"; + when 55 => SATA_MAX_WAKE_0_BINARY <= "110111"; + when 56 => SATA_MAX_WAKE_0_BINARY <= "111000"; + when 57 => SATA_MAX_WAKE_0_BINARY <= "111001"; + when 58 => SATA_MAX_WAKE_0_BINARY <= "111010"; + when 59 => SATA_MAX_WAKE_0_BINARY <= "111011"; + when 60 => SATA_MAX_WAKE_0_BINARY <= "111100"; + when 61 => SATA_MAX_WAKE_0_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_WAKE_0 is not in range 1...61." severity error; + end case; + case SATA_MIN_BURST_1 is + when 1 => SATA_MIN_BURST_1_BINARY <= "000001"; + when 2 => SATA_MIN_BURST_1_BINARY <= "000010"; + when 3 => SATA_MIN_BURST_1_BINARY <= "000011"; + when 4 => SATA_MIN_BURST_1_BINARY <= "000100"; + when 5 => SATA_MIN_BURST_1_BINARY <= "000101"; + when 6 => SATA_MIN_BURST_1_BINARY <= "000110"; + when 7 => SATA_MIN_BURST_1_BINARY <= "000111"; + when 8 => SATA_MIN_BURST_1_BINARY <= "001000"; + when 9 => SATA_MIN_BURST_1_BINARY <= "001001"; + when 10 => SATA_MIN_BURST_1_BINARY <= "001010"; + when 11 => SATA_MIN_BURST_1_BINARY <= "001011"; + when 12 => SATA_MIN_BURST_1_BINARY <= "001100"; + when 13 => SATA_MIN_BURST_1_BINARY <= "001101"; + when 14 => SATA_MIN_BURST_1_BINARY <= "001110"; + when 15 => SATA_MIN_BURST_1_BINARY <= "001111"; + when 16 => SATA_MIN_BURST_1_BINARY <= "010000"; + when 17 => SATA_MIN_BURST_1_BINARY <= "010001"; + when 18 => SATA_MIN_BURST_1_BINARY <= "010010"; + when 19 => SATA_MIN_BURST_1_BINARY <= "010011"; + when 20 => SATA_MIN_BURST_1_BINARY <= "010100"; + when 21 => SATA_MIN_BURST_1_BINARY <= "010101"; + when 22 => SATA_MIN_BURST_1_BINARY <= "010110"; + when 23 => SATA_MIN_BURST_1_BINARY <= "010111"; + when 24 => SATA_MIN_BURST_1_BINARY <= "011000"; + when 25 => SATA_MIN_BURST_1_BINARY <= "011001"; + when 26 => SATA_MIN_BURST_1_BINARY <= "011010"; + when 27 => SATA_MIN_BURST_1_BINARY <= "011011"; + when 28 => SATA_MIN_BURST_1_BINARY <= "011100"; + when 29 => SATA_MIN_BURST_1_BINARY <= "011101"; + when 30 => SATA_MIN_BURST_1_BINARY <= "011110"; + when 31 => SATA_MIN_BURST_1_BINARY <= "011111"; + when 32 => SATA_MIN_BURST_1_BINARY <= "100000"; + when 33 => SATA_MIN_BURST_1_BINARY <= "100001"; + when 34 => SATA_MIN_BURST_1_BINARY <= "100010"; + when 35 => SATA_MIN_BURST_1_BINARY <= "100011"; + when 36 => SATA_MIN_BURST_1_BINARY <= "100100"; + when 37 => SATA_MIN_BURST_1_BINARY <= "100101"; + when 38 => SATA_MIN_BURST_1_BINARY <= "100110"; + when 39 => SATA_MIN_BURST_1_BINARY <= "100111"; + when 40 => SATA_MIN_BURST_1_BINARY <= "101000"; + when 41 => SATA_MIN_BURST_1_BINARY <= "101001"; + when 42 => SATA_MIN_BURST_1_BINARY <= "101010"; + when 43 => SATA_MIN_BURST_1_BINARY <= "101011"; + when 44 => SATA_MIN_BURST_1_BINARY <= "101100"; + when 45 => SATA_MIN_BURST_1_BINARY <= "101101"; + when 46 => SATA_MIN_BURST_1_BINARY <= "101110"; + when 47 => SATA_MIN_BURST_1_BINARY <= "101111"; + when 48 => SATA_MIN_BURST_1_BINARY <= "110000"; + when 49 => SATA_MIN_BURST_1_BINARY <= "110001"; + when 50 => SATA_MIN_BURST_1_BINARY <= "110010"; + when 51 => SATA_MIN_BURST_1_BINARY <= "110011"; + when 52 => SATA_MIN_BURST_1_BINARY <= "110100"; + when 53 => SATA_MIN_BURST_1_BINARY <= "110101"; + when 54 => SATA_MIN_BURST_1_BINARY <= "110110"; + when 55 => SATA_MIN_BURST_1_BINARY <= "110111"; + when 56 => SATA_MIN_BURST_1_BINARY <= "111000"; + when 57 => SATA_MIN_BURST_1_BINARY <= "111001"; + when 58 => SATA_MIN_BURST_1_BINARY <= "111010"; + when 59 => SATA_MIN_BURST_1_BINARY <= "111011"; + when 60 => SATA_MIN_BURST_1_BINARY <= "111100"; + when 61 => SATA_MIN_BURST_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_BURST_1 is not in range 1...61." severity error; + end case; + case SATA_MAX_BURST_1 is + when 1 => SATA_MAX_BURST_1_BINARY <= "000001"; + when 2 => SATA_MAX_BURST_1_BINARY <= "000010"; + when 3 => SATA_MAX_BURST_1_BINARY <= "000011"; + when 4 => SATA_MAX_BURST_1_BINARY <= "000100"; + when 5 => SATA_MAX_BURST_1_BINARY <= "000101"; + when 6 => SATA_MAX_BURST_1_BINARY <= "000110"; + when 7 => SATA_MAX_BURST_1_BINARY <= "000111"; + when 8 => SATA_MAX_BURST_1_BINARY <= "001000"; + when 9 => SATA_MAX_BURST_1_BINARY <= "001001"; + when 10 => SATA_MAX_BURST_1_BINARY <= "001010"; + when 11 => SATA_MAX_BURST_1_BINARY <= "001011"; + when 12 => SATA_MAX_BURST_1_BINARY <= "001100"; + when 13 => SATA_MAX_BURST_1_BINARY <= "001101"; + when 14 => SATA_MAX_BURST_1_BINARY <= "001110"; + when 15 => SATA_MAX_BURST_1_BINARY <= "001111"; + when 16 => SATA_MAX_BURST_1_BINARY <= "010000"; + when 17 => SATA_MAX_BURST_1_BINARY <= "010001"; + when 18 => SATA_MAX_BURST_1_BINARY <= "010010"; + when 19 => SATA_MAX_BURST_1_BINARY <= "010011"; + when 20 => SATA_MAX_BURST_1_BINARY <= "010100"; + when 21 => SATA_MAX_BURST_1_BINARY <= "010101"; + when 22 => SATA_MAX_BURST_1_BINARY <= "010110"; + when 23 => SATA_MAX_BURST_1_BINARY <= "010111"; + when 24 => SATA_MAX_BURST_1_BINARY <= "011000"; + when 25 => SATA_MAX_BURST_1_BINARY <= "011001"; + when 26 => SATA_MAX_BURST_1_BINARY <= "011010"; + when 27 => SATA_MAX_BURST_1_BINARY <= "011011"; + when 28 => SATA_MAX_BURST_1_BINARY <= "011100"; + when 29 => SATA_MAX_BURST_1_BINARY <= "011101"; + when 30 => SATA_MAX_BURST_1_BINARY <= "011110"; + when 31 => SATA_MAX_BURST_1_BINARY <= "011111"; + when 32 => SATA_MAX_BURST_1_BINARY <= "100000"; + when 33 => SATA_MAX_BURST_1_BINARY <= "100001"; + when 34 => SATA_MAX_BURST_1_BINARY <= "100010"; + when 35 => SATA_MAX_BURST_1_BINARY <= "100011"; + when 36 => SATA_MAX_BURST_1_BINARY <= "100100"; + when 37 => SATA_MAX_BURST_1_BINARY <= "100101"; + when 38 => SATA_MAX_BURST_1_BINARY <= "100110"; + when 39 => SATA_MAX_BURST_1_BINARY <= "100111"; + when 40 => SATA_MAX_BURST_1_BINARY <= "101000"; + when 41 => SATA_MAX_BURST_1_BINARY <= "101001"; + when 42 => SATA_MAX_BURST_1_BINARY <= "101010"; + when 43 => SATA_MAX_BURST_1_BINARY <= "101011"; + when 44 => SATA_MAX_BURST_1_BINARY <= "101100"; + when 45 => SATA_MAX_BURST_1_BINARY <= "101101"; + when 46 => SATA_MAX_BURST_1_BINARY <= "101110"; + when 47 => SATA_MAX_BURST_1_BINARY <= "101111"; + when 48 => SATA_MAX_BURST_1_BINARY <= "110000"; + when 49 => SATA_MAX_BURST_1_BINARY <= "110001"; + when 50 => SATA_MAX_BURST_1_BINARY <= "110010"; + when 51 => SATA_MAX_BURST_1_BINARY <= "110011"; + when 52 => SATA_MAX_BURST_1_BINARY <= "110100"; + when 53 => SATA_MAX_BURST_1_BINARY <= "110101"; + when 54 => SATA_MAX_BURST_1_BINARY <= "110110"; + when 55 => SATA_MAX_BURST_1_BINARY <= "110111"; + when 56 => SATA_MAX_BURST_1_BINARY <= "111000"; + when 57 => SATA_MAX_BURST_1_BINARY <= "111001"; + when 58 => SATA_MAX_BURST_1_BINARY <= "111010"; + when 59 => SATA_MAX_BURST_1_BINARY <= "111011"; + when 60 => SATA_MAX_BURST_1_BINARY <= "111100"; + when 61 => SATA_MAX_BURST_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_BURST_1 is not in range 1...61." severity error; + end case; + case SATA_MIN_INIT_1 is + when 1 => SATA_MIN_INIT_1_BINARY <= "000001"; + when 2 => SATA_MIN_INIT_1_BINARY <= "000010"; + when 3 => SATA_MIN_INIT_1_BINARY <= "000011"; + when 4 => SATA_MIN_INIT_1_BINARY <= "000100"; + when 5 => SATA_MIN_INIT_1_BINARY <= "000101"; + when 6 => SATA_MIN_INIT_1_BINARY <= "000110"; + when 7 => SATA_MIN_INIT_1_BINARY <= "000111"; + when 8 => SATA_MIN_INIT_1_BINARY <= "001000"; + when 9 => SATA_MIN_INIT_1_BINARY <= "001001"; + when 10 => SATA_MIN_INIT_1_BINARY <= "001010"; + when 11 => SATA_MIN_INIT_1_BINARY <= "001011"; + when 12 => SATA_MIN_INIT_1_BINARY <= "001100"; + when 13 => SATA_MIN_INIT_1_BINARY <= "001101"; + when 14 => SATA_MIN_INIT_1_BINARY <= "001110"; + when 15 => SATA_MIN_INIT_1_BINARY <= "001111"; + when 16 => SATA_MIN_INIT_1_BINARY <= "010000"; + when 17 => SATA_MIN_INIT_1_BINARY <= "010001"; + when 18 => SATA_MIN_INIT_1_BINARY <= "010010"; + when 19 => SATA_MIN_INIT_1_BINARY <= "010011"; + when 20 => SATA_MIN_INIT_1_BINARY <= "010100"; + when 21 => SATA_MIN_INIT_1_BINARY <= "010101"; + when 22 => SATA_MIN_INIT_1_BINARY <= "010110"; + when 23 => SATA_MIN_INIT_1_BINARY <= "010111"; + when 24 => SATA_MIN_INIT_1_BINARY <= "011000"; + when 25 => SATA_MIN_INIT_1_BINARY <= "011001"; + when 26 => SATA_MIN_INIT_1_BINARY <= "011010"; + when 27 => SATA_MIN_INIT_1_BINARY <= "011011"; + when 28 => SATA_MIN_INIT_1_BINARY <= "011100"; + when 29 => SATA_MIN_INIT_1_BINARY <= "011101"; + when 30 => SATA_MIN_INIT_1_BINARY <= "011110"; + when 31 => SATA_MIN_INIT_1_BINARY <= "011111"; + when 32 => SATA_MIN_INIT_1_BINARY <= "100000"; + when 33 => SATA_MIN_INIT_1_BINARY <= "100001"; + when 34 => SATA_MIN_INIT_1_BINARY <= "100010"; + when 35 => SATA_MIN_INIT_1_BINARY <= "100011"; + when 36 => SATA_MIN_INIT_1_BINARY <= "100100"; + when 37 => SATA_MIN_INIT_1_BINARY <= "100101"; + when 38 => SATA_MIN_INIT_1_BINARY <= "100110"; + when 39 => SATA_MIN_INIT_1_BINARY <= "100111"; + when 40 => SATA_MIN_INIT_1_BINARY <= "101000"; + when 41 => SATA_MIN_INIT_1_BINARY <= "101001"; + when 42 => SATA_MIN_INIT_1_BINARY <= "101010"; + when 43 => SATA_MIN_INIT_1_BINARY <= "101011"; + when 44 => SATA_MIN_INIT_1_BINARY <= "101100"; + when 45 => SATA_MIN_INIT_1_BINARY <= "101101"; + when 46 => SATA_MIN_INIT_1_BINARY <= "101110"; + when 47 => SATA_MIN_INIT_1_BINARY <= "101111"; + when 48 => SATA_MIN_INIT_1_BINARY <= "110000"; + when 49 => SATA_MIN_INIT_1_BINARY <= "110001"; + when 50 => SATA_MIN_INIT_1_BINARY <= "110010"; + when 51 => SATA_MIN_INIT_1_BINARY <= "110011"; + when 52 => SATA_MIN_INIT_1_BINARY <= "110100"; + when 53 => SATA_MIN_INIT_1_BINARY <= "110101"; + when 54 => SATA_MIN_INIT_1_BINARY <= "110110"; + when 55 => SATA_MIN_INIT_1_BINARY <= "110111"; + when 56 => SATA_MIN_INIT_1_BINARY <= "111000"; + when 57 => SATA_MIN_INIT_1_BINARY <= "111001"; + when 58 => SATA_MIN_INIT_1_BINARY <= "111010"; + when 59 => SATA_MIN_INIT_1_BINARY <= "111011"; + when 60 => SATA_MIN_INIT_1_BINARY <= "111100"; + when 61 => SATA_MIN_INIT_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_INIT_1 is not in range 1...61." severity error; + end case; + case SATA_MAX_INIT_1 is + when 1 => SATA_MAX_INIT_1_BINARY <= "000001"; + when 2 => SATA_MAX_INIT_1_BINARY <= "000010"; + when 3 => SATA_MAX_INIT_1_BINARY <= "000011"; + when 4 => SATA_MAX_INIT_1_BINARY <= "000100"; + when 5 => SATA_MAX_INIT_1_BINARY <= "000101"; + when 6 => SATA_MAX_INIT_1_BINARY <= "000110"; + when 7 => SATA_MAX_INIT_1_BINARY <= "000111"; + when 8 => SATA_MAX_INIT_1_BINARY <= "001000"; + when 9 => SATA_MAX_INIT_1_BINARY <= "001001"; + when 10 => SATA_MAX_INIT_1_BINARY <= "001010"; + when 11 => SATA_MAX_INIT_1_BINARY <= "001011"; + when 12 => SATA_MAX_INIT_1_BINARY <= "001100"; + when 13 => SATA_MAX_INIT_1_BINARY <= "001101"; + when 14 => SATA_MAX_INIT_1_BINARY <= "001110"; + when 15 => SATA_MAX_INIT_1_BINARY <= "001111"; + when 16 => SATA_MAX_INIT_1_BINARY <= "010000"; + when 17 => SATA_MAX_INIT_1_BINARY <= "010001"; + when 18 => SATA_MAX_INIT_1_BINARY <= "010010"; + when 19 => SATA_MAX_INIT_1_BINARY <= "010011"; + when 20 => SATA_MAX_INIT_1_BINARY <= "010100"; + when 21 => SATA_MAX_INIT_1_BINARY <= "010101"; + when 22 => SATA_MAX_INIT_1_BINARY <= "010110"; + when 23 => SATA_MAX_INIT_1_BINARY <= "010111"; + when 24 => SATA_MAX_INIT_1_BINARY <= "011000"; + when 25 => SATA_MAX_INIT_1_BINARY <= "011001"; + when 26 => SATA_MAX_INIT_1_BINARY <= "011010"; + when 27 => SATA_MAX_INIT_1_BINARY <= "011011"; + when 28 => SATA_MAX_INIT_1_BINARY <= "011100"; + when 29 => SATA_MAX_INIT_1_BINARY <= "011101"; + when 30 => SATA_MAX_INIT_1_BINARY <= "011110"; + when 31 => SATA_MAX_INIT_1_BINARY <= "011111"; + when 32 => SATA_MAX_INIT_1_BINARY <= "100000"; + when 33 => SATA_MAX_INIT_1_BINARY <= "100001"; + when 34 => SATA_MAX_INIT_1_BINARY <= "100010"; + when 35 => SATA_MAX_INIT_1_BINARY <= "100011"; + when 36 => SATA_MAX_INIT_1_BINARY <= "100100"; + when 37 => SATA_MAX_INIT_1_BINARY <= "100101"; + when 38 => SATA_MAX_INIT_1_BINARY <= "100110"; + when 39 => SATA_MAX_INIT_1_BINARY <= "100111"; + when 40 => SATA_MAX_INIT_1_BINARY <= "101000"; + when 41 => SATA_MAX_INIT_1_BINARY <= "101001"; + when 42 => SATA_MAX_INIT_1_BINARY <= "101010"; + when 43 => SATA_MAX_INIT_1_BINARY <= "101011"; + when 44 => SATA_MAX_INIT_1_BINARY <= "101100"; + when 45 => SATA_MAX_INIT_1_BINARY <= "101101"; + when 46 => SATA_MAX_INIT_1_BINARY <= "101110"; + when 47 => SATA_MAX_INIT_1_BINARY <= "101111"; + when 48 => SATA_MAX_INIT_1_BINARY <= "110000"; + when 49 => SATA_MAX_INIT_1_BINARY <= "110001"; + when 50 => SATA_MAX_INIT_1_BINARY <= "110010"; + when 51 => SATA_MAX_INIT_1_BINARY <= "110011"; + when 52 => SATA_MAX_INIT_1_BINARY <= "110100"; + when 53 => SATA_MAX_INIT_1_BINARY <= "110101"; + when 54 => SATA_MAX_INIT_1_BINARY <= "110110"; + when 55 => SATA_MAX_INIT_1_BINARY <= "110111"; + when 56 => SATA_MAX_INIT_1_BINARY <= "111000"; + when 57 => SATA_MAX_INIT_1_BINARY <= "111001"; + when 58 => SATA_MAX_INIT_1_BINARY <= "111010"; + when 59 => SATA_MAX_INIT_1_BINARY <= "111011"; + when 60 => SATA_MAX_INIT_1_BINARY <= "111100"; + when 61 => SATA_MAX_INIT_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_INIT_1 is not in range 1...61." severity error; + end case; + case SATA_MIN_WAKE_1 is + when 1 => SATA_MIN_WAKE_1_BINARY <= "000001"; + when 2 => SATA_MIN_WAKE_1_BINARY <= "000010"; + when 3 => SATA_MIN_WAKE_1_BINARY <= "000011"; + when 4 => SATA_MIN_WAKE_1_BINARY <= "000100"; + when 5 => SATA_MIN_WAKE_1_BINARY <= "000101"; + when 6 => SATA_MIN_WAKE_1_BINARY <= "000110"; + when 7 => SATA_MIN_WAKE_1_BINARY <= "000111"; + when 8 => SATA_MIN_WAKE_1_BINARY <= "001000"; + when 9 => SATA_MIN_WAKE_1_BINARY <= "001001"; + when 10 => SATA_MIN_WAKE_1_BINARY <= "001010"; + when 11 => SATA_MIN_WAKE_1_BINARY <= "001011"; + when 12 => SATA_MIN_WAKE_1_BINARY <= "001100"; + when 13 => SATA_MIN_WAKE_1_BINARY <= "001101"; + when 14 => SATA_MIN_WAKE_1_BINARY <= "001110"; + when 15 => SATA_MIN_WAKE_1_BINARY <= "001111"; + when 16 => SATA_MIN_WAKE_1_BINARY <= "010000"; + when 17 => SATA_MIN_WAKE_1_BINARY <= "010001"; + when 18 => SATA_MIN_WAKE_1_BINARY <= "010010"; + when 19 => SATA_MIN_WAKE_1_BINARY <= "010011"; + when 20 => SATA_MIN_WAKE_1_BINARY <= "010100"; + when 21 => SATA_MIN_WAKE_1_BINARY <= "010101"; + when 22 => SATA_MIN_WAKE_1_BINARY <= "010110"; + when 23 => SATA_MIN_WAKE_1_BINARY <= "010111"; + when 24 => SATA_MIN_WAKE_1_BINARY <= "011000"; + when 25 => SATA_MIN_WAKE_1_BINARY <= "011001"; + when 26 => SATA_MIN_WAKE_1_BINARY <= "011010"; + when 27 => SATA_MIN_WAKE_1_BINARY <= "011011"; + when 28 => SATA_MIN_WAKE_1_BINARY <= "011100"; + when 29 => SATA_MIN_WAKE_1_BINARY <= "011101"; + when 30 => SATA_MIN_WAKE_1_BINARY <= "011110"; + when 31 => SATA_MIN_WAKE_1_BINARY <= "011111"; + when 32 => SATA_MIN_WAKE_1_BINARY <= "100000"; + when 33 => SATA_MIN_WAKE_1_BINARY <= "100001"; + when 34 => SATA_MIN_WAKE_1_BINARY <= "100010"; + when 35 => SATA_MIN_WAKE_1_BINARY <= "100011"; + when 36 => SATA_MIN_WAKE_1_BINARY <= "100100"; + when 37 => SATA_MIN_WAKE_1_BINARY <= "100101"; + when 38 => SATA_MIN_WAKE_1_BINARY <= "100110"; + when 39 => SATA_MIN_WAKE_1_BINARY <= "100111"; + when 40 => SATA_MIN_WAKE_1_BINARY <= "101000"; + when 41 => SATA_MIN_WAKE_1_BINARY <= "101001"; + when 42 => SATA_MIN_WAKE_1_BINARY <= "101010"; + when 43 => SATA_MIN_WAKE_1_BINARY <= "101011"; + when 44 => SATA_MIN_WAKE_1_BINARY <= "101100"; + when 45 => SATA_MIN_WAKE_1_BINARY <= "101101"; + when 46 => SATA_MIN_WAKE_1_BINARY <= "101110"; + when 47 => SATA_MIN_WAKE_1_BINARY <= "101111"; + when 48 => SATA_MIN_WAKE_1_BINARY <= "110000"; + when 49 => SATA_MIN_WAKE_1_BINARY <= "110001"; + when 50 => SATA_MIN_WAKE_1_BINARY <= "110010"; + when 51 => SATA_MIN_WAKE_1_BINARY <= "110011"; + when 52 => SATA_MIN_WAKE_1_BINARY <= "110100"; + when 53 => SATA_MIN_WAKE_1_BINARY <= "110101"; + when 54 => SATA_MIN_WAKE_1_BINARY <= "110110"; + when 55 => SATA_MIN_WAKE_1_BINARY <= "110111"; + when 56 => SATA_MIN_WAKE_1_BINARY <= "111000"; + when 57 => SATA_MIN_WAKE_1_BINARY <= "111001"; + when 58 => SATA_MIN_WAKE_1_BINARY <= "111010"; + when 59 => SATA_MIN_WAKE_1_BINARY <= "111011"; + when 60 => SATA_MIN_WAKE_1_BINARY <= "111100"; + when 61 => SATA_MIN_WAKE_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MIN_WAKE_1 is not in range 1...61." severity error; + end case; + case SATA_MAX_WAKE_1 is + when 1 => SATA_MAX_WAKE_1_BINARY <= "000001"; + when 2 => SATA_MAX_WAKE_1_BINARY <= "000010"; + when 3 => SATA_MAX_WAKE_1_BINARY <= "000011"; + when 4 => SATA_MAX_WAKE_1_BINARY <= "000100"; + when 5 => SATA_MAX_WAKE_1_BINARY <= "000101"; + when 6 => SATA_MAX_WAKE_1_BINARY <= "000110"; + when 7 => SATA_MAX_WAKE_1_BINARY <= "000111"; + when 8 => SATA_MAX_WAKE_1_BINARY <= "001000"; + when 9 => SATA_MAX_WAKE_1_BINARY <= "001001"; + when 10 => SATA_MAX_WAKE_1_BINARY <= "001010"; + when 11 => SATA_MAX_WAKE_1_BINARY <= "001011"; + when 12 => SATA_MAX_WAKE_1_BINARY <= "001100"; + when 13 => SATA_MAX_WAKE_1_BINARY <= "001101"; + when 14 => SATA_MAX_WAKE_1_BINARY <= "001110"; + when 15 => SATA_MAX_WAKE_1_BINARY <= "001111"; + when 16 => SATA_MAX_WAKE_1_BINARY <= "010000"; + when 17 => SATA_MAX_WAKE_1_BINARY <= "010001"; + when 18 => SATA_MAX_WAKE_1_BINARY <= "010010"; + when 19 => SATA_MAX_WAKE_1_BINARY <= "010011"; + when 20 => SATA_MAX_WAKE_1_BINARY <= "010100"; + when 21 => SATA_MAX_WAKE_1_BINARY <= "010101"; + when 22 => SATA_MAX_WAKE_1_BINARY <= "010110"; + when 23 => SATA_MAX_WAKE_1_BINARY <= "010111"; + when 24 => SATA_MAX_WAKE_1_BINARY <= "011000"; + when 25 => SATA_MAX_WAKE_1_BINARY <= "011001"; + when 26 => SATA_MAX_WAKE_1_BINARY <= "011010"; + when 27 => SATA_MAX_WAKE_1_BINARY <= "011011"; + when 28 => SATA_MAX_WAKE_1_BINARY <= "011100"; + when 29 => SATA_MAX_WAKE_1_BINARY <= "011101"; + when 30 => SATA_MAX_WAKE_1_BINARY <= "011110"; + when 31 => SATA_MAX_WAKE_1_BINARY <= "011111"; + when 32 => SATA_MAX_WAKE_1_BINARY <= "100000"; + when 33 => SATA_MAX_WAKE_1_BINARY <= "100001"; + when 34 => SATA_MAX_WAKE_1_BINARY <= "100010"; + when 35 => SATA_MAX_WAKE_1_BINARY <= "100011"; + when 36 => SATA_MAX_WAKE_1_BINARY <= "100100"; + when 37 => SATA_MAX_WAKE_1_BINARY <= "100101"; + when 38 => SATA_MAX_WAKE_1_BINARY <= "100110"; + when 39 => SATA_MAX_WAKE_1_BINARY <= "100111"; + when 40 => SATA_MAX_WAKE_1_BINARY <= "101000"; + when 41 => SATA_MAX_WAKE_1_BINARY <= "101001"; + when 42 => SATA_MAX_WAKE_1_BINARY <= "101010"; + when 43 => SATA_MAX_WAKE_1_BINARY <= "101011"; + when 44 => SATA_MAX_WAKE_1_BINARY <= "101100"; + when 45 => SATA_MAX_WAKE_1_BINARY <= "101101"; + when 46 => SATA_MAX_WAKE_1_BINARY <= "101110"; + when 47 => SATA_MAX_WAKE_1_BINARY <= "101111"; + when 48 => SATA_MAX_WAKE_1_BINARY <= "110000"; + when 49 => SATA_MAX_WAKE_1_BINARY <= "110001"; + when 50 => SATA_MAX_WAKE_1_BINARY <= "110010"; + when 51 => SATA_MAX_WAKE_1_BINARY <= "110011"; + when 52 => SATA_MAX_WAKE_1_BINARY <= "110100"; + when 53 => SATA_MAX_WAKE_1_BINARY <= "110101"; + when 54 => SATA_MAX_WAKE_1_BINARY <= "110110"; + when 55 => SATA_MAX_WAKE_1_BINARY <= "110111"; + when 56 => SATA_MAX_WAKE_1_BINARY <= "111000"; + when 57 => SATA_MAX_WAKE_1_BINARY <= "111001"; + when 58 => SATA_MAX_WAKE_1_BINARY <= "111010"; + when 59 => SATA_MAX_WAKE_1_BINARY <= "111011"; + when 60 => SATA_MAX_WAKE_1_BINARY <= "111100"; + when 61 => SATA_MAX_WAKE_1_BINARY <= "111101"; + when others => assert FALSE report "Error : SATA_MAX_WAKE_1 is not in range 1...61." severity error; + end case; + case CLK25_DIVIDER is + when 1 => CLK25_DIVIDER_BINARY <= "000"; + when 2 => CLK25_DIVIDER_BINARY <= "001"; + when 3 => CLK25_DIVIDER_BINARY <= "010"; + when 4 => CLK25_DIVIDER_BINARY <= "011"; + when 5 => CLK25_DIVIDER_BINARY <= "100"; + when 6 => CLK25_DIVIDER_BINARY <= "101"; + when 10 => CLK25_DIVIDER_BINARY <= "110"; + when 12 => CLK25_DIVIDER_BINARY <= "111"; + when others => assert FALSE report "Error : CLK25_DIVIDER is not in 1, 2, 3, 4, 5, 6, 10, 12." severity error; + end case; + case OVERSAMPLE_MODE is + when FALSE => OVERSAMPLE_MODE_BINARY <= '0'; + when TRUE => OVERSAMPLE_MODE_BINARY <= '1'; + when others => assert FALSE report "Error : OVERSAMPLE_MODE is neither TRUE nor FALSE." severity error; + end case; + case TXGEARBOX_USE_0 is + when FALSE => TXGEARBOX_USE_0_BINARY <= '0'; + when TRUE => TXGEARBOX_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : TXGEARBOX_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case RXGEARBOX_USE_0 is + when FALSE => RXGEARBOX_USE_0_BINARY <= '0'; + when TRUE => RXGEARBOX_USE_0_BINARY <= '1'; + when others => assert FALSE report "Error : RXGEARBOX_USE_0 is neither TRUE nor FALSE." severity error; + end case; + case TXGEARBOX_USE_1 is + when FALSE => TXGEARBOX_USE_1_BINARY <= '0'; + when TRUE => TXGEARBOX_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : TXGEARBOX_USE_1 is neither TRUE nor FALSE." severity error; + end case; + case RXGEARBOX_USE_1 is + when FALSE => RXGEARBOX_USE_1_BINARY <= '0'; + when TRUE => RXGEARBOX_USE_1_BINARY <= '1'; + when others => assert FALSE report "Error : RXGEARBOX_USE_1 is neither TRUE nor FALSE." severity error; + end case; + case PLL_FB_DCCEN is + when FALSE => PLL_FB_DCCEN_BINARY <= '0'; + when TRUE => PLL_FB_DCCEN_BINARY <= '1'; + when others => assert FALSE report "Error : PLL_FB_DCCEN is neither TRUE nor FALSE." severity error; + end case; + case CLKRCV_TRST is + when FALSE => CLKRCV_TRST_BINARY <= '0'; + when TRUE => CLKRCV_TRST_BINARY <= '1'; + when others => assert FALSE report "Error : CLKRCV_TRST is neither TRUE nor FALSE." severity error; + end case; + case RX_EN_IDLE_HOLD_DFE_0 is + when FALSE => RX_EN_IDLE_HOLD_DFE_0_BINARY <= '0'; + when TRUE => RX_EN_IDLE_HOLD_DFE_0_BINARY <= '1'; + when others => assert FALSE report "Error : RX_EN_IDLE_HOLD_DFE_0 is neither TRUE nor FALSE." severity error; + end case; + case RX_EN_IDLE_RESET_BUF_0 is + when FALSE => RX_EN_IDLE_RESET_BUF_0_BINARY <= '0'; + when TRUE => RX_EN_IDLE_RESET_BUF_0_BINARY <= '1'; + when others => assert FALSE report "Error : RX_EN_IDLE_RESET_BUF_0 is neither TRUE nor FALSE." severity error; + end case; + case RX_EN_IDLE_HOLD_DFE_1 is + when FALSE => RX_EN_IDLE_HOLD_DFE_1_BINARY <= '0'; + when TRUE => RX_EN_IDLE_HOLD_DFE_1_BINARY <= '1'; + when others => assert FALSE report "Error : RX_EN_IDLE_HOLD_DFE_1 is neither TRUE nor FALSE." severity error; + end case; + case RX_EN_IDLE_RESET_BUF_1 is + when FALSE => RX_EN_IDLE_RESET_BUF_1_BINARY <= '0'; + when TRUE => RX_EN_IDLE_RESET_BUF_1_BINARY <= '1'; + when others => assert FALSE report "Error : RX_EN_IDLE_RESET_BUF_1 is neither TRUE nor FALSE." severity error; + end case; + case RX_EN_IDLE_HOLD_CDR is + when FALSE => RX_EN_IDLE_HOLD_CDR_BINARY <= '0'; + when TRUE => RX_EN_IDLE_HOLD_CDR_BINARY <= '1'; + when others => assert FALSE report "Error : RX_EN_IDLE_HOLD_CDR is neither TRUE nor FALSE." severity error; + end case; + case RX_EN_IDLE_RESET_PH is + when FALSE => RX_EN_IDLE_RESET_PH_BINARY <= '0'; + when TRUE => RX_EN_IDLE_RESET_PH_BINARY <= '1'; + when others => assert FALSE report "Error : RX_EN_IDLE_RESET_PH is neither TRUE nor FALSE." severity error; + end case; + case RX_EN_IDLE_RESET_FR is + when FALSE => RX_EN_IDLE_RESET_FR_BINARY <= '0'; + when TRUE => RX_EN_IDLE_RESET_FR_BINARY <= '1'; + when others => assert FALSE report "Error : RX_EN_IDLE_RESET_FR is neither TRUE nor FALSE." severity error; + end case; + case SIM_GTXRESET_SPEEDUP is + when 0 => SIM_GTXRESET_SPEEDUP_BINARY <= '0'; + when 1 => SIM_GTXRESET_SPEEDUP_BINARY <= '1'; + when others => assert FALSE report "Error : SIM_GTXRESET_SPEEDUP is not in 0, 1." severity error; + end case; +-- case SIM_MODE is + if((SIM_MODE = "LEGACY") or (SIM_MODE = "legacy")) then + SIM_MODE_BINARY <= '1'; + elsif((SIM_MODE = "FAST") or (SIM_MODE = "fast")) then + SIM_MODE_BINARY <= '0'; + else + assert FALSE report "Error : SIM_MODE = is not LEGACY, FAST." severity error; + end if; +-- end case; + case SIM_RECEIVER_DETECT_PASS_0 is + when FALSE => SIM_RECEIVER_DETECT_PASS_0_BINARY <= '0'; + when TRUE => SIM_RECEIVER_DETECT_PASS_0_BINARY <= '1'; + when others => assert FALSE report "Error : SIM_RECEIVER_DETECT_PASS_0 is neither TRUE nor FALSE." severity error; + end case; + case SIM_RECEIVER_DETECT_PASS_1 is + when FALSE => SIM_RECEIVER_DETECT_PASS_1_BINARY <= '0'; + when TRUE => SIM_RECEIVER_DETECT_PASS_1_BINARY <= '1'; + when others => assert FALSE report "Error : SIM_RECEIVER_DETECT_PASS_1 is neither TRUE nor FALSE." severity error; + end case; + wait; + end process INIPROC; + + TIMING : process + + + + variable REFCLKOUT_GlitchData : VitalGlitchDataType; + variable RXRECCLK0_GlitchData : VitalGlitchDataType; + variable TXOUTCLK0_GlitchData : VitalGlitchDataType; + variable RXRECCLK1_GlitchData : VitalGlitchDataType; + variable TXOUTCLK1_GlitchData : VitalGlitchDataType; + variable TXP0_GlitchData : VitalGlitchDataType; + variable TXN0_GlitchData : VitalGlitchDataType; + variable TXP1_GlitchData : VitalGlitchDataType; + variable TXN1_GlitchData : VitalGlitchDataType; + variable RXDATA00_GlitchData : VitalGlitchDataType; + variable RXDATA01_GlitchData : VitalGlitchDataType; + variable RXDATA02_GlitchData : VitalGlitchDataType; + variable RXDATA03_GlitchData : VitalGlitchDataType; + variable RXDATA04_GlitchData : VitalGlitchDataType; + variable RXDATA05_GlitchData : VitalGlitchDataType; + variable RXDATA06_GlitchData : VitalGlitchDataType; + variable RXDATA07_GlitchData : VitalGlitchDataType; + variable RXDATA08_GlitchData : VitalGlitchDataType; + variable RXDATA09_GlitchData : VitalGlitchDataType; + variable RXDATA010_GlitchData : VitalGlitchDataType; + variable RXDATA011_GlitchData : VitalGlitchDataType; + variable RXDATA012_GlitchData : VitalGlitchDataType; + variable RXDATA013_GlitchData : VitalGlitchDataType; + variable RXDATA014_GlitchData : VitalGlitchDataType; + variable RXDATA015_GlitchData : VitalGlitchDataType; + variable RXDATA016_GlitchData : VitalGlitchDataType; + variable RXDATA017_GlitchData : VitalGlitchDataType; + variable RXDATA018_GlitchData : VitalGlitchDataType; + variable RXDATA019_GlitchData : VitalGlitchDataType; + variable RXDATA020_GlitchData : VitalGlitchDataType; + variable RXDATA021_GlitchData : VitalGlitchDataType; + variable RXDATA022_GlitchData : VitalGlitchDataType; + variable RXDATA023_GlitchData : VitalGlitchDataType; + variable RXDATA024_GlitchData : VitalGlitchDataType; + variable RXDATA025_GlitchData : VitalGlitchDataType; + variable RXDATA026_GlitchData : VitalGlitchDataType; + variable RXDATA027_GlitchData : VitalGlitchDataType; + variable RXDATA028_GlitchData : VitalGlitchDataType; + variable RXDATA029_GlitchData : VitalGlitchDataType; + variable RXDATA030_GlitchData : VitalGlitchDataType; + variable RXDATA031_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE00_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE01_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE02_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE03_GlitchData : VitalGlitchDataType; + variable RXDISPERR00_GlitchData : VitalGlitchDataType; + variable RXDISPERR01_GlitchData : VitalGlitchDataType; + variable RXDISPERR02_GlitchData : VitalGlitchDataType; + variable RXDISPERR03_GlitchData : VitalGlitchDataType; + variable RXCHARISK00_GlitchData : VitalGlitchDataType; + variable RXCHARISK01_GlitchData : VitalGlitchDataType; + variable RXCHARISK02_GlitchData : VitalGlitchDataType; + variable RXCHARISK03_GlitchData : VitalGlitchDataType; + variable RXRUNDISP00_GlitchData : VitalGlitchDataType; + variable RXRUNDISP01_GlitchData : VitalGlitchDataType; + variable RXRUNDISP02_GlitchData : VitalGlitchDataType; + variable RXRUNDISP03_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA00_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA01_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA02_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA03_GlitchData : VitalGlitchDataType; + variable RXVALID0_GlitchData : VitalGlitchDataType; + variable RXDATA10_GlitchData : VitalGlitchDataType; + variable RXDATA11_GlitchData : VitalGlitchDataType; + variable RXDATA12_GlitchData : VitalGlitchDataType; + variable RXDATA13_GlitchData : VitalGlitchDataType; + variable RXDATA14_GlitchData : VitalGlitchDataType; + variable RXDATA15_GlitchData : VitalGlitchDataType; + variable RXDATA16_GlitchData : VitalGlitchDataType; + variable RXDATA17_GlitchData : VitalGlitchDataType; + variable RXDATA18_GlitchData : VitalGlitchDataType; + variable RXDATA19_GlitchData : VitalGlitchDataType; + variable RXDATA110_GlitchData : VitalGlitchDataType; + variable RXDATA111_GlitchData : VitalGlitchDataType; + variable RXDATA112_GlitchData : VitalGlitchDataType; + variable RXDATA113_GlitchData : VitalGlitchDataType; + variable RXDATA114_GlitchData : VitalGlitchDataType; + variable RXDATA115_GlitchData : VitalGlitchDataType; + variable RXDATA116_GlitchData : VitalGlitchDataType; + variable RXDATA117_GlitchData : VitalGlitchDataType; + variable RXDATA118_GlitchData : VitalGlitchDataType; + variable RXDATA119_GlitchData : VitalGlitchDataType; + variable RXDATA120_GlitchData : VitalGlitchDataType; + variable RXDATA121_GlitchData : VitalGlitchDataType; + variable RXDATA122_GlitchData : VitalGlitchDataType; + variable RXDATA123_GlitchData : VitalGlitchDataType; + variable RXDATA124_GlitchData : VitalGlitchDataType; + variable RXDATA125_GlitchData : VitalGlitchDataType; + variable RXDATA126_GlitchData : VitalGlitchDataType; + variable RXDATA127_GlitchData : VitalGlitchDataType; + variable RXDATA128_GlitchData : VitalGlitchDataType; + variable RXDATA129_GlitchData : VitalGlitchDataType; + variable RXDATA130_GlitchData : VitalGlitchDataType; + variable RXDATA131_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE10_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE11_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE12_GlitchData : VitalGlitchDataType; + variable RXNOTINTABLE13_GlitchData : VitalGlitchDataType; + variable RXDISPERR10_GlitchData : VitalGlitchDataType; + variable RXDISPERR11_GlitchData : VitalGlitchDataType; + variable RXDISPERR12_GlitchData : VitalGlitchDataType; + variable RXDISPERR13_GlitchData : VitalGlitchDataType; + variable RXCHARISK10_GlitchData : VitalGlitchDataType; + variable RXCHARISK11_GlitchData : VitalGlitchDataType; + variable RXCHARISK12_GlitchData : VitalGlitchDataType; + variable RXCHARISK13_GlitchData : VitalGlitchDataType; + variable RXRUNDISP10_GlitchData : VitalGlitchDataType; + variable RXRUNDISP11_GlitchData : VitalGlitchDataType; + variable RXRUNDISP12_GlitchData : VitalGlitchDataType; + variable RXRUNDISP13_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA10_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA11_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA12_GlitchData : VitalGlitchDataType; + variable RXCHARISCOMMA13_GlitchData : VitalGlitchDataType; + variable RXVALID1_GlitchData : VitalGlitchDataType; + variable RESETDONE0_GlitchData : VitalGlitchDataType; + variable RESETDONE1_GlitchData : VitalGlitchDataType; + variable TXKERR00_GlitchData : VitalGlitchDataType; + variable TXKERR01_GlitchData : VitalGlitchDataType; + variable TXKERR02_GlitchData : VitalGlitchDataType; + variable TXKERR03_GlitchData : VitalGlitchDataType; + variable TXRUNDISP00_GlitchData : VitalGlitchDataType; + variable TXRUNDISP01_GlitchData : VitalGlitchDataType; + variable TXRUNDISP02_GlitchData : VitalGlitchDataType; + variable TXRUNDISP03_GlitchData : VitalGlitchDataType; + variable TXBUFSTATUS00_GlitchData : VitalGlitchDataType; + variable TXBUFSTATUS01_GlitchData : VitalGlitchDataType; + variable TXKERR10_GlitchData : VitalGlitchDataType; + variable TXKERR11_GlitchData : VitalGlitchDataType; + variable TXKERR12_GlitchData : VitalGlitchDataType; + variable TXKERR13_GlitchData : VitalGlitchDataType; + variable TXRUNDISP10_GlitchData : VitalGlitchDataType; + variable TXRUNDISP11_GlitchData : VitalGlitchDataType; + variable TXRUNDISP12_GlitchData : VitalGlitchDataType; + variable TXRUNDISP13_GlitchData : VitalGlitchDataType; + variable TXBUFSTATUS10_GlitchData : VitalGlitchDataType; + variable TXBUFSTATUS11_GlitchData : VitalGlitchDataType; + variable RXCOMMADET0_GlitchData : VitalGlitchDataType; + variable RXBYTEREALIGN0_GlitchData : VitalGlitchDataType; + variable RXBYTEISALIGNED0_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC00_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC01_GlitchData : VitalGlitchDataType; + variable RXCHBONDO00_GlitchData : VitalGlitchDataType; + variable RXCHBONDO01_GlitchData : VitalGlitchDataType; + variable RXCHBONDO02_GlitchData : VitalGlitchDataType; + variable RXCHBONDO03_GlitchData : VitalGlitchDataType; + variable RXCHANBONDSEQ0_GlitchData : VitalGlitchDataType; + variable RXCHANREALIGN0_GlitchData : VitalGlitchDataType; + variable RXCHANISALIGNED0_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS00_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS01_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS02_GlitchData : VitalGlitchDataType; + variable RXCOMMADET1_GlitchData : VitalGlitchDataType; + variable RXBYTEREALIGN1_GlitchData : VitalGlitchDataType; + variable RXBYTEISALIGNED1_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC10_GlitchData : VitalGlitchDataType; + variable RXLOSSOFSYNC11_GlitchData : VitalGlitchDataType; + variable RXCHBONDO10_GlitchData : VitalGlitchDataType; + variable RXCHBONDO11_GlitchData : VitalGlitchDataType; + variable RXCHBONDO12_GlitchData : VitalGlitchDataType; + variable RXCHBONDO13_GlitchData : VitalGlitchDataType; + variable RXCHANBONDSEQ1_GlitchData : VitalGlitchDataType; + variable RXCHANREALIGN1_GlitchData : VitalGlitchDataType; + variable RXCHANISALIGNED1_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS10_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS11_GlitchData : VitalGlitchDataType; + variable RXBUFSTATUS12_GlitchData : VitalGlitchDataType; + variable PHYSTATUS0_GlitchData : VitalGlitchDataType; + variable PHYSTATUS1_GlitchData : VitalGlitchDataType; + variable RXELECIDLE0_GlitchData : VitalGlitchDataType; + variable RXSTATUS00_GlitchData : VitalGlitchDataType; + variable RXSTATUS01_GlitchData : VitalGlitchDataType; + variable RXSTATUS02_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT00_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT01_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT02_GlitchData : VitalGlitchDataType; + variable RXELECIDLE1_GlitchData : VitalGlitchDataType; + variable RXSTATUS10_GlitchData : VitalGlitchDataType; + variable RXSTATUS11_GlitchData : VitalGlitchDataType; + variable RXSTATUS12_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT10_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT11_GlitchData : VitalGlitchDataType; + variable RXCLKCORCNT12_GlitchData : VitalGlitchDataType; + variable PLLLKDET_GlitchData : VitalGlitchDataType; + variable RXPRBSERR0_GlitchData : VitalGlitchDataType; + variable RXPRBSERR1_GlitchData : VitalGlitchDataType; + variable DO0_GlitchData : VitalGlitchDataType; + variable DO1_GlitchData : VitalGlitchDataType; + variable DO2_GlitchData : VitalGlitchDataType; + variable DO3_GlitchData : VitalGlitchDataType; + variable DO4_GlitchData : VitalGlitchDataType; + variable DO5_GlitchData : VitalGlitchDataType; + variable DO6_GlitchData : VitalGlitchDataType; + variable DO7_GlitchData : VitalGlitchDataType; + variable DO8_GlitchData : VitalGlitchDataType; + variable DO9_GlitchData : VitalGlitchDataType; + variable DO10_GlitchData : VitalGlitchDataType; + variable DO11_GlitchData : VitalGlitchDataType; + variable DO12_GlitchData : VitalGlitchDataType; + variable DO13_GlitchData : VitalGlitchDataType; + variable DO14_GlitchData : VitalGlitchDataType; + variable DO15_GlitchData : VitalGlitchDataType; + variable DRDY_GlitchData : VitalGlitchDataType; + variable RXOVERSAMPLEERR0_GlitchData : VitalGlitchDataType; + variable RXOVERSAMPLEERR1_GlitchData : VitalGlitchDataType; + variable TXGEARBOXREADY0_GlitchData : VitalGlitchDataType; + variable RXHEADER00_GlitchData : VitalGlitchDataType; + variable RXHEADER01_GlitchData : VitalGlitchDataType; + variable RXHEADER02_GlitchData : VitalGlitchDataType; + variable RXHEADERVALID0_GlitchData : VitalGlitchDataType; + variable RXDATAVALID0_GlitchData : VitalGlitchDataType; + variable RXSTARTOFSEQ0_GlitchData : VitalGlitchDataType; + variable TXGEARBOXREADY1_GlitchData : VitalGlitchDataType; + variable RXHEADER10_GlitchData : VitalGlitchDataType; + variable RXHEADER11_GlitchData : VitalGlitchDataType; + variable RXHEADER12_GlitchData : VitalGlitchDataType; + variable RXHEADERVALID1_GlitchData : VitalGlitchDataType; + variable RXDATAVALID1_GlitchData : VitalGlitchDataType; + variable RXSTARTOFSEQ1_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR00_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR01_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR02_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR03_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR04_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR05_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR00_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR01_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR02_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR03_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR04_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR00_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR01_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR02_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR03_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR04_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR00_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR01_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR02_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR03_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR04_GlitchData : VitalGlitchDataType; + variable DFETAP3MONITOR00_GlitchData : VitalGlitchDataType; + variable DFETAP3MONITOR01_GlitchData : VitalGlitchDataType; + variable DFETAP3MONITOR02_GlitchData : VitalGlitchDataType; + variable DFETAP3MONITOR03_GlitchData : VitalGlitchDataType; + variable DFETAP4MONITOR00_GlitchData : VitalGlitchDataType; + variable DFETAP4MONITOR01_GlitchData : VitalGlitchDataType; + variable DFETAP4MONITOR02_GlitchData : VitalGlitchDataType; + variable DFETAP4MONITOR03_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR10_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR11_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR12_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR13_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR14_GlitchData : VitalGlitchDataType; + variable DFECLKDLYADJMONITOR15_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR10_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR11_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR12_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR13_GlitchData : VitalGlitchDataType; + variable DFEEYEDACMONITOR14_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR10_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR11_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR12_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR13_GlitchData : VitalGlitchDataType; + variable DFETAP1MONITOR14_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR10_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR11_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR12_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR13_GlitchData : VitalGlitchDataType; + variable DFETAP2MONITOR14_GlitchData : VitalGlitchDataType; + variable DFETAP3MONITOR10_GlitchData : VitalGlitchDataType; + variable DFETAP3MONITOR11_GlitchData : VitalGlitchDataType; + variable DFETAP3MONITOR12_GlitchData : VitalGlitchDataType; + variable DFETAP3MONITOR13_GlitchData : VitalGlitchDataType; + variable DFETAP4MONITOR10_GlitchData : VitalGlitchDataType; + variable DFETAP4MONITOR11_GlitchData : VitalGlitchDataType; + variable DFETAP4MONITOR12_GlitchData : VitalGlitchDataType; + variable DFETAP4MONITOR13_GlitchData : VitalGlitchDataType; + variable DFESENSCAL00_GlitchData : VitalGlitchDataType; + variable DFESENSCAL01_GlitchData : VitalGlitchDataType; + variable DFESENSCAL02_GlitchData : VitalGlitchDataType; + variable DFESENSCAL10_GlitchData : VitalGlitchDataType; + variable DFESENSCAL11_GlitchData : VitalGlitchDataType; + variable DFESENSCAL12_GlitchData : VitalGlitchDataType; +begin + + VitalPathDelay01 + ( + OutSignal => REFCLKOUT, + GlitchData => REFCLKOUT_GlitchData, + OutSignalName => "REFCLKOUT", + OutTemp => REFCLKOUT_OUT, + Paths => (0 => (CLKIN_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(0), + GlitchData => RXDATA00_GlitchData, + OutSignalName => "RXDATA0(0)", + OutTemp => RXDATA0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(1), + GlitchData => RXDATA01_GlitchData, + OutSignalName => "RXDATA0(1)", + OutTemp => RXDATA0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(2), + GlitchData => RXDATA02_GlitchData, + OutSignalName => "RXDATA0(2)", + OutTemp => RXDATA0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(3), + GlitchData => RXDATA03_GlitchData, + OutSignalName => "RXDATA0(3)", + OutTemp => RXDATA0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(4), + GlitchData => RXDATA04_GlitchData, + OutSignalName => "RXDATA0(4)", + OutTemp => RXDATA0_OUT(4), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(5), + GlitchData => RXDATA05_GlitchData, + OutSignalName => "RXDATA0(5)", + OutTemp => RXDATA0_OUT(5), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(6), + GlitchData => RXDATA06_GlitchData, + OutSignalName => "RXDATA0(6)", + OutTemp => RXDATA0_OUT(6), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(7), + GlitchData => RXDATA07_GlitchData, + OutSignalName => "RXDATA0(7)", + OutTemp => RXDATA0_OUT(7), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(8), + GlitchData => RXDATA08_GlitchData, + OutSignalName => "RXDATA0(8)", + OutTemp => RXDATA0_OUT(8), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(9), + GlitchData => RXDATA09_GlitchData, + OutSignalName => "RXDATA0(9)", + OutTemp => RXDATA0_OUT(9), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(10), + GlitchData => RXDATA010_GlitchData, + OutSignalName => "RXDATA0(10)", + OutTemp => RXDATA0_OUT(10), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(11), + GlitchData => RXDATA011_GlitchData, + OutSignalName => "RXDATA0(11)", + OutTemp => RXDATA0_OUT(11), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(12), + GlitchData => RXDATA012_GlitchData, + OutSignalName => "RXDATA0(12)", + OutTemp => RXDATA0_OUT(12), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(13), + GlitchData => RXDATA013_GlitchData, + OutSignalName => "RXDATA0(13)", + OutTemp => RXDATA0_OUT(13), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(14), + GlitchData => RXDATA014_GlitchData, + OutSignalName => "RXDATA0(14)", + OutTemp => RXDATA0_OUT(14), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(15), + GlitchData => RXDATA015_GlitchData, + OutSignalName => "RXDATA0(15)", + OutTemp => RXDATA0_OUT(15), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(16), + GlitchData => RXDATA016_GlitchData, + OutSignalName => "RXDATA0(16)", + OutTemp => RXDATA0_OUT(16), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(17), + GlitchData => RXDATA017_GlitchData, + OutSignalName => "RXDATA0(17)", + OutTemp => RXDATA0_OUT(17), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(18), + GlitchData => RXDATA018_GlitchData, + OutSignalName => "RXDATA0(18)", + OutTemp => RXDATA0_OUT(18), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(19), + GlitchData => RXDATA019_GlitchData, + OutSignalName => "RXDATA0(19)", + OutTemp => RXDATA0_OUT(19), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(20), + GlitchData => RXDATA020_GlitchData, + OutSignalName => "RXDATA0(20)", + OutTemp => RXDATA0_OUT(20), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(21), + GlitchData => RXDATA021_GlitchData, + OutSignalName => "RXDATA0(21)", + OutTemp => RXDATA0_OUT(21), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(22), + GlitchData => RXDATA022_GlitchData, + OutSignalName => "RXDATA0(22)", + OutTemp => RXDATA0_OUT(22), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(23), + GlitchData => RXDATA023_GlitchData, + OutSignalName => "RXDATA0(23)", + OutTemp => RXDATA0_OUT(23), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(24), + GlitchData => RXDATA024_GlitchData, + OutSignalName => "RXDATA0(24)", + OutTemp => RXDATA0_OUT(24), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(25), + GlitchData => RXDATA025_GlitchData, + OutSignalName => "RXDATA0(25)", + OutTemp => RXDATA0_OUT(25), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(26), + GlitchData => RXDATA026_GlitchData, + OutSignalName => "RXDATA0(26)", + OutTemp => RXDATA0_OUT(26), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(27), + GlitchData => RXDATA027_GlitchData, + OutSignalName => "RXDATA0(27)", + OutTemp => RXDATA0_OUT(27), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(28), + GlitchData => RXDATA028_GlitchData, + OutSignalName => "RXDATA0(28)", + OutTemp => RXDATA0_OUT(28), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(29), + GlitchData => RXDATA029_GlitchData, + OutSignalName => "RXDATA0(29)", + OutTemp => RXDATA0_OUT(29), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(30), + GlitchData => RXDATA030_GlitchData, + OutSignalName => "RXDATA0(30)", + OutTemp => RXDATA0_OUT(30), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA0(31), + GlitchData => RXDATA031_GlitchData, + OutSignalName => "RXDATA0(31)", + OutTemp => RXDATA0_OUT(31), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE0(0), + GlitchData => RXNOTINTABLE00_GlitchData, + OutSignalName => "RXNOTINTABLE0(0)", + OutTemp => RXNOTINTABLE0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE0(1), + GlitchData => RXNOTINTABLE01_GlitchData, + OutSignalName => "RXNOTINTABLE0(1)", + OutTemp => RXNOTINTABLE0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE0(2), + GlitchData => RXNOTINTABLE02_GlitchData, + OutSignalName => "RXNOTINTABLE0(2)", + OutTemp => RXNOTINTABLE0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE0(3), + GlitchData => RXNOTINTABLE03_GlitchData, + OutSignalName => "RXNOTINTABLE0(3)", + OutTemp => RXNOTINTABLE0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR0(0), + GlitchData => RXDISPERR00_GlitchData, + OutSignalName => "RXDISPERR0(0)", + OutTemp => RXDISPERR0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR0(1), + GlitchData => RXDISPERR01_GlitchData, + OutSignalName => "RXDISPERR0(1)", + OutTemp => RXDISPERR0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR0(2), + GlitchData => RXDISPERR02_GlitchData, + OutSignalName => "RXDISPERR0(2)", + OutTemp => RXDISPERR0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR0(3), + GlitchData => RXDISPERR03_GlitchData, + OutSignalName => "RXDISPERR0(3)", + OutTemp => RXDISPERR0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK0(0), + GlitchData => RXCHARISK00_GlitchData, + OutSignalName => "RXCHARISK0(0)", + OutTemp => RXCHARISK0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK0(1), + GlitchData => RXCHARISK01_GlitchData, + OutSignalName => "RXCHARISK0(1)", + OutTemp => RXCHARISK0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK0(2), + GlitchData => RXCHARISK02_GlitchData, + OutSignalName => "RXCHARISK0(2)", + OutTemp => RXCHARISK0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK0(3), + GlitchData => RXCHARISK03_GlitchData, + OutSignalName => "RXCHARISK0(3)", + OutTemp => RXCHARISK0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP0(0), + GlitchData => RXRUNDISP00_GlitchData, + OutSignalName => "RXRUNDISP0(0)", + OutTemp => RXRUNDISP0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP0(1), + GlitchData => RXRUNDISP01_GlitchData, + OutSignalName => "RXRUNDISP0(1)", + OutTemp => RXRUNDISP0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP0(2), + GlitchData => RXRUNDISP02_GlitchData, + OutSignalName => "RXRUNDISP0(2)", + OutTemp => RXRUNDISP0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP0(3), + GlitchData => RXRUNDISP03_GlitchData, + OutSignalName => "RXRUNDISP0(3)", + OutTemp => RXRUNDISP0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA0(0), + GlitchData => RXCHARISCOMMA00_GlitchData, + OutSignalName => "RXCHARISCOMMA0(0)", + OutTemp => RXCHARISCOMMA0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA0(1), + GlitchData => RXCHARISCOMMA01_GlitchData, + OutSignalName => "RXCHARISCOMMA0(1)", + OutTemp => RXCHARISCOMMA0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA0(2), + GlitchData => RXCHARISCOMMA02_GlitchData, + OutSignalName => "RXCHARISCOMMA0(2)", + OutTemp => RXCHARISCOMMA0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA0(3), + GlitchData => RXCHARISCOMMA03_GlitchData, + OutSignalName => "RXCHARISCOMMA0(3)", + OutTemp => RXCHARISCOMMA0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXVALID0, + GlitchData => RXVALID0_GlitchData, + OutSignalName => "RXVALID0", + OutTemp => RXVALID0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(0), + GlitchData => RXDATA10_GlitchData, + OutSignalName => "RXDATA1(0)", + OutTemp => RXDATA1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(1), + GlitchData => RXDATA11_GlitchData, + OutSignalName => "RXDATA1(1)", + OutTemp => RXDATA1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(2), + GlitchData => RXDATA12_GlitchData, + OutSignalName => "RXDATA1(2)", + OutTemp => RXDATA1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(3), + GlitchData => RXDATA13_GlitchData, + OutSignalName => "RXDATA1(3)", + OutTemp => RXDATA1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(4), + GlitchData => RXDATA14_GlitchData, + OutSignalName => "RXDATA1(4)", + OutTemp => RXDATA1_OUT(4), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(5), + GlitchData => RXDATA15_GlitchData, + OutSignalName => "RXDATA1(5)", + OutTemp => RXDATA1_OUT(5), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(6), + GlitchData => RXDATA16_GlitchData, + OutSignalName => "RXDATA1(6)", + OutTemp => RXDATA1_OUT(6), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(7), + GlitchData => RXDATA17_GlitchData, + OutSignalName => "RXDATA1(7)", + OutTemp => RXDATA1_OUT(7), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(8), + GlitchData => RXDATA18_GlitchData, + OutSignalName => "RXDATA1(8)", + OutTemp => RXDATA1_OUT(8), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(9), + GlitchData => RXDATA19_GlitchData, + OutSignalName => "RXDATA1(9)", + OutTemp => RXDATA1_OUT(9), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(10), + GlitchData => RXDATA110_GlitchData, + OutSignalName => "RXDATA1(10)", + OutTemp => RXDATA1_OUT(10), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(11), + GlitchData => RXDATA111_GlitchData, + OutSignalName => "RXDATA1(11)", + OutTemp => RXDATA1_OUT(11), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(12), + GlitchData => RXDATA112_GlitchData, + OutSignalName => "RXDATA1(12)", + OutTemp => RXDATA1_OUT(12), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(13), + GlitchData => RXDATA113_GlitchData, + OutSignalName => "RXDATA1(13)", + OutTemp => RXDATA1_OUT(13), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(14), + GlitchData => RXDATA114_GlitchData, + OutSignalName => "RXDATA1(14)", + OutTemp => RXDATA1_OUT(14), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(15), + GlitchData => RXDATA115_GlitchData, + OutSignalName => "RXDATA1(15)", + OutTemp => RXDATA1_OUT(15), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(16), + GlitchData => RXDATA116_GlitchData, + OutSignalName => "RXDATA1(16)", + OutTemp => RXDATA1_OUT(16), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(17), + GlitchData => RXDATA117_GlitchData, + OutSignalName => "RXDATA1(17)", + OutTemp => RXDATA1_OUT(17), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(18), + GlitchData => RXDATA118_GlitchData, + OutSignalName => "RXDATA1(18)", + OutTemp => RXDATA1_OUT(18), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(19), + GlitchData => RXDATA119_GlitchData, + OutSignalName => "RXDATA1(19)", + OutTemp => RXDATA1_OUT(19), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(20), + GlitchData => RXDATA120_GlitchData, + OutSignalName => "RXDATA1(20)", + OutTemp => RXDATA1_OUT(20), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(21), + GlitchData => RXDATA121_GlitchData, + OutSignalName => "RXDATA1(21)", + OutTemp => RXDATA1_OUT(21), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(22), + GlitchData => RXDATA122_GlitchData, + OutSignalName => "RXDATA1(22)", + OutTemp => RXDATA1_OUT(22), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(23), + GlitchData => RXDATA123_GlitchData, + OutSignalName => "RXDATA1(23)", + OutTemp => RXDATA1_OUT(23), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(24), + GlitchData => RXDATA124_GlitchData, + OutSignalName => "RXDATA1(24)", + OutTemp => RXDATA1_OUT(24), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(25), + GlitchData => RXDATA125_GlitchData, + OutSignalName => "RXDATA1(25)", + OutTemp => RXDATA1_OUT(25), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(26), + GlitchData => RXDATA126_GlitchData, + OutSignalName => "RXDATA1(26)", + OutTemp => RXDATA1_OUT(26), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(27), + GlitchData => RXDATA127_GlitchData, + OutSignalName => "RXDATA1(27)", + OutTemp => RXDATA1_OUT(27), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(28), + GlitchData => RXDATA128_GlitchData, + OutSignalName => "RXDATA1(28)", + OutTemp => RXDATA1_OUT(28), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(29), + GlitchData => RXDATA129_GlitchData, + OutSignalName => "RXDATA1(29)", + OutTemp => RXDATA1_OUT(29), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(30), + GlitchData => RXDATA130_GlitchData, + OutSignalName => "RXDATA1(30)", + OutTemp => RXDATA1_OUT(30), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATA1(31), + GlitchData => RXDATA131_GlitchData, + OutSignalName => "RXDATA1(31)", + OutTemp => RXDATA1_OUT(31), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE1(0), + GlitchData => RXNOTINTABLE10_GlitchData, + OutSignalName => "RXNOTINTABLE1(0)", + OutTemp => RXNOTINTABLE1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE1(1), + GlitchData => RXNOTINTABLE11_GlitchData, + OutSignalName => "RXNOTINTABLE1(1)", + OutTemp => RXNOTINTABLE1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE1(2), + GlitchData => RXNOTINTABLE12_GlitchData, + OutSignalName => "RXNOTINTABLE1(2)", + OutTemp => RXNOTINTABLE1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXNOTINTABLE1(3), + GlitchData => RXNOTINTABLE13_GlitchData, + OutSignalName => "RXNOTINTABLE1(3)", + OutTemp => RXNOTINTABLE1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR1(0), + GlitchData => RXDISPERR10_GlitchData, + OutSignalName => "RXDISPERR1(0)", + OutTemp => RXDISPERR1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR1(1), + GlitchData => RXDISPERR11_GlitchData, + OutSignalName => "RXDISPERR1(1)", + OutTemp => RXDISPERR1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR1(2), + GlitchData => RXDISPERR12_GlitchData, + OutSignalName => "RXDISPERR1(2)", + OutTemp => RXDISPERR1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDISPERR1(3), + GlitchData => RXDISPERR13_GlitchData, + OutSignalName => "RXDISPERR1(3)", + OutTemp => RXDISPERR1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK1(0), + GlitchData => RXCHARISK10_GlitchData, + OutSignalName => "RXCHARISK1(0)", + OutTemp => RXCHARISK1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK1(1), + GlitchData => RXCHARISK11_GlitchData, + OutSignalName => "RXCHARISK1(1)", + OutTemp => RXCHARISK1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK1(2), + GlitchData => RXCHARISK12_GlitchData, + OutSignalName => "RXCHARISK1(2)", + OutTemp => RXCHARISK1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISK1(3), + GlitchData => RXCHARISK13_GlitchData, + OutSignalName => "RXCHARISK1(3)", + OutTemp => RXCHARISK1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP1(0), + GlitchData => RXRUNDISP10_GlitchData, + OutSignalName => "RXRUNDISP1(0)", + OutTemp => RXRUNDISP1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP1(1), + GlitchData => RXRUNDISP11_GlitchData, + OutSignalName => "RXRUNDISP1(1)", + OutTemp => RXRUNDISP1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP1(2), + GlitchData => RXRUNDISP12_GlitchData, + OutSignalName => "RXRUNDISP1(2)", + OutTemp => RXRUNDISP1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXRUNDISP1(3), + GlitchData => RXRUNDISP13_GlitchData, + OutSignalName => "RXRUNDISP1(3)", + OutTemp => RXRUNDISP1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA1(0), + GlitchData => RXCHARISCOMMA10_GlitchData, + OutSignalName => "RXCHARISCOMMA1(0)", + OutTemp => RXCHARISCOMMA1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA1(1), + GlitchData => RXCHARISCOMMA11_GlitchData, + OutSignalName => "RXCHARISCOMMA1(1)", + OutTemp => RXCHARISCOMMA1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA1(2), + GlitchData => RXCHARISCOMMA12_GlitchData, + OutSignalName => "RXCHARISCOMMA1(2)", + OutTemp => RXCHARISCOMMA1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHARISCOMMA1(3), + GlitchData => RXCHARISCOMMA13_GlitchData, + OutSignalName => "RXCHARISCOMMA1(3)", + OutTemp => RXCHARISCOMMA1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXVALID1, + GlitchData => RXVALID1_GlitchData, + OutSignalName => "RXVALID1", + OutTemp => RXVALID1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR0(0), + GlitchData => TXKERR00_GlitchData, + OutSignalName => "TXKERR0(0)", + OutTemp => TXKERR0_OUT(0), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR0(1), + GlitchData => TXKERR01_GlitchData, + OutSignalName => "TXKERR0(1)", + OutTemp => TXKERR0_OUT(1), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR0(2), + GlitchData => TXKERR02_GlitchData, + OutSignalName => "TXKERR0(2)", + OutTemp => TXKERR0_OUT(2), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR0(3), + GlitchData => TXKERR03_GlitchData, + OutSignalName => "TXKERR0(3)", + OutTemp => TXKERR0_OUT(3), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP0(0), + GlitchData => TXRUNDISP00_GlitchData, + OutSignalName => "TXRUNDISP0(0)", + OutTemp => TXRUNDISP0_OUT(0), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP0(1), + GlitchData => TXRUNDISP01_GlitchData, + OutSignalName => "TXRUNDISP0(1)", + OutTemp => TXRUNDISP0_OUT(1), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP0(2), + GlitchData => TXRUNDISP02_GlitchData, + OutSignalName => "TXRUNDISP0(2)", + OutTemp => TXRUNDISP0_OUT(2), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP0(3), + GlitchData => TXRUNDISP03_GlitchData, + OutSignalName => "TXRUNDISP0(3)", + OutTemp => TXRUNDISP0_OUT(3), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXBUFSTATUS0(0), + GlitchData => TXBUFSTATUS00_GlitchData, + OutSignalName => "TXBUFSTATUS0(0)", + OutTemp => TXBUFSTATUS0_OUT(0), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXBUFSTATUS0(1), + GlitchData => TXBUFSTATUS01_GlitchData, + OutSignalName => "TXBUFSTATUS0(1)", + OutTemp => TXBUFSTATUS0_OUT(1), + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR1(0), + GlitchData => TXKERR10_GlitchData, + OutSignalName => "TXKERR1(0)", + OutTemp => TXKERR1_OUT(0), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR1(1), + GlitchData => TXKERR11_GlitchData, + OutSignalName => "TXKERR1(1)", + OutTemp => TXKERR1_OUT(1), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR1(2), + GlitchData => TXKERR12_GlitchData, + OutSignalName => "TXKERR1(2)", + OutTemp => TXKERR1_OUT(2), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXKERR1(3), + GlitchData => TXKERR13_GlitchData, + OutSignalName => "TXKERR1(3)", + OutTemp => TXKERR1_OUT(3), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP1(0), + GlitchData => TXRUNDISP10_GlitchData, + OutSignalName => "TXRUNDISP1(0)", + OutTemp => TXRUNDISP1_OUT(0), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP1(1), + GlitchData => TXRUNDISP11_GlitchData, + OutSignalName => "TXRUNDISP1(1)", + OutTemp => TXRUNDISP1_OUT(1), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP1(2), + GlitchData => TXRUNDISP12_GlitchData, + OutSignalName => "TXRUNDISP1(2)", + OutTemp => TXRUNDISP1_OUT(2), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXRUNDISP1(3), + GlitchData => TXRUNDISP13_GlitchData, + OutSignalName => "TXRUNDISP1(3)", + OutTemp => TXRUNDISP1_OUT(3), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXBUFSTATUS1(0), + GlitchData => TXBUFSTATUS10_GlitchData, + OutSignalName => "TXBUFSTATUS1(0)", + OutTemp => TXBUFSTATUS1_OUT(0), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXBUFSTATUS1(1), + GlitchData => TXBUFSTATUS11_GlitchData, + OutSignalName => "TXBUFSTATUS1(1)", + OutTemp => TXBUFSTATUS1_OUT(1), + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCOMMADET0, + GlitchData => RXCOMMADET0_GlitchData, + OutSignalName => "RXCOMMADET0", + OutTemp => RXCOMMADET0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBYTEREALIGN0, + GlitchData => RXBYTEREALIGN0_GlitchData, + OutSignalName => "RXBYTEREALIGN0", + OutTemp => RXBYTEREALIGN0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBYTEISALIGNED0, + GlitchData => RXBYTEISALIGNED0_GlitchData, + OutSignalName => "RXBYTEISALIGNED0", + OutTemp => RXBYTEISALIGNED0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC0(0), + GlitchData => RXLOSSOFSYNC00_GlitchData, + OutSignalName => "RXLOSSOFSYNC0(0)", + OutTemp => RXLOSSOFSYNC0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC0(1), + GlitchData => RXLOSSOFSYNC01_GlitchData, + OutSignalName => "RXLOSSOFSYNC0(1)", + OutTemp => RXLOSSOFSYNC0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO0(0), + GlitchData => RXCHBONDO00_GlitchData, + OutSignalName => "RXCHBONDO0(0)", + OutTemp => RXCHBONDO0_OUT(0), + Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO0(1), + GlitchData => RXCHBONDO01_GlitchData, + OutSignalName => "RXCHBONDO0(1)", + OutTemp => RXCHBONDO0_OUT(1), + Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO0(2), + GlitchData => RXCHBONDO02_GlitchData, + OutSignalName => "RXCHBONDO0(2)", + OutTemp => RXCHBONDO0_OUT(2), + Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO0(3), + GlitchData => RXCHBONDO03_GlitchData, + OutSignalName => "RXCHBONDO0(3)", + OutTemp => RXCHBONDO0_OUT(3), + Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANBONDSEQ0, + GlitchData => RXCHANBONDSEQ0_GlitchData, + OutSignalName => "RXCHANBONDSEQ0", + OutTemp => RXCHANBONDSEQ0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANREALIGN0, + GlitchData => RXCHANREALIGN0_GlitchData, + OutSignalName => "RXCHANREALIGN0", + OutTemp => RXCHANREALIGN0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANISALIGNED0, + GlitchData => RXCHANISALIGNED0_GlitchData, + OutSignalName => "RXCHANISALIGNED0", + OutTemp => RXCHANISALIGNED0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS0(0), + GlitchData => RXBUFSTATUS00_GlitchData, + OutSignalName => "RXBUFSTATUS0(0)", + OutTemp => RXBUFSTATUS0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS0(1), + GlitchData => RXBUFSTATUS01_GlitchData, + OutSignalName => "RXBUFSTATUS0(1)", + OutTemp => RXBUFSTATUS0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS0(2), + GlitchData => RXBUFSTATUS02_GlitchData, + OutSignalName => "RXBUFSTATUS0(2)", + OutTemp => RXBUFSTATUS0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCOMMADET1, + GlitchData => RXCOMMADET1_GlitchData, + OutSignalName => "RXCOMMADET1", + OutTemp => RXCOMMADET1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBYTEREALIGN1, + GlitchData => RXBYTEREALIGN1_GlitchData, + OutSignalName => "RXBYTEREALIGN1", + OutTemp => RXBYTEREALIGN1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBYTEISALIGNED1, + GlitchData => RXBYTEISALIGNED1_GlitchData, + OutSignalName => "RXBYTEISALIGNED1", + OutTemp => RXBYTEISALIGNED1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC1(0), + GlitchData => RXLOSSOFSYNC10_GlitchData, + OutSignalName => "RXLOSSOFSYNC1(0)", + OutTemp => RXLOSSOFSYNC1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXLOSSOFSYNC1(1), + GlitchData => RXLOSSOFSYNC11_GlitchData, + OutSignalName => "RXLOSSOFSYNC1(1)", + OutTemp => RXLOSSOFSYNC1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO1(0), + GlitchData => RXCHBONDO10_GlitchData, + OutSignalName => "RXCHBONDO1(0)", + OutTemp => RXCHBONDO1_OUT(0), + Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO1(1), + GlitchData => RXCHBONDO11_GlitchData, + OutSignalName => "RXCHBONDO1(1)", + OutTemp => RXCHBONDO1_OUT(1), + Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO1(2), + GlitchData => RXCHBONDO12_GlitchData, + OutSignalName => "RXCHBONDO1(2)", + OutTemp => RXCHBONDO1_OUT(2), + Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHBONDO1(3), + GlitchData => RXCHBONDO13_GlitchData, + OutSignalName => "RXCHBONDO1(3)", + OutTemp => RXCHBONDO1_OUT(3), + Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANBONDSEQ1, + GlitchData => RXCHANBONDSEQ1_GlitchData, + OutSignalName => "RXCHANBONDSEQ1", + OutTemp => RXCHANBONDSEQ1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANREALIGN1, + GlitchData => RXCHANREALIGN1_GlitchData, + OutSignalName => "RXCHANREALIGN1", + OutTemp => RXCHANREALIGN1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCHANISALIGNED1, + GlitchData => RXCHANISALIGNED1_GlitchData, + OutSignalName => "RXCHANISALIGNED1", + OutTemp => RXCHANISALIGNED1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS1(0), + GlitchData => RXBUFSTATUS10_GlitchData, + OutSignalName => "RXBUFSTATUS1(0)", + OutTemp => RXBUFSTATUS1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS1(1), + GlitchData => RXBUFSTATUS11_GlitchData, + OutSignalName => "RXBUFSTATUS1(1)", + OutTemp => RXBUFSTATUS1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXBUFSTATUS1(2), + GlitchData => RXBUFSTATUS12_GlitchData, + OutSignalName => "RXBUFSTATUS1(2)", + OutTemp => RXBUFSTATUS1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PHYSTATUS0, + GlitchData => PHYSTATUS0_GlitchData, + OutSignalName => "PHYSTATUS0", + OutTemp => PHYSTATUS0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PHYSTATUS1, + GlitchData => PHYSTATUS1_GlitchData, + OutSignalName => "PHYSTATUS1", + OutTemp => PHYSTATUS1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS0(0), + GlitchData => RXSTATUS00_GlitchData, + OutSignalName => "RXSTATUS0(0)", + OutTemp => RXSTATUS0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS0(1), + GlitchData => RXSTATUS01_GlitchData, + OutSignalName => "RXSTATUS0(1)", + OutTemp => RXSTATUS0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS0(2), + GlitchData => RXSTATUS02_GlitchData, + OutSignalName => "RXSTATUS0(2)", + OutTemp => RXSTATUS0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT0(0), + GlitchData => RXCLKCORCNT00_GlitchData, + OutSignalName => "RXCLKCORCNT0(0)", + OutTemp => RXCLKCORCNT0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT0(1), + GlitchData => RXCLKCORCNT01_GlitchData, + OutSignalName => "RXCLKCORCNT0(1)", + OutTemp => RXCLKCORCNT0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT0(2), + GlitchData => RXCLKCORCNT02_GlitchData, + OutSignalName => "RXCLKCORCNT0(2)", + OutTemp => RXCLKCORCNT0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS1(0), + GlitchData => RXSTATUS10_GlitchData, + OutSignalName => "RXSTATUS1(0)", + OutTemp => RXSTATUS1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS1(1), + GlitchData => RXSTATUS11_GlitchData, + OutSignalName => "RXSTATUS1(1)", + OutTemp => RXSTATUS1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTATUS1(2), + GlitchData => RXSTATUS12_GlitchData, + OutSignalName => "RXSTATUS1(2)", + OutTemp => RXSTATUS1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT1(0), + GlitchData => RXCLKCORCNT10_GlitchData, + OutSignalName => "RXCLKCORCNT1(0)", + OutTemp => RXCLKCORCNT1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT1(1), + GlitchData => RXCLKCORCNT11_GlitchData, + OutSignalName => "RXCLKCORCNT1(1)", + OutTemp => RXCLKCORCNT1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXCLKCORCNT1(2), + GlitchData => RXCLKCORCNT12_GlitchData, + OutSignalName => "RXCLKCORCNT1(2)", + OutTemp => RXCLKCORCNT1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXPRBSERR0, + GlitchData => RXPRBSERR0_GlitchData, + OutSignalName => "RXPRBSERR0", + OutTemp => RXPRBSERR0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXPRBSERR1, + GlitchData => RXPRBSERR1_GlitchData, + OutSignalName => "RXPRBSERR1", + OutTemp => RXPRBSERR1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(0), + GlitchData => DO0_GlitchData, + OutSignalName => "DO(0)", + OutTemp => DO_OUT(0), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(1), + GlitchData => DO1_GlitchData, + OutSignalName => "DO(1)", + OutTemp => DO_OUT(1), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(2), + GlitchData => DO2_GlitchData, + OutSignalName => "DO(2)", + OutTemp => DO_OUT(2), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(3), + GlitchData => DO3_GlitchData, + OutSignalName => "DO(3)", + OutTemp => DO_OUT(3), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(4), + GlitchData => DO4_GlitchData, + OutSignalName => "DO(4)", + OutTemp => DO_OUT(4), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(5), + GlitchData => DO5_GlitchData, + OutSignalName => "DO(5)", + OutTemp => DO_OUT(5), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(6), + GlitchData => DO6_GlitchData, + OutSignalName => "DO(6)", + OutTemp => DO_OUT(6), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(7), + GlitchData => DO7_GlitchData, + OutSignalName => "DO(7)", + OutTemp => DO_OUT(7), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(8), + GlitchData => DO8_GlitchData, + OutSignalName => "DO(8)", + OutTemp => DO_OUT(8), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(9), + GlitchData => DO9_GlitchData, + OutSignalName => "DO(9)", + OutTemp => DO_OUT(9), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(10), + GlitchData => DO10_GlitchData, + OutSignalName => "DO(10)", + OutTemp => DO_OUT(10), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(11), + GlitchData => DO11_GlitchData, + OutSignalName => "DO(11)", + OutTemp => DO_OUT(11), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(12), + GlitchData => DO12_GlitchData, + OutSignalName => "DO(12)", + OutTemp => DO_OUT(12), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(13), + GlitchData => DO13_GlitchData, + OutSignalName => "DO(13)", + OutTemp => DO_OUT(13), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(14), + GlitchData => DO14_GlitchData, + OutSignalName => "DO(14)", + OutTemp => DO_OUT(14), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DO(15), + GlitchData => DO15_GlitchData, + OutSignalName => "DO(15)", + OutTemp => DO_OUT(15), + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DRDY, + GlitchData => DRDY_GlitchData, + OutSignalName => "DRDY", + OutTemp => DRDY_OUT, + Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXOVERSAMPLEERR0, + GlitchData => RXOVERSAMPLEERR0_GlitchData, + OutSignalName => "RXOVERSAMPLEERR0", + OutTemp => RXOVERSAMPLEERR0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXOVERSAMPLEERR1, + GlitchData => RXOVERSAMPLEERR1_GlitchData, + OutSignalName => "RXOVERSAMPLEERR1", + OutTemp => RXOVERSAMPLEERR1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXGEARBOXREADY0, + GlitchData => TXGEARBOXREADY0_GlitchData, + OutSignalName => "TXGEARBOXREADY0", + OutTemp => TXGEARBOXREADY0_OUT, + Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXHEADER0(0), + GlitchData => RXHEADER00_GlitchData, + OutSignalName => "RXHEADER0(0)", + OutTemp => RXHEADER0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXHEADER0(1), + GlitchData => RXHEADER01_GlitchData, + OutSignalName => "RXHEADER0(1)", + OutTemp => RXHEADER0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXHEADER0(2), + GlitchData => RXHEADER02_GlitchData, + OutSignalName => "RXHEADER0(2)", + OutTemp => RXHEADER0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXHEADERVALID0, + GlitchData => RXHEADERVALID0_GlitchData, + OutSignalName => "RXHEADERVALID0", + OutTemp => RXHEADERVALID0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATAVALID0, + GlitchData => RXDATAVALID0_GlitchData, + OutSignalName => "RXDATAVALID0", + OutTemp => RXDATAVALID0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTARTOFSEQ0, + GlitchData => RXSTARTOFSEQ0_GlitchData, + OutSignalName => "RXSTARTOFSEQ0", + OutTemp => RXSTARTOFSEQ0_OUT, + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => TXGEARBOXREADY1, + GlitchData => TXGEARBOXREADY1_GlitchData, + OutSignalName => "TXGEARBOXREADY1", + OutTemp => TXGEARBOXREADY1_OUT, + Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXHEADER1(0), + GlitchData => RXHEADER10_GlitchData, + OutSignalName => "RXHEADER1(0)", + OutTemp => RXHEADER1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXHEADER1(1), + GlitchData => RXHEADER11_GlitchData, + OutSignalName => "RXHEADER1(1)", + OutTemp => RXHEADER1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXHEADER1(2), + GlitchData => RXHEADER12_GlitchData, + OutSignalName => "RXHEADER1(2)", + OutTemp => RXHEADER1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXHEADERVALID1, + GlitchData => RXHEADERVALID1_GlitchData, + OutSignalName => "RXHEADERVALID1", + OutTemp => RXHEADERVALID1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXDATAVALID1, + GlitchData => RXDATAVALID1_GlitchData, + OutSignalName => "RXDATAVALID1", + OutTemp => RXDATAVALID1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => RXSTARTOFSEQ1, + GlitchData => RXSTARTOFSEQ1_GlitchData, + OutSignalName => "RXSTARTOFSEQ1", + OutTemp => RXSTARTOFSEQ1_OUT, + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR0(0), + GlitchData => DFECLKDLYADJMONITOR00_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR0(0)", + OutTemp => DFECLKDLYADJMONITOR0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR0(1), + GlitchData => DFECLKDLYADJMONITOR01_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR0(1)", + OutTemp => DFECLKDLYADJMONITOR0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR0(2), + GlitchData => DFECLKDLYADJMONITOR02_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR0(2)", + OutTemp => DFECLKDLYADJMONITOR0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR0(3), + GlitchData => DFECLKDLYADJMONITOR03_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR0(3)", + OutTemp => DFECLKDLYADJMONITOR0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR0(4), + GlitchData => DFECLKDLYADJMONITOR04_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR0(4)", + OutTemp => DFECLKDLYADJMONITOR0_OUT(4), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR0(5), + GlitchData => DFECLKDLYADJMONITOR05_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR0(5)", + OutTemp => DFECLKDLYADJMONITOR0_OUT(5), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR0(0), + GlitchData => DFEEYEDACMONITOR00_GlitchData, + OutSignalName => "DFEEYEDACMONITOR0(0)", + OutTemp => DFEEYEDACMONITOR0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR0(1), + GlitchData => DFEEYEDACMONITOR01_GlitchData, + OutSignalName => "DFEEYEDACMONITOR0(1)", + OutTemp => DFEEYEDACMONITOR0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR0(2), + GlitchData => DFEEYEDACMONITOR02_GlitchData, + OutSignalName => "DFEEYEDACMONITOR0(2)", + OutTemp => DFEEYEDACMONITOR0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR0(3), + GlitchData => DFEEYEDACMONITOR03_GlitchData, + OutSignalName => "DFEEYEDACMONITOR0(3)", + OutTemp => DFEEYEDACMONITOR0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR0(4), + GlitchData => DFEEYEDACMONITOR04_GlitchData, + OutSignalName => "DFEEYEDACMONITOR0(4)", + OutTemp => DFEEYEDACMONITOR0_OUT(4), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR0(0), + GlitchData => DFETAP1MONITOR00_GlitchData, + OutSignalName => "DFETAP1MONITOR0(0)", + OutTemp => DFETAP1MONITOR0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR0(1), + GlitchData => DFETAP1MONITOR01_GlitchData, + OutSignalName => "DFETAP1MONITOR0(1)", + OutTemp => DFETAP1MONITOR0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR0(2), + GlitchData => DFETAP1MONITOR02_GlitchData, + OutSignalName => "DFETAP1MONITOR0(2)", + OutTemp => DFETAP1MONITOR0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR0(3), + GlitchData => DFETAP1MONITOR03_GlitchData, + OutSignalName => "DFETAP1MONITOR0(3)", + OutTemp => DFETAP1MONITOR0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR0(4), + GlitchData => DFETAP1MONITOR04_GlitchData, + OutSignalName => "DFETAP1MONITOR0(4)", + OutTemp => DFETAP1MONITOR0_OUT(4), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR0(0), + GlitchData => DFETAP2MONITOR00_GlitchData, + OutSignalName => "DFETAP2MONITOR0(0)", + OutTemp => DFETAP2MONITOR0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR0(1), + GlitchData => DFETAP2MONITOR01_GlitchData, + OutSignalName => "DFETAP2MONITOR0(1)", + OutTemp => DFETAP2MONITOR0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR0(2), + GlitchData => DFETAP2MONITOR02_GlitchData, + OutSignalName => "DFETAP2MONITOR0(2)", + OutTemp => DFETAP2MONITOR0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR0(3), + GlitchData => DFETAP2MONITOR03_GlitchData, + OutSignalName => "DFETAP2MONITOR0(3)", + OutTemp => DFETAP2MONITOR0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR0(4), + GlitchData => DFETAP2MONITOR04_GlitchData, + OutSignalName => "DFETAP2MONITOR0(4)", + OutTemp => DFETAP2MONITOR0_OUT(4), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP3MONITOR0(0), + GlitchData => DFETAP3MONITOR00_GlitchData, + OutSignalName => "DFETAP3MONITOR0(0)", + OutTemp => DFETAP3MONITOR0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP3MONITOR0(1), + GlitchData => DFETAP3MONITOR01_GlitchData, + OutSignalName => "DFETAP3MONITOR0(1)", + OutTemp => DFETAP3MONITOR0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP3MONITOR0(2), + GlitchData => DFETAP3MONITOR02_GlitchData, + OutSignalName => "DFETAP3MONITOR0(2)", + OutTemp => DFETAP3MONITOR0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP3MONITOR0(3), + GlitchData => DFETAP3MONITOR03_GlitchData, + OutSignalName => "DFETAP3MONITOR0(3)", + OutTemp => DFETAP3MONITOR0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP4MONITOR0(0), + GlitchData => DFETAP4MONITOR00_GlitchData, + OutSignalName => "DFETAP4MONITOR0(0)", + OutTemp => DFETAP4MONITOR0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP4MONITOR0(1), + GlitchData => DFETAP4MONITOR01_GlitchData, + OutSignalName => "DFETAP4MONITOR0(1)", + OutTemp => DFETAP4MONITOR0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP4MONITOR0(2), + GlitchData => DFETAP4MONITOR02_GlitchData, + OutSignalName => "DFETAP4MONITOR0(2)", + OutTemp => DFETAP4MONITOR0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP4MONITOR0(3), + GlitchData => DFETAP4MONITOR03_GlitchData, + OutSignalName => "DFETAP4MONITOR0(3)", + OutTemp => DFETAP4MONITOR0_OUT(3), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR1(0), + GlitchData => DFECLKDLYADJMONITOR10_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR1(0)", + OutTemp => DFECLKDLYADJMONITOR1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR1(1), + GlitchData => DFECLKDLYADJMONITOR11_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR1(1)", + OutTemp => DFECLKDLYADJMONITOR1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR1(2), + GlitchData => DFECLKDLYADJMONITOR12_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR1(2)", + OutTemp => DFECLKDLYADJMONITOR1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR1(3), + GlitchData => DFECLKDLYADJMONITOR13_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR1(3)", + OutTemp => DFECLKDLYADJMONITOR1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR1(4), + GlitchData => DFECLKDLYADJMONITOR14_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR1(4)", + OutTemp => DFECLKDLYADJMONITOR1_OUT(4), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFECLKDLYADJMONITOR1(5), + GlitchData => DFECLKDLYADJMONITOR15_GlitchData, + OutSignalName => "DFECLKDLYADJMONITOR1(5)", + OutTemp => DFECLKDLYADJMONITOR1_OUT(5), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR1(0), + GlitchData => DFEEYEDACMONITOR10_GlitchData, + OutSignalName => "DFEEYEDACMONITOR1(0)", + OutTemp => DFEEYEDACMONITOR1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR1(1), + GlitchData => DFEEYEDACMONITOR11_GlitchData, + OutSignalName => "DFEEYEDACMONITOR1(1)", + OutTemp => DFEEYEDACMONITOR1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR1(2), + GlitchData => DFEEYEDACMONITOR12_GlitchData, + OutSignalName => "DFEEYEDACMONITOR1(2)", + OutTemp => DFEEYEDACMONITOR1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR1(3), + GlitchData => DFEEYEDACMONITOR13_GlitchData, + OutSignalName => "DFEEYEDACMONITOR1(3)", + OutTemp => DFEEYEDACMONITOR1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFEEYEDACMONITOR1(4), + GlitchData => DFEEYEDACMONITOR14_GlitchData, + OutSignalName => "DFEEYEDACMONITOR1(4)", + OutTemp => DFEEYEDACMONITOR1_OUT(4), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR1(0), + GlitchData => DFETAP1MONITOR10_GlitchData, + OutSignalName => "DFETAP1MONITOR1(0)", + OutTemp => DFETAP1MONITOR1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR1(1), + GlitchData => DFETAP1MONITOR11_GlitchData, + OutSignalName => "DFETAP1MONITOR1(1)", + OutTemp => DFETAP1MONITOR1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR1(2), + GlitchData => DFETAP1MONITOR12_GlitchData, + OutSignalName => "DFETAP1MONITOR1(2)", + OutTemp => DFETAP1MONITOR1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR1(3), + GlitchData => DFETAP1MONITOR13_GlitchData, + OutSignalName => "DFETAP1MONITOR1(3)", + OutTemp => DFETAP1MONITOR1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP1MONITOR1(4), + GlitchData => DFETAP1MONITOR14_GlitchData, + OutSignalName => "DFETAP1MONITOR1(4)", + OutTemp => DFETAP1MONITOR1_OUT(4), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR1(0), + GlitchData => DFETAP2MONITOR10_GlitchData, + OutSignalName => "DFETAP2MONITOR1(0)", + OutTemp => DFETAP2MONITOR1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR1(1), + GlitchData => DFETAP2MONITOR11_GlitchData, + OutSignalName => "DFETAP2MONITOR1(1)", + OutTemp => DFETAP2MONITOR1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR1(2), + GlitchData => DFETAP2MONITOR12_GlitchData, + OutSignalName => "DFETAP2MONITOR1(2)", + OutTemp => DFETAP2MONITOR1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR1(3), + GlitchData => DFETAP2MONITOR13_GlitchData, + OutSignalName => "DFETAP2MONITOR1(3)", + OutTemp => DFETAP2MONITOR1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP2MONITOR1(4), + GlitchData => DFETAP2MONITOR14_GlitchData, + OutSignalName => "DFETAP2MONITOR1(4)", + OutTemp => DFETAP2MONITOR1_OUT(4), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP3MONITOR1(0), + GlitchData => DFETAP3MONITOR10_GlitchData, + OutSignalName => "DFETAP3MONITOR1(0)", + OutTemp => DFETAP3MONITOR1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP3MONITOR1(1), + GlitchData => DFETAP3MONITOR11_GlitchData, + OutSignalName => "DFETAP3MONITOR1(1)", + OutTemp => DFETAP3MONITOR1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP3MONITOR1(2), + GlitchData => DFETAP3MONITOR12_GlitchData, + OutSignalName => "DFETAP3MONITOR1(2)", + OutTemp => DFETAP3MONITOR1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP3MONITOR1(3), + GlitchData => DFETAP3MONITOR13_GlitchData, + OutSignalName => "DFETAP3MONITOR1(3)", + OutTemp => DFETAP3MONITOR1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP4MONITOR1(0), + GlitchData => DFETAP4MONITOR10_GlitchData, + OutSignalName => "DFETAP4MONITOR1(0)", + OutTemp => DFETAP4MONITOR1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP4MONITOR1(1), + GlitchData => DFETAP4MONITOR11_GlitchData, + OutSignalName => "DFETAP4MONITOR1(1)", + OutTemp => DFETAP4MONITOR1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP4MONITOR1(2), + GlitchData => DFETAP4MONITOR12_GlitchData, + OutSignalName => "DFETAP4MONITOR1(2)", + OutTemp => DFETAP4MONITOR1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFETAP4MONITOR1(3), + GlitchData => DFETAP4MONITOR13_GlitchData, + OutSignalName => "DFETAP4MONITOR1(3)", + OutTemp => DFETAP4MONITOR1_OUT(3), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFESENSCAL0(0), + GlitchData => DFESENSCAL00_GlitchData, + OutSignalName => "DFESENSCAL0(0)", + OutTemp => DFESENSCAL0_OUT(0), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFESENSCAL0(1), + GlitchData => DFESENSCAL01_GlitchData, + OutSignalName => "DFESENSCAL0(1)", + OutTemp => DFESENSCAL0_OUT(1), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFESENSCAL0(2), + GlitchData => DFESENSCAL02_GlitchData, + OutSignalName => "DFESENSCAL0(2)", + OutTemp => DFESENSCAL0_OUT(2), + Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFESENSCAL1(0), + GlitchData => DFESENSCAL10_GlitchData, + OutSignalName => "DFESENSCAL1(0)", + OutTemp => DFESENSCAL1_OUT(0), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFESENSCAL1(1), + GlitchData => DFESENSCAL11_GlitchData, + OutSignalName => "DFESENSCAL1(1)", + OutTemp => DFESENSCAL1_OUT(1), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DFESENSCAL1(2), + GlitchData => DFESENSCAL12_GlitchData, + OutSignalName => "DFESENSCAL1(2)", + OutTemp => DFESENSCAL1_OUT(2), + Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + + wait on + DFECLKDLYADJMONITOR0_out, + DFECLKDLYADJMONITOR1_out, + DFEEYEDACMONITOR0_out, + DFEEYEDACMONITOR1_out, + DFESENSCAL0_out, + DFESENSCAL1_out, + DFETAP1MONITOR0_out, + DFETAP1MONITOR1_out, + DFETAP2MONITOR0_out, + DFETAP2MONITOR1_out, + DFETAP3MONITOR0_out, + DFETAP3MONITOR1_out, + DFETAP4MONITOR0_out, + DFETAP4MONITOR1_out, + DO_out, + DRDY_out, + REFCLKOUT_out, + RXBUFSTATUS0_out, + RXBUFSTATUS1_out, + RXBYTEISALIGNED0_out, + RXBYTEISALIGNED1_out, + RXBYTEREALIGN0_out, + RXBYTEREALIGN1_out, + RXCHANBONDSEQ0_out, + RXCHANBONDSEQ1_out, + RXCHANISALIGNED0_out, + RXCHANISALIGNED1_out, + RXCHANREALIGN0_out, + RXCHANREALIGN1_out, + RXCHARISCOMMA0_out, + RXCHARISCOMMA1_out, + RXCHARISK0_out, + RXCHARISK1_out, + RXCHBONDO0_out, + RXCHBONDO1_out, + RXCLKCORCNT0_out, + RXCLKCORCNT1_out, + RXCOMMADET0_out, + RXCOMMADET1_out, + RXDATA0_out, + RXDATA1_out, + RXDATAVALID0_out, + RXDATAVALID1_out, + RXDISPERR0_out, + RXDISPERR1_out, + RXHEADER0_out, + RXHEADER1_out, + RXHEADERVALID0_out, + RXHEADERVALID1_out, + RXLOSSOFSYNC0_out, + RXLOSSOFSYNC1_out, + RXNOTINTABLE0_out, + RXNOTINTABLE1_out, + RXOVERSAMPLEERR0_out, + RXOVERSAMPLEERR1_out, + RXPRBSERR0_out, + RXPRBSERR1_out, + RXRUNDISP0_out, + RXRUNDISP1_out, + RXSTARTOFSEQ0_out, + RXSTARTOFSEQ1_out, + RXSTATUS0_out, + RXSTATUS1_out, + RXVALID0_out, + RXVALID1_out, + TXBUFSTATUS0_out, + TXBUFSTATUS1_out, + TXGEARBOXREADY0_out, + TXGEARBOXREADY1_out, + TXKERR0_out, + TXKERR1_out, + TXRUNDISP0_out, + TXRUNDISP1_out, + + CLKIN_ipd, + DADDR_ipd, + DCLK_ipd, + DEN_ipd, + DFECLKDLYADJ0_ipd, + DFECLKDLYADJ1_ipd, + DFETAP10_ipd, + DFETAP11_ipd, + DFETAP20_ipd, + DFETAP21_ipd, + DFETAP30_ipd, + DFETAP31_ipd, + DFETAP40_ipd, + DFETAP41_ipd, + DI_ipd, + DWE_ipd, + GTXRESET_ipd, + GTXTEST_ipd, + INTDATAWIDTH_ipd, + LOOPBACK0_ipd, + LOOPBACK1_ipd, + PLLLKDETEN_ipd, + PLLPOWERDOWN_ipd, + PRBSCNTRESET0_ipd, + PRBSCNTRESET1_ipd, + REFCLKPWRDNB_ipd, + RXBUFRESET0_ipd, + RXBUFRESET1_ipd, + RXCDRRESET0_ipd, + RXCDRRESET1_ipd, + RXCHBONDI0_ipd, + RXCHBONDI1_ipd, + RXCOMMADETUSE0_ipd, + RXCOMMADETUSE1_ipd, + RXDATAWIDTH0_ipd, + RXDATAWIDTH1_ipd, + RXDEC8B10BUSE0_ipd, + RXDEC8B10BUSE1_ipd, + RXENCHANSYNC0_ipd, + RXENCHANSYNC1_ipd, + RXENEQB0_ipd, + RXENEQB1_ipd, + RXENMCOMMAALIGN0_ipd, + RXENMCOMMAALIGN1_ipd, + RXENPCOMMAALIGN0_ipd, + RXENPCOMMAALIGN1_ipd, + RXENPMAPHASEALIGN0_ipd, + RXENPMAPHASEALIGN1_ipd, + RXENPRBSTST0_ipd, + RXENPRBSTST1_ipd, + RXENSAMPLEALIGN0_ipd, + RXENSAMPLEALIGN1_ipd, + RXEQMIX0_ipd, + RXEQMIX1_ipd, + RXEQPOLE0_ipd, + RXEQPOLE1_ipd, + RXGEARBOXSLIP0_ipd, + RXGEARBOXSLIP1_ipd, + RXN0_ipd, + RXN1_ipd, + RXP0_ipd, + RXP1_ipd, + RXPMASETPHASE0_ipd, + RXPMASETPHASE1_ipd, + RXPOLARITY0_ipd, + RXPOLARITY1_ipd, + RXPOWERDOWN0_ipd, + RXPOWERDOWN1_ipd, + RXRESET0_ipd, + RXRESET1_ipd, + RXSLIDE0_ipd, + RXSLIDE1_ipd, + RXUSRCLK0_ipd, + RXUSRCLK1_ipd, + RXUSRCLK20_ipd, + RXUSRCLK21_ipd, + TXBUFDIFFCTRL0_ipd, + TXBUFDIFFCTRL1_ipd, + TXBYPASS8B10B0_ipd, + TXBYPASS8B10B1_ipd, + TXCHARDISPMODE0_ipd, + TXCHARDISPMODE1_ipd, + TXCHARDISPVAL0_ipd, + TXCHARDISPVAL1_ipd, + TXCHARISK0_ipd, + TXCHARISK1_ipd, + TXCOMSTART0_ipd, + TXCOMSTART1_ipd, + TXCOMTYPE0_ipd, + TXCOMTYPE1_ipd, + TXDATA0_ipd, + TXDATA1_ipd, + TXDATAWIDTH0_ipd, + TXDATAWIDTH1_ipd, + TXDETECTRX0_ipd, + TXDETECTRX1_ipd, + TXDIFFCTRL0_ipd, + TXDIFFCTRL1_ipd, + TXELECIDLE0_ipd, + TXELECIDLE1_ipd, + TXENC8B10BUSE0_ipd, + TXENC8B10BUSE1_ipd, + TXENPMAPHASEALIGN0_ipd, + TXENPMAPHASEALIGN1_ipd, + TXENPRBSTST0_ipd, + TXENPRBSTST1_ipd, + TXHEADER0_ipd, + TXHEADER1_ipd, + TXINHIBIT0_ipd, + TXINHIBIT1_ipd, + TXPMASETPHASE0_ipd, + TXPMASETPHASE1_ipd, + TXPOLARITY0_ipd, + TXPOLARITY1_ipd, + TXPOWERDOWN0_ipd, + TXPOWERDOWN1_ipd, + TXPREEMPHASIS0_ipd, + TXPREEMPHASIS1_ipd, + TXRESET0_ipd, + TXRESET1_ipd, + TXSEQUENCE0_ipd, + TXSEQUENCE1_ipd, + TXSTARTSEQ0_ipd, + TXSTARTSEQ1_ipd, + TXUSRCLK0_ipd, + TXUSRCLK1_ipd, + TXUSRCLK20_ipd, + TXUSRCLK21_ipd; + + end process TIMING; + + PLLLKDET <= PLLLKDET_out; + RESETDONE0 <= RESETDONE0_out; + RESETDONE1 <= RESETDONE1_out; + RXELECIDLE0 <= RXELECIDLE0_out; + RXELECIDLE1 <= RXELECIDLE1_out; + RXRECCLK0 <= RXRECCLK0_out; + RXRECCLK1 <= RXRECCLK1_out; + TXN0 <= TXN0_out; + TXN1 <= TXN1_out; + TXOUTCLK0 <= TXOUTCLK0_out; + TXOUTCLK1 <= TXOUTCLK1_out; + TXP0 <= TXP0_out; + TXP1 <= TXP1_out; + +end GTX_DUAL_V; +-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex5fxt/SMODEL/Attic/jtagppc440.vhd,v 1.1 2006/09/18 21:16:09 sranade Exp $ +------------------------------------------------------------------------------- +-- Copyright (c) 1995/2004 Xilinx, Inc. +-- All Right Reserved. +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : Xilinx Functional Simulation Library Component +-- / / JTAG Primitive for Virtex5 Power PC +-- /___/ /\ Filename : JTAGPPC440.vhd +-- \ \ / \ Timestamp : hu Aug 18 13:47:04 PDT 2005 +-- \___\/\___\ +-- +-- Revision: +-- 08/19/05 - Initial version. + +----- CELL JTAGPPC440 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity JTAGPPC440 is + port ( + TCK : out std_ulogic; + TDIPPC : out std_ulogic; + TMS : out std_ulogic; + + TDOPPC : in std_ulogic + ); +end JTAGPPC440; + +architecture JTAGPPC440_v of JTAGPPC440 is + begin + TCK <= '1'; + TDIPPC <= '1'; + TMS <= '1'; +end JTAGPPC440_v; +------------------------------------------------------- +-- Copyright (c) 1995/2006 Xilinx Inc. +-- All Right Reserved. +------------------------------------------------------- +-- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 10.1i +-- \ \ Description : +-- / / +-- /___/ /\ Filename : PPC440.vhd +-- \ \ / \ Timestamp : Thu Apr 19 15:56:12 2007 + +-- \__ \/\__ \ +-- +-- Generated by : write_vhdl +-- Revision: +------------------------------------------------------- + +----- CELL PPC440 ----- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library IEEE; +use IEEE.VITAL_Timing.all; + +library unisim; +use unisim.VCOMPONENTS.all; + +entity PPC440 is +generic ( + APU_CONTROL : bit_vector := X"02000"; + APU_UDI0 : bit_vector := X"000000"; + APU_UDI1 : bit_vector := X"000000"; + APU_UDI10 : bit_vector := X"000000"; + APU_UDI11 : bit_vector := X"000000"; + APU_UDI12 : bit_vector := X"000000"; + APU_UDI13 : bit_vector := X"000000"; + APU_UDI14 : bit_vector := X"000000"; + APU_UDI15 : bit_vector := X"000000"; + APU_UDI2 : bit_vector := X"000000"; + APU_UDI3 : bit_vector := X"000000"; + APU_UDI4 : bit_vector := X"000000"; + APU_UDI5 : bit_vector := X"000000"; + APU_UDI6 : bit_vector := X"000000"; + APU_UDI7 : bit_vector := X"000000"; + APU_UDI8 : bit_vector := X"000000"; + APU_UDI9 : bit_vector := X"000000"; + CLOCK_DELAY : boolean := FALSE; + DCR_AUTOLOCK_ENABLE : boolean := TRUE; + DMA0_CONTROL : bit_vector := X"00"; + DMA0_RXCHANNELCTRL : bit_vector := X"01010000"; + DMA0_RXIRQTIMER : bit_vector := X"3FF"; + DMA0_TXCHANNELCTRL : bit_vector := X"01010000"; + DMA0_TXIRQTIMER : bit_vector := X"3FF"; + DMA1_CONTROL : bit_vector := X"00"; + DMA1_RXCHANNELCTRL : bit_vector := X"01010000"; + DMA1_RXIRQTIMER : bit_vector := X"3FF"; + DMA1_TXCHANNELCTRL : bit_vector := X"01010000"; + DMA1_TXIRQTIMER : bit_vector := X"3FF"; + DMA2_CONTROL : bit_vector := X"00"; + DMA2_RXCHANNELCTRL : bit_vector := X"01010000"; + DMA2_RXIRQTIMER : bit_vector := X"3FF"; + DMA2_TXCHANNELCTRL : bit_vector := X"01010000"; + DMA2_TXIRQTIMER : bit_vector := X"3FF"; + DMA3_CONTROL : bit_vector := X"00"; + DMA3_RXCHANNELCTRL : bit_vector := X"01010000"; + DMA3_RXIRQTIMER : bit_vector := X"3FF"; + DMA3_TXCHANNELCTRL : bit_vector := X"01010000"; + DMA3_TXIRQTIMER : bit_vector := X"3FF"; + INTERCONNECT_IMASK : bit_vector := X"FFFFFFFF"; + INTERCONNECT_TMPL_SEL : bit_vector := X"3FFFFFFF"; + MI_ARBCONFIG : bit_vector := X"00432010"; + MI_BANKCONFLICT_MASK : bit_vector := X"00000000"; + MI_CONTROL : bit_vector := X"0000008F"; + MI_ROWCONFLICT_MASK : bit_vector := X"00000000"; + PPCDM_ASYNCMODE : boolean := FALSE; + PPCDS_ASYNCMODE : boolean := FALSE; + PPCM_ARBCONFIG : bit_vector := X"00432010"; + PPCM_CONTROL : bit_vector := X"8000009F"; + PPCM_COUNTER : bit_vector := X"00000500"; + PPCS0_ADDRMAP_TMPL0 : bit_vector := X"FFFFFFFF"; + PPCS0_ADDRMAP_TMPL1 : bit_vector := X"FFFFFFFF"; + PPCS0_ADDRMAP_TMPL2 : bit_vector := X"FFFFFFFF"; + PPCS0_ADDRMAP_TMPL3 : bit_vector := X"FFFFFFFF"; + PPCS0_CONTROL : bit_vector := X"8033336C"; + PPCS0_WIDTH_128N64 : boolean := TRUE; + PPCS1_ADDRMAP_TMPL0 : bit_vector := X"FFFFFFFF"; + PPCS1_ADDRMAP_TMPL1 : bit_vector := X"FFFFFFFF"; + PPCS1_ADDRMAP_TMPL2 : bit_vector := X"FFFFFFFF"; + PPCS1_ADDRMAP_TMPL3 : bit_vector := X"FFFFFFFF"; + PPCS1_CONTROL : bit_vector := X"8033336C"; + PPCS1_WIDTH_128N64 : boolean := TRUE; + XBAR_ADDRMAP_TMPL0 : bit_vector := X"FFFF0000"; + XBAR_ADDRMAP_TMPL1 : bit_vector := X"00000000"; + XBAR_ADDRMAP_TMPL2 : bit_vector := X"00000000"; + XBAR_ADDRMAP_TMPL3 : bit_vector := X"00000000" + + + + + ); + +port ( + APUFCMDECFPUOP : out std_ulogic; + APUFCMDECLDSTXFERSIZE : out std_logic_vector(0 to 2); + APUFCMDECLOAD : out std_ulogic; + APUFCMDECNONAUTON : out std_ulogic; + APUFCMDECSTORE : out std_ulogic; + APUFCMDECUDI : out std_logic_vector(0 to 3); + APUFCMDECUDIVALID : out std_ulogic; + APUFCMENDIAN : out std_ulogic; + APUFCMFLUSH : out std_ulogic; + APUFCMINSTRUCTION : out std_logic_vector(0 to 31); + APUFCMINSTRVALID : out std_ulogic; + APUFCMLOADBYTEADDR : out std_logic_vector(0 to 3); + APUFCMLOADDATA : out std_logic_vector(0 to 127); + APUFCMLOADDVALID : out std_ulogic; + APUFCMMSRFE0 : out std_ulogic; + APUFCMMSRFE1 : out std_ulogic; + APUFCMNEXTINSTRREADY : out std_ulogic; + APUFCMOPERANDVALID : out std_ulogic; + APUFCMRADATA : out std_logic_vector(0 to 31); + APUFCMRBDATA : out std_logic_vector(0 to 31); + APUFCMWRITEBACKOK : out std_ulogic; + C440CPMCORESLEEPREQ : out std_ulogic; + C440CPMDECIRPTREQ : out std_ulogic; + C440CPMFITIRPTREQ : out std_ulogic; + C440CPMMSRCE : out std_ulogic; + C440CPMMSREE : out std_ulogic; + C440CPMTIMERRESETREQ : out std_ulogic; + C440CPMWDIRPTREQ : out std_ulogic; + C440DBGSYSTEMCONTROL : out std_logic_vector(0 to 7); + C440JTGTDO : out std_ulogic; + C440JTGTDOEN : out std_ulogic; + C440MACHINECHECK : out std_ulogic; + C440RSTCHIPRESETREQ : out std_ulogic; + C440RSTCORERESETREQ : out std_ulogic; + C440RSTSYSTEMRESETREQ : out std_ulogic; + C440TRCBRANCHSTATUS : out std_logic_vector(0 to 2); + C440TRCCYCLE : out std_ulogic; + C440TRCEXECUTIONSTATUS : out std_logic_vector(0 to 4); + C440TRCTRACESTATUS : out std_logic_vector(0 to 6); + C440TRCTRIGGEREVENTOUT : out std_ulogic; + C440TRCTRIGGEREVENTTYPE : out std_logic_vector(0 to 13); + DMA0LLRSTENGINEACK : out std_ulogic; + DMA0LLRXDSTRDYN : out std_ulogic; + DMA0LLTXD : out std_logic_vector(0 to 31); + DMA0LLTXEOFN : out std_ulogic; + DMA0LLTXEOPN : out std_ulogic; + DMA0LLTXREM : out std_logic_vector(0 to 3); + DMA0LLTXSOFN : out std_ulogic; + DMA0LLTXSOPN : out std_ulogic; + DMA0LLTXSRCRDYN : out std_ulogic; + DMA0RXIRQ : out std_ulogic; + DMA0TXIRQ : out std_ulogic; + DMA1LLRSTENGINEACK : out std_ulogic; + DMA1LLRXDSTRDYN : out std_ulogic; + DMA1LLTXD : out std_logic_vector(0 to 31); + DMA1LLTXEOFN : out std_ulogic; + DMA1LLTXEOPN : out std_ulogic; + DMA1LLTXREM : out std_logic_vector(0 to 3); + DMA1LLTXSOFN : out std_ulogic; + DMA1LLTXSOPN : out std_ulogic; + DMA1LLTXSRCRDYN : out std_ulogic; + DMA1RXIRQ : out std_ulogic; + DMA1TXIRQ : out std_ulogic; + DMA2LLRSTENGINEACK : out std_ulogic; + DMA2LLRXDSTRDYN : out std_ulogic; + DMA2LLTXD : out std_logic_vector(0 to 31); + DMA2LLTXEOFN : out std_ulogic; + DMA2LLTXEOPN : out std_ulogic; + DMA2LLTXREM : out std_logic_vector(0 to 3); + DMA2LLTXSOFN : out std_ulogic; + DMA2LLTXSOPN : out std_ulogic; + DMA2LLTXSRCRDYN : out std_ulogic; + DMA2RXIRQ : out std_ulogic; + DMA2TXIRQ : out std_ulogic; + DMA3LLRSTENGINEACK : out std_ulogic; + DMA3LLRXDSTRDYN : out std_ulogic; + DMA3LLTXD : out std_logic_vector(0 to 31); + DMA3LLTXEOFN : out std_ulogic; + DMA3LLTXEOPN : out std_ulogic; + DMA3LLTXREM : out std_logic_vector(0 to 3); + DMA3LLTXSOFN : out std_ulogic; + DMA3LLTXSOPN : out std_ulogic; + DMA3LLTXSRCRDYN : out std_ulogic; + DMA3RXIRQ : out std_ulogic; + DMA3TXIRQ : out std_ulogic; + MIMCADDRESS : out std_logic_vector(0 to 35); + MIMCADDRESSVALID : out std_ulogic; + MIMCBANKCONFLICT : out std_ulogic; + MIMCBYTEENABLE : out std_logic_vector(0 to 15); + MIMCREADNOTWRITE : out std_ulogic; + MIMCROWCONFLICT : out std_ulogic; + MIMCWRITEDATA : out std_logic_vector(0 to 127); + MIMCWRITEDATAVALID : out std_ulogic; + PPCCPMINTERCONNECTBUSY : out std_ulogic; + PPCDMDCRABUS : out std_logic_vector(0 to 9); + PPCDMDCRDBUSOUT : out std_logic_vector(0 to 31); + PPCDMDCRREAD : out std_ulogic; + PPCDMDCRUABUS : out std_logic_vector(20 to 21); + PPCDMDCRWRITE : out std_ulogic; + PPCDSDCRACK : out std_ulogic; + PPCDSDCRDBUSIN : out std_logic_vector(0 to 31); + PPCDSDCRTIMEOUTWAIT : out std_ulogic; + PPCEICINTERCONNECTIRQ : out std_ulogic; + PPCMPLBABORT : out std_ulogic; + PPCMPLBABUS : out std_logic_vector(0 to 31); + PPCMPLBBE : out std_logic_vector(0 to 15); + PPCMPLBBUSLOCK : out std_ulogic; + PPCMPLBLOCKERR : out std_ulogic; + PPCMPLBPRIORITY : out std_logic_vector(0 to 1); + PPCMPLBRDBURST : out std_ulogic; + PPCMPLBREQUEST : out std_ulogic; + PPCMPLBRNW : out std_ulogic; + PPCMPLBSIZE : out std_logic_vector(0 to 3); + PPCMPLBTATTRIBUTE : out std_logic_vector(0 to 15); + PPCMPLBTYPE : out std_logic_vector(0 to 2); + PPCMPLBUABUS : out std_logic_vector(28 to 31); + PPCMPLBWRBURST : out std_ulogic; + PPCMPLBWRDBUS : out std_logic_vector(0 to 127); + PPCS0PLBADDRACK : out std_ulogic; + PPCS0PLBMBUSY : out std_logic_vector(0 to 3); + PPCS0PLBMIRQ : out std_logic_vector(0 to 3); + PPCS0PLBMRDERR : out std_logic_vector(0 to 3); + PPCS0PLBMWRERR : out std_logic_vector(0 to 3); + PPCS0PLBRDBTERM : out std_ulogic; + PPCS0PLBRDCOMP : out std_ulogic; + PPCS0PLBRDDACK : out std_ulogic; + PPCS0PLBRDDBUS : out std_logic_vector(0 to 127); + PPCS0PLBRDWDADDR : out std_logic_vector(0 to 3); + PPCS0PLBREARBITRATE : out std_ulogic; + PPCS0PLBSSIZE : out std_logic_vector(0 to 1); + PPCS0PLBWAIT : out std_ulogic; + PPCS0PLBWRBTERM : out std_ulogic; + PPCS0PLBWRCOMP : out std_ulogic; + PPCS0PLBWRDACK : out std_ulogic; + PPCS1PLBADDRACK : out std_ulogic; + PPCS1PLBMBUSY : out std_logic_vector(0 to 3); + PPCS1PLBMIRQ : out std_logic_vector(0 to 3); + PPCS1PLBMRDERR : out std_logic_vector(0 to 3); + PPCS1PLBMWRERR : out std_logic_vector(0 to 3); + PPCS1PLBRDBTERM : out std_ulogic; + PPCS1PLBRDCOMP : out std_ulogic; + PPCS1PLBRDDACK : out std_ulogic; + PPCS1PLBRDDBUS : out std_logic_vector(0 to 127); + PPCS1PLBRDWDADDR : out std_logic_vector(0 to 3); + PPCS1PLBREARBITRATE : out std_ulogic; + PPCS1PLBSSIZE : out std_logic_vector(0 to 1); + PPCS1PLBWAIT : out std_ulogic; + PPCS1PLBWRBTERM : out std_ulogic; + PPCS1PLBWRCOMP : out std_ulogic; + PPCS1PLBWRDACK : out std_ulogic; + + CPMC440CLK : in std_ulogic; + CPMC440CLKEN : in std_ulogic; + CPMC440CORECLOCKINACTIVE : in std_ulogic; + CPMC440TIMERCLOCK : in std_ulogic; + CPMDCRCLK : in std_ulogic; + CPMDMA0LLCLK : in std_ulogic; + CPMDMA1LLCLK : in std_ulogic; + CPMDMA2LLCLK : in std_ulogic; + CPMDMA3LLCLK : in std_ulogic; + CPMFCMCLK : in std_ulogic; + CPMINTERCONNECTCLK : in std_ulogic; + CPMINTERCONNECTCLKEN : in std_ulogic; + CPMINTERCONNECTCLKNTO1 : in std_ulogic; + CPMMCCLK : in std_ulogic; + CPMPPCMPLBCLK : in std_ulogic; + CPMPPCS0PLBCLK : in std_ulogic; + CPMPPCS1PLBCLK : in std_ulogic; + DBGC440DEBUGHALT : in std_ulogic; + DBGC440SYSTEMSTATUS : in std_logic_vector(0 to 4); + DBGC440UNCONDDEBUGEVENT : in std_ulogic; + DCRPPCDMACK : in std_ulogic; + DCRPPCDMDBUSIN : in std_logic_vector(0 to 31); + DCRPPCDMTIMEOUTWAIT : in std_ulogic; + DCRPPCDSABUS : in std_logic_vector(0 to 9); + DCRPPCDSDBUSOUT : in std_logic_vector(0 to 31); + DCRPPCDSREAD : in std_ulogic; + DCRPPCDSWRITE : in std_ulogic; + EICC440CRITIRQ : in std_ulogic; + EICC440EXTIRQ : in std_ulogic; + FCMAPUCONFIRMINSTR : in std_ulogic; + FCMAPUCR : in std_logic_vector(0 to 3); + FCMAPUDONE : in std_ulogic; + FCMAPUEXCEPTION : in std_ulogic; + FCMAPUFPSCRFEX : in std_ulogic; + FCMAPURESULT : in std_logic_vector(0 to 31); + FCMAPURESULTVALID : in std_ulogic; + FCMAPUSLEEPNOTREADY : in std_ulogic; + FCMAPUSTOREDATA : in std_logic_vector(0 to 127); + JTGC440TCK : in std_ulogic; + JTGC440TDI : in std_ulogic; + JTGC440TMS : in std_ulogic; + JTGC440TRSTNEG : in std_ulogic; + LLDMA0RSTENGINEREQ : in std_ulogic; + LLDMA0RXD : in std_logic_vector(0 to 31); + LLDMA0RXEOFN : in std_ulogic; + LLDMA0RXEOPN : in std_ulogic; + LLDMA0RXREM : in std_logic_vector(0 to 3); + LLDMA0RXSOFN : in std_ulogic; + LLDMA0RXSOPN : in std_ulogic; + LLDMA0RXSRCRDYN : in std_ulogic; + LLDMA0TXDSTRDYN : in std_ulogic; + LLDMA1RSTENGINEREQ : in std_ulogic; + LLDMA1RXD : in std_logic_vector(0 to 31); + LLDMA1RXEOFN : in std_ulogic; + LLDMA1RXEOPN : in std_ulogic; + LLDMA1RXREM : in std_logic_vector(0 to 3); + LLDMA1RXSOFN : in std_ulogic; + LLDMA1RXSOPN : in std_ulogic; + LLDMA1RXSRCRDYN : in std_ulogic; + LLDMA1TXDSTRDYN : in std_ulogic; + LLDMA2RSTENGINEREQ : in std_ulogic; + LLDMA2RXD : in std_logic_vector(0 to 31); + LLDMA2RXEOFN : in std_ulogic; + LLDMA2RXEOPN : in std_ulogic; + LLDMA2RXREM : in std_logic_vector(0 to 3); + LLDMA2RXSOFN : in std_ulogic; + LLDMA2RXSOPN : in std_ulogic; + LLDMA2RXSRCRDYN : in std_ulogic; + LLDMA2TXDSTRDYN : in std_ulogic; + LLDMA3RSTENGINEREQ : in std_ulogic; + LLDMA3RXD : in std_logic_vector(0 to 31); + LLDMA3RXEOFN : in std_ulogic; + LLDMA3RXEOPN : in std_ulogic; + LLDMA3RXREM : in std_logic_vector(0 to 3); + LLDMA3RXSOFN : in std_ulogic; + LLDMA3RXSOPN : in std_ulogic; + LLDMA3RXSRCRDYN : in std_ulogic; + LLDMA3TXDSTRDYN : in std_ulogic; + MCMIADDRREADYTOACCEPT : in std_ulogic; + MCMIREADDATA : in std_logic_vector(0 to 127); + MCMIREADDATAERR : in std_ulogic; + MCMIREADDATAVALID : in std_ulogic; + PLBPPCMADDRACK : in std_ulogic; + PLBPPCMMBUSY : in std_ulogic; + PLBPPCMMIRQ : in std_ulogic; + PLBPPCMMRDERR : in std_ulogic; + PLBPPCMMWRERR : in std_ulogic; + PLBPPCMRDBTERM : in std_ulogic; + PLBPPCMRDDACK : in std_ulogic; + PLBPPCMRDDBUS : in std_logic_vector(0 to 127); + PLBPPCMRDPENDPRI : in std_logic_vector(0 to 1); + PLBPPCMRDPENDREQ : in std_ulogic; + PLBPPCMRDWDADDR : in std_logic_vector(0 to 3); + PLBPPCMREARBITRATE : in std_ulogic; + PLBPPCMREQPRI : in std_logic_vector(0 to 1); + PLBPPCMSSIZE : in std_logic_vector(0 to 1); + PLBPPCMTIMEOUT : in std_ulogic; + PLBPPCMWRBTERM : in std_ulogic; + PLBPPCMWRDACK : in std_ulogic; + PLBPPCMWRPENDPRI : in std_logic_vector(0 to 1); + PLBPPCMWRPENDREQ : in std_ulogic; + PLBPPCS0ABORT : in std_ulogic; + PLBPPCS0ABUS : in std_logic_vector(0 to 31); + PLBPPCS0BE : in std_logic_vector(0 to 15); + PLBPPCS0BUSLOCK : in std_ulogic; + PLBPPCS0LOCKERR : in std_ulogic; + PLBPPCS0MASTERID : in std_logic_vector(0 to 1); + PLBPPCS0MSIZE : in std_logic_vector(0 to 1); + PLBPPCS0PAVALID : in std_ulogic; + PLBPPCS0RDBURST : in std_ulogic; + PLBPPCS0RDPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS0RDPENDREQ : in std_ulogic; + PLBPPCS0RDPRIM : in std_ulogic; + PLBPPCS0REQPRI : in std_logic_vector(0 to 1); + PLBPPCS0RNW : in std_ulogic; + PLBPPCS0SAVALID : in std_ulogic; + PLBPPCS0SIZE : in std_logic_vector(0 to 3); + PLBPPCS0TATTRIBUTE : in std_logic_vector(0 to 15); + PLBPPCS0TYPE : in std_logic_vector(0 to 2); + PLBPPCS0UABUS : in std_logic_vector(28 to 31); + PLBPPCS0WRBURST : in std_ulogic; + PLBPPCS0WRDBUS : in std_logic_vector(0 to 127); + PLBPPCS0WRPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS0WRPENDREQ : in std_ulogic; + PLBPPCS0WRPRIM : in std_ulogic; + PLBPPCS1ABORT : in std_ulogic; + PLBPPCS1ABUS : in std_logic_vector(0 to 31); + PLBPPCS1BE : in std_logic_vector(0 to 15); + PLBPPCS1BUSLOCK : in std_ulogic; + PLBPPCS1LOCKERR : in std_ulogic; + PLBPPCS1MASTERID : in std_logic_vector(0 to 1); + PLBPPCS1MSIZE : in std_logic_vector(0 to 1); + PLBPPCS1PAVALID : in std_ulogic; + PLBPPCS1RDBURST : in std_ulogic; + PLBPPCS1RDPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS1RDPENDREQ : in std_ulogic; + PLBPPCS1RDPRIM : in std_ulogic; + PLBPPCS1REQPRI : in std_logic_vector(0 to 1); + PLBPPCS1RNW : in std_ulogic; + PLBPPCS1SAVALID : in std_ulogic; + PLBPPCS1SIZE : in std_logic_vector(0 to 3); + PLBPPCS1TATTRIBUTE : in std_logic_vector(0 to 15); + PLBPPCS1TYPE : in std_logic_vector(0 to 2); + PLBPPCS1UABUS : in std_logic_vector(28 to 31); + PLBPPCS1WRBURST : in std_ulogic; + PLBPPCS1WRDBUS : in std_logic_vector(0 to 127); + PLBPPCS1WRPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS1WRPENDREQ : in std_ulogic; + PLBPPCS1WRPRIM : in std_ulogic; + RSTC440RESETCHIP : in std_ulogic; + RSTC440RESETCORE : in std_ulogic; + RSTC440RESETSYSTEM : in std_ulogic; + TIEC440DCURDLDCACHEPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCURDNONCACHEPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCURDTOUCHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCURDURGENTPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCUWRFLUSHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCUWRSTOREPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCUWRURGENTPLBPRIO : in std_logic_vector(0 to 1); + TIEC440ENDIANRESET : in std_ulogic; + TIEC440ERPNRESET : in std_logic_vector(0 to 3); + TIEC440ICURDFETCHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440ICURDSPECPLBPRIO : in std_logic_vector(0 to 1); + TIEC440ICURDTOUCHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440PIR : in std_logic_vector(28 to 31); + TIEC440PVR : in std_logic_vector(28 to 31); + TIEC440USERRESET : in std_logic_vector(0 to 3); + TIEDCRBASEADDR : in std_logic_vector(0 to 1); + TRCC440TRACEDISABLE : in std_ulogic; + TRCC440TRIGGEREVENTIN : in std_ulogic + ); +end PPC440; + +architecture PPC440_V of PPC440 is + + component PPC440_SWIFT_BUS + port ( + APUFCMDECFPUOP : out std_ulogic; + APUFCMDECLDSTXFERSIZE : out std_logic_vector(0 to 2); + APUFCMDECLOAD : out std_ulogic; + APUFCMDECNONAUTON : out std_ulogic; + APUFCMDECSTORE : out std_ulogic; + APUFCMDECUDI : out std_logic_vector(0 to 3); + APUFCMDECUDIVALID : out std_ulogic; + APUFCMENDIAN : out std_ulogic; + APUFCMFLUSH : out std_ulogic; + APUFCMINSTRUCTION : out std_logic_vector(0 to 31); + APUFCMINSTRVALID : out std_ulogic; + APUFCMLOADBYTEADDR : out std_logic_vector(0 to 3); + APUFCMLOADDATA : out std_logic_vector(0 to 127); + APUFCMLOADDVALID : out std_ulogic; + APUFCMMSRFE0 : out std_ulogic; + APUFCMMSRFE1 : out std_ulogic; + APUFCMNEXTINSTRREADY : out std_ulogic; + APUFCMOPERANDVALID : out std_ulogic; + APUFCMRADATA : out std_logic_vector(0 to 31); + APUFCMRBDATA : out std_logic_vector(0 to 31); + APUFCMWRITEBACKOK : out std_ulogic; + C440CPMCORESLEEPREQ : out std_ulogic; + C440CPMDECIRPTREQ : out std_ulogic; + C440CPMFITIRPTREQ : out std_ulogic; + C440CPMMSRCE : out std_ulogic; + C440CPMMSREE : out std_ulogic; + C440CPMTIMERRESETREQ : out std_ulogic; + C440CPMWDIRPTREQ : out std_ulogic; + C440DBGSYSTEMCONTROL : out std_logic_vector(0 to 7); + C440JTGTDO : out std_ulogic; + C440JTGTDOEN : out std_ulogic; + C440MACHINECHECK : out std_ulogic; + C440RSTCHIPRESETREQ : out std_ulogic; + C440RSTCORERESETREQ : out std_ulogic; + C440RSTSYSTEMRESETREQ : out std_ulogic; + C440TRCBRANCHSTATUS : out std_logic_vector(0 to 2); + C440TRCCYCLE : out std_ulogic; + C440TRCEXECUTIONSTATUS : out std_logic_vector(0 to 4); + C440TRCTRACESTATUS : out std_logic_vector(0 to 6); + C440TRCTRIGGEREVENTOUT : out std_ulogic; + C440TRCTRIGGEREVENTTYPE : out std_logic_vector(0 to 13); + DMA0LLRSTENGINEACK : out std_ulogic; + DMA0LLRXDSTRDYN : out std_ulogic; + DMA0LLTXD : out std_logic_vector(0 to 31); + DMA0LLTXEOFN : out std_ulogic; + DMA0LLTXEOPN : out std_ulogic; + DMA0LLTXREM : out std_logic_vector(0 to 3); + DMA0LLTXSOFN : out std_ulogic; + DMA0LLTXSOPN : out std_ulogic; + DMA0LLTXSRCRDYN : out std_ulogic; + DMA0RXIRQ : out std_ulogic; + DMA0TXIRQ : out std_ulogic; + DMA1LLRSTENGINEACK : out std_ulogic; + DMA1LLRXDSTRDYN : out std_ulogic; + DMA1LLTXD : out std_logic_vector(0 to 31); + DMA1LLTXEOFN : out std_ulogic; + DMA1LLTXEOPN : out std_ulogic; + DMA1LLTXREM : out std_logic_vector(0 to 3); + DMA1LLTXSOFN : out std_ulogic; + DMA1LLTXSOPN : out std_ulogic; + DMA1LLTXSRCRDYN : out std_ulogic; + DMA1RXIRQ : out std_ulogic; + DMA1TXIRQ : out std_ulogic; + DMA2LLRSTENGINEACK : out std_ulogic; + DMA2LLRXDSTRDYN : out std_ulogic; + DMA2LLTXD : out std_logic_vector(0 to 31); + DMA2LLTXEOFN : out std_ulogic; + DMA2LLTXEOPN : out std_ulogic; + DMA2LLTXREM : out std_logic_vector(0 to 3); + DMA2LLTXSOFN : out std_ulogic; + DMA2LLTXSOPN : out std_ulogic; + DMA2LLTXSRCRDYN : out std_ulogic; + DMA2RXIRQ : out std_ulogic; + DMA2TXIRQ : out std_ulogic; + DMA3LLRSTENGINEACK : out std_ulogic; + DMA3LLRXDSTRDYN : out std_ulogic; + DMA3LLTXD : out std_logic_vector(0 to 31); + DMA3LLTXEOFN : out std_ulogic; + DMA3LLTXEOPN : out std_ulogic; + DMA3LLTXREM : out std_logic_vector(0 to 3); + DMA3LLTXSOFN : out std_ulogic; + DMA3LLTXSOPN : out std_ulogic; + DMA3LLTXSRCRDYN : out std_ulogic; + DMA3RXIRQ : out std_ulogic; + DMA3TXIRQ : out std_ulogic; + MIMCADDRESS : out std_logic_vector(0 to 35); + MIMCADDRESSVALID : out std_ulogic; + MIMCBANKCONFLICT : out std_ulogic; + MIMCBYTEENABLE : out std_logic_vector(0 to 15); + MIMCREADNOTWRITE : out std_ulogic; + MIMCROWCONFLICT : out std_ulogic; + MIMCWRITEDATA : out std_logic_vector(0 to 127); + MIMCWRITEDATAVALID : out std_ulogic; + PPCCPMINTERCONNECTBUSY : out std_ulogic; + PPCDMDCRABUS : out std_logic_vector(0 to 9); + PPCDMDCRDBUSOUT : out std_logic_vector(0 to 31); + PPCDMDCRREAD : out std_ulogic; + PPCDMDCRUABUS : out std_logic_vector(20 to 21); + PPCDMDCRWRITE : out std_ulogic; + PPCDSDCRACK : out std_ulogic; + PPCDSDCRDBUSIN : out std_logic_vector(0 to 31); + PPCDSDCRTIMEOUTWAIT : out std_ulogic; + PPCEICINTERCONNECTIRQ : out std_ulogic; + PPCMPLBABORT : out std_ulogic; + PPCMPLBABUS : out std_logic_vector(0 to 31); + PPCMPLBBE : out std_logic_vector(0 to 15); + PPCMPLBBUSLOCK : out std_ulogic; + PPCMPLBLOCKERR : out std_ulogic; + PPCMPLBPRIORITY : out std_logic_vector(0 to 1); + PPCMPLBRDBURST : out std_ulogic; + PPCMPLBREQUEST : out std_ulogic; + PPCMPLBRNW : out std_ulogic; + PPCMPLBSIZE : out std_logic_vector(0 to 3); + PPCMPLBTATTRIBUTE : out std_logic_vector(0 to 15); + PPCMPLBTYPE : out std_logic_vector(0 to 2); + PPCMPLBUABUS : out std_logic_vector(28 to 31); + PPCMPLBWRBURST : out std_ulogic; + PPCMPLBWRDBUS : out std_logic_vector(0 to 127); + PPCS0PLBADDRACK : out std_ulogic; + PPCS0PLBMBUSY : out std_logic_vector(0 to 3); + PPCS0PLBMIRQ : out std_logic_vector(0 to 3); + PPCS0PLBMRDERR : out std_logic_vector(0 to 3); + PPCS0PLBMWRERR : out std_logic_vector(0 to 3); + PPCS0PLBRDBTERM : out std_ulogic; + PPCS0PLBRDCOMP : out std_ulogic; + PPCS0PLBRDDACK : out std_ulogic; + PPCS0PLBRDDBUS : out std_logic_vector(0 to 127); + PPCS0PLBRDWDADDR : out std_logic_vector(0 to 3); + PPCS0PLBREARBITRATE : out std_ulogic; + PPCS0PLBSSIZE : out std_logic_vector(0 to 1); + PPCS0PLBWAIT : out std_ulogic; + PPCS0PLBWRBTERM : out std_ulogic; + PPCS0PLBWRCOMP : out std_ulogic; + PPCS0PLBWRDACK : out std_ulogic; + PPCS1PLBADDRACK : out std_ulogic; + PPCS1PLBMBUSY : out std_logic_vector(0 to 3); + PPCS1PLBMIRQ : out std_logic_vector(0 to 3); + PPCS1PLBMRDERR : out std_logic_vector(0 to 3); + PPCS1PLBMWRERR : out std_logic_vector(0 to 3); + PPCS1PLBRDBTERM : out std_ulogic; + PPCS1PLBRDCOMP : out std_ulogic; + PPCS1PLBRDDACK : out std_ulogic; + PPCS1PLBRDDBUS : out std_logic_vector(0 to 127); + PPCS1PLBRDWDADDR : out std_logic_vector(0 to 3); + PPCS1PLBREARBITRATE : out std_ulogic; + PPCS1PLBSSIZE : out std_logic_vector(0 to 1); + PPCS1PLBWAIT : out std_ulogic; + PPCS1PLBWRBTERM : out std_ulogic; + PPCS1PLBWRCOMP : out std_ulogic; + PPCS1PLBWRDACK : out std_ulogic; + + CPMC440CLK : in std_ulogic; + CPMC440CLKEN : in std_ulogic; + CPMC440CORECLOCKINACTIVE : in std_ulogic; + CPMC440TIMERCLOCK : in std_ulogic; + CPMDCRCLK : in std_ulogic; + CPMDMA0LLCLK : in std_ulogic; + CPMDMA1LLCLK : in std_ulogic; + CPMDMA2LLCLK : in std_ulogic; + CPMDMA3LLCLK : in std_ulogic; + CPMFCMCLK : in std_ulogic; + CPMINTERCONNECTCLK : in std_ulogic; + CPMINTERCONNECTCLKEN : in std_ulogic; + CPMINTERCONNECTCLKNTO1 : in std_ulogic; + CPMMCCLK : in std_ulogic; + CPMPPCMPLBCLK : in std_ulogic; + CPMPPCS0PLBCLK : in std_ulogic; + CPMPPCS1PLBCLK : in std_ulogic; + DBGC440DEBUGHALT : in std_ulogic; + DBGC440SYSTEMSTATUS : in std_logic_vector(0 to 4); + DBGC440UNCONDDEBUGEVENT : in std_ulogic; + DCRPPCDMACK : in std_ulogic; + DCRPPCDMDBUSIN : in std_logic_vector(0 to 31); + DCRPPCDMTIMEOUTWAIT : in std_ulogic; + DCRPPCDSABUS : in std_logic_vector(0 to 9); + DCRPPCDSDBUSOUT : in std_logic_vector(0 to 31); + DCRPPCDSREAD : in std_ulogic; + DCRPPCDSWRITE : in std_ulogic; + EICC440CRITIRQ : in std_ulogic; + EICC440EXTIRQ : in std_ulogic; + FCMAPUCONFIRMINSTR : in std_ulogic; + FCMAPUCR : in std_logic_vector(0 to 3); + FCMAPUDONE : in std_ulogic; + FCMAPUEXCEPTION : in std_ulogic; + FCMAPUFPSCRFEX : in std_ulogic; + FCMAPURESULT : in std_logic_vector(0 to 31); + FCMAPURESULTVALID : in std_ulogic; + FCMAPUSLEEPNOTREADY : in std_ulogic; + FCMAPUSTOREDATA : in std_logic_vector(0 to 127); + GSR : in std_ulogic; + JTGC440TCK : in std_ulogic; + JTGC440TDI : in std_ulogic; + JTGC440TMS : in std_ulogic; + JTGC440TRSTNEG : in std_ulogic; + LLDMA0RSTENGINEREQ : in std_ulogic; + LLDMA0RXD : in std_logic_vector(0 to 31); + LLDMA0RXEOFN : in std_ulogic; + LLDMA0RXEOPN : in std_ulogic; + LLDMA0RXREM : in std_logic_vector(0 to 3); + LLDMA0RXSOFN : in std_ulogic; + LLDMA0RXSOPN : in std_ulogic; + LLDMA0RXSRCRDYN : in std_ulogic; + LLDMA0TXDSTRDYN : in std_ulogic; + LLDMA1RSTENGINEREQ : in std_ulogic; + LLDMA1RXD : in std_logic_vector(0 to 31); + LLDMA1RXEOFN : in std_ulogic; + LLDMA1RXEOPN : in std_ulogic; + LLDMA1RXREM : in std_logic_vector(0 to 3); + LLDMA1RXSOFN : in std_ulogic; + LLDMA1RXSOPN : in std_ulogic; + LLDMA1RXSRCRDYN : in std_ulogic; + LLDMA1TXDSTRDYN : in std_ulogic; + LLDMA2RSTENGINEREQ : in std_ulogic; + LLDMA2RXD : in std_logic_vector(0 to 31); + LLDMA2RXEOFN : in std_ulogic; + LLDMA2RXEOPN : in std_ulogic; + LLDMA2RXREM : in std_logic_vector(0 to 3); + LLDMA2RXSOFN : in std_ulogic; + LLDMA2RXSOPN : in std_ulogic; + LLDMA2RXSRCRDYN : in std_ulogic; + LLDMA2TXDSTRDYN : in std_ulogic; + LLDMA3RSTENGINEREQ : in std_ulogic; + LLDMA3RXD : in std_logic_vector(0 to 31); + LLDMA3RXEOFN : in std_ulogic; + LLDMA3RXEOPN : in std_ulogic; + LLDMA3RXREM : in std_logic_vector(0 to 3); + LLDMA3RXSOFN : in std_ulogic; + LLDMA3RXSOPN : in std_ulogic; + LLDMA3RXSRCRDYN : in std_ulogic; + LLDMA3TXDSTRDYN : in std_ulogic; + MCMIADDRREADYTOACCEPT : in std_ulogic; + MCMIREADDATA : in std_logic_vector(0 to 127); + MCMIREADDATAERR : in std_ulogic; + MCMIREADDATAVALID : in std_ulogic; + PLBPPCMADDRACK : in std_ulogic; + PLBPPCMMBUSY : in std_ulogic; + PLBPPCMMIRQ : in std_ulogic; + PLBPPCMMRDERR : in std_ulogic; + PLBPPCMMWRERR : in std_ulogic; + PLBPPCMRDBTERM : in std_ulogic; + PLBPPCMRDDACK : in std_ulogic; + PLBPPCMRDDBUS : in std_logic_vector(0 to 127); + PLBPPCMRDPENDPRI : in std_logic_vector(0 to 1); + PLBPPCMRDPENDREQ : in std_ulogic; + PLBPPCMRDWDADDR : in std_logic_vector(0 to 3); + PLBPPCMREARBITRATE : in std_ulogic; + PLBPPCMREQPRI : in std_logic_vector(0 to 1); + PLBPPCMSSIZE : in std_logic_vector(0 to 1); + PLBPPCMTIMEOUT : in std_ulogic; + PLBPPCMWRBTERM : in std_ulogic; + PLBPPCMWRDACK : in std_ulogic; + PLBPPCMWRPENDPRI : in std_logic_vector(0 to 1); + PLBPPCMWRPENDREQ : in std_ulogic; + PLBPPCS0ABORT : in std_ulogic; + PLBPPCS0ABUS : in std_logic_vector(0 to 31); + PLBPPCS0BE : in std_logic_vector(0 to 15); + PLBPPCS0BUSLOCK : in std_ulogic; + PLBPPCS0LOCKERR : in std_ulogic; + PLBPPCS0MASTERID : in std_logic_vector(0 to 1); + PLBPPCS0MSIZE : in std_logic_vector(0 to 1); + PLBPPCS0PAVALID : in std_ulogic; + PLBPPCS0RDBURST : in std_ulogic; + PLBPPCS0RDPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS0RDPENDREQ : in std_ulogic; + PLBPPCS0RDPRIM : in std_ulogic; + PLBPPCS0REQPRI : in std_logic_vector(0 to 1); + PLBPPCS0RNW : in std_ulogic; + PLBPPCS0SAVALID : in std_ulogic; + PLBPPCS0SIZE : in std_logic_vector(0 to 3); + PLBPPCS0TATTRIBUTE : in std_logic_vector(0 to 15); + PLBPPCS0TYPE : in std_logic_vector(0 to 2); + PLBPPCS0UABUS : in std_logic_vector(28 to 31); + PLBPPCS0WRBURST : in std_ulogic; + PLBPPCS0WRDBUS : in std_logic_vector(0 to 127); + PLBPPCS0WRPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS0WRPENDREQ : in std_ulogic; + PLBPPCS0WRPRIM : in std_ulogic; + PLBPPCS1ABORT : in std_ulogic; + PLBPPCS1ABUS : in std_logic_vector(0 to 31); + PLBPPCS1BE : in std_logic_vector(0 to 15); + PLBPPCS1BUSLOCK : in std_ulogic; + PLBPPCS1LOCKERR : in std_ulogic; + PLBPPCS1MASTERID : in std_logic_vector(0 to 1); + PLBPPCS1MSIZE : in std_logic_vector(0 to 1); + PLBPPCS1PAVALID : in std_ulogic; + PLBPPCS1RDBURST : in std_ulogic; + PLBPPCS1RDPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS1RDPENDREQ : in std_ulogic; + PLBPPCS1RDPRIM : in std_ulogic; + PLBPPCS1REQPRI : in std_logic_vector(0 to 1); + PLBPPCS1RNW : in std_ulogic; + PLBPPCS1SAVALID : in std_ulogic; + PLBPPCS1SIZE : in std_logic_vector(0 to 3); + PLBPPCS1TATTRIBUTE : in std_logic_vector(0 to 15); + PLBPPCS1TYPE : in std_logic_vector(0 to 2); + PLBPPCS1UABUS : in std_logic_vector(28 to 31); + PLBPPCS1WRBURST : in std_ulogic; + PLBPPCS1WRDBUS : in std_logic_vector(0 to 127); + PLBPPCS1WRPENDPRI : in std_logic_vector(0 to 1); + PLBPPCS1WRPENDREQ : in std_ulogic; + PLBPPCS1WRPRIM : in std_ulogic; + RSTC440RESETCHIP : in std_ulogic; + RSTC440RESETCORE : in std_ulogic; + RSTC440RESETSYSTEM : in std_ulogic; + TIEC440DCURDLDCACHEPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCURDNONCACHEPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCURDTOUCHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCURDURGENTPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCUWRFLUSHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCUWRSTOREPLBPRIO : in std_logic_vector(0 to 1); + TIEC440DCUWRURGENTPLBPRIO : in std_logic_vector(0 to 1); + TIEC440ENDIANRESET : in std_ulogic; + TIEC440ERPNRESET : in std_logic_vector(0 to 3); + TIEC440ICURDFETCHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440ICURDSPECPLBPRIO : in std_logic_vector(0 to 1); + TIEC440ICURDTOUCHPLBPRIO : in std_logic_vector(0 to 1); + TIEC440PIR : in std_logic_vector(28 to 31); + TIEC440PVR : in std_logic_vector(28 to 31); + TIEC440USERRESET : in std_logic_vector(0 to 3); + TIEDCRBASEADDR : in std_logic_vector(0 to 1); + TRCC440TRACEDISABLE : in std_ulogic; + TRCC440TRIGGEREVENTIN : in std_ulogic; + + APU_CONTROL : in std_logic_vector(0 to 16); + APU_UDI0 : in std_logic_vector(0 to 23); + APU_UDI1 : in std_logic_vector(0 to 23); + APU_UDI10 : in std_logic_vector(0 to 23); + APU_UDI11 : in std_logic_vector(0 to 23); + APU_UDI12 : in std_logic_vector(0 to 23); + APU_UDI13 : in std_logic_vector(0 to 23); + APU_UDI14 : in std_logic_vector(0 to 23); + APU_UDI15 : in std_logic_vector(0 to 23); + APU_UDI2 : in std_logic_vector(0 to 23); + APU_UDI3 : in std_logic_vector(0 to 23); + APU_UDI4 : in std_logic_vector(0 to 23); + APU_UDI5 : in std_logic_vector(0 to 23); + APU_UDI6 : in std_logic_vector(0 to 23); + APU_UDI7 : in std_logic_vector(0 to 23); + APU_UDI8 : in std_logic_vector(0 to 23); + APU_UDI9 : in std_logic_vector(0 to 23); +-- CLOCK_DELAY : in std_ulogic; + CLOCK_DELAY : in std_logic_vector(0 to 4); + DCR_AUTOLOCK_ENABLE : in std_ulogic; + DMA0_CONTROL : in std_logic_vector(0 to 7); + DMA0_RXCHANNELCTRL : in std_logic_vector(0 to 31); + DMA0_RXIRQTIMER : in std_logic_vector(0 to 9); + DMA0_TXCHANNELCTRL : in std_logic_vector(0 to 31); + DMA0_TXIRQTIMER : in std_logic_vector(0 to 9); + DMA1_CONTROL : in std_logic_vector(0 to 7); + DMA1_RXCHANNELCTRL : in std_logic_vector(0 to 31); + DMA1_RXIRQTIMER : in std_logic_vector(0 to 9); + DMA1_TXCHANNELCTRL : in std_logic_vector(0 to 31); + DMA1_TXIRQTIMER : in std_logic_vector(0 to 9); + DMA2_CONTROL : in std_logic_vector(0 to 7); + DMA2_RXCHANNELCTRL : in std_logic_vector(0 to 31); + DMA2_RXIRQTIMER : in std_logic_vector(0 to 9); + DMA2_TXCHANNELCTRL : in std_logic_vector(0 to 31); + DMA2_TXIRQTIMER : in std_logic_vector(0 to 9); + DMA3_CONTROL : in std_logic_vector(0 to 7); + DMA3_RXCHANNELCTRL : in std_logic_vector(0 to 31); + DMA3_RXIRQTIMER : in std_logic_vector(0 to 9); + DMA3_TXCHANNELCTRL : in std_logic_vector(0 to 31); + DMA3_TXIRQTIMER : in std_logic_vector(0 to 9); + INTERCONNECT_IMASK : in std_logic_vector(0 to 31); + INTERCONNECT_TMPL_SEL : in std_logic_vector(0 to 31); + MI_ARBCONFIG : in std_logic_vector(0 to 31); + MI_BANKCONFLICT_MASK : in std_logic_vector(0 to 31); + MI_CONTROL : in std_logic_vector(0 to 31); + MI_ROWCONFLICT_MASK : in std_logic_vector(0 to 31); + PPCDM_ASYNCMODE : in std_ulogic; + PPCDS_ASYNCMODE : in std_ulogic; + PPCM_ARBCONFIG : in std_logic_vector(0 to 31); + PPCM_CONTROL : in std_logic_vector(0 to 31); + PPCM_COUNTER : in std_logic_vector(0 to 31); + PPCS0_ADDRMAP_TMPL0 : in std_logic_vector(0 to 31); + PPCS0_ADDRMAP_TMPL1 : in std_logic_vector(0 to 31); + PPCS0_ADDRMAP_TMPL2 : in std_logic_vector(0 to 31); + PPCS0_ADDRMAP_TMPL3 : in std_logic_vector(0 to 31); + PPCS0_CONTROL : in std_logic_vector(0 to 31); + PPCS0_WIDTH_128N64 : in std_ulogic; + PPCS1_ADDRMAP_TMPL0 : in std_logic_vector(0 to 31); + PPCS1_ADDRMAP_TMPL1 : in std_logic_vector(0 to 31); + PPCS1_ADDRMAP_TMPL2 : in std_logic_vector(0 to 31); + PPCS1_ADDRMAP_TMPL3 : in std_logic_vector(0 to 31); + PPCS1_CONTROL : in std_logic_vector(0 to 31); + PPCS1_WIDTH_128N64 : in std_ulogic; + XBAR_ADDRMAP_TMPL0 : in std_logic_vector(0 to 31); + XBAR_ADDRMAP_TMPL1 : in std_logic_vector(0 to 31); + XBAR_ADDRMAP_TMPL2 : in std_logic_vector(0 to 31); + XBAR_ADDRMAP_TMPL3 : in std_logic_vector(0 to 31) + ); + end component; + + constant IN_DELAY : time := 1 ps; + constant OUT_DELAY : time := 0 ps; + constant CLK_DELAY : time := 0 ps; + constant ZERO_DELAY : time := 0 ps; + + constant PATH_DELAY : VitalDelayType01 := (100 ps, 100 ps); + + + signal DMA3_TXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA3_TXCHANNELCTRL); + signal DMA3_CONTROL_BINARY : std_logic_vector(0 to 7) := To_StdLogicVector(DMA3_CONTROL); + signal DMA3_RXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA3_RXCHANNELCTRL); + signal DMA3_TXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA3_TXIRQTIMER)(9 downto 0); + signal DMA3_RXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA3_RXIRQTIMER)(9 downto 0); + signal DMA2_TXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA2_TXCHANNELCTRL); + signal DMA2_CONTROL_BINARY : std_logic_vector(0 to 7) := To_StdLogicVector(DMA2_CONTROL); + signal DMA2_RXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA2_RXCHANNELCTRL); + signal DMA2_TXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA2_TXIRQTIMER)(9 downto 0); + signal DMA2_RXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA2_RXIRQTIMER)(9 downto 0); + signal PPCM_CONTROL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCM_CONTROL); + signal PPCM_COUNTER_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCM_COUNTER); + signal PPCM_ARBCONFIG_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCM_ARBCONFIG); + signal DMA1_RXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA1_RXIRQTIMER)(9 downto 0); + signal DMA1_TXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA1_TXIRQTIMER)(9 downto 0); + signal DMA1_RXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA1_RXCHANNELCTRL); + signal DMA1_CONTROL_BINARY : std_logic_vector(0 to 7) := To_StdLogicVector(DMA1_CONTROL); + signal DMA1_TXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA1_TXCHANNELCTRL); + signal DMA0_RXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA0_RXIRQTIMER)(9 downto 0); + signal DMA0_TXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA0_TXIRQTIMER)(9 downto 0); + signal DMA0_RXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA0_RXCHANNELCTRL); + signal DMA0_CONTROL_BINARY : std_logic_vector(0 to 7) := To_StdLogicVector(DMA0_CONTROL); + signal DMA0_TXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA0_TXCHANNELCTRL); + signal MI_ROWCONFLICT_MASK_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(MI_ROWCONFLICT_MASK); + signal MI_BANKCONFLICT_MASK_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(MI_BANKCONFLICT_MASK); + signal MI_ARBCONFIG_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(MI_ARBCONFIG); + signal MI_CONTROL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(MI_CONTROL); + signal APU_UDI0_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI0); + signal APU_UDI1_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI1); + signal APU_UDI2_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI2); + signal APU_UDI3_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI3); + signal APU_UDI4_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI4); + signal APU_UDI5_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI5); + signal APU_UDI6_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI6); + signal APU_UDI7_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI7); + signal APU_UDI8_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI8); + signal APU_UDI9_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI9); + signal APU_UDI10_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI10); + signal APU_UDI11_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI11); + signal APU_UDI12_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI12); + signal APU_UDI13_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI13); + signal APU_UDI14_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI14); + signal APU_UDI15_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI15); + signal APU_CONTROL_BINARY : std_logic_vector(0 to 16) := To_StdLogicVector(APU_CONTROL)(16 downto 0); + signal INTERCONNECT_IMASK_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(INTERCONNECT_IMASK); + signal XBAR_ADDRMAP_TMPL0_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(XBAR_ADDRMAP_TMPL0); + signal XBAR_ADDRMAP_TMPL1_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(XBAR_ADDRMAP_TMPL1); + signal XBAR_ADDRMAP_TMPL2_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(XBAR_ADDRMAP_TMPL2); + signal XBAR_ADDRMAP_TMPL3_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(XBAR_ADDRMAP_TMPL3); + signal INTERCONNECT_TMPL_SEL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(INTERCONNECT_TMPL_SEL); + signal PPCS0_CONTROL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS0_CONTROL); + signal PPCS0_WIDTH_128N64_BINARY : std_ulogic; + signal PPCS0_ADDRMAP_TMPL0_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS0_ADDRMAP_TMPL0); + signal PPCS0_ADDRMAP_TMPL1_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS0_ADDRMAP_TMPL1); + signal PPCS0_ADDRMAP_TMPL2_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS0_ADDRMAP_TMPL2); + signal PPCS0_ADDRMAP_TMPL3_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS0_ADDRMAP_TMPL3); + signal PPCS1_CONTROL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS1_CONTROL); + signal PPCS1_WIDTH_128N64_BINARY : std_ulogic; + signal PPCS1_ADDRMAP_TMPL0_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS1_ADDRMAP_TMPL0); + signal PPCS1_ADDRMAP_TMPL1_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS1_ADDRMAP_TMPL1); + signal PPCS1_ADDRMAP_TMPL2_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS1_ADDRMAP_TMPL2); + signal PPCS1_ADDRMAP_TMPL3_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS1_ADDRMAP_TMPL3); + signal PPCDM_ASYNCMODE_BINARY : std_ulogic; + signal PPCDS_ASYNCMODE_BINARY : std_ulogic; + signal DCR_AUTOLOCK_ENABLE_BINARY : std_ulogic; + signal CLOCK_DELAY_BINARY : std_logic_vector(0 to 4); + + signal DMA0LLRSTENGINEACK_out : std_ulogic; + signal DMA0LLRXDSTRDYN_out : std_ulogic; + signal DMA0LLTXD_out : std_logic_vector(0 to 31); + signal DMA0LLTXEOFN_out : std_ulogic; + signal DMA0LLTXEOPN_out : std_ulogic; + signal DMA0LLTXREM_out : std_logic_vector(0 to 3); + signal DMA0LLTXSOFN_out : std_ulogic; + signal DMA0LLTXSOPN_out : std_ulogic; + signal DMA0LLTXSRCRDYN_out : std_ulogic; + signal DMA0RXIRQ_out : std_ulogic; + signal DMA0TXIRQ_out : std_ulogic; + signal DMA1LLRSTENGINEACK_out : std_ulogic; + signal DMA1LLRXDSTRDYN_out : std_ulogic; + signal DMA1LLTXD_out : std_logic_vector(0 to 31); + signal DMA1LLTXEOFN_out : std_ulogic; + signal DMA1LLTXEOPN_out : std_ulogic; + signal DMA1LLTXREM_out : std_logic_vector(0 to 3); + signal DMA1LLTXSOFN_out : std_ulogic; + signal DMA1LLTXSOPN_out : std_ulogic; + signal DMA1LLTXSRCRDYN_out : std_ulogic; + signal DMA1RXIRQ_out : std_ulogic; + signal DMA1TXIRQ_out : std_ulogic; + signal DMA2LLRSTENGINEACK_out : std_ulogic; + signal DMA2LLRXDSTRDYN_out : std_ulogic; + signal DMA2LLTXD_out : std_logic_vector(0 to 31); + signal DMA2LLTXEOFN_out : std_ulogic; + signal DMA2LLTXEOPN_out : std_ulogic; + signal DMA2LLTXREM_out : std_logic_vector(0 to 3); + signal DMA2LLTXSOFN_out : std_ulogic; + signal DMA2LLTXSOPN_out : std_ulogic; + signal DMA2LLTXSRCRDYN_out : std_ulogic; + signal DMA2RXIRQ_out : std_ulogic; + signal DMA2TXIRQ_out : std_ulogic; + signal DMA3LLRSTENGINEACK_out : std_ulogic; + signal DMA3LLRXDSTRDYN_out : std_ulogic; + signal DMA3LLTXD_out : std_logic_vector(0 to 31); + signal DMA3LLTXEOFN_out : std_ulogic; + signal DMA3LLTXEOPN_out : std_ulogic; + signal DMA3LLTXREM_out : std_logic_vector(0 to 3); + signal DMA3LLTXSOFN_out : std_ulogic; + signal DMA3LLTXSOPN_out : std_ulogic; + signal DMA3LLTXSRCRDYN_out : std_ulogic; + signal DMA3RXIRQ_out : std_ulogic; + signal DMA3TXIRQ_out : std_ulogic; + signal PPCDMDCRABUS_out : std_logic_vector(0 to 9); + signal PPCDMDCRDBUSOUT_out : std_logic_vector(0 to 31); + signal PPCDMDCRREAD_out : std_ulogic; + signal PPCDMDCRUABUS_out : std_logic_vector(20 to 21); + signal PPCDMDCRWRITE_out : std_ulogic; + signal PPCMPLBABORT_out : std_ulogic; + signal PPCMPLBABUS_out : std_logic_vector(0 to 31); + signal PPCMPLBBE_out : std_logic_vector(0 to 15); + signal PPCMPLBBUSLOCK_out : std_ulogic; + signal PPCMPLBLOCKERR_out : std_ulogic; + signal PPCMPLBPRIORITY_out : std_logic_vector(0 to 1); + signal PPCMPLBRDBURST_out : std_ulogic; + signal PPCMPLBREQUEST_out : std_ulogic; + signal PPCMPLBRNW_out : std_ulogic; + signal PPCMPLBSIZE_out : std_logic_vector(0 to 3); + signal PPCMPLBTATTRIBUTE_out : std_logic_vector(0 to 15); + signal PPCMPLBTYPE_out : std_logic_vector(0 to 2); + signal PPCMPLBUABUS_out : std_logic_vector(28 to 31); + signal PPCMPLBWRBURST_out : std_ulogic; + signal PPCMPLBWRDBUS_out : std_logic_vector(0 to 127); + signal PPCS0PLBADDRACK_out : std_ulogic; + signal PPCS0PLBMBUSY_out : std_logic_vector(0 to 3); + signal PPCS0PLBMIRQ_out : std_logic_vector(0 to 3); + signal PPCS0PLBMRDERR_out : std_logic_vector(0 to 3); + signal PPCS0PLBMWRERR_out : std_logic_vector(0 to 3); + signal PPCS0PLBRDBTERM_out : std_ulogic; + signal PPCS0PLBRDCOMP_out : std_ulogic; + signal PPCS0PLBRDDACK_out : std_ulogic; + signal PPCS0PLBRDDBUS_out : std_logic_vector(0 to 127); + signal PPCS0PLBRDWDADDR_out : std_logic_vector(0 to 3); + signal PPCS0PLBREARBITRATE_out : std_ulogic; + signal PPCS0PLBSSIZE_out : std_logic_vector(0 to 1); + signal PPCS0PLBWAIT_out : std_ulogic; + signal PPCS0PLBWRBTERM_out : std_ulogic; + signal PPCS0PLBWRCOMP_out : std_ulogic; + signal PPCS0PLBWRDACK_out : std_ulogic; + signal PPCS1PLBADDRACK_out : std_ulogic; + signal PPCS1PLBMBUSY_out : std_logic_vector(0 to 3); + signal PPCS1PLBMIRQ_out : std_logic_vector(0 to 3); + signal PPCS1PLBMRDERR_out : std_logic_vector(0 to 3); + signal PPCS1PLBMWRERR_out : std_logic_vector(0 to 3); + signal PPCS1PLBRDBTERM_out : std_ulogic; + signal PPCS1PLBRDCOMP_out : std_ulogic; + signal PPCS1PLBRDDACK_out : std_ulogic; + signal PPCS1PLBRDDBUS_out : std_logic_vector(0 to 127); + signal PPCS1PLBRDWDADDR_out : std_logic_vector(0 to 3); + signal PPCS1PLBREARBITRATE_out : std_ulogic; + signal PPCS1PLBSSIZE_out : std_logic_vector(0 to 1); + signal PPCS1PLBWAIT_out : std_ulogic; + signal PPCS1PLBWRBTERM_out : std_ulogic; + signal PPCS1PLBWRCOMP_out : std_ulogic; + signal PPCS1PLBWRDACK_out : std_ulogic; + signal APUFCMDECFPUOP_out : std_ulogic; + signal APUFCMDECLDSTXFERSIZE_out : std_logic_vector(0 to 2); + signal APUFCMDECLOAD_out : std_ulogic; + signal APUFCMDECNONAUTON_out : std_ulogic; + signal APUFCMDECSTORE_out : std_ulogic; + signal APUFCMDECUDI_out : std_logic_vector(0 to 3); + signal APUFCMDECUDIVALID_out : std_ulogic; + signal APUFCMENDIAN_out : std_ulogic; + signal APUFCMFLUSH_out : std_ulogic; + signal APUFCMINSTRUCTION_out : std_logic_vector(0 to 31); + signal APUFCMINSTRVALID_out : std_ulogic; + signal APUFCMLOADBYTEADDR_out : std_logic_vector(0 to 3); + signal APUFCMLOADDATA_out : std_logic_vector(0 to 127); + signal APUFCMLOADDVALID_out : std_ulogic; + signal APUFCMMSRFE0_out : std_ulogic; + signal APUFCMMSRFE1_out : std_ulogic; + signal APUFCMNEXTINSTRREADY_out : std_ulogic; + signal APUFCMOPERANDVALID_out : std_ulogic; + signal APUFCMRADATA_out : std_logic_vector(0 to 31); + signal APUFCMRBDATA_out : std_logic_vector(0 to 31); + signal APUFCMWRITEBACKOK_out : std_ulogic; + signal C440CPMCORESLEEPREQ_out : std_ulogic; + signal C440CPMDECIRPTREQ_out : std_ulogic; + signal C440CPMFITIRPTREQ_out : std_ulogic; + signal C440CPMMSRCE_out : std_ulogic; + signal C440CPMMSREE_out : std_ulogic; + signal C440CPMTIMERRESETREQ_out : std_ulogic; + signal C440CPMWDIRPTREQ_out : std_ulogic; + signal C440DBGSYSTEMCONTROL_out : std_logic_vector(0 to 7); + signal C440JTGTDO_out : std_ulogic; + signal C440JTGTDOEN_out : std_ulogic; + signal C440MACHINECHECK_out : std_ulogic; + signal C440RSTCHIPRESETREQ_out : std_ulogic; + signal C440RSTCORERESETREQ_out : std_ulogic; + signal C440RSTSYSTEMRESETREQ_out : std_ulogic; + signal C440TRCBRANCHSTATUS_out : std_logic_vector(0 to 2); + signal C440TRCCYCLE_out : std_ulogic; + signal C440TRCEXECUTIONSTATUS_out : std_logic_vector(0 to 4); + signal C440TRCTRACESTATUS_out : std_logic_vector(0 to 6); + signal C440TRCTRIGGEREVENTOUT_out : std_ulogic; + signal C440TRCTRIGGEREVENTTYPE_out : std_logic_vector(0 to 13); + signal MIMCADDRESS_out : std_logic_vector(0 to 35); + signal MIMCADDRESSVALID_out : std_ulogic; + signal MIMCBANKCONFLICT_out : std_ulogic; + signal MIMCBYTEENABLE_out : std_logic_vector(0 to 15); + signal MIMCREADNOTWRITE_out : std_ulogic; + signal MIMCROWCONFLICT_out : std_ulogic; + signal MIMCWRITEDATA_out : std_logic_vector(0 to 127); + signal MIMCWRITEDATAVALID_out : std_ulogic; + signal PPCCPMINTERCONNECTBUSY_out : std_ulogic; + signal PPCDSDCRACK_out : std_ulogic; + signal PPCDSDCRTIMEOUTWAIT_out : std_ulogic; + signal PPCDSDCRDBUSIN_out : std_logic_vector(0 to 31); + signal PPCEICINTERCONNECTIRQ_out : std_ulogic; + + + signal DMA0LLRSTENGINEACK_outdelay : std_ulogic; + signal DMA0LLRXDSTRDYN_outdelay : std_ulogic; + signal DMA0LLTXD_outdelay : std_logic_vector(0 to 31); + signal DMA0LLTXEOFN_outdelay : std_ulogic; + signal DMA0LLTXEOPN_outdelay : std_ulogic; + signal DMA0LLTXREM_outdelay : std_logic_vector(0 to 3); + signal DMA0LLTXSOFN_outdelay : std_ulogic; + signal DMA0LLTXSOPN_outdelay : std_ulogic; + signal DMA0LLTXSRCRDYN_outdelay : std_ulogic; + signal DMA0RXIRQ_outdelay : std_ulogic; + signal DMA0TXIRQ_outdelay : std_ulogic; + signal DMA1LLRSTENGINEACK_outdelay : std_ulogic; + signal DMA1LLRXDSTRDYN_outdelay : std_ulogic; + signal DMA1LLTXD_outdelay : std_logic_vector(0 to 31); + signal DMA1LLTXEOFN_outdelay : std_ulogic; + signal DMA1LLTXEOPN_outdelay : std_ulogic; + signal DMA1LLTXREM_outdelay : std_logic_vector(0 to 3); + signal DMA1LLTXSOFN_outdelay : std_ulogic; + signal DMA1LLTXSOPN_outdelay : std_ulogic; + signal DMA1LLTXSRCRDYN_outdelay : std_ulogic; + signal DMA1RXIRQ_outdelay : std_ulogic; + signal DMA1TXIRQ_outdelay : std_ulogic; + signal DMA2LLRSTENGINEACK_outdelay : std_ulogic; + signal DMA2LLRXDSTRDYN_outdelay : std_ulogic; + signal DMA2LLTXD_outdelay : std_logic_vector(0 to 31); + signal DMA2LLTXEOFN_outdelay : std_ulogic; + signal DMA2LLTXEOPN_outdelay : std_ulogic; + signal DMA2LLTXREM_outdelay : std_logic_vector(0 to 3); + signal DMA2LLTXSOFN_outdelay : std_ulogic; + signal DMA2LLTXSOPN_outdelay : std_ulogic; + signal DMA2LLTXSRCRDYN_outdelay : std_ulogic; + signal DMA2RXIRQ_outdelay : std_ulogic; + signal DMA2TXIRQ_outdelay : std_ulogic; + signal DMA3LLRSTENGINEACK_outdelay : std_ulogic; + signal DMA3LLRXDSTRDYN_outdelay : std_ulogic; + signal DMA3LLTXD_outdelay : std_logic_vector(0 to 31); + signal DMA3LLTXEOFN_outdelay : std_ulogic; + signal DMA3LLTXEOPN_outdelay : std_ulogic; + signal DMA3LLTXREM_outdelay : std_logic_vector(0 to 3); + signal DMA3LLTXSOFN_outdelay : std_ulogic; + signal DMA3LLTXSOPN_outdelay : std_ulogic; + signal DMA3LLTXSRCRDYN_outdelay : std_ulogic; + signal DMA3RXIRQ_outdelay : std_ulogic; + signal DMA3TXIRQ_outdelay : std_ulogic; + signal PPCDMDCRABUS_outdelay : std_logic_vector(0 to 9); + signal PPCDMDCRDBUSOUT_outdelay : std_logic_vector(0 to 31); + signal PPCDMDCRREAD_outdelay : std_ulogic; + signal PPCDMDCRUABUS_outdelay : std_logic_vector(20 to 21); + signal PPCDMDCRWRITE_outdelay : std_ulogic; + signal PPCMPLBABORT_outdelay : std_ulogic; + signal PPCMPLBABUS_outdelay : std_logic_vector(0 to 31); + signal PPCMPLBBE_outdelay : std_logic_vector(0 to 15); + signal PPCMPLBBUSLOCK_outdelay : std_ulogic; + signal PPCMPLBLOCKERR_outdelay : std_ulogic; + signal PPCMPLBPRIORITY_outdelay : std_logic_vector(0 to 1); + signal PPCMPLBRDBURST_outdelay : std_ulogic; + signal PPCMPLBREQUEST_outdelay : std_ulogic; + signal PPCMPLBRNW_outdelay : std_ulogic; + signal PPCMPLBSIZE_outdelay : std_logic_vector(0 to 3); + signal PPCMPLBTATTRIBUTE_outdelay : std_logic_vector(0 to 15); + signal PPCMPLBTYPE_outdelay : std_logic_vector(0 to 2); + signal PPCMPLBUABUS_outdelay : std_logic_vector(28 to 31); + signal PPCMPLBWRBURST_outdelay : std_ulogic; + signal PPCMPLBWRDBUS_outdelay : std_logic_vector(0 to 127); + signal PPCS0PLBADDRACK_outdelay : std_ulogic; + signal PPCS0PLBMBUSY_outdelay : std_logic_vector(0 to 3); + signal PPCS0PLBMIRQ_outdelay : std_logic_vector(0 to 3); + signal PPCS0PLBMRDERR_outdelay : std_logic_vector(0 to 3); + signal PPCS0PLBMWRERR_outdelay : std_logic_vector(0 to 3); + signal PPCS0PLBRDBTERM_outdelay : std_ulogic; + signal PPCS0PLBRDCOMP_outdelay : std_ulogic; + signal PPCS0PLBRDDACK_outdelay : std_ulogic; + signal PPCS0PLBRDDBUS_outdelay : std_logic_vector(0 to 127); + signal PPCS0PLBRDWDADDR_outdelay : std_logic_vector(0 to 3); + signal PPCS0PLBREARBITRATE_outdelay : std_ulogic; + signal PPCS0PLBSSIZE_outdelay : std_logic_vector(0 to 1); + signal PPCS0PLBWAIT_outdelay : std_ulogic; + signal PPCS0PLBWRBTERM_outdelay : std_ulogic; + signal PPCS0PLBWRCOMP_outdelay : std_ulogic; + signal PPCS0PLBWRDACK_outdelay : std_ulogic; + signal PPCS1PLBADDRACK_outdelay : std_ulogic; + signal PPCS1PLBMBUSY_outdelay : std_logic_vector(0 to 3); + signal PPCS1PLBMIRQ_outdelay : std_logic_vector(0 to 3); + signal PPCS1PLBMRDERR_outdelay : std_logic_vector(0 to 3); + signal PPCS1PLBMWRERR_outdelay : std_logic_vector(0 to 3); + signal PPCS1PLBRDBTERM_outdelay : std_ulogic; + signal PPCS1PLBRDCOMP_outdelay : std_ulogic; + signal PPCS1PLBRDDACK_outdelay : std_ulogic; + signal PPCS1PLBRDDBUS_outdelay : std_logic_vector(0 to 127); + signal PPCS1PLBRDWDADDR_outdelay : std_logic_vector(0 to 3); + signal PPCS1PLBREARBITRATE_outdelay : std_ulogic; + signal PPCS1PLBSSIZE_outdelay : std_logic_vector(0 to 1); + signal PPCS1PLBWAIT_outdelay : std_ulogic; + signal PPCS1PLBWRBTERM_outdelay : std_ulogic; + signal PPCS1PLBWRCOMP_outdelay : std_ulogic; + signal PPCS1PLBWRDACK_outdelay : std_ulogic; + signal APUFCMDECFPUOP_outdelay : std_ulogic; + signal APUFCMDECLDSTXFERSIZE_outdelay : std_logic_vector(0 to 2); + signal APUFCMDECLOAD_outdelay : std_ulogic; + signal APUFCMDECNONAUTON_outdelay : std_ulogic; + signal APUFCMDECSTORE_outdelay : std_ulogic; + signal APUFCMDECUDI_outdelay : std_logic_vector(0 to 3); + signal APUFCMDECUDIVALID_outdelay : std_ulogic; + signal APUFCMENDIAN_outdelay : std_ulogic; + signal APUFCMFLUSH_outdelay : std_ulogic; + signal APUFCMINSTRUCTION_outdelay : std_logic_vector(0 to 31); + signal APUFCMINSTRVALID_outdelay : std_ulogic; + signal APUFCMLOADBYTEADDR_outdelay : std_logic_vector(0 to 3); + signal APUFCMLOADDATA_outdelay : std_logic_vector(0 to 127); + signal APUFCMLOADDVALID_outdelay : std_ulogic; + signal APUFCMMSRFE0_outdelay : std_ulogic; + signal APUFCMMSRFE1_outdelay : std_ulogic; + signal APUFCMNEXTINSTRREADY_outdelay : std_ulogic; + signal APUFCMOPERANDVALID_outdelay : std_ulogic; + signal APUFCMRADATA_outdelay : std_logic_vector(0 to 31); + signal APUFCMRBDATA_outdelay : std_logic_vector(0 to 31); + signal APUFCMWRITEBACKOK_outdelay : std_ulogic; + signal C440CPMCORESLEEPREQ_outdelay : std_ulogic; + signal C440CPMDECIRPTREQ_outdelay : std_ulogic; + signal C440CPMFITIRPTREQ_outdelay : std_ulogic; + signal C440CPMMSRCE_outdelay : std_ulogic; + signal C440CPMMSREE_outdelay : std_ulogic; + signal C440CPMTIMERRESETREQ_outdelay : std_ulogic; + signal C440CPMWDIRPTREQ_outdelay : std_ulogic; + signal C440DBGSYSTEMCONTROL_outdelay : std_logic_vector(0 to 7); + signal C440JTGTDO_outdelay : std_ulogic; + signal C440JTGTDOEN_outdelay : std_ulogic; + signal C440MACHINECHECK_outdelay : std_ulogic; + signal C440RSTCHIPRESETREQ_outdelay : std_ulogic; + signal C440RSTCORERESETREQ_outdelay : std_ulogic; + signal C440RSTSYSTEMRESETREQ_outdelay : std_ulogic; + signal C440TRCBRANCHSTATUS_outdelay : std_logic_vector(0 to 2); + signal C440TRCCYCLE_outdelay : std_ulogic; + signal C440TRCEXECUTIONSTATUS_outdelay : std_logic_vector(0 to 4); + signal C440TRCTRACESTATUS_outdelay : std_logic_vector(0 to 6); + signal C440TRCTRIGGEREVENTOUT_outdelay : std_ulogic; + signal C440TRCTRIGGEREVENTTYPE_outdelay : std_logic_vector(0 to 13); + signal MIMCADDRESS_outdelay : std_logic_vector(0 to 35); + signal MIMCADDRESSVALID_outdelay : std_ulogic; + signal MIMCBANKCONFLICT_outdelay : std_ulogic; + signal MIMCBYTEENABLE_outdelay : std_logic_vector(0 to 15); + signal MIMCREADNOTWRITE_outdelay : std_ulogic; + signal MIMCROWCONFLICT_outdelay : std_ulogic; + signal MIMCWRITEDATA_outdelay : std_logic_vector(0 to 127); + signal MIMCWRITEDATAVALID_outdelay : std_ulogic; + signal PPCCPMINTERCONNECTBUSY_outdelay : std_ulogic; + signal PPCDSDCRACK_outdelay : std_ulogic; + signal PPCDSDCRTIMEOUTWAIT_outdelay : std_ulogic; + signal PPCDSDCRDBUSIN_outdelay : std_logic_vector(0 to 31); + signal PPCEICINTERCONNECTIRQ_outdelay : std_ulogic; + + signal PLBPPCS0RNW_ipd : std_ulogic; + signal PLBPPCS1RNW_ipd : std_ulogic; + signal CPMDCRCLK_ipd : std_ulogic; + signal CPMDMA0LLCLK_ipd : std_ulogic; + signal CPMDMA1LLCLK_ipd : std_ulogic; + signal CPMDMA2LLCLK_ipd : std_ulogic; + signal CPMDMA3LLCLK_ipd : std_ulogic; + signal CPMINTERCONNECTCLKNTO1_ipd : std_ulogic; + signal CPMPPCMPLBCLK_ipd : std_ulogic; + signal CPMPPCS0PLBCLK_ipd : std_ulogic; + signal CPMPPCS1PLBCLK_ipd : std_ulogic; + signal DCRPPCDMACK_ipd : std_ulogic; + signal DCRPPCDMDBUSIN_ipd : std_logic_vector(0 to 31); + signal DCRPPCDMTIMEOUTWAIT_ipd : std_ulogic; + signal LLDMA0RSTENGINEREQ_ipd : std_ulogic; + signal LLDMA0RXD_ipd : std_logic_vector(0 to 31); + signal LLDMA0RXEOFN_ipd : std_ulogic; + signal LLDMA0RXEOPN_ipd : std_ulogic; + signal LLDMA0RXREM_ipd : std_logic_vector(0 to 3); + signal LLDMA0RXSOFN_ipd : std_ulogic; + signal LLDMA0RXSOPN_ipd : std_ulogic; + signal LLDMA0RXSRCRDYN_ipd : std_ulogic; + signal LLDMA0TXDSTRDYN_ipd : std_ulogic; + signal LLDMA1RSTENGINEREQ_ipd : std_ulogic; + signal LLDMA1RXD_ipd : std_logic_vector(0 to 31); + signal LLDMA1RXEOFN_ipd : std_ulogic; + signal LLDMA1RXEOPN_ipd : std_ulogic; + signal LLDMA1RXREM_ipd : std_logic_vector(0 to 3); + signal LLDMA1RXSOFN_ipd : std_ulogic; + signal LLDMA1RXSOPN_ipd : std_ulogic; + signal LLDMA1RXSRCRDYN_ipd : std_ulogic; + signal LLDMA1TXDSTRDYN_ipd : std_ulogic; + signal LLDMA2RSTENGINEREQ_ipd : std_ulogic; + signal LLDMA2RXD_ipd : std_logic_vector(0 to 31); + signal LLDMA2RXEOFN_ipd : std_ulogic; + signal LLDMA2RXEOPN_ipd : std_ulogic; + signal LLDMA2RXREM_ipd : std_logic_vector(0 to 3); + signal LLDMA2RXSOFN_ipd : std_ulogic; + signal LLDMA2RXSOPN_ipd : std_ulogic; + signal LLDMA2RXSRCRDYN_ipd : std_ulogic; + signal LLDMA2TXDSTRDYN_ipd : std_ulogic; + signal LLDMA3RSTENGINEREQ_ipd : std_ulogic; + signal LLDMA3RXD_ipd : std_logic_vector(0 to 31); + signal LLDMA3RXEOFN_ipd : std_ulogic; + signal LLDMA3RXEOPN_ipd : std_ulogic; + signal LLDMA3RXREM_ipd : std_logic_vector(0 to 3); + signal LLDMA3RXSOFN_ipd : std_ulogic; + signal LLDMA3RXSOPN_ipd : std_ulogic; + signal LLDMA3RXSRCRDYN_ipd : std_ulogic; + signal LLDMA3TXDSTRDYN_ipd : std_ulogic; + signal PLBPPCMADDRACK_ipd : std_ulogic; + signal PLBPPCMMBUSY_ipd : std_ulogic; + signal PLBPPCMMIRQ_ipd : std_ulogic; + signal PLBPPCMMRDERR_ipd : std_ulogic; + signal PLBPPCMMWRERR_ipd : std_ulogic; + signal PLBPPCMRDBTERM_ipd : std_ulogic; + signal PLBPPCMRDDACK_ipd : std_ulogic; + signal PLBPPCMRDDBUS_ipd : std_logic_vector(0 to 127); + signal PLBPPCMRDPENDPRI_ipd : std_logic_vector(0 to 1); + signal PLBPPCMRDPENDREQ_ipd : std_ulogic; + signal PLBPPCMRDWDADDR_ipd : std_logic_vector(0 to 3); + signal PLBPPCMREARBITRATE_ipd : std_ulogic; + signal PLBPPCMREQPRI_ipd : std_logic_vector(0 to 1); + signal PLBPPCMSSIZE_ipd : std_logic_vector(0 to 1); + signal PLBPPCMTIMEOUT_ipd : std_ulogic; + signal PLBPPCMWRBTERM_ipd : std_ulogic; + signal PLBPPCMWRDACK_ipd : std_ulogic; + signal PLBPPCMWRPENDPRI_ipd : std_logic_vector(0 to 1); + signal PLBPPCMWRPENDREQ_ipd : std_ulogic; + signal PLBPPCS0ABORT_ipd : std_ulogic; + signal PLBPPCS0ABUS_ipd : std_logic_vector(0 to 31); + signal PLBPPCS0BE_ipd : std_logic_vector(0 to 15); + signal PLBPPCS0BUSLOCK_ipd : std_ulogic; + signal PLBPPCS0LOCKERR_ipd : std_ulogic; + signal PLBPPCS0MASTERID_ipd : std_logic_vector(0 to 1); + signal PLBPPCS0MSIZE_ipd : std_logic_vector(0 to 1); + signal PLBPPCS0PAVALID_ipd : std_ulogic; + signal PLBPPCS0RDBURST_ipd : std_ulogic; + signal PLBPPCS0RDPENDPRI_ipd : std_logic_vector(0 to 1); + signal PLBPPCS0RDPENDREQ_ipd : std_ulogic; + signal PLBPPCS0RDPRIM_ipd : std_ulogic; + signal PLBPPCS0REQPRI_ipd : std_logic_vector(0 to 1); + signal PLBPPCS0SAVALID_ipd : std_ulogic; + signal PLBPPCS0SIZE_ipd : std_logic_vector(0 to 3); + signal PLBPPCS0TATTRIBUTE_ipd : std_logic_vector(0 to 15); + signal PLBPPCS0TYPE_ipd : std_logic_vector(0 to 2); + signal PLBPPCS0UABUS_ipd : std_logic_vector(28 to 31); + signal PLBPPCS0WRBURST_ipd : std_ulogic; + signal PLBPPCS0WRDBUS_ipd : std_logic_vector(0 to 127); + signal PLBPPCS0WRPENDPRI_ipd : std_logic_vector(0 to 1); + signal PLBPPCS0WRPENDREQ_ipd : std_ulogic; + signal PLBPPCS0WRPRIM_ipd : std_ulogic; + signal PLBPPCS1ABORT_ipd : std_ulogic; + signal PLBPPCS1ABUS_ipd : std_logic_vector(0 to 31); + signal PLBPPCS1BE_ipd : std_logic_vector(0 to 15); + signal PLBPPCS1BUSLOCK_ipd : std_ulogic; + signal PLBPPCS1LOCKERR_ipd : std_ulogic; + signal PLBPPCS1MASTERID_ipd : std_logic_vector(0 to 1); + signal PLBPPCS1MSIZE_ipd : std_logic_vector(0 to 1); + signal PLBPPCS1PAVALID_ipd : std_ulogic; + signal PLBPPCS1RDBURST_ipd : std_ulogic; + signal PLBPPCS1RDPENDPRI_ipd : std_logic_vector(0 to 1); + signal PLBPPCS1RDPENDREQ_ipd : std_ulogic; + signal PLBPPCS1RDPRIM_ipd : std_ulogic; + signal PLBPPCS1REQPRI_ipd : std_logic_vector(0 to 1); + signal PLBPPCS1SAVALID_ipd : std_ulogic; + signal PLBPPCS1SIZE_ipd : std_logic_vector(0 to 3); + signal PLBPPCS1TATTRIBUTE_ipd : std_logic_vector(0 to 15); + signal PLBPPCS1TYPE_ipd : std_logic_vector(0 to 2); + signal PLBPPCS1UABUS_ipd : std_logic_vector(28 to 31); + signal PLBPPCS1WRBURST_ipd : std_ulogic; + signal PLBPPCS1WRDBUS_ipd : std_logic_vector(0 to 127); + signal PLBPPCS1WRPENDPRI_ipd : std_logic_vector(0 to 1); + signal PLBPPCS1WRPENDREQ_ipd : std_ulogic; + signal PLBPPCS1WRPRIM_ipd : std_ulogic; + signal TIEDCRBASEADDR_ipd : std_logic_vector(0 to 1); + signal CPMC440CLK_ipd : std_ulogic; + signal CPMC440CLKEN_ipd : std_ulogic; + signal CPMC440CORECLOCKINACTIVE_ipd : std_ulogic; + signal CPMC440TIMERCLOCK_ipd : std_ulogic; + signal CPMFCMCLK_ipd : std_ulogic; + signal CPMINTERCONNECTCLK_ipd : std_ulogic; + signal CPMINTERCONNECTCLKEN_ipd : std_ulogic; + signal CPMMCCLK_ipd : std_ulogic; + signal DBGC440DEBUGHALT_ipd : std_ulogic; + signal DBGC440SYSTEMSTATUS_ipd : std_logic_vector(0 to 4); + signal DBGC440UNCONDDEBUGEVENT_ipd : std_ulogic; + signal DCRPPCDSABUS_ipd : std_logic_vector(0 to 9); + signal DCRPPCDSDBUSOUT_ipd : std_logic_vector(0 to 31); + signal DCRPPCDSREAD_ipd : std_ulogic; + signal DCRPPCDSWRITE_ipd : std_ulogic; + signal EICC440CRITIRQ_ipd : std_ulogic; + signal EICC440EXTIRQ_ipd : std_ulogic; + signal FCMAPUCONFIRMINSTR_ipd : std_ulogic; + signal FCMAPUCR_ipd : std_logic_vector(0 to 3); + signal FCMAPUDONE_ipd : std_ulogic; + signal FCMAPUEXCEPTION_ipd : std_ulogic; + signal FCMAPUFPSCRFEX_ipd : std_ulogic; + signal FCMAPURESULT_ipd : std_logic_vector(0 to 31); + signal FCMAPURESULTVALID_ipd : std_ulogic; + signal FCMAPUSLEEPNOTREADY_ipd : std_ulogic; + signal FCMAPUSTOREDATA_ipd : std_logic_vector(0 to 127); + signal JTGC440TCK_ipd : std_ulogic; + signal JTGC440TDI_ipd : std_ulogic; + signal JTGC440TMS_ipd : std_ulogic; + signal JTGC440TRSTNEG_ipd : std_ulogic; + signal MCMIADDRREADYTOACCEPT_ipd : std_ulogic; + signal MCMIREADDATA_ipd : std_logic_vector(0 to 127); + signal MCMIREADDATAERR_ipd : std_ulogic; + signal MCMIREADDATAVALID_ipd : std_ulogic; + signal RSTC440RESETCHIP_ipd : std_ulogic; + signal RSTC440RESETCORE_ipd : std_ulogic; + signal RSTC440RESETSYSTEM_ipd : std_ulogic; + signal TIEC440DCURDLDCACHEPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440DCURDNONCACHEPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440DCURDTOUCHPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440DCURDURGENTPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440DCUWRFLUSHPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440DCUWRSTOREPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440DCUWRURGENTPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440ENDIANRESET_ipd : std_ulogic; + signal TIEC440ERPNRESET_ipd : std_logic_vector(0 to 3); + signal TIEC440ICURDFETCHPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440ICURDSPECPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440ICURDTOUCHPLBPRIO_ipd : std_logic_vector(0 to 1); + signal TIEC440PIR_ipd : std_logic_vector(28 to 31); + signal TIEC440PVR_ipd : std_logic_vector(28 to 31); + signal TIEC440USERRESET_ipd : std_logic_vector(0 to 3); + signal TRCC440TRACEDISABLE_ipd : std_ulogic; + signal TRCC440TRIGGEREVENTIN_ipd : std_ulogic; + + + signal PLBPPCS0RNW_indelay : std_ulogic; + signal PLBPPCS1RNW_indelay : std_ulogic; + signal CPMDCRCLK_indelay : std_ulogic; + signal CPMDMA0LLCLK_indelay : std_ulogic; + signal CPMDMA1LLCLK_indelay : std_ulogic; + signal CPMDMA2LLCLK_indelay : std_ulogic; + signal CPMDMA3LLCLK_indelay : std_ulogic; + signal CPMINTERCONNECTCLKNTO1_indelay : std_ulogic; + signal CPMPPCMPLBCLK_indelay : std_ulogic; + signal CPMPPCS0PLBCLK_indelay : std_ulogic; + signal CPMPPCS1PLBCLK_indelay : std_ulogic; + signal DCRPPCDMACK_indelay : std_ulogic; + signal DCRPPCDMDBUSIN_indelay : std_logic_vector(0 to 31); + signal DCRPPCDMTIMEOUTWAIT_indelay : std_ulogic; + signal LLDMA0RSTENGINEREQ_indelay : std_ulogic; + signal LLDMA0RXD_indelay : std_logic_vector(0 to 31); + signal LLDMA0RXEOFN_indelay : std_ulogic; + signal LLDMA0RXEOPN_indelay : std_ulogic; + signal LLDMA0RXREM_indelay : std_logic_vector(0 to 3); + signal LLDMA0RXSOFN_indelay : std_ulogic; + signal LLDMA0RXSOPN_indelay : std_ulogic; + signal LLDMA0RXSRCRDYN_indelay : std_ulogic; + signal LLDMA0TXDSTRDYN_indelay : std_ulogic; + signal LLDMA1RSTENGINEREQ_indelay : std_ulogic; + signal LLDMA1RXD_indelay : std_logic_vector(0 to 31); + signal LLDMA1RXEOFN_indelay : std_ulogic; + signal LLDMA1RXEOPN_indelay : std_ulogic; + signal LLDMA1RXREM_indelay : std_logic_vector(0 to 3); + signal LLDMA1RXSOFN_indelay : std_ulogic; + signal LLDMA1RXSOPN_indelay : std_ulogic; + signal LLDMA1RXSRCRDYN_indelay : std_ulogic; + signal LLDMA1TXDSTRDYN_indelay : std_ulogic; + signal LLDMA2RSTENGINEREQ_indelay : std_ulogic; + signal LLDMA2RXD_indelay : std_logic_vector(0 to 31); + signal LLDMA2RXEOFN_indelay : std_ulogic; + signal LLDMA2RXEOPN_indelay : std_ulogic; + signal LLDMA2RXREM_indelay : std_logic_vector(0 to 3); + signal LLDMA2RXSOFN_indelay : std_ulogic; + signal LLDMA2RXSOPN_indelay : std_ulogic; + signal LLDMA2RXSRCRDYN_indelay : std_ulogic; + signal LLDMA2TXDSTRDYN_indelay : std_ulogic; + signal LLDMA3RSTENGINEREQ_indelay : std_ulogic; + signal LLDMA3RXD_indelay : std_logic_vector(0 to 31); + signal LLDMA3RXEOFN_indelay : std_ulogic; + signal LLDMA3RXEOPN_indelay : std_ulogic; + signal LLDMA3RXREM_indelay : std_logic_vector(0 to 3); + signal LLDMA3RXSOFN_indelay : std_ulogic; + signal LLDMA3RXSOPN_indelay : std_ulogic; + signal LLDMA3RXSRCRDYN_indelay : std_ulogic; + signal LLDMA3TXDSTRDYN_indelay : std_ulogic; + signal PLBPPCMADDRACK_indelay : std_ulogic; + signal PLBPPCMMBUSY_indelay : std_ulogic; + signal PLBPPCMMIRQ_indelay : std_ulogic; + signal PLBPPCMMRDERR_indelay : std_ulogic; + signal PLBPPCMMWRERR_indelay : std_ulogic; + signal PLBPPCMRDBTERM_indelay : std_ulogic; + signal PLBPPCMRDDACK_indelay : std_ulogic; + signal PLBPPCMRDDBUS_indelay : std_logic_vector(0 to 127); + signal PLBPPCMRDPENDPRI_indelay : std_logic_vector(0 to 1); + signal PLBPPCMRDPENDREQ_indelay : std_ulogic; + signal PLBPPCMRDWDADDR_indelay : std_logic_vector(0 to 3); + signal PLBPPCMREARBITRATE_indelay : std_ulogic; + signal PLBPPCMREQPRI_indelay : std_logic_vector(0 to 1); + signal PLBPPCMSSIZE_indelay : std_logic_vector(0 to 1); + signal PLBPPCMTIMEOUT_indelay : std_ulogic; + signal PLBPPCMWRBTERM_indelay : std_ulogic; + signal PLBPPCMWRDACK_indelay : std_ulogic; + signal PLBPPCMWRPENDPRI_indelay : std_logic_vector(0 to 1); + signal PLBPPCMWRPENDREQ_indelay : std_ulogic; + signal PLBPPCS0ABORT_indelay : std_ulogic; + signal PLBPPCS0ABUS_indelay : std_logic_vector(0 to 31); + signal PLBPPCS0BE_indelay : std_logic_vector(0 to 15); + signal PLBPPCS0BUSLOCK_indelay : std_ulogic; + signal PLBPPCS0LOCKERR_indelay : std_ulogic; + signal PLBPPCS0MASTERID_indelay : std_logic_vector(0 to 1); + signal PLBPPCS0MSIZE_indelay : std_logic_vector(0 to 1); + signal PLBPPCS0PAVALID_indelay : std_ulogic; + signal PLBPPCS0RDBURST_indelay : std_ulogic; + signal PLBPPCS0RDPENDPRI_indelay : std_logic_vector(0 to 1); + signal PLBPPCS0RDPENDREQ_indelay : std_ulogic; + signal PLBPPCS0RDPRIM_indelay : std_ulogic; + signal PLBPPCS0REQPRI_indelay : std_logic_vector(0 to 1); + signal PLBPPCS0SAVALID_indelay : std_ulogic; + signal PLBPPCS0SIZE_indelay : std_logic_vector(0 to 3); + signal PLBPPCS0TATTRIBUTE_indelay : std_logic_vector(0 to 15); + signal PLBPPCS0TYPE_indelay : std_logic_vector(0 to 2); + signal PLBPPCS0UABUS_indelay : std_logic_vector(28 to 31); + signal PLBPPCS0WRBURST_indelay : std_ulogic; + signal PLBPPCS0WRDBUS_indelay : std_logic_vector(0 to 127); + signal PLBPPCS0WRPENDPRI_indelay : std_logic_vector(0 to 1); + signal PLBPPCS0WRPENDREQ_indelay : std_ulogic; + signal PLBPPCS0WRPRIM_indelay : std_ulogic; + signal PLBPPCS1ABORT_indelay : std_ulogic; + signal PLBPPCS1ABUS_indelay : std_logic_vector(0 to 31); + signal PLBPPCS1BE_indelay : std_logic_vector(0 to 15); + signal PLBPPCS1BUSLOCK_indelay : std_ulogic; + signal PLBPPCS1LOCKERR_indelay : std_ulogic; + signal PLBPPCS1MASTERID_indelay : std_logic_vector(0 to 1); + signal PLBPPCS1MSIZE_indelay : std_logic_vector(0 to 1); + signal PLBPPCS1PAVALID_indelay : std_ulogic; + signal PLBPPCS1RDBURST_indelay : std_ulogic; + signal PLBPPCS1RDPENDPRI_indelay : std_logic_vector(0 to 1); + signal PLBPPCS1RDPENDREQ_indelay : std_ulogic; + signal PLBPPCS1RDPRIM_indelay : std_ulogic; + signal PLBPPCS1REQPRI_indelay : std_logic_vector(0 to 1); + signal PLBPPCS1SAVALID_indelay : std_ulogic; + signal PLBPPCS1SIZE_indelay : std_logic_vector(0 to 3); + signal PLBPPCS1TATTRIBUTE_indelay : std_logic_vector(0 to 15); + signal PLBPPCS1TYPE_indelay : std_logic_vector(0 to 2); + signal PLBPPCS1UABUS_indelay : std_logic_vector(28 to 31); + signal PLBPPCS1WRBURST_indelay : std_ulogic; + signal PLBPPCS1WRDBUS_indelay : std_logic_vector(0 to 127); + signal PLBPPCS1WRPENDPRI_indelay : std_logic_vector(0 to 1); + signal PLBPPCS1WRPENDREQ_indelay : std_ulogic; + signal PLBPPCS1WRPRIM_indelay : std_ulogic; + signal TIEDCRBASEADDR_indelay : std_logic_vector(0 to 1); + signal CPMC440CLK_indelay : std_ulogic; + signal CPMC440CLKEN_indelay : std_ulogic; + signal CPMC440CORECLOCKINACTIVE_indelay : std_ulogic; + signal CPMC440TIMERCLOCK_indelay : std_ulogic; + signal CPMFCMCLK_indelay : std_ulogic; + signal CPMINTERCONNECTCLK_indelay : std_ulogic; + signal CPMINTERCONNECTCLKEN_indelay : std_ulogic; + signal CPMMCCLK_indelay : std_ulogic; + signal DBGC440DEBUGHALT_indelay : std_ulogic; + signal DBGC440SYSTEMSTATUS_indelay : std_logic_vector(0 to 4); + signal DBGC440UNCONDDEBUGEVENT_indelay : std_ulogic; + signal DCRPPCDSABUS_indelay : std_logic_vector(0 to 9); + signal DCRPPCDSDBUSOUT_indelay : std_logic_vector(0 to 31); + signal DCRPPCDSREAD_indelay : std_ulogic; + signal DCRPPCDSWRITE_indelay : std_ulogic; + signal EICC440CRITIRQ_indelay : std_ulogic; + signal EICC440EXTIRQ_indelay : std_ulogic; + signal FCMAPUCONFIRMINSTR_indelay : std_ulogic; + signal FCMAPUCR_indelay : std_logic_vector(0 to 3); + signal FCMAPUDONE_indelay : std_ulogic; + signal FCMAPUEXCEPTION_indelay : std_ulogic; + signal FCMAPUFPSCRFEX_indelay : std_ulogic; + signal FCMAPURESULT_indelay : std_logic_vector(0 to 31); + signal FCMAPURESULTVALID_indelay : std_ulogic; + signal FCMAPUSLEEPNOTREADY_indelay : std_ulogic; + signal FCMAPUSTOREDATA_indelay : std_logic_vector(0 to 127); + signal JTGC440TCK_indelay : std_ulogic; + signal JTGC440TDI_indelay : std_ulogic; + signal JTGC440TMS_indelay : std_ulogic; + signal JTGC440TRSTNEG_indelay : std_ulogic; + signal MCMIADDRREADYTOACCEPT_indelay : std_ulogic; + signal MCMIREADDATA_indelay : std_logic_vector(0 to 127); + signal MCMIREADDATAERR_indelay : std_ulogic; + signal MCMIREADDATAVALID_indelay : std_ulogic; + signal RSTC440RESETCHIP_indelay : std_ulogic; + signal RSTC440RESETCORE_indelay : std_ulogic; + signal RSTC440RESETSYSTEM_indelay : std_ulogic; + signal TIEC440DCURDLDCACHEPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440DCURDNONCACHEPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440DCURDTOUCHPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440DCURDURGENTPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440DCUWRFLUSHPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440DCUWRSTOREPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440DCUWRURGENTPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440ENDIANRESET_indelay : std_ulogic; + signal TIEC440ERPNRESET_indelay : std_logic_vector(0 to 3); + signal TIEC440ICURDFETCHPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440ICURDSPECPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440ICURDTOUCHPLBPRIO_indelay : std_logic_vector(0 to 1); + signal TIEC440PIR_indelay : std_logic_vector(28 to 31); + signal TIEC440PVR_indelay : std_logic_vector(28 to 31); + signal TIEC440USERRESET_indelay : std_logic_vector(0 to 3); + signal TRCC440TRACEDISABLE_indelay : std_ulogic; + signal TRCC440TRIGGEREVENTIN_indelay : std_ulogic; + +begin + + + APUFCMDECFPUOP_out <= APUFCMDECFPUOP_outdelay after OUT_DELAY; + APUFCMDECLDSTXFERSIZE_out <= APUFCMDECLDSTXFERSIZE_outdelay after OUT_DELAY; + APUFCMDECLOAD_out <= APUFCMDECLOAD_outdelay after OUT_DELAY; + APUFCMDECNONAUTON_out <= APUFCMDECNONAUTON_outdelay after OUT_DELAY; + APUFCMDECSTORE_out <= APUFCMDECSTORE_outdelay after OUT_DELAY; + APUFCMDECUDIVALID_out <= APUFCMDECUDIVALID_outdelay after OUT_DELAY; + APUFCMDECUDI_out <= APUFCMDECUDI_outdelay after OUT_DELAY; + APUFCMENDIAN_out <= APUFCMENDIAN_outdelay after OUT_DELAY; + APUFCMFLUSH_out <= APUFCMFLUSH_outdelay after OUT_DELAY; + APUFCMINSTRUCTION_out <= APUFCMINSTRUCTION_outdelay after OUT_DELAY; + APUFCMINSTRVALID_out <= APUFCMINSTRVALID_outdelay after OUT_DELAY; + APUFCMLOADBYTEADDR_out <= APUFCMLOADBYTEADDR_outdelay after OUT_DELAY; + APUFCMLOADDATA_out <= APUFCMLOADDATA_outdelay after OUT_DELAY; + APUFCMLOADDVALID_out <= APUFCMLOADDVALID_outdelay after OUT_DELAY; + APUFCMMSRFE0_out <= APUFCMMSRFE0_outdelay after OUT_DELAY; + APUFCMMSRFE1_out <= APUFCMMSRFE1_outdelay after OUT_DELAY; + APUFCMNEXTINSTRREADY_out <= APUFCMNEXTINSTRREADY_outdelay after OUT_DELAY; + APUFCMOPERANDVALID_out <= APUFCMOPERANDVALID_outdelay after OUT_DELAY; + APUFCMRADATA_out <= APUFCMRADATA_outdelay after OUT_DELAY; + APUFCMRBDATA_out <= APUFCMRBDATA_outdelay after OUT_DELAY; + APUFCMWRITEBACKOK_out <= APUFCMWRITEBACKOK_outdelay after OUT_DELAY; + C440CPMCORESLEEPREQ_out <= C440CPMCORESLEEPREQ_outdelay after OUT_DELAY; + C440CPMDECIRPTREQ_out <= C440CPMDECIRPTREQ_outdelay after OUT_DELAY; + C440CPMFITIRPTREQ_out <= C440CPMFITIRPTREQ_outdelay after OUT_DELAY; + C440CPMMSRCE_out <= C440CPMMSRCE_outdelay after OUT_DELAY; + C440CPMMSREE_out <= C440CPMMSREE_outdelay after OUT_DELAY; + C440CPMTIMERRESETREQ_out <= C440CPMTIMERRESETREQ_outdelay after OUT_DELAY; + C440CPMWDIRPTREQ_out <= C440CPMWDIRPTREQ_outdelay after OUT_DELAY; + C440DBGSYSTEMCONTROL_out <= C440DBGSYSTEMCONTROL_outdelay after OUT_DELAY; + C440JTGTDOEN_out <= C440JTGTDOEN_outdelay after OUT_DELAY; + C440JTGTDO_out <= C440JTGTDO_outdelay after OUT_DELAY; + C440MACHINECHECK_out <= C440MACHINECHECK_outdelay after OUT_DELAY; + C440RSTCHIPRESETREQ_out <= C440RSTCHIPRESETREQ_outdelay after OUT_DELAY; + C440RSTCORERESETREQ_out <= C440RSTCORERESETREQ_outdelay after OUT_DELAY; + C440RSTSYSTEMRESETREQ_out <= C440RSTSYSTEMRESETREQ_outdelay after OUT_DELAY; + C440TRCBRANCHSTATUS_out <= C440TRCBRANCHSTATUS_outdelay after OUT_DELAY; + C440TRCCYCLE_out <= C440TRCCYCLE_outdelay after OUT_DELAY; + C440TRCEXECUTIONSTATUS_out <= C440TRCEXECUTIONSTATUS_outdelay after OUT_DELAY; + C440TRCTRACESTATUS_out <= C440TRCTRACESTATUS_outdelay after OUT_DELAY; + C440TRCTRIGGEREVENTOUT_out <= C440TRCTRIGGEREVENTOUT_outdelay after OUT_DELAY; + C440TRCTRIGGEREVENTTYPE_out <= C440TRCTRIGGEREVENTTYPE_outdelay after OUT_DELAY; + DMA0LLRSTENGINEACK_out <= DMA0LLRSTENGINEACK_outdelay after OUT_DELAY; + DMA0LLRXDSTRDYN_out <= DMA0LLRXDSTRDYN_outdelay after OUT_DELAY; + DMA0LLTXD_out <= DMA0LLTXD_outdelay after OUT_DELAY; + DMA0LLTXEOFN_out <= DMA0LLTXEOFN_outdelay after OUT_DELAY; + DMA0LLTXEOPN_out <= DMA0LLTXEOPN_outdelay after OUT_DELAY; + DMA0LLTXREM_out <= DMA0LLTXREM_outdelay after OUT_DELAY; + DMA0LLTXSOFN_out <= DMA0LLTXSOFN_outdelay after OUT_DELAY; + DMA0LLTXSOPN_out <= DMA0LLTXSOPN_outdelay after OUT_DELAY; + DMA0LLTXSRCRDYN_out <= DMA0LLTXSRCRDYN_outdelay after OUT_DELAY; + DMA0RXIRQ_out <= DMA0RXIRQ_outdelay after OUT_DELAY; + DMA0TXIRQ_out <= DMA0TXIRQ_outdelay after OUT_DELAY; + DMA1LLRSTENGINEACK_out <= DMA1LLRSTENGINEACK_outdelay after OUT_DELAY; + DMA1LLRXDSTRDYN_out <= DMA1LLRXDSTRDYN_outdelay after OUT_DELAY; + DMA1LLTXD_out <= DMA1LLTXD_outdelay after OUT_DELAY; + DMA1LLTXEOFN_out <= DMA1LLTXEOFN_outdelay after OUT_DELAY; + DMA1LLTXEOPN_out <= DMA1LLTXEOPN_outdelay after OUT_DELAY; + DMA1LLTXREM_out <= DMA1LLTXREM_outdelay after OUT_DELAY; + DMA1LLTXSOFN_out <= DMA1LLTXSOFN_outdelay after OUT_DELAY; + DMA1LLTXSOPN_out <= DMA1LLTXSOPN_outdelay after OUT_DELAY; + DMA1LLTXSRCRDYN_out <= DMA1LLTXSRCRDYN_outdelay after OUT_DELAY; + DMA1RXIRQ_out <= DMA1RXIRQ_outdelay after OUT_DELAY; + DMA1TXIRQ_out <= DMA1TXIRQ_outdelay after OUT_DELAY; + DMA2LLRSTENGINEACK_out <= DMA2LLRSTENGINEACK_outdelay after OUT_DELAY; + DMA2LLRXDSTRDYN_out <= DMA2LLRXDSTRDYN_outdelay after OUT_DELAY; + DMA2LLTXD_out <= DMA2LLTXD_outdelay after OUT_DELAY; + DMA2LLTXEOFN_out <= DMA2LLTXEOFN_outdelay after OUT_DELAY; + DMA2LLTXEOPN_out <= DMA2LLTXEOPN_outdelay after OUT_DELAY; + DMA2LLTXREM_out <= DMA2LLTXREM_outdelay after OUT_DELAY; + DMA2LLTXSOFN_out <= DMA2LLTXSOFN_outdelay after OUT_DELAY; + DMA2LLTXSOPN_out <= DMA2LLTXSOPN_outdelay after OUT_DELAY; + DMA2LLTXSRCRDYN_out <= DMA2LLTXSRCRDYN_outdelay after OUT_DELAY; + DMA2RXIRQ_out <= DMA2RXIRQ_outdelay after OUT_DELAY; + DMA2TXIRQ_out <= DMA2TXIRQ_outdelay after OUT_DELAY; + DMA3LLRSTENGINEACK_out <= DMA3LLRSTENGINEACK_outdelay after OUT_DELAY; + DMA3LLRXDSTRDYN_out <= DMA3LLRXDSTRDYN_outdelay after OUT_DELAY; + DMA3LLTXD_out <= DMA3LLTXD_outdelay after OUT_DELAY; + DMA3LLTXEOFN_out <= DMA3LLTXEOFN_outdelay after OUT_DELAY; + DMA3LLTXEOPN_out <= DMA3LLTXEOPN_outdelay after OUT_DELAY; + DMA3LLTXREM_out <= DMA3LLTXREM_outdelay after OUT_DELAY; + DMA3LLTXSOFN_out <= DMA3LLTXSOFN_outdelay after OUT_DELAY; + DMA3LLTXSOPN_out <= DMA3LLTXSOPN_outdelay after OUT_DELAY; + DMA3LLTXSRCRDYN_out <= DMA3LLTXSRCRDYN_outdelay after OUT_DELAY; + DMA3RXIRQ_out <= DMA3RXIRQ_outdelay after OUT_DELAY; + DMA3TXIRQ_out <= DMA3TXIRQ_outdelay after OUT_DELAY; + MIMCADDRESSVALID_out <= MIMCADDRESSVALID_outdelay after OUT_DELAY; + MIMCADDRESS_out <= MIMCADDRESS_outdelay after OUT_DELAY; + MIMCBANKCONFLICT_out <= MIMCBANKCONFLICT_outdelay after OUT_DELAY; + MIMCBYTEENABLE_out <= MIMCBYTEENABLE_outdelay after OUT_DELAY; + MIMCREADNOTWRITE_out <= MIMCREADNOTWRITE_outdelay after OUT_DELAY; + MIMCROWCONFLICT_out <= MIMCROWCONFLICT_outdelay after OUT_DELAY; + MIMCWRITEDATAVALID_out <= MIMCWRITEDATAVALID_outdelay after OUT_DELAY; + MIMCWRITEDATA_out <= MIMCWRITEDATA_outdelay after OUT_DELAY; + PPCCPMINTERCONNECTBUSY_out <= PPCCPMINTERCONNECTBUSY_outdelay after OUT_DELAY; + PPCDMDCRABUS_out <= PPCDMDCRABUS_outdelay after OUT_DELAY; + PPCDMDCRDBUSOUT_out <= PPCDMDCRDBUSOUT_outdelay after OUT_DELAY; + PPCDMDCRREAD_out <= PPCDMDCRREAD_outdelay after OUT_DELAY; + PPCDMDCRUABUS_out <= PPCDMDCRUABUS_outdelay after OUT_DELAY; + PPCDMDCRWRITE_out <= PPCDMDCRWRITE_outdelay after OUT_DELAY; + PPCDSDCRACK_out <= PPCDSDCRACK_outdelay after OUT_DELAY; + PPCDSDCRDBUSIN_out <= PPCDSDCRDBUSIN_outdelay after OUT_DELAY; + PPCDSDCRTIMEOUTWAIT_out <= PPCDSDCRTIMEOUTWAIT_outdelay after OUT_DELAY; + PPCEICINTERCONNECTIRQ_out <= PPCEICINTERCONNECTIRQ_outdelay after OUT_DELAY; + PPCMPLBABORT_out <= PPCMPLBABORT_outdelay after OUT_DELAY; + PPCMPLBABUS_out <= PPCMPLBABUS_outdelay after OUT_DELAY; + PPCMPLBBE_out <= PPCMPLBBE_outdelay after OUT_DELAY; + PPCMPLBBUSLOCK_out <= PPCMPLBBUSLOCK_outdelay after OUT_DELAY; + PPCMPLBLOCKERR_out <= PPCMPLBLOCKERR_outdelay after OUT_DELAY; + PPCMPLBPRIORITY_out <= PPCMPLBPRIORITY_outdelay after OUT_DELAY; + PPCMPLBRDBURST_out <= PPCMPLBRDBURST_outdelay after OUT_DELAY; + PPCMPLBREQUEST_out <= PPCMPLBREQUEST_outdelay after OUT_DELAY; + PPCMPLBRNW_out <= PPCMPLBRNW_outdelay after OUT_DELAY; + PPCMPLBSIZE_out <= PPCMPLBSIZE_outdelay after OUT_DELAY; + PPCMPLBTATTRIBUTE_out <= PPCMPLBTATTRIBUTE_outdelay after OUT_DELAY; + PPCMPLBTYPE_out <= PPCMPLBTYPE_outdelay after OUT_DELAY; + PPCMPLBUABUS_out <= PPCMPLBUABUS_outdelay after OUT_DELAY; + PPCMPLBWRBURST_out <= PPCMPLBWRBURST_outdelay after OUT_DELAY; + PPCMPLBWRDBUS_out <= PPCMPLBWRDBUS_outdelay after OUT_DELAY; + PPCS0PLBADDRACK_out <= PPCS0PLBADDRACK_outdelay after OUT_DELAY; + PPCS0PLBMBUSY_out <= PPCS0PLBMBUSY_outdelay after OUT_DELAY; + PPCS0PLBMIRQ_out <= PPCS0PLBMIRQ_outdelay after OUT_DELAY; + PPCS0PLBMRDERR_out <= PPCS0PLBMRDERR_outdelay after OUT_DELAY; + PPCS0PLBMWRERR_out <= PPCS0PLBMWRERR_outdelay after OUT_DELAY; + PPCS0PLBRDBTERM_out <= PPCS0PLBRDBTERM_outdelay after OUT_DELAY; + PPCS0PLBRDCOMP_out <= PPCS0PLBRDCOMP_outdelay after OUT_DELAY; + PPCS0PLBRDDACK_out <= PPCS0PLBRDDACK_outdelay after OUT_DELAY; + PPCS0PLBRDDBUS_out <= PPCS0PLBRDDBUS_outdelay after OUT_DELAY; + PPCS0PLBRDWDADDR_out <= PPCS0PLBRDWDADDR_outdelay after OUT_DELAY; + PPCS0PLBREARBITRATE_out <= PPCS0PLBREARBITRATE_outdelay after OUT_DELAY; + PPCS0PLBSSIZE_out <= PPCS0PLBSSIZE_outdelay after OUT_DELAY; + PPCS0PLBWAIT_out <= PPCS0PLBWAIT_outdelay after OUT_DELAY; + PPCS0PLBWRBTERM_out <= PPCS0PLBWRBTERM_outdelay after OUT_DELAY; + PPCS0PLBWRCOMP_out <= PPCS0PLBWRCOMP_outdelay after OUT_DELAY; + PPCS0PLBWRDACK_out <= PPCS0PLBWRDACK_outdelay after OUT_DELAY; + PPCS1PLBADDRACK_out <= PPCS1PLBADDRACK_outdelay after OUT_DELAY; + PPCS1PLBMBUSY_out <= PPCS1PLBMBUSY_outdelay after OUT_DELAY; + PPCS1PLBMIRQ_out <= PPCS1PLBMIRQ_outdelay after OUT_DELAY; + PPCS1PLBMRDERR_out <= PPCS1PLBMRDERR_outdelay after OUT_DELAY; + PPCS1PLBMWRERR_out <= PPCS1PLBMWRERR_outdelay after OUT_DELAY; + PPCS1PLBRDBTERM_out <= PPCS1PLBRDBTERM_outdelay after OUT_DELAY; + PPCS1PLBRDCOMP_out <= PPCS1PLBRDCOMP_outdelay after OUT_DELAY; + PPCS1PLBRDDACK_out <= PPCS1PLBRDDACK_outdelay after OUT_DELAY; + PPCS1PLBRDDBUS_out <= PPCS1PLBRDDBUS_outdelay after OUT_DELAY; + PPCS1PLBRDWDADDR_out <= PPCS1PLBRDWDADDR_outdelay after OUT_DELAY; + PPCS1PLBREARBITRATE_out <= PPCS1PLBREARBITRATE_outdelay after OUT_DELAY; + PPCS1PLBSSIZE_out <= PPCS1PLBSSIZE_outdelay after OUT_DELAY; + PPCS1PLBWAIT_out <= PPCS1PLBWAIT_outdelay after OUT_DELAY; + PPCS1PLBWRBTERM_out <= PPCS1PLBWRBTERM_outdelay after OUT_DELAY; + PPCS1PLBWRCOMP_out <= PPCS1PLBWRCOMP_outdelay after OUT_DELAY; + PPCS1PLBWRDACK_out <= PPCS1PLBWRDACK_outdelay after OUT_DELAY; + + CPMC440CLK_ipd <= CPMC440CLK after ZERO_DELAY; + CPMC440TIMERCLOCK_ipd <= CPMC440TIMERCLOCK after ZERO_DELAY; + CPMDCRCLK_ipd <= CPMDCRCLK after ZERO_DELAY; + CPMDMA0LLCLK_ipd <= CPMDMA0LLCLK after ZERO_DELAY; + CPMDMA1LLCLK_ipd <= CPMDMA1LLCLK after ZERO_DELAY; + CPMDMA2LLCLK_ipd <= CPMDMA2LLCLK after ZERO_DELAY; + CPMDMA3LLCLK_ipd <= CPMDMA3LLCLK after ZERO_DELAY; + CPMFCMCLK_ipd <= CPMFCMCLK after ZERO_DELAY; + CPMINTERCONNECTCLK_ipd <= CPMINTERCONNECTCLK after ZERO_DELAY; + CPMMCCLK_ipd <= CPMMCCLK after ZERO_DELAY; + CPMPPCMPLBCLK_ipd <= CPMPPCMPLBCLK after ZERO_DELAY; + CPMPPCS0PLBCLK_ipd <= CPMPPCS0PLBCLK after ZERO_DELAY; + CPMPPCS1PLBCLK_ipd <= CPMPPCS1PLBCLK after ZERO_DELAY; + JTGC440TCK_ipd <= JTGC440TCK after ZERO_DELAY; + + CPMC440CLKEN_ipd <= CPMC440CLKEN after ZERO_DELAY; + CPMC440CORECLOCKINACTIVE_ipd <= CPMC440CORECLOCKINACTIVE after ZERO_DELAY; + CPMINTERCONNECTCLKEN_ipd <= CPMINTERCONNECTCLKEN after ZERO_DELAY; + CPMINTERCONNECTCLKNTO1_ipd <= CPMINTERCONNECTCLKNTO1 after ZERO_DELAY; + DBGC440DEBUGHALT_ipd <= DBGC440DEBUGHALT after ZERO_DELAY; + DBGC440SYSTEMSTATUS_ipd <= DBGC440SYSTEMSTATUS after ZERO_DELAY; + DBGC440UNCONDDEBUGEVENT_ipd <= DBGC440UNCONDDEBUGEVENT after ZERO_DELAY; + DCRPPCDMACK_ipd <= DCRPPCDMACK after ZERO_DELAY; + DCRPPCDMDBUSIN_ipd <= DCRPPCDMDBUSIN after ZERO_DELAY; + DCRPPCDMTIMEOUTWAIT_ipd <= DCRPPCDMTIMEOUTWAIT after ZERO_DELAY; + DCRPPCDSABUS_ipd <= DCRPPCDSABUS after ZERO_DELAY; + DCRPPCDSDBUSOUT_ipd <= DCRPPCDSDBUSOUT after ZERO_DELAY; + DCRPPCDSREAD_ipd <= DCRPPCDSREAD after ZERO_DELAY; + DCRPPCDSWRITE_ipd <= DCRPPCDSWRITE after ZERO_DELAY; + EICC440CRITIRQ_ipd <= EICC440CRITIRQ after ZERO_DELAY; + EICC440EXTIRQ_ipd <= EICC440EXTIRQ after ZERO_DELAY; + FCMAPUCONFIRMINSTR_ipd <= FCMAPUCONFIRMINSTR after ZERO_DELAY; + FCMAPUCR_ipd <= FCMAPUCR after ZERO_DELAY; + FCMAPUDONE_ipd <= FCMAPUDONE after ZERO_DELAY; + FCMAPUEXCEPTION_ipd <= FCMAPUEXCEPTION after ZERO_DELAY; + FCMAPUFPSCRFEX_ipd <= FCMAPUFPSCRFEX after ZERO_DELAY; + FCMAPURESULTVALID_ipd <= FCMAPURESULTVALID after ZERO_DELAY; + FCMAPURESULT_ipd <= FCMAPURESULT after ZERO_DELAY; + FCMAPUSLEEPNOTREADY_ipd <= FCMAPUSLEEPNOTREADY after ZERO_DELAY; + FCMAPUSTOREDATA_ipd <= FCMAPUSTOREDATA after ZERO_DELAY; + JTGC440TDI_ipd <= JTGC440TDI after ZERO_DELAY; + JTGC440TMS_ipd <= JTGC440TMS after ZERO_DELAY; + JTGC440TRSTNEG_ipd <= JTGC440TRSTNEG after ZERO_DELAY; + LLDMA0RSTENGINEREQ_ipd <= LLDMA0RSTENGINEREQ after ZERO_DELAY; + LLDMA0RXD_ipd <= LLDMA0RXD after ZERO_DELAY; + LLDMA0RXEOFN_ipd <= LLDMA0RXEOFN after ZERO_DELAY; + LLDMA0RXEOPN_ipd <= LLDMA0RXEOPN after ZERO_DELAY; + LLDMA0RXREM_ipd <= LLDMA0RXREM after ZERO_DELAY; + LLDMA0RXSOFN_ipd <= LLDMA0RXSOFN after ZERO_DELAY; + LLDMA0RXSOPN_ipd <= LLDMA0RXSOPN after ZERO_DELAY; + LLDMA0RXSRCRDYN_ipd <= LLDMA0RXSRCRDYN after ZERO_DELAY; + LLDMA0TXDSTRDYN_ipd <= LLDMA0TXDSTRDYN after ZERO_DELAY; + LLDMA1RSTENGINEREQ_ipd <= LLDMA1RSTENGINEREQ after ZERO_DELAY; + LLDMA1RXD_ipd <= LLDMA1RXD after ZERO_DELAY; + LLDMA1RXEOFN_ipd <= LLDMA1RXEOFN after ZERO_DELAY; + LLDMA1RXEOPN_ipd <= LLDMA1RXEOPN after ZERO_DELAY; + LLDMA1RXREM_ipd <= LLDMA1RXREM after ZERO_DELAY; + LLDMA1RXSOFN_ipd <= LLDMA1RXSOFN after ZERO_DELAY; + LLDMA1RXSOPN_ipd <= LLDMA1RXSOPN after ZERO_DELAY; + LLDMA1RXSRCRDYN_ipd <= LLDMA1RXSRCRDYN after ZERO_DELAY; + LLDMA1TXDSTRDYN_ipd <= LLDMA1TXDSTRDYN after ZERO_DELAY; + LLDMA2RSTENGINEREQ_ipd <= LLDMA2RSTENGINEREQ after ZERO_DELAY; + LLDMA2RXD_ipd <= LLDMA2RXD after ZERO_DELAY; + LLDMA2RXEOFN_ipd <= LLDMA2RXEOFN after ZERO_DELAY; + LLDMA2RXEOPN_ipd <= LLDMA2RXEOPN after ZERO_DELAY; + LLDMA2RXREM_ipd <= LLDMA2RXREM after ZERO_DELAY; + LLDMA2RXSOFN_ipd <= LLDMA2RXSOFN after ZERO_DELAY; + LLDMA2RXSOPN_ipd <= LLDMA2RXSOPN after ZERO_DELAY; + LLDMA2RXSRCRDYN_ipd <= LLDMA2RXSRCRDYN after ZERO_DELAY; + LLDMA2TXDSTRDYN_ipd <= LLDMA2TXDSTRDYN after ZERO_DELAY; + LLDMA3RSTENGINEREQ_ipd <= LLDMA3RSTENGINEREQ after ZERO_DELAY; + LLDMA3RXD_ipd <= LLDMA3RXD after ZERO_DELAY; + LLDMA3RXEOFN_ipd <= LLDMA3RXEOFN after ZERO_DELAY; + LLDMA3RXEOPN_ipd <= LLDMA3RXEOPN after ZERO_DELAY; + LLDMA3RXREM_ipd <= LLDMA3RXREM after ZERO_DELAY; + LLDMA3RXSOFN_ipd <= LLDMA3RXSOFN after ZERO_DELAY; + LLDMA3RXSOPN_ipd <= LLDMA3RXSOPN after ZERO_DELAY; + LLDMA3RXSRCRDYN_ipd <= LLDMA3RXSRCRDYN after ZERO_DELAY; + LLDMA3TXDSTRDYN_ipd <= LLDMA3TXDSTRDYN after ZERO_DELAY; + MCMIADDRREADYTOACCEPT_ipd <= MCMIADDRREADYTOACCEPT after ZERO_DELAY; + MCMIREADDATAERR_ipd <= MCMIREADDATAERR after ZERO_DELAY; + MCMIREADDATAVALID_ipd <= MCMIREADDATAVALID after ZERO_DELAY; + MCMIREADDATA_ipd <= MCMIREADDATA after ZERO_DELAY; + PLBPPCMADDRACK_ipd <= PLBPPCMADDRACK after ZERO_DELAY; + PLBPPCMMBUSY_ipd <= PLBPPCMMBUSY after ZERO_DELAY; + PLBPPCMMIRQ_ipd <= PLBPPCMMIRQ after ZERO_DELAY; + PLBPPCMMRDERR_ipd <= PLBPPCMMRDERR after ZERO_DELAY; + PLBPPCMMWRERR_ipd <= PLBPPCMMWRERR after ZERO_DELAY; + PLBPPCMRDBTERM_ipd <= PLBPPCMRDBTERM after ZERO_DELAY; + PLBPPCMRDDACK_ipd <= PLBPPCMRDDACK after ZERO_DELAY; + PLBPPCMRDDBUS_ipd <= PLBPPCMRDDBUS after ZERO_DELAY; + PLBPPCMRDPENDPRI_ipd <= PLBPPCMRDPENDPRI after ZERO_DELAY; + PLBPPCMRDPENDREQ_ipd <= PLBPPCMRDPENDREQ after ZERO_DELAY; + PLBPPCMRDWDADDR_ipd <= PLBPPCMRDWDADDR after ZERO_DELAY; + PLBPPCMREARBITRATE_ipd <= PLBPPCMREARBITRATE after ZERO_DELAY; + PLBPPCMREQPRI_ipd <= PLBPPCMREQPRI after ZERO_DELAY; + PLBPPCMSSIZE_ipd <= PLBPPCMSSIZE after ZERO_DELAY; + PLBPPCMTIMEOUT_ipd <= PLBPPCMTIMEOUT after ZERO_DELAY; + PLBPPCMWRBTERM_ipd <= PLBPPCMWRBTERM after ZERO_DELAY; + PLBPPCMWRDACK_ipd <= PLBPPCMWRDACK after ZERO_DELAY; + PLBPPCMWRPENDPRI_ipd <= PLBPPCMWRPENDPRI after ZERO_DELAY; + PLBPPCMWRPENDREQ_ipd <= PLBPPCMWRPENDREQ after ZERO_DELAY; + PLBPPCS0ABORT_ipd <= PLBPPCS0ABORT after ZERO_DELAY; + PLBPPCS0ABUS_ipd <= PLBPPCS0ABUS after ZERO_DELAY; + PLBPPCS0BE_ipd <= PLBPPCS0BE after ZERO_DELAY; + PLBPPCS0BUSLOCK_ipd <= PLBPPCS0BUSLOCK after ZERO_DELAY; + PLBPPCS0LOCKERR_ipd <= PLBPPCS0LOCKERR after ZERO_DELAY; + PLBPPCS0MASTERID_ipd <= PLBPPCS0MASTERID after ZERO_DELAY; + PLBPPCS0MSIZE_ipd <= PLBPPCS0MSIZE after ZERO_DELAY; + PLBPPCS0PAVALID_ipd <= PLBPPCS0PAVALID after ZERO_DELAY; + PLBPPCS0RDBURST_ipd <= PLBPPCS0RDBURST after ZERO_DELAY; + PLBPPCS0RDPENDPRI_ipd <= PLBPPCS0RDPENDPRI after ZERO_DELAY; + PLBPPCS0RDPENDREQ_ipd <= PLBPPCS0RDPENDREQ after ZERO_DELAY; + PLBPPCS0RDPRIM_ipd <= PLBPPCS0RDPRIM after ZERO_DELAY; + PLBPPCS0REQPRI_ipd <= PLBPPCS0REQPRI after ZERO_DELAY; + PLBPPCS0RNW_ipd <= PLBPPCS0RNW after ZERO_DELAY; + PLBPPCS0SAVALID_ipd <= PLBPPCS0SAVALID after ZERO_DELAY; + PLBPPCS0SIZE_ipd <= PLBPPCS0SIZE after ZERO_DELAY; + PLBPPCS0TATTRIBUTE_ipd <= PLBPPCS0TATTRIBUTE after ZERO_DELAY; + PLBPPCS0TYPE_ipd <= PLBPPCS0TYPE after ZERO_DELAY; + PLBPPCS0UABUS_ipd <= PLBPPCS0UABUS after ZERO_DELAY; + PLBPPCS0WRBURST_ipd <= PLBPPCS0WRBURST after ZERO_DELAY; + PLBPPCS0WRDBUS_ipd <= PLBPPCS0WRDBUS after ZERO_DELAY; + PLBPPCS0WRPENDPRI_ipd <= PLBPPCS0WRPENDPRI after ZERO_DELAY; + PLBPPCS0WRPENDREQ_ipd <= PLBPPCS0WRPENDREQ after ZERO_DELAY; + PLBPPCS0WRPRIM_ipd <= PLBPPCS0WRPRIM after ZERO_DELAY; + PLBPPCS1ABORT_ipd <= PLBPPCS1ABORT after ZERO_DELAY; + PLBPPCS1ABUS_ipd <= PLBPPCS1ABUS after ZERO_DELAY; + PLBPPCS1BE_ipd <= PLBPPCS1BE after ZERO_DELAY; + PLBPPCS1BUSLOCK_ipd <= PLBPPCS1BUSLOCK after ZERO_DELAY; + PLBPPCS1LOCKERR_ipd <= PLBPPCS1LOCKERR after ZERO_DELAY; + PLBPPCS1MASTERID_ipd <= PLBPPCS1MASTERID after ZERO_DELAY; + PLBPPCS1MSIZE_ipd <= PLBPPCS1MSIZE after ZERO_DELAY; + PLBPPCS1PAVALID_ipd <= PLBPPCS1PAVALID after ZERO_DELAY; + PLBPPCS1RDBURST_ipd <= PLBPPCS1RDBURST after ZERO_DELAY; + PLBPPCS1RDPENDPRI_ipd <= PLBPPCS1RDPENDPRI after ZERO_DELAY; + PLBPPCS1RDPENDREQ_ipd <= PLBPPCS1RDPENDREQ after ZERO_DELAY; + PLBPPCS1RDPRIM_ipd <= PLBPPCS1RDPRIM after ZERO_DELAY; + PLBPPCS1REQPRI_ipd <= PLBPPCS1REQPRI after ZERO_DELAY; + PLBPPCS1RNW_ipd <= PLBPPCS1RNW after ZERO_DELAY; + PLBPPCS1SAVALID_ipd <= PLBPPCS1SAVALID after ZERO_DELAY; + PLBPPCS1SIZE_ipd <= PLBPPCS1SIZE after ZERO_DELAY; + PLBPPCS1TATTRIBUTE_ipd <= PLBPPCS1TATTRIBUTE after ZERO_DELAY; + PLBPPCS1TYPE_ipd <= PLBPPCS1TYPE after ZERO_DELAY; + PLBPPCS1UABUS_ipd <= PLBPPCS1UABUS after ZERO_DELAY; + PLBPPCS1WRBURST_ipd <= PLBPPCS1WRBURST after ZERO_DELAY; + PLBPPCS1WRDBUS_ipd <= PLBPPCS1WRDBUS after ZERO_DELAY; + PLBPPCS1WRPENDPRI_ipd <= PLBPPCS1WRPENDPRI after ZERO_DELAY; + PLBPPCS1WRPENDREQ_ipd <= PLBPPCS1WRPENDREQ after ZERO_DELAY; + PLBPPCS1WRPRIM_ipd <= PLBPPCS1WRPRIM after ZERO_DELAY; + RSTC440RESETCHIP_ipd <= RSTC440RESETCHIP after ZERO_DELAY; + RSTC440RESETCORE_ipd <= RSTC440RESETCORE after ZERO_DELAY; + RSTC440RESETSYSTEM_ipd <= RSTC440RESETSYSTEM after ZERO_DELAY; + TIEC440DCURDLDCACHEPLBPRIO_ipd <= TIEC440DCURDLDCACHEPLBPRIO after ZERO_DELAY; + TIEC440DCURDNONCACHEPLBPRIO_ipd <= TIEC440DCURDNONCACHEPLBPRIO after ZERO_DELAY; + TIEC440DCURDTOUCHPLBPRIO_ipd <= TIEC440DCURDTOUCHPLBPRIO after ZERO_DELAY; + TIEC440DCURDURGENTPLBPRIO_ipd <= TIEC440DCURDURGENTPLBPRIO after ZERO_DELAY; + TIEC440DCUWRFLUSHPLBPRIO_ipd <= TIEC440DCUWRFLUSHPLBPRIO after ZERO_DELAY; + TIEC440DCUWRSTOREPLBPRIO_ipd <= TIEC440DCUWRSTOREPLBPRIO after ZERO_DELAY; + TIEC440DCUWRURGENTPLBPRIO_ipd <= TIEC440DCUWRURGENTPLBPRIO after ZERO_DELAY; + TIEC440ENDIANRESET_ipd <= TIEC440ENDIANRESET after ZERO_DELAY; + TIEC440ERPNRESET_ipd <= TIEC440ERPNRESET after ZERO_DELAY; + TIEC440ICURDFETCHPLBPRIO_ipd <= TIEC440ICURDFETCHPLBPRIO after ZERO_DELAY; + TIEC440ICURDSPECPLBPRIO_ipd <= TIEC440ICURDSPECPLBPRIO after ZERO_DELAY; + TIEC440ICURDTOUCHPLBPRIO_ipd <= TIEC440ICURDTOUCHPLBPRIO after ZERO_DELAY; + TIEC440PIR_ipd <= TIEC440PIR after ZERO_DELAY; + TIEC440PVR_ipd <= TIEC440PVR after ZERO_DELAY; + TIEC440USERRESET_ipd <= TIEC440USERRESET after ZERO_DELAY; + TIEDCRBASEADDR_ipd <= TIEDCRBASEADDR after ZERO_DELAY; + TRCC440TRACEDISABLE_ipd <= TRCC440TRACEDISABLE after ZERO_DELAY; + TRCC440TRIGGEREVENTIN_ipd <= TRCC440TRIGGEREVENTIN after ZERO_DELAY; + + + CPMC440CLK_indelay <= CPMC440CLK_ipd after CLK_DELAY; + CPMC440TIMERCLOCK_indelay <= CPMC440TIMERCLOCK_ipd after CLK_DELAY; + CPMDCRCLK_indelay <= CPMDCRCLK_ipd after CLK_DELAY; + CPMDMA0LLCLK_indelay <= CPMDMA0LLCLK_ipd after CLK_DELAY; + CPMDMA1LLCLK_indelay <= CPMDMA1LLCLK_ipd after CLK_DELAY; + CPMDMA2LLCLK_indelay <= CPMDMA2LLCLK_ipd after CLK_DELAY; + CPMDMA3LLCLK_indelay <= CPMDMA3LLCLK_ipd after CLK_DELAY; + CPMFCMCLK_indelay <= CPMFCMCLK_ipd after CLK_DELAY; + CPMINTERCONNECTCLK_indelay <= CPMINTERCONNECTCLK_ipd after CLK_DELAY; + CPMMCCLK_indelay <= CPMMCCLK_ipd after CLK_DELAY; + CPMPPCMPLBCLK_indelay <= CPMPPCMPLBCLK_ipd after CLK_DELAY; + CPMPPCS0PLBCLK_indelay <= CPMPPCS0PLBCLK_ipd after CLK_DELAY; + CPMPPCS1PLBCLK_indelay <= CPMPPCS1PLBCLK_ipd after CLK_DELAY; + JTGC440TCK_indelay <= JTGC440TCK_ipd after CLK_DELAY; + + CPMC440CLKEN_indelay <= CPMC440CLKEN_ipd after IN_DELAY; + CPMC440CORECLOCKINACTIVE_indelay <= CPMC440CORECLOCKINACTIVE_ipd after IN_DELAY; + CPMINTERCONNECTCLKEN_indelay <= CPMINTERCONNECTCLKEN_ipd after IN_DELAY; + CPMINTERCONNECTCLKNTO1_indelay <= CPMINTERCONNECTCLKNTO1_ipd after IN_DELAY; + DBGC440DEBUGHALT_indelay <= DBGC440DEBUGHALT_ipd after IN_DELAY; + DBGC440SYSTEMSTATUS_indelay <= DBGC440SYSTEMSTATUS_ipd after IN_DELAY; + DBGC440UNCONDDEBUGEVENT_indelay <= DBGC440UNCONDDEBUGEVENT_ipd after IN_DELAY; + DCRPPCDMACK_indelay <= DCRPPCDMACK_ipd after IN_DELAY; + DCRPPCDMDBUSIN_indelay <= DCRPPCDMDBUSIN_ipd after IN_DELAY; + DCRPPCDMTIMEOUTWAIT_indelay <= DCRPPCDMTIMEOUTWAIT_ipd after IN_DELAY; + DCRPPCDSABUS_indelay <= DCRPPCDSABUS_ipd after IN_DELAY; + DCRPPCDSDBUSOUT_indelay <= DCRPPCDSDBUSOUT_ipd after IN_DELAY; + DCRPPCDSREAD_indelay <= DCRPPCDSREAD_ipd after IN_DELAY; + DCRPPCDSWRITE_indelay <= DCRPPCDSWRITE_ipd after IN_DELAY; + EICC440CRITIRQ_indelay <= EICC440CRITIRQ_ipd after IN_DELAY; + EICC440EXTIRQ_indelay <= EICC440EXTIRQ_ipd after IN_DELAY; + FCMAPUCONFIRMINSTR_indelay <= FCMAPUCONFIRMINSTR_ipd after IN_DELAY; + FCMAPUCR_indelay <= FCMAPUCR_ipd after IN_DELAY; + FCMAPUDONE_indelay <= FCMAPUDONE_ipd after IN_DELAY; + FCMAPUEXCEPTION_indelay <= FCMAPUEXCEPTION_ipd after IN_DELAY; + FCMAPUFPSCRFEX_indelay <= FCMAPUFPSCRFEX_ipd after IN_DELAY; + FCMAPURESULTVALID_indelay <= FCMAPURESULTVALID_ipd after IN_DELAY; + FCMAPURESULT_indelay <= FCMAPURESULT_ipd after IN_DELAY; + FCMAPUSLEEPNOTREADY_indelay <= FCMAPUSLEEPNOTREADY_ipd after IN_DELAY; + FCMAPUSTOREDATA_indelay <= FCMAPUSTOREDATA_ipd after IN_DELAY; + JTGC440TDI_indelay <= JTGC440TDI_ipd after IN_DELAY; + JTGC440TMS_indelay <= JTGC440TMS_ipd after IN_DELAY; + JTGC440TRSTNEG_indelay <= JTGC440TRSTNEG_ipd after IN_DELAY; + LLDMA0RSTENGINEREQ_indelay <= LLDMA0RSTENGINEREQ_ipd after IN_DELAY; + LLDMA0RXD_indelay <= LLDMA0RXD_ipd after IN_DELAY; + LLDMA0RXEOFN_indelay <= LLDMA0RXEOFN_ipd after IN_DELAY; + LLDMA0RXEOPN_indelay <= LLDMA0RXEOPN_ipd after IN_DELAY; + LLDMA0RXREM_indelay <= LLDMA0RXREM_ipd after IN_DELAY; + LLDMA0RXSOFN_indelay <= LLDMA0RXSOFN_ipd after IN_DELAY; + LLDMA0RXSOPN_indelay <= LLDMA0RXSOPN_ipd after IN_DELAY; + LLDMA0RXSRCRDYN_indelay <= LLDMA0RXSRCRDYN_ipd after IN_DELAY; + LLDMA0TXDSTRDYN_indelay <= LLDMA0TXDSTRDYN_ipd after IN_DELAY; + LLDMA1RSTENGINEREQ_indelay <= LLDMA1RSTENGINEREQ_ipd after IN_DELAY; + LLDMA1RXD_indelay <= LLDMA1RXD_ipd after IN_DELAY; + LLDMA1RXEOFN_indelay <= LLDMA1RXEOFN_ipd after IN_DELAY; + LLDMA1RXEOPN_indelay <= LLDMA1RXEOPN_ipd after IN_DELAY; + LLDMA1RXREM_indelay <= LLDMA1RXREM_ipd after IN_DELAY; + LLDMA1RXSOFN_indelay <= LLDMA1RXSOFN_ipd after IN_DELAY; + LLDMA1RXSOPN_indelay <= LLDMA1RXSOPN_ipd after IN_DELAY; + LLDMA1RXSRCRDYN_indelay <= LLDMA1RXSRCRDYN_ipd after IN_DELAY; + LLDMA1TXDSTRDYN_indelay <= LLDMA1TXDSTRDYN_ipd after IN_DELAY; + LLDMA2RSTENGINEREQ_indelay <= LLDMA2RSTENGINEREQ_ipd after IN_DELAY; + LLDMA2RXD_indelay <= LLDMA2RXD_ipd after IN_DELAY; + LLDMA2RXEOFN_indelay <= LLDMA2RXEOFN_ipd after IN_DELAY; + LLDMA2RXEOPN_indelay <= LLDMA2RXEOPN_ipd after IN_DELAY; + LLDMA2RXREM_indelay <= LLDMA2RXREM_ipd after IN_DELAY; + LLDMA2RXSOFN_indelay <= LLDMA2RXSOFN_ipd after IN_DELAY; + LLDMA2RXSOPN_indelay <= LLDMA2RXSOPN_ipd after IN_DELAY; + LLDMA2RXSRCRDYN_indelay <= LLDMA2RXSRCRDYN_ipd after IN_DELAY; + LLDMA2TXDSTRDYN_indelay <= LLDMA2TXDSTRDYN_ipd after IN_DELAY; + LLDMA3RSTENGINEREQ_indelay <= LLDMA3RSTENGINEREQ_ipd after IN_DELAY; + LLDMA3RXD_indelay <= LLDMA3RXD_ipd after IN_DELAY; + LLDMA3RXEOFN_indelay <= LLDMA3RXEOFN_ipd after IN_DELAY; + LLDMA3RXEOPN_indelay <= LLDMA3RXEOPN_ipd after IN_DELAY; + LLDMA3RXREM_indelay <= LLDMA3RXREM_ipd after IN_DELAY; + LLDMA3RXSOFN_indelay <= LLDMA3RXSOFN_ipd after IN_DELAY; + LLDMA3RXSOPN_indelay <= LLDMA3RXSOPN_ipd after IN_DELAY; + LLDMA3RXSRCRDYN_indelay <= LLDMA3RXSRCRDYN_ipd after IN_DELAY; + LLDMA3TXDSTRDYN_indelay <= LLDMA3TXDSTRDYN_ipd after IN_DELAY; + MCMIADDRREADYTOACCEPT_indelay <= MCMIADDRREADYTOACCEPT_ipd after IN_DELAY; + MCMIREADDATAERR_indelay <= MCMIREADDATAERR_ipd after IN_DELAY; + MCMIREADDATAVALID_indelay <= MCMIREADDATAVALID_ipd after IN_DELAY; + MCMIREADDATA_indelay <= MCMIREADDATA_ipd after IN_DELAY; + PLBPPCMADDRACK_indelay <= PLBPPCMADDRACK_ipd after IN_DELAY; + PLBPPCMMBUSY_indelay <= PLBPPCMMBUSY_ipd after IN_DELAY; + PLBPPCMMIRQ_indelay <= PLBPPCMMIRQ_ipd after IN_DELAY; + PLBPPCMMRDERR_indelay <= PLBPPCMMRDERR_ipd after IN_DELAY; + PLBPPCMMWRERR_indelay <= PLBPPCMMWRERR_ipd after IN_DELAY; + PLBPPCMRDBTERM_indelay <= PLBPPCMRDBTERM_ipd after IN_DELAY; + PLBPPCMRDDACK_indelay <= PLBPPCMRDDACK_ipd after IN_DELAY; + PLBPPCMRDDBUS_indelay <= PLBPPCMRDDBUS_ipd after IN_DELAY; + PLBPPCMRDPENDPRI_indelay <= PLBPPCMRDPENDPRI_ipd after IN_DELAY; + PLBPPCMRDPENDREQ_indelay <= PLBPPCMRDPENDREQ_ipd after IN_DELAY; + PLBPPCMRDWDADDR_indelay <= PLBPPCMRDWDADDR_ipd after IN_DELAY; + PLBPPCMREARBITRATE_indelay <= PLBPPCMREARBITRATE_ipd after IN_DELAY; + PLBPPCMREQPRI_indelay <= PLBPPCMREQPRI_ipd after IN_DELAY; + PLBPPCMSSIZE_indelay <= PLBPPCMSSIZE_ipd after IN_DELAY; + PLBPPCMTIMEOUT_indelay <= PLBPPCMTIMEOUT_ipd after IN_DELAY; + PLBPPCMWRBTERM_indelay <= PLBPPCMWRBTERM_ipd after IN_DELAY; + PLBPPCMWRDACK_indelay <= PLBPPCMWRDACK_ipd after IN_DELAY; + PLBPPCMWRPENDPRI_indelay <= PLBPPCMWRPENDPRI_ipd after IN_DELAY; + PLBPPCMWRPENDREQ_indelay <= PLBPPCMWRPENDREQ_ipd after IN_DELAY; + PLBPPCS0ABORT_indelay <= PLBPPCS0ABORT_ipd after IN_DELAY; + PLBPPCS0ABUS_indelay <= PLBPPCS0ABUS_ipd after IN_DELAY; + PLBPPCS0BE_indelay <= PLBPPCS0BE_ipd after IN_DELAY; + PLBPPCS0BUSLOCK_indelay <= PLBPPCS0BUSLOCK_ipd after IN_DELAY; + PLBPPCS0LOCKERR_indelay <= PLBPPCS0LOCKERR_ipd after IN_DELAY; + PLBPPCS0MASTERID_indelay <= PLBPPCS0MASTERID_ipd after IN_DELAY; + PLBPPCS0MSIZE_indelay <= PLBPPCS0MSIZE_ipd after IN_DELAY; + PLBPPCS0PAVALID_indelay <= PLBPPCS0PAVALID_ipd after IN_DELAY; + PLBPPCS0RDBURST_indelay <= PLBPPCS0RDBURST_ipd after IN_DELAY; + PLBPPCS0RDPENDPRI_indelay <= PLBPPCS0RDPENDPRI_ipd after IN_DELAY; + PLBPPCS0RDPENDREQ_indelay <= PLBPPCS0RDPENDREQ_ipd after IN_DELAY; + PLBPPCS0RDPRIM_indelay <= PLBPPCS0RDPRIM_ipd after IN_DELAY; + PLBPPCS0REQPRI_indelay <= PLBPPCS0REQPRI_ipd after IN_DELAY; + PLBPPCS0RNW_indelay <= PLBPPCS0RNW_ipd after IN_DELAY; + PLBPPCS0SAVALID_indelay <= PLBPPCS0SAVALID_ipd after IN_DELAY; + PLBPPCS0SIZE_indelay <= PLBPPCS0SIZE_ipd after IN_DELAY; + PLBPPCS0TATTRIBUTE_indelay <= PLBPPCS0TATTRIBUTE_ipd after IN_DELAY; + PLBPPCS0TYPE_indelay <= PLBPPCS0TYPE_ipd after IN_DELAY; + PLBPPCS0UABUS_indelay <= PLBPPCS0UABUS_ipd after IN_DELAY; + PLBPPCS0WRBURST_indelay <= PLBPPCS0WRBURST_ipd after IN_DELAY; + PLBPPCS0WRDBUS_indelay <= PLBPPCS0WRDBUS_ipd after IN_DELAY; + PLBPPCS0WRPENDPRI_indelay <= PLBPPCS0WRPENDPRI_ipd after IN_DELAY; + PLBPPCS0WRPENDREQ_indelay <= PLBPPCS0WRPENDREQ_ipd after IN_DELAY; + PLBPPCS0WRPRIM_indelay <= PLBPPCS0WRPRIM_ipd after IN_DELAY; + PLBPPCS1ABORT_indelay <= PLBPPCS1ABORT_ipd after IN_DELAY; + PLBPPCS1ABUS_indelay <= PLBPPCS1ABUS_ipd after IN_DELAY; + PLBPPCS1BE_indelay <= PLBPPCS1BE_ipd after IN_DELAY; + PLBPPCS1BUSLOCK_indelay <= PLBPPCS1BUSLOCK_ipd after IN_DELAY; + PLBPPCS1LOCKERR_indelay <= PLBPPCS1LOCKERR_ipd after IN_DELAY; + PLBPPCS1MASTERID_indelay <= PLBPPCS1MASTERID_ipd after IN_DELAY; + PLBPPCS1MSIZE_indelay <= PLBPPCS1MSIZE_ipd after IN_DELAY; + PLBPPCS1PAVALID_indelay <= PLBPPCS1PAVALID_ipd after IN_DELAY; + PLBPPCS1RDBURST_indelay <= PLBPPCS1RDBURST_ipd after IN_DELAY; + PLBPPCS1RDPENDPRI_indelay <= PLBPPCS1RDPENDPRI_ipd after IN_DELAY; + PLBPPCS1RDPENDREQ_indelay <= PLBPPCS1RDPENDREQ_ipd after IN_DELAY; + PLBPPCS1RDPRIM_indelay <= PLBPPCS1RDPRIM_ipd after IN_DELAY; + PLBPPCS1REQPRI_indelay <= PLBPPCS1REQPRI_ipd after IN_DELAY; + PLBPPCS1RNW_indelay <= PLBPPCS1RNW_ipd after IN_DELAY; + PLBPPCS1SAVALID_indelay <= PLBPPCS1SAVALID_ipd after IN_DELAY; + PLBPPCS1SIZE_indelay <= PLBPPCS1SIZE_ipd after IN_DELAY; + PLBPPCS1TATTRIBUTE_indelay <= PLBPPCS1TATTRIBUTE_ipd after IN_DELAY; + PLBPPCS1TYPE_indelay <= PLBPPCS1TYPE_ipd after IN_DELAY; + PLBPPCS1UABUS_indelay <= PLBPPCS1UABUS_ipd after IN_DELAY; + PLBPPCS1WRBURST_indelay <= PLBPPCS1WRBURST_ipd after IN_DELAY; + PLBPPCS1WRDBUS_indelay <= PLBPPCS1WRDBUS_ipd after IN_DELAY; + PLBPPCS1WRPENDPRI_indelay <= PLBPPCS1WRPENDPRI_ipd after IN_DELAY; + PLBPPCS1WRPENDREQ_indelay <= PLBPPCS1WRPENDREQ_ipd after IN_DELAY; + PLBPPCS1WRPRIM_indelay <= PLBPPCS1WRPRIM_ipd after IN_DELAY; + RSTC440RESETCHIP_indelay <= RSTC440RESETCHIP_ipd after IN_DELAY; + RSTC440RESETCORE_indelay <= RSTC440RESETCORE_ipd after IN_DELAY; + RSTC440RESETSYSTEM_indelay <= RSTC440RESETSYSTEM_ipd after IN_DELAY; + TIEC440DCURDLDCACHEPLBPRIO_indelay <= TIEC440DCURDLDCACHEPLBPRIO_ipd after IN_DELAY; + TIEC440DCURDNONCACHEPLBPRIO_indelay <= TIEC440DCURDNONCACHEPLBPRIO_ipd after IN_DELAY; + TIEC440DCURDTOUCHPLBPRIO_indelay <= TIEC440DCURDTOUCHPLBPRIO_ipd after IN_DELAY; + TIEC440DCURDURGENTPLBPRIO_indelay <= TIEC440DCURDURGENTPLBPRIO_ipd after IN_DELAY; + TIEC440DCUWRFLUSHPLBPRIO_indelay <= TIEC440DCUWRFLUSHPLBPRIO_ipd after IN_DELAY; + TIEC440DCUWRSTOREPLBPRIO_indelay <= TIEC440DCUWRSTOREPLBPRIO_ipd after IN_DELAY; + TIEC440DCUWRURGENTPLBPRIO_indelay <= TIEC440DCUWRURGENTPLBPRIO_ipd after IN_DELAY; + TIEC440ENDIANRESET_indelay <= TIEC440ENDIANRESET_ipd after IN_DELAY; + TIEC440ERPNRESET_indelay <= TIEC440ERPNRESET_ipd after IN_DELAY; + TIEC440ICURDFETCHPLBPRIO_indelay <= TIEC440ICURDFETCHPLBPRIO_ipd after IN_DELAY; + TIEC440ICURDSPECPLBPRIO_indelay <= TIEC440ICURDSPECPLBPRIO_ipd after IN_DELAY; + TIEC440ICURDTOUCHPLBPRIO_indelay <= TIEC440ICURDTOUCHPLBPRIO_ipd after IN_DELAY; + TIEC440PIR_indelay <= TIEC440PIR_ipd after IN_DELAY; + TIEC440PVR_indelay <= TIEC440PVR_ipd after IN_DELAY; + TIEC440USERRESET_indelay <= TIEC440USERRESET_ipd after IN_DELAY; + TIEDCRBASEADDR_indelay <= TIEDCRBASEADDR_ipd after IN_DELAY; + TRCC440TRACEDISABLE_indelay <= TRCC440TRACEDISABLE_ipd after IN_DELAY; + TRCC440TRIGGEREVENTIN_indelay <= TRCC440TRIGGEREVENTIN_ipd after IN_DELAY; + + + ppc440_swift_1 : PPC440_SWIFT_BUS + port map ( + APU_CONTROL => APU_CONTROL_BINARY, + APU_UDI0 => APU_UDI0_BINARY, + APU_UDI1 => APU_UDI1_BINARY, + APU_UDI10 => APU_UDI10_BINARY, + APU_UDI11 => APU_UDI11_BINARY, + APU_UDI12 => APU_UDI12_BINARY, + APU_UDI13 => APU_UDI13_BINARY, + APU_UDI14 => APU_UDI14_BINARY, + APU_UDI15 => APU_UDI15_BINARY, + APU_UDI2 => APU_UDI2_BINARY, + APU_UDI3 => APU_UDI3_BINARY, + APU_UDI4 => APU_UDI4_BINARY, + APU_UDI5 => APU_UDI5_BINARY, + APU_UDI6 => APU_UDI6_BINARY, + APU_UDI7 => APU_UDI7_BINARY, + APU_UDI8 => APU_UDI8_BINARY, + APU_UDI9 => APU_UDI9_BINARY, + CLOCK_DELAY => CLOCK_DELAY_BINARY, + DCR_AUTOLOCK_ENABLE => DCR_AUTOLOCK_ENABLE_BINARY, + DMA0_CONTROL => DMA0_CONTROL_BINARY, + DMA0_RXCHANNELCTRL => DMA0_RXCHANNELCTRL_BINARY, + DMA0_RXIRQTIMER => DMA0_RXIRQTIMER_BINARY, + DMA0_TXCHANNELCTRL => DMA0_TXCHANNELCTRL_BINARY, + DMA0_TXIRQTIMER => DMA0_TXIRQTIMER_BINARY, + DMA1_CONTROL => DMA1_CONTROL_BINARY, + DMA1_RXCHANNELCTRL => DMA1_RXCHANNELCTRL_BINARY, + DMA1_RXIRQTIMER => DMA1_RXIRQTIMER_BINARY, + DMA1_TXCHANNELCTRL => DMA1_TXCHANNELCTRL_BINARY, + DMA1_TXIRQTIMER => DMA1_TXIRQTIMER_BINARY, + DMA2_CONTROL => DMA2_CONTROL_BINARY, + DMA2_RXCHANNELCTRL => DMA2_RXCHANNELCTRL_BINARY, + DMA2_RXIRQTIMER => DMA2_RXIRQTIMER_BINARY, + DMA2_TXCHANNELCTRL => DMA2_TXCHANNELCTRL_BINARY, + DMA2_TXIRQTIMER => DMA2_TXIRQTIMER_BINARY, + DMA3_CONTROL => DMA3_CONTROL_BINARY, + DMA3_RXCHANNELCTRL => DMA3_RXCHANNELCTRL_BINARY, + DMA3_RXIRQTIMER => DMA3_RXIRQTIMER_BINARY, + DMA3_TXCHANNELCTRL => DMA3_TXCHANNELCTRL_BINARY, + DMA3_TXIRQTIMER => DMA3_TXIRQTIMER_BINARY, + INTERCONNECT_IMASK => INTERCONNECT_IMASK_BINARY, + INTERCONNECT_TMPL_SEL => INTERCONNECT_TMPL_SEL_BINARY, + MI_ARBCONFIG => MI_ARBCONFIG_BINARY, + MI_BANKCONFLICT_MASK => MI_BANKCONFLICT_MASK_BINARY, + MI_CONTROL => MI_CONTROL_BINARY, + MI_ROWCONFLICT_MASK => MI_ROWCONFLICT_MASK_BINARY, + PPCDM_ASYNCMODE => PPCDM_ASYNCMODE_BINARY, + PPCDS_ASYNCMODE => PPCDS_ASYNCMODE_BINARY, + PPCM_ARBCONFIG => PPCM_ARBCONFIG_BINARY, + PPCM_CONTROL => PPCM_CONTROL_BINARY, + PPCM_COUNTER => PPCM_COUNTER_BINARY, + PPCS0_ADDRMAP_TMPL0 => PPCS0_ADDRMAP_TMPL0_BINARY, + PPCS0_ADDRMAP_TMPL1 => PPCS0_ADDRMAP_TMPL1_BINARY, + PPCS0_ADDRMAP_TMPL2 => PPCS0_ADDRMAP_TMPL2_BINARY, + PPCS0_ADDRMAP_TMPL3 => PPCS0_ADDRMAP_TMPL3_BINARY, + PPCS0_CONTROL => PPCS0_CONTROL_BINARY, + PPCS0_WIDTH_128N64 => PPCS0_WIDTH_128N64_BINARY, + PPCS1_ADDRMAP_TMPL0 => PPCS1_ADDRMAP_TMPL0_BINARY, + PPCS1_ADDRMAP_TMPL1 => PPCS1_ADDRMAP_TMPL1_BINARY, + PPCS1_ADDRMAP_TMPL2 => PPCS1_ADDRMAP_TMPL2_BINARY, + PPCS1_ADDRMAP_TMPL3 => PPCS1_ADDRMAP_TMPL3_BINARY, + PPCS1_CONTROL => PPCS1_CONTROL_BINARY, + PPCS1_WIDTH_128N64 => PPCS1_WIDTH_128N64_BINARY, + XBAR_ADDRMAP_TMPL0 => XBAR_ADDRMAP_TMPL0_BINARY, + XBAR_ADDRMAP_TMPL1 => XBAR_ADDRMAP_TMPL1_BINARY, + XBAR_ADDRMAP_TMPL2 => XBAR_ADDRMAP_TMPL2_BINARY, + XBAR_ADDRMAP_TMPL3 => XBAR_ADDRMAP_TMPL3_BINARY, + + APUFCMDECFPUOP => APUFCMDECFPUOP_outdelay, + APUFCMDECLDSTXFERSIZE => APUFCMDECLDSTXFERSIZE_outdelay, + APUFCMDECLOAD => APUFCMDECLOAD_outdelay, + APUFCMDECNONAUTON => APUFCMDECNONAUTON_outdelay, + APUFCMDECSTORE => APUFCMDECSTORE_outdelay, + APUFCMDECUDI => APUFCMDECUDI_outdelay, + APUFCMDECUDIVALID => APUFCMDECUDIVALID_outdelay, + APUFCMENDIAN => APUFCMENDIAN_outdelay, + APUFCMFLUSH => APUFCMFLUSH_outdelay, + APUFCMINSTRUCTION => APUFCMINSTRUCTION_outdelay, + APUFCMINSTRVALID => APUFCMINSTRVALID_outdelay, + APUFCMLOADBYTEADDR => APUFCMLOADBYTEADDR_outdelay, + APUFCMLOADDATA => APUFCMLOADDATA_outdelay, + APUFCMLOADDVALID => APUFCMLOADDVALID_outdelay, + APUFCMMSRFE0 => APUFCMMSRFE0_outdelay, + APUFCMMSRFE1 => APUFCMMSRFE1_outdelay, + APUFCMNEXTINSTRREADY => APUFCMNEXTINSTRREADY_outdelay, + APUFCMOPERANDVALID => APUFCMOPERANDVALID_outdelay, + APUFCMRADATA => APUFCMRADATA_outdelay, + APUFCMRBDATA => APUFCMRBDATA_outdelay, + APUFCMWRITEBACKOK => APUFCMWRITEBACKOK_outdelay, + C440CPMCORESLEEPREQ => C440CPMCORESLEEPREQ_outdelay, + C440CPMDECIRPTREQ => C440CPMDECIRPTREQ_outdelay, + C440CPMFITIRPTREQ => C440CPMFITIRPTREQ_outdelay, + C440CPMMSRCE => C440CPMMSRCE_outdelay, + C440CPMMSREE => C440CPMMSREE_outdelay, + C440CPMTIMERRESETREQ => C440CPMTIMERRESETREQ_outdelay, + C440CPMWDIRPTREQ => C440CPMWDIRPTREQ_outdelay, + C440DBGSYSTEMCONTROL => C440DBGSYSTEMCONTROL_outdelay, + C440JTGTDO => C440JTGTDO_outdelay, + C440JTGTDOEN => C440JTGTDOEN_outdelay, + C440MACHINECHECK => C440MACHINECHECK_outdelay, + C440RSTCHIPRESETREQ => C440RSTCHIPRESETREQ_outdelay, + C440RSTCORERESETREQ => C440RSTCORERESETREQ_outdelay, + C440RSTSYSTEMRESETREQ => C440RSTSYSTEMRESETREQ_outdelay, + C440TRCBRANCHSTATUS => C440TRCBRANCHSTATUS_outdelay, + C440TRCCYCLE => C440TRCCYCLE_outdelay, + C440TRCEXECUTIONSTATUS => C440TRCEXECUTIONSTATUS_outdelay, + C440TRCTRACESTATUS => C440TRCTRACESTATUS_outdelay, + C440TRCTRIGGEREVENTOUT => C440TRCTRIGGEREVENTOUT_outdelay, + C440TRCTRIGGEREVENTTYPE => C440TRCTRIGGEREVENTTYPE_outdelay, + DMA0LLRSTENGINEACK => DMA0LLRSTENGINEACK_outdelay, + DMA0LLRXDSTRDYN => DMA0LLRXDSTRDYN_outdelay, + DMA0LLTXD => DMA0LLTXD_outdelay, + DMA0LLTXEOFN => DMA0LLTXEOFN_outdelay, + DMA0LLTXEOPN => DMA0LLTXEOPN_outdelay, + DMA0LLTXREM => DMA0LLTXREM_outdelay, + DMA0LLTXSOFN => DMA0LLTXSOFN_outdelay, + DMA0LLTXSOPN => DMA0LLTXSOPN_outdelay, + DMA0LLTXSRCRDYN => DMA0LLTXSRCRDYN_outdelay, + DMA0RXIRQ => DMA0RXIRQ_outdelay, + DMA0TXIRQ => DMA0TXIRQ_outdelay, + DMA1LLRSTENGINEACK => DMA1LLRSTENGINEACK_outdelay, + DMA1LLRXDSTRDYN => DMA1LLRXDSTRDYN_outdelay, + DMA1LLTXD => DMA1LLTXD_outdelay, + DMA1LLTXEOFN => DMA1LLTXEOFN_outdelay, + DMA1LLTXEOPN => DMA1LLTXEOPN_outdelay, + DMA1LLTXREM => DMA1LLTXREM_outdelay, + DMA1LLTXSOFN => DMA1LLTXSOFN_outdelay, + DMA1LLTXSOPN => DMA1LLTXSOPN_outdelay, + DMA1LLTXSRCRDYN => DMA1LLTXSRCRDYN_outdelay, + DMA1RXIRQ => DMA1RXIRQ_outdelay, + DMA1TXIRQ => DMA1TXIRQ_outdelay, + DMA2LLRSTENGINEACK => DMA2LLRSTENGINEACK_outdelay, + DMA2LLRXDSTRDYN => DMA2LLRXDSTRDYN_outdelay, + DMA2LLTXD => DMA2LLTXD_outdelay, + DMA2LLTXEOFN => DMA2LLTXEOFN_outdelay, + DMA2LLTXEOPN => DMA2LLTXEOPN_outdelay, + DMA2LLTXREM => DMA2LLTXREM_outdelay, + DMA2LLTXSOFN => DMA2LLTXSOFN_outdelay, + DMA2LLTXSOPN => DMA2LLTXSOPN_outdelay, + DMA2LLTXSRCRDYN => DMA2LLTXSRCRDYN_outdelay, + DMA2RXIRQ => DMA2RXIRQ_outdelay, + DMA2TXIRQ => DMA2TXIRQ_outdelay, + DMA3LLRSTENGINEACK => DMA3LLRSTENGINEACK_outdelay, + DMA3LLRXDSTRDYN => DMA3LLRXDSTRDYN_outdelay, + DMA3LLTXD => DMA3LLTXD_outdelay, + DMA3LLTXEOFN => DMA3LLTXEOFN_outdelay, + DMA3LLTXEOPN => DMA3LLTXEOPN_outdelay, + DMA3LLTXREM => DMA3LLTXREM_outdelay, + DMA3LLTXSOFN => DMA3LLTXSOFN_outdelay, + DMA3LLTXSOPN => DMA3LLTXSOPN_outdelay, + DMA3LLTXSRCRDYN => DMA3LLTXSRCRDYN_outdelay, + DMA3RXIRQ => DMA3RXIRQ_outdelay, + DMA3TXIRQ => DMA3TXIRQ_outdelay, + MIMCADDRESS => MIMCADDRESS_outdelay, + MIMCADDRESSVALID => MIMCADDRESSVALID_outdelay, + MIMCBANKCONFLICT => MIMCBANKCONFLICT_outdelay, + MIMCBYTEENABLE => MIMCBYTEENABLE_outdelay, + MIMCREADNOTWRITE => MIMCREADNOTWRITE_outdelay, + MIMCROWCONFLICT => MIMCROWCONFLICT_outdelay, + MIMCWRITEDATA => MIMCWRITEDATA_outdelay, + MIMCWRITEDATAVALID => MIMCWRITEDATAVALID_outdelay, + PPCCPMINTERCONNECTBUSY => PPCCPMINTERCONNECTBUSY_outdelay, + PPCDMDCRABUS => PPCDMDCRABUS_outdelay, + PPCDMDCRDBUSOUT => PPCDMDCRDBUSOUT_outdelay, + PPCDMDCRREAD => PPCDMDCRREAD_outdelay, + PPCDMDCRUABUS => PPCDMDCRUABUS_outdelay, + PPCDMDCRWRITE => PPCDMDCRWRITE_outdelay, + PPCDSDCRACK => PPCDSDCRACK_outdelay, + PPCDSDCRDBUSIN => PPCDSDCRDBUSIN_outdelay, + PPCDSDCRTIMEOUTWAIT => PPCDSDCRTIMEOUTWAIT_outdelay, + PPCEICINTERCONNECTIRQ => PPCEICINTERCONNECTIRQ_outdelay, + PPCMPLBABORT => PPCMPLBABORT_outdelay, + PPCMPLBABUS => PPCMPLBABUS_outdelay, + PPCMPLBBE => PPCMPLBBE_outdelay, + PPCMPLBBUSLOCK => PPCMPLBBUSLOCK_outdelay, + PPCMPLBLOCKERR => PPCMPLBLOCKERR_outdelay, + PPCMPLBPRIORITY => PPCMPLBPRIORITY_outdelay, + PPCMPLBRDBURST => PPCMPLBRDBURST_outdelay, + PPCMPLBREQUEST => PPCMPLBREQUEST_outdelay, + PPCMPLBRNW => PPCMPLBRNW_outdelay, + PPCMPLBSIZE => PPCMPLBSIZE_outdelay, + PPCMPLBTATTRIBUTE => PPCMPLBTATTRIBUTE_outdelay, + PPCMPLBTYPE => PPCMPLBTYPE_outdelay, + PPCMPLBUABUS => PPCMPLBUABUS_outdelay, + PPCMPLBWRBURST => PPCMPLBWRBURST_outdelay, + PPCMPLBWRDBUS => PPCMPLBWRDBUS_outdelay, + PPCS0PLBADDRACK => PPCS0PLBADDRACK_outdelay, + PPCS0PLBMBUSY => PPCS0PLBMBUSY_outdelay, + PPCS0PLBMIRQ => PPCS0PLBMIRQ_outdelay, + PPCS0PLBMRDERR => PPCS0PLBMRDERR_outdelay, + PPCS0PLBMWRERR => PPCS0PLBMWRERR_outdelay, + PPCS0PLBRDBTERM => PPCS0PLBRDBTERM_outdelay, + PPCS0PLBRDCOMP => PPCS0PLBRDCOMP_outdelay, + PPCS0PLBRDDACK => PPCS0PLBRDDACK_outdelay, + PPCS0PLBRDDBUS => PPCS0PLBRDDBUS_outdelay, + PPCS0PLBRDWDADDR => PPCS0PLBRDWDADDR_outdelay, + PPCS0PLBREARBITRATE => PPCS0PLBREARBITRATE_outdelay, + PPCS0PLBSSIZE => PPCS0PLBSSIZE_outdelay, + PPCS0PLBWAIT => PPCS0PLBWAIT_outdelay, + PPCS0PLBWRBTERM => PPCS0PLBWRBTERM_outdelay, + PPCS0PLBWRCOMP => PPCS0PLBWRCOMP_outdelay, + PPCS0PLBWRDACK => PPCS0PLBWRDACK_outdelay, + PPCS1PLBADDRACK => PPCS1PLBADDRACK_outdelay, + PPCS1PLBMBUSY => PPCS1PLBMBUSY_outdelay, + PPCS1PLBMIRQ => PPCS1PLBMIRQ_outdelay, + PPCS1PLBMRDERR => PPCS1PLBMRDERR_outdelay, + PPCS1PLBMWRERR => PPCS1PLBMWRERR_outdelay, + PPCS1PLBRDBTERM => PPCS1PLBRDBTERM_outdelay, + PPCS1PLBRDCOMP => PPCS1PLBRDCOMP_outdelay, + PPCS1PLBRDDACK => PPCS1PLBRDDACK_outdelay, + PPCS1PLBRDDBUS => PPCS1PLBRDDBUS_outdelay, + PPCS1PLBRDWDADDR => PPCS1PLBRDWDADDR_outdelay, + PPCS1PLBREARBITRATE => PPCS1PLBREARBITRATE_outdelay, + PPCS1PLBSSIZE => PPCS1PLBSSIZE_outdelay, + PPCS1PLBWAIT => PPCS1PLBWAIT_outdelay, + PPCS1PLBWRBTERM => PPCS1PLBWRBTERM_outdelay, + PPCS1PLBWRCOMP => PPCS1PLBWRCOMP_outdelay, + PPCS1PLBWRDACK => PPCS1PLBWRDACK_outdelay, + + CPMC440CLK => CPMC440CLK_indelay, + CPMC440CLKEN => CPMC440CLKEN_indelay, + CPMC440CORECLOCKINACTIVE => CPMC440CORECLOCKINACTIVE_indelay, + CPMC440TIMERCLOCK => CPMC440TIMERCLOCK_indelay, + CPMDCRCLK => CPMDCRCLK_indelay, + CPMDMA0LLCLK => CPMDMA0LLCLK_indelay, + CPMDMA1LLCLK => CPMDMA1LLCLK_indelay, + CPMDMA2LLCLK => CPMDMA2LLCLK_indelay, + CPMDMA3LLCLK => CPMDMA3LLCLK_indelay, + CPMFCMCLK => CPMFCMCLK_indelay, + CPMINTERCONNECTCLK => CPMINTERCONNECTCLK_indelay, + CPMINTERCONNECTCLKEN => CPMINTERCONNECTCLKEN_indelay, + CPMINTERCONNECTCLKNTO1 => CPMINTERCONNECTCLKNTO1_indelay, + CPMMCCLK => CPMMCCLK_indelay, + CPMPPCMPLBCLK => CPMPPCMPLBCLK_indelay, + CPMPPCS0PLBCLK => CPMPPCS0PLBCLK_indelay, + CPMPPCS1PLBCLK => CPMPPCS1PLBCLK_indelay, + DBGC440DEBUGHALT => DBGC440DEBUGHALT_indelay, + DBGC440SYSTEMSTATUS => DBGC440SYSTEMSTATUS_indelay, + DBGC440UNCONDDEBUGEVENT => DBGC440UNCONDDEBUGEVENT_indelay, + DCRPPCDMACK => DCRPPCDMACK_indelay, + DCRPPCDMDBUSIN => DCRPPCDMDBUSIN_indelay, + DCRPPCDMTIMEOUTWAIT => DCRPPCDMTIMEOUTWAIT_indelay, + DCRPPCDSABUS => DCRPPCDSABUS_indelay, + DCRPPCDSDBUSOUT => DCRPPCDSDBUSOUT_indelay, + DCRPPCDSREAD => DCRPPCDSREAD_indelay, + DCRPPCDSWRITE => DCRPPCDSWRITE_indelay, + EICC440CRITIRQ => EICC440CRITIRQ_indelay, + EICC440EXTIRQ => EICC440EXTIRQ_indelay, + FCMAPUCONFIRMINSTR => FCMAPUCONFIRMINSTR_indelay, + FCMAPUCR => FCMAPUCR_indelay, + FCMAPUDONE => FCMAPUDONE_indelay, + FCMAPUEXCEPTION => FCMAPUEXCEPTION_indelay, + FCMAPUFPSCRFEX => FCMAPUFPSCRFEX_indelay, + FCMAPURESULT => FCMAPURESULT_indelay, + FCMAPURESULTVALID => FCMAPURESULTVALID_indelay, + FCMAPUSLEEPNOTREADY => FCMAPUSLEEPNOTREADY_indelay, + FCMAPUSTOREDATA => FCMAPUSTOREDATA_indelay, + GSR => GSR, + JTGC440TCK => JTGC440TCK_indelay, + JTGC440TDI => JTGC440TDI_indelay, + JTGC440TMS => JTGC440TMS_indelay, + JTGC440TRSTNEG => JTGC440TRSTNEG_indelay, + LLDMA0RSTENGINEREQ => LLDMA0RSTENGINEREQ_indelay, + LLDMA0RXD => LLDMA0RXD_indelay, + LLDMA0RXEOFN => LLDMA0RXEOFN_indelay, + LLDMA0RXEOPN => LLDMA0RXEOPN_indelay, + LLDMA0RXREM => LLDMA0RXREM_indelay, + LLDMA0RXSOFN => LLDMA0RXSOFN_indelay, + LLDMA0RXSOPN => LLDMA0RXSOPN_indelay, + LLDMA0RXSRCRDYN => LLDMA0RXSRCRDYN_indelay, + LLDMA0TXDSTRDYN => LLDMA0TXDSTRDYN_indelay, + LLDMA1RSTENGINEREQ => LLDMA1RSTENGINEREQ_indelay, + LLDMA1RXD => LLDMA1RXD_indelay, + LLDMA1RXEOFN => LLDMA1RXEOFN_indelay, + LLDMA1RXEOPN => LLDMA1RXEOPN_indelay, + LLDMA1RXREM => LLDMA1RXREM_indelay, + LLDMA1RXSOFN => LLDMA1RXSOFN_indelay, + LLDMA1RXSOPN => LLDMA1RXSOPN_indelay, + LLDMA1RXSRCRDYN => LLDMA1RXSRCRDYN_indelay, + LLDMA1TXDSTRDYN => LLDMA1TXDSTRDYN_indelay, + LLDMA2RSTENGINEREQ => LLDMA2RSTENGINEREQ_indelay, + LLDMA2RXD => LLDMA2RXD_indelay, + LLDMA2RXEOFN => LLDMA2RXEOFN_indelay, + LLDMA2RXEOPN => LLDMA2RXEOPN_indelay, + LLDMA2RXREM => LLDMA2RXREM_indelay, + LLDMA2RXSOFN => LLDMA2RXSOFN_indelay, + LLDMA2RXSOPN => LLDMA2RXSOPN_indelay, + LLDMA2RXSRCRDYN => LLDMA2RXSRCRDYN_indelay, + LLDMA2TXDSTRDYN => LLDMA2TXDSTRDYN_indelay, + LLDMA3RSTENGINEREQ => LLDMA3RSTENGINEREQ_indelay, + LLDMA3RXD => LLDMA3RXD_indelay, + LLDMA3RXEOFN => LLDMA3RXEOFN_indelay, + LLDMA3RXEOPN => LLDMA3RXEOPN_indelay, + LLDMA3RXREM => LLDMA3RXREM_indelay, + LLDMA3RXSOFN => LLDMA3RXSOFN_indelay, + LLDMA3RXSOPN => LLDMA3RXSOPN_indelay, + LLDMA3RXSRCRDYN => LLDMA3RXSRCRDYN_indelay, + LLDMA3TXDSTRDYN => LLDMA3TXDSTRDYN_indelay, + MCMIADDRREADYTOACCEPT => MCMIADDRREADYTOACCEPT_indelay, + MCMIREADDATA => MCMIREADDATA_indelay, + MCMIREADDATAERR => MCMIREADDATAERR_indelay, + MCMIREADDATAVALID => MCMIREADDATAVALID_indelay, + PLBPPCMADDRACK => PLBPPCMADDRACK_indelay, + PLBPPCMMBUSY => PLBPPCMMBUSY_indelay, + PLBPPCMMIRQ => PLBPPCMMIRQ_indelay, + PLBPPCMMRDERR => PLBPPCMMRDERR_indelay, + PLBPPCMMWRERR => PLBPPCMMWRERR_indelay, + PLBPPCMRDBTERM => PLBPPCMRDBTERM_indelay, + PLBPPCMRDDACK => PLBPPCMRDDACK_indelay, + PLBPPCMRDDBUS => PLBPPCMRDDBUS_indelay, + PLBPPCMRDPENDPRI => PLBPPCMRDPENDPRI_indelay, + PLBPPCMRDPENDREQ => PLBPPCMRDPENDREQ_indelay, + PLBPPCMRDWDADDR => PLBPPCMRDWDADDR_indelay, + PLBPPCMREARBITRATE => PLBPPCMREARBITRATE_indelay, + PLBPPCMREQPRI => PLBPPCMREQPRI_indelay, + PLBPPCMSSIZE => PLBPPCMSSIZE_indelay, + PLBPPCMTIMEOUT => PLBPPCMTIMEOUT_indelay, + PLBPPCMWRBTERM => PLBPPCMWRBTERM_indelay, + PLBPPCMWRDACK => PLBPPCMWRDACK_indelay, + PLBPPCMWRPENDPRI => PLBPPCMWRPENDPRI_indelay, + PLBPPCMWRPENDREQ => PLBPPCMWRPENDREQ_indelay, + PLBPPCS0ABORT => PLBPPCS0ABORT_indelay, + PLBPPCS0ABUS => PLBPPCS0ABUS_indelay, + PLBPPCS0BE => PLBPPCS0BE_indelay, + PLBPPCS0BUSLOCK => PLBPPCS0BUSLOCK_indelay, + PLBPPCS0LOCKERR => PLBPPCS0LOCKERR_indelay, + PLBPPCS0MASTERID => PLBPPCS0MASTERID_indelay, + PLBPPCS0MSIZE => PLBPPCS0MSIZE_indelay, + PLBPPCS0PAVALID => PLBPPCS0PAVALID_indelay, + PLBPPCS0RDBURST => PLBPPCS0RDBURST_indelay, + PLBPPCS0RDPENDPRI => PLBPPCS0RDPENDPRI_indelay, + PLBPPCS0RDPENDREQ => PLBPPCS0RDPENDREQ_indelay, + PLBPPCS0RDPRIM => PLBPPCS0RDPRIM_indelay, + PLBPPCS0REQPRI => PLBPPCS0REQPRI_indelay, + PLBPPCS0RNW => PLBPPCS0RNW_indelay, + PLBPPCS0SAVALID => PLBPPCS0SAVALID_indelay, + PLBPPCS0SIZE => PLBPPCS0SIZE_indelay, + PLBPPCS0TATTRIBUTE => PLBPPCS0TATTRIBUTE_indelay, + PLBPPCS0TYPE => PLBPPCS0TYPE_indelay, + PLBPPCS0UABUS => PLBPPCS0UABUS_indelay, + PLBPPCS0WRBURST => PLBPPCS0WRBURST_indelay, + PLBPPCS0WRDBUS => PLBPPCS0WRDBUS_indelay, + PLBPPCS0WRPENDPRI => PLBPPCS0WRPENDPRI_indelay, + PLBPPCS0WRPENDREQ => PLBPPCS0WRPENDREQ_indelay, + PLBPPCS0WRPRIM => PLBPPCS0WRPRIM_indelay, + PLBPPCS1ABORT => PLBPPCS1ABORT_indelay, + PLBPPCS1ABUS => PLBPPCS1ABUS_indelay, + PLBPPCS1BE => PLBPPCS1BE_indelay, + PLBPPCS1BUSLOCK => PLBPPCS1BUSLOCK_indelay, + PLBPPCS1LOCKERR => PLBPPCS1LOCKERR_indelay, + PLBPPCS1MASTERID => PLBPPCS1MASTERID_indelay, + PLBPPCS1MSIZE => PLBPPCS1MSIZE_indelay, + PLBPPCS1PAVALID => PLBPPCS1PAVALID_indelay, + PLBPPCS1RDBURST => PLBPPCS1RDBURST_indelay, + PLBPPCS1RDPENDPRI => PLBPPCS1RDPENDPRI_indelay, + PLBPPCS1RDPENDREQ => PLBPPCS1RDPENDREQ_indelay, + PLBPPCS1RDPRIM => PLBPPCS1RDPRIM_indelay, + PLBPPCS1REQPRI => PLBPPCS1REQPRI_indelay, + PLBPPCS1RNW => PLBPPCS1RNW_indelay, + PLBPPCS1SAVALID => PLBPPCS1SAVALID_indelay, + PLBPPCS1SIZE => PLBPPCS1SIZE_indelay, + PLBPPCS1TATTRIBUTE => PLBPPCS1TATTRIBUTE_indelay, + PLBPPCS1TYPE => PLBPPCS1TYPE_indelay, + PLBPPCS1UABUS => PLBPPCS1UABUS_indelay, + PLBPPCS1WRBURST => PLBPPCS1WRBURST_indelay, + PLBPPCS1WRDBUS => PLBPPCS1WRDBUS_indelay, + PLBPPCS1WRPENDPRI => PLBPPCS1WRPENDPRI_indelay, + PLBPPCS1WRPENDREQ => PLBPPCS1WRPENDREQ_indelay, + PLBPPCS1WRPRIM => PLBPPCS1WRPRIM_indelay, + RSTC440RESETCHIP => RSTC440RESETCHIP_indelay, + RSTC440RESETCORE => RSTC440RESETCORE_indelay, + RSTC440RESETSYSTEM => RSTC440RESETSYSTEM_indelay, + TIEC440DCURDLDCACHEPLBPRIO => TIEC440DCURDLDCACHEPLBPRIO_indelay, + TIEC440DCURDNONCACHEPLBPRIO => TIEC440DCURDNONCACHEPLBPRIO_indelay, + TIEC440DCURDTOUCHPLBPRIO => TIEC440DCURDTOUCHPLBPRIO_indelay, + TIEC440DCURDURGENTPLBPRIO => TIEC440DCURDURGENTPLBPRIO_indelay, + TIEC440DCUWRFLUSHPLBPRIO => TIEC440DCUWRFLUSHPLBPRIO_indelay, + TIEC440DCUWRSTOREPLBPRIO => TIEC440DCUWRSTOREPLBPRIO_indelay, + TIEC440DCUWRURGENTPLBPRIO => TIEC440DCUWRURGENTPLBPRIO_indelay, + TIEC440ENDIANRESET => TIEC440ENDIANRESET_indelay, + TIEC440ERPNRESET => TIEC440ERPNRESET_indelay, + TIEC440ICURDFETCHPLBPRIO => TIEC440ICURDFETCHPLBPRIO_indelay, + TIEC440ICURDSPECPLBPRIO => TIEC440ICURDSPECPLBPRIO_indelay, + TIEC440ICURDTOUCHPLBPRIO => TIEC440ICURDTOUCHPLBPRIO_indelay, + TIEC440PIR => TIEC440PIR_indelay, + TIEC440PVR => TIEC440PVR_indelay, + TIEC440USERRESET => TIEC440USERRESET_indelay, + TIEDCRBASEADDR => TIEDCRBASEADDR_indelay, + TRCC440TRACEDISABLE => TRCC440TRACEDISABLE_indelay, + TRCC440TRIGGEREVENTIN => TRCC440TRIGGEREVENTIN_indelay + ); + + INIPROC : process + begin + case PPCS0_WIDTH_128N64 is + when FALSE => PPCS0_WIDTH_128N64_BINARY <= '0'; + when TRUE => PPCS0_WIDTH_128N64_BINARY <= '1'; + when others => assert FALSE report "Error : PPCS0_WIDTH_128N64 is neither TRUE nor FALSE." severity error; + end case; + case PPCS1_WIDTH_128N64 is + when FALSE => PPCS1_WIDTH_128N64_BINARY <= '0'; + when TRUE => PPCS1_WIDTH_128N64_BINARY <= '1'; + when others => assert FALSE report "Error : PPCS1_WIDTH_128N64 is neither TRUE nor FALSE." severity error; + end case; + case PPCDM_ASYNCMODE is + when FALSE => PPCDM_ASYNCMODE_BINARY <= '0'; + when TRUE => PPCDM_ASYNCMODE_BINARY <= '1'; + when others => assert FALSE report "Error : PPCDM_ASYNCMODE is neither TRUE nor FALSE." severity error; + end case; + case PPCDS_ASYNCMODE is + when FALSE => PPCDS_ASYNCMODE_BINARY <= '0'; + when TRUE => PPCDS_ASYNCMODE_BINARY <= '1'; + when others => assert FALSE report "Error : PPCDS_ASYNCMODE is neither TRUE nor FALSE." severity error; + end case; + case DCR_AUTOLOCK_ENABLE is + when FALSE => DCR_AUTOLOCK_ENABLE_BINARY <= '0'; + when TRUE => DCR_AUTOLOCK_ENABLE_BINARY <= '1'; + when others => assert FALSE report "Error : DCR_AUTOLOCK_ENABLE is neither TRUE nor FALSE." severity error; + end case; + case CLOCK_DELAY is + when FALSE => CLOCK_DELAY_BINARY <= "10000"; + when TRUE => CLOCK_DELAY_BINARY <= "00000"; + when others => assert FALSE report "Error : CLOCK_DELAY is neither TRUE nor FALSE." severity error; + end case; + wait; + end process INIPROC; + + TIMING : process + + + + variable DMA0LLRSTENGINEACK_GlitchData : VitalGlitchDataType; + variable DMA0LLRXDSTRDYN_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD0_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD1_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD2_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD3_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD4_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD5_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD6_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD7_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD8_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD9_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD10_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD11_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD12_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD13_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD14_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD15_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD16_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD17_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD18_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD19_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD20_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD21_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD22_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD23_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD24_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD25_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD26_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD27_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD28_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD29_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD30_GlitchData : VitalGlitchDataType; + variable DMA0LLTXD31_GlitchData : VitalGlitchDataType; + variable DMA0LLTXEOFN_GlitchData : VitalGlitchDataType; + variable DMA0LLTXEOPN_GlitchData : VitalGlitchDataType; + variable DMA0LLTXREM0_GlitchData : VitalGlitchDataType; + variable DMA0LLTXREM1_GlitchData : VitalGlitchDataType; + variable DMA0LLTXREM2_GlitchData : VitalGlitchDataType; + variable DMA0LLTXREM3_GlitchData : VitalGlitchDataType; + variable DMA0LLTXSOFN_GlitchData : VitalGlitchDataType; + variable DMA0LLTXSOPN_GlitchData : VitalGlitchDataType; + variable DMA0LLTXSRCRDYN_GlitchData : VitalGlitchDataType; + variable DMA0RXIRQ_GlitchData : VitalGlitchDataType; + variable DMA0TXIRQ_GlitchData : VitalGlitchDataType; + variable DMA1LLRSTENGINEACK_GlitchData : VitalGlitchDataType; + variable DMA1LLRXDSTRDYN_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD0_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD1_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD2_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD3_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD4_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD5_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD6_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD7_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD8_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD9_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD10_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD11_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD12_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD13_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD14_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD15_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD16_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD17_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD18_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD19_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD20_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD21_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD22_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD23_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD24_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD25_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD26_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD27_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD28_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD29_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD30_GlitchData : VitalGlitchDataType; + variable DMA1LLTXD31_GlitchData : VitalGlitchDataType; + variable DMA1LLTXEOFN_GlitchData : VitalGlitchDataType; + variable DMA1LLTXEOPN_GlitchData : VitalGlitchDataType; + variable DMA1LLTXREM0_GlitchData : VitalGlitchDataType; + variable DMA1LLTXREM1_GlitchData : VitalGlitchDataType; + variable DMA1LLTXREM2_GlitchData : VitalGlitchDataType; + variable DMA1LLTXREM3_GlitchData : VitalGlitchDataType; + variable DMA1LLTXSOFN_GlitchData : VitalGlitchDataType; + variable DMA1LLTXSOPN_GlitchData : VitalGlitchDataType; + variable DMA1LLTXSRCRDYN_GlitchData : VitalGlitchDataType; + variable DMA1RXIRQ_GlitchData : VitalGlitchDataType; + variable DMA1TXIRQ_GlitchData : VitalGlitchDataType; + variable DMA2LLRSTENGINEACK_GlitchData : VitalGlitchDataType; + variable DMA2LLRXDSTRDYN_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD0_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD1_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD2_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD3_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD4_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD5_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD6_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD7_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD8_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD9_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD10_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD11_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD12_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD13_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD14_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD15_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD16_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD17_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD18_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD19_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD20_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD21_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD22_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD23_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD24_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD25_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD26_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD27_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD28_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD29_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD30_GlitchData : VitalGlitchDataType; + variable DMA2LLTXD31_GlitchData : VitalGlitchDataType; + variable DMA2LLTXEOFN_GlitchData : VitalGlitchDataType; + variable DMA2LLTXEOPN_GlitchData : VitalGlitchDataType; + variable DMA2LLTXREM0_GlitchData : VitalGlitchDataType; + variable DMA2LLTXREM1_GlitchData : VitalGlitchDataType; + variable DMA2LLTXREM2_GlitchData : VitalGlitchDataType; + variable DMA2LLTXREM3_GlitchData : VitalGlitchDataType; + variable DMA2LLTXSOFN_GlitchData : VitalGlitchDataType; + variable DMA2LLTXSOPN_GlitchData : VitalGlitchDataType; + variable DMA2LLTXSRCRDYN_GlitchData : VitalGlitchDataType; + variable DMA2RXIRQ_GlitchData : VitalGlitchDataType; + variable DMA2TXIRQ_GlitchData : VitalGlitchDataType; + variable DMA3LLRSTENGINEACK_GlitchData : VitalGlitchDataType; + variable DMA3LLRXDSTRDYN_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD0_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD1_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD2_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD3_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD4_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD5_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD6_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD7_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD8_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD9_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD10_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD11_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD12_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD13_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD14_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD15_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD16_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD17_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD18_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD19_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD20_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD21_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD22_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD23_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD24_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD25_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD26_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD27_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD28_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD29_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD30_GlitchData : VitalGlitchDataType; + variable DMA3LLTXD31_GlitchData : VitalGlitchDataType; + variable DMA3LLTXEOFN_GlitchData : VitalGlitchDataType; + variable DMA3LLTXEOPN_GlitchData : VitalGlitchDataType; + variable DMA3LLTXREM0_GlitchData : VitalGlitchDataType; + variable DMA3LLTXREM1_GlitchData : VitalGlitchDataType; + variable DMA3LLTXREM2_GlitchData : VitalGlitchDataType; + variable DMA3LLTXREM3_GlitchData : VitalGlitchDataType; + variable DMA3LLTXSOFN_GlitchData : VitalGlitchDataType; + variable DMA3LLTXSOPN_GlitchData : VitalGlitchDataType; + variable DMA3LLTXSRCRDYN_GlitchData : VitalGlitchDataType; + variable DMA3RXIRQ_GlitchData : VitalGlitchDataType; + variable DMA3TXIRQ_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS0_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS1_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS2_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS3_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS4_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS5_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS6_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS7_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS8_GlitchData : VitalGlitchDataType; + variable PPCDMDCRABUS9_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT0_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT1_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT2_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT3_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT4_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT5_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT6_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT7_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT8_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT9_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT10_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT11_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT12_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT13_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT14_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT15_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT16_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT17_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT18_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT19_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT20_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT21_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT22_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT23_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT24_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT25_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT26_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT27_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT28_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT29_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT30_GlitchData : VitalGlitchDataType; + variable PPCDMDCRDBUSOUT31_GlitchData : VitalGlitchDataType; + variable PPCDMDCRREAD_GlitchData : VitalGlitchDataType; + variable PPCDMDCRUABUS20_GlitchData : VitalGlitchDataType; + variable PPCDMDCRUABUS21_GlitchData : VitalGlitchDataType; + variable PPCDMDCRWRITE_GlitchData : VitalGlitchDataType; + variable PPCMPLBABORT_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS0_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS1_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS2_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS3_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS4_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS5_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS6_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS7_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS8_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS9_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS10_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS11_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS12_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS13_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS14_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS15_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS16_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS17_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS18_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS19_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS20_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS21_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS22_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS23_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS24_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS25_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS26_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS27_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS28_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS29_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS30_GlitchData : VitalGlitchDataType; + variable PPCMPLBABUS31_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE0_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE1_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE2_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE3_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE4_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE5_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE6_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE7_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE8_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE9_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE10_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE11_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE12_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE13_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE14_GlitchData : VitalGlitchDataType; + variable PPCMPLBBE15_GlitchData : VitalGlitchDataType; + variable PPCMPLBBUSLOCK_GlitchData : VitalGlitchDataType; + variable PPCMPLBLOCKERR_GlitchData : VitalGlitchDataType; + variable PPCMPLBPRIORITY0_GlitchData : VitalGlitchDataType; + variable PPCMPLBPRIORITY1_GlitchData : VitalGlitchDataType; + variable PPCMPLBRDBURST_GlitchData : VitalGlitchDataType; + variable PPCMPLBREQUEST_GlitchData : VitalGlitchDataType; + variable PPCMPLBRNW_GlitchData : VitalGlitchDataType; + variable PPCMPLBSIZE0_GlitchData : VitalGlitchDataType; + variable PPCMPLBSIZE1_GlitchData : VitalGlitchDataType; + variable PPCMPLBSIZE2_GlitchData : VitalGlitchDataType; + variable PPCMPLBSIZE3_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE0_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE1_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE2_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE3_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE4_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE5_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE6_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE7_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE8_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE9_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE10_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE11_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE12_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE13_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE14_GlitchData : VitalGlitchDataType; + variable PPCMPLBTATTRIBUTE15_GlitchData : VitalGlitchDataType; + variable PPCMPLBTYPE0_GlitchData : VitalGlitchDataType; + variable PPCMPLBTYPE1_GlitchData : VitalGlitchDataType; + variable PPCMPLBTYPE2_GlitchData : VitalGlitchDataType; + variable PPCMPLBUABUS28_GlitchData : VitalGlitchDataType; + variable PPCMPLBUABUS29_GlitchData : VitalGlitchDataType; + variable PPCMPLBUABUS30_GlitchData : VitalGlitchDataType; + variable PPCMPLBUABUS31_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRBURST_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS0_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS1_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS2_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS3_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS4_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS5_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS6_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS7_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS8_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS9_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS10_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS11_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS12_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS13_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS14_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS15_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS16_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS17_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS18_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS19_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS20_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS21_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS22_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS23_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS24_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS25_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS26_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS27_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS28_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS29_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS30_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS31_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS32_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS33_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS34_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS35_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS36_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS37_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS38_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS39_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS40_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS41_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS42_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS43_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS44_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS45_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS46_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS47_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS48_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS49_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS50_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS51_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS52_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS53_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS54_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS55_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS56_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS57_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS58_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS59_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS60_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS61_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS62_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS63_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS64_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS65_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS66_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS67_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS68_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS69_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS70_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS71_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS72_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS73_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS74_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS75_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS76_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS77_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS78_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS79_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS80_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS81_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS82_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS83_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS84_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS85_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS86_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS87_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS88_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS89_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS90_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS91_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS92_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS93_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS94_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS95_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS96_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS97_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS98_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS99_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS100_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS101_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS102_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS103_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS104_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS105_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS106_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS107_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS108_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS109_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS110_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS111_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS112_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS113_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS114_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS115_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS116_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS117_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS118_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS119_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS120_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS121_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS122_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS123_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS124_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS125_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS126_GlitchData : VitalGlitchDataType; + variable PPCMPLBWRDBUS127_GlitchData : VitalGlitchDataType; + variable PPCS0PLBADDRACK_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMBUSY0_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMBUSY1_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMBUSY2_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMBUSY3_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMIRQ0_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMIRQ1_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMIRQ2_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMIRQ3_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMRDERR0_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMRDERR1_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMRDERR2_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMRDERR3_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMWRERR0_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMWRERR1_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMWRERR2_GlitchData : VitalGlitchDataType; + variable PPCS0PLBMWRERR3_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDBTERM_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDCOMP_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDACK_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS0_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS1_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS2_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS3_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS4_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS5_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS6_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS7_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS8_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS9_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS10_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS11_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS12_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS13_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS14_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS15_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS16_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS17_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS18_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS19_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS20_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS21_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS22_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS23_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS24_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS25_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS26_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS27_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS28_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS29_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS30_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS31_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS32_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS33_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS34_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS35_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS36_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS37_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS38_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS39_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS40_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS41_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS42_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS43_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS44_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS45_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS46_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS47_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS48_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS49_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS50_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS51_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS52_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS53_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS54_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS55_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS56_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS57_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS58_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS59_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS60_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS61_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS62_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS63_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS64_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS65_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS66_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS67_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS68_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS69_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS70_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS71_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS72_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS73_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS74_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS75_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS76_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS77_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS78_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS79_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS80_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS81_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS82_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS83_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS84_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS85_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS86_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS87_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS88_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS89_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS90_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS91_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS92_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS93_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS94_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS95_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS96_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS97_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS98_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS99_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS100_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS101_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS102_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS103_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS104_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS105_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS106_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS107_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS108_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS109_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS110_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS111_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS112_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS113_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS114_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS115_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS116_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS117_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS118_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS119_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS120_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS121_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS122_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS123_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS124_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS125_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS126_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDDBUS127_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDWDADDR0_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDWDADDR1_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDWDADDR2_GlitchData : VitalGlitchDataType; + variable PPCS0PLBRDWDADDR3_GlitchData : VitalGlitchDataType; + variable PPCS0PLBREARBITRATE_GlitchData : VitalGlitchDataType; + variable PPCS0PLBSSIZE0_GlitchData : VitalGlitchDataType; + variable PPCS0PLBSSIZE1_GlitchData : VitalGlitchDataType; + variable PPCS0PLBWAIT_GlitchData : VitalGlitchDataType; + variable PPCS0PLBWRBTERM_GlitchData : VitalGlitchDataType; + variable PPCS0PLBWRCOMP_GlitchData : VitalGlitchDataType; + variable PPCS0PLBWRDACK_GlitchData : VitalGlitchDataType; + variable PPCS1PLBADDRACK_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMBUSY0_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMBUSY1_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMBUSY2_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMBUSY3_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMIRQ0_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMIRQ1_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMIRQ2_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMIRQ3_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMRDERR0_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMRDERR1_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMRDERR2_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMRDERR3_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMWRERR0_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMWRERR1_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMWRERR2_GlitchData : VitalGlitchDataType; + variable PPCS1PLBMWRERR3_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDBTERM_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDCOMP_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDACK_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS0_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS1_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS2_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS3_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS4_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS5_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS6_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS7_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS8_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS9_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS10_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS11_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS12_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS13_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS14_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS15_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS16_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS17_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS18_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS19_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS20_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS21_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS22_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS23_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS24_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS25_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS26_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS27_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS28_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS29_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS30_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS31_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS32_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS33_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS34_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS35_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS36_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS37_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS38_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS39_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS40_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS41_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS42_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS43_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS44_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS45_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS46_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS47_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS48_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS49_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS50_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS51_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS52_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS53_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS54_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS55_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS56_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS57_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS58_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS59_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS60_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS61_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS62_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS63_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS64_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS65_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS66_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS67_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS68_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS69_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS70_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS71_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS72_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS73_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS74_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS75_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS76_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS77_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS78_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS79_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS80_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS81_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS82_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS83_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS84_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS85_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS86_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS87_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS88_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS89_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS90_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS91_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS92_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS93_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS94_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS95_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS96_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS97_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS98_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS99_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS100_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS101_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS102_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS103_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS104_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS105_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS106_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS107_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS108_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS109_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS110_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS111_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS112_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS113_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS114_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS115_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS116_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS117_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS118_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS119_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS120_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS121_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS122_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS123_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS124_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS125_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS126_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDDBUS127_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDWDADDR0_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDWDADDR1_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDWDADDR2_GlitchData : VitalGlitchDataType; + variable PPCS1PLBRDWDADDR3_GlitchData : VitalGlitchDataType; + variable PPCS1PLBREARBITRATE_GlitchData : VitalGlitchDataType; + variable PPCS1PLBSSIZE0_GlitchData : VitalGlitchDataType; + variable PPCS1PLBSSIZE1_GlitchData : VitalGlitchDataType; + variable PPCS1PLBWAIT_GlitchData : VitalGlitchDataType; + variable PPCS1PLBWRBTERM_GlitchData : VitalGlitchDataType; + variable PPCS1PLBWRCOMP_GlitchData : VitalGlitchDataType; + variable PPCS1PLBWRDACK_GlitchData : VitalGlitchDataType; + variable APUFCMDECFPUOP_GlitchData : VitalGlitchDataType; + variable APUFCMDECLDSTXFERSIZE0_GlitchData : VitalGlitchDataType; + variable APUFCMDECLDSTXFERSIZE1_GlitchData : VitalGlitchDataType; + variable APUFCMDECLDSTXFERSIZE2_GlitchData : VitalGlitchDataType; + variable APUFCMDECLOAD_GlitchData : VitalGlitchDataType; + variable APUFCMDECNONAUTON_GlitchData : VitalGlitchDataType; + variable APUFCMDECSTORE_GlitchData : VitalGlitchDataType; + variable APUFCMDECUDI0_GlitchData : VitalGlitchDataType; + variable APUFCMDECUDI1_GlitchData : VitalGlitchDataType; + variable APUFCMDECUDI2_GlitchData : VitalGlitchDataType; + variable APUFCMDECUDI3_GlitchData : VitalGlitchDataType; + variable APUFCMDECUDIVALID_GlitchData : VitalGlitchDataType; + variable APUFCMENDIAN_GlitchData : VitalGlitchDataType; + variable APUFCMFLUSH_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION0_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION1_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION2_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION3_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION4_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION5_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION6_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION7_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION8_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION9_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION10_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION11_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION12_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION13_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION14_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION15_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION16_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION17_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION18_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION19_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION20_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION21_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION22_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION23_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION24_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION25_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION26_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION27_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION28_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION29_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION30_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRUCTION31_GlitchData : VitalGlitchDataType; + variable APUFCMINSTRVALID_GlitchData : VitalGlitchDataType; + variable APUFCMLOADBYTEADDR0_GlitchData : VitalGlitchDataType; + variable APUFCMLOADBYTEADDR1_GlitchData : VitalGlitchDataType; + variable APUFCMLOADBYTEADDR2_GlitchData : VitalGlitchDataType; + variable APUFCMLOADBYTEADDR3_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA0_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA1_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA2_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA3_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA4_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA5_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA6_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA7_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA8_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA9_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA10_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA11_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA12_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA13_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA14_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA15_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA16_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA17_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA18_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA19_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA20_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA21_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA22_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA23_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA24_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA25_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA26_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA27_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA28_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA29_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA30_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA31_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA32_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA33_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA34_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA35_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA36_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA37_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA38_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA39_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA40_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA41_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA42_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA43_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA44_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA45_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA46_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA47_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA48_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA49_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA50_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA51_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA52_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA53_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA54_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA55_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA56_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA57_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA58_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA59_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA60_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA61_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA62_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA63_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA64_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA65_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA66_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA67_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA68_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA69_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA70_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA71_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA72_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA73_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA74_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA75_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA76_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA77_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA78_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA79_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA80_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA81_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA82_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA83_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA84_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA85_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA86_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA87_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA88_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA89_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA90_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA91_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA92_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA93_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA94_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA95_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA96_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA97_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA98_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA99_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA100_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA101_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA102_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA103_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA104_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA105_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA106_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA107_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA108_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA109_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA110_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA111_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA112_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA113_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA114_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA115_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA116_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA117_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA118_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA119_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA120_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA121_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA122_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA123_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA124_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA125_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA126_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDATA127_GlitchData : VitalGlitchDataType; + variable APUFCMLOADDVALID_GlitchData : VitalGlitchDataType; + variable APUFCMMSRFE0_GlitchData : VitalGlitchDataType; + variable APUFCMMSRFE1_GlitchData : VitalGlitchDataType; + variable APUFCMNEXTINSTRREADY_GlitchData : VitalGlitchDataType; + variable APUFCMOPERANDVALID_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA0_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA1_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA2_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA3_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA4_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA5_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA6_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA7_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA8_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA9_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA10_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA11_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA12_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA13_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA14_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA15_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA16_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA17_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA18_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA19_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA20_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA21_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA22_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA23_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA24_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA25_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA26_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA27_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA28_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA29_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA30_GlitchData : VitalGlitchDataType; + variable APUFCMRADATA31_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA0_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA1_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA2_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA3_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA4_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA5_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA6_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA7_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA8_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA9_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA10_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA11_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA12_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA13_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA14_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA15_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA16_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA17_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA18_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA19_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA20_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA21_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA22_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA23_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA24_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA25_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA26_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA27_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA28_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA29_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA30_GlitchData : VitalGlitchDataType; + variable APUFCMRBDATA31_GlitchData : VitalGlitchDataType; + variable APUFCMWRITEBACKOK_GlitchData : VitalGlitchDataType; + variable C440CPMCORESLEEPREQ_GlitchData : VitalGlitchDataType; + variable C440CPMDECIRPTREQ_GlitchData : VitalGlitchDataType; + variable C440CPMFITIRPTREQ_GlitchData : VitalGlitchDataType; + variable C440CPMMSRCE_GlitchData : VitalGlitchDataType; + variable C440CPMMSREE_GlitchData : VitalGlitchDataType; + variable C440CPMTIMERRESETREQ_GlitchData : VitalGlitchDataType; + variable C440CPMWDIRPTREQ_GlitchData : VitalGlitchDataType; + variable C440DBGSYSTEMCONTROL0_GlitchData : VitalGlitchDataType; + variable C440DBGSYSTEMCONTROL1_GlitchData : VitalGlitchDataType; + variable C440DBGSYSTEMCONTROL2_GlitchData : VitalGlitchDataType; + variable C440DBGSYSTEMCONTROL3_GlitchData : VitalGlitchDataType; + variable C440DBGSYSTEMCONTROL4_GlitchData : VitalGlitchDataType; + variable C440DBGSYSTEMCONTROL5_GlitchData : VitalGlitchDataType; + variable C440DBGSYSTEMCONTROL6_GlitchData : VitalGlitchDataType; + variable C440DBGSYSTEMCONTROL7_GlitchData : VitalGlitchDataType; + variable C440JTGTDO_GlitchData : VitalGlitchDataType; + variable C440JTGTDOEN_GlitchData : VitalGlitchDataType; + variable C440MACHINECHECK_GlitchData : VitalGlitchDataType; + variable C440RSTCHIPRESETREQ_GlitchData : VitalGlitchDataType; + variable C440RSTCORERESETREQ_GlitchData : VitalGlitchDataType; + variable C440RSTSYSTEMRESETREQ_GlitchData : VitalGlitchDataType; + variable C440TRCBRANCHSTATUS0_GlitchData : VitalGlitchDataType; + variable C440TRCBRANCHSTATUS1_GlitchData : VitalGlitchDataType; + variable C440TRCBRANCHSTATUS2_GlitchData : VitalGlitchDataType; + variable C440TRCCYCLE_GlitchData : VitalGlitchDataType; + variable C440TRCEXECUTIONSTATUS0_GlitchData : VitalGlitchDataType; + variable C440TRCEXECUTIONSTATUS1_GlitchData : VitalGlitchDataType; + variable C440TRCEXECUTIONSTATUS2_GlitchData : VitalGlitchDataType; + variable C440TRCEXECUTIONSTATUS3_GlitchData : VitalGlitchDataType; + variable C440TRCEXECUTIONSTATUS4_GlitchData : VitalGlitchDataType; + variable C440TRCTRACESTATUS0_GlitchData : VitalGlitchDataType; + variable C440TRCTRACESTATUS1_GlitchData : VitalGlitchDataType; + variable C440TRCTRACESTATUS2_GlitchData : VitalGlitchDataType; + variable C440TRCTRACESTATUS3_GlitchData : VitalGlitchDataType; + variable C440TRCTRACESTATUS4_GlitchData : VitalGlitchDataType; + variable C440TRCTRACESTATUS5_GlitchData : VitalGlitchDataType; + variable C440TRCTRACESTATUS6_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTOUT_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE0_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE1_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE2_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE3_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE4_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE5_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE6_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE7_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE8_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE9_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE10_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE11_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE12_GlitchData : VitalGlitchDataType; + variable C440TRCTRIGGEREVENTTYPE13_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS0_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS1_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS2_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS3_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS4_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS5_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS6_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS7_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS8_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS9_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS10_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS11_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS12_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS13_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS14_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS15_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS16_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS17_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS18_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS19_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS20_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS21_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS22_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS23_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS24_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS25_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS26_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS27_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS28_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS29_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS30_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS31_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS32_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS33_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS34_GlitchData : VitalGlitchDataType; + variable MIMCADDRESS35_GlitchData : VitalGlitchDataType; + variable MIMCADDRESSVALID_GlitchData : VitalGlitchDataType; + variable MIMCBANKCONFLICT_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE0_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE1_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE2_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE3_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE4_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE5_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE6_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE7_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE8_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE9_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE10_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE11_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE12_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE13_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE14_GlitchData : VitalGlitchDataType; + variable MIMCBYTEENABLE15_GlitchData : VitalGlitchDataType; + variable MIMCREADNOTWRITE_GlitchData : VitalGlitchDataType; + variable MIMCROWCONFLICT_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA0_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA1_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA2_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA3_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA4_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA5_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA6_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA7_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA8_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA9_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA10_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA11_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA12_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA13_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA14_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA15_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA16_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA17_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA18_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA19_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA20_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA21_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA22_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA23_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA24_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA25_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA26_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA27_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA28_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA29_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA30_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA31_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA32_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA33_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA34_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA35_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA36_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA37_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA38_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA39_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA40_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA41_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA42_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA43_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA44_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA45_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA46_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA47_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA48_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA49_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA50_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA51_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA52_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA53_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA54_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA55_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA56_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA57_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA58_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA59_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA60_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA61_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA62_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA63_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA64_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA65_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA66_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA67_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA68_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA69_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA70_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA71_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA72_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA73_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA74_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA75_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA76_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA77_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA78_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA79_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA80_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA81_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA82_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA83_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA84_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA85_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA86_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA87_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA88_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA89_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA90_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA91_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA92_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA93_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA94_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA95_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA96_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA97_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA98_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA99_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA100_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA101_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA102_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA103_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA104_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA105_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA106_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA107_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA108_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA109_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA110_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA111_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA112_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA113_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA114_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA115_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA116_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA117_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA118_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA119_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA120_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA121_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA122_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA123_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA124_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA125_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA126_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATA127_GlitchData : VitalGlitchDataType; + variable MIMCWRITEDATAVALID_GlitchData : VitalGlitchDataType; + variable PPCCPMINTERCONNECTBUSY_GlitchData : VitalGlitchDataType; + variable PPCDSDCRACK_GlitchData : VitalGlitchDataType; + variable PPCDSDCRTIMEOUTWAIT_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN0_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN1_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN2_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN3_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN4_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN5_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN6_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN7_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN8_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN9_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN10_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN11_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN12_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN13_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN14_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN15_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN16_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN17_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN18_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN19_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN20_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN21_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN22_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN23_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN24_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN25_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN26_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN27_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN28_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN29_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN30_GlitchData : VitalGlitchDataType; + variable PPCDSDCRDBUSIN31_GlitchData : VitalGlitchDataType; + variable PPCEICINTERCONNECTIRQ_GlitchData : VitalGlitchDataType; +begin + + VitalPathDelay01 + ( + OutSignal => DMA0LLRSTENGINEACK, + GlitchData => DMA0LLRSTENGINEACK_GlitchData, + OutSignalName => "DMA0LLRSTENGINEACK", + OutTemp => DMA0LLRSTENGINEACK_OUT, + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLRXDSTRDYN, + GlitchData => DMA0LLRXDSTRDYN_GlitchData, + OutSignalName => "DMA0LLRXDSTRDYN", + OutTemp => DMA0LLRXDSTRDYN_OUT, + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(0), + GlitchData => DMA0LLTXD0_GlitchData, + OutSignalName => "DMA0LLTXD(0)", + OutTemp => DMA0LLTXD_OUT(0), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(1), + GlitchData => DMA0LLTXD1_GlitchData, + OutSignalName => "DMA0LLTXD(1)", + OutTemp => DMA0LLTXD_OUT(1), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(2), + GlitchData => DMA0LLTXD2_GlitchData, + OutSignalName => "DMA0LLTXD(2)", + OutTemp => DMA0LLTXD_OUT(2), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(3), + GlitchData => DMA0LLTXD3_GlitchData, + OutSignalName => "DMA0LLTXD(3)", + OutTemp => DMA0LLTXD_OUT(3), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(4), + GlitchData => DMA0LLTXD4_GlitchData, + OutSignalName => "DMA0LLTXD(4)", + OutTemp => DMA0LLTXD_OUT(4), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(5), + GlitchData => DMA0LLTXD5_GlitchData, + OutSignalName => "DMA0LLTXD(5)", + OutTemp => DMA0LLTXD_OUT(5), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(6), + GlitchData => DMA0LLTXD6_GlitchData, + OutSignalName => "DMA0LLTXD(6)", + OutTemp => DMA0LLTXD_OUT(6), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(7), + GlitchData => DMA0LLTXD7_GlitchData, + OutSignalName => "DMA0LLTXD(7)", + OutTemp => DMA0LLTXD_OUT(7), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(8), + GlitchData => DMA0LLTXD8_GlitchData, + OutSignalName => "DMA0LLTXD(8)", + OutTemp => DMA0LLTXD_OUT(8), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(9), + GlitchData => DMA0LLTXD9_GlitchData, + OutSignalName => "DMA0LLTXD(9)", + OutTemp => DMA0LLTXD_OUT(9), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(10), + GlitchData => DMA0LLTXD10_GlitchData, + OutSignalName => "DMA0LLTXD(10)", + OutTemp => DMA0LLTXD_OUT(10), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(11), + GlitchData => DMA0LLTXD11_GlitchData, + OutSignalName => "DMA0LLTXD(11)", + OutTemp => DMA0LLTXD_OUT(11), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(12), + GlitchData => DMA0LLTXD12_GlitchData, + OutSignalName => "DMA0LLTXD(12)", + OutTemp => DMA0LLTXD_OUT(12), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(13), + GlitchData => DMA0LLTXD13_GlitchData, + OutSignalName => "DMA0LLTXD(13)", + OutTemp => DMA0LLTXD_OUT(13), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(14), + GlitchData => DMA0LLTXD14_GlitchData, + OutSignalName => "DMA0LLTXD(14)", + OutTemp => DMA0LLTXD_OUT(14), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(15), + GlitchData => DMA0LLTXD15_GlitchData, + OutSignalName => "DMA0LLTXD(15)", + OutTemp => DMA0LLTXD_OUT(15), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(16), + GlitchData => DMA0LLTXD16_GlitchData, + OutSignalName => "DMA0LLTXD(16)", + OutTemp => DMA0LLTXD_OUT(16), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(17), + GlitchData => DMA0LLTXD17_GlitchData, + OutSignalName => "DMA0LLTXD(17)", + OutTemp => DMA0LLTXD_OUT(17), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(18), + GlitchData => DMA0LLTXD18_GlitchData, + OutSignalName => "DMA0LLTXD(18)", + OutTemp => DMA0LLTXD_OUT(18), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(19), + GlitchData => DMA0LLTXD19_GlitchData, + OutSignalName => "DMA0LLTXD(19)", + OutTemp => DMA0LLTXD_OUT(19), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(20), + GlitchData => DMA0LLTXD20_GlitchData, + OutSignalName => "DMA0LLTXD(20)", + OutTemp => DMA0LLTXD_OUT(20), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(21), + GlitchData => DMA0LLTXD21_GlitchData, + OutSignalName => "DMA0LLTXD(21)", + OutTemp => DMA0LLTXD_OUT(21), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(22), + GlitchData => DMA0LLTXD22_GlitchData, + OutSignalName => "DMA0LLTXD(22)", + OutTemp => DMA0LLTXD_OUT(22), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(23), + GlitchData => DMA0LLTXD23_GlitchData, + OutSignalName => "DMA0LLTXD(23)", + OutTemp => DMA0LLTXD_OUT(23), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(24), + GlitchData => DMA0LLTXD24_GlitchData, + OutSignalName => "DMA0LLTXD(24)", + OutTemp => DMA0LLTXD_OUT(24), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(25), + GlitchData => DMA0LLTXD25_GlitchData, + OutSignalName => "DMA0LLTXD(25)", + OutTemp => DMA0LLTXD_OUT(25), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(26), + GlitchData => DMA0LLTXD26_GlitchData, + OutSignalName => "DMA0LLTXD(26)", + OutTemp => DMA0LLTXD_OUT(26), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(27), + GlitchData => DMA0LLTXD27_GlitchData, + OutSignalName => "DMA0LLTXD(27)", + OutTemp => DMA0LLTXD_OUT(27), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(28), + GlitchData => DMA0LLTXD28_GlitchData, + OutSignalName => "DMA0LLTXD(28)", + OutTemp => DMA0LLTXD_OUT(28), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(29), + GlitchData => DMA0LLTXD29_GlitchData, + OutSignalName => "DMA0LLTXD(29)", + OutTemp => DMA0LLTXD_OUT(29), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(30), + GlitchData => DMA0LLTXD30_GlitchData, + OutSignalName => "DMA0LLTXD(30)", + OutTemp => DMA0LLTXD_OUT(30), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXD(31), + GlitchData => DMA0LLTXD31_GlitchData, + OutSignalName => "DMA0LLTXD(31)", + OutTemp => DMA0LLTXD_OUT(31), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXEOFN, + GlitchData => DMA0LLTXEOFN_GlitchData, + OutSignalName => "DMA0LLTXEOFN", + OutTemp => DMA0LLTXEOFN_OUT, + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXEOPN, + GlitchData => DMA0LLTXEOPN_GlitchData, + OutSignalName => "DMA0LLTXEOPN", + OutTemp => DMA0LLTXEOPN_OUT, + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXREM(0), + GlitchData => DMA0LLTXREM0_GlitchData, + OutSignalName => "DMA0LLTXREM(0)", + OutTemp => DMA0LLTXREM_OUT(0), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXREM(1), + GlitchData => DMA0LLTXREM1_GlitchData, + OutSignalName => "DMA0LLTXREM(1)", + OutTemp => DMA0LLTXREM_OUT(1), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXREM(2), + GlitchData => DMA0LLTXREM2_GlitchData, + OutSignalName => "DMA0LLTXREM(2)", + OutTemp => DMA0LLTXREM_OUT(2), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXREM(3), + GlitchData => DMA0LLTXREM3_GlitchData, + OutSignalName => "DMA0LLTXREM(3)", + OutTemp => DMA0LLTXREM_OUT(3), + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXSOFN, + GlitchData => DMA0LLTXSOFN_GlitchData, + OutSignalName => "DMA0LLTXSOFN", + OutTemp => DMA0LLTXSOFN_OUT, + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXSOPN, + GlitchData => DMA0LLTXSOPN_GlitchData, + OutSignalName => "DMA0LLTXSOPN", + OutTemp => DMA0LLTXSOPN_OUT, + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0LLTXSRCRDYN, + GlitchData => DMA0LLTXSRCRDYN_GlitchData, + OutSignalName => "DMA0LLTXSRCRDYN", + OutTemp => DMA0LLTXSRCRDYN_OUT, + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0RXIRQ, + GlitchData => DMA0RXIRQ_GlitchData, + OutSignalName => "DMA0RXIRQ", + OutTemp => DMA0RXIRQ_OUT, + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA0TXIRQ, + GlitchData => DMA0TXIRQ_GlitchData, + OutSignalName => "DMA0TXIRQ", + OutTemp => DMA0TXIRQ_OUT, + Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLRSTENGINEACK, + GlitchData => DMA1LLRSTENGINEACK_GlitchData, + OutSignalName => "DMA1LLRSTENGINEACK", + OutTemp => DMA1LLRSTENGINEACK_OUT, + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLRXDSTRDYN, + GlitchData => DMA1LLRXDSTRDYN_GlitchData, + OutSignalName => "DMA1LLRXDSTRDYN", + OutTemp => DMA1LLRXDSTRDYN_OUT, + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(0), + GlitchData => DMA1LLTXD0_GlitchData, + OutSignalName => "DMA1LLTXD(0)", + OutTemp => DMA1LLTXD_OUT(0), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(1), + GlitchData => DMA1LLTXD1_GlitchData, + OutSignalName => "DMA1LLTXD(1)", + OutTemp => DMA1LLTXD_OUT(1), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(2), + GlitchData => DMA1LLTXD2_GlitchData, + OutSignalName => "DMA1LLTXD(2)", + OutTemp => DMA1LLTXD_OUT(2), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(3), + GlitchData => DMA1LLTXD3_GlitchData, + OutSignalName => "DMA1LLTXD(3)", + OutTemp => DMA1LLTXD_OUT(3), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(4), + GlitchData => DMA1LLTXD4_GlitchData, + OutSignalName => "DMA1LLTXD(4)", + OutTemp => DMA1LLTXD_OUT(4), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(5), + GlitchData => DMA1LLTXD5_GlitchData, + OutSignalName => "DMA1LLTXD(5)", + OutTemp => DMA1LLTXD_OUT(5), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(6), + GlitchData => DMA1LLTXD6_GlitchData, + OutSignalName => "DMA1LLTXD(6)", + OutTemp => DMA1LLTXD_OUT(6), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(7), + GlitchData => DMA1LLTXD7_GlitchData, + OutSignalName => "DMA1LLTXD(7)", + OutTemp => DMA1LLTXD_OUT(7), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(8), + GlitchData => DMA1LLTXD8_GlitchData, + OutSignalName => "DMA1LLTXD(8)", + OutTemp => DMA1LLTXD_OUT(8), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(9), + GlitchData => DMA1LLTXD9_GlitchData, + OutSignalName => "DMA1LLTXD(9)", + OutTemp => DMA1LLTXD_OUT(9), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(10), + GlitchData => DMA1LLTXD10_GlitchData, + OutSignalName => "DMA1LLTXD(10)", + OutTemp => DMA1LLTXD_OUT(10), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(11), + GlitchData => DMA1LLTXD11_GlitchData, + OutSignalName => "DMA1LLTXD(11)", + OutTemp => DMA1LLTXD_OUT(11), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(12), + GlitchData => DMA1LLTXD12_GlitchData, + OutSignalName => "DMA1LLTXD(12)", + OutTemp => DMA1LLTXD_OUT(12), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(13), + GlitchData => DMA1LLTXD13_GlitchData, + OutSignalName => "DMA1LLTXD(13)", + OutTemp => DMA1LLTXD_OUT(13), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(14), + GlitchData => DMA1LLTXD14_GlitchData, + OutSignalName => "DMA1LLTXD(14)", + OutTemp => DMA1LLTXD_OUT(14), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(15), + GlitchData => DMA1LLTXD15_GlitchData, + OutSignalName => "DMA1LLTXD(15)", + OutTemp => DMA1LLTXD_OUT(15), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(16), + GlitchData => DMA1LLTXD16_GlitchData, + OutSignalName => "DMA1LLTXD(16)", + OutTemp => DMA1LLTXD_OUT(16), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(17), + GlitchData => DMA1LLTXD17_GlitchData, + OutSignalName => "DMA1LLTXD(17)", + OutTemp => DMA1LLTXD_OUT(17), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(18), + GlitchData => DMA1LLTXD18_GlitchData, + OutSignalName => "DMA1LLTXD(18)", + OutTemp => DMA1LLTXD_OUT(18), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(19), + GlitchData => DMA1LLTXD19_GlitchData, + OutSignalName => "DMA1LLTXD(19)", + OutTemp => DMA1LLTXD_OUT(19), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(20), + GlitchData => DMA1LLTXD20_GlitchData, + OutSignalName => "DMA1LLTXD(20)", + OutTemp => DMA1LLTXD_OUT(20), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(21), + GlitchData => DMA1LLTXD21_GlitchData, + OutSignalName => "DMA1LLTXD(21)", + OutTemp => DMA1LLTXD_OUT(21), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(22), + GlitchData => DMA1LLTXD22_GlitchData, + OutSignalName => "DMA1LLTXD(22)", + OutTemp => DMA1LLTXD_OUT(22), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(23), + GlitchData => DMA1LLTXD23_GlitchData, + OutSignalName => "DMA1LLTXD(23)", + OutTemp => DMA1LLTXD_OUT(23), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(24), + GlitchData => DMA1LLTXD24_GlitchData, + OutSignalName => "DMA1LLTXD(24)", + OutTemp => DMA1LLTXD_OUT(24), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(25), + GlitchData => DMA1LLTXD25_GlitchData, + OutSignalName => "DMA1LLTXD(25)", + OutTemp => DMA1LLTXD_OUT(25), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(26), + GlitchData => DMA1LLTXD26_GlitchData, + OutSignalName => "DMA1LLTXD(26)", + OutTemp => DMA1LLTXD_OUT(26), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(27), + GlitchData => DMA1LLTXD27_GlitchData, + OutSignalName => "DMA1LLTXD(27)", + OutTemp => DMA1LLTXD_OUT(27), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(28), + GlitchData => DMA1LLTXD28_GlitchData, + OutSignalName => "DMA1LLTXD(28)", + OutTemp => DMA1LLTXD_OUT(28), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(29), + GlitchData => DMA1LLTXD29_GlitchData, + OutSignalName => "DMA1LLTXD(29)", + OutTemp => DMA1LLTXD_OUT(29), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(30), + GlitchData => DMA1LLTXD30_GlitchData, + OutSignalName => "DMA1LLTXD(30)", + OutTemp => DMA1LLTXD_OUT(30), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXD(31), + GlitchData => DMA1LLTXD31_GlitchData, + OutSignalName => "DMA1LLTXD(31)", + OutTemp => DMA1LLTXD_OUT(31), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXEOFN, + GlitchData => DMA1LLTXEOFN_GlitchData, + OutSignalName => "DMA1LLTXEOFN", + OutTemp => DMA1LLTXEOFN_OUT, + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXEOPN, + GlitchData => DMA1LLTXEOPN_GlitchData, + OutSignalName => "DMA1LLTXEOPN", + OutTemp => DMA1LLTXEOPN_OUT, + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXREM(0), + GlitchData => DMA1LLTXREM0_GlitchData, + OutSignalName => "DMA1LLTXREM(0)", + OutTemp => DMA1LLTXREM_OUT(0), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXREM(1), + GlitchData => DMA1LLTXREM1_GlitchData, + OutSignalName => "DMA1LLTXREM(1)", + OutTemp => DMA1LLTXREM_OUT(1), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXREM(2), + GlitchData => DMA1LLTXREM2_GlitchData, + OutSignalName => "DMA1LLTXREM(2)", + OutTemp => DMA1LLTXREM_OUT(2), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXREM(3), + GlitchData => DMA1LLTXREM3_GlitchData, + OutSignalName => "DMA1LLTXREM(3)", + OutTemp => DMA1LLTXREM_OUT(3), + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXSOFN, + GlitchData => DMA1LLTXSOFN_GlitchData, + OutSignalName => "DMA1LLTXSOFN", + OutTemp => DMA1LLTXSOFN_OUT, + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXSOPN, + GlitchData => DMA1LLTXSOPN_GlitchData, + OutSignalName => "DMA1LLTXSOPN", + OutTemp => DMA1LLTXSOPN_OUT, + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1LLTXSRCRDYN, + GlitchData => DMA1LLTXSRCRDYN_GlitchData, + OutSignalName => "DMA1LLTXSRCRDYN", + OutTemp => DMA1LLTXSRCRDYN_OUT, + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1RXIRQ, + GlitchData => DMA1RXIRQ_GlitchData, + OutSignalName => "DMA1RXIRQ", + OutTemp => DMA1RXIRQ_OUT, + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA1TXIRQ, + GlitchData => DMA1TXIRQ_GlitchData, + OutSignalName => "DMA1TXIRQ", + OutTemp => DMA1TXIRQ_OUT, + Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLRSTENGINEACK, + GlitchData => DMA2LLRSTENGINEACK_GlitchData, + OutSignalName => "DMA2LLRSTENGINEACK", + OutTemp => DMA2LLRSTENGINEACK_OUT, + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLRXDSTRDYN, + GlitchData => DMA2LLRXDSTRDYN_GlitchData, + OutSignalName => "DMA2LLRXDSTRDYN", + OutTemp => DMA2LLRXDSTRDYN_OUT, + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(0), + GlitchData => DMA2LLTXD0_GlitchData, + OutSignalName => "DMA2LLTXD(0)", + OutTemp => DMA2LLTXD_OUT(0), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(1), + GlitchData => DMA2LLTXD1_GlitchData, + OutSignalName => "DMA2LLTXD(1)", + OutTemp => DMA2LLTXD_OUT(1), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(2), + GlitchData => DMA2LLTXD2_GlitchData, + OutSignalName => "DMA2LLTXD(2)", + OutTemp => DMA2LLTXD_OUT(2), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(3), + GlitchData => DMA2LLTXD3_GlitchData, + OutSignalName => "DMA2LLTXD(3)", + OutTemp => DMA2LLTXD_OUT(3), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(4), + GlitchData => DMA2LLTXD4_GlitchData, + OutSignalName => "DMA2LLTXD(4)", + OutTemp => DMA2LLTXD_OUT(4), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(5), + GlitchData => DMA2LLTXD5_GlitchData, + OutSignalName => "DMA2LLTXD(5)", + OutTemp => DMA2LLTXD_OUT(5), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(6), + GlitchData => DMA2LLTXD6_GlitchData, + OutSignalName => "DMA2LLTXD(6)", + OutTemp => DMA2LLTXD_OUT(6), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(7), + GlitchData => DMA2LLTXD7_GlitchData, + OutSignalName => "DMA2LLTXD(7)", + OutTemp => DMA2LLTXD_OUT(7), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(8), + GlitchData => DMA2LLTXD8_GlitchData, + OutSignalName => "DMA2LLTXD(8)", + OutTemp => DMA2LLTXD_OUT(8), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(9), + GlitchData => DMA2LLTXD9_GlitchData, + OutSignalName => "DMA2LLTXD(9)", + OutTemp => DMA2LLTXD_OUT(9), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(10), + GlitchData => DMA2LLTXD10_GlitchData, + OutSignalName => "DMA2LLTXD(10)", + OutTemp => DMA2LLTXD_OUT(10), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(11), + GlitchData => DMA2LLTXD11_GlitchData, + OutSignalName => "DMA2LLTXD(11)", + OutTemp => DMA2LLTXD_OUT(11), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(12), + GlitchData => DMA2LLTXD12_GlitchData, + OutSignalName => "DMA2LLTXD(12)", + OutTemp => DMA2LLTXD_OUT(12), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(13), + GlitchData => DMA2LLTXD13_GlitchData, + OutSignalName => "DMA2LLTXD(13)", + OutTemp => DMA2LLTXD_OUT(13), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(14), + GlitchData => DMA2LLTXD14_GlitchData, + OutSignalName => "DMA2LLTXD(14)", + OutTemp => DMA2LLTXD_OUT(14), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(15), + GlitchData => DMA2LLTXD15_GlitchData, + OutSignalName => "DMA2LLTXD(15)", + OutTemp => DMA2LLTXD_OUT(15), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(16), + GlitchData => DMA2LLTXD16_GlitchData, + OutSignalName => "DMA2LLTXD(16)", + OutTemp => DMA2LLTXD_OUT(16), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(17), + GlitchData => DMA2LLTXD17_GlitchData, + OutSignalName => "DMA2LLTXD(17)", + OutTemp => DMA2LLTXD_OUT(17), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(18), + GlitchData => DMA2LLTXD18_GlitchData, + OutSignalName => "DMA2LLTXD(18)", + OutTemp => DMA2LLTXD_OUT(18), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(19), + GlitchData => DMA2LLTXD19_GlitchData, + OutSignalName => "DMA2LLTXD(19)", + OutTemp => DMA2LLTXD_OUT(19), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(20), + GlitchData => DMA2LLTXD20_GlitchData, + OutSignalName => "DMA2LLTXD(20)", + OutTemp => DMA2LLTXD_OUT(20), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(21), + GlitchData => DMA2LLTXD21_GlitchData, + OutSignalName => "DMA2LLTXD(21)", + OutTemp => DMA2LLTXD_OUT(21), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(22), + GlitchData => DMA2LLTXD22_GlitchData, + OutSignalName => "DMA2LLTXD(22)", + OutTemp => DMA2LLTXD_OUT(22), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(23), + GlitchData => DMA2LLTXD23_GlitchData, + OutSignalName => "DMA2LLTXD(23)", + OutTemp => DMA2LLTXD_OUT(23), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(24), + GlitchData => DMA2LLTXD24_GlitchData, + OutSignalName => "DMA2LLTXD(24)", + OutTemp => DMA2LLTXD_OUT(24), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(25), + GlitchData => DMA2LLTXD25_GlitchData, + OutSignalName => "DMA2LLTXD(25)", + OutTemp => DMA2LLTXD_OUT(25), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(26), + GlitchData => DMA2LLTXD26_GlitchData, + OutSignalName => "DMA2LLTXD(26)", + OutTemp => DMA2LLTXD_OUT(26), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(27), + GlitchData => DMA2LLTXD27_GlitchData, + OutSignalName => "DMA2LLTXD(27)", + OutTemp => DMA2LLTXD_OUT(27), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(28), + GlitchData => DMA2LLTXD28_GlitchData, + OutSignalName => "DMA2LLTXD(28)", + OutTemp => DMA2LLTXD_OUT(28), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(29), + GlitchData => DMA2LLTXD29_GlitchData, + OutSignalName => "DMA2LLTXD(29)", + OutTemp => DMA2LLTXD_OUT(29), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(30), + GlitchData => DMA2LLTXD30_GlitchData, + OutSignalName => "DMA2LLTXD(30)", + OutTemp => DMA2LLTXD_OUT(30), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXD(31), + GlitchData => DMA2LLTXD31_GlitchData, + OutSignalName => "DMA2LLTXD(31)", + OutTemp => DMA2LLTXD_OUT(31), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXEOFN, + GlitchData => DMA2LLTXEOFN_GlitchData, + OutSignalName => "DMA2LLTXEOFN", + OutTemp => DMA2LLTXEOFN_OUT, + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXEOPN, + GlitchData => DMA2LLTXEOPN_GlitchData, + OutSignalName => "DMA2LLTXEOPN", + OutTemp => DMA2LLTXEOPN_OUT, + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXREM(0), + GlitchData => DMA2LLTXREM0_GlitchData, + OutSignalName => "DMA2LLTXREM(0)", + OutTemp => DMA2LLTXREM_OUT(0), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXREM(1), + GlitchData => DMA2LLTXREM1_GlitchData, + OutSignalName => "DMA2LLTXREM(1)", + OutTemp => DMA2LLTXREM_OUT(1), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXREM(2), + GlitchData => DMA2LLTXREM2_GlitchData, + OutSignalName => "DMA2LLTXREM(2)", + OutTemp => DMA2LLTXREM_OUT(2), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXREM(3), + GlitchData => DMA2LLTXREM3_GlitchData, + OutSignalName => "DMA2LLTXREM(3)", + OutTemp => DMA2LLTXREM_OUT(3), + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXSOFN, + GlitchData => DMA2LLTXSOFN_GlitchData, + OutSignalName => "DMA2LLTXSOFN", + OutTemp => DMA2LLTXSOFN_OUT, + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXSOPN, + GlitchData => DMA2LLTXSOPN_GlitchData, + OutSignalName => "DMA2LLTXSOPN", + OutTemp => DMA2LLTXSOPN_OUT, + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2LLTXSRCRDYN, + GlitchData => DMA2LLTXSRCRDYN_GlitchData, + OutSignalName => "DMA2LLTXSRCRDYN", + OutTemp => DMA2LLTXSRCRDYN_OUT, + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2RXIRQ, + GlitchData => DMA2RXIRQ_GlitchData, + OutSignalName => "DMA2RXIRQ", + OutTemp => DMA2RXIRQ_OUT, + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA2TXIRQ, + GlitchData => DMA2TXIRQ_GlitchData, + OutSignalName => "DMA2TXIRQ", + OutTemp => DMA2TXIRQ_OUT, + Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLRSTENGINEACK, + GlitchData => DMA3LLRSTENGINEACK_GlitchData, + OutSignalName => "DMA3LLRSTENGINEACK", + OutTemp => DMA3LLRSTENGINEACK_OUT, + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLRXDSTRDYN, + GlitchData => DMA3LLRXDSTRDYN_GlitchData, + OutSignalName => "DMA3LLRXDSTRDYN", + OutTemp => DMA3LLRXDSTRDYN_OUT, + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(0), + GlitchData => DMA3LLTXD0_GlitchData, + OutSignalName => "DMA3LLTXD(0)", + OutTemp => DMA3LLTXD_OUT(0), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(1), + GlitchData => DMA3LLTXD1_GlitchData, + OutSignalName => "DMA3LLTXD(1)", + OutTemp => DMA3LLTXD_OUT(1), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(2), + GlitchData => DMA3LLTXD2_GlitchData, + OutSignalName => "DMA3LLTXD(2)", + OutTemp => DMA3LLTXD_OUT(2), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(3), + GlitchData => DMA3LLTXD3_GlitchData, + OutSignalName => "DMA3LLTXD(3)", + OutTemp => DMA3LLTXD_OUT(3), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(4), + GlitchData => DMA3LLTXD4_GlitchData, + OutSignalName => "DMA3LLTXD(4)", + OutTemp => DMA3LLTXD_OUT(4), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(5), + GlitchData => DMA3LLTXD5_GlitchData, + OutSignalName => "DMA3LLTXD(5)", + OutTemp => DMA3LLTXD_OUT(5), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(6), + GlitchData => DMA3LLTXD6_GlitchData, + OutSignalName => "DMA3LLTXD(6)", + OutTemp => DMA3LLTXD_OUT(6), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(7), + GlitchData => DMA3LLTXD7_GlitchData, + OutSignalName => "DMA3LLTXD(7)", + OutTemp => DMA3LLTXD_OUT(7), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(8), + GlitchData => DMA3LLTXD8_GlitchData, + OutSignalName => "DMA3LLTXD(8)", + OutTemp => DMA3LLTXD_OUT(8), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(9), + GlitchData => DMA3LLTXD9_GlitchData, + OutSignalName => "DMA3LLTXD(9)", + OutTemp => DMA3LLTXD_OUT(9), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(10), + GlitchData => DMA3LLTXD10_GlitchData, + OutSignalName => "DMA3LLTXD(10)", + OutTemp => DMA3LLTXD_OUT(10), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(11), + GlitchData => DMA3LLTXD11_GlitchData, + OutSignalName => "DMA3LLTXD(11)", + OutTemp => DMA3LLTXD_OUT(11), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(12), + GlitchData => DMA3LLTXD12_GlitchData, + OutSignalName => "DMA3LLTXD(12)", + OutTemp => DMA3LLTXD_OUT(12), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(13), + GlitchData => DMA3LLTXD13_GlitchData, + OutSignalName => "DMA3LLTXD(13)", + OutTemp => DMA3LLTXD_OUT(13), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(14), + GlitchData => DMA3LLTXD14_GlitchData, + OutSignalName => "DMA3LLTXD(14)", + OutTemp => DMA3LLTXD_OUT(14), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(15), + GlitchData => DMA3LLTXD15_GlitchData, + OutSignalName => "DMA3LLTXD(15)", + OutTemp => DMA3LLTXD_OUT(15), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(16), + GlitchData => DMA3LLTXD16_GlitchData, + OutSignalName => "DMA3LLTXD(16)", + OutTemp => DMA3LLTXD_OUT(16), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(17), + GlitchData => DMA3LLTXD17_GlitchData, + OutSignalName => "DMA3LLTXD(17)", + OutTemp => DMA3LLTXD_OUT(17), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(18), + GlitchData => DMA3LLTXD18_GlitchData, + OutSignalName => "DMA3LLTXD(18)", + OutTemp => DMA3LLTXD_OUT(18), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(19), + GlitchData => DMA3LLTXD19_GlitchData, + OutSignalName => "DMA3LLTXD(19)", + OutTemp => DMA3LLTXD_OUT(19), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(20), + GlitchData => DMA3LLTXD20_GlitchData, + OutSignalName => "DMA3LLTXD(20)", + OutTemp => DMA3LLTXD_OUT(20), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(21), + GlitchData => DMA3LLTXD21_GlitchData, + OutSignalName => "DMA3LLTXD(21)", + OutTemp => DMA3LLTXD_OUT(21), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(22), + GlitchData => DMA3LLTXD22_GlitchData, + OutSignalName => "DMA3LLTXD(22)", + OutTemp => DMA3LLTXD_OUT(22), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(23), + GlitchData => DMA3LLTXD23_GlitchData, + OutSignalName => "DMA3LLTXD(23)", + OutTemp => DMA3LLTXD_OUT(23), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(24), + GlitchData => DMA3LLTXD24_GlitchData, + OutSignalName => "DMA3LLTXD(24)", + OutTemp => DMA3LLTXD_OUT(24), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(25), + GlitchData => DMA3LLTXD25_GlitchData, + OutSignalName => "DMA3LLTXD(25)", + OutTemp => DMA3LLTXD_OUT(25), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(26), + GlitchData => DMA3LLTXD26_GlitchData, + OutSignalName => "DMA3LLTXD(26)", + OutTemp => DMA3LLTXD_OUT(26), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(27), + GlitchData => DMA3LLTXD27_GlitchData, + OutSignalName => "DMA3LLTXD(27)", + OutTemp => DMA3LLTXD_OUT(27), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(28), + GlitchData => DMA3LLTXD28_GlitchData, + OutSignalName => "DMA3LLTXD(28)", + OutTemp => DMA3LLTXD_OUT(28), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(29), + GlitchData => DMA3LLTXD29_GlitchData, + OutSignalName => "DMA3LLTXD(29)", + OutTemp => DMA3LLTXD_OUT(29), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(30), + GlitchData => DMA3LLTXD30_GlitchData, + OutSignalName => "DMA3LLTXD(30)", + OutTemp => DMA3LLTXD_OUT(30), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXD(31), + GlitchData => DMA3LLTXD31_GlitchData, + OutSignalName => "DMA3LLTXD(31)", + OutTemp => DMA3LLTXD_OUT(31), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXEOFN, + GlitchData => DMA3LLTXEOFN_GlitchData, + OutSignalName => "DMA3LLTXEOFN", + OutTemp => DMA3LLTXEOFN_OUT, + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXEOPN, + GlitchData => DMA3LLTXEOPN_GlitchData, + OutSignalName => "DMA3LLTXEOPN", + OutTemp => DMA3LLTXEOPN_OUT, + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXREM(0), + GlitchData => DMA3LLTXREM0_GlitchData, + OutSignalName => "DMA3LLTXREM(0)", + OutTemp => DMA3LLTXREM_OUT(0), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXREM(1), + GlitchData => DMA3LLTXREM1_GlitchData, + OutSignalName => "DMA3LLTXREM(1)", + OutTemp => DMA3LLTXREM_OUT(1), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXREM(2), + GlitchData => DMA3LLTXREM2_GlitchData, + OutSignalName => "DMA3LLTXREM(2)", + OutTemp => DMA3LLTXREM_OUT(2), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXREM(3), + GlitchData => DMA3LLTXREM3_GlitchData, + OutSignalName => "DMA3LLTXREM(3)", + OutTemp => DMA3LLTXREM_OUT(3), + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXSOFN, + GlitchData => DMA3LLTXSOFN_GlitchData, + OutSignalName => "DMA3LLTXSOFN", + OutTemp => DMA3LLTXSOFN_OUT, + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXSOPN, + GlitchData => DMA3LLTXSOPN_GlitchData, + OutSignalName => "DMA3LLTXSOPN", + OutTemp => DMA3LLTXSOPN_OUT, + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3LLTXSRCRDYN, + GlitchData => DMA3LLTXSRCRDYN_GlitchData, + OutSignalName => "DMA3LLTXSRCRDYN", + OutTemp => DMA3LLTXSRCRDYN_OUT, + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3RXIRQ, + GlitchData => DMA3RXIRQ_GlitchData, + OutSignalName => "DMA3RXIRQ", + OutTemp => DMA3RXIRQ_OUT, + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => DMA3TXIRQ, + GlitchData => DMA3TXIRQ_GlitchData, + OutSignalName => "DMA3TXIRQ", + OutTemp => DMA3TXIRQ_OUT, + Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(0), + GlitchData => PPCDMDCRABUS0_GlitchData, + OutSignalName => "PPCDMDCRABUS(0)", + OutTemp => PPCDMDCRABUS_OUT(0), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(1), + GlitchData => PPCDMDCRABUS1_GlitchData, + OutSignalName => "PPCDMDCRABUS(1)", + OutTemp => PPCDMDCRABUS_OUT(1), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(2), + GlitchData => PPCDMDCRABUS2_GlitchData, + OutSignalName => "PPCDMDCRABUS(2)", + OutTemp => PPCDMDCRABUS_OUT(2), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(3), + GlitchData => PPCDMDCRABUS3_GlitchData, + OutSignalName => "PPCDMDCRABUS(3)", + OutTemp => PPCDMDCRABUS_OUT(3), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(4), + GlitchData => PPCDMDCRABUS4_GlitchData, + OutSignalName => "PPCDMDCRABUS(4)", + OutTemp => PPCDMDCRABUS_OUT(4), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(5), + GlitchData => PPCDMDCRABUS5_GlitchData, + OutSignalName => "PPCDMDCRABUS(5)", + OutTemp => PPCDMDCRABUS_OUT(5), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(6), + GlitchData => PPCDMDCRABUS6_GlitchData, + OutSignalName => "PPCDMDCRABUS(6)", + OutTemp => PPCDMDCRABUS_OUT(6), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(7), + GlitchData => PPCDMDCRABUS7_GlitchData, + OutSignalName => "PPCDMDCRABUS(7)", + OutTemp => PPCDMDCRABUS_OUT(7), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(8), + GlitchData => PPCDMDCRABUS8_GlitchData, + OutSignalName => "PPCDMDCRABUS(8)", + OutTemp => PPCDMDCRABUS_OUT(8), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRABUS(9), + GlitchData => PPCDMDCRABUS9_GlitchData, + OutSignalName => "PPCDMDCRABUS(9)", + OutTemp => PPCDMDCRABUS_OUT(9), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(0), + GlitchData => PPCDMDCRDBUSOUT0_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(0)", + OutTemp => PPCDMDCRDBUSOUT_OUT(0), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(1), + GlitchData => PPCDMDCRDBUSOUT1_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(1)", + OutTemp => PPCDMDCRDBUSOUT_OUT(1), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(2), + GlitchData => PPCDMDCRDBUSOUT2_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(2)", + OutTemp => PPCDMDCRDBUSOUT_OUT(2), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(3), + GlitchData => PPCDMDCRDBUSOUT3_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(3)", + OutTemp => PPCDMDCRDBUSOUT_OUT(3), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(4), + GlitchData => PPCDMDCRDBUSOUT4_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(4)", + OutTemp => PPCDMDCRDBUSOUT_OUT(4), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(5), + GlitchData => PPCDMDCRDBUSOUT5_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(5)", + OutTemp => PPCDMDCRDBUSOUT_OUT(5), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(6), + GlitchData => PPCDMDCRDBUSOUT6_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(6)", + OutTemp => PPCDMDCRDBUSOUT_OUT(6), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(7), + GlitchData => PPCDMDCRDBUSOUT7_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(7)", + OutTemp => PPCDMDCRDBUSOUT_OUT(7), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(8), + GlitchData => PPCDMDCRDBUSOUT8_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(8)", + OutTemp => PPCDMDCRDBUSOUT_OUT(8), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(9), + GlitchData => PPCDMDCRDBUSOUT9_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(9)", + OutTemp => PPCDMDCRDBUSOUT_OUT(9), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(10), + GlitchData => PPCDMDCRDBUSOUT10_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(10)", + OutTemp => PPCDMDCRDBUSOUT_OUT(10), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(11), + GlitchData => PPCDMDCRDBUSOUT11_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(11)", + OutTemp => PPCDMDCRDBUSOUT_OUT(11), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(12), + GlitchData => PPCDMDCRDBUSOUT12_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(12)", + OutTemp => PPCDMDCRDBUSOUT_OUT(12), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(13), + GlitchData => PPCDMDCRDBUSOUT13_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(13)", + OutTemp => PPCDMDCRDBUSOUT_OUT(13), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(14), + GlitchData => PPCDMDCRDBUSOUT14_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(14)", + OutTemp => PPCDMDCRDBUSOUT_OUT(14), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(15), + GlitchData => PPCDMDCRDBUSOUT15_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(15)", + OutTemp => PPCDMDCRDBUSOUT_OUT(15), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(16), + GlitchData => PPCDMDCRDBUSOUT16_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(16)", + OutTemp => PPCDMDCRDBUSOUT_OUT(16), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(17), + GlitchData => PPCDMDCRDBUSOUT17_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(17)", + OutTemp => PPCDMDCRDBUSOUT_OUT(17), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(18), + GlitchData => PPCDMDCRDBUSOUT18_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(18)", + OutTemp => PPCDMDCRDBUSOUT_OUT(18), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(19), + GlitchData => PPCDMDCRDBUSOUT19_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(19)", + OutTemp => PPCDMDCRDBUSOUT_OUT(19), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(20), + GlitchData => PPCDMDCRDBUSOUT20_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(20)", + OutTemp => PPCDMDCRDBUSOUT_OUT(20), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(21), + GlitchData => PPCDMDCRDBUSOUT21_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(21)", + OutTemp => PPCDMDCRDBUSOUT_OUT(21), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(22), + GlitchData => PPCDMDCRDBUSOUT22_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(22)", + OutTemp => PPCDMDCRDBUSOUT_OUT(22), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(23), + GlitchData => PPCDMDCRDBUSOUT23_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(23)", + OutTemp => PPCDMDCRDBUSOUT_OUT(23), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(24), + GlitchData => PPCDMDCRDBUSOUT24_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(24)", + OutTemp => PPCDMDCRDBUSOUT_OUT(24), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(25), + GlitchData => PPCDMDCRDBUSOUT25_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(25)", + OutTemp => PPCDMDCRDBUSOUT_OUT(25), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(26), + GlitchData => PPCDMDCRDBUSOUT26_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(26)", + OutTemp => PPCDMDCRDBUSOUT_OUT(26), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(27), + GlitchData => PPCDMDCRDBUSOUT27_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(27)", + OutTemp => PPCDMDCRDBUSOUT_OUT(27), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(28), + GlitchData => PPCDMDCRDBUSOUT28_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(28)", + OutTemp => PPCDMDCRDBUSOUT_OUT(28), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(29), + GlitchData => PPCDMDCRDBUSOUT29_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(29)", + OutTemp => PPCDMDCRDBUSOUT_OUT(29), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(30), + GlitchData => PPCDMDCRDBUSOUT30_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(30)", + OutTemp => PPCDMDCRDBUSOUT_OUT(30), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRDBUSOUT(31), + GlitchData => PPCDMDCRDBUSOUT31_GlitchData, + OutSignalName => "PPCDMDCRDBUSOUT(31)", + OutTemp => PPCDMDCRDBUSOUT_OUT(31), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRREAD, + GlitchData => PPCDMDCRREAD_GlitchData, + OutSignalName => "PPCDMDCRREAD", + OutTemp => PPCDMDCRREAD_OUT, + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRUABUS(20), + GlitchData => PPCDMDCRUABUS20_GlitchData, + OutSignalName => "PPCDMDCRUABUS(20)", + OutTemp => PPCDMDCRUABUS_OUT(20), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRUABUS(21), + GlitchData => PPCDMDCRUABUS21_GlitchData, + OutSignalName => "PPCDMDCRUABUS(21)", + OutTemp => PPCDMDCRUABUS_OUT(21), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDMDCRWRITE, + GlitchData => PPCDMDCRWRITE_GlitchData, + OutSignalName => "PPCDMDCRWRITE", + OutTemp => PPCDMDCRWRITE_OUT, + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABORT, + GlitchData => PPCMPLBABORT_GlitchData, + OutSignalName => "PPCMPLBABORT", + OutTemp => PPCMPLBABORT_OUT, + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(0), + GlitchData => PPCMPLBABUS0_GlitchData, + OutSignalName => "PPCMPLBABUS(0)", + OutTemp => PPCMPLBABUS_OUT(0), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(1), + GlitchData => PPCMPLBABUS1_GlitchData, + OutSignalName => "PPCMPLBABUS(1)", + OutTemp => PPCMPLBABUS_OUT(1), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(2), + GlitchData => PPCMPLBABUS2_GlitchData, + OutSignalName => "PPCMPLBABUS(2)", + OutTemp => PPCMPLBABUS_OUT(2), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(3), + GlitchData => PPCMPLBABUS3_GlitchData, + OutSignalName => "PPCMPLBABUS(3)", + OutTemp => PPCMPLBABUS_OUT(3), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(4), + GlitchData => PPCMPLBABUS4_GlitchData, + OutSignalName => "PPCMPLBABUS(4)", + OutTemp => PPCMPLBABUS_OUT(4), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(5), + GlitchData => PPCMPLBABUS5_GlitchData, + OutSignalName => "PPCMPLBABUS(5)", + OutTemp => PPCMPLBABUS_OUT(5), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(6), + GlitchData => PPCMPLBABUS6_GlitchData, + OutSignalName => "PPCMPLBABUS(6)", + OutTemp => PPCMPLBABUS_OUT(6), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(7), + GlitchData => PPCMPLBABUS7_GlitchData, + OutSignalName => "PPCMPLBABUS(7)", + OutTemp => PPCMPLBABUS_OUT(7), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(8), + GlitchData => PPCMPLBABUS8_GlitchData, + OutSignalName => "PPCMPLBABUS(8)", + OutTemp => PPCMPLBABUS_OUT(8), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(9), + GlitchData => PPCMPLBABUS9_GlitchData, + OutSignalName => "PPCMPLBABUS(9)", + OutTemp => PPCMPLBABUS_OUT(9), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(10), + GlitchData => PPCMPLBABUS10_GlitchData, + OutSignalName => "PPCMPLBABUS(10)", + OutTemp => PPCMPLBABUS_OUT(10), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(11), + GlitchData => PPCMPLBABUS11_GlitchData, + OutSignalName => "PPCMPLBABUS(11)", + OutTemp => PPCMPLBABUS_OUT(11), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(12), + GlitchData => PPCMPLBABUS12_GlitchData, + OutSignalName => "PPCMPLBABUS(12)", + OutTemp => PPCMPLBABUS_OUT(12), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(13), + GlitchData => PPCMPLBABUS13_GlitchData, + OutSignalName => "PPCMPLBABUS(13)", + OutTemp => PPCMPLBABUS_OUT(13), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(14), + GlitchData => PPCMPLBABUS14_GlitchData, + OutSignalName => "PPCMPLBABUS(14)", + OutTemp => PPCMPLBABUS_OUT(14), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(15), + GlitchData => PPCMPLBABUS15_GlitchData, + OutSignalName => "PPCMPLBABUS(15)", + OutTemp => PPCMPLBABUS_OUT(15), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(16), + GlitchData => PPCMPLBABUS16_GlitchData, + OutSignalName => "PPCMPLBABUS(16)", + OutTemp => PPCMPLBABUS_OUT(16), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(17), + GlitchData => PPCMPLBABUS17_GlitchData, + OutSignalName => "PPCMPLBABUS(17)", + OutTemp => PPCMPLBABUS_OUT(17), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(18), + GlitchData => PPCMPLBABUS18_GlitchData, + OutSignalName => "PPCMPLBABUS(18)", + OutTemp => PPCMPLBABUS_OUT(18), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(19), + GlitchData => PPCMPLBABUS19_GlitchData, + OutSignalName => "PPCMPLBABUS(19)", + OutTemp => PPCMPLBABUS_OUT(19), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(20), + GlitchData => PPCMPLBABUS20_GlitchData, + OutSignalName => "PPCMPLBABUS(20)", + OutTemp => PPCMPLBABUS_OUT(20), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(21), + GlitchData => PPCMPLBABUS21_GlitchData, + OutSignalName => "PPCMPLBABUS(21)", + OutTemp => PPCMPLBABUS_OUT(21), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(22), + GlitchData => PPCMPLBABUS22_GlitchData, + OutSignalName => "PPCMPLBABUS(22)", + OutTemp => PPCMPLBABUS_OUT(22), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(23), + GlitchData => PPCMPLBABUS23_GlitchData, + OutSignalName => "PPCMPLBABUS(23)", + OutTemp => PPCMPLBABUS_OUT(23), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(24), + GlitchData => PPCMPLBABUS24_GlitchData, + OutSignalName => "PPCMPLBABUS(24)", + OutTemp => PPCMPLBABUS_OUT(24), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(25), + GlitchData => PPCMPLBABUS25_GlitchData, + OutSignalName => "PPCMPLBABUS(25)", + OutTemp => PPCMPLBABUS_OUT(25), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(26), + GlitchData => PPCMPLBABUS26_GlitchData, + OutSignalName => "PPCMPLBABUS(26)", + OutTemp => PPCMPLBABUS_OUT(26), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(27), + GlitchData => PPCMPLBABUS27_GlitchData, + OutSignalName => "PPCMPLBABUS(27)", + OutTemp => PPCMPLBABUS_OUT(27), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(28), + GlitchData => PPCMPLBABUS28_GlitchData, + OutSignalName => "PPCMPLBABUS(28)", + OutTemp => PPCMPLBABUS_OUT(28), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(29), + GlitchData => PPCMPLBABUS29_GlitchData, + OutSignalName => "PPCMPLBABUS(29)", + OutTemp => PPCMPLBABUS_OUT(29), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(30), + GlitchData => PPCMPLBABUS30_GlitchData, + OutSignalName => "PPCMPLBABUS(30)", + OutTemp => PPCMPLBABUS_OUT(30), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBABUS(31), + GlitchData => PPCMPLBABUS31_GlitchData, + OutSignalName => "PPCMPLBABUS(31)", + OutTemp => PPCMPLBABUS_OUT(31), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(0), + GlitchData => PPCMPLBBE0_GlitchData, + OutSignalName => "PPCMPLBBE(0)", + OutTemp => PPCMPLBBE_OUT(0), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(1), + GlitchData => PPCMPLBBE1_GlitchData, + OutSignalName => "PPCMPLBBE(1)", + OutTemp => PPCMPLBBE_OUT(1), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(2), + GlitchData => PPCMPLBBE2_GlitchData, + OutSignalName => "PPCMPLBBE(2)", + OutTemp => PPCMPLBBE_OUT(2), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(3), + GlitchData => PPCMPLBBE3_GlitchData, + OutSignalName => "PPCMPLBBE(3)", + OutTemp => PPCMPLBBE_OUT(3), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(4), + GlitchData => PPCMPLBBE4_GlitchData, + OutSignalName => "PPCMPLBBE(4)", + OutTemp => PPCMPLBBE_OUT(4), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(5), + GlitchData => PPCMPLBBE5_GlitchData, + OutSignalName => "PPCMPLBBE(5)", + OutTemp => PPCMPLBBE_OUT(5), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(6), + GlitchData => PPCMPLBBE6_GlitchData, + OutSignalName => "PPCMPLBBE(6)", + OutTemp => PPCMPLBBE_OUT(6), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(7), + GlitchData => PPCMPLBBE7_GlitchData, + OutSignalName => "PPCMPLBBE(7)", + OutTemp => PPCMPLBBE_OUT(7), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(8), + GlitchData => PPCMPLBBE8_GlitchData, + OutSignalName => "PPCMPLBBE(8)", + OutTemp => PPCMPLBBE_OUT(8), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(9), + GlitchData => PPCMPLBBE9_GlitchData, + OutSignalName => "PPCMPLBBE(9)", + OutTemp => PPCMPLBBE_OUT(9), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(10), + GlitchData => PPCMPLBBE10_GlitchData, + OutSignalName => "PPCMPLBBE(10)", + OutTemp => PPCMPLBBE_OUT(10), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(11), + GlitchData => PPCMPLBBE11_GlitchData, + OutSignalName => "PPCMPLBBE(11)", + OutTemp => PPCMPLBBE_OUT(11), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(12), + GlitchData => PPCMPLBBE12_GlitchData, + OutSignalName => "PPCMPLBBE(12)", + OutTemp => PPCMPLBBE_OUT(12), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(13), + GlitchData => PPCMPLBBE13_GlitchData, + OutSignalName => "PPCMPLBBE(13)", + OutTemp => PPCMPLBBE_OUT(13), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(14), + GlitchData => PPCMPLBBE14_GlitchData, + OutSignalName => "PPCMPLBBE(14)", + OutTemp => PPCMPLBBE_OUT(14), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBE(15), + GlitchData => PPCMPLBBE15_GlitchData, + OutSignalName => "PPCMPLBBE(15)", + OutTemp => PPCMPLBBE_OUT(15), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBBUSLOCK, + GlitchData => PPCMPLBBUSLOCK_GlitchData, + OutSignalName => "PPCMPLBBUSLOCK", + OutTemp => PPCMPLBBUSLOCK_OUT, + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBLOCKERR, + GlitchData => PPCMPLBLOCKERR_GlitchData, + OutSignalName => "PPCMPLBLOCKERR", + OutTemp => PPCMPLBLOCKERR_OUT, + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBPRIORITY(0), + GlitchData => PPCMPLBPRIORITY0_GlitchData, + OutSignalName => "PPCMPLBPRIORITY(0)", + OutTemp => PPCMPLBPRIORITY_OUT(0), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBPRIORITY(1), + GlitchData => PPCMPLBPRIORITY1_GlitchData, + OutSignalName => "PPCMPLBPRIORITY(1)", + OutTemp => PPCMPLBPRIORITY_OUT(1), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBRDBURST, + GlitchData => PPCMPLBRDBURST_GlitchData, + OutSignalName => "PPCMPLBRDBURST", + OutTemp => PPCMPLBRDBURST_OUT, + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBREQUEST, + GlitchData => PPCMPLBREQUEST_GlitchData, + OutSignalName => "PPCMPLBREQUEST", + OutTemp => PPCMPLBREQUEST_OUT, + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBRNW, + GlitchData => PPCMPLBRNW_GlitchData, + OutSignalName => "PPCMPLBRNW", + OutTemp => PPCMPLBRNW_OUT, + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBSIZE(0), + GlitchData => PPCMPLBSIZE0_GlitchData, + OutSignalName => "PPCMPLBSIZE(0)", + OutTemp => PPCMPLBSIZE_OUT(0), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBSIZE(1), + GlitchData => PPCMPLBSIZE1_GlitchData, + OutSignalName => "PPCMPLBSIZE(1)", + OutTemp => PPCMPLBSIZE_OUT(1), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBSIZE(2), + GlitchData => PPCMPLBSIZE2_GlitchData, + OutSignalName => "PPCMPLBSIZE(2)", + OutTemp => PPCMPLBSIZE_OUT(2), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBSIZE(3), + GlitchData => PPCMPLBSIZE3_GlitchData, + OutSignalName => "PPCMPLBSIZE(3)", + OutTemp => PPCMPLBSIZE_OUT(3), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(0), + GlitchData => PPCMPLBTATTRIBUTE0_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(0)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(0), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(1), + GlitchData => PPCMPLBTATTRIBUTE1_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(1)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(1), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(2), + GlitchData => PPCMPLBTATTRIBUTE2_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(2)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(2), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(3), + GlitchData => PPCMPLBTATTRIBUTE3_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(3)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(3), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(4), + GlitchData => PPCMPLBTATTRIBUTE4_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(4)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(4), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(5), + GlitchData => PPCMPLBTATTRIBUTE5_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(5)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(5), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(6), + GlitchData => PPCMPLBTATTRIBUTE6_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(6)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(6), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(7), + GlitchData => PPCMPLBTATTRIBUTE7_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(7)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(7), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(8), + GlitchData => PPCMPLBTATTRIBUTE8_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(8)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(8), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(9), + GlitchData => PPCMPLBTATTRIBUTE9_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(9)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(9), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(10), + GlitchData => PPCMPLBTATTRIBUTE10_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(10)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(10), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(11), + GlitchData => PPCMPLBTATTRIBUTE11_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(11)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(11), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(12), + GlitchData => PPCMPLBTATTRIBUTE12_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(12)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(12), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(13), + GlitchData => PPCMPLBTATTRIBUTE13_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(13)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(13), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(14), + GlitchData => PPCMPLBTATTRIBUTE14_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(14)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(14), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTATTRIBUTE(15), + GlitchData => PPCMPLBTATTRIBUTE15_GlitchData, + OutSignalName => "PPCMPLBTATTRIBUTE(15)", + OutTemp => PPCMPLBTATTRIBUTE_OUT(15), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTYPE(0), + GlitchData => PPCMPLBTYPE0_GlitchData, + OutSignalName => "PPCMPLBTYPE(0)", + OutTemp => PPCMPLBTYPE_OUT(0), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTYPE(1), + GlitchData => PPCMPLBTYPE1_GlitchData, + OutSignalName => "PPCMPLBTYPE(1)", + OutTemp => PPCMPLBTYPE_OUT(1), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBTYPE(2), + GlitchData => PPCMPLBTYPE2_GlitchData, + OutSignalName => "PPCMPLBTYPE(2)", + OutTemp => PPCMPLBTYPE_OUT(2), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBUABUS(28), + GlitchData => PPCMPLBUABUS28_GlitchData, + OutSignalName => "PPCMPLBUABUS(28)", + OutTemp => PPCMPLBUABUS_OUT(28), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBUABUS(29), + GlitchData => PPCMPLBUABUS29_GlitchData, + OutSignalName => "PPCMPLBUABUS(29)", + OutTemp => PPCMPLBUABUS_OUT(29), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBUABUS(30), + GlitchData => PPCMPLBUABUS30_GlitchData, + OutSignalName => "PPCMPLBUABUS(30)", + OutTemp => PPCMPLBUABUS_OUT(30), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBUABUS(31), + GlitchData => PPCMPLBUABUS31_GlitchData, + OutSignalName => "PPCMPLBUABUS(31)", + OutTemp => PPCMPLBUABUS_OUT(31), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRBURST, + GlitchData => PPCMPLBWRBURST_GlitchData, + OutSignalName => "PPCMPLBWRBURST", + OutTemp => PPCMPLBWRBURST_OUT, + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(0), + GlitchData => PPCMPLBWRDBUS0_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(0)", + OutTemp => PPCMPLBWRDBUS_OUT(0), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(1), + GlitchData => PPCMPLBWRDBUS1_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(1)", + OutTemp => PPCMPLBWRDBUS_OUT(1), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(2), + GlitchData => PPCMPLBWRDBUS2_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(2)", + OutTemp => PPCMPLBWRDBUS_OUT(2), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(3), + GlitchData => PPCMPLBWRDBUS3_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(3)", + OutTemp => PPCMPLBWRDBUS_OUT(3), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(4), + GlitchData => PPCMPLBWRDBUS4_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(4)", + OutTemp => PPCMPLBWRDBUS_OUT(4), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(5), + GlitchData => PPCMPLBWRDBUS5_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(5)", + OutTemp => PPCMPLBWRDBUS_OUT(5), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(6), + GlitchData => PPCMPLBWRDBUS6_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(6)", + OutTemp => PPCMPLBWRDBUS_OUT(6), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(7), + GlitchData => PPCMPLBWRDBUS7_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(7)", + OutTemp => PPCMPLBWRDBUS_OUT(7), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(8), + GlitchData => PPCMPLBWRDBUS8_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(8)", + OutTemp => PPCMPLBWRDBUS_OUT(8), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(9), + GlitchData => PPCMPLBWRDBUS9_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(9)", + OutTemp => PPCMPLBWRDBUS_OUT(9), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(10), + GlitchData => PPCMPLBWRDBUS10_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(10)", + OutTemp => PPCMPLBWRDBUS_OUT(10), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(11), + GlitchData => PPCMPLBWRDBUS11_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(11)", + OutTemp => PPCMPLBWRDBUS_OUT(11), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(12), + GlitchData => PPCMPLBWRDBUS12_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(12)", + OutTemp => PPCMPLBWRDBUS_OUT(12), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(13), + GlitchData => PPCMPLBWRDBUS13_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(13)", + OutTemp => PPCMPLBWRDBUS_OUT(13), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(14), + GlitchData => PPCMPLBWRDBUS14_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(14)", + OutTemp => PPCMPLBWRDBUS_OUT(14), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(15), + GlitchData => PPCMPLBWRDBUS15_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(15)", + OutTemp => PPCMPLBWRDBUS_OUT(15), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(16), + GlitchData => PPCMPLBWRDBUS16_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(16)", + OutTemp => PPCMPLBWRDBUS_OUT(16), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(17), + GlitchData => PPCMPLBWRDBUS17_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(17)", + OutTemp => PPCMPLBWRDBUS_OUT(17), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(18), + GlitchData => PPCMPLBWRDBUS18_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(18)", + OutTemp => PPCMPLBWRDBUS_OUT(18), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(19), + GlitchData => PPCMPLBWRDBUS19_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(19)", + OutTemp => PPCMPLBWRDBUS_OUT(19), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(20), + GlitchData => PPCMPLBWRDBUS20_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(20)", + OutTemp => PPCMPLBWRDBUS_OUT(20), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(21), + GlitchData => PPCMPLBWRDBUS21_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(21)", + OutTemp => PPCMPLBWRDBUS_OUT(21), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(22), + GlitchData => PPCMPLBWRDBUS22_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(22)", + OutTemp => PPCMPLBWRDBUS_OUT(22), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(23), + GlitchData => PPCMPLBWRDBUS23_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(23)", + OutTemp => PPCMPLBWRDBUS_OUT(23), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(24), + GlitchData => PPCMPLBWRDBUS24_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(24)", + OutTemp => PPCMPLBWRDBUS_OUT(24), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(25), + GlitchData => PPCMPLBWRDBUS25_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(25)", + OutTemp => PPCMPLBWRDBUS_OUT(25), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(26), + GlitchData => PPCMPLBWRDBUS26_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(26)", + OutTemp => PPCMPLBWRDBUS_OUT(26), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(27), + GlitchData => PPCMPLBWRDBUS27_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(27)", + OutTemp => PPCMPLBWRDBUS_OUT(27), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(28), + GlitchData => PPCMPLBWRDBUS28_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(28)", + OutTemp => PPCMPLBWRDBUS_OUT(28), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(29), + GlitchData => PPCMPLBWRDBUS29_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(29)", + OutTemp => PPCMPLBWRDBUS_OUT(29), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(30), + GlitchData => PPCMPLBWRDBUS30_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(30)", + OutTemp => PPCMPLBWRDBUS_OUT(30), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(31), + GlitchData => PPCMPLBWRDBUS31_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(31)", + OutTemp => PPCMPLBWRDBUS_OUT(31), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(32), + GlitchData => PPCMPLBWRDBUS32_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(32)", + OutTemp => PPCMPLBWRDBUS_OUT(32), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(33), + GlitchData => PPCMPLBWRDBUS33_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(33)", + OutTemp => PPCMPLBWRDBUS_OUT(33), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(34), + GlitchData => PPCMPLBWRDBUS34_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(34)", + OutTemp => PPCMPLBWRDBUS_OUT(34), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(35), + GlitchData => PPCMPLBWRDBUS35_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(35)", + OutTemp => PPCMPLBWRDBUS_OUT(35), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(36), + GlitchData => PPCMPLBWRDBUS36_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(36)", + OutTemp => PPCMPLBWRDBUS_OUT(36), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(37), + GlitchData => PPCMPLBWRDBUS37_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(37)", + OutTemp => PPCMPLBWRDBUS_OUT(37), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(38), + GlitchData => PPCMPLBWRDBUS38_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(38)", + OutTemp => PPCMPLBWRDBUS_OUT(38), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(39), + GlitchData => PPCMPLBWRDBUS39_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(39)", + OutTemp => PPCMPLBWRDBUS_OUT(39), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(40), + GlitchData => PPCMPLBWRDBUS40_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(40)", + OutTemp => PPCMPLBWRDBUS_OUT(40), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(41), + GlitchData => PPCMPLBWRDBUS41_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(41)", + OutTemp => PPCMPLBWRDBUS_OUT(41), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(42), + GlitchData => PPCMPLBWRDBUS42_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(42)", + OutTemp => PPCMPLBWRDBUS_OUT(42), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(43), + GlitchData => PPCMPLBWRDBUS43_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(43)", + OutTemp => PPCMPLBWRDBUS_OUT(43), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(44), + GlitchData => PPCMPLBWRDBUS44_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(44)", + OutTemp => PPCMPLBWRDBUS_OUT(44), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(45), + GlitchData => PPCMPLBWRDBUS45_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(45)", + OutTemp => PPCMPLBWRDBUS_OUT(45), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(46), + GlitchData => PPCMPLBWRDBUS46_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(46)", + OutTemp => PPCMPLBWRDBUS_OUT(46), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(47), + GlitchData => PPCMPLBWRDBUS47_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(47)", + OutTemp => PPCMPLBWRDBUS_OUT(47), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(48), + GlitchData => PPCMPLBWRDBUS48_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(48)", + OutTemp => PPCMPLBWRDBUS_OUT(48), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(49), + GlitchData => PPCMPLBWRDBUS49_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(49)", + OutTemp => PPCMPLBWRDBUS_OUT(49), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(50), + GlitchData => PPCMPLBWRDBUS50_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(50)", + OutTemp => PPCMPLBWRDBUS_OUT(50), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(51), + GlitchData => PPCMPLBWRDBUS51_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(51)", + OutTemp => PPCMPLBWRDBUS_OUT(51), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(52), + GlitchData => PPCMPLBWRDBUS52_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(52)", + OutTemp => PPCMPLBWRDBUS_OUT(52), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(53), + GlitchData => PPCMPLBWRDBUS53_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(53)", + OutTemp => PPCMPLBWRDBUS_OUT(53), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(54), + GlitchData => PPCMPLBWRDBUS54_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(54)", + OutTemp => PPCMPLBWRDBUS_OUT(54), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(55), + GlitchData => PPCMPLBWRDBUS55_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(55)", + OutTemp => PPCMPLBWRDBUS_OUT(55), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(56), + GlitchData => PPCMPLBWRDBUS56_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(56)", + OutTemp => PPCMPLBWRDBUS_OUT(56), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(57), + GlitchData => PPCMPLBWRDBUS57_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(57)", + OutTemp => PPCMPLBWRDBUS_OUT(57), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(58), + GlitchData => PPCMPLBWRDBUS58_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(58)", + OutTemp => PPCMPLBWRDBUS_OUT(58), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(59), + GlitchData => PPCMPLBWRDBUS59_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(59)", + OutTemp => PPCMPLBWRDBUS_OUT(59), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(60), + GlitchData => PPCMPLBWRDBUS60_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(60)", + OutTemp => PPCMPLBWRDBUS_OUT(60), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(61), + GlitchData => PPCMPLBWRDBUS61_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(61)", + OutTemp => PPCMPLBWRDBUS_OUT(61), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(62), + GlitchData => PPCMPLBWRDBUS62_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(62)", + OutTemp => PPCMPLBWRDBUS_OUT(62), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(63), + GlitchData => PPCMPLBWRDBUS63_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(63)", + OutTemp => PPCMPLBWRDBUS_OUT(63), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(64), + GlitchData => PPCMPLBWRDBUS64_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(64)", + OutTemp => PPCMPLBWRDBUS_OUT(64), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(65), + GlitchData => PPCMPLBWRDBUS65_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(65)", + OutTemp => PPCMPLBWRDBUS_OUT(65), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(66), + GlitchData => PPCMPLBWRDBUS66_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(66)", + OutTemp => PPCMPLBWRDBUS_OUT(66), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(67), + GlitchData => PPCMPLBWRDBUS67_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(67)", + OutTemp => PPCMPLBWRDBUS_OUT(67), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(68), + GlitchData => PPCMPLBWRDBUS68_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(68)", + OutTemp => PPCMPLBWRDBUS_OUT(68), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(69), + GlitchData => PPCMPLBWRDBUS69_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(69)", + OutTemp => PPCMPLBWRDBUS_OUT(69), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(70), + GlitchData => PPCMPLBWRDBUS70_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(70)", + OutTemp => PPCMPLBWRDBUS_OUT(70), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(71), + GlitchData => PPCMPLBWRDBUS71_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(71)", + OutTemp => PPCMPLBWRDBUS_OUT(71), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(72), + GlitchData => PPCMPLBWRDBUS72_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(72)", + OutTemp => PPCMPLBWRDBUS_OUT(72), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(73), + GlitchData => PPCMPLBWRDBUS73_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(73)", + OutTemp => PPCMPLBWRDBUS_OUT(73), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(74), + GlitchData => PPCMPLBWRDBUS74_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(74)", + OutTemp => PPCMPLBWRDBUS_OUT(74), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(75), + GlitchData => PPCMPLBWRDBUS75_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(75)", + OutTemp => PPCMPLBWRDBUS_OUT(75), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(76), + GlitchData => PPCMPLBWRDBUS76_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(76)", + OutTemp => PPCMPLBWRDBUS_OUT(76), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(77), + GlitchData => PPCMPLBWRDBUS77_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(77)", + OutTemp => PPCMPLBWRDBUS_OUT(77), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(78), + GlitchData => PPCMPLBWRDBUS78_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(78)", + OutTemp => PPCMPLBWRDBUS_OUT(78), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(79), + GlitchData => PPCMPLBWRDBUS79_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(79)", + OutTemp => PPCMPLBWRDBUS_OUT(79), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(80), + GlitchData => PPCMPLBWRDBUS80_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(80)", + OutTemp => PPCMPLBWRDBUS_OUT(80), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(81), + GlitchData => PPCMPLBWRDBUS81_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(81)", + OutTemp => PPCMPLBWRDBUS_OUT(81), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(82), + GlitchData => PPCMPLBWRDBUS82_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(82)", + OutTemp => PPCMPLBWRDBUS_OUT(82), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(83), + GlitchData => PPCMPLBWRDBUS83_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(83)", + OutTemp => PPCMPLBWRDBUS_OUT(83), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(84), + GlitchData => PPCMPLBWRDBUS84_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(84)", + OutTemp => PPCMPLBWRDBUS_OUT(84), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(85), + GlitchData => PPCMPLBWRDBUS85_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(85)", + OutTemp => PPCMPLBWRDBUS_OUT(85), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(86), + GlitchData => PPCMPLBWRDBUS86_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(86)", + OutTemp => PPCMPLBWRDBUS_OUT(86), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(87), + GlitchData => PPCMPLBWRDBUS87_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(87)", + OutTemp => PPCMPLBWRDBUS_OUT(87), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(88), + GlitchData => PPCMPLBWRDBUS88_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(88)", + OutTemp => PPCMPLBWRDBUS_OUT(88), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(89), + GlitchData => PPCMPLBWRDBUS89_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(89)", + OutTemp => PPCMPLBWRDBUS_OUT(89), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(90), + GlitchData => PPCMPLBWRDBUS90_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(90)", + OutTemp => PPCMPLBWRDBUS_OUT(90), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(91), + GlitchData => PPCMPLBWRDBUS91_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(91)", + OutTemp => PPCMPLBWRDBUS_OUT(91), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(92), + GlitchData => PPCMPLBWRDBUS92_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(92)", + OutTemp => PPCMPLBWRDBUS_OUT(92), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(93), + GlitchData => PPCMPLBWRDBUS93_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(93)", + OutTemp => PPCMPLBWRDBUS_OUT(93), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(94), + GlitchData => PPCMPLBWRDBUS94_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(94)", + OutTemp => PPCMPLBWRDBUS_OUT(94), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(95), + GlitchData => PPCMPLBWRDBUS95_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(95)", + OutTemp => PPCMPLBWRDBUS_OUT(95), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(96), + GlitchData => PPCMPLBWRDBUS96_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(96)", + OutTemp => PPCMPLBWRDBUS_OUT(96), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(97), + GlitchData => PPCMPLBWRDBUS97_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(97)", + OutTemp => PPCMPLBWRDBUS_OUT(97), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(98), + GlitchData => PPCMPLBWRDBUS98_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(98)", + OutTemp => PPCMPLBWRDBUS_OUT(98), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(99), + GlitchData => PPCMPLBWRDBUS99_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(99)", + OutTemp => PPCMPLBWRDBUS_OUT(99), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(100), + GlitchData => PPCMPLBWRDBUS100_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(100)", + OutTemp => PPCMPLBWRDBUS_OUT(100), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(101), + GlitchData => PPCMPLBWRDBUS101_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(101)", + OutTemp => PPCMPLBWRDBUS_OUT(101), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(102), + GlitchData => PPCMPLBWRDBUS102_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(102)", + OutTemp => PPCMPLBWRDBUS_OUT(102), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(103), + GlitchData => PPCMPLBWRDBUS103_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(103)", + OutTemp => PPCMPLBWRDBUS_OUT(103), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(104), + GlitchData => PPCMPLBWRDBUS104_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(104)", + OutTemp => PPCMPLBWRDBUS_OUT(104), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(105), + GlitchData => PPCMPLBWRDBUS105_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(105)", + OutTemp => PPCMPLBWRDBUS_OUT(105), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(106), + GlitchData => PPCMPLBWRDBUS106_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(106)", + OutTemp => PPCMPLBWRDBUS_OUT(106), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(107), + GlitchData => PPCMPLBWRDBUS107_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(107)", + OutTemp => PPCMPLBWRDBUS_OUT(107), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(108), + GlitchData => PPCMPLBWRDBUS108_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(108)", + OutTemp => PPCMPLBWRDBUS_OUT(108), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(109), + GlitchData => PPCMPLBWRDBUS109_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(109)", + OutTemp => PPCMPLBWRDBUS_OUT(109), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(110), + GlitchData => PPCMPLBWRDBUS110_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(110)", + OutTemp => PPCMPLBWRDBUS_OUT(110), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(111), + GlitchData => PPCMPLBWRDBUS111_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(111)", + OutTemp => PPCMPLBWRDBUS_OUT(111), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(112), + GlitchData => PPCMPLBWRDBUS112_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(112)", + OutTemp => PPCMPLBWRDBUS_OUT(112), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(113), + GlitchData => PPCMPLBWRDBUS113_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(113)", + OutTemp => PPCMPLBWRDBUS_OUT(113), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(114), + GlitchData => PPCMPLBWRDBUS114_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(114)", + OutTemp => PPCMPLBWRDBUS_OUT(114), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(115), + GlitchData => PPCMPLBWRDBUS115_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(115)", + OutTemp => PPCMPLBWRDBUS_OUT(115), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(116), + GlitchData => PPCMPLBWRDBUS116_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(116)", + OutTemp => PPCMPLBWRDBUS_OUT(116), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(117), + GlitchData => PPCMPLBWRDBUS117_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(117)", + OutTemp => PPCMPLBWRDBUS_OUT(117), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(118), + GlitchData => PPCMPLBWRDBUS118_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(118)", + OutTemp => PPCMPLBWRDBUS_OUT(118), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(119), + GlitchData => PPCMPLBWRDBUS119_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(119)", + OutTemp => PPCMPLBWRDBUS_OUT(119), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(120), + GlitchData => PPCMPLBWRDBUS120_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(120)", + OutTemp => PPCMPLBWRDBUS_OUT(120), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(121), + GlitchData => PPCMPLBWRDBUS121_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(121)", + OutTemp => PPCMPLBWRDBUS_OUT(121), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(122), + GlitchData => PPCMPLBWRDBUS122_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(122)", + OutTemp => PPCMPLBWRDBUS_OUT(122), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(123), + GlitchData => PPCMPLBWRDBUS123_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(123)", + OutTemp => PPCMPLBWRDBUS_OUT(123), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(124), + GlitchData => PPCMPLBWRDBUS124_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(124)", + OutTemp => PPCMPLBWRDBUS_OUT(124), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(125), + GlitchData => PPCMPLBWRDBUS125_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(125)", + OutTemp => PPCMPLBWRDBUS_OUT(125), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(126), + GlitchData => PPCMPLBWRDBUS126_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(126)", + OutTemp => PPCMPLBWRDBUS_OUT(126), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCMPLBWRDBUS(127), + GlitchData => PPCMPLBWRDBUS127_GlitchData, + OutSignalName => "PPCMPLBWRDBUS(127)", + OutTemp => PPCMPLBWRDBUS_OUT(127), + Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBADDRACK, + GlitchData => PPCS0PLBADDRACK_GlitchData, + OutSignalName => "PPCS0PLBADDRACK", + OutTemp => PPCS0PLBADDRACK_OUT, + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMBUSY(0), + GlitchData => PPCS0PLBMBUSY0_GlitchData, + OutSignalName => "PPCS0PLBMBUSY(0)", + OutTemp => PPCS0PLBMBUSY_OUT(0), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMBUSY(1), + GlitchData => PPCS0PLBMBUSY1_GlitchData, + OutSignalName => "PPCS0PLBMBUSY(1)", + OutTemp => PPCS0PLBMBUSY_OUT(1), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMBUSY(2), + GlitchData => PPCS0PLBMBUSY2_GlitchData, + OutSignalName => "PPCS0PLBMBUSY(2)", + OutTemp => PPCS0PLBMBUSY_OUT(2), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMBUSY(3), + GlitchData => PPCS0PLBMBUSY3_GlitchData, + OutSignalName => "PPCS0PLBMBUSY(3)", + OutTemp => PPCS0PLBMBUSY_OUT(3), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMIRQ(0), + GlitchData => PPCS0PLBMIRQ0_GlitchData, + OutSignalName => "PPCS0PLBMIRQ(0)", + OutTemp => PPCS0PLBMIRQ_OUT(0), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMIRQ(1), + GlitchData => PPCS0PLBMIRQ1_GlitchData, + OutSignalName => "PPCS0PLBMIRQ(1)", + OutTemp => PPCS0PLBMIRQ_OUT(1), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMIRQ(2), + GlitchData => PPCS0PLBMIRQ2_GlitchData, + OutSignalName => "PPCS0PLBMIRQ(2)", + OutTemp => PPCS0PLBMIRQ_OUT(2), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMIRQ(3), + GlitchData => PPCS0PLBMIRQ3_GlitchData, + OutSignalName => "PPCS0PLBMIRQ(3)", + OutTemp => PPCS0PLBMIRQ_OUT(3), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMRDERR(0), + GlitchData => PPCS0PLBMRDERR0_GlitchData, + OutSignalName => "PPCS0PLBMRDERR(0)", + OutTemp => PPCS0PLBMRDERR_OUT(0), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMRDERR(1), + GlitchData => PPCS0PLBMRDERR1_GlitchData, + OutSignalName => "PPCS0PLBMRDERR(1)", + OutTemp => PPCS0PLBMRDERR_OUT(1), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMRDERR(2), + GlitchData => PPCS0PLBMRDERR2_GlitchData, + OutSignalName => "PPCS0PLBMRDERR(2)", + OutTemp => PPCS0PLBMRDERR_OUT(2), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMRDERR(3), + GlitchData => PPCS0PLBMRDERR3_GlitchData, + OutSignalName => "PPCS0PLBMRDERR(3)", + OutTemp => PPCS0PLBMRDERR_OUT(3), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMWRERR(0), + GlitchData => PPCS0PLBMWRERR0_GlitchData, + OutSignalName => "PPCS0PLBMWRERR(0)", + OutTemp => PPCS0PLBMWRERR_OUT(0), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMWRERR(1), + GlitchData => PPCS0PLBMWRERR1_GlitchData, + OutSignalName => "PPCS0PLBMWRERR(1)", + OutTemp => PPCS0PLBMWRERR_OUT(1), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMWRERR(2), + GlitchData => PPCS0PLBMWRERR2_GlitchData, + OutSignalName => "PPCS0PLBMWRERR(2)", + OutTemp => PPCS0PLBMWRERR_OUT(2), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBMWRERR(3), + GlitchData => PPCS0PLBMWRERR3_GlitchData, + OutSignalName => "PPCS0PLBMWRERR(3)", + OutTemp => PPCS0PLBMWRERR_OUT(3), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDBTERM, + GlitchData => PPCS0PLBRDBTERM_GlitchData, + OutSignalName => "PPCS0PLBRDBTERM", + OutTemp => PPCS0PLBRDBTERM_OUT, + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDCOMP, + GlitchData => PPCS0PLBRDCOMP_GlitchData, + OutSignalName => "PPCS0PLBRDCOMP", + OutTemp => PPCS0PLBRDCOMP_OUT, + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDACK, + GlitchData => PPCS0PLBRDDACK_GlitchData, + OutSignalName => "PPCS0PLBRDDACK", + OutTemp => PPCS0PLBRDDACK_OUT, + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(0), + GlitchData => PPCS0PLBRDDBUS0_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(0)", + OutTemp => PPCS0PLBRDDBUS_OUT(0), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(1), + GlitchData => PPCS0PLBRDDBUS1_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(1)", + OutTemp => PPCS0PLBRDDBUS_OUT(1), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(2), + GlitchData => PPCS0PLBRDDBUS2_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(2)", + OutTemp => PPCS0PLBRDDBUS_OUT(2), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(3), + GlitchData => PPCS0PLBRDDBUS3_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(3)", + OutTemp => PPCS0PLBRDDBUS_OUT(3), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(4), + GlitchData => PPCS0PLBRDDBUS4_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(4)", + OutTemp => PPCS0PLBRDDBUS_OUT(4), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(5), + GlitchData => PPCS0PLBRDDBUS5_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(5)", + OutTemp => PPCS0PLBRDDBUS_OUT(5), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(6), + GlitchData => PPCS0PLBRDDBUS6_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(6)", + OutTemp => PPCS0PLBRDDBUS_OUT(6), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(7), + GlitchData => PPCS0PLBRDDBUS7_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(7)", + OutTemp => PPCS0PLBRDDBUS_OUT(7), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(8), + GlitchData => PPCS0PLBRDDBUS8_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(8)", + OutTemp => PPCS0PLBRDDBUS_OUT(8), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(9), + GlitchData => PPCS0PLBRDDBUS9_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(9)", + OutTemp => PPCS0PLBRDDBUS_OUT(9), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(10), + GlitchData => PPCS0PLBRDDBUS10_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(10)", + OutTemp => PPCS0PLBRDDBUS_OUT(10), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(11), + GlitchData => PPCS0PLBRDDBUS11_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(11)", + OutTemp => PPCS0PLBRDDBUS_OUT(11), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(12), + GlitchData => PPCS0PLBRDDBUS12_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(12)", + OutTemp => PPCS0PLBRDDBUS_OUT(12), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(13), + GlitchData => PPCS0PLBRDDBUS13_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(13)", + OutTemp => PPCS0PLBRDDBUS_OUT(13), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(14), + GlitchData => PPCS0PLBRDDBUS14_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(14)", + OutTemp => PPCS0PLBRDDBUS_OUT(14), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(15), + GlitchData => PPCS0PLBRDDBUS15_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(15)", + OutTemp => PPCS0PLBRDDBUS_OUT(15), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(16), + GlitchData => PPCS0PLBRDDBUS16_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(16)", + OutTemp => PPCS0PLBRDDBUS_OUT(16), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(17), + GlitchData => PPCS0PLBRDDBUS17_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(17)", + OutTemp => PPCS0PLBRDDBUS_OUT(17), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(18), + GlitchData => PPCS0PLBRDDBUS18_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(18)", + OutTemp => PPCS0PLBRDDBUS_OUT(18), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(19), + GlitchData => PPCS0PLBRDDBUS19_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(19)", + OutTemp => PPCS0PLBRDDBUS_OUT(19), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(20), + GlitchData => PPCS0PLBRDDBUS20_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(20)", + OutTemp => PPCS0PLBRDDBUS_OUT(20), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(21), + GlitchData => PPCS0PLBRDDBUS21_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(21)", + OutTemp => PPCS0PLBRDDBUS_OUT(21), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(22), + GlitchData => PPCS0PLBRDDBUS22_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(22)", + OutTemp => PPCS0PLBRDDBUS_OUT(22), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(23), + GlitchData => PPCS0PLBRDDBUS23_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(23)", + OutTemp => PPCS0PLBRDDBUS_OUT(23), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(24), + GlitchData => PPCS0PLBRDDBUS24_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(24)", + OutTemp => PPCS0PLBRDDBUS_OUT(24), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(25), + GlitchData => PPCS0PLBRDDBUS25_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(25)", + OutTemp => PPCS0PLBRDDBUS_OUT(25), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(26), + GlitchData => PPCS0PLBRDDBUS26_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(26)", + OutTemp => PPCS0PLBRDDBUS_OUT(26), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(27), + GlitchData => PPCS0PLBRDDBUS27_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(27)", + OutTemp => PPCS0PLBRDDBUS_OUT(27), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(28), + GlitchData => PPCS0PLBRDDBUS28_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(28)", + OutTemp => PPCS0PLBRDDBUS_OUT(28), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(29), + GlitchData => PPCS0PLBRDDBUS29_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(29)", + OutTemp => PPCS0PLBRDDBUS_OUT(29), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(30), + GlitchData => PPCS0PLBRDDBUS30_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(30)", + OutTemp => PPCS0PLBRDDBUS_OUT(30), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(31), + GlitchData => PPCS0PLBRDDBUS31_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(31)", + OutTemp => PPCS0PLBRDDBUS_OUT(31), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(32), + GlitchData => PPCS0PLBRDDBUS32_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(32)", + OutTemp => PPCS0PLBRDDBUS_OUT(32), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(33), + GlitchData => PPCS0PLBRDDBUS33_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(33)", + OutTemp => PPCS0PLBRDDBUS_OUT(33), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(34), + GlitchData => PPCS0PLBRDDBUS34_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(34)", + OutTemp => PPCS0PLBRDDBUS_OUT(34), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(35), + GlitchData => PPCS0PLBRDDBUS35_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(35)", + OutTemp => PPCS0PLBRDDBUS_OUT(35), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(36), + GlitchData => PPCS0PLBRDDBUS36_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(36)", + OutTemp => PPCS0PLBRDDBUS_OUT(36), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(37), + GlitchData => PPCS0PLBRDDBUS37_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(37)", + OutTemp => PPCS0PLBRDDBUS_OUT(37), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(38), + GlitchData => PPCS0PLBRDDBUS38_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(38)", + OutTemp => PPCS0PLBRDDBUS_OUT(38), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(39), + GlitchData => PPCS0PLBRDDBUS39_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(39)", + OutTemp => PPCS0PLBRDDBUS_OUT(39), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(40), + GlitchData => PPCS0PLBRDDBUS40_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(40)", + OutTemp => PPCS0PLBRDDBUS_OUT(40), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(41), + GlitchData => PPCS0PLBRDDBUS41_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(41)", + OutTemp => PPCS0PLBRDDBUS_OUT(41), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(42), + GlitchData => PPCS0PLBRDDBUS42_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(42)", + OutTemp => PPCS0PLBRDDBUS_OUT(42), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(43), + GlitchData => PPCS0PLBRDDBUS43_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(43)", + OutTemp => PPCS0PLBRDDBUS_OUT(43), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(44), + GlitchData => PPCS0PLBRDDBUS44_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(44)", + OutTemp => PPCS0PLBRDDBUS_OUT(44), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(45), + GlitchData => PPCS0PLBRDDBUS45_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(45)", + OutTemp => PPCS0PLBRDDBUS_OUT(45), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(46), + GlitchData => PPCS0PLBRDDBUS46_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(46)", + OutTemp => PPCS0PLBRDDBUS_OUT(46), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(47), + GlitchData => PPCS0PLBRDDBUS47_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(47)", + OutTemp => PPCS0PLBRDDBUS_OUT(47), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(48), + GlitchData => PPCS0PLBRDDBUS48_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(48)", + OutTemp => PPCS0PLBRDDBUS_OUT(48), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(49), + GlitchData => PPCS0PLBRDDBUS49_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(49)", + OutTemp => PPCS0PLBRDDBUS_OUT(49), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(50), + GlitchData => PPCS0PLBRDDBUS50_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(50)", + OutTemp => PPCS0PLBRDDBUS_OUT(50), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(51), + GlitchData => PPCS0PLBRDDBUS51_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(51)", + OutTemp => PPCS0PLBRDDBUS_OUT(51), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(52), + GlitchData => PPCS0PLBRDDBUS52_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(52)", + OutTemp => PPCS0PLBRDDBUS_OUT(52), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(53), + GlitchData => PPCS0PLBRDDBUS53_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(53)", + OutTemp => PPCS0PLBRDDBUS_OUT(53), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(54), + GlitchData => PPCS0PLBRDDBUS54_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(54)", + OutTemp => PPCS0PLBRDDBUS_OUT(54), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(55), + GlitchData => PPCS0PLBRDDBUS55_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(55)", + OutTemp => PPCS0PLBRDDBUS_OUT(55), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(56), + GlitchData => PPCS0PLBRDDBUS56_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(56)", + OutTemp => PPCS0PLBRDDBUS_OUT(56), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(57), + GlitchData => PPCS0PLBRDDBUS57_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(57)", + OutTemp => PPCS0PLBRDDBUS_OUT(57), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(58), + GlitchData => PPCS0PLBRDDBUS58_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(58)", + OutTemp => PPCS0PLBRDDBUS_OUT(58), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(59), + GlitchData => PPCS0PLBRDDBUS59_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(59)", + OutTemp => PPCS0PLBRDDBUS_OUT(59), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(60), + GlitchData => PPCS0PLBRDDBUS60_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(60)", + OutTemp => PPCS0PLBRDDBUS_OUT(60), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(61), + GlitchData => PPCS0PLBRDDBUS61_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(61)", + OutTemp => PPCS0PLBRDDBUS_OUT(61), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(62), + GlitchData => PPCS0PLBRDDBUS62_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(62)", + OutTemp => PPCS0PLBRDDBUS_OUT(62), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(63), + GlitchData => PPCS0PLBRDDBUS63_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(63)", + OutTemp => PPCS0PLBRDDBUS_OUT(63), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(64), + GlitchData => PPCS0PLBRDDBUS64_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(64)", + OutTemp => PPCS0PLBRDDBUS_OUT(64), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(65), + GlitchData => PPCS0PLBRDDBUS65_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(65)", + OutTemp => PPCS0PLBRDDBUS_OUT(65), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(66), + GlitchData => PPCS0PLBRDDBUS66_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(66)", + OutTemp => PPCS0PLBRDDBUS_OUT(66), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(67), + GlitchData => PPCS0PLBRDDBUS67_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(67)", + OutTemp => PPCS0PLBRDDBUS_OUT(67), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(68), + GlitchData => PPCS0PLBRDDBUS68_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(68)", + OutTemp => PPCS0PLBRDDBUS_OUT(68), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(69), + GlitchData => PPCS0PLBRDDBUS69_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(69)", + OutTemp => PPCS0PLBRDDBUS_OUT(69), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(70), + GlitchData => PPCS0PLBRDDBUS70_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(70)", + OutTemp => PPCS0PLBRDDBUS_OUT(70), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(71), + GlitchData => PPCS0PLBRDDBUS71_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(71)", + OutTemp => PPCS0PLBRDDBUS_OUT(71), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(72), + GlitchData => PPCS0PLBRDDBUS72_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(72)", + OutTemp => PPCS0PLBRDDBUS_OUT(72), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(73), + GlitchData => PPCS0PLBRDDBUS73_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(73)", + OutTemp => PPCS0PLBRDDBUS_OUT(73), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(74), + GlitchData => PPCS0PLBRDDBUS74_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(74)", + OutTemp => PPCS0PLBRDDBUS_OUT(74), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(75), + GlitchData => PPCS0PLBRDDBUS75_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(75)", + OutTemp => PPCS0PLBRDDBUS_OUT(75), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(76), + GlitchData => PPCS0PLBRDDBUS76_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(76)", + OutTemp => PPCS0PLBRDDBUS_OUT(76), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(77), + GlitchData => PPCS0PLBRDDBUS77_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(77)", + OutTemp => PPCS0PLBRDDBUS_OUT(77), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(78), + GlitchData => PPCS0PLBRDDBUS78_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(78)", + OutTemp => PPCS0PLBRDDBUS_OUT(78), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(79), + GlitchData => PPCS0PLBRDDBUS79_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(79)", + OutTemp => PPCS0PLBRDDBUS_OUT(79), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(80), + GlitchData => PPCS0PLBRDDBUS80_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(80)", + OutTemp => PPCS0PLBRDDBUS_OUT(80), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(81), + GlitchData => PPCS0PLBRDDBUS81_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(81)", + OutTemp => PPCS0PLBRDDBUS_OUT(81), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(82), + GlitchData => PPCS0PLBRDDBUS82_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(82)", + OutTemp => PPCS0PLBRDDBUS_OUT(82), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(83), + GlitchData => PPCS0PLBRDDBUS83_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(83)", + OutTemp => PPCS0PLBRDDBUS_OUT(83), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(84), + GlitchData => PPCS0PLBRDDBUS84_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(84)", + OutTemp => PPCS0PLBRDDBUS_OUT(84), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(85), + GlitchData => PPCS0PLBRDDBUS85_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(85)", + OutTemp => PPCS0PLBRDDBUS_OUT(85), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(86), + GlitchData => PPCS0PLBRDDBUS86_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(86)", + OutTemp => PPCS0PLBRDDBUS_OUT(86), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(87), + GlitchData => PPCS0PLBRDDBUS87_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(87)", + OutTemp => PPCS0PLBRDDBUS_OUT(87), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(88), + GlitchData => PPCS0PLBRDDBUS88_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(88)", + OutTemp => PPCS0PLBRDDBUS_OUT(88), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(89), + GlitchData => PPCS0PLBRDDBUS89_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(89)", + OutTemp => PPCS0PLBRDDBUS_OUT(89), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(90), + GlitchData => PPCS0PLBRDDBUS90_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(90)", + OutTemp => PPCS0PLBRDDBUS_OUT(90), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(91), + GlitchData => PPCS0PLBRDDBUS91_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(91)", + OutTemp => PPCS0PLBRDDBUS_OUT(91), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(92), + GlitchData => PPCS0PLBRDDBUS92_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(92)", + OutTemp => PPCS0PLBRDDBUS_OUT(92), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(93), + GlitchData => PPCS0PLBRDDBUS93_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(93)", + OutTemp => PPCS0PLBRDDBUS_OUT(93), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(94), + GlitchData => PPCS0PLBRDDBUS94_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(94)", + OutTemp => PPCS0PLBRDDBUS_OUT(94), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(95), + GlitchData => PPCS0PLBRDDBUS95_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(95)", + OutTemp => PPCS0PLBRDDBUS_OUT(95), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(96), + GlitchData => PPCS0PLBRDDBUS96_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(96)", + OutTemp => PPCS0PLBRDDBUS_OUT(96), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(97), + GlitchData => PPCS0PLBRDDBUS97_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(97)", + OutTemp => PPCS0PLBRDDBUS_OUT(97), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(98), + GlitchData => PPCS0PLBRDDBUS98_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(98)", + OutTemp => PPCS0PLBRDDBUS_OUT(98), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(99), + GlitchData => PPCS0PLBRDDBUS99_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(99)", + OutTemp => PPCS0PLBRDDBUS_OUT(99), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(100), + GlitchData => PPCS0PLBRDDBUS100_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(100)", + OutTemp => PPCS0PLBRDDBUS_OUT(100), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(101), + GlitchData => PPCS0PLBRDDBUS101_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(101)", + OutTemp => PPCS0PLBRDDBUS_OUT(101), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(102), + GlitchData => PPCS0PLBRDDBUS102_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(102)", + OutTemp => PPCS0PLBRDDBUS_OUT(102), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(103), + GlitchData => PPCS0PLBRDDBUS103_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(103)", + OutTemp => PPCS0PLBRDDBUS_OUT(103), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(104), + GlitchData => PPCS0PLBRDDBUS104_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(104)", + OutTemp => PPCS0PLBRDDBUS_OUT(104), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(105), + GlitchData => PPCS0PLBRDDBUS105_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(105)", + OutTemp => PPCS0PLBRDDBUS_OUT(105), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(106), + GlitchData => PPCS0PLBRDDBUS106_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(106)", + OutTemp => PPCS0PLBRDDBUS_OUT(106), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(107), + GlitchData => PPCS0PLBRDDBUS107_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(107)", + OutTemp => PPCS0PLBRDDBUS_OUT(107), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(108), + GlitchData => PPCS0PLBRDDBUS108_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(108)", + OutTemp => PPCS0PLBRDDBUS_OUT(108), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(109), + GlitchData => PPCS0PLBRDDBUS109_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(109)", + OutTemp => PPCS0PLBRDDBUS_OUT(109), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(110), + GlitchData => PPCS0PLBRDDBUS110_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(110)", + OutTemp => PPCS0PLBRDDBUS_OUT(110), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(111), + GlitchData => PPCS0PLBRDDBUS111_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(111)", + OutTemp => PPCS0PLBRDDBUS_OUT(111), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(112), + GlitchData => PPCS0PLBRDDBUS112_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(112)", + OutTemp => PPCS0PLBRDDBUS_OUT(112), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(113), + GlitchData => PPCS0PLBRDDBUS113_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(113)", + OutTemp => PPCS0PLBRDDBUS_OUT(113), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(114), + GlitchData => PPCS0PLBRDDBUS114_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(114)", + OutTemp => PPCS0PLBRDDBUS_OUT(114), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(115), + GlitchData => PPCS0PLBRDDBUS115_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(115)", + OutTemp => PPCS0PLBRDDBUS_OUT(115), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(116), + GlitchData => PPCS0PLBRDDBUS116_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(116)", + OutTemp => PPCS0PLBRDDBUS_OUT(116), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(117), + GlitchData => PPCS0PLBRDDBUS117_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(117)", + OutTemp => PPCS0PLBRDDBUS_OUT(117), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(118), + GlitchData => PPCS0PLBRDDBUS118_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(118)", + OutTemp => PPCS0PLBRDDBUS_OUT(118), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(119), + GlitchData => PPCS0PLBRDDBUS119_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(119)", + OutTemp => PPCS0PLBRDDBUS_OUT(119), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(120), + GlitchData => PPCS0PLBRDDBUS120_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(120)", + OutTemp => PPCS0PLBRDDBUS_OUT(120), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(121), + GlitchData => PPCS0PLBRDDBUS121_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(121)", + OutTemp => PPCS0PLBRDDBUS_OUT(121), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(122), + GlitchData => PPCS0PLBRDDBUS122_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(122)", + OutTemp => PPCS0PLBRDDBUS_OUT(122), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(123), + GlitchData => PPCS0PLBRDDBUS123_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(123)", + OutTemp => PPCS0PLBRDDBUS_OUT(123), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(124), + GlitchData => PPCS0PLBRDDBUS124_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(124)", + OutTemp => PPCS0PLBRDDBUS_OUT(124), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(125), + GlitchData => PPCS0PLBRDDBUS125_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(125)", + OutTemp => PPCS0PLBRDDBUS_OUT(125), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(126), + GlitchData => PPCS0PLBRDDBUS126_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(126)", + OutTemp => PPCS0PLBRDDBUS_OUT(126), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDDBUS(127), + GlitchData => PPCS0PLBRDDBUS127_GlitchData, + OutSignalName => "PPCS0PLBRDDBUS(127)", + OutTemp => PPCS0PLBRDDBUS_OUT(127), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDWDADDR(0), + GlitchData => PPCS0PLBRDWDADDR0_GlitchData, + OutSignalName => "PPCS0PLBRDWDADDR(0)", + OutTemp => PPCS0PLBRDWDADDR_OUT(0), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDWDADDR(1), + GlitchData => PPCS0PLBRDWDADDR1_GlitchData, + OutSignalName => "PPCS0PLBRDWDADDR(1)", + OutTemp => PPCS0PLBRDWDADDR_OUT(1), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDWDADDR(2), + GlitchData => PPCS0PLBRDWDADDR2_GlitchData, + OutSignalName => "PPCS0PLBRDWDADDR(2)", + OutTemp => PPCS0PLBRDWDADDR_OUT(2), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBRDWDADDR(3), + GlitchData => PPCS0PLBRDWDADDR3_GlitchData, + OutSignalName => "PPCS0PLBRDWDADDR(3)", + OutTemp => PPCS0PLBRDWDADDR_OUT(3), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBREARBITRATE, + GlitchData => PPCS0PLBREARBITRATE_GlitchData, + OutSignalName => "PPCS0PLBREARBITRATE", + OutTemp => PPCS0PLBREARBITRATE_OUT, + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBSSIZE(0), + GlitchData => PPCS0PLBSSIZE0_GlitchData, + OutSignalName => "PPCS0PLBSSIZE(0)", + OutTemp => PPCS0PLBSSIZE_OUT(0), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBSSIZE(1), + GlitchData => PPCS0PLBSSIZE1_GlitchData, + OutSignalName => "PPCS0PLBSSIZE(1)", + OutTemp => PPCS0PLBSSIZE_OUT(1), + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBWAIT, + GlitchData => PPCS0PLBWAIT_GlitchData, + OutSignalName => "PPCS0PLBWAIT", + OutTemp => PPCS0PLBWAIT_OUT, + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBWRBTERM, + GlitchData => PPCS0PLBWRBTERM_GlitchData, + OutSignalName => "PPCS0PLBWRBTERM", + OutTemp => PPCS0PLBWRBTERM_OUT, + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBWRCOMP, + GlitchData => PPCS0PLBWRCOMP_GlitchData, + OutSignalName => "PPCS0PLBWRCOMP", + OutTemp => PPCS0PLBWRCOMP_OUT, + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS0PLBWRDACK, + GlitchData => PPCS0PLBWRDACK_GlitchData, + OutSignalName => "PPCS0PLBWRDACK", + OutTemp => PPCS0PLBWRDACK_OUT, + Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBADDRACK, + GlitchData => PPCS1PLBADDRACK_GlitchData, + OutSignalName => "PPCS1PLBADDRACK", + OutTemp => PPCS1PLBADDRACK_OUT, + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMBUSY(0), + GlitchData => PPCS1PLBMBUSY0_GlitchData, + OutSignalName => "PPCS1PLBMBUSY(0)", + OutTemp => PPCS1PLBMBUSY_OUT(0), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMBUSY(1), + GlitchData => PPCS1PLBMBUSY1_GlitchData, + OutSignalName => "PPCS1PLBMBUSY(1)", + OutTemp => PPCS1PLBMBUSY_OUT(1), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMBUSY(2), + GlitchData => PPCS1PLBMBUSY2_GlitchData, + OutSignalName => "PPCS1PLBMBUSY(2)", + OutTemp => PPCS1PLBMBUSY_OUT(2), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMBUSY(3), + GlitchData => PPCS1PLBMBUSY3_GlitchData, + OutSignalName => "PPCS1PLBMBUSY(3)", + OutTemp => PPCS1PLBMBUSY_OUT(3), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMIRQ(0), + GlitchData => PPCS1PLBMIRQ0_GlitchData, + OutSignalName => "PPCS1PLBMIRQ(0)", + OutTemp => PPCS1PLBMIRQ_OUT(0), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMIRQ(1), + GlitchData => PPCS1PLBMIRQ1_GlitchData, + OutSignalName => "PPCS1PLBMIRQ(1)", + OutTemp => PPCS1PLBMIRQ_OUT(1), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMIRQ(2), + GlitchData => PPCS1PLBMIRQ2_GlitchData, + OutSignalName => "PPCS1PLBMIRQ(2)", + OutTemp => PPCS1PLBMIRQ_OUT(2), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMIRQ(3), + GlitchData => PPCS1PLBMIRQ3_GlitchData, + OutSignalName => "PPCS1PLBMIRQ(3)", + OutTemp => PPCS1PLBMIRQ_OUT(3), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMRDERR(0), + GlitchData => PPCS1PLBMRDERR0_GlitchData, + OutSignalName => "PPCS1PLBMRDERR(0)", + OutTemp => PPCS1PLBMRDERR_OUT(0), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMRDERR(1), + GlitchData => PPCS1PLBMRDERR1_GlitchData, + OutSignalName => "PPCS1PLBMRDERR(1)", + OutTemp => PPCS1PLBMRDERR_OUT(1), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMRDERR(2), + GlitchData => PPCS1PLBMRDERR2_GlitchData, + OutSignalName => "PPCS1PLBMRDERR(2)", + OutTemp => PPCS1PLBMRDERR_OUT(2), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMRDERR(3), + GlitchData => PPCS1PLBMRDERR3_GlitchData, + OutSignalName => "PPCS1PLBMRDERR(3)", + OutTemp => PPCS1PLBMRDERR_OUT(3), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMWRERR(0), + GlitchData => PPCS1PLBMWRERR0_GlitchData, + OutSignalName => "PPCS1PLBMWRERR(0)", + OutTemp => PPCS1PLBMWRERR_OUT(0), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMWRERR(1), + GlitchData => PPCS1PLBMWRERR1_GlitchData, + OutSignalName => "PPCS1PLBMWRERR(1)", + OutTemp => PPCS1PLBMWRERR_OUT(1), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMWRERR(2), + GlitchData => PPCS1PLBMWRERR2_GlitchData, + OutSignalName => "PPCS1PLBMWRERR(2)", + OutTemp => PPCS1PLBMWRERR_OUT(2), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBMWRERR(3), + GlitchData => PPCS1PLBMWRERR3_GlitchData, + OutSignalName => "PPCS1PLBMWRERR(3)", + OutTemp => PPCS1PLBMWRERR_OUT(3), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDBTERM, + GlitchData => PPCS1PLBRDBTERM_GlitchData, + OutSignalName => "PPCS1PLBRDBTERM", + OutTemp => PPCS1PLBRDBTERM_OUT, + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDCOMP, + GlitchData => PPCS1PLBRDCOMP_GlitchData, + OutSignalName => "PPCS1PLBRDCOMP", + OutTemp => PPCS1PLBRDCOMP_OUT, + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDACK, + GlitchData => PPCS1PLBRDDACK_GlitchData, + OutSignalName => "PPCS1PLBRDDACK", + OutTemp => PPCS1PLBRDDACK_OUT, + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(0), + GlitchData => PPCS1PLBRDDBUS0_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(0)", + OutTemp => PPCS1PLBRDDBUS_OUT(0), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(1), + GlitchData => PPCS1PLBRDDBUS1_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(1)", + OutTemp => PPCS1PLBRDDBUS_OUT(1), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(2), + GlitchData => PPCS1PLBRDDBUS2_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(2)", + OutTemp => PPCS1PLBRDDBUS_OUT(2), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(3), + GlitchData => PPCS1PLBRDDBUS3_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(3)", + OutTemp => PPCS1PLBRDDBUS_OUT(3), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(4), + GlitchData => PPCS1PLBRDDBUS4_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(4)", + OutTemp => PPCS1PLBRDDBUS_OUT(4), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(5), + GlitchData => PPCS1PLBRDDBUS5_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(5)", + OutTemp => PPCS1PLBRDDBUS_OUT(5), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(6), + GlitchData => PPCS1PLBRDDBUS6_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(6)", + OutTemp => PPCS1PLBRDDBUS_OUT(6), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(7), + GlitchData => PPCS1PLBRDDBUS7_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(7)", + OutTemp => PPCS1PLBRDDBUS_OUT(7), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(8), + GlitchData => PPCS1PLBRDDBUS8_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(8)", + OutTemp => PPCS1PLBRDDBUS_OUT(8), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(9), + GlitchData => PPCS1PLBRDDBUS9_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(9)", + OutTemp => PPCS1PLBRDDBUS_OUT(9), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(10), + GlitchData => PPCS1PLBRDDBUS10_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(10)", + OutTemp => PPCS1PLBRDDBUS_OUT(10), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(11), + GlitchData => PPCS1PLBRDDBUS11_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(11)", + OutTemp => PPCS1PLBRDDBUS_OUT(11), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(12), + GlitchData => PPCS1PLBRDDBUS12_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(12)", + OutTemp => PPCS1PLBRDDBUS_OUT(12), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(13), + GlitchData => PPCS1PLBRDDBUS13_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(13)", + OutTemp => PPCS1PLBRDDBUS_OUT(13), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(14), + GlitchData => PPCS1PLBRDDBUS14_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(14)", + OutTemp => PPCS1PLBRDDBUS_OUT(14), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(15), + GlitchData => PPCS1PLBRDDBUS15_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(15)", + OutTemp => PPCS1PLBRDDBUS_OUT(15), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(16), + GlitchData => PPCS1PLBRDDBUS16_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(16)", + OutTemp => PPCS1PLBRDDBUS_OUT(16), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(17), + GlitchData => PPCS1PLBRDDBUS17_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(17)", + OutTemp => PPCS1PLBRDDBUS_OUT(17), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(18), + GlitchData => PPCS1PLBRDDBUS18_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(18)", + OutTemp => PPCS1PLBRDDBUS_OUT(18), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(19), + GlitchData => PPCS1PLBRDDBUS19_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(19)", + OutTemp => PPCS1PLBRDDBUS_OUT(19), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(20), + GlitchData => PPCS1PLBRDDBUS20_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(20)", + OutTemp => PPCS1PLBRDDBUS_OUT(20), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(21), + GlitchData => PPCS1PLBRDDBUS21_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(21)", + OutTemp => PPCS1PLBRDDBUS_OUT(21), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(22), + GlitchData => PPCS1PLBRDDBUS22_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(22)", + OutTemp => PPCS1PLBRDDBUS_OUT(22), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(23), + GlitchData => PPCS1PLBRDDBUS23_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(23)", + OutTemp => PPCS1PLBRDDBUS_OUT(23), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(24), + GlitchData => PPCS1PLBRDDBUS24_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(24)", + OutTemp => PPCS1PLBRDDBUS_OUT(24), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(25), + GlitchData => PPCS1PLBRDDBUS25_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(25)", + OutTemp => PPCS1PLBRDDBUS_OUT(25), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(26), + GlitchData => PPCS1PLBRDDBUS26_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(26)", + OutTemp => PPCS1PLBRDDBUS_OUT(26), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(27), + GlitchData => PPCS1PLBRDDBUS27_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(27)", + OutTemp => PPCS1PLBRDDBUS_OUT(27), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(28), + GlitchData => PPCS1PLBRDDBUS28_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(28)", + OutTemp => PPCS1PLBRDDBUS_OUT(28), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(29), + GlitchData => PPCS1PLBRDDBUS29_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(29)", + OutTemp => PPCS1PLBRDDBUS_OUT(29), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(30), + GlitchData => PPCS1PLBRDDBUS30_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(30)", + OutTemp => PPCS1PLBRDDBUS_OUT(30), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(31), + GlitchData => PPCS1PLBRDDBUS31_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(31)", + OutTemp => PPCS1PLBRDDBUS_OUT(31), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(32), + GlitchData => PPCS1PLBRDDBUS32_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(32)", + OutTemp => PPCS1PLBRDDBUS_OUT(32), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(33), + GlitchData => PPCS1PLBRDDBUS33_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(33)", + OutTemp => PPCS1PLBRDDBUS_OUT(33), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(34), + GlitchData => PPCS1PLBRDDBUS34_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(34)", + OutTemp => PPCS1PLBRDDBUS_OUT(34), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(35), + GlitchData => PPCS1PLBRDDBUS35_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(35)", + OutTemp => PPCS1PLBRDDBUS_OUT(35), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(36), + GlitchData => PPCS1PLBRDDBUS36_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(36)", + OutTemp => PPCS1PLBRDDBUS_OUT(36), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(37), + GlitchData => PPCS1PLBRDDBUS37_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(37)", + OutTemp => PPCS1PLBRDDBUS_OUT(37), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(38), + GlitchData => PPCS1PLBRDDBUS38_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(38)", + OutTemp => PPCS1PLBRDDBUS_OUT(38), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(39), + GlitchData => PPCS1PLBRDDBUS39_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(39)", + OutTemp => PPCS1PLBRDDBUS_OUT(39), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(40), + GlitchData => PPCS1PLBRDDBUS40_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(40)", + OutTemp => PPCS1PLBRDDBUS_OUT(40), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(41), + GlitchData => PPCS1PLBRDDBUS41_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(41)", + OutTemp => PPCS1PLBRDDBUS_OUT(41), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(42), + GlitchData => PPCS1PLBRDDBUS42_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(42)", + OutTemp => PPCS1PLBRDDBUS_OUT(42), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(43), + GlitchData => PPCS1PLBRDDBUS43_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(43)", + OutTemp => PPCS1PLBRDDBUS_OUT(43), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(44), + GlitchData => PPCS1PLBRDDBUS44_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(44)", + OutTemp => PPCS1PLBRDDBUS_OUT(44), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(45), + GlitchData => PPCS1PLBRDDBUS45_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(45)", + OutTemp => PPCS1PLBRDDBUS_OUT(45), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(46), + GlitchData => PPCS1PLBRDDBUS46_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(46)", + OutTemp => PPCS1PLBRDDBUS_OUT(46), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(47), + GlitchData => PPCS1PLBRDDBUS47_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(47)", + OutTemp => PPCS1PLBRDDBUS_OUT(47), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(48), + GlitchData => PPCS1PLBRDDBUS48_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(48)", + OutTemp => PPCS1PLBRDDBUS_OUT(48), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(49), + GlitchData => PPCS1PLBRDDBUS49_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(49)", + OutTemp => PPCS1PLBRDDBUS_OUT(49), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(50), + GlitchData => PPCS1PLBRDDBUS50_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(50)", + OutTemp => PPCS1PLBRDDBUS_OUT(50), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(51), + GlitchData => PPCS1PLBRDDBUS51_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(51)", + OutTemp => PPCS1PLBRDDBUS_OUT(51), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(52), + GlitchData => PPCS1PLBRDDBUS52_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(52)", + OutTemp => PPCS1PLBRDDBUS_OUT(52), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(53), + GlitchData => PPCS1PLBRDDBUS53_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(53)", + OutTemp => PPCS1PLBRDDBUS_OUT(53), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(54), + GlitchData => PPCS1PLBRDDBUS54_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(54)", + OutTemp => PPCS1PLBRDDBUS_OUT(54), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(55), + GlitchData => PPCS1PLBRDDBUS55_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(55)", + OutTemp => PPCS1PLBRDDBUS_OUT(55), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(56), + GlitchData => PPCS1PLBRDDBUS56_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(56)", + OutTemp => PPCS1PLBRDDBUS_OUT(56), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(57), + GlitchData => PPCS1PLBRDDBUS57_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(57)", + OutTemp => PPCS1PLBRDDBUS_OUT(57), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(58), + GlitchData => PPCS1PLBRDDBUS58_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(58)", + OutTemp => PPCS1PLBRDDBUS_OUT(58), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(59), + GlitchData => PPCS1PLBRDDBUS59_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(59)", + OutTemp => PPCS1PLBRDDBUS_OUT(59), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(60), + GlitchData => PPCS1PLBRDDBUS60_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(60)", + OutTemp => PPCS1PLBRDDBUS_OUT(60), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(61), + GlitchData => PPCS1PLBRDDBUS61_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(61)", + OutTemp => PPCS1PLBRDDBUS_OUT(61), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(62), + GlitchData => PPCS1PLBRDDBUS62_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(62)", + OutTemp => PPCS1PLBRDDBUS_OUT(62), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(63), + GlitchData => PPCS1PLBRDDBUS63_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(63)", + OutTemp => PPCS1PLBRDDBUS_OUT(63), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(64), + GlitchData => PPCS1PLBRDDBUS64_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(64)", + OutTemp => PPCS1PLBRDDBUS_OUT(64), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(65), + GlitchData => PPCS1PLBRDDBUS65_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(65)", + OutTemp => PPCS1PLBRDDBUS_OUT(65), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(66), + GlitchData => PPCS1PLBRDDBUS66_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(66)", + OutTemp => PPCS1PLBRDDBUS_OUT(66), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(67), + GlitchData => PPCS1PLBRDDBUS67_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(67)", + OutTemp => PPCS1PLBRDDBUS_OUT(67), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(68), + GlitchData => PPCS1PLBRDDBUS68_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(68)", + OutTemp => PPCS1PLBRDDBUS_OUT(68), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(69), + GlitchData => PPCS1PLBRDDBUS69_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(69)", + OutTemp => PPCS1PLBRDDBUS_OUT(69), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(70), + GlitchData => PPCS1PLBRDDBUS70_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(70)", + OutTemp => PPCS1PLBRDDBUS_OUT(70), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(71), + GlitchData => PPCS1PLBRDDBUS71_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(71)", + OutTemp => PPCS1PLBRDDBUS_OUT(71), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(72), + GlitchData => PPCS1PLBRDDBUS72_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(72)", + OutTemp => PPCS1PLBRDDBUS_OUT(72), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(73), + GlitchData => PPCS1PLBRDDBUS73_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(73)", + OutTemp => PPCS1PLBRDDBUS_OUT(73), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(74), + GlitchData => PPCS1PLBRDDBUS74_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(74)", + OutTemp => PPCS1PLBRDDBUS_OUT(74), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(75), + GlitchData => PPCS1PLBRDDBUS75_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(75)", + OutTemp => PPCS1PLBRDDBUS_OUT(75), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(76), + GlitchData => PPCS1PLBRDDBUS76_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(76)", + OutTemp => PPCS1PLBRDDBUS_OUT(76), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(77), + GlitchData => PPCS1PLBRDDBUS77_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(77)", + OutTemp => PPCS1PLBRDDBUS_OUT(77), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(78), + GlitchData => PPCS1PLBRDDBUS78_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(78)", + OutTemp => PPCS1PLBRDDBUS_OUT(78), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(79), + GlitchData => PPCS1PLBRDDBUS79_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(79)", + OutTemp => PPCS1PLBRDDBUS_OUT(79), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(80), + GlitchData => PPCS1PLBRDDBUS80_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(80)", + OutTemp => PPCS1PLBRDDBUS_OUT(80), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(81), + GlitchData => PPCS1PLBRDDBUS81_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(81)", + OutTemp => PPCS1PLBRDDBUS_OUT(81), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(82), + GlitchData => PPCS1PLBRDDBUS82_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(82)", + OutTemp => PPCS1PLBRDDBUS_OUT(82), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(83), + GlitchData => PPCS1PLBRDDBUS83_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(83)", + OutTemp => PPCS1PLBRDDBUS_OUT(83), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(84), + GlitchData => PPCS1PLBRDDBUS84_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(84)", + OutTemp => PPCS1PLBRDDBUS_OUT(84), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(85), + GlitchData => PPCS1PLBRDDBUS85_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(85)", + OutTemp => PPCS1PLBRDDBUS_OUT(85), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(86), + GlitchData => PPCS1PLBRDDBUS86_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(86)", + OutTemp => PPCS1PLBRDDBUS_OUT(86), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(87), + GlitchData => PPCS1PLBRDDBUS87_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(87)", + OutTemp => PPCS1PLBRDDBUS_OUT(87), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(88), + GlitchData => PPCS1PLBRDDBUS88_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(88)", + OutTemp => PPCS1PLBRDDBUS_OUT(88), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(89), + GlitchData => PPCS1PLBRDDBUS89_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(89)", + OutTemp => PPCS1PLBRDDBUS_OUT(89), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(90), + GlitchData => PPCS1PLBRDDBUS90_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(90)", + OutTemp => PPCS1PLBRDDBUS_OUT(90), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(91), + GlitchData => PPCS1PLBRDDBUS91_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(91)", + OutTemp => PPCS1PLBRDDBUS_OUT(91), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(92), + GlitchData => PPCS1PLBRDDBUS92_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(92)", + OutTemp => PPCS1PLBRDDBUS_OUT(92), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(93), + GlitchData => PPCS1PLBRDDBUS93_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(93)", + OutTemp => PPCS1PLBRDDBUS_OUT(93), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(94), + GlitchData => PPCS1PLBRDDBUS94_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(94)", + OutTemp => PPCS1PLBRDDBUS_OUT(94), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(95), + GlitchData => PPCS1PLBRDDBUS95_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(95)", + OutTemp => PPCS1PLBRDDBUS_OUT(95), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(96), + GlitchData => PPCS1PLBRDDBUS96_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(96)", + OutTemp => PPCS1PLBRDDBUS_OUT(96), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(97), + GlitchData => PPCS1PLBRDDBUS97_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(97)", + OutTemp => PPCS1PLBRDDBUS_OUT(97), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(98), + GlitchData => PPCS1PLBRDDBUS98_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(98)", + OutTemp => PPCS1PLBRDDBUS_OUT(98), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(99), + GlitchData => PPCS1PLBRDDBUS99_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(99)", + OutTemp => PPCS1PLBRDDBUS_OUT(99), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(100), + GlitchData => PPCS1PLBRDDBUS100_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(100)", + OutTemp => PPCS1PLBRDDBUS_OUT(100), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(101), + GlitchData => PPCS1PLBRDDBUS101_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(101)", + OutTemp => PPCS1PLBRDDBUS_OUT(101), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(102), + GlitchData => PPCS1PLBRDDBUS102_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(102)", + OutTemp => PPCS1PLBRDDBUS_OUT(102), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(103), + GlitchData => PPCS1PLBRDDBUS103_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(103)", + OutTemp => PPCS1PLBRDDBUS_OUT(103), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(104), + GlitchData => PPCS1PLBRDDBUS104_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(104)", + OutTemp => PPCS1PLBRDDBUS_OUT(104), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(105), + GlitchData => PPCS1PLBRDDBUS105_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(105)", + OutTemp => PPCS1PLBRDDBUS_OUT(105), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(106), + GlitchData => PPCS1PLBRDDBUS106_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(106)", + OutTemp => PPCS1PLBRDDBUS_OUT(106), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(107), + GlitchData => PPCS1PLBRDDBUS107_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(107)", + OutTemp => PPCS1PLBRDDBUS_OUT(107), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(108), + GlitchData => PPCS1PLBRDDBUS108_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(108)", + OutTemp => PPCS1PLBRDDBUS_OUT(108), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(109), + GlitchData => PPCS1PLBRDDBUS109_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(109)", + OutTemp => PPCS1PLBRDDBUS_OUT(109), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(110), + GlitchData => PPCS1PLBRDDBUS110_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(110)", + OutTemp => PPCS1PLBRDDBUS_OUT(110), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(111), + GlitchData => PPCS1PLBRDDBUS111_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(111)", + OutTemp => PPCS1PLBRDDBUS_OUT(111), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(112), + GlitchData => PPCS1PLBRDDBUS112_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(112)", + OutTemp => PPCS1PLBRDDBUS_OUT(112), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(113), + GlitchData => PPCS1PLBRDDBUS113_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(113)", + OutTemp => PPCS1PLBRDDBUS_OUT(113), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(114), + GlitchData => PPCS1PLBRDDBUS114_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(114)", + OutTemp => PPCS1PLBRDDBUS_OUT(114), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(115), + GlitchData => PPCS1PLBRDDBUS115_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(115)", + OutTemp => PPCS1PLBRDDBUS_OUT(115), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(116), + GlitchData => PPCS1PLBRDDBUS116_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(116)", + OutTemp => PPCS1PLBRDDBUS_OUT(116), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(117), + GlitchData => PPCS1PLBRDDBUS117_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(117)", + OutTemp => PPCS1PLBRDDBUS_OUT(117), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(118), + GlitchData => PPCS1PLBRDDBUS118_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(118)", + OutTemp => PPCS1PLBRDDBUS_OUT(118), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(119), + GlitchData => PPCS1PLBRDDBUS119_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(119)", + OutTemp => PPCS1PLBRDDBUS_OUT(119), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(120), + GlitchData => PPCS1PLBRDDBUS120_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(120)", + OutTemp => PPCS1PLBRDDBUS_OUT(120), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(121), + GlitchData => PPCS1PLBRDDBUS121_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(121)", + OutTemp => PPCS1PLBRDDBUS_OUT(121), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(122), + GlitchData => PPCS1PLBRDDBUS122_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(122)", + OutTemp => PPCS1PLBRDDBUS_OUT(122), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(123), + GlitchData => PPCS1PLBRDDBUS123_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(123)", + OutTemp => PPCS1PLBRDDBUS_OUT(123), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(124), + GlitchData => PPCS1PLBRDDBUS124_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(124)", + OutTemp => PPCS1PLBRDDBUS_OUT(124), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(125), + GlitchData => PPCS1PLBRDDBUS125_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(125)", + OutTemp => PPCS1PLBRDDBUS_OUT(125), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(126), + GlitchData => PPCS1PLBRDDBUS126_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(126)", + OutTemp => PPCS1PLBRDDBUS_OUT(126), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDDBUS(127), + GlitchData => PPCS1PLBRDDBUS127_GlitchData, + OutSignalName => "PPCS1PLBRDDBUS(127)", + OutTemp => PPCS1PLBRDDBUS_OUT(127), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDWDADDR(0), + GlitchData => PPCS1PLBRDWDADDR0_GlitchData, + OutSignalName => "PPCS1PLBRDWDADDR(0)", + OutTemp => PPCS1PLBRDWDADDR_OUT(0), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDWDADDR(1), + GlitchData => PPCS1PLBRDWDADDR1_GlitchData, + OutSignalName => "PPCS1PLBRDWDADDR(1)", + OutTemp => PPCS1PLBRDWDADDR_OUT(1), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDWDADDR(2), + GlitchData => PPCS1PLBRDWDADDR2_GlitchData, + OutSignalName => "PPCS1PLBRDWDADDR(2)", + OutTemp => PPCS1PLBRDWDADDR_OUT(2), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBRDWDADDR(3), + GlitchData => PPCS1PLBRDWDADDR3_GlitchData, + OutSignalName => "PPCS1PLBRDWDADDR(3)", + OutTemp => PPCS1PLBRDWDADDR_OUT(3), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBREARBITRATE, + GlitchData => PPCS1PLBREARBITRATE_GlitchData, + OutSignalName => "PPCS1PLBREARBITRATE", + OutTemp => PPCS1PLBREARBITRATE_OUT, + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBSSIZE(0), + GlitchData => PPCS1PLBSSIZE0_GlitchData, + OutSignalName => "PPCS1PLBSSIZE(0)", + OutTemp => PPCS1PLBSSIZE_OUT(0), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBSSIZE(1), + GlitchData => PPCS1PLBSSIZE1_GlitchData, + OutSignalName => "PPCS1PLBSSIZE(1)", + OutTemp => PPCS1PLBSSIZE_OUT(1), + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBWAIT, + GlitchData => PPCS1PLBWAIT_GlitchData, + OutSignalName => "PPCS1PLBWAIT", + OutTemp => PPCS1PLBWAIT_OUT, + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBWRBTERM, + GlitchData => PPCS1PLBWRBTERM_GlitchData, + OutSignalName => "PPCS1PLBWRBTERM", + OutTemp => PPCS1PLBWRBTERM_OUT, + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBWRCOMP, + GlitchData => PPCS1PLBWRCOMP_GlitchData, + OutSignalName => "PPCS1PLBWRCOMP", + OutTemp => PPCS1PLBWRCOMP_OUT, + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCS1PLBWRDACK, + GlitchData => PPCS1PLBWRDACK_GlitchData, + OutSignalName => "PPCS1PLBWRDACK", + OutTemp => PPCS1PLBWRDACK_OUT, + Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECFPUOP, + GlitchData => APUFCMDECFPUOP_GlitchData, + OutSignalName => "APUFCMDECFPUOP", + OutTemp => APUFCMDECFPUOP_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECLDSTXFERSIZE(0), + GlitchData => APUFCMDECLDSTXFERSIZE0_GlitchData, + OutSignalName => "APUFCMDECLDSTXFERSIZE(0)", + OutTemp => APUFCMDECLDSTXFERSIZE_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECLDSTXFERSIZE(1), + GlitchData => APUFCMDECLDSTXFERSIZE1_GlitchData, + OutSignalName => "APUFCMDECLDSTXFERSIZE(1)", + OutTemp => APUFCMDECLDSTXFERSIZE_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECLDSTXFERSIZE(2), + GlitchData => APUFCMDECLDSTXFERSIZE2_GlitchData, + OutSignalName => "APUFCMDECLDSTXFERSIZE(2)", + OutTemp => APUFCMDECLDSTXFERSIZE_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECLOAD, + GlitchData => APUFCMDECLOAD_GlitchData, + OutSignalName => "APUFCMDECLOAD", + OutTemp => APUFCMDECLOAD_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECNONAUTON, + GlitchData => APUFCMDECNONAUTON_GlitchData, + OutSignalName => "APUFCMDECNONAUTON", + OutTemp => APUFCMDECNONAUTON_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECSTORE, + GlitchData => APUFCMDECSTORE_GlitchData, + OutSignalName => "APUFCMDECSTORE", + OutTemp => APUFCMDECSTORE_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECUDI(0), + GlitchData => APUFCMDECUDI0_GlitchData, + OutSignalName => "APUFCMDECUDI(0)", + OutTemp => APUFCMDECUDI_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECUDI(1), + GlitchData => APUFCMDECUDI1_GlitchData, + OutSignalName => "APUFCMDECUDI(1)", + OutTemp => APUFCMDECUDI_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECUDI(2), + GlitchData => APUFCMDECUDI2_GlitchData, + OutSignalName => "APUFCMDECUDI(2)", + OutTemp => APUFCMDECUDI_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECUDI(3), + GlitchData => APUFCMDECUDI3_GlitchData, + OutSignalName => "APUFCMDECUDI(3)", + OutTemp => APUFCMDECUDI_OUT(3), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMDECUDIVALID, + GlitchData => APUFCMDECUDIVALID_GlitchData, + OutSignalName => "APUFCMDECUDIVALID", + OutTemp => APUFCMDECUDIVALID_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMENDIAN, + GlitchData => APUFCMENDIAN_GlitchData, + OutSignalName => "APUFCMENDIAN", + OutTemp => APUFCMENDIAN_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMFLUSH, + GlitchData => APUFCMFLUSH_GlitchData, + OutSignalName => "APUFCMFLUSH", + OutTemp => APUFCMFLUSH_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(0), + GlitchData => APUFCMINSTRUCTION0_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(0)", + OutTemp => APUFCMINSTRUCTION_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(1), + GlitchData => APUFCMINSTRUCTION1_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(1)", + OutTemp => APUFCMINSTRUCTION_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(2), + GlitchData => APUFCMINSTRUCTION2_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(2)", + OutTemp => APUFCMINSTRUCTION_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(3), + GlitchData => APUFCMINSTRUCTION3_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(3)", + OutTemp => APUFCMINSTRUCTION_OUT(3), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(4), + GlitchData => APUFCMINSTRUCTION4_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(4)", + OutTemp => APUFCMINSTRUCTION_OUT(4), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(5), + GlitchData => APUFCMINSTRUCTION5_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(5)", + OutTemp => APUFCMINSTRUCTION_OUT(5), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(6), + GlitchData => APUFCMINSTRUCTION6_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(6)", + OutTemp => APUFCMINSTRUCTION_OUT(6), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(7), + GlitchData => APUFCMINSTRUCTION7_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(7)", + OutTemp => APUFCMINSTRUCTION_OUT(7), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(8), + GlitchData => APUFCMINSTRUCTION8_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(8)", + OutTemp => APUFCMINSTRUCTION_OUT(8), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(9), + GlitchData => APUFCMINSTRUCTION9_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(9)", + OutTemp => APUFCMINSTRUCTION_OUT(9), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(10), + GlitchData => APUFCMINSTRUCTION10_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(10)", + OutTemp => APUFCMINSTRUCTION_OUT(10), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(11), + GlitchData => APUFCMINSTRUCTION11_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(11)", + OutTemp => APUFCMINSTRUCTION_OUT(11), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(12), + GlitchData => APUFCMINSTRUCTION12_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(12)", + OutTemp => APUFCMINSTRUCTION_OUT(12), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(13), + GlitchData => APUFCMINSTRUCTION13_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(13)", + OutTemp => APUFCMINSTRUCTION_OUT(13), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(14), + GlitchData => APUFCMINSTRUCTION14_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(14)", + OutTemp => APUFCMINSTRUCTION_OUT(14), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(15), + GlitchData => APUFCMINSTRUCTION15_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(15)", + OutTemp => APUFCMINSTRUCTION_OUT(15), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(16), + GlitchData => APUFCMINSTRUCTION16_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(16)", + OutTemp => APUFCMINSTRUCTION_OUT(16), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(17), + GlitchData => APUFCMINSTRUCTION17_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(17)", + OutTemp => APUFCMINSTRUCTION_OUT(17), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(18), + GlitchData => APUFCMINSTRUCTION18_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(18)", + OutTemp => APUFCMINSTRUCTION_OUT(18), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(19), + GlitchData => APUFCMINSTRUCTION19_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(19)", + OutTemp => APUFCMINSTRUCTION_OUT(19), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(20), + GlitchData => APUFCMINSTRUCTION20_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(20)", + OutTemp => APUFCMINSTRUCTION_OUT(20), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(21), + GlitchData => APUFCMINSTRUCTION21_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(21)", + OutTemp => APUFCMINSTRUCTION_OUT(21), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(22), + GlitchData => APUFCMINSTRUCTION22_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(22)", + OutTemp => APUFCMINSTRUCTION_OUT(22), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(23), + GlitchData => APUFCMINSTRUCTION23_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(23)", + OutTemp => APUFCMINSTRUCTION_OUT(23), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(24), + GlitchData => APUFCMINSTRUCTION24_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(24)", + OutTemp => APUFCMINSTRUCTION_OUT(24), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(25), + GlitchData => APUFCMINSTRUCTION25_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(25)", + OutTemp => APUFCMINSTRUCTION_OUT(25), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(26), + GlitchData => APUFCMINSTRUCTION26_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(26)", + OutTemp => APUFCMINSTRUCTION_OUT(26), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(27), + GlitchData => APUFCMINSTRUCTION27_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(27)", + OutTemp => APUFCMINSTRUCTION_OUT(27), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(28), + GlitchData => APUFCMINSTRUCTION28_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(28)", + OutTemp => APUFCMINSTRUCTION_OUT(28), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(29), + GlitchData => APUFCMINSTRUCTION29_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(29)", + OutTemp => APUFCMINSTRUCTION_OUT(29), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(30), + GlitchData => APUFCMINSTRUCTION30_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(30)", + OutTemp => APUFCMINSTRUCTION_OUT(30), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRUCTION(31), + GlitchData => APUFCMINSTRUCTION31_GlitchData, + OutSignalName => "APUFCMINSTRUCTION(31)", + OutTemp => APUFCMINSTRUCTION_OUT(31), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMINSTRVALID, + GlitchData => APUFCMINSTRVALID_GlitchData, + OutSignalName => "APUFCMINSTRVALID", + OutTemp => APUFCMINSTRVALID_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADBYTEADDR(0), + GlitchData => APUFCMLOADBYTEADDR0_GlitchData, + OutSignalName => "APUFCMLOADBYTEADDR(0)", + OutTemp => APUFCMLOADBYTEADDR_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADBYTEADDR(1), + GlitchData => APUFCMLOADBYTEADDR1_GlitchData, + OutSignalName => "APUFCMLOADBYTEADDR(1)", + OutTemp => APUFCMLOADBYTEADDR_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADBYTEADDR(2), + GlitchData => APUFCMLOADBYTEADDR2_GlitchData, + OutSignalName => "APUFCMLOADBYTEADDR(2)", + OutTemp => APUFCMLOADBYTEADDR_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADBYTEADDR(3), + GlitchData => APUFCMLOADBYTEADDR3_GlitchData, + OutSignalName => "APUFCMLOADBYTEADDR(3)", + OutTemp => APUFCMLOADBYTEADDR_OUT(3), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(0), + GlitchData => APUFCMLOADDATA0_GlitchData, + OutSignalName => "APUFCMLOADDATA(0)", + OutTemp => APUFCMLOADDATA_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(1), + GlitchData => APUFCMLOADDATA1_GlitchData, + OutSignalName => "APUFCMLOADDATA(1)", + OutTemp => APUFCMLOADDATA_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(2), + GlitchData => APUFCMLOADDATA2_GlitchData, + OutSignalName => "APUFCMLOADDATA(2)", + OutTemp => APUFCMLOADDATA_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(3), + GlitchData => APUFCMLOADDATA3_GlitchData, + OutSignalName => "APUFCMLOADDATA(3)", + OutTemp => APUFCMLOADDATA_OUT(3), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(4), + GlitchData => APUFCMLOADDATA4_GlitchData, + OutSignalName => "APUFCMLOADDATA(4)", + OutTemp => APUFCMLOADDATA_OUT(4), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(5), + GlitchData => APUFCMLOADDATA5_GlitchData, + OutSignalName => "APUFCMLOADDATA(5)", + OutTemp => APUFCMLOADDATA_OUT(5), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(6), + GlitchData => APUFCMLOADDATA6_GlitchData, + OutSignalName => "APUFCMLOADDATA(6)", + OutTemp => APUFCMLOADDATA_OUT(6), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(7), + GlitchData => APUFCMLOADDATA7_GlitchData, + OutSignalName => "APUFCMLOADDATA(7)", + OutTemp => APUFCMLOADDATA_OUT(7), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(8), + GlitchData => APUFCMLOADDATA8_GlitchData, + OutSignalName => "APUFCMLOADDATA(8)", + OutTemp => APUFCMLOADDATA_OUT(8), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(9), + GlitchData => APUFCMLOADDATA9_GlitchData, + OutSignalName => "APUFCMLOADDATA(9)", + OutTemp => APUFCMLOADDATA_OUT(9), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(10), + GlitchData => APUFCMLOADDATA10_GlitchData, + OutSignalName => "APUFCMLOADDATA(10)", + OutTemp => APUFCMLOADDATA_OUT(10), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(11), + GlitchData => APUFCMLOADDATA11_GlitchData, + OutSignalName => "APUFCMLOADDATA(11)", + OutTemp => APUFCMLOADDATA_OUT(11), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(12), + GlitchData => APUFCMLOADDATA12_GlitchData, + OutSignalName => "APUFCMLOADDATA(12)", + OutTemp => APUFCMLOADDATA_OUT(12), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(13), + GlitchData => APUFCMLOADDATA13_GlitchData, + OutSignalName => "APUFCMLOADDATA(13)", + OutTemp => APUFCMLOADDATA_OUT(13), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(14), + GlitchData => APUFCMLOADDATA14_GlitchData, + OutSignalName => "APUFCMLOADDATA(14)", + OutTemp => APUFCMLOADDATA_OUT(14), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(15), + GlitchData => APUFCMLOADDATA15_GlitchData, + OutSignalName => "APUFCMLOADDATA(15)", + OutTemp => APUFCMLOADDATA_OUT(15), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(16), + GlitchData => APUFCMLOADDATA16_GlitchData, + OutSignalName => "APUFCMLOADDATA(16)", + OutTemp => APUFCMLOADDATA_OUT(16), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(17), + GlitchData => APUFCMLOADDATA17_GlitchData, + OutSignalName => "APUFCMLOADDATA(17)", + OutTemp => APUFCMLOADDATA_OUT(17), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(18), + GlitchData => APUFCMLOADDATA18_GlitchData, + OutSignalName => "APUFCMLOADDATA(18)", + OutTemp => APUFCMLOADDATA_OUT(18), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(19), + GlitchData => APUFCMLOADDATA19_GlitchData, + OutSignalName => "APUFCMLOADDATA(19)", + OutTemp => APUFCMLOADDATA_OUT(19), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(20), + GlitchData => APUFCMLOADDATA20_GlitchData, + OutSignalName => "APUFCMLOADDATA(20)", + OutTemp => APUFCMLOADDATA_OUT(20), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(21), + GlitchData => APUFCMLOADDATA21_GlitchData, + OutSignalName => "APUFCMLOADDATA(21)", + OutTemp => APUFCMLOADDATA_OUT(21), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(22), + GlitchData => APUFCMLOADDATA22_GlitchData, + OutSignalName => "APUFCMLOADDATA(22)", + OutTemp => APUFCMLOADDATA_OUT(22), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(23), + GlitchData => APUFCMLOADDATA23_GlitchData, + OutSignalName => "APUFCMLOADDATA(23)", + OutTemp => APUFCMLOADDATA_OUT(23), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(24), + GlitchData => APUFCMLOADDATA24_GlitchData, + OutSignalName => "APUFCMLOADDATA(24)", + OutTemp => APUFCMLOADDATA_OUT(24), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(25), + GlitchData => APUFCMLOADDATA25_GlitchData, + OutSignalName => "APUFCMLOADDATA(25)", + OutTemp => APUFCMLOADDATA_OUT(25), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(26), + GlitchData => APUFCMLOADDATA26_GlitchData, + OutSignalName => "APUFCMLOADDATA(26)", + OutTemp => APUFCMLOADDATA_OUT(26), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(27), + GlitchData => APUFCMLOADDATA27_GlitchData, + OutSignalName => "APUFCMLOADDATA(27)", + OutTemp => APUFCMLOADDATA_OUT(27), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(28), + GlitchData => APUFCMLOADDATA28_GlitchData, + OutSignalName => "APUFCMLOADDATA(28)", + OutTemp => APUFCMLOADDATA_OUT(28), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(29), + GlitchData => APUFCMLOADDATA29_GlitchData, + OutSignalName => "APUFCMLOADDATA(29)", + OutTemp => APUFCMLOADDATA_OUT(29), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(30), + GlitchData => APUFCMLOADDATA30_GlitchData, + OutSignalName => "APUFCMLOADDATA(30)", + OutTemp => APUFCMLOADDATA_OUT(30), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(31), + GlitchData => APUFCMLOADDATA31_GlitchData, + OutSignalName => "APUFCMLOADDATA(31)", + OutTemp => APUFCMLOADDATA_OUT(31), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(32), + GlitchData => APUFCMLOADDATA32_GlitchData, + OutSignalName => "APUFCMLOADDATA(32)", + OutTemp => APUFCMLOADDATA_OUT(32), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(33), + GlitchData => APUFCMLOADDATA33_GlitchData, + OutSignalName => "APUFCMLOADDATA(33)", + OutTemp => APUFCMLOADDATA_OUT(33), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(34), + GlitchData => APUFCMLOADDATA34_GlitchData, + OutSignalName => "APUFCMLOADDATA(34)", + OutTemp => APUFCMLOADDATA_OUT(34), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(35), + GlitchData => APUFCMLOADDATA35_GlitchData, + OutSignalName => "APUFCMLOADDATA(35)", + OutTemp => APUFCMLOADDATA_OUT(35), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(36), + GlitchData => APUFCMLOADDATA36_GlitchData, + OutSignalName => "APUFCMLOADDATA(36)", + OutTemp => APUFCMLOADDATA_OUT(36), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(37), + GlitchData => APUFCMLOADDATA37_GlitchData, + OutSignalName => "APUFCMLOADDATA(37)", + OutTemp => APUFCMLOADDATA_OUT(37), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(38), + GlitchData => APUFCMLOADDATA38_GlitchData, + OutSignalName => "APUFCMLOADDATA(38)", + OutTemp => APUFCMLOADDATA_OUT(38), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(39), + GlitchData => APUFCMLOADDATA39_GlitchData, + OutSignalName => "APUFCMLOADDATA(39)", + OutTemp => APUFCMLOADDATA_OUT(39), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(40), + GlitchData => APUFCMLOADDATA40_GlitchData, + OutSignalName => "APUFCMLOADDATA(40)", + OutTemp => APUFCMLOADDATA_OUT(40), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(41), + GlitchData => APUFCMLOADDATA41_GlitchData, + OutSignalName => "APUFCMLOADDATA(41)", + OutTemp => APUFCMLOADDATA_OUT(41), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(42), + GlitchData => APUFCMLOADDATA42_GlitchData, + OutSignalName => "APUFCMLOADDATA(42)", + OutTemp => APUFCMLOADDATA_OUT(42), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(43), + GlitchData => APUFCMLOADDATA43_GlitchData, + OutSignalName => "APUFCMLOADDATA(43)", + OutTemp => APUFCMLOADDATA_OUT(43), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(44), + GlitchData => APUFCMLOADDATA44_GlitchData, + OutSignalName => "APUFCMLOADDATA(44)", + OutTemp => APUFCMLOADDATA_OUT(44), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(45), + GlitchData => APUFCMLOADDATA45_GlitchData, + OutSignalName => "APUFCMLOADDATA(45)", + OutTemp => APUFCMLOADDATA_OUT(45), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(46), + GlitchData => APUFCMLOADDATA46_GlitchData, + OutSignalName => "APUFCMLOADDATA(46)", + OutTemp => APUFCMLOADDATA_OUT(46), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(47), + GlitchData => APUFCMLOADDATA47_GlitchData, + OutSignalName => "APUFCMLOADDATA(47)", + OutTemp => APUFCMLOADDATA_OUT(47), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(48), + GlitchData => APUFCMLOADDATA48_GlitchData, + OutSignalName => "APUFCMLOADDATA(48)", + OutTemp => APUFCMLOADDATA_OUT(48), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(49), + GlitchData => APUFCMLOADDATA49_GlitchData, + OutSignalName => "APUFCMLOADDATA(49)", + OutTemp => APUFCMLOADDATA_OUT(49), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(50), + GlitchData => APUFCMLOADDATA50_GlitchData, + OutSignalName => "APUFCMLOADDATA(50)", + OutTemp => APUFCMLOADDATA_OUT(50), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(51), + GlitchData => APUFCMLOADDATA51_GlitchData, + OutSignalName => "APUFCMLOADDATA(51)", + OutTemp => APUFCMLOADDATA_OUT(51), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(52), + GlitchData => APUFCMLOADDATA52_GlitchData, + OutSignalName => "APUFCMLOADDATA(52)", + OutTemp => APUFCMLOADDATA_OUT(52), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(53), + GlitchData => APUFCMLOADDATA53_GlitchData, + OutSignalName => "APUFCMLOADDATA(53)", + OutTemp => APUFCMLOADDATA_OUT(53), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(54), + GlitchData => APUFCMLOADDATA54_GlitchData, + OutSignalName => "APUFCMLOADDATA(54)", + OutTemp => APUFCMLOADDATA_OUT(54), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(55), + GlitchData => APUFCMLOADDATA55_GlitchData, + OutSignalName => "APUFCMLOADDATA(55)", + OutTemp => APUFCMLOADDATA_OUT(55), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(56), + GlitchData => APUFCMLOADDATA56_GlitchData, + OutSignalName => "APUFCMLOADDATA(56)", + OutTemp => APUFCMLOADDATA_OUT(56), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(57), + GlitchData => APUFCMLOADDATA57_GlitchData, + OutSignalName => "APUFCMLOADDATA(57)", + OutTemp => APUFCMLOADDATA_OUT(57), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(58), + GlitchData => APUFCMLOADDATA58_GlitchData, + OutSignalName => "APUFCMLOADDATA(58)", + OutTemp => APUFCMLOADDATA_OUT(58), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(59), + GlitchData => APUFCMLOADDATA59_GlitchData, + OutSignalName => "APUFCMLOADDATA(59)", + OutTemp => APUFCMLOADDATA_OUT(59), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(60), + GlitchData => APUFCMLOADDATA60_GlitchData, + OutSignalName => "APUFCMLOADDATA(60)", + OutTemp => APUFCMLOADDATA_OUT(60), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(61), + GlitchData => APUFCMLOADDATA61_GlitchData, + OutSignalName => "APUFCMLOADDATA(61)", + OutTemp => APUFCMLOADDATA_OUT(61), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(62), + GlitchData => APUFCMLOADDATA62_GlitchData, + OutSignalName => "APUFCMLOADDATA(62)", + OutTemp => APUFCMLOADDATA_OUT(62), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(63), + GlitchData => APUFCMLOADDATA63_GlitchData, + OutSignalName => "APUFCMLOADDATA(63)", + OutTemp => APUFCMLOADDATA_OUT(63), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(64), + GlitchData => APUFCMLOADDATA64_GlitchData, + OutSignalName => "APUFCMLOADDATA(64)", + OutTemp => APUFCMLOADDATA_OUT(64), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(65), + GlitchData => APUFCMLOADDATA65_GlitchData, + OutSignalName => "APUFCMLOADDATA(65)", + OutTemp => APUFCMLOADDATA_OUT(65), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(66), + GlitchData => APUFCMLOADDATA66_GlitchData, + OutSignalName => "APUFCMLOADDATA(66)", + OutTemp => APUFCMLOADDATA_OUT(66), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(67), + GlitchData => APUFCMLOADDATA67_GlitchData, + OutSignalName => "APUFCMLOADDATA(67)", + OutTemp => APUFCMLOADDATA_OUT(67), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(68), + GlitchData => APUFCMLOADDATA68_GlitchData, + OutSignalName => "APUFCMLOADDATA(68)", + OutTemp => APUFCMLOADDATA_OUT(68), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(69), + GlitchData => APUFCMLOADDATA69_GlitchData, + OutSignalName => "APUFCMLOADDATA(69)", + OutTemp => APUFCMLOADDATA_OUT(69), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(70), + GlitchData => APUFCMLOADDATA70_GlitchData, + OutSignalName => "APUFCMLOADDATA(70)", + OutTemp => APUFCMLOADDATA_OUT(70), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(71), + GlitchData => APUFCMLOADDATA71_GlitchData, + OutSignalName => "APUFCMLOADDATA(71)", + OutTemp => APUFCMLOADDATA_OUT(71), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(72), + GlitchData => APUFCMLOADDATA72_GlitchData, + OutSignalName => "APUFCMLOADDATA(72)", + OutTemp => APUFCMLOADDATA_OUT(72), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(73), + GlitchData => APUFCMLOADDATA73_GlitchData, + OutSignalName => "APUFCMLOADDATA(73)", + OutTemp => APUFCMLOADDATA_OUT(73), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(74), + GlitchData => APUFCMLOADDATA74_GlitchData, + OutSignalName => "APUFCMLOADDATA(74)", + OutTemp => APUFCMLOADDATA_OUT(74), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(75), + GlitchData => APUFCMLOADDATA75_GlitchData, + OutSignalName => "APUFCMLOADDATA(75)", + OutTemp => APUFCMLOADDATA_OUT(75), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(76), + GlitchData => APUFCMLOADDATA76_GlitchData, + OutSignalName => "APUFCMLOADDATA(76)", + OutTemp => APUFCMLOADDATA_OUT(76), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(77), + GlitchData => APUFCMLOADDATA77_GlitchData, + OutSignalName => "APUFCMLOADDATA(77)", + OutTemp => APUFCMLOADDATA_OUT(77), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(78), + GlitchData => APUFCMLOADDATA78_GlitchData, + OutSignalName => "APUFCMLOADDATA(78)", + OutTemp => APUFCMLOADDATA_OUT(78), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(79), + GlitchData => APUFCMLOADDATA79_GlitchData, + OutSignalName => "APUFCMLOADDATA(79)", + OutTemp => APUFCMLOADDATA_OUT(79), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(80), + GlitchData => APUFCMLOADDATA80_GlitchData, + OutSignalName => "APUFCMLOADDATA(80)", + OutTemp => APUFCMLOADDATA_OUT(80), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(81), + GlitchData => APUFCMLOADDATA81_GlitchData, + OutSignalName => "APUFCMLOADDATA(81)", + OutTemp => APUFCMLOADDATA_OUT(81), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(82), + GlitchData => APUFCMLOADDATA82_GlitchData, + OutSignalName => "APUFCMLOADDATA(82)", + OutTemp => APUFCMLOADDATA_OUT(82), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(83), + GlitchData => APUFCMLOADDATA83_GlitchData, + OutSignalName => "APUFCMLOADDATA(83)", + OutTemp => APUFCMLOADDATA_OUT(83), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(84), + GlitchData => APUFCMLOADDATA84_GlitchData, + OutSignalName => "APUFCMLOADDATA(84)", + OutTemp => APUFCMLOADDATA_OUT(84), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(85), + GlitchData => APUFCMLOADDATA85_GlitchData, + OutSignalName => "APUFCMLOADDATA(85)", + OutTemp => APUFCMLOADDATA_OUT(85), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(86), + GlitchData => APUFCMLOADDATA86_GlitchData, + OutSignalName => "APUFCMLOADDATA(86)", + OutTemp => APUFCMLOADDATA_OUT(86), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(87), + GlitchData => APUFCMLOADDATA87_GlitchData, + OutSignalName => "APUFCMLOADDATA(87)", + OutTemp => APUFCMLOADDATA_OUT(87), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(88), + GlitchData => APUFCMLOADDATA88_GlitchData, + OutSignalName => "APUFCMLOADDATA(88)", + OutTemp => APUFCMLOADDATA_OUT(88), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(89), + GlitchData => APUFCMLOADDATA89_GlitchData, + OutSignalName => "APUFCMLOADDATA(89)", + OutTemp => APUFCMLOADDATA_OUT(89), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(90), + GlitchData => APUFCMLOADDATA90_GlitchData, + OutSignalName => "APUFCMLOADDATA(90)", + OutTemp => APUFCMLOADDATA_OUT(90), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(91), + GlitchData => APUFCMLOADDATA91_GlitchData, + OutSignalName => "APUFCMLOADDATA(91)", + OutTemp => APUFCMLOADDATA_OUT(91), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(92), + GlitchData => APUFCMLOADDATA92_GlitchData, + OutSignalName => "APUFCMLOADDATA(92)", + OutTemp => APUFCMLOADDATA_OUT(92), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(93), + GlitchData => APUFCMLOADDATA93_GlitchData, + OutSignalName => "APUFCMLOADDATA(93)", + OutTemp => APUFCMLOADDATA_OUT(93), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(94), + GlitchData => APUFCMLOADDATA94_GlitchData, + OutSignalName => "APUFCMLOADDATA(94)", + OutTemp => APUFCMLOADDATA_OUT(94), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(95), + GlitchData => APUFCMLOADDATA95_GlitchData, + OutSignalName => "APUFCMLOADDATA(95)", + OutTemp => APUFCMLOADDATA_OUT(95), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(96), + GlitchData => APUFCMLOADDATA96_GlitchData, + OutSignalName => "APUFCMLOADDATA(96)", + OutTemp => APUFCMLOADDATA_OUT(96), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(97), + GlitchData => APUFCMLOADDATA97_GlitchData, + OutSignalName => "APUFCMLOADDATA(97)", + OutTemp => APUFCMLOADDATA_OUT(97), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(98), + GlitchData => APUFCMLOADDATA98_GlitchData, + OutSignalName => "APUFCMLOADDATA(98)", + OutTemp => APUFCMLOADDATA_OUT(98), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(99), + GlitchData => APUFCMLOADDATA99_GlitchData, + OutSignalName => "APUFCMLOADDATA(99)", + OutTemp => APUFCMLOADDATA_OUT(99), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(100), + GlitchData => APUFCMLOADDATA100_GlitchData, + OutSignalName => "APUFCMLOADDATA(100)", + OutTemp => APUFCMLOADDATA_OUT(100), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(101), + GlitchData => APUFCMLOADDATA101_GlitchData, + OutSignalName => "APUFCMLOADDATA(101)", + OutTemp => APUFCMLOADDATA_OUT(101), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(102), + GlitchData => APUFCMLOADDATA102_GlitchData, + OutSignalName => "APUFCMLOADDATA(102)", + OutTemp => APUFCMLOADDATA_OUT(102), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(103), + GlitchData => APUFCMLOADDATA103_GlitchData, + OutSignalName => "APUFCMLOADDATA(103)", + OutTemp => APUFCMLOADDATA_OUT(103), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(104), + GlitchData => APUFCMLOADDATA104_GlitchData, + OutSignalName => "APUFCMLOADDATA(104)", + OutTemp => APUFCMLOADDATA_OUT(104), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(105), + GlitchData => APUFCMLOADDATA105_GlitchData, + OutSignalName => "APUFCMLOADDATA(105)", + OutTemp => APUFCMLOADDATA_OUT(105), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(106), + GlitchData => APUFCMLOADDATA106_GlitchData, + OutSignalName => "APUFCMLOADDATA(106)", + OutTemp => APUFCMLOADDATA_OUT(106), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(107), + GlitchData => APUFCMLOADDATA107_GlitchData, + OutSignalName => "APUFCMLOADDATA(107)", + OutTemp => APUFCMLOADDATA_OUT(107), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(108), + GlitchData => APUFCMLOADDATA108_GlitchData, + OutSignalName => "APUFCMLOADDATA(108)", + OutTemp => APUFCMLOADDATA_OUT(108), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(109), + GlitchData => APUFCMLOADDATA109_GlitchData, + OutSignalName => "APUFCMLOADDATA(109)", + OutTemp => APUFCMLOADDATA_OUT(109), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(110), + GlitchData => APUFCMLOADDATA110_GlitchData, + OutSignalName => "APUFCMLOADDATA(110)", + OutTemp => APUFCMLOADDATA_OUT(110), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(111), + GlitchData => APUFCMLOADDATA111_GlitchData, + OutSignalName => "APUFCMLOADDATA(111)", + OutTemp => APUFCMLOADDATA_OUT(111), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(112), + GlitchData => APUFCMLOADDATA112_GlitchData, + OutSignalName => "APUFCMLOADDATA(112)", + OutTemp => APUFCMLOADDATA_OUT(112), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(113), + GlitchData => APUFCMLOADDATA113_GlitchData, + OutSignalName => "APUFCMLOADDATA(113)", + OutTemp => APUFCMLOADDATA_OUT(113), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(114), + GlitchData => APUFCMLOADDATA114_GlitchData, + OutSignalName => "APUFCMLOADDATA(114)", + OutTemp => APUFCMLOADDATA_OUT(114), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(115), + GlitchData => APUFCMLOADDATA115_GlitchData, + OutSignalName => "APUFCMLOADDATA(115)", + OutTemp => APUFCMLOADDATA_OUT(115), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(116), + GlitchData => APUFCMLOADDATA116_GlitchData, + OutSignalName => "APUFCMLOADDATA(116)", + OutTemp => APUFCMLOADDATA_OUT(116), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(117), + GlitchData => APUFCMLOADDATA117_GlitchData, + OutSignalName => "APUFCMLOADDATA(117)", + OutTemp => APUFCMLOADDATA_OUT(117), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(118), + GlitchData => APUFCMLOADDATA118_GlitchData, + OutSignalName => "APUFCMLOADDATA(118)", + OutTemp => APUFCMLOADDATA_OUT(118), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(119), + GlitchData => APUFCMLOADDATA119_GlitchData, + OutSignalName => "APUFCMLOADDATA(119)", + OutTemp => APUFCMLOADDATA_OUT(119), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(120), + GlitchData => APUFCMLOADDATA120_GlitchData, + OutSignalName => "APUFCMLOADDATA(120)", + OutTemp => APUFCMLOADDATA_OUT(120), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(121), + GlitchData => APUFCMLOADDATA121_GlitchData, + OutSignalName => "APUFCMLOADDATA(121)", + OutTemp => APUFCMLOADDATA_OUT(121), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(122), + GlitchData => APUFCMLOADDATA122_GlitchData, + OutSignalName => "APUFCMLOADDATA(122)", + OutTemp => APUFCMLOADDATA_OUT(122), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(123), + GlitchData => APUFCMLOADDATA123_GlitchData, + OutSignalName => "APUFCMLOADDATA(123)", + OutTemp => APUFCMLOADDATA_OUT(123), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(124), + GlitchData => APUFCMLOADDATA124_GlitchData, + OutSignalName => "APUFCMLOADDATA(124)", + OutTemp => APUFCMLOADDATA_OUT(124), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(125), + GlitchData => APUFCMLOADDATA125_GlitchData, + OutSignalName => "APUFCMLOADDATA(125)", + OutTemp => APUFCMLOADDATA_OUT(125), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(126), + GlitchData => APUFCMLOADDATA126_GlitchData, + OutSignalName => "APUFCMLOADDATA(126)", + OutTemp => APUFCMLOADDATA_OUT(126), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDATA(127), + GlitchData => APUFCMLOADDATA127_GlitchData, + OutSignalName => "APUFCMLOADDATA(127)", + OutTemp => APUFCMLOADDATA_OUT(127), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMLOADDVALID, + GlitchData => APUFCMLOADDVALID_GlitchData, + OutSignalName => "APUFCMLOADDVALID", + OutTemp => APUFCMLOADDVALID_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMMSRFE0, + GlitchData => APUFCMMSRFE0_GlitchData, + OutSignalName => "APUFCMMSRFE0", + OutTemp => APUFCMMSRFE0_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMMSRFE1, + GlitchData => APUFCMMSRFE1_GlitchData, + OutSignalName => "APUFCMMSRFE1", + OutTemp => APUFCMMSRFE1_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMNEXTINSTRREADY, + GlitchData => APUFCMNEXTINSTRREADY_GlitchData, + OutSignalName => "APUFCMNEXTINSTRREADY", + OutTemp => APUFCMNEXTINSTRREADY_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMOPERANDVALID, + GlitchData => APUFCMOPERANDVALID_GlitchData, + OutSignalName => "APUFCMOPERANDVALID", + OutTemp => APUFCMOPERANDVALID_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(0), + GlitchData => APUFCMRADATA0_GlitchData, + OutSignalName => "APUFCMRADATA(0)", + OutTemp => APUFCMRADATA_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(1), + GlitchData => APUFCMRADATA1_GlitchData, + OutSignalName => "APUFCMRADATA(1)", + OutTemp => APUFCMRADATA_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(2), + GlitchData => APUFCMRADATA2_GlitchData, + OutSignalName => "APUFCMRADATA(2)", + OutTemp => APUFCMRADATA_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(3), + GlitchData => APUFCMRADATA3_GlitchData, + OutSignalName => "APUFCMRADATA(3)", + OutTemp => APUFCMRADATA_OUT(3), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(4), + GlitchData => APUFCMRADATA4_GlitchData, + OutSignalName => "APUFCMRADATA(4)", + OutTemp => APUFCMRADATA_OUT(4), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(5), + GlitchData => APUFCMRADATA5_GlitchData, + OutSignalName => "APUFCMRADATA(5)", + OutTemp => APUFCMRADATA_OUT(5), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(6), + GlitchData => APUFCMRADATA6_GlitchData, + OutSignalName => "APUFCMRADATA(6)", + OutTemp => APUFCMRADATA_OUT(6), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(7), + GlitchData => APUFCMRADATA7_GlitchData, + OutSignalName => "APUFCMRADATA(7)", + OutTemp => APUFCMRADATA_OUT(7), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(8), + GlitchData => APUFCMRADATA8_GlitchData, + OutSignalName => "APUFCMRADATA(8)", + OutTemp => APUFCMRADATA_OUT(8), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(9), + GlitchData => APUFCMRADATA9_GlitchData, + OutSignalName => "APUFCMRADATA(9)", + OutTemp => APUFCMRADATA_OUT(9), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(10), + GlitchData => APUFCMRADATA10_GlitchData, + OutSignalName => "APUFCMRADATA(10)", + OutTemp => APUFCMRADATA_OUT(10), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(11), + GlitchData => APUFCMRADATA11_GlitchData, + OutSignalName => "APUFCMRADATA(11)", + OutTemp => APUFCMRADATA_OUT(11), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(12), + GlitchData => APUFCMRADATA12_GlitchData, + OutSignalName => "APUFCMRADATA(12)", + OutTemp => APUFCMRADATA_OUT(12), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(13), + GlitchData => APUFCMRADATA13_GlitchData, + OutSignalName => "APUFCMRADATA(13)", + OutTemp => APUFCMRADATA_OUT(13), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(14), + GlitchData => APUFCMRADATA14_GlitchData, + OutSignalName => "APUFCMRADATA(14)", + OutTemp => APUFCMRADATA_OUT(14), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(15), + GlitchData => APUFCMRADATA15_GlitchData, + OutSignalName => "APUFCMRADATA(15)", + OutTemp => APUFCMRADATA_OUT(15), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(16), + GlitchData => APUFCMRADATA16_GlitchData, + OutSignalName => "APUFCMRADATA(16)", + OutTemp => APUFCMRADATA_OUT(16), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(17), + GlitchData => APUFCMRADATA17_GlitchData, + OutSignalName => "APUFCMRADATA(17)", + OutTemp => APUFCMRADATA_OUT(17), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(18), + GlitchData => APUFCMRADATA18_GlitchData, + OutSignalName => "APUFCMRADATA(18)", + OutTemp => APUFCMRADATA_OUT(18), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(19), + GlitchData => APUFCMRADATA19_GlitchData, + OutSignalName => "APUFCMRADATA(19)", + OutTemp => APUFCMRADATA_OUT(19), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(20), + GlitchData => APUFCMRADATA20_GlitchData, + OutSignalName => "APUFCMRADATA(20)", + OutTemp => APUFCMRADATA_OUT(20), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(21), + GlitchData => APUFCMRADATA21_GlitchData, + OutSignalName => "APUFCMRADATA(21)", + OutTemp => APUFCMRADATA_OUT(21), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(22), + GlitchData => APUFCMRADATA22_GlitchData, + OutSignalName => "APUFCMRADATA(22)", + OutTemp => APUFCMRADATA_OUT(22), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(23), + GlitchData => APUFCMRADATA23_GlitchData, + OutSignalName => "APUFCMRADATA(23)", + OutTemp => APUFCMRADATA_OUT(23), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(24), + GlitchData => APUFCMRADATA24_GlitchData, + OutSignalName => "APUFCMRADATA(24)", + OutTemp => APUFCMRADATA_OUT(24), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(25), + GlitchData => APUFCMRADATA25_GlitchData, + OutSignalName => "APUFCMRADATA(25)", + OutTemp => APUFCMRADATA_OUT(25), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(26), + GlitchData => APUFCMRADATA26_GlitchData, + OutSignalName => "APUFCMRADATA(26)", + OutTemp => APUFCMRADATA_OUT(26), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(27), + GlitchData => APUFCMRADATA27_GlitchData, + OutSignalName => "APUFCMRADATA(27)", + OutTemp => APUFCMRADATA_OUT(27), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(28), + GlitchData => APUFCMRADATA28_GlitchData, + OutSignalName => "APUFCMRADATA(28)", + OutTemp => APUFCMRADATA_OUT(28), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(29), + GlitchData => APUFCMRADATA29_GlitchData, + OutSignalName => "APUFCMRADATA(29)", + OutTemp => APUFCMRADATA_OUT(29), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(30), + GlitchData => APUFCMRADATA30_GlitchData, + OutSignalName => "APUFCMRADATA(30)", + OutTemp => APUFCMRADATA_OUT(30), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRADATA(31), + GlitchData => APUFCMRADATA31_GlitchData, + OutSignalName => "APUFCMRADATA(31)", + OutTemp => APUFCMRADATA_OUT(31), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(0), + GlitchData => APUFCMRBDATA0_GlitchData, + OutSignalName => "APUFCMRBDATA(0)", + OutTemp => APUFCMRBDATA_OUT(0), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(1), + GlitchData => APUFCMRBDATA1_GlitchData, + OutSignalName => "APUFCMRBDATA(1)", + OutTemp => APUFCMRBDATA_OUT(1), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(2), + GlitchData => APUFCMRBDATA2_GlitchData, + OutSignalName => "APUFCMRBDATA(2)", + OutTemp => APUFCMRBDATA_OUT(2), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(3), + GlitchData => APUFCMRBDATA3_GlitchData, + OutSignalName => "APUFCMRBDATA(3)", + OutTemp => APUFCMRBDATA_OUT(3), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(4), + GlitchData => APUFCMRBDATA4_GlitchData, + OutSignalName => "APUFCMRBDATA(4)", + OutTemp => APUFCMRBDATA_OUT(4), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(5), + GlitchData => APUFCMRBDATA5_GlitchData, + OutSignalName => "APUFCMRBDATA(5)", + OutTemp => APUFCMRBDATA_OUT(5), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(6), + GlitchData => APUFCMRBDATA6_GlitchData, + OutSignalName => "APUFCMRBDATA(6)", + OutTemp => APUFCMRBDATA_OUT(6), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(7), + GlitchData => APUFCMRBDATA7_GlitchData, + OutSignalName => "APUFCMRBDATA(7)", + OutTemp => APUFCMRBDATA_OUT(7), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(8), + GlitchData => APUFCMRBDATA8_GlitchData, + OutSignalName => "APUFCMRBDATA(8)", + OutTemp => APUFCMRBDATA_OUT(8), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(9), + GlitchData => APUFCMRBDATA9_GlitchData, + OutSignalName => "APUFCMRBDATA(9)", + OutTemp => APUFCMRBDATA_OUT(9), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(10), + GlitchData => APUFCMRBDATA10_GlitchData, + OutSignalName => "APUFCMRBDATA(10)", + OutTemp => APUFCMRBDATA_OUT(10), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(11), + GlitchData => APUFCMRBDATA11_GlitchData, + OutSignalName => "APUFCMRBDATA(11)", + OutTemp => APUFCMRBDATA_OUT(11), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(12), + GlitchData => APUFCMRBDATA12_GlitchData, + OutSignalName => "APUFCMRBDATA(12)", + OutTemp => APUFCMRBDATA_OUT(12), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(13), + GlitchData => APUFCMRBDATA13_GlitchData, + OutSignalName => "APUFCMRBDATA(13)", + OutTemp => APUFCMRBDATA_OUT(13), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(14), + GlitchData => APUFCMRBDATA14_GlitchData, + OutSignalName => "APUFCMRBDATA(14)", + OutTemp => APUFCMRBDATA_OUT(14), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(15), + GlitchData => APUFCMRBDATA15_GlitchData, + OutSignalName => "APUFCMRBDATA(15)", + OutTemp => APUFCMRBDATA_OUT(15), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(16), + GlitchData => APUFCMRBDATA16_GlitchData, + OutSignalName => "APUFCMRBDATA(16)", + OutTemp => APUFCMRBDATA_OUT(16), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(17), + GlitchData => APUFCMRBDATA17_GlitchData, + OutSignalName => "APUFCMRBDATA(17)", + OutTemp => APUFCMRBDATA_OUT(17), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(18), + GlitchData => APUFCMRBDATA18_GlitchData, + OutSignalName => "APUFCMRBDATA(18)", + OutTemp => APUFCMRBDATA_OUT(18), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(19), + GlitchData => APUFCMRBDATA19_GlitchData, + OutSignalName => "APUFCMRBDATA(19)", + OutTemp => APUFCMRBDATA_OUT(19), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(20), + GlitchData => APUFCMRBDATA20_GlitchData, + OutSignalName => "APUFCMRBDATA(20)", + OutTemp => APUFCMRBDATA_OUT(20), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(21), + GlitchData => APUFCMRBDATA21_GlitchData, + OutSignalName => "APUFCMRBDATA(21)", + OutTemp => APUFCMRBDATA_OUT(21), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(22), + GlitchData => APUFCMRBDATA22_GlitchData, + OutSignalName => "APUFCMRBDATA(22)", + OutTemp => APUFCMRBDATA_OUT(22), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(23), + GlitchData => APUFCMRBDATA23_GlitchData, + OutSignalName => "APUFCMRBDATA(23)", + OutTemp => APUFCMRBDATA_OUT(23), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(24), + GlitchData => APUFCMRBDATA24_GlitchData, + OutSignalName => "APUFCMRBDATA(24)", + OutTemp => APUFCMRBDATA_OUT(24), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(25), + GlitchData => APUFCMRBDATA25_GlitchData, + OutSignalName => "APUFCMRBDATA(25)", + OutTemp => APUFCMRBDATA_OUT(25), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(26), + GlitchData => APUFCMRBDATA26_GlitchData, + OutSignalName => "APUFCMRBDATA(26)", + OutTemp => APUFCMRBDATA_OUT(26), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(27), + GlitchData => APUFCMRBDATA27_GlitchData, + OutSignalName => "APUFCMRBDATA(27)", + OutTemp => APUFCMRBDATA_OUT(27), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(28), + GlitchData => APUFCMRBDATA28_GlitchData, + OutSignalName => "APUFCMRBDATA(28)", + OutTemp => APUFCMRBDATA_OUT(28), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(29), + GlitchData => APUFCMRBDATA29_GlitchData, + OutSignalName => "APUFCMRBDATA(29)", + OutTemp => APUFCMRBDATA_OUT(29), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(30), + GlitchData => APUFCMRBDATA30_GlitchData, + OutSignalName => "APUFCMRBDATA(30)", + OutTemp => APUFCMRBDATA_OUT(30), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMRBDATA(31), + GlitchData => APUFCMRBDATA31_GlitchData, + OutSignalName => "APUFCMRBDATA(31)", + OutTemp => APUFCMRBDATA_OUT(31), + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => APUFCMWRITEBACKOK, + GlitchData => APUFCMWRITEBACKOK_GlitchData, + OutSignalName => "APUFCMWRITEBACKOK", + OutTemp => APUFCMWRITEBACKOK_OUT, + Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440CPMCORESLEEPREQ, + GlitchData => C440CPMCORESLEEPREQ_GlitchData, + OutSignalName => "C440CPMCORESLEEPREQ", + OutTemp => C440CPMCORESLEEPREQ_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440CPMDECIRPTREQ, + GlitchData => C440CPMDECIRPTREQ_GlitchData, + OutSignalName => "C440CPMDECIRPTREQ", + OutTemp => C440CPMDECIRPTREQ_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440CPMFITIRPTREQ, + GlitchData => C440CPMFITIRPTREQ_GlitchData, + OutSignalName => "C440CPMFITIRPTREQ", + OutTemp => C440CPMFITIRPTREQ_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440CPMMSRCE, + GlitchData => C440CPMMSRCE_GlitchData, + OutSignalName => "C440CPMMSRCE", + OutTemp => C440CPMMSRCE_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440CPMMSREE, + GlitchData => C440CPMMSREE_GlitchData, + OutSignalName => "C440CPMMSREE", + OutTemp => C440CPMMSREE_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440CPMTIMERRESETREQ, + GlitchData => C440CPMTIMERRESETREQ_GlitchData, + OutSignalName => "C440CPMTIMERRESETREQ", + OutTemp => C440CPMTIMERRESETREQ_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440CPMWDIRPTREQ, + GlitchData => C440CPMWDIRPTREQ_GlitchData, + OutSignalName => "C440CPMWDIRPTREQ", + OutTemp => C440CPMWDIRPTREQ_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440DBGSYSTEMCONTROL(0), + GlitchData => C440DBGSYSTEMCONTROL0_GlitchData, + OutSignalName => "C440DBGSYSTEMCONTROL(0)", + OutTemp => C440DBGSYSTEMCONTROL_OUT(0), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440DBGSYSTEMCONTROL(1), + GlitchData => C440DBGSYSTEMCONTROL1_GlitchData, + OutSignalName => "C440DBGSYSTEMCONTROL(1)", + OutTemp => C440DBGSYSTEMCONTROL_OUT(1), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440DBGSYSTEMCONTROL(2), + GlitchData => C440DBGSYSTEMCONTROL2_GlitchData, + OutSignalName => "C440DBGSYSTEMCONTROL(2)", + OutTemp => C440DBGSYSTEMCONTROL_OUT(2), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440DBGSYSTEMCONTROL(3), + GlitchData => C440DBGSYSTEMCONTROL3_GlitchData, + OutSignalName => "C440DBGSYSTEMCONTROL(3)", + OutTemp => C440DBGSYSTEMCONTROL_OUT(3), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440DBGSYSTEMCONTROL(4), + GlitchData => C440DBGSYSTEMCONTROL4_GlitchData, + OutSignalName => "C440DBGSYSTEMCONTROL(4)", + OutTemp => C440DBGSYSTEMCONTROL_OUT(4), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440DBGSYSTEMCONTROL(5), + GlitchData => C440DBGSYSTEMCONTROL5_GlitchData, + OutSignalName => "C440DBGSYSTEMCONTROL(5)", + OutTemp => C440DBGSYSTEMCONTROL_OUT(5), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440DBGSYSTEMCONTROL(6), + GlitchData => C440DBGSYSTEMCONTROL6_GlitchData, + OutSignalName => "C440DBGSYSTEMCONTROL(6)", + OutTemp => C440DBGSYSTEMCONTROL_OUT(6), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440DBGSYSTEMCONTROL(7), + GlitchData => C440DBGSYSTEMCONTROL7_GlitchData, + OutSignalName => "C440DBGSYSTEMCONTROL(7)", + OutTemp => C440DBGSYSTEMCONTROL_OUT(7), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440JTGTDO, + GlitchData => C440JTGTDO_GlitchData, + OutSignalName => "C440JTGTDO", + OutTemp => C440JTGTDO_OUT, + Paths => (0 => (JTGC440TCK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440JTGTDOEN, + GlitchData => C440JTGTDOEN_GlitchData, + OutSignalName => "C440JTGTDOEN", + OutTemp => C440JTGTDOEN_OUT, + Paths => (0 => (JTGC440TCK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440MACHINECHECK, + GlitchData => C440MACHINECHECK_GlitchData, + OutSignalName => "C440MACHINECHECK", + OutTemp => C440MACHINECHECK_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440RSTCHIPRESETREQ, + GlitchData => C440RSTCHIPRESETREQ_GlitchData, + OutSignalName => "C440RSTCHIPRESETREQ", + OutTemp => C440RSTCHIPRESETREQ_OUT, + Paths => (0 => (CPMINTERCONNECTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440RSTCORERESETREQ, + GlitchData => C440RSTCORERESETREQ_GlitchData, + OutSignalName => "C440RSTCORERESETREQ", + OutTemp => C440RSTCORERESETREQ_OUT, + Paths => (0 => (CPMINTERCONNECTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440RSTSYSTEMRESETREQ, + GlitchData => C440RSTSYSTEMRESETREQ_GlitchData, + OutSignalName => "C440RSTSYSTEMRESETREQ", + OutTemp => C440RSTSYSTEMRESETREQ_OUT, + Paths => (0 => (CPMINTERCONNECTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCBRANCHSTATUS(0), + GlitchData => C440TRCBRANCHSTATUS0_GlitchData, + OutSignalName => "C440TRCBRANCHSTATUS(0)", + OutTemp => C440TRCBRANCHSTATUS_OUT(0), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCBRANCHSTATUS(1), + GlitchData => C440TRCBRANCHSTATUS1_GlitchData, + OutSignalName => "C440TRCBRANCHSTATUS(1)", + OutTemp => C440TRCBRANCHSTATUS_OUT(1), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCBRANCHSTATUS(2), + GlitchData => C440TRCBRANCHSTATUS2_GlitchData, + OutSignalName => "C440TRCBRANCHSTATUS(2)", + OutTemp => C440TRCBRANCHSTATUS_OUT(2), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCCYCLE, + GlitchData => C440TRCCYCLE_GlitchData, + OutSignalName => "C440TRCCYCLE", + OutTemp => C440TRCCYCLE_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCEXECUTIONSTATUS(0), + GlitchData => C440TRCEXECUTIONSTATUS0_GlitchData, + OutSignalName => "C440TRCEXECUTIONSTATUS(0)", + OutTemp => C440TRCEXECUTIONSTATUS_OUT(0), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCEXECUTIONSTATUS(1), + GlitchData => C440TRCEXECUTIONSTATUS1_GlitchData, + OutSignalName => "C440TRCEXECUTIONSTATUS(1)", + OutTemp => C440TRCEXECUTIONSTATUS_OUT(1), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCEXECUTIONSTATUS(2), + GlitchData => C440TRCEXECUTIONSTATUS2_GlitchData, + OutSignalName => "C440TRCEXECUTIONSTATUS(2)", + OutTemp => C440TRCEXECUTIONSTATUS_OUT(2), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCEXECUTIONSTATUS(3), + GlitchData => C440TRCEXECUTIONSTATUS3_GlitchData, + OutSignalName => "C440TRCEXECUTIONSTATUS(3)", + OutTemp => C440TRCEXECUTIONSTATUS_OUT(3), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCEXECUTIONSTATUS(4), + GlitchData => C440TRCEXECUTIONSTATUS4_GlitchData, + OutSignalName => "C440TRCEXECUTIONSTATUS(4)", + OutTemp => C440TRCEXECUTIONSTATUS_OUT(4), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRACESTATUS(0), + GlitchData => C440TRCTRACESTATUS0_GlitchData, + OutSignalName => "C440TRCTRACESTATUS(0)", + OutTemp => C440TRCTRACESTATUS_OUT(0), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRACESTATUS(1), + GlitchData => C440TRCTRACESTATUS1_GlitchData, + OutSignalName => "C440TRCTRACESTATUS(1)", + OutTemp => C440TRCTRACESTATUS_OUT(1), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRACESTATUS(2), + GlitchData => C440TRCTRACESTATUS2_GlitchData, + OutSignalName => "C440TRCTRACESTATUS(2)", + OutTemp => C440TRCTRACESTATUS_OUT(2), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRACESTATUS(3), + GlitchData => C440TRCTRACESTATUS3_GlitchData, + OutSignalName => "C440TRCTRACESTATUS(3)", + OutTemp => C440TRCTRACESTATUS_OUT(3), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRACESTATUS(4), + GlitchData => C440TRCTRACESTATUS4_GlitchData, + OutSignalName => "C440TRCTRACESTATUS(4)", + OutTemp => C440TRCTRACESTATUS_OUT(4), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRACESTATUS(5), + GlitchData => C440TRCTRACESTATUS5_GlitchData, + OutSignalName => "C440TRCTRACESTATUS(5)", + OutTemp => C440TRCTRACESTATUS_OUT(5), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRACESTATUS(6), + GlitchData => C440TRCTRACESTATUS6_GlitchData, + OutSignalName => "C440TRCTRACESTATUS(6)", + OutTemp => C440TRCTRACESTATUS_OUT(6), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTOUT, + GlitchData => C440TRCTRIGGEREVENTOUT_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTOUT", + OutTemp => C440TRCTRIGGEREVENTOUT_OUT, + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(0), + GlitchData => C440TRCTRIGGEREVENTTYPE0_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(0)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(0), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(1), + GlitchData => C440TRCTRIGGEREVENTTYPE1_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(1)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(1), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(2), + GlitchData => C440TRCTRIGGEREVENTTYPE2_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(2)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(2), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(3), + GlitchData => C440TRCTRIGGEREVENTTYPE3_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(3)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(3), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(4), + GlitchData => C440TRCTRIGGEREVENTTYPE4_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(4)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(4), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(5), + GlitchData => C440TRCTRIGGEREVENTTYPE5_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(5)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(5), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(6), + GlitchData => C440TRCTRIGGEREVENTTYPE6_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(6)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(6), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(7), + GlitchData => C440TRCTRIGGEREVENTTYPE7_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(7)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(7), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(8), + GlitchData => C440TRCTRIGGEREVENTTYPE8_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(8)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(8), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(9), + GlitchData => C440TRCTRIGGEREVENTTYPE9_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(9)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(9), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(10), + GlitchData => C440TRCTRIGGEREVENTTYPE10_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(10)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(10), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(11), + GlitchData => C440TRCTRIGGEREVENTTYPE11_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(11)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(11), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(12), + GlitchData => C440TRCTRIGGEREVENTTYPE12_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(12)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(12), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => C440TRCTRIGGEREVENTTYPE(13), + GlitchData => C440TRCTRIGGEREVENTTYPE13_GlitchData, + OutSignalName => "C440TRCTRIGGEREVENTTYPE(13)", + OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(13), + Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(0), + GlitchData => MIMCADDRESS0_GlitchData, + OutSignalName => "MIMCADDRESS(0)", + OutTemp => MIMCADDRESS_OUT(0), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(1), + GlitchData => MIMCADDRESS1_GlitchData, + OutSignalName => "MIMCADDRESS(1)", + OutTemp => MIMCADDRESS_OUT(1), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(2), + GlitchData => MIMCADDRESS2_GlitchData, + OutSignalName => "MIMCADDRESS(2)", + OutTemp => MIMCADDRESS_OUT(2), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(3), + GlitchData => MIMCADDRESS3_GlitchData, + OutSignalName => "MIMCADDRESS(3)", + OutTemp => MIMCADDRESS_OUT(3), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(4), + GlitchData => MIMCADDRESS4_GlitchData, + OutSignalName => "MIMCADDRESS(4)", + OutTemp => MIMCADDRESS_OUT(4), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(5), + GlitchData => MIMCADDRESS5_GlitchData, + OutSignalName => "MIMCADDRESS(5)", + OutTemp => MIMCADDRESS_OUT(5), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(6), + GlitchData => MIMCADDRESS6_GlitchData, + OutSignalName => "MIMCADDRESS(6)", + OutTemp => MIMCADDRESS_OUT(6), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(7), + GlitchData => MIMCADDRESS7_GlitchData, + OutSignalName => "MIMCADDRESS(7)", + OutTemp => MIMCADDRESS_OUT(7), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(8), + GlitchData => MIMCADDRESS8_GlitchData, + OutSignalName => "MIMCADDRESS(8)", + OutTemp => MIMCADDRESS_OUT(8), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(9), + GlitchData => MIMCADDRESS9_GlitchData, + OutSignalName => "MIMCADDRESS(9)", + OutTemp => MIMCADDRESS_OUT(9), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(10), + GlitchData => MIMCADDRESS10_GlitchData, + OutSignalName => "MIMCADDRESS(10)", + OutTemp => MIMCADDRESS_OUT(10), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(11), + GlitchData => MIMCADDRESS11_GlitchData, + OutSignalName => "MIMCADDRESS(11)", + OutTemp => MIMCADDRESS_OUT(11), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(12), + GlitchData => MIMCADDRESS12_GlitchData, + OutSignalName => "MIMCADDRESS(12)", + OutTemp => MIMCADDRESS_OUT(12), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(13), + GlitchData => MIMCADDRESS13_GlitchData, + OutSignalName => "MIMCADDRESS(13)", + OutTemp => MIMCADDRESS_OUT(13), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(14), + GlitchData => MIMCADDRESS14_GlitchData, + OutSignalName => "MIMCADDRESS(14)", + OutTemp => MIMCADDRESS_OUT(14), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(15), + GlitchData => MIMCADDRESS15_GlitchData, + OutSignalName => "MIMCADDRESS(15)", + OutTemp => MIMCADDRESS_OUT(15), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(16), + GlitchData => MIMCADDRESS16_GlitchData, + OutSignalName => "MIMCADDRESS(16)", + OutTemp => MIMCADDRESS_OUT(16), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(17), + GlitchData => MIMCADDRESS17_GlitchData, + OutSignalName => "MIMCADDRESS(17)", + OutTemp => MIMCADDRESS_OUT(17), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(18), + GlitchData => MIMCADDRESS18_GlitchData, + OutSignalName => "MIMCADDRESS(18)", + OutTemp => MIMCADDRESS_OUT(18), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(19), + GlitchData => MIMCADDRESS19_GlitchData, + OutSignalName => "MIMCADDRESS(19)", + OutTemp => MIMCADDRESS_OUT(19), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(20), + GlitchData => MIMCADDRESS20_GlitchData, + OutSignalName => "MIMCADDRESS(20)", + OutTemp => MIMCADDRESS_OUT(20), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(21), + GlitchData => MIMCADDRESS21_GlitchData, + OutSignalName => "MIMCADDRESS(21)", + OutTemp => MIMCADDRESS_OUT(21), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(22), + GlitchData => MIMCADDRESS22_GlitchData, + OutSignalName => "MIMCADDRESS(22)", + OutTemp => MIMCADDRESS_OUT(22), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(23), + GlitchData => MIMCADDRESS23_GlitchData, + OutSignalName => "MIMCADDRESS(23)", + OutTemp => MIMCADDRESS_OUT(23), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(24), + GlitchData => MIMCADDRESS24_GlitchData, + OutSignalName => "MIMCADDRESS(24)", + OutTemp => MIMCADDRESS_OUT(24), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(25), + GlitchData => MIMCADDRESS25_GlitchData, + OutSignalName => "MIMCADDRESS(25)", + OutTemp => MIMCADDRESS_OUT(25), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(26), + GlitchData => MIMCADDRESS26_GlitchData, + OutSignalName => "MIMCADDRESS(26)", + OutTemp => MIMCADDRESS_OUT(26), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(27), + GlitchData => MIMCADDRESS27_GlitchData, + OutSignalName => "MIMCADDRESS(27)", + OutTemp => MIMCADDRESS_OUT(27), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(28), + GlitchData => MIMCADDRESS28_GlitchData, + OutSignalName => "MIMCADDRESS(28)", + OutTemp => MIMCADDRESS_OUT(28), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(29), + GlitchData => MIMCADDRESS29_GlitchData, + OutSignalName => "MIMCADDRESS(29)", + OutTemp => MIMCADDRESS_OUT(29), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(30), + GlitchData => MIMCADDRESS30_GlitchData, + OutSignalName => "MIMCADDRESS(30)", + OutTemp => MIMCADDRESS_OUT(30), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(31), + GlitchData => MIMCADDRESS31_GlitchData, + OutSignalName => "MIMCADDRESS(31)", + OutTemp => MIMCADDRESS_OUT(31), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(32), + GlitchData => MIMCADDRESS32_GlitchData, + OutSignalName => "MIMCADDRESS(32)", + OutTemp => MIMCADDRESS_OUT(32), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(33), + GlitchData => MIMCADDRESS33_GlitchData, + OutSignalName => "MIMCADDRESS(33)", + OutTemp => MIMCADDRESS_OUT(33), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(34), + GlitchData => MIMCADDRESS34_GlitchData, + OutSignalName => "MIMCADDRESS(34)", + OutTemp => MIMCADDRESS_OUT(34), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESS(35), + GlitchData => MIMCADDRESS35_GlitchData, + OutSignalName => "MIMCADDRESS(35)", + OutTemp => MIMCADDRESS_OUT(35), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCADDRESSVALID, + GlitchData => MIMCADDRESSVALID_GlitchData, + OutSignalName => "MIMCADDRESSVALID", + OutTemp => MIMCADDRESSVALID_OUT, + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBANKCONFLICT, + GlitchData => MIMCBANKCONFLICT_GlitchData, + OutSignalName => "MIMCBANKCONFLICT", + OutTemp => MIMCBANKCONFLICT_OUT, + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(0), + GlitchData => MIMCBYTEENABLE0_GlitchData, + OutSignalName => "MIMCBYTEENABLE(0)", + OutTemp => MIMCBYTEENABLE_OUT(0), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(1), + GlitchData => MIMCBYTEENABLE1_GlitchData, + OutSignalName => "MIMCBYTEENABLE(1)", + OutTemp => MIMCBYTEENABLE_OUT(1), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(2), + GlitchData => MIMCBYTEENABLE2_GlitchData, + OutSignalName => "MIMCBYTEENABLE(2)", + OutTemp => MIMCBYTEENABLE_OUT(2), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(3), + GlitchData => MIMCBYTEENABLE3_GlitchData, + OutSignalName => "MIMCBYTEENABLE(3)", + OutTemp => MIMCBYTEENABLE_OUT(3), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(4), + GlitchData => MIMCBYTEENABLE4_GlitchData, + OutSignalName => "MIMCBYTEENABLE(4)", + OutTemp => MIMCBYTEENABLE_OUT(4), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(5), + GlitchData => MIMCBYTEENABLE5_GlitchData, + OutSignalName => "MIMCBYTEENABLE(5)", + OutTemp => MIMCBYTEENABLE_OUT(5), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(6), + GlitchData => MIMCBYTEENABLE6_GlitchData, + OutSignalName => "MIMCBYTEENABLE(6)", + OutTemp => MIMCBYTEENABLE_OUT(6), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(7), + GlitchData => MIMCBYTEENABLE7_GlitchData, + OutSignalName => "MIMCBYTEENABLE(7)", + OutTemp => MIMCBYTEENABLE_OUT(7), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(8), + GlitchData => MIMCBYTEENABLE8_GlitchData, + OutSignalName => "MIMCBYTEENABLE(8)", + OutTemp => MIMCBYTEENABLE_OUT(8), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(9), + GlitchData => MIMCBYTEENABLE9_GlitchData, + OutSignalName => "MIMCBYTEENABLE(9)", + OutTemp => MIMCBYTEENABLE_OUT(9), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(10), + GlitchData => MIMCBYTEENABLE10_GlitchData, + OutSignalName => "MIMCBYTEENABLE(10)", + OutTemp => MIMCBYTEENABLE_OUT(10), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(11), + GlitchData => MIMCBYTEENABLE11_GlitchData, + OutSignalName => "MIMCBYTEENABLE(11)", + OutTemp => MIMCBYTEENABLE_OUT(11), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(12), + GlitchData => MIMCBYTEENABLE12_GlitchData, + OutSignalName => "MIMCBYTEENABLE(12)", + OutTemp => MIMCBYTEENABLE_OUT(12), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(13), + GlitchData => MIMCBYTEENABLE13_GlitchData, + OutSignalName => "MIMCBYTEENABLE(13)", + OutTemp => MIMCBYTEENABLE_OUT(13), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(14), + GlitchData => MIMCBYTEENABLE14_GlitchData, + OutSignalName => "MIMCBYTEENABLE(14)", + OutTemp => MIMCBYTEENABLE_OUT(14), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCBYTEENABLE(15), + GlitchData => MIMCBYTEENABLE15_GlitchData, + OutSignalName => "MIMCBYTEENABLE(15)", + OutTemp => MIMCBYTEENABLE_OUT(15), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCREADNOTWRITE, + GlitchData => MIMCREADNOTWRITE_GlitchData, + OutSignalName => "MIMCREADNOTWRITE", + OutTemp => MIMCREADNOTWRITE_OUT, + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCROWCONFLICT, + GlitchData => MIMCROWCONFLICT_GlitchData, + OutSignalName => "MIMCROWCONFLICT", + OutTemp => MIMCROWCONFLICT_OUT, + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(0), + GlitchData => MIMCWRITEDATA0_GlitchData, + OutSignalName => "MIMCWRITEDATA(0)", + OutTemp => MIMCWRITEDATA_OUT(0), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(1), + GlitchData => MIMCWRITEDATA1_GlitchData, + OutSignalName => "MIMCWRITEDATA(1)", + OutTemp => MIMCWRITEDATA_OUT(1), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(2), + GlitchData => MIMCWRITEDATA2_GlitchData, + OutSignalName => "MIMCWRITEDATA(2)", + OutTemp => MIMCWRITEDATA_OUT(2), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(3), + GlitchData => MIMCWRITEDATA3_GlitchData, + OutSignalName => "MIMCWRITEDATA(3)", + OutTemp => MIMCWRITEDATA_OUT(3), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(4), + GlitchData => MIMCWRITEDATA4_GlitchData, + OutSignalName => "MIMCWRITEDATA(4)", + OutTemp => MIMCWRITEDATA_OUT(4), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(5), + GlitchData => MIMCWRITEDATA5_GlitchData, + OutSignalName => "MIMCWRITEDATA(5)", + OutTemp => MIMCWRITEDATA_OUT(5), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(6), + GlitchData => MIMCWRITEDATA6_GlitchData, + OutSignalName => "MIMCWRITEDATA(6)", + OutTemp => MIMCWRITEDATA_OUT(6), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(7), + GlitchData => MIMCWRITEDATA7_GlitchData, + OutSignalName => "MIMCWRITEDATA(7)", + OutTemp => MIMCWRITEDATA_OUT(7), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(8), + GlitchData => MIMCWRITEDATA8_GlitchData, + OutSignalName => "MIMCWRITEDATA(8)", + OutTemp => MIMCWRITEDATA_OUT(8), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(9), + GlitchData => MIMCWRITEDATA9_GlitchData, + OutSignalName => "MIMCWRITEDATA(9)", + OutTemp => MIMCWRITEDATA_OUT(9), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(10), + GlitchData => MIMCWRITEDATA10_GlitchData, + OutSignalName => "MIMCWRITEDATA(10)", + OutTemp => MIMCWRITEDATA_OUT(10), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(11), + GlitchData => MIMCWRITEDATA11_GlitchData, + OutSignalName => "MIMCWRITEDATA(11)", + OutTemp => MIMCWRITEDATA_OUT(11), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(12), + GlitchData => MIMCWRITEDATA12_GlitchData, + OutSignalName => "MIMCWRITEDATA(12)", + OutTemp => MIMCWRITEDATA_OUT(12), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(13), + GlitchData => MIMCWRITEDATA13_GlitchData, + OutSignalName => "MIMCWRITEDATA(13)", + OutTemp => MIMCWRITEDATA_OUT(13), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(14), + GlitchData => MIMCWRITEDATA14_GlitchData, + OutSignalName => "MIMCWRITEDATA(14)", + OutTemp => MIMCWRITEDATA_OUT(14), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(15), + GlitchData => MIMCWRITEDATA15_GlitchData, + OutSignalName => "MIMCWRITEDATA(15)", + OutTemp => MIMCWRITEDATA_OUT(15), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(16), + GlitchData => MIMCWRITEDATA16_GlitchData, + OutSignalName => "MIMCWRITEDATA(16)", + OutTemp => MIMCWRITEDATA_OUT(16), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(17), + GlitchData => MIMCWRITEDATA17_GlitchData, + OutSignalName => "MIMCWRITEDATA(17)", + OutTemp => MIMCWRITEDATA_OUT(17), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(18), + GlitchData => MIMCWRITEDATA18_GlitchData, + OutSignalName => "MIMCWRITEDATA(18)", + OutTemp => MIMCWRITEDATA_OUT(18), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(19), + GlitchData => MIMCWRITEDATA19_GlitchData, + OutSignalName => "MIMCWRITEDATA(19)", + OutTemp => MIMCWRITEDATA_OUT(19), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(20), + GlitchData => MIMCWRITEDATA20_GlitchData, + OutSignalName => "MIMCWRITEDATA(20)", + OutTemp => MIMCWRITEDATA_OUT(20), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(21), + GlitchData => MIMCWRITEDATA21_GlitchData, + OutSignalName => "MIMCWRITEDATA(21)", + OutTemp => MIMCWRITEDATA_OUT(21), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(22), + GlitchData => MIMCWRITEDATA22_GlitchData, + OutSignalName => "MIMCWRITEDATA(22)", + OutTemp => MIMCWRITEDATA_OUT(22), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(23), + GlitchData => MIMCWRITEDATA23_GlitchData, + OutSignalName => "MIMCWRITEDATA(23)", + OutTemp => MIMCWRITEDATA_OUT(23), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(24), + GlitchData => MIMCWRITEDATA24_GlitchData, + OutSignalName => "MIMCWRITEDATA(24)", + OutTemp => MIMCWRITEDATA_OUT(24), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(25), + GlitchData => MIMCWRITEDATA25_GlitchData, + OutSignalName => "MIMCWRITEDATA(25)", + OutTemp => MIMCWRITEDATA_OUT(25), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(26), + GlitchData => MIMCWRITEDATA26_GlitchData, + OutSignalName => "MIMCWRITEDATA(26)", + OutTemp => MIMCWRITEDATA_OUT(26), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(27), + GlitchData => MIMCWRITEDATA27_GlitchData, + OutSignalName => "MIMCWRITEDATA(27)", + OutTemp => MIMCWRITEDATA_OUT(27), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(28), + GlitchData => MIMCWRITEDATA28_GlitchData, + OutSignalName => "MIMCWRITEDATA(28)", + OutTemp => MIMCWRITEDATA_OUT(28), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(29), + GlitchData => MIMCWRITEDATA29_GlitchData, + OutSignalName => "MIMCWRITEDATA(29)", + OutTemp => MIMCWRITEDATA_OUT(29), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(30), + GlitchData => MIMCWRITEDATA30_GlitchData, + OutSignalName => "MIMCWRITEDATA(30)", + OutTemp => MIMCWRITEDATA_OUT(30), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(31), + GlitchData => MIMCWRITEDATA31_GlitchData, + OutSignalName => "MIMCWRITEDATA(31)", + OutTemp => MIMCWRITEDATA_OUT(31), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(32), + GlitchData => MIMCWRITEDATA32_GlitchData, + OutSignalName => "MIMCWRITEDATA(32)", + OutTemp => MIMCWRITEDATA_OUT(32), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(33), + GlitchData => MIMCWRITEDATA33_GlitchData, + OutSignalName => "MIMCWRITEDATA(33)", + OutTemp => MIMCWRITEDATA_OUT(33), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(34), + GlitchData => MIMCWRITEDATA34_GlitchData, + OutSignalName => "MIMCWRITEDATA(34)", + OutTemp => MIMCWRITEDATA_OUT(34), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(35), + GlitchData => MIMCWRITEDATA35_GlitchData, + OutSignalName => "MIMCWRITEDATA(35)", + OutTemp => MIMCWRITEDATA_OUT(35), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(36), + GlitchData => MIMCWRITEDATA36_GlitchData, + OutSignalName => "MIMCWRITEDATA(36)", + OutTemp => MIMCWRITEDATA_OUT(36), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(37), + GlitchData => MIMCWRITEDATA37_GlitchData, + OutSignalName => "MIMCWRITEDATA(37)", + OutTemp => MIMCWRITEDATA_OUT(37), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(38), + GlitchData => MIMCWRITEDATA38_GlitchData, + OutSignalName => "MIMCWRITEDATA(38)", + OutTemp => MIMCWRITEDATA_OUT(38), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(39), + GlitchData => MIMCWRITEDATA39_GlitchData, + OutSignalName => "MIMCWRITEDATA(39)", + OutTemp => MIMCWRITEDATA_OUT(39), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(40), + GlitchData => MIMCWRITEDATA40_GlitchData, + OutSignalName => "MIMCWRITEDATA(40)", + OutTemp => MIMCWRITEDATA_OUT(40), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(41), + GlitchData => MIMCWRITEDATA41_GlitchData, + OutSignalName => "MIMCWRITEDATA(41)", + OutTemp => MIMCWRITEDATA_OUT(41), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(42), + GlitchData => MIMCWRITEDATA42_GlitchData, + OutSignalName => "MIMCWRITEDATA(42)", + OutTemp => MIMCWRITEDATA_OUT(42), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(43), + GlitchData => MIMCWRITEDATA43_GlitchData, + OutSignalName => "MIMCWRITEDATA(43)", + OutTemp => MIMCWRITEDATA_OUT(43), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(44), + GlitchData => MIMCWRITEDATA44_GlitchData, + OutSignalName => "MIMCWRITEDATA(44)", + OutTemp => MIMCWRITEDATA_OUT(44), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(45), + GlitchData => MIMCWRITEDATA45_GlitchData, + OutSignalName => "MIMCWRITEDATA(45)", + OutTemp => MIMCWRITEDATA_OUT(45), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(46), + GlitchData => MIMCWRITEDATA46_GlitchData, + OutSignalName => "MIMCWRITEDATA(46)", + OutTemp => MIMCWRITEDATA_OUT(46), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(47), + GlitchData => MIMCWRITEDATA47_GlitchData, + OutSignalName => "MIMCWRITEDATA(47)", + OutTemp => MIMCWRITEDATA_OUT(47), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(48), + GlitchData => MIMCWRITEDATA48_GlitchData, + OutSignalName => "MIMCWRITEDATA(48)", + OutTemp => MIMCWRITEDATA_OUT(48), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(49), + GlitchData => MIMCWRITEDATA49_GlitchData, + OutSignalName => "MIMCWRITEDATA(49)", + OutTemp => MIMCWRITEDATA_OUT(49), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(50), + GlitchData => MIMCWRITEDATA50_GlitchData, + OutSignalName => "MIMCWRITEDATA(50)", + OutTemp => MIMCWRITEDATA_OUT(50), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(51), + GlitchData => MIMCWRITEDATA51_GlitchData, + OutSignalName => "MIMCWRITEDATA(51)", + OutTemp => MIMCWRITEDATA_OUT(51), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(52), + GlitchData => MIMCWRITEDATA52_GlitchData, + OutSignalName => "MIMCWRITEDATA(52)", + OutTemp => MIMCWRITEDATA_OUT(52), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(53), + GlitchData => MIMCWRITEDATA53_GlitchData, + OutSignalName => "MIMCWRITEDATA(53)", + OutTemp => MIMCWRITEDATA_OUT(53), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(54), + GlitchData => MIMCWRITEDATA54_GlitchData, + OutSignalName => "MIMCWRITEDATA(54)", + OutTemp => MIMCWRITEDATA_OUT(54), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(55), + GlitchData => MIMCWRITEDATA55_GlitchData, + OutSignalName => "MIMCWRITEDATA(55)", + OutTemp => MIMCWRITEDATA_OUT(55), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(56), + GlitchData => MIMCWRITEDATA56_GlitchData, + OutSignalName => "MIMCWRITEDATA(56)", + OutTemp => MIMCWRITEDATA_OUT(56), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(57), + GlitchData => MIMCWRITEDATA57_GlitchData, + OutSignalName => "MIMCWRITEDATA(57)", + OutTemp => MIMCWRITEDATA_OUT(57), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(58), + GlitchData => MIMCWRITEDATA58_GlitchData, + OutSignalName => "MIMCWRITEDATA(58)", + OutTemp => MIMCWRITEDATA_OUT(58), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(59), + GlitchData => MIMCWRITEDATA59_GlitchData, + OutSignalName => "MIMCWRITEDATA(59)", + OutTemp => MIMCWRITEDATA_OUT(59), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(60), + GlitchData => MIMCWRITEDATA60_GlitchData, + OutSignalName => "MIMCWRITEDATA(60)", + OutTemp => MIMCWRITEDATA_OUT(60), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(61), + GlitchData => MIMCWRITEDATA61_GlitchData, + OutSignalName => "MIMCWRITEDATA(61)", + OutTemp => MIMCWRITEDATA_OUT(61), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(62), + GlitchData => MIMCWRITEDATA62_GlitchData, + OutSignalName => "MIMCWRITEDATA(62)", + OutTemp => MIMCWRITEDATA_OUT(62), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(63), + GlitchData => MIMCWRITEDATA63_GlitchData, + OutSignalName => "MIMCWRITEDATA(63)", + OutTemp => MIMCWRITEDATA_OUT(63), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(64), + GlitchData => MIMCWRITEDATA64_GlitchData, + OutSignalName => "MIMCWRITEDATA(64)", + OutTemp => MIMCWRITEDATA_OUT(64), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(65), + GlitchData => MIMCWRITEDATA65_GlitchData, + OutSignalName => "MIMCWRITEDATA(65)", + OutTemp => MIMCWRITEDATA_OUT(65), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(66), + GlitchData => MIMCWRITEDATA66_GlitchData, + OutSignalName => "MIMCWRITEDATA(66)", + OutTemp => MIMCWRITEDATA_OUT(66), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(67), + GlitchData => MIMCWRITEDATA67_GlitchData, + OutSignalName => "MIMCWRITEDATA(67)", + OutTemp => MIMCWRITEDATA_OUT(67), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(68), + GlitchData => MIMCWRITEDATA68_GlitchData, + OutSignalName => "MIMCWRITEDATA(68)", + OutTemp => MIMCWRITEDATA_OUT(68), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(69), + GlitchData => MIMCWRITEDATA69_GlitchData, + OutSignalName => "MIMCWRITEDATA(69)", + OutTemp => MIMCWRITEDATA_OUT(69), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(70), + GlitchData => MIMCWRITEDATA70_GlitchData, + OutSignalName => "MIMCWRITEDATA(70)", + OutTemp => MIMCWRITEDATA_OUT(70), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(71), + GlitchData => MIMCWRITEDATA71_GlitchData, + OutSignalName => "MIMCWRITEDATA(71)", + OutTemp => MIMCWRITEDATA_OUT(71), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(72), + GlitchData => MIMCWRITEDATA72_GlitchData, + OutSignalName => "MIMCWRITEDATA(72)", + OutTemp => MIMCWRITEDATA_OUT(72), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(73), + GlitchData => MIMCWRITEDATA73_GlitchData, + OutSignalName => "MIMCWRITEDATA(73)", + OutTemp => MIMCWRITEDATA_OUT(73), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(74), + GlitchData => MIMCWRITEDATA74_GlitchData, + OutSignalName => "MIMCWRITEDATA(74)", + OutTemp => MIMCWRITEDATA_OUT(74), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(75), + GlitchData => MIMCWRITEDATA75_GlitchData, + OutSignalName => "MIMCWRITEDATA(75)", + OutTemp => MIMCWRITEDATA_OUT(75), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(76), + GlitchData => MIMCWRITEDATA76_GlitchData, + OutSignalName => "MIMCWRITEDATA(76)", + OutTemp => MIMCWRITEDATA_OUT(76), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(77), + GlitchData => MIMCWRITEDATA77_GlitchData, + OutSignalName => "MIMCWRITEDATA(77)", + OutTemp => MIMCWRITEDATA_OUT(77), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(78), + GlitchData => MIMCWRITEDATA78_GlitchData, + OutSignalName => "MIMCWRITEDATA(78)", + OutTemp => MIMCWRITEDATA_OUT(78), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(79), + GlitchData => MIMCWRITEDATA79_GlitchData, + OutSignalName => "MIMCWRITEDATA(79)", + OutTemp => MIMCWRITEDATA_OUT(79), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(80), + GlitchData => MIMCWRITEDATA80_GlitchData, + OutSignalName => "MIMCWRITEDATA(80)", + OutTemp => MIMCWRITEDATA_OUT(80), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(81), + GlitchData => MIMCWRITEDATA81_GlitchData, + OutSignalName => "MIMCWRITEDATA(81)", + OutTemp => MIMCWRITEDATA_OUT(81), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(82), + GlitchData => MIMCWRITEDATA82_GlitchData, + OutSignalName => "MIMCWRITEDATA(82)", + OutTemp => MIMCWRITEDATA_OUT(82), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(83), + GlitchData => MIMCWRITEDATA83_GlitchData, + OutSignalName => "MIMCWRITEDATA(83)", + OutTemp => MIMCWRITEDATA_OUT(83), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(84), + GlitchData => MIMCWRITEDATA84_GlitchData, + OutSignalName => "MIMCWRITEDATA(84)", + OutTemp => MIMCWRITEDATA_OUT(84), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(85), + GlitchData => MIMCWRITEDATA85_GlitchData, + OutSignalName => "MIMCWRITEDATA(85)", + OutTemp => MIMCWRITEDATA_OUT(85), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(86), + GlitchData => MIMCWRITEDATA86_GlitchData, + OutSignalName => "MIMCWRITEDATA(86)", + OutTemp => MIMCWRITEDATA_OUT(86), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(87), + GlitchData => MIMCWRITEDATA87_GlitchData, + OutSignalName => "MIMCWRITEDATA(87)", + OutTemp => MIMCWRITEDATA_OUT(87), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(88), + GlitchData => MIMCWRITEDATA88_GlitchData, + OutSignalName => "MIMCWRITEDATA(88)", + OutTemp => MIMCWRITEDATA_OUT(88), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(89), + GlitchData => MIMCWRITEDATA89_GlitchData, + OutSignalName => "MIMCWRITEDATA(89)", + OutTemp => MIMCWRITEDATA_OUT(89), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(90), + GlitchData => MIMCWRITEDATA90_GlitchData, + OutSignalName => "MIMCWRITEDATA(90)", + OutTemp => MIMCWRITEDATA_OUT(90), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(91), + GlitchData => MIMCWRITEDATA91_GlitchData, + OutSignalName => "MIMCWRITEDATA(91)", + OutTemp => MIMCWRITEDATA_OUT(91), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(92), + GlitchData => MIMCWRITEDATA92_GlitchData, + OutSignalName => "MIMCWRITEDATA(92)", + OutTemp => MIMCWRITEDATA_OUT(92), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(93), + GlitchData => MIMCWRITEDATA93_GlitchData, + OutSignalName => "MIMCWRITEDATA(93)", + OutTemp => MIMCWRITEDATA_OUT(93), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(94), + GlitchData => MIMCWRITEDATA94_GlitchData, + OutSignalName => "MIMCWRITEDATA(94)", + OutTemp => MIMCWRITEDATA_OUT(94), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(95), + GlitchData => MIMCWRITEDATA95_GlitchData, + OutSignalName => "MIMCWRITEDATA(95)", + OutTemp => MIMCWRITEDATA_OUT(95), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(96), + GlitchData => MIMCWRITEDATA96_GlitchData, + OutSignalName => "MIMCWRITEDATA(96)", + OutTemp => MIMCWRITEDATA_OUT(96), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(97), + GlitchData => MIMCWRITEDATA97_GlitchData, + OutSignalName => "MIMCWRITEDATA(97)", + OutTemp => MIMCWRITEDATA_OUT(97), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(98), + GlitchData => MIMCWRITEDATA98_GlitchData, + OutSignalName => "MIMCWRITEDATA(98)", + OutTemp => MIMCWRITEDATA_OUT(98), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(99), + GlitchData => MIMCWRITEDATA99_GlitchData, + OutSignalName => "MIMCWRITEDATA(99)", + OutTemp => MIMCWRITEDATA_OUT(99), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(100), + GlitchData => MIMCWRITEDATA100_GlitchData, + OutSignalName => "MIMCWRITEDATA(100)", + OutTemp => MIMCWRITEDATA_OUT(100), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(101), + GlitchData => MIMCWRITEDATA101_GlitchData, + OutSignalName => "MIMCWRITEDATA(101)", + OutTemp => MIMCWRITEDATA_OUT(101), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(102), + GlitchData => MIMCWRITEDATA102_GlitchData, + OutSignalName => "MIMCWRITEDATA(102)", + OutTemp => MIMCWRITEDATA_OUT(102), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(103), + GlitchData => MIMCWRITEDATA103_GlitchData, + OutSignalName => "MIMCWRITEDATA(103)", + OutTemp => MIMCWRITEDATA_OUT(103), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(104), + GlitchData => MIMCWRITEDATA104_GlitchData, + OutSignalName => "MIMCWRITEDATA(104)", + OutTemp => MIMCWRITEDATA_OUT(104), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(105), + GlitchData => MIMCWRITEDATA105_GlitchData, + OutSignalName => "MIMCWRITEDATA(105)", + OutTemp => MIMCWRITEDATA_OUT(105), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(106), + GlitchData => MIMCWRITEDATA106_GlitchData, + OutSignalName => "MIMCWRITEDATA(106)", + OutTemp => MIMCWRITEDATA_OUT(106), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(107), + GlitchData => MIMCWRITEDATA107_GlitchData, + OutSignalName => "MIMCWRITEDATA(107)", + OutTemp => MIMCWRITEDATA_OUT(107), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(108), + GlitchData => MIMCWRITEDATA108_GlitchData, + OutSignalName => "MIMCWRITEDATA(108)", + OutTemp => MIMCWRITEDATA_OUT(108), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(109), + GlitchData => MIMCWRITEDATA109_GlitchData, + OutSignalName => "MIMCWRITEDATA(109)", + OutTemp => MIMCWRITEDATA_OUT(109), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(110), + GlitchData => MIMCWRITEDATA110_GlitchData, + OutSignalName => "MIMCWRITEDATA(110)", + OutTemp => MIMCWRITEDATA_OUT(110), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(111), + GlitchData => MIMCWRITEDATA111_GlitchData, + OutSignalName => "MIMCWRITEDATA(111)", + OutTemp => MIMCWRITEDATA_OUT(111), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(112), + GlitchData => MIMCWRITEDATA112_GlitchData, + OutSignalName => "MIMCWRITEDATA(112)", + OutTemp => MIMCWRITEDATA_OUT(112), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(113), + GlitchData => MIMCWRITEDATA113_GlitchData, + OutSignalName => "MIMCWRITEDATA(113)", + OutTemp => MIMCWRITEDATA_OUT(113), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(114), + GlitchData => MIMCWRITEDATA114_GlitchData, + OutSignalName => "MIMCWRITEDATA(114)", + OutTemp => MIMCWRITEDATA_OUT(114), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(115), + GlitchData => MIMCWRITEDATA115_GlitchData, + OutSignalName => "MIMCWRITEDATA(115)", + OutTemp => MIMCWRITEDATA_OUT(115), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(116), + GlitchData => MIMCWRITEDATA116_GlitchData, + OutSignalName => "MIMCWRITEDATA(116)", + OutTemp => MIMCWRITEDATA_OUT(116), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(117), + GlitchData => MIMCWRITEDATA117_GlitchData, + OutSignalName => "MIMCWRITEDATA(117)", + OutTemp => MIMCWRITEDATA_OUT(117), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(118), + GlitchData => MIMCWRITEDATA118_GlitchData, + OutSignalName => "MIMCWRITEDATA(118)", + OutTemp => MIMCWRITEDATA_OUT(118), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(119), + GlitchData => MIMCWRITEDATA119_GlitchData, + OutSignalName => "MIMCWRITEDATA(119)", + OutTemp => MIMCWRITEDATA_OUT(119), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(120), + GlitchData => MIMCWRITEDATA120_GlitchData, + OutSignalName => "MIMCWRITEDATA(120)", + OutTemp => MIMCWRITEDATA_OUT(120), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(121), + GlitchData => MIMCWRITEDATA121_GlitchData, + OutSignalName => "MIMCWRITEDATA(121)", + OutTemp => MIMCWRITEDATA_OUT(121), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(122), + GlitchData => MIMCWRITEDATA122_GlitchData, + OutSignalName => "MIMCWRITEDATA(122)", + OutTemp => MIMCWRITEDATA_OUT(122), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(123), + GlitchData => MIMCWRITEDATA123_GlitchData, + OutSignalName => "MIMCWRITEDATA(123)", + OutTemp => MIMCWRITEDATA_OUT(123), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(124), + GlitchData => MIMCWRITEDATA124_GlitchData, + OutSignalName => "MIMCWRITEDATA(124)", + OutTemp => MIMCWRITEDATA_OUT(124), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(125), + GlitchData => MIMCWRITEDATA125_GlitchData, + OutSignalName => "MIMCWRITEDATA(125)", + OutTemp => MIMCWRITEDATA_OUT(125), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(126), + GlitchData => MIMCWRITEDATA126_GlitchData, + OutSignalName => "MIMCWRITEDATA(126)", + OutTemp => MIMCWRITEDATA_OUT(126), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATA(127), + GlitchData => MIMCWRITEDATA127_GlitchData, + OutSignalName => "MIMCWRITEDATA(127)", + OutTemp => MIMCWRITEDATA_OUT(127), + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => MIMCWRITEDATAVALID, + GlitchData => MIMCWRITEDATAVALID_GlitchData, + OutSignalName => "MIMCWRITEDATAVALID", + OutTemp => MIMCWRITEDATAVALID_OUT, + Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCCPMINTERCONNECTBUSY, + GlitchData => PPCCPMINTERCONNECTBUSY_GlitchData, + OutSignalName => "PPCCPMINTERCONNECTBUSY", + OutTemp => PPCCPMINTERCONNECTBUSY_OUT, + Paths => (0 => (CPMINTERCONNECTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRACK, + GlitchData => PPCDSDCRACK_GlitchData, + OutSignalName => "PPCDSDCRACK", + OutTemp => PPCDSDCRACK_OUT, + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRTIMEOUTWAIT, + GlitchData => PPCDSDCRTIMEOUTWAIT_GlitchData, + OutSignalName => "PPCDSDCRTIMEOUTWAIT", + OutTemp => PPCDSDCRTIMEOUTWAIT_OUT, + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(0), + GlitchData => PPCDSDCRDBUSIN0_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(0)", + OutTemp => PPCDSDCRDBUSIN_OUT(0), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(1), + GlitchData => PPCDSDCRDBUSIN1_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(1)", + OutTemp => PPCDSDCRDBUSIN_OUT(1), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(2), + GlitchData => PPCDSDCRDBUSIN2_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(2)", + OutTemp => PPCDSDCRDBUSIN_OUT(2), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(3), + GlitchData => PPCDSDCRDBUSIN3_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(3)", + OutTemp => PPCDSDCRDBUSIN_OUT(3), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(4), + GlitchData => PPCDSDCRDBUSIN4_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(4)", + OutTemp => PPCDSDCRDBUSIN_OUT(4), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(5), + GlitchData => PPCDSDCRDBUSIN5_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(5)", + OutTemp => PPCDSDCRDBUSIN_OUT(5), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(6), + GlitchData => PPCDSDCRDBUSIN6_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(6)", + OutTemp => PPCDSDCRDBUSIN_OUT(6), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(7), + GlitchData => PPCDSDCRDBUSIN7_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(7)", + OutTemp => PPCDSDCRDBUSIN_OUT(7), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(8), + GlitchData => PPCDSDCRDBUSIN8_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(8)", + OutTemp => PPCDSDCRDBUSIN_OUT(8), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(9), + GlitchData => PPCDSDCRDBUSIN9_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(9)", + OutTemp => PPCDSDCRDBUSIN_OUT(9), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(10), + GlitchData => PPCDSDCRDBUSIN10_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(10)", + OutTemp => PPCDSDCRDBUSIN_OUT(10), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(11), + GlitchData => PPCDSDCRDBUSIN11_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(11)", + OutTemp => PPCDSDCRDBUSIN_OUT(11), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(12), + GlitchData => PPCDSDCRDBUSIN12_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(12)", + OutTemp => PPCDSDCRDBUSIN_OUT(12), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(13), + GlitchData => PPCDSDCRDBUSIN13_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(13)", + OutTemp => PPCDSDCRDBUSIN_OUT(13), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(14), + GlitchData => PPCDSDCRDBUSIN14_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(14)", + OutTemp => PPCDSDCRDBUSIN_OUT(14), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(15), + GlitchData => PPCDSDCRDBUSIN15_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(15)", + OutTemp => PPCDSDCRDBUSIN_OUT(15), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(16), + GlitchData => PPCDSDCRDBUSIN16_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(16)", + OutTemp => PPCDSDCRDBUSIN_OUT(16), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(17), + GlitchData => PPCDSDCRDBUSIN17_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(17)", + OutTemp => PPCDSDCRDBUSIN_OUT(17), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(18), + GlitchData => PPCDSDCRDBUSIN18_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(18)", + OutTemp => PPCDSDCRDBUSIN_OUT(18), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(19), + GlitchData => PPCDSDCRDBUSIN19_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(19)", + OutTemp => PPCDSDCRDBUSIN_OUT(19), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(20), + GlitchData => PPCDSDCRDBUSIN20_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(20)", + OutTemp => PPCDSDCRDBUSIN_OUT(20), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(21), + GlitchData => PPCDSDCRDBUSIN21_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(21)", + OutTemp => PPCDSDCRDBUSIN_OUT(21), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(22), + GlitchData => PPCDSDCRDBUSIN22_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(22)", + OutTemp => PPCDSDCRDBUSIN_OUT(22), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(23), + GlitchData => PPCDSDCRDBUSIN23_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(23)", + OutTemp => PPCDSDCRDBUSIN_OUT(23), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(24), + GlitchData => PPCDSDCRDBUSIN24_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(24)", + OutTemp => PPCDSDCRDBUSIN_OUT(24), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(25), + GlitchData => PPCDSDCRDBUSIN25_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(25)", + OutTemp => PPCDSDCRDBUSIN_OUT(25), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(26), + GlitchData => PPCDSDCRDBUSIN26_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(26)", + OutTemp => PPCDSDCRDBUSIN_OUT(26), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(27), + GlitchData => PPCDSDCRDBUSIN27_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(27)", + OutTemp => PPCDSDCRDBUSIN_OUT(27), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(28), + GlitchData => PPCDSDCRDBUSIN28_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(28)", + OutTemp => PPCDSDCRDBUSIN_OUT(28), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(29), + GlitchData => PPCDSDCRDBUSIN29_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(29)", + OutTemp => PPCDSDCRDBUSIN_OUT(29), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(30), + GlitchData => PPCDSDCRDBUSIN30_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(30)", + OutTemp => PPCDSDCRDBUSIN_OUT(30), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCDSDCRDBUSIN(31), + GlitchData => PPCDSDCRDBUSIN31_GlitchData, + OutSignalName => "PPCDSDCRDBUSIN(31)", + OutTemp => PPCDSDCRDBUSIN_OUT(31), + Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + VitalPathDelay01 + ( + OutSignal => PPCEICINTERCONNECTIRQ, + GlitchData => PPCEICINTERCONNECTIRQ_GlitchData, + OutSignalName => "PPCEICINTERCONNECTIRQ", + OutTemp => PPCEICINTERCONNECTIRQ_OUT, + Paths => (0 => (CPMINTERCONNECTCLK_ipd'last_event, PATH_DELAY,TRUE)), + Mode => VitalTransport, DefaultDelay => PATH_DELAY, + Xon => false, + MsgOn => false, + MsgSeverity => WARNING + ); + + wait on + APUFCMDECFPUOP_out, + APUFCMDECLDSTXFERSIZE_out, + APUFCMDECLOAD_out, + APUFCMDECNONAUTON_out, + APUFCMDECSTORE_out, + APUFCMDECUDIVALID_out, + APUFCMDECUDI_out, + APUFCMENDIAN_out, + APUFCMFLUSH_out, + APUFCMINSTRUCTION_out, + APUFCMINSTRVALID_out, + APUFCMLOADBYTEADDR_out, + APUFCMLOADDATA_out, + APUFCMLOADDVALID_out, + APUFCMMSRFE0_out, + APUFCMMSRFE1_out, + APUFCMNEXTINSTRREADY_out, + APUFCMOPERANDVALID_out, + APUFCMRADATA_out, + APUFCMRBDATA_out, + APUFCMWRITEBACKOK_out, + C440CPMCORESLEEPREQ_out, + C440CPMDECIRPTREQ_out, + C440CPMFITIRPTREQ_out, + C440CPMMSRCE_out, + C440CPMMSREE_out, + C440CPMTIMERRESETREQ_out, + C440CPMWDIRPTREQ_out, + C440DBGSYSTEMCONTROL_out, + C440JTGTDOEN_out, + C440JTGTDO_out, + C440MACHINECHECK_out, + C440RSTCHIPRESETREQ_out, + C440RSTCORERESETREQ_out, + C440RSTSYSTEMRESETREQ_out, + C440TRCBRANCHSTATUS_out, + C440TRCCYCLE_out, + C440TRCEXECUTIONSTATUS_out, + C440TRCTRACESTATUS_out, + C440TRCTRIGGEREVENTOUT_out, + C440TRCTRIGGEREVENTTYPE_out, + DMA0LLRSTENGINEACK_out, + DMA0LLRXDSTRDYN_out, + DMA0LLTXD_out, + DMA0LLTXEOFN_out, + DMA0LLTXEOPN_out, + DMA0LLTXREM_out, + DMA0LLTXSOFN_out, + DMA0LLTXSOPN_out, + DMA0LLTXSRCRDYN_out, + DMA0RXIRQ_out, + DMA0TXIRQ_out, + DMA1LLRSTENGINEACK_out, + DMA1LLRXDSTRDYN_out, + DMA1LLTXD_out, + DMA1LLTXEOFN_out, + DMA1LLTXEOPN_out, + DMA1LLTXREM_out, + DMA1LLTXSOFN_out, + DMA1LLTXSOPN_out, + DMA1LLTXSRCRDYN_out, + DMA1RXIRQ_out, + DMA1TXIRQ_out, + DMA2LLRSTENGINEACK_out, + DMA2LLRXDSTRDYN_out, + DMA2LLTXD_out, + DMA2LLTXEOFN_out, + DMA2LLTXEOPN_out, + DMA2LLTXREM_out, + DMA2LLTXSOFN_out, + DMA2LLTXSOPN_out, + DMA2LLTXSRCRDYN_out, + DMA2RXIRQ_out, + DMA2TXIRQ_out, + DMA3LLRSTENGINEACK_out, + DMA3LLRXDSTRDYN_out, + DMA3LLTXD_out, + DMA3LLTXEOFN_out, + DMA3LLTXEOPN_out, + DMA3LLTXREM_out, + DMA3LLTXSOFN_out, + DMA3LLTXSOPN_out, + DMA3LLTXSRCRDYN_out, + DMA3RXIRQ_out, + DMA3TXIRQ_out, + MIMCADDRESSVALID_out, + MIMCADDRESS_out, + MIMCBANKCONFLICT_out, + MIMCBYTEENABLE_out, + MIMCREADNOTWRITE_out, + MIMCROWCONFLICT_out, + MIMCWRITEDATAVALID_out, + MIMCWRITEDATA_out, + PPCCPMINTERCONNECTBUSY_out, + PPCDMDCRABUS_out, + PPCDMDCRDBUSOUT_out, + PPCDMDCRREAD_out, + PPCDMDCRUABUS_out, + PPCDMDCRWRITE_out, + PPCDSDCRACK_out, + PPCDSDCRDBUSIN_out, + PPCDSDCRTIMEOUTWAIT_out, + PPCEICINTERCONNECTIRQ_out, + PPCMPLBABORT_out, + PPCMPLBABUS_out, + PPCMPLBBE_out, + PPCMPLBBUSLOCK_out, + PPCMPLBLOCKERR_out, + PPCMPLBPRIORITY_out, + PPCMPLBRDBURST_out, + PPCMPLBREQUEST_out, + PPCMPLBRNW_out, + PPCMPLBSIZE_out, + PPCMPLBTATTRIBUTE_out, + PPCMPLBTYPE_out, + PPCMPLBUABUS_out, + PPCMPLBWRBURST_out, + PPCMPLBWRDBUS_out, + PPCS0PLBADDRACK_out, + PPCS0PLBMBUSY_out, + PPCS0PLBMIRQ_out, + PPCS0PLBMRDERR_out, + PPCS0PLBMWRERR_out, + PPCS0PLBRDBTERM_out, + PPCS0PLBRDCOMP_out, + PPCS0PLBRDDACK_out, + PPCS0PLBRDDBUS_out, + PPCS0PLBRDWDADDR_out, + PPCS0PLBREARBITRATE_out, + PPCS0PLBSSIZE_out, + PPCS0PLBWAIT_out, + PPCS0PLBWRBTERM_out, + PPCS0PLBWRCOMP_out, + PPCS0PLBWRDACK_out, + PPCS1PLBADDRACK_out, + PPCS1PLBMBUSY_out, + PPCS1PLBMIRQ_out, + PPCS1PLBMRDERR_out, + PPCS1PLBMWRERR_out, + PPCS1PLBRDBTERM_out, + PPCS1PLBRDCOMP_out, + PPCS1PLBRDDACK_out, + PPCS1PLBRDDBUS_out, + PPCS1PLBRDWDADDR_out, + PPCS1PLBREARBITRATE_out, + PPCS1PLBSSIZE_out, + PPCS1PLBWAIT_out, + PPCS1PLBWRBTERM_out, + PPCS1PLBWRCOMP_out, + PPCS1PLBWRDACK_out, + + CPMC440CLKEN_ipd, + CPMC440CLK_ipd, + CPMC440CORECLOCKINACTIVE_ipd, + CPMC440TIMERCLOCK_ipd, + CPMDCRCLK_ipd, + CPMDMA0LLCLK_ipd, + CPMDMA1LLCLK_ipd, + CPMDMA2LLCLK_ipd, + CPMDMA3LLCLK_ipd, + CPMFCMCLK_ipd, + CPMINTERCONNECTCLKEN_ipd, + CPMINTERCONNECTCLKNTO1_ipd, + CPMINTERCONNECTCLK_ipd, + CPMMCCLK_ipd, + CPMPPCMPLBCLK_ipd, + CPMPPCS0PLBCLK_ipd, + CPMPPCS1PLBCLK_ipd, + DBGC440DEBUGHALT_ipd, + DBGC440SYSTEMSTATUS_ipd, + DBGC440UNCONDDEBUGEVENT_ipd, + DCRPPCDMACK_ipd, + DCRPPCDMDBUSIN_ipd, + DCRPPCDMTIMEOUTWAIT_ipd, + DCRPPCDSABUS_ipd, + DCRPPCDSDBUSOUT_ipd, + DCRPPCDSREAD_ipd, + DCRPPCDSWRITE_ipd, + EICC440CRITIRQ_ipd, + EICC440EXTIRQ_ipd, + FCMAPUCONFIRMINSTR_ipd, + FCMAPUCR_ipd, + FCMAPUDONE_ipd, + FCMAPUEXCEPTION_ipd, + FCMAPUFPSCRFEX_ipd, + FCMAPURESULTVALID_ipd, + FCMAPURESULT_ipd, + FCMAPUSLEEPNOTREADY_ipd, + FCMAPUSTOREDATA_ipd, + JTGC440TCK_ipd, + JTGC440TDI_ipd, + JTGC440TMS_ipd, + JTGC440TRSTNEG_ipd, + LLDMA0RSTENGINEREQ_ipd, + LLDMA0RXD_ipd, + LLDMA0RXEOFN_ipd, + LLDMA0RXEOPN_ipd, + LLDMA0RXREM_ipd, + LLDMA0RXSOFN_ipd, + LLDMA0RXSOPN_ipd, + LLDMA0RXSRCRDYN_ipd, + LLDMA0TXDSTRDYN_ipd, + LLDMA1RSTENGINEREQ_ipd, + LLDMA1RXD_ipd, + LLDMA1RXEOFN_ipd, + LLDMA1RXEOPN_ipd, + LLDMA1RXREM_ipd, + LLDMA1RXSOFN_ipd, + LLDMA1RXSOPN_ipd, + LLDMA1RXSRCRDYN_ipd, + LLDMA1TXDSTRDYN_ipd, + LLDMA2RSTENGINEREQ_ipd, + LLDMA2RXD_ipd, + LLDMA2RXEOFN_ipd, + LLDMA2RXEOPN_ipd, + LLDMA2RXREM_ipd, + LLDMA2RXSOFN_ipd, + LLDMA2RXSOPN_ipd, + LLDMA2RXSRCRDYN_ipd, + LLDMA2TXDSTRDYN_ipd, + LLDMA3RSTENGINEREQ_ipd, + LLDMA3RXD_ipd, + LLDMA3RXEOFN_ipd, + LLDMA3RXEOPN_ipd, + LLDMA3RXREM_ipd, + LLDMA3RXSOFN_ipd, + LLDMA3RXSOPN_ipd, + LLDMA3RXSRCRDYN_ipd, + LLDMA3TXDSTRDYN_ipd, + MCMIADDRREADYTOACCEPT_ipd, + MCMIREADDATAERR_ipd, + MCMIREADDATAVALID_ipd, + MCMIREADDATA_ipd, + PLBPPCMADDRACK_ipd, + PLBPPCMMBUSY_ipd, + PLBPPCMMIRQ_ipd, + PLBPPCMMRDERR_ipd, + PLBPPCMMWRERR_ipd, + PLBPPCMRDBTERM_ipd, + PLBPPCMRDDACK_ipd, + PLBPPCMRDDBUS_ipd, + PLBPPCMRDPENDPRI_ipd, + PLBPPCMRDPENDREQ_ipd, + PLBPPCMRDWDADDR_ipd, + PLBPPCMREARBITRATE_ipd, + PLBPPCMREQPRI_ipd, + PLBPPCMSSIZE_ipd, + PLBPPCMTIMEOUT_ipd, + PLBPPCMWRBTERM_ipd, + PLBPPCMWRDACK_ipd, + PLBPPCMWRPENDPRI_ipd, + PLBPPCMWRPENDREQ_ipd, + PLBPPCS0ABORT_ipd, + PLBPPCS0ABUS_ipd, + PLBPPCS0BE_ipd, + PLBPPCS0BUSLOCK_ipd, + PLBPPCS0LOCKERR_ipd, + PLBPPCS0MASTERID_ipd, + PLBPPCS0MSIZE_ipd, + PLBPPCS0PAVALID_ipd, + PLBPPCS0RDBURST_ipd, + PLBPPCS0RDPENDPRI_ipd, + PLBPPCS0RDPENDREQ_ipd, + PLBPPCS0RDPRIM_ipd, + PLBPPCS0REQPRI_ipd, + PLBPPCS0RNW_ipd, + PLBPPCS0SAVALID_ipd, + PLBPPCS0SIZE_ipd, + PLBPPCS0TATTRIBUTE_ipd, + PLBPPCS0TYPE_ipd, + PLBPPCS0UABUS_ipd, + PLBPPCS0WRBURST_ipd, + PLBPPCS0WRDBUS_ipd, + PLBPPCS0WRPENDPRI_ipd, + PLBPPCS0WRPENDREQ_ipd, + PLBPPCS0WRPRIM_ipd, + PLBPPCS1ABORT_ipd, + PLBPPCS1ABUS_ipd, + PLBPPCS1BE_ipd, + PLBPPCS1BUSLOCK_ipd, + PLBPPCS1LOCKERR_ipd, + PLBPPCS1MASTERID_ipd, + PLBPPCS1MSIZE_ipd, + PLBPPCS1PAVALID_ipd, + PLBPPCS1RDBURST_ipd, + PLBPPCS1RDPENDPRI_ipd, + PLBPPCS1RDPENDREQ_ipd, + PLBPPCS1RDPRIM_ipd, + PLBPPCS1REQPRI_ipd, + PLBPPCS1RNW_ipd, + PLBPPCS1SAVALID_ipd, + PLBPPCS1SIZE_ipd, + PLBPPCS1TATTRIBUTE_ipd, + PLBPPCS1TYPE_ipd, + PLBPPCS1UABUS_ipd, + PLBPPCS1WRBURST_ipd, + PLBPPCS1WRDBUS_ipd, + PLBPPCS1WRPENDPRI_ipd, + PLBPPCS1WRPENDREQ_ipd, + PLBPPCS1WRPRIM_ipd, + RSTC440RESETCHIP_ipd, + RSTC440RESETCORE_ipd, + RSTC440RESETSYSTEM_ipd, + TIEC440DCURDLDCACHEPLBPRIO_ipd, + TIEC440DCURDNONCACHEPLBPRIO_ipd, + TIEC440DCURDTOUCHPLBPRIO_ipd, + TIEC440DCURDURGENTPLBPRIO_ipd, + TIEC440DCUWRFLUSHPLBPRIO_ipd, + TIEC440DCUWRSTOREPLBPRIO_ipd, + TIEC440DCUWRURGENTPLBPRIO_ipd, + TIEC440ENDIANRESET_ipd, + TIEC440ERPNRESET_ipd, + TIEC440ICURDFETCHPLBPRIO_ipd, + TIEC440ICURDSPECPLBPRIO_ipd, + TIEC440ICURDTOUCHPLBPRIO_ipd, + TIEC440PIR_ipd, + TIEC440PVR_ipd, + TIEC440USERRESET_ipd, + TIEDCRBASEADDR_ipd, + TRCC440TRACEDISABLE_ipd, + TRCC440TRIGGEREVENTIN_ipd; + + end process TIMING; + + +end PPC440_V;